From 3ddab49587aab1402c3285c454497f50de2abc93 Mon Sep 17 00:00:00 2001 From: Jack O'Connor Date: Sat, 23 Dec 2023 16:44:15 -0600 Subject: [PATCH] riscv64gcv.S -> riscv_rva23u64.S With QEMU v8.2 the test command is now: for VLEN in 128 256 512 1024 ; do CC="$HOME/llvm-project/build/bin/clang" CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER=riscv64-linux-gnu-gcc CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUSTFLAGS="-L /usr/lib/gcc/riscv64-linux-gnu/12.2.0" CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER="$HOME/qemu/build/qemu-riscv64 -L /usr/riscv64-linux-gnu -cpu rv64,v=true,vext_spec=v1.0,vlen=$VLEN,zbb=true,zvbb=true" cargo test --target riscv64gc-unknown-linux-gnu done --- rust/guts/build.rs | 2 +- rust/guts/src/{riscv64gcv.S => riscv_rva23u64.S} | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) rename rust/guts/src/{riscv64gcv.S => riscv_rva23u64.S} (99%) diff --git a/rust/guts/build.rs b/rust/guts/build.rs index bf15cdfe3..f68d10330 100644 --- a/rust/guts/build.rs +++ b/rust/guts/build.rs @@ -232,7 +232,7 @@ fn build_neon_c_intrinsics() { fn build_riscv64gcv_assembly() { println!("cargo:rustc-cfg=blake3_riscv64gcv_ffi"); let mut build = new_build(); - let asm_path = "src/riscv64gcv.S"; + let asm_path = "src/riscv_rva23u64.S"; build.file(asm_path); build.flag("--target=riscv64"); build.flag("-march=rv64gcv_zbb_zvbb1p0"); diff --git a/rust/guts/src/riscv64gcv.S b/rust/guts/src/riscv_rva23u64.S similarity index 99% rename from rust/guts/src/riscv64gcv.S rename to rust/guts/src/riscv_rva23u64.S index 424b95a90..7758ff4b6 100644 --- a/rust/guts/src/riscv64gcv.S +++ b/rust/guts/src/riscv_rva23u64.S @@ -1,8 +1,11 @@ -// This implementation currently assumes riscv64gcv_zbb_zvbb. Zvbb in particular ("Vector -// Bit-manipulation used in Cryptography") is a bleeding-edge extension that was only frozen a few -// weeks ago at the time I'm writing this comment. Compiling and testing this code currently -// requires quite a lot of effort, including building Clang from master and building QEMU from a -// custom branch. Please don't expect this code to be usable on real hardware for some time. +// This implementation targets the RVA23 profile, particularly V, Zvbb, and +// Zbb, that is the vector extension and the bit-manipulation extensions. As of +// December 2023, most real-world hardware does *not* support these extensions. +// This implementation also assumes that misaligned vector loads and stores are +// supported, in particular for the vlsseg8e32.v and vssseg8e32.v instructions. +// +// Compiling and testing this code requires very recent versions of Clang (v17) +// and QEMU (v8.2). #define IV0 0x6A09E667 #define IV1 0xBB67AE85