Input nodes generated with ports in the wrong order

[doug-q]

This program, using guppy 0.5.1

from guppylang.decorator import guppy
from guppylang.module import GuppyModule
from guppylang.prelude import quantum
from guppylang.prelude.builtins import py
from guppylang.prelude.quantum import measure, phased_x, qubit

mod = GuppyModule("main")
mod.load(quantum)

@guppy(mod)
def rx(q: qubit, x: float) -> qubit:
  # Implement Rx via Rz rotation
  return h(rz(h(q), x))


@guppy(mod)
def main() -> bool:
  q = qubit()
  z = rx(q,1.5)
  return measure(z)

if __name__ == "__main__":
    print(mod.compile().serialize())

results in this hugr:

graph LR
    subgraph 0 ["(0) Module"]
        direction LR
        subgraph 13 ["(13) FuncDefn"]
            direction LR
            5["(5) Input"]
            5--"0:0<br>qubit"-->15
            5--"1:1<br>float64"-->15
            10["(10) Output"]
            subgraph 15 ["(15) CFG"]
                direction LR
                subgraph 1 ["(1) DataflowBlock"]
                    direction LR
                    6["(6) Input"]
                    6--"0:1<br>float64"-->17
                    6--"1:0<br>qubit"-->16
                    9["(9) Output"]
                    16["(16) quantum.tket2.H"]
                    16--"0:0<br>qubit"-->17
                    17["(17) quantum.tket2.RzF64"]
                    17--"0:0<br>qubit"-->18
                    18["(18) quantum.tket2.H"]
                    18--"0:1<br>qubit"-->9
                    19["(19) Tag"]
                    19--"0:0<br>[]"-->9
                end
                1-."0:0".->3
                3["(3) ExitBlock"]
            end
            15--"0:0<br>qubit"-->10
        end
        13--"0:2<br>forall . [qubit, float64] -> [[]][qubit]"-->24
        subgraph 14 ["(14) FuncDefn"]
            direction LR
            7["(7) Input"]
            12["(12) Output"]
            subgraph 20 ["(20) CFG"]
                direction LR
                subgraph 2 ["(2) DataflowBlock"]
                    direction LR
                    8["(8) Input"]
                    11["(11) Output"]
                    21["(21) quantum.tket2.QAlloc"]
                    21--"0:0<br>qubit"-->24
                    22["(22) const:custom:f64(1.5)"]
                    22--"0:0<br>float64"-->23
                    23["(23) LoadConstant"]
                    23--"0:1<br>float64"-->24
                    24["(24) Call"]
                    24--"0:0<br>qubit"-->25
                    25["(25) quantum.tket2.Measure"]
                    25--"0:0<br>qubit"-->26
                    25--"1:1<br>[]+[]"-->11
                    26["(26) quantum.tket2.QFree"]
                    27["(27) Tag"]
                    27--"0:0<br>[]"-->11
                end
                2-."0:0".->4
                4["(4) ExitBlock"]
            end
            20--"0:0<br>[]+[]"-->12
        end
    end

Loading

Note that the the output ports of node 6 are the reverse of the input nodes of node 15.

Hugr validation should catch this, but it does currently not.