From 0a66a0660be691b967baa65c0239eb7e809078ac Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Sun, 25 Apr 2021 13:23:33 +0200 Subject: [PATCH] Fix t0 restore when exiting interrupt An oversight when arrangeing the code according to the nucleisys docs, t0 was overriden with the value of msubm and never actually restored. To fix the issue we restore the csrs after the general purpose registers. The offical docs want it the other way around but this should be fine as well, as the interrupts are still globaly disabled at this point. --- .../ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S b/os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S index db896902f8..897224e764 100644 --- a/os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S +++ b/os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S @@ -103,6 +103,13 @@ # registers and status csr registers from stack. # -------------------------------------------------------------------------- .macro RESTORE_CONTEXT + LOAD t0, 17*REGBYTES(sp) + csrw CSR_MEPC, t0 + LOAD t0, 18*REGBYTES(sp) + csrw CSR_MCAUSE, t0 + LOAD t0, 19*REGBYTES(sp) + csrw CSR_MSUBM, t0 + LOAD ra, 0*REGBYTES(sp) LOAD tp, 1*REGBYTES(sp) LOAD t0, 2*REGBYTES(sp) @@ -121,13 +128,6 @@ LOAD t5, 15*REGBYTES(sp) LOAD t6, 16*REGBYTES(sp) - LOAD t0, 17*REGBYTES(sp) - csrw CSR_MEPC, t0 - LOAD t0, 18*REGBYTES(sp) - csrw CSR_MCAUSE, t0 - LOAD t0, 19*REGBYTES(sp) - csrw CSR_MSUBM, t0 - # De-allocate the stack space addi sp, sp, 20*REGBYTES .endm