-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathv4l2_nv_extensions.h
2686 lines (2455 loc) · 91.3 KB
/
v4l2_nv_extensions.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. The names of its contributors may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This file contains amendments to the V4L2 headers made after the
* supported kernel version and NVIDIA extensions.
*/
#ifndef __V4L2_NV_EXTENSIONS_H__
#define __V4L2_NV_EXTENSIONS_H__
/**
* @file
* <b>NVIDIA V4L2 API Extensions</b>
*
* @b Description: This file declares NVIDIA V4L2 extensions,
* controls and structures.
*/
/**
*
* @defgroup ee_extensions_group V4L2 NV Extensions API
*
* This file declares NVIDIA V4L2 extensions, controls, and structures.
*
*/
/**
* Defines V4L2 pixel format for DIVX.
*/
#define V4L2_PIX_FMT_DIVX4 v4l2_fourcc('D', 'V', 'X', '4')
#define V4L2_PIX_FMT_DIVX5 v4l2_fourcc('D', 'V', 'X', '5')
/**
* Defines V4L2 pixel format for H.265.
*/
#define V4L2_PIX_FMT_H265 v4l2_fourcc('H', '2', '6', '5')
/**
* Defines the V4L2 pixel format for VP9.
*/
#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0')
/**
* Defines the V4L2 pixel format for AV1.
*/
#define V4L2_PIX_FMT_AV1 v4l2_fourcc('A', 'V', '1', '0')
/**
* Defines the V4L2 pixel format for representing single plane 10-bit Y/CbCr 4:2:0 decoder data.
*/
#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* Y/CbCr 4:2:0, 10 bits per channel */
/**
* Defines the V4L2 pixel format for representing semi-planar 10-bit Y/CbCr 4:2:0 decoder data.
*/
#define V4L2_PIX_FMT_P010M v4l2_fourcc('P', 'M', '1', '0') /* Y/CbCr 4:2:0, 10 bits per channel */
/**
* Defines the V4L2 pixel format for representing single plane 12-bit Y/CbCr 4:2:0 decoder data.
*/
#define V4L2_PIX_FMT_P012 v4l2_fourcc('P', '0', '1', '2') /* Y/CbCr 4:2:0, 12 bits per channel */
/**
* Defines the V4L2 pixel format for representing semi-planar 12-bit Y/CbCr 4:2:0 decoder data.
*/
#define V4L2_PIX_FMT_P012M v4l2_fourcc('P', 'M', '1', '2') /* Y/CbCr 4:2:0, 12 bits per channel */
/**
* Defines the V4L2 pixel format for representing semi-planar 8-bit Y/CbCr 4:4:4 decoder data.
*/
#define V4L2_PIX_FMT_NV24M v4l2_fourcc('N', 'M', '2', '4') /* Y/CbCr 4:4:4, 8 bits per channel */
/**
* Defines the V4L2 pixel format for representing semi-planar 10-bit Y/CbCr 4:4:4 decoder data.
*/
#define V4L2_PIX_FMT_NV24_10LE v4l2_fourcc('N', 'V', '1', '0') /* Y/CbCr 4:4:4, 10 bits per channel */
/** @cond UNUSED */
/* >> The declarations from here to the next endcond statement are not
* >> currently implemented. DO NOT USE. */
#define V4L2_PIX_FMT_YUV422RM v4l2_fourcc('4', '2', 'R', 'M')
#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /** H264 parsed slices. */
#define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /** VP8 parsed frames. */
#define V4L2_CTRL_FLAG_CAN_STORE 0x0200
/** @endcond */
/**
* Defines the V4L2 event type for decoder resolution event change.
*/
#define V4L2_EVENT_RESOLUTION_CHANGE 5
/** @cond UNUSED */
/* >> The declarations from here to the next endcond statement are not
* >> currently implemented. DO NOT USE. */
/*---------------Below are changes from the v4l2-controls.h----------------------*/
#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+383)
#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+384)
#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+385)
#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAM (V4L2_CID_MPEG_BASE+386)
#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAM (V4L2_CID_MPEG_BASE+387)
#define V4L2_CID_MPEG_VIDEO_VP8_FRAME_HDR (V4L2_CID_MPEG_BASE+512)
/** @endcond */
/**
* Defines the control ID to set the H.265 encoder profile.
*
* A v4l2_mpeg_video_h265_profile must be passed.
*/
#define V4L2_CID_MPEG_VIDEO_H265_PROFILE (V4L2_CID_MPEG_BASE+513)
/**
* Defines the possible profiles for H.265 encoder.
*/
enum v4l2_mpeg_video_h265_profile {
/** H.265 Main profile. */
V4L2_MPEG_VIDEO_H265_PROFILE_MAIN = 0,
/** H.265 Main10 profile. */
V4L2_MPEG_VIDEO_H265_PROFILE_MAIN10 = 1,
/** H.265 MainStillPicture profile. */
V4L2_MPEG_VIDEO_H265_PROFILE_MAINSTILLPICTURE = 2,
};
/**
* Defines the control ID to set the encoder IDR frame interval.
* Must be used with \c VIDIOC_S_EXT_CTRLS IOCTL.
*/
#define V4L2_CID_MPEG_VIDEO_IDR_INTERVAL (V4L2_CID_MPEG_BASE+514)
/** @cond UNUSED */
/* >> The declarations from here to the next endcond statement are not
* >> currently implemented. DO NOT USE. */
/* Complex controls */
#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01
#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02
#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04
#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08
#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10
#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20
#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01
#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02
#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04
#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08
#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10
#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20
#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40
struct v4l2_ctrl_h264_sps {
__u8 profile_idc;
__u8 constraint_set_flags;
__u8 level_idc;
__u8 seq_parameter_set_id;
__u8 chroma_format_idc;
__u8 bit_depth_luma_minus8;
__u8 bit_depth_chroma_minus8;
__u8 log2_max_frame_num_minus4;
__u8 pic_order_cnt_type;
__u8 log2_max_pic_order_cnt_lsb_minus4;
__s32 offset_for_non_ref_pic;
__s32 offset_for_top_to_bottom_field;
__u8 num_ref_frames_in_pic_order_cnt_cycle;
__s32 offset_for_ref_frame[255];
__u8 max_num_ref_frames;
__u16 pic_width_in_mbs_minus1;
__u16 pic_height_in_map_units_minus1;
__u8 flags;
};
#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001
#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002
#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004
#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008
#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010
#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020
#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040
#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080
struct v4l2_ctrl_h264_pps {
__u8 pic_parameter_set_id;
__u8 seq_parameter_set_id;
__u8 num_slice_groups_minus1;
__u8 num_ref_idx_l0_default_active_minus1;
__u8 num_ref_idx_l1_default_active_minus1;
__u8 weighted_bipred_idc;
__s8 pic_init_qp_minus26;
__s8 pic_init_qs_minus26;
__s8 chroma_qp_index_offset;
__s8 second_chroma_qp_index_offset;
__u8 flags;
};
struct v4l2_ctrl_h264_scaling_matrix {
__u8 scaling_list_4x4[6][16];
__u8 scaling_list_8x8[6][64];
};
struct v4l2_h264_weight_factors {
__s8 luma_weight[32];
__s8 luma_offset[32];
__s8 chroma_weight[32][2];
__s8 chroma_offset[32][2];
};
struct v4l2_h264_pred_weight_table {
__u8 luma_log2_weight_denom;
__u8 chroma_log2_weight_denom;
struct v4l2_h264_weight_factors weight_factors[2];
};
#define V4L2_SLICE_FLAG_FIELD_PIC 0x01
#define V4L2_SLICE_FLAG_BOTTOM_FIELD 0x02
#define V4L2_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04
#define V4L2_SLICE_FLAG_SP_FOR_SWITCH 0x08
struct v4l2_ctrl_h264_slice_param {
/** Holds the size in bytes, including the header. */
__u32 size;
/** Holds the offset in bits to slice_data() from the beginning of this slice. */
__u32 header_bit_size;
__u16 first_mb_in_slice;
__u8 slice_type;
__u8 pic_parameter_set_id;
__u8 colour_plane_id;
__u16 frame_num;
__u16 idr_pic_id;
__u16 pic_order_cnt_lsb;
__s32 delta_pic_order_cnt_bottom;
__s32 delta_pic_order_cnt0;
__s32 delta_pic_order_cnt1;
__u8 redundant_pic_cnt;
struct v4l2_h264_pred_weight_table pred_weight_table;
/* Size in bits of dec_ref_pic_marking() syntax element. */
__u32 dec_ref_pic_marking_bit_size;
/* Size in bits of pic order count syntax. */
__u32 pic_order_cnt_bit_size;
__u8 cabac_init_idc;
__s8 slice_qp_delta;
__s8 slice_qs_delta;
__u8 disable_deblocking_filter_idc;
__s8 slice_alpha_c0_offset_div2;
__s8 slice_beta_offset_div2;
__u32 slice_group_change_cycle;
__u8 num_ref_idx_l0_active_minus1;
__u8 num_ref_idx_l1_active_minus1;
/* Entries on each list are indices
* into v4l2_ctrl_h264_decode_param.dpb[]. */
__u8 ref_pic_list0[32];
__u8 ref_pic_list1[32];
__u8 flags;
};
/** Defines whether the v4l2_h264_dpb_entry structure is used.
If not set, this entry is unused for reference. */
#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x01
#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x02
struct v4l2_h264_dpb_entry {
__u32 buf_index; /**< v4l2_buffer index. */
__u16 frame_num;
__u16 pic_num;
/** @note `v4l2_buffer.field` specifies this field. */
__s32 top_field_order_cnt;
__s32 bottom_field_order_cnt;
__u8 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */
};
struct v4l2_ctrl_h264_decode_param {
__u32 num_slices;
__u8 idr_pic_flag;
__u8 nal_ref_idc;
__s32 top_field_order_cnt;
__s32 bottom_field_order_cnt;
__u8 ref_pic_list_p0[32];
__u8 ref_pic_list_b0[32];
__u8 ref_pic_list_b1[32];
struct v4l2_h264_dpb_entry dpb[16];
};
#define V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED 0x01
#define V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_MAP 0x02
#define V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_FEATURE_DATA 0x04
struct v4l2_vp8_sgmnt_hdr {
__u8 segment_feature_mode;
__s8 quant_update[4];
__s8 lf_update[4];
__u8 segment_probs[3];
__u8 flags;
};
#define V4L2_VP8_LF_HDR_ADJ_ENABLE 0x01
#define V4L2_VP8_LF_HDR_DELTA_UPDATE 0x02
struct v4l2_vp8_loopfilter_hdr {
__u8 type;
__u8 level;
__u8 sharpness_level;
__s8 ref_frm_delta_magnitude[4];
__s8 mb_mode_delta_magnitude[4];
__u8 flags;
};
struct v4l2_vp8_quantization_hdr {
__u8 y_ac_qi;
__s8 y_dc_delta;
__s8 y2_dc_delta;
__s8 y2_ac_delta;
__s8 uv_dc_delta;
__s8 uv_ac_delta;
__u16 dequant_factors[4][3][2];
};
struct v4l2_vp8_entropy_hdr {
__u8 coeff_probs[4][8][3][11];
__u8 y_mode_probs[4];
__u8 uv_mode_probs[3];
__u8 mv_probs[2][19];
};
#define V4L2_VP8_FRAME_HDR_FLAG_EXPERIMENTAL 0x01
#define V4L2_VP8_FRAME_HDR_FLAG_SHOW_FRAME 0x02
#define V4L2_VP8_FRAME_HDR_FLAG_MB_NO_SKIP_COEFF 0x04
struct v4l2_ctrl_vp8_frame_hdr {
/** 0: keyframe, 1: not a keyframe. */
__u8 key_frame;
__u8 version;
/** Populated also if not a key frame. */
__u16 width;
__u8 horizontal_scale;
__u16 height;
__u8 vertical_scale;
struct v4l2_vp8_sgmnt_hdr sgmnt_hdr;
struct v4l2_vp8_loopfilter_hdr lf_hdr;
struct v4l2_vp8_quantization_hdr quant_hdr;
struct v4l2_vp8_entropy_hdr entropy_hdr;
__u8 sign_bias_golden;
__u8 sign_bias_alternate;
__u8 prob_skip_false;
__u8 prob_intra;
__u8 prob_last;
__u8 prob_gf;
__u32 first_part_size;
/**
* Holds the offset in bits of the MB data in the first partition,
* i.e. bit offset starting from first_part_offset.
*/
__u32 first_part_offset;
__u32 macroblock_bit_offset;
__u8 num_dct_parts;
__u32 dct_part_sizes[8];
__u8 bool_dec_range;
__u8 bool_dec_value;
__u8 bool_dec_count;
/** Holds the v4l2_buffer index of the last reference frame. */
__u32 last_frame;
/** Holds the v4l2_buffer index of the golden reference frame. */
__u32 golden_frame;
/** Holds the v4l2_buffer index of the alt reference frame. */
__u32 alt_frame;
__u8 flags;
};
/** @endcond */
/*---------------Add below NVIDIA specific extensions ----------------------*/
/**
* @defgroup V4L2Dec V4L2 Video Decoder
*
* @brief NVIDIA V4L2 Video Decoder Description and Extensions
*
* The video decoder device node is
*
* /dev/nvhost-nvdec
*
* ### Supported Pixel Formats
* OUTPUT PLANE | CAPTURE PLANE | PLATFORM
* :----------------: | :----------------: | :--------------------:
* V4L2_PIX_FMT_H264 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_H265 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_VP8 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_VP9 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_MPEG1 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_MPEG2 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_MPEG4 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_DIVX4 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_DIVX5 | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_JPEG | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_MJPEG | V4L2_PIX_FMT_NV12M | T210, T186, T194, T234
* V4L2_PIX_FMT_AV1 | V4L2_PIX_FMT_NV12M | T234
*
* ### Supported Memory Types
* MEMORY | OUTPUT PLANE | CAPTURE PLANE
* :------------------: | :----------: | :-----------:
* V4L2_MEMORY_MMAP | Y | Y
* V4L2_MEMORY_DMABUF | N | Y
* V4L2_MEMORY_USERPTR | Y | N
*
* ### Supported Controls
* - #V4L2_CID_MPEG_VIDEO_DISABLE_COMPLETE_FRAME_INPUT
* - #V4L2_CID_MPEG_VIDEO_DISABLE_DPB
* - #V4L2_CID_MPEG_VIDEO_ERROR_REPORTING
* - #V4L2_CID_MPEG_VIDEO_SKIP_FRAMES
* - V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (Get the minimum buffers to be allocated on capture plane.
* Read only. Valid after #V4L2_EVENT_RESOLUTION_CHANGE)
* - #V4L2_CID_MPEG_VIDEODEC_INPUT_METADATA
* - #V4L2_CID_MPEG_VIDEODEC_METADATA
* - #V4L2_CID_MPEG_VIDEO_BUF_API_TYPE
* - #V4L2_CID_MPEG_VIDEO_CUDA_MEM_TYPE
* - #V4L2_CID_MPEG_VIDEO_CUDA_GPU_ID
* - #V4L2_CID_MPEG_VIDEODEC_DROP_FRAME_INTERVAL
*
* ### Supported Events
* Event | Purpose
* ----------------------------- | :----------------------------:
* #V4L2_EVENT_RESOLUTION_CHANGE | Resolution of the stream has changed.
*
* ### Handling Resolution Change Events
* When the decoder generates a \c V4L2_EVENT_RESOLUTION_CHANGE event, the
* application calls \c STREAMOFF on the capture plane to tell the decoder to
* deallocate the current buffers by calling REQBUF with count zero, get
* the new capture plane format, and then proceed with setting up the buffers
* for the capture plane.
*
* In case of decoder, the buffer format might differ from the display resolution.
* The application must use \c VIDIOC_G_CROP to get the display resolution.
*
* ### EOS Handling
* The following sequence must be followed for sending EOS and recieving EOS
* from the decoder.
* -# Send EOS to decoder by queueing on the output plane a buffer with
* bytesused = 0 for the 0th plane (`v4l2_buffer.m.planes[0].bytesused = 0`).
* -# Dequeues buffers on the output plane until it gets a buffer with bytesused = 0
* for the 0th plane (`v4l2_buffer.m.planes[0].bytesused == 0`)
* -# Dequeues buffers on the capture plane until it gets a buffer with bytesused = 0
* for the 0th plane.
*
* ### Decoder Input Frame Metadata
* Decoder supports reporting stream header parsing error info as input frame metadata.
* See \c V4L2_CID_MPEG_VIDEO_ERROR_REPORTING, \c V4L2_CID_MPEG_VIDEODEC_INPUT_METADATA
* and \c v4l2_ctrl_video_metadata for more information.
*
* ### Decoder Output Frame Metadata
* Decoder supports reporting frame related metadata, including error reports and
* DPB info. See \c V4L2_CID_MPEG_VIDEO_ERROR_REPORTING, \c V4L2_CID_MPEG_VIDEODEC_METADATA
* and \c v4l2_ctrl_video_metadata for more information.
*
* @note Currently, V4L2 plugins do not support odd resolution.
* @{
* @ingroup ee_extensions_group
*/
/**
* Defines the Control ID to indicate to the decoder that the input
* buffers do not contain complete buffers.
*
* @note This control must be set in case of frames containing multiple slices
* when the input buffers do not contain all the slices of the frame.
*
* A boolean value must be supplied with this control.
*
*/
#define V4L2_CID_MPEG_VIDEO_DISABLE_COMPLETE_FRAME_INPUT (V4L2_CID_MPEG_BASE+515)
/**
* Defines the Control ID to disable decoder DPB management.
*
* @note This only works for streams having a single reference frame.
*
* A boolean value must be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEO_DISABLE_DPB (V4L2_CID_MPEG_BASE+516)
/**
* Defines the Control ID to enable decoder error and metadata reporting.
*
* A boolean value must be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEO_ERROR_REPORTING (V4L2_CID_MPEG_BASE+517)
/**
* Defines the Control ID to set the skip frames property of the decoder.
*
* Decoder must be configured to skip certain types of frames. One
* \c v4l2_skip_frames_type must be passed.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
* This control ID is supported only for H264.
*/
#define V4L2_CID_MPEG_VIDEO_SKIP_FRAMES (V4L2_CID_MPEG_BASE+518)
/**
* Defines the Control ID to get the decoder output metadata.
*
* @note Metadata reporting must be enabled using
* #V4L2_CID_MPEG_VIDEO_ERROR_REPORTING IOCTL for this.
*
* A pointer to a valid \c v4l2_ctrl_video_metadata structure must be supplied
* with this control.
*
* @attention This control must be read after dequeueing a buffer successfully from
* the capture plane. The values in the structure are valid until the buffer is queued
* again.
*/
#define V4L2_CID_MPEG_VIDEODEC_METADATA (V4L2_CID_MPEG_BASE+519)
/**
* Defines the Control ID to get the decoder input header error metadata.
*
* @note Metadata reporting must be enabled using
* #V4L2_CID_MPEG_VIDEO_ERROR_REPORTING IOCTL for this.
*
* A pointer to a valid \c v4l2_ctrl_video_metadata structure must be supplied
* with this control.
*
* @attention This control must be read after dequeueing a buffer successfully from
* the output plane. The values in the structure are valid until the buffer is queued
* again.
*/
#define V4L2_CID_MPEG_VIDEODEC_INPUT_METADATA (V4L2_CID_MPEG_BASE+520)
/**
* Defines the Control ID to check if display data is present.
*
* This control returns true if HDR metadata is present in the stream.
*
*/
#define V4L2_CID_VIDEODEC_DISPLAYDATA_PRESENT (V4L2_CID_MPEG_BASE+521)
/**
* Defines the Control ID to get display data if V4L2_CID_VIDEODEC_DISPLAYDATA_PRESENT returns true.
*
* This control returns display data such as display_primaries, white_point and
* display_parameter_luminance required for display module.
*
*/
#define V4L2_CID_VIDEODEC_HDR_MASTERING_DISPLAY_DATA (V4L2_CID_MPEG_BASE+522)
/**
* Defines the Control ID to get Sample Aspect Ratio width for decoding.
*
* This control returns unsigned integer of Sample Aspect Ratio width.
*
* @attention This control must be set after receiving V4L2_EVENT_RESOLUTION_CHANGE.
*
*/
#define V4L2_CID_MPEG_VIDEODEC_SAR_WIDTH (V4L2_CID_MPEG_BASE+569)
/**
* Defines the Control ID to get Sample Aspect Ratio height for decoding.
*
* This control returns unsigned integer of Sample Aspect Ratio height.
*
* @attention This control must be set after receiving V4L2_EVENT_RESOLUTION_CHANGE.
*
*/
#define V4L2_CID_MPEG_VIDEODEC_SAR_HEIGHT (V4L2_CID_MPEG_BASE+570)
/**
* Defines the Control ID to embed the SEI data coming from upstream plugins.
*
* This control sets the SEI payload size and SEI data pointer for encoder.
*
* @attention This control must be set after receiving V4L2_EVENT_RESOLUTION_CHANGE.
*
*/
#define V4L2_CID_MPEG_VIDEOENC_DS_SEI_DATA (V4L2_CID_MPEG_BASE+571)
/** @} */
/**
* @defgroup V4L2Conv V4L2 Video Converter
*
* @brief NVIDIA V4L2 Video Converter Description and Extensions
*
* Use the video converter for color space conversion, scaling, and
* conversion between hardware buffer memory (\c V4L2_MEMORY_MMAP/\c
* V4L2_MEMORY_DMABUF), software buffer memory (\c V4L2_MEMORY_USERPTR), and
* other operations such as cropping, flipping/rotating, and
* temporal noise reduction (TNR).
* The video converter device node is \c "/dev/nvhost-vic".
*
* ### Supported Pixelformats
* PIXEL FORMAT | PIXEL FORMAT
* :---------------------: | :--------------:
* V4L2_PIX_FMT_YUV444M | V4L2_PIX_FMT_YVU422M
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_YVU420M
* V4L2_PIX_FMT_NV12M | V4L2_PIX_FMT_GREY
* V4L2_PIX_FMT_YUYV | V4L2_PIX_FMT_YVYU
* V4L2_PIX_FMT_UYVY | V4L2_PIX_FMT_VYUY
* V4L2_PIX_FMT_ABGR32 | V4L2_PIX_FMT_XBGR32
*
* ### Supported Pixel Formats for TNR
* PIXEL FORMAT | PIXEL FORMAT
* :---------------------: | :--------------:
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_NV12M
* V4L2_PIX_FMT_UYVY | V4L2_PIX_FMT_YUYV
*
* ### Supported Memory Types
* MEMORY | OUTPUT PLANE | CAPTURE PLANE
* :------------------: | :----------: | :-----------:
* V4L2_MEMORY_MMAP | Y | Y
* V4L2_MEMORY_DMABUF | Y | Y
* V4L2_MEMORY_USERPTR | Y | Y
*
* ### Supported Controls
* - #V4L2_CID_VIDEO_CONVERT_OUTPUT_PLANE_LAYOUT
* - #V4L2_CID_VIDEO_CONVERT_CAPTURE_PLANE_LAYOUT
* - #V4L2_CID_VIDEO_CONVERT_FLIP_METHOD
* - #V4L2_CID_VIDEO_CONVERT_INTERPOLATION_METHOD
* - #V4L2_CID_VIDEO_CONVERT_TNR_ALGORITHM
* - #V4L2_CID_VIDEO_CONVERT_YUV_RESCALE_METHOD
*
* ### Cropping
* Video converter supports cropping using \c VIDIOC_S_SELECTION IOCTL with type
* \c V4L2_BUF_TYPE_VIDEO_CAPTURE and target \c V4L2_SEL_TGT_CROP. This must
* be set before requesting buffers on either plane.
*
* ### EOS Handling
* The following sequence must be followed for sending EOS and recieving EOS
* from the converter.
* -# Send EOS to converter by queueing on the output plane a buffer with
* bytesused = 0 for the 0th plane (`v4l2_buffer.m.planes[0].bytesused = 0`).
* -# Dequeues buffers on the capture plane until it gets a buffer with bytesused = 0
* for the 0th plane.
*
* @note Currently, V4L2 plugins do not support odd resolution.
* @{
* @ingroup ee_extensions_group
*/
/**
* Defines the Control ID to set converter output plane buffer layout.
*
* A value of type \c v4l2_nv_buffer_layout must be supplied with this control.
*
* @attention This control must be set before requesting buffers on the output plane.
*/
#define V4L2_CID_VIDEO_CONVERT_OUTPUT_PLANE_LAYOUT (V4L2_CID_MPEG_BASE+523)
/**
* Defines the Control ID to set converter capture plane buffer layout.
*
* A value of type \c v4l2_nv_buffer_layout must be supplied with this control.
*
* @attention This control must be set before requesting buffers on the capture plane.
*/
#define V4L2_CID_VIDEO_CONVERT_CAPTURE_PLANE_LAYOUT (V4L2_CID_MPEG_BASE+524)
/**
* Defines the Control ID to set the converter flip/rotation method.
*
* A value of type \c v4l2_flip_method must be supplied with this control.
*
* @attention This control must be set before requesting buffers on either plane.
*/
#define V4L2_CID_VIDEO_CONVERT_FLIP_METHOD (V4L2_CID_MPEG_BASE+525)
/**
* Defines the Control ID to set the converter interpolation method.
*
* A value of type \c v4l2_interpolation_method must be supplied with this control.
*
* @attention This control must be set before requesting buffers on either plane.
*/
#define V4L2_CID_VIDEO_CONVERT_INTERPOLATION_METHOD (V4L2_CID_MPEG_BASE+526)
/**
* Defines the Control ID to set the converter Temporal Noise Reduction (TNR) algorithm.
*
* A value of type \c v4l2_tnr_algorithm must be supplied with this control.
*
* @attention This control must be set before requesting buffers on either plane.
* @attention TNR algorithms are not supported with YUV422 and YUV444 capture
* plane formats.
*/
#define V4L2_CID_VIDEO_CONVERT_TNR_ALGORITHM (V4L2_CID_MPEG_BASE+527)
/** @} */
/**
* @defgroup V4L2Enc V4L2 Video Encoder
*
* @brief NVIDIA V4L2 Video Encoder Description and Extensions
*
* The video encoder device node is \c "/dev/nvhost-msenc".
*
* ### Supported Pixelformats
* OUTPUT PLANE | CAPTURE PLANE | PLATFORM
* :---------------------: | :-----------------: | :--------------------:
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_H264 | T210, T186, T194, T234
* V4L2_PIX_FMT_NV12M | |
* V4L2_PIX_FMT_YUV444M | |
* V4L2_PIX_FMT_NV24M | |
* | |
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_H265 | T210, T186, T194, T234
* V4L2_PIX_FMT_NV12M | |
* V4L2_PIX_FMT_YUV444M | |
* V4L2_PIX_FMT_NV24M | |
* V4L2_PIX_FMT_P010M | |
* V4L2_PIX_FMT_NV24_10LE | |
* | |
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_VP8 | T210, T186
* V4L2_PIX_FMT_NV12M | |
* | |
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_VP9 | T186, T194
* V4L2_PIX_FMT_NV12M | |
* | |
* V4L2_PIX_FMT_YUV420M | V4L2_PIX_FMT_AV1 | T234
* V4L2_PIX_FMT_NV12M | |
*
* ### Supported Memory Types
* MEMORY | OUTPUT PLANE | CAPTURE PLANE
* :------------------: | :----------: | :-----------:
* V4L2_MEMORY_MMAP | Y | Y
* V4L2_MEMORY_DMABUF | Y | N
* V4L2_MEMORY_USERPTR | N | N
* \attention For the video encoder, it is necessary that the capture plane
* format be set before the output plane format and only then request buffers on
* any of the planes.
*
* ### Supported Controls
* The following sections describe the supported controls.
*
* #### Controls From the Open Source V4L2-Controls Header
* Control ID | Purpose | Runtime Configurable
* -------------------------------- | -------------------- | :------------------:
* V4L2_CID_MPEG_VIDEO_BITRATE | Bitrate | Y
* V4L2_CID_MPEG_VIDEO_H264_PROFILE | H.264 Encode Profile | N
* V4L2_CID_MPEG_VIDEO_BITRATE_MODE | Rate Control Mode | N
* V4L2_CID_MPEG_VIDEO_GOP_SIZE | I-frame Interval | N
* V4L2_CID_MPEG_VIDEO_H264_LEVEL | Encode Level | N
* V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE | Force I-frame on one of queued output plane buffer | Y
*
* All non-runtime configurable options must be set after setting formats on
* both the planes and before requesting buffers on either plane.
*
* The runtime configurable parameters can be called anytime after setting
* formats on both the planes.
*
* #### NVIDIA-Specific Controls
* - #V4L2_CID_MPEG_VIDEO_H265_PROFILE
* - #V4L2_CID_MPEG_VIDEO_IDR_INTERVAL
* - #V4L2_CID_MPEG_VIDEOENC_TEMPORAL_TRADEOFF_LEVEL
* - #V4L2_CID_MPEG_VIDEOENC_SLICE_LENGTH_PARAM
* - #V4L2_CID_MPEG_VIDEOENC_ROI_PARAMS
* - #V4L2_CID_MPEG_VIDEOENC_VIRTUALBUFFER_SIZE
* - #V4L2_CID_MPEG_VIDEOENC_NUM_REFERENCE_FRAMES
* - #V4L2_CID_MPEG_VIDEOENC_SLICE_INTRAREFRESH_PARAM
* - #V4L2_CID_MPEG_VIDEOENC_NUM_BFRAMES
* - #V4L2_CID_MPEG_VIDEOENC_INSERT_SPS_PPS_AT_IDR
* - #V4L2_CID_MPEG_VIDEOENC_METADATA
* - #V4L2_CID_MPEG_VIDEOENC_METADATA_MV
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_METADATA_MV
* - #V4L2_CID_MPEG_VIDEOENC_QP_RANGE
* - #V4L2_CID_MPEG_VIDEOENC_HW_PRESET_TYPE_PARAM
* - #V4L2_CID_MPEG_VIDEOENC_INPUT_METADATA
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_EXTERNAL_RPS_CONTROL
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_EXTERNAL_RATE_CONTROL
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_ROI_PARAM
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_RECONCRC_PARAM
* - #V4L2_CID_MPEG_VIDEOENC_INSERT_VUI
* - #V4L2_CID_MPEG_VIDEOENC_INSERT_AUD
* - #V4L2_CID_MPEG_VIDEOENC_EXTEDED_COLORFORMAT
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_ALLIFRAME_ENCODE
* - #V4L2_CID_MPEG_VIDEOENC_H265_LEVEL
* - #V4L2_CID_MPEG_VIDEOENC_ENABLE_SLICE_LEVEL_ENCODE
* - #V4L2_CID_MPEG_VIDEOENC_POC_TYPE
* - #V4L2_CID_MPEG_VIDEOENC_H265_VUI_EXT_SAR_WIDTH
* - #V4L2_CID_MPEG_VIDEOENC_H265_VUI_EXT_SAR_HEIGHT
* - #V4L2_CID_MPEG_VIDEOENC_FORCE_INTRA_FRAME
* - #V4L2_CID_MPEG_VIDEOENC_FORCE_IDR_FRAME
* - #V4L2_CID_MPEG_VIDEOENC_AV1_HEADERS_WITH_FRAME
* - #V4L2_CID_MPEG_VIDEOENC_AV1_TILE_CONFIGURATION
* - #V4L2_CID_MPEG_VIDEOENC_AV1_ENABLE_SSIMRDO
* - #V4L2_CID_MPEG_VIDEOENC_AV1_DISABLE_CDF_UPDATE
* - #V4L2_CID_MPEG_VIDEOENC_PPE_INIT_PARAMS
*
* #### Setting Framerate
* The encoder framerate can be set with \c VIDIOC_S_PARM IOCTL by setting the numerator
* and denominator in `v4l2_streamparm.parm.output.timeperframe`.
*
* ### Supported Encoder Profiles
* #### H.264
* - V4L2_MPEG_VIDEO_H264_PROFILE_MAIN
* - V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE
* - V4L2_MPEG_VIDEO_H264_PROFILE_HIGH
*
* #### H.265
* - V4L2_MPEG_VIDEO_H265_PROFILE_MAIN
* - V4L2_MPEG_VIDEO_H265_PROFILE_MAIN10
*
* ### Encoder Output Metadata
* The encoder supports reporting frame related metadata, including motion vectors
* for that frame. See \c V4L2_CID_MPEG_VIDEOENC_METADATA,
* \c V4L2_CID_MPEG_VIDEOENC_METADATA_MV and \c V4L2_CID_MPEG_VIDEOENC_ENABLE_METADATA_MV
* for more information.
*
* ### EOS Handling
* The following sequence must be followed for sending EOS and recieving EOS
* from the encoder.
* -# Send EOS to encoder by queueing on the output plane a buffer with
* bytesused = 0 for the 0th plane (`v4l2_buffer.m.planes[0].bytesused = 0`).
* -# Dequeues buffers on the capture plane until it gets a buffer with bytesused = 0
* for the 0th plane.
*
* @note Currently, V4L2 plugins do not support odd resolution.
* @{
* @ingroup ee_extensions_group
*/
/**
* Defines the Control ID to configure encoder to drop frames while encoding.
*
* A value of type \c v4l2_enc_temporal_tradeoff_level_type must be supplied
* with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_TEMPORAL_TRADEOFF_LEVEL (V4L2_CID_MPEG_BASE+528)
/**
* Defines the Control ID to configure encoder slice length either in terms of MBs or bits.
*
* A pointer to a valid \c v4l2_enc_slice_length_param structure must be supplied
* with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_SLICE_LENGTH_PARAM (V4L2_CID_MPEG_BASE+529)
/**
* Defines the Control ID to configure encoder to encode particular region of frame in high
* quality.
*
* A pointer to a valid \c v4l2_enc_frame_ROI_params structure must be supplied
* with this control.
*
* @attention This control must be set after requesting buffers on both the
* planes.
*/
#define V4L2_CID_MPEG_VIDEOENC_ROI_PARAMS (V4L2_CID_MPEG_BASE+530)
/**
* Defines the Control ID to specify virtual buffer size in bits for encoder.
*
* A pointer to a valid \c v4l2_enc_virtual_buffer_size structure must be
* supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_VIRTUALBUFFER_SIZE (V4L2_CID_MPEG_BASE+531)
/**
* Defines the Control ID to specify maximum number of reference frames that can be used.
*
* An integer value must be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_NUM_REFERENCE_FRAMES (V4L2_CID_MPEG_BASE+532)
/**
* Defines the Control ID to specify the encoder slice intra refresh interval.
*
* A pointer to a valid \c v4l2_enc_slice_intrarefresh_param structure must be
* supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_SLICE_INTRAREFRESH_PARAM (V4L2_CID_MPEG_BASE+533)
/**
* Defines the Control ID to set number of B frames to be encoded between two P frames.
*
* This works with H.264 encoder. This also works with H.265 encoder for Jetson Xavier and
* Jetson Xavier NX platforms. An integer value must be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_NUM_BFRAMES (V4L2_CID_MPEG_BASE+534)
/**
* Defines the Control ID to enable/disable inserting SPS and PPS explicitly at IDR interval.
*
* A boolean value must be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_INSERT_SPS_PPS_AT_IDR (V4L2_CID_MPEG_BASE+535)
/**
* Defines the Control ID to get encoder output metadata.
*
* A pointer to valid #v4l2_ctrl_video_metadata structure must be supplied with
* this control.
*
* @attention This control must be read after dequeueing a buffer successfully from
* the capture plane. The values in the structure are valid until the buffer is queued
* again.
*/
#define V4L2_CID_MPEG_VIDEOENC_METADATA (V4L2_CID_MPEG_BASE+536)
/**
* Defines the Control ID to enable/disable encoder motion vector reporting.
*
* A boolean value must be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_METADATA_MV (V4L2_CID_MPEG_BASE+537)
/**
* Defines the Control ID to get encoder output motion vector metadata.
*
* A pointer to valid \c v4l2_ctrl_videoenc_outputbuf_metadata_MV structure must
* be supplied with this control.
*
* @attention This control must be read after dequeueing a buffer successfully from
* the capture plane. The values in the structure are valid until the buffer is queued
* again.
*/
#define V4L2_CID_MPEG_VIDEOENC_METADATA_MV (V4L2_CID_MPEG_BASE+538)
/**
* Defines the Control ID to set QP range for I/P/B frames.
*
* A pointer to a valid \c v4l2_ctrl_video_qp_range structure must
* be supplied with this control.
*
* @attention This control must be set after setting formats on both the planes
* and before requesting buffers on either plane.
*/
#define V4L2_CID_MPEG_VIDEOENC_QP_RANGE (V4L2_CID_MPEG_BASE+539)
/**
* Defines the Control ID to set encoder HW Preset type.