[BUG] - Error in the ITER_Cyl_SDDR geometry

[mcampos16]

According to the description of the ITER_Cyl_SDDR geometry in the JADE benchmark documentation (and to other sources like this paper), there is a 2cm gap between the rear plate and the outer cylinder (see screenshots below):

When plotting the ITER_Cyl_SDDR geometry available in this repository, I spotted that the cell corresponding to that gap is filled with material. Going back to the MCNP input file, I confirmed that the cell corresponding to that part of the gap (cell 3600), instead of being void, was indeed filled with steel:

I suspect that this is an error in the ITER_Cyl_SDDR geometry, as I believe that this cell should be void.