From 49962cafb84889913c3e9a85cb811b4fb006b6bd Mon Sep 17 00:00:00 2001 From: "Salvador E. Tropea" Date: Wed, 2 Mar 2022 18:16:51 -0300 Subject: [PATCH] Added some basic layer and schematic inclusion in reports. - Related to #93 --- kibot/out_report.py | 37 +++++++++++++++++ kibot/report_templates/report_full.txt | 41 +++++++++++++++++++ .../reference/5_1_6/light_control-report.txt | 33 +++++++++++++++ .../reference/6_0_0/light_control-report.txt | 36 ++++++++++++++++ tests/test_plot/test_misc.py | 2 +- tests/yaml_samples/report_simple_1.kibot.yaml | 27 ++++++++++++ 6 files changed, 175 insertions(+), 1 deletion(-) diff --git a/kibot/out_report.py b/kibot/out_report.py index 6bed092a2..2897b5631 100644 --- a/kibot/out_report.py +++ b/kibot/out_report.py @@ -9,8 +9,10 @@ from .gs import GS from .misc import UI_SMD, UI_VIRTUAL, MOD_THROUGH_HOLE, MOD_SMD, MOD_EXCLUDE_FROM_POS_FILES +from .registrable import RegOutput from .out_base import BaseOptions from .error import KiPlotConfigurationError +from .kiplot import config_output from .macros import macros, document, output_class # noqa: F401 from . import log @@ -244,6 +246,22 @@ def context_stackup(self, line): text += self.do_replacements(line, context) return text + def context_layer_pdfs(self, line): + """ Replace iterator for the `layer_pdfs` context """ + text = '' + for s in self._layer_pdfs: + context = {'path': s[0], 'comment': s[1], 'new_line': '\n'} + text += self.do_replacements(line, context) + return text + + def context_schematic_pdfs(self, line): + """ Replace iterator for the `schematic_pdfs` context """ + text = '' + for s in self._schematic_pdfs: + context = {'path': s[0], 'comment': s[1], 'new_line': '\n'} + text += self.do_replacements(line, context) + return text + @staticmethod def is_pure_smd_5(m): return m.GetAttributes() == UI_SMD @@ -531,6 +549,25 @@ def run(self, fname): self.stackup = 'yes' if GS.stackup else '' self._stackup = GS.stackup if GS.stackup else [] self.collect_data(GS.board) + base_dir = os.path.dirname(fname) + self._layer_pdfs = [] + self._schematic_pdfs = [] + for o in RegOutput.get_outputs(): + if o.type == 'pdf_pcb_print': + if not o._configured: + config_output(o) + out_file = o.get_targets(o.expand_dirname(os.path.join(GS.out_dir, o.dir)))[0] + rel_path = os.path.relpath(out_file, base_dir) + self._layer_pdfs.append((rel_path, o.comment)) + elif o.type == 'pdf_sch_print': + if not o._configured: + config_output(o) + out_files = o.get_targets(o.expand_dirname(os.path.join(GS.out_dir, o.dir))) + for of in out_files: + rel_path = os.path.relpath(of, base_dir) + self._schematic_pdfs.append((rel_path, o.comment)) + self.layer_pdfs = len(self._layer_pdfs) > 0 + self.schematic_pdfs = len(self._schematic_pdfs) > 0 self.do_template(self.template, fname) diff --git a/kibot/report_templates/report_full.txt b/kibot/report_templates/report_full.txt index f221cd202..49f4f570d 100644 --- a/kibot/report_templates/report_full.txt +++ b/kibot/report_templates/report_full.txt @@ -1,19 +1,26 @@ # PCB Board size: ${bb_w_mm}x${bb_h_mm} mm (${bb_w_in}x${bb_h_in} inches) + - This is the size of the rectangle that contains the board - Thickness: ${thickness_mm} mm (${thickness_mils} mils) - Material: ${pcb_material} - Finish: ${pcb_finish} - Layers: ${layers} - Copper thickness: ${copper_thickness} µm + Solder mask: ${solder_mask} + - Color: ${solder_mask_color_text} + Silk screen: ${silk_screen} + - Color: ${silk_screen_color_text} #?edge_connector or castellated_pads or edge_plating Special features: +#?edge_connector or castellated_pads or edge_plating + #?edge_connector - Edge connector: ${edge_connector} #?castellated_pads @@ -23,8 +30,12 @@ Special features: #?stackup Stackup: +#?stackup and impedance_controlled + #?stackup and impedance_controlled Impedance controlled: YES +#?stackup + #?stackup | Name | Type | Color | Thickness | Material | Epsilon_r | Loss tangent | #?stackup @@ -36,16 +47,24 @@ Impedance controlled: YES # Important sizes Clearance: ${clearance_mm} mm (${clearance_mils} mils) + Track width: ${track_mm} mm (${track_mils} mils) + - By design rules: ${track_d_mm} mm (${track_d_mils} mils) + Drill: ${drill_mm} mm (${drill_mils} mils) + - Vias: ${via_drill_mm} mm (${via_drill_mils} mils) [Design: ${via_drill_d_mm} mm (${via_drill_d_mils} mils)] - Pads: ${pad_drill_mm} mm (${pad_drill_mils} mils) + Via: ${via_pad_mm}/${via_drill_mm} mm (${via_pad_mils}/${via_drill_mils} mils) + - By design rules: ${via_pad_d_mm}/${via_drill_d_mm} mm (${via_pad_d_mils}/${via_drill_d_mils} mils) - Micro via: ${micro_vias} [${uvia_pad_mm}/${uvia_drill_mm} mm (${uvia_pad_mils}/${uvia_drill_mils} mils)] - Burried/blind via: ${blind_vias} + Outer Annular Ring: ${oar_mm} mm (${oar_mils} mils) + - By design rules: ${oar_d_mm} mm (${oar_d_mils} mils) Eurocircuits class: ${pattern_class}${drill_class} @@ -54,20 +73,42 @@ Eurocircuits class: ${pattern_class}${drill_class} # General stats Components count: (SMD/THT) + - Top: ${top_smd}/${top_tht} (${top_comp_type}) - Bottom: ${bot_smd}/${bot_tht} (${bot_comp_type}) Defined tracks: + #defined_tracks:- ${track_mm} mm (${track_mils} mils) Used tracks: + #used_tracks:- ${track_mm} mm (${track_mils} mils) (${count}) defined: ${defined} Defined vias: + #defined_vias:- ${pad_mm}/${drill_mm} mm (${pad_mils}/${drill_mils} mils) Used vias: + #used_vias:- ${pad_mm}/${drill_mm} mm (${pad_mils}/${drill_mils} mils) (Count: ${count}, Aspect: ${aspect} ${producibility_level}) defined: ${defined} Holes (excluding vias): + #hole_sizes_no_vias:- ${drill_mm} mm (${drill_mils} mils) (${count}) + + +#?schematic_pdfs +# Schematic +#?schematic_pdfs + +#?schematic_pdfs +#schematic_pdfs:![${comment}](${path}){ width=16.5cm height=11.7cm }${new_line} + + +#?layer_pdfs +# PCB Layers +#?layer_pdfs + +#?layer_pdfs +#layer_pdfs:![${comment}](${path}){ width=16.5cm height=11.7cm }${new_line} diff --git a/tests/reference/5_1_6/light_control-report.txt b/tests/reference/5_1_6/light_control-report.txt index b1110b800..7c892c1b9 100644 --- a/tests/reference/5_1_6/light_control-report.txt +++ b/tests/reference/5_1_6/light_control-report.txt @@ -1,31 +1,44 @@ # PCB Board size: 59.69x48.26 mm (2.35x1.9 inches) + - This is the size of the rectangle that contains the board - Thickness: 1.6 mm (63 mils) - Material: FR4 - Finish: ENIG - Layers: 4 - Copper thickness: 35 µm + Solder mask: TOP / BOTTOM + - Color: Top: Blue / Bottom: Red + Silk screen: TOP / BOTTOM + - Color: White # Important sizes Clearance: 0.15 mm (6 mils) + Track width: 0.15 mm (6 mils) + - By design rules: 0.13 mm (5 mils) + Drill: 0.25 mm (10 mils) + - Vias: 0.25 mm (10 mils) [Design: 0.2 mm (8 mils)] - Pads: 0.6 mm (24 mils) + Via: 0.51/0.25 mm (20/10 mils) + - By design rules: 0.46/0.2 mm (18/8 mils) - Micro via: no [0.2/0.1 mm (8/4 mils)] - Burried/blind via: no + Outer Annular Ring: 0.25 mm (10 mils) + - By design rules: 0.25 mm (10 mils) Eurocircuits class: 6D @@ -34,32 +47,52 @@ Eurocircuits class: 6D # General stats Components count: (SMD/THT) + - Top: 61/12 (SMD + THT) - Bottom: 0/0 (NONE) Defined tracks: + - 0.15 mm (6 mils) - 0.25 mm (10 mils) - 0.3 mm (12 mils) - 0.64 mm (25 mils) Used tracks: + - 0.15 mm (6 mils) (276) defined: yes - 0.3 mm (12 mils) (11) defined: yes - 0.64 mm (25 mils) (175) defined: yes Defined vias: + - 0.51/0.25 mm (20/10 mils) - 0.8/0.4 mm (31/16 mils) - 0.89/0.51 mm (35/20 mils) Used vias: + - 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes - 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes Holes (excluding vias): + - 0.8 mm (31 mils) (4) - 0.85 mm (33 mils) (2) - 0.95 mm (37 mils) (3) - 1.2 mm (47 mils) (20) - 3.2 mm (126 mils) (4) + + +# Schematic + +![Schematic](Schematic.pdf){ width=16.5cm height=11.7cm } + + + +# PCB Layers + +![Top copper and silkscreen](Layers/light_control-F_Cu+F_SilkS.pdf){ width=16.5cm height=11.7cm } + +![Bottom copper and silkscreen](Layers/light_control-B_Cu+B_SilkS.pdf){ width=16.5cm height=11.7cm } + diff --git a/tests/reference/6_0_0/light_control-report.txt b/tests/reference/6_0_0/light_control-report.txt index 3ececd942..15036404b 100644 --- a/tests/reference/6_0_0/light_control-report.txt +++ b/tests/reference/6_0_0/light_control-report.txt @@ -1,24 +1,32 @@ # PCB Board size: 59.69x48.26 mm (2.35x1.9 inches) + - This is the size of the rectangle that contains the board - Thickness: 1.6 mm (63 mils) - Material: FR4 - Finish: ENIG - Layers: 4 - Copper thickness: 35 µm + Solder mask: TOP / BOTTOM + - Color: Top: Blue / Bottom: Red + Silk screen: TOP / BOTTOM + - Color: Top: White / Bottom: Black Special features: + - Edge connector: yes, bevelled - Castellated pads - Edge plating Stackup: + Impedance controlled: YES + | Name | Type | Color | Thickness | Material | Epsilon_r | Loss tangent | |----------------------|----------------------|----------|-----------|-----------------|-----------|--------------| | F.SilkS | Top Silk Screen | White | | Liquid Photo | | | @@ -38,16 +46,24 @@ Impedance controlled: YES # Important sizes Clearance: 0.15 mm (6 mils) + Track width: 0.15 mm (6 mils) + - By design rules: 0.13 mm (5 mils) + Drill: 0.25 mm (10 mils) + - Vias: 0.25 mm (10 mils) [Design: 0.2 mm (8 mils)] - Pads: 0.6 mm (24 mils) + Via: 0.51/0.25 mm (20/10 mils) + - By design rules: 0.46/0.2 mm (18/8 mils) - Micro via: no [0.2/0.1 mm (8/4 mils)] - Burried/blind via: no + Outer Annular Ring: 0.25 mm (10 mils) + - By design rules: 0.25 mm (10 mils) Eurocircuits class: 6D @@ -56,30 +72,50 @@ Eurocircuits class: 6D # General stats Components count: (SMD/THT) + - Top: 61/12 (SMD + THT) - Bottom: 0/0 (NONE) Defined tracks: + - 0.15 mm (6 mils) - 0.3 mm (12 mils) - 0.64 mm (25 mils) Used tracks: + - 0.15 mm (6 mils) (276) defined: yes - 0.3 mm (12 mils) (11) defined: yes - 0.64 mm (25 mils) (175) defined: yes Defined vias: + - 0.51/0.25 mm (20/10 mils) - 0.89/0.51 mm (35/20 mils) Used vias: + - 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes - 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes Holes (excluding vias): + - 0.8 mm (31 mils) (4) - 0.85 mm (33 mils) (2) - 0.95 mm (37 mils) (3) - 1.2 mm (47 mils) (20) - 3.2 mm (126 mils) (4) + + +# Schematic + +![Schematic](Schematic.pdf){ width=16.5cm height=11.7cm } + + + +# PCB Layers + +![Top copper and silkscreen](Layers/light_control-F_Cu+F_SilkS.pdf){ width=16.5cm height=11.7cm } + +![Bottom copper and silkscreen](Layers/light_control-B_Cu+B_SilkS.pdf){ width=16.5cm height=11.7cm } + diff --git a/tests/test_plot/test_misc.py b/tests/test_plot/test_misc.py index 3310d5f91..f69f4fb85 100644 --- a/tests/test_plot/test_misc.py +++ b/tests/test_plot/test_misc.py @@ -997,7 +997,7 @@ def test_qr_lib_1(test_dir): def test_report_simple_1(test_dir): prj = 'light_control' ctx = context.TestContext(test_dir, 'test_report_simple_1', prj, 'report_simple_1', POS_DIR) - ctx.run() + ctx.run(extra=['report_full', 'report_simple']) ctx.expect_out_file(prj+'-report.txt') ctx.expect_out_file(prj+'-report_simple.txt') ctx.compare_txt(prj+'-report.txt') diff --git a/tests/yaml_samples/report_simple_1.kibot.yaml b/tests/yaml_samples/report_simple_1.kibot.yaml index f5f381dee..4a7ee7e9d 100644 --- a/tests/yaml_samples/report_simple_1.kibot.yaml +++ b/tests/yaml_samples/report_simple_1.kibot.yaml @@ -19,3 +19,30 @@ outputs: output_id: _simple options: template: simple + + - name: 'print_front' + comment: "Top copper and silkscreen" + type: pdf_pcb_print + dir: Layers + options: + title: 'Fake title for front copper and silk' + layers: + - layer: F.Cu + - layer: F.SilkS + + - name: 'print_bottom' + comment: "Bottom copper and silkscreen" + type: pdf_pcb_print + dir: Layers + options: + title: 'Fake title for bottom copper and silk' + layers: + - layer: B.Cu + - layer: B.SilkS + + - name: 'print_sch' + comment: "Schematic" + type: pdf_sch_print + dir: . + options: + output: Schematic.pdf