diff --git a/Make.inc b/Make.inc index 9d6e20bf8bd45..24ec6db63e4a2 100644 --- a/Make.inc +++ b/Make.inc @@ -928,17 +928,17 @@ LIBUNWIND:= else ifeq ($(USE_SYSTEM_LIBUNWIND), 1) ifneq ($(OS),Darwin) -LIBUNWIND:=-lunwind-generic -lunwind +LIBUNWIND:=-lunwind # Only for linux since we want to use not yet released libunwind features JCFLAGS+=-DSYSTEM_LIBUNWIND JCPPFLAGS+=-DSYSTEM_LIBUNWIND endif else ifeq ($(OS),Darwin) -LIBUNWIND:=$(build_libdir)/libosxunwind.a +LIBUNWIND:=-losxunwind JCPPFLAGS+=-DLIBOSXUNWIND else -LIBUNWIND:=$(build_libdir)/libunwind-generic.a $(build_libdir)/libunwind.a +LIBUNWIND:=-lunwind endif endif endif @@ -1194,12 +1194,12 @@ OSLIBS += -lelf -lkvm -lrt -lpthread OSLIBS += -lgcc_s OSLIBS += -Wl,--export-dynamic -Wl,--version-script=$(JULIAHOME)/src/julia.expmap \ - $(NO_WHOLE_ARCHIVE) $(LIBUNWIND) + $(NO_WHOLE_ARCHIVE) endif ifeq ($(OS), Darwin) SHLIB_EXT := dylib -OSLIBS += -framework CoreFoundation $(LIBUNWIND) +OSLIBS += -framework CoreFoundation WHOLE_ARCHIVE := -Xlinker -all_load NO_WHOLE_ARCHIVE := JLDFLAGS := diff --git a/Makefile b/Makefile index 9e1a697b739ee..9e9f2c8f0c900 100644 --- a/Makefile +++ b/Makefile @@ -181,6 +181,11 @@ endif ifeq ($(USE_LLVM_SHLIB),1) JL_PRIVATE_LIBS-$(USE_SYSTEM_LLVM) += libLLVM libLLVM-9jl endif +ifeq ($(OS),Darwin) +JL_PRIVATE_LIBS-$(USE_SYSTEM_LIBUNWIND) += libosxunwind +else +JL_PRIVATE_LIBS-$(USE_SYSTEM_LIBUNWIND) += libunwind +endif ifeq ($(USE_SYSTEM_LIBM),0) JL_PRIVATE_LIBS-$(USE_SYSTEM_OPENLIBM) += libopenlibm diff --git a/base/file.jl b/base/file.jl index bb5a203a0e554..66640a20a39a7 100644 --- a/base/file.jl +++ b/base/file.jl @@ -890,12 +890,11 @@ function unlink(p::AbstractString) end # For move command -function rename(src::AbstractString, dst::AbstractString) +function rename(src::AbstractString, dst::AbstractString; force::Bool=false) err = ccall(:jl_fs_rename, Int32, (Cstring, Cstring), src, dst) # on error, default to cp && rm if err < 0 - # force: is already done in the mv function - cp(src, dst; force=false, follow_symlinks=false) + cp(src, dst; force=force, follow_symlinks=false) rm(src; recursive=true) end nothing diff --git a/base/loading.jl b/base/loading.jl index ec8283edc0896..f63bb6bfefaf3 100644 --- a/base/loading.jl +++ b/base/loading.jl @@ -1256,9 +1256,9 @@ const MAX_NUM_PRECOMPILE_FILES = 10 function compilecache(pkg::PkgId, path::String) # decide where to put the resulting cache file cachefile = compilecache_path(pkg) + cachepath = dirname(cachefile) # prune the directory with cache files if pkg.uuid !== nothing - cachepath = dirname(cachefile) entrypath, entryfile = cache_file_entry(pkg) cachefiles = filter!(x -> startswith(x, entryfile * "_"), readdir(cachepath)) if length(cachefiles) >= MAX_NUM_PRECOMPILE_FILES @@ -1276,20 +1276,34 @@ function compilecache(pkg::PkgId, path::String) # run the expression and cache the result verbosity = isinteractive() ? CoreLogging.Info : CoreLogging.Debug @logmsg verbosity "Precompiling $pkg" - p = create_expr_cache(path, cachefile, concrete_deps, pkg.uuid) - if success(p) - # append checksum to the end of the .ji file: - open(cachefile, "a+") do f - write(f, _crc32c(seekstart(f))) + + # create a temporary file in `cachepath` directory, write the cache in it, + # write the checksum, _and then_ atomically move the file to `cachefile`. + tmppath, tmpio = mktemp(cachepath) + local p + try + close(tmpio) + p = create_expr_cache(path, tmppath, concrete_deps, pkg.uuid) + if success(p) + # append checksum to the end of the .ji file: + open(tmppath, "a+") do f + write(f, _crc32c(seekstart(f))) + end + # inherit permission from the source file + chmod(tmppath, filemode(path) & 0o777) + + # this is atomic according to POSIX: + rename(tmppath, cachefile; force=true) + return cachefile end - # inherit permission from the source file - chmod(cachefile, filemode(path) & 0o777) - elseif p.exitcode == 125 + finally + rm(tmppath, force=true) + end + if p.exitcode == 125 return PrecompilableError() else error("Failed to precompile $pkg to $cachefile.") end - return cachefile end module_build_id(m::Module) = ccall(:jl_module_build_id, UInt64, (Any,), m) diff --git a/base/reduce.jl b/base/reduce.jl index e772929787f5a..598ce088da51c 100644 --- a/base/reduce.jl +++ b/base/reduce.jl @@ -861,7 +861,15 @@ julia> count([true, false, true, true]) """ count(itr) = count(identity, itr) -count(f, itr) = mapreduce(_bool(f), add_sum, itr, init=0) +count(f, itr) = _simple_count(f, itr) + +function _simple_count(pred, itr) + n = 0 + for x in itr + n += pred(x)::Bool + end + return n +end function count(::typeof(identity), x::Array{Bool}) n = 0 diff --git a/base/reducedim.jl b/base/reducedim.jl index 75ba333211cf3..82febb133f132 100644 --- a/base/reducedim.jl +++ b/base/reducedim.jl @@ -387,7 +387,10 @@ julia> count(<=(2), A, dims=2) ``` """ count(A::AbstractArrayOrBroadcasted; dims=:) = count(identity, A, dims=dims) -count(f, A::AbstractArrayOrBroadcasted; dims=:) = mapreduce(_bool(f), add_sum, A, dims=dims, init=0) +count(f, A::AbstractArrayOrBroadcasted; dims=:) = _count(f, A, dims) + +_count(f, A::AbstractArrayOrBroadcasted, dims::Colon) = _simple_count(f, A) +_count(f, A::AbstractArrayOrBroadcasted, dims) = mapreduce(_bool(f), add_sum, A, dims=dims, init=0) """ count!([f=identity,] r, A) diff --git a/base/ryu/shortest.jl b/base/ryu/shortest.jl index 641f0116729f4..e1463cad63a45 100644 --- a/base/ryu/shortest.jl +++ b/base/ryu/shortest.jl @@ -330,7 +330,8 @@ end olength = decimallength(output) exp_form = true pt = nexp + olength - if -4 < pt <= (precision == -1 ? (T == Float16 ? 3 : 6) : precision) + if -4 < pt <= (precision == -1 ? (T == Float16 ? 3 : 6) : precision) && + !(pt >= olength && abs(mod(x + 0.05, 10^(pt - olength)) - 0.05) > 0.05) exp_form = false if pt <= 0 buf[pos] = UInt8('0') diff --git a/base/set.jl b/base/set.jl index a3041ea927e3d..6b74da6c7e830 100644 --- a/base/set.jl +++ b/base/set.jl @@ -385,9 +385,7 @@ end allunique(::Union{AbstractSet,AbstractDict}) = true -allunique(r::AbstractRange{T}) where {T} = (step(r) != zero(T)) || (length(r) <= 1) -allunique(r::StepRange{T,S}) where {T,S} = (step(r) != zero(S)) || (length(r) <= 1) -allunique(r::StepRangeLen{T,R,S}) where {T,R,S} = (step(r) != zero(S)) || (length(r) <= 1) +allunique(r::AbstractRange) = !iszero(step(r)) || length(r) <= 1 filter!(f, s::Set) = unsafe_filter!(f, s) diff --git a/base/strings/util.jl b/base/strings/util.jl index e7abfa0bf3f98..3569130020512 100644 --- a/base/strings/util.jl +++ b/base/strings/util.jl @@ -521,7 +521,7 @@ function replace(str::String, pat_repl::Pair; count::Integer=typemax(Int)) i = k = nextind(str, k) end r = something(findnext(pattern,str,k), 0) - r == 0:-1 || n == count && break + r === 0:-1 || n == count && break j, k = first(r), last(r) n += 1 end diff --git a/contrib/mac/app/Entitlements.plist b/contrib/mac/app/Entitlements.plist index 2e0912b4c0bf4..b84dccb00f95c 100644 --- a/contrib/mac/app/Entitlements.plist +++ b/contrib/mac/app/Entitlements.plist @@ -4,6 +4,8 @@ com.apple.security.automation.apple-events + com.apple.security.cs.get-task-allow + com.apple.security.cs.allow-dyld-environment-variables com.apple.security.cs.allow-jit diff --git a/contrib/refresh_bb_tarballs.sh b/contrib/refresh_bb_tarballs.sh index 5cac80d52fd78..e76b2dccdb5ff 100755 --- a/contrib/refresh_bb_tarballs.sh +++ b/contrib/refresh_bb_tarballs.sh @@ -35,6 +35,12 @@ fi # Get "contrib/" directory path CONTRIB_DIR=$(CDPATH= cd -- "$(dirname -- "$0")" && pwd) +# Get the source hash for each project +for proj in ${BB_PROJECTS}; do + PROJ="$(echo ${proj} | tr [a-z] [A-Z])" + make -C "${CONTRIB_DIR}/../deps" USE_BINARYBUILDER_${PROJ}=0 DEPS_GIT=0 extract-${proj} +done + # For each triplet and each project, download the BB tarball and save its hash: for triplet in ${TRIPLETS}; do for proj in ${BB_PROJECTS}; do diff --git a/deps/Makefile b/deps/Makefile index e6a975ba18731..90e231f30e85d 100644 --- a/deps/Makefile +++ b/deps/Makefile @@ -157,7 +157,11 @@ ifneq ($(OS), WINNT) DEP_LIBS += libwhich endif -DEP_LIBS_STAGED := $(filter-out suitesparse-wrapper osxunwind,$(DEP_LIBS)) # unlist targets that have not been converted to use the staged-install +# unlist targets that have not been converted to use the staged-install +DEP_LIBS_STAGED := $(filter-out suitesparse-wrapper,$(DEP_LIBS)) +ifneq ($(USE_BINARYBUILDER_LIBUNWIND),1) +DEP_LIBS_STAGED := $(filter-out osxunwind,$(DEP_LIBS)) +endif ## Common build target prefixes diff --git a/deps/Versions.make b/deps/Versions.make index fc381abe4896b..be2303484ba7c 100644 --- a/deps/Versions.make +++ b/deps/Versions.make @@ -1,5 +1,5 @@ LLVM_VER = 9.0.1 -LLVM_BB_REL = 6 +LLVM_BB_REL = 8 PCRE_VER = 10.31 PCRE_BB_REL = 0 DSFMT_VER = 2.2.3 @@ -13,12 +13,13 @@ OPENLIBM_VER = 0.7.0 OPENLIBM_BB_REL = 0 UNWIND_VER = 1.3.1 UNWIND_BB_REL = 4 -OSXUNWIND_VER = 0.0.5 +OSXUNWIND_VER = 0.0.6 OSXUNWIND_BB_REL = 0 GMP_VER = 6.1.2 GMP_BB_REL = 4 -MPFR_VER = 4.0.2 MPFR_BB_REL = 2 +MPFR_VER = 4.1.0 +MPFR_BB_REL = 1 PATCHELF_VER = 0.9 MBEDTLS_VER = 2.16.0 MBEDTLS_BB_REL = 1 @@ -40,4 +41,4 @@ P7ZIP_BB_REL = 1 # Specify the version of the Mozilla CA Certificate Store to obtain. # The versions of cacert.pem are identified by the date (YYYY-MM-DD) of their changes. # See https://curl.haxx.se/docs/caextract.html for more details. -MOZILLA_CACERT_VERSION := 2020-01-01 +MOZILLA_CACERT_VERSION := 2020-07-22 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx03.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx03.tar.gz/md5 deleted file mode 100644 index 25ad515487ffb..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx03.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -820e29ee232dfb3f3dd3a1e6252a092d diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx03.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx03.tar.gz/sha512 deleted file mode 100644 index bb7f04eeb2400..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx03.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -67e2a5751b5dd1fc57a9a06aef7498ea32d31653bcc5c806f8fde6a6be42a562694ec283e721f6c33112095bda876f2653bfe642466e96e18aaded6281a3a944 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx11.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx11.tar.gz/md5 deleted file mode 100644 index 5490765976adc..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx11.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -26025efc645de8626736ce90caf5e550 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx11.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx11.tar.gz/sha512 deleted file mode 100644 index c4dc9c0eba4f3..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-gnu-cxx11.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -6724a19f05eb70e8a411bf70c5c49f0b122cefdf59cb6c99bc5da5e2c298df3449b6e032bca2389872bb2c2eff8d59b1ac399792256570811bff736dfa7d027e diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx03.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx03.tar.gz/md5 deleted file mode 100644 index 16c9a64325235..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx03.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -d4d389a1365f449584c293304f90254a diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx03.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx03.tar.gz/sha512 deleted file mode 100644 index 62530d15f3d39..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx03.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -f7046adda3f15347098ac426694961457ae0e34673befde8b8058d904745ada77ece51217d0e047039aaf45e74bd4763b87e3fdcc2a07a5c35eb30c28e6af700 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx11.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx11.tar.gz/md5 deleted file mode 100644 index 27ef3f3de6ee2..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx11.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -e0395a7182276cfc20c0f2e1d83b3223 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx11.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx11.tar.gz/sha512 deleted file mode 100644 index 57faa6cfae5a1..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.aarch64-linux-musl-cxx11.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -e8f7732da3e8b0f8172c673ce12c1e53f2c1e9f9c24e74e2ef0adef7bda43ade7ca28dadbc2a876907adbff34ca3a81dccc4edab0f9133d7f94d3e5f9204e7db diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx03.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx03.tar.gz/md5 deleted file mode 100644 index 9486a3e5ee855..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx03.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -72e6cd12c1e9d2346d0092a62aa521ee diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx03.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx03.tar.gz/sha512 deleted file mode 100644 index 7887bbeff6a38..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx03.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -3270e090fc282a7806e7459e7a6c0561a3ee638172d0ad6841f61c57bf84842e1a0819b9b6a4be02ac2a5d2ced85eb9e5113e22193254a5257f527663cb284c0 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx11.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx11.tar.gz/md5 deleted file mode 100644 index eac215619570e..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx11.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -3afa76198012e539d6fb58417ffc75fe diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx11.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx11.tar.gz/sha512 deleted file mode 100644 index a6c3855be3857..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-gnueabihf-cxx11.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -68aae6fa278f442cf7d4c9d51c16c3bfa340b524d697746632c6d36f47be6ef83f61757d68fb8ad9f065af44199b8864ba042658ceea3ccce139a2581dc21949 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx03.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx03.tar.gz/md5 deleted file mode 100644 index e0e3914ce5437..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx03.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -6d28d58c61da92ee59d8ded989911a89 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx03.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx03.tar.gz/sha512 deleted file mode 100644 index f5d81fcd0cf99..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx03.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -ae2ac396cafec1589279bed8525e4c9417e87af36a9a87694b31dbbb39d8c0900f9a05e0aba0f95324568b5e777bdd9e50056c573d5cdc6b1d5846d688a84324 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx11.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx11.tar.gz/md5 deleted file mode 100644 index 96147635b40d7..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx11.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -6747af86c9264357dc35ececbb82a2c2 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx11.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx11.tar.gz/sha512 deleted file mode 100644 index 639c99ccfb164..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.armv7l-linux-musleabihf-cxx11.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -5b7cb7d6576d5875f308f3fccb3defac90a7426f7889ea6e868c6677f5ba6e5e60a98c76b62c90b7e8f648abfeac909ad5ef3b35717122a3d7da00d177740bf3 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx03.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx03.tar.gz/md5 deleted file mode 100644 index 86a3e20422ec3..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx03.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -fbe7c189ed08859280e630847a369e8b diff --git a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx03.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx03.tar.gz/sha512 deleted file mode 100644 index e5a9200b1cbfb..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx03.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -078c8e844090bdba22de9a4d775a3f6591d581f5229ea256fba351ad38eee0a0fbbec39d1d8bc2b5711ad1104eecca02b31ada0d509d01e72dca6e2416c535c3 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx11.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx11.tar.gz/md5 deleted file mode 100644 index a4799e427603d..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx11.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -42cfb1e97a96aaf24dc630643b1161b9 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx11.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx11.tar.gz/sha512 deleted file mode 100644 index 403d8b272c310..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-gnu-cxx11.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -fff5fcc9acf18b3cae9e6bd5debe6b5afbf521787572f46daaed29c29198b2710f0c388588a805466acfb3bd470e263a676fdd259d49d74a4594acf5d7e34802 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-musl-cxx03.tar.gz/md5 b/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-musl-cxx03.tar.gz/md5 deleted file mode 100644 index 3102aa7d2fcbd..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-musl-cxx03.tar.gz/md5 +++ /dev/null @@ -1 +0,0 @@ -0bc13770ee11d026a116a031c9a7b753 diff --git a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-musl-cxx03.tar.gz/sha512 b/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-musl-cxx03.tar.gz/sha512 deleted file mode 100644 index 2f23c287fdc81..0000000000000 --- a/deps/checksums/LLVM_full.v9.0.1-6.i686-linux-musl-cxx03.tar.gz/sha512 +++ /dev/null @@ -1 +0,0 @@ -21a5d27441fb3603c852bee30fddd3eb52be7214704fbe61e73541fb1b31882bb1a1b60317bc92d313baada0eea912262bc56e7227506efe0d1e18d63b373551 diff --git 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+0,0 @@ -6d8a8bb46fe09ff44e21cdbf84f5cdac diff --git a/deps/checksums/mpfr-4.0.2.tar.bz2/sha512 b/deps/checksums/mpfr-4.0.2.tar.bz2/sha512 deleted file mode 100644 index d073360a775c8..0000000000000 --- a/deps/checksums/mpfr-4.0.2.tar.bz2/sha512 +++ /dev/null @@ -1 +0,0 @@ -18bb3a87123d02b7537bc298d41bdbb33e58b8c196cc4040578e3b470e86c6c89e1bd8ab8b3919d106fe5b86922ef8999dc1aba7c521ee90a69f690be288a30d diff --git a/deps/checksums/mpfr-4.1.0.tar.bz2/md5 b/deps/checksums/mpfr-4.1.0.tar.bz2/md5 new file mode 100644 index 0000000000000..c0d910b6130bf --- /dev/null +++ b/deps/checksums/mpfr-4.1.0.tar.bz2/md5 @@ -0,0 +1 @@ +44b892bc5a45bafb4294d134e13aad1d diff --git a/deps/checksums/mpfr-4.1.0.tar.bz2/sha512 b/deps/checksums/mpfr-4.1.0.tar.bz2/sha512 new file mode 100644 index 0000000000000..3ccc3031e1fee --- /dev/null +++ b/deps/checksums/mpfr-4.1.0.tar.bz2/sha512 @@ -0,0 +1 @@ +410208ee0d48474c1c10d3d4a59decd2dfa187064183b09358ec4c4666e34d74383128436b404123b831e585d81a9176b24c7ced9d913967c5fce35d4040a0b4 diff --git a/deps/llvm.mk b/deps/llvm.mk index 1eda48f91b065..18dc41e40f57f 100644 --- a/deps/llvm.mk +++ b/deps/llvm.mk @@ -410,6 +410,7 @@ $(eval $(call LLVM_PATCH,llvm-D75072-SCEV-add-type)) $(eval $(call LLVM_PATCH,llvm-9.0-D65174-limit-merge-stores)) # remove for 10.0 $(eval $(call LLVM_PATCH,llvm9-D71443-PPC-MC-redef-symbol)) # remove for 10.0 $(eval $(call LLVM_PATCH,llvm-9.0-D78196)) # remove for 11.0 +$(eval $(call LLVM_PATCH,llvm-9.0-D85499)) endif # LLVM_VER 9.0 ifeq ($(LLVM_VER_SHORT),10.0) diff --git a/deps/mpfr.mk b/deps/mpfr.mk index b2ea87801a89b..f05dc60cb0e29 100644 --- a/deps/mpfr.mk +++ b/deps/mpfr.mk @@ -6,14 +6,13 @@ endif ifneq ($(USE_BINARYBUILDER_MPFR),1) -ifeq ($(USE_SYSTEM_MPFR), 0) +MPFR_OPTS := --enable-thread-safe --enable-shared-cache --disable-float128 --disable-decimal-float ifeq ($(USE_SYSTEM_GMP), 0) -MPFR_OPTS := --with-gmp-include=$(abspath $(build_includedir)) --with-gmp-lib=$(abspath $(build_shlibdir)) -endif +MPFR_OPTS += --with-gmp-include=$(abspath $(build_includedir)) --with-gmp-lib=$(abspath $(build_shlibdir)) endif ifeq ($(BUILD_OS),WINNT) ifeq ($(OS),WINNT) -MPFR_OPTS += --disable-thread-safe CFLAGS="$(CFLAGS) -DNPRINTF_L -DNPRINTF_T -DNPRINTF_J" +MPFR_OPTS += CFLAGS="$(CFLAGS) -DNPRINTF_L -DNPRINTF_T -DNPRINTF_J" endif endif diff --git a/deps/patches/llvm-9.0-D85499.patch b/deps/patches/llvm-9.0-D85499.patch new file mode 100644 index 0000000000000..1be91fc4717f5 --- /dev/null +++ b/deps/patches/llvm-9.0-D85499.patch @@ -0,0 +1,425 @@ +commit ac8729e23232d0fd3933b76093a40b7c65332aff +Author: Keno Fischer +Date: Fri Aug 7 00:31:43 2020 -0400 + + [X86] Canonicalize andnp for bitmask arithmetic + + We have a DAG combine that tries to fold (vselect cond, 0000..., X) -> (andnp cond, x). + However, it does so by attempting to create an i64 vector with the number + of elements obtained by truncating division by 64 from the bitwidth. This is + bad for mask vectors like v8i1, since that division is just zero. Besides, + we don't want i64 vectors anyway. The easy change is just to avoid changing + the VT, but this is slightly problematic because the canonical pattern for + `kandn` is `(and (vnot a) b)` rather than `(x86andnp a b)`, so this fails + to select. Rather than playing games here with having the mask vectors + use a different canonical representation, the bulk of this commit switches + the canonical ISD representation for `kandn` to `(x86andnp a b)` such + that all vector types may be handled equally here. To avoid regressing + other tests, we need to extend a few other folds to handle `x86andnp` in + addition to plain `and`. However, that should be generally a good + improvement, since x86andnp is already canonical for non-i1 vectors + prior to this commit, and said folds were just missing. + + When all is said and done, fixes the issue reported in + https://github.com/JuliaLang/julia/issues/36955. + + Differential Revision: https://reviews.llvm.org/D85499 + +diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp +index 34ad589d205..eb21b0de89d 100644 +--- a/lib/Target/X86/X86ISelDAGToDAG.cpp ++++ b/lib/Target/X86/X86ISelDAGToDAG.cpp +@@ -503,7 +503,7 @@ namespace { + bool isMaskZeroExtended(SDNode *N) const; + bool tryShiftAmountMod(SDNode *N); + bool tryShrinkShlLogicImm(SDNode *N); +- bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask); ++ bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask, bool Invert); + + MachineSDNode *emitPCMPISTR(unsigned ROpc, unsigned MOpc, bool MayFoldLoad, + const SDLoc &dl, MVT VT, SDNode *Node); +@@ -2998,7 +2998,7 @@ bool X86DAGToDAGISel::foldLoadStoreIntoMemOperand(SDNode *Node) { + bool IsNegOne = isAllOnesConstant(StoredVal.getOperand(1)); + // ADD/SUB with 1/-1 and carry flag isn't used can use inc/dec. + if ((IsOne || IsNegOne) && hasNoCarryFlagUses(StoredVal.getValue(1))) { +- unsigned NewOpc = ++ unsigned NewOpc = + ((Opc == X86ISD::ADD) == IsOne) + ? SelectOpcode(X86::INC64m, X86::INC32m, X86::INC16m, X86::INC8m) + : SelectOpcode(X86::DEC64m, X86::DEC32m, X86::DEC16m, X86::DEC8m); +@@ -3999,8 +3999,8 @@ static unsigned getVPTESTMOpc(MVT TestVT, bool IsTestN, bool FoldedLoad, + + // Try to create VPTESTM instruction. If InMask is not null, it will be used + // to form a masked operation. +-bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, +- SDValue InMask) { ++bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue InMask, ++ bool Invert) { + assert(Subtarget->hasAVX512() && "Expected AVX512!"); + assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 && + "Unexpected VT!"); +@@ -4140,6 +4140,9 @@ bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, + } + + bool IsTestN = CC == ISD::SETEQ; ++ if (Invert) ++ IsTestN = !IsTestN; ++ + unsigned Opc = getVPTESTMOpc(CmpVT, IsTestN, FoldedLoad, FoldedBCast, + IsMasked); + +@@ -4309,16 +4312,27 @@ void X86DAGToDAGISel::Select(SDNode *Node) { + return; + break; + ++ case X86ISD::ANDNP: ++ if (NVT.isVector() && NVT.getVectorElementType() == MVT::i1) { ++ SDValue N0 = Node->getOperand(0); ++ SDValue N1 = Node->getOperand(1); ++ // Try to form a masked VPTESTM ++ if (N0.getOpcode() == ISD::SETCC && N0.hasOneUse() && ++ tryVPTESTM(Node, N0, N1, true)) ++ return; ++ } ++ break; ++ + case ISD::AND: + if (NVT.isVector() && NVT.getVectorElementType() == MVT::i1) { + // Try to form a masked VPTESTM. Operands can be in either order. + SDValue N0 = Node->getOperand(0); + SDValue N1 = Node->getOperand(1); + if (N0.getOpcode() == ISD::SETCC && N0.hasOneUse() && +- tryVPTESTM(Node, N0, N1)) ++ tryVPTESTM(Node, N0, N1, false)) + return; + if (N1.getOpcode() == ISD::SETCC && N1.hasOneUse() && +- tryVPTESTM(Node, N1, N0)) ++ tryVPTESTM(Node, N1, N0, false)) + return; + } + +@@ -5000,7 +5014,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) { + } + + case ISD::SETCC: { +- if (NVT.isVector() && tryVPTESTM(Node, SDValue(Node, 0), SDValue())) ++ if (NVT.isVector() && tryVPTESTM(Node, SDValue(Node, 0), SDValue(), false)) + return; + + break; +diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp +index 920cdd7e625..6b9738074c7 100644 +--- a/lib/Target/X86/X86ISelLowering.cpp ++++ b/lib/Target/X86/X86ISelLowering.cpp +@@ -196,7 +196,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, + // Integer absolute. + if (Subtarget.hasCMov()) { + setOperationAction(ISD::ABS , MVT::i16 , Custom); +- setOperationAction(ISD::ABS , MVT::i32 , Custom); ++ setOperationAction(ISD::ABS , MVT::i32 , Custom); + } + setOperationAction(ISD::ABS , MVT::i64 , Custom); + +@@ -26053,7 +26053,7 @@ X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const { + + // If this is a canonical idempotent atomicrmw w/no uses, we have a better + // lowering available in lowerAtomicArith. +- // TODO: push more cases through this path. ++ // TODO: push more cases through this path. + if (auto *C = dyn_cast(AI->getValOperand())) + if (AI->getOperation() == AtomicRMWInst::Or && C->isZero() && + AI->use_empty()) +@@ -26111,7 +26111,7 @@ X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const { + /// Emit a locked operation on a stack location which does not change any + /// memory location, but does involve a lock prefix. Location is chosen to be + /// a) very likely accessed only by a single thread to minimize cache traffic, +-/// and b) definitely dereferenceable. Returns the new Chain result. ++/// and b) definitely dereferenceable. Returns the new Chain result. + static SDValue emitLockedStackOp(SelectionDAG &DAG, + const X86Subtarget &Subtarget, + SDValue Chain, SDLoc DL) { +@@ -26120,22 +26120,22 @@ static SDValue emitLockedStackOp(SelectionDAG &DAG, + // operations issued by the current processor. As such, the location + // referenced is not relevant for the ordering properties of the instruction. + // See: Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, +- // 8.2.3.9 Loads and Stores Are Not Reordered with Locked Instructions ++ // 8.2.3.9 Loads and Stores Are Not Reordered with Locked Instructions + // 2) Using an immediate operand appears to be the best encoding choice + // here since it doesn't require an extra register. + // 3) OR appears to be very slightly faster than ADD. (Though, the difference + // is small enough it might just be measurement noise.) + // 4) When choosing offsets, there are several contributing factors: + // a) If there's no redzone, we default to TOS. (We could allocate a cache +- // line aligned stack object to improve this case.) ++ // line aligned stack object to improve this case.) + // b) To minimize our chances of introducing a false dependence, we prefer +- // to offset the stack usage from TOS slightly. ++ // to offset the stack usage from TOS slightly. + // c) To minimize concerns about cross thread stack usage - in particular, + // the idiomatic MyThreadPool.run([&StackVars]() {...}) pattern which + // captures state in the TOS frame and accesses it from many threads - + // we want to use an offset such that the offset is in a distinct cache + // line from the TOS frame. +- // ++ // + // For a general discussion of the tradeoffs and benchmark results, see: + // https://shipilev.net/blog/2014/on-the-fence-with-dependencies/ + +@@ -26188,7 +26188,7 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget &Subtarget, + if (Subtarget.hasMFence()) + return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); + +- SDValue Chain = Op.getOperand(0); ++ SDValue Chain = Op.getOperand(0); + return emitLockedStackOp(DAG, Subtarget, Chain, dl); + } + +@@ -26677,12 +26677,12 @@ static SDValue lowerAtomicArith(SDValue N, SelectionDAG &DAG, + // seq_cst which isn't SingleThread, everything just needs to be preserved + // during codegen and then dropped. Note that we expect (but don't assume), + // that orderings other than seq_cst and acq_rel have been canonicalized to +- // a store or load. ++ // a store or load. + if (AN->getOrdering() == AtomicOrdering::SequentiallyConsistent && + AN->getSyncScopeID() == SyncScope::System) { + // Prefer a locked operation against a stack location to minimize cache + // traffic. This assumes that stack locations are very likely to be +- // accessed only by the owning thread. ++ // accessed only by the owning thread. + SDValue NewChain = emitLockedStackOp(DAG, Subtarget, Chain, DL); + assert(!N->hasAnyUseOfValue(0)); + // NOTE: The getUNDEF is needed to give something for the unused result 0. +@@ -35620,7 +35620,7 @@ static SDValue scalarizeExtEltFP(SDNode *ExtElt, SelectionDAG &DAG) { + } + + // TODO: This switch could include FNEG and the x86-specific FP logic ops +- // (FAND, FANDN, FOR, FXOR). But that may require enhancements to avoid ++ // (FAND, FANDN, FOR, FXOR). But that may require enhancements to avoid + // missed load folding and fma+fneg combining. + switch (Vec.getOpcode()) { + case ISD::FMA: // Begin 3 operands +@@ -35935,10 +35935,8 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, + + // vselect Cond, 000..., X -> andn Cond, X + if (TValIsAllZeros) { +- MVT AndNVT = MVT::getVectorVT(MVT::i64, CondVT.getSizeInBits() / 64); +- SDValue CastCond = DAG.getBitcast(AndNVT, Cond); +- SDValue CastRHS = DAG.getBitcast(AndNVT, RHS); +- SDValue AndN = DAG.getNode(X86ISD::ANDNP, DL, AndNVT, CastCond, CastRHS); ++ SDValue CastRHS = DAG.getBitcast(CondVT, RHS); ++ SDValue AndN = DAG.getNode(X86ISD::ANDNP, DL, CondVT, Cond, CastRHS); + return DAG.getBitcast(VT, AndN); + } + +@@ -38147,12 +38145,17 @@ static SDValue IsNOT(SDValue V, SelectionDAG &DAG) { + return SDValue(); + } + +-/// Try to fold: (and (xor X, -1), Y) -> (andnp X, Y). +-static SDValue combineANDXORWithAllOnesIntoANDNP(SDNode *N, SelectionDAG &DAG) { ++ ++/// Try to fold: ++/// (and (not X), Y) -> (andnp X, Y) ++/// (and (xor X, -1), Y) -> (andnp X, Y). ++static SDValue combineANDXORWithAllOnesIntoANDNP(SDNode *N, SelectionDAG &DAG, ++ const X86Subtarget &Subtarget) { + assert(N->getOpcode() == ISD::AND); + + MVT VT = N->getSimpleValueType(0); +- if (!VT.is128BitVector() && !VT.is256BitVector() && !VT.is512BitVector()) ++ if (!VT.is128BitVector() && !VT.is256BitVector() && !VT.is512BitVector() && ++ !(VT.isVector() && VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512())) + return SDValue(); + + SDValue X, Y; +@@ -38558,7 +38561,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG, + if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget)) + return FPLogic; + +- if (SDValue R = combineANDXORWithAllOnesIntoANDNP(N, DAG)) ++ if (SDValue R = combineANDXORWithAllOnesIntoANDNP(N, DAG, Subtarget)) + return R; + + if (SDValue ShiftRight = combineAndMaskToShift(N, DAG, Subtarget)) +diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td +index 54eddeacaa1..91027fa903f 100644 +--- a/lib/Target/X86/X86InstrAVX512.td ++++ b/lib/Target/X86/X86InstrAVX512.td +@@ -2978,7 +2978,6 @@ multiclass avx512_mask_binop_all opc, string OpcodeStr, + def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>; + def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>; + // These nodes use 'vnot' instead of 'not' to support vectors. +-def vandn : PatFrag<(ops node:$i0, node:$i1), (and (vnot node:$i0), node:$i1)>; + def vxnor : PatFrag<(ops node:$i0, node:$i1), (vnot (xor node:$i0, node:$i1))>; + + // TODO - do we need a X86SchedWriteWidths::KMASK type? +@@ -2986,7 +2985,7 @@ defm KAND : avx512_mask_binop_all<0x41, "kand", and, SchedWriteVecLogic.XM + defm KOR : avx512_mask_binop_all<0x45, "kor", or, SchedWriteVecLogic.XMM, 1>; + defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", vxnor, SchedWriteVecLogic.XMM, 1>; + defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, SchedWriteVecLogic.XMM, 1>; +-defm KANDN : avx512_mask_binop_all<0x42, "kandn", vandn, SchedWriteVecLogic.XMM, 0>; ++defm KANDN : avx512_mask_binop_all<0x42, "kandn", X86andnp, SchedWriteVecLogic.XMM, 0>; + defm KADD : avx512_mask_binop_all<0x4A, "kadd", X86kadd, SchedWriteVecLogic.XMM, 1, HasDQI>; + + multiclass avx512_binop_pat; +-defm : avx512_binop_pat; ++defm : avx512_binop_pat; + defm : avx512_binop_pat; + defm : avx512_binop_pat; + defm : avx512_binop_pat; +@@ -11570,7 +11569,7 @@ multiclass avx512_fixupimm_scalar opc, string OpcodeStr, + } + + multiclass avx512_fixupimm_packed_all { + let Predicates = [HasAVX512] in + defm Z : avx512_fixupimm_packed_sae<0x54, "vfixupimm", sched.ZMM, +@@ -11687,7 +11686,7 @@ multiclass AVX512_scalar_math_fp_patterns("V"#OpcPrefix#Zrr_Intkz) ++ (!cast("V"#OpcPrefix#Zrr_Intkz) + VK1WM:$mask, _.VT:$src1, + (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)))>; + def : Pat<(MoveNode (_.VT VR128X:$src1), +diff --git a/test/CodeGen/X86/avx512-select.ll b/test/CodeGen/X86/avx512-select.ll +index 1ed7b408baf..64320d63eac 100644 +--- a/test/CodeGen/X86/avx512-select.ll ++++ b/test/CodeGen/X86/avx512-select.ll +@@ -595,3 +595,74 @@ define <16 x i64> @narrowExtractedVectorSelect_crash(<16 x i64> %arg, <16 x i16> + %tmp3 = zext <16 x i16> %tmp2 to <16 x i64> + ret <16 x i64> %tmp3 + } ++ ++; Regression test from https://github.com/JuliaLang/julia/issues/36955 ++define i8 @julia_issue36955(<8 x i1> %mask, <8 x double> %a) { ++; X86-AVX512F-LABEL: julia_issue36955: ++; X86-AVX512F: # %bb.0: ++; X86-AVX512F-NEXT: vpmovsxwq %xmm0, %zmm0 ++; X86-AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ++; X86-AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ++; X86-AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0 ++; X86-AVX512F-NEXT: vcmpnlepd %zmm0, %zmm1, %k1 ++; X86-AVX512F-NEXT: kandnw %k0, %k1, %k0 ++; X86-AVX512F-NEXT: kandw %k1, %k0, %k0 ++; X86-AVX512F-NEXT: knotw %k1, %k1 ++; X86-AVX512F-NEXT: korw %k1, %k0, %k0 ++; X86-AVX512F-NEXT: kmovw %k0, %eax ++; X86-AVX512F-NEXT: # kill: def $al killed $al killed $eax ++; X86-AVX512F-NEXT: vzeroupper ++; X86-AVX512F-NEXT: retl ++; ++; X64-AVX512F-LABEL: julia_issue36955: ++; X64-AVX512F: # %bb.0: ++; X64-AVX512F-NEXT: vpmovsxwq %xmm0, %zmm0 ++; X64-AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ++; X64-AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ++; X64-AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0 ++; X64-AVX512F-NEXT: vcmpnlepd %zmm0, %zmm1, %k1 ++; X64-AVX512F-NEXT: kandnw %k0, %k1, %k0 ++; X64-AVX512F-NEXT: kandw %k1, %k0, %k0 ++; X64-AVX512F-NEXT: knotw %k1, %k1 ++; X64-AVX512F-NEXT: korw %k1, %k0, %k0 ++; X64-AVX512F-NEXT: kmovw %k0, %eax ++; X64-AVX512F-NEXT: # kill: def $al killed $al killed $eax ++; X64-AVX512F-NEXT: vzeroupper ++; X64-AVX512F-NEXT: retq ++; ++; X86-AVX512BW-LABEL: julia_issue36955: ++; X86-AVX512BW: # %bb.0: ++; X86-AVX512BW-NEXT: vpsllw $15, %xmm0, %xmm0 ++; X86-AVX512BW-NEXT: vpmovw2m %zmm0, %k0 ++; X86-AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0 ++; X86-AVX512BW-NEXT: vcmpnlepd %zmm0, %zmm1, %k1 ++; X86-AVX512BW-NEXT: kandnw %k0, %k1, %k0 ++; X86-AVX512BW-NEXT: kandw %k1, %k0, %k0 ++; X86-AVX512BW-NEXT: knotw %k1, %k1 ++; X86-AVX512BW-NEXT: korw %k1, %k0, %k0 ++; X86-AVX512BW-NEXT: kmovd %k0, %eax ++; X86-AVX512BW-NEXT: # kill: def $al killed $al killed $eax ++; X86-AVX512BW-NEXT: vzeroupper ++; X86-AVX512BW-NEXT: retl ++; ++; X64-AVX512BW-LABEL: julia_issue36955: ++; X64-AVX512BW: # %bb.0: ++; X64-AVX512BW-NEXT: vpsllw $15, %xmm0, %xmm0 ++; X64-AVX512BW-NEXT: vpmovw2m %zmm0, %k0 ++; X64-AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0 ++; X64-AVX512BW-NEXT: vcmpnlepd %zmm0, %zmm1, %k1 ++; X64-AVX512BW-NEXT: kandnw %k0, %k1, %k0 ++; X64-AVX512BW-NEXT: kandw %k1, %k0, %k0 ++; X64-AVX512BW-NEXT: knotw %k1, %k1 ++; X64-AVX512BW-NEXT: korw %k1, %k0, %k0 ++; X64-AVX512BW-NEXT: kmovd %k0, %eax ++; X64-AVX512BW-NEXT: # kill: def $al killed $al killed $eax ++; X64-AVX512BW-NEXT: vzeroupper ++; X64-AVX512BW-NEXT: retq ++ %fcmp = fcmp ugt <8 x double> %a, zeroinitializer ++ %xor = xor <8 x i1> %fcmp, ++ %select1 = select <8 x i1> %fcmp, <8 x i1> zeroinitializer, <8 x i1> %mask ++ %select2 = select <8 x i1> %xor, <8 x i1> , <8 x i1> %select1 ++ %ret = bitcast <8 x i1> %select2 to i8 ++ ret i8 %ret ++} +diff --git a/test/CodeGen/X86/combine-bitselect.ll b/test/CodeGen/X86/combine-bitselect.ll +index 8cb6a4dca09..3c08a871c86 100644 +--- a/test/CodeGen/X86/combine-bitselect.ll ++++ b/test/CodeGen/X86/combine-bitselect.ll +@@ -616,13 +616,13 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) { + ; AVX512F: # %bb.0: # %bb + ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 + ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 +-; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm2 = [12,12,12,12] +-; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm1, %k1 ++; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 ++; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm0 = [12,12,12,12] + ; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm2 = [15,15,15,15] +-; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm1, %k2 +-; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0 {%k2} +-; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 {%k1} +-; AVX512F-NEXT: korw %k0, %k1, %k1 ++; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm1, %k0 ++; AVX512F-NEXT: vpcmpeqd %zmm0, %zmm1, %k2 {%k1} ++; AVX512F-NEXT: kandnw %k0, %k1, %k0 ++; AVX512F-NEXT: korw %k0, %k2, %k1 + ; AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} + ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 + ; AVX512F-NEXT: vzeroupper +diff --git a/test/CodeGen/X86/vec_ssubo.ll b/test/CodeGen/X86/vec_ssubo.ll +index 515dc5c5aa2..dfb1e7c4dee 100644 +--- a/test/CodeGen/X86/vec_ssubo.ll ++++ b/test/CodeGen/X86/vec_ssubo.ll +@@ -1640,7 +1640,7 @@ define <4 x i32> @ssubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind + ; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k0 + ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 + ; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 +-; AVX512-NEXT: vptestnmd %xmm1, %xmm1, %k2 {%k1} ++; AVX512-NEXT: kandnw %k1, %k0, %k2 + ; AVX512-NEXT: kxorw %k0, %k1, %k0 + ; AVX512-NEXT: kxorw %k2, %k0, %k1 + ; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +diff --git a/test/CodeGen/X86/vec_usubo.ll b/test/CodeGen/X86/vec_usubo.ll +index c5a7b19cf14..367c491d25a 100644 +--- a/test/CodeGen/X86/vec_usubo.ll ++++ b/test/CodeGen/X86/vec_usubo.ll +@@ -1244,10 +1244,10 @@ define <4 x i32> @usubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind + ; AVX512: # %bb.0: + ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 + ; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 +-; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 +-; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 ++; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 ++; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 + ; AVX512-NEXT: kxorw %k1, %k0, %k1 +-; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k2 {%k1} ++; AVX512-NEXT: kandnw %k1, %k0, %k2 + ; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 + ; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k2} {z} + ; AVX512-NEXT: kmovd %k1, %eax diff --git a/deps/unwind.mk b/deps/unwind.mk index f44917c28981a..08d8990a720e8 100644 --- a/deps/unwind.mk +++ b/deps/unwind.mk @@ -109,7 +109,7 @@ UNWIND_BB_NAME := LibUnwind.v$(UNWIND_VER) $(eval $(call bb-install,unwind,UNWIND,false)) -OSXUNWIND_BB_URL_BASE := https://github.com/JuliaPackaging/Yggdrasil/releases/download/LibOSXUnwind-$(OSXUNWIND_VER)-$(OSXUNWIND_BB_REL) +OSXUNWIND_BB_URL_BASE := https://github.com/JuliaBinaryWrappers/LibOSXUnwind_jll.jl/releases/download/LibOSXUnwind-v$(OSXUNWIND_VER)+$(OSXUNWIND_BB_REL) OSXUNWIND_BB_NAME := LibOSXUnwind.v$(OSXUNWIND_VER) $(eval $(call bb-install,osxunwind,OSXUNWIND,false)) diff --git a/doc/Manifest.toml b/doc/Manifest.toml index 7dd3aff71011f..5410f3c03ab9f 100644 --- a/doc/Manifest.toml +++ b/doc/Manifest.toml @@ -13,15 +13,15 @@ uuid = "8ba89e20-285c-5b6f-9357-94700520ee1b" [[DocStringExtensions]] deps = ["LibGit2", "Markdown", "Pkg", "Test"] -git-tree-sha1 = "88bb0edb352b16608036faadcc071adda068582a" +git-tree-sha1 = "c5714d9bcdba66389612dc4c47ed827c64112997" uuid = "ffbed154-4ef7-542d-bbb7-c09d3a79fcae" -version = "0.8.1" +version = "0.8.2" [[Documenter]] deps = ["Base64", "Dates", "DocStringExtensions", "InteractiveUtils", "JSON", "LibGit2", "Logging", "Markdown", "REPL", "Test", "Unicode"] -git-tree-sha1 = "395fa1554c69735802bba37d9e7d9586fd44326c" +git-tree-sha1 = "1c593d1efa27437ed9dd365d1143c594b563e138" uuid = "e30172f5-a6a5-5a46-863b-614d45cd2de4" -version = "0.24.11" +version = "0.25.1" [[DocumenterLaTeX]] deps = ["Documenter", "Test"] @@ -58,9 +58,9 @@ uuid = "a63ad114-7e13-5084-954f-fe012c677804" [[Parsers]] deps = ["Dates", "Test"] -git-tree-sha1 = "f8f5d2d4b4b07342e5811d2b6428e45524e241df" +git-tree-sha1 = "8077624b3c450b15c087944363606a6ba12f925e" uuid = "69de0a69-1ddd-5017-9359-2bf0b02dc9f0" -version = "1.0.2" +version = "1.0.10" [[Pkg]] deps = ["Dates", "LibGit2", "Libdl", "Logging", "Markdown", "Printf", "REPL", "Random", "SHA", "UUIDs"] @@ -71,7 +71,7 @@ deps = ["Unicode"] uuid = "de0858da-6303-5e67-8744-51eddeeeb8d7" [[REPL]] -deps = ["InteractiveUtils", "Markdown", "Sockets"] +deps = ["InteractiveUtils", "Markdown", "Sockets", "Unicode"] uuid = "3fa0cd96-eef1-5676-8a61-b3b8758bbffb" [[Random]] diff --git a/doc/make.jl b/doc/make.jl index 8b6d3e650a31c..391eb21c571c4 100644 --- a/doc/make.jl +++ b/doc/make.jl @@ -217,23 +217,49 @@ makedocs( # Define our own DeployConfig struct BuildBotConfig <: Documenter.DeployConfig end -function Documenter.deploy_folder(::BuildBotConfig; devurl, kwargs...) - haskey(ENV, "DOCUMENTER_KEY") || return nothing +function Documenter.deploy_folder(::BuildBotConfig; devurl, repo, branch, kwargs...) + haskey(ENV, "DOCUMENTER_KEY") || return Documenter.DeployDecision(; all_ok=false) if Base.GIT_VERSION_INFO.tagged_commit - return "v$(Base.VERSION)" + # Strip extra pre-release info (1.5.0-rc2.0 -> 1.5.0-rc2) + ver = VersionNumber(VERSION.major, VERSION.minor, VERSION.patch, + isempty(VERSION.prerelease) ? () : (VERSION.prerelease[1],)) + subfolder = "v$(ver)" + return Documenter.DeployDecision(; all_ok=true, repo, branch, subfolder) elseif Base.GIT_VERSION_INFO.branch == "master" - return devurl + return Documenter.DeployDecision(; all_ok=true, repo, branch, subfolder=devurl) end - return nothing + return Documenter.DeployDecision(; all_ok=false) end const devurl = "v$(VERSION.major).$(VERSION.minor)-dev" +# Hack to make rc docs visible in the version selector +struct Versions versions end +function Documenter.Writers.HTMLWriter.expand_versions(dir::String, v::Versions) + # Find all available docs + available_folders = readdir(dir) + cd(() -> filter!(!islink, available_folders), dir) + filter!(x -> occursin(Base.VERSION_REGEX, x), available_folders) + + # Look for docs for an "active" release candidate and insert it + vnums = [VersionNumber(x) for x in available_folders] + master_version = maximum(vnums) + filter!(x -> x.major == 1 && x.minor == master_version.minor-1, vnums) + rc = maximum(vnums) + if !isempty(rc.prerelease) && occursin(r"^rc", rc.prerelease[1]) + src = "v$(rc)" + @assert src ∈ available_folders + push!(v.versions, src => src, pop!(v.versions)) + end + + return Documenter.Writers.HTMLWriter.expand_versions(dir, v.versions) +end + deploydocs( repo = "github.com/JuliaLang/docs.julialang.org.git", deploy_config = BuildBotConfig(), target = joinpath(buildroot, "doc", "_build", "html", "en"), dirname = "en", devurl = devurl, - versions = ["v#.#", devurl => devurl] + versions = Versions(["v#.#", devurl => devurl]), ) diff --git a/doc/src/manual/faq.md b/doc/src/manual/faq.md index b02f2d20dbd17..7c81a3828b87a 100644 --- a/doc/src/manual/faq.md +++ b/doc/src/manual/faq.md @@ -935,6 +935,22 @@ Julia compiles and uses its own copy of OpenBLAS, with threads currently capped Modifying OpenBLAS settings or compiling Julia with a different BLAS library, eg [Intel MKL](https://software.intel.com/en-us/mkl), may provide performance improvements. You can use [MKL.jl](https://github.com/JuliaComputing/MKL.jl), a package that makes Julia's linear algebra use Intel MKL BLAS and LAPACK instead of OpenBLAS, or search the discussion forum for suggestions on how to set this up manually. Note that Intel MKL cannot be bundled with Julia, as it is not open source. +## Computing cluster + +### How do I manage precompilation caches in distributed file systems? + +When using `julia` in high-performance computing (HPC) facilities, invoking +_n_ `julia` processes simultaneously creates at most _n_ temporary copies of +precompilation cache files. If this is an issue (slow and/or small distributed +file system), you may: + +1. Use `julia` with `--compiled-modules=no` flag to turn off precompilation. +2. Configure a private writable depot using `pushfirst!(DEPOT_PATH, private_path)` + where `private_path` is a path unique to this `julia` process. This + can also be done by setting environment variable `JULIA_DEPOT_PATH` to + `$private_path:$HOME/.julia`. +3. Create a symlink from `~/.julia/compiled` to a directory in a scratch space. + ## Julia Releases ### Do I want to use the Stable, LTS, or nightly version of Julia? diff --git a/doc/src/manual/types.md b/doc/src/manual/types.md index c29c85500e130..6b3319c5dfb67 100644 --- a/doc/src/manual/types.md +++ b/doc/src/manual/types.md @@ -237,12 +237,12 @@ of function arguments that are containers of abstract types; see [Performance Ti ## Primitive Types !!! warning - It is almost always preferable to wrap an existing primitive type in a new - composite type than to define your own primitive type. + It is almost always preferable to wrap an existing primitive type in a new + composite type than to define your own primitive type. - This functionality exists to allow Julia to bootstrap the standard primitive - types that LLVM supports. Once they are defined, there is very little reason - to define more. + This functionality exists to allow Julia to bootstrap the standard primitive + types that LLVM supports. Once they are defined, there is very little reason + to define more. A primitive type is a concrete type whose data consists of plain old bits. Classic examples of primitive types are integers and floating-point values. Unlike most languages, Julia lets you declare your diff --git a/src/Makefile b/src/Makefile index 1c51e01d45c92..0eaa214e5d074 100644 --- a/src/Makefile +++ b/src/Makefile @@ -55,7 +55,8 @@ SRCS += codegen llvm-ptls RUNTIME_SRCS += jitlayers aotcompile debuginfo disasm llvm-simdloop llvm-muladd \ llvm-final-gc-lowering llvm-pass-helpers llvm-late-gc-lowering \ llvm-lower-handlers llvm-gc-invariant-verifier llvm-propagate-addrspaces \ - llvm-multiversioning llvm-alloc-opt cgmemmgr llvm-api llvm-remove-addrspaces + llvm-multiversioning llvm-alloc-opt cgmemmgr llvm-api llvm-remove-addrspaces \ + llvm-remove-ni FLAGS += -I$(shell $(LLVM_CONFIG_HOST) --includedir) LLVM_LIBS := all ifeq ($(USE_POLLY),1) @@ -120,7 +121,7 @@ CLANG_LDFLAGS += -Wl,-undefined,dynamic_lookup endif -COMMON_LIBS := -L$(build_shlibdir) -L$(build_libdir) $(LIBUV) $(LIBUTF8PROC) $(NO_WHOLE_ARCHIVE) $(LLVMLINK) $(OSLIBS) $(LIBUNWIND) +COMMON_LIBS := -L$(build_shlibdir) -L$(build_libdir) $(LIBUV) $(LIBUTF8PROC) $(NO_WHOLE_ARCHIVE) $(LIBUNWIND) $(LLVMLINK) $(OSLIBS) DEBUG_LIBS := $(WHOLE_ARCHIVE) $(BUILDDIR)/flisp/libflisp-debug.a $(WHOLE_ARCHIVE) $(BUILDDIR)/support/libsupport-debug.a $(COMMON_LIBS) RELEASE_LIBS := $(WHOLE_ARCHIVE) $(BUILDDIR)/flisp/libflisp.a $(WHOLE_ARCHIVE) $(BUILDDIR)/support/libsupport.a $(COMMON_LIBS) diff --git a/src/aotcompile.cpp b/src/aotcompile.cpp index 7ad21841ab693..03b90640ee71a 100644 --- a/src/aotcompile.cpp +++ b/src/aotcompile.cpp @@ -631,6 +631,7 @@ void addOptimizationPasses(legacy::PassManagerBase *PM, int opt_level, PM->add(createFinalLowerGCPass()); PM->add(createLowerPTLSPass(dump_native)); } + PM->add(createRemoveNIPass()); PM->add(createLowerSimdLoopPass()); // Annotate loop marked with "loopinfo" as LLVM parallel loop if (dump_native) PM->add(createMultiVersioningPass()); @@ -753,6 +754,7 @@ void addOptimizationPasses(legacy::PassManagerBase *PM, int opt_level, // Clean up write barrier and ptls lowering PM->add(createCFGSimplificationPass()); } + PM->add(createRemoveNIPass()); PM->add(createCombineMulAddPass()); PM->add(createDivRemPairsPass()); #if defined(JL_ASAN_ENABLED) diff --git a/src/dump.c b/src/dump.c index 9ef0fa9d237c1..f9c0211c61b86 100644 --- a/src/dump.c +++ b/src/dump.c @@ -2837,11 +2837,10 @@ JL_DLLEXPORT jl_value_t *jl_uncompress_argname_n(jl_value_t *syms, size_t i) JL_DLLEXPORT int jl_save_incremental(const char *fname, jl_array_t *worklist) { JL_TIMING(SAVE_MODULE); - char *tmpfname = strcat(strcpy((char *) alloca(strlen(fname)+8), fname), ".XXXXXX"); ios_t f; jl_array_t *mod_array = NULL, *udeps = NULL; - if (ios_mkstemp(&f, tmpfname) == NULL) { - jl_printf(JL_STDERR, "Cannot open cache file \"%s\" for writing.\n", tmpfname); + if (ios_file(&f, fname, 1, 1, 1, 1) == NULL) { + jl_printf(JL_STDERR, "Cannot open cache file \"%s\" for writing.\n", fname); return 1; } JL_GC_PUSH2(&mod_array, &udeps); @@ -2955,12 +2954,7 @@ JL_DLLEXPORT int jl_save_incremental(const char *fname, jl_array_t *worklist) } write_int32(&f, 0); // mark the end of the source text ios_close(&f); - JL_GC_POP(); - if (jl_fs_rename(tmpfname, fname) < 0) { - jl_printf(JL_STDERR, "Cannot write cache file \"%s\".\n", fname); - return 1; - } return 0; } diff --git a/src/features_aarch32.h b/src/features_aarch32.h index d160ea7464c42..9862ae71ebe63 100644 --- a/src/features_aarch32.h +++ b/src/features_aarch32.h @@ -1,5 +1,10 @@ // This file is a part of Julia. License is MIT: https://julialang.org/license +// Copy values `from arch/arm/include/uapi/asm/hwcap.h` from linux kernel source tree +// and match LLVM names. + +// LLVM features in `llvm/lib/Target/ARM/ARM.td` + // AArch32 features definition // hwcap JL_FEATURE_DEF(neon, 12, 0) @@ -24,5 +29,8 @@ JL_FEATURE_DEF(v7, 32 * 2 + 3, 0) JL_FEATURE_DEF(v8, 32 * 2 + 4, 0) JL_FEATURE_DEF(v8_1a, 32 * 2 + 5, 0) JL_FEATURE_DEF(v8_2a, 32 * 2 + 6, 0) -JL_FEATURE_DEF(v8_3a, 32 * 2 + 7, 60000) +JL_FEATURE_DEF(v8_3a, 32 * 2 + 7, 0) JL_FEATURE_DEF(v8_m_main, 32 * 2 + 8, 0) +JL_FEATURE_DEF(v8_4a, 32 * 2 + 9, 0) +JL_FEATURE_DEF(v8_5a, 32 * 2 + 10, 0) +JL_FEATURE_DEF(v8_6a, 32 * 2 + 11, 110000) diff --git a/src/features_aarch64.h b/src/features_aarch64.h index 1cb869f06c4f0..a6b70b8ffd79e 100644 --- a/src/features_aarch64.h +++ b/src/features_aarch64.h @@ -1,25 +1,83 @@ // This file is a part of Julia. License is MIT: https://julialang.org/license +// Copy values `from arch/arm64/include/uapi/asm/hwcap.h` from linux kernel source tree +// and match LLVM names. +// See also https://www.kernel.org/doc/html/latest/arm64/elf_hwcaps.html + +// LLVM features in `llvm/lib/Target/AArch64/AArch64.td` + // AArch64 features definition // hwcap -JL_FEATURE_DEF(crypto, 3, 0) -JL_FEATURE_DEF(crc, 7, 0) -JL_FEATURE_DEF(lse, 8, 40000) // ARMv8.1-Atomics -JL_FEATURE_DEF(fullfp16, 9, 0) -JL_FEATURE_DEF(rdm, 12, 50000) // ARMv8.1-SIMD -JL_FEATURE_DEF(jscvt, 13, UINT32_MAX) // Linux Kernel HWCAP name -JL_FEATURE_DEF(fcma, 14, UINT32_MAX) // Linux Kernel HWCAP name -JL_FEATURE_DEF(rcpc, 15, 60000) -JL_FEATURE_DEF(dcpop, 16, UINT32_MAX) // Linux Kernel HWCAP name -// JL_FEATURE_DEF(dotprod, ???, 60000) // ARMv8.2-DotProd -// JL_FEATURE_DEF(ras, ???, 0) -// JL_FEATURE_DEF(sve, ???, UINT32_MAX) +// JL_FEATURE_DEF(fp, 0, 0) // HWCAP_HP. Required +// JL_FEATURE_DEF(asimd, 1, 0) // HWCAP_ASIMD. Required +// JL_FEATURE_DEF(evtstrm, 2, 0) // HWCAP_EVTSTRM. Not needed +// JL_FEATURE_DEF(aes, 3, 0) // HWCAP_AES. Implied by `aes` +JL_FEATURE_DEF(aes, 4, 0) // HWCAP_PMULL, ID_AA64ISAR0_EL1.AES == 2 +// JL_FEATURE_DEF(sha1, 5, UINT32_MAX) // HWCAP_SHA1. Implied by `sha2` +JL_FEATURE_DEF(sha2, 6, 0) // HWCAP_SHA2 +JL_FEATURE_DEF(crc, 7, 0) // HWCAP_CRC32. Required in ARMv8.1 +JL_FEATURE_DEF(lse, 8, 0) // HWCAP_ATOMICS, ARMv8.1-Atomics. Required in ARMv8.1 +JL_FEATURE_DEF(fullfp16, 9, 0) // HWCAP_FPHP +// JL_FEATURE_DEF(asimdhp, 10, 0) // HWCAP_ASIMDHP. Same as `fullfp16` +// JL_FEATURE_DEF(cpuid, 11, 0) // HWCAP_CPUID. Not needed +JL_FEATURE_DEF(rdm, 12, 0) // HWCAP_ASIMDRDM, ARMv8.1-SIMD. Required in ARMv8.1 +JL_FEATURE_DEF(jsconv, 13, 0) // HWCAP_JSCVT. Required in ARMv8.3 +JL_FEATURE_DEF(complxnum, 14, 0) // HWCAP_FCMA. Required in ARMv8.3 +JL_FEATURE_DEF(rcpc, 15, 0) // HWCAP_LRCPC, ARMv8.3-RCPC. Required in ARMv8.3 +JL_FEATURE_DEF(ccpp, 16, 0) // HWCAP_DCPOP, ARMv8.2-DCPoP. Required in ARMv8.2 +JL_FEATURE_DEF(sha3, 17, 0) // HWCAP_SHA3. ARMv8.2-SHA +// JL_FEATURE_DEF(sm3, 18, 0) // HWCAP_SM3. Same as `sm4` +JL_FEATURE_DEF(sm4, 19, 0) // HWCAP_SM4, ARMv8.2-SM +JL_FEATURE_DEF(dotprod, 20, 0) // HWCAP_ASIMDDP, ARMv8.2-DotProd +// JL_FEATURE_DEF(sha512, 21, UINT32_MAX) // HWCAP_SHA512. Not implement in LLVM yet +JL_FEATURE_DEF(sve, 22, 0) // HWCAP_SVE +JL_FEATURE_DEF(fp16fml, 23, 0) // HWCAP_ASIMDFHM, ARMv8.2-FHM +JL_FEATURE_DEF(dit, 24, 0) // HWCAP_DIT, ARMv8.4-DIT. Required in ARMv8.4 +// JL_FEATURE_DEF(uscat, 25, UINT32_MAX) // HWCAP_USCAT, ARMv8.4-LSE +JL_FEATURE_DEF_NAME(rcpc_immo, 26, 0, "rcpc-immo") // HWCAP_ILRCPC, ARMv8.4-RCPC. Required in ARMv8.4 +JL_FEATURE_DEF(fmi, 27, 0) // HWCAP_FLAGM, ARMv8.4-CondM. Requird in ARMv8.4 +JL_FEATURE_DEF(ssbs, 28, 0) // HWCAP_SSBS +JL_FEATURE_DEF(sb, 29, 0) // HWCAP_SB. Required in ARMv8.5 +JL_FEATURE_DEF(pa, 30, 0) // HWCAP_PACA +// JL_FEATURE_DEF(pa, 31, 0) // HWCAP_PACG. Merged with `pa`. // hwcap2 -// JL_FEATURE_DEF(?, 32 + ?, 0) +JL_FEATURE_DEF(ccdp, 32 + 0, 0) // HWCAP2_DCPODP, ARMv8.2-DCCVADP. Required in ARMv8.5 +JL_FEATURE_DEF(sve2, 32 + 1, 90000) // HWCAP2_SVE2 +// JL_FEATURE_DEF_NAME(sve2_aes, 32 + 2, 90000, "sve2-aes") // HWCAP2_SVEAES, Implied by `sve2-aes` +JL_FEATURE_DEF_NAME(sve2_aes, 32 + 3, 90000, "sve2-aes") // HWCAP2_SVEPMULL, ID_AA64ZFR0_EL1.AES == 2 +JL_FEATURE_DEF_NAME(sve2_bitperm, 32 + 4, 100000, "sve2-bitperm") // HWCAP2_SVEBITPERM +JL_FEATURE_DEF_NAME(sve2_sha3, 32 + 5, 90000, "sve2-sha3") // HWCAP2_SVESHA3 +JL_FEATURE_DEF_NAME(sve2_sm4, 32 + 6, 90000, "sve2-sm4") // HWCAP2_SM4 +JL_FEATURE_DEF(altnzcv, 32 + 7, 0) // HWCAP2_FLAGM2, ARMv8.5-CondM. Required in ARMv8.5 +JL_FEATURE_DEF(fptoint, 32 + 8, 0) // HWCAP2_FRINT. Required in ARMv8.5 +// JL_FEATURE_DEF(svei8mm, 32 + 9, UINT32_MAX) // HWCAP2_SVEI8MM, ARMv8.2-I8MM. Same as `i8mm` +JL_FEATURE_DEF(f32mm, 32 + 10, 110000) // HWCAP2_SVEF32MM, ARMv8.2-F32MM +JL_FEATURE_DEF(f64mm, 32 + 11, 110000) // HWCAP2_SVEF64MM, ARMv8.2-F64MM +// JL_FEATURE_DEF(svebf16, 32 + 12, UINT32_MAX) // HWCAP2_SVEBF16, ARMv8.2-BF16. Same as `bf16` +JL_FEATURE_DEF(i8mm, 32 + 13, 110000) // HWCAP2_I8MM, ARMv8.2-I8MM. Required in ARMv8.6 +JL_FEATURE_DEF(bf16, 32 + 14, 110000) // HWCAP2_BF16, ARMv8.2-BF16. Required in ARMv8.6 +// JL_FEATURE_DEF(dgh, 32 + 15, UINT32_MAX) // HWCAP2_DGH, ARMv8.0-DGH. Not implement in LLVM yet +JL_FEATURE_DEF(rand, 32 + 16, 0) // HWCAP2_RNG, ARMv8.5-RNG +JL_FEATURE_DEF(bti, 32 + 17, 0) // HWCAP2_BTI // custom bits to match llvm model JL_FEATURE_DEF(v8_1a, 32 * 2 + 0, 0) JL_FEATURE_DEF(v8_2a, 32 * 2 + 1, 0) -JL_FEATURE_DEF(v8_3a, 32 * 2 + 2, 60000) -// JL_FEATURE_DEF(v8_4a, 32 * 2 + 3, ???) +JL_FEATURE_DEF(v8_3a, 32 * 2 + 2, 0) +JL_FEATURE_DEF(v8_4a, 32 * 2 + 3, 0) +JL_FEATURE_DEF(v8_5a, 32 * 2 + 4, 0) +JL_FEATURE_DEF(v8_6a, 32 * 2 + 5, 110000) + +// Missing LLVM features available at EL0: +// tme: ID_AA64ISAR0_EL1.TME (0b1) (LLVM 10) +// am: ID_AA64PFR0_EL1.AMU (0b1, 0b10) +// specrestrict: ID_AA64PFR0_EL1.CSV2 (0b10) +// predres: ID_AA64PFR0_EL1.CSV3 (0b1) +// mte: ID_AA64PFR1_EL1.MTE (0b1, 0b10) +// ecv: ID_AA64MMFR0_EL1.ECV (0b1, 0b10) (LLVM 11) +// lor: ID_AA64MMFR1_EL1.LO (0b1) +// perfmon: ID_AA64DFR0_EL1.PMUVer (0b1, 0b100, 0b101, 0b110) +// spe: ID_AA64DFR0_EL1.PMSVer (0b1 or 0b10) +// tracev8.4: ID_AA64DFR0_EL1.TraceFilt (0b1) +// ete: ??? diff --git a/src/features_x86.h b/src/features_x86.h index f5c567cba4e7e..6fc8fa0b303e6 100644 --- a/src/features_x86.h +++ b/src/features_x86.h @@ -1,11 +1,8 @@ // This file is a part of Julia. License is MIT: https://julialang.org/license #ifdef _CPU_X86_ -// avx is unusable on 32bit before LLVM 5.0 due to LLVM bug (try to encode too many registers) -#define JL_X86_AVX_MIN_VER 50000 #define JL_X86_64ONLY_VER(x) UINT32_MAX #else -#define JL_X86_AVX_MIN_VER 0 #define JL_X86_64ONLY_VER(x) x #endif @@ -14,7 +11,7 @@ JL_FEATURE_DEF(sse3, 0, 0) JL_FEATURE_DEF(pclmul, 1, 0) JL_FEATURE_DEF(ssse3, 9, 0) -JL_FEATURE_DEF(fma, 12, JL_X86_AVX_MIN_VER) +JL_FEATURE_DEF(fma, 12, 0) JL_FEATURE_DEF(cx16, 13, JL_X86_64ONLY_VER(0)) // cx16 requires 64bit JL_FEATURE_DEF_NAME(sse41, 19, 0, "sse4.1") JL_FEATURE_DEF_NAME(sse42, 20, 0, "sse4.2") @@ -22,8 +19,8 @@ JL_FEATURE_DEF(movbe, 22, 0) JL_FEATURE_DEF(popcnt, 23, 0) JL_FEATURE_DEF(aes, 25, 0) JL_FEATURE_DEF(xsave, 26, 0) -JL_FEATURE_DEF(avx, 28, JL_X86_AVX_MIN_VER) -JL_FEATURE_DEF(f16c, 29, JL_X86_AVX_MIN_VER) +JL_FEATURE_DEF(avx, 28, 0) +JL_FEATURE_DEF(f16c, 29, 0) JL_FEATURE_DEF(rdrnd, 30, 0) // EAX=1: EDX @@ -34,37 +31,56 @@ JL_FEATURE_DEF(fsgsbase, 32 * 2 + 0, 0) // JL_FEATURE_DEF(sgx, 32 * 2 + 2, 0) // Disable for now since it's very hard to detect JL_FEATURE_DEF(bmi, 32 * 2 + 3, 0) // JL_FEATURE_DEF(hle, 32 * 2 + 4, 0) // Not used and gone in LLVM 5.0 -JL_FEATURE_DEF(avx2, 32 * 2 + 5, JL_X86_AVX_MIN_VER) +JL_FEATURE_DEF(avx2, 32 * 2 + 5, 0) JL_FEATURE_DEF(bmi2, 32 * 2 + 8, 0) -// JL_FEATURE_DEF(invpcid, 32 * 2 + 10, 0) // Not used and gone in LLVM 5.0 +// JL_FEATURE_DEF(invpcid, 32 * 2 + 10, 0) // Priviledged instruction JL_FEATURE_DEF(rtm, 32 * 2 + 11, 0) -JL_FEATURE_DEF(mpx, 32 * 2 + 14, 0) -// Disable avx512 pre-5.0 since it can't handle address space -JL_FEATURE_DEF(avx512f, 32 * 2 + 16, 50000) -JL_FEATURE_DEF(avx512dq, 32 * 2 + 17, 50000) +// JL_FEATURE_DEF(mpx, 32 * 2 + 14, 0) // Deprecated in LLVM 10.0 +JL_FEATURE_DEF(avx512f, 32 * 2 + 16, 0) +JL_FEATURE_DEF(avx512dq, 32 * 2 + 17, 0) JL_FEATURE_DEF(rdseed, 32 * 2 + 18, 0) JL_FEATURE_DEF(adx, 32 * 2 + 19, 0) // JL_FEATURE_DEF(smap, 32 * 2 + 20, 0) // Not used and gone in LLVM 5.0 -JL_FEATURE_DEF(avx512ifma, 32 * 2 + 21, 50000) +JL_FEATURE_DEF(avx512ifma, 32 * 2 + 21, 0) // JL_FEATURE_DEF(pcommit, 32 * 2 + 22, 0) // Deprecated JL_FEATURE_DEF(clflushopt, 32 * 2 + 23, 0) JL_FEATURE_DEF(clwb, 32 * 2 + 24, 0) -JL_FEATURE_DEF(avx512pf, 32 * 2 + 26, 50000) -JL_FEATURE_DEF(avx512er, 32 * 2 + 27, 50000) -JL_FEATURE_DEF(avx512cd, 32 * 2 + 28, 50000) +JL_FEATURE_DEF(avx512pf, 32 * 2 + 26, 0) +JL_FEATURE_DEF(avx512er, 32 * 2 + 27, 0) +JL_FEATURE_DEF(avx512cd, 32 * 2 + 28, 0) JL_FEATURE_DEF(sha, 32 * 2 + 29, 0) -JL_FEATURE_DEF(avx512bw, 32 * 2 + 30, 50000) -JL_FEATURE_DEF(avx512vl, 32 * 2 + 31, 50000) +JL_FEATURE_DEF(avx512bw, 32 * 2 + 30, 0) +JL_FEATURE_DEF(avx512vl, 32 * 2 + 31, 0) // EAX=7,ECX=0: ECX JL_FEATURE_DEF(prefetchwt1, 32 * 3 + 0, 0) -JL_FEATURE_DEF(avx512vbmi, 32 * 3 + 1, 50000) +JL_FEATURE_DEF(avx512vbmi, 32 * 3 + 1, 0) JL_FEATURE_DEF(pku, 32 * 3 + 4, 0) // ospke -JL_FEATURE_DEF(avx512vpopcntdq, 32 * 3 + 14, 50000) +JL_FEATURE_DEF(waitpkg, 32 * 3 + 5, 0) +JL_FEATURE_DEF(avx512vbmi2, 32 * 3 + 6, 0) +JL_FEATURE_DEF(shstk, 32 * 3 + 7, 0) +JL_FEATURE_DEF(gfni, 32 * 3 + 8, 0) +JL_FEATURE_DEF(vaes, 32 * 3 + 9, 0) +JL_FEATURE_DEF(vpclmulqdq, 32 * 3 + 10, 0) +JL_FEATURE_DEF(avx512vnni, 32 * 3 + 11, 0) +JL_FEATURE_DEF(avx512bitalg, 32 * 3 + 12, 0) +JL_FEATURE_DEF(avx512vpopcntdq, 32 * 3 + 14, 0) +JL_FEATURE_DEF(rdpid, 32 * 3 + 22, 0) +JL_FEATURE_DEF(cldemote, 32 * 3 + 25, 0) +JL_FEATURE_DEF(movdiri, 32 * 3 + 27, 0) +JL_FEATURE_DEF(movdir64b, 32 * 3 + 28, 0) +JL_FEATURE_DEF(enqcmd, 32 * 3 + 29, 90000) // EAX=7,ECX=0: EDX -// JL_FEATURE_DEF(avx512_4vnniw, 32 * 4 + 2, ?????) -// JL_FEATURE_DEF(avx512_4fmaps, 32 * 4 + 3, ?????) +// JL_FEATURE_DEF(avx5124vnniw, 32 * 4 + 2, ?????) +// JL_FEATURE_DEF(avx5124fmaps, 32 * 4 + 3, ?????) +JL_FEATURE_DEF(avx512vp2intersect, 32 * 4 + 8, 90000) +JL_FEATURE_DEF(serialize, 32 * 4 + 14, 110000) +JL_FEATURE_DEF(tsxldtrk, 32 * 4 + 16, 110000) +JL_FEATURE_DEF(pconfig, 32 * 4 + 18, 0) +JL_FEATURE_DEF_NAME(amx_bf16, 32 * 4 + 22, 110000, "amx-bf16") +JL_FEATURE_DEF_NAME(amx_tile, 32 * 4 + 24, 110000, "amx-tile") +JL_FEATURE_DEF_NAME(amx_int8, 32 * 4 + 25, 110000, "amx-int8") // EAX=0x80000001: ECX // ignore sahf on 32bit x86 since it is required @@ -72,9 +88,9 @@ JL_FEATURE_DEF(sahf, 32 * 5 + 0, JL_X86_64ONLY_VER(0)) JL_FEATURE_DEF(lzcnt, 32 * 5 + 5, 0) JL_FEATURE_DEF(sse4a, 32 * 5 + 6, 0) JL_FEATURE_DEF(prfchw, 32 * 5 + 8, 0) -JL_FEATURE_DEF(xop, 32 * 5 + 11, JL_X86_AVX_MIN_VER) -JL_FEATURE_DEF(lwp, 32 * 5 + 15, 50000) -JL_FEATURE_DEF(fma4, 32 * 5 + 16, JL_X86_AVX_MIN_VER) +JL_FEATURE_DEF(xop, 32 * 5 + 11, 0) +JL_FEATURE_DEF(lwp, 32 * 5 + 15, 0) +JL_FEATURE_DEF(fma4, 32 * 5 + 16, 0) JL_FEATURE_DEF(tbm, 32 * 5 + 21, 0) JL_FEATURE_DEF(mwaitx, 32 * 5 + 29, 0) @@ -88,7 +104,13 @@ JL_FEATURE_DEF(xsavec, 32 * 7 + 1, 0) JL_FEATURE_DEF(xsaves, 32 * 7 + 3, 0) // EAX=0x80000008: EBX -JL_FEATURE_DEF(clzero, 32 * 8 + 0, 50000) +JL_FEATURE_DEF(clzero, 32 * 8 + 0, 0) +JL_FEATURE_DEF(wbnoinvd, 32 * 8 + 9, 0) + +// EAX=7,ECX=1: EAX +JL_FEATURE_DEF(avx512bf16, 32 * 9 + 5, 90000) + +// EAX=0x14,ECX=0: EBX +JL_FEATURE_DEF(ptwrite, 32 * 10 + 4, 0) -#undef JL_X86_AVX_MIN_VER #undef JL_X86_64ONLY_VER diff --git a/src/jitlayers.h b/src/jitlayers.h index c7f2dbbe90b26..4ca69f803ee22 100644 --- a/src/jitlayers.h +++ b/src/jitlayers.h @@ -247,6 +247,7 @@ Pass *createLowerExcHandlersPass(); Pass *createGCInvariantVerifierPass(bool Strong); Pass *createPropagateJuliaAddrspaces(); Pass *createRemoveJuliaAddrspacesPass(); +Pass *createRemoveNIPass(); Pass *createMultiVersioningPass(); Pass *createAllocOptPass(); // Whether the Function is an llvm or julia intrinsic. diff --git a/src/llvm-remove-ni.cpp b/src/llvm-remove-ni.cpp new file mode 100644 index 0000000000000..2da30f25e75af --- /dev/null +++ b/src/llvm-remove-ni.cpp @@ -0,0 +1,49 @@ +// This file is a part of Julia. License is MIT: https://julialang.org/license + +#include "llvm-version.h" + +#include +#include +#include + +#define DEBUG_TYPE "remove_ni" + +using namespace llvm; + +namespace { + +struct RemoveNIPass : public ModulePass { + static char ID; + RemoveNIPass() : ModulePass(ID) {}; + + bool runOnModule(Module &M) + { + auto dlstr = M.getDataLayoutStr(); + auto nistart = dlstr.find("-ni:"); + if (nistart == std::string::npos) + return false; + auto len = dlstr.size(); + auto niend = nistart + 1; + for (; niend < len; niend++) { + if (dlstr[niend] == '-') { + break; + } + } + dlstr.erase(nistart, niend - nistart); + M.setDataLayout(dlstr); + return true; + } +}; + +char RemoveNIPass::ID = 0; +static RegisterPass + Y("RemoveNI", + "Remove non-integral address space.", + false, + false); +} + +Pass *createRemoveNIPass() +{ + return new RemoveNIPass(); +} diff --git a/src/processor_arm.cpp b/src/processor_arm.cpp index 5570d69455e2e..ea52fbc0b4175 100644 --- a/src/processor_arm.cpp +++ b/src/processor_arm.cpp @@ -32,7 +32,9 @@ enum class CPU : uint32_t { armv8_1_a, armv8_2_a, armv8_3_a, - // armv8_4_a, + armv8_4_a, + armv8_5_a, + armv8_6_a, // ARM // armv6l @@ -65,13 +67,24 @@ enum class CPU : uint32_t { arm_cortex_a32, arm_cortex_r52, // aarch64 + arm_cortex_a34, arm_cortex_a35, arm_cortex_a53, arm_cortex_a55, arm_cortex_a57, + arm_cortex_a65, + arm_cortex_a65ae, arm_cortex_a72, arm_cortex_a73, arm_cortex_a75, + arm_cortex_a76, + arm_cortex_a76ae, + arm_cortex_a77, + arm_cortex_a78, + arm_cortex_x1, + arm_neoverse_e1, + arm_neoverse_n1, + arm_zeus, // Cavium // aarch64 @@ -82,11 +95,30 @@ enum class CPU : uint32_t { cavium_thunderx83, cavium_thunderx2t99, cavium_thunderx2t99p1, + cavium_octeontx2, + cavium_octeontx2t98, + cavium_octeontx2t96, + cavium_octeontx2f95, + cavium_octeontx2f95n, + cavium_octeontx2f95mm, + + // Fujitsu + // aarch64 + fujitsu_a64fx, + + // HiSilicon + // aarch64 + hisilicon_tsv110, + + // Huaxingtong + // aarch64 + hxt_phecda, // NVIDIA // aarch64 nvidia_denver1, nvidia_denver2, + nvidia_carmel, // AppliedMicro // aarch64 @@ -108,19 +140,28 @@ enum class CPU : uint32_t { samsung_exynos_m1, samsung_exynos_m2, samsung_exynos_m3, + samsung_exynos_m4, + samsung_exynos_m5, // Apple // armv7l apple_swift, // aarch64 - apple_cyclone, - apple_typhoon, - apple_twister, - apple_hurricane, + apple_a7, // cyclone + apple_a8, // typhoon + apple_a9, // twister + apple_a10, // hurricane + apple_a11, + apple_a12, + apple_a13, + apple_s4, + apple_s5, // Marvell // armv7l marvell_pj4, + // aarch64 + marvell_thunderx3t110, // Intel // armv7l @@ -162,48 +203,137 @@ enum : uint32_t { #undef JL_FEATURE_DEF_NAME // This does not cover all dependencies (e.g. the ones that depends on arm versions) static constexpr FeatureDep deps[] = { - {0, 0} // dummy + {rcpc_immo, rcpc}, + {sha3, sha2}, + // {sha512, sha3}, + {ccdp, ccpp}, + {sve, fullfp16}, + {fp16fml, fullfp16}, + {altnzcv, fmi}, + {sve2, sve}, + {sve2_aes, sve2}, + {sve2_aes, aes}, + {sve2_bitperm, sve2}, + {sve2_sha3, sve2}, + {sve2_sha3, sha3}, + {sve2_sm4, sve2}, + {sve2_sm4, sm4}, + {f32mm, sve}, + {f64mm, sve}, }; constexpr auto generic = get_feature_masks(); constexpr auto armv8a_crc = get_feature_masks(crc); -constexpr auto armv8a_crc_crypto = armv8a_crc | get_feature_masks(crypto); -constexpr auto armv8_1a = armv8a_crc | get_feature_masks(v8_1a, lse, rdm); // lor, hpd -constexpr auto armv8_2a = armv8_1a | get_feature_masks(v8_2a); // ras -constexpr auto armv8_2a_crypto = armv8_2a | get_feature_masks(crypto); -constexpr auto armv8_3a = armv8_2a | get_feature_masks(v8_3a, rcpc); -constexpr auto armv8_3a_crypto = armv8_3a | get_feature_masks(crypto); - -constexpr auto arm_cortex_a32 = generic; // TODO? (crc, crypto) -constexpr auto arm_cortex_a35 = generic; // TODO? (crc, crypto) +constexpr auto armv8a_crc_crypto = armv8a_crc | get_feature_masks(aes, sha2); +constexpr auto armv8_1a = armv8a_crc | get_feature_masks(v8_1a, lse, rdm); // lor +constexpr auto armv8_1a_crypto = armv8_1a | get_feature_masks(aes, sha2); +constexpr auto armv8_2a = armv8_1a | get_feature_masks(v8_2a, ccpp); +constexpr auto armv8_2a_crypto = armv8_2a | get_feature_masks(aes, sha2); +constexpr auto armv8_3a = armv8_2a | get_feature_masks(v8_3a, jsconv, complxnum, rcpc); +constexpr auto armv8_3a_crypto = armv8_3a | get_feature_masks(aes, sha2); +constexpr auto armv8_4a = armv8_3a | get_feature_masks(v8_4a, dit, rcpc_immo, fmi); +constexpr auto armv8_4a_crypto = armv8_4a | get_feature_masks(aes, sha2); +constexpr auto armv8_5a = armv8_4a | get_feature_masks(v8_5a, sb, ccdp, altnzcv, fptoint); +constexpr auto armv8_6a = armv8_5a | get_feature_masks(v8_6a, i8mm, bf16); + +// For ARM cores, the features required can be found in the technical reference manual +// The relevant register values and the features they are related to are: +// ID_AA64ISAR0_EL1: +// .AES: aes, pmull +// .SHA1: sha1 +// .SHA2: sha2, sha512 +// .CRC32: crc +// .Atomic: les +// .RDM: rdm +// .SHA3: sha3 +// .SM3: sm3 (sm4) +// .SM4: sm4 +// .DP: dotprod +// .FHM: fp16fml +// .TS: fmi, altnzcz +// .RNDR: rand + +// ID_AA64ISAR1_EL1 +// .JSCVT: jsconv +// .FCMA: complxnum +// .LRCPC: rcpc, rcpc_immo +// .DPB: ccpp, ccdp +// .SB: sb +// .APA/.API: paca (pa) +// .GPA/.GPI: paga (pa) +// .FRINTTS: fptoint +// .I8MM: i8mm +// .BF16: bf16 +// .DGH: dgh + +// ID_AA64PFR0_EL1 +// .FP: fullfp16 +// .SVE: sve +// .DIT: dit +// .BT: bti + +// ID_AA64PFR1_EL1.SSBS: ssbs + +// ID_AA64MMFR2_EL1.AT: uscat + +// ID_AA64ZFR0_EL1 +// .SVEVer: sve2 +// .AES: sve2-aes, sve2-pmull +// .BitPerm: sve2-bitperm +// .SHA3: sve2-sha3 +// .SM4: sve2-sm4 +// .F32MM: f32mm +// .F64MM: f64mm + +constexpr auto arm_cortex_a34 = armv8a_crc; +constexpr auto arm_cortex_a35 = armv8a_crc; constexpr auto arm_cortex_a53 = armv8a_crc; -constexpr auto arm_cortex_a55 = armv8_2a_crypto | get_feature_masks(rcpc); // dotprod; +constexpr auto arm_cortex_a55 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); constexpr auto arm_cortex_a57 = armv8a_crc; +constexpr auto arm_cortex_a65 = armv8_2a | get_feature_masks(rcpc, fullfp16, ssbs); constexpr auto arm_cortex_a72 = armv8a_crc; constexpr auto arm_cortex_a73 = armv8a_crc; -constexpr auto arm_cortex_a75 = armv8_2a_crypto | get_feature_masks(rcpc); // dotprod; +constexpr auto arm_cortex_a75 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16); +constexpr auto arm_cortex_a76 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); +constexpr auto arm_cortex_a77 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); +constexpr auto arm_cortex_a78 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); // spe +constexpr auto arm_cortex_x1 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); // spe +constexpr auto arm_neoverse_e1 = armv8_2a | get_feature_masks(rcpc, fullfp16, ssbs); +constexpr auto arm_neoverse_n1 = armv8_2a | get_feature_masks(dotprod, rcpc, fullfp16, ssbs); +constexpr auto arm_zeus = armv8_4a | get_feature_masks(sve, i8mm, bf16, fullfp16, ssbs, rand); constexpr auto cavium_thunderx = armv8a_crc_crypto; constexpr auto cavium_thunderx88 = armv8a_crc_crypto; constexpr auto cavium_thunderx88p1 = armv8a_crc_crypto; constexpr auto cavium_thunderx81 = armv8a_crc_crypto; constexpr auto cavium_thunderx83 = armv8a_crc_crypto; -constexpr auto cavium_thunderx2t99 = armv8a_crc_crypto | get_feature_masks(v8_1a); -constexpr auto cavium_thunderx2t99p1 = armv8a_crc_crypto | get_feature_masks(v8_1a); +constexpr auto cavium_thunderx2t99 = armv8_1a_crypto; +constexpr auto cavium_thunderx2t99p1 = cavium_thunderx2t99; +constexpr auto cavium_octeontx2 = armv8_2a_crypto; +constexpr auto fujitsu_a64fx = armv8_2a | get_feature_masks(sha2, fullfp16, sve, complxnum); +constexpr auto hisilicon_tsv110 = armv8_2a_crypto | get_feature_masks(dotprod, fullfp16); +constexpr auto hxt_phecda = armv8a_crc_crypto; +constexpr auto marvell_thunderx3t110 = armv8_3a_crypto; constexpr auto nvidia_denver1 = generic; // TODO? (crc, crypto) constexpr auto nvidia_denver2 = armv8a_crc_crypto; +constexpr auto nvidia_carmel = armv8_2a_crypto | get_feature_masks(fullfp16); constexpr auto apm_xgene1 = generic; constexpr auto apm_xgene2 = generic; // TODO? constexpr auto apm_xgene3 = generic; // TODO? constexpr auto qualcomm_kyro = armv8a_crc_crypto; -constexpr auto qualcomm_falkor = armv8a_crc_crypto; -constexpr auto qualcomm_saphira = armv8_3a_crypto; +constexpr auto qualcomm_falkor = armv8a_crc_crypto | get_feature_masks(rdm); +constexpr auto qualcomm_saphira = armv8_4a_crypto; constexpr auto samsung_exynos_m1 = armv8a_crc_crypto; constexpr auto samsung_exynos_m2 = armv8a_crc_crypto; constexpr auto samsung_exynos_m3 = armv8a_crc_crypto; -constexpr auto apple_cyclone = armv8a_crc_crypto; -constexpr auto apple_typhoon = armv8a_crc_crypto; -constexpr auto apple_twister = armv8a_crc_crypto; -constexpr auto apple_hurricane = armv8a_crc_crypto; +constexpr auto samsung_exynos_m4 = armv8_2a_crypto | get_feature_masks(dotprod, fullfp16); +constexpr auto samsung_exynos_m5 = samsung_exynos_m4; +constexpr auto apple_a7 = armv8a_crc_crypto; +constexpr auto apple_a10 = armv8a_crc_crypto | get_feature_masks(rdm); +constexpr auto apple_a11 = armv8_2a_crypto | get_feature_masks(fullfp16); +constexpr auto apple_a12 = armv8_3a_crypto | get_feature_masks(fullfp16); +constexpr auto apple_a13 = armv8_4a_crypto | get_feature_masks(fp16fml, fullfp16, sha3); +constexpr auto apple_s4 = apple_a12; +constexpr auto apple_s5 = apple_a12; } @@ -212,40 +342,77 @@ static constexpr CPUSpec cpus[] = { {"armv8.1-a", CPU::armv8_1_a, CPU::generic, 0, Feature::armv8_1a}, {"armv8.2-a", CPU::armv8_2_a, CPU::generic, 0, Feature::armv8_2a}, {"armv8.3_a", CPU::armv8_3_a, CPU::generic, 0, Feature::armv8_3a}, + {"armv8.4-a", CPU::armv8_4_a, CPU::generic, 0, Feature::armv8_4a}, + {"armv8.5-a", CPU::armv8_5_a, CPU::generic, 0, Feature::armv8_5a}, + {"armv8.6_a", CPU::armv8_6_a, CPU::generic, 0, Feature::armv8_6a}, + {"cortex-a34", CPU::arm_cortex_a34, CPU::arm_cortex_a35, 110000, Feature::arm_cortex_a34}, {"cortex-a35", CPU::arm_cortex_a35, CPU::generic, 0, Feature::arm_cortex_a35}, {"cortex-a53", CPU::arm_cortex_a53, CPU::generic, 0, Feature::arm_cortex_a53}, - {"cortex-a55", CPU::arm_cortex_a55, CPU::arm_cortex_a53, UINT32_MAX, Feature::arm_cortex_a55}, + {"cortex-a55", CPU::arm_cortex_a55, CPU::generic, 0, Feature::arm_cortex_a55}, {"cortex-a57", CPU::arm_cortex_a57, CPU::generic, 0, Feature::arm_cortex_a57}, + {"cortex-a65", CPU::arm_cortex_a65, CPU::arm_cortex_a75, 100000, Feature::arm_cortex_a65}, + {"cortex-a65ae", CPU::arm_cortex_a65ae, CPU::arm_cortex_a75, 100000, Feature::arm_cortex_a65}, {"cortex-a72", CPU::arm_cortex_a72, CPU::generic, 0, Feature::arm_cortex_a72}, {"cortex-a73", CPU::arm_cortex_a73, CPU::generic, 0, Feature::arm_cortex_a73}, - {"cortex-a75", CPU::arm_cortex_a75, CPU::arm_cortex_a73, UINT32_MAX, Feature::arm_cortex_a75}, - {"thunderx", CPU::cavium_thunderx, CPU::generic, 50000, Feature::cavium_thunderx}, - {"thunderxt88", CPU::cavium_thunderx88, CPU::generic, 50000, Feature::cavium_thunderx88}, + {"cortex-a75", CPU::arm_cortex_a75, CPU::generic, 0, Feature::arm_cortex_a75}, + {"cortex-a76", CPU::arm_cortex_a76, CPU::arm_cortex_a75, 90000, Feature::arm_cortex_a76}, + {"cortex-a76ae", CPU::arm_cortex_a76ae, CPU::arm_cortex_a75, 90000, Feature::arm_cortex_a76}, + {"cortex-a77", CPU::arm_cortex_a77, CPU::arm_cortex_a76, 110000, Feature::arm_cortex_a77}, + {"cortex-a78", CPU::arm_cortex_a78, CPU::arm_cortex_a77, 110000, Feature::arm_cortex_a78}, + {"cortex-x1", CPU::arm_cortex_x1, CPU::arm_cortex_a78, 110000, Feature::arm_cortex_x1}, + {"neoverse-e1", CPU::arm_neoverse_e1, CPU::arm_cortex_a76, 100000, Feature::arm_neoverse_e1}, + {"neoverse-n1", CPU::arm_neoverse_n1, CPU::arm_cortex_a76, 100000, Feature::arm_neoverse_n1}, + {"zeus", CPU::arm_zeus, CPU::arm_neoverse_n1, UINT32_MAX, Feature::arm_zeus}, + {"thunderx", CPU::cavium_thunderx, CPU::generic, 0, Feature::cavium_thunderx}, + {"thunderxt88", CPU::cavium_thunderx88, CPU::generic, 0, Feature::cavium_thunderx88}, {"thunderxt88p1", CPU::cavium_thunderx88p1, CPU::cavium_thunderx88, UINT32_MAX, Feature::cavium_thunderx88p1}, - {"thunderxt81", CPU::cavium_thunderx81, CPU::generic, 50000, Feature::cavium_thunderx81}, - {"thunderxt83", CPU::cavium_thunderx83, CPU::generic, 50000, Feature::cavium_thunderx83}, - {"thunderx2t99", CPU::cavium_thunderx2t99, CPU::generic, 50000, - Feature::cavium_thunderx2t99}, + {"thunderxt81", CPU::cavium_thunderx81, CPU::generic, 0, Feature::cavium_thunderx81}, + {"thunderxt83", CPU::cavium_thunderx83, CPU::generic, 0, Feature::cavium_thunderx83}, + {"thunderx2t99", CPU::cavium_thunderx2t99, CPU::generic, 0, Feature::cavium_thunderx2t99}, {"thunderx2t99p1", CPU::cavium_thunderx2t99p1, CPU::cavium_thunderx2t99, UINT32_MAX, Feature::cavium_thunderx2t99p1}, + {"octeontx2", CPU::cavium_octeontx2, CPU::arm_cortex_a57, UINT32_MAX, + Feature::cavium_octeontx2}, + {"octeontx2t98", CPU::cavium_octeontx2t98, CPU::arm_cortex_a57, UINT32_MAX, + Feature::cavium_octeontx2}, + {"octeontx2t96", CPU::cavium_octeontx2t96, CPU::arm_cortex_a57, UINT32_MAX, + Feature::cavium_octeontx2}, + {"octeontx2f95", CPU::cavium_octeontx2f95, CPU::arm_cortex_a57, UINT32_MAX, + Feature::cavium_octeontx2}, + {"octeontx2f95n", CPU::cavium_octeontx2f95n, CPU::arm_cortex_a57, UINT32_MAX, + Feature::cavium_octeontx2}, + {"octeontx2f95mm", CPU::cavium_octeontx2f95mm, CPU::arm_cortex_a57, UINT32_MAX, + Feature::cavium_octeontx2}, + {"a64fx", CPU::fujitsu_a64fx, CPU::generic, 110000, Feature::fujitsu_a64fx}, + {"tsv110", CPU::hisilicon_tsv110, CPU::generic, 0, Feature::hisilicon_tsv110}, + {"phecda", CPU::hxt_phecda, CPU::qualcomm_falkor, UINT32_MAX, Feature::hxt_phecda}, {"denver1", CPU::nvidia_denver1, CPU::generic, UINT32_MAX, Feature::nvidia_denver1}, {"denver2", CPU::nvidia_denver2, CPU::generic, UINT32_MAX, Feature::nvidia_denver2}, + {"carmel", CPU::nvidia_carmel, CPU::generic, 110000, Feature::nvidia_carmel}, {"xgene1", CPU::apm_xgene1, CPU::generic, UINT32_MAX, Feature::apm_xgene1}, {"xgene2", CPU::apm_xgene2, CPU::generic, UINT32_MAX, Feature::apm_xgene2}, {"xgene3", CPU::apm_xgene3, CPU::generic, UINT32_MAX, Feature::apm_xgene3}, {"kyro", CPU::qualcomm_kyro, CPU::generic, 0, Feature::qualcomm_kyro}, - {"falkor", CPU::qualcomm_falkor, CPU::generic, 40000, Feature::qualcomm_falkor}, - {"saphira", CPU::qualcomm_saphira, CPU::qualcomm_falkor, 60000, Feature::qualcomm_saphira}, - {"exynos-m1", CPU::samsung_exynos_m1, CPU::generic, 0, Feature::samsung_exynos_m1}, - {"exynos-m2", CPU::samsung_exynos_m2, CPU::samsung_exynos_m1, 40000, - Feature::samsung_exynos_m2}, - {"exynos-m3", CPU::samsung_exynos_m3, CPU::samsung_exynos_m2, 40000, - Feature::samsung_exynos_m3}, - {"cyclone", CPU::apple_cyclone, CPU::generic, 0, Feature::apple_cyclone}, - {"typhoon", CPU::apple_typhoon, CPU::apple_cyclone, UINT32_MAX, Feature::apple_typhoon}, - {"twister", CPU::apple_twister, CPU::apple_typhoon, UINT32_MAX, Feature::apple_twister}, - {"hurricane", CPU::apple_hurricane, CPU::apple_twister, UINT32_MAX, Feature::apple_hurricane}, + {"falkor", CPU::qualcomm_falkor, CPU::generic, 0, Feature::qualcomm_falkor}, + {"saphira", CPU::qualcomm_saphira, CPU::generic, 0, Feature::qualcomm_saphira}, + {"exynos-m1", CPU::samsung_exynos_m1, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m1}, + {"exynos-m2", CPU::samsung_exynos_m2, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m2}, + {"exynos-m3", CPU::samsung_exynos_m3, CPU::generic, 0, Feature::samsung_exynos_m3}, + {"exynos-m4", CPU::samsung_exynos_m4, CPU::generic, 0, Feature::samsung_exynos_m4}, + {"exynos-m5", CPU::samsung_exynos_m5, CPU::samsung_exynos_m4, 110000, + Feature::samsung_exynos_m5}, + {"apple-a7", CPU::apple_a7, CPU::generic, 100000, Feature::apple_a7}, + {"apple-a8", CPU::apple_a8, CPU::generic, 100000, Feature::apple_a7}, + {"apple-a9", CPU::apple_a9, CPU::generic, 100000, Feature::apple_a7}, + {"apple-a10", CPU::apple_a10, CPU::generic, 100000, Feature::apple_a10}, + {"apple-a11", CPU::apple_a11, CPU::generic, 100000, Feature::apple_a11}, + {"apple-a12", CPU::apple_a12, CPU::generic, 100000, Feature::apple_a12}, + {"apple-a13", CPU::apple_a13, CPU::generic, 100000, Feature::apple_a13}, + {"apple-s4", CPU::apple_s4, CPU::generic, 100000, Feature::apple_s4}, + {"apple-s5", CPU::apple_s5, CPU::generic, 100000, Feature::apple_s5}, + {"thunderx3t110", CPU::marvell_thunderx3t110, CPU::cavium_thunderx2t99, 110000, + Feature::marvell_thunderx3t110}, }; #else static constexpr size_t feature_sz = 3; @@ -365,23 +532,27 @@ constexpr auto armv8a_crc_crypto = armv8a_crc | get_feature_masks(crypto); constexpr auto armv8_2a_crypto = armv8_2a | get_feature_masks(crypto); constexpr auto armv8_3a = armv8_2a | get_feature_masks(v8_3a); constexpr auto armv8_3a_crypto = armv8_3a | get_feature_masks(crypto); - -constexpr auto arm_cortex_a32 = armv8a; // TODO? (crc, crypto) -constexpr auto arm_cortex_r52 = armv8r; // TODO? (crc, crypto) -constexpr auto arm_cortex_a35 = armv8a; // TODO? (crc, crypto) +constexpr auto armv8_4a = armv8_3a | get_feature_masks(v8_4a); +constexpr auto armv8_4a_crypto = armv8_4a | get_feature_masks(crypto); +constexpr auto armv8_5a = armv8_4a | get_feature_masks(v8_5a); +constexpr auto armv8_5a_crypto = armv8_5a | get_feature_masks(crypto); +constexpr auto armv8_6a = armv8_5a | get_feature_masks(v8_6a); +constexpr auto armv8_6a_crypto = armv8_6a | get_feature_masks(crypto); + +constexpr auto arm_cortex_a32 = armv8a_crc; +constexpr auto arm_cortex_r52 = armv8a_crc; +constexpr auto arm_cortex_a35 = armv8a_crc; constexpr auto arm_cortex_a53 = armv8a_crc; -constexpr auto arm_cortex_a55 = armv8_2a_crypto; +constexpr auto arm_cortex_a55 = armv8_2a; constexpr auto arm_cortex_a57 = armv8a_crc; constexpr auto arm_cortex_a72 = armv8a_crc; constexpr auto arm_cortex_a73 = armv8a_crc; -constexpr auto arm_cortex_a75 = armv8_2a_crypto; -constexpr auto cavium_thunderx = armv8a_crc_crypto; -constexpr auto cavium_thunderx88 = armv8a_crc_crypto; -constexpr auto cavium_thunderx88p1 = armv8a_crc_crypto; -constexpr auto cavium_thunderx81 = armv8a_crc_crypto; -constexpr auto cavium_thunderx83 = armv8a_crc_crypto; -constexpr auto cavium_thunderx2t99 = armv8a_crc_crypto | get_feature_masks(v8_1a); -constexpr auto cavium_thunderx2t99p1 = armv8a_crc_crypto | get_feature_masks(v8_1a); +constexpr auto arm_cortex_a75 = armv8_2a; +constexpr auto arm_cortex_a76 = armv8_2a; +constexpr auto arm_cortex_a77 = armv8_2a; +constexpr auto arm_cortex_a78 = armv8_2a; +constexpr auto arm_cortex_x1 = armv8_2a; +constexpr auto arm_neoverse_n1 = armv8_2a; constexpr auto nvidia_denver1 = armv8a; // TODO? (crc, crypto) constexpr auto nvidia_denver2 = armv8a_crc_crypto; constexpr auto apm_xgene1 = armv8a; @@ -393,10 +564,9 @@ constexpr auto qualcomm_saphira = armv8_3a_crypto; constexpr auto samsung_exynos_m1 = armv8a_crc_crypto; constexpr auto samsung_exynos_m2 = armv8a_crc_crypto; constexpr auto samsung_exynos_m3 = armv8a_crc_crypto; -constexpr auto apple_cyclone = armv8a_crc_crypto; -constexpr auto apple_typhoon = armv8a_crc_crypto; -constexpr auto apple_twister = armv8a_crc_crypto; -constexpr auto apple_hurricane = armv8a_crc_crypto; +constexpr auto samsung_exynos_m4 = armv8_2a_crypto; +constexpr auto samsung_exynos_m5 = samsung_exynos_m4; +constexpr auto apple_a7 = armv8a_crc_crypto; } @@ -438,8 +608,8 @@ static constexpr CPUSpec cpus[] = { // armv8ml {"armv8-m.base", CPU::armv8_m_base, CPU::generic, 0, Feature::armv8m}, {"armv8-m.main", CPU::armv8_m_main, CPU::generic, 0, Feature::armv8m}, - {"cortex-m23", CPU::arm_cortex_m23, CPU::armv8_m_base, 50000, Feature::arm_cortex_m23}, - {"cortex-m33", CPU::arm_cortex_m33, CPU::armv8_m_main, 50000, Feature::arm_cortex_m33}, + {"cortex-m23", CPU::arm_cortex_m23, CPU::armv8_m_base, 0, Feature::arm_cortex_m23}, + {"cortex-m33", CPU::arm_cortex_m33, CPU::armv8_m_main, 0, Feature::arm_cortex_m33}, // armv8l {"armv8-a", CPU::armv8_a, CPU::generic, 0, Feature::armv8a}, @@ -447,27 +617,24 @@ static constexpr CPUSpec cpus[] = { {"armv8.1-a", CPU::armv8_1_a, CPU::generic, 0, Feature::armv8_1a}, {"armv8.2-a", CPU::armv8_2_a, CPU::generic, 0, Feature::armv8_2a}, {"armv8.3-a", CPU::armv8_3_a, CPU::generic, 0, Feature::armv8_3a}, + {"armv8.4-a", CPU::armv8_4_a, CPU::generic, 0, Feature::armv8_4a}, + {"armv8.5-a", CPU::armv8_5_a, CPU::generic, 0, Feature::armv8_5a}, + {"armv8.6_a", CPU::armv8_6_a, CPU::generic, 0, Feature::armv8_6a}, {"cortex-a32", CPU::arm_cortex_a32, CPU::generic, 0, Feature::arm_cortex_a32}, - {"cortex-r52", CPU::arm_cortex_r52, CPU::armv8_r, 40000, Feature::arm_cortex_r52}, + {"cortex-r52", CPU::arm_cortex_r52, CPU::generic, 0, Feature::arm_cortex_r52}, {"cortex-a35", CPU::arm_cortex_a35, CPU::generic, 0, Feature::arm_cortex_a35}, {"cortex-a53", CPU::arm_cortex_a53, CPU::generic, 0, Feature::arm_cortex_a53}, - {"cortex-a55", CPU::arm_cortex_a55, CPU::arm_cortex_a53, 60000, Feature::arm_cortex_a55}, + {"cortex-a55", CPU::arm_cortex_a55, CPU::generic, 0, Feature::arm_cortex_a55}, {"cortex-a57", CPU::arm_cortex_a57, CPU::generic, 0, Feature::arm_cortex_a57}, {"cortex-a72", CPU::arm_cortex_a72, CPU::generic, 0, Feature::arm_cortex_a72}, {"cortex-a73", CPU::arm_cortex_a73, CPU::generic, 0, Feature::arm_cortex_a73}, - {"cortex-a75", CPU::arm_cortex_a75, CPU::arm_cortex_a73, 60000, Feature::arm_cortex_a75}, - {"thunderx", CPU::cavium_thunderx, CPU::armv8_a, UINT32_MAX, Feature::cavium_thunderx}, - {"thunderx88", CPU::cavium_thunderx88, CPU::armv8_a, UINT32_MAX, Feature::cavium_thunderx88}, - {"thunderx88p1", CPU::cavium_thunderx88p1, CPU::armv8_a, UINT32_MAX, - Feature::cavium_thunderx88p1}, - {"thunderx81", CPU::cavium_thunderx81, CPU::armv8_a, UINT32_MAX, - Feature::cavium_thunderx81}, - {"thunderx83", CPU::cavium_thunderx83, CPU::armv8_a, UINT32_MAX, - Feature::cavium_thunderx83}, - {"thunderx2t99", CPU::cavium_thunderx2t99, CPU::armv8_a, UINT32_MAX, - Feature::cavium_thunderx2t99}, - {"thunderx2t99p1", CPU::cavium_thunderx2t99p1, CPU::armv8_a, UINT32_MAX, - Feature::cavium_thunderx2t99p1}, + {"cortex-a75", CPU::arm_cortex_a75, CPU::generic, 0, Feature::arm_cortex_a75}, + {"cortex-a76", CPU::arm_cortex_a76, CPU::arm_cortex_a75, 90000, Feature::arm_cortex_a76}, + {"cortex-a76ae", CPU::arm_cortex_a76ae, CPU::arm_cortex_a75, 90000, Feature::arm_cortex_a76}, + {"cortex-a77", CPU::arm_cortex_a77, CPU::arm_cortex_a76, 110000, Feature::arm_cortex_a77}, + {"cortex-a78", CPU::arm_cortex_a78, CPU::arm_cortex_a77, 110000, Feature::arm_cortex_a78}, + {"cortex-x1", CPU::arm_cortex_x1, CPU::arm_cortex_a78, 110000, Feature::arm_cortex_x1}, + {"neoverse-n1", CPU::arm_neoverse_n1, CPU::arm_cortex_a76, 100000, Feature::arm_neoverse_n1}, {"denver1", CPU::nvidia_denver1, CPU::arm_cortex_a53, UINT32_MAX, Feature::nvidia_denver1}, {"denver2", CPU::nvidia_denver2, CPU::arm_cortex_a57, UINT32_MAX, Feature::nvidia_denver2}, {"xgene1", CPU::apm_xgene1, CPU::armv8_a, UINT32_MAX, Feature::apm_xgene1}, @@ -476,15 +643,13 @@ static constexpr CPUSpec cpus[] = { {"kyro", CPU::qualcomm_kyro, CPU::armv8_a, UINT32_MAX, Feature::qualcomm_kyro}, {"falkor", CPU::qualcomm_falkor, CPU::armv8_a, UINT32_MAX, Feature::qualcomm_falkor}, {"saphira", CPU::qualcomm_saphira, CPU::armv8_a, UINT32_MAX, Feature::qualcomm_saphira}, - {"exynos-m1", CPU::samsung_exynos_m1, CPU::generic, 0, Feature::samsung_exynos_m1}, - {"exynos-m2", CPU::samsung_exynos_m2, CPU::samsung_exynos_m1, 40000, - Feature::samsung_exynos_m2}, - {"exynos-m3", CPU::samsung_exynos_m3, CPU::samsung_exynos_m2, 40000, - Feature::samsung_exynos_m3}, - {"cyclone", CPU::apple_cyclone, CPU::generic, 0, Feature::apple_cyclone}, - {"typhoon", CPU::apple_typhoon, CPU::apple_cyclone, UINT32_MAX, Feature::apple_typhoon}, - {"twister", CPU::apple_twister, CPU::apple_typhoon, UINT32_MAX, Feature::apple_twister}, - {"hurricane", CPU::apple_hurricane, CPU::apple_twister, UINT32_MAX, Feature::apple_hurricane}, + {"exynos-m1", CPU::samsung_exynos_m1, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m1}, + {"exynos-m2", CPU::samsung_exynos_m2, CPU::generic, UINT32_MAX, Feature::samsung_exynos_m2}, + {"exynos-m3", CPU::samsung_exynos_m3, CPU::generic, 0, Feature::samsung_exynos_m3}, + {"exynos-m4", CPU::samsung_exynos_m4, CPU::generic, 0, Feature::samsung_exynos_m4}, + {"exynos-m5", CPU::samsung_exynos_m5, CPU::samsung_exynos_m4, 110000, + Feature::samsung_exynos_m5}, + {"apple-a7", CPU::apple_a7, CPU::generic, 0, Feature::apple_a7}, }; #endif static constexpr size_t ncpu_names = sizeof(cpus) / sizeof(cpus[0]); @@ -645,13 +810,6 @@ static CPU get_cpu_name(CPUID cpuid) case 0xb36: return CPU::arm_1136jf_s; case 0xb56: return CPU::arm_1156t2f_s; case 0xb76: return CPU::arm_1176jzf_s; - case 0xc20: return CPU::arm_cortex_m0; - case 0xc21: return CPU::arm_cortex_m1; - case 0xc23: return CPU::arm_cortex_m3; - case 0xc24: return CPU::arm_cortex_m4; - case 0xc27: return CPU::arm_cortex_m7; - case 0xd20: return CPU::arm_cortex_m23; - case 0xd21: return CPU::arm_cortex_m33; case 0xc05: return CPU::arm_cortex_a5; case 0xc07: return CPU::arm_cortex_a7; case 0xc08: return CPU::arm_cortex_a8; @@ -663,19 +821,39 @@ static CPU get_cpu_name(CPUID cpuid) case 0xc15: return CPU::arm_cortex_r5; case 0xc17: return CPU::arm_cortex_r7; case 0xc18: return CPU::arm_cortex_r8; - case 0xd13: return CPU::arm_cortex_r52; + case 0xc20: return CPU::arm_cortex_m0; + case 0xc21: return CPU::arm_cortex_m1; + case 0xc23: return CPU::arm_cortex_m3; + case 0xc24: return CPU::arm_cortex_m4; + case 0xc27: return CPU::arm_cortex_m7; case 0xd01: return CPU::arm_cortex_a32; - case 0xd04: return CPU::arm_cortex_a35; + case 0xd02: return CPU::arm_cortex_a34; case 0xd03: return CPU::arm_cortex_a53; + case 0xd04: return CPU::arm_cortex_a35; case 0xd05: return CPU::arm_cortex_a55; + case 0xd06: return CPU::arm_cortex_a65; case 0xd07: return CPU::arm_cortex_a57; case 0xd08: return CPU::arm_cortex_a72; case 0xd09: return CPU::arm_cortex_a73; case 0xd0a: return CPU::arm_cortex_a75; + case 0xd0b: return CPU::arm_cortex_a76; + case 0xd0c: return CPU::arm_neoverse_n1; + case 0xd0d: return CPU::arm_cortex_a77; + case 0xd0e: return CPU::arm_cortex_a76ae; + case 0xd13: return CPU::arm_cortex_r52; + case 0xd20: return CPU::arm_cortex_m23; + case 0xd21: return CPU::arm_cortex_m33; + // case 0xd22: return CPU::arm_cortex_m55; + case 0xd40: return CPU::arm_zeus; + case 0xd41: return CPU::arm_cortex_a78; + case 0xd43: return CPU::arm_cortex_a65ae; + case 0xd44: return CPU::arm_cortex_x1; + case 0xd4a: return CPU::arm_neoverse_e1; default: return CPU::generic; } case 0x42: // Broadcom (Cavium) switch (cpuid.part) { + // case 0x100: return CPU::broadcom_brahma_b53; case 0x516: return CPU::cavium_thunderx2t99p1; default: return CPU::generic; } @@ -689,12 +867,30 @@ static CPU get_cpu_name(CPUID cpuid) case 0xa2: return CPU::cavium_thunderx81; case 0xa3: return CPU::cavium_thunderx83; case 0xaf: return CPU::cavium_thunderx2t99; + case 0xb0: return CPU::cavium_octeontx2; + case 0xb1: return CPU::cavium_octeontx2t98; + case 0xb2: return CPU::cavium_octeontx2t96; + case 0xb3: return CPU::cavium_octeontx2f95; + case 0xb4: return CPU::cavium_octeontx2f95n; + case 0xb5: return CPU::cavium_octeontx2f95mm; + case 0xb8: return CPU::marvell_thunderx3t110; + default: return CPU::generic; + } + case 0x46: // Fujitsu + switch (cpuid.part) { + case 0x1: return CPU::fujitsu_a64fx; + default: return CPU::generic; + } + case 0x48: // HiSilicon + switch (cpuid.part) { + case 0xd01: return CPU::hisilicon_tsv110; default: return CPU::generic; } case 0x4e: // NVIDIA switch (cpuid.part) { case 0x000: return CPU::nvidia_denver1; case 0x003: return CPU::nvidia_denver2; + case 0x004: return CPU::nvidia_carmel; default: return CPU::generic; } case 0x50: // AppliedMicro @@ -718,6 +914,10 @@ static CPU get_cpu_name(CPUID cpuid) return CPU::qualcomm_kyro; case 0x800: case 0x801: + case 0x802: + case 0x803: + case 0x804: + case 0x805: return CPU::arm_cortex_a73; // second-generation Kryo case 0xc00: return CPU::qualcomm_falkor; @@ -726,10 +926,13 @@ static CPU get_cpu_name(CPUID cpuid) default: return CPU::generic; } case 0x53: // Samsung - // exynos-m2 - // exynos-m3 + if (cpuid.part == 1) + return CPU::samsung_exynos_m1; + if (cpuid.variant != 1) + return CPU::generic; switch (cpuid.part) { - case 0x001: return CPU::samsung_exynos_m1; + case 0x2: return CPU::samsung_exynos_m3; + case 0x3: return CPU::samsung_exynos_m4; default: return CPU::generic; } case 0x56: // Marvell @@ -739,13 +942,40 @@ static CPU get_cpu_name(CPUID cpuid) return CPU::marvell_pj4; default: return CPU::generic; } - case 0x67: // Apple - // swift - // cyclone - // twister - // hurricane + case 0x61: // Apple + // https://opensource.apple.com/source/xnu/xnu-6153.81.5/osfmk/arm/cpuid.h.auto.html + switch (cpuid.part) { + case 0x0: // Swift + return CPU::apple_swift; + case 0x1: // Cyclone + return CPU::apple_a7; + case 0x2: // Typhoon + case 0x3: // Typhoo/Capri + return CPU::apple_a8; + case 0x4: // Twister + case 0x5: // Twister/Elba/Malta + return CPU::apple_a9; + case 0x6: // Hurricane + case 0x7: // Hurricane/Myst + return CPU::apple_a10; + case 0x8: // Monsoon + case 0x9: // Mistral + return CPU::apple_a11; + case 0xB: // Vortex + case 0xC: // Tempest + case 0x10: // A12X, Vortex Aruba + case 0x11: // A12X, Tempest Aruba + return CPU::apple_a12; + case 0xF: // Tempest M9 + return CPU::apple_s4; + case 0x12: // Lightning + case 0x13: // Thunder + return CPU::apple_a13; + default: return CPU::generic; + } + case 0x68: // Huaxintong Semiconductor switch (cpuid.part) { - case 0x072: return CPU::apple_typhoon; + case 0x0: return CPU::hxt_phecda; default: return CPU::generic; } case 0x69: // Intel @@ -758,10 +988,20 @@ static CPU get_cpu_name(CPUID cpuid) } } -static std::pair get_elf_arch(void) +namespace { + +struct arm_arch { + int version; + char klass; + constexpr bool mclass() const { return klass == 'M'; } +}; + +} + +static arm_arch get_elf_arch(void) { #ifdef _CPU_AARCH64_ - return std::make_pair(8, 'A'); + return {8, 'A'}; #else int ver = 0; char profile = 0; @@ -787,7 +1027,7 @@ static std::pair get_elf_arch(void) # if __ARM_ARCH > 6 && defined(__ARM_ARCH_PROFILE) profile = __ARM_ARCH_PROFILE; # endif - return std::make_pair(ver, profile); + return {ver, profile}; #endif } @@ -806,20 +1046,35 @@ static inline const char *find_cpu_name(uint32_t cpu) return ::find_cpu_name(cpu, cpus, ncpu_names); } -static std::pair feature_arch_version(const FeatureList &feature) +static arm_arch feature_arch_version(const FeatureList &feature) { #ifdef _CPU_AARCH64_ - return std::make_pair(8, false); + return {8, 'A'}; #else - if (test_nbit(feature, Feature::v8)) - return std::make_pair(8, test_nbit(feature, Feature::mclass)); - if (test_nbit(feature, Feature::v7)) - return std::make_pair(7, test_nbit(feature, Feature::mclass)); - return std::make_pair(6, false); + int ver; + if (test_nbit(feature, Feature::v8)) { + ver = 8; + } + else if (test_nbit(feature, Feature::v7)) { + ver = 7; + } + else { + return {6, 0}; + } + if (test_nbit(feature, Feature::mclass)) { + return {ver, 'M'}; + } + else if (test_nbit(feature, Feature::rclass)) { + return {ver, 'R'}; + } + else if (test_nbit(feature, Feature::aclass)) { + return {ver, 'A'}; + } + return {ver, 0}; #endif } -static CPU generic_for_arch(std::pair arch) +static CPU generic_for_arch(arm_arch arch) { #ifdef _CPU_AARCH64_ return CPU::generic; @@ -827,9 +1082,9 @@ static CPU generic_for_arch(std::pair arch) # if defined(__ARM_ARCH_PROFILE) char klass = __ARM_ARCH_PROFILE; # else - char klass = arch.second ? 'M' : 'A'; + char klass = arch.klass; # endif - if (arch.first >= 8) { + if (arch.version >= 8) { if (klass == 'M') { return CPU::armv8_m_base; } @@ -840,7 +1095,7 @@ static CPU generic_for_arch(std::pair arch) return CPU::armv8_a; } } - else if (arch.first == 7) { + else if (arch.version == 7) { if (klass == 'M') { return CPU::armv7_m; } @@ -855,16 +1110,16 @@ static CPU generic_for_arch(std::pair arch) #endif } -static bool check_cpu_arch_ver(uint32_t cpu, std::pair arch) +static bool check_cpu_arch_ver(uint32_t cpu, arm_arch arch) { auto spec = find_cpu(cpu); // This happens on AArch64 and indicates that the cpu name isn't a valid aarch64 CPU if (!spec) return false; - auto cpu_arch = feature_arch_version(spec->features); - if (arch.second != cpu_arch.second) + auto feature_arch = feature_arch_version(spec->features); + if (arch.mclass() != feature_arch.mclass()) return false; - if (arch.first > cpu_arch.first) + if (arch.version > feature_arch.version) return false; return true; } @@ -903,29 +1158,33 @@ static NOINLINE std::pair> _get_host_cpu() // high bits that we want to detect). features[0] = (uint32_t)jl_getauxval(AT_HWCAP); features[1] = (uint32_t)jl_getauxval(AT_HWCAP2); +#ifdef _CPU_AARCH64_ + if (test_nbit(features, 31)) // HWCAP_PACG + set_bit(features, Feature::pa, true); +#endif auto cpuinfo = get_cpuinfo(); auto arch = get_elf_arch(); #ifdef _CPU_ARM_ - if (arch.first >= 7) { - if (arch.second == 'M') { + if (arch.version >= 7) { + if (arch.klass == 'M') { set_bit(features, Feature::mclass, true); } - else if (arch.second == 'R') { + else if (arch.klass == 'R') { set_bit(features, Feature::rclass, true); } - else if (arch.second == 'A') { + else if (arch.klass == 'A') { set_bit(features, Feature::aclass, true); } } - switch (arch.first) { + switch (arch.version) { case 8: - set_bit(features, Feature::v8, true); - JL_FALLTHROUGH; + set_bit(features, Feature::v8, true); + JL_FALLTHROUGH; case 7: - set_bit(features, Feature::v7, true); - break; + set_bit(features, Feature::v7, true); + break; default: - break; + break; } #endif @@ -944,7 +1203,6 @@ static NOINLINE std::pair> _get_host_cpu() } // Not all elements/pairs are valid static constexpr CPU v8order[] = { - CPU::arm_cortex_a32, CPU::arm_cortex_a35, CPU::arm_cortex_a53, CPU::arm_cortex_a55, @@ -952,8 +1210,15 @@ static NOINLINE std::pair> _get_host_cpu() CPU::arm_cortex_a72, CPU::arm_cortex_a73, CPU::arm_cortex_a75, + CPU::arm_cortex_a76, + CPU::arm_neoverse_n1, CPU::nvidia_denver2, - CPU::samsung_exynos_m1 + CPU::nvidia_carmel, + CPU::samsung_exynos_m1, + CPU::samsung_exynos_m2, + CPU::samsung_exynos_m3, + CPU::samsung_exynos_m4, + CPU::samsung_exynos_m5, }; shrink_big_little(list, v8order, sizeof(v8order) / sizeof(CPU)); #ifdef _CPU_ARM_ @@ -1006,6 +1271,9 @@ static bool is_generic_cpu_name(uint32_t cpu) case CPU::armv8_1_a: case CPU::armv8_2_a: case CPU::armv8_3_a: + case CPU::armv8_4_a: + case CPU::armv8_5_a: + case CPU::armv8_6_a: return true; default: return false; @@ -1026,9 +1294,30 @@ static inline const std::string &host_cpu_name() return name; } +static inline const char *normalize_cpu_name(llvm::StringRef name) +{ + if (name == "ares") + return "neoverse-n1"; + if (name == "cyclone") + return "apple-a7"; + if (name == "typhoon") + return "apple-a8"; + if (name == "twister") + return "apple-a9"; + if (name == "hurricane") + return "apple-a10"; + return nullptr; +} + template static inline void enable_depends(FeatureList &features) { + if (test_nbit(features, Feature::v8_6a)) + set_bit(features, Feature::v8_5a, true); + if (test_nbit(features, Feature::v8_5a)) + set_bit(features, Feature::v8_4a, true); + if (test_nbit(features, Feature::v8_4a)) + set_bit(features, Feature::v8_3a, true); if (test_nbit(features, Feature::v8_3a)) set_bit(features, Feature::v8_2a, true); if (test_nbit(features, Feature::v8_2a)) @@ -1055,33 +1344,68 @@ static inline void enable_depends(FeatureList &features) set_bit(features, Feature::d32, true); } } - ::enable_depends(features, Feature::deps, sizeof(Feature::deps) / sizeof(FeatureDep)); #else if (test_nbit(features, Feature::v8_1a)) { set_bit(features, Feature::lse, true); set_bit(features, Feature::rdm, true); } + if (test_nbit(features, Feature::v8_2a)) { + set_bit(features, Feature::ccpp, true); + } + if (test_nbit(features, Feature::v8_3a)) { + set_bit(features, Feature::jsconv, true); + set_bit(features, Feature::complxnum, true); + set_bit(features, Feature::rcpc, true); + } + if (test_nbit(features, Feature::v8_4a)) { + set_bit(features, Feature::dit, true); + set_bit(features, Feature::rcpc_immo, true); + set_bit(features, Feature::fmi, true); + } + if (test_nbit(features, Feature::v8_5a)) { + set_bit(features, Feature::sb, true); + set_bit(features, Feature::ccdp, true); + set_bit(features, Feature::altnzcv, true); + set_bit(features, Feature::fptoint, true); + } + if (test_nbit(features, Feature::v8_6a)) { + set_bit(features, Feature::i8mm, true); + set_bit(features, Feature::bf16, true); + } #endif + ::enable_depends(features, Feature::deps, sizeof(Feature::deps) / sizeof(FeatureDep)); } template static inline void disable_depends(FeatureList &features) { -#ifdef _CPU_ARM_ ::disable_depends(features, Feature::deps, sizeof(Feature::deps) / sizeof(FeatureDep)); -#endif } static const std::vector> &get_cmdline_targets(void) { auto feature_cb = [] (const char *str, size_t len, FeatureList &list) { +#ifdef _CPU_AARCH64_ + // On AArch64, treat `crypto` as an alias of aes + sha2 just like LLVM + if (llvm::StringRef(str, len) == "crypto") { + set_bit(list, Feature::aes, true); + set_bit(list, Feature::sha2, true); + return true; + } +#endif auto fbit = find_feature_bit(feature_names, nfeature_names, str, len); if (fbit == (uint32_t)-1) return false; set_bit(list, fbit, true); return true; }; - return ::get_cmdline_targets(feature_cb); + auto &targets = ::get_cmdline_targets(feature_cb); + for (auto &t: targets) { + if (auto nname = normalize_cpu_name(t.name)) { + t.name = nname; + } + } + return targets; } static std::vector> jit_targets; @@ -1130,7 +1454,10 @@ static int max_vector_size(const FeatureList &features) return 16; return 8; #else - // TODO SVE + if (test_nbit(features, Feature::sve2)) + return 256; + if (test_nbit(features, Feature::sve)) + return 128; return 16; #endif } @@ -1142,6 +1469,11 @@ static uint32_t sysimg_init_cb(const void *id) TargetData target = arg_target_data(cmdline[0], true); // Then find the best match in the sysimg auto sysimg = deserialize_target_data((const uint8_t*)id); + for (auto &t: sysimg) { + if (auto nname = normalize_cpu_name(t.name)) { + t.name = nname; + } + } auto match = match_sysimg_targets(sysimg, target, max_vector_size); // Now we've decided on which sysimg version to use. // Make sure the JIT target is compatible with it and save the JIT target. @@ -1211,6 +1543,11 @@ get_llvm_target_noext(const TargetData &data) name = "generic"; } } +#ifdef _CPU_ARM_ + // We use the name on aarch64 internally but the LLVM ARM backend still use the old name... + if (name == "apple-a7") + name = "cyclone"; +#endif std::vector feature_strs; for (auto &fename: feature_names) { if (fename.llvmver > JL_LLVM_VERSION) @@ -1238,6 +1575,16 @@ get_llvm_target_noext(const TargetData &data) feature_strs.push_back(std::string("-") + fename_str); } } +#if JL_LLVM_VERSION >= 110000 + if (test_nbit(features, Feature::v8_6a)) + feature_strs.push_back("+v8.6a"); +#endif + if (test_nbit(features, Feature::v8_5a)) + feature_strs.push_back("+v8.5a"); + if (test_nbit(features, Feature::v8_4a)) + feature_strs.push_back("+v8.4a"); + if (test_nbit(features, Feature::v8_3a)) + feature_strs.push_back("+v8.3a"); if (test_nbit(features, Feature::v8_2a)) feature_strs.push_back("+v8.2a"); if (test_nbit(features, Feature::v8_1a)) @@ -1304,21 +1651,25 @@ static FeatureList get_max_feature(void) #ifdef _CPU_ARM_ auto arch = get_elf_arch(); auto features = real_feature_masks; - if (arch.second == 0) - arch.second = 'A'; + if (arch.klass == 0) + arch.klass = 'A'; set_bit(features, Feature::v7, true); set_bit(features, Feature::v8, true); - if (arch.second == 'M') { + if (arch.klass == 'M') { set_bit(features, Feature::mclass, true); set_bit(features, Feature::v8_m_main, true); } - else if (arch.second == 'R') { + else if (arch.klass == 'R') { set_bit(features, Feature::rclass, true); } - else if (arch.second == 'A') { + else if (arch.klass == 'A') { set_bit(features, Feature::aclass, true); set_bit(features, Feature::v8_1a, true); set_bit(features, Feature::v8_2a, true); + set_bit(features, Feature::v8_3a, true); + set_bit(features, Feature::v8_4a, true); + set_bit(features, Feature::v8_5a, true); + set_bit(features, Feature::v8_6a, true); } return features; #else @@ -1358,10 +1709,19 @@ std::pair> jl_get_llvm_target(bool imaging, const std::pair &jl_get_llvm_disasm_target(void) { - // RAS is not currently detectable AFAICT auto max_feature = get_max_feature(); static const auto res = get_llvm_target_str(TargetData{host_cpu_name(), - "+dotprod,+ras", +#ifdef _CPU_AARCH64_ +# if JL_LLVM_VERSION > 110000 + "+ecv," +# endif +# if JL_LLVM_VERSION > 100000 + "+tme," +# endif + "+am,+specrestrict,+predres,+mte,+lor,+perfmon,+spe,+tracev8.4", +#else + "+dotprod", +#endif {max_feature, 0}, {feature_masks & ~max_feature, 0}, 0}); return res; } diff --git a/src/processor_x86.cpp b/src/processor_x86.cpp index 2ff392175f0b5..4f3c391b30660 100644 --- a/src/processor_x86.cpp +++ b/src/processor_x86.cpp @@ -60,6 +60,8 @@ enum class CPU : uint32_t { intel_atom_bonnell, intel_atom_silvermont, intel_atom_goldmont, + intel_atom_goldmont_plus, + intel_atom_tremont, intel_core2, intel_core2_penryn, intel_yonah, @@ -71,8 +73,14 @@ enum class CPU : uint32_t { intel_corei7_broadwell, intel_corei7_skylake, intel_corei7_skylake_avx512, + intel_corei7_cascadelake, + intel_corei7_cooperlake, intel_corei7_cannonlake, + intel_corei7_icelake_client, + intel_corei7_icelake_server, + intel_corei7_tigerlake, intel_knights_landing, + intel_knights_mill, amd_fam10h, amd_athlon_fx, @@ -90,9 +98,10 @@ enum class CPU : uint32_t { amd_opteron_sse3, amd_barcelona, amd_znver1, + amd_znver2, }; -static constexpr size_t feature_sz = 9; +static constexpr size_t feature_sz = 11; static constexpr FeatureName feature_names[] = { #define JL_FEATURE_DEF(name, bit, llvmver) {#name, bit, llvmver}, #define JL_FEATURE_DEF_NAME(name, bit, llvmver, str) {str, bit, llvmver}, @@ -130,6 +139,10 @@ static constexpr FeatureDep deps[] = { {avx, sse42}, {f16c, avx}, {avx2, avx}, + {vaes, avx}, + {vaes, aes}, + {vpclmulqdq, avx}, + {vpclmulqdq, pclmul}, {avx512f, avx2}, {avx512dq, avx512f}, {avx512ifma, avx512f}, @@ -137,13 +150,23 @@ static constexpr FeatureDep deps[] = { {avx512er, avx512f}, {avx512cd, avx512f}, {avx512bw, avx512f}, + {avx512bf16, avx512bw}, + {avx512bitalg, avx512bw}, {avx512vl, avx512f}, {avx512vbmi, avx512bw}, + {avx512vbmi2, avx512bw}, + {avx512vnni, avx512f}, + {avx512vp2intersect, avx512f}, {avx512vpopcntdq, avx512f}, + {amx_int8, amx_tile}, + {amx_bf16, amx_tile}, {sse4a, sse3}, {xop, fma4}, {fma4, avx}, - {fma4, sse4a} + {fma4, sse4a}, + {xsaveopt, xsave}, + {xsavec, xsave}, + {xsaves, xsave}, }; // We require cx16 on 64bit by default. This can be overwritten with `-cx16` @@ -151,27 +174,41 @@ static constexpr FeatureDep deps[] = { constexpr auto generic = get_feature_masks(cx16); constexpr auto bonnell = get_feature_masks(sse3, ssse3, cx16, movbe, sahf); constexpr auto silvermont = bonnell | get_feature_masks(sse41, sse42, popcnt, - pclmul, aes, prfchw); -constexpr auto goldmont = silvermont | get_feature_masks(mpx, sha, rdrnd, rdseed, xsave, - xsaveopt, xsavec, xsaves, clflushopt); + pclmul, prfchw, rdrnd); +constexpr auto goldmont = silvermont | get_feature_masks(aes, sha, rdseed, xsave, xsaveopt, + xsavec, xsaves, clflushopt, fsgsbase); +constexpr auto goldmont_plus = goldmont | get_feature_masks(ptwrite, rdpid); // sgx +constexpr auto tremont = goldmont_plus | get_feature_masks(clwb, gfni); +constexpr auto knl = get_feature_masks(sse3, ssse3, sse41, sse42, cx16, sahf, popcnt, + aes, pclmul, avx, xsave, xsaveopt, rdrnd, f16c, fsgsbase, + avx2, bmi, bmi2, fma, lzcnt, movbe, adx, rdseed, prfchw, + avx512f, avx512er, avx512cd, avx512pf, prefetchwt1); +constexpr auto knm = knl | get_feature_masks(avx512vpopcntdq); constexpr auto yonah = get_feature_masks(sse3); constexpr auto prescott = yonah; constexpr auto core2 = get_feature_masks(sse3, ssse3, cx16, sahf); constexpr auto nocona = get_feature_masks(sse3, cx16); constexpr auto penryn = nocona | get_feature_masks(ssse3, sse41, sahf); constexpr auto nehalem = penryn | get_feature_masks(sse42, popcnt); -constexpr auto westmere = nehalem | get_feature_masks(aes, pclmul); +constexpr auto westmere = nehalem | get_feature_masks(pclmul); constexpr auto sandybridge = westmere | get_feature_masks(avx, xsave, xsaveopt); constexpr auto ivybridge = sandybridge | get_feature_masks(rdrnd, f16c, fsgsbase); constexpr auto haswell = ivybridge | get_feature_masks(avx2, bmi, bmi2, fma, lzcnt, movbe); constexpr auto broadwell = haswell | get_feature_masks(adx, rdseed, prfchw); -constexpr auto skylake = broadwell | get_feature_masks(mpx, rtm, xsavec, xsaves, - clflushopt); // ignore sgx; hle -constexpr auto knl = broadwell | get_feature_masks(avx512f, avx512er, avx512cd, avx512pf, - prefetchwt1); +constexpr auto skylake = broadwell | get_feature_masks(aes, xsavec, xsaves, clflushopt); // sgx constexpr auto skx = skylake | get_feature_masks(avx512f, avx512cd, avx512dq, avx512bw, avx512vl, pku, clwb); -constexpr auto cannonlake = skx | get_feature_masks(avx512vbmi, avx512ifma, sha); +constexpr auto cascadelake = skx | get_feature_masks(avx512vnni); +constexpr auto cooperlake = cascadelake | get_feature_masks(avx512bf16); +constexpr auto cannonlake = skylake | get_feature_masks(avx512f, avx512cd, avx512dq, avx512bw, + avx512vl, pku, avx512vbmi, avx512ifma, + sha); // sgx +constexpr auto icelake = cannonlake | get_feature_masks(avx512bitalg, vaes, avx512vbmi2, + vpclmulqdq, avx512vpopcntdq, + gfni, clwb, rdpid); +constexpr auto icelake_server = icelake | get_feature_masks(pconfig, wbnoinvd); +constexpr auto tigerlake = icelake | get_feature_masks(avx512vp2intersect, movdiri, + movdir64b, shstk); constexpr auto k8_sse3 = get_feature_masks(sse3, cx16); constexpr auto amdfam10 = k8_sse3 | get_feature_masks(sse4a, lzcnt, popcnt, sahf); @@ -184,10 +221,11 @@ constexpr auto bdver1 = amdfam10 | get_feature_masks(xop, fma4, avx, ssse3, sse4 prfchw, pclmul, xsave, lwp); constexpr auto bdver2 = bdver1 | get_feature_masks(f16c, bmi, tbm, fma); constexpr auto bdver3 = bdver2 | get_feature_masks(xsaveopt, fsgsbase); -constexpr auto bdver4 = bdver3 | get_feature_masks(avx2, bmi2, mwaitx); +constexpr auto bdver4 = bdver3 | get_feature_masks(avx2, bmi2, mwaitx, movbe, rdrnd); -constexpr auto znver1 = haswell | get_feature_masks(adx, clflushopt, clzero, mwaitx, prfchw, +constexpr auto znver1 = haswell | get_feature_masks(adx, aes, clflushopt, clzero, mwaitx, prfchw, rdseed, sha, sse4a, xsavec, xsaves); +constexpr auto znver2 = znver1 | get_feature_masks(clwb, rdpid, wbnoinvd); } @@ -195,7 +233,9 @@ static constexpr CPUSpec cpus[] = { {"generic", CPU::generic, CPU::generic, 0, Feature::generic}, {"bonnell", CPU::intel_atom_bonnell, CPU::generic, 0, Feature::bonnell}, {"silvermont", CPU::intel_atom_silvermont, CPU::generic, 0, Feature::silvermont}, - {"goldmont", CPU::intel_atom_goldmont, CPU::generic, 50000, Feature::goldmont}, + {"goldmont", CPU::intel_atom_goldmont, CPU::generic, 0, Feature::goldmont}, + {"goldmont-plus", CPU::intel_atom_goldmont_plus, CPU::generic, 0, Feature::goldmont_plus}, + {"tremont", CPU::intel_atom_tremont, CPU::generic, 0, Feature::tremont}, {"core2", CPU::intel_core2, CPU::generic, 0, Feature::core2}, {"yonah", CPU::intel_yonah, CPU::generic, 0, Feature::yonah}, {"prescott", CPU::intel_prescott, CPU::generic, 0, Feature::prescott}, @@ -209,9 +249,17 @@ static constexpr CPUSpec cpus[] = { {"broadwell", CPU::intel_corei7_broadwell, CPU::generic, 0, Feature::broadwell}, {"skylake", CPU::intel_corei7_skylake, CPU::generic, 0, Feature::skylake}, {"knl", CPU::intel_knights_landing, CPU::generic, 0, Feature::knl}, + {"knm", CPU::intel_knights_mill, CPU::generic, 0, Feature::knm}, {"skylake-avx512", CPU::intel_corei7_skylake_avx512, CPU::generic, 0, Feature::skx}, - {"cannonlake", CPU::intel_corei7_cannonlake, CPU::intel_corei7_skylake_avx512, 40000, - Feature::cannonlake}, + {"cascadelake", CPU::intel_corei7_cascadelake, CPU::generic, 0, Feature::cascadelake}, + {"cooperlake", CPU::intel_corei7_cooperlake, CPU::intel_corei7_cascadelake, + 90000, Feature::cooperlake}, + {"cannonlake", CPU::intel_corei7_cannonlake, CPU::generic, 0, Feature::cannonlake}, + {"icelake-client", CPU::intel_corei7_icelake_client, CPU::generic, 0, Feature::icelake}, + {"icelake-server", CPU::intel_corei7_icelake_server, CPU::generic, 0, + Feature::icelake_server}, + {"tigerlake", CPU::intel_corei7_tigerlake, CPU::intel_corei7_icelake_client, 100000, + Feature::tigerlake}, {"athlon64", CPU::amd_athlon_64, CPU::generic, 0, Feature::generic}, {"athlon-fx", CPU::amd_athlon_fx, CPU::generic, 0, Feature::generic}, @@ -234,6 +282,7 @@ static constexpr CPUSpec cpus[] = { {"bdver4", CPU::amd_bdver4, CPU::generic, 0, Feature::bdver4}, {"znver1", CPU::amd_znver1, CPU::generic, 0, Feature::znver1}, + {"znver2", CPU::amd_znver2, CPU::amd_znver1, 90000, Feature::znver2}, }; static constexpr size_t ncpu_names = sizeof(cpus) / sizeof(cpus[0]); @@ -338,11 +387,37 @@ static CPU get_intel_processor_name(uint32_t family, uint32_t model, uint32_t br case 0x5e: // Skylake desktop case 0x8e: // Kaby Lake mobile case 0x9e: // Kaby Lake desktop + case 0xa5: // Comet Lake-H/S + case 0xa6: // Comet Lake-U return CPU::intel_corei7_skylake; // Skylake Xeon: case 0x55: - return CPU::intel_corei7_skylake; + if (test_nbit(features, Feature::avx512bf16)) + return CPU::intel_corei7_cooperlake; + if (test_nbit(features, Feature::avx512vnni)) + return CPU::intel_corei7_cascadelake; + return CPU::intel_corei7_skylake_avx512; + + // Cannonlake: + case 0x66: + return CPU::intel_corei7_cannonlake; + + // Icelake: + case 0x7d: + case 0x7e: + case 0x9d: + return CPU::intel_corei7_icelake_client; + + // Icelake Xeon: + case 0x6a: + case 0x6c: + return CPU::intel_corei7_icelake_server; + + // Tiger Lake + case 0x8c: + case 0x8d: + return CPU::intel_corei7_tigerlake; case 0x1c: // Most 45 nm Intel Atom processors case 0x26: // 45 nm Atom Lincroft @@ -355,19 +430,30 @@ static CPU get_intel_processor_name(uint32_t family, uint32_t model, uint32_t br case 0x37: case 0x4a: case 0x4d: - case 0x5a: case 0x5d: - case 0x4c: // really airmont + // Airmont + case 0x4c: + case 0x5a: + case 0x75: return CPU::intel_atom_silvermont; // Goldmont: case 0x5c: case 0x5f: return CPU::intel_atom_goldmont; + case 0x7a: + return CPU::intel_atom_goldmont_plus; + case 0x86: + case 0x96: + case 0x9c: + return CPU::intel_atom_tremont; case 0x57: return CPU::intel_knights_landing; + case 0x85: + return CPU::intel_knights_mill; + default: return CPU::generic; } @@ -441,8 +527,6 @@ static CPU get_amd_processor_name(uint32_t family, uint32_t model, const uint32_ case 20: return CPU::amd_btver1; case 21: - if (!test_nbit(features, Feature::avx)) - return CPU::amd_btver1; if (model >= 0x50 && model <= 0x6f) return CPU::amd_bdver4; if (model >= 0x30 && model <= 0x3f) @@ -453,13 +537,15 @@ static CPU get_amd_processor_name(uint32_t family, uint32_t model, const uint32_ return CPU::amd_bdver1; return CPU::amd_btver1; // fallback case 22: - if (!test_nbit(features, Feature::avx)) - return CPU::amd_btver1; return CPU::amd_btver2; case 23: - if (test_nbit(features, Feature::adx)) - return CPU::amd_znver1; - return CPU::amd_btver1; + // Known models: + // Zen: 1, 17 + // Zen+: 8, 24 + // Zen2: 96, 113 + if (model >= 0x30) + return CPU::amd_znver2; + return CPU::amd_znver1; } } @@ -468,7 +554,8 @@ static inline void features_disable_avx512(T &features) { using namespace Feature; unset_bits(features, avx512f, avx512dq, avx512ifma, avx512pf, avx512er, avx512cd, - avx512bw, avx512vl, avx512vbmi); + avx512bw, avx512vl, avx512vbmi, avx512vpopcntdq, avx512vbmi2, avx512vnni, + avx512bitalg, avx512vp2intersect, avx512bf16); } template @@ -476,7 +563,14 @@ static inline void features_disable_avx(T &features) { using namespace Feature; unset_bits(features, avx, Feature::fma, f16c, xsave, avx2, xop, fma4, - xsaveopt, xsavec, xsaves); + xsaveopt, xsavec, xsaves, vaes, vpclmulqdq); +} + +template +static inline void features_disable_amx(T &features) +{ + using namespace Feature; + unset_bits(features, amx_bf16, amx_tile, amx_int8); } static NOINLINE std::pair> _get_host_cpu(void) @@ -533,21 +627,35 @@ static NOINLINE std::pair> _get_host_cpu(void) jl_cpuidex(infoex8, 0x80000008, 0); features[8] = infoex8[1]; } + if (maxleaf >= 7) { + int32_t info7[4]; + jl_cpuidex(info7, 7, 1); + features[9] = info7[0]; + } + if (maxleaf >= 0x14) { + int32_t info14[4]; + jl_cpuidex(info14, 0x14, 0); + features[10] = info14[1]; + } // Fix up AVX bits to account for OS support and match LLVM model uint64_t xcr0 = 0; - const uint32_t avx_mask = (1 << 27) | (1 << 28); - bool hasavx = test_all_bits(features[0], avx_mask); - if (hasavx) { + bool hasxsave = test_all_bits(features[0], 1 << 27); + if (hasxsave) { xcr0 = get_xcr0(); - hasavx = test_all_bits(xcr0, 0x6); + hasxsave = test_all_bits(xcr0, 0x6); } + bool hasavx = hasxsave && test_all_bits(features[0], 1 << 28); unset_bits(features, 32 + 27); if (!hasavx) features_disable_avx(features); bool hasavx512save = hasavx && test_all_bits(xcr0, 0xe0); if (!hasavx512save) features_disable_avx512(features); + // AMX requires additional context to be saved by the OS. + bool hasamxsave = hasxsave && test_all_bits(xcr0, (1 << 17) | (1 << 18)); + if (!hasamxsave) + features_disable_amx(features); // Ignore feature bits that we are not interested in. mask_features(feature_masks, &features[0]); @@ -768,9 +876,10 @@ static void ensure_jit_target(bool imaging) // The most useful one in general... t.en.flags |= JL_TARGET_CLONE_LOOP; auto &features0 = jit_targets[t.base].en.features; - // Special case for KNL since it's so different + // Special case for KNL/KNM since they're so different if (!(t.dis.flags & JL_TARGET_CLONE_ALL)) { - if (t.name == "knl" && jit_targets[t.base].name != "knl") { + if ((t.name == "knl" || t.name == "knm") && + jit_targets[t.base].name != "knl" && jit_targets[t.base].name != "knm") { t.en.flags |= JL_TARGET_CLONE_ALL; break; } @@ -779,12 +888,16 @@ static void ensure_jit_target(bool imaging) static constexpr uint32_t clone_simd[] = {Feature::sse3, Feature::ssse3, Feature::sse41, Feature::sse42, Feature::avx, Feature::avx2, + Feature::vaes, Feature::vpclmulqdq, Feature::sse4a, Feature::avx512f, Feature::avx512dq, Feature::avx512ifma, Feature::avx512pf, Feature::avx512er, Feature::avx512cd, Feature::avx512bw, Feature::avx512vl, Feature::avx512vbmi, - Feature::avx512vpopcntdq}; + Feature::avx512vpopcntdq, + Feature::avx512vbmi2, Feature::avx512vnni, + Feature::avx512bitalg, Feature::avx512bf16, + Feature::avx512vp2intersect}; for (auto fe: clone_math) { if (!test_nbit(features0, fe) && test_nbit(t.en.features, fe)) { t.en.flags |= JL_TARGET_CLONE_MATH; @@ -838,6 +951,9 @@ get_llvm_target_noext(const TargetData &data) // returns a value that may not have 64bit support. // This can happen with virtualization. features.push_back("+64bit"); +#endif +#if JL_LLVM_VERSION >= 90000 + features.push_back("+cx8"); #endif return std::make_pair(std::move(name), std::move(features)); } diff --git a/src/subtype.c b/src/subtype.c index 841ea17ff3584..4aadeef340440 100644 --- a/src/subtype.c +++ b/src/subtype.c @@ -2750,7 +2750,7 @@ static jl_value_t *intersect_sub_datatype(jl_datatype_t *xd, jl_datatype_t *yd, jl_value_t *isuper = R ? intersect((jl_value_t*)yd, (jl_value_t*)xd->super, e, param) : intersect((jl_value_t*)xd->super, (jl_value_t*)yd, e, param); if (isuper == jl_bottom_type) return jl_bottom_type; - if (jl_nparams(xd) == 0 || jl_nparams(xd->super) == 0) + if (jl_nparams(xd) == 0 || jl_nparams(xd->super) == 0 || !jl_has_free_typevars(xd)) return (jl_value_t*)xd; jl_value_t *super_pattern=NULL; JL_GC_PUSH2(&isuper, &super_pattern); diff --git a/stdlib/LinearAlgebra/src/matmul.jl b/stdlib/LinearAlgebra/src/matmul.jl index 66242177f2ea6..812d114a992b1 100644 --- a/stdlib/LinearAlgebra/src/matmul.jl +++ b/stdlib/LinearAlgebra/src/matmul.jl @@ -646,30 +646,34 @@ function generic_matvecmul!(C::AbstractVector{R}, tA, A::AbstractVecOrMat, B::Ab @inbounds begin if tA == 'T' # fastest case - for k = 1:mA - aoffs = (k-1)*Astride - if mB == 0 - s = false - else - s = zero(A[aoffs + 1]*B[1] + A[aoffs + 1]*B[1]) + if nA == 0 + for k = 1:mA + _modify!(_add, false, C, k) end - for i = 1:nA - s += transpose(A[aoffs+i]) * B[i] + else + for k = 1:mA + aoffs = (k-1)*Astride + s = zero(A[aoffs + 1]*B[1] + A[aoffs + 1]*B[1]) + for i = 1:nA + s += transpose(A[aoffs+i]) * B[i] + end + _modify!(_add, s, C, k) end - _modify!(_add, s, C, k) end elseif tA == 'C' - for k = 1:mA - aoffs = (k-1)*Astride - if mB == 0 - s = false - else - s = zero(A[aoffs + 1]*B[1] + A[aoffs + 1]*B[1]) + if nA == 0 + for k = 1:mA + _modify!(_add, false, C, k) end - for i = 1:nA - s += A[aoffs + i]'B[i] + else + for k = 1:mA + aoffs = (k-1)*Astride + s = zero(A[aoffs + 1]*B[1] + A[aoffs + 1]*B[1]) + for i = 1:nA + s += A[aoffs + i]'B[i] + end + _modify!(_add, s, C, k) end - _modify!(_add, s, C, k) end else # tA == 'N' for i = 1:mA diff --git a/stdlib/Pkg.version b/stdlib/Pkg.version index 38c43c15f11c4..addb75df5a5d5 100644 --- a/stdlib/Pkg.version +++ b/stdlib/Pkg.version @@ -1,2 +1,2 @@ PKG_BRANCH = master -PKG_SHA1 = edc31a25ad441b28bbe5608696cca978af6c988a +PKG_SHA1 = aaf4e6e8ab784f7435c1bdc56832bc03e014dedb diff --git a/stdlib/REPL/src/REPL.jl b/stdlib/REPL/src/REPL.jl index acf6ebdb727d7..7f52201dd1fc9 100644 --- a/stdlib/REPL/src/REPL.jl +++ b/stdlib/REPL/src/REPL.jl @@ -961,7 +961,8 @@ function setup_interface( end hist_from_file(hp, f, hist_path) catch - print_response(repl, (catch_stack(),true), true, hascolor(repl)) + # use REPL.hascolor to avoid using the local variable with the same name + print_response(repl, (catch_stack(),true), true, REPL.hascolor(repl)) println(outstream(repl)) @info "Disabling history file for this session" repl.history_file = false diff --git a/test/numbers.jl b/test/numbers.jl index 546c262e31e8c..03487cc353089 100644 --- a/test/numbers.jl +++ b/test/numbers.jl @@ -415,14 +415,16 @@ end @test repr(-NaN) == "NaN" @test repr(Float64(pi)) == "3.141592653589793" # issue 6608 - @test sprint(show, 666666.6, context=:compact => true) == "666667.0" + @test sprint(show, 666666.6, context=:compact => true) == "6.66667e5" @test sprint(show, 666666.049, context=:compact => true) == "666666.0" @test sprint(show, 666665.951, context=:compact => true) == "666666.0" @test sprint(show, 66.66666, context=:compact => true) == "66.6667" - @test sprint(show, -666666.6, context=:compact => true) == "-666667.0" + @test sprint(show, -666666.6, context=:compact => true) == "-6.66667e5" @test sprint(show, -666666.049, context=:compact => true) == "-666666.0" @test sprint(show, -666665.951, context=:compact => true) == "-666666.0" @test sprint(show, -66.66666, context=:compact => true) == "-66.6667" + @test sprint(show, -498796.2749933266, context=:compact => true) == "-4.98796e5" + @test sprint(show, 123456.78, context=:compact=>true) == "1.23457e5" @test repr(1.0f0) == "1.0f0" @test repr(-1.0f0) == "-1.0f0" diff --git a/test/precompile.jl b/test/precompile.jl index bf82c1037f18e..711387842146b 100644 --- a/test/precompile.jl +++ b/test/precompile.jl @@ -403,7 +403,7 @@ try error("break me") end """) - @test_warn "ERROR: LoadError: break me\nStacktrace:\n [1] error" try + @test_warn "LoadError: break me\nStacktrace:\n [1] error" try Base.require(Main, :FooBar2) error("the \"break me\" test failed") catch exc diff --git a/test/reducedim.jl b/test/reducedim.jl index 3f59ae6e2570a..8a070f97c593f 100644 --- a/test/reducedim.jl +++ b/test/reducedim.jl @@ -4,6 +4,10 @@ using Random # main tests +# issue #35800 +# tested very early since it can be state-dependent +@test @inferred(mapreduce(x->count(!iszero,x), +, [rand(1)]; init = 0.)) == 1.0 + function safe_mapslices(op, A, region) newregion = intersect(region, 1:ndims(A)) return isempty(newregion) ? A : mapslices(op, A, dims = newregion) diff --git a/test/sets.jl b/test/sets.jl index 5d8db78803cb8..75e4537972e96 100644 --- a/test/sets.jl +++ b/test/sets.jl @@ -454,6 +454,13 @@ end @test allunique(Date(2018, 8, 7):Day(1):Date(2018, 8, 11)) # JuliaCon 2018 @test allunique(DateTime(2018, 8, 7):Hour(1):DateTime(2018, 8, 11)) @test allunique(('a':1:'c')[1:2]) == true + for r = (Base.OneTo(-1), Base.OneTo(0), Base.OneTo(1), Base.OneTo(5), + 1:0, 1:1, 1:2, 1:10, 1:.5:.5, 1:.5:1, 1:.5:10, 3:-2:5, 3:-2:3, 3:-2:1, + StepRangeLen(1.0, 2.0, 0), StepRangeLen(1.0, 2.0, 2), StepRangeLen(1.0, 2.0, 3), + StepRangeLen(1.0, 0.0, 0), StepRangeLen(1.0, -0.0, 1), StepRangeLen(1.0, 0.0, 2), + LinRange(1, 2, 3), LinRange(1, 1, 0), LinRange(1, 1, 1), LinRange(1, 1, 10)) + @test allunique(r) == invoke(allunique, Tuple{Any}, r) + end end @testset "filter(f, ::$S)" for S = (Set, BitSet) s = S([1,2,3,4]) diff --git a/test/strings/util.jl b/test/strings/util.jl index 59024e972021b..7a144e3c35000 100644 --- a/test/strings/util.jl +++ b/test/strings/util.jl @@ -297,6 +297,9 @@ end @test replace("a", in("a") => typeof) == "Char" @test replace("a", ['a'] => typeof) == "Char" + # Issue 36953 + @test replace("abc", "" => "_", count=1) == "_abc" + end @testset "chomp/chop" begin diff --git a/test/subtype.jl b/test/subtype.jl index d528a2230fca9..11589afdf1271 100644 --- a/test/subtype.jl +++ b/test/subtype.jl @@ -1757,3 +1757,10 @@ s26065 = Ref{Tuple{T,Ref{Union{Ref{Tuple{Ref{Union{Ref{Ref{Tuple{Ref{Tuple{Union # issue 36100 @test NamedTuple{(:a, :b), Tuple{Missing, Union{}}} == NamedTuple{(:a, :b), Tuple{Missing, Union{}}} @test Val{Tuple{Missing, Union{}}} === Val{Tuple{Missing, Union{}}} + +# issue #36869 +struct F36869{T, V} <: AbstractArray{Union{T, V}, 1} +end +@testintersect(Tuple{Type{T}, AbstractVector{T}} where T, + Tuple{Union, F36869{Int64, Missing}}, + Tuple{Union, F36869{Int64, Missing}})