diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index db900cf805..e220f42d19 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -227,7 +227,7 @@ PMP::pmpcfg_from_index(uint32_t pmp_index){
     int xlen =64;
     assert(pmp_index <16);
     int cfgPerCSR = xlen / 8;
-    int cfg_csr_addr;
+    int cfg_csr_addr = 0;
     switch (pmp_index / cfgPerCSR) {
         case 0:
             cfg_csr_addr = 0;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7cdf9c0b8a..192892776c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1254,7 +1254,7 @@ CPU::instDone(ThreadID tid, const DynInstPtr &inst)
         if (this->nextDumpInstCount
                 && totalInsts() == this->nextDumpInstCount) {
             fprintf(stderr, "Will trigger stat dump and reset\n");
-            Stats::schedStatEvent(true, true, curTick(), 0);
+            statistics::schedStatEvent(true, true, curTick(), 0);
             scheduleInstStop(tid,0,"Will trigger stat dump and reset");
 
             /*if (this->repeatDumpInstCount) {
@@ -1267,7 +1267,7 @@ CPU::instDone(ThreadID tid, const DynInstPtr &inst)
 
         if (this->warmupInstCount && totalInsts() == this->warmupInstCount) {
             fprintf(stderr, "Will trigger stat dump and reset\n");
-            Stats::schedStatEvent(true, true, curTick(), 0);
+            statistics::schedStatEvent(true, true, curTick(), 0);
             scheduleInstStop(tid,0,"Will trigger stat dump and reset");
         }
     }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index d0779ea5a0..5bee40588d 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1049,16 +1049,16 @@ class DynInst : public ExecContext, public RefCounted
             bool set = vecinst->vmi.rs < RiscvISA::vtype_VLMAX(vecinst->machInst.vtype8);
             bool eleFullCover = vecinst->vmi.re <= vl;
             bool oldVdElim = set && ((vl > 0 && vecinst->vma && vecinst->vta) || (vecinst->vma && eleFullCover));
-            DPRINTF(Schedule, "[sn %llu] vl: %llu, rs: %llu, re: %llu, set: %d, eleFullCover: %d, oldVdElim: %d\n",
+            DPRINTF(Schedule, "[sn:%llu] vl: %llu, rs: %llu, re: %llu, set: %d, eleFullCover: %d, oldVdElim: %d\n",
                     seqNum, vl, vecinst->vmi.rs, vecinst->vmi.re, set, eleFullCover, oldVdElim);
             if (oldVdElim) {
-                DPRINTF(Schedule, "[sn %llu] old vd elim\n", seqNum);
+                DPRINTF(Schedule, "[sn:%llu] old vd elim\n", seqNum);
                 renameSrcReg(vecinst->oldDstIdx, cpu->vecOnesPhysRegId);
                 if (!readySrcIdx(vecinst->oldDstIdx)) {
                     markSrcRegReady(vecinst->oldDstIdx);
                 }
             } else {
-                DPRINTF(Schedule, "[sn %llu] assert failed\n", seqNum);
+                DPRINTF(Schedule, "[sn:%llu] assert failed\n", seqNum);
                 assert(srcRegIdx(vecinst->oldDstIdx) != RiscvISA::VecOnesReg);
             }
             return oldVdElim;
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index cf05392649..3dd97b8e05 100644
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -1464,7 +1464,7 @@ IEW::executeInsts()
 
         updateExeInstStats(inst);
 
-        if (Debug::IEW) {
+        if (debug::IEW) {
             inst->printDisassemblyAndResult(cpu->name());
         }
 
diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index afbf7a0da8..f5834a539e 100644
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -522,7 +522,10 @@ bool
 InstructionQueue::execLatencyCheck(const DynInstPtr& inst, uint32_t& op_latency)
 {
     // Leading zero count
-    auto lzc = [](RegVal val) {
+    auto clz = [](RegVal val) {
+#if defined(__GNUC__) || defined(__clang__)
+        return val == 0 ? 64 : __builtin_clzll(val);
+#else
         for (int i = 0; i < 64; i++) {
             if (val & (0x1lu << 63)) {
                 return i;
@@ -530,7 +533,10 @@ InstructionQueue::execLatencyCheck(const DynInstPtr& inst, uint32_t& op_latency)
             val <<= 1;
         }
         return 64;
+#endif
     };
+
+
     RegVal rs1;
     RegVal rs2;
     int delay_;
@@ -542,14 +548,14 @@ InstructionQueue::execLatencyCheck(const DynInstPtr& inst, uint32_t& op_latency)
                                       inst->threadNumber);
             // rs1 / rs2 : 0x80/0x8 ,delay_ = 4
             // get the leading zero difference between rs1 and rs2 (rs1 > rs2)
-            delay_ = std::max(lzc(std::labs(rs2)) - lzc(std::labs(rs1)), 0);
+            delay_ = std::max(clz(rs2) - clz(rs1), 0);
             if (rs2 == 1) {
                 // rs1 / 1 = rs1
                 op_latency = 6;
             } else if (rs1 == rs2) {
                 // rs1 / rs2 = 1 rem 0
                 op_latency = 8;
-            } else if (lzc(std::labs(rs2)) - lzc(std::labs(rs1)) < 0) {
+            } else if (clz(rs2) - clz(rs1) < 0) {
                 // if rs2 > rs1 then rs1/rs2 = 0 rem rs1
                 op_latency = 6;
             } else {
@@ -689,7 +695,7 @@ InstructionQueue::scheduleReadyInsts()
         uint32_t op_latency = scheduler->getOpLatency(issued_inst);
         execLatencyCheck(issued_inst, op_latency);
         assert(op_latency < 64);
-        DPRINTF(Schedule, "[sn %lu] start execute %u cycles\n", issued_inst->seqNum, op_latency);
+        DPRINTF(Schedule, "[sn:%llu] start execute %u cycles\n", issued_inst->seqNum, op_latency);
         if (op_latency <= 1) {
             i2e_info->size++;
             instsToExecute.push_back(issued_inst);
diff --git a/src/cpu/o3/issue_queue.cc b/src/cpu/o3/issue_queue.cc
index b42b8abdc5..7763708fb1 100644
--- a/src/cpu/o3/issue_queue.cc
+++ b/src/cpu/o3/issue_queue.cc
@@ -186,7 +186,7 @@ IssueQue::checkScoreboard(const DynInstPtr& inst)
                 panic("dst is not load");
             }
             scheduler->loadCancel(dst_inst);
-            DPRINTF(Schedule, "[sn %lu] %s can't get data from bypassNetwork, dst inst: %s\n",
+            DPRINTF(Schedule, "[sn:%llu] %s can't get data from bypassNetwork, dst inst: %s\n",
                     inst->seqNum, inst->srcRegIdx(i), dst_inst->genDisassembly());
             return false;
         }
@@ -199,7 +199,7 @@ void
 IssueQue::addToFu(const DynInstPtr& inst)
 {
     if (inst->isIssued()) [[unlikely]] {
-        panic("%s [sn %lu] has alreayd been issued\n", enums::OpClassStrings[inst->opClass()], inst->seqNum);
+        panic("%s [sn:%llu] has alreayd been issued\n", enums::OpClassStrings[inst->opClass()], inst->seqNum);
     }
     inst->setIssued();
     scheduler->addToFU(inst);
@@ -239,7 +239,7 @@ IssueQue::retryMem(const DynInstPtr& inst)
 {
     assert(!inst->isNonSpeculative());
     iqstats->retryMem++;
-    DPRINTF(Schedule, "retry %s [sn %lu]\n", enums::OpClassStrings[inst->opClass()], inst->seqNum);
+    DPRINTF(Schedule, "retry %s [sn:%llu]\n", enums::OpClassStrings[inst->opClass()], inst->seqNum);
     // scheduler->loadCancel(inst);
     scheduler->addToFU(inst);
 }
@@ -248,7 +248,7 @@ void
 IssueQue::markMemDepDone(const DynInstPtr& inst)
 {
     assert(inst->isMemRef());
-    DPRINTF(Schedule, "[sn %lu] has solved memdependency\n", inst->seqNum);
+    DPRINTF(Schedule, "[sn:%llu] has solved memdependency\n", inst->seqNum);
     inst->setMemDepDone();
     addIfReady(inst);
 }
@@ -265,7 +265,7 @@ IssueQue::wakeUpDependents(const DynInstPtr& inst, bool speculative)
             continue;
         }
 
-        DPRINTF(Schedule, "was %s woken by p%lu [sn %lu]\n", speculative ? "spec" : "wb", dst->flatIndex(),
+        DPRINTF(Schedule, "was %s woken by p%lu [sn:%llu]\n", speculative ? "spec" : "wb", dst->flatIndex(),
                 inst->seqNum);
         for (auto& it : subDepGraph[dst->flatIndex()]) {
             int srcIdx = it.first;
@@ -279,7 +279,7 @@ IssueQue::wakeUpDependents(const DynInstPtr& inst, bool speculative)
                 consumer->checkOldVdElim();
             }
 
-            DPRINTF(Schedule, "[sn %lu] src%d was woken\n", consumer->seqNum, srcIdx);
+            DPRINTF(Schedule, "[sn:%llu] src%d was woken\n", consumer->seqNum, srcIdx);
             addIfReady(consumer);
         }
 
@@ -308,7 +308,7 @@ IssueQue::addIfReady(const DynInstPtr& inst)
             }
         }
 
-        DPRINTF(Schedule, "[sn %lu] add to readyInstsQue\n", inst->seqNum);
+        DPRINTF(Schedule, "[sn:%llu] add to readyInstsQue\n", inst->seqNum);
         inst->clearCancel();
         if (!inst->inReadyQ()) {
             inst->setInReadyQ();
@@ -333,7 +333,7 @@ IssueQue::selectInst()
         }
         if (!readyQ->empty()) {
             auto inst = readyQ->top();
-            DPRINTF(Schedule, "[sn %ld] was selected\n", inst->seqNum);
+            DPRINTF(Schedule, "[sn:%llu] was selected\n", inst->seqNum);
             scheduler->insertSlot(inst);
             selectQ.push_back(std::make_pair(pi, inst));
             inst->clearInReadyQ();
@@ -350,15 +350,15 @@ IssueQue::scheduleInst()
         auto& pi = info.first;  // port id
         auto& inst = info.second;
         if (inst->canceled()) {
-            DPRINTF(Schedule, "[sn %ld] was canceled\n", inst->seqNum);
+            DPRINTF(Schedule, "[sn:%llu] was canceled\n", inst->seqNum);
         } else if (inst->arbFailed()) {
-            DPRINTF(Schedule, "[sn %ld] arbitration failed, retry\n", inst->seqNum);
+            DPRINTF(Schedule, "[sn:%llu] arbitration failed, retry\n", inst->seqNum);
             iqstats->arbFailed++;
             assert(inst->readyToIssue());
             inst->setInReadyQ();
             readyQclassify[inst->opClass()]->push(inst);  // retry
         } else [[likely]] {
-            DPRINTF(Schedule, "[sn %ld] no conflict, scheduled\n", inst->seqNum);
+            DPRINTF(Schedule, "[sn:%llu] no conflict, scheduled\n", inst->seqNum);
             iqstats->portissued[pi]++;
             inst->clearInIQ();
             toIssue->push(inst);
@@ -420,8 +420,8 @@ IssueQue::insert(const DynInstPtr& inst)
         instNumInsert++;
     }
 
-    DPRINTF(Schedule, "[sn %lu] %s insert into %s\n", inst->seqNum, enums::OpClassStrings[inst->opClass()], iqname);
-    DPRINTF(Schedule, "[sn %lu] instNum++\n", inst->seqNum);
+    DPRINTF(Schedule, "[sn:%llu] %s insert into %s\n", inst->seqNum, enums::OpClassStrings[inst->opClass()], iqname);
+    DPRINTF(Schedule, "[sn:%llu] instNum++\n", inst->seqNum);
     inst->issueQue = this;
     instList.emplace_back(inst);
     bool addToDepGraph = false;
@@ -431,7 +431,7 @@ IssueQue::insert(const DynInstPtr& inst)
             if (scheduler->scoreboard[src->flatIndex()] || scheduler->earlyScoreboard[src->flatIndex()]) {
                 inst->markSrcRegReady(i);
             } else {
-                DPRINTF(Schedule, "[sn %lu] src p%d add to depGraph\n", inst->seqNum, src->flatIndex());
+                DPRINTF(Schedule, "[sn:%llu] src p%d add to depGraph\n", inst->seqNum, src->flatIndex());
                 subDepGraph[src->flatIndex()].push_back({i, inst});
                 addToDepGraph = true;
             }
@@ -455,7 +455,7 @@ IssueQue::insert(const DynInstPtr& inst)
 void
 IssueQue::insertNonSpec(const DynInstPtr& inst)
 {
-    DPRINTF(Schedule, "[sn %lu] insertNonSpec into %s\n", inst->seqNum, iqname);
+    DPRINTF(Schedule, "[sn:%llu] insertNonSpec into %s\n", inst->seqNum, iqname);
     inst->issueQue = this;
     if (inst->isMemRef()) {
         scheduler->memDepUnit[inst->threadNumber].insertNonSpec(inst);
@@ -639,7 +639,7 @@ Scheduler::resetDepGraph(uint64_t numPhysRegs)
 void
 Scheduler::addToFU(const DynInstPtr& inst)
 {
-    DPRINTF(Schedule, "%s [sn %lu] add to FUs\n", enums::OpClassStrings[inst->opClass()], inst->seqNum);
+    DPRINTF(Schedule, "%s [sn:%llu] add to FUs\n", enums::OpClassStrings[inst->opClass()], inst->seqNum);
     instsToFu.push_back(inst);
 }
 
@@ -666,14 +666,14 @@ Scheduler::issueAndSelect()
         auto& slot = intSlot.top();
         slot.inst->setArbFailed();
         intSlotOccupied -= slot.resourceDemand;
-        DPRINTF(Schedule, "[sn %lu] remove from slot\n", slot.inst->seqNum);
+        DPRINTF(Schedule, "[sn:%llu] remove from slot\n", slot.inst->seqNum);
         intSlot.pop();
     }
     while (fpSlotOccupied > fpSlotNum) {
         auto& slot = fpSlot.top();
         slot.inst->setArbFailed();
         fpSlotOccupied -= slot.resourceDemand;
-        DPRINTF(Schedule, "[sn %lu] remove from slot\n", slot.inst->seqNum);
+        DPRINTF(Schedule, "[sn:%llu] remove from slot\n", slot.inst->seqNum);
         fpSlot.pop();
     }
 
@@ -731,7 +731,7 @@ Scheduler::getInstByDstReg(RegIndex flatIdx)
 void
 Scheduler::addProducer(const DynInstPtr& inst)
 {
-    DPRINTF(Schedule, "[sn %lu] addProdecer\n", inst->seqNum);
+    DPRINTF(Schedule, "[sn:%llu] addProdecer\n", inst->seqNum);
     for (int i = 0; i < inst->numDestRegs(); i++) {
         auto dst = inst->renamedDestIdx(i);
         if (dst->isFixedMapping()) {
@@ -762,7 +762,7 @@ Scheduler::insert(const DynInstPtr& inst)
     }
 
     assert(inserted);
-    DPRINTF(Dispatch, "[sn %lu] dispatch: %s\n", inst->seqNum, inst->staticInst->disassemble(0));
+    DPRINTF(Dispatch, "[sn:%llu] dispatch: %s\n", inst->seqNum, inst->staticInst->disassemble(0));
 }
 
 void
@@ -797,7 +797,7 @@ Scheduler::specWakeUpDependents(const DynInstPtr& inst, IssueQue* from_issue_que
             wakeDelay -= diff;
         }
 
-        DPRINTF(Schedule, "[sn %lu] %s create wakeupEvent to %s, delay %d cycles\n", inst->seqNum,
+        DPRINTF(Schedule, "[sn:%llu] %s create wakeupEvent to %s, delay %d cycles\n", inst->seqNum,
                 from_issue_queue->getName(), to->getName(), wakeDelay);
         if (wakeDelay == 0) {
             to->wakeUpDependents(inst, true);
@@ -844,7 +844,7 @@ Scheduler::insertSlot(const DynInstPtr& inst)
         intSlotOccupied += needed;
         intSlot.push(Slot(priority, needed, inst));
     }
-    DPRINTF(Schedule, "[sn %lu] insert slot, priority: %u, needed: %u\n", inst->seqNum, priority, needed);
+    DPRINTF(Schedule, "[sn:%llu] insert slot, priority: %u, needed: %u\n", inst->seqNum, priority, needed);
 }
 
 void
@@ -853,7 +853,7 @@ Scheduler::loadCancel(const DynInstPtr& inst)
     if (inst->canceled()) {
         return;
     }
-    DPRINTF(Schedule, "[sn %lu] %s cache miss, cancel consumers\n", inst->seqNum,
+    DPRINTF(Schedule, "[sn:%llu] %s cache miss, cancel consumers\n", inst->seqNum,
             enums::OpClassStrings[inst->opClass()]);
     inst->setCancel();
     if (inst->issueQue) {
@@ -876,7 +876,7 @@ Scheduler::loadCancel(const DynInstPtr& inst)
                     auto& depInst = it.second;
                     if (depInst->readySrcIdx(srcIdx) && depInst->renamedSrcIdx(srcIdx) != cpu->vecOnesPhysRegId) {
                         assert(!depInst->isIssued());
-                        DPRINTF(Schedule, "cancel [sn %lu], clear src p%d ready\n", depInst->seqNum,
+                        DPRINTF(Schedule, "cancel [sn:%llu], clear src p%d ready\n", depInst->seqNum,
                                 depInst->renamedSrcIdx(srcIdx)->flatIndex());
                         depInst->setCancel();
                         iq->iqstats->canceledInst++;
@@ -904,7 +904,7 @@ Scheduler::loadCancel(const DynInstPtr& inst)
 void
 Scheduler::writebackWakeup(const DynInstPtr& inst)
 {
-    DPRINTF(Schedule, "[sn %lu] was writeback\n", inst->seqNum);
+    DPRINTF(Schedule, "[sn:%llu] was writeback\n", inst->seqNum);
     inst->setWriteback();  // clear in issueQue
     for (int i = 0; i < inst->numDestRegs(); i++) {
         auto dst = inst->renamedDestIdx(i);
@@ -924,7 +924,7 @@ Scheduler::bypassWriteback(const DynInstPtr& inst)
     if (inst->issueportid >= 0) {
         inst->issueQue->portBusy[inst->issueportid] = 0;
     }
-    DPRINTF(Schedule, "[sn %lu] bypass write\n", inst->seqNum);
+    DPRINTF(Schedule, "[sn:%llu] bypass write\n", inst->seqNum);
     for (int i = 0; i < inst->numDestRegs(); i++) {
         auto dst = inst->renamedDestIdx(i);
         if (dst->isFixedMapping()) {
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 1e7af2a31d..d9282374a8 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -1235,7 +1235,7 @@ LSQUnit::offloadToStoreBuffer()
             request->mainReq()->isRelease() ||
             request->mainReq()->isStrictlyOrdered() ||
             inst->isStoreConditional()) {
-            DPRINTF(StoreBuffer, "Find atomic/SC store[sn %llu]\n", storeWBIt->instruction()->seqNum);
+            DPRINTF(StoreBuffer, "Find atomic/SC store [sn:%llu]\n", storeWBIt->instruction()->seqNum);
             if (!(storeWBIt.idx() == storeQueue.head())) {
                 DPRINTF(StoreBuffer, "atomic/SC store waiting\n");
                 break;