From fbf5444d28b21e603d6e86338decbb4bd62534d8 Mon Sep 17 00:00:00 2001
From: tastynoob <934348725@qq.com>
Date: Tue, 18 Feb 2025 15:21:26 +0800
Subject: [PATCH] cpu-o3: align fcvt, fmv's latency

Change-Id: I1ff3420c72aea9df09d811f54465f67c3f2556d9
---
 src/arch/riscv/isa/decoder.isa | 12 ++++++------
 src/cpu/FuncUnit.py            |  6 +++---
 src/cpu/o3/FuncUnitConfig.py   |  3 ++-
 src/cpu/o3/issue_queue.cc      |  7 ++++++-
 src/cpu/op_class.hh            |  1 +
 5 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 14e2e66cd3..7da6c0d8c5 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2133,7 +2133,7 @@ decode QUADRANT default Unknown::unknown() {
                         if ((Rd&0x80000000) != 0) {
                             Rd |= (0xFFFFFFFFULL << 32);
                         }
-                    }}, FloatCvtOp);
+                    }}, FloatMvOp);
                     0x1: fclass_s({{
                         Rd = f32_classify(f32(freg(Fs1_bits)));
                     }}, FloatMiscOp);
@@ -2141,7 +2141,7 @@ decode QUADRANT default Unknown::unknown() {
                 0x71: decode ROUND_MODE {
                     0x0: fmv_x_d({{
                         Rd = freg(Fs1_bits).v;
-                    }}, FloatCvtOp);
+                    }}, FloatMvOp);
                     0x1: fclass_d({{
                         Rd = f64_classify(f64(freg(Fs1_bits)));
                     }}, FloatMiscOp);
@@ -2152,7 +2152,7 @@ decode QUADRANT default Unknown::unknown() {
                         if ((Rd&0x8000) != 0) {
                             Rd |= (0xFFFFFFFFFFFFULL << 16);
                         }
-                    }}, FloatCvtOp);
+                    }}, FloatMvOp);
                     0x1: fclass_h({{
                         Rd = f16_classify(f16(freg(Fs1_bits)));
                     }}, FloatMiscOp);
@@ -2163,19 +2163,19 @@ decode QUADRANT default Unknown::unknown() {
                     Fd_bits = fd.v;
                         status.fs = 3;
                         xc->setMiscReg(MISCREG_STATUS,status);
-                }}, FloatCvtOp);
+                }}, FloatMvOp);
                 0x79: fmv_d_x({{
                     freg_t fd;
                     fd = freg(f64(Rs1));
                     Fd_bits = fd.v;
                     status.fs = 3;
                     xc->setMiscReg(MISCREG_STATUS,status);
-                }}, FloatCvtOp);
+                }}, FloatMvOp);
                 0x7a: fmv_h_x({{
                     freg_t fd;
                     fd = freg(f16(Rs1_uh));
                     Fd_bits = fd.v;
-                }}, FloatCvtOp);
+                }}, FloatMvOp);
             }
         }
 
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 81e4d5e4e8..13e65f9051 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -40,9 +40,9 @@
 from m5.params import *
 
 class OpClass(Enum):
-    vals = ['No_OpClass', 'IntAlu', 'IntBr', 'IntMult', 'IntDiv', 'FloatAdd',
-            'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv',
-            'FloatMisc', 'FloatSqrt',
+    vals = ['No_OpClass', 'IntAlu', 'IntBr', 'IntMult', 'IntDiv',
+            'FloatAdd', 'FloatMult', 'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
+            'FloatCmp', 'FloatCvt', 'FloatMv','FloatMisc',
             'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
             'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
             'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu',
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index b7390f8d3c..f0c0201c10 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -87,7 +87,8 @@ class FP_ALU(FUDesc):
                OpDesc(opClass='FloatMult', opLat=4)]
 
 class FP_MISC(FUDesc):
-    opList = [ OpDesc(opClass='FloatCvt', opLat=3)]
+    opList = [ OpDesc(opClass='FloatCvt', opLat=5), # float -> int 5 cycles, int -> float 7 cycle
+               OpDesc(opClass='FloatMv', opLat=5)]
 
 class FP_MAC(FUDesc):
     opList = [ OpDesc(opClass='FMAAcc', opLat=2),
diff --git a/src/cpu/o3/issue_queue.cc b/src/cpu/o3/issue_queue.cc
index f86a029143..4e65a3b905 100644
--- a/src/cpu/o3/issue_queue.cc
+++ b/src/cpu/o3/issue_queue.cc
@@ -1097,13 +1097,18 @@ Scheduler::bypassWriteback(const DynInstPtr& inst)
 uint32_t
 Scheduler::getOpLatency(const DynInstPtr& inst)
 {
+    if (inst->opClass() == FloatCvtOp) [[unlikely]] {
+        if (inst->destRegIdx(0).isFloatReg()) {
+            return 2 + opExecTimeTable[inst->opClass()];
+        }
+    }
     return opExecTimeTable[inst->opClass()];
 }
 
 uint32_t
 Scheduler::getCorrectedOpLat(const DynInstPtr& inst)
 {
-    uint32_t oplat = opExecTimeTable[inst->opClass()];
+    uint32_t oplat = getOpLatency(inst);
     oplat += inst->isLoad() ? 2 : 0;
     return oplat;
 }
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 161082d6b1..1dfdebbcfa 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -60,6 +60,7 @@ static const OpClass IntDivOp = enums::IntDiv;
 static const OpClass FloatAddOp = enums::FloatAdd;
 static const OpClass FloatCmpOp = enums::FloatCmp;
 static const OpClass FloatCvtOp = enums::FloatCvt;
+static const OpClass FloatMvOp = enums::FloatMv;
 static const OpClass FloatMultOp = enums::FloatMult;
 static const OpClass FloatMultAccOp = enums::FloatMultAcc;
 static const OpClass FloatDivOp = enums::FloatDiv;