From 056dc040a34ec02c27b3f82d952ed86b5f4d4782 Mon Sep 17 00:00:00 2001
From: tastynoob <934348725@qq.com>
Date: Wed, 26 Feb 2025 16:02:00 +0800
Subject: [PATCH] mem: l2 cache use drrip replacement

Change-Id: I3b208d4796352cfb3b6519865d1f789aa111ff7c
---
 configs/common/Caches.py | 2 ++
 src/mem/cache/cache.cc   | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 34c52e3fd3..17b8abacaf 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -103,6 +103,8 @@ class L2Cache(Cache):
     # recvTimingResp serviceMSHR latency
     response_latency = 0
 
+    replacement_policy = DRRIPRP(constituency_size = 64, team_size = 8)
+
     cache_level = 2
     enable_wayprediction = False
 
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 2735864e48..78a633c2b4 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -814,7 +814,7 @@ Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)
                     .missLatency[tgt_pkt->req->requestorId()] +=
                     completion_time - target.recvTime;
                 stats.cmdStats(tgt_pkt)
-                    .missLatencyDist.sample((completion_time - target.recvTime)/500);
+                    .missLatencyDist.sample(ticksToCycles(completion_time - target.recvTime));
 
                 if (tgt_pkt->cmd == MemCmd::LockedRMWReadReq) {
                     // We're going to leave a target in the MSHR until the