Inconsistent values ​​of mip registers

[fly-1011]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

Describe

Use riscv64-spike-so as the reference model to test Xiangshan, set the 13th bit (LCOFI) in the hvip register to 1, and the 13th bit in the reference model mip register is also set to 1, but Xiangshan does not.

This is the test programtest.zip The following is a screenshot of the log information：

And after testing, when VSSIP, VSTIP, and VSEIP in hvip are set to 1, the corresponding fields in mip will also be set to 1

Environment：

xiangshan:commit 7d20eb3
ready-to-run:commit 567138c30ae3b5987124342303753151541ee96c

[NewPaulWalker]

It seems that writing a 1 to the 13th bit of hvip causes the 13th bit of mip in Spike to also become 1. I believe hvip.LCOFI is not an alias of mip.LCOFI (as we haven’t seen such a description in the manual; if you know of any related information, please let us know). Therefore, this might be a bug in Spike. I have submitted a PR to the upstream to check whether this is indeed an issue and if it can be fixed.
riscv-software-src/riscv-isa-sim#1869

[fly-1011]

@NewPaulWalker 😄 Thank you very much for your response and for submitting the PR. I apologize for the delayed reply.

As you mentioned, I also did not find in the manual that hvip.LCOFI is an alias of mip.LCOFI. However, I found the following information in the manual:

VSSIP in hip is an alias (writable) of the same bit in hvip.
Bits SGEIP, VSEIP, VSTIP, and VSSIP in mip are aliases for the same bits in hypervisor CSR hip, while SGEIE, VSEIE, VSTIE, and VSSIE in mie are aliases for the same bits in hie

This suggests that hvip.VSSIP is an alias of mip.VSSIP.

Additionally, when I set VSEIP, VSTIP, and VSSIP in hvip to 1, the corresponding fields in the mip register in both Xiangshan and Spike are also set to 1, as shown in the attached log screenshot below:

[NewPaulWalker]

Thank you for the information.

It seems that the read value of CSR mip should depend on hvip.VSTIP and hvip.VSEIP.

Since hvip.VSSIP is an alias of mip.VSSIP, we don't need to retrieve the value of VSSIP from hvip when reading mip.VSSIP.

Moreover, since hvip.LCOFI is not an alias of mip.LCOFI, its value should not be OR-ed into mip when reading.