diff --git a/boards/arm/quick_feather/Kconfig.defconfig b/boards/arm/quick_feather/Kconfig.defconfig index 2d8fb8646746c0..4447235702eeaa 100644 --- a/boards/arm/quick_feather/Kconfig.defconfig +++ b/boards/arm/quick_feather/Kconfig.defconfig @@ -11,6 +11,10 @@ config BOARD if PWM config PWM_LITEX + select SOC_EOS_S3_FPGA + default n + +config EOS_S3_PWM select EOS_S3_PROGRAM_FPGA default y diff --git a/boards/arm/quick_feather/board.c b/boards/arm/quick_feather/board.c index a0ac48697afda5..87572a802df831 100644 --- a/boards/arm/quick_feather/board.c +++ b/boards/arm/quick_feather/board.c @@ -25,7 +25,7 @@ static int eos_s3_board_init(struct device *arg) eos_s3_io_mux(SPI_SS1_PAD, SPI_SS1_PAD_CFG); #endif -#ifdef CONFIG_PWM_LITEX +#if defined CONFIG_PWM_LITEX || CONFIG_EOS_S3_PWM eos_s3_io_mux(PWM0_PAD, PWM0_PAD_CFG); eos_s3_io_mux(PWM1_PAD, PWM1_PAD_CFG); eos_s3_io_mux(PWM2_PAD, PWM2_PAD_CFG); diff --git a/boards/arm/quick_feather/board.h b/boards/arm/quick_feather/board.h index 8801844619405e..f09c50ca9822dd 100644 --- a/boards/arm/quick_feather/board.h +++ b/boards/arm/quick_feather/board.h @@ -28,7 +28,7 @@ #define SPI_SS1_PAD_CFG SPI_SS1_PAD39 #endif /* CONFIG_SPI_EOS_S3 */ -#ifdef CONFIG_PWM_LITEX +#if defined CONFIG_PWM_LITEX || CONFIG_EOS_S3_PWM /* FPGA IP core peripherals */ #define DT_PWM_GEN_EOS_S3_BASE_ADDRESS DT_QUICKLOGIC_EOS_S3_PWM_GEN_40020000_BASE_ADDRESS #define DT_PWM_GEN_EOS_S3_DIVIDER DT_QUICKLOGIC_EOS_S3_PWM_GEN_40020000_DIVIDER diff --git a/drivers/led/CMakeLists.txt b/drivers/led/CMakeLists.txt index ca3ae51789bee4..4b46a382a8d193 100644 --- a/drivers/led/CMakeLists.txt +++ b/drivers/led/CMakeLists.txt @@ -4,6 +4,6 @@ zephyr_sources_ifdef(CONFIG_HT16K33 ht16k33.c) zephyr_sources_ifdef(CONFIG_LP3943 lp3943.c) zephyr_sources_ifdef(CONFIG_LP5562 lp5562.c) zephyr_sources_ifdef(CONFIG_PCA9633 pca9633.c) -zephyr_sources_ifdef(CONFIG_EOS_S3_LED1 led_eos_s3_1.c) +zephyr_sources_ifdef(CONFIG_EOS_S3_LED_BASIC led_eos_s3_basic.c) zephyr_sources_ifdef(CONFIG_USERSPACE led_handlers.c) diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 1e6f483b4539da..823174b5b79df3 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -24,6 +24,6 @@ source "drivers/led/Kconfig.ht16k33" source "drivers/led/Kconfig.lp3943" source "drivers/led/Kconfig.lp5562" source "drivers/led/Kconfig.pca9633" -source "drivers/led/Kconfig.eos_s3_1" +source "drivers/led/Kconfig.eos_s3_basic" endif # LED diff --git a/drivers/led/Kconfig.eos_s3_1 b/drivers/led/Kconfig.eos_s3_1 deleted file mode 100644 index 9b4bd3caac9450..00000000000000 --- a/drivers/led/Kconfig.eos_s3_1 +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2018 Workaround GmbH -# SPDX-License-Identifier: Apache-2.0 - -config EOS_S3_LED1 - bool "EOS S3 LED driver 1" - help - Enable LED driver 1 for QL S3. - diff --git a/drivers/led/Kconfig.eos_s3_basic b/drivers/led/Kconfig.eos_s3_basic new file mode 100644 index 00000000000000..0e85d26623fdb1 --- /dev/null +++ b/drivers/led/Kconfig.eos_s3_basic @@ -0,0 +1,8 @@ +# Copyright 2020 QuickLogic +# Licensed under the Apache License, Version 2.0 + +config EOS_S3_LED_BASIC + bool "EOS S3 basic LED driver" + help + Enable basic LED driver for QL S3. + diff --git a/drivers/led/eos_s3_led1_ip.h b/drivers/led/eos_s3_led_basic_ip.h similarity index 100% rename from drivers/led/eos_s3_led1_ip.h rename to drivers/led/eos_s3_led_basic_ip.h diff --git a/drivers/led/led_eos_s3_1.c b/drivers/led/led_eos_s3_basic.c similarity index 58% rename from drivers/led/led_eos_s3_1.c rename to drivers/led/led_eos_s3_basic.c index 4482674e4c1f79..9ea694f9144fe9 100644 --- a/drivers/led/led_eos_s3_1.c +++ b/drivers/led/led_eos_s3_basic.c @@ -1,21 +1,21 @@ /* * ========================================================== * - * Copyright (C) 2020 QuickLogic Corporation + * Copyright (C) 2020 QuickLogic Corporation * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * - * File : led_eos_s3_1.c - * Purpose : This is the driver for LED controller IP. - * - * + * File : led_eos_s3_basic.c + * Purpose : This is the driver for basic LED controller IP. + * + * * =========================================================== * */ @@ -23,27 +23,27 @@ #include #include #include -#include "eos_s3_led1_ip.h" +#include "eos_s3_led_basic_ip.h" #include "eos_s3_led_config.h" -static void config_ios() +static void config_ios(void) { eos_s3_io_mux(FPGA_LED0_PAD, FPGA_LED0_PAD_CFG); eos_s3_io_mux(FPGA_LED1_PAD, FPGA_LED1_PAD_CFG); eos_s3_io_mux(FPGA_LED2_PAD, FPGA_LED2_PAD_CFG); - eos_s3_fbio_select(FPGA_LED0_PAD,FPGA_LED0_FBIO_SEL); - eos_s3_fbio_select(FPGA_LED1_PAD,FPGA_LED1_FBIO_SEL); - eos_s3_fbio_select(FPGA_LED2_PAD,FPGA_LED2_FBIO_SEL); - + eos_s3_fbio_select(FPGA_LED0_PAD, FPGA_LED0_FBIO_SEL); + eos_s3_fbio_select(FPGA_LED1_PAD, FPGA_LED1_FBIO_SEL); + eos_s3_fbio_select(FPGA_LED2_PAD, FPGA_LED2_FBIO_SEL); + } -void program_fpga_ip() +void program_fpga_ip(void) { - // Load bitstrem into FPGA - load_fpga(sizeof(axFPGABitStream),axFPGABitStream); + /* Load bitstrem into FPGA */ + load_fpga(sizeof(axFPGABitStream), axFPGABitStream); - // Configure IOs + /* Configure IOs */ config_ios(); } diff --git a/drivers/pwm/CMakeLists.txt b/drivers/pwm/CMakeLists.txt index 3766d1474874d1..69bd40d6fa1447 100644 --- a/drivers/pwm/CMakeLists.txt +++ b/drivers/pwm/CMakeLists.txt @@ -15,7 +15,8 @@ zephyr_library_sources_ifdef(CONFIG_PWM_SAM pwm_sam.c) zephyr_library_sources_ifdef(CONFIG_PWM_MCUX pwm_mcux.c) zephyr_library_sources_ifdef(CONFIG_PWM_XEC pwm_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_PWM_LITEX pwm_litex.c) -zephyr_library_sources_ifdef(CONFIG_PWM_LITEX pwm_eos_s3.c) +zephyr_library_sources_ifdef(CONFIG_EOS_S3_PWM pwm_litex.c) +zephyr_library_sources_ifdef(CONFIG_EOS_S3_PWM pwm_eos_s3.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c) zephyr_library_sources_ifdef(CONFIG_PWM_SHELL pwm_shell.c) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index c25c3702dba80a..62795d292fcfe1 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -61,4 +61,6 @@ source "drivers/pwm/Kconfig.xec" source "drivers/pwm/Kconfig.litex" +source "drivers/pwm/Kconfig.eos_s3" + endif # PWM diff --git a/drivers/pwm/Kconfig.eos_s3 b/drivers/pwm/Kconfig.eos_s3 new file mode 100644 index 00000000000000..56c53ae07aad7a --- /dev/null +++ b/drivers/pwm/Kconfig.eos_s3 @@ -0,0 +1,18 @@ +# Copyright 2020 QuickLogic +# Licensed under the Apache License, Version 2.0 + +menuconfig EOS_S3_PWM + bool "EOS S3 LiteX PWM driver" + depends on HAS_DTS + help + Set if PWM IP generated with EOS S3 tools + +if EOS_S3_PWM + +config PWM_LITEX_INIT_PRIORITY + int "Init priority" + default 70 + help + PWM device driver initialization priority. + +endif # PWM_LITEX diff --git a/drivers/pwm/pwm_eos_s3.c b/drivers/pwm/pwm_eos_s3.c index e99b22d983ec5e..4e832aaae30172 100644 --- a/drivers/pwm/pwm_eos_s3.c +++ b/drivers/pwm/pwm_eos_s3.c @@ -1,11 +1,11 @@ /* * ========================================================== * - * Copyright (C) 2020 QuickLogic Corporation + * Copyright (C) 2020 QuickLogic Corporation * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -14,10 +14,9 @@ * * File : pwm_eos_s3.c * Purpose : This file has the function to load pwm fpga ip - * - * - * =========================================================== * + * + * =========================================================== */ #include @@ -25,9 +24,9 @@ #include #include "eos_s3_pwm_ip.h" -void program_fpga_ip() +void program_fpga_ip(void) { - // Load bitstrem into FPGA - load_fpga(sizeof(axFPGABitStream),axFPGABitStream); + /* Load bitstrem into FPGA */ + load_fpga(sizeof(axFPGABitStream), axFPGABitStream); } diff --git a/samples/drivers/led_eos_s3_1/sample.yaml b/samples/drivers/led_eos_s3_1/sample.yaml deleted file mode 100644 index 8654aba4cb07ee..00000000000000 --- a/samples/drivers/led_eos_s3_1/sample.yaml +++ /dev/null @@ -1,8 +0,0 @@ -sample: - description: Demonstration of the eos_s3_1 LED driver - name: led_eos_s3_1 sample -tests: - sample.drivers.led.eos_s3_1: - platform_whitelist: quick_feather - tags: led - harness: TBD diff --git a/samples/drivers/led_eos_s3_1/src/main.c b/samples/drivers/led_eos_s3_1/src/main.c deleted file mode 100644 index d30936e696502a..00000000000000 --- a/samples/drivers/led_eos_s3_1/src/main.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -void main(void) -{ - printk("\n\n"); - printk( "##########################\n"); - printk( "Quicklogic Open Platform 2.0\n"); - printk( "SW Version: "); - printk("OP2-QuickFeather-led-eos-s3-sample1"); - printk( "\n" ); - printk( __DATE__ " " __TIME__ "\n" ); - printk( "##########################\n\n"); - - while (1); -} diff --git a/samples/drivers/led_eos_s3_1/CMakeLists.txt b/samples/drivers/led_eos_s3_basic/CMakeLists.txt similarity index 64% rename from samples/drivers/led_eos_s3_1/CMakeLists.txt rename to samples/drivers/led_eos_s3_basic/CMakeLists.txt index c6db3944364c03..3baac6bff034fb 100644 --- a/samples/drivers/led_eos_s3_1/CMakeLists.txt +++ b/samples/drivers/led_eos_s3_basic/CMakeLists.txt @@ -1,8 +1,9 @@ -# SPDX-License-Identifier: Apache-2.0 +# Copyright (C) 2020 QuickLogic Corporation +# Licensed under the Apache License, Version 2.0 cmake_minimum_required(VERSION 3.13.1) include($ENV{ZEPHYR_BASE}/cmake/app/boilerplate.cmake NO_POLICY_SCOPE) -project(led_eos_s3_1) +project(led_eos_s3_basic) FILE(GLOB app_sources src/*.c) target_sources(app PRIVATE ${app_sources}) diff --git a/samples/drivers/led_eos_s3_1/README.rst b/samples/drivers/led_eos_s3_basic/README.rst similarity index 80% rename from samples/drivers/led_eos_s3_1/README.rst rename to samples/drivers/led_eos_s3_basic/README.rst index c510c83042708b..87137ee030a64e 100644 --- a/samples/drivers/led_eos_s3_1/README.rst +++ b/samples/drivers/led_eos_s3_basic/README.rst @@ -1,12 +1,12 @@ -.. _eos_s3_1: +.. _eos_s3_basic: -EOS_S3_1: Preconfigured LED +EOS_S3_BASIC: Preconfigured LED ########################### Overview ******** -This sample blinks the LEDs which is preconfigured in the FPGA IP: +This sample blinks the LEDs which is preconfigured in the FPGA IP Building and Running @@ -15,7 +15,7 @@ Building and Running Build the application for the :ref:`quick_feather` board. .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_eos_s3_1 + :zephyr-app: samples/drivers/led_eos_s3_basic :board: quick_feather :goals: build :compact: diff --git a/samples/drivers/led_eos_s3_1/prj.conf b/samples/drivers/led_eos_s3_basic/prj.conf similarity index 100% rename from samples/drivers/led_eos_s3_1/prj.conf rename to samples/drivers/led_eos_s3_basic/prj.conf diff --git a/samples/drivers/led_eos_s3_basic/sample.yaml b/samples/drivers/led_eos_s3_basic/sample.yaml new file mode 100644 index 00000000000000..3d2e4da738eef2 --- /dev/null +++ b/samples/drivers/led_eos_s3_basic/sample.yaml @@ -0,0 +1,8 @@ +sample: + description: Demonstration of the eos_s3 basic LED driver + name: led_eos_s3_basic sample +tests: + sample.drivers.led.eos_s3_basic: + platform_whitelist: quick_feather + tags: led + harness: TBD diff --git a/samples/drivers/led_eos_s3_basic/src/main.c b/samples/drivers/led_eos_s3_basic/src/main.c new file mode 100644 index 00000000000000..50762450aa9a19 --- /dev/null +++ b/samples/drivers/led_eos_s3_basic/src/main.c @@ -0,0 +1,36 @@ +/* + * ========================================================== + * + * Copyright (C) 2020 QuickLogic Corporation + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * File : main.c + * Purpose : This file has simple prints. + * No other configuration needs to be done here + * + * =========================================================== + */ + +#include +#include +#include + +void main(void) +{ + printk("\n\n"); + printk("##########################\n"); + printk("Quicklogic Open Platform 2.0\n"); + printk("SW Version: "); + printk(" OP2-QuickFeather-led-eos-s3-basic sample"); + printk("\n"); + printk(__DATE__ " " __TIME__ "\n"); + printk("##########################\n\n"); +} diff --git a/samples/drivers/spi_flash/src/main.c b/samples/drivers/spi_flash/src/main.c old mode 100644 new mode 100755 index 1cf53f47cf8bfb..149fe93807eb75 --- a/samples/drivers/spi_flash/src/main.c +++ b/samples/drivers/spi_flash/src/main.c @@ -21,7 +21,7 @@ #error Unsupported flash driver #endif -#define FLASH_TEST_REGION_OFFSET 0xff000 +#define FLASH_TEST_REGION_OFFSET 0x100000 #define FLASH_SECTOR_SIZE 4096 void main(void) @@ -68,6 +68,8 @@ void main(void) printf("Flash write failed! %d\n", rc); return; } + // Sleep for a while + k_sleep(100); //in ms memset(buf, 0, len); rc = flash_read(flash_dev, FLASH_TEST_REGION_OFFSET, buf, len); diff --git a/soc/arm/quicklogic_eos_s3/CMakeLists.txt b/soc/arm/quicklogic_eos_s3/CMakeLists.txt index 2fbf9907ba6b1d..847db868766746 100644 --- a/soc/arm/quicklogic_eos_s3/CMakeLists.txt +++ b/soc/arm/quicklogic_eos_s3/CMakeLists.txt @@ -5,5 +5,6 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers) zephyr_sources( soc.c irq_handlers.c - fpga_loader.c ) +zephyr_sources_ifdef(CONFIG_EOS_S3_PROGRAM_FPGA fpga_loader.c) + diff --git a/soc/arm/quicklogic_eos_s3/Kconfig.defconfig b/soc/arm/quicklogic_eos_s3/Kconfig.defconfig index ca8c175a3a8132..44598d10230a98 100644 --- a/soc/arm/quicklogic_eos_s3/Kconfig.defconfig +++ b/soc/arm/quicklogic_eos_s3/Kconfig.defconfig @@ -58,7 +58,7 @@ config SPI_EOS_S3 endif # SPI if LED -config EOS_S3_LED1 +config EOS_S3_LED_BASIC select EOS_S3_PROGRAM_FPGA default y endif # LED diff --git a/soc/arm/quicklogic_eos_s3/fpga_loader.c b/soc/arm/quicklogic_eos_s3/fpga_loader.c index b3d837e826274a..04f9d513878da1 100755 --- a/soc/arm/quicklogic_eos_s3/fpga_loader.c +++ b/soc/arm/quicklogic_eos_s3/fpga_loader.c @@ -1,153 +1,92 @@ -/*========================================================== -* -* Copyright 2020 QuickLogic -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -* -* File : fpga_loader.c -* Purpose: Contains functionality to load FPGA -* -*=========================================================*/ - -#include -#include -#include - - -#define REG1 (*(volatile uint32_t *)(0x40004610)) -#define REG2 (*(volatile uint32_t *)(0x40004044)) -#define REG3 (*(volatile uint32_t *)(0x4000404C)) -#define REG4 (*(volatile uint32_t *)(0x40004064)) - -#define REG5 (*(volatile uint32_t *)(0x40004070)) -#define REG6 (*(volatile uint32_t *)(0x4000411C)) -#define REG7 (*(volatile uint32_t *)(0x40004054)) -#define REG8 (*(volatile uint32_t *)(0x400047F8)) - -#define REG9 (*(volatile uint32_t *)(0x40014000)) - -#define REG10 (*(volatile uint32_t *)(0x400047F0)) -#define REG11 (*(volatile uint32_t *)(0x400047F4)) -#define REG12 (*(volatile uint32_t *)(0x40004088)) -#define REG13 (*(volatile uint32_t *)(0x40004094)) -#define REG14 (*(volatile uint32_t *)(0x400047F8)) -#define REG15 (*(volatile uint32_t *)(0x40004040)) -#define REG16 (*(volatile uint32_t *)(0x40004048)) -#define REG17 (*(volatile uint32_t *)(0x4000404C)) - -#define CFG_CTL_CFG_DATA (*(volatile uint32_t *)(0x40014FFC)) -#define CFG_CTL_CFG_CTL (*(volatile uint32_t *)(0x40014000)) - -static void enable_clocks() -{ - PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_PF_WU - | PMU_FFE_FB_PF_SW_WU_FB_WU - | PMU_FFE_FB_PF_SW_WU_FFE_WU; - CRU->FB_SW_RESET = FB_C21_DOMAIN_SW_RESET | FB_C16_DOMAIN_SW_RESET - | FB_C09_DOMAIN_SW_RESET | FB_C02_DOMAIN_SW_RESET; - - CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_0_ON | C02_CLK_GATE_PATH_1_ON - | C02_CLK_GATE_PATH_2_ON; - - CRU->C08_X1_CLK_GATE = C08_X1_CLK_GATE_PATH_1_ON - | C08_X1_CLK_GATE_PATH_2_ON; - - CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON; - - CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON; - - CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_ON | C09_CLK_GATE_PATH_2_ON; -} - -/************************************************************* - * - * Load FPGA from in memory description - * - *************************************************************/ - -int load_fpga(uint32_t img_size,uint32_t* image_ptr) -{ - unsigned int i = 0; - uint32_t chunk_cnt=0; - volatile uint32_t *gFPGAPtr = (volatile uint32_t*)image_ptr; - - *((volatile unsigned int*) 0x40004c4c) = 0x00000180; - - enable_clocks(); - - // Configuration of CFG_CTRL for writes - CFG_CTL_CFG_CTL = 0x0000bdff ; - // wait some time for fpga to get reset pulse - for (i=0;i<50; i++) { - PMU->GEN_PURPOSE_1 = i << 4; - } - - REG8 = 0x10; - REG8 = 0x20; - REG8 = 0x30; - REG8 = 0x40; - REG8 = 0x50; - REG8 = 0x60; - REG8 = 0x70; - REG8 = 0x80; - - REG9 = 0xBDFF; - - REG8 = 0x10; - REG8 = 0x20; - REG8 = 0x30; - REG8 = 0x40; - REG8 = 0x50; - REG8 = 0x60; - REG8 = 0x70; - REG8 = 0x80; - - - for(chunk_cnt=0;chunk_cnt<(img_size/4);chunk_cnt++) - CFG_CTL_CFG_DATA = gFPGAPtr[chunk_cnt]; - - // wait some time for fpga to get reset pulse - for (i=0;i<50; i++) { - PMU->GEN_PURPOSE_1 = i << 4; - } - - CFG_CTL_CFG_CTL = 0x0; // exit config mode - REG10 = 0; - - - REG11 = 0; - - - - REG12 = 0; - REG13 = 0; - REG14 = 0x90; - - - PMU->GEN_PURPOSE_0 = 0x0; //set APB_FB_EN = 0 for normal mode - - // required wait time before releasing LTH_ENB - for (i=0;i<500; i++) { - PMU->GEN_PURPOSE_1 = i << 4; - } - - //release isolation - LTH_ENB - PMU->FB_ISOLATION = 0x0; - *((volatile unsigned int*) 0x40004c4c) = 0x000009a0; - - printf("FPGA is programmed\r\n"); - - return 1; - -} +/* + * ========================================================== + * + * Copyright 2020 QuickLogic + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * File : fpga_loader.c + * Purpose: Contains functionality to load FPGA + * + *========================================================= + */ + + +#include +#include + +#define CFG_CTL_CFG_DATA (*(volatile u32_t *)(0x40014FFC)) +#define CFG_CTL_CFG_CTL (*(volatile u32_t *)(0x40014000)) + + +int load_fpga(u32_t img_size, u32_t *image_ptr) +{ + unsigned int i = 0; + u32_t chunk_cnt = 0; + volatile u32_t *gFPGAPtr = (volatile u32_t *)image_ptr; + + IO_MUX->PAD_19_CTRL = 0x00000180; + + enable_fpga_clocks(); + + /* wait some time for fpga to get reset pulse */ +#if 0 + k_sleep(100); +#else + for (i = 0; i < 60; i++) + PMU->GEN_PURPOSE_1 = i << 4; +#endif + + /* Configuration of CFG_CTRL for writes */ + CFG_CTL_CFG_CTL = 0xBDFF; + +#if 0 + k_sleep(100); +#else + for (i = 0; i < 60; i++) + PMU->GEN_PURPOSE_1 = i << 4; +#endif + + for (chunk_cnt = 0; chunk_cnt < (img_size/4); chunk_cnt++) + CFG_CTL_CFG_DATA = gFPGAPtr[chunk_cnt]; + + /* wait some time for fpga to get reset pulse */ +#if 0 + k_sleep(100); +#else + for (i = 0; i < 60; i++) + PMU->GEN_PURPOSE_1 = i << 4; +#endif + + /* exit config mode */ + CFG_CTL_CFG_CTL = 0x0; + PMU->GEN_PURPOSE_0 = 0; /* set APB_FB_EN = 0 for normal mode */ + + PMU->FB_ISOLATION = 0; + + CRU->FB_SW_RESET = 0; + CRU->FB_MISC_SW_RST_CTL = 0; + PMU->GEN_PURPOSE_1 = 0x90; + + /* required wait time before releasing LTH_ENB */ +#if 0 + k_sleep(100); +#else + for (i = 0; i < 60; i++) + PMU->GEN_PURPOSE_1 = i << 4; +#endif + IO_MUX->PAD_19_CTRL = 0x000009a0; + + return 0; +} diff --git a/soc/arm/quicklogic_eos_s3/fpga_loader.h b/soc/arm/quicklogic_eos_s3/fpga_loader.h index 24c27802640add..01b3526fcba414 100755 --- a/soc/arm/quicklogic_eos_s3/fpga_loader.h +++ b/soc/arm/quicklogic_eos_s3/fpga_loader.h @@ -1,23 +1,24 @@ -/*========================================================== -* -* Copyright 2020 QuickLogic -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -* -* File : fpga_loader.h -* Purpose: Contains functionality to load FPGA -* -*=========================================================*/ - -extern int load_fpga(uint32_t img_size,uint32_t* image_ptr); \ No newline at end of file +/*========================================================== + * + * Copyright 2020 QuickLogic + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * File : fpga_loader.h + * Purpose: Contains functionality to load FPGA + * + *========================================================= + */ + +int load_fpga(u32_t img_size, u32_t *image_ptr); diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/arm/quicklogic_eos_s3/soc.c index 3ff476d6766bcc..4f14d9072b69d7 100644 --- a/soc/arm/quicklogic_eos_s3/soc.c +++ b/soc/arm/quicklogic_eos_s3/soc.c @@ -87,21 +87,39 @@ int eos_s3_fbio_select(u32_t pad_nr, u32_t ucFunc) uiExtRegAddr = ucFunc >> EXT_REG_OFFSET_SHIFT; - if(uiExtRegAddr == FBIO_SEL_2) - { - uiExtRegAddr = uiExtRegAddr | IO_MUX_BASE; - pExtRegAddr = (uint32_t *)uiExtRegAddr; - *pExtRegAddr |= 1 << (pad_nr - 32); - } - else - { - uiExtRegAddr |= IO_MUX_BASE; - pExtRegAddr = (uint32_t *)uiExtRegAddr; - *pExtRegAddr |= 1 << pad_nr; - } + if (uiExtRegAddr == FBIO_SEL_2) { + uiExtRegAddr = uiExtRegAddr | IO_MUX_BASE; + pExtRegAddr = (uint32_t *)uiExtRegAddr; + *pExtRegAddr |= 1 << (pad_nr - 32); + } else { + uiExtRegAddr |= IO_MUX_BASE; + pExtRegAddr = (uint32_t *)uiExtRegAddr; + *pExtRegAddr |= 1 << pad_nr; + } return 0; } +void enable_fpga_clocks(void) +{ + PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_PF_WU + | PMU_FFE_FB_PF_SW_WU_FB_WU + | PMU_FFE_FB_PF_SW_WU_FFE_WU; + CRU->FB_SW_RESET = FB_C21_DOMAIN_SW_RESET | FB_C16_DOMAIN_SW_RESET + | FB_C09_DOMAIN_SW_RESET | FB_C02_DOMAIN_SW_RESET; + + CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_0_ON | C02_CLK_GATE_PATH_1_ON + | C02_CLK_GATE_PATH_2_ON; + + CRU->C08_X1_CLK_GATE = C08_X1_CLK_GATE_PATH_1_ON + | C08_X1_CLK_GATE_PATH_2_ON; + + CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON; + + CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON; + + CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_ON | C09_CLK_GATE_PATH_2_ON; +} + static void eos_s3_cru_init(void) { @@ -137,23 +155,7 @@ static void eos_s3_cru_init(void) #ifdef CONFIG_SOC_EOS_S3_FPGA static void eos_s3_fpga_init(void) { - PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_PF_WU - | PMU_FFE_FB_PF_SW_WU_FB_WU - | PMU_FFE_FB_PF_SW_WU_FFE_WU; - CRU->FB_SW_RESET = FB_C21_DOMAIN_SW_RESET | FB_C16_DOMAIN_SW_RESET - | FB_C09_DOMAIN_SW_RESET | FB_C02_DOMAIN_SW_RESET; - - CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_0_ON | C02_CLK_GATE_PATH_1_ON - | C02_CLK_GATE_PATH_2_ON; - - CRU->C08_X1_CLK_GATE = C08_X1_CLK_GATE_PATH_1_ON - | C08_X1_CLK_GATE_PATH_2_ON; - - CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON; - - CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON; - - CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_0_ON; + enable_fpga_clocks(); PMU->GEN_PURPOSE_0 = 0; PMU->FB_ISOLATION = 0; diff --git a/soc/arm/quicklogic_eos_s3/soc.h b/soc/arm/quicklogic_eos_s3/soc.h index 8ba43e387df2e3..68138ad56199a3 100644 --- a/soc/arm/quicklogic_eos_s3/soc.h +++ b/soc/arm/quicklogic_eos_s3/soc.h @@ -66,7 +66,8 @@ void EOSS3_DisableIRQ(IRQn_Type IRQn); void EOSS3_EnableIRQ(IRQn_Type IRQn); void EOSS3_ClearPendingIRQ(IRQn_Type IRQn); -void program_fpga_ip(); +void program_fpga_ip(void); +void enable_fpga_clocks(void); #define NVIC_DisableIRQ EOSS3_DisableIRQ #define NVIC_EnableIRQ EOSS3_EnableIRQ