From a2f81ec1c225879e98c4314af2250c0bbaad5b84 Mon Sep 17 00:00:00 2001
From: spingaliQL <spingali@quicklogic.com>
Date: Thu, 25 Jun 2020 17:28:06 +0530
Subject: [PATCH] Changes for flash samples

-Change QF dts file with new partitions
-Removed sleep which was added for testing
-Reinitialize C02 clock divider so that it will not change after running
boot loader
---
 boards/arm/quick_feather/quick_feather.dts | 17 +++++++++++++----
 samples/drivers/spi_flash/src/main.c       |  2 --
 soc/arm/quicklogic_eos_s3/soc.c            |  5 +++++
 3 files changed, 18 insertions(+), 6 deletions(-)
 mode change 100644 => 100755 boards/arm/quick_feather/quick_feather.dts

diff --git a/boards/arm/quick_feather/quick_feather.dts b/boards/arm/quick_feather/quick_feather.dts
old mode 100644
new mode 100755
index e735dc01a43f..1cf4f6c8f142
--- a/boards/arm/quick_feather/quick_feather.dts
+++ b/boards/arm/quick_feather/quick_feather.dts
@@ -132,8 +132,8 @@
 		 * 0x0001ffff (sectors 16-31) is reserved for use
 		 * by the application.
 		 */
-		storage_partition: partition@10000 {
-			label = "storage";
+		metadata_partition: partition@10000 {
+			label = "metadata";
 			reg = <0x00010000 0x00010000>;
 		};
 
@@ -145,9 +145,18 @@
 			label = "image-1";
 			reg = <0x00040000 0x00020000>;
 		};
-		scratch_partition: partition@60000 {
-			label = "image-scratch";
+		slot2_partition: partition@60000 {
+			label = "image-2";
 			reg = <0x00060000 0x00020000>;
 		};
+		slot3_partition: partition@80000 {
+			label = "image-3";
+			reg = <0x00080000 0x00020000>;
+		};
+		storage_partition: partition@100000 {
+			label = "storage";
+			reg = <0x00100000 0x00010000>;
+		};
+
 	};
 };
diff --git a/samples/drivers/spi_flash/src/main.c b/samples/drivers/spi_flash/src/main.c
index 149fe93807eb..f7dd4a9fe95c 100755
--- a/samples/drivers/spi_flash/src/main.c
+++ b/samples/drivers/spi_flash/src/main.c
@@ -68,8 +68,6 @@ void main(void)
 		printf("Flash write failed! %d\n", rc);
 		return;
 	}
-	// Sleep for a while
-        k_sleep(100); //in ms
 
 	memset(buf, 0, len);
 	rc = flash_read(flash_dev, FLASH_TEST_REGION_OFFSET, buf, len);
diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/arm/quicklogic_eos_s3/soc.c
index 3ff476d6766b..6c7550886a78 100644
--- a/soc/arm/quicklogic_eos_s3/soc.c
+++ b/soc/arm/quicklogic_eos_s3/soc.c
@@ -132,6 +132,11 @@ static void eos_s3_cru_init(void)
 	/* Set divider for domain C11 to ~ 5.12MHz */
 	CRU->CLK_CTRL_D_0 = (CLK_CTRL_CLK_DIVIDER_ENABLE |
 		CLK_CTRL_CLK_DIVIDER_RATIO_12);
+
+	/* Set C02 clock to default value,
+	 * if any prev app such as boot loader changes it will be set back
+	 */
+	CRU->CLK_CTRL_B_0 = 0x204;
 }
 
 #ifdef CONFIG_SOC_EOS_S3_FPGA