From 39905cbb231874f1b31497794929a0b1df4182d4 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Mon, 21 Mar 2022 02:25:16 +0100 Subject: [PATCH] cpu/esp32: add ESP32-C3 support in Kconfig --- cpu/esp32/Kconfig | 1 + cpu/esp32/Kconfig.esp32c3 | 118 +++++++++++++++++++++++++++ cpu/esp_common/vendor/xtensa/Kconfig | 2 +- 3 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 cpu/esp32/Kconfig.esp32c3 diff --git a/cpu/esp32/Kconfig b/cpu/esp32/Kconfig index 8727784a84c3..d5f848b1a0f1 100644 --- a/cpu/esp32/Kconfig +++ b/cpu/esp32/Kconfig @@ -58,6 +58,7 @@ menu "ESP32x configurations" endmenu orsource "Kconfig.esp32" +orsource "Kconfig.esp32c3" rsource "bootloader/Kconfig" rsource "esp-idf/Kconfig" diff --git a/cpu/esp32/Kconfig.esp32c3 b/cpu/esp32/Kconfig.esp32c3 new file mode 100644 index 000000000000..269501d4b9b6 --- /dev/null +++ b/cpu/esp32/Kconfig.esp32c3 @@ -0,0 +1,118 @@ +# Copyright (c) 2020 HAW Hamburg +# 2022 Gunar Schorcht +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. + +config CPU_ARCH_RISCV_ESP32 + bool + select HAS_ARCH_32BIT + select HAS_ARCH_ESP + help + RISC-V based ESP32x SoC variant is used. + +config CPU_ARCH + default "riscv_esp32" if CPU_ARCH_RISCV_ESP32 + +config CPU_CORE_RISCV32 + bool + select CPU_ARCH_RISCV_ESP32 + help + CPU core of the ESP32x SoC is a RISC-V core. + +config CPU_CORE + default "riscv32" if CPU_CORE_RISCV32 + +config CPU_FAM_ESP32C3 + bool + select CPU_COMMON_ESP + select CPU_CORE_RISCV32 + select HAS_ARCH_ESP32 + select HAS_CPU_ESP32 + select HAS_ESP_WIFI_ENTERPRISE + select HAS_PUF_SRAM + + select PACKAGE_ESP32_SDK if TEST_KCONFIG + + select MODULE_LIBC_GETTIMEOFDAY if TEST_KCONFIG + select MODULE_PERIPH_RTT if HAS_PERIPH_RTT && MODULE_PM_LAYERED + select MODULE_PS if MODULE_SHELL + select MODULE_PTHREAD if MODULE_CPP + select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC + imply MODULE_NEWLIB_NANO + +config CPU_FAM + default "esp32c3" if CPU_FAM_ESP32C3 + +## CPU Models +config CPU_MODEL_ESP32C3_WROOM_02X + bool + select CPU_FAM_ESP32C3 + +config CPU_MODEL_ESP32C3_MINI_1X + bool + select CPU_FAM_ESP32C3 + +config CPU_MODEL_ESP32C3 + bool + select CPU_FAM_ESP32C3 + +config CPU_MODEL_ESP32C3_FN4 + bool + select CPU_FAM_ESP32C3 + +config CPU_MODEL_ESP32C3_FH4 + bool + select CPU_FAM_ESP32C3 + +config CPU_MODEL + depends on CPU_FAM_ESP32C3 + default "esp32c3_wroom_02x" if CPU_MODEL_ESP32C3_WROOM_02X + default "esp32c3_mini_1x" if CPU_MODEL_ESP32C3_MINI_1X + default "esp32c3" if CPU_MODEL_ESP32C3 + default "esp32c3_fn4" if CPU_MODEL_ESP32C3_FN4 + default "esp32c3_fh4" if CPU_MODEL_ESP32C3_FH4 + +if CPU_FAM_ESP32C3 + +menu "ESP32-C3 specific configurations" + depends on TEST_KCONFIG + depends on HAS_ARCH_ESP32 + + choice + bool "CPU clock frequency" + default ESP32C3_DEFAULT_CPU_FREQ_MHZ_80 + help + CPU clock frequency used (default 80 MHz). + Please note that peripherals such as I2C or SPI might not work at + the specified clock frequency if the selected CPU clock frequency + is too low. These peripherals are clocked by the APB clock, which + has a clock rate of 80 MHz for CPU clock frequencies greater than + or equal to 80 MHz, but is equal to the CPU clock frequency for + CPU clock frequencies less than 80 MHz. Thus, for SPI, the APB + clock rate must be at least five times the SPI clock rate. For the + I2C hardware implementation, the APB clock rate must be at least + 3 MHZ to use I2C in fast mode with a I2C clock rate of 400 kHz. + For the I2C software implementation, the maximum I2C clock rate + is 1/130 times the CPU clock rate. + + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_2 + bool "2 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_5 + bool "50 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_10 + bool "10 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_20 + bool "20 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_40 + bool "40 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_80 + bool "80 MHz" + config ESP32C3_DEFAULT_CPU_FREQ_MHZ_160 + bool "160 MHz" + endchoice + +endmenu + +endif # CPU_FAM_ESP32C3 diff --git a/cpu/esp_common/vendor/xtensa/Kconfig b/cpu/esp_common/vendor/xtensa/Kconfig index 0234d0fc3383..7a0817363de2 100644 --- a/cpu/esp_common/vendor/xtensa/Kconfig +++ b/cpu/esp_common/vendor/xtensa/Kconfig @@ -8,7 +8,7 @@ config MODULE_XTENSA bool depends on TEST_KCONFIG - depends on HAS_ARCH_ESP + depends on CPU_ARCH_XTENSA default y help Third-party software components used by the RIOT port for ESP32 and