diff --git a/boards/rpi-pico/include/board.h b/boards/rpi-pico/include/board.h index ecf74bbfdf132..e3cc8a45ff283 100644 --- a/boards/rpi-pico/include/board.h +++ b/boards/rpi-pico/include/board.h @@ -34,9 +34,9 @@ extern "C" { * @{ */ #define LED0_PIN GPIO_PIN(0, 25) -#define LED0_ON do {SIO->GPIO_OUT_SET.reg = 1UL << 25;} while (0) -#define LED0_OFF do {SIO->GPIO_OUT_CLR.reg = 1UL << 25;} while (0) -#define LED0_TOGGLE do {SIO->GPIO_OUT_XOR.reg = 1UL << 25;} while (0) +#define LED0_ON do {SIO->GPIO_OUT_SET = 1UL << 25;} while (0) +#define LED0_OFF do {SIO->GPIO_OUT_CLR = 1UL << 25;} while (0) +#define LED0_TOGGLE do {SIO->GPIO_OUT_XOR = 1UL << 25;} while (0) #define LED0_NAME "LED(Green)" /** @} */ diff --git a/cpu/rpx0xx/clock.c b/cpu/rpx0xx/clock.c index 3602493623f1a..424632b263390 100644 --- a/cpu/rpx0xx/clock.c +++ b/cpu/rpx0xx/clock.c @@ -29,25 +29,25 @@ static void _clk_sys_set_source(CLOCKS_CLK_SYS_CTRL_SRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos, CLOCKS_CLK_SYS_CTRL_SRC_Msk); } static void _clk_sys_set_aux_source(CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos, CLOCKS_CLK_SYS_CTRL_AUXSRC_Msk); } static void _clk_ref_set_source(CLOCKS_CLK_REF_CTRL_SRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL.reg, source << CLOCKS_CLK_REF_CTRL_SRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL, source << CLOCKS_CLK_REF_CTRL_SRC_Pos, CLOCKS_CLK_REF_CTRL_SRC_Msk); } static void _clk_ref_set_aux_source(CLOCKS_CLK_REF_CTRL_AUXSRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL.reg, source << CLOCKS_CLK_REF_CTRL_AUXSRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL, source << CLOCKS_CLK_REF_CTRL_AUXSRC_Pos, CLOCKS_CLK_REF_CTRL_AUXSRC_Msk); } @@ -66,7 +66,7 @@ void clock_sys_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CT /* switch the glitchless mux to clk_ref */ _clk_sys_set_source(source); /* apply divider */ - CLOCKS->CLK_SYS_DIV.reg = div; + CLOCKS->CLK_SYS_DIV = div; /* poll SELECTED until the switch is completed */ while (!(CLOCKS->CLK_SYS_SELECTED & (1U << source))) { } } @@ -83,7 +83,7 @@ void clock_sys_configure_aux_source(uint32_t f_in, uint32_t f_out, /* change the auxiliary mux */ _clk_sys_set_aux_source(aux); /* apply divider */ - CLOCKS->CLK_SYS_DIV.reg = div; + CLOCKS->CLK_SYS_DIV = div; /* switch the glitchless mux to clk_sys_aux */ _clk_sys_set_source(CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux); /* poll SELECTED until the switch is completed */ @@ -98,7 +98,7 @@ void clock_ref_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CT /* switch the glitchless mux to clock source */ _clk_ref_set_source(source); /* apply divider */ - CLOCKS->CLK_REF_DIV.reg = div & CLOCKS_CLK_REF_DIV_INT_Msk; + CLOCKS->CLK_REF_DIV = div & CLOCKS_CLK_REF_DIV_INT_Msk; /* poll SELECTED until the switch is completed */ while (!(CLOCKS->CLK_REF_SELECTED & (1U << source))) { } } @@ -115,7 +115,7 @@ void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out, /* change the auxiliary mux */ _clk_ref_set_aux_source(aux); /* apply divider */ - CLOCKS->CLK_REF_DIV.reg = div & CLOCKS_CLK_REF_DIV_INT_Msk; + CLOCKS->CLK_REF_DIV = div & CLOCKS_CLK_REF_DIV_INT_Msk; /* switch the glitchless mux to clk_ref_aux */ _clk_ref_set_source(CLOCKS_CLK_REF_CTRL_SRC_clksrc_clk_ref_aux); /* poll SELECTED until the switch is completed */ @@ -124,21 +124,21 @@ void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out, void clock_periph_configure(CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux) { - io_reg_atomic_clear(&CLOCKS->CLK_PERI_CTRL.reg, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); - io_reg_write_dont_corrupt(&CLOCKS->CLK_PERI_CTRL.reg, aux << CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos, + io_reg_atomic_clear(&CLOCKS->CLK_PERI_CTRL, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); + io_reg_write_dont_corrupt(&CLOCKS->CLK_PERI_CTRL, aux << CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos, CLOCKS_CLK_PERI_CTRL_AUXSRC_Msk); - io_reg_atomic_set(&CLOCKS->CLK_PERI_CTRL.reg, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); + io_reg_atomic_set(&CLOCKS->CLK_PERI_CTRL, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); } void clock_gpout0_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux) { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT0_CTRL.reg, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT0_CTRL.reg, aux); - CLOCKS->CLK_GPOUT0_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT0_CTRL.reg, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO21.reg, 1U << PADS_BANK0_GPIO21_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT0_CTRL, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT0_CTRL, aux); + CLOCKS->CLK_GPOUT0_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT0_CTRL, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO21, 1U << PADS_BANK0_GPIO21_IE_Pos); gpio_set_function_select(21, FUNCTION_SELECT_CLOCK); } @@ -146,11 +146,11 @@ void clock_gpout1_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTR { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT1_CTRL.reg, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT1_CTRL.reg, aux); - CLOCKS->CLK_GPOUT1_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT1_CTRL.reg, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO23.reg, 1U << PADS_BANK0_GPIO23_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT1_CTRL, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT1_CTRL, aux); + CLOCKS->CLK_GPOUT1_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT1_CTRL, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO23, 1U << PADS_BANK0_GPIO23_IE_Pos); gpio_set_function_select(23, FUNCTION_SELECT_CLOCK); } @@ -158,11 +158,11 @@ void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTR { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT2_CTRL.reg, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT2_CTRL.reg, aux); - CLOCKS->CLK_GPOUT2_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT2_CTRL.reg, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO24.reg, 1U << PADS_BANK0_GPIO24_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT2_CTRL, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT2_CTRL, aux); + CLOCKS->CLK_GPOUT2_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT2_CTRL, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO24, 1U << PADS_BANK0_GPIO24_IE_Pos); gpio_set_function_select(24, FUNCTION_SELECT_CLOCK); } @@ -170,10 +170,10 @@ void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTR { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT3_CTRL.reg, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT3_CTRL.reg, aux); - CLOCKS->CLK_GPOUT3_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT3_CTRL.reg, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO25.reg, 1U << PADS_BANK0_GPIO25_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT3_CTRL, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT3_CTRL, aux); + CLOCKS->CLK_GPOUT3_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT3_CTRL, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO25, 1U << PADS_BANK0_GPIO25_IE_Pos); gpio_set_function_select(25, FUNCTION_SELECT_CLOCK); } diff --git a/cpu/rpx0xx/include/periph_cpu.h b/cpu/rpx0xx/include/periph_cpu.h index dc12c214bf665..bd6d40ff18315 100644 --- a/cpu/rpx0xx/include/periph_cpu.h +++ b/cpu/rpx0xx/include/periph_cpu.h @@ -487,7 +487,7 @@ static inline void gpio_reset_all_config(uint8_t pin) */ static inline void periph_reset(uint32_t components) { - io_reg_atomic_set(&RESETS->RESET.reg, components); + io_reg_atomic_set(&RESETS->RESET, components); } /** @@ -498,8 +498,8 @@ static inline void periph_reset(uint32_t components) */ static inline void periph_reset_done(uint32_t components) { - io_reg_atomic_clear(&RESETS->RESET.reg, components); - while ((~RESETS->RESET_DONE.reg) & components) { } + io_reg_atomic_clear(&RESETS->RESET, components); + while ((~RESETS->RESET_DONE) & components) { } } /** diff --git a/cpu/rpx0xx/include/vendor/RP2040.h b/cpu/rpx0xx/include/vendor/RP2040.h index 3b31151573777..170b43b093f33 100644 --- a/cpu/rpx0xx/include/vendor/RP2040.h +++ b/cpu/rpx0xx/include/vendor/RP2040.h @@ -3,12 +3,12 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * @file /home/fabian/rp2040//RP2040.h + * @file /home/maribu/Downloads/tmp/CMSIS/Utilities/Linux64//RP2040.h * @brief CMSIS HeaderFile * @version 0.1 - * @date 01. June 2021 - * @note Generated by SVDConv V3.3.35 on Tuesday, 01.06.2021 16:07:25 - * from File '/usr/lib/python3.9/site-packages/cmsis_svd/data/RaspberryPi/rp2040.svd', + * @date 22. March 2023 + * @note Generated by SVDConv V3.3.42 on Wednesday, 22.03.2023 16:07:51 + * from File '/home/maribu/Repos/software/pico-sdk/src/rp2040/hardware_regs/rp2040.svd', */ @@ -109,6 +109,31 @@ typedef enum { #endif +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ @@ -132,7 +157,7 @@ typedef enum { typedef struct { /*!< (@ 0x14000000) XIP_CTRL Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Cache control */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Cache control */ struct { __IOM uint32_t EN : 1; /*!< [0..0] When 1, enable the cache. When the cache is disabled, @@ -165,11 +190,11 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str when the cache is powered down. */ uint32_t : 28; - } bit; - } CTRL; + } CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Cache Flush control */ + __IOM uint32_t FLUSH; /*!< (@ 0x00000004) Cache Flush control */ struct { __IOM uint32_t FLUSH : 1; /*!< [0..0] Write 1 to flush the cache. This clears the tag memory, @@ -180,11 +205,11 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str flush completes. Alternatively STAT can be polled until completion. */ uint32_t : 31; - } bit; - } FLUSH; + } FLUSH_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Cache Status */ + __IOM uint32_t STAT; /*!< (@ 0x00000008) Cache Status */ struct { __IM uint32_t FLUSH_READY : 1; /*!< [0..0] Reads as 0 while a cache flush is in progress, and 1 @@ -199,8 +224,8 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained. */ uint32_t : 29; - } bit; - } STAT; + } STAT_b; + } ; __IOM uint32_t CTR_HIT; /*!< (@ 0x0000000C) Cache Hit counter A 32 bit saturating counter that increments upon each cache hit, @@ -215,7 +240,7 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str Write any value to clear. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000014) FIFO stream address */ + __IOM uint32_t STREAM_ADDR; /*!< (@ 0x00000014) FIFO stream address */ struct { uint32_t : 2; @@ -224,11 +249,11 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str Increments automatically after each flash access. Write the initial access address here before starting a streaming read. */ - } bit; - } STREAM_ADDR; + } STREAM_ADDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) FIFO stream control */ + __IOM uint32_t STREAM_CTR; /*!< (@ 0x00000018) FIFO stream control */ struct { __IOM uint32_t STREAM_CTR : 22; /*!< [21..0] Write a nonzero value to start a streaming read. This @@ -240,10 +265,10 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (aft */ + read, so that a new stream can immediately be started (after */ uint32_t : 10; - } bit; - } STREAM_CTR; + } STREAM_CTR_b; + } ; __IM uint32_t STREAM_FIFO; /*!< (@ 0x0000001C) FIFO stream data Streamed data is buffered here, for retrieval by the system DMA. @@ -292,7 +317,7 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str typedef struct { /*!< (@ 0x18000000) XIP_SSI Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control register 0 */ + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control register 0 */ struct { __IOM uint32_t DFS : 4; /*!< [3..0] Data frame size */ @@ -310,96 +335,96 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru uint32_t : 1; __IOM uint32_t SSTE : 1; /*!< [24..24] Slave select toggle enable */ uint32_t : 7; - } bit; - } CTRLR0; + } CTRLR0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Master Control register 1 */ + __IOM uint32_t CTRLR1; /*!< (@ 0x00000004) Master Control register 1 */ struct { __IOM uint32_t NDF : 16; /*!< [15..0] Number of data frames */ uint32_t : 16; - } bit; - } CTRLR1; + } CTRLR1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) SSI Enable */ + __IOM uint32_t SSIENR; /*!< (@ 0x00000008) SSI Enable */ struct { __IOM uint32_t SSI_EN : 1; /*!< [0..0] SSI enable */ uint32_t : 31; - } bit; - } SSIENR; + } SSIENR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Microwire Control */ + __IOM uint32_t MWCR; /*!< (@ 0x0000000C) Microwire Control */ struct { __IOM uint32_t MWMOD : 1; /*!< [0..0] Microwire transfer mode */ __IOM uint32_t MDD : 1; /*!< [1..1] Microwire control */ __IOM uint32_t MHS : 1; /*!< [2..2] Microwire handshaking */ uint32_t : 29; - } bit; - } MWCR; + } MWCR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Slave enable */ + __IOM uint32_t SER; /*!< (@ 0x00000010) Slave enable */ struct { __IOM uint32_t SER : 1; /*!< [0..0] For each bit: 0 -> slave not selected 1 -> slave selected */ uint32_t : 31; - } bit; - } SER; + } SER_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Baud rate */ + __IOM uint32_t BAUDR; /*!< (@ 0x00000014) Baud rate */ struct { __IOM uint32_t SCKDV : 16; /*!< [15..0] SSI clock divider */ uint32_t : 16; - } bit; - } BAUDR; + } BAUDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) TX FIFO threshold level */ + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) TX FIFO threshold level */ struct { __IOM uint32_t TFT : 8; /*!< [7..0] Transmit FIFO threshold */ uint32_t : 24; - } bit; - } TXFTLR; + } TXFTLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) RX FIFO threshold level */ + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) RX FIFO threshold level */ struct { __IOM uint32_t RFT : 8; /*!< [7..0] Receive FIFO threshold */ uint32_t : 24; - } bit; - } RXFTLR; + } RXFTLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) TX FIFO level */ + __IOM uint32_t TXFLR; /*!< (@ 0x00000020) TX FIFO level */ struct { __IM uint32_t TFTFL : 8; /*!< [7..0] Transmit FIFO level */ uint32_t : 24; - } bit; - } TXFLR; + } TXFLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) RX FIFO level */ + __IOM uint32_t RXFLR; /*!< (@ 0x00000024) RX FIFO level */ struct { __IM uint32_t RXTFL : 8; /*!< [7..0] Receive FIFO level */ uint32_t : 24; - } bit; - } RXFLR; + } RXFLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Status register */ + __IOM uint32_t SR; /*!< (@ 0x00000028) Status register */ struct { __IM uint32_t BUSY : 1; /*!< [0..0] SSI busy flag */ @@ -410,11 +435,11 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru __IM uint32_t TXE : 1; /*!< [5..5] Transmission error */ __IM uint32_t DCOL : 1; /*!< [6..6] Data collision error */ uint32_t : 25; - } bit; - } SR; + } SR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Interrupt mask */ + __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt mask */ struct { __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO empty interrupt mask */ @@ -424,11 +449,11 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO full interrupt mask */ __IOM uint32_t MSTIM : 1; /*!< [5..5] Multi-master contention interrupt mask */ uint32_t : 26; - } bit; - } IMR; + } IMR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Interrupt status */ + __IOM uint32_t ISR; /*!< (@ 0x00000030) Interrupt status */ struct { __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO empty interrupt status */ @@ -438,11 +463,11 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO full interrupt status */ __IM uint32_t MSTIS : 1; /*!< [5..5] Multi-master contention interrupt status */ uint32_t : 26; - } bit; - } ISR; + } ISR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Raw interrupt status */ + __IOM uint32_t RISR; /*!< (@ 0x00000034) Raw interrupt status */ struct { __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO empty raw interrupt status */ @@ -452,118 +477,118 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO full raw interrupt status */ __IM uint32_t MSTIR : 1; /*!< [5..5] Multi-master contention raw interrupt status */ uint32_t : 26; - } bit; - } RISR; + } RISR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) TX FIFO overflow interrupt clear */ + __IOM uint32_t TXOICR; /*!< (@ 0x00000038) TX FIFO overflow interrupt clear */ struct { __IM uint32_t TXOICR : 1; /*!< [0..0] Clear-on-read transmit FIFO overflow interrupt */ uint32_t : 31; - } bit; - } TXOICR; + } TXOICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) RX FIFO overflow interrupt clear */ + __IOM uint32_t RXOICR; /*!< (@ 0x0000003C) RX FIFO overflow interrupt clear */ struct { __IM uint32_t RXOICR : 1; /*!< [0..0] Clear-on-read receive FIFO overflow interrupt */ uint32_t : 31; - } bit; - } RXOICR; + } RXOICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) RX FIFO underflow interrupt clear */ + __IOM uint32_t RXUICR; /*!< (@ 0x00000040) RX FIFO underflow interrupt clear */ struct { __IM uint32_t RXUICR : 1; /*!< [0..0] Clear-on-read receive FIFO underflow interrupt */ uint32_t : 31; - } bit; - } RXUICR; + } RXUICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Multi-master interrupt clear */ + __IOM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-master interrupt clear */ struct { __IM uint32_t MSTICR : 1; /*!< [0..0] Clear-on-read multi-master contention interrupt */ uint32_t : 31; - } bit; - } MSTICR; + } MSTICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Interrupt clear */ + __IOM uint32_t ICR; /*!< (@ 0x00000048) Interrupt clear */ struct { __IM uint32_t ICR : 1; /*!< [0..0] Clear-on-read all active interrupts */ uint32_t : 31; - } bit; - } ICR; + } ICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) DMA control */ + __IOM uint32_t DMACR; /*!< (@ 0x0000004C) DMA control */ struct { __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA enable */ __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA enable */ uint32_t : 30; - } bit; - } DMACR; + } DMACR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) DMA TX data level */ + __IOM uint32_t DMATDLR; /*!< (@ 0x00000050) DMA TX data level */ struct { __IOM uint32_t DMATDL : 8; /*!< [7..0] Transmit data watermark level */ uint32_t : 24; - } bit; - } DMATDLR; + } DMATDLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) DMA RX data level */ + __IOM uint32_t DMARDLR; /*!< (@ 0x00000054) DMA RX data level */ struct { __IOM uint32_t DMARDL : 8; /*!< [7..0] Receive data watermark level (DMARDLR+1) */ uint32_t : 24; - } bit; - } DMARDLR; + } DMARDLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Identification register */ + __IOM uint32_t IDR; /*!< (@ 0x00000058) Identification register */ struct { __IM uint32_t IDCODE : 32; /*!< [31..0] Peripheral dentification code */ - } bit; - } IDR; + } IDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Version ID */ + __IOM uint32_t SSI_VERSION_ID; /*!< (@ 0x0000005C) Version ID */ struct { __IM uint32_t SSI_COMP_VERSION : 32; /*!< [31..0] SNPS component version (format X.YY) */ - } bit; - } SSI_VERSION_ID; + } SSI_VERSION_ID_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Data Register 0 (of 36) */ + __IOM uint32_t DR0; /*!< (@ 0x00000060) Data Register 0 (of 36) */ struct { __IOM uint32_t DR : 32; /*!< [31..0] First data register of 36 */ - } bit; - } DR0; + } DR0_b; + } ; __IM uint32_t RESERVED[35]; union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) RX sample delay */ + __IOM uint32_t RX_SAMPLE_DLY; /*!< (@ 0x000000F0) RX sample delay */ struct { __IOM uint32_t RSD : 8; /*!< [7..0] RXD sample delay (in SCLK cycles) */ uint32_t : 24; - } bit; - } RX_SAMPLE_DLY; + } RX_SAMPLE_DLY_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) SPI control */ + __IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control */ struct { __IOM uint32_t TRANS_TYPE : 2; /*!< [1..0] Address and instruction transfer format */ @@ -579,17 +604,17 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru uint32_t : 5; __IOM uint32_t XIP_CMD : 8; /*!< [31..24] SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) */ - } bit; - } SPI_CTRLR0; + } SPI_CTRLR0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) TX drive edge */ + __IOM uint32_t TXD_DRIVE_EDGE; /*!< (@ 0x000000F8) TX drive edge */ struct { __IOM uint32_t TDE : 8; /*!< [7..0] TXD drive edge */ uint32_t : 24; - } bit; - } TXD_DRIVE_EDGE; + } TXD_DRIVE_EDGE_b; + } ; } XIP_SSI_Type; /*!< Size = 252 (0xfc) */ @@ -606,25 +631,25 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru typedef struct { /*!< (@ 0x40000000) SYSINFO Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) JEDEC JEP-106 compliant chip identifier. */ + __IOM uint32_t CHIP_ID; /*!< (@ 0x00000000) JEDEC JEP-106 compliant chip identifier. */ struct { __IM uint32_t MANUFACTURER : 12; /*!< [11..0] MANUFACTURER */ __IM uint32_t PART : 16; /*!< [27..12] PART */ __IM uint32_t REVISION : 4; /*!< [31..28] REVISION */ - } bit; - } CHIP_ID; + } CHIP_ID_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Platform register. Allows software to know what + __IOM uint32_t PLATFORM; /*!< (@ 0x00000004) Platform register. Allows software to know what environment it is running in. */ struct { __IM uint32_t FPGA : 1; /*!< [0..0] FPGA */ __IM uint32_t ASIC : 1; /*!< [1..1] ASIC */ uint32_t : 30; - } bit; - } PLATFORM; + } PLATFORM_b; + } ; __IM uint32_t RESERVED[14]; __IM uint32_t GITREF_RP2040; /*!< (@ 0x00000040) Git hash of the chip source. Used to identify chip version. */ @@ -648,7 +673,7 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc Set a bit high to enable NMI from that IRQ */ union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Configuration for processors */ + __IOM uint32_t PROC_CONFIG; /*!< (@ 0x00000008) Configuration for processors */ struct { __IM uint32_t PROC0_HALTED : 1; /*!< [0..0] Indication that proc0 has halted */ @@ -662,11 +687,11 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP */ - } bit; - } PROC_CONFIG; + } PROC_CONFIG_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) For each bit, if 1, bypass the input synchronizer + __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< (@ 0x0000000C) For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -679,11 +704,11 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc struct { __IOM uint32_t PROC_IN_SYNC_BYPASS : 30; /*!< [29..0] PROC_IN_SYNC_BYPASS */ uint32_t : 2; - } bit; - } PROC_IN_SYNC_BYPASS; + } PROC_IN_SYNC_BYPASS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) For each bit, if 1, bypass the input synchronizer + __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< (@ 0x00000010) For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -697,11 +722,11 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc struct { __IOM uint32_t PROC_IN_SYNC_BYPASS_HI : 6;/*!< [5..0] PROC_IN_SYNC_BYPASS_HI */ uint32_t : 26; - } bit; - } PROC_IN_SYNC_BYPASS_HI; + } PROC_IN_SYNC_BYPASS_HI_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Directly control the SWD debug port of either + __IOM uint32_t DBGFORCE; /*!< (@ 0x00000014) Directly control the SWD debug port of either processor */ struct { @@ -720,11 +745,11 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc __IOM uint32_t PROC1_ATTACH : 1; /*!< [7..7] Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. */ uint32_t : 24; - } bit; - } DBGFORCE; + } DBGFORCE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Control power downs to memories. Set high to + __IOM uint32_t MEMPOWERDOWN; /*!< (@ 0x00000018) Control power downs to memories. Set high to power down memories. Use with extreme caution */ @@ -738,8 +763,8 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc __IOM uint32_t USB : 1; /*!< [6..6] USB */ __IOM uint32_t ROM : 1; /*!< [7..7] ROM */ uint32_t : 24; - } bit; - } MEMPOWERDOWN; + } MEMPOWERDOWN_b; + } ; } SYSCFG_Type; /*!< Size = 28 (0x1c) */ @@ -756,7 +781,7 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc typedef struct { /*!< (@ 0x40008000) CLOCKS Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT0_CTRL; /*!< (@ 0x00000000) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -777,21 +802,25 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_GPOUT0_CTRL; + } CLK_GPOUT0_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT0_DIV; /*!< (@ 0x00000004) Clock divisor, can be changed on-the-fly */ struct { __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT0_DIV; - __IM uint32_t CLK_GPOUT0_SELECTED; /*!< (@ 0x00000008) Indicates which src is currently selected (one-hot) */ + } CLK_GPOUT0_DIV_b; + } ; + __IM uint32_t CLK_GPOUT0_SELECTED; /*!< (@ 0x00000008) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT1_CTRL; /*!< (@ 0x0000000C) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -812,21 +841,25 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_GPOUT1_CTRL; + } CLK_GPOUT1_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT1_DIV; /*!< (@ 0x00000010) Clock divisor, can be changed on-the-fly */ struct { __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT1_DIV; - __IM uint32_t CLK_GPOUT1_SELECTED; /*!< (@ 0x00000014) Indicates which src is currently selected (one-hot) */ + } CLK_GPOUT1_DIV_b; + } ; + __IM uint32_t CLK_GPOUT1_SELECTED; /*!< (@ 0x00000014) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT2_CTRL; /*!< (@ 0x00000018) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -847,21 +880,25 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_GPOUT2_CTRL; + } CLK_GPOUT2_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT2_DIV; /*!< (@ 0x0000001C) Clock divisor, can be changed on-the-fly */ struct { __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT2_DIV; - __IM uint32_t CLK_GPOUT2_SELECTED; /*!< (@ 0x00000020) Indicates which src is currently selected (one-hot) */ + } CLK_GPOUT2_DIV_b; + } ; + __IM uint32_t CLK_GPOUT2_SELECTED; /*!< (@ 0x00000020) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT3_CTRL; /*!< (@ 0x00000024) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -882,21 +919,25 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_GPOUT3_CTRL; + } CLK_GPOUT3_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT3_DIV; /*!< (@ 0x00000028) Clock divisor, can be changed on-the-fly */ struct { __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT3_DIV; - __IM uint32_t CLK_GPOUT3_SELECTED; /*!< (@ 0x0000002C) Indicates which src is currently selected (one-hot) */ + } CLK_GPOUT3_DIV_b; + } ; + __IM uint32_t CLK_GPOUT3_SELECTED; /*!< (@ 0x0000002C) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_REF_CTRL; /*!< (@ 0x00000030) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -906,22 +947,33 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t AUXSRC : 2; /*!< [6..5] Selects the auxiliary clock source, will glitch when switching */ uint32_t : 25; - } bit; - } CLK_REF_CTRL; + } CLK_REF_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_REF_DIV; /*!< (@ 0x00000034) Clock divisor, can be changed on-the-fly */ struct { uint32_t : 8; __IOM uint32_t INT : 2; /*!< [9..8] Integer component of the divisor, 0 -> divide by 2^16 */ uint32_t : 22; - } bit; - } CLK_REF_DIV; - __IM uint32_t CLK_REF_SELECTED; /*!< (@ 0x00000038) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Clock control, can be changed on-the-fly (except + } CLK_REF_DIV_b; + } ; + __IM uint32_t CLK_REF_SELECTED; /*!< (@ 0x00000038) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + The glitchless multiplexer does not switch + instantaneously (to avoid glitches), so + software should poll this register to wait + for the switch to complete. This register + contains one decoded bit for each of the + clock sources enumerated in the CTRL SRC + field. At most one of these bits will be + set at any time, indicating that clock is + currently present at the output of the glitchless + mux. Whilst switching i */ + + union { + __IOM uint32_t CLK_SYS_CTRL; /*!< (@ 0x0000003C) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -931,21 +983,32 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t AUXSRC : 3; /*!< [7..5] Selects the auxiliary clock source, will glitch when switching */ uint32_t : 24; - } bit; - } CLK_SYS_CTRL; + } CLK_SYS_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_SYS_DIV; /*!< (@ 0x00000040) Clock divisor, can be changed on-the-fly */ struct { __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_SYS_DIV; - __IM uint32_t CLK_SYS_SELECTED; /*!< (@ 0x00000044) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Clock control, can be changed on-the-fly (except + } CLK_SYS_DIV_b; + } ; + __IM uint32_t CLK_SYS_SELECTED; /*!< (@ 0x00000044) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + The glitchless multiplexer does not switch + instantaneously (to avoid glitches), so + software should poll this register to wait + for the switch to complete. This register + contains one decoded bit for each of the + clock sources enumerated in the CTRL SRC + field. At most one of these bits will be + set at any time, indicating that clock is + currently present at the output of the glitchless + mux. Whilst switching i */ + + union { + __IOM uint32_t CLK_PERI_CTRL; /*!< (@ 0x00000048) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -956,13 +1019,17 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ uint32_t : 20; - } bit; - } CLK_PERI_CTRL; + } CLK_PERI_CTRL_b; + } ; __IM uint32_t RESERVED; - __IM uint32_t CLK_PERI_SELECTED; /*!< (@ 0x00000050) Indicates which src is currently selected (one-hot) */ + __IM uint32_t CLK_PERI_SELECTED; /*!< (@ 0x00000050) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_USB_CTRL; /*!< (@ 0x00000054) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -982,22 +1049,26 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_USB_CTRL; + } CLK_USB_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_USB_DIV; /*!< (@ 0x00000058) Clock divisor, can be changed on-the-fly */ struct { uint32_t : 8; __IOM uint32_t INT : 2; /*!< [9..8] Integer component of the divisor, 0 -> divide by 2^16 */ uint32_t : 22; - } bit; - } CLK_USB_DIV; - __IM uint32_t CLK_USB_SELECTED; /*!< (@ 0x0000005C) Indicates which src is currently selected (one-hot) */ + } CLK_USB_DIV_b; + } ; + __IM uint32_t CLK_USB_SELECTED; /*!< (@ 0x0000005C) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_ADC_CTRL; /*!< (@ 0x00000060) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -1017,22 +1088,26 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_ADC_CTRL; + } CLK_ADC_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_ADC_DIV; /*!< (@ 0x00000064) Clock divisor, can be changed on-the-fly */ struct { uint32_t : 8; __IOM uint32_t INT : 2; /*!< [9..8] Integer component of the divisor, 0 -> divide by 2^16 */ uint32_t : 22; - } bit; - } CLK_ADC_DIV; - __IM uint32_t CLK_ADC_SELECTED; /*!< (@ 0x00000068) Indicates which src is currently selected (one-hot) */ + } CLK_ADC_DIV_b; + } ; + __IM uint32_t CLK_ADC_SELECTED; /*!< (@ 0x00000068) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_RTC_CTRL; /*!< (@ 0x0000006C) Clock control, can be changed on-the-fly (except for auxsrc) */ struct { @@ -1052,21 +1127,25 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc by 1 cycle of the input clock This can be done at any time */ uint32_t : 11; - } bit; - } CLK_RTC_CTRL; + } CLK_RTC_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_RTC_DIV; /*!< (@ 0x00000070) Clock divisor, can be changed on-the-fly */ struct { __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_RTC_DIV; - __IM uint32_t CLK_RTC_SELECTED; /*!< (@ 0x00000074) Indicates which src is currently selected (one-hot) */ + } CLK_RTC_DIV_b; + } ; + __IM uint32_t CLK_RTC_SELECTED; /*!< (@ 0x00000074) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000078) CLK_SYS_RESUS_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< (@ 0x00000078) CLK_SYS_RESUS_CTRL */ struct { __IOM uint32_t TIMEOUT : 8; /*!< [7..0] This is expressed as a number of clk_ref cycles @@ -1078,52 +1157,52 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t CLEAR : 1; /*!< [16..16] For clearing the resus after the fault that triggered it has been corrected */ uint32_t : 15; - } bit; - } CLK_SYS_RESUS_CTRL; + } CLK_SYS_RESUS_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) CLK_SYS_RESUS_STATUS */ + __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< (@ 0x0000007C) CLK_SYS_RESUS_STATUS */ struct { __IM uint32_t RESUSSED : 1; /*!< [0..0] Clock has been resuscitated, correct the error then send ctrl_clear=1 */ uint32_t : 31; - } bit; - } CLK_SYS_RESUS_STATUS; + } CLK_SYS_RESUS_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Reference clock frequency in kHz */ + __IOM uint32_t FC0_REF_KHZ; /*!< (@ 0x00000080) Reference clock frequency in kHz */ struct { __IOM uint32_t FC0_REF_KHZ : 20; /*!< [19..0] FC0_REF_KHZ */ uint32_t : 12; - } bit; - } FC0_REF_KHZ; + } FC0_REF_KHZ_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Minimum pass frequency in kHz. This is optional. + __IOM uint32_t FC0_MIN_KHZ; /*!< (@ 0x00000084) Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags */ struct { __IOM uint32_t FC0_MIN_KHZ : 25; /*!< [24..0] FC0_MIN_KHZ */ uint32_t : 7; - } bit; - } FC0_MIN_KHZ; + } FC0_MIN_KHZ_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000088) Maximum pass frequency in kHz. This is optional. + __IOM uint32_t FC0_MAX_KHZ; /*!< (@ 0x00000088) Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags */ struct { __IOM uint32_t FC0_MAX_KHZ : 25; /*!< [24..0] FC0_MAX_KHZ */ uint32_t : 7; - } bit; - } FC0_MAX_KHZ; + } FC0_MAX_KHZ_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Delays the start of frequency counting to allow + __IOM uint32_t FC0_DELAY; /*!< (@ 0x0000008C) Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period */ @@ -1131,22 +1210,22 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc struct { __IOM uint32_t FC0_DELAY : 3; /*!< [2..0] FC0_DELAY */ uint32_t : 29; - } bit; - } FC0_DELAY; + } FC0_DELAY_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000090) The test interval is 0.98us * 2**interval, but + __IOM uint32_t FC0_INTERVAL; /*!< (@ 0x00000090) The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us */ struct { __IOM uint32_t FC0_INTERVAL : 4; /*!< [3..0] FC0_INTERVAL */ uint32_t : 28; - } bit; - } FC0_INTERVAL; + } FC0_INTERVAL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Clock sent to frequency counter, set to 0 when + __IOM uint32_t FC0_SRC; /*!< (@ 0x00000094) Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count */ @@ -1154,11 +1233,11 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc struct { __IOM uint32_t FC0_SRC : 8; /*!< [7..0] FC0_SRC */ uint32_t : 24; - } bit; - } FC0_SRC; + } FC0_SRC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Frequency counter status */ + __IOM uint32_t FC0_STATUS; /*!< (@ 0x00000098) Frequency counter status */ struct { __IM uint32_t PASS : 1; /*!< [0..0] Test passed */ @@ -1177,22 +1256,22 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc uint32_t : 3; __IM uint32_t DIED : 1; /*!< [28..28] Test clock stopped during test */ uint32_t : 3; - } bit; - } FC0_STATUS; + } FC0_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) Result of frequency measurement, only valid when + __IOM uint32_t FC0_RESULT; /*!< (@ 0x0000009C) Result of frequency measurement, only valid when status_done=1 */ struct { __IM uint32_t FRAC : 5; /*!< [4..0] FRAC */ __IM uint32_t KHZ : 25; /*!< [29..5] KHZ */ uint32_t : 2; - } bit; - } FC0_RESULT; + } FC0_RESULT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) enable clock in wake mode */ + __IOM uint32_t WAKE_EN0; /*!< (@ 0x000000A0) enable clock in wake mode */ struct { __IOM uint32_t clk_sys_clocks : 1; /*!< [0..0] clk_sys_clocks */ @@ -1227,11 +1306,11 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t clk_sys_sram1 : 1; /*!< [29..29] clk_sys_sram1 */ __IOM uint32_t clk_sys_sram2 : 1; /*!< [30..30] clk_sys_sram2 */ __IOM uint32_t clk_sys_sram3 : 1; /*!< [31..31] clk_sys_sram3 */ - } bit; - } WAKE_EN0; + } WAKE_EN0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) enable clock in wake mode */ + __IOM uint32_t WAKE_EN1; /*!< (@ 0x000000A4) enable clock in wake mode */ struct { __IOM uint32_t clk_sys_sram4 : 1; /*!< [0..0] clk_sys_sram4 */ @@ -1250,11 +1329,11 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t clk_sys_xip : 1; /*!< [13..13] clk_sys_xip */ __IOM uint32_t clk_sys_xosc : 1; /*!< [14..14] clk_sys_xosc */ uint32_t : 17; - } bit; - } WAKE_EN1; + } WAKE_EN1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN0; /*!< (@ 0x000000A8) enable clock in sleep mode */ struct { __IOM uint32_t clk_sys_clocks : 1; /*!< [0..0] clk_sys_clocks */ @@ -1289,11 +1368,11 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t clk_sys_sram1 : 1; /*!< [29..29] clk_sys_sram1 */ __IOM uint32_t clk_sys_sram2 : 1; /*!< [30..30] clk_sys_sram2 */ __IOM uint32_t clk_sys_sram3 : 1; /*!< [31..31] clk_sys_sram3 */ - } bit; - } SLEEP_EN0; + } SLEEP_EN0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN1; /*!< (@ 0x000000AC) enable clock in sleep mode */ struct { __IOM uint32_t clk_sys_sram4 : 1; /*!< [0..0] clk_sys_sram4 */ @@ -1312,11 +1391,11 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IOM uint32_t clk_sys_xip : 1; /*!< [13..13] clk_sys_xip */ __IOM uint32_t clk_sys_xosc : 1; /*!< [14..14] clk_sys_xosc */ uint32_t : 17; - } bit; - } SLEEP_EN1; + } SLEEP_EN1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) indicates the state of the clock enable */ + __IOM uint32_t ENABLED0; /*!< (@ 0x000000B0) indicates the state of the clock enable */ struct { __IM uint32_t clk_sys_clocks : 1; /*!< [0..0] clk_sys_clocks */ @@ -1351,11 +1430,11 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IM uint32_t clk_sys_sram1 : 1; /*!< [29..29] clk_sys_sram1 */ __IM uint32_t clk_sys_sram2 : 1; /*!< [30..30] clk_sys_sram2 */ __IM uint32_t clk_sys_sram3 : 1; /*!< [31..31] clk_sys_sram3 */ - } bit; - } ENABLED0; + } ENABLED0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) indicates the state of the clock enable */ + __IOM uint32_t ENABLED1; /*!< (@ 0x000000B4) indicates the state of the clock enable */ struct { __IM uint32_t clk_sys_sram4 : 1; /*!< [0..0] clk_sys_sram4 */ @@ -1374,44 +1453,44 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc __IM uint32_t clk_sys_xip : 1; /*!< [13..13] clk_sys_xip */ __IM uint32_t clk_sys_xosc : 1; /*!< [14..14] clk_sys_xosc */ uint32_t : 17; - } bit; - } ENABLED1; + } ENABLED1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x000000B8) Raw Interrupts */ struct { __IM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ uint32_t : 31; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000BC) Interrupt Enable */ + __IOM uint32_t INTE; /*!< (@ 0x000000BC) Interrupt Enable */ struct { __IOM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ uint32_t : 31; - } bit; - } INTE; + } INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C0) Interrupt Force */ + __IOM uint32_t INTF; /*!< (@ 0x000000C0) Interrupt Force */ struct { __IOM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ uint32_t : 31; - } bit; - } INTF; + } INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C4) Interrupt status after masking & forcing */ + __IOM uint32_t INTS; /*!< (@ 0x000000C4) Interrupt status after masking & forcing */ struct { __IM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ uint32_t : 31; - } bit; - } INTS; + } INTS_b; + } ; } CLOCKS_Type; /*!< Size = 200 (0xc8) */ @@ -1428,7 +1507,7 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc typedef struct { /*!< (@ 0x4000C000) RESETS Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Reset control. If a bit is set it means the peripheral + __IOM uint32_t RESET; /*!< (@ 0x00000000) Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. */ @@ -1459,11 +1538,11 @@ typedef struct { /*!< (@ 0x4000C000) RESETS Struc __IOM uint32_t uart1 : 1; /*!< [23..23] uart1 */ __IOM uint32_t usbctrl : 1; /*!< [24..24] usbctrl */ uint32_t : 7; - } bit; - } RESET; + } RESET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Watchdog select. If a bit is set then the watchdog + __IOM uint32_t WDSEL; /*!< (@ 0x00000004) Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. */ @@ -1494,11 +1573,11 @@ typedef struct { /*!< (@ 0x4000C000) RESETS Struc __IOM uint32_t uart1 : 1; /*!< [23..23] uart1 */ __IOM uint32_t usbctrl : 1; /*!< [24..24] usbctrl */ uint32_t : 7; - } bit; - } WDSEL; + } WDSEL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Reset done. If a bit is set then a reset done + __IOM uint32_t RESET_DONE; /*!< (@ 0x00000008) Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. */ @@ -1530,8 +1609,8 @@ typedef struct { /*!< (@ 0x4000C000) RESETS Struc __IM uint32_t uart1 : 1; /*!< [23..23] uart1 */ __IM uint32_t usbctrl : 1; /*!< [24..24] usbctrl */ uint32_t : 7; - } bit; - } RESET_DONE; + } RESET_DONE_b; + } ; } RESETS_Type; /*!< Size = 12 (0xc) */ @@ -1548,7 +1627,7 @@ typedef struct { /*!< (@ 0x4000C000) RESETS Struc typedef struct { /*!< (@ 0x40010000) PSM Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Force block out of reset (i.e. power it on) */ + __IOM uint32_t FRCE_ON; /*!< (@ 0x00000000) Force block out of reset (i.e. power it on) */ struct { __IOM uint32_t rosc : 1; /*!< [0..0] rosc */ @@ -1569,11 +1648,11 @@ typedef struct { /*!< (@ 0x40010000) PSM Structur __IOM uint32_t proc0 : 1; /*!< [15..15] proc0 */ __IOM uint32_t proc1 : 1; /*!< [16..16] proc1 */ uint32_t : 15; - } bit; - } FRCE_ON; + } FRCE_ON_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Force into reset (i.e. power it off) */ + __IOM uint32_t FRCE_OFF; /*!< (@ 0x00000004) Force into reset (i.e. power it off) */ struct { __IOM uint32_t rosc : 1; /*!< [0..0] rosc */ @@ -1594,11 +1673,11 @@ typedef struct { /*!< (@ 0x40010000) PSM Structur __IOM uint32_t proc0 : 1; /*!< [15..15] proc0 */ __IOM uint32_t proc1 : 1; /*!< [16..16] proc1 */ uint32_t : 15; - } bit; - } FRCE_OFF; + } FRCE_OFF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Set to 1 if this peripheral should be reset when + __IOM uint32_t WDSEL; /*!< (@ 0x00000008) Set to 1 if this peripheral should be reset when the watchdog fires. */ struct { @@ -1620,11 +1699,11 @@ typedef struct { /*!< (@ 0x40010000) PSM Structur __IOM uint32_t proc0 : 1; /*!< [15..15] proc0 */ __IOM uint32_t proc1 : 1; /*!< [16..16] proc1 */ uint32_t : 15; - } bit; - } WDSEL; + } WDSEL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Indicates the peripheral's registers are ready + __IOM uint32_t DONE; /*!< (@ 0x0000000C) Indicates the peripheral's registers are ready to access. */ struct { @@ -1646,8 +1725,8 @@ typedef struct { /*!< (@ 0x40010000) PSM Structur __IM uint32_t proc0 : 1; /*!< [15..15] proc0 */ __IM uint32_t proc1 : 1; /*!< [16..16] proc1 */ uint32_t : 15; - } bit; - } DONE; + } DONE_b; + } ; } PSM_Type; /*!< Size = 16 (0x10) */ @@ -1664,7 +1743,7 @@ typedef struct { /*!< (@ 0x40010000) PSM Structur typedef struct { /*!< (@ 0x40014000) IO_BANK0 Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) GPIO status */ + __IOM uint32_t GPIO0_STATUS; /*!< (@ 0x00000000) GPIO status */ struct { uint32_t : 8; @@ -1684,11 +1763,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO0_STATUS; + } GPIO0_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO0_CTRL; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1702,11 +1781,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO0_CTRL; + } GPIO0_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) GPIO status */ + __IOM uint32_t GPIO1_STATUS; /*!< (@ 0x00000008) GPIO status */ struct { uint32_t : 8; @@ -1726,11 +1805,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO1_STATUS; + } GPIO1_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO1_CTRL; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1744,11 +1823,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO1_CTRL; + } GPIO1_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) GPIO status */ + __IOM uint32_t GPIO2_STATUS; /*!< (@ 0x00000010) GPIO status */ struct { uint32_t : 8; @@ -1768,11 +1847,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO2_STATUS; + } GPIO2_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO2_CTRL; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1786,11 +1865,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO2_CTRL; + } GPIO2_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) GPIO status */ + __IOM uint32_t GPIO3_STATUS; /*!< (@ 0x00000018) GPIO status */ struct { uint32_t : 8; @@ -1810,11 +1889,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO3_STATUS; + } GPIO3_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO3_CTRL; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1828,11 +1907,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO3_CTRL; + } GPIO3_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) GPIO status */ + __IOM uint32_t GPIO4_STATUS; /*!< (@ 0x00000020) GPIO status */ struct { uint32_t : 8; @@ -1852,11 +1931,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO4_STATUS; + } GPIO4_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO4_CTRL; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1870,11 +1949,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO4_CTRL; + } GPIO4_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) GPIO status */ + __IOM uint32_t GPIO5_STATUS; /*!< (@ 0x00000028) GPIO status */ struct { uint32_t : 8; @@ -1894,11 +1973,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO5_STATUS; + } GPIO5_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO5_CTRL; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1912,11 +1991,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO5_CTRL; + } GPIO5_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) GPIO status */ + __IOM uint32_t GPIO6_STATUS; /*!< (@ 0x00000030) GPIO status */ struct { uint32_t : 8; @@ -1936,11 +2015,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO6_STATUS; + } GPIO6_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO6_CTRL; /*!< (@ 0x00000034) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1954,11 +2033,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO6_CTRL; + } GPIO6_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) GPIO status */ + __IOM uint32_t GPIO7_STATUS; /*!< (@ 0x00000038) GPIO status */ struct { uint32_t : 8; @@ -1978,11 +2057,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO7_STATUS; + } GPIO7_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO7_CTRL; /*!< (@ 0x0000003C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -1996,11 +2075,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO7_CTRL; + } GPIO7_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) GPIO status */ + __IOM uint32_t GPIO8_STATUS; /*!< (@ 0x00000040) GPIO status */ struct { uint32_t : 8; @@ -2020,11 +2099,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO8_STATUS; + } GPIO8_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO8_CTRL; /*!< (@ 0x00000044) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2038,11 +2117,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO8_CTRL; + } GPIO8_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) GPIO status */ + __IOM uint32_t GPIO9_STATUS; /*!< (@ 0x00000048) GPIO status */ struct { uint32_t : 8; @@ -2062,11 +2141,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO9_STATUS; + } GPIO9_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO9_CTRL; /*!< (@ 0x0000004C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2080,11 +2159,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO9_CTRL; + } GPIO9_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) GPIO status */ + __IOM uint32_t GPIO10_STATUS; /*!< (@ 0x00000050) GPIO status */ struct { uint32_t : 8; @@ -2104,11 +2183,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO10_STATUS; + } GPIO10_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO10_CTRL; /*!< (@ 0x00000054) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2122,11 +2201,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO10_CTRL; + } GPIO10_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) GPIO status */ + __IOM uint32_t GPIO11_STATUS; /*!< (@ 0x00000058) GPIO status */ struct { uint32_t : 8; @@ -2146,11 +2225,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO11_STATUS; + } GPIO11_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO11_CTRL; /*!< (@ 0x0000005C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2164,11 +2243,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO11_CTRL; + } GPIO11_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) GPIO status */ + __IOM uint32_t GPIO12_STATUS; /*!< (@ 0x00000060) GPIO status */ struct { uint32_t : 8; @@ -2188,11 +2267,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO12_STATUS; + } GPIO12_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO12_CTRL; /*!< (@ 0x00000064) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2206,11 +2285,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO12_CTRL; + } GPIO12_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000068) GPIO status */ + __IOM uint32_t GPIO13_STATUS; /*!< (@ 0x00000068) GPIO status */ struct { uint32_t : 8; @@ -2230,11 +2309,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO13_STATUS; + } GPIO13_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO13_CTRL; /*!< (@ 0x0000006C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2248,11 +2327,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO13_CTRL; + } GPIO13_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) GPIO status */ + __IOM uint32_t GPIO14_STATUS; /*!< (@ 0x00000070) GPIO status */ struct { uint32_t : 8; @@ -2272,11 +2351,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO14_STATUS; + } GPIO14_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000074) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO14_CTRL; /*!< (@ 0x00000074) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2290,11 +2369,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO14_CTRL; + } GPIO14_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000078) GPIO status */ + __IOM uint32_t GPIO15_STATUS; /*!< (@ 0x00000078) GPIO status */ struct { uint32_t : 8; @@ -2314,11 +2393,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO15_STATUS; + } GPIO15_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO15_CTRL; /*!< (@ 0x0000007C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2332,11 +2411,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO15_CTRL; + } GPIO15_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) GPIO status */ + __IOM uint32_t GPIO16_STATUS; /*!< (@ 0x00000080) GPIO status */ struct { uint32_t : 8; @@ -2356,11 +2435,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO16_STATUS; + } GPIO16_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000084) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO16_CTRL; /*!< (@ 0x00000084) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2374,11 +2453,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO16_CTRL; + } GPIO16_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000088) GPIO status */ + __IOM uint32_t GPIO17_STATUS; /*!< (@ 0x00000088) GPIO status */ struct { uint32_t : 8; @@ -2398,11 +2477,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO17_STATUS; + } GPIO17_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO17_CTRL; /*!< (@ 0x0000008C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2416,11 +2495,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO17_CTRL; + } GPIO17_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000090) GPIO status */ + __IOM uint32_t GPIO18_STATUS; /*!< (@ 0x00000090) GPIO status */ struct { uint32_t : 8; @@ -2440,11 +2519,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO18_STATUS; + } GPIO18_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000094) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO18_CTRL; /*!< (@ 0x00000094) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2458,11 +2537,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO18_CTRL; + } GPIO18_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000098) GPIO status */ + __IOM uint32_t GPIO19_STATUS; /*!< (@ 0x00000098) GPIO status */ struct { uint32_t : 8; @@ -2482,11 +2561,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO19_STATUS; + } GPIO19_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO19_CTRL; /*!< (@ 0x0000009C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2500,11 +2579,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO19_CTRL; + } GPIO19_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) GPIO status */ + __IOM uint32_t GPIO20_STATUS; /*!< (@ 0x000000A0) GPIO status */ struct { uint32_t : 8; @@ -2524,11 +2603,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO20_STATUS; + } GPIO20_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO20_CTRL; /*!< (@ 0x000000A4) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2542,11 +2621,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO20_CTRL; + } GPIO20_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) GPIO status */ + __IOM uint32_t GPIO21_STATUS; /*!< (@ 0x000000A8) GPIO status */ struct { uint32_t : 8; @@ -2566,11 +2645,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO21_STATUS; + } GPIO21_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO21_CTRL; /*!< (@ 0x000000AC) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2584,11 +2663,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO21_CTRL; + } GPIO21_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) GPIO status */ + __IOM uint32_t GPIO22_STATUS; /*!< (@ 0x000000B0) GPIO status */ struct { uint32_t : 8; @@ -2608,11 +2687,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO22_STATUS; + } GPIO22_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO22_CTRL; /*!< (@ 0x000000B4) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2626,11 +2705,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO22_CTRL; + } GPIO22_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) GPIO status */ + __IOM uint32_t GPIO23_STATUS; /*!< (@ 0x000000B8) GPIO status */ struct { uint32_t : 8; @@ -2650,11 +2729,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO23_STATUS; + } GPIO23_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000BC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO23_CTRL; /*!< (@ 0x000000BC) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2668,11 +2747,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO23_CTRL; + } GPIO23_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C0) GPIO status */ + __IOM uint32_t GPIO24_STATUS; /*!< (@ 0x000000C0) GPIO status */ struct { uint32_t : 8; @@ -2692,11 +2771,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO24_STATUS; + } GPIO24_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO24_CTRL; /*!< (@ 0x000000C4) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2710,11 +2789,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO24_CTRL; + } GPIO24_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C8) GPIO status */ + __IOM uint32_t GPIO25_STATUS; /*!< (@ 0x000000C8) GPIO status */ struct { uint32_t : 8; @@ -2734,11 +2813,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO25_STATUS; + } GPIO25_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000CC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO25_CTRL; /*!< (@ 0x000000CC) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2752,11 +2831,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO25_CTRL; + } GPIO25_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000D0) GPIO status */ + __IOM uint32_t GPIO26_STATUS; /*!< (@ 0x000000D0) GPIO status */ struct { uint32_t : 8; @@ -2776,11 +2855,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO26_STATUS; + } GPIO26_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000D4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO26_CTRL; /*!< (@ 0x000000D4) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2794,11 +2873,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO26_CTRL; + } GPIO26_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000D8) GPIO status */ + __IOM uint32_t GPIO27_STATUS; /*!< (@ 0x000000D8) GPIO status */ struct { uint32_t : 8; @@ -2818,11 +2897,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO27_STATUS; + } GPIO27_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000DC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO27_CTRL; /*!< (@ 0x000000DC) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2836,11 +2915,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO27_CTRL; + } GPIO27_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000E0) GPIO status */ + __IOM uint32_t GPIO28_STATUS; /*!< (@ 0x000000E0) GPIO status */ struct { uint32_t : 8; @@ -2860,11 +2939,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO28_STATUS; + } GPIO28_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000E4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO28_CTRL; /*!< (@ 0x000000E4) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2878,11 +2957,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO28_CTRL; + } GPIO28_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000E8) GPIO status */ + __IOM uint32_t GPIO29_STATUS; /*!< (@ 0x000000E8) GPIO status */ struct { uint32_t : 8; @@ -2902,11 +2981,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO29_STATUS; + } GPIO29_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000EC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO29_CTRL; /*!< (@ 0x000000EC) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -2920,11 +2999,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO29_CTRL; + } GPIO29_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) Raw Interrupts */ + __IOM uint32_t INTR0; /*!< (@ 0x000000F0) Raw Interrupts */ struct { __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -2959,11 +3038,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } INTR0; + } INTR0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) Raw Interrupts */ + __IOM uint32_t INTR1; /*!< (@ 0x000000F4) Raw Interrupts */ struct { __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -2998,11 +3077,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } INTR1; + } INTR1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) Raw Interrupts */ + __IOM uint32_t INTR2; /*!< (@ 0x000000F8) Raw Interrupts */ struct { __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -3037,11 +3116,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } INTR2; + } INTR2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000FC) Raw Interrupts */ + __IOM uint32_t INTR3; /*!< (@ 0x000000FC) Raw Interrupts */ struct { __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -3069,11 +3148,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } INTR3; + } INTR3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000100) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE0; /*!< (@ 0x00000100) Interrupt Enable for proc0 */ struct { __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -3108,11 +3187,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC0_INTE0; + } PROC0_INTE0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000104) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE1; /*!< (@ 0x00000104) Interrupt Enable for proc0 */ struct { __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -3147,11 +3226,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC0_INTE1; + } PROC0_INTE1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000108) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE2; /*!< (@ 0x00000108) Interrupt Enable for proc0 */ struct { __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -3186,11 +3265,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC0_INTE2; + } PROC0_INTE2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000010C) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE3; /*!< (@ 0x0000010C) Interrupt Enable for proc0 */ struct { __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -3218,11 +3297,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC0_INTE3; + } PROC0_INTE3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000110) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF0; /*!< (@ 0x00000110) Interrupt Force for proc0 */ struct { __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -3257,11 +3336,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC0_INTF0; + } PROC0_INTF0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000114) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF1; /*!< (@ 0x00000114) Interrupt Force for proc0 */ struct { __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -3296,11 +3375,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC0_INTF1; + } PROC0_INTF1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000118) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF2; /*!< (@ 0x00000118) Interrupt Force for proc0 */ struct { __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -3335,11 +3414,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC0_INTF2; + } PROC0_INTF2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000011C) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF3; /*!< (@ 0x0000011C) Interrupt Force for proc0 */ struct { __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -3367,11 +3446,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC0_INTF3; + } PROC0_INTF3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000120) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS0; /*!< (@ 0x00000120) Interrupt status after masking & forcing for proc0 */ struct { @@ -3407,11 +3486,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC0_INTS0; + } PROC0_INTS0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000124) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS1; /*!< (@ 0x00000124) Interrupt status after masking & forcing for proc0 */ struct { @@ -3447,11 +3526,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC0_INTS1; + } PROC0_INTS1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000128) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS2; /*!< (@ 0x00000128) Interrupt status after masking & forcing for proc0 */ struct { @@ -3487,11 +3566,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC0_INTS2; + } PROC0_INTS2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000012C) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS3; /*!< (@ 0x0000012C) Interrupt status after masking & forcing for proc0 */ struct { @@ -3520,11 +3599,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC0_INTS3; + } PROC0_INTS3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000130) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE0; /*!< (@ 0x00000130) Interrupt Enable for proc1 */ struct { __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -3559,11 +3638,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC1_INTE0; + } PROC1_INTE0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000134) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE1; /*!< (@ 0x00000134) Interrupt Enable for proc1 */ struct { __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -3598,11 +3677,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC1_INTE1; + } PROC1_INTE1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000138) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE2; /*!< (@ 0x00000138) Interrupt Enable for proc1 */ struct { __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -3637,11 +3716,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC1_INTE2; + } PROC1_INTE2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000013C) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE3; /*!< (@ 0x0000013C) Interrupt Enable for proc1 */ struct { __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -3669,11 +3748,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC1_INTE3; + } PROC1_INTE3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000140) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF0; /*!< (@ 0x00000140) Interrupt Force for proc1 */ struct { __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -3708,11 +3787,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC1_INTF0; + } PROC1_INTF0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000144) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF1; /*!< (@ 0x00000144) Interrupt Force for proc1 */ struct { __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -3747,11 +3826,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC1_INTF1; + } PROC1_INTF1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000148) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF2; /*!< (@ 0x00000148) Interrupt Force for proc1 */ struct { __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -3786,11 +3865,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC1_INTF2; + } PROC1_INTF2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000014C) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF3; /*!< (@ 0x0000014C) Interrupt Force for proc1 */ struct { __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -3818,11 +3897,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC1_INTF3; + } PROC1_INTF3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000150) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS0; /*!< (@ 0x00000150) Interrupt status after masking & forcing for proc1 */ struct { @@ -3858,11 +3937,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC1_INTS0; + } PROC1_INTS0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000154) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS1; /*!< (@ 0x00000154) Interrupt status after masking & forcing for proc1 */ struct { @@ -3898,11 +3977,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC1_INTS1; + } PROC1_INTS1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000158) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS2; /*!< (@ 0x00000158) Interrupt status after masking & forcing for proc1 */ struct { @@ -3938,11 +4017,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC1_INTS2; + } PROC1_INTS2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000015C) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS3; /*!< (@ 0x0000015C) Interrupt status after masking & forcing for proc1 */ struct { @@ -3971,11 +4050,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC1_INTS3; + } PROC1_INTS3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000160) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE0; /*!< (@ 0x00000160) Interrupt Enable for dormant_wake */ struct { __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -4010,11 +4089,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTE0; + } DORMANT_WAKE_INTE0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000164) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE1; /*!< (@ 0x00000164) Interrupt Enable for dormant_wake */ struct { __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -4049,11 +4128,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTE1; + } DORMANT_WAKE_INTE1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000168) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE2; /*!< (@ 0x00000168) Interrupt Enable for dormant_wake */ struct { __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -4088,11 +4167,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTE2; + } DORMANT_WAKE_INTE2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000016C) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE3; /*!< (@ 0x0000016C) Interrupt Enable for dormant_wake */ struct { __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -4120,11 +4199,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } DORMANT_WAKE_INTE3; + } DORMANT_WAKE_INTE3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000170) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF0; /*!< (@ 0x00000170) Interrupt Force for dormant_wake */ struct { __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ @@ -4159,11 +4238,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTF0; + } DORMANT_WAKE_INTF0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000174) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF1; /*!< (@ 0x00000174) Interrupt Force for dormant_wake */ struct { __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ @@ -4198,11 +4277,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTF1; + } DORMANT_WAKE_INTF1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000178) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF2; /*!< (@ 0x00000178) Interrupt Force for dormant_wake */ struct { __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ @@ -4237,11 +4316,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTF2; + } DORMANT_WAKE_INTF2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000017C) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF3; /*!< (@ 0x0000017C) Interrupt Force for dormant_wake */ struct { __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ @@ -4269,11 +4348,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } DORMANT_WAKE_INTF3; + } DORMANT_WAKE_INTF3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000180) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS0; /*!< (@ 0x00000180) Interrupt status after masking & forcing for dormant_wake */ struct { @@ -4309,11 +4388,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTS0; + } DORMANT_WAKE_INTS0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000184) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS1; /*!< (@ 0x00000184) Interrupt status after masking & forcing for dormant_wake */ struct { @@ -4349,11 +4428,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTS1; + } DORMANT_WAKE_INTS1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000188) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS2; /*!< (@ 0x00000188) Interrupt status after masking & forcing for dormant_wake */ struct { @@ -4389,11 +4468,11 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTS2; + } DORMANT_WAKE_INTS2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000018C) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS3; /*!< (@ 0x0000018C) Interrupt status after masking & forcing for dormant_wake */ struct { @@ -4422,8 +4501,8 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ uint32_t : 8; - } bit; - } DORMANT_WAKE_INTS3; + } DORMANT_WAKE_INTS3_b; + } ; } IO_BANK0_Type; /*!< Size = 400 (0x190) */ @@ -4440,7 +4519,7 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str typedef struct { /*!< (@ 0x40018000) IO_QSPI Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) GPIO status */ + __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< (@ 0x00000000) GPIO status */ struct { uint32_t : 8; @@ -4460,11 +4539,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO_QSPI_SCLK_STATUS; + } GPIO_QSPI_SCLK_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -4478,11 +4557,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO_QSPI_SCLK_CTRL; + } GPIO_QSPI_SCLK_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) GPIO status */ + __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< (@ 0x00000008) GPIO status */ struct { uint32_t : 8; @@ -4502,11 +4581,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO_QSPI_SS_STATUS; + } GPIO_QSPI_SS_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -4520,11 +4599,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO_QSPI_SS_CTRL; + } GPIO_QSPI_SS_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< (@ 0x00000010) GPIO status */ struct { uint32_t : 8; @@ -4544,11 +4623,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO_QSPI_SD0_STATUS; + } GPIO_QSPI_SD0_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -4562,11 +4641,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO_QSPI_SD0_CTRL; + } GPIO_QSPI_SD0_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< (@ 0x00000018) GPIO status */ struct { uint32_t : 8; @@ -4586,11 +4665,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO_QSPI_SD1_STATUS; + } GPIO_QSPI_SD1_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -4604,11 +4683,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO_QSPI_SD1_CTRL; + } GPIO_QSPI_SD1_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< (@ 0x00000020) GPIO status */ struct { uint32_t : 8; @@ -4628,11 +4707,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO_QSPI_SD2_STATUS; + } GPIO_QSPI_SD2_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -4646,11 +4725,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO_QSPI_SD2_CTRL; + } GPIO_QSPI_SD2_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< (@ 0x00000028) GPIO status */ struct { uint32_t : 8; @@ -4670,11 +4749,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 1; __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ uint32_t : 5; - } bit; - } GPIO_QSPI_SD3_STATUS; + } GPIO_QSPI_SD3_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ struct { __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table @@ -4688,11 +4767,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru uint32_t : 10; __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ uint32_t : 2; - } bit; - } GPIO_QSPI_SD3_CTRL; + } GPIO_QSPI_SD3_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x00000030) Raw Interrupts */ struct { __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4720,11 +4799,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE; /*!< (@ 0x00000034) Interrupt Enable for proc0 */ struct { __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4752,11 +4831,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC0_INTE; + } PROC0_INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF; /*!< (@ 0x00000038) Interrupt Force for proc0 */ struct { __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4784,11 +4863,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC0_INTF; + } PROC0_INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS; /*!< (@ 0x0000003C) Interrupt status after masking & forcing for proc0 */ struct { @@ -4817,11 +4896,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC0_INTS; + } PROC0_INTS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE; /*!< (@ 0x00000040) Interrupt Enable for proc1 */ struct { __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4849,11 +4928,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC1_INTE; + } PROC1_INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF; /*!< (@ 0x00000044) Interrupt Force for proc1 */ struct { __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4881,11 +4960,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC1_INTF; + } PROC1_INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS; /*!< (@ 0x00000048) Interrupt status after masking & forcing for proc1 */ struct { @@ -4914,11 +4993,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } PROC1_INTS; + } PROC1_INTS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE; /*!< (@ 0x0000004C) Interrupt Enable for dormant_wake */ struct { __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4946,11 +5025,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } DORMANT_WAKE_INTE; + } DORMANT_WAKE_INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF; /*!< (@ 0x00000050) Interrupt Force for dormant_wake */ struct { __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ @@ -4978,11 +5057,11 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } DORMANT_WAKE_INTF; + } DORMANT_WAKE_INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS; /*!< (@ 0x00000054) Interrupt status after masking & forcing for dormant_wake */ struct { @@ -5011,8 +5090,8 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ uint32_t : 8; - } bit; - } DORMANT_WAKE_INTS; + } DORMANT_WAKE_INTS_b; + } ; } IO_QSPI_Type; /*!< Size = 88 (0x58) */ @@ -5029,16 +5108,16 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Voltage select. Per bank control */ + __IOM uint32_t VOLTAGE_SELECT; /*!< (@ 0x00000000) Voltage select. Per bank control */ struct { __IOM uint32_t VOLTAGE_SELECT : 1; /*!< [0..0] VOLTAGE_SELECT */ uint32_t : 31; - } bit; - } VOLTAGE_SELECT; + } VOLTAGE_SELECT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Pad control register */ + __IOM uint32_t GPIO0; /*!< (@ 0x00000004) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5050,11 +5129,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO0; + } GPIO0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Pad control register */ + __IOM uint32_t GPIO1; /*!< (@ 0x00000008) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5066,11 +5145,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO1; + } GPIO1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Pad control register */ + __IOM uint32_t GPIO2; /*!< (@ 0x0000000C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5082,11 +5161,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO2; + } GPIO2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Pad control register */ + __IOM uint32_t GPIO3; /*!< (@ 0x00000010) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5098,11 +5177,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO3; + } GPIO3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Pad control register */ + __IOM uint32_t GPIO4; /*!< (@ 0x00000014) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5114,11 +5193,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO4; + } GPIO4_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Pad control register */ + __IOM uint32_t GPIO5; /*!< (@ 0x00000018) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5130,11 +5209,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO5; + } GPIO5_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Pad control register */ + __IOM uint32_t GPIO6; /*!< (@ 0x0000001C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5146,11 +5225,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO6; + } GPIO6_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Pad control register */ + __IOM uint32_t GPIO7; /*!< (@ 0x00000020) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5162,11 +5241,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO7; + } GPIO7_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Pad control register */ + __IOM uint32_t GPIO8; /*!< (@ 0x00000024) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5178,11 +5257,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO8; + } GPIO8_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Pad control register */ + __IOM uint32_t GPIO9; /*!< (@ 0x00000028) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5194,11 +5273,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO9; + } GPIO9_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Pad control register */ + __IOM uint32_t GPIO10; /*!< (@ 0x0000002C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5210,11 +5289,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO10; + } GPIO10_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Pad control register */ + __IOM uint32_t GPIO11; /*!< (@ 0x00000030) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5226,11 +5305,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO11; + } GPIO11_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Pad control register */ + __IOM uint32_t GPIO12; /*!< (@ 0x00000034) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5242,11 +5321,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO12; + } GPIO12_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Pad control register */ + __IOM uint32_t GPIO13; /*!< (@ 0x00000038) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5258,11 +5337,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO13; + } GPIO13_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Pad control register */ + __IOM uint32_t GPIO14; /*!< (@ 0x0000003C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5274,11 +5353,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO14; + } GPIO14_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Pad control register */ + __IOM uint32_t GPIO15; /*!< (@ 0x00000040) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5290,11 +5369,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO15; + } GPIO15_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Pad control register */ + __IOM uint32_t GPIO16; /*!< (@ 0x00000044) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5306,11 +5385,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO16; + } GPIO16_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Pad control register */ + __IOM uint32_t GPIO17; /*!< (@ 0x00000048) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5322,11 +5401,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO17; + } GPIO17_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Pad control register */ + __IOM uint32_t GPIO18; /*!< (@ 0x0000004C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5338,11 +5417,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO18; + } GPIO18_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Pad control register */ + __IOM uint32_t GPIO19; /*!< (@ 0x00000050) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5354,11 +5433,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO19; + } GPIO19_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Pad control register */ + __IOM uint32_t GPIO20; /*!< (@ 0x00000054) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5370,11 +5449,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO20; + } GPIO20_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Pad control register */ + __IOM uint32_t GPIO21; /*!< (@ 0x00000058) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5386,11 +5465,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO21; + } GPIO21_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Pad control register */ + __IOM uint32_t GPIO22; /*!< (@ 0x0000005C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5402,11 +5481,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO22; + } GPIO22_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Pad control register */ + __IOM uint32_t GPIO23; /*!< (@ 0x00000060) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5418,11 +5497,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO23; + } GPIO23_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Pad control register */ + __IOM uint32_t GPIO24; /*!< (@ 0x00000064) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5434,11 +5513,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO24; + } GPIO24_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Pad control register */ + __IOM uint32_t GPIO25; /*!< (@ 0x00000068) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5450,11 +5529,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO25; + } GPIO25_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Pad control register */ + __IOM uint32_t GPIO26; /*!< (@ 0x0000006C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5466,11 +5545,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO26; + } GPIO26_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Pad control register */ + __IOM uint32_t GPIO27; /*!< (@ 0x00000070) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5482,11 +5561,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO27; + } GPIO27_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Pad control register */ + __IOM uint32_t GPIO28; /*!< (@ 0x00000074) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5498,11 +5577,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO28; + } GPIO28_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Pad control register */ + __IOM uint32_t GPIO29; /*!< (@ 0x00000078) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5514,11 +5593,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO29; + } GPIO29_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) Pad control register */ + __IOM uint32_t SWCLK; /*!< (@ 0x0000007C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5530,11 +5609,11 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } SWCLK; + } SWCLK_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Pad control register */ + __IOM uint32_t SWD; /*!< (@ 0x00000080) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5546,8 +5625,8 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } SWD; + } SWD_b; + } ; } PADS_BANK0_Type; /*!< Size = 132 (0x84) */ @@ -5564,16 +5643,16 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S typedef struct { /*!< (@ 0x40020000) PADS_QSPI Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Voltage select. Per bank control */ + __IOM uint32_t VOLTAGE_SELECT; /*!< (@ 0x00000000) Voltage select. Per bank control */ struct { __IOM uint32_t VOLTAGE_SELECT : 1; /*!< [0..0] VOLTAGE_SELECT */ uint32_t : 31; - } bit; - } VOLTAGE_SELECT; + } VOLTAGE_SELECT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Pad control register */ + __IOM uint32_t GPIO_QSPI_SCLK; /*!< (@ 0x00000004) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5585,11 +5664,11 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO_QSPI_SCLK; + } GPIO_QSPI_SCLK_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD0; /*!< (@ 0x00000008) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5601,11 +5680,11 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO_QSPI_SD0; + } GPIO_QSPI_SD0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD1; /*!< (@ 0x0000000C) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5617,11 +5696,11 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO_QSPI_SD1; + } GPIO_QSPI_SD1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD2; /*!< (@ 0x00000010) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5633,11 +5712,11 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO_QSPI_SD2; + } GPIO_QSPI_SD2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD3; /*!< (@ 0x00000014) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5649,11 +5728,11 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO_QSPI_SD3; + } GPIO_QSPI_SD3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Pad control register */ + __IOM uint32_t GPIO_QSPI_SS; /*!< (@ 0x00000018) Pad control register */ struct { __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ @@ -5665,8 +5744,8 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from peripherals */ uint32_t : 24; - } bit; - } GPIO_QSPI_SS; + } GPIO_QSPI_SS_b; + } ; } PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ @@ -5683,7 +5762,7 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St typedef struct { /*!< (@ 0x40024000) XOSC Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Crystal Oscillator Control */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Crystal Oscillator Control */ struct { __IOM uint32_t FREQ_RANGE : 12; /*!< [11..0] Frequency range. This resets to 0xAA0 and cannot be @@ -5697,11 +5776,11 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */ uint32_t : 8; - } bit; - } CTRL; + } CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Crystal Oscillator Status */ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Crystal Oscillator Status */ struct { __IM uint32_t FREQ_RANGE : 2; /*!< [1..0] The current frequency range setting, always reads 0 */ @@ -5713,8 +5792,8 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu CTRL_FREQ_RANGE or DORMANT */ uint32_t : 6; __IM uint32_t STABLE : 1; /*!< [31..31] Oscillator is running and stable */ - } bit; - } STATUS; + } STATUS_b; + } ; __IOM uint32_t DORMANT; /*!< (@ 0x00000008) Crystal Oscillator pause control This is used to save power by pausing the XOSC @@ -5727,21 +5806,22 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu dormant mode */ union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Controls the startup delay */ + __IOM uint32_t STARTUP; /*!< (@ 0x0000000C) Controls the startup delay */ struct { - __IOM uint32_t DELAY : 14; /*!< [13..0] in multiples of 256*xtal_period */ + __IOM uint32_t DELAY : 14; /*!< [13..0] in multiples of 256*xtal_period. The reset value of + 0xc4 corresponds to approx 50 000 cycles. */ uint32_t : 6; __IOM uint32_t X4 : 1; /*!< [20..20] Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed - directly */ + directly. */ uint32_t : 11; - } bit; - } STARTUP; + } STARTUP_b; + } ; __IM uint32_t RESERVED[3]; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) A down counter running at the xosc frequency + __IOM uint32_t COUNT; /*!< (@ 0x0000001C) A down counter running at the xosc frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when @@ -5750,8 +5830,8 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu struct { __IOM uint32_t COUNT : 8; /*!< [7..0] COUNT */ uint32_t : 24; - } bit; - } COUNT; + } COUNT_b; + } ; } XOSC_Type; /*!< Size = 32 (0x20) */ @@ -5768,11 +5848,11 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu typedef struct { /*!< (@ 0x40028000) PLL_SYS Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control and Status + __IOM uint32_t CS; /*!< (@ 0x00000000) Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 - VCO frequency min=400MHz, max=1600MHz */ + VCO frequency min=750MHz, max=1600MHz */ struct { __IOM uint32_t REFDIV : 6; /*!< [5..0] Divides the PLL input reference clock. @@ -5786,11 +5866,11 @@ typedef struct { /*!< (@ 0x40028000) PLL_SYS Stru output will glitch when doing so. */ uint32_t : 22; __IM uint32_t LOCK : 1; /*!< [31..31] PLL is locked */ - } bit; - } CS; + } CS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Controls the PLL power modes. */ + __IOM uint32_t PWR; /*!< (@ 0x00000004) Controls the PLL power modes. */ struct { __IOM uint32_t PD : 1; /*!< [0..0] PLL powerdown @@ -5806,22 +5886,22 @@ typedef struct { /*!< (@ 0x40028000) PLL_SYS Stru To save power set high when PLL output not required or bypass=1. */ uint32_t : 26; - } bit; - } PWR; + } PWR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Feedback divisor + __IOM uint32_t FBDIV_INT; /*!< (@ 0x00000008) Feedback divisor (note: this PLL does not support fractional division) */ struct { __IOM uint32_t FBDIV_INT : 12; /*!< [11..0] see ctrl reg description for constraints */ uint32_t : 20; - } bit; - } FBDIV_INT; + } FBDIV_INT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Controls the PLL post dividers for the primary + __IOM uint32_t PRIM; /*!< (@ 0x0000000C) Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) @@ -5834,8 +5914,8 @@ typedef struct { /*!< (@ 0x40028000) PLL_SYS Stru uint32_t : 1; __IOM uint32_t POSTDIV1 : 3; /*!< [18..16] divide by 1-7 */ uint32_t : 13; - } bit; - } PRIM; + } PRIM_b; + } ; } PLL_SYS_Type; /*!< Size = 16 (0x10) */ @@ -5852,7 +5932,7 @@ typedef struct { /*!< (@ 0x40028000) PLL_SYS Stru typedef struct { /*!< (@ 0x40030000) BUSCTRL Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Set the priority of each master for bus arbitration. */ + __IOM uint32_t BUS_PRIORITY; /*!< (@ 0x00000000) Set the priority of each master for bus arbitration. */ struct { __IOM uint32_t PROC0 : 1; /*!< [0..0] 0 - low priority, 1 - high priority */ @@ -5863,11 +5943,11 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru uint32_t : 3; __IOM uint32_t DMA_W : 1; /*!< [12..12] 0 - low priority, 1 - high priority */ uint32_t : 19; - } bit; - } BUS_PRIORITY; + } BUS_PRIORITY_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Bus priority acknowledge */ + __IOM uint32_t BUS_PRIORITY_ACK; /*!< (@ 0x00000004) Bus priority acknowledge */ struct { __IM uint32_t BUS_PRIORITY_ACK : 1; /*!< [0..0] Goes to 1 once all arbiters have registered the new global @@ -5876,11 +5956,11 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru nonsequential access. In normal circumstances this will happen almost immediately. */ uint32_t : 31; - } bit; - } BUS_PRIORITY_ACK; + } BUS_PRIORITY_ACK_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Bus fabric performance counter 0 */ + __IOM uint32_t PERFCTR0; /*!< (@ 0x00000008) Bus fabric performance counter 0 */ struct { __IOM uint32_t PERFCTR0 : 24; /*!< [23..0] Busfabric saturating performance counter 0 @@ -5888,20 +5968,22 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru Write any value to clear. Select an event to count using PERFSEL0 */ uint32_t : 8; - } bit; - } PERFCTR0; + } PERFCTR0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Bus fabric performance event select for PERFCTR0 */ + __IOM uint32_t PERFSEL0; /*!< (@ 0x0000000C) Bus fabric performance event select for PERFCTR0 */ struct { - __IOM uint32_t PERFSEL0 : 5; /*!< [4..0] Select a performance event for PERFCTR0 */ + __IOM uint32_t PERFSEL0 : 5; /*!< [4..0] Select an event for PERFCTR0. Count either contested + accesses, or all accesses, on a downstream port of the + main crossbar. */ uint32_t : 27; - } bit; - } PERFSEL0; + } PERFSEL0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Bus fabric performance counter 1 */ + __IOM uint32_t PERFCTR1; /*!< (@ 0x00000010) Bus fabric performance counter 1 */ struct { __IOM uint32_t PERFCTR1 : 24; /*!< [23..0] Busfabric saturating performance counter 1 @@ -5909,20 +5991,22 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru Write any value to clear. Select an event to count using PERFSEL1 */ uint32_t : 8; - } bit; - } PERFCTR1; + } PERFCTR1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Bus fabric performance event select for PERFCTR1 */ + __IOM uint32_t PERFSEL1; /*!< (@ 0x00000014) Bus fabric performance event select for PERFCTR1 */ struct { - __IOM uint32_t PERFSEL1 : 5; /*!< [4..0] Select a performance event for PERFCTR1 */ + __IOM uint32_t PERFSEL1 : 5; /*!< [4..0] Select an event for PERFCTR1. Count either contested + accesses, or all accesses, on a downstream port of the + main crossbar. */ uint32_t : 27; - } bit; - } PERFSEL1; + } PERFSEL1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Bus fabric performance counter 2 */ + __IOM uint32_t PERFCTR2; /*!< (@ 0x00000018) Bus fabric performance counter 2 */ struct { __IOM uint32_t PERFCTR2 : 24; /*!< [23..0] Busfabric saturating performance counter 2 @@ -5930,20 +6014,22 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru Write any value to clear. Select an event to count using PERFSEL2 */ uint32_t : 8; - } bit; - } PERFCTR2; + } PERFCTR2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Bus fabric performance event select for PERFCTR2 */ + __IOM uint32_t PERFSEL2; /*!< (@ 0x0000001C) Bus fabric performance event select for PERFCTR2 */ struct { - __IOM uint32_t PERFSEL2 : 5; /*!< [4..0] Select a performance event for PERFCTR2 */ + __IOM uint32_t PERFSEL2 : 5; /*!< [4..0] Select an event for PERFCTR2. Count either contested + accesses, or all accesses, on a downstream port of the + main crossbar. */ uint32_t : 27; - } bit; - } PERFSEL2; + } PERFSEL2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Bus fabric performance counter 3 */ + __IOM uint32_t PERFCTR3; /*!< (@ 0x00000020) Bus fabric performance counter 3 */ struct { __IOM uint32_t PERFCTR3 : 24; /*!< [23..0] Busfabric saturating performance counter 3 @@ -5951,17 +6037,19 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru Write any value to clear. Select an event to count using PERFSEL3 */ uint32_t : 8; - } bit; - } PERFCTR3; + } PERFCTR3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Bus fabric performance event select for PERFCTR3 */ + __IOM uint32_t PERFSEL3; /*!< (@ 0x00000024) Bus fabric performance event select for PERFCTR3 */ struct { - __IOM uint32_t PERFSEL3 : 5; /*!< [4..0] Select a performance event for PERFCTR3 */ + __IOM uint32_t PERFSEL3 : 5; /*!< [4..0] Select an event for PERFCTR3. Count either contested + accesses, or all accesses, on a downstream port of the + main crossbar. */ uint32_t : 27; - } bit; - } PERFSEL3; + } PERFSEL3_b; + } ; } BUSCTRL_Type; /*!< Size = 40 (0x28) */ @@ -5978,7 +6066,7 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru typedef struct { /*!< (@ 0x40034000) UART0 Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Data Register, UARTDR */ + __IOM uint32_t UARTDR; /*!< (@ 0x00000000) Data Register, UARTDR */ struct { __IOM uint32_t DATA : 8; /*!< [7..0] Receive (read) data character. Transmit (write) data @@ -6006,11 +6094,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct 0 once there is an empty space in the FIFO and a new character can be written to it. */ uint32_t : 20; - } bit; - } UARTDR; + } UARTDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Receive Status Register/Error Clear Register, + __IOM uint32_t UARTRSR; /*!< (@ 0x00000004) Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ struct { @@ -6034,7 +6122,7 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) - */ + an */ __IOM uint32_t OE : 1; /*!< [3..3] Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because @@ -6042,12 +6130,12 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. */ uint32_t : 28; - } bit; - } UARTRSR; + } UARTRSR_b; + } ; __IM uint32_t RESERVED[4]; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Flag Register, UARTFR */ + __IOM uint32_t UARTFR; /*!< (@ 0x00000018) Flag Register, UARTFR */ struct { __IM uint32_t CTS : 1; /*!< [0..0] Clear to send. This bit is the complement of the UART @@ -6091,42 +6179,42 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. */ uint32_t : 23; - } bit; - } UARTFR; + } UARTFR_b; + } ; __IM uint32_t RESERVED1; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) IrDA Low-Power Counter Register, UARTILPR */ + __IOM uint32_t UARTILPR; /*!< (@ 0x00000020) IrDA Low-Power Counter Register, UARTILPR */ struct { __IOM uint32_t ILPDVSR : 8; /*!< [7..0] 8-bit low-power divisor value. These bits are cleared to 0 at reset. */ uint32_t : 24; - } bit; - } UARTILPR; + } UARTILPR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Integer Baud Rate Register, UARTIBRD */ + __IOM uint32_t UARTIBRD; /*!< (@ 0x00000024) Integer Baud Rate Register, UARTIBRD */ struct { __IOM uint32_t BAUD_DIVINT : 16; /*!< [15..0] The integer baud rate divisor. These bits are cleared to 0 on reset. */ uint32_t : 16; - } bit; - } UARTIBRD; + } UARTIBRD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Fractional Baud Rate Register, UARTFBRD */ + __IOM uint32_t UARTFBRD; /*!< (@ 0x00000028) Fractional Baud Rate Register, UARTFBRD */ struct { __IOM uint32_t BAUD_DIVFRAC : 6; /*!< [5..0] The fractional baud rate divisor. These bits are cleared to 0 on reset. */ uint32_t : 26; - } bit; - } UARTFBRD; + } UARTFBRD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Line Control Register, UARTLCR_H */ + __IOM uint32_t UARTLCR_H; /*!< (@ 0x0000002C) Line Control Register, UARTLCR_H */ struct { __IOM uint32_t BRK : 1; /*!< [0..0] Send break. If this bit is set to 1, a low-level is continually @@ -6161,11 +6249,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. */ uint32_t : 24; - } bit; - } UARTLCR_H; + } UARTLCR_H_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Control Register, UARTCR */ + __IOM uint32_t UARTCR; /*!< (@ 0x00000030) Control Register, UARTCR */ struct { __IOM uint32_t UARTEN : 1; /*!< [0..0] UART enable: 0 = UART is disabled. If the UART is disabled @@ -6198,7 +6286,7 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing - is finished. This feature reduces the amount of ext */ + is finished. This feature reduces the amount of exter */ __IOM uint32_t TXE : 1; /*!< [8..8] Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the @@ -6235,11 +6323,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. */ uint32_t : 16; - } bit; - } UARTCR; + } UARTCR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Interrupt FIFO Level Select Register, UARTIFLS */ + __IOM uint32_t UARTIFLS; /*!< (@ 0x00000034) Interrupt FIFO Level Select Register, UARTIFLS */ struct { __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] Transmit interrupt FIFO level select. The trigger points @@ -6255,11 +6343,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. */ uint32_t : 26; - } bit; - } UARTIFLS; + } UARTIFLS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt Mask Set/Clear Register, UARTIMSC */ + __IOM uint32_t UARTIMSC; /*!< (@ 0x00000038) Interrupt Mask Set/Clear Register, UARTIMSC */ struct { __IOM uint32_t RIMIM : 1; /*!< [0..0] nUARTRI modem interrupt mask. A read returns the current @@ -6307,11 +6395,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. */ uint32_t : 21; - } bit; - } UARTIMSC; + } UARTIMSC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Raw Interrupt Status Register, UARTRIS */ + __IOM uint32_t UARTRIS; /*!< (@ 0x0000003C) Raw Interrupt Status Register, UARTRIS */ struct { __IM uint32_t RIRMIS : 1; /*!< [0..0] nUARTRI modem interrupt status. Returns the raw interrupt @@ -6337,11 +6425,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct __IM uint32_t OERIS : 1; /*!< [10..10] Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. */ uint32_t : 21; - } bit; - } UARTRIS; + } UARTRIS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Masked Interrupt Status Register, UARTMIS */ + __IOM uint32_t UARTMIS; /*!< (@ 0x00000040) Masked Interrupt Status Register, UARTMIS */ struct { __IM uint32_t RIMMIS : 1; /*!< [0..0] nUARTRI modem masked interrupt status. Returns the masked @@ -6367,11 +6455,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct __IM uint32_t OEMIS : 1; /*!< [10..10] Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. */ uint32_t : 21; - } bit; - } UARTMIS; + } UARTMIS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Interrupt Clear Register, UARTICR */ + __IOM uint32_t UARTICR; /*!< (@ 0x00000044) Interrupt Clear Register, UARTICR */ struct { __IOM uint32_t RIMIC : 1; /*!< [0..0] nUARTRI modem interrupt clear. Clears the UARTRIINTR @@ -6393,11 +6481,11 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct __IOM uint32_t OEIC : 1; /*!< [10..10] Overrun error interrupt clear. Clears the UARTOEINTR interrupt. */ uint32_t : 21; - } bit; - } UARTICR; + } UARTICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) DMA Control Register, UARTDMACR */ + __IOM uint32_t UARTDMACR; /*!< (@ 0x00000048) DMA Control Register, UARTDMACR */ struct { __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA enable. If this bit is set to 1, DMA for @@ -6408,84 +6496,84 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. */ uint32_t : 29; - } bit; - } UARTDMACR; + } UARTDMACR_b; + } ; __IM uint32_t RESERVED2[997]; union { - __IOM uint32_t reg; /*!< (@ 0x00000FE0) UARTPeriphID0 Register */ + __IOM uint32_t UARTPERIPHID0; /*!< (@ 0x00000FE0) UARTPeriphID0 Register */ struct { __IM uint32_t PARTNUMBER0 : 8; /*!< [7..0] These bits read back as 0x11 */ uint32_t : 24; - } bit; - } UARTPERIPHID0; + } UARTPERIPHID0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FE4) UARTPeriphID1 Register */ + __IOM uint32_t UARTPERIPHID1; /*!< (@ 0x00000FE4) UARTPeriphID1 Register */ struct { __IM uint32_t PARTNUMBER1 : 4; /*!< [3..0] These bits read back as 0x0 */ __IM uint32_t DESIGNER0 : 4; /*!< [7..4] These bits read back as 0x1 */ uint32_t : 24; - } bit; - } UARTPERIPHID1; + } UARTPERIPHID1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FE8) UARTPeriphID2 Register */ + __IOM uint32_t UARTPERIPHID2; /*!< (@ 0x00000FE8) UARTPeriphID2 Register */ struct { __IM uint32_t DESIGNER1 : 4; /*!< [3..0] These bits read back as 0x4 */ __IM uint32_t REVISION : 4; /*!< [7..4] This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 */ uint32_t : 24; - } bit; - } UARTPERIPHID2; + } UARTPERIPHID2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FEC) UARTPeriphID3 Register */ + __IOM uint32_t UARTPERIPHID3; /*!< (@ 0x00000FEC) UARTPeriphID3 Register */ struct { __IM uint32_t CONFIGURATION : 8; /*!< [7..0] These bits read back as 0x00 */ uint32_t : 24; - } bit; - } UARTPERIPHID3; + } UARTPERIPHID3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FF0) UARTPCellID0 Register */ + __IOM uint32_t UARTPCELLID0; /*!< (@ 0x00000FF0) UARTPCellID0 Register */ struct { __IM uint32_t UARTPCELLID0 : 8; /*!< [7..0] These bits read back as 0x0D */ uint32_t : 24; - } bit; - } UARTPCELLID0; + } UARTPCELLID0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FF4) UARTPCellID1 Register */ + __IOM uint32_t UARTPCELLID1; /*!< (@ 0x00000FF4) UARTPCellID1 Register */ struct { __IM uint32_t UARTPCELLID1 : 8; /*!< [7..0] These bits read back as 0xF0 */ uint32_t : 24; - } bit; - } UARTPCELLID1; + } UARTPCELLID1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FF8) UARTPCellID2 Register */ + __IOM uint32_t UARTPCELLID2; /*!< (@ 0x00000FF8) UARTPCellID2 Register */ struct { __IM uint32_t UARTPCELLID2 : 8; /*!< [7..0] These bits read back as 0x05 */ uint32_t : 24; - } bit; - } UARTPCELLID2; + } UARTPCELLID2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FFC) UARTPCellID3 Register */ + __IOM uint32_t UARTPCELLID3; /*!< (@ 0x00000FFC) UARTPCellID3 Register */ struct { __IM uint32_t UARTPCELLID3 : 8; /*!< [7..0] These bits read back as 0xB1 */ uint32_t : 24; - } bit; - } UARTPCELLID3; + } UARTPCELLID3_b; + } ; } UART0_Type; /*!< Size = 4096 (0x1000) */ @@ -6502,7 +6590,7 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct typedef struct { /*!< (@ 0x4003C000) SPI0 Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control register 0, SSPCR0 on page 3-4 */ + __IOM uint32_t SSPCR0; /*!< (@ 0x00000000) Control register 0, SSPCR0 on page 3-4 */ struct { __IOM uint32_t DSS : 4; /*!< [3..0] Data Size Select: 0000 Reserved, undefined operation. @@ -6525,11 +6613,11 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. */ uint32_t : 16; - } bit; - } SSPCR0; + } SSPCR0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Control register 1, SSPCR1 on page 3-5 */ + __IOM uint32_t SSPCR1; /*!< (@ 0x00000004) Control register 1, SSPCR1 on page 3-5 */ struct { __IOM uint32_t LBM : 1; /*!< [0..0] Loop back mode: 0 Normal serial port operation enabled. @@ -6549,13 +6637,13 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output - in sl */ + in slav */ uint32_t : 28; - } bit; - } SSPCR1; + } SSPCR1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Data register, SSPDR on page 3-6 */ + __IOM uint32_t SSPDR; /*!< (@ 0x00000008) Data register, SSPDR on page 3-6 */ struct { __IOM uint32_t DATA : 16; /*!< [15..0] Transmit/Receive FIFO: Read Receive FIFO. Write Transmit @@ -6564,11 +6652,11 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. */ uint32_t : 16; - } bit; - } SSPDR; + } SSPDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Status register, SSPSR on page 3-7 */ + __IOM uint32_t SSPSR; /*!< (@ 0x0000000C) Status register, SSPSR on page 3-7 */ struct { __IM uint32_t TFE : 1; /*!< [0..0] Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. @@ -6583,22 +6671,22 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu currently transmitting and/or receiving a frame or the transmit FIFO is not empty. */ uint32_t : 27; - } bit; - } SSPSR; + } SSPSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Clock prescale register, SSPCPSR on page 3-8 */ + __IOM uint32_t SSPCPSR; /*!< (@ 0x00000010) Clock prescale register, SSPCPSR on page 3-8 */ struct { __IOM uint32_t CPSDVSR : 8; /*!< [7..0] Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. */ uint32_t : 24; - } bit; - } SSPCPSR; + } SSPCPSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Interrupt mask set or clear register, SSPIMSC + __IOM uint32_t SSPIMSC; /*!< (@ 0x00000014) Interrupt mask set or clear register, SSPIMSC on page 3-9 */ struct { @@ -6616,11 +6704,11 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. */ uint32_t : 28; - } bit; - } SSPIMSC; + } SSPIMSC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Raw interrupt status register, SSPRIS on page + __IOM uint32_t SSPRIS; /*!< (@ 0x00000018) Raw interrupt status register, SSPRIS on page 3-10 */ struct { @@ -6633,11 +6721,11 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu __IM uint32_t TXRIS : 1; /*!< [3..3] Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt */ uint32_t : 28; - } bit; - } SSPRIS; + } SSPRIS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Masked interrupt status register, SSPMIS on page + __IOM uint32_t SSPMIS; /*!< (@ 0x0000001C) Masked interrupt status register, SSPMIS on page 3-11 */ struct { @@ -6650,21 +6738,21 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu __IM uint32_t TXMIS : 1; /*!< [3..3] Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt */ uint32_t : 28; - } bit; - } SSPMIS; + } SSPMIS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Interrupt clear register, SSPICR on page 3-11 */ + __IOM uint32_t SSPICR; /*!< (@ 0x00000020) Interrupt clear register, SSPICR on page 3-11 */ struct { __IOM uint32_t RORIC : 1; /*!< [0..0] Clears the SSPRORINTR interrupt */ __IOM uint32_t RTIC : 1; /*!< [1..1] Clears the SSPRTINTR interrupt */ uint32_t : 30; - } bit; - } SSPICR; + } SSPICR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) DMA control register, SSPDMACR on page 3-12 */ + __IOM uint32_t SSPDMACR; /*!< (@ 0x00000024) DMA control register, SSPDMACR on page 3-12 */ struct { __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA Enable. If this bit is set to 1, DMA for @@ -6672,91 +6760,91 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu __IOM uint32_t TXDMAE : 1; /*!< [1..1] Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. */ uint32_t : 30; - } bit; - } SSPDMACR; + } SSPDMACR_b; + } ; __IM uint32_t RESERVED[1006]; union { - __IOM uint32_t reg; /*!< (@ 0x00000FE0) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID0; /*!< (@ 0x00000FE0) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ struct { __IM uint32_t PARTNUMBER0 : 8; /*!< [7..0] These bits read back as 0x22 */ uint32_t : 24; - } bit; - } SSPPERIPHID0; + } SSPPERIPHID0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FE4) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID1; /*!< (@ 0x00000FE4) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ struct { __IM uint32_t PARTNUMBER1 : 4; /*!< [3..0] These bits read back as 0x0 */ __IM uint32_t DESIGNER0 : 4; /*!< [7..4] These bits read back as 0x1 */ uint32_t : 24; - } bit; - } SSPPERIPHID1; + } SSPPERIPHID1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FE8) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID2; /*!< (@ 0x00000FE8) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ struct { __IM uint32_t DESIGNER1 : 4; /*!< [3..0] These bits read back as 0x4 */ __IM uint32_t REVISION : 4; /*!< [7..4] These bits return the peripheral revision */ uint32_t : 24; - } bit; - } SSPPERIPHID2; + } SSPPERIPHID2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FEC) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID3; /*!< (@ 0x00000FEC) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ struct { __IM uint32_t CONFIGURATION : 8; /*!< [7..0] These bits read back as 0x00 */ uint32_t : 24; - } bit; - } SSPPERIPHID3; + } SSPPERIPHID3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FF0) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID0; /*!< (@ 0x00000FF0) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ struct { __IM uint32_t SSPPCELLID0 : 8; /*!< [7..0] These bits read back as 0x0D */ uint32_t : 24; - } bit; - } SSPPCELLID0; + } SSPPCELLID0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FF4) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID1; /*!< (@ 0x00000FF4) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ struct { __IM uint32_t SSPPCELLID1 : 8; /*!< [7..0] These bits read back as 0xF0 */ uint32_t : 24; - } bit; - } SSPPCELLID1; + } SSPPCELLID1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FF8) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID2; /*!< (@ 0x00000FF8) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ struct { __IM uint32_t SSPPCELLID2 : 8; /*!< [7..0] These bits read back as 0x05 */ uint32_t : 24; - } bit; - } SSPPCELLID2; + } SSPPCELLID2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000FFC) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID3; /*!< (@ 0x00000FFC) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ struct { __IM uint32_t SSPPCELLID3 : 8; /*!< [7..0] These bits read back as 0xB1 */ uint32_t : 24; - } bit; - } SSPPCELLID3; + } SSPPCELLID3_b; + } ; } SPI0_Type; /*!< Size = 4096 (0x1000) */ @@ -6767,13 +6855,82 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu /** - * @brief DW_apb_i2c address block (I2C0) + * @brief DW_apb_i2c address block\n\n + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n + IC_ULTRA_FAST_MODE ................ 0x0\n + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n + IC_UFM_SCL_LOW_COUNT .............. 0x0008\n + IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n + IC_TX_TL .......................... 0x0\n + IC_TX_CMD_BLOCK ................... 0x1\n + IC_HAS_DMA ........................ 0x1\n + IC_HAS_ASYNC_FIFO ................. 0x0\n + IC_SMBUS_ARP ...................... 0x0\n + IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n + IC_INTR_IO ........................ 0x1\n + IC_MASTER_MODE .................... 0x1\n + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n + IC_INTR_POL ....................... 0x1\n + IC_OPTIONAL_SAR ................... 0x0\n + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n + IC_DEFAULT_SLAVE_ADDR ............. 0x055\n + IC_DEFAULT_HS_SPKLEN .............. 0x1\n + IC_FS_SCL_HIGH_COUNT .............. 0x0006\n + IC_HS_SCL_LOW_COUNT ............... 0x0008\n + IC_DEVICE_ID_VALUE ................ 0x0\n + IC_10BITADDR_MASTER ............... 0x0\n + IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n + IC_DEFAULT_FS_SPKLEN .............. 0x7\n + IC_ADD_ENCODED_PARAMS ............. 0x0\n + IC_DEFAULT_SDA_HOLD ............... 0x000001\n + IC_DEFAULT_SDA_SETUP .............. 0x64\n + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n + IC_CLOCK_PERIOD ................... 100\n + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n + IC_RESTART_EN ..................... 0x1\n + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n + IC_BUS_CLEAR_FEATURE .............. 0x0\n + IC_CAP_LOADING .................... 100\n + IC_FS_SCL_LOW_COUNT ............... 0x000d\n + APB_DATA_WIDTH .................... 32\n + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_SLV_DATA_NACK_ONLY ............. 0x1\n + IC_10BITADDR_SLAVE ................ 0x0\n + IC_CLK_TYPE ....................... 0x0\n + IC_SMBUS_UDID_MSB ................. 0x0\n + IC_SMBUS_SUSPEND_ALERT ............ 0x0\n + IC_HS_SCL_HIGH_COUNT .............. 0x0006\n + IC_SLV_RESTART_DET_EN ............. 0x1\n + IC_SMBUS .......................... 0x0\n + IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n + IC_USE_COUNTS ..................... 0x0\n + IC_RX_BUFFER_DEPTH ................ 16\n + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_RX_FULL_HLD_BUS_EN ............. 0x1\n + IC_SLAVE_DISABLE .................. 0x1\n + IC_RX_TL .......................... 0x0\n + IC_DEVICE_ID ...................... 0x0\n + IC_HC_COUNT_VALUES ................ 0x0\n + I2C_DYNAMIC_TAR_UPDATE ............ 0\n + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n + IC_HS_MASTER_CODE ................. 0x1\n + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n + IC_SS_SCL_HIGH_COUNT .............. 0x0028\n + IC_SS_SCL_LOW_COUNT ............... 0x002f\n + IC_MAX_SPEED_MODE ................. 0x2\n + IC_STAT_FOR_CLK_STRETCH ........... 0x0\n + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n + IC_DEFAULT_UFM_SPKLEN ............. 0x1\n + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) */ typedef struct { /*!< (@ 0x40044000) I2C0 Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) I2C Control Register. This register can be written + __IOM uint32_t IC_CON; /*!< (@ 0x00000000) I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have @@ -6798,7 +6955,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware - updates this register */ + updates this register wi */ __IOM uint32_t IC_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve @@ -6817,7 +6974,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing - a read operation with a 10-bit address By repla */ + a read operation with a 10-bit address By replaci */ __IOM uint32_t IC_SLAVE_DISABLE : 1; /*!< [6..6] This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. @@ -6851,11 +7008,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu __IM uint32_t STOP_DET_IF_MASTER_ACTIVE : 1;/*!< [10..10] Master issues the STOP_DET interrupt irrespective of whether master is active or not */ uint32_t : 21; - } bit; - } IC_CON; + } IC_CON_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) I2C Target Address Register + __IOM uint32_t IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be @@ -6869,7 +7026,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if - DW_ap */ + DW_apb_ */ struct { __IOM uint32_t IC_TAR : 10; /*!< [9..0] This is the target address for any master transaction. @@ -6897,11 +7054,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 */ uint32_t : 20; - } bit; - } IC_TAR; + } IC_TAR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) I2C Slave Address Register */ + __IOM uint32_t IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ struct { __IOM uint32_t IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the I2C is operating @@ -6914,14 +7071,14 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if - you */ + you pr */ uint32_t : 22; - } bit; - } IC_SAR; + } IC_SAR_b; + } ; __IM uint32_t RESERVED; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register; this + __IOM uint32_t IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. @@ -6933,7 +7090,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to - continue acknowledgi */ + continue acknowledging */ struct { __IOM uint32_t DAT : 8; /*!< [7..0] This register contains the data to be transmitted or @@ -6966,7 +7123,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving - data */ + data by */ __IOM uint32_t RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is issued before the byte is sent or received. @@ -6977,7 +7134,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if - the transfer direction is changing from the previous com */ + the transfer direction is changing from the previous comma */ __IM uint32_t FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. @@ -6991,13 +7148,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform - the second read [15:8] (offset 0x11) */ + the second read [15:8] (offset 0x11) i */ uint32_t : 20; - } bit; - } IC_DATA_CMD; + } IC_DATA_CMD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ struct { __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction @@ -7010,13 +7167,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values - less */ + less th */ uint32_t : 16; - } bit; - } IC_SS_SCL_HCNT; + } IC_SS_SCL_HCNT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ struct { __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction @@ -7029,13 +7186,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values - less th */ + less than */ uint32_t : 16; - } bit; - } IC_SS_SCL_LCNT; + } IC_SS_SCL_LCNT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Fast Mode or Fast Mode Plus I2C Clock SCL High + __IOM uint32_t IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ struct { @@ -7048,13 +7205,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be - written only when the I2C interface is */ + written only when the I2C interface is di */ uint32_t : 16; - } bit; - } IC_FS_SCL_HCNT; + } IC_FS_SCL_HCNT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Fast Mode or Fast Mode Plus I2C Clock SCL Low + __IOM uint32_t IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ struct { @@ -7069,14 +7226,14 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface - */ + is */ uint32_t : 16; - } bit; - } IC_FS_SCL_LCNT; + } IC_FS_SCL_LCNT_b; + } ; __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) I2C Interrupt Status Register + __IOM uint32_t IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These @@ -7138,16 +7295,12 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu R_RESTART_DET bit. Reset value: 0x0 */ - __IM uint32_t R_MASTER_ON_HOLD : 1; /*!< [13..13] See IC_RAW_INTR_STAT for a detailed description of - R_MASTER_ON_HOLD bit. - - Reset value: 0x0 */ - uint32_t : 18; - } bit; - } IC_INTR_STAT; + uint32_t : 19; + } IC_INTR_STAT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) I2C Interrupt Mask Register. + __IOM uint32_t IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; @@ -7207,16 +7360,12 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu register. Reset value: 0x0 */ - __IM uint32_t M_MASTER_ON_HOLD_READ_ONLY : 1;/*!< [13..13] This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD - interrupt in IC_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 18; - } bit; - } IC_INTR_MASK; + uint32_t : 19; + } IC_INTR_MASK_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register + __IOM uint32_t IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show @@ -7239,7 +7388,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) - is programmed to HIG */ + is programmed to HIGH, */ __IM uint32_t RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. @@ -7266,7 +7415,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift - register for the most recently popped command is complet */ + register for the most recently popped command is completed */ __IM uint32_t RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait @@ -7275,7 +7424,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 - just after the processor reads the IC_CLR_RD_REQ registe */ + just after the processor reads the IC_CLR_RD_REQ register. */ __IM uint32_t TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as @@ -7286,7 +7435,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by - any of the eve */ + any of the event */ __IM uint32_t RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the @@ -7312,7 +7461,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address - by generating ACK. The STOP_DET interrupt is generat */ + by generating ACK. The STOP_DET interrupt is generated */ __IM uint32_t START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. @@ -7337,17 +7486,12 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu does not generate the RESTART_DET interrupt. */ - __IM uint32_t MASTER_ON_HOLD : 1; /*!< [13..13] Indicates whether master is holding the bus and TX - FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 - and IC_EMPTYFIFO_HOLD_MASTER_EN=1. - - Reset value: 0x0 */ - uint32_t : 18; - } bit; - } IC_RAW_INTR_STAT; + uint32_t : 19; + } IC_RAW_INTR_STAT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + __IOM uint32_t IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ struct { __IOM uint32_t RX_TL : 8; /*!< [7..0] Receive FIFO Threshold Level. @@ -7360,13 +7504,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 - */ + en */ uint32_t : 24; - } bit; - } IC_RX_TL; + } IC_RX_TL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + __IOM uint32_t IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ struct { __IOM uint32_t TX_TL : 8; /*!< [7..0] Transmit FIFO Threshold Level. @@ -7380,11 +7524,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. */ uint32_t : 24; - } bit; - } IC_TX_TL; + } IC_TX_TL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + __IOM uint32_t IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ struct { __IM uint32_t CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined interrupt, all @@ -7395,11 +7539,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_INTR; + } IC_CLR_INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ struct { __IM uint32_t CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear the RX_UNDER interrupt (bit @@ -7407,11 +7551,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_RX_UNDER; + } IC_CLR_RX_UNDER_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ struct { __IM uint32_t CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the RX_OVER interrupt (bit @@ -7419,11 +7563,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_RX_OVER; + } IC_CLR_RX_OVER_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ struct { __IM uint32_t CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the TX_OVER interrupt (bit @@ -7431,11 +7575,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_TX_OVER; + } IC_CLR_TX_OVER_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + __IOM uint32_t IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ struct { __IM uint32_t CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the RD_REQ interrupt (bit @@ -7443,11 +7587,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_RD_REQ; + } IC_CLR_RD_REQ_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + __IOM uint32_t IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ struct { __IM uint32_t CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT interrupt (bit @@ -7459,11 +7603,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_TX_ABRT; + } IC_CLR_TX_ABRT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + __IOM uint32_t IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ struct { __IM uint32_t CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the RX_DONE interrupt (bit @@ -7471,11 +7615,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_RX_DONE; + } IC_CLR_RX_DONE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + __IOM uint32_t IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ struct { __IM uint32_t CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears the ACTIVITY interrupt if @@ -7489,11 +7633,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_ACTIVITY; + } IC_CLR_ACTIVITY_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + __IOM uint32_t IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ struct { __IM uint32_t CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear the STOP_DET interrupt (bit @@ -7501,11 +7645,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_STOP_DET; + } IC_CLR_STOP_DET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + __IOM uint32_t IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ struct { __IM uint32_t CLR_START_DET : 1; /*!< [0..0] Read this register to clear the START_DET interrupt (bit @@ -7513,11 +7657,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_START_DET; + } IC_CLR_START_DET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + __IOM uint32_t IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ struct { __IM uint32_t CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear the GEN_CALL interrupt (bit @@ -7525,11 +7669,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_GEN_CALL; + } IC_CLR_GEN_CALL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) I2C Enable Register */ + __IOM uint32_t IC_ENABLE; /*!< (@ 0x0000006C) I2C Enable Register */ struct { __IOM uint32_t ENABLE : 1; /*!< [0..0] Controls whether the DW_apb_i2c is enabled. - 0: Disables @@ -7541,7 +7685,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT - register are stil */ + register are still */ __IOM uint32_t ABORT : 1; /*!< [1..1] When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in @@ -7550,7 +7694,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing - the current transfer, then sets the TX_A */ + the current transfer, then sets the TX_ABO */ __IOM uint32_t TX_CMD_BLOCK : 1; /*!< [2..2] In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, @@ -7559,13 +7703,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK - bit is unset. Reset value: IC_TX_CMD_B */ + bit is unset. Reset value: IC_TX_CMD_BLO */ uint32_t : 29; - } bit; - } IC_ENABLE; + } IC_ENABLE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) I2C Status Register + __IOM uint32_t IC_STATUS; /*!< (@ 0x00000070) I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. @@ -7615,11 +7759,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 */ uint32_t : 25; - } bit; - } IC_STATUS; + } IC_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register This register + __IOM uint32_t IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There @@ -7636,11 +7780,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 27; - } bit; - } IC_TXFLR; + } IC_TXFLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000078) I2C Receive FIFO Level Register This register + __IOM uint32_t IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever @@ -7656,11 +7800,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 27; - } bit; - } IC_RXFLR; + } IC_RXFLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register + __IOM uint32_t IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register The bits [15:0] of this register are used to control the hold time of SDA during transmit @@ -7675,7 +7819,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Writes to this register succeed only when IC_ENABLE[0]=0. - The values in this register a */ + The values in this register are */ struct { __IOM uint32_t IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in units of ic_clk period, @@ -7687,11 +7831,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: IC_DEFAULT_SDA_HOLD[23:16]. */ uint32_t : 8; - } bit; - } IC_SDA_HOLD; + } IC_SDA_HOLD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) I2C Transmit Abort Source Register + __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for @@ -7703,7 +7847,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). - Once the source of the AB */ + Once the source of the ABRT */ struct { __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] This field indicates that the Master is in 7-bit addressing @@ -7777,7 +7921,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then - gets reasserted. When this field is set */ + gets reasserted. When this field is set t */ __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. @@ -7817,7 +7961,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 - Role */ + Role of */ __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< [15..15] 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. @@ -7839,11 +7983,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter */ - } bit; - } IC_TX_ABRT_SOURCE; + } IC_TX_ABRT_SOURCE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Generate Slave Data NACK Register + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c @@ -7856,7 +8000,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu A write can occur on this register if both of the following conditions are met: - DW_apb_i2c - is disabled (IC_ENABLE */ + is disabled (IC_ENABLE[0 */ struct { __IOM uint32_t NACK : 1; /*!< [0..0] Generate NACK. This NACK generation only occurs when @@ -7870,11 +8014,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_SLV_DATA_NACK_ONLY; + } IC_SLV_DATA_NACK_ONLY_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000088) DMA Control Register + __IOM uint32_t IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate @@ -7887,11 +8031,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 */ uint32_t : 30; - } bit; - } IC_DMA_CR; + } IC_DMA_CR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + __IOM uint32_t IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ struct { __IOM uint32_t DMATDL : 4; /*!< [3..0] Transmit Data Level. This bit field controls the level @@ -7903,11 +8047,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 28; - } bit; - } IC_DMA_TDLR; + } IC_DMA_TDLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + __IOM uint32_t IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ struct { __IOM uint32_t DMARDL : 4; /*!< [3..0] Receive Data Level. This bit field controls the level @@ -7921,11 +8065,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 28; - } bit; - } IC_DMA_RDLR; + } IC_DMA_RDLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000094) I2C SDA Setup Register + __IOM uint32_t IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock @@ -7938,7 +8082,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu programmed with a value equal to or greater than 2. - Writes to this register succeed only wh */ + Writes to this register succeed only when */ struct { __IOM uint32_t SDA_SETUP : 8; /*!< [7..0] SDA Setup. It is recommended that if the required delay @@ -7946,11 +8090,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. */ uint32_t : 24; - } bit; - } IC_SDA_SETUP; + } IC_SDA_SETUP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000098) I2C ACK General Call Register + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives @@ -7965,11 +8109,11 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). */ uint32_t : 31; - } bit; - } IC_ACK_GENERAL_CALL; + } IC_ACK_GENERAL_CALL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) I2C Enable Status Register + __IOM uint32_t IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register @@ -7985,7 +8129,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu read as '0'. Note: When IC_ENABLE[0] has been set to - 0, a delay occurs for bit 0 */ + 0, a delay occurs for bit 0 t */ struct { __IM uint32_t IC_EN : 1; /*!< [0..0] ic_en Status. This bit always reflects the value driven @@ -8009,7 +8153,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu OR, (b) address and data bytes of the Slave-Receiver operation - from a remote master */ + from a remote master.\ */ __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 @@ -8020,13 +8164,13 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu has been responded with a NACK. Note: If the remote I2C master terminates the transfer - */ + wi */ uint32_t : 29; - } bit; - } IC_ENABLE_STATUS; + } IC_ENABLE_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) I2C SS, FS or FM+ spike suppression limit + __IOM uint32_t IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest @@ -8047,14 +8191,14 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is - 1; hardware prevents values less than this being */ + 1; hardware prevents values less than this being wr */ uint32_t : 24; - } bit; - } IC_FS_SPKLEN; + } IC_FS_SPKLEN_b; + } ; __IM uint32_t RESERVED2; union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */ + __IOM uint32_t IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */ struct { __IM uint32_t CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear the RESTART_DET interrupt @@ -8062,12 +8206,12 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Reset value: 0x0 */ uint32_t : 31; - } bit; - } IC_CLR_RESTART_DET; + } IC_CLR_RESTART_DET_b; + } ; __IM uint32_t RESERVED3[18]; union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) Component Parameter Register 1 + __IOM uint32_t IC_COMP_PARAM_1; /*!< (@ 0x000000F4) Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented @@ -8086,27 +8230,27 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu __IM uint32_t RX_BUFFER_DEPTH : 8; /*!< [15..8] RX Buffer Depth = 16 */ __IM uint32_t TX_BUFFER_DEPTH : 8; /*!< [23..16] TX Buffer Depth = 16 */ uint32_t : 8; - } bit; - } IC_COMP_PARAM_1; + } IC_COMP_PARAM_1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) I2C Component Version Register */ + __IOM uint32_t IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ struct { __IM uint32_t IC_COMP_VERSION : 32; /*!< [31..0] IC_COMP_VERSION */ - } bit; - } IC_COMP_VERSION; + } IC_COMP_VERSION_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000FC) I2C Component Type Register */ + __IOM uint32_t IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ struct { __IM uint32_t IC_COMP_TYPE : 32; /*!< [31..0] Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. */ - } bit; - } IC_COMP_TYPE; + } IC_COMP_TYPE_b; + } ; } I2C0_Type; /*!< Size = 256 (0x100) */ @@ -8123,7 +8267,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu typedef struct { /*!< (@ 0x4004C000) ADC Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) ADC Control and Status */ + __IOM uint32_t CS; /*!< (@ 0x00000000) ADC Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Power on ADC and enable its clock. @@ -8155,20 +8299,20 @@ typedef struct { /*!< (@ 0x4004C000) ADC Structur AINSEL will be updated after each conversion with the newly-selected channel. */ uint32_t : 11; - } bit; - } CS; + } CS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Result of most recent ADC conversion */ + __IOM uint32_t RESULT; /*!< (@ 0x00000004) Result of most recent ADC conversion */ struct { __IM uint32_t RESULT : 12; /*!< [11..0] RESULT */ uint32_t : 20; - } bit; - } RESULT; + } RESULT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) FIFO control and status */ + __IOM uint32_t FCS; /*!< (@ 0x00000008) FIFO control and status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] If 1: write result to the FIFO after each conversion. */ @@ -8188,11 +8332,11 @@ typedef struct { /*!< (@ 0x4004C000) ADC Structur uint32_t : 4; __IOM uint32_t THRESH : 4; /*!< [27..24] DREQ/IRQ asserted when level >= threshold */ uint32_t : 4; - } bit; - } FCS; + } FCS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Conversion result FIFO */ + __IOM uint32_t FIFO; /*!< (@ 0x0000000C) Conversion result FIFO */ struct { __IM uint32_t VAL : 12; /*!< [11..0] VAL */ @@ -8200,11 +8344,11 @@ typedef struct { /*!< (@ 0x4004C000) ADC Structur __IM uint32_t ERR : 1; /*!< [15..15] 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. */ uint32_t : 16; - } bit; - } FIFO; + } FIFO_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Clock divider. If non-zero, CS_START_MANY will + __IOM uint32_t DIV; /*!< (@ 0x00000010) Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these @@ -8215,48 +8359,48 @@ typedef struct { /*!< (@ 0x4004C000) ADC Structur __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional part of clock divisor. First-order delta-sigma. */ __IOM uint32_t INT : 16; /*!< [23..8] Integer part of clock divisor. */ uint32_t : 8; - } bit; - } DIV; + } DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x00000014) Raw Interrupts */ struct { __IM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. */ uint32_t : 31; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Interrupt Enable */ + __IOM uint32_t INTE; /*!< (@ 0x00000018) Interrupt Enable */ struct { __IOM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. */ uint32_t : 31; - } bit; - } INTE; + } INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Interrupt Force */ + __IOM uint32_t INTF; /*!< (@ 0x0000001C) Interrupt Force */ struct { __IOM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. */ uint32_t : 31; - } bit; - } INTF; + } INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Interrupt status after masking & forcing */ + __IOM uint32_t INTS; /*!< (@ 0x00000020) Interrupt status after masking & forcing */ struct { __IM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. */ uint32_t : 31; - } bit; - } INTS; + } INTS_b; + } ; } ADC_Type; /*!< Size = 36 (0x24) */ @@ -8273,7 +8417,7 @@ typedef struct { /*!< (@ 0x4004C000) ADC Structur typedef struct { /*!< (@ 0x40050000) PWM Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control and status register */ + __IOM uint32_t CH0_CSR; /*!< (@ 0x00000000) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8291,11 +8435,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH0_CSR; + } CH0_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH0_DIV; /*!< (@ 0x00000004) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8305,38 +8449,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH0_DIV; + } CH0_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Direct access to the PWM counter */ + __IOM uint32_t CH0_CTR; /*!< (@ 0x00000008) Direct access to the PWM counter */ struct { __IOM uint32_t CH0_CTR : 16; /*!< [15..0] CH0_CTR */ uint32_t : 16; - } bit; - } CH0_CTR; + } CH0_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Counter compare values */ + __IOM uint32_t CH0_CC; /*!< (@ 0x0000000C) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH0_CC; + } CH0_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Counter wrap value */ + __IOM uint32_t CH0_TOP; /*!< (@ 0x00000010) Counter wrap value */ struct { __IOM uint32_t CH0_TOP : 16; /*!< [15..0] CH0_TOP */ uint32_t : 16; - } bit; - } CH0_TOP; + } CH0_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Control and status register */ + __IOM uint32_t CH1_CSR; /*!< (@ 0x00000014) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8354,11 +8498,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH1_CSR; + } CH1_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH1_DIV; /*!< (@ 0x00000018) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8368,38 +8512,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH1_DIV; + } CH1_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Direct access to the PWM counter */ + __IOM uint32_t CH1_CTR; /*!< (@ 0x0000001C) Direct access to the PWM counter */ struct { __IOM uint32_t CH1_CTR : 16; /*!< [15..0] CH1_CTR */ uint32_t : 16; - } bit; - } CH1_CTR; + } CH1_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Counter compare values */ + __IOM uint32_t CH1_CC; /*!< (@ 0x00000020) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH1_CC; + } CH1_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Counter wrap value */ + __IOM uint32_t CH1_TOP; /*!< (@ 0x00000024) Counter wrap value */ struct { __IOM uint32_t CH1_TOP : 16; /*!< [15..0] CH1_TOP */ uint32_t : 16; - } bit; - } CH1_TOP; + } CH1_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Control and status register */ + __IOM uint32_t CH2_CSR; /*!< (@ 0x00000028) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8417,11 +8561,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH2_CSR; + } CH2_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH2_DIV; /*!< (@ 0x0000002C) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8431,38 +8575,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH2_DIV; + } CH2_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Direct access to the PWM counter */ + __IOM uint32_t CH2_CTR; /*!< (@ 0x00000030) Direct access to the PWM counter */ struct { __IOM uint32_t CH2_CTR : 16; /*!< [15..0] CH2_CTR */ uint32_t : 16; - } bit; - } CH2_CTR; + } CH2_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Counter compare values */ + __IOM uint32_t CH2_CC; /*!< (@ 0x00000034) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH2_CC; + } CH2_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Counter wrap value */ + __IOM uint32_t CH2_TOP; /*!< (@ 0x00000038) Counter wrap value */ struct { __IOM uint32_t CH2_TOP : 16; /*!< [15..0] CH2_TOP */ uint32_t : 16; - } bit; - } CH2_TOP; + } CH2_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Control and status register */ + __IOM uint32_t CH3_CSR; /*!< (@ 0x0000003C) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8480,11 +8624,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH3_CSR; + } CH3_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH3_DIV; /*!< (@ 0x00000040) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8494,38 +8638,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH3_DIV; + } CH3_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Direct access to the PWM counter */ + __IOM uint32_t CH3_CTR; /*!< (@ 0x00000044) Direct access to the PWM counter */ struct { __IOM uint32_t CH3_CTR : 16; /*!< [15..0] CH3_CTR */ uint32_t : 16; - } bit; - } CH3_CTR; + } CH3_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Counter compare values */ + __IOM uint32_t CH3_CC; /*!< (@ 0x00000048) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH3_CC; + } CH3_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Counter wrap value */ + __IOM uint32_t CH3_TOP; /*!< (@ 0x0000004C) Counter wrap value */ struct { __IOM uint32_t CH3_TOP : 16; /*!< [15..0] CH3_TOP */ uint32_t : 16; - } bit; - } CH3_TOP; + } CH3_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Control and status register */ + __IOM uint32_t CH4_CSR; /*!< (@ 0x00000050) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8543,11 +8687,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH4_CSR; + } CH4_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH4_DIV; /*!< (@ 0x00000054) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8557,38 +8701,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH4_DIV; + } CH4_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Direct access to the PWM counter */ + __IOM uint32_t CH4_CTR; /*!< (@ 0x00000058) Direct access to the PWM counter */ struct { __IOM uint32_t CH4_CTR : 16; /*!< [15..0] CH4_CTR */ uint32_t : 16; - } bit; - } CH4_CTR; + } CH4_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Counter compare values */ + __IOM uint32_t CH4_CC; /*!< (@ 0x0000005C) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH4_CC; + } CH4_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Counter wrap value */ + __IOM uint32_t CH4_TOP; /*!< (@ 0x00000060) Counter wrap value */ struct { __IOM uint32_t CH4_TOP : 16; /*!< [15..0] CH4_TOP */ uint32_t : 16; - } bit; - } CH4_TOP; + } CH4_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Control and status register */ + __IOM uint32_t CH5_CSR; /*!< (@ 0x00000064) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8606,11 +8750,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH5_CSR; + } CH5_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000068) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH5_DIV; /*!< (@ 0x00000068) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8620,38 +8764,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH5_DIV; + } CH5_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Direct access to the PWM counter */ + __IOM uint32_t CH5_CTR; /*!< (@ 0x0000006C) Direct access to the PWM counter */ struct { __IOM uint32_t CH5_CTR : 16; /*!< [15..0] CH5_CTR */ uint32_t : 16; - } bit; - } CH5_CTR; + } CH5_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Counter compare values */ + __IOM uint32_t CH5_CC; /*!< (@ 0x00000070) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH5_CC; + } CH5_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Counter wrap value */ + __IOM uint32_t CH5_TOP; /*!< (@ 0x00000074) Counter wrap value */ struct { __IOM uint32_t CH5_TOP : 16; /*!< [15..0] CH5_TOP */ uint32_t : 16; - } bit; - } CH5_TOP; + } CH5_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Control and status register */ + __IOM uint32_t CH6_CSR; /*!< (@ 0x00000078) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8669,11 +8813,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH6_CSR; + } CH6_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH6_DIV; /*!< (@ 0x0000007C) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8683,38 +8827,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH6_DIV; + } CH6_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Direct access to the PWM counter */ + __IOM uint32_t CH6_CTR; /*!< (@ 0x00000080) Direct access to the PWM counter */ struct { __IOM uint32_t CH6_CTR : 16; /*!< [15..0] CH6_CTR */ uint32_t : 16; - } bit; - } CH6_CTR; + } CH6_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Counter compare values */ + __IOM uint32_t CH6_CC; /*!< (@ 0x00000084) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH6_CC; + } CH6_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000088) Counter wrap value */ + __IOM uint32_t CH6_TOP; /*!< (@ 0x00000088) Counter wrap value */ struct { __IOM uint32_t CH6_TOP : 16; /*!< [15..0] CH6_TOP */ uint32_t : 16; - } bit; - } CH6_TOP; + } CH6_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Control and status register */ + __IOM uint32_t CH7_CSR; /*!< (@ 0x0000008C) Control and status register */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ @@ -8732,11 +8876,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur be running at less than full speed (div_int + div_frac / 16 > 1) */ uint32_t : 24; - } bit; - } CH7_CSR; + } CH7_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000090) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH7_DIV; /*!< (@ 0x00000090) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order @@ -8746,38 +8890,38 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ __IOM uint32_t INT : 8; /*!< [11..4] INT */ uint32_t : 20; - } bit; - } CH7_DIV; + } CH7_DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Direct access to the PWM counter */ + __IOM uint32_t CH7_CTR; /*!< (@ 0x00000094) Direct access to the PWM counter */ struct { __IOM uint32_t CH7_CTR : 16; /*!< [15..0] CH7_CTR */ uint32_t : 16; - } bit; - } CH7_CTR; + } CH7_CTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Counter compare values */ + __IOM uint32_t CH7_CC; /*!< (@ 0x00000098) Counter compare values */ struct { __IOM uint32_t A : 16; /*!< [15..0] A */ __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH7_CC; + } CH7_CC_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) Counter wrap value */ + __IOM uint32_t CH7_TOP; /*!< (@ 0x0000009C) Counter wrap value */ struct { __IOM uint32_t CH7_TOP : 16; /*!< [15..0] CH7_TOP */ uint32_t : 16; - } bit; - } CH7_TOP; + } CH7_TOP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) This register aliases the CSR_EN bits for all + __IOM uint32_t EN; /*!< (@ 0x000000A0) This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled @@ -8797,11 +8941,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ uint32_t : 24; - } bit; - } EN; + } EN_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x000000A4) Raw Interrupts */ struct { __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ @@ -8813,11 +8957,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ uint32_t : 24; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) Interrupt Enable */ + __IOM uint32_t INTE; /*!< (@ 0x000000A8) Interrupt Enable */ struct { __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ @@ -8829,11 +8973,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ uint32_t : 24; - } bit; - } INTE; + } INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) Interrupt Force */ + __IOM uint32_t INTF; /*!< (@ 0x000000AC) Interrupt Force */ struct { __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ @@ -8845,11 +8989,11 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ uint32_t : 24; - } bit; - } INTF; + } INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) Interrupt status after masking & forcing */ + __IOM uint32_t INTS; /*!< (@ 0x000000B0) Interrupt status after masking & forcing */ struct { __IM uint32_t CH0 : 1; /*!< [0..0] CH0 */ @@ -8861,8 +9005,8 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur __IM uint32_t CH6 : 1; /*!< [6..6] CH6 */ __IM uint32_t CH7 : 1; /*!< [7..7] CH7 */ uint32_t : 24; - } bit; - } INTS; + } INTS_b; + } ; } PWM_Type; /*!< Size = 180 (0xb4) */ @@ -8924,7 +9068,7 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct register. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Indicates the armed/disarmed status of each alarm. + __IOM uint32_t ARMED; /*!< (@ 0x00000020) Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, @@ -8935,13 +9079,13 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct struct { __IOM uint32_t ARMED : 4; /*!< [3..0] ARMED */ uint32_t : 28; - } bit; - } ARMED; + } ARMED_b; + } ; __IM uint32_t TIMERAWH; /*!< (@ 0x00000024) Raw read from bits 63:32 of time (no side effects) */ __IM uint32_t TIMERAWL; /*!< (@ 0x00000028) Raw read from bits 31:0 of time (no side effects) */ union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Set bits high to enable pause when the corresponding + __IOM uint32_t DBGPAUSE; /*!< (@ 0x0000002C) Set bits high to enable pause when the corresponding debug ports are active */ struct { @@ -8949,20 +9093,20 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct __IOM uint32_t DBG0 : 1; /*!< [1..1] Pause when processor 0 is in debug mode */ __IOM uint32_t DBG1 : 1; /*!< [2..2] Pause when processor 1 is in debug mode */ uint32_t : 29; - } bit; - } DBGPAUSE; + } DBGPAUSE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Set high to pause the timer */ + __IOM uint32_t PAUSE; /*!< (@ 0x00000030) Set high to pause the timer */ struct { __IOM uint32_t PAUSE : 1; /*!< [0..0] PAUSE */ uint32_t : 31; - } bit; - } PAUSE; + } PAUSE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x00000034) Raw Interrupts */ struct { __IOM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ @@ -8970,11 +9114,11 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct __IOM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ __IOM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ uint32_t : 28; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt Enable */ + __IOM uint32_t INTE; /*!< (@ 0x00000038) Interrupt Enable */ struct { __IOM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ @@ -8982,11 +9126,11 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct __IOM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ __IOM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ uint32_t : 28; - } bit; - } INTE; + } INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Interrupt Force */ + __IOM uint32_t INTF; /*!< (@ 0x0000003C) Interrupt Force */ struct { __IOM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ @@ -8994,11 +9138,11 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct __IOM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ __IOM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ uint32_t : 28; - } bit; - } INTF; + } INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Interrupt status after masking & forcing */ + __IOM uint32_t INTS; /*!< (@ 0x00000040) Interrupt status after masking & forcing */ struct { __IM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ @@ -9006,8 +9150,8 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct __IM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ __IM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ uint32_t : 28; - } bit; - } INTS; + } INTS_b; + } ; } TIMER_Type; /*!< Size = 68 (0x44) */ @@ -9024,7 +9168,7 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct typedef struct { /*!< (@ 0x40058000) WATCHDOG Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Watchdog control + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. @@ -9042,11 +9186,11 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str uint32_t : 3; __IOM uint32_t ENABLE : 1; /*!< [30..30] When not enabled the watchdog timer is paused */ __IOM uint32_t TRIGGER : 1; /*!< [31..31] Trigger a watchdog reset */ - } bit; - } CTRL; + } CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Load the watchdog timer. The maximum setting + __IOM uint32_t LOAD; /*!< (@ 0x00000004) Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). */ @@ -9054,19 +9198,19 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str struct { __OM uint32_t LOAD : 24; /*!< [23..0] LOAD */ uint32_t : 8; - } bit; - } LOAD; + } LOAD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Logs the reason for the last reset. Both bits + __IOM uint32_t REASON; /*!< (@ 0x00000008) Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. */ struct { __IM uint32_t TIMER : 1; /*!< [0..0] TIMER */ __IM uint32_t FORCE : 1; /*!< [1..1] FORCE */ uint32_t : 30; - } bit; - } REASON; + } REASON_b; + } ; __IOM uint32_t SCRATCH0; /*!< (@ 0x0000000C) Scratch register. Information persists through soft reset of the chip. */ __IOM uint32_t SCRATCH1; /*!< (@ 0x00000010) Scratch register. Information persists through @@ -9085,7 +9229,7 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str soft reset of the chip. */ union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Controls the tick generator */ + __IOM uint32_t TICK; /*!< (@ 0x0000002C) Controls the tick generator */ struct { __IOM uint32_t CYCLES : 9; /*!< [8..0] Total number of clk_tick cycles before the next tick. */ @@ -9094,8 +9238,8 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str __IM uint32_t COUNT : 9; /*!< [19..11] Count down timer: the remaining number clk_tick cycles before the next tick is generated. */ uint32_t : 12; - } bit; - } TICK; + } TICK_b; + } ; } WATCHDOG_Type; /*!< Size = 48 (0x30) */ @@ -9112,17 +9256,17 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str typedef struct { /*!< (@ 0x4005C000) RTC Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Divider minus 1 for the 1 second counter. Safe + __IOM uint32_t CLKDIV_M1; /*!< (@ 0x00000000) Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. */ struct { __IOM uint32_t CLKDIV_M1 : 16; /*!< [15..0] CLKDIV_M1 */ uint32_t : 16; - } bit; - } CLKDIV_M1; + } CLKDIV_M1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) RTC setup register 0 */ + __IOM uint32_t SETUP_0; /*!< (@ 0x00000004) RTC setup register 0 */ struct { __IOM uint32_t DAY : 5; /*!< [4..0] Day of the month (1..31) */ @@ -9130,11 +9274,11 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur __IOM uint32_t MONTH : 4; /*!< [11..8] Month (1..12) */ __IOM uint32_t YEAR : 12; /*!< [23..12] Year */ uint32_t : 8; - } bit; - } SETUP_0; + } SETUP_0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) RTC setup register 1 */ + __IOM uint32_t SETUP_1; /*!< (@ 0x00000008) RTC setup register 1 */ struct { __IOM uint32_t SEC : 6; /*!< [5..0] Seconds */ @@ -9145,11 +9289,11 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur uint32_t : 3; __IOM uint32_t DOTW : 3; /*!< [26..24] Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 */ uint32_t : 5; - } bit; - } SETUP_1; + } SETUP_1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) RTC Control and status */ + __IOM uint32_t CTRL; /*!< (@ 0x0000000C) RTC Control and status */ struct { __IOM uint32_t RTC_ENABLE : 1; /*!< [0..0] Enable RTC */ @@ -9160,11 +9304,11 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur __IOM uint32_t FORCE_NOTLEAPYEAR : 1; /*!< [8..8] If set, leapyear is forced off. Useful for years divisible by 100 but not by 400 */ uint32_t : 23; - } bit; - } CTRL; + } CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Interrupt setup register 0 */ + __IOM uint32_t IRQ_SETUP_0; /*!< (@ 0x00000010) Interrupt setup register 0 */ struct { __IOM uint32_t DAY : 5; /*!< [4..0] Day of the month (1..31) */ @@ -9179,11 +9323,11 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur this one is enabled */ __IM uint32_t MATCH_ACTIVE : 1; /*!< [29..29] MATCH_ACTIVE */ uint32_t : 2; - } bit; - } IRQ_SETUP_0; + } IRQ_SETUP_0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Interrupt setup register 1 */ + __IOM uint32_t IRQ_SETUP_1; /*!< (@ 0x00000014) Interrupt setup register 1 */ struct { __IOM uint32_t SEC : 6; /*!< [5..0] Seconds */ @@ -9198,11 +9342,11 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur __IOM uint32_t MIN_ENA : 1; /*!< [29..29] Enable minute matching */ __IOM uint32_t HOUR_ENA : 1; /*!< [30..30] Enable hour matching */ __IOM uint32_t DOTW_ENA : 1; /*!< [31..31] Enable day of the week matching */ - } bit; - } IRQ_SETUP_1; + } IRQ_SETUP_1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) RTC register 1. */ + __IOM uint32_t RTC_1; /*!< (@ 0x00000018) RTC register 1. */ struct { __IM uint32_t DAY : 5; /*!< [4..0] Day of the month (1..31) */ @@ -9210,11 +9354,11 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur __IM uint32_t MONTH : 4; /*!< [11..8] Month (1..12) */ __IM uint32_t YEAR : 12; /*!< [23..12] Year */ uint32_t : 8; - } bit; - } RTC_1; + } RTC_1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) RTC register 0 + __IOM uint32_t RTC_0; /*!< (@ 0x0000001C) RTC register 0 Read this before RTC 1! */ struct { @@ -9226,44 +9370,44 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur uint32_t : 3; __IM uint32_t DOTW : 3; /*!< [26..24] Day of the week */ uint32_t : 5; - } bit; - } RTC_0; + } RTC_0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x00000020) Raw Interrupts */ struct { __IM uint32_t RTC : 1; /*!< [0..0] RTC */ uint32_t : 31; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Interrupt Enable */ + __IOM uint32_t INTE; /*!< (@ 0x00000024) Interrupt Enable */ struct { __IOM uint32_t RTC : 1; /*!< [0..0] RTC */ uint32_t : 31; - } bit; - } INTE; + } INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Interrupt Force */ + __IOM uint32_t INTF; /*!< (@ 0x00000028) Interrupt Force */ struct { __IOM uint32_t RTC : 1; /*!< [0..0] RTC */ uint32_t : 31; - } bit; - } INTF; + } INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Interrupt status after masking & forcing */ + __IOM uint32_t INTS; /*!< (@ 0x0000002C) Interrupt status after masking & forcing */ struct { __IM uint32_t RTC : 1; /*!< [0..0] RTC */ uint32_t : 31; - } bit; - } INTS; + } INTS_b; + } ; } RTC_Type; /*!< Size = 48 (0x30) */ @@ -9280,7 +9424,7 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur typedef struct { /*!< (@ 0x40060000) ROSC Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Ring Oscillator control */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Ring Oscillator control */ struct { __IOM uint32_t FREQ_RANGE : 12; /*!< [11..0] Controls the number of delay stages in the ROSC ring @@ -9292,7 +9436,7 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down - Note: the v */ + Note: the val */ __IOM uint32_t ENABLE : 12; /*!< [23..12] On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock @@ -9300,11 +9444,11 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */ uint32_t : 8; - } bit; - } CTRL; + } CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) The FREQA & FREQB registers control the frequency + __IOM uint32_t FREQA; /*!< (@ 0x00000004) The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined @@ -9315,7 +9459,7 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength - 3 bits set quadruples */ + 3 bits set quadruples dr */ struct { __IOM uint32_t DS0 : 3; /*!< [2..0] Stage 0 drive strength */ @@ -9329,11 +9473,11 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu __IOM uint32_t PASSWD : 16; /*!< [31..16] Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */ - } bit; - } FREQA; + } FREQA_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) For a detailed description see freqa register */ + __IOM uint32_t FREQB; /*!< (@ 0x00000008) For a detailed description see freqa register */ struct { __IOM uint32_t DS4 : 3; /*!< [2..0] Stage 4 drive strength */ @@ -9347,8 +9491,8 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu __IOM uint32_t PASSWD : 16; /*!< [31..16] Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */ - } bit; - } FREQB; + } FREQB_b; + } ; __IOM uint32_t DORMANT; /*!< (@ 0x0000000C) Ring Oscillator pause control This is used to save power by pausing the ROSC @@ -9359,20 +9503,20 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu dormant mode */ union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Controls the output divider */ + __IOM uint32_t DIV; /*!< (@ 0x00000010) Controls the output divider */ struct { __IOM uint32_t DIV : 12; /*!< [11..0] set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div - any other value sets div=0 and therefore divides by 32 + any other value sets div=31 this register resets to div=16 */ uint32_t : 20; - } bit; - } DIV; + } DIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Controls the phase shifted output */ + __IOM uint32_t PHASE; /*!< (@ 0x00000014) Controls the phase shifted output */ struct { __IOM uint32_t SHIFT : 2; /*!< [1..0] phase shift the phase-shifted output by SHIFT input clocks @@ -9382,14 +9526,14 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu this is ignored when div=1 */ __IOM uint32_t ENABLE : 1; /*!< [3..3] enable the phase-shifted output this can be changed on-the-fly */ - __IOM uint32_t PASSWD : 8; /*!< [11..4] set to 0xaa0 + __IOM uint32_t PASSWD : 8; /*!< [11..4] set to 0xaa any other value enables the output with shift=0 */ uint32_t : 20; - } bit; - } PHASE; + } PHASE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Ring Oscillator Status */ + __IOM uint32_t STATUS; /*!< (@ 0x00000018) Ring Oscillator Status */ struct { uint32_t : 12; @@ -9401,14 +9545,14 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu this resets to 0 but transitions to 1 during chip startup */ uint32_t : 7; __IOM uint32_t BADWRITE : 1; /*!< [24..24] An invalid value has been written to CTRL_ENABLE or - CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT */ + CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT */ uint32_t : 6; __IM uint32_t STABLE : 1; /*!< [31..31] Oscillator is running and stable */ - } bit; - } STATUS; + } STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) This just reads the state of the oscillator output + __IOM uint32_t RANDOMBIT; /*!< (@ 0x0000001C) This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency */ @@ -9416,11 +9560,11 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu struct { __IM uint32_t RANDOMBIT : 1; /*!< [0..0] RANDOMBIT */ uint32_t : 31; - } bit; - } RANDOMBIT; + } RANDOMBIT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) A down counter running at the ROSC frequency + __IOM uint32_t COUNT; /*!< (@ 0x00000020) A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when @@ -9429,8 +9573,8 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu struct { __IOM uint32_t COUNT : 8; /*!< [7..0] COUNT */ uint32_t : 24; - } bit; - } COUNT; + } COUNT_b; + } ; } ROSC_Type; /*!< Size = 36 (0x24) */ @@ -9447,7 +9591,7 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu typedef struct { /*!< (@ 0x40064000) VREG_AND_CHIP_RESET Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Voltage regulator control and status */ + __IOM uint32_t VREG; /*!< (@ 0x00000000) Voltage regulator control and status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] enable @@ -9471,11 +9615,11 @@ typedef struct { /*!< (@ 0x40064000) VREG_AND_CHI __IM uint32_t ROK : 1; /*!< [12..12] regulation status 0=not in regulation, 1=in regulation */ uint32_t : 19; - } bit; - } VREG; + } VREG_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) brown-out detection control */ + __IOM uint32_t BOD; /*!< (@ 0x00000004) brown-out detection control */ struct { __IOM uint32_t EN : 1; /*!< [0..0] enable @@ -9496,13 +9640,13 @@ typedef struct { /*!< (@ 0x40064000) VREG_AND_CHI 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V - 1 */ + 111 */ uint32_t : 24; - } bit; - } BOD; + } BOD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Chip reset control and status */ + __IOM uint32_t CHIP_RESET; /*!< (@ 0x00000008) Chip reset control and status */ struct { uint32_t : 8; @@ -9520,8 +9664,8 @@ typedef struct { /*!< (@ 0x40064000) VREG_AND_CHI In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. */ uint32_t : 7; - } bit; - } CHIP_RESET; + } CHIP_RESET_b; + } ; } VREG_AND_CHIP_RESET_Type; /*!< Size = 12 (0xc) */ @@ -9538,14 +9682,14 @@ typedef struct { /*!< (@ 0x40064000) VREG_AND_CHI typedef struct { /*!< (@ 0x4006C000) TBMAN Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Indicates the type of platform in use */ + __IOM uint32_t PLATFORM; /*!< (@ 0x00000000) Indicates the type of platform in use */ struct { __IM uint32_t ASIC : 1; /*!< [0..0] Indicates the platform is an ASIC */ __IM uint32_t FPGA : 1; /*!< [1..1] Indicates the platform is an FPGA */ uint32_t : 30; - } bit; - } PLATFORM; + } PLATFORM_b; + } ; } TBMAN_Type; /*!< Size = 4 (0x4) */ @@ -9582,10 +9726,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) DMA Channel 0 Control and Status */ + __IOM uint32_t CH0_CTRL_TRIG; /*!< (@ 0x0000000C) DMA Channel 0 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -9630,8 +9774,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (0). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -9667,38 +9810,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH0_CTRL_TRIG; - __IM uint32_t CH0_AL1_CTRL; /*!< (@ 0x00000010) Alias for channel 0 CTRL register */ - __IM uint32_t CH0_AL1_READ_ADDR; /*!< (@ 0x00000014) Alias for channel 0 READ_ADDR register */ - __IM uint32_t CH0_AL1_WRITE_ADDR; /*!< (@ 0x00000018) Alias for channel 0 WRITE_ADDR register */ - __IM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000001C) Alias for channel 0 TRANS_COUNT register + } CH0_CTRL_TRIG_b; + } ; + __IOM uint32_t CH0_AL1_CTRL; /*!< (@ 0x00000010) Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL1_READ_ADDR; /*!< (@ 0x00000014) Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< (@ 0x00000018) Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000001C) Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH0_AL2_CTRL; /*!< (@ 0x00000020) Alias for channel 0 CTRL register */ - __IM uint32_t CH0_AL2_TRANS_COUNT; /*!< (@ 0x00000024) Alias for channel 0 TRANS_COUNT register */ - __IM uint32_t CH0_AL2_READ_ADDR; /*!< (@ 0x00000028) Alias for channel 0 READ_ADDR register */ - __IM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000002C) Alias for channel 0 WRITE_ADDR register + __IOM uint32_t CH0_AL2_CTRL; /*!< (@ 0x00000020) Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< (@ 0x00000024) Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL2_READ_ADDR; /*!< (@ 0x00000028) Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000002C) Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH0_AL3_CTRL; /*!< (@ 0x00000030) Alias for channel 0 CTRL register */ - __IM uint32_t CH0_AL3_WRITE_ADDR; /*!< (@ 0x00000034) Alias for channel 0 WRITE_ADDR register */ - __IM uint32_t CH0_AL3_TRANS_COUNT; /*!< (@ 0x00000038) Alias for channel 0 TRANS_COUNT register */ - __IM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000003C) Alias for channel 0 READ_ADDR register + __IOM uint32_t CH0_AL3_CTRL; /*!< (@ 0x00000030) Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< (@ 0x00000034) Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< (@ 0x00000038) Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000003C) Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -9725,10 +9868,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) DMA Channel 1 Control and Status */ + __IOM uint32_t CH1_CTRL_TRIG; /*!< (@ 0x0000004C) DMA Channel 1 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -9773,8 +9916,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (1). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -9810,38 +9952,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH1_CTRL_TRIG; - __IM uint32_t CH1_AL1_CTRL; /*!< (@ 0x00000050) Alias for channel 1 CTRL register */ - __IM uint32_t CH1_AL1_READ_ADDR; /*!< (@ 0x00000054) Alias for channel 1 READ_ADDR register */ - __IM uint32_t CH1_AL1_WRITE_ADDR; /*!< (@ 0x00000058) Alias for channel 1 WRITE_ADDR register */ - __IM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000005C) Alias for channel 1 TRANS_COUNT register + } CH1_CTRL_TRIG_b; + } ; + __IOM uint32_t CH1_AL1_CTRL; /*!< (@ 0x00000050) Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL1_READ_ADDR; /*!< (@ 0x00000054) Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< (@ 0x00000058) Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000005C) Alias for channel 1 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH1_AL2_CTRL; /*!< (@ 0x00000060) Alias for channel 1 CTRL register */ - __IM uint32_t CH1_AL2_TRANS_COUNT; /*!< (@ 0x00000064) Alias for channel 1 TRANS_COUNT register */ - __IM uint32_t CH1_AL2_READ_ADDR; /*!< (@ 0x00000068) Alias for channel 1 READ_ADDR register */ - __IM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000006C) Alias for channel 1 WRITE_ADDR register + __IOM uint32_t CH1_AL2_CTRL; /*!< (@ 0x00000060) Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< (@ 0x00000064) Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL2_READ_ADDR; /*!< (@ 0x00000068) Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000006C) Alias for channel 1 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH1_AL3_CTRL; /*!< (@ 0x00000070) Alias for channel 1 CTRL register */ - __IM uint32_t CH1_AL3_WRITE_ADDR; /*!< (@ 0x00000074) Alias for channel 1 WRITE_ADDR register */ - __IM uint32_t CH1_AL3_TRANS_COUNT; /*!< (@ 0x00000078) Alias for channel 1 TRANS_COUNT register */ - __IM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000007C) Alias for channel 1 READ_ADDR register + __IOM uint32_t CH1_AL3_CTRL; /*!< (@ 0x00000070) Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< (@ 0x00000074) Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< (@ 0x00000078) Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000007C) Alias for channel 1 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -9868,10 +10010,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) DMA Channel 2 Control and Status */ + __IOM uint32_t CH2_CTRL_TRIG; /*!< (@ 0x0000008C) DMA Channel 2 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -9916,8 +10058,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (2). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -9953,38 +10094,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH2_CTRL_TRIG; - __IM uint32_t CH2_AL1_CTRL; /*!< (@ 0x00000090) Alias for channel 2 CTRL register */ - __IM uint32_t CH2_AL1_READ_ADDR; /*!< (@ 0x00000094) Alias for channel 2 READ_ADDR register */ - __IM uint32_t CH2_AL1_WRITE_ADDR; /*!< (@ 0x00000098) Alias for channel 2 WRITE_ADDR register */ - __IM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000009C) Alias for channel 2 TRANS_COUNT register + } CH2_CTRL_TRIG_b; + } ; + __IOM uint32_t CH2_AL1_CTRL; /*!< (@ 0x00000090) Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL1_READ_ADDR; /*!< (@ 0x00000094) Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< (@ 0x00000098) Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000009C) Alias for channel 2 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH2_AL2_CTRL; /*!< (@ 0x000000A0) Alias for channel 2 CTRL register */ - __IM uint32_t CH2_AL2_TRANS_COUNT; /*!< (@ 0x000000A4) Alias for channel 2 TRANS_COUNT register */ - __IM uint32_t CH2_AL2_READ_ADDR; /*!< (@ 0x000000A8) Alias for channel 2 READ_ADDR register */ - __IM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000AC) Alias for channel 2 WRITE_ADDR register + __IOM uint32_t CH2_AL2_CTRL; /*!< (@ 0x000000A0) Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< (@ 0x000000A4) Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL2_READ_ADDR; /*!< (@ 0x000000A8) Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000AC) Alias for channel 2 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH2_AL3_CTRL; /*!< (@ 0x000000B0) Alias for channel 2 CTRL register */ - __IM uint32_t CH2_AL3_WRITE_ADDR; /*!< (@ 0x000000B4) Alias for channel 2 WRITE_ADDR register */ - __IM uint32_t CH2_AL3_TRANS_COUNT; /*!< (@ 0x000000B8) Alias for channel 2 TRANS_COUNT register */ - __IM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000BC) Alias for channel 2 READ_ADDR register + __IOM uint32_t CH2_AL3_CTRL; /*!< (@ 0x000000B0) Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< (@ 0x000000B4) Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< (@ 0x000000B8) Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000BC) Alias for channel 2 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10011,10 +10152,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x000000CC) DMA Channel 3 Control and Status */ + __IOM uint32_t CH3_CTRL_TRIG; /*!< (@ 0x000000CC) DMA Channel 3 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10059,8 +10200,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (3). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10096,38 +10236,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH3_CTRL_TRIG; - __IM uint32_t CH3_AL1_CTRL; /*!< (@ 0x000000D0) Alias for channel 3 CTRL register */ - __IM uint32_t CH3_AL1_READ_ADDR; /*!< (@ 0x000000D4) Alias for channel 3 READ_ADDR register */ - __IM uint32_t CH3_AL1_WRITE_ADDR; /*!< (@ 0x000000D8) Alias for channel 3 WRITE_ADDR register */ - __IM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000000DC) Alias for channel 3 TRANS_COUNT register + } CH3_CTRL_TRIG_b; + } ; + __IOM uint32_t CH3_AL1_CTRL; /*!< (@ 0x000000D0) Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL1_READ_ADDR; /*!< (@ 0x000000D4) Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< (@ 0x000000D8) Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000000DC) Alias for channel 3 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH3_AL2_CTRL; /*!< (@ 0x000000E0) Alias for channel 3 CTRL register */ - __IM uint32_t CH3_AL2_TRANS_COUNT; /*!< (@ 0x000000E4) Alias for channel 3 TRANS_COUNT register */ - __IM uint32_t CH3_AL2_READ_ADDR; /*!< (@ 0x000000E8) Alias for channel 3 READ_ADDR register */ - __IM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000EC) Alias for channel 3 WRITE_ADDR register + __IOM uint32_t CH3_AL2_CTRL; /*!< (@ 0x000000E0) Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< (@ 0x000000E4) Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL2_READ_ADDR; /*!< (@ 0x000000E8) Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000EC) Alias for channel 3 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH3_AL3_CTRL; /*!< (@ 0x000000F0) Alias for channel 3 CTRL register */ - __IM uint32_t CH3_AL3_WRITE_ADDR; /*!< (@ 0x000000F4) Alias for channel 3 WRITE_ADDR register */ - __IM uint32_t CH3_AL3_TRANS_COUNT; /*!< (@ 0x000000F8) Alias for channel 3 TRANS_COUNT register */ - __IM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000FC) Alias for channel 3 READ_ADDR register + __IOM uint32_t CH3_AL3_CTRL; /*!< (@ 0x000000F0) Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< (@ 0x000000F4) Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< (@ 0x000000F8) Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000FC) Alias for channel 3 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10154,10 +10294,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000010C) DMA Channel 4 Control and Status */ + __IOM uint32_t CH4_CTRL_TRIG; /*!< (@ 0x0000010C) DMA Channel 4 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10202,8 +10342,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (4). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10239,38 +10378,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH4_CTRL_TRIG; - __IM uint32_t CH4_AL1_CTRL; /*!< (@ 0x00000110) Alias for channel 4 CTRL register */ - __IM uint32_t CH4_AL1_READ_ADDR; /*!< (@ 0x00000114) Alias for channel 4 READ_ADDR register */ - __IM uint32_t CH4_AL1_WRITE_ADDR; /*!< (@ 0x00000118) Alias for channel 4 WRITE_ADDR register */ - __IM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000011C) Alias for channel 4 TRANS_COUNT register + } CH4_CTRL_TRIG_b; + } ; + __IOM uint32_t CH4_AL1_CTRL; /*!< (@ 0x00000110) Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL1_READ_ADDR; /*!< (@ 0x00000114) Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< (@ 0x00000118) Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000011C) Alias for channel 4 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH4_AL2_CTRL; /*!< (@ 0x00000120) Alias for channel 4 CTRL register */ - __IM uint32_t CH4_AL2_TRANS_COUNT; /*!< (@ 0x00000124) Alias for channel 4 TRANS_COUNT register */ - __IM uint32_t CH4_AL2_READ_ADDR; /*!< (@ 0x00000128) Alias for channel 4 READ_ADDR register */ - __IM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000012C) Alias for channel 4 WRITE_ADDR register + __IOM uint32_t CH4_AL2_CTRL; /*!< (@ 0x00000120) Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< (@ 0x00000124) Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL2_READ_ADDR; /*!< (@ 0x00000128) Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000012C) Alias for channel 4 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH4_AL3_CTRL; /*!< (@ 0x00000130) Alias for channel 4 CTRL register */ - __IM uint32_t CH4_AL3_WRITE_ADDR; /*!< (@ 0x00000134) Alias for channel 4 WRITE_ADDR register */ - __IM uint32_t CH4_AL3_TRANS_COUNT; /*!< (@ 0x00000138) Alias for channel 4 TRANS_COUNT register */ - __IM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000013C) Alias for channel 4 READ_ADDR register + __IOM uint32_t CH4_AL3_CTRL; /*!< (@ 0x00000130) Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< (@ 0x00000134) Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< (@ 0x00000138) Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000013C) Alias for channel 4 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10297,10 +10436,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000014C) DMA Channel 5 Control and Status */ + __IOM uint32_t CH5_CTRL_TRIG; /*!< (@ 0x0000014C) DMA Channel 5 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10345,8 +10484,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (5). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10382,38 +10520,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH5_CTRL_TRIG; - __IM uint32_t CH5_AL1_CTRL; /*!< (@ 0x00000150) Alias for channel 5 CTRL register */ - __IM uint32_t CH5_AL1_READ_ADDR; /*!< (@ 0x00000154) Alias for channel 5 READ_ADDR register */ - __IM uint32_t CH5_AL1_WRITE_ADDR; /*!< (@ 0x00000158) Alias for channel 5 WRITE_ADDR register */ - __IM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000015C) Alias for channel 5 TRANS_COUNT register + } CH5_CTRL_TRIG_b; + } ; + __IOM uint32_t CH5_AL1_CTRL; /*!< (@ 0x00000150) Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL1_READ_ADDR; /*!< (@ 0x00000154) Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< (@ 0x00000158) Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000015C) Alias for channel 5 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH5_AL2_CTRL; /*!< (@ 0x00000160) Alias for channel 5 CTRL register */ - __IM uint32_t CH5_AL2_TRANS_COUNT; /*!< (@ 0x00000164) Alias for channel 5 TRANS_COUNT register */ - __IM uint32_t CH5_AL2_READ_ADDR; /*!< (@ 0x00000168) Alias for channel 5 READ_ADDR register */ - __IM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000016C) Alias for channel 5 WRITE_ADDR register + __IOM uint32_t CH5_AL2_CTRL; /*!< (@ 0x00000160) Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< (@ 0x00000164) Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL2_READ_ADDR; /*!< (@ 0x00000168) Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000016C) Alias for channel 5 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH5_AL3_CTRL; /*!< (@ 0x00000170) Alias for channel 5 CTRL register */ - __IM uint32_t CH5_AL3_WRITE_ADDR; /*!< (@ 0x00000174) Alias for channel 5 WRITE_ADDR register */ - __IM uint32_t CH5_AL3_TRANS_COUNT; /*!< (@ 0x00000178) Alias for channel 5 TRANS_COUNT register */ - __IM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000017C) Alias for channel 5 READ_ADDR register + __IOM uint32_t CH5_AL3_CTRL; /*!< (@ 0x00000170) Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< (@ 0x00000174) Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< (@ 0x00000178) Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000017C) Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10440,10 +10578,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000018C) DMA Channel 6 Control and Status */ + __IOM uint32_t CH6_CTRL_TRIG; /*!< (@ 0x0000018C) DMA Channel 6 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10488,8 +10626,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (6). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10525,38 +10662,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH6_CTRL_TRIG; - __IM uint32_t CH6_AL1_CTRL; /*!< (@ 0x00000190) Alias for channel 6 CTRL register */ - __IM uint32_t CH6_AL1_READ_ADDR; /*!< (@ 0x00000194) Alias for channel 6 READ_ADDR register */ - __IM uint32_t CH6_AL1_WRITE_ADDR; /*!< (@ 0x00000198) Alias for channel 6 WRITE_ADDR register */ - __IM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000019C) Alias for channel 6 TRANS_COUNT register + } CH6_CTRL_TRIG_b; + } ; + __IOM uint32_t CH6_AL1_CTRL; /*!< (@ 0x00000190) Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL1_READ_ADDR; /*!< (@ 0x00000194) Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< (@ 0x00000198) Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000019C) Alias for channel 6 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH6_AL2_CTRL; /*!< (@ 0x000001A0) Alias for channel 6 CTRL register */ - __IM uint32_t CH6_AL2_TRANS_COUNT; /*!< (@ 0x000001A4) Alias for channel 6 TRANS_COUNT register */ - __IM uint32_t CH6_AL2_READ_ADDR; /*!< (@ 0x000001A8) Alias for channel 6 READ_ADDR register */ - __IM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001AC) Alias for channel 6 WRITE_ADDR register + __IOM uint32_t CH6_AL2_CTRL; /*!< (@ 0x000001A0) Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< (@ 0x000001A4) Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL2_READ_ADDR; /*!< (@ 0x000001A8) Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001AC) Alias for channel 6 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH6_AL3_CTRL; /*!< (@ 0x000001B0) Alias for channel 6 CTRL register */ - __IM uint32_t CH6_AL3_WRITE_ADDR; /*!< (@ 0x000001B4) Alias for channel 6 WRITE_ADDR register */ - __IM uint32_t CH6_AL3_TRANS_COUNT; /*!< (@ 0x000001B8) Alias for channel 6 TRANS_COUNT register */ - __IM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001BC) Alias for channel 6 READ_ADDR register + __IOM uint32_t CH6_AL3_CTRL; /*!< (@ 0x000001B0) Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< (@ 0x000001B4) Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< (@ 0x000001B8) Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001BC) Alias for channel 6 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10583,10 +10720,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x000001CC) DMA Channel 7 Control and Status */ + __IOM uint32_t CH7_CTRL_TRIG; /*!< (@ 0x000001CC) DMA Channel 7 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10631,8 +10768,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (7). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10668,38 +10804,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH7_CTRL_TRIG; - __IM uint32_t CH7_AL1_CTRL; /*!< (@ 0x000001D0) Alias for channel 7 CTRL register */ - __IM uint32_t CH7_AL1_READ_ADDR; /*!< (@ 0x000001D4) Alias for channel 7 READ_ADDR register */ - __IM uint32_t CH7_AL1_WRITE_ADDR; /*!< (@ 0x000001D8) Alias for channel 7 WRITE_ADDR register */ - __IM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000001DC) Alias for channel 7 TRANS_COUNT register + } CH7_CTRL_TRIG_b; + } ; + __IOM uint32_t CH7_AL1_CTRL; /*!< (@ 0x000001D0) Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL1_READ_ADDR; /*!< (@ 0x000001D4) Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< (@ 0x000001D8) Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000001DC) Alias for channel 7 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH7_AL2_CTRL; /*!< (@ 0x000001E0) Alias for channel 7 CTRL register */ - __IM uint32_t CH7_AL2_TRANS_COUNT; /*!< (@ 0x000001E4) Alias for channel 7 TRANS_COUNT register */ - __IM uint32_t CH7_AL2_READ_ADDR; /*!< (@ 0x000001E8) Alias for channel 7 READ_ADDR register */ - __IM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001EC) Alias for channel 7 WRITE_ADDR register + __IOM uint32_t CH7_AL2_CTRL; /*!< (@ 0x000001E0) Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< (@ 0x000001E4) Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL2_READ_ADDR; /*!< (@ 0x000001E8) Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001EC) Alias for channel 7 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH7_AL3_CTRL; /*!< (@ 0x000001F0) Alias for channel 7 CTRL register */ - __IM uint32_t CH7_AL3_WRITE_ADDR; /*!< (@ 0x000001F4) Alias for channel 7 WRITE_ADDR register */ - __IM uint32_t CH7_AL3_TRANS_COUNT; /*!< (@ 0x000001F8) Alias for channel 7 TRANS_COUNT register */ - __IM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001FC) Alias for channel 7 READ_ADDR register + __IOM uint32_t CH7_AL3_CTRL; /*!< (@ 0x000001F0) Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< (@ 0x000001F4) Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< (@ 0x000001F8) Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001FC) Alias for channel 7 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10726,10 +10862,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000020C) DMA Channel 8 Control and Status */ + __IOM uint32_t CH8_CTRL_TRIG; /*!< (@ 0x0000020C) DMA Channel 8 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10774,8 +10910,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (8). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10811,38 +10946,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH8_CTRL_TRIG; - __IM uint32_t CH8_AL1_CTRL; /*!< (@ 0x00000210) Alias for channel 8 CTRL register */ - __IM uint32_t CH8_AL1_READ_ADDR; /*!< (@ 0x00000214) Alias for channel 8 READ_ADDR register */ - __IM uint32_t CH8_AL1_WRITE_ADDR; /*!< (@ 0x00000218) Alias for channel 8 WRITE_ADDR register */ - __IM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000021C) Alias for channel 8 TRANS_COUNT register + } CH8_CTRL_TRIG_b; + } ; + __IOM uint32_t CH8_AL1_CTRL; /*!< (@ 0x00000210) Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL1_READ_ADDR; /*!< (@ 0x00000214) Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< (@ 0x00000218) Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000021C) Alias for channel 8 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH8_AL2_CTRL; /*!< (@ 0x00000220) Alias for channel 8 CTRL register */ - __IM uint32_t CH8_AL2_TRANS_COUNT; /*!< (@ 0x00000224) Alias for channel 8 TRANS_COUNT register */ - __IM uint32_t CH8_AL2_READ_ADDR; /*!< (@ 0x00000228) Alias for channel 8 READ_ADDR register */ - __IM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000022C) Alias for channel 8 WRITE_ADDR register + __IOM uint32_t CH8_AL2_CTRL; /*!< (@ 0x00000220) Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< (@ 0x00000224) Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL2_READ_ADDR; /*!< (@ 0x00000228) Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000022C) Alias for channel 8 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH8_AL3_CTRL; /*!< (@ 0x00000230) Alias for channel 8 CTRL register */ - __IM uint32_t CH8_AL3_WRITE_ADDR; /*!< (@ 0x00000234) Alias for channel 8 WRITE_ADDR register */ - __IM uint32_t CH8_AL3_TRANS_COUNT; /*!< (@ 0x00000238) Alias for channel 8 TRANS_COUNT register */ - __IM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000023C) Alias for channel 8 READ_ADDR register + __IOM uint32_t CH8_AL3_CTRL; /*!< (@ 0x00000230) Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< (@ 0x00000234) Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< (@ 0x00000238) Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000023C) Alias for channel 8 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10869,10 +11004,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ + for the transf */ union { - __IOM uint32_t reg; /*!< (@ 0x0000024C) DMA Channel 9 Control and Status */ + __IOM uint32_t CH9_CTRL_TRIG; /*!< (@ 0x0000024C) DMA Channel 9 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -10917,8 +11052,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (9). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -10954,38 +11088,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH9_CTRL_TRIG; - __IM uint32_t CH9_AL1_CTRL; /*!< (@ 0x00000250) Alias for channel 9 CTRL register */ - __IM uint32_t CH9_AL1_READ_ADDR; /*!< (@ 0x00000254) Alias for channel 9 READ_ADDR register */ - __IM uint32_t CH9_AL1_WRITE_ADDR; /*!< (@ 0x00000258) Alias for channel 9 WRITE_ADDR register */ - __IM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000025C) Alias for channel 9 TRANS_COUNT register + } CH9_CTRL_TRIG_b; + } ; + __IOM uint32_t CH9_AL1_CTRL; /*!< (@ 0x00000250) Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL1_READ_ADDR; /*!< (@ 0x00000254) Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< (@ 0x00000258) Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000025C) Alias for channel 9 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH9_AL2_CTRL; /*!< (@ 0x00000260) Alias for channel 9 CTRL register */ - __IM uint32_t CH9_AL2_TRANS_COUNT; /*!< (@ 0x00000264) Alias for channel 9 TRANS_COUNT register */ - __IM uint32_t CH9_AL2_READ_ADDR; /*!< (@ 0x00000268) Alias for channel 9 READ_ADDR register */ - __IM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000026C) Alias for channel 9 WRITE_ADDR register + __IOM uint32_t CH9_AL2_CTRL; /*!< (@ 0x00000260) Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< (@ 0x00000264) Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL2_READ_ADDR; /*!< (@ 0x00000268) Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000026C) Alias for channel 9 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH9_AL3_CTRL; /*!< (@ 0x00000270) Alias for channel 9 CTRL register */ - __IM uint32_t CH9_AL3_WRITE_ADDR; /*!< (@ 0x00000274) Alias for channel 9 WRITE_ADDR register */ - __IM uint32_t CH9_AL3_TRANS_COUNT; /*!< (@ 0x00000278) Alias for channel 9 TRANS_COUNT register */ - __IM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000027C) Alias for channel 9 READ_ADDR register + __IOM uint32_t CH9_AL3_CTRL; /*!< (@ 0x00000270) Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< (@ 0x00000274) Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< (@ 0x00000278) Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000027C) Alias for channel 9 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -11012,10 +11146,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tra */ + for the trans */ union { - __IOM uint32_t reg; /*!< (@ 0x0000028C) DMA Channel 10 Control and Status */ + __IOM uint32_t CH10_CTRL_TRIG; /*!< (@ 0x0000028C) DMA Channel 10 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -11060,8 +11194,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (10). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -11097,38 +11230,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH10_CTRL_TRIG; - __IM uint32_t CH10_AL1_CTRL; /*!< (@ 0x00000290) Alias for channel 10 CTRL register */ - __IM uint32_t CH10_AL1_READ_ADDR; /*!< (@ 0x00000294) Alias for channel 10 READ_ADDR register */ - __IM uint32_t CH10_AL1_WRITE_ADDR; /*!< (@ 0x00000298) Alias for channel 10 WRITE_ADDR register */ - __IM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000029C) Alias for channel 10 TRANS_COUNT register + } CH10_CTRL_TRIG_b; + } ; + __IOM uint32_t CH10_AL1_CTRL; /*!< (@ 0x00000290) Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL1_READ_ADDR; /*!< (@ 0x00000294) Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< (@ 0x00000298) Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000029C) Alias for channel 10 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH10_AL2_CTRL; /*!< (@ 0x000002A0) Alias for channel 10 CTRL register */ - __IM uint32_t CH10_AL2_TRANS_COUNT; /*!< (@ 0x000002A4) Alias for channel 10 TRANS_COUNT register */ - __IM uint32_t CH10_AL2_READ_ADDR; /*!< (@ 0x000002A8) Alias for channel 10 READ_ADDR register */ - __IM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002AC) Alias for channel 10 WRITE_ADDR register + __IOM uint32_t CH10_AL2_CTRL; /*!< (@ 0x000002A0) Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< (@ 0x000002A4) Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL2_READ_ADDR; /*!< (@ 0x000002A8) Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002AC) Alias for channel 10 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH10_AL3_CTRL; /*!< (@ 0x000002B0) Alias for channel 10 CTRL register */ - __IM uint32_t CH10_AL3_WRITE_ADDR; /*!< (@ 0x000002B4) Alias for channel 10 WRITE_ADDR register */ - __IM uint32_t CH10_AL3_TRANS_COUNT; /*!< (@ 0x000002B8) Alias for channel 10 TRANS_COUNT register */ - __IM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002BC) Alias for channel 10 READ_ADDR register + __IOM uint32_t CH10_AL3_CTRL; /*!< (@ 0x000002B0) Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< (@ 0x000002B4) Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< (@ 0x000002B8) Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002BC) Alias for channel 10 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -11155,10 +11288,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tra */ + for the trans */ union { - __IOM uint32_t reg; /*!< (@ 0x000002CC) DMA Channel 11 Control and Status */ + __IOM uint32_t CH11_CTRL_TRIG; /*!< (@ 0x000002CC) DMA Channel 11 Control and Status */ struct { __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. @@ -11203,8 +11336,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur boundary. If 1, write addresses are wrapped. */ __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (11). */ + channel)_. */ __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal @@ -11240,38 +11372,38 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ + error was encountered (will not be earlier, or more than + 5 transfers later) */ __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ + was encountered (will not be earlier, or more than 3 transfers + later) */ __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */ - } bit; - } CH11_CTRL_TRIG; - __IM uint32_t CH11_AL1_CTRL; /*!< (@ 0x000002D0) Alias for channel 11 CTRL register */ - __IM uint32_t CH11_AL1_READ_ADDR; /*!< (@ 0x000002D4) Alias for channel 11 READ_ADDR register */ - __IM uint32_t CH11_AL1_WRITE_ADDR; /*!< (@ 0x000002D8) Alias for channel 11 WRITE_ADDR register */ - __IM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000002DC) Alias for channel 11 TRANS_COUNT register + } CH11_CTRL_TRIG_b; + } ; + __IOM uint32_t CH11_AL1_CTRL; /*!< (@ 0x000002D0) Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL1_READ_ADDR; /*!< (@ 0x000002D4) Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< (@ 0x000002D8) Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000002DC) Alias for channel 11 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH11_AL2_CTRL; /*!< (@ 0x000002E0) Alias for channel 11 CTRL register */ - __IM uint32_t CH11_AL2_TRANS_COUNT; /*!< (@ 0x000002E4) Alias for channel 11 TRANS_COUNT register */ - __IM uint32_t CH11_AL2_READ_ADDR; /*!< (@ 0x000002E8) Alias for channel 11 READ_ADDR register */ - __IM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002EC) Alias for channel 11 WRITE_ADDR register + __IOM uint32_t CH11_AL2_CTRL; /*!< (@ 0x000002E0) Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< (@ 0x000002E4) Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL2_READ_ADDR; /*!< (@ 0x000002E8) Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002EC) Alias for channel 11 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH11_AL3_CTRL; /*!< (@ 0x000002F0) Alias for channel 11 CTRL register */ - __IM uint32_t CH11_AL3_WRITE_ADDR; /*!< (@ 0x000002F4) Alias for channel 11 WRITE_ADDR register */ - __IM uint32_t CH11_AL3_TRANS_COUNT; /*!< (@ 0x000002F8) Alias for channel 11 TRANS_COUNT register */ - __IM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002FC) Alias for channel 11 READ_ADDR register + __IOM uint32_t CH11_AL3_CTRL; /*!< (@ 0x000002F0) Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< (@ 0x000002F4) Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< (@ 0x000002F8) Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002FC) Alias for channel 11 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -11279,10 +11411,10 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur __IM uint32_t RESERVED[64]; union { - __IOM uint32_t reg; /*!< (@ 0x00000400) Interrupt Status (raw) */ + __IOM uint32_t INTR; /*!< (@ 0x00000400) Interrupt Status (raw) */ struct { - __IM uint32_t INTR : 16; /*!< [15..0] Raw interrupt status for DMA Channels 0..15. Bit n corresponds + __IOM uint32_t INTR : 16; /*!< [15..0] Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. @@ -11293,33 +11425,33 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load - across d */ + across dif */ uint32_t : 16; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000404) Interrupt Enables for IRQ 0 */ + __IOM uint32_t INTE0; /*!< (@ 0x00000404) Interrupt Enables for IRQ 0 */ struct { __IOM uint32_t INTE0 : 16; /*!< [15..0] Set bit n to pass interrupts from channel n to DMA IRQ 0. */ uint32_t : 16; - } bit; - } INTE0; + } INTE0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000408) Force Interrupts */ + __IOM uint32_t INTF0; /*!< (@ 0x00000408) Force Interrupts */ struct { __IOM uint32_t INTF0 : 16; /*!< [15..0] Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. */ uint32_t : 16; - } bit; - } INTF0; + } INTF0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000040C) Interrupt Status for IRQ 0 */ + __IOM uint32_t INTS0; /*!< (@ 0x0000040C) Interrupt Status for IRQ 0 */ struct { __IOM uint32_t INTS0 : 16; /*!< [15..0] Indicates active channel interrupt requests which are @@ -11327,32 +11459,32 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur Channel interrupts can be cleared by writing a bit mask here. */ uint32_t : 16; - } bit; - } INTS0; + } INTS0_b; + } ; __IM uint32_t RESERVED1; union { - __IOM uint32_t reg; /*!< (@ 0x00000414) Interrupt Enables for IRQ 1 */ + __IOM uint32_t INTE1; /*!< (@ 0x00000414) Interrupt Enables for IRQ 1 */ struct { __IOM uint32_t INTE1 : 16; /*!< [15..0] Set bit n to pass interrupts from channel n to DMA IRQ 1. */ uint32_t : 16; - } bit; - } INTE1; + } INTE1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000418) Force Interrupts for IRQ 1 */ + __IOM uint32_t INTF1; /*!< (@ 0x00000418) Force Interrupts for IRQ 1 */ struct { __IOM uint32_t INTF1 : 16; /*!< [15..0] Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. */ uint32_t : 16; - } bit; - } INTF1; + } INTF1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000041C) Interrupt Status (masked) for IRQ 1 */ + __IOM uint32_t INTS1; /*!< (@ 0x0000041C) Interrupt Status (masked) for IRQ 1 */ struct { __IOM uint32_t INTS1 : 16; /*!< [15..0] Indicates active channel interrupt requests which are @@ -11360,11 +11492,11 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur Channel interrupts can be cleared by writing a bit mask here. */ uint32_t : 16; - } bit; - } INTS1; + } INTS1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000420) Pacing (X/Y) Fractional Timer + __IOM uint32_t TIMER0; /*!< (@ 0x00000420) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles @@ -11377,11 +11509,11 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur (X/Y) fractional timer. */ __IOM uint32_t X : 16; /*!< [31..16] Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */ - } bit; - } TIMER0; + } TIMER0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000424) Pacing (X/Y) Fractional Timer + __IOM uint32_t TIMER1; /*!< (@ 0x00000424) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles @@ -11394,12 +11526,45 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur (X/Y) fractional timer. */ __IOM uint32_t X : 16; /*!< [31..16] Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */ - } bit; - } TIMER1; - __IM uint32_t RESERVED2[2]; + } TIMER1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000430) Trigger one or more channels simultaneously */ + __IOM uint32_t TIMER2; /*!< (@ 0x00000428) Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions + at a rate set by ((X/Y) * sys_clk). This + equation is evaluated every sys_clk cycles + and therefore can only generate TREQs at + a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + + struct { + __IOM uint32_t Y : 16; /*!< [15..0] Pacing Timer Divisor. Specifies the Y value for the + (X/Y) fractional timer. */ + __IOM uint32_t X : 16; /*!< [31..16] Pacing Timer Dividend. Specifies the X value for the + (X/Y) fractional timer. */ + } TIMER2_b; + } ; + + union { + __IOM uint32_t TIMER3; /*!< (@ 0x0000042C) Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions + at a rate set by ((X/Y) * sys_clk). This + equation is evaluated every sys_clk cycles + and therefore can only generate TREQs at + a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + + struct { + __IOM uint32_t Y : 16; /*!< [15..0] Pacing Timer Divisor. Specifies the Y value for the + (X/Y) fractional timer. */ + __IOM uint32_t X : 16; /*!< [31..16] Pacing Timer Dividend. Specifies the X value for the + (X/Y) fractional timer. */ + } TIMER3_b; + } ; + + union { + __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< (@ 0x00000430) Trigger one or more channels simultaneously */ struct { __IOM uint32_t MULTI_CHAN_TRIGGER : 16; /*!< [15..0] Each bit in this register corresponds to a DMA channel. @@ -11407,11 +11572,11 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur to that channel's trigger register; the channel will start if it is currently enabled and not already busy. */ uint32_t : 16; - } bit; - } MULTI_CHAN_TRIGGER; + } MULTI_CHAN_TRIGGER_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000434) Sniffer Control */ + __IOM uint32_t SNIFF_CTRL; /*!< (@ 0x00000434) Sniffer Control */ struct { __IOM uint32_t EN : 1; /*!< [0..0] Enable sniffer */ @@ -11433,8 +11598,8 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur calculated; the result is transformed on-the-fly between the result register and the bus. */ uint32_t : 20; - } bit; - } SNIFF_CTRL; + } SNIFF_CTRL_b; + } ; __IOM uint32_t SNIFF_DATA; /*!< (@ 0x00000438) Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated @@ -11443,21 +11608,21 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur from the indicated channel. Once the channel completes, the final result can be read from this register. */ - __IM uint32_t RESERVED3; + __IM uint32_t RESERVED2; union { - __IOM uint32_t reg; /*!< (@ 0x00000440) Debug RAF, WAF, TDF levels */ + __IOM uint32_t FIFO_LEVELS; /*!< (@ 0x00000440) Debug RAF, WAF, TDF levels */ struct { __IM uint32_t TDF_LVL : 8; /*!< [7..0] Current Transfer-Data-FIFO fill level */ __IM uint32_t WAF_LVL : 8; /*!< [15..8] Current Write-Address-FIFO fill level */ __IM uint32_t RAF_LVL : 8; /*!< [23..16] Current Read-Address-FIFO fill level */ uint32_t : 8; - } bit; - } FIFO_LEVELS; + } FIFO_LEVELS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000444) Abort an in-progress transfer sequence on one + __IOM uint32_t CHAN_ABORT; /*!< (@ 0x00000444) Abort an in-progress transfer sequence on one or more channels */ struct { @@ -11470,11 +11635,11 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur all-zero. Until this point, it is unsafe to restart the channel. */ uint32_t : 16; - } bit; - } CHAN_ABORT; + } CHAN_ABORT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000448) The number of channels this DMA instance is equipped + __IOM uint32_t N_CHANNELS; /*!< (@ 0x00000448) The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. */ @@ -11482,204 +11647,2147 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur struct { __IM uint32_t N_CHANNELS : 5; /*!< [4..0] N_CHANNELS */ uint32_t : 27; - } bit; - } N_CHANNELS; - __IM uint32_t RESERVED4[237]; + } N_CHANNELS_b; + } ; + __IM uint32_t RESERVED3[237]; union { - __IOM uint32_t reg; /*!< (@ 0x00000800) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH0_DBG_CTDREQ; /*!< (@ 0x00000800) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH0_DBG_CTDREQ : 6; /*!< [5..0] CH0_DBG_CTDREQ */ + __IOM uint32_t CH0_DBG_CTDREQ : 6; /*!< [5..0] CH0_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH0_DBG_CTDREQ; + } CH0_DBG_CTDREQ_b; + } ; __IM uint32_t CH0_DBG_TCR; /*!< (@ 0x00000804) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED5[14]; + __IM uint32_t RESERVED4[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000840) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH1_DBG_CTDREQ; /*!< (@ 0x00000840) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH1_DBG_CTDREQ : 6; /*!< [5..0] CH1_DBG_CTDREQ */ + __IOM uint32_t CH1_DBG_CTDREQ : 6; /*!< [5..0] CH1_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH1_DBG_CTDREQ; + } CH1_DBG_CTDREQ_b; + } ; __IM uint32_t CH1_DBG_TCR; /*!< (@ 0x00000844) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED6[14]; + __IM uint32_t RESERVED5[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000880) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH2_DBG_CTDREQ; /*!< (@ 0x00000880) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH2_DBG_CTDREQ : 6; /*!< [5..0] CH2_DBG_CTDREQ */ + __IOM uint32_t CH2_DBG_CTDREQ : 6; /*!< [5..0] CH2_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH2_DBG_CTDREQ; + } CH2_DBG_CTDREQ_b; + } ; __IM uint32_t CH2_DBG_TCR; /*!< (@ 0x00000884) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED7[14]; + __IM uint32_t RESERVED6[14]; union { - __IOM uint32_t reg; /*!< (@ 0x000008C0) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH3_DBG_CTDREQ; /*!< (@ 0x000008C0) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH3_DBG_CTDREQ : 6; /*!< [5..0] CH3_DBG_CTDREQ */ + __IOM uint32_t CH3_DBG_CTDREQ : 6; /*!< [5..0] CH3_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH3_DBG_CTDREQ; + } CH3_DBG_CTDREQ_b; + } ; __IM uint32_t CH3_DBG_TCR; /*!< (@ 0x000008C4) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED8[14]; + __IM uint32_t RESERVED7[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000900) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH4_DBG_CTDREQ; /*!< (@ 0x00000900) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH4_DBG_CTDREQ : 6; /*!< [5..0] CH4_DBG_CTDREQ */ + __IOM uint32_t CH4_DBG_CTDREQ : 6; /*!< [5..0] CH4_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH4_DBG_CTDREQ; + } CH4_DBG_CTDREQ_b; + } ; __IM uint32_t CH4_DBG_TCR; /*!< (@ 0x00000904) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED9[14]; + __IM uint32_t RESERVED8[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000940) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH5_DBG_CTDREQ; /*!< (@ 0x00000940) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH5_DBG_CTDREQ : 6; /*!< [5..0] CH5_DBG_CTDREQ */ + __IOM uint32_t CH5_DBG_CTDREQ : 6; /*!< [5..0] CH5_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH5_DBG_CTDREQ; + } CH5_DBG_CTDREQ_b; + } ; __IM uint32_t CH5_DBG_TCR; /*!< (@ 0x00000944) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED10[14]; + __IM uint32_t RESERVED9[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000980) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH6_DBG_CTDREQ; /*!< (@ 0x00000980) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH6_DBG_CTDREQ : 6; /*!< [5..0] CH6_DBG_CTDREQ */ + __IOM uint32_t CH6_DBG_CTDREQ : 6; /*!< [5..0] CH6_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH6_DBG_CTDREQ; + } CH6_DBG_CTDREQ_b; + } ; __IM uint32_t CH6_DBG_TCR; /*!< (@ 0x00000984) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED11[14]; + __IM uint32_t RESERVED10[14]; union { - __IOM uint32_t reg; /*!< (@ 0x000009C0) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH7_DBG_CTDREQ; /*!< (@ 0x000009C0) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH7_DBG_CTDREQ : 6; /*!< [5..0] CH7_DBG_CTDREQ */ + __IOM uint32_t CH7_DBG_CTDREQ : 6; /*!< [5..0] CH7_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH7_DBG_CTDREQ; + } CH7_DBG_CTDREQ_b; + } ; __IM uint32_t CH7_DBG_TCR; /*!< (@ 0x000009C4) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED12[14]; + __IM uint32_t RESERVED11[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000A00) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH8_DBG_CTDREQ; /*!< (@ 0x00000A00) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH8_DBG_CTDREQ : 6; /*!< [5..0] CH8_DBG_CTDREQ */ + __IOM uint32_t CH8_DBG_CTDREQ : 6; /*!< [5..0] CH8_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH8_DBG_CTDREQ; + } CH8_DBG_CTDREQ_b; + } ; __IM uint32_t CH8_DBG_TCR; /*!< (@ 0x00000A04) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED13[14]; + __IM uint32_t RESERVED12[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000A40) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH9_DBG_CTDREQ; /*!< (@ 0x00000A40) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH9_DBG_CTDREQ : 6; /*!< [5..0] CH9_DBG_CTDREQ */ + __IOM uint32_t CH9_DBG_CTDREQ : 6; /*!< [5..0] CH9_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH9_DBG_CTDREQ; + } CH9_DBG_CTDREQ_b; + } ; __IM uint32_t CH9_DBG_TCR; /*!< (@ 0x00000A44) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED14[14]; + __IM uint32_t RESERVED13[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000A80) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH10_DBG_CTDREQ; /*!< (@ 0x00000A80) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH10_DBG_CTDREQ : 6; /*!< [5..0] CH10_DBG_CTDREQ */ + __IOM uint32_t CH10_DBG_CTDREQ : 6; /*!< [5..0] CH10_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH10_DBG_CTDREQ; + } CH10_DBG_CTDREQ_b; + } ; __IM uint32_t CH10_DBG_TCR; /*!< (@ 0x00000A84) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED15[14]; + __IM uint32_t RESERVED14[14]; union { - __IOM uint32_t reg; /*!< (@ 0x00000AC0) Read: get channel DREQ counter (i.e. how many + __IOM uint32_t CH11_DBG_CTDREQ; /*!< (@ 0x00000AC0) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ struct { - __IM uint32_t CH11_DBG_CTDREQ : 6; /*!< [5..0] CH11_DBG_CTDREQ */ + __IOM uint32_t CH11_DBG_CTDREQ : 6; /*!< [5..0] CH11_DBG_CTDREQ */ uint32_t : 26; - } bit; - } CH11_DBG_CTDREQ; + } CH11_DBG_CTDREQ_b; + } ; __IM uint32_t CH11_DBG_TCR; /*!< (@ 0x00000AC4) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ } DMA_Type; /*!< Size = 2760 (0xac8) */ +/* =========================================================================================================================== */ +/* ================ USBCTRL_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USBCTRL_DPRAM) + */ + +typedef struct { /*!< (@ 0x50100000) USBCTRL_DPRAM Structure */ + + union { + __IOM uint32_t SETUP_PACKET_LOW; /*!< (@ 0x00000000) Bytes 0-3 of the SETUP packet from the host. */ + + struct { + __IOM uint32_t BMREQUESTTYPE : 8; /*!< [7..0] BMREQUESTTYPE */ + __IOM uint32_t BREQUEST : 8; /*!< [15..8] BREQUEST */ + __IOM uint32_t WVALUE : 16; /*!< [31..16] WVALUE */ + } SETUP_PACKET_LOW_b; + } ; + + union { + __IOM uint32_t SETUP_PACKET_HIGH; /*!< (@ 0x00000004) Bytes 4-7 of the setup packet from the host. */ + + struct { + __IOM uint32_t WINDEX : 16; /*!< [15..0] WINDEX */ + __IOM uint32_t WLENGTH : 16; /*!< [31..16] WLENGTH */ + } SETUP_PACKET_HIGH_b; + } ; + + union { + __IOM uint32_t EP1_IN_CONTROL; /*!< (@ 0x00000008) EP1_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP1_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP1_OUT_CONTROL; /*!< (@ 0x0000000C) EP1_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP1_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP2_IN_CONTROL; /*!< (@ 0x00000010) EP2_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP2_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP2_OUT_CONTROL; /*!< (@ 0x00000014) EP2_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP2_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP3_IN_CONTROL; /*!< (@ 0x00000018) EP3_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP3_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP3_OUT_CONTROL; /*!< (@ 0x0000001C) EP3_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP3_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP4_IN_CONTROL; /*!< (@ 0x00000020) EP4_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP4_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP4_OUT_CONTROL; /*!< (@ 0x00000024) EP4_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP4_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP5_IN_CONTROL; /*!< (@ 0x00000028) EP5_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP5_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP5_OUT_CONTROL; /*!< (@ 0x0000002C) EP5_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP5_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP6_IN_CONTROL; /*!< (@ 0x00000030) EP6_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP6_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP6_OUT_CONTROL; /*!< (@ 0x00000034) EP6_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP6_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP7_IN_CONTROL; /*!< (@ 0x00000038) EP7_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP7_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP7_OUT_CONTROL; /*!< (@ 0x0000003C) EP7_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP7_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP8_IN_CONTROL; /*!< (@ 0x00000040) EP8_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP8_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP8_OUT_CONTROL; /*!< (@ 0x00000044) EP8_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP8_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP9_IN_CONTROL; /*!< (@ 0x00000048) EP9_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP9_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP9_OUT_CONTROL; /*!< (@ 0x0000004C) EP9_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP9_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP10_IN_CONTROL; /*!< (@ 0x00000050) EP10_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP10_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP10_OUT_CONTROL; /*!< (@ 0x00000054) EP10_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP10_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP11_IN_CONTROL; /*!< (@ 0x00000058) EP11_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP11_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP11_OUT_CONTROL; /*!< (@ 0x0000005C) EP11_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP11_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP12_IN_CONTROL; /*!< (@ 0x00000060) EP12_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP12_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP12_OUT_CONTROL; /*!< (@ 0x00000064) EP12_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP12_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP13_IN_CONTROL; /*!< (@ 0x00000068) EP13_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP13_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP13_OUT_CONTROL; /*!< (@ 0x0000006C) EP13_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP13_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP14_IN_CONTROL; /*!< (@ 0x00000070) EP14_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP14_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP14_OUT_CONTROL; /*!< (@ 0x00000074) EP14_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP14_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP15_IN_CONTROL; /*!< (@ 0x00000078) EP15_IN_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP15_IN_CONTROL_b; + } ; + + union { + __IOM uint32_t EP15_OUT_CONTROL; /*!< (@ 0x0000007C) EP15_OUT_CONTROL */ + + struct { + __IOM uint32_t BUFFER_ADDRESS : 16; /*!< [15..0] 64 byte aligned buffer address for this EP (bits 0-5 + are ignored). Relative to the start of the DPRAM. */ + __IOM uint32_t INTERRUPT_ON_NAK : 1; /*!< [16..16] Trigger an interrupt if a NAK is sent. Intended for + debug only. */ + __IOM uint32_t INTERRUPT_ON_STALL : 1; /*!< [17..17] Trigger an interrupt if a STALL is sent. Intended for + debug only. */ + uint32_t : 8; + __IOM uint32_t ENDPOINT_TYPE : 2; /*!< [27..26] ENDPOINT_TYPE */ + __IOM uint32_t INTERRUPT_PER_DOUBLE_BUFF : 1;/*!< [28..28] Trigger an interrupt each time both buffers are done. + Only valid in double buffered mode. */ + __IOM uint32_t INTERRUPT_PER_BUFF : 1; /*!< [29..29] Trigger an interrupt each time a buffer is done. */ + __IOM uint32_t DOUBLE_BUFFERED : 1; /*!< [30..30] This endpoint is double buffered. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Enable this endpoint. The device will not reply to + any packets for this endpoint if this bit is not set. */ + } EP15_OUT_CONTROL_b; + } ; + + union { + __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< (@ 0x00000080) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP0_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< (@ 0x00000084) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP0_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< (@ 0x00000088) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP1_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< (@ 0x0000008C) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP1_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< (@ 0x00000090) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP2_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< (@ 0x00000094) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP2_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< (@ 0x00000098) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP3_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< (@ 0x0000009C) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP3_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< (@ 0x000000A0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP4_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< (@ 0x000000A4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP4_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< (@ 0x000000A8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP5_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< (@ 0x000000AC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP5_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< (@ 0x000000B0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP6_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< (@ 0x000000B4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP6_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< (@ 0x000000B8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP7_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< (@ 0x000000BC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP7_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< (@ 0x000000C0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP8_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< (@ 0x000000C4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP8_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< (@ 0x000000C8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP9_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< (@ 0x000000CC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP9_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< (@ 0x000000D0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP10_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< (@ 0x000000D4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP10_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< (@ 0x000000D8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP11_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< (@ 0x000000DC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP11_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< (@ 0x000000E0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP12_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< (@ 0x000000E4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP12_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< (@ 0x000000E8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP13_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< (@ 0x000000EC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP13_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< (@ 0x000000F0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP14_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< (@ 0x000000F4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP14_OUT_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< (@ 0x000000F8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP15_IN_BUFFER_CONTROL_b; + } ; + + union { + __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< (@ 0x000000FC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + + struct { + __IOM uint32_t LENGTH_0 : 10; /*!< [9..0] The length of the data in buffer 0. */ + __IOM uint32_t AVAILABLE_0 : 1; /*!< [10..10] Buffer 0 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t STALL : 1; /*!< [11..11] Reply with a stall (valid for both buffers). */ + __IOM uint32_t RESET : 1; /*!< [12..12] Reset the buffer selector to buffer 0. */ + __IOM uint32_t PID_0 : 1; /*!< [13..13] The data pid of buffer 0. */ + __IOM uint32_t LAST_0 : 1; /*!< [14..14] Buffer 0 is the last buffer of the transfer. */ + __IOM uint32_t FULL_0 : 1; /*!< [15..15] Buffer 0 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + __IOM uint32_t LENGTH_1 : 10; /*!< [25..16] The length of the data in buffer 1. */ + __IOM uint32_t AVAILABLE_1 : 1; /*!< [26..26] Buffer 1 is available. This bit is set to indicate + the buffer can be used by the controller. The controller + clears the available bit when writing the status back. */ + __IOM uint32_t DOUBLE_BUFFER_ISO_OFFSET : 2;/*!< [28..27] The number of bytes buffer 1 is offset from buffer + 0 in Isochronous mode. Only valid in double buffered mode + for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 + bytes. */ + __IOM uint32_t PID_1 : 1; /*!< [29..29] The data pid of buffer 1. */ + __IOM uint32_t LAST_1 : 1; /*!< [30..30] Buffer 1 is the last buffer of the transfer. */ + __IOM uint32_t FULL_1 : 1; /*!< [31..31] Buffer 1 is full. For an IN transfer (TX to the host) + the bit is set to indicate the data is valid. For an OUT + transfer (RX from the host) this bit should be left as + a 0. The host will set it when it has filled the buffer + with data. */ + } EP15_OUT_BUFFER_CONTROL_b; + } ; +} USBCTRL_DPRAM_Type; /*!< Size = 256 (0x100) */ + + + /* =========================================================================================================================== */ /* ================ USBCTRL_REGS ================ */ /* =========================================================================================================================== */ @@ -11692,7 +13800,7 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Device address and endpoint control */ + __IOM uint32_t ADDR_ENDP; /*!< (@ 0x00000000) Device address and endpoint control */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] In device mode, the address that the device should respond @@ -11703,11 +13811,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Device endpoint to send data to. Only valid for HOST mode. */ uint32_t : 12; - } bit; - } ADDR_ENDP; + } ADDR_ENDP_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Interrupt endpoint 1. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP1; /*!< (@ 0x00000004) Interrupt endpoint 1. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11718,11 +13826,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP1; + } ADDR_ENDP1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Interrupt endpoint 2. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP2; /*!< (@ 0x00000008) Interrupt endpoint 2. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11733,11 +13841,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP2; + } ADDR_ENDP2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Interrupt endpoint 3. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP3; /*!< (@ 0x0000000C) Interrupt endpoint 3. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11748,11 +13856,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP3; + } ADDR_ENDP3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Interrupt endpoint 4. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP4; /*!< (@ 0x00000010) Interrupt endpoint 4. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11763,11 +13871,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP4; + } ADDR_ENDP4_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Interrupt endpoint 5. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP5; /*!< (@ 0x00000014) Interrupt endpoint 5. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11778,11 +13886,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP5; + } ADDR_ENDP5_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Interrupt endpoint 6. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP6; /*!< (@ 0x00000018) Interrupt endpoint 6. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11793,11 +13901,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP6; + } ADDR_ENDP6_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Interrupt endpoint 7. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP7; /*!< (@ 0x0000001C) Interrupt endpoint 7. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11808,11 +13916,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP7; + } ADDR_ENDP7_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Interrupt endpoint 8. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP8; /*!< (@ 0x00000020) Interrupt endpoint 8. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11823,11 +13931,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP8; + } ADDR_ENDP8_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Interrupt endpoint 9. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP9; /*!< (@ 0x00000024) Interrupt endpoint 9. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11838,11 +13946,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP9; + } ADDR_ENDP9_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Interrupt endpoint 10. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP10; /*!< (@ 0x00000028) Interrupt endpoint 10. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11853,11 +13961,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP10; + } ADDR_ENDP10_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Interrupt endpoint 11. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP11; /*!< (@ 0x0000002C) Interrupt endpoint 11. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11868,11 +13976,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP11; + } ADDR_ENDP11_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Interrupt endpoint 12. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP12; /*!< (@ 0x00000030) Interrupt endpoint 12. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11883,11 +13991,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP12; + } ADDR_ENDP12_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Interrupt endpoint 13. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP13; /*!< (@ 0x00000034) Interrupt endpoint 13. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11898,11 +14006,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP13; + } ADDR_ENDP13_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt endpoint 14. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP14; /*!< (@ 0x00000038) Interrupt endpoint 14. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11913,11 +14021,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP14; + } ADDR_ENDP14_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Interrupt endpoint 15. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP15; /*!< (@ 0x0000003C) Interrupt endpoint 15. Only valid for HOST mode. */ struct { __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ @@ -11928,22 +14036,22 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device on a full speed hub) */ uint32_t : 5; - } bit; - } ADDR_ENDP15; + } ADDR_ENDP15_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Main control register */ + __IOM uint32_t MAIN_CTRL; /*!< (@ 0x00000040) Main control register */ struct { __IOM uint32_t CONTROLLER_EN : 1; /*!< [0..0] Enable controller */ __IOM uint32_t HOST_NDEVICE : 1; /*!< [1..1] Device mode = 0, Host mode = 1 */ uint32_t : 29; __IOM uint32_t SIM_TIMING : 1; /*!< [31..31] Reduced timings for simulation */ - } bit; - } MAIN_CTRL; + } MAIN_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Set the SOF (Start of Frame) frame number in + __IOM uint32_t SOF_WR; /*!< (@ 0x00000044) Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. */ @@ -11951,11 +14059,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS struct { __OM uint32_t COUNT : 11; /*!< [10..0] COUNT */ uint32_t : 21; - } bit; - } SOF_WR; + } SOF_WR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Read the last SOF (Start of Frame) frame number + __IOM uint32_t SOF_RD; /*!< (@ 0x00000048) Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. */ @@ -11963,11 +14071,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS struct { __IM uint32_t COUNT : 11; /*!< [10..0] COUNT */ uint32_t : 21; - } bit; - } SOF_RD; + } SOF_RD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) SIE control register */ + __IOM uint32_t SIE_CTRL; /*!< (@ 0x0000004C) SIE control register */ struct { __IOM uint32_t START_TRANS : 1; /*!< [0..0] Host: Start transaction */ @@ -12004,27 +14112,27 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS 1 */ __IOM uint32_t EP0_INT_STALL : 1; /*!< [31..31] Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL */ - } bit; - } SIE_CTRL; + } SIE_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) SIE status register */ + __IOM uint32_t SIE_STATUS; /*!< (@ 0x00000050) SIE status register */ struct { __IM uint32_t VBUS_DETECTED : 1; /*!< [0..0] Device: VBUS Detected */ uint32_t : 1; __IM uint32_t LINE_STATE : 2; /*!< [3..2] USB bus line state */ - __IM uint32_t SUSPENDED : 1; /*!< [4..4] Bus in suspended state. Valid for device and host. Host + __IOM uint32_t SUSPENDED : 1; /*!< [4..4] Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. */ uint32_t : 3; - __IM uint32_t SPEED : 2; /*!< [9..8] Host: device speed. Disconnected = 00, LS = 01, FS = + __IOM uint32_t SPEED : 2; /*!< [9..8] Host: device speed. Disconnected = 00, LS = 01, FS = 10 */ __IM uint32_t VBUS_OVER_CURR : 1; /*!< [10..10] VBUS over current detected */ __IOM uint32_t RESUME : 1; /*!< [11..11] Host: Device has initiated a remote resume. Device: host has initiated a resume. */ uint32_t : 4; - __IM uint32_t CONNECTED : 1; /*!< [16..16] Device: connected */ + __IOM uint32_t CONNECTED : 1; /*!< [16..16] Device: connected */ __IOM uint32_t SETUP_REC : 1; /*!< [17..17] Device: Setup packet received */ __IOM uint32_t TRANS_COMPLETE : 1; /*!< [18..18] Transaction complete. @@ -12066,21 +14174,21 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS conditions: * An IN packet from the device has the wrong data PID */ - } bit; - } SIE_STATUS; + } SIE_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) interrupt endpoint control register */ + __IOM uint32_t INT_EP_CTRL; /*!< (@ 0x00000054) interrupt endpoint control register */ struct { uint32_t : 1; __IOM uint32_t INT_EP_ACTIVE : 15; /*!< [15..1] Host: Enable interrupt endpoint 1 -> 15 */ uint32_t : 16; - } bit; - } INT_EP_CTRL; + } INT_EP_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Buffer status register. A bit set here indicates + __IOM uint32_t BUFF_STATUS; /*!< (@ 0x00000058) Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, @@ -12088,43 +14196,43 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS re set it on the next clock cycle. */ struct { - __IM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - __IM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ - __IM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ - __IM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ - __IM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ - __IM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ - __IM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ - __IM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ - __IM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ - __IM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ - __IM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ - __IM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ - __IM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ - __IM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ - __IM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ - __IM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ - __IM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ - __IM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ - __IM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ - __IM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ - __IM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ - __IM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ - __IM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ - __IM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ - __IM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ - __IM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ - __IM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ - __IM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ - __IM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ - __IM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ - __IM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } BUFF_STATUS; + __IOM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ + __IOM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ + __IOM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ + __IOM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ + __IOM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ + __IOM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ + __IOM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ + __IOM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ + __IOM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ + __IOM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ + __IOM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ + __IOM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ + __IOM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ + __IOM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ + __IOM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ + __IOM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ + __IOM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ + __IOM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ + __IOM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ + __IOM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ + __IOM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ + __IOM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ + __IOM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ + __IOM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ + __IOM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ + __IOM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ + __IOM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ + __IOM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ + __IOM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ + __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ + __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ + __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ + } BUFF_STATUS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Which of the double buffers should be handled. + __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< (@ 0x0000005C) Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because @@ -12163,11 +14271,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ __IM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ __IM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } BUFF_CPU_SHOULD_HANDLE; + } BUFF_CPU_SHOULD_HANDLE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Device only: Can be set to ignore the buffer + __IOM uint32_t EP_ABORT; /*!< (@ 0x00000060) Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint @@ -12208,11 +14316,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } EP_ABORT; + } EP_ABORT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Device only: Used in conjunction with `EP_ABORT`. + __IOM uint32_t EP_ABORT_DONE; /*!< (@ 0x00000064) Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. */ @@ -12250,11 +14358,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } EP_ABORT_DONE; + } EP_ABORT_DONE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Device: this bit must be set in conjunction with + __IOM uint32_t EP_STALL_ARM; /*!< (@ 0x00000068) Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is @@ -12266,11 +14374,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ __IOM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ uint32_t : 30; - } bit; - } EP_STALL_ARM; + } EP_STALL_ARM_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Used by the host controller. Sets the wait time + __IOM uint32_t NAK_POLL; /*!< (@ 0x0000006C) Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. */ @@ -12279,11 +14387,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS uint32_t : 6; __IOM uint32_t DELAY_FS : 10; /*!< [25..16] NAK polling interval for a full speed device */ uint32_t : 6; - } bit; - } NAK_POLL; + } NAK_POLL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Device: bits are set when the `IRQ_ON_NAK` or + __IOM uint32_t EP_STATUS_STALL_NAK; /*!< (@ 0x00000070) Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. */ @@ -12321,11 +14429,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } EP_STATUS_STALL_NAK; + } EP_STATUS_STALL_NAK_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Where to connect the USB controller. Should be + __IOM uint32_t USB_MUXING; /*!< (@ 0x00000074) Where to connect the USB controller. Should be to_phy by default. */ struct { @@ -12334,11 +14442,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t TO_DIGITAL_PAD : 1; /*!< [2..2] TO_DIGITAL_PAD */ __IOM uint32_t SOFTCON : 1; /*!< [3..3] SOFTCON */ uint32_t : 28; - } bit; - } USB_MUXING; + } USB_MUXING_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Overrides for the power signals in the event + __IOM uint32_t USB_PWR; /*!< (@ 0x00000078) Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over @@ -12352,11 +14460,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t OVERCURR_DETECT : 1; /*!< [4..4] OVERCURR_DETECT */ __IOM uint32_t OVERCURR_DETECT_EN : 1; /*!< [5..5] OVERCURR_DETECT_EN */ uint32_t : 26; - } bit; - } USB_PWR; + } USB_PWR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) This register allows for direct control of the + __IOM uint32_t USBPHY_DIRECT; /*!< (@ 0x0000007C) This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. */ @@ -12402,11 +14510,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IM uint32_t DP_OVV : 1; /*!< [21..21] DP over voltage */ __IM uint32_t DM_OVV : 1; /*!< [22..22] DM over voltage */ uint32_t : 9; - } bit; - } USBPHY_DIRECT; + } USBPHY_DIRECT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Override enable for each control in usbphy_direct */ + __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< (@ 0x00000080) Override enable for each control in usbphy_direct */ struct { __IOM uint32_t DP_PULLUP_HISEL_OVERRIDE_EN : 1;/*!< [0..0] DP_PULLUP_HISEL_OVERRIDE_EN */ @@ -12425,11 +14533,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS uint32_t : 2; __IOM uint32_t TX_DIFFMODE_OVERRIDE_EN : 1;/*!< [15..15] TX_DIFFMODE_OVERRIDE_EN */ uint32_t : 16; - } bit; - } USBPHY_DIRECT_OVERRIDE; + } USBPHY_DIRECT_OVERRIDE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Used to adjust trim values of USB phy pull down + __IOM uint32_t USBPHY_TRIM; /*!< (@ 0x00000084) Used to adjust trim values of USB phy pull down resistors. */ struct { @@ -12443,12 +14551,12 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS Experimental data suggests that the reset value will work, but this register allows adjustment if required */ uint32_t : 19; - } bit; - } USBPHY_TRIM; + } USBPHY_TRIM_b; + } ; __IM uint32_t RESERVED; union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Raw Interrupts */ + __IOM uint32_t INTR; /*!< (@ 0x0000008C) Raw Interrupts */ struct { __IM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected @@ -12468,7 +14576,7 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ __IM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ __IM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ + __IM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECTED */ __IM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ __IM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ @@ -12484,11 +14592,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ uint32_t : 12; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000090) Interrupt Enable */ + __IOM uint32_t INTE; /*!< (@ 0x00000090) Interrupt Enable */ struct { __IOM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected @@ -12508,7 +14616,7 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ __IOM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ __IOM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IOM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ + __IOM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECTED */ __IOM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ __IOM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ @@ -12524,11 +14632,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ uint32_t : 12; - } bit; - } INTE; + } INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Interrupt Force */ + __IOM uint32_t INTF; /*!< (@ 0x00000094) Interrupt Force */ struct { __IOM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected @@ -12548,7 +14656,7 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ __IOM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ __IOM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IOM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ + __IOM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECTED */ __IOM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ __IOM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ @@ -12564,11 +14672,11 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IOM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ uint32_t : 12; - } bit; - } INTF; + } INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Interrupt status after masking & forcing */ + __IOM uint32_t INTS; /*!< (@ 0x00000098) Interrupt status after masking & forcing */ struct { __IM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected @@ -12588,7 +14696,7 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ __IM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ __IM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ + __IM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECTED */ __IM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ __IM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */ @@ -12604,8 +14712,8 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS __IM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */ uint32_t : 12; - } bit; - } INTS; + } INTS_b; + } ; } USBCTRL_REGS_Type; /*!< Size = 156 (0x9c) */ @@ -12622,23 +14730,43 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS typedef struct { /*!< (@ 0x50200000) PIO0 Structure */ union { - __IOM uint32_t reg; /*!< (@ 0x00000000) PIO control register */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) PIO control register */ struct { - __IOM uint32_t SM_ENABLE : 4; /*!< [3..0] Enable state machine */ - __IOM uint32_t SM_RESTART : 4; /*!< [7..4] Clear internal SM state which is otherwise difficult - to access - (e.g. shift counters). Self-clearing. */ - __IOM uint32_t CLKDIV_RESTART : 4; /*!< [11..8] Force clock dividers to restart their count and clear - fractional - accumulators. Restart multiple dividers to synchronise - them. */ + __IOM uint32_t SM_ENABLE : 4; /*!< [3..0] Enable/disable each of the four state machines by writing + 1/0 to each of these four bits. When disabled, a state + machine will cease executing instructions, except those + written directly to SMx_INSTR by the system. Multiple bits + can be set/cleared at once to run/halt multiple state machines + simultaneously. */ + __IOM uint32_t SM_RESTART : 4; /*!< [7..4] Write 1 to instantly clear internal SM state which may + be otherwise difficult to access and will affect future + execution. + + Specifically, the following are cleared: input and output + shift counters; the contents of the input shift register; + the delay counter; the waiting-on-IRQ state; any stalled + instruction written to SMx_INSTR or run by OUT/MOV EXEC; + any pin write left asserted due to OUT_STICKY. + + The program counter, the contents of the output shift register + and the */ + __IOM uint32_t CLKDIV_RESTART : 4; /*!< [11..8] Restart a state machine's clock divider from an initial + phase of 0. Clock dividers are free-running, so once started, + their output (including fractional jitter) is completely + determined by the integer/fractional divisor configured + in SMx_CLKDIV. This means that, if multiple clock dividers + with the same divisor are restarted simultaneously, by + writing multiple 1 bits to this field, the execution clocks + of those state machines will run in precise lockstep. + + Note that setting/clearing SM_E */ uint32_t : 20; - } bit; - } CTRL; + } CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000004) FIFO status register */ + __IOM uint32_t FSTAT; /*!< (@ 0x00000004) FIFO status register */ struct { __IM uint32_t RXFULL : 4; /*!< [3..0] State machine RX FIFO is full */ @@ -12649,28 +14777,42 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu uint32_t : 4; __IM uint32_t TXEMPTY : 4; /*!< [27..24] State machine TX FIFO is empty */ uint32_t : 4; - } bit; - } FSTAT; + } FSTAT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) FIFO debug register */ + __IOM uint32_t FDEBUG; /*!< (@ 0x00000008) FIFO debug register */ struct { - __IOM uint32_t RXSTALL : 4; /*!< [3..0] State machine has stalled on full RX FIFO. Write 1 to - clear. */ + __IOM uint32_t RXSTALL : 4; /*!< [3..0] State machine has stalled on full RX FIFO during a blocking + PUSH, or an IN with autopush enabled. This flag is also + set when a nonblocking PUSH to a full FIFO took place, + in which case the state machine has dropped data. Write + 1 to clear. */ uint32_t : 4; - __IOM uint32_t RXUNDER : 4; /*!< [11..8] RX FIFO underflow has occurred. Write 1 to clear. */ + __IOM uint32_t RXUNDER : 4; /*!< [11..8] RX FIFO underflow (i.e. read-on-empty by the system) + has occurred. Write 1 to clear. Note that read-on-empty + does not perturb the state of the FIFO in any way, but + the data returned by reading from an empty FIFO is undefined, + so this flag generally only becomes set due to some kind + of software error. */ uint32_t : 4; - __IOM uint32_t TXOVER : 4; /*!< [19..16] TX FIFO overflow has occurred. Write 1 to clear. */ + __IOM uint32_t TXOVER : 4; /*!< [19..16] TX FIFO overflow (i.e. write-on-full by the system) + has occurred. Write 1 to clear. Note that write-on-full + does not alter the state or contents of the FIFO in any + way, but the data that the system attempted to write is + dropped, so if this flag is set, your software has quite + likely dropped some data on the floor. */ uint32_t : 4; - __IOM uint32_t TXSTALL : 4; /*!< [27..24] State machine has stalled on empty TX FIFO. Write 1 + __IOM uint32_t TXSTALL : 4; /*!< [27..24] State machine has stalled on empty TX FIFO during a + blocking PULL, or an OUT with autopull enabled. Write 1 to clear. */ uint32_t : 4; - } bit; - } FDEBUG; + } FDEBUG_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) FIFO levels */ + __IOM uint32_t FLEVEL; /*!< (@ 0x0000000C) FIFO levels */ struct { __IM uint32_t TX0 : 4; /*!< [3..0] TX0 */ @@ -12681,75 +14823,117 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IM uint32_t RX2 : 4; /*!< [23..20] RX2 */ __IM uint32_t TX3 : 4; /*!< [27..24] TX3 */ __IM uint32_t RX3 : 4; /*!< [31..28] RX3 */ - } bit; - } FLEVEL; + } FLEVEL_b; + } ; __OM uint32_t TXF0; /*!< (@ 0x00000010) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __OM uint32_t TXF1; /*!< (@ 0x00000014) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __OM uint32_t TXF2; /*!< (@ 0x00000018) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __OM uint32_t TXF3; /*!< (@ 0x0000001C) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __IM uint32_t RXF0; /*!< (@ 0x00000020) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ __IM uint32_t RXF1; /*!< (@ 0x00000024) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ __IM uint32_t RXF2; /*!< (@ 0x00000028) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ __IM uint32_t RXF3; /*!< (@ 0x0000002C) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Interrupt request register. Write 1 to clear */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ + + union { + __IOM uint32_t IRQ; /*!< (@ 0x00000030) State machine IRQ flags register. Write 1 to + clear. There are 8 state machine IRQ flags, + which can be set, cleared, and waited on + by the state machines. There's no fixed + association between flags and state machines + -- any state machine can use any flag. + + Any of the 8 flags can be used for timing + synchronisation between state machines, + using IRQ and WAIT instructions. The lower + four of these flags are also routed out + to system-level interrupt requests, alongside + FIFO status in */ struct { __IOM uint32_t IRQ : 8; /*!< [7..0] IRQ */ uint32_t : 24; - } bit; - } IRQ; + } IRQ_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Writing a 1 to each of these bits will forcibly - assert the corresponding IRQ. - Note this is different to the INTF register: - writing here affects PIO internal - state. INTF just asserts the processor-facing - IRQ signal for testing ISRs, - and is not visible to the state machines. */ + __IOM uint32_t IRQ_FORCE; /*!< (@ 0x00000034) Writing a 1 to each of these bits will forcibly + assert the corresponding IRQ. Note this + is different to the INTF register: writing + here affects PIO internal state. INTF just + asserts the processor-facing IRQ signal + for testing ISRs, and is not visible to + the state machines. */ struct { __OM uint32_t IRQ_FORCE : 8; /*!< [7..0] IRQ_FORCE */ uint32_t : 24; - } bit; - } IRQ_FORCE; + } IRQ_FORCE_b; + } ; __IOM uint32_t INPUT_SYNC_BYPASS; /*!< (@ 0x00000038) There is a 2-flipflop synchronizer on each GPIO - input, which protects - PIO logic from metastabilities. This increases - input delay, and for fast + input, which protects PIO logic from metastabilities. + This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers - may need to be bypassed. - Each bit in this register corresponds to - one GPIO. + may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. */ __IM uint32_t DBG_PADOUT; /*!< (@ 0x0000003C) Read to sample the pad output values PIO is currently - driving to the GPIOs. */ + driving to the GPIOs. On RP2040 there are + 30 GPIOs, so the two most significant bits + are hardwired to 0. */ __IM uint32_t DBG_PADOE; /*!< (@ 0x00000040) Read to sample the pad output enables (direction) - PIO is currently driving to the GPIOs. */ + PIO is currently driving to the GPIOs. On + RP2040 there are 30 GPIOs, so the two most + significant bits are hardwired to 0. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000044) The PIO hardware has some free parameters that + __IOM uint32_t DBG_CFGINFO; /*!< (@ 0x00000044) The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. */ @@ -12766,344 +14950,345 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IM uint32_t IMEM_SIZE : 6; /*!< [21..16] The size of the instruction memory, measured in units of one instruction */ uint32_t : 10; - } bit; - } DBG_CFGINFO; + } DBG_CFGINFO_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM0; /*!< (@ 0x00000048) Write-only access to instruction memory location 0 */ struct { - __IOM uint32_t INSTR_MEM0 : 16; /*!< [15..0] INSTR_MEM0 */ + __OM uint32_t INSTR_MEM0 : 16; /*!< [15..0] INSTR_MEM0 */ uint32_t : 16; - } bit; - } INSTR_MEM0; + } INSTR_MEM0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM1; /*!< (@ 0x0000004C) Write-only access to instruction memory location 1 */ struct { - __IOM uint32_t INSTR_MEM1 : 16; /*!< [15..0] INSTR_MEM1 */ + __OM uint32_t INSTR_MEM1 : 16; /*!< [15..0] INSTR_MEM1 */ uint32_t : 16; - } bit; - } INSTR_MEM1; + } INSTR_MEM1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM2; /*!< (@ 0x00000050) Write-only access to instruction memory location 2 */ struct { - __IOM uint32_t INSTR_MEM2 : 16; /*!< [15..0] INSTR_MEM2 */ + __OM uint32_t INSTR_MEM2 : 16; /*!< [15..0] INSTR_MEM2 */ uint32_t : 16; - } bit; - } INSTR_MEM2; + } INSTR_MEM2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM3; /*!< (@ 0x00000054) Write-only access to instruction memory location 3 */ struct { - __IOM uint32_t INSTR_MEM3 : 16; /*!< [15..0] INSTR_MEM3 */ + __OM uint32_t INSTR_MEM3 : 16; /*!< [15..0] INSTR_MEM3 */ uint32_t : 16; - } bit; - } INSTR_MEM3; + } INSTR_MEM3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM4; /*!< (@ 0x00000058) Write-only access to instruction memory location 4 */ struct { - __IOM uint32_t INSTR_MEM4 : 16; /*!< [15..0] INSTR_MEM4 */ + __OM uint32_t INSTR_MEM4 : 16; /*!< [15..0] INSTR_MEM4 */ uint32_t : 16; - } bit; - } INSTR_MEM4; + } INSTR_MEM4_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM5; /*!< (@ 0x0000005C) Write-only access to instruction memory location 5 */ struct { - __IOM uint32_t INSTR_MEM5 : 16; /*!< [15..0] INSTR_MEM5 */ + __OM uint32_t INSTR_MEM5 : 16; /*!< [15..0] INSTR_MEM5 */ uint32_t : 16; - } bit; - } INSTR_MEM5; + } INSTR_MEM5_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM6; /*!< (@ 0x00000060) Write-only access to instruction memory location 6 */ struct { - __IOM uint32_t INSTR_MEM6 : 16; /*!< [15..0] INSTR_MEM6 */ + __OM uint32_t INSTR_MEM6 : 16; /*!< [15..0] INSTR_MEM6 */ uint32_t : 16; - } bit; - } INSTR_MEM6; + } INSTR_MEM6_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM7; /*!< (@ 0x00000064) Write-only access to instruction memory location 7 */ struct { - __IOM uint32_t INSTR_MEM7 : 16; /*!< [15..0] INSTR_MEM7 */ + __OM uint32_t INSTR_MEM7 : 16; /*!< [15..0] INSTR_MEM7 */ uint32_t : 16; - } bit; - } INSTR_MEM7; + } INSTR_MEM7_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM8; /*!< (@ 0x00000068) Write-only access to instruction memory location 8 */ struct { - __IOM uint32_t INSTR_MEM8 : 16; /*!< [15..0] INSTR_MEM8 */ + __OM uint32_t INSTR_MEM8 : 16; /*!< [15..0] INSTR_MEM8 */ uint32_t : 16; - } bit; - } INSTR_MEM8; + } INSTR_MEM8_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM9; /*!< (@ 0x0000006C) Write-only access to instruction memory location 9 */ struct { - __IOM uint32_t INSTR_MEM9 : 16; /*!< [15..0] INSTR_MEM9 */ + __OM uint32_t INSTR_MEM9 : 16; /*!< [15..0] INSTR_MEM9 */ uint32_t : 16; - } bit; - } INSTR_MEM9; + } INSTR_MEM9_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM10; /*!< (@ 0x00000070) Write-only access to instruction memory location 10 */ struct { - __IOM uint32_t INSTR_MEM10 : 16; /*!< [15..0] INSTR_MEM10 */ + __OM uint32_t INSTR_MEM10 : 16; /*!< [15..0] INSTR_MEM10 */ uint32_t : 16; - } bit; - } INSTR_MEM10; + } INSTR_MEM10_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM11; /*!< (@ 0x00000074) Write-only access to instruction memory location 11 */ struct { - __IOM uint32_t INSTR_MEM11 : 16; /*!< [15..0] INSTR_MEM11 */ + __OM uint32_t INSTR_MEM11 : 16; /*!< [15..0] INSTR_MEM11 */ uint32_t : 16; - } bit; - } INSTR_MEM11; + } INSTR_MEM11_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM12; /*!< (@ 0x00000078) Write-only access to instruction memory location 12 */ struct { - __IOM uint32_t INSTR_MEM12 : 16; /*!< [15..0] INSTR_MEM12 */ + __OM uint32_t INSTR_MEM12 : 16; /*!< [15..0] INSTR_MEM12 */ uint32_t : 16; - } bit; - } INSTR_MEM12; + } INSTR_MEM12_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM13; /*!< (@ 0x0000007C) Write-only access to instruction memory location 13 */ struct { - __IOM uint32_t INSTR_MEM13 : 16; /*!< [15..0] INSTR_MEM13 */ + __OM uint32_t INSTR_MEM13 : 16; /*!< [15..0] INSTR_MEM13 */ uint32_t : 16; - } bit; - } INSTR_MEM13; + } INSTR_MEM13_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM14; /*!< (@ 0x00000080) Write-only access to instruction memory location 14 */ struct { - __IOM uint32_t INSTR_MEM14 : 16; /*!< [15..0] INSTR_MEM14 */ + __OM uint32_t INSTR_MEM14 : 16; /*!< [15..0] INSTR_MEM14 */ uint32_t : 16; - } bit; - } INSTR_MEM14; + } INSTR_MEM14_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM15; /*!< (@ 0x00000084) Write-only access to instruction memory location 15 */ struct { - __IOM uint32_t INSTR_MEM15 : 16; /*!< [15..0] INSTR_MEM15 */ + __OM uint32_t INSTR_MEM15 : 16; /*!< [15..0] INSTR_MEM15 */ uint32_t : 16; - } bit; - } INSTR_MEM15; + } INSTR_MEM15_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000088) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM16; /*!< (@ 0x00000088) Write-only access to instruction memory location 16 */ struct { - __IOM uint32_t INSTR_MEM16 : 16; /*!< [15..0] INSTR_MEM16 */ + __OM uint32_t INSTR_MEM16 : 16; /*!< [15..0] INSTR_MEM16 */ uint32_t : 16; - } bit; - } INSTR_MEM16; + } INSTR_MEM16_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM17; /*!< (@ 0x0000008C) Write-only access to instruction memory location 17 */ struct { - __IOM uint32_t INSTR_MEM17 : 16; /*!< [15..0] INSTR_MEM17 */ + __OM uint32_t INSTR_MEM17 : 16; /*!< [15..0] INSTR_MEM17 */ uint32_t : 16; - } bit; - } INSTR_MEM17; + } INSTR_MEM17_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000090) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM18; /*!< (@ 0x00000090) Write-only access to instruction memory location 18 */ struct { - __IOM uint32_t INSTR_MEM18 : 16; /*!< [15..0] INSTR_MEM18 */ + __OM uint32_t INSTR_MEM18 : 16; /*!< [15..0] INSTR_MEM18 */ uint32_t : 16; - } bit; - } INSTR_MEM18; + } INSTR_MEM18_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM19; /*!< (@ 0x00000094) Write-only access to instruction memory location 19 */ struct { - __IOM uint32_t INSTR_MEM19 : 16; /*!< [15..0] INSTR_MEM19 */ + __OM uint32_t INSTR_MEM19 : 16; /*!< [15..0] INSTR_MEM19 */ uint32_t : 16; - } bit; - } INSTR_MEM19; + } INSTR_MEM19_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM20; /*!< (@ 0x00000098) Write-only access to instruction memory location 20 */ struct { - __IOM uint32_t INSTR_MEM20 : 16; /*!< [15..0] INSTR_MEM20 */ + __OM uint32_t INSTR_MEM20 : 16; /*!< [15..0] INSTR_MEM20 */ uint32_t : 16; - } bit; - } INSTR_MEM20; + } INSTR_MEM20_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM21; /*!< (@ 0x0000009C) Write-only access to instruction memory location 21 */ struct { - __IOM uint32_t INSTR_MEM21 : 16; /*!< [15..0] INSTR_MEM21 */ + __OM uint32_t INSTR_MEM21 : 16; /*!< [15..0] INSTR_MEM21 */ uint32_t : 16; - } bit; - } INSTR_MEM21; + } INSTR_MEM21_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM22; /*!< (@ 0x000000A0) Write-only access to instruction memory location 22 */ struct { - __IOM uint32_t INSTR_MEM22 : 16; /*!< [15..0] INSTR_MEM22 */ + __OM uint32_t INSTR_MEM22 : 16; /*!< [15..0] INSTR_MEM22 */ uint32_t : 16; - } bit; - } INSTR_MEM22; + } INSTR_MEM22_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM23; /*!< (@ 0x000000A4) Write-only access to instruction memory location 23 */ struct { - __IOM uint32_t INSTR_MEM23 : 16; /*!< [15..0] INSTR_MEM23 */ + __OM uint32_t INSTR_MEM23 : 16; /*!< [15..0] INSTR_MEM23 */ uint32_t : 16; - } bit; - } INSTR_MEM23; + } INSTR_MEM23_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM24; /*!< (@ 0x000000A8) Write-only access to instruction memory location 24 */ struct { - __IOM uint32_t INSTR_MEM24 : 16; /*!< [15..0] INSTR_MEM24 */ + __OM uint32_t INSTR_MEM24 : 16; /*!< [15..0] INSTR_MEM24 */ uint32_t : 16; - } bit; - } INSTR_MEM24; + } INSTR_MEM24_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM25; /*!< (@ 0x000000AC) Write-only access to instruction memory location 25 */ struct { - __IOM uint32_t INSTR_MEM25 : 16; /*!< [15..0] INSTR_MEM25 */ + __OM uint32_t INSTR_MEM25 : 16; /*!< [15..0] INSTR_MEM25 */ uint32_t : 16; - } bit; - } INSTR_MEM25; + } INSTR_MEM25_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM26; /*!< (@ 0x000000B0) Write-only access to instruction memory location 26 */ struct { - __IOM uint32_t INSTR_MEM26 : 16; /*!< [15..0] INSTR_MEM26 */ + __OM uint32_t INSTR_MEM26 : 16; /*!< [15..0] INSTR_MEM26 */ uint32_t : 16; - } bit; - } INSTR_MEM26; + } INSTR_MEM26_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM27; /*!< (@ 0x000000B4) Write-only access to instruction memory location 27 */ struct { - __IOM uint32_t INSTR_MEM27 : 16; /*!< [15..0] INSTR_MEM27 */ + __OM uint32_t INSTR_MEM27 : 16; /*!< [15..0] INSTR_MEM27 */ uint32_t : 16; - } bit; - } INSTR_MEM27; + } INSTR_MEM27_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM28; /*!< (@ 0x000000B8) Write-only access to instruction memory location 28 */ struct { - __IOM uint32_t INSTR_MEM28 : 16; /*!< [15..0] INSTR_MEM28 */ + __OM uint32_t INSTR_MEM28 : 16; /*!< [15..0] INSTR_MEM28 */ uint32_t : 16; - } bit; - } INSTR_MEM28; + } INSTR_MEM28_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000BC) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM29; /*!< (@ 0x000000BC) Write-only access to instruction memory location 29 */ struct { - __IOM uint32_t INSTR_MEM29 : 16; /*!< [15..0] INSTR_MEM29 */ + __OM uint32_t INSTR_MEM29 : 16; /*!< [15..0] INSTR_MEM29 */ uint32_t : 16; - } bit; - } INSTR_MEM29; + } INSTR_MEM29_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C0) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM30; /*!< (@ 0x000000C0) Write-only access to instruction memory location 30 */ struct { - __IOM uint32_t INSTR_MEM30 : 16; /*!< [15..0] INSTR_MEM30 */ + __OM uint32_t INSTR_MEM30 : 16; /*!< [15..0] INSTR_MEM30 */ uint32_t : 16; - } bit; - } INSTR_MEM30; + } INSTR_MEM30_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C4) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM31; /*!< (@ 0x000000C4) Write-only access to instruction memory location 31 */ struct { - __IOM uint32_t INSTR_MEM31 : 16; /*!< [15..0] INSTR_MEM31 */ + __OM uint32_t INSTR_MEM31 : 16; /*!< [15..0] INSTR_MEM31 */ uint32_t : 16; - } bit; - } INSTR_MEM31; + } INSTR_MEM31_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000C8) Clock divider register for state machine 0 + __IOM uint32_t SM0_CLKDIV; /*!< (@ 0x000000C8) Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ struct { uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM0_CLKDIV; + __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must + also be 0. */ + } SM0_CLKDIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000CC) Execution/behavioural settings for state machine + __IOM uint32_t SM0_EXECCTRL; /*!< (@ 0x000000CC) Execution/behavioural settings for state machine 0 */ struct { @@ -13128,38 +15313,41 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM0_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D0) Control behaviour of the input/output shift registers + __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] If 1, side-set data is asserted to pin directions, + instead of pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the MSB of the Delay/Side-set instruction field + is used as side-set enable, rather than a side-set data + bit. This allows instructions to perform side-set optionally, + rather than on every instruction, but the maximum possible + side-set width is reduced from 5 to 4. Note that the value + of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] If 1, an instruction written to SMx_INSTR is stalled, + and latched by the state machine. Will clear to 0 once + this instruction completes. */ + } SM0_EXECCTRL_b; + } ; + + union { + __IOM uint32_t SM0_SHIFTCTRL; /*!< (@ 0x000000D0) Control behaviour of the input/output shift registers for state machine 0 */ struct { uint32_t : 16; __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ + filled, i.e. on an IN instruction which causes the input + shift counter to reach or exceed PUSH_THRESH. */ __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ + emptied, i.e. on or following an OUT instruction which + causes the output shift counter to reach or exceed PULL_THRESH. */ __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters from left). 0 = to left. */ __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. + __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into ISR before autopush, or + conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. + __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of OSR before autopull, + or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. */ __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. @@ -13171,62 +15359,80 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */ - } bit; - } SM0_SHIFTCTRL; + } SM0_SHIFTCTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000D4) Current instruction address of state machine + __IOM uint32_t SM0_ADDR; /*!< (@ 0x000000D4) Current instruction address of state machine 0 */ struct { __IM uint32_t SM0_ADDR : 5; /*!< [4..0] SM0_ADDR */ uint32_t : 27; - } bit; - } SM0_ADDR; + } SM0_ADDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000D8) Instruction currently being executed by state - machine 0 + __IOM uint32_t SM0_INSTR; /*!< (@ 0x000000D8) Read to see the instruction currently addressed + by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ struct { __IOM uint32_t SM0_INSTR : 16; /*!< [15..0] SM0_INSTR */ uint32_t : 16; - } bit; - } SM0_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000DC) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM0_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E0) Clock divider register for state machine 1 + } SM0_INSTR_b; + } ; + + union { + __IOM uint32_t SM0_PINCTRL; /*!< (@ 0x000000DC) State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The lowest-numbered pin that will be affected by an OUT + PINS, OUT PINDIRS or MOV PINS instruction. The data written + to this pin will always be the least-significant bit of + the OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< [9..5] The lowest-numbered pin that will be affected by a SET + PINS or SET PINDIRS instruction. The data written to this + pin is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The lowest-numbered pin that will be affected by a + side-set operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< [19..15] The pin which is mapped to the least-significant bit + of a state machine's IN data bus. Higher-numbered pins + are mapped to consecutively more-significant data bits, + with a modulo of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT PINS, OUT PINDIRS + or MOV PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. In the range + 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of MSBs of the Delay/Side-set instruction + field which are used for side-set. Inclusive of the enable + bit, if present. Minimum of 0 (all delay bits, no side-set) + and maximum of 5 (all side-set, no delay). */ + } SM0_PINCTRL_b; + } ; + + union { + __IOM uint32_t SM1_CLKDIV; /*!< (@ 0x000000E0) Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ struct { uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM1_CLKDIV; + __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must + also be 0. */ + } SM1_CLKDIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000E4) Execution/behavioural settings for state machine + __IOM uint32_t SM1_EXECCTRL; /*!< (@ 0x000000E4) Execution/behavioural settings for state machine 1 */ struct { @@ -13251,38 +15457,41 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM1_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E8) Control behaviour of the input/output shift registers + __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] If 1, side-set data is asserted to pin directions, + instead of pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the MSB of the Delay/Side-set instruction field + is used as side-set enable, rather than a side-set data + bit. This allows instructions to perform side-set optionally, + rather than on every instruction, but the maximum possible + side-set width is reduced from 5 to 4. Note that the value + of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] If 1, an instruction written to SMx_INSTR is stalled, + and latched by the state machine. Will clear to 0 once + this instruction completes. */ + } SM1_EXECCTRL_b; + } ; + + union { + __IOM uint32_t SM1_SHIFTCTRL; /*!< (@ 0x000000E8) Control behaviour of the input/output shift registers for state machine 1 */ struct { uint32_t : 16; __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ + filled, i.e. on an IN instruction which causes the input + shift counter to reach or exceed PUSH_THRESH. */ __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ + emptied, i.e. on or following an OUT instruction which + causes the output shift counter to reach or exceed PULL_THRESH. */ __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters from left). 0 = to left. */ __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. + __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into ISR before autopush, or + conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. + __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of OSR before autopull, + or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. */ __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. @@ -13294,62 +15503,80 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */ - } bit; - } SM1_SHIFTCTRL; + } SM1_SHIFTCTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000EC) Current instruction address of state machine + __IOM uint32_t SM1_ADDR; /*!< (@ 0x000000EC) Current instruction address of state machine 1 */ struct { __IM uint32_t SM1_ADDR : 5; /*!< [4..0] SM1_ADDR */ uint32_t : 27; - } bit; - } SM1_ADDR; + } SM1_ADDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) Instruction currently being executed by state - machine 1 + __IOM uint32_t SM1_INSTR; /*!< (@ 0x000000F0) Read to see the instruction currently addressed + by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ struct { __IOM uint32_t SM1_INSTR : 16; /*!< [15..0] SM1_INSTR */ uint32_t : 16; - } bit; - } SM1_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM1_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) Clock divider register for state machine 2 + } SM1_INSTR_b; + } ; + + union { + __IOM uint32_t SM1_PINCTRL; /*!< (@ 0x000000F4) State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The lowest-numbered pin that will be affected by an OUT + PINS, OUT PINDIRS or MOV PINS instruction. The data written + to this pin will always be the least-significant bit of + the OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< [9..5] The lowest-numbered pin that will be affected by a SET + PINS or SET PINDIRS instruction. The data written to this + pin is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The lowest-numbered pin that will be affected by a + side-set operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< [19..15] The pin which is mapped to the least-significant bit + of a state machine's IN data bus. Higher-numbered pins + are mapped to consecutively more-significant data bits, + with a modulo of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT PINS, OUT PINDIRS + or MOV PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. In the range + 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of MSBs of the Delay/Side-set instruction + field which are used for side-set. Inclusive of the enable + bit, if present. Minimum of 0 (all delay bits, no side-set) + and maximum of 5 (all side-set, no delay). */ + } SM1_PINCTRL_b; + } ; + + union { + __IOM uint32_t SM2_CLKDIV; /*!< (@ 0x000000F8) Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ struct { uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM2_CLKDIV; + __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must + also be 0. */ + } SM2_CLKDIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000FC) Execution/behavioural settings for state machine + __IOM uint32_t SM2_EXECCTRL; /*!< (@ 0x000000FC) Execution/behavioural settings for state machine 2 */ struct { @@ -13374,38 +15601,41 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM2_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000100) Control behaviour of the input/output shift registers + __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] If 1, side-set data is asserted to pin directions, + instead of pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the MSB of the Delay/Side-set instruction field + is used as side-set enable, rather than a side-set data + bit. This allows instructions to perform side-set optionally, + rather than on every instruction, but the maximum possible + side-set width is reduced from 5 to 4. Note that the value + of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] If 1, an instruction written to SMx_INSTR is stalled, + and latched by the state machine. Will clear to 0 once + this instruction completes. */ + } SM2_EXECCTRL_b; + } ; + + union { + __IOM uint32_t SM2_SHIFTCTRL; /*!< (@ 0x00000100) Control behaviour of the input/output shift registers for state machine 2 */ struct { uint32_t : 16; __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ + filled, i.e. on an IN instruction which causes the input + shift counter to reach or exceed PUSH_THRESH. */ __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ + emptied, i.e. on or following an OUT instruction which + causes the output shift counter to reach or exceed PULL_THRESH. */ __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters from left). 0 = to left. */ __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. + __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into ISR before autopush, or + conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. + __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of OSR before autopull, + or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. */ __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. @@ -13417,62 +15647,80 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */ - } bit; - } SM2_SHIFTCTRL; + } SM2_SHIFTCTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000104) Current instruction address of state machine + __IOM uint32_t SM2_ADDR; /*!< (@ 0x00000104) Current instruction address of state machine 2 */ struct { __IM uint32_t SM2_ADDR : 5; /*!< [4..0] SM2_ADDR */ uint32_t : 27; - } bit; - } SM2_ADDR; + } SM2_ADDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000108) Instruction currently being executed by state - machine 2 + __IOM uint32_t SM2_INSTR; /*!< (@ 0x00000108) Read to see the instruction currently addressed + by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ struct { __IOM uint32_t SM2_INSTR : 16; /*!< [15..0] SM2_INSTR */ uint32_t : 16; - } bit; - } SM2_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000010C) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM2_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000110) Clock divider register for state machine 3 + } SM2_INSTR_b; + } ; + + union { + __IOM uint32_t SM2_PINCTRL; /*!< (@ 0x0000010C) State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The lowest-numbered pin that will be affected by an OUT + PINS, OUT PINDIRS or MOV PINS instruction. The data written + to this pin will always be the least-significant bit of + the OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< [9..5] The lowest-numbered pin that will be affected by a SET + PINS or SET PINDIRS instruction. The data written to this + pin is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The lowest-numbered pin that will be affected by a + side-set operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< [19..15] The pin which is mapped to the least-significant bit + of a state machine's IN data bus. Higher-numbered pins + are mapped to consecutively more-significant data bits, + with a modulo of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT PINS, OUT PINDIRS + or MOV PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. In the range + 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of MSBs of the Delay/Side-set instruction + field which are used for side-set. Inclusive of the enable + bit, if present. Minimum of 0 (all delay bits, no side-set) + and maximum of 5 (all side-set, no delay). */ + } SM2_PINCTRL_b; + } ; + + union { + __IOM uint32_t SM3_CLKDIV; /*!< (@ 0x00000110) Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ struct { uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM3_CLKDIV; + __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divisor */ + __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must + also be 0. */ + } SM3_CLKDIV_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000114) Execution/behavioural settings for state machine + __IOM uint32_t SM3_EXECCTRL; /*!< (@ 0x00000114) Execution/behavioural settings for state machine 3 */ struct { @@ -13497,38 +15745,41 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM3_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000118) Control behaviour of the input/output shift registers + __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] If 1, side-set data is asserted to pin directions, + instead of pin values */ + __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the MSB of the Delay/Side-set instruction field + is used as side-set enable, rather than a side-set data + bit. This allows instructions to perform side-set optionally, + rather than on every instruction, but the maximum possible + side-set width is reduced from 5 to 4. Note that the value + of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. */ + __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] If 1, an instruction written to SMx_INSTR is stalled, + and latched by the state machine. Will clear to 0 once + this instruction completes. */ + } SM3_EXECCTRL_b; + } ; + + union { + __IOM uint32_t SM3_SHIFTCTRL; /*!< (@ 0x00000118) Control behaviour of the input/output shift registers for state machine 3 */ struct { uint32_t : 16; __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ + filled, i.e. on an IN instruction which causes the input + shift counter to reach or exceed PUSH_THRESH. */ __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ + emptied, i.e. on or following an OUT instruction which + causes the output shift counter to reach or exceed PULL_THRESH. */ __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters from left). 0 = to left. */ __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. + __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into ISR before autopush, or + conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. + __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of OSR before autopull, + or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. */ __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. @@ -13540,49 +15791,66 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */ - } bit; - } SM3_SHIFTCTRL; + } SM3_SHIFTCTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000011C) Current instruction address of state machine + __IOM uint32_t SM3_ADDR; /*!< (@ 0x0000011C) Current instruction address of state machine 3 */ struct { __IM uint32_t SM3_ADDR : 5; /*!< [4..0] SM3_ADDR */ uint32_t : 27; - } bit; - } SM3_ADDR; + } SM3_ADDR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000120) Instruction currently being executed by state - machine 3 + __IOM uint32_t SM3_INSTR; /*!< (@ 0x00000120) Read to see the instruction currently addressed + by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ struct { __IOM uint32_t SM3_INSTR : 16; /*!< [15..0] SM3_INSTR */ uint32_t : 16; - } bit; - } SM3_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000124) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM3_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000128) Raw Interrupts */ + } SM3_INSTR_b; + } ; + + union { + __IOM uint32_t SM3_PINCTRL; /*!< (@ 0x00000124) State machine pin control */ + + struct { + __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The lowest-numbered pin that will be affected by an OUT + PINS, OUT PINDIRS or MOV PINS instruction. The data written + to this pin will always be the least-significant bit of + the OUT or MOV data. */ + __IOM uint32_t SET_BASE : 5; /*!< [9..5] The lowest-numbered pin that will be affected by a SET + PINS or SET PINDIRS instruction. The data written to this + pin is the least-significant bit of the SET data. */ + __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The lowest-numbered pin that will be affected by a + side-set operation. The MSBs of an instruction's side-set/delay + field (up to 5, determined by SIDESET_COUNT) are used for + side-set data, with the remaining LSBs used for delay. + The least-significant bit of the side-set portion is the + bit written to this pin, with more-significant bits written + to higher-numbered pins. */ + __IOM uint32_t IN_BASE : 5; /*!< [19..15] The pin which is mapped to the least-significant bit + of a state machine's IN data bus. Higher-numbered pins + are mapped to consecutively more-significant data bits, + with a modulo of 32 applied to pin number. */ + __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT PINS, OUT PINDIRS + or MOV PINS instruction. In the range 0 to 32 inclusive. */ + __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. In the range + 0 to 5 inclusive. */ + __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of MSBs of the Delay/Side-set instruction + field which are used for side-set. Inclusive of the enable + bit, if present. Minimum of 0 (all delay bits, no side-set) + and maximum of 5 (all side-set, no delay). */ + } SM3_PINCTRL_b; + } ; + + union { + __IOM uint32_t INTR; /*!< (@ 0x00000128) Raw Interrupts */ struct { __IM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ @@ -13598,11 +15866,11 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } INTR; + } INTR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000012C) Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTE; /*!< (@ 0x0000012C) Interrupt Enable for irq0 */ struct { __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ @@ -13618,11 +15886,11 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } IRQ0_INTE; + } IRQ0_INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000130) Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< (@ 0x00000130) Interrupt Force for irq0 */ struct { __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ @@ -13638,11 +15906,11 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } IRQ0_INTF; + } IRQ0_INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000134) Interrupt status after masking & forcing for + __IOM uint32_t IRQ0_INTS; /*!< (@ 0x00000134) Interrupt status after masking & forcing for irq0 */ struct { @@ -13659,11 +15927,11 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } IRQ0_INTS; + } IRQ0_INTS_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000138) Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTE; /*!< (@ 0x00000138) Interrupt Enable for irq1 */ struct { __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ @@ -13679,11 +15947,11 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } IRQ1_INTE; + } IRQ1_INTE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000013C) Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< (@ 0x0000013C) Interrupt Force for irq1 */ struct { __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ @@ -13699,11 +15967,11 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } IRQ1_INTF; + } IRQ1_INTF_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000140) Interrupt status after masking & forcing for + __IOM uint32_t IRQ1_INTS; /*!< (@ 0x00000140) Interrupt status after masking & forcing for irq1 */ struct { @@ -13720,8 +15988,8 @@ typedef struct { /*!< (@ 0x50200000) PIO0 Structu __IM uint32_t SM2 : 1; /*!< [10..10] SM2 */ __IM uint32_t SM3 : 1; /*!< [11..11] SM3 */ uint32_t : 20; - } bit; - } IRQ1_INTS; + } IRQ1_INTS_b; + } ; } PIO0_Type; /*!< Size = 324 (0x144) */ @@ -13742,27 +16010,27 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur 0, and 1 when read from processor core 1. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Input value for GPIO pins */ + __IOM uint32_t GPIO_IN; /*!< (@ 0x00000004) Input value for GPIO pins */ struct { __IM uint32_t GPIO_IN : 30; /*!< [29..0] Input value for GPIO0...29 */ uint32_t : 2; - } bit; - } GPIO_IN; + } GPIO_IN_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Input value for QSPI pins */ + __IOM uint32_t GPIO_HI_IN; /*!< (@ 0x00000008) Input value for QSPI pins */ struct { __IM uint32_t GPIO_HI_IN : 6; /*!< [5..0] Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 */ uint32_t : 26; - } bit; - } GPIO_HI_IN; + } GPIO_HI_IN_b; + } ; __IM uint32_t RESERVED; union { - __IOM uint32_t reg; /*!< (@ 0x00000010) GPIO output value */ + __IOM uint32_t GPIO_OUT; /*!< (@ 0x00000010) GPIO output value */ struct { __IOM uint32_t GPIO_OUT : 30; /*!< [29..0] Set output level (1/0 -> high/low) for GPIO0...29. @@ -13775,41 +16043,41 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur and the write from core 1 was then applied to that intermediate result. */ uint32_t : 2; - } bit; - } GPIO_OUT; + } GPIO_OUT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000014) GPIO output value set */ + __IOM uint32_t GPIO_OUT_SET; /*!< (@ 0x00000014) GPIO output value set */ struct { - __IOM uint32_t GPIO_OUT_SET : 30; /*!< [29..0] Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT + __OM uint32_t GPIO_OUT_SET : 30; /*!< [29..0] Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` */ uint32_t : 2; - } bit; - } GPIO_OUT_SET; + } GPIO_OUT_SET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000018) GPIO output value clear */ + __IOM uint32_t GPIO_OUT_CLR; /*!< (@ 0x00000018) GPIO output value clear */ struct { - __IOM uint32_t GPIO_OUT_CLR : 30; /*!< [29..0] Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT + __OM uint32_t GPIO_OUT_CLR : 30; /*!< [29..0] Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` */ uint32_t : 2; - } bit; - } GPIO_OUT_CLR; + } GPIO_OUT_CLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) GPIO output value XOR */ + __IOM uint32_t GPIO_OUT_XOR; /*!< (@ 0x0000001C) GPIO output value XOR */ struct { - __IOM uint32_t GPIO_OUT_XOR : 30; /*!< [29..0] Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT + __OM uint32_t GPIO_OUT_XOR : 30; /*!< [29..0] Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` */ uint32_t : 2; - } bit; - } GPIO_OUT_XOR; + } GPIO_OUT_XOR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000020) GPIO output enable */ + __IOM uint32_t GPIO_OE; /*!< (@ 0x00000020) GPIO output enable */ struct { __IOM uint32_t GPIO_OE : 30; /*!< [29..0] Set output enable (1/0 -> output/input) for GPIO0...29. @@ -13821,41 +16089,41 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur and the write from core 1 was then applied to that intermediate result. */ uint32_t : 2; - } bit; - } GPIO_OE; + } GPIO_OE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000024) GPIO output enable set */ + __IOM uint32_t GPIO_OE_SET; /*!< (@ 0x00000024) GPIO output enable set */ struct { - __IOM uint32_t GPIO_OE_SET : 30; /*!< [29..0] Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE + __OM uint32_t GPIO_OE_SET : 30; /*!< [29..0] Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` */ uint32_t : 2; - } bit; - } GPIO_OE_SET; + } GPIO_OE_SET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000028) GPIO output enable clear */ + __IOM uint32_t GPIO_OE_CLR; /*!< (@ 0x00000028) GPIO output enable clear */ struct { - __IOM uint32_t GPIO_OE_CLR : 30; /*!< [29..0] Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE + __OM uint32_t GPIO_OE_CLR : 30; /*!< [29..0] Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` */ uint32_t : 2; - } bit; - } GPIO_OE_CLR; + } GPIO_OE_CLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) GPIO output enable XOR */ + __IOM uint32_t GPIO_OE_XOR; /*!< (@ 0x0000002C) GPIO output enable XOR */ struct { - __IOM uint32_t GPIO_OE_XOR : 30; /*!< [29..0] Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE + __OM uint32_t GPIO_OE_XOR : 30; /*!< [29..0] Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` */ uint32_t : 2; - } bit; - } GPIO_OE_XOR; + } GPIO_OE_XOR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000030) QSPI output value */ + __IOM uint32_t GPIO_HI_OUT; /*!< (@ 0x00000030) QSPI output value */ struct { __IOM uint32_t GPIO_HI_OUT : 6; /*!< [5..0] Set output level (1/0 -> high/low) for QSPI IO0...5. @@ -13868,41 +16136,41 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur and the write from core 1 was then applied to that intermediate result. */ uint32_t : 26; - } bit; - } GPIO_HI_OUT; + } GPIO_HI_OUT_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000034) QSPI output value set */ + __IOM uint32_t GPIO_HI_OUT_SET; /*!< (@ 0x00000034) QSPI output value set */ struct { - __IOM uint32_t GPIO_HI_OUT_SET : 6; /*!< [5..0] Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT + __OM uint32_t GPIO_HI_OUT_SET : 6; /*!< [5..0] Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` */ uint32_t : 26; - } bit; - } GPIO_HI_OUT_SET; + } GPIO_HI_OUT_SET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000038) QSPI output value clear */ + __IOM uint32_t GPIO_HI_OUT_CLR; /*!< (@ 0x00000038) QSPI output value clear */ struct { - __IOM uint32_t GPIO_HI_OUT_CLR : 6; /*!< [5..0] Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT + __OM uint32_t GPIO_HI_OUT_CLR : 6; /*!< [5..0] Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` */ uint32_t : 26; - } bit; - } GPIO_HI_OUT_CLR; + } GPIO_HI_OUT_CLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) QSPI output value XOR */ + __IOM uint32_t GPIO_HI_OUT_XOR; /*!< (@ 0x0000003C) QSPI output value XOR */ struct { - __IOM uint32_t GPIO_HI_OUT_XOR : 6; /*!< [5..0] Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT + __OM uint32_t GPIO_HI_OUT_XOR : 6; /*!< [5..0] Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` */ uint32_t : 26; - } bit; - } GPIO_HI_OUT_XOR; + } GPIO_HI_OUT_XOR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000040) QSPI output enable */ + __IOM uint32_t GPIO_HI_OE; /*!< (@ 0x00000040) QSPI output enable */ struct { __IOM uint32_t GPIO_HI_OE : 6; /*!< [5..0] Set output enable (1/0 -> output/input) for QSPI IO0...5. @@ -13914,41 +16182,41 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur and the write from core 1 was then applied to that intermediate result. */ uint32_t : 26; - } bit; - } GPIO_HI_OE; + } GPIO_HI_OE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000044) QSPI output enable set */ + __IOM uint32_t GPIO_HI_OE_SET; /*!< (@ 0x00000044) QSPI output enable set */ struct { - __IOM uint32_t GPIO_HI_OE_SET : 6; /*!< [5..0] Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE + __OM uint32_t GPIO_HI_OE_SET : 6; /*!< [5..0] Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */ uint32_t : 26; - } bit; - } GPIO_HI_OE_SET; + } GPIO_HI_OE_SET_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000048) QSPI output enable clear */ + __IOM uint32_t GPIO_HI_OE_CLR; /*!< (@ 0x00000048) QSPI output enable clear */ struct { - __IOM uint32_t GPIO_HI_OE_CLR : 6; /*!< [5..0] Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE + __OM uint32_t GPIO_HI_OE_CLR : 6; /*!< [5..0] Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` */ uint32_t : 26; - } bit; - } GPIO_HI_OE_CLR; + } GPIO_HI_OE_CLR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) QSPI output enable XOR */ + __IOM uint32_t GPIO_HI_OE_XOR; /*!< (@ 0x0000004C) QSPI output enable XOR */ struct { - __IOM uint32_t GPIO_HI_OE_XOR : 6; /*!< [5..0] Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE + __OM uint32_t GPIO_HI_OE_XOR : 6; /*!< [5..0] Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` */ uint32_t : 26; - } bit; - } GPIO_HI_OE_XOR; + } GPIO_HI_OE_XOR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Status register for inter-core FIFOs (mailboxes). + __IOM uint32_t FIFO_ST; /*!< (@ 0x00000050) Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. @@ -13960,7 +16228,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its - FIF */ + FIFO_ */ struct { __IM uint32_t VLD : 1; /*!< [0..0] Value is 1 if this core's RX FIFO is not empty (i.e. @@ -13972,8 +16240,8 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur __IOM uint32_t ROE : 1; /*!< [3..3] Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. */ uint32_t : 28; - } bit; - } FIFO_ST; + } FIFO_ST_b; + } ; __OM uint32_t FIFO_WR; /*!< (@ 0x00000054) Write access to this core's TX FIFO */ __IM uint32_t FIFO_RD; /*!< (@ 0x00000058) Read access to this core's RX FIFO */ __IM uint32_t SPINLOCK_ST; /*!< (@ 0x0000005C) Spinlock state @@ -13994,7 +16262,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same + UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. */ @@ -14015,7 +16283,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY - flag, so */ + flag, so sh */ __IOM uint32_t DIV_REMAINDER; /*!< (@ 0x00000074) Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. @@ -14028,7 +16296,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur and CSR_DIRTY flags. */ union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Control and status register for divider. */ + __IOM uint32_t DIV_CSR; /*!< (@ 0x00000078) Control and status register for divider. */ struct { __IM uint32_t READY : 1; /*!< [0..0] Reads as 0 when a calculation is in progress, 1 otherwise. @@ -14047,8 +16315,8 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur or REMAINDER and then QUOTIENT, to prevent data loss on context switch. */ uint32_t : 30; - } bit; - } DIV_CSR; + } DIV_CSR_b; + } ; __IM uint32_t RESERVED1; __IOM uint32_t INTERP0_ACCUM0; /*!< (@ 0x00000080) Read/write access to accumulator 0 */ __IOM uint32_t INTERP0_ACCUM1; /*!< (@ 0x00000084) Read/write access to accumulator 1 */ @@ -14069,7 +16337,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur state (PEEK). */ union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) Control register for lane 0 */ + __IOM uint32_t INTERP0_CTRL_LANE0; /*!< (@ 0x000000AC) Control register for lane 0 */ struct { __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ @@ -14112,11 +16380,11 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur __IM uint32_t OVERF1 : 1; /*!< [24..24] Indicates if any masked-off MSBs in ACCUM1 are set. */ __IM uint32_t OVERF : 1; /*!< [25..25] Set if either OVERF0 or OVERF1 is set. */ uint32_t : 6; - } bit; - } INTERP0_CTRL_LANE0; + } INTERP0_CTRL_LANE0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) Control register for lane 1 */ + __IOM uint32_t INTERP0_CTRL_LANE1; /*!< (@ 0x000000B0) Control register for lane 1 */ struct { __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ @@ -14143,31 +16411,31 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur a lane to generate sequence of pointers into flash or SRAM. */ uint32_t : 11; - } bit; - } INTERP0_CTRL_LANE1; + } INTERP0_CTRL_LANE1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) Values written here are atomically added to ACCUM0 + __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< (@ 0x000000B4) Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). */ struct { __IOM uint32_t INTERP0_ACCUM0_ADD : 24; /*!< [23..0] INTERP0_ACCUM0_ADD */ uint32_t : 8; - } bit; - } INTERP0_ACCUM0_ADD; + } INTERP0_ACCUM0_ADD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) Values written here are atomically added to ACCUM1 + __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< (@ 0x000000B8) Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). */ struct { __IOM uint32_t INTERP0_ACCUM1_ADD : 24; /*!< [23..0] INTERP0_ACCUM1_ADD */ uint32_t : 8; - } bit; - } INTERP0_ACCUM1_ADD; - __IOM uint32_t INTERP0_BASE_1AND0; /*!< (@ 0x000000BC) On write, the lower 16 bits go to BASE0, upper + } INTERP0_ACCUM1_ADD_b; + } ; + __OM uint32_t INTERP0_BASE_1AND0; /*!< (@ 0x000000BC) On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. */ @@ -14190,7 +16458,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur state (PEEK). */ union { - __IOM uint32_t reg; /*!< (@ 0x000000EC) Control register for lane 0 */ + __IOM uint32_t INTERP1_CTRL_LANE0; /*!< (@ 0x000000EC) Control register for lane 0 */ struct { __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ @@ -14227,11 +16495,11 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur __IM uint32_t OVERF1 : 1; /*!< [24..24] Indicates if any masked-off MSBs in ACCUM1 are set. */ __IM uint32_t OVERF : 1; /*!< [25..25] Set if either OVERF0 or OVERF1 is set. */ uint32_t : 6; - } bit; - } INTERP1_CTRL_LANE0; + } INTERP1_CTRL_LANE0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) Control register for lane 1 */ + __IOM uint32_t INTERP1_CTRL_LANE1; /*!< (@ 0x000000F0) Control register for lane 1 */ struct { __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ @@ -14258,35 +16526,35 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur a lane to generate sequence of pointers into flash or SRAM. */ uint32_t : 11; - } bit; - } INTERP1_CTRL_LANE1; + } INTERP1_CTRL_LANE1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) Values written here are atomically added to ACCUM0 + __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< (@ 0x000000F4) Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). */ struct { __IOM uint32_t INTERP1_ACCUM0_ADD : 24; /*!< [23..0] INTERP1_ACCUM0_ADD */ uint32_t : 8; - } bit; - } INTERP1_ACCUM0_ADD; + } INTERP1_ACCUM0_ADD_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) Values written here are atomically added to ACCUM1 + __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< (@ 0x000000F8) Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). */ struct { __IOM uint32_t INTERP1_ACCUM1_ADD : 24; /*!< [23..0] INTERP1_ACCUM1_ADD */ uint32_t : 8; - } bit; - } INTERP1_ACCUM1_ADD; - __IOM uint32_t INTERP1_BASE_1AND0; /*!< (@ 0x000000FC) On write, the lower 16 bits go to BASE0, upper + } INTERP1_ACCUM1_ADD_b; + } ; + __OM uint32_t INTERP1_BASE_1AND0; /*!< (@ 0x000000FC) On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. */ - __IM uint32_t SPINLOCK0; /*!< (@ 0x00000100) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK0; /*!< (@ 0x00000100) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14296,7 +16564,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK1; /*!< (@ 0x00000104) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK1; /*!< (@ 0x00000104) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14306,7 +16574,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK2; /*!< (@ 0x00000108) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK2; /*!< (@ 0x00000108) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14316,7 +16584,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK3; /*!< (@ 0x0000010C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK3; /*!< (@ 0x0000010C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14326,7 +16594,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK4; /*!< (@ 0x00000110) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK4; /*!< (@ 0x00000110) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14336,7 +16604,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK5; /*!< (@ 0x00000114) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK5; /*!< (@ 0x00000114) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14346,7 +16614,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK6; /*!< (@ 0x00000118) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK6; /*!< (@ 0x00000118) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14356,7 +16624,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK7; /*!< (@ 0x0000011C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK7; /*!< (@ 0x0000011C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14366,7 +16634,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK8; /*!< (@ 0x00000120) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK8; /*!< (@ 0x00000120) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14376,7 +16644,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK9; /*!< (@ 0x00000124) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK9; /*!< (@ 0x00000124) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14386,7 +16654,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK10; /*!< (@ 0x00000128) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK10; /*!< (@ 0x00000128) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14396,7 +16664,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK11; /*!< (@ 0x0000012C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK11; /*!< (@ 0x0000012C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14406,7 +16674,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK12; /*!< (@ 0x00000130) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK12; /*!< (@ 0x00000130) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14416,7 +16684,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK13; /*!< (@ 0x00000134) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK13; /*!< (@ 0x00000134) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14426,7 +16694,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK14; /*!< (@ 0x00000138) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK14; /*!< (@ 0x00000138) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14436,7 +16704,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK15; /*!< (@ 0x0000013C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK15; /*!< (@ 0x0000013C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14446,7 +16714,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK16; /*!< (@ 0x00000140) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK16; /*!< (@ 0x00000140) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14456,7 +16724,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK17; /*!< (@ 0x00000144) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK17; /*!< (@ 0x00000144) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14466,7 +16734,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK18; /*!< (@ 0x00000148) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK18; /*!< (@ 0x00000148) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14476,7 +16744,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK19; /*!< (@ 0x0000014C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK19; /*!< (@ 0x0000014C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14486,7 +16754,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK20; /*!< (@ 0x00000150) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK20; /*!< (@ 0x00000150) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14496,7 +16764,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK21; /*!< (@ 0x00000154) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK21; /*!< (@ 0x00000154) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14506,7 +16774,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK22; /*!< (@ 0x00000158) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK22; /*!< (@ 0x00000158) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14516,7 +16784,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK23; /*!< (@ 0x0000015C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK23; /*!< (@ 0x0000015C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14526,7 +16794,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK24; /*!< (@ 0x00000160) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK24; /*!< (@ 0x00000160) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14536,7 +16804,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK25; /*!< (@ 0x00000164) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK25; /*!< (@ 0x00000164) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14546,7 +16814,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK26; /*!< (@ 0x00000168) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK26; /*!< (@ 0x00000168) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14556,7 +16824,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK27; /*!< (@ 0x0000016C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK27; /*!< (@ 0x0000016C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14566,7 +16834,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK28; /*!< (@ 0x00000170) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK28; /*!< (@ 0x00000170) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14576,7 +16844,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK29; /*!< (@ 0x00000174) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK29; /*!< (@ 0x00000174) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14586,7 +16854,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK30; /*!< (@ 0x00000178) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK30; /*!< (@ 0x00000178) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14596,7 +16864,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK31; /*!< (@ 0x0000017C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK31; /*!< (@ 0x0000017C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14623,7 +16891,7 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IM uint32_t RESERVED[14340]; union { - __IOM uint32_t reg; /*!< (@ 0x0000E010) Use the SysTick Control and Status Register to + __IOM uint32_t SYST_CSR; /*!< (@ 0x0000E010) Use the SysTick Control and Status Register to enable the SysTick features. */ struct { @@ -14644,11 +16912,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IM uint32_t COUNTFLAG : 1; /*!< [16..16] Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. */ uint32_t : 15; - } bit; - } SYST_CSR; + } SYST_CSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E014) Use the SysTick Reload Value Register to specify + __IOM uint32_t SYST_RVR; /*!< (@ 0x0000E014) Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. @@ -14659,17 +16927,17 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD - value of N-1. For example, if the */ + value of N-1. For example, if the S */ struct { __IOM uint32_t RELOAD : 24; /*!< [23..0] Value to load into the SysTick Current Value Register when the counter reaches 0. */ uint32_t : 8; - } bit; - } SYST_RVR; + } SYST_RVR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E018) Use the SysTick Current Value Register to find + __IOM uint32_t SYST_CVR; /*!< (@ 0x0000E018) Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. */ @@ -14679,11 +16947,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. */ uint32_t : 8; - } bit; - } SYST_CVR; + } SYST_CVR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E01C) Use the SysTick Calibration Value Register to + __IOM uint32_t SYST_CALIB; /*!< (@ 0x0000E01C) Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. */ @@ -14697,12 +16965,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IM uint32_t NOREF : 1; /*!< [31..31] If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. */ - } bit; - } SYST_CALIB; + } SYST_CALIB_b; + } ; __IM uint32_t RESERVED1[56]; union { - __IOM uint32_t reg; /*!< (@ 0x0000E100) Use the Interrupt Set-Enable Register to enable + __IOM uint32_t NVIC_ISER; /*!< (@ 0x0000E100) Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC @@ -14720,12 +16988,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur Read: 0 = Interrupt disabled. 1 = Interrupt enabled. */ - } bit; - } NVIC_ISER; + } NVIC_ISER_b; + } ; __IM uint32_t RESERVED2[31]; union { - __IOM uint32_t reg; /*!< (@ 0x0000E180) Use the Interrupt Clear-Enable Registers to disable + __IOM uint32_t NVIC_ICER; /*!< (@ 0x0000E180) Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. */ @@ -14737,12 +17005,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur Read: 0 = Interrupt disabled. 1 = Interrupt enabled. */ - } bit; - } NVIC_ICER; + } NVIC_ICER_b; + } ; __IM uint32_t RESERVED3[31]; union { - __IOM uint32_t reg; /*!< (@ 0x0000E200) The NVIC_ISPR forces interrupts into the pending + __IOM uint32_t NVIC_ISPR; /*!< (@ 0x0000E200) The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. */ struct { @@ -14757,12 +17025,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending. */ - } bit; - } NVIC_ISPR; + } NVIC_ISPR_b; + } ; __IM uint32_t RESERVED4[31]; union { - __IOM uint32_t reg; /*!< (@ 0x0000E280) Use the Interrupt Clear-Pending Register to clear + __IOM uint32_t NVIC_ICPR; /*!< (@ 0x0000E280) Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. */ @@ -14774,12 +17042,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. */ - } bit; - } NVIC_ICPR; + } NVIC_ICPR_b; + } ; __IM uint32_t RESERVED5[95]; union { - __IOM uint32_t reg; /*!< (@ 0x0000E400) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR0; /*!< (@ 0x0000E400) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -14797,11 +17065,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_2 : 2; /*!< [23..22] Priority of interrupt 2 */ uint32_t : 6; __IOM uint32_t IP_3 : 2; /*!< [31..30] Priority of interrupt 3 */ - } bit; - } NVIC_IPR0; + } NVIC_IPR0_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E404) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR1; /*!< (@ 0x0000E404) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14815,11 +17083,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_6 : 2; /*!< [23..22] Priority of interrupt 6 */ uint32_t : 6; __IOM uint32_t IP_7 : 2; /*!< [31..30] Priority of interrupt 7 */ - } bit; - } NVIC_IPR1; + } NVIC_IPR1_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E408) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR2; /*!< (@ 0x0000E408) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14833,11 +17101,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_10 : 2; /*!< [23..22] Priority of interrupt 10 */ uint32_t : 6; __IOM uint32_t IP_11 : 2; /*!< [31..30] Priority of interrupt 11 */ - } bit; - } NVIC_IPR2; + } NVIC_IPR2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E40C) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR3; /*!< (@ 0x0000E40C) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14851,11 +17119,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_14 : 2; /*!< [23..22] Priority of interrupt 14 */ uint32_t : 6; __IOM uint32_t IP_15 : 2; /*!< [31..30] Priority of interrupt 15 */ - } bit; - } NVIC_IPR3; + } NVIC_IPR3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E410) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR4; /*!< (@ 0x0000E410) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14869,11 +17137,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_18 : 2; /*!< [23..22] Priority of interrupt 18 */ uint32_t : 6; __IOM uint32_t IP_19 : 2; /*!< [31..30] Priority of interrupt 19 */ - } bit; - } NVIC_IPR4; + } NVIC_IPR4_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E414) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR5; /*!< (@ 0x0000E414) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14887,11 +17155,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_22 : 2; /*!< [23..22] Priority of interrupt 22 */ uint32_t : 6; __IOM uint32_t IP_23 : 2; /*!< [31..30] Priority of interrupt 23 */ - } bit; - } NVIC_IPR5; + } NVIC_IPR5_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E418) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR6; /*!< (@ 0x0000E418) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14905,11 +17173,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_26 : 2; /*!< [23..22] Priority of interrupt 26 */ uint32_t : 6; __IOM uint32_t IP_27 : 2; /*!< [31..30] Priority of interrupt 27 */ - } bit; - } NVIC_IPR6; + } NVIC_IPR6_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000E41C) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR7; /*!< (@ 0x0000E41C) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ @@ -14923,12 +17191,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t IP_30 : 2; /*!< [23..22] Priority of interrupt 30 */ uint32_t : 6; __IOM uint32_t IP_31 : 2; /*!< [31..30] Priority of interrupt 31 */ - } bit; - } NVIC_IPR7; + } NVIC_IPR7_b; + } ; __IM uint32_t RESERVED6[568]; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED00) Read the CPU ID Base Register to determine: the + __IOM uint32_t CPUID; /*!< (@ 0x0000ED00) Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. */ @@ -14942,11 +17210,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IM uint32_t VARIANT : 4; /*!< [23..20] Major revision number n in the rnpm revision status: 0x0 = Revision 0. */ __IM uint32_t IMPLEMENTER : 8; /*!< [31..24] Implementor code: 0x41 = ARM */ - } bit; - } CPUID; + } CPUID_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED04) Use the Interrupt Control State Register to set + __IOM uint32_t ICSR; /*!< (@ 0x0000ED04) Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, @@ -15008,22 +17276,22 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally - the processor */ - } bit; - } ICSR; + the processor en */ + } ICSR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED08) The VTOR holds the vector table offset address. */ + __IOM uint32_t VTOR; /*!< (@ 0x0000ED08) The VTOR holds the vector table offset address. */ struct { uint32_t : 8; __IOM uint32_t TBLOFF : 24; /*!< [31..8] Bits [31:8] of the indicate the vector table offset address. */ - } bit; - } VTOR; + } VTOR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED0C) Use the Application Interrupt and Reset Control + __IOM uint32_t AIRCR; /*!< (@ 0x0000ED0C) Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. */ @@ -15049,11 +17317,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. */ - } bit; - } AIRCR; + } AIRCR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED10) System Control Register. Use the System Control + __IOM uint32_t SCR; /*!< (@ 0x0000ED10) System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how @@ -15083,13 +17351,13 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. - The */ + The p */ uint32_t : 27; - } bit; - } SCR; + } SCR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED14) The Configuration and Control Register permanently + __IOM uint32_t CCR; /*!< (@ 0x0000ED14) The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. */ @@ -15104,12 +17372,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur On return from the exception it uses this stacked bit to restore the correct stack alignment. */ uint32_t : 22; - } bit; - } CCR; + } CCR_b; + } ; __IM uint32_t RESERVED7; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED1C) System handlers are a special class of exception + __IOM uint32_t SHPR2; /*!< (@ 0x0000ED1C) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority @@ -15118,11 +17386,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur struct { uint32_t : 30; __IOM uint32_t PRI_11 : 2; /*!< [31..30] Priority of system handler 11, SVCall */ - } bit; - } SHPR2; + } SHPR2_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED20) System handlers are a special class of exception + __IOM uint32_t SHPR3; /*!< (@ 0x0000ED20) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority @@ -15133,11 +17401,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t PRI_14 : 2; /*!< [23..22] Priority of system handler 14, PendSV */ uint32_t : 6; __IOM uint32_t PRI_15 : 2; /*!< [31..30] Priority of system handler 15, SysTick */ - } bit; - } SHPR3; + } SHPR3_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED24) Use the System Handler Control and State Register + __IOM uint32_t SHCSR; /*!< (@ 0x0000ED24) Use the System Handler Control and State Register to determine or clear the pending status of SVCall. */ @@ -15146,12 +17414,12 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IOM uint32_t SVCALLPENDED : 1; /*!< [15..15] Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. */ uint32_t : 16; - } bit; - } SHCSR; + } SHCSR_b; + } ; __IM uint32_t RESERVED8[26]; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED90) Read the MPU Type Register to determine if the + __IOM uint32_t MPU_TYPE; /*!< (@ 0x0000ED90) Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. */ @@ -15163,11 +17431,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur __IM uint32_t IREGION : 8; /*!< [23..16] Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. */ uint32_t : 8; - } bit; - } MPU_TYPE; + } MPU_TYPE_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED94) Use the MPU Control Register to enable and disable + __IOM uint32_t MPU_CTRL; /*!< (@ 0x0000ED94) Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the @@ -15193,13 +17461,13 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - When enabled, the bac */ + When enabled, the backg */ uint32_t : 29; - } bit; - } MPU_CTRL; + } MPU_CTRL_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED98) Use the MPU Region Number Register to select + __IOM uint32_t MPU_RNR; /*!< (@ 0x0000ED98) Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. */ @@ -15209,11 +17477,11 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur The MPU supports 8 memory regions, so the permitted values of this field are 0-7. */ uint32_t : 28; - } bit; - } MPU_RNR; + } MPU_RNR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000ED9C) Read the MPU Region Base Address Register to + __IOM uint32_t MPU_RBAR; /*!< (@ 0x0000ED9C) Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a @@ -15233,14 +17501,14 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur MPU_RNR. Ignores the value of the REGION field. 1 = The processor: - Updates the value of the MPU_RNR to the value of the REG */ + Updates the value of the MPU_RNR to the value of the REGIO */ uint32_t : 3; __IOM uint32_t ADDR : 24; /*!< [31..8] Base address of the region. */ - } bit; - } MPU_RBAR; + } MPU_RBAR_b; + } ; union { - __IOM uint32_t reg; /*!< (@ 0x0000EDA0) Use the MPU Region Attribute and Size Register + __IOM uint32_t MPU_RASR; /*!< (@ 0x0000EDA0) Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. */ @@ -15262,8 +17530,8 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit */ - } bit; - } MPU_RASR; + } MPU_RASR_b; + } ; } PPB_Type; /*!< Size = 60836 (0xeda4) */ @@ -15309,6 +17577,7 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define VREG_AND_CHIP_RESET_BASE 0x40064000UL #define TBMAN_BASE 0x4006C000UL #define DMA_BASE 0x50000000UL +#define USBCTRL_DPRAM_BASE 0x50100000UL #define USBCTRL_REGS_BASE 0x50110000UL #define PIO0_BASE 0x50200000UL #define PIO1_BASE 0x50300000UL @@ -15357,6 +17626,7 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define VREG_AND_CHIP_RESET ((VREG_AND_CHIP_RESET_Type*) VREG_AND_CHIP_RESET_BASE) #define TBMAN ((TBMAN_Type*) TBMAN_BASE) #define DMA ((DMA_Type*) DMA_BASE) +#define USBCTRL_DPRAM ((USBCTRL_DPRAM_Type*) USBCTRL_DPRAM_BASE) #define USBCTRL_REGS ((USBCTRL_REGS_Type*) USBCTRL_REGS_BASE) #define PIO0 ((PIO0_Type*) PIO0_BASE) #define PIO1 ((PIO0_Type*) PIO1_BASE) @@ -15366,6 +17636,24 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur /** @} */ /* End of group Device_Peripheral_declaration */ +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + /* =========================================================================================================================== */ /* ================ Pos/Mask Peripheral Section ================ */ /* =========================================================================================================================== */ @@ -21503,8 +23791,6 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ #define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ /* ===================================================== IC_INTR_STAT ====================================================== */ -#define I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */ -#define I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_STAT_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ #define I2C0_IC_INTR_STAT_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_STAT_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ @@ -21532,8 +23818,6 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define I2C0_IC_INTR_STAT_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ #define I2C0_IC_INTR_STAT_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ /* ===================================================== IC_INTR_MASK ====================================================== */ -#define I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Pos (13UL) /*!< M_MASTER_ON_HOLD_READ_ONLY (Bit 13) */ -#define I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD_READ_ONLY (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_MASK_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ #define I2C0_IC_INTR_MASK_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_MASK_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ @@ -21561,8 +23845,6 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define I2C0_IC_INTR_MASK_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ #define I2C0_IC_INTR_MASK_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ /* =================================================== IC_RAW_INTR_STAT ==================================================== */ -#define I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */ -#define I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ #define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ #define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ #define I2C0_IC_RAW_INTR_STAT_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ @@ -23081,6 +25363,16 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define DMA_TIMER1_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ #define DMA_TIMER1_Y_Pos (0UL) /*!< Y (Bit 0) */ #define DMA_TIMER1_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER2 ========================================================= */ +#define DMA_TIMER2_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER2_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER2_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER2_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER3 ========================================================= */ +#define DMA_TIMER3_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER3_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER3_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER3_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ /* ================================================== MULTI_CHAN_TRIGGER =================================================== */ #define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Pos (0UL) /*!< MULTI_CHAN_TRIGGER (Bit 0) */ #define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Msk (0xffffUL) /*!< MULTI_CHAN_TRIGGER (Bitfield-Mask: 0xffff) */ @@ -23161,6 +25453,1398 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur /* ===================================================== CH11_DBG_TCR ====================================================== */ +/* =========================================================================================================================== */ +/* ================ USBCTRL_DPRAM ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SETUP_PACKET_LOW ==================================================== */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_WVALUE_Pos (16UL) /*!< WVALUE (Bit 16) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_WVALUE_Msk (0xffff0000UL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* =================================================== SETUP_PACKET_HIGH =================================================== */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Pos (16UL) /*!< WLENGTH (Bit 16) */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Msk (0xffff0000UL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP1_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP1_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP2_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP2_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP3_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP3_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP4_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP4_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP5_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP5_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP6_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP6_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP7_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP7_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP8_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP8_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP9_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP9_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP10_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP10_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP11_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP11_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP12_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP12_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP13_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP13_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP14_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP14_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP15_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP15_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ + + /* =========================================================================================================================== */ /* ================ USBCTRL_REGS ================ */ /* =========================================================================================================================== */ @@ -27665,12 +31349,108 @@ typedef enum { /*!< XOSC_STATUS_FREQ_RANGE /* =================================================== BUS_PRIORITY_ACK ==================================================== */ /* ======================================================= PERFCTR0 ======================================================== */ /* ======================================================= PERFSEL0 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL0 PERFSEL0 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL0_PERFSEL0 */ + BUSCTRL_PERFSEL0_PERFSEL0_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL0_PERFSEL0_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL0_PERFSEL0_Enum; + /* ======================================================= PERFCTR1 ======================================================== */ /* ======================================================= PERFSEL1 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL1 PERFSEL1 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL1_PERFSEL1 */ + BUSCTRL_PERFSEL1_PERFSEL1_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL1_PERFSEL1_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL1_PERFSEL1_Enum; + /* ======================================================= PERFCTR2 ======================================================== */ /* ======================================================= PERFSEL2 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL2 PERFSEL2 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL2_PERFSEL2 */ + BUSCTRL_PERFSEL2_PERFSEL2_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL2_PERFSEL2_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL2_PERFSEL2_Enum; + /* ======================================================= PERFCTR3 ======================================================== */ /* ======================================================= PERFSEL3 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL3 PERFSEL3 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL3_PERFSEL3 */ + BUSCTRL_PERFSEL3_PERFSEL3_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL3_PERFSEL3_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL3_PERFSEL3_Enum; + /* =========================================================================================================================== */ @@ -27831,12 +31611,6 @@ typedef enum { /*!< I2C0_IC_DATA_CMD_CMD /* ==================================================== IC_FS_SCL_HCNT ===================================================== */ /* ==================================================== IC_FS_SCL_LCNT ===================================================== */ /* ===================================================== IC_INTR_STAT ====================================================== */ -/* ====================================== I2C0 IC_INTR_STAT R_MASTER_ON_HOLD [13..13] ====================================== */ -typedef enum { /*!< I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD */ - I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_INACTIVE = 0,/*!< INACTIVE : R_MASTER_ON_HOLD interrupt is inactive */ - I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_ACTIVE = 1,/*!< ACTIVE : R_MASTER_ON_HOLD interrupt is active */ -} I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_Enum; - /* ======================================= I2C0 IC_INTR_STAT R_RESTART_DET [12..12] ======================================== */ typedef enum { /*!< I2C0_IC_INTR_STAT_R_RESTART_DET */ I2C0_IC_INTR_STAT_R_RESTART_DET_INACTIVE = 0, /*!< INACTIVE : R_RESTART_DET interrupt is inactive */ @@ -27916,12 +31690,6 @@ typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_UNDE } I2C0_IC_INTR_STAT_R_RX_UNDER_Enum; /* ===================================================== IC_INTR_MASK ====================================================== */ -/* ================================= I2C0 IC_INTR_MASK M_MASTER_ON_HOLD_READ_ONLY [13..13] ================================= */ -typedef enum { /*!< I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY */ - I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ENABLED = 0,/*!< ENABLED : MASTER_ON_HOLD interrupt is masked */ - I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_DISABLED = 1,/*!< DISABLED : MASTER_ON_HOLD interrupt is unmasked */ -} I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Enum; - /* ======================================= I2C0 IC_INTR_MASK M_RESTART_DET [12..12] ======================================== */ typedef enum { /*!< I2C0_IC_INTR_MASK_M_RESTART_DET */ I2C0_IC_INTR_MASK_M_RESTART_DET_ENABLED = 0, /*!< ENABLED : RESTART_DET interrupt is masked */ @@ -28001,12 +31769,6 @@ typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_UNDE } I2C0_IC_INTR_MASK_M_RX_UNDER_Enum; /* =================================================== IC_RAW_INTR_STAT ==================================================== */ -/* ===================================== I2C0 IC_RAW_INTR_STAT MASTER_ON_HOLD [13..13] ===================================== */ -typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD */ - I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_INACTIVE = 0,/*!< INACTIVE : MASTER_ON_HOLD interrupt is inactive */ - I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACTIVE = 1,/*!< ACTIVE : MASTER_ON_HOLD interrupt is active */ -} I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_Enum; - /* ====================================== I2C0 IC_RAW_INTR_STAT RESTART_DET [12..12] ======================================= */ typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RESTART_DET */ I2C0_IC_RAW_INTR_STAT_RESTART_DET_INACTIVE = 0,/*!< INACTIVE : RESTART_DET interrupt is inactive */ @@ -29060,6 +32822,8 @@ typedef enum { /*!< DMA_CH11_CTRL_TRIG_DATA_SIZ /* ========================================================= INTS1 ========================================================= */ /* ======================================================== TIMER0 ========================================================= */ /* ======================================================== TIMER1 ========================================================= */ +/* ======================================================== TIMER2 ========================================================= */ +/* ======================================================== TIMER3 ========================================================= */ /* ================================================== MULTI_CHAN_TRIGGER =================================================== */ /* ====================================================== SNIFF_CTRL ======================================================= */ /* ============================================== DMA SNIFF_CTRL CALC [5..8] =============================================== */ @@ -29105,6 +32869,572 @@ typedef enum { /*!< DMA_SNIFF_CTRL_CALC /* ===================================================== CH11_DBG_TCR ====================================================== */ +/* =========================================================================================================================== */ +/* ================ USBCTRL_DPRAM ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SETUP_PACKET_LOW ==================================================== */ +/* =================================================== SETUP_PACKET_HIGH =================================================== */ +/* ==================================================== EP1_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP1_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP1_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP1_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP2_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP2_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP2_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP2_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP3_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP3_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP3_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP3_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP4_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP4_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP4_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP4_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP5_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP5_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP5_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP5_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP6_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP6_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP6_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP6_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP7_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP7_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP7_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP7_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP8_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP8_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP8_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP8_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP9_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP9_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP9_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP9_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP10_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP10_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP10_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP10_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP11_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP11_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP11_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP11_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP12_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP12_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP12_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP12_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP13_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP13_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP13_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP13_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP14_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP14_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP14_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP14_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP15_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP15_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP15_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP15_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP0_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP0_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP1_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP1_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP2_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP2_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP3_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP3_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP4_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP4_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP5_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP5_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP6_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP6_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP7_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP7_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP8_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP8_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP9_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP9_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP10_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP10_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP11_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP11_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP12_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP12_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP13_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP13_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP14_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP14_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP15_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP15_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + + + /* =========================================================================================================================== */ /* ================ USBCTRL_REGS ================ */ /* =========================================================================================================================== */ diff --git a/cpu/rpx0xx/periph/gpio.c b/cpu/rpx0xx/periph/gpio.c index 483ed447228a4..96afefd06b69e 100644 --- a/cpu/rpx0xx/periph/gpio.c +++ b/cpu/rpx0xx/periph/gpio.c @@ -42,8 +42,8 @@ static void *_args[GPIO_PIN_NUMOF]; int gpio_init(gpio_t pin, gpio_mode_t mode) { assert(pin < GPIO_PIN_NUMOF); - SIO->GPIO_OE_CLR.reg = 1LU << pin; - SIO->GPIO_OUT_CLR.reg = 1LU << pin; + SIO->GPIO_OE_CLR = 1LU << pin; + SIO->GPIO_OUT_CLR = 1LU << pin; switch (mode) { case GPIO_IN: @@ -98,7 +98,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) gpio_set_pad_config(pin, pad_config); gpio_set_io_config(pin, io_config); } - SIO->GPIO_OE_SET.reg = 1LU << pin; + SIO->GPIO_OE_SET = 1LU << pin; break; default: return -ENOTSUP; @@ -108,27 +108,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) int gpio_read(gpio_t pin) { - if (SIO->GPIO_OE.reg & (1LU << pin)) { + if (SIO->GPIO_OE & (1LU << pin)) { /* pin is output: */ - return SIO->GPIO_OUT.reg & (1LU << pin); + return SIO->GPIO_OUT & (1LU << pin); } /* pin is input: */ - return SIO->GPIO_IN.reg & (1LU << pin); + return SIO->GPIO_IN & (1LU << pin); } void gpio_set(gpio_t pin) { - SIO->GPIO_OUT_SET.reg = 1LU << pin; + SIO->GPIO_OUT_SET = 1LU << pin; } void gpio_clear(gpio_t pin) { - SIO->GPIO_OUT_CLR.reg = 1LU << pin; + SIO->GPIO_OUT_CLR = 1LU << pin; } void gpio_toggle(gpio_t pin) { - SIO->GPIO_OUT_XOR.reg = 1LU << pin; + SIO->GPIO_OUT_XOR = 1LU << pin; } void gpio_write(gpio_t pin, int value) @@ -144,8 +144,8 @@ void gpio_write(gpio_t pin, int value) #ifdef MODULE_PERIPH_GPIO_IRQ static void _irq_enable(gpio_t pin, unsigned flank) { - volatile uint32_t *irq_enable_regs = &IO_BANK0->PROC0_INTE0.reg; - volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0.reg; + volatile uint32_t *irq_enable_regs = &IO_BANK0->PROC0_INTE0; + volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0; /* There are 4 bits to control IRQs per pin, hence the configuration is split across multiple * I/O registers. The following calculates the position the four bits matching the given pin, * where idx refers to the I/O register and shift_amount to the position in the I/O register. @@ -201,15 +201,15 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_cb_t cb void isr_io_bank0(void) { unsigned offset = 0; - volatile uint32_t *irq_status_regs = &IO_BANK0->PROC0_INTS0.reg; - volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0.reg; + volatile uint32_t *irq_status_regs = &IO_BANK0->PROC0_INTS0; + volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0; DEBUG("[rp0x00] GPIO IRQ mask: %08x, %08x, %08x, %08x\n", - (unsigned)IO_BANK0->PROC0_INTE0.reg, (unsigned)IO_BANK0->PROC0_INTE1.reg, - (unsigned)IO_BANK0->PROC0_INTE2.reg, (unsigned)IO_BANK0->PROC0_INTE3.reg); + (unsigned)IO_BANK0->PROC0_INTE0, (unsigned)IO_BANK0->PROC0_INTE1, + (unsigned)IO_BANK0->PROC0_INTE2, (unsigned)IO_BANK0->PROC0_INTE3); DEBUG("[rp0x00] GPIO IRQ status: %08x, %08x, %08x, %08x\n", - (unsigned)IO_BANK0->PROC0_INTS0.reg, (unsigned)IO_BANK0->PROC0_INTS1.reg, - (unsigned)IO_BANK0->PROC0_INTS2.reg, (unsigned)IO_BANK0->PROC0_INTS3.reg); + (unsigned)IO_BANK0->PROC0_INTS0, (unsigned)IO_BANK0->PROC0_INTS1, + (unsigned)IO_BANK0->PROC0_INTS2, (unsigned)IO_BANK0->PROC0_INTS3); /* There are four IRQ status bits per pin, so there is info for 8 pins per I/O register. * We will iterate over all IRQ status I/O registers in the outer loop, and over all 8 pins diff --git a/cpu/rpx0xx/periph/uart.c b/cpu/rpx0xx/periph/uart.c index 26b7e6fcca4ea..23ed6b2ed2350 100644 --- a/cpu/rpx0xx/periph/uart.c +++ b/cpu/rpx0xx/periph/uart.c @@ -48,7 +48,7 @@ static uint32_t uartcr; void _irq_enable(uart_t uart) { UART0_Type *dev = uart_config[uart].dev; - dev->UARTIMSC.reg = UART0_UARTIMSC_RXIM_Msk; + dev->UARTIMSC = UART0_UARTIMSC_RXIM_Msk; NVIC_EnableIRQ(uart_config[uart].irqn); } @@ -72,8 +72,8 @@ void _set_symbolrate(uart_t uart, uint32_t baud) baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; } - dev->UARTIBRD.reg = baud_ibrd; - dev->UARTFBRD.reg = baud_fbrd; + dev->UARTIBRD = baud_ibrd; + dev->UARTFBRD = baud_fbrd; } int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity, @@ -82,7 +82,7 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity assert((unsigned)uart < UART_NUMOF); UART0_Type *dev = uart_config[uart].dev; - io_reg_atomic_clear(&dev->UARTCR.reg, + io_reg_atomic_clear(&dev->UARTCR, UART0_UARTCR_UARTEN_Msk | UART0_UARTCR_TXE_Msk | UART0_UARTCR_RXE_Msk); /* Beware of strange hardware bug: If the configuration bitmask is prepared in register and @@ -91,26 +91,26 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity * next char send out. If the configuration is updated in multiple bus accesses, it will apply * directly to the next char. So: Double check e.g. with tests/periph_uart_mode after touching * the initialization code here */ - dev->UARTLCR_H.reg = (uint32_t)data_bits << UART0_UARTLCR_H_WLEN_Pos; + dev->UARTLCR_H = (uint32_t)data_bits << UART0_UARTLCR_H_WLEN_Pos; if (stop_bits == UART_STOP_BITS_2) { - io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_STP2_Msk); + io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_STP2_Msk); } switch (uart_parity) { case UART_PARITY_NONE: break; case UART_PARITY_EVEN: - io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk); + io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk); break; case UART_PARITY_ODD: - io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_PEN_Msk); + io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk); break; default: return UART_NOMODE; } - io_reg_atomic_set(&dev->UARTCR.reg, + io_reg_atomic_set(&dev->UARTCR, UART0_UARTCR_UARTEN_Msk | UART0_UARTCR_TXE_Msk | UART0_UARTCR_RXE_Msk); return UART_OK; @@ -148,7 +148,7 @@ void uart_deinit_pins(uart_t uart) { assert((unsigned)uart < UART_NUMOF); gpio_reset_all_config(uart_config[uart].tx_pin); - SIO->GPIO_OE_CLR.reg = 1LU << uart_config[uart].tx_pin; + SIO->GPIO_OE_CLR = 1LU << uart_config[uart].tx_pin; if (ctx[uart].rx_cb) { gpio_reset_all_config(uart_config[uart].rx_pin); } @@ -167,10 +167,10 @@ void uart_poweron(uart_t uart) _poweron(uart); UART0_Type *dev = uart_config[uart].dev; /* restore configuration registers */ - dev->UARTIBRD.reg = uartibrd; - dev->UARTFBRD.reg = uartfbrd; - dev->UARTLCR_H.reg = uartlcr_h; - dev->UARTCR.reg = uartcr; + dev->UARTIBRD = uartibrd; + dev->UARTFBRD = uartfbrd; + dev->UARTLCR_H = uartlcr_h; + dev->UARTCR = uartcr; /* restore IRQs, if needed */ if (ctx[uart].rx_cb != NULL) { _irq_enable(uart); @@ -183,10 +183,10 @@ void uart_poweroff(uart_t uart) assert((unsigned)uart < UART_NUMOF); UART0_Type *dev = uart_config[uart].dev; /* backup configuration registers */ - uartibrd = dev->UARTIBRD.reg; - uartfbrd = dev->UARTFBRD.reg; - uartlcr_h = dev->UARTLCR_H.reg; - uartcr = dev->UARTCR.reg; + uartibrd = dev->UARTIBRD; + uartfbrd = dev->UARTFBRD; + uartlcr_h = dev->UARTLCR_H; + uartcr = dev->UARTCR; /* disconnect GPIOs and power off peripheral */ uart_deinit_pins(uart); periph_reset((uart) ? RESETS_RESET_uart1_Msk : RESETS_RESET_uart0_Msk); @@ -217,10 +217,10 @@ int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) if (rx_cb != NULL) { _irq_enable(uart); /* clear any pending data and IRQ to avoid receiving a garbage char */ - uint32_t status = dev->UARTRIS.reg; - dev->UARTICR.reg = status; - (void)dev->UARTDR.reg; - io_reg_atomic_set(&dev->UARTCR.reg, UART0_UARTCR_RXE_Msk); + uint32_t status = dev->UARTRIS; + dev->UARTICR = status; + (void)dev->UARTDR; + io_reg_atomic_set(&dev->UARTCR, UART0_UARTCR_RXE_Msk); } return UART_OK; @@ -232,8 +232,8 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len) UART0_Type *dev = uart_config[uart].dev; for (size_t i = 0; i < len; i++) { - dev->UARTDR.reg = data[i]; - while (!(dev->UARTRIS.reg & UART0_UARTRIS_TXRIS_Msk)) { } + dev->UARTDR = data[i]; + while (!(dev->UARTRIS & UART0_UARTRIS_TXRIS_Msk)) { } } } @@ -253,11 +253,11 @@ void isr_handler(uint8_t num) { UART0_Type *dev = uart_config[num].dev; - uint32_t status = dev->UARTMIS.reg; - dev->UARTICR.reg = status; + uint32_t status = dev->UARTMIS; + dev->UARTICR = status; if (status & UART0_UARTMIS_RXMIS_Msk) { - uint32_t data = dev->UARTDR.reg; + uint32_t data = dev->UARTDR; if (data & (UART0_UARTDR_BE_Msk | UART0_UARTDR_PE_Msk | UART0_UARTDR_FE_Msk)) { DEBUG_PUTS("[rpx0xx] uart RX error (parity, break, or framing error"); } diff --git a/cpu/rpx0xx/pll.c b/cpu/rpx0xx/pll.c index ce78350706ea6..33c9de7a1115a 100644 --- a/cpu/rpx0xx/pll.c +++ b/cpu/rpx0xx/pll.c @@ -44,22 +44,22 @@ static void _pll_start(PLL_SYS_Type *pll, uint8_t ref_div, assert(post_div_2 <= PLL_POSTDIV_MAX); /* program reference clock divider */ - io_reg_write_dont_corrupt(&pll->CS.reg, ref_div << PLL_SYS_CS_REFDIV_Pos, + io_reg_write_dont_corrupt(&pll->CS, ref_div << PLL_SYS_CS_REFDIV_Pos, PLL_SYS_CS_REFDIV_Msk); /* program feedback divider */ - io_reg_write_dont_corrupt(&pll->FBDIV_INT.reg, + io_reg_write_dont_corrupt(&pll->FBDIV_INT, vco_feedback_scale << PLL_SYS_FBDIV_INT_FBDIV_INT_Pos, PLL_SYS_FBDIV_INT_FBDIV_INT_Msk); /* turn on the main power */ - io_reg_atomic_clear(&pll->PWR.reg, (1U << PLL_SYS_PWR_VCOPD_Pos) + io_reg_atomic_clear(&pll->PWR, (1U << PLL_SYS_PWR_VCOPD_Pos) | (1U << PLL_SYS_PWR_DSMPD_Pos) | (1U << PLL_SYS_PWR_PD_Pos)); /* wait for VCO to lock (i.e. keep its output stable) */ - while (!pll->CS.bit.LOCK) { } + while (!(pll->CS & PLL_SYS_CS_LOCK_Msk)) { } /* set up post divisors and turn them on */ - pll->PRIM.reg = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos) + pll->PRIM = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos) | (post_div_2 << PLL_SYS_PRIM_POSTDIV2_Pos); - io_reg_atomic_clear(&pll->PWR.reg, 1U << PLL_SYS_PWR_POSTDIVPD_Pos); + io_reg_atomic_clear(&pll->PWR, 1U << PLL_SYS_PWR_POSTDIVPD_Pos); } /** @@ -72,7 +72,7 @@ static void _pll_stop(PLL_SYS_Type *pll) | (1U << PLL_SYS_PWR_POSTDIVPD_Pos) | (1U << PLL_SYS_PWR_DSMPD_Pos) | (1U << PLL_SYS_PWR_PD_Pos); - io_reg_atomic_set(&pll->PWR.reg, reg); + io_reg_atomic_set(&pll->PWR, reg); } void pll_start_sys(uint8_t ref_div, diff --git a/cpu/rpx0xx/rosc.c b/cpu/rpx0xx/rosc.c index 9783efa91b431..77b997d092223 100644 --- a/cpu/rpx0xx/rosc.c +++ b/cpu/rpx0xx/rosc.c @@ -31,19 +31,19 @@ void rosc_start(void) { /* set drive strengths to default 0 */ - io_reg_atomic_clear(&ROSC->FREQA.reg, ROSC_FREQA_PASSWD_Msk); - io_reg_atomic_clear(&ROSC->FREQB.reg, ROSC_FREQB_PASSWD_Msk); + io_reg_atomic_clear(&ROSC->FREQA, ROSC_FREQA_PASSWD_Msk); + io_reg_atomic_clear(&ROSC->FREQB, ROSC_FREQB_PASSWD_Msk); /* apply settings with magic value 0x9696 */ const uint32_t magic = 0x9696U; - io_reg_write_dont_corrupt(&ROSC->FREQA.reg, magic << ROSC_FREQA_PASSWD_Pos, + io_reg_write_dont_corrupt(&ROSC->FREQA, magic << ROSC_FREQA_PASSWD_Pos, ROSC_FREQA_PASSWD_Msk); - io_reg_write_dont_corrupt(&ROSC->FREQB.reg, magic << ROSC_FREQB_PASSWD_Pos, + io_reg_write_dont_corrupt(&ROSC->FREQB, magic << ROSC_FREQB_PASSWD_Pos, ROSC_FREQB_PASSWD_Msk); /* default divider is 16 */ - io_reg_write_dont_corrupt(&ROSC->DIV.reg, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk); - io_reg_atomic_set(&ROSC->CTRL.reg, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos); - while (!ROSC->STATUS.bit.STABLE) { } + io_reg_write_dont_corrupt(&ROSC->DIV, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk); + io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos); + while (!(ROSC->STATUS & ROSC_STATUS_STABLE_Msk)) { } } /** @@ -53,5 +53,5 @@ void rosc_start(void) */ void rosc_stop(void) { - io_reg_atomic_set(&ROSC->CTRL.reg, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos); + io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos); } diff --git a/cpu/rpx0xx/xosc.c b/cpu/rpx0xx/xosc.c index 4d22b59018d3b..ddf522d5efd34 100644 --- a/cpu/rpx0xx/xosc.c +++ b/cpu/rpx0xx/xosc.c @@ -34,15 +34,15 @@ void xosc_start(uint32_t f_ref) { assert(f_ref == MHZ(12)); uint32_t delay = _xosc_conf_sartup_delay(f_ref, 1); - io_reg_write_dont_corrupt(&XOSC->STARTUP.reg, delay << XOSC_STARTUP_DELAY_Pos, + io_reg_write_dont_corrupt(&XOSC->STARTUP, delay << XOSC_STARTUP_DELAY_Pos, XOSC_STARTUP_DELAY_Msk); - io_reg_write_dont_corrupt(&XOSC->CTRL.reg, XOSC_CTRL_ENABLE_ENABLE << XOSC_CTRL_ENABLE_Pos, + io_reg_write_dont_corrupt(&XOSC->CTRL, XOSC_CTRL_ENABLE_ENABLE << XOSC_CTRL_ENABLE_Pos, XOSC_CTRL_ENABLE_Msk); - while (!XOSC->STATUS.bit.STABLE) { } + while (!(XOSC->STATUS & XOSC_STATUS_STABLE_Msk)) { } } void xosc_stop(void) { - io_reg_write_dont_corrupt(&XOSC->CTRL.reg, XOSC_CTRL_ENABLE_DISABLE << XOSC_CTRL_ENABLE_Pos, + io_reg_write_dont_corrupt(&XOSC->CTRL, XOSC_CTRL_ENABLE_DISABLE << XOSC_CTRL_ENABLE_Pos, XOSC_CTRL_ENABLE_Msk); }