From 3e59f40057be464d2f7a444b5b6ec683b1fafc6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 2 May 2017 19:33:05 +0200 Subject: [PATCH 01/82] drivers/kw41zrf: Transceiver driver for the KW41Z radio This is the radio found in NXP Kinetis KW41Z, KW21Z. Only 802.15.4 mode is implemented (KW41Z also supports BLE on the same transceiver). The driver uses vendor supplied initialization code for the low level XCVR hardware, these files were imported from KSDK 2.2.0 (framework_5.3.5) --- boards/frdm-kw41z/Makefile.dep | 4 + cpu/kw41z/include/vendor/MKW21Z4_features.h | 1781 ++++++++++++++ cpu/kw41z/include/vendor/MKW31Z4_features.h | 2016 ++++++++++++++++ cpu/kw41z/include/vendor/MKW41Z4_features.h | 2020 ++++++++++++++++ drivers/Makefile.dep | 10 + drivers/Makefile.include | 4 + drivers/include/kw41zrf.h | 169 ++ drivers/kw41zrf/Makefile | 4 + drivers/kw41zrf/include/kw41zrf_getset.h | 186 ++ drivers/kw41zrf/include/kw41zrf_intern.h | 212 ++ drivers/kw41zrf/include/kw41zrf_netdev.h | 36 + drivers/kw41zrf/kw41zrf.c | 222 ++ drivers/kw41zrf/kw41zrf_getset.c | 287 +++ drivers/kw41zrf/kw41zrf_intern.c | 195 ++ drivers/kw41zrf/kw41zrf_netdev.c | 1102 +++++++++ drivers/kw41zrf/vendor/Common/EmbeddedTypes.h | 221 ++ .../Interface/fsl_os_abstraction.h | 614 +++++ .../Interface/fsl_os_abstraction_config.h | 69 + drivers/kw41zrf/vendor/XCVR/MKW41Z4/Makefile | 8 + .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c | 212 ++ .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h | 157 ++ .../XCVR/MKW41Z4/fsl_os_abstraction_riot.c | 27 + .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 2142 +++++++++++++++++ .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 1247 ++++++++++ .../vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c | 213 ++ .../vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c | 207 ++ .../XCVR/MKW41Z4/fsl_xcvr_common_config.c | 629 +++++ .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 418 ++++ .../fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c | 403 ++++ .../fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c | 422 ++++ .../fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c | 404 ++++ .../fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c | 404 ++++ .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 418 ++++ .../MKW41Z4/fsl_xcvr_mode_datarate_config.c | 218 ++ .../vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c | 407 ++++ .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 1002 ++++++++ .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 139 ++ .../XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c | 250 ++ .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c | 536 +++++ .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h | 186 ++ sys/auto_init/auto_init.c | 5 + sys/auto_init/netif/auto_init_kw41zrf.c | 61 + 42 files changed, 19267 insertions(+) create mode 100644 cpu/kw41z/include/vendor/MKW21Z4_features.h create mode 100644 cpu/kw41z/include/vendor/MKW31Z4_features.h create mode 100644 cpu/kw41z/include/vendor/MKW41Z4_features.h create mode 100644 drivers/include/kw41zrf.h create mode 100644 drivers/kw41zrf/Makefile create mode 100644 drivers/kw41zrf/include/kw41zrf_getset.h create mode 100644 drivers/kw41zrf/include/kw41zrf_intern.h create mode 100644 drivers/kw41zrf/include/kw41zrf_netdev.h create mode 100644 drivers/kw41zrf/kw41zrf.c create mode 100644 drivers/kw41zrf/kw41zrf_getset.c create mode 100644 drivers/kw41zrf/kw41zrf_intern.c create mode 100644 drivers/kw41zrf/kw41zrf_netdev.c create mode 100644 drivers/kw41zrf/vendor/Common/EmbeddedTypes.h create mode 100644 drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h create mode 100644 drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/Makefile create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h create mode 100644 sys/auto_init/netif/auto_init_kw41zrf.c diff --git a/boards/frdm-kw41z/Makefile.dep b/boards/frdm-kw41z/Makefile.dep index 5fa6d7562001..e548752127d2 100644 --- a/boards/frdm-kw41z/Makefile.dep +++ b/boards/frdm-kw41z/Makefile.dep @@ -4,4 +4,8 @@ ifneq (,$(filter saul_default,$(USEMODULE))) USEMODULE += fxos8700 endif +ifneq (,$(filter netdev_default gnrc_netdev_default,$(USEMODULE))) + USEMODULE += kw41zrf +endif + include $(RIOTCPU)/kinetis/Makefile.dep diff --git a/cpu/kw41z/include/vendor/MKW21Z4_features.h b/cpu/kw41z/include/vendor/MKW21Z4_features.h new file mode 100644 index 000000000000..f9e93c01dc69 --- /dev/null +++ b/cpu/kw41z/include/vendor/MKW21Z4_features.h @@ -0,0 +1,1781 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2015-09-23 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MKW21Z4_FEATURES_H_ +#define _MKW21Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (1) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (3) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (1) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DCDC module features */ + +/* @brief Has VDD1P5 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) +/* @brief Has VDD1P45 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKW21Z256VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKW21Z512VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKW21Z256VHT4) */ + +/* GENFSK module features */ + +/* No feature definitions */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) + +/* LLWU module features */ + +/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) +/* @brief Has pins 8-15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) +/* @brief Maximum number of internal modules connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) +/* @brief Number of digital filters. */ +#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) +/* @brief Has MF register. */ +#define FSL_FEATURE_LLWU_HAS_MF (0) +/* @brief Has PF register. */ +#define FSL_FEATURE_LLWU_HAS_PF (0) +/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ +#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) +/* @brief Has no internal module wakeup flag register. */ +#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) +/* @brief Has external pin 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) +/* @brief Has external pin 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) +/* @brief Has external pin 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) +/* @brief Has external pin 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) +/* @brief Has external pin 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) +/* @brief Has external pin 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) +/* @brief Has external pin 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) +/* @brief Has external pin 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) +/* @brief Has external pin 8 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) +/* @brief Has external pin 9 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) +/* @brief Has external pin 10 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) +/* @brief Has external pin 11 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) +/* @brief Has external pin 12 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) +/* @brief Has external pin 13 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) +/* @brief Has external pin 14 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) +/* @brief Has external pin 15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) +/* @brief Has external pin 16 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) +/* @brief Has external pin 17 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) +/* @brief Has external pin 18 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) +/* @brief Has external pin 19 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) +/* @brief Has external pin 20 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) +/* @brief Has external pin 21 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) +/* @brief Has external pin 22 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) +/* @brief Has external pin 23 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) +/* @brief Has external pin 24 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) +/* @brief Has external pin 25 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) +/* @brief Has external pin 26 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) +/* @brief Has external pin 27 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) +/* @brief Has external pin 28 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) +/* @brief Has external pin 29 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) +/* @brief Has external pin 30 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) +/* @brief Has external pin 31 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) +/* @brief Has internal module 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) +/* @brief Has internal module 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) +/* @brief Has internal module 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) +/* @brief Has internal module 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) +/* @brief Has internal module 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) +/* @brief Has internal module 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) +/* @brief Has internal module 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) +/* @brief Has internal module 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) +/* @brief Has Version ID Register (LLWU_VERID). */ +#define FSL_FEATURE_LLWU_HAS_VERID (0) +/* @brief Has Parameter Register (LLWU_PARAM). */ +#define FSL_FEATURE_LLWU_HAS_PARAM (0) +/* @brief Width of registers of the LLWU. */ +#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) +/* @brief Has DMA Enable register (LLWU_DE). */ +#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* LTC module features */ + +/* @brief LTC module supports DES algorithm. */ +#define FSL_FEATURE_LTC_HAS_DES (0) +/* @brief LTC module supports PKHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_PKHA (0) +/* @brief LTC module supports SHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_SHA (0) +/* @brief LTC module supports AES GCM mode. */ +#define FSL_FEATURE_LTC_HAS_GCM (0) +/* @brief LTC module supports DPAMS registers. */ +#define FSL_FEATURE_LTC_HAS_DPAMS (0) +/* @brief LTC module supports AES with 24 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES192 (0) +/* @brief LTC module supports AES with 32 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES256 (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (0) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (0) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (0) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (0) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RADIO module features */ + +/* @brief Zigbee availability. */ +#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) +/* @brief Bluetooth availability. */ +#define FSL_FEATURE_RADIO_HAS_BLE (0) +/* @brief ANT availability */ +#define FSL_FEATURE_RADIO_HAS_ANT (1) +/* @brief Generic FSK module availability */ +#define FSL_FEATURE_RADIO_HAS_GENFSK (1) +/* @brief Major version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) +/* @brief Minor version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MINOR (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RSIM module features */ + +/* No feature definitions */ + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (4) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) + +/* TRNG module features */ + +/* No feature definitions */ + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* XCVR_ANALOG module features */ + +/* No feature definitions */ + +/* XCVR_PHY module features */ + +/* No feature definitions */ + +/* ZLL module features */ + +/* No feature definitions */ + +#endif /* _MKW21Z4_FEATURES_H_ */ + diff --git a/cpu/kw41z/include/vendor/MKW31Z4_features.h b/cpu/kw41z/include/vendor/MKW31Z4_features.h new file mode 100644 index 000000000000..56b14a01a5b4 --- /dev/null +++ b/cpu/kw41z/include/vendor/MKW31Z4_features.h @@ -0,0 +1,2016 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2015-09-23 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MKW31Z4_FEATURES_H_ +#define _MKW31Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (1) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (3) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (1) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* BTLE_RF module features */ + +/* No feature definitions */ + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DCDC module features */ + +/* @brief Has VDD1P5 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) +/* @brief Has VDD1P45 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKW31Z256VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKW31Z512CAT4) || defined(CPU_MKW31Z512VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKW31Z256VHT4) */ + +/* GENFSK module features */ + +/* No feature definitions */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) + +/* LLWU module features */ + +#if defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MKW31Z512CAT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) */ + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* LTC module features */ + +/* @brief LTC module supports DES algorithm. */ +#define FSL_FEATURE_LTC_HAS_DES (0) +/* @brief LTC module supports PKHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_PKHA (0) +/* @brief LTC module supports SHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_SHA (0) +/* @brief LTC module supports AES GCM mode. */ +#define FSL_FEATURE_LTC_HAS_GCM (0) +/* @brief LTC module supports DPAMS registers. */ +#define FSL_FEATURE_LTC_HAS_DPAMS (0) +/* @brief LTC module supports AES with 24 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES192 (0) +/* @brief LTC module supports AES with 32 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES256 (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (0) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (0) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (0) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (0) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RADIO module features */ + +/* @brief Zigbee availability. */ +#define FSL_FEATURE_RADIO_HAS_ZIGBEE (0) +/* @brief Bluetooth availability. */ +#define FSL_FEATURE_RADIO_HAS_BLE (1) +/* @brief ANT availability */ +#define FSL_FEATURE_RADIO_HAS_ANT (1) +/* @brief Generic FSK module availability */ +#define FSL_FEATURE_RADIO_HAS_GENFSK (1) +/* @brief Major version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) +/* @brief Minor version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MINOR (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RSIM module features */ + +/* No feature definitions */ + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (4) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) + +/* TRNG module features */ + +/* No feature definitions */ + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* XCVR_ANALOG module features */ + +/* No feature definitions */ + +/* XCVR_PHY module features */ + +/* No feature definitions */ + +#endif /* _MKW31Z4_FEATURES_H_ */ + diff --git a/cpu/kw41z/include/vendor/MKW41Z4_features.h b/cpu/kw41z/include/vendor/MKW41Z4_features.h new file mode 100644 index 000000000000..7e7fee364b5c --- /dev/null +++ b/cpu/kw41z/include/vendor/MKW41Z4_features.h @@ -0,0 +1,2020 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2015-09-23 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-09-23) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MKW41Z4_FEATURES_H_ +#define _MKW41Z4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (1) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (1) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (1) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (2) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (1) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (1) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (1) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (1) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (1) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (1) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (1) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (3) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (1) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (1) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (1) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (1) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (3) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (1) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (1) + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* BTLE_RF module features */ + +/* No feature definitions */ + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* COP module features */ + +/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ +#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) +/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ +#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) +/* @brief Has more clock sources like MCGIRC */ +#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) +/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ +#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (2) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) + +/* DCDC module features */ + +/* @brief Has VDD1P5 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) +/* @brief Has VDD1P45 bits in DCDC REG3. */ +#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* FLASH module features */ + +#if defined(CPU_MKW41Z256VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#elif defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4) + /* @brief Is of type FTFA. */ + #define FSL_FEATURE_FLASH_IS_FTFA (1) + /* @brief Is of type FTFE. */ + #define FSL_FEATURE_FLASH_IS_FTFE (0) + /* @brief Is of type FTFL. */ + #define FSL_FEATURE_FLASH_IS_FTFL (0) + /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) + /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) + /* @brief Has EEPROM region protection (register FEPROT). */ + #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) + /* @brief Has data flash region protection (register FDPROT). */ + #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) + /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ + #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) + /* @brief Has flash cache control in FMC module. */ + #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) + /* @brief Has flash cache control in MCM module. */ + #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) + /* @brief Has flash cache control in MSCM module. */ + #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) + /* @brief Has prefetch speculation control in flash, such as kv5x. */ + #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) + /* @brief P-Flash start address. */ + #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) + /* @brief P-Flash block count. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) + /* @brief P-Flash block size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) + /* @brief P-Flash sector size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) + /* @brief P-Flash write unit size. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) + /* @brief P-Flash data path width. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) + /* @brief P-Flash block swap feature. */ + #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) + /* @brief P-Flash protection region count. */ + #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) + /* @brief Has FlexNVM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) + /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) + /* @brief FlexNVM block count. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) + /* @brief FlexNVM block size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) + /* @brief FlexNVM sector size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) + /* @brief FlexNVM write unit size. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) + /* @brief FlexNVM data path width. */ + #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) + /* @brief Has FlexRAM memory. */ + #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) + /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ + #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) + /* @brief FlexRAM size. */ + #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) + /* @brief Has 0x00 Read 1s Block command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) + /* @brief Has 0x01 Read 1s Section command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) + /* @brief Has 0x02 Program Check command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) + /* @brief Has 0x03 Read Resource command. */ + #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) + /* @brief Has 0x06 Program Longword command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) + /* @brief Has 0x07 Program Phrase command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) + /* @brief Has 0x08 Erase Flash Block command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) + /* @brief Has 0x09 Erase Flash Sector command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) + /* @brief Has 0x0B Program Section command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) + /* @brief Has 0x40 Read 1s All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) + /* @brief Has 0x41 Read Once command. */ + #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) + /* @brief Has 0x43 Program Once command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) + /* @brief Has 0x44 Erase All Blocks command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) + /* @brief Has 0x45 Verify Backdoor Access Key command. */ + #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) + /* @brief Has 0x46 Swap Control command. */ + #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) + /* @brief Has 0x49 Erase All Blocks Unsecure command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) + /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x4B Erase All Execute-only Segments command. */ + #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) + /* @brief Has 0x80 Program Partition command. */ + #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) + /* @brief Has 0x81 Set FlexRAM Function command. */ + #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) + /* @brief P-Flash Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) + /* @brief P-Flash Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) + /* @brief P-Flash Program check command address alignment. */ + #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Erase sector command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Rrogram/Verify section command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Read resource command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM Program check command address alignment. */ + #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) + /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) + /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) + /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) + /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) + /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) + /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) + /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) + /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) + /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) + /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) + /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) + /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) + /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) + /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) + /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) + /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) + /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) + /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ + #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) +#endif /* defined(CPU_MKW41Z256VHT4) */ + +/* GENFSK module features */ + +/* No feature definitions */ + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) + +/* LLWU module features */ + +#if defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#elif defined(CPU_MKW41Z512CAT4) + /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) + /* @brief Has pins 8-15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) + /* @brief Maximum number of internal modules connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) + /* @brief Number of digital filters. */ + #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) + /* @brief Has MF register. */ + #define FSL_FEATURE_LLWU_HAS_MF (0) + /* @brief Has PF register. */ + #define FSL_FEATURE_LLWU_HAS_PF (0) + /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ + #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) + /* @brief Has no internal module wakeup flag register. */ + #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) + /* @brief Has external pin 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) + /* @brief Has external pin 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) + /* @brief Has external pin 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) + /* @brief Has external pin 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) + /* @brief Has external pin 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) + /* @brief Has external pin 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) + /* @brief Has external pin 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) + /* @brief Has external pin 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) + /* @brief Has external pin 8 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) + /* @brief Has external pin 9 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) + /* @brief Has external pin 10 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) + /* @brief Has external pin 11 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) + /* @brief Has external pin 12 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) + /* @brief Has external pin 13 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) + /* @brief Has external pin 14 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) + /* @brief Has external pin 15 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) + /* @brief Has external pin 16 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) + /* @brief Has external pin 17 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) + /* @brief Has external pin 18 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) + /* @brief Has external pin 19 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) + /* @brief Has external pin 20 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) + /* @brief Has external pin 21 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) + /* @brief Has external pin 22 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) + /* @brief Has external pin 23 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) + /* @brief Has external pin 24 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) + /* @brief Has external pin 25 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) + /* @brief Has external pin 26 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) + /* @brief Has external pin 27 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) + /* @brief Has external pin 28 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) + /* @brief Has external pin 29 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) + /* @brief Has external pin 30 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) + /* @brief Has external pin 31 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) + /* @brief Index of port of external pin. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) + /* @brief Number of external pin port on specified port. */ + #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) + /* @brief Has internal module 0 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) + /* @brief Has internal module 1 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) + /* @brief Has internal module 2 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) + /* @brief Has internal module 3 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) + /* @brief Has internal module 4 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) + /* @brief Has internal module 5 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) + /* @brief Has internal module 6 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) + /* @brief Has internal module 7 connected to LLWU device. */ + #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) + /* @brief Has Version ID Register (LLWU_VERID). */ + #define FSL_FEATURE_LLWU_HAS_VERID (0) + /* @brief Has Parameter Register (LLWU_PARAM). */ + #define FSL_FEATURE_LLWU_HAS_PARAM (0) + /* @brief Width of registers of the LLWU. */ + #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) + /* @brief Has DMA Enable register (LLWU_DE). */ + #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) +#endif /* defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) */ + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* LPUART module features */ + +/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ +#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (0) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (0) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (0) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (0) + +/* LTC module features */ + +/* @brief LTC module supports DES algorithm. */ +#define FSL_FEATURE_LTC_HAS_DES (0) +/* @brief LTC module supports PKHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_PKHA (0) +/* @brief LTC module supports SHA algorithm. */ +#define FSL_FEATURE_LTC_HAS_SHA (0) +/* @brief LTC module supports AES GCM mode. */ +#define FSL_FEATURE_LTC_HAS_GCM (0) +/* @brief LTC module supports DPAMS registers. */ +#define FSL_FEATURE_LTC_HAS_DPAMS (0) +/* @brief LTC module supports AES with 24 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES192 (0) +/* @brief LTC module supports AES with 32 bytes key. */ +#define FSL_FEATURE_LTC_HAS_AES256 (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (0) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (0) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (0) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (0) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (0) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (2) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (0) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (1) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RADIO module features */ + +/* @brief Zigbee availability. */ +#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) +/* @brief Bluetooth availability. */ +#define FSL_FEATURE_RADIO_HAS_BLE (1) +/* @brief ANT availability */ +#define FSL_FEATURE_RADIO_HAS_ANT (1) +/* @brief Generic FSK module availability */ +#define FSL_FEATURE_RADIO_HAS_GENFSK (1) +/* @brief Major version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) +/* @brief Minor version of the radio submodule */ +#define FSL_FEATURE_RADIO_VERSION_MINOR (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (0) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (0) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (0) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (0) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RSIM module features */ + +/* No feature definitions */ + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (1) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (1) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (0) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) + +/* TPM module features */ + +/* @brief Bus clock is the source clock for the module. */ +#define FSL_FEATURE_TPM_BUS_CLOCK (0) +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ + ((x) == TPM0 ? (4) : \ + ((x) == TPM1 ? (2) : \ + ((x) == TPM2 ? (2) : (-1)))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (0) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (0) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (0) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (0) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ + ((x) == TPM0 ? (0) : \ + ((x) == TPM1 ? (1) : \ + ((x) == TPM2 ? (1) : (-1)))) + +/* TRNG module features */ + +/* No feature definitions */ + +/* TSI module features */ + +/* @brief TSI module version. */ +#define FSL_FEATURE_TSI_VERSION (4) +/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ +#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) +/* @brief Number of TSI channels. */ +#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* XCVR_ANALOG module features */ + +/* No feature definitions */ + +/* XCVR_PHY module features */ + +/* No feature definitions */ + +/* ZLL module features */ + +/* No feature definitions */ + +#endif /* _MKW41Z4_FEATURES_H_ */ + diff --git a/drivers/Makefile.dep b/drivers/Makefile.dep index 23d614e08f8e..33370f107271 100644 --- a/drivers/Makefile.dep +++ b/drivers/Makefile.dep @@ -215,6 +215,16 @@ ifneq (,$(filter kw2xrf,$(USEMODULE))) FEATURES_REQUIRED += periph_gpio_irq endif +ifneq (,$(filter kw41zrf,$(USEMODULE))) + USEMODULE += luid + USEMODULE += netif + USEMODULE += ieee802154 + USEMODULE += netdev_ieee802154 + USEMODULE += core_thread_flags + USEMODULE += random + USEMODULE += mcux_xcvr_mkw41z +endif + ifneq (,$(filter l3g4200d,$(USEMODULE))) FEATURES_REQUIRED += periph_i2c endif diff --git a/drivers/Makefile.include b/drivers/Makefile.include index 3abdeb334161..9d2c9b794e63 100644 --- a/drivers/Makefile.include +++ b/drivers/Makefile.include @@ -122,6 +122,10 @@ ifneq (,$(filter kw2xrf,$(USEMODULE))) USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw2xrf/include endif +ifneq (,$(filter kw41zrf,$(USEMODULE))) + USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw41zrf/include +endif + ifneq (,$(filter l3g4200d,$(USEMODULE))) USEMODULE_INCLUDES += $(RIOTBASE)/drivers/l3g4200d/include endif diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h new file mode 100644 index 000000000000..573ed22465cc --- /dev/null +++ b/drivers/include/kw41zrf.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup drivers_kw41zrf KW41Z radio-driver + * @ingroup drivers_netdev + * @brief Device driver for the NXP KW41Z, KW21Z in-cpu transceiver + * @{ + * + * @file + * @brief Interface definition for the kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_H +#define KW41ZRF_H + +#include + +#include "mutex.h" +#include "board.h" +#include "net/netdev.h" +#include "net/netdev/ieee802154.h" +#include "net/gnrc/nettype.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Maximum packet length + */ +#define KW41ZRF_MAX_PKT_LENGTH (IEEE802154_FRAME_LEN_MAX) + +/** + * @brief Default PAN ID used after initialization + */ +#define KW41ZRF_DEFAULT_PANID (IEEE802154_DEFAULT_PANID) + +/** + * @brief Default channel used after initialization + * + * @{ + */ +#ifndef KW41ZRF_DEFAULT_CHANNEL +#define KW41ZRF_DEFAULT_CHANNEL (IEEE802154_DEFAULT_CHANNEL) +#endif +/** @} */ + +/** + * @brief Allowed range of channels + * + * @{ + */ +#define KW41ZRF_MIN_CHANNEL (11U) +#define KW41ZRF_MAX_CHANNEL (26U) +/** @} */ + +/** + * @brief Default TX_POWER in dbm used after initialization + */ +#define KW41ZRF_DEFAULT_TX_POWER (IEEE802154_DEFAULT_TXPOWER) + +/** + * @brief Maximum output power of the kw41z device in dBm + */ +#define KW41ZRF_OUTPUT_POWER_MAX (4) + +/** + * @brief Minimum output power of the kw41z device in dBm + */ +#define KW41ZRF_OUTPUT_POWER_MIN (-19) + +/** + * @brief Internal device option flags + * + * `0x00ff` is reserved for general IEEE 802.15.4 flags + * (see @ref netdev_ieee802154_t) + * + * @{ + */ +enum kw41zrf_opt { + KW41ZRF_OPT_SRC_ADDR_LONG = NETDEV_IEEE802154_SRC_MODE_LONG, /**< legacy define */ + KW41ZRF_OPT_RAWDUMP = NETDEV_IEEE802154_RAW, /**< legacy define */ + KW41ZRF_OPT_ACK_REQ = NETDEV_IEEE802154_ACK_REQ, /**< legacy define */ + + KW41ZRF_OPT_CSMA = (0x0100), /**< use CSMA/CA algorithm for sending */ + KW41ZRF_OPT_PROMISCUOUS = (0x0200), /**< promiscuous mode active */ + KW41ZRF_OPT_PRELOADING = (0x0400), /**< preloading enabled */ + KW41ZRF_OPT_TELL_TX_START = (0x0800), /**< notify MAC layer on TX start */ + KW41ZRF_OPT_TELL_TX_END = (0x1000), /**< notify MAC layer on TX finished */ + KW41ZRF_OPT_TELL_RX_START = (0x2000), /**< notify MAC layer on RX start */ + KW41ZRF_OPT_TELL_RX_END = (0x4000), /**< notify MAC layer on RX finished */ + KW41ZRF_OPT_AUTOACK = (0x8000), /**< enable automatic sending of + * ACKs for incoming packet */ +}; +/** @} */ + +/** + * @brief ISR callback function type + */ +typedef void (*kw41zrf_cb_t)(void *arg); + +/** + * @brief Device descriptor for KW41ZRF radio devices + * + * @extends netdev_ieee802154_t + */ +typedef struct { + netdev_ieee802154_t netdev; /**< netdev parent struct */ + /** + * @name device specific fields + * @{ + */ + thread_t *thread; /**< Network driver thread, for providing feedback from IRQ handler */ + uint32_t tx_warmup_time; /**< TX warmup time, in event timer ticks */ + uint32_t rx_warmup_time; /**< RX warmup time, in event timer ticks */ + uint8_t max_retrans; /**< Maximum number of frame retransmissions + * when no Ack frame is received (macMaxFrameRetries) */ + uint8_t csma_max_backoffs; /**< Maximum number of CSMA backoffs when + * waiting for channel clear (macMaxCsmaBackoffs) */ + uint8_t csma_min_be; /**< Minimum backoff exponent (macMinBe) */ + uint8_t csma_max_be; /**< Maximum backoff exponent (macMaxBe) */ + int16_t tx_power; /**< The current tx-power setting of the device */ + uint8_t idle_seq; /**< state to return to after sending */ + uint8_t cca_result; /**< Used for passing CCA result from ISR to user */ + uint8_t csma_be; /**< Counter used internally by send implementation */ + uint8_t csma_num_backoffs; /**< Counter used internally by send implementation */ + uint8_t num_retrans; /**< Counter used internally by send implementation */ + /** @} */ +} kw41zrf_t; + +/** + * @brief Setup an KW41ZRF based device state + * + * @param[out] dev device descriptor + */ +void kw41zrf_setup(kw41zrf_t *dev); + +/** + * @brief Initialize the given KW41ZRF device + * + * @param[out] dev device descriptor + * @param[in] cb irq callback + * + * @return 0 on success + * @return <0 on error + */ +int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb); + +/** + * @brief Configure radio with default values + * + * @param[in] dev device to reset + */ +void kw41zrf_reset_phy(kw41zrf_t *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_H */ +/** @} */ diff --git a/drivers/kw41zrf/Makefile b/drivers/kw41zrf/Makefile new file mode 100644 index 000000000000..4f09d6a0e290 --- /dev/null +++ b/drivers/kw41zrf/Makefile @@ -0,0 +1,4 @@ +# Use vendor-supplied low level XCVR hardware initialization +DIRS += vendor/XCVR/MKW41Z4 + +include $(RIOTBASE)/Makefile.base diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h new file mode 100644 index 000000000000..c5e84cc82174 --- /dev/null +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2017 SKF AB + * Copyright (C) 2016 Phytec Messtechnik GmbH + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief get/set interfaces for kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_GETSET_H +#define KW41ZRF_GETSET_H + +#include "kw41zrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Transceiver sequence identifiers */ +enum kw41zrf_xcvseq { + XCVSEQ_IDLE = 0b000, + XCVSEQ_RECEIVE = 0b001, + XCVSEQ_TRANSMIT = 0b010, + XCVSEQ_CCA = 0b011, + XCVSEQ_TX_RX = 0b100, + XCVSEQ_CONTINUOUS_CCA = 0b101, + /* Other values are reserved */ +}; + +/** + * @brief Set tx power of given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] txpower transmit power in dBm + */ +void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower); + +/** + * @brief Get tx power value of given device + * + * @param[in] dev kw41zrf device descriptor + * + * @return current tx power value + */ +uint16_t kw41zrf_get_txpower(kw41zrf_t *dev); + +/** + * @brief Set channel of given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] val channel + */ +int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t val); + +/** + * @brief Get channel of given device + * + * @param[in] dev kw41zrf device descriptor + * + * @return current channel + */ +uint8_t kw41zrf_get_channel(kw41zrf_t *dev); + +/** + * @brief Set PAN ID of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] pan PAN ID value + */ +void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan); + +/** + * @brief Set short address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] addr short address + */ +void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr); + +/** + * @brief Set long address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] addr long address + */ +void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr); + +/** + * @brief Get short address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current short address + */ +uint16_t kw41zrf_get_addr_short(kw41zrf_t *dev); + +/** + * @brief Get long address of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current long address + */ +uint64_t kw41zrf_get_addr_long(kw41zrf_t *dev); + +/** + * @brief Get CCA threshhold of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current CCA threshhold + */ +int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev); + +/** + * @brief Set CCA threshold of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] value CCA threshold + */ +void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value); + +/** + * @brief Set CCA mode of a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] mode CCA mode + */ +void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode); + +/** + * @brief Get CCA mode of a given device + * + * @param[in] dev kw41zrf device descriptor + * @return current CCA mode + */ +uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev); + +/** + * @brief Get latest ED measurement from the device + * + * @param[in] dev kw41zrf device descriptor + * @return most recent ED level + */ +int8_t kw41zrf_get_ed_level(kw41zrf_t *dev); + +/** + * @brief Perform one CCA measurement and return the result + * + * @param[in] dev kw41zrf device descriptor + * + * @return 0 if channel is idle + * @return 1 if channel is busy + */ +int kw41zrf_cca(kw41zrf_t *dev); + +/** + * @brief Set receive watermark + * + * @param[in] dev kw41zrf device descriptor + * @param[in] value watermark + */ +void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value); + +/** + * @brief Set netopt a given device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] option Netopt option type + * @param[in] state state + */ +void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_GETSET_H */ +/** @} */ diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h new file mode 100644 index 000000000000..d5801b56f839 --- /dev/null +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2017 SKF AB + * Copyright (C) 2016 Phytec Messtechnik GmbH + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief Internal function interfaces for kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_INTERN_H +#define KW41ZRF_INTERN_H + +#include +#include "kw41zrf.h" +/* For XCVSEQ_IDLE */ +#include "kw41zrf_getset.h" +/* For ZLL CPU registers */ +#include "cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief KW41Z transceiver power modes + */ +typedef enum { + KW41ZRF_POWER_IDLE = 0, /**< All parts powered */ + KW41ZRF_POWER_DSM, /**< Deep sleep mode */ +} kw41zrf_powermode_t; + +/** + * @brief Timebase settings + */ +typedef enum kw41zrf_timer_timebase { + KW41ZRF_TIMEBASE_500000HZ = 0b010, + KW41ZRF_TIMEBASE_250000HZ = 0b011, + KW41ZRF_TIMEBASE_125000HZ = 0b100, + KW41ZRF_TIMEBASE_62500HZ = 0b101, + KW41ZRF_TIMEBASE_31250HZ = 0b110, + KW41ZRF_TIMEBASE_15625HZ = 0b111, +} kw41zrf_timer_timebase_t; + +/** + * @brief Mask all transceiver interrupts + */ +static inline void kw41zrf_mask_irqs(void) +{ + NVIC_DisableIRQ(Radio_1_IRQn); +} + +/** + * @brief Unmask all transceiver interrupts + */ +static inline void kw41zrf_unmask_irqs(void) +{ + NVIC_EnableIRQ(Radio_1_IRQn); +} + +/** + * @brief Set the callback function for the radio ISR + * + * This callback will be called from ISR context when a radio_1 interrupt occurs + * + * @param[in] cb Pointer to callback function + * @param[in] arg Argument that will be passed to the callback + */ +void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg); + +/** + * @brief Disable all interrupts on transceiver + * + * @param[in] dev kw41zrf device descriptor + */ +void kw41zrf_disable_interrupts(kw41zrf_t *dev); + +/** + * @brief Set power mode for device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] pm power mode value + */ +void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm); + +/** + * @brief Determine if the transceiver is busy doing TX or RX + * + * @param[in] dev kw41zrf device descriptor + * + * @return 0 if transceiver is in progress transmitting a packet + * @return 1 otherwise + */ +int kw41zrf_can_switch_to_idle(kw41zrf_t *dev); + +/** + * @brief Set sequence state of device + * + * @param[in] dev kw41zrf device descriptor + * @param[in] seq sequence + */ +void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq); + +/** + * @brief Abort the current autosequence + * + * @param[in] dev kw41zrf device descriptor + */ +static inline void kw41zrf_abort_sequence(kw41zrf_t *dev) +{ + /* Writing IDLE to XCVSEQ aborts any ongoing sequence */ + ZLL->PHY_CTRL = (ZLL->PHY_CTRL & + ~(ZLL_PHY_CTRL_XCVSEQ_MASK | + ZLL_PHY_CTRL_TC3TMOUT_MASK | ZLL_PHY_CTRL_TMRTRIGEN_MASK)) | + ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE) | ZLL_PHY_CTRL_SEQMSK_MASK; + /* Spin until the sequence manager has acknowledged the sequence abort, this + * should not take many cycles */ + while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> + ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != XCVSEQ_IDLE) {} + + /* Clear interrupt flags */ + ZLL->IRQSTS = ZLL->IRQSTS; +} + +/** + * @brief Set event timer counter value + * + * @param[in] dev kw41zrf device descriptor + * @param[in] value new time + */ +static inline void kw41zrf_timer_load(kw41zrf_t *dev, uint32_t value) +{ + (void) dev; + ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR(value) | ZLL_EVENT_TMR_EVENT_TMR_LD_MASK; +} + +/** + * @brief Get current event timer counter value + * + * @param[in] dev kw41zrf device descriptor + * + * @return Current timer value + */ +static inline uint32_t kw41zrf_timer_get(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->EVENT_TMR & ZLL_EVENT_TMR_EVENT_TMR_MASK) >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT; +} + +/** + * @brief Set a timeout value for the given compare register of the Event Timer + * + * @param[in] dev kw41zrf device descriptor + * @param[out] cmp_reg pointer to timer compare register, &ZLL->TxCMP + * @param[in] timeout timer offset from current time + */ +static inline void kw41zrf_timer_set(kw41zrf_t *dev, volatile uint32_t *cmp_reg, uint32_t timeout) +{ + uint32_t now = kw41zrf_timer_get(dev); + + *cmp_reg = now + timeout; +} + +/** + * @brief Initialize the Event Timer Block (up counter) + * + * The Event Timer Block provides: + * - Abort an RX and CCA sequence at pre-determined time + * - Latches "timestamp" value during packet reception + * - Initiates timer-triggered sequences + * + * @param[in] dev kw41zrf device descriptor + * @param[in] tb timer base value + */ +static inline void kw41zrf_timer_init(kw41zrf_t *dev, kw41zrf_timer_timebase_t tb) +{ + ZLL->TMR_PRESCALE = (ZLL->TMR_PRESCALE & ~ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK) | + ZLL_TMR_PRESCALE_TMR_PRESCALE(tb); + kw41zrf_timer_load(dev, 0); +} + +/** + * @brief Returns timestamp of the beginning of the most recently received packet + * + * The latched timestamp corresponds to the point where the SFD detection was + * triggered for the most recent packet, i.e. right before the first byte of the + * packet. + * + * @param[in] dev kw41zrf device descriptor + * + * @return timestamp value + */ +static inline uint32_t kw41zrf_get_timestamp(kw41zrf_t *dev) +{ + return ZLL->TIMESTAMP; +} + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_INTERN_H */ +/** @} */ diff --git a/drivers/kw41zrf/include/kw41zrf_netdev.h b/drivers/kw41zrf/include/kw41zrf_netdev.h new file mode 100644 index 000000000000..59af06d740d1 --- /dev/null +++ b/drivers/kw41zrf/include/kw41zrf_netdev.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief Netdev interface for kw41zrf driver + * + * @author Joakim Nohlgård + */ + +#ifndef KW41ZRF_NETDEV_H +#define KW41ZRF_NETDEV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reference to the netdev device driver struct + */ +extern const netdev_driver_t kw41zrf_driver; + +#ifdef __cplusplus +} +#endif + +#endif /* KW41ZRF_NETDEV_H */ +/** @} */ diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c new file mode 100644 index 000000000000..42e37a9e8cb2 --- /dev/null +++ b/drivers/kw41zrf/kw41zrf.c @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief Basic functionality of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ +#include +#include + +#include "log.h" +#include "msg.h" +#include "net/gnrc.h" +#include "net/ieee802154.h" +#include "luid.h" + +#include "kw41zrf.h" +#include "kw41zrf_netdev.h" +#include "kw41zrf_getset.h" +#include "kw41zrf_intern.h" +#include "vendor/XCVR/MKW41Z4/fsl_xcvr.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +enum { + KW41Z_CCA_ED, + KW41Z_CCA_MODE1, + KW41Z_CCA_MODE2, + KW41Z_CCA_MODE3 +}; + +enum { + KW41Z_STATE_IDLE, + KW41Z_STATE_RX, + KW41Z_STATE_TX, + KW41Z_STATE_CCA, + KW41Z_STATE_TXRX, + KW41Z_STATE_CCCA +}; + +static void kw41zrf_set_address(kw41zrf_t *dev) +{ + DEBUG("[kw41zrf] Set MAC address\n"); + eui64_t addr_long; + /* get an 8-byte unique ID to use as hardware address */ + luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN); + /* make sure we mark the address as non-multicast and not globally unique */ + addr_long.uint8[0] &= ~(0x01); + addr_long.uint8[0] |= (0x02); + /* set short and long address */ + kw41zrf_set_addr_long(dev, ntohll(addr_long.uint64.u64)); + kw41zrf_set_addr_short(dev, ntohs(addr_long.uint16[0].u16)); +} + +void kw41zrf_setup(kw41zrf_t *dev) +{ + netdev_t *netdev = (netdev_t *)dev; + + netdev->driver = &kw41zrf_driver; + /* initialize device descriptor */ + dev->idle_seq = XCVSEQ_RECEIVE; + /* Set default parameters according to STD IEEE802.15.4-2015 */ + dev->csma_max_be = 5; + dev->csma_min_be = 3; + dev->max_retrans = 3; + dev->csma_max_backoffs = 4; + +// kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + DEBUG("[kw41zrf] setup finished\n"); +} + +int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) +{ + if (dev == NULL) { + return -ENODEV; + } + + /* Enable RSIM oscillator in Run mode, in order to be able to access the XCVR + * registers if using the internal reference clock for the CPU core */ + bit_set32(&RSIM->CONTROL, RSIM_CONTROL_RF_OSC_EN_SHIFT); + + /* Wait for oscillator ready signal */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + + xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); + if (xcvrStatus != gXcvrSuccess_c) { + return -EIO; + } + + /* Software reset of most settings */ + kw41zrf_reset_phy(dev); + + /* Compute warmup times (scaled to 16us) */ + dev->rx_warmup_time = + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + dev->tx_warmup_time = + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + + /* divide by 16 and round up */ + dev->rx_warmup_time = (dev->rx_warmup_time + 15) / 16; + dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16; + + /* Configre Radio IRQ */ + kw41zrf_set_irq_callback(cb, dev); + NVIC_ClearPendingIRQ(Radio_1_IRQn); + NVIC_EnableIRQ(Radio_1_IRQn); + + kw41zrf_abort_sequence(dev); + kw41zrf_unmask_irqs(); + + DEBUG("[kw41zrf] init finished\n"); + + return 0; +} + +void kw41zrf_reset_phy(kw41zrf_t *dev) +{ + /* reset options and sequence number */ + dev->netdev.seq = 0; + dev->netdev.flags = 0; + + /* set default protocol */ +#ifdef MODULE_GNRC_SIXLOWPAN + dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN; +#elif MODULE_GNRC + dev->netdev.proto = GNRC_NETTYPE_UNDEF; +#endif + + /* Configure DSM exit oscillator stabilization delay */ + uint32_t tmp = (RSIM->RF_OSC_CTRL & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK) >> + RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT; + /* Stabilization time is 1024 * 2^x radio crystal clocks, 0 <= x <= 3 */ + RSIM->DSM_OSC_OFFSET = (1024ul << tmp) / (CLOCK_RADIOXTAL / 32768) + 1; /* round up */ + + /* Bring the device out of low power mode */ + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + + /* Reset PHY_CTRL to the default value of mask all interrupts and all other + * settings disabled */ + ZLL->PHY_CTRL = + ZLL_PHY_CTRL_CCATYPE(1) | + ZLL_PHY_CTRL_TSM_MSK_MASK | + ZLL_PHY_CTRL_WAKE_MSK_MASK | + ZLL_PHY_CTRL_CRC_MSK_MASK | + ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | + ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK | + ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | + ZLL_PHY_CTRL_CCAMSK_MASK | + ZLL_PHY_CTRL_RXMSK_MASK | + ZLL_PHY_CTRL_TXMSK_MASK | + ZLL_PHY_CTRL_SEQMSK_MASK | + ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE); + + /* Clear and disable all interrupts */ + kw41zrf_disable_interrupts(dev); + + /* Clear source address cache */ + ZLL->SAM_TABLE |= ZLL_SAM_TABLE_INVALIDATE_ALL_MASK; + + /* Accept FrameVersion 0 and 1 packets, reject all others */ + ZLL->RX_FRAME_FILTER = ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3) | + ZLL_RX_FRAME_FILTER_ACK_FT_MASK | + ZLL_RX_FRAME_FILTER_DATA_FT_MASK; + + /* Set prescaler to obtain 1 symbol (16us) timebase */ + kw41zrf_timer_init(dev, KW41ZRF_TIMEBASE_62500HZ); + + /* Set CCA threshold to -75 dBm */ + ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | + ZLL_CCA_LQI_CTRL_CCA1_THRESH(0xB5); + + /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */ + ZLL->ACKDELAY = (ZLL->ACKDELAY & ~ZLL_ACKDELAY_ACKDELAY_MASK) | ZLL_ACKDELAY_ACKDELAY(-8); + + /* Adjust LQI compensation */ + /* Hardware reset default is 102 */ + ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) | + ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(96); + + /* set defaults */ + ZLL->SEQ_CTRL_STS = ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK; + + dev->tx_power = KW41ZRF_DEFAULT_TX_POWER; + kw41zrf_set_tx_power(dev, dev->tx_power); + + kw41zrf_set_channel(dev, KW41ZRF_DEFAULT_CHANNEL); + + kw41zrf_set_pan(dev, KW41ZRF_DEFAULT_PANID); + kw41zrf_set_address(dev); + + kw41zrf_set_cca_mode(dev, 1); + + kw41zrf_set_rx_watermark(dev, 1); + + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, true); + + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + kw41zrf_set_sequence(dev, dev->idle_seq); + + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, true); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_SEQMSK_SHIFT); + + DEBUG("[kw41zrf] reset PHY and (re)set to channel %d and pan %d.\n", + KW41ZRF_DEFAULT_CHANNEL, KW41ZRF_DEFAULT_PANID); +} diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c new file mode 100644 index 000000000000..a56cc2fd4d56 --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief get/set functionality of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ + +#include +#include "log.h" +#include "cpu.h" +#include "byteorder.h" +#include "kw41zrf.h" +#include "kw41zrf_intern.h" +#include "kw41zrf_getset.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +#define KW41ZRF_NUM_CHANNEL (KW41ZRF_MAX_CHANNEL - KW41ZRF_MIN_CHANNEL + 1) + +/* Lookup table for PA_PWR register */ +/* Source: KW41Z data sheet, 5.3 Transmit and PLL Feature Summary, + * Table 8. Transmit Output Power as a function of PA_POWER[5:0] */ +static const uint8_t tx_power_dbm_to_pa_pwr[29] = { + 4, 4, 4, 4, /* -19:-16 dBm */ + 6, 6, /* -15:-14 dBm */ + 8, 8, /* -13:-12 dBm */ + 10, 10, /* -11:-10 dBm */ + 12, /* -9 dBm */ + 14, /* -8 dBm */ + 16, /* -7 dBm */ + 18, /* -6 dBm */ + 20, /* -5 dBm */ + 22, /* -4 dBm */ + 26, /* -3 dBm */ + 28, /* -2 dBm */ + 34, /* -1 dBm */ + 38, /* 0 dBm */ + 42, /* 1 dBm */ + 48, /* 2 dBm */ + 56, /* 3 dBm */ + 62, /* 4 dBm */ +}; + +void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower_dbm) +{ + if (txpower_dbm < KW41ZRF_OUTPUT_POWER_MIN) { + ZLL->PA_PWR = 1; + } + else if (txpower_dbm > KW41ZRF_OUTPUT_POWER_MAX) { + ZLL->PA_PWR = 62; + } + else { + ZLL->PA_PWR = tx_power_dbm_to_pa_pwr[txpower_dbm - KW41ZRF_OUTPUT_POWER_MIN]; + } + + LOG_DEBUG("[kw41zrf] set txpower to: %d\n", txpower_dbm); + dev->tx_power = txpower_dbm; +} + +uint16_t kw41zrf_get_txpower(kw41zrf_t *dev) +{ + return dev->tx_power; +} + +uint8_t kw41zrf_get_channel(kw41zrf_t *dev) +{ + return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK); +} + +int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel) +{ + if (channel < KW41ZRF_MIN_CHANNEL || channel > KW41ZRF_MAX_CHANNEL) { + LOG_ERROR("[kw41zrf] Invalid channel %u\n", channel); + return -EINVAL; + } + + ZLL->CHANNEL_NUM0 = channel; + dev->netdev.chan = channel; + + LOG_DEBUG("[kw41zrf] set channel to %u\n", channel); + return 0; +} + +void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan) +{ + dev->netdev.pan = pan; + + ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACPANID0_MASK) | + ZLL_MACSHORTADDRS0_MACPANID0(pan); + + LOG_DEBUG("[kw41zrf] set pan to: 0x%x\n", pan); + dev->netdev.pan = pan; +} + +void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr) +{ +#ifdef MODULE_SIXLOWPAN + /* https://tools.ietf.org/html/rfc4944#section-12 requires the first bit to + * 0 for unicast addresses */ + addr &= 0x7fff; +#endif + /* Network byte order */ + /* TODO use byteorder.h */ + dev->netdev.short_addr[0] = (addr & 0xff); + dev->netdev.short_addr[1] = (addr >> 8); + ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) | + ZLL_MACSHORTADDRS0_MACSHORTADDRS0(addr); +} + +void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr) +{ + (void) dev; + for (unsigned i = 0; i < IEEE802154_LONG_ADDRESS_LEN; i++) { + dev->netdev.long_addr[i] = (uint8_t)(addr >> (i * 8)); + } + /* Network byte order */ + addr = byteorder_swapll(addr); + ZLL->MACLONGADDRS0_LSB = (uint32_t)addr; + ZLL->MACLONGADDRS0_MSB = (addr >> 32); +} + +uint16_t kw41zrf_get_addr_short(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->MACSHORTADDRS0 & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) >> + ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT; +} + +uint64_t kw41zrf_get_addr_long(kw41zrf_t *dev) +{ + (void) dev; + uint64_t addr = ((uint64_t)ZLL->MACLONGADDRS0_MSB << 32) | ZLL->MACLONGADDRS0_LSB; + /* Network byte order */ + addr = byteorder_swapll(addr); + + return addr; +} + +int8_t kw41zrf_get_cca_threshold(kw41zrf_t *dev) +{ + (void) dev; + uint8_t tmp = (ZLL->CCA_LQI_CTRL & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) >> + ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT; + return (int8_t)tmp; +} + +void kw41zrf_set_cca_threshold(kw41zrf_t *dev, int8_t value) +{ + (void) dev; + ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | + ZLL_CCA_LQI_CTRL_CCA1_THRESH(value); +} + +void kw41zrf_set_cca_mode(kw41zrf_t *dev, uint8_t mode) +{ + (void) dev; + ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) | + ZLL_PHY_CTRL_CCATYPE(mode); +} + +uint8_t kw41zrf_get_cca_mode(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCATYPE_MASK) >> ZLL_PHY_CTRL_CCATYPE_SHIFT; +} + +int8_t kw41zrf_get_ed_level(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT; +} + +void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) +{ + DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state); + + /* set option field */ + if (state) { + dev->netdev.flags |= option; + + /* trigger option specific actions */ + switch (option) { + case KW41ZRF_OPT_CSMA: + LOG_DEBUG("[kw41zrf] enable: CSMA\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT); + break; + + case KW41ZRF_OPT_PROMISCUOUS: + LOG_DEBUG("[kw41zrf] enable: PROMISCUOUS\n"); + /* enable promiscuous mode */ + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT); + /* auto ACK is always disabled in promiscuous mode by the hardware */ + break; + + case KW41ZRF_OPT_AUTOACK: + LOG_DEBUG("[kw41zrf] enable: AUTOACK\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT); + break; + + case KW41ZRF_OPT_ACK_REQ: + LOG_DEBUG("[kw41zrf] enable: ACK_REQ\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_START: + LOG_DEBUG("[kw41zrf] enable: TELL_RX_START\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_END: + LOG_DEBUG("[kw41zrf] enable: TELL_RX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_END: + LOG_DEBUG("[kw41zrf] enable: TELL_TX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_START: + LOG_DEBUG("[kw41zrf] enable: TELL_TX_START (ignored)\n"); + default: + /* do nothing */ + break; + } + } + else { + dev->netdev.flags &= ~(option); + /* trigger option specific actions */ + switch (option) { + case KW41ZRF_OPT_CSMA: + LOG_DEBUG("[kw41zrf] disable: CSMA\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_CCABFRTX_SHIFT); + break; + + case KW41ZRF_OPT_PROMISCUOUS: + LOG_DEBUG("[kw41zrf] disable: PROMISCUOUS\n"); + /* disable promiscuous mode */ + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_PROMISCUOUS_SHIFT); + break; + + case KW41ZRF_OPT_AUTOACK: + LOG_DEBUG("[kw41zrf] disable: AUTOACK\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT); + break; + + case KW41ZRF_OPT_ACK_REQ: + LOG_DEBUG("[kw41zrf] disable: ACK_REQ\n"); + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_START: + LOG_DEBUG("[kw41zrf] disable: TELL_RX_START\n"); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT); + break; + + case KW41ZRF_OPT_TELL_RX_END: + LOG_DEBUG("[kw41zrf] disable: TELL_RX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_END: + LOG_DEBUG("[kw41zrf] disable: TELL_TX_END\n"); + break; + + case KW41ZRF_OPT_TELL_TX_START: + LOG_DEBUG("[kw41zrf] disable: TELL_TX_START (ignored)\n"); + default: + /* do nothing */ + break; + } + } +} + +void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value) +{ + ZLL->RX_WTR_MARK = ZLL_RX_WTR_MARK_RX_WTR_MARK(value); +} diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c new file mode 100644 index 000000000000..3de296d23add --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief Internal function of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ + +#include "irq.h" +#include "panic.h" +#include "kw41zrf.h" +#include "kw41zrf_getset.h" +#include "kw41zrf_intern.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +/** + * @brief Delay before entering deep sleep mode, in DSM_TIMER ticks (32.768 kHz) + * + * @attention must be >= 4 according to SoC ref. manual + */ +#define KW41ZRF_DSM_ENTER_DELAY 5 + +/** + * @brief Delay before leaving deep sleep mode, in DSM_TIMER ticks (32.768 kHz) + * + * @attention must be >= 4 according to SoC ref. manual + */ +#define KW41ZRF_DSM_EXIT_DELAY 5 + +struct { + void (*cb)(void *arg); /**< Callback function called from radio ISR */ + void *arg; /**< Argument to callback */ +} isr_config; + +void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg) +{ + unsigned int mask = irq_disable(); + isr_config.cb = cb; + isr_config.arg = arg; + irq_restore(mask); +} + +void kw41zrf_disable_interrupts(kw41zrf_t *dev) +{ + DEBUG("[kw41zrf] disable interrupts\n"); + /* Clear and disable all interrupts */ + ZLL->PHY_CTRL |= + ZLL_PHY_CTRL_TSM_MSK_MASK | + ZLL_PHY_CTRL_WAKE_MSK_MASK | + ZLL_PHY_CTRL_CRC_MSK_MASK | + ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | + ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK | + ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | + ZLL_PHY_CTRL_CCAMSK_MASK | + ZLL_PHY_CTRL_RXMSK_MASK | + ZLL_PHY_CTRL_TXMSK_MASK | + ZLL_PHY_CTRL_SEQMSK_MASK; + + /* Mask all timer interrupts and clear all interrupt flags */ + ZLL->IRQSTS = + ZLL_IRQSTS_TMR1MSK_MASK | + ZLL_IRQSTS_TMR2MSK_MASK | + ZLL_IRQSTS_TMR3MSK_MASK | + ZLL_IRQSTS_TMR4MSK_MASK | + ZLL_IRQSTS_TMR1IRQ_MASK | + ZLL_IRQSTS_TMR2IRQ_MASK | + ZLL_IRQSTS_TMR3IRQ_MASK | + ZLL_IRQSTS_TMR4IRQ_MASK | + ZLL_IRQSTS_WAKE_IRQ_MASK | + ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | + ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | + ZLL_IRQSTS_RXWTRMRKIRQ_MASK | + ZLL_IRQSTS_CCAIRQ_MASK | + ZLL_IRQSTS_RXIRQ_MASK | + ZLL_IRQSTS_TXIRQ_MASK | + ZLL_IRQSTS_SEQIRQ_MASK; +} + +void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) +{ + DEBUG("[kw41zrf] set power mode to %u\n", pm); + unsigned state = irq_disable(); + switch (pm) { + case KW41ZRF_POWER_IDLE: + { + if (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) { + /* Already awake */ + break; + } + /* Assume DSM timer has been running since we entered sleep mode */ + /* In case it was not already running, however, we still set the + * enable flag here. */ + RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK | + RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK); + /* The wake target must be at least (4 + RSIM_DSM_OSC_OFFSET) ticks + * into the future, to let the oscillator stabilize before switching + * on the clocks */ + RSIM->ZIG_WAKE = KW41ZRF_DSM_EXIT_DELAY + RSIM->DSM_TIMER + RSIM->DSM_OSC_OFFSET; + while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) {} + /* Convert DSM ticks (32.768 kHz) to event timer ticks (1 MHz) */ + uint64_t tmp = (uint64_t)(RSIM->ZIG_WAKE - RSIM->ZIG_SLEEP) * 15625ul; + uint32_t usec = (tmp >> 9); /* equivalent to (usec / 512) */ + ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK | + ZLL_EVENT_TMR_EVENT_TMR(usec); + break; + } + case KW41ZRF_POWER_DSM: + { + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Already asleep */ + break; + } + /* Clear IRQ flags */ + RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; + /* Enable timer triggered sleep */ + ZLL->DSM_CTRL = ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; + /* Set sleep start time */ + /* The target time must be at least 4 DSM_TIMER ticks into the future */ + RSIM->ZIG_SLEEP = RSIM->DSM_TIMER + KW41ZRF_DSM_ENTER_DELAY; + /* The device will automatically wake up 8.5 minutes from now if not + * awoken sooner by software */ + /* TODO handle automatic wake in the ISR if it becomes an issue */ + RSIM->ZIG_WAKE = RSIM->DSM_TIMER - 1; + /* Start the 32.768 kHz DSM timer in case it was not already running */ + /* If ZIG_SYSCLK_REQUEST_EN is not set then the hardware will not + * enter DSM and we get stuck in the while() below */ + RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK | + RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK); + while (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) {} + /* Let the DSM timer run until we exit deep sleep mode */ + break; + } + default: + DEBUG("[kw41zrf] Unknown power mode %u\n", pm); + break; + } + irq_restore(state); +} + +void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) +{ + DEBUG("[kw41zrf] set sequence to %u\n", (unsigned int)seq); + assert((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) == XCVSEQ_IDLE); + while ((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) == 0) { + kw41zrf_abort_sequence(dev); + } + /* Clear interrupt flags, sometimes the sequence complete flag is immediately set */ + ZLL->IRQSTS = ZLL->IRQSTS; + ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | ZLL_PHY_CTRL_SEQMSK_MASK)) | seq; + while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> + ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != (ZLL_PHY_CTRL_XCVSEQ_MASK & seq)) {} +} + +int kw41zrf_can_switch_to_idle(kw41zrf_t *dev) +{ + uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + + DEBUG("[kw41zrf] XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 ", SEQ_CTRL_STS=0x%" PRIx32 "\n", seq, + ZLL->SEQ_STATE, ZLL->SEQ_CTRL_STS); + + switch (seq) + { + case XCVSEQ_TRANSMIT: + case XCVSEQ_TX_RX: + case XCVSEQ_CCA: + /* We should wait until TX or CCA has finished before moving to + * another mode */ + return 0; + default: + break; + } + + return 1; +} + +void isr_radio_1(void) +{ + DEBUG("[kw41zrf] INT1\n"); + if (isr_config.cb != NULL) { + isr_config.cb(isr_config.arg); + } + cortexm_isr_end(); +} diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c new file mode 100644 index 000000000000..642603e96ba5 --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -0,0 +1,1102 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * + * @file + * @brief Netdev interface for kw41zrf drivers + * + * @author Joakim Nohlgård + */ + +#include +#include +#include +#include + +#include "log.h" +#include "random.h" +#include "thread_flags.h" +#include "net/eui64.h" +#include "net/ieee802154.h" +#include "net/netdev.h" +#include "net/netdev/ieee802154.h" + +#include "kw41zrf.h" +#include "kw41zrf_netdev.h" +#include "kw41zrf_intern.h" +#include "kw41zrf_getset.h" + +#if MODULE_OD +#include "od.h" +#endif + +#define ENABLE_DEBUG (0) +#include "debug.h" + +#define _MAX_MHR_OVERHEAD (25) + +/* Timing */ +#define KW41ZRF_CCA_TIME 8 +#define KW41ZRF_SHR_PHY_TIME 12 +#define KW41ZRF_PER_BYTE_TIME 2 +#define KW41ZRF_ACK_WAIT_TIME 54 +#define KW41ZRF_CSMA_UNIT_TIME 20 + +static void kw41zrf_netdev_isr(netdev_t *netdev); + +static volatile unsigned int num_irqs_queued = 0; +static volatile unsigned int num_irqs_handled = 0; +static unsigned int spinning_for_irq = 0; + +/* Set this to a flag bit that is not used by the MAC implementation */ +#define KW41ZRF_THREAD_FLAG_ISR (1 << 8) + +static void kw41zrf_irq_handler(void *arg) +{ + netdev_t *netdev = arg; + kw41zrf_t *dev = (kw41zrf_t *)netdev; + + kw41zrf_mask_irqs(); + /* Signal to the thread that an IRQ has arrived, if it is waiting */ + thread_flags_set(dev->thread, KW41ZRF_THREAD_FLAG_ISR); + + /* We use this counter to avoid filling the message queue with redundant ISR events */ + if (num_irqs_queued == num_irqs_handled) { + ++num_irqs_queued; + if (netdev->event_callback) { + netdev->event_callback(netdev, NETDEV_EVENT_ISR); + } + } +} + +static int kw41zrf_netdev_init(netdev_t *netdev) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + dev->thread = (thread_t *)thread_get(thread_getpid()); + + /* initialise SPI and GPIOs */ + if (kw41zrf_init(dev, kw41zrf_irq_handler)) { + LOG_ERROR("[kw41zrf] unable to initialize device\n"); + return -1; + } + +#ifdef MODULE_NETSTATS_L2 + memset(&netdev->stats, 0, sizeof(netstats_t)); +#endif + + /* reset device to default values and put it into RX state */ + kw41zrf_reset_phy(dev); + + return 0; +} + +/** + * @brief Generate a random number for using as a CSMA delay value + */ +static inline uint32_t kw41zrf_csma_random_delay(kw41zrf_t *dev) +{ + /* Use topmost csma_be bits of the random number */ + uint32_t rnd = random_uint32() >> (32 - dev->csma_be); + return (rnd * KW41ZRF_CSMA_UNIT_TIME); +} + +static inline size_t kw41zrf_tx_load(const void *buf, size_t len, size_t offset) +{ + /* Array bounds are checked in the kw41zrf_netdev_send loop */ + /* offset + 1 is used because buf[0] contains the frame length byte */ + memcpy(((uint8_t *)&ZLL->PKT_BUFFER_TX[0]) + offset + 1, buf, len); + return offset + len; +} + +static void kw41zrf_tx_exec(kw41zrf_t *dev) +{ + kw41zrf_abort_sequence(dev); + uint16_t len_fcf = ZLL->PKT_BUFFER_TX[0]; + DEBUG("[kw41zrf] len_fcf=0x%04x\n", len_fcf); + /* Check FCF field in the TX buffer to see if the ACK_REQ flag was set in + * the packet that is queued for transmission */ + uint8_t fcf = (len_fcf >> 8) & 0xff; + uint32_t backoff_delay; + if (dev->netdev.flags & KW41ZRF_OPT_CSMA) { + /* Use CSMA/CA random delay in the interval [0, 2**dev->csma_be) */ + backoff_delay = kw41zrf_csma_random_delay(dev); + } + else { + /* No CSMA */ + backoff_delay = 0; + } + if ((dev->netdev.flags & KW41ZRF_OPT_ACK_REQ) && + (fcf & IEEE802154_FCF_ACK_REQ)) { + uint8_t payload_len = len_fcf & 0xff; + uint32_t tx_timeout = backoff_delay + dev->tx_warmup_time + + KW41ZRF_SHR_PHY_TIME + payload_len * KW41ZRF_PER_BYTE_TIME + + KW41ZRF_ACK_WAIT_TIME; + DEBUG("[kw41zrf] Start TR\n"); + /* This is quite timing sensitive, as interrupts may lead to delays + * causing the timeout or trigger timers to expire before we have had a + * chance to write the new autosequence to the PHY_CTRL register. */ + unsigned mask = irq_disable(); + if (backoff_delay > 0) { + /* Avoid risk of setting a timer in the past */ + /* Set trigger time for CSMA */ + kw41zrf_timer_set(dev, &ZLL->T2CMP, backoff_delay); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); + } + /* Set timeout for RX ACK */ + kw41zrf_timer_set(dev, &ZLL->T3CMP, tx_timeout); + /* Initiate transmission, with timeout */ + kw41zrf_set_sequence(dev, XCVSEQ_TX_RX | ZLL_PHY_CTRL_TC3TMOUT_MASK); + irq_restore(mask); + } + else { + DEBUG("[kw41zrf] Start T\n"); + unsigned mask = irq_disable(); + if (backoff_delay > 0) { + /* Avoid risk of setting a timer in the past */ + /* Set trigger time for CSMA */ + kw41zrf_timer_set(dev, &ZLL->T2CMP, backoff_delay); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); + } + /* Initiate transmission */ + kw41zrf_set_sequence(dev, XCVSEQ_TRANSMIT); + irq_restore(mask); + } +} + +/** + * @brief Block the current thread until the radio is idle + * + * Any ongoing TX or CCA sequence will have finished when this function returns. + * + * @param[in] dev kw41zrf device descriptor + */ +static void kw41zrf_wait_idle(kw41zrf_t *dev) +{ + /* make sure any ongoing T or TR sequence is finished */ + if (kw41zrf_can_switch_to_idle(dev) == 0) { + DEBUG("[kw41zrf] TX already in progress\n"); + num_irqs_handled = num_irqs_queued; + spinning_for_irq = 1; + thread_flags_clear(KW41ZRF_THREAD_FLAG_ISR); + while (1) { + /* TX in progress */ + /* Handle any outstanding IRQ first */ + kw41zrf_netdev_isr((netdev_t *)dev); + /* kw41zrf_netdev_isr() will switch the transceiver back to idle after + * handling the TX complete IRQ */ + if (kw41zrf_can_switch_to_idle(dev)) { + break; + } + /* Block until we get another IRQ */ + thread_flags_wait_any(KW41ZRF_THREAD_FLAG_ISR); + DEBUG("[kw41zrf] waited ISR\n"); + } + spinning_for_irq = 0; + DEBUG("[kw41zrf] previous TX done\n"); + } +} + +int kw41zrf_cca(kw41zrf_t *dev) +{ + kw41zrf_wait_idle(dev); + kw41zrf_abort_sequence(dev); + kw41zrf_unmask_irqs(); + kw41zrf_set_sequence(dev, XCVSEQ_CCA); + /* Wait for the CCA to finish, it will take exactly RX warmup time + 128 µs */ + kw41zrf_wait_idle(dev); + DEBUG("[kw41zrf] CCA: %u RSSI: %d\n", (unsigned)dev->cca_result, + kw41zrf_get_ed_level(dev)); + return dev->cca_result; +} + +static int kw41zrf_netdev_send(netdev_t *netdev, const iolist_t *iolist) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + size_t len = 0; + + kw41zrf_wait_idle(dev); + + /* load packet data into buffer */ + for (const iolist_t *iol = iolist; iol; iol = iol->iol_next) { + /* current packet data + FCS too long */ + if ((len + iol->iol_len) > (KW41ZRF_MAX_PKT_LENGTH - IEEE802154_FCS_LEN)) { + LOG_ERROR("[kw41zrf] packet too large (%u byte) to fit\n", + (unsigned)len + IEEE802154_FCS_LEN); + return -EOVERFLOW; + } + len = kw41zrf_tx_load(iol->iol_base, iol->iol_len, len); + } + + DEBUG("[kw41zrf] TX %u bytes\n", len); + + /* + * First octet in the TX buffer contains the frame length. + * Nbytes = FRAME_LEN - 2 -> FRAME_LEN = Nbytes + 2 + * MKW41Z ref. man. 44.6.2.6.3.1.3 Sequence T (Transmit), p. 2147 + */ + *((volatile uint8_t *)&ZLL->PKT_BUFFER_TX[0]) = len + IEEE802154_FCS_LEN; +#if defined(MODULE_OD) && ENABLE_DEBUG + DEBUG("[kw41zrf] send:\n"); + od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_TX, len, OD_WIDTH_DEFAULT); +#endif + +#ifdef MODULE_NETSTATS_L2 + netdev->stats.tx_bytes += len; +#endif + + /* send data out directly if pre-loading is disabled */ + if (!(dev->netdev.flags & KW41ZRF_OPT_PRELOADING)) { + dev->csma_be = dev->csma_min_be; + dev->csma_num_backoffs = 0; + dev->num_retrans = 0; + kw41zrf_tx_exec(dev); + } + + return (int)len; +} + +static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *info) +{ + /* get size of the received packet */ + uint8_t pkt_len = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; + kw41zrf_t *dev = (kw41zrf_t *)netdev; + if (pkt_len < IEEE802154_FCS_LEN) { + return -EAGAIN; + } + /* skip FCS */ + pkt_len -= IEEE802154_FCS_LEN; + DEBUG("[kw41zrf] RX %u bytes\n", pkt_len); + + /* just return length when buf == NULL */ + if (buf == NULL) { + if (len > 0) { + /* discard what we have stored in the buffer, go back to RX mode */ + dev->idle_seq = XCVSEQ_RECEIVE; + if (kw41zrf_can_switch_to_idle(dev)) { + kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); + } + } + return pkt_len; + } + +#if defined(MODULE_OD) && ENABLE_DEBUG + DEBUG("[kw41zrf] recv:\n"); + od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_RX, pkt_len, OD_WIDTH_DEFAULT); +#endif + +#ifdef MODULE_NETSTATS_L2 + netdev->stats.rx_count++; + netdev->stats.rx_bytes += pkt_len; +#else + (void)netdev; +#endif + + if (pkt_len > len) { + /* not enough space in buf */ + return -ENOBUFS; + } + memcpy(buf, (const void *)&ZLL->PKT_BUFFER_RX[0], pkt_len); + + if (info != NULL) { + netdev_ieee802154_rx_info_t *radio_info = info; + uint8_t hw_lqi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >> + ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT; + /* TODO Validate, verify or adjust this LQI calculation */ + if (hw_lqi >= 220) { + radio_info->lqi = 255; + } else { + radio_info->lqi = (51 * hw_lqi) / 44; + } + radio_info->rssi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_RSSI_MASK) >> ZLL_LQI_AND_RSSI_RSSI_SHIFT; + } + + /* Go back to RX mode */ + dev->idle_seq = XCVSEQ_RECEIVE; + if (kw41zrf_can_switch_to_idle(dev)) { + kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); + } + + return pkt_len; +} + +static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) +{ + switch (state) { + case NETOPT_STATE_OFF: + /* There is no deeper 'off' mode than deep sleep mode */ + /* fall through */ + case NETOPT_STATE_SLEEP: + kw41zrf_abort_sequence(dev); + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); + break; + case NETOPT_STATE_STANDBY: + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + kw41zrf_abort_sequence(dev); + dev->idle_seq = XCVSEQ_IDLE; + kw41zrf_set_sequence(dev, dev->idle_seq); + break; + case NETOPT_STATE_IDLE: + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + kw41zrf_abort_sequence(dev); + dev->idle_seq = XCVSEQ_RECEIVE; + kw41zrf_set_sequence(dev, dev->idle_seq); + break; + case NETOPT_STATE_TX: + if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { + kw41zrf_wait_idle(dev); + dev->csma_be = dev->csma_min_be; + dev->csma_num_backoffs = 0; + dev->num_retrans = 0; + kw41zrf_tx_exec(dev); + } + break; + case NETOPT_STATE_RESET: + kw41zrf_reset_phy(dev); + break; + default: + return -ENOTSUP; + } + return sizeof(netopt_state_t); +} + +static netopt_state_t kw41zrf_netdev_get_state(kw41zrf_t *dev) +{ + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + return NETOPT_STATE_SLEEP; + } + uint32_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + + switch (seq) { + case XCVSEQ_TRANSMIT: + case XCVSEQ_TX_RX: + return NETOPT_STATE_TX; + case XCVSEQ_CCA: + case XCVSEQ_CONTINUOUS_CCA: + return NETOPT_STATE_RX; + case XCVSEQ_RECEIVE: + { + uint32_t seq_state = ZLL->SEQ_STATE; + if (seq_state & ZLL_SEQ_STATE_SFD_DET_MASK) { + if (seq_state & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK) { + return NETOPT_STATE_RX; + } + } + /* IDLE in netopt means on, and listening for incoming packets */ + return NETOPT_STATE_IDLE; + } + case XCVSEQ_IDLE: + /* SEQ_IDLE in kw41z means on, but not listening for incoming traffic */ + return NETOPT_STATE_STANDBY; + default: + /* Unknown state */ + return NETOPT_STATE_OFF; + } +} + +int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + + if (dev == NULL) { + return -ENODEV; + } + + switch (opt) { + case NETOPT_MAX_PACKET_SIZE: + if (len < sizeof(int16_t)) { + return -EOVERFLOW; + } + + *((uint16_t *)value) = KW41ZRF_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD; + return sizeof(uint16_t); + + case NETOPT_STATE: + if (len < sizeof(netopt_state_t)) { + return -EOVERFLOW; + } + *((netopt_state_t *)value) = kw41zrf_netdev_get_state(dev); + return sizeof(netopt_state_t); + + case NETOPT_PRELOADING: + if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { + *((netopt_enable_t *)value) = NETOPT_ENABLE; + } + else { + *((netopt_enable_t *)value) = NETOPT_DISABLE; + } + return sizeof(netopt_enable_t); + + case NETOPT_PROMISCUOUSMODE: + if (dev->netdev.flags & KW41ZRF_OPT_PROMISCUOUS) { + *((netopt_enable_t *)value) = NETOPT_ENABLE; + } + else { + *((netopt_enable_t *)value) = NETOPT_DISABLE; + } + return sizeof(netopt_enable_t); + + case NETOPT_RX_START_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START); + return sizeof(netopt_enable_t); + + case NETOPT_RX_END_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END); + return sizeof(netopt_enable_t); + + case NETOPT_TX_START_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START); + return sizeof(netopt_enable_t); + + case NETOPT_TX_END_IRQ: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END); + return sizeof(netopt_enable_t); + + case NETOPT_CSMA: + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_CSMA); + return sizeof(netopt_enable_t); + + case NETOPT_CSMA_RETRIES: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + *((uint8_t *)value) = dev->csma_max_backoffs; + return sizeof(uint8_t); + + case NETOPT_CSMA_MAXBE: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + *((uint8_t *)value) = dev->csma_max_be; + return sizeof(uint8_t); + + case NETOPT_CSMA_MINBE: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + *((uint8_t *)value) = dev->csma_min_be; + return sizeof(uint8_t); + + case NETOPT_RETRANS: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + *((uint8_t *)value) = dev->max_retrans; + return sizeof(uint8_t); + + case NETOPT_TX_POWER: + if (len < sizeof(int16_t)) { + return -EOVERFLOW; + } + *((uint16_t *)value) = kw41zrf_get_txpower(dev); + return sizeof(uint16_t); + + case NETOPT_IS_CHANNEL_CLR: + if (kw41zrf_cca(dev) == 0) { + *((netopt_enable_t *)value) = NETOPT_ENABLE; + } + else { + *((netopt_enable_t *)value) = NETOPT_DISABLE; + } + return sizeof(netopt_enable_t); + + case NETOPT_CCA_THRESHOLD: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + else { + *(int8_t *)value = kw41zrf_get_cca_threshold(dev); + } + return sizeof(int8_t); + + case NETOPT_CCA_MODE: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + else { + *(uint8_t *)value = kw41zrf_get_cca_mode(dev); + switch (*((int8_t *)value)) { + case NETDEV_IEEE802154_CCA_MODE_1: + case NETDEV_IEEE802154_CCA_MODE_2: + case NETDEV_IEEE802154_CCA_MODE_3: + return sizeof(uint8_t); + default: + break; + } + return -EOVERFLOW; + } + break; + + case NETOPT_LAST_ED_LEVEL: + if (len < sizeof(int8_t)) { + return -EOVERFLOW; + } + else { + *(int8_t *)value = kw41zrf_get_ed_level(dev); + } + return sizeof(int8_t); + + case NETOPT_TX_RETRIES_NEEDED: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + else { + *(uint8_t *)value = dev->num_retrans; + } + return sizeof(uint8_t); + + case NETOPT_CHANNEL_PAGE: + if (len < sizeof(uint16_t)) { + return -EOVERFLOW; + } + else { + *(uint16_t *)value = 0; + } + return sizeof(uint16_t); + + default: + break; + } + + return netdev_ieee802154_get((netdev_ieee802154_t *)netdev, opt, value, len); +} + +static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, size_t len) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + int res = -ENOTSUP; + + if (dev == NULL) { + return -ENODEV; + } + + switch (opt) { + case NETOPT_ADDRESS: + if (len > sizeof(uint16_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_addr_short(dev, *((const uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ + } + break; + + case NETOPT_ADDRESS_LONG: + if (len > sizeof(uint64_t)) { + return -EOVERFLOW; + } + else { + kw41zrf_set_addr_long(dev, *((const uint64_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ + } + break; + + case NETOPT_NID: + if (len > sizeof(uint16_t)) { + return -EOVERFLOW; + } + + else { + kw41zrf_set_pan(dev, *((const uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::pan */ + } + break; + + case NETOPT_CHANNEL: + if (len < sizeof(uint8_t)) { + res = -EINVAL; + } + else { + uint8_t chan = ((const uint8_t *)value)[0]; + if (kw41zrf_set_channel(dev, chan)) { + res = -EINVAL; + break; + } + /* don't set res to set netdev_ieee802154_t::chan */ + } + break; + + case NETOPT_CHANNEL_PAGE: + res = -EINVAL; + break; + + case NETOPT_TX_POWER: + if (len < sizeof(int16_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_tx_power(dev, *(const int16_t *)value); + res = sizeof(int16_t); + } + break; + + case NETOPT_STATE: + if (len > sizeof(netopt_state_t)) { + res = -EOVERFLOW; + } + else { + res = kw41zrf_netdev_set_state(dev, *((const netopt_state_t *)value)); + } + break; + + case NETOPT_AUTOACK: + /* Set up HW generated automatic ACK after Receive */ + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_ACK_REQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, + ((const netopt_enable_t *)value)[0]); + /* don't set res to set netdev_ieee802154_t::flags */ + break; + + case NETOPT_PRELOADING: + kw41zrf_set_option(dev, KW41ZRF_OPT_PRELOADING, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_PROMISCUOUSMODE: + kw41zrf_set_option(dev, KW41ZRF_OPT_PROMISCUOUS, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_RX_START_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_RX_END_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_TX_START_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_START, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_TX_END_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_CSMA: + kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_CSMA_RETRIES: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + dev->csma_max_backoffs = *((const uint8_t*)value); + res = sizeof(uint8_t); + } + break; + + case NETOPT_CSMA_MAXBE: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + dev->csma_max_be = *((const uint8_t*)value); + res = sizeof(uint8_t); + } + break; + + case NETOPT_CSMA_MINBE: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + dev->csma_min_be = *((const uint8_t*)value); + res = sizeof(uint8_t); + } + break; + + case NETOPT_RETRANS: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + dev->max_retrans = *((const uint8_t *)value); + res = sizeof(uint8_t); + break; + + case NETOPT_CCA_THRESHOLD: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_cca_threshold(dev, *((const uint8_t*)value)); + res = sizeof(uint8_t); + } + break; + + case NETOPT_CCA_MODE: + if (len < sizeof(uint8_t)) { + res = -EOVERFLOW; + } + else { + switch (*((const uint8_t*)value)) { + case NETDEV_IEEE802154_CCA_MODE_1: + case NETDEV_IEEE802154_CCA_MODE_2: + case NETDEV_IEEE802154_CCA_MODE_3: + kw41zrf_set_cca_mode(dev, *((const uint8_t*)value)); + res = sizeof(uint8_t); + break; + case NETDEV_IEEE802154_CCA_MODE_4: + case NETDEV_IEEE802154_CCA_MODE_5: + case NETDEV_IEEE802154_CCA_MODE_6: + default: + break; + } + } + break; + + default: + break; + } + + if (res == -ENOTSUP) { + res = netdev_ieee802154_set((netdev_ieee802154_t *)netdev, opt, + value, len); + } + + return res; +} + +/* Common CCA check handler code for sequences T and TR */ +static uint32_t _isr_event_seq_t_ccairq(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_CCAIRQ_MASK) { + /* CCA before TX has completed */ + handled_irqs |= ZLL_IRQSTS_CCAIRQ_MASK; + if (irqsts & ZLL_IRQSTS_CCA_MASK) { + /* Channel was determined busy */ + DEBUG("[kw41zrf] CCA ch busy (RSSI: %d)\n", + (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> + ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)); + if (dev->csma_num_backoffs < dev->csma_max_backoffs) { + /* Perform CSMA/CA backoff algorithm */ + ++dev->csma_num_backoffs; + if (dev->csma_be < dev->csma_max_be) { + /* Increase delay exponent */ + ++dev->csma_be; + } + /* Resubmit the frame for transmission */ + kw41zrf_tx_exec(dev); + return handled_irqs; + } + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); + } + } + else { + /* Channel is idle */ + DEBUG("[kw41zrf] CCA ch idle (RSSI: %d)\n", + (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> + ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)); + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START) { + /* TX will start automatically after CCA check succeeded */ + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_STARTED); + } + } + } + return handled_irqs; +} + +static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + + if (irqsts & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) { + DEBUG("[kw41zrf] RXWTRMRKIRQ (R)\n"); + handled_irqs |= ZLL_IRQSTS_RXWTRMRKIRQ_MASK; + if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_STARTED); + } + } + + if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) { + DEBUG("[kw41zrf] FILTERFAILIRQ: %04"PRIx32"\n", ZLL->FILTERFAIL_CODE); + handled_irqs |= ZLL_IRQSTS_FILTERFAIL_IRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { + DEBUG("[kw41zrf] finished RX\n"); + handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK; + DEBUG("[kw41zrf] RX len: %3u\n", + (unsigned int)((ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> + ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)); + if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_AUTOACK_MASK) { + DEBUG("[kw41zrf] perform TXACK\n"); + } + } + + if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + DEBUG("[kw41zrf] finished TXACK\n"); + handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + uint32_t seq_ctrl_sts = ZLL->SEQ_CTRL_STS; + kw41zrf_abort_sequence(dev); + DEBUG("[kw41zrf] SEQIRQ (R)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if ((irqsts & ZLL_IRQSTS_CRCVALID_MASK) == 0) { + LOG_ERROR("[kw41zrf] CRC failure (R)\n"); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { + LOG_ERROR("[kw41zrf] RX timeout (R)\n"); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) { + LOG_ERROR("[kw41zrf] PLL unlock (R)\n"); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) { + LOG_ERROR("[kw41zrf] SW abort (R)\n"); + } + else { + /* No error reported */ + DEBUG("[kw41zrf] success (R)\n"); + /* Wait in SEQ_IDLE until recv has been called */ + dev->idle_seq = XCVSEQ_IDLE; + kw41zrf_set_sequence(dev, dev->idle_seq); + if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_COMPLETE); + } + return handled_irqs; + } + kw41zrf_set_sequence(dev, dev->idle_seq); + } + + return handled_irqs; +} + +static uint32_t _isr_event_seq_t(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + DEBUG("[kw41zrf] finished TX (T)\n"); + handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; + } + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + /* Finished T sequence */ + kw41zrf_abort_sequence(dev); + DEBUG("[kw41zrf] SEQIRQ (T)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); + } + /* Go back to being idle */ + kw41zrf_set_sequence(dev, dev->idle_seq); + } + + return handled_irqs; +} + +/* Standalone CCA */ +static uint32_t _isr_event_seq_cca(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + /* Finished CCA sequence */ + kw41zrf_abort_sequence(dev); + DEBUG("[kw41zrf] SEQIRQ (C)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (irqsts & ZLL_IRQSTS_CCA_MASK) { + DEBUG("[kw41zrf] CCA ch busy\n"); + dev->cca_result = 1; + } + else { + DEBUG("[kw41zrf] CCA ch idle\n"); + dev->cca_result = 0; + } + kw41zrf_set_sequence(dev, dev->idle_seq); + } + + return handled_irqs; +} + +static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + DEBUG("[kw41zrf] finished TX (TR)\n"); + handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; + if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_RXACKRQD_MASK) { + DEBUG("[kw41zrf] wait for RX ACK\n"); + } + } + + if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { + DEBUG("[kw41zrf] got RX ACK\n"); + handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) { + DEBUG("[kw41zrf] FILTERFAILIRQ (TR): %04"PRIx32"\n", ZLL->FILTERFAIL_CODE); + handled_irqs |= ZLL_IRQSTS_FILTERFAIL_IRQ_MASK; + } + + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + uint32_t seq_ctrl_sts = ZLL->SEQ_CTRL_STS; + kw41zrf_abort_sequence(dev); + DEBUG("[kw41zrf] SEQIRQ (TR)\n"); + + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { + DEBUG("[kw41zrf] RXACK timeout (TR)\n"); + if (dev->num_retrans < dev->max_retrans) { + /* Perform frame retransmission */ + ++dev->num_retrans; + DEBUG("[kw41zrf] retry %u\n", (unsigned)dev->num_retrans); + /* Reset CSMA counters for backoff handling */ + dev->csma_be = dev->csma_min_be; + dev->csma_num_backoffs = 0; + /* Resubmit the frame for transmission */ + kw41zrf_tx_exec(dev); + return handled_irqs; + } + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_NOACK); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) { + DEBUG("[kw41zrf] PLL unlock (TR)\n"); + /* TODO: there is no other error event for TX failures */ + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); + } + else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) { + DEBUG("[kw41zrf] SW abort (TR)\n"); + /* TODO: there is no other error event for TX failures */ + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); + } + else { + /* No error reported */ + DEBUG("[kw41zrf] TX success (TR)\n"); + dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); + } + } + kw41zrf_set_sequence(dev, dev->idle_seq); + } + + return handled_irqs; +} + +static uint32_t _isr_event_seq_ccca(kw41zrf_t *dev, uint32_t irqsts) +{ + uint32_t handled_irqs = 0; + if (irqsts & ZLL_IRQSTS_SEQIRQ_MASK) { + DEBUG("[kw41zrf] SEQIRQ (CCCA)\n"); + handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (irqsts & ZLL_IRQSTS_CCA_MASK) { + DEBUG("[kw41zrf] CCCA ch busy\n"); + } + else { + DEBUG("[kw41zrf] CCCA ch idle\n"); + } + kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); + } + + return handled_irqs; +} + +static void kw41zrf_netdev_isr(netdev_t *netdev) +{ + kw41zrf_t *dev = (kw41zrf_t *)netdev; + if (!spinning_for_irq) { + num_irqs_handled = num_irqs_queued; + } + uint32_t irqsts = ZLL->IRQSTS; + + /* Clear all IRQ flags now */ + ZLL->IRQSTS = irqsts; + + kw41zrf_unmask_irqs(); + + uint32_t handled_irqs = 0; + DEBUG("[kw41zrf] CTRL %08" PRIx32 ", IRQSTS %08" PRIx32 ", FILTERFAIL %08" PRIx32 "\n", + ZLL->PHY_CTRL, irqsts, ZLL->FILTERFAIL_CODE); + + uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + + switch (seq) { + case XCVSEQ_RECEIVE: + handled_irqs |= _isr_event_seq_r(dev, irqsts); + break; + + case XCVSEQ_TRANSMIT: + /* First check CCA flags */ + handled_irqs |= _isr_event_seq_t_ccairq(dev, irqsts); + /* Then TX flags */ + handled_irqs |= _isr_event_seq_t(dev, irqsts); + break; + + case XCVSEQ_CCA: + handled_irqs |= _isr_event_seq_cca(dev, irqsts); + break; + + case XCVSEQ_TX_RX: + /* First check CCA flags */ + handled_irqs |= _isr_event_seq_t_ccairq(dev, irqsts); + /* Then TX/RX flags */ + handled_irqs |= _isr_event_seq_tr(dev, irqsts); + break; + + case XCVSEQ_CONTINUOUS_CCA: + handled_irqs |= _isr_event_seq_ccca(dev, irqsts); + break; + + case XCVSEQ_IDLE: + DEBUG("[kw41zrf] IRQ while IDLE\n"); + break; + + default: + DEBUG("[kw41zrf] undefined seq state in isr\n"); + break; + } + + irqsts &= ~handled_irqs; + + if (irqsts & 0x000f017f) { + DEBUG("[kw41zrf] Unhandled IRQs: 0x%08"PRIx32"\n", + (irqsts & 0x000f017f)); + } +} + +const netdev_driver_t kw41zrf_driver = { + .init = kw41zrf_netdev_init, + .send = kw41zrf_netdev_send, + .recv = kw41zrf_netdev_recv, + .get = kw41zrf_netdev_get, + .set = kw41zrf_netdev_set, + .isr = kw41zrf_netdev_isr, +}; + +/** @} */ diff --git a/drivers/kw41zrf/vendor/Common/EmbeddedTypes.h b/drivers/kw41zrf/vendor/Common/EmbeddedTypes.h new file mode 100644 index 000000000000..6a0ffd325de4 --- /dev/null +++ b/drivers/kw41zrf/vendor/Common/EmbeddedTypes.h @@ -0,0 +1,221 @@ +/*! +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* \file +* +* This file holds type definitions that maps the standard c-types into types +* with guaranteed sizes. The types are target/platform specific and must be edited +* for each new target/platform. +* The header file also provides definitions for TRUE, FALSE and NULL. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _EMBEDDEDTYPES_H_ +#define _EMBEDDEDTYPES_H_ + + +/************************************************************************************ +* +* INCLUDES +* +************************************************************************************/ + +#include + + +/************************************************************************************ +* +* TYPE DEFINITIONS +* +************************************************************************************/ + +/* boolean types */ +typedef uint8_t bool_t; + +typedef uint8_t index_t; + +/* TRUE/FALSE definition*/ +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* null pointer definition*/ +#ifndef NULL +#define NULL (( void * )( 0x0UL )) +#endif + +#if defined(__GNUC__) +#define PACKED_STRUCT struct __attribute__ ((__packed__)) +#define PACKED_UNION union __attribute__ ((__packed__)) +#elif defined(__IAR_SYSTEMS_ICC__) +#define PACKED_STRUCT __packed struct +#define PACKED_UNION __packed union +#else +#define PACKED_STRUCT struct +#define PACKED_UNION union +#endif + +typedef unsigned char uintn8_t; +typedef unsigned long uintn32_t; + +typedef unsigned char uchar_t; + +#if !defined(MIN) +#define MIN(a,b) (((a) < (b))?(a):(b)) +#endif + +#if !defined(MAX) +#define MAX(a,b) (((a) > (b))?(a):(b)) +#endif + +/* Compute the number of elements of an array */ +#define NumberOfElements(x) (sizeof(x)/sizeof((x)[0])) + +/* Compute the size of a string initialized with quotation marks */ +#define SizeOfString(string) (sizeof(string) - 1) + +#define GetRelAddr(strct, member) ((uint32_t)&(((strct*)(void *)0)->member)) +#define GetSizeOfMember(strct, member) sizeof(((strct*)(void *)0)->member) + +/* Type definitions for link configuration of instantiable layers */ +#define gInvalidInstanceId_c (instanceId_t)(-1) +typedef uint32_t instanceId_t; + +/* Bit shift definitions */ +#define BIT0 0x01 +#define BIT1 0x02 +#define BIT2 0x04 +#define BIT3 0x08 +#define BIT4 0x10 +#define BIT5 0x20 +#define BIT6 0x40 +#define BIT7 0x80 +#define BIT8 0x100 +#define BIT9 0x200 +#define BIT10 0x400 +#define BIT11 0x800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x10000 +#define BIT17 0x20000 +#define BIT18 0x40000 +#define BIT19 0x80000 +#define BIT20 0x100000 +#define BIT21 0x200000 +#define BIT22 0x400000 +#define BIT23 0x800000 +#define BIT24 0x1000000 +#define BIT25 0x2000000 +#define BIT26 0x4000000 +#define BIT27 0x8000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* Shift definitions */ +#define SHIFT0 (0) +#define SHIFT1 (1) +#define SHIFT2 (2) +#define SHIFT3 (3) +#define SHIFT4 (4) +#define SHIFT5 (5) +#define SHIFT6 (6) +#define SHIFT7 (7) +#define SHIFT8 (8) +#define SHIFT9 (9) +#define SHIFT10 (10) +#define SHIFT11 (11) +#define SHIFT12 (12) +#define SHIFT13 (13) +#define SHIFT14 (14) +#define SHIFT15 (15) +#define SHIFT16 (16) +#define SHIFT17 (17) +#define SHIFT18 (18) +#define SHIFT19 (19) +#define SHIFT20 (20) +#define SHIFT21 (21) +#define SHIFT22 (22) +#define SHIFT23 (23) +#define SHIFT24 (24) +#define SHIFT25 (25) +#define SHIFT26 (26) +#define SHIFT27 (27) +#define SHIFT28 (28) +#define SHIFT29 (29) +#define SHIFT30 (30) +#define SHIFT31 (31) + +#define SHIFT32 (32) +#define SHIFT33 (33) +#define SHIFT34 (34) +#define SHIFT35 (35) +#define SHIFT36 (36) +#define SHIFT37 (37) +#define SHIFT38 (38) +#define SHIFT39 (39) +#define SHIFT40 (40) +#define SHIFT41 (41) +#define SHIFT42 (42) +#define SHIFT43 (43) +#define SHIFT44 (44) +#define SHIFT45 (45) +#define SHIFT46 (46) +#define SHIFT47 (47) +#define SHIFT48 (48) +#define SHIFT49 (49) +#define SHIFT50 (50) +#define SHIFT51 (51) +#define SHIFT52 (52) +#define SHIFT53 (53) +#define SHIFT54 (54) +#define SHIFT55 (55) +#define SHIFT56 (56) +#define SHIFT57 (57) +#define SHIFT58 (58) +#define SHIFT59 (59) +#define SHIFT60 (60) +#define SHIFT61 (61) +#define SHIFT62 (62) +#define SHIFT63 (63) + + +#endif /* _EMBEDDEDTYPES_H_ */ diff --git a/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h new file mode 100644 index 000000000000..fd07180f73d8 --- /dev/null +++ b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h @@ -0,0 +1,614 @@ +/*! +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* \file +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#ifndef _FSL_OS_ABSTRACTION_H_ +#define _FSL_OS_ABSTRACTION_H_ + +#include "EmbeddedTypes.h" +#include "fsl_os_abstraction_config.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +/*! @brief Type for the Task Priority*/ + typedef uint16_t osaTaskPriority_t; +/*! @brief Type for the timer definition*/ + typedef enum { + osaTimer_Once = 0, /*!< one-shot timer*/ + osaTimer_Periodic = 1 /*!< repeating timer*/ + } osaTimer_t; + /*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */ + typedef void* osaTaskId_t; +/*! @brief Type for the parameter to be passed to the task at its creation */ + typedef void* osaTaskParam_t; + /*! @brief Type for task pointer. Task prototype declaration */ + typedef void (*osaTaskPtr_t) (osaTaskParam_t task_param); +/*! @brief Type for the semaphore handler, returned by the OSA_SemaphoreCreate function. */ + typedef void* osaSemaphoreId_t; +/*! @brief Type for the mutex handler, returned by the OSA_MutexCreate function. */ + typedef void* osaMutexId_t; +/*! @brief Type for the event handler, returned by the OSA_EventCreate function. */ + typedef void* osaEventId_t; +/*! @brief Type for an event flags group, bit 32 is reserved. */ + typedef uint32_t osaEventFlags_t; +/*! @brief Message definition. */ + typedef void* osaMsg_t; +/*! @brief Type for the message queue handler, returned by the OSA_MsgQCreate function. */ + typedef void* osaMsgQId_t; + /*! @brief Type for the Timer handler, returned by the OSA_TimerCreate function. */ + typedef void *osaTimerId_t; +/*! @brief Type for the Timer callback function pointer. */ + typedef void (*osaTimerFctPtr_t) (void const *argument); +/*! @brief Thread Definition structure contains startup information of a thread.*/ +typedef struct osaThreadDef_tag { + osaTaskPtr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; + void *tlink; + uint8_t *tname; + bool_t useFloat; +} osaThreadDef_t; +/*! @brief Thread Link Definition structure .*/ +typedef struct osaThreadLink_tag{ + uint8_t link[12]; + osaTaskId_t osThreadId; + osaThreadDef_t *osThreadDefHandle; + uint32_t *osThreadStackHandle; +}osaThreadLink_t, *osaThreadLinkHandle_t; + +/*! @Timer Definition structure contains timer parameters.*/ +typedef struct osaTimerDef_tag { + osaTimerFctPtr_t pfCallback; /* < start address of a timer function */ + void *argument; +} osaTimerDef_t; +/*! @brief Defines the return status of OSA's functions */ +typedef enum osaStatus_tag +{ + osaStatus_Success = 0U, /*!< Success */ + osaStatus_Error = 1U, /*!< Failed */ + osaStatus_Timeout = 2U, /*!< Timeout occurs while waiting */ + osaStatus_Idle = 3U /*!< Used for bare metal only, the wait object is not ready + and timeout still not occur */ +}osaStatus_t; + + +/*! ********************************************************************************* +************************************************************************************* +* Public macros +************************************************************************************* +********************************************************************************** */ +#if defined (FSL_RTOS_MQX) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_FREE_RTOS) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_UCOSII) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_UCOSIII) + #define USE_RTOS 1 +#else + #define USE_RTOS 0 +#endif + +#define OSA_PRIORITY_IDLE (6) +#define OSA_PRIORITY_LOW (5) +#define OSA_PRIORITY_BELOW_NORMAL (4) +#define OSA_PRIORITY_NORMAL (3) +#define OSA_PRIORITY_ABOVE_NORMAL (2) +#define OSA_PRIORITY_HIGH (1) +#define OSA_PRIORITY_REAL_TIME (0) +#define OSA_TASK_PRIORITY_MAX (0) +#define OSA_TASK_PRIORITY_MIN (15) +#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define osaWaitForever_c ((uint32_t)(-1)) +#define osaEventFlagsAll_c ((osaEventFlags_t)(0x00FFFFFF)) +#define osThreadStackArray(name) osThread_##name##_stack +#define osThreadStackDef(name, stacksize, instances) \ + uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize)*(instances)]; + +/* ==== Thread Management ==== */ + +/* Create a Thread Definition with function, priority, and stack requirements. + * \param name name of the thread function. + * \param priority initial priority of the thread function. + * \param instances number of possible thread instances. + * \param stackSz stack size (in bytes) requirements for the thread function. + * \param useFloat + */ +#if defined(FSL_RTOS_MQX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadLink_t osThreadLink_##name[instances] = {0}; \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + osThreadLink_##name, \ + (uint8_t*) #name,\ + (useFloat)} +#elif defined (FSL_RTOS_UCOSII) + #if gTaskMultipleInstancesManagement_c +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadLink_t osThreadLink_##name[instances] = {0}; \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + osThreadLink_##name, \ + (uint8_t*) #name,\ + (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + NULL, \ + (uint8_t*) #name,\ + (useFloat)} +#endif +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + NULL, \ + NULL, \ + (uint8_t*) #name,\ + (useFloat)} +#endif +/* Access a Thread defintion. + * \param name name of the thread definition object. + */ +#define OSA_TASK(name) \ +&os_thread_def_##name + +#define OSA_TASK_PROTO(name) \ +extern osaThreadDef_t os_thread_def_##name +/* ==== Timer Management ==== + * Define a Timer object. + * \param name name of the timer object. + * \param function name of the timer call back function. + */ + +#define OSA_TIMER_DEF(name, function) \ +osaTimerDef_t os_timer_def_##name = \ +{ (function), NULL } + +/* Access a Timer definition. + * \param name name of the timer object. + */ +#define OSA_TIMER(name) \ +&os_timer_def_##name + + +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ +extern const uint8_t gUseRtos_c; + + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! + * @name Task management + * @{ + */ + +/*! + * @brief Creates a task. + * + * This function is used to create task based on the resources defined + * by the macro OSA_TASK_DEFINE. + * + * @param thread_def pointer to the osaThreadDef_t structure which defines the task. + * @param task_param Pointer to be passed to the task when it is created. + * + * @retval taskId The task is successfully created. + * @retval NULL The task can not be created.. + * + * Example: + @code + osaTaskId_t taskId; + OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);; + taskId = OSA__TaskCreate(OSA__TASK(Job1), (osaTaskParam_t)NULL); + @endcode + */ +osaTaskId_t OSA_TaskCreate(osaThreadDef_t *thread_def, osaTaskParam_t task_param); + +/*! + * @brief Gets the handler of active task. + * + * @return Handler to current active task. + */ +osaTaskId_t OSA_TaskGetId(void); + +/*! + * @brief Puts the active task to the end of scheduler's queue. + * + * When a task calls this function, it gives up the CPU and puts itself to the + * end of a task ready list. + * + * @retval osaStatus_Success The function is called successfully. + * @retval osaStatus_Error Error occurs with this function. + */ +osaStatus_t OSA_TaskYield(void); + +/*! + * @brief Gets the priority of a task. + * + * @param taskId The handler of the task whose priority is received. + * + * @return Task's priority. + */ +osaTaskPriority_t OSA_TaskGetPriority(osaTaskId_t taskId); + +/*! + * @brief Sets the priority of a task. + * + * @param taskId The handler of the task whose priority is set. + * @param taskPriority The priority to set. + * + * @retval osaStatus_Success Task's priority is set successfully. + * @retval osaStatus_Error Task's priority can not be set. + */ +osaStatus_t OSA_TaskSetPriority(osaTaskId_t taskId, osaTaskPriority_t taskPriority); +/*! + * @brief Destroys a previously created task. + * + * @param taskId The handler of the task to destroy. Returned by the OSA_TaskCreate function. + * + * @retval osaStatus_Success The task was successfully destroyed. + * @retval osaStatus_Error Task destruction failed or invalid parameter. + */ +osaStatus_t OSA_TaskDestroy(osaTaskId_t taskId); + +/*! + * @brief Creates a semaphore with a given value. + * + * This function creates a semaphore and sets the value to the parameter + * initValue. + * + * @param initValue Initial value the semaphore will be set to. + * + * @retval handler to the new semaphore if the semaphore is created successfully. + * @retval NULL if the semaphore can not be created. + * + * + */ +osaSemaphoreId_t OSA_SemaphoreCreate(uint32_t initValue); + +/*! + * @brief Destroys a previously created semaphore. + * + * @param semId Pointer to the semaphore to destroy. + * + * @retval osaStatus_Success The semaphore is successfully destroyed. + * @retval osaStatus_Error The semaphore can not be destroyed. + */ +osaStatus_t OSA_SemaphoreDestroy(osaSemaphoreId_t semId); + +/*! + * @brief Pending a semaphore with timeout. + * + * This function checks the semaphore's counting value. If it is positive, + * decreases it and returns osaStatus_Success. Otherwise, a timeout is used + * to wait. + * + * @param semId Pointer to the semaphore. + * @param millisec The maximum number of milliseconds to wait if semaphore is not + * positive. Pass osaWaitForever_c to wait indefinitely, pass 0 + * will return osaStatus_Timeout immediately. + * + * @retval osaStatus_Success The semaphore is received. + * @retval osaStatus_Timeout The semaphore is not received within the specified 'timeout'. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_SemaphoreWait(osaSemaphoreId_t semId, uint32_t millisec); + +/*! + * @brief Signals for someone waiting on the semaphore to wake up. + * + * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases + * the semaphore's counting value. + * + * @param semId Pointer to the semaphore to signal. + * + * @retval osaStatus_Success The semaphore is successfully signaled. + * @retval osaStatus_Error The object can not be signaled or invalid parameter. + * + */ +osaStatus_t OSA_SemaphorePost(osaSemaphoreId_t semId); + +/*! + * @brief Create an unlocked mutex. + * + * This function creates a non-recursive mutex and sets it to unlocked status. + * + * @param none. + * + * @retval handler to the new mutex if the mutex is created successfully. + * @retval NULL if the mutex can not be created. + */ +osaMutexId_t OSA_MutexCreate(void); + +/*! + * @brief Waits for a mutex and locks it. + * + * This function checks the mutex's status. If it is unlocked, locks it and returns the + * osaStatus_Success. Otherwise, waits for a timeout in milliseconds to lock. + * + * @param mutexId Pointer to the Mutex. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return osaStatus_Timeout + * immediately. + * + * @retval osaStatus_Success The mutex is locked successfully. + * @retval osaStatus_Timeout Timeout occurred. + * @retval osaStatus_Error Incorrect parameter was passed. + * + * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked. + */ +osaStatus_t OSA_MutexLock(osaMutexId_t mutexId, uint32_t millisec); + +/*! + * @brief Unlocks a previously locked mutex. + * + * @param mutexId Pointer to the Mutex. + * + * @retval osaStatus_Success The mutex is successfully unlocked. + * @retval osaStatus_Error The mutex can not be unlocked or invalid parameter. + */ +osaStatus_t OSA_MutexUnlock(osaMutexId_t mutexId); + +/*! + * @brief Destroys a previously created mutex. + * + * @param mutexId Pointer to the Mutex. + * + * @retval osaStatus_Success The mutex is successfully destroyed. + * @retval osaStatus_Error The mutex can not be destroyed. + * + */ +osaStatus_t OSA_MutexDestroy(osaMutexId_t mutexId); + +/*! + * @brief Initializes an event object with all flags cleared. + * + * This function creates an event object and set its clear mode. If autoClear + * is TRUE, when a task gets the event flags, these flags will be + * cleared automatically. Otherwise these flags must + * be cleared manually. + * + * @param autoClear TRUE The event is auto-clear. + * FALSE The event manual-clear + * @retval handler to the new event if the event is created successfully. + * @retval NULL if the event can not be created. + */ +osaEventId_t OSA_EventCreate(bool_t autoClear); + +/*! + * @brief Sets one or more event flags. + * + * Sets specified flags of an event object. + * + * @param eventId Pointer to the event. + * @param flagsToSet Flags to be set. + * + * @retval osaStatus_Success The flags were successfully set. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_EventSet(osaEventId_t eventId, osaEventFlags_t flagsToSet); + +/*! + * @brief Clears one or more flags. + * + * Clears specified flags of an event object. + * + * @param eventId Pointer to the event. + * @param flagsToClear Flags to be clear. + * + * @retval osaStatus_Success The flags were successfully cleared. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_EventClear(osaEventId_t eventId, osaEventFlags_t flagsToClear); + +/*! + * @brief Waits for specified event flags to be set. + * + * This function waits for a combination of flags to be set in an event object. + * Applications can wait for any/all bits to be set. Also this function could + * obtain the flags who wakeup the waiting task. + * + * @param eventId Pointer to the event. + * @param flagsToWait Flags that to wait. + * @param waitAll Wait all flags or any flag to be set. + * @param millisec The maximum number of milliseconds to wait for the event. + * If the wait condition is not met, pass osaWaitForever_c will + * wait indefinitely, pass 0 will return osaStatus_Timeout + * immediately. + * @param setFlags Flags that wakeup the waiting task are obtained by this parameter. + * + * @retval osaStatus_Success The wait condition met and function returns successfully. + * @retval osaStatus_Timeout Has not met wait condition within timeout. + * @retval osaStatus_Error An incorrect parameter was passed. + + * + * @note Please pay attention to the flags bit width, FreeRTOS uses the most + * significant 8 bis as control bits, so do not wait these bits while using + * FreeRTOS. + * + */ +osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool_t waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags); + +/*! + * @brief Destroys a previously created event object. + * + * @param eventId Pointer to the event. + * + * @retval osaStatus_Success The event is successfully destroyed. + * @retval osaStatus_Error Event destruction failed. + */ +osaStatus_t OSA_EventDestroy(osaEventId_t eventId); + +/*! + * @brief Initializes a message queue. + * + * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*. + * + * @param msgNo :number of messages the message queue should accommodate. + * This parameter should not exceed osNumberOfMessages defined in OSAbstractionConfig.h. + * +* @return: Handler to access the queue for put and get operations. If message queue + * creation failed, return NULL. + */ +osaMsgQId_t OSA_MsgQCreate(uint32_t msgNo); + +/*! + * @brief Puts a message at the end of the queue. + * + * This function puts a message to the end of the message queue. If the queue + * is full, this function returns the osaStatus_Error; + * + * @param msgQId pointer to queue returned by the OSA_MsgQCreate function. + * @param pMessage Pointer to the message to be put into the queue. + * + * @retval osaStatus_Success Message successfully put into the queue. + * @retval osaStatus_Error The queue was full or an invalid parameter was passed. + */ +osaStatus_t OSA_MsgQPut(osaMsgQId_t msgQId, osaMsg_t pMessage); + +/*! + * @brief Reads and remove a message at the head of the queue. + * + * This function gets a message from the head of the message queue. If the + * queue is empty, timeout is used to wait. + * + * @param msgQId Queue handler returned by the OSA_MsgQCreate function. + * @param pMessage Pointer to a memory to save the message. + * @param millisec The number of milliseconds to wait for a message. If the + * queue is empty, pass osaWaitForever_c will wait indefinitely, + * pass 0 will return osaStatus_Timeout immediately. + * + * @retval osaStatus_Success Message successfully obtained from the queue. + * @retval osaStatus_Timeout The queue remains empty after timeout. + * @retval osaStatus_Error Invalid parameter. + */ +osaStatus_t OSA_MsgQGet(osaMsgQId_t msgQId, osaMsg_t pMessage, uint32_t millisec); + +/*! + * @brief Destroys a previously created queue. + * + * @param msgQId queue handler returned by the OSA_MsgQCreate function. + * + * @retval osaStatus_Success The queue was successfully destroyed. + * @retval osaStatus_Error Message queue destruction failed. +*/ +osaStatus_t OSA_MsgQDestroy(osaMsgQId_t msgQId); + +/*! + * @brief Enable all interrupts. +*/ +void OSA_InterruptEnable(void); + +/*! + * @brief Disable all interrupts. +*/ +void OSA_InterruptDisable(void); + +/*! + * @brief Enable all interrupts using PRIMASK. +*/ +void OSA_EnableIRQGlobal(void); + +/*! + * @brief Disable all interrupts using PRIMASK. +*/ +void OSA_DisableIRQGlobal(void); + +/*! + * @brief Delays execution for a number of milliseconds. + * + * @param millisec The time in milliseconds to wait. + */ +void OSA_TimeDelay(uint32_t millisec); + +/*! + * @brief This function gets current time in milliseconds. + * + * @retval current time in milliseconds + */ +uint32_t OSA_TimeGetMsec(void); + +/*! + * @brief Installs the interrupt handler. + * + * @param IRQNumber IRQ number of the interrupt. + * @param handler The interrupt handler to install. + */ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h new file mode 100644 index 000000000000..9cb94012eb8a --- /dev/null +++ b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h @@ -0,0 +1,69 @@ +/*! +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* \file +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ +#define _FSL_OS_ABSTRACTION_CONFIG_H_ + +#ifndef osNumberOfSemaphores +#define osNumberOfSemaphores 5 +#endif +#ifndef osNumberOfMutexes +#define osNumberOfMutexes 5 +#endif +#ifndef osNumberOfMessageQs +#define osNumberOfMessageQs 0 +#endif +#ifndef osNumberOfMessages +#define osNumberOfMessages 10 +#endif +#ifndef osNumberOfEvents +#define osNumberOfEvents 5 +#endif + +#ifndef gMainThreadStackSize_c +#define gMainThreadStackSize_c 1024 +#endif +#ifndef gMainThreadPriority_c +#define gMainThreadPriority_c 7 +#endif + +#ifndef gTaskMultipleInstancesManagement_c +#define gTaskMultipleInstancesManagement_c 0 +#endif +#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/Makefile b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/Makefile new file mode 100644 index 000000000000..3c647adb54dc --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/Makefile @@ -0,0 +1,8 @@ +MODULE = mcux_xcvr_mkw41z + +# This vendor code expect all the vendor headers to also be in the include path +# These include paths are only added when building this particular directory and +# should not be available to the rest of the system. +INCLUDES += -I../../OSAbstraction/Interface + +include $(RIOTBASE)/Makefile.base diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c new file mode 100644 index 000000000000..7a5c118ce0c4 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c @@ -0,0 +1,212 @@ +/*! +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" +#include "xcvr_test_fsk.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private type definitions +************************************************************************************* +********************************************************************************** */ +enum { + gDftNormal_c = 0, + gDftTxNoMod_Carrier_c = 1, + gDftTxPattern_c = 2, + gDftTxRandom_c = 3, +}; + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +void XcvrFskModTx(void); +void XcvrFskNoModTx(void); +void XcvrFskIdle(void); +void XcvrFskTxRand(void); +void XcvrFskLoadPattern(uint32_t u32Pattern); +void XcvrFskSetTxPower(uint8_t u8TxPow); +void XcvrFskSetTxChannel(uint8_t u8TxChan); +void XcvrFskRestoreTXControl(void); +uint8_t XcvrFskGetInstantRssi(void); + +/*! ********************************************************************************* +* XcvrFskModTx +***********************************************************************************/ +void XcvrFskModTx(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxPattern_c) | + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK; + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskNoModTx +***********************************************************************************/ +void XcvrFskNoModTx(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxNoMod_Carrier_c); + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskIdle +***********************************************************************************/ +void XcvrFskIdle(void) +{ + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | + XCVR_TX_DIG_CTRL_LFSR_EN_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; + XCVR_MISC->DTEST_CTRL &= ~XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskTxRand +***********************************************************************************/ +void XcvrFskTxRand(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | + XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxRandom_c) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(0) | /* length 9 */ + XCVR_TX_DIG_CTRL_LFSR_EN_MASK; + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskLoadPattern +***********************************************************************************/ +void XcvrFskLoadPattern(uint32_t u32Pattern) +{ + XCVR_TX_DIG->DFT_PATTERN = u32Pattern; +} + +/*! ********************************************************************************* +* XcvrFskGetInstantRssi +***********************************************************************************/ +uint8_t XcvrFskGetInstantRssi(void) +{ + uint8_t u8Rssi; + uint32_t t1,t2,t3; + t1 = XCVR_RX_DIG->RX_DIG_CTRL; + t2 = XCVR_RX_DIG->RSSI_CTRL_0; + t3 = XCVR_PHY->CFG1; + XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate == 0 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ; + + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5); + + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); + + uint32_t temp = XCVR_PHY->CFG1; + temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK; + temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF); + XCVR_PHY->CFG1 = temp; + + XCVR_ForceRxWu(); + for(uint32_t i = 0; i < 10000; i++) + { + __asm("nop"); + } + u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & + XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> + XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT); + XCVR_ForceRxWd(); + + XCVR_RX_DIG->RX_DIG_CTRL = t1; + XCVR_RX_DIG->RSSI_CTRL_0 = t2; + XCVR_PHY->CFG1 = t3; + return u8Rssi; +} + +/*! ********************************************************************************* +* XcvrFskSetTxPower +***********************************************************************************/ +void XcvrFskSetTxPower(uint8_t u8TxPow) +{ + return; +} + +/*! ********************************************************************************* +* XcvrFskSetTxChannel +***********************************************************************************/ +void XcvrFskSetTxChannel(uint8_t u8TxChan) +{ + return; +} + +/*! ********************************************************************************* +* XcvrFskRestoreTXControl +* After calling this function user should switch to +* previous protocol and set the protocol channel to default +***********************************************************************************/ +void XcvrFskRestoreTXControl(void) +{ + return; +} + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h new file mode 100644 index 000000000000..a3be92c53c2e --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h @@ -0,0 +1,157 @@ +/*! +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __XCVR_TEST_FSK_H__ +#define __XCVR_TEST_FSK_H__ + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* +* \brief This function returns instant RSSI value and returns it as unsigned byte. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Initialization of the xcvr is necessary prior to calling this function +* +***********************************************************************************/ +extern uint8_t XcvrFskGetInstantRssi(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous modulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Initialization of the xcvr and calling XcvrFskLoadPattern are necessary +* prior to calling this function +* +***********************************************************************************/ +extern void XcvrFskModTx(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous unmodulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskNoModTx(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into idle. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskIdle(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous modulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details The modulation used is a pseudo-random pattern generated using a LFSR. +* +***********************************************************************************/ +extern void XcvrFskTxRand(void); + +/*! ********************************************************************************* +* \brief This function loads a 32 bit value into the pattern register used by XcvrFskModTx. +* +* \param[in] u32Pattern The pattern to be loaded. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskLoadPattern(uint32_t u32Pattern); + +/*! ********************************************************************************* +* \brief This function gives tx power control to xcvr and sets the power to u8TxPow. +* +* \param[in] u8TxPow Values should be between 0x00 and 0x0F. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskSetTxPower(uint8_t u8TxPow); + +/*! ********************************************************************************* +* \brief This function gives tx channel control to xcvr and sets the channel to u8TxChan. +* +* \param[in] u8TxChan Values should be between 0 and 39. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskSetTxChannel(uint8_t u8TxChan); + +/*! ********************************************************************************* +* \brief This function gives tx channel control and power to the upper layer. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Call this function only if XcvrFskSetTxChannel or XcvrFskSetTxPower were called +* previously. +* +***********************************************************************************/ +extern void XcvrFskRestoreTXControl(void); + +#endif + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c new file mode 100644 index 000000000000..c0f86fc9b67d --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_os_abstraction_riot.c @@ -0,0 +1,27 @@ +#include "irq.h" + +#include "fsl_os_abstraction.h" + +static unsigned int irq_mask; + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + irq_restore(irq_mask); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + irq_mask = irq_disable(); +} diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c new file mode 100644 index 000000000000..5701713df20a --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -0,0 +1,2142 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_xcvr.h" +#include "fsl_xcvr_trim.h" +#include +#include "ifr_radio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define channelMapTableSize (128U) +#define gPllDenom_c 0x02000000U /* Denominator is a constant value */ +#define ABS(x) ((x) > 0 ? (x) : -(x)) + +#ifndef TRUE +#define TRUE (true) +#endif + +#ifndef FALSE +#define FALSE (false) +#endif +#define RF_OSCILLATOR_STAYS_ON (false) /* Control whether RF_OSC can be left on all the time. */ +#define RF_OSCILLATOR_READY ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U) + +#ifndef EXTERNAL_CLOCK_GEN +#define EXTERNAL_CLOCK_GEN 0 +#endif + +#define ANT_A 1 +#define ANT_B 0 + +#ifndef XCVR_COEX_RF_ACTIVE_PIN +#define XCVR_COEX_RF_ACTIVE_PIN ANT_B +#endif /* XCVR_COEX_RF_ACTIVE_PIN */ + +typedef struct xcvr_pllChannel_tag +{ + unsigned int integer; + unsigned int numerator; +} xcvr_pllChannel_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address); +void rf_osc_startup(void); +void rf_osc_shutdown(void); +extern double trunc (double); +extern double round (double); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static panic_fptr s_PanicFunctionPtr = NULL; +const xcvr_pllChannel_t mapTable [channelMapTableSize] = +{ + {0x00000025, 0x07C00000}, /* 0 */ + {0x00000025, 0x07C80000}, /* 1 */ + {0x00000025, 0x07D00000}, /* 2 */ + {0x00000025, 0x07D80000}, /* 3 */ + {0x00000025, 0x07E00000}, /* 4 */ + {0x00000025, 0x07E80000}, /* 5 */ + {0x00000025, 0x07F00000}, /* 6 */ + {0x00000025, 0x07F80000}, /* 7 */ + {0x00000025, 0x00000000}, /* 8 */ + {0x00000025, 0x00080000}, /* 9 */ + {0x00000025, 0x00100000}, /* 10 */ + {0x00000025, 0x00180000}, /* 11 */ + {0x00000025, 0x00200000}, /* 12 */ + {0x00000025, 0x00280000}, /* 13 */ + {0x00000025, 0x00300000}, /* 14 */ + {0x00000025, 0x00380000}, /* 15 */ + {0x00000025, 0x00400000}, /* 16 */ + {0x00000025, 0x00480000}, /* 17 */ + {0x00000025, 0x00500000}, /* 18 */ + {0x00000025, 0x00580000}, /* 19 */ + {0x00000025, 0x00600000}, /* 20 */ + {0x00000025, 0x00680000}, /* 21 */ + {0x00000025, 0x00700000}, /* 22 */ + {0x00000025, 0x00780000}, /* 23 */ + {0x00000025, 0x00800000}, /* 24 */ + {0x00000025, 0x00880000}, /* 25 */ + {0x00000025, 0x00900000}, /* 26 */ + {0x00000025, 0x00980000}, /* 27 */ + {0x00000025, 0x00A00000}, /* 28 */ + {0x00000025, 0x00A80000}, /* 29 */ + {0x00000025, 0x00B00000}, /* 30 */ + {0x00000025, 0x00B80000}, /* 31 */ + {0x00000025, 0x00C00000}, /* 32 */ + {0x00000025, 0x00C80000}, /* 33 */ + {0x00000025, 0x00D00000}, /* 34 */ + {0x00000025, 0x00D80000}, /* 35 */ + {0x00000025, 0x00E00000}, /* 36 */ + {0x00000025, 0x00E80000}, /* 37 */ + {0x00000025, 0x00F00000}, /* 38 */ + {0x00000025, 0x00F80000}, /* 39 */ + {0x00000025, 0x01000000}, /* 40 */ + {0x00000026, 0x07080000}, /* 41 */ + {0x00000026, 0x07100000}, /* 42 */ + {0x00000026, 0x07180000}, /* 43 */ + {0x00000026, 0x07200000}, /* 44 */ + {0x00000026, 0x07280000}, /* 45 */ + {0x00000026, 0x07300000}, /* 46 */ + {0x00000026, 0x07380000}, /* 47 */ + {0x00000026, 0x07400000}, /* 48 */ + {0x00000026, 0x07480000}, /* 49 */ + {0x00000026, 0x07500000}, /* 50 */ + {0x00000026, 0x07580000}, /* 51 */ + {0x00000026, 0x07600000}, /* 52 */ + {0x00000026, 0x07680000}, /* 53 */ + {0x00000026, 0x07700000}, /* 54 */ + {0x00000026, 0x07780000}, /* 55 */ + {0x00000026, 0x07800000}, /* 56 */ + {0x00000026, 0x07880000}, /* 57 */ + {0x00000026, 0x07900000}, /* 58 */ + {0x00000026, 0x07980000}, /* 59 */ + {0x00000026, 0x07A00000}, /* 60 */ + {0x00000026, 0x07A80000}, /* 61 */ + {0x00000026, 0x07B00000}, /* 62 */ + {0x00000026, 0x07B80000}, /* 63 */ + {0x00000026, 0x07C00000}, /* 64 */ + {0x00000026, 0x07C80000}, /* 65 */ + {0x00000026, 0x07D00000}, /* 66 */ + {0x00000026, 0x07D80000}, /* 67 */ + {0x00000026, 0x07E00000}, /* 68 */ + {0x00000026, 0x07E80000}, /* 69 */ + {0x00000026, 0x07F00000}, /* 70 */ + {0x00000026, 0x07F80000}, /* 71 */ + {0x00000026, 0x00000000}, /* 72 */ + {0x00000026, 0x00080000}, /* 73 */ + {0x00000026, 0x00100000}, /* 74 */ + {0x00000026, 0x00180000}, /* 75 */ + {0x00000026, 0x00200000}, /* 76 */ + {0x00000026, 0x00280000}, /* 77 */ + {0x00000026, 0x00300000}, /* 78 */ + {0x00000026, 0x00380000}, /* 79 */ + {0x00000026, 0x00400000}, /* 80 */ + {0x00000026, 0x00480000}, /* 81 */ + {0x00000026, 0x00500000}, /* 82 */ + {0x00000026, 0x00580000}, /* 83 */ + {0x00000026, 0x00600000}, /* 84 */ + {0x00000026, 0x00680000}, /* 85 */ + {0x00000026, 0x00700000}, /* 86 */ + {0x00000026, 0x00780000}, /* 87 */ + {0x00000026, 0x00800000}, /* 88 */ + {0x00000026, 0x00880000}, /* 89 */ + {0x00000026, 0x00900000}, /* 90 */ + {0x00000026, 0x00980000}, /* 91 */ + {0x00000026, 0x00A00000}, /* 92 */ + {0x00000026, 0x00A80000}, /* 93 */ + {0x00000026, 0x00B00000}, /* 94 */ + {0x00000026, 0x00B80000}, /* 95 */ + {0x00000026, 0x00C00000}, /* 96 */ + {0x00000026, 0x00C80000}, /* 97 */ + {0x00000026, 0x00D00000}, /* 98 */ + {0x00000026, 0x00D80000}, /* 99 */ + {0x00000026, 0x00E00000}, /* 100 */ + {0x00000026, 0x00E80000}, /* 101 */ + {0x00000026, 0x00F00000}, /* 102 */ + {0x00000026, 0x00F80000}, /* 103 */ + {0x00000026, 0x01000000}, /* 104 */ + {0x00000027, 0x07080000}, /* 105 */ + {0x00000027, 0x07100000}, /* 106 */ + {0x00000027, 0x07180000}, /* 107 */ + {0x00000027, 0x07200000}, /* 108 */ + {0x00000027, 0x07280000}, /* 109 */ + {0x00000027, 0x07300000}, /* 110 */ + {0x00000027, 0x07380000}, /* 111 */ + {0x00000027, 0x07400000}, /* 112 */ + {0x00000027, 0x07480000}, /* 113 */ + {0x00000027, 0x07500000}, /* 114 */ + {0x00000027, 0x07580000}, /* 115 */ + {0x00000027, 0x07600000}, /* 116 */ + {0x00000027, 0x07680000}, /* 117 */ + {0x00000027, 0x07700000}, /* 118 */ + {0x00000027, 0x07780000}, /* 119 */ + {0x00000027, 0x07800000}, /* 120 */ + {0x00000027, 0x07880000}, /* 121 */ + {0x00000027, 0x07900000}, /* 122 */ + {0x00000027, 0x07980000}, /* 123 */ + {0x00000027, 0x07A00000}, /* 124 */ + {0x00000027, 0x07A80000}, /* 125 */ + {0x00000027, 0x07B00000}, /* 126 */ + {0x00000027, 0x07B80000} /* 127 */ +}; + +/* Registers for timing of TX & RX */ +#if RADIO_IS_GEN_3P0 +uint16_t tx_rx_on_delay = TX_RX_ON_DELinit; +uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init; +#else +#if RF_OSC_26MHZ == 1 +uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ; +#else +uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL; +#endif /* RF_OSC_26MHZ == 1 */ +uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL; +#endif /* RADIO_IS_GEN_3P0 */ + +/* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */ +#if RADIO_IS_GEN_3P0 +const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] = +{ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config, + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config, + &xcvr_MSK_2mbps_config, +}; +#endif /* RADIO_IS_GEN_3P0 */ + +const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ + &xcvr_ANT_1mbps_config, +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config, + &xcvr_MSK_1mbps_config, +}; + +const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, /* Invalid option */ +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */ + &xcvr_ANT_1mbps_config, /* Invalid option */ +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config, + &xcvr_MSK_500kbps_config, +}; +const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, /* Invalid option */ +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ + &xcvr_ANT_1mbps_config, /* Invalid option */ +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config, + &xcvr_MSK_250kbps_config, +}; + +static xcvr_currConfig_t current_xcvr_config; + +void rf_osc_startup(void) +{ + if (!RF_OSCILLATOR_READY) + { + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; + } + while (!RF_OSCILLATOR_READY) + { + /* Wait for RF_OSC_READY to be asserted before continuing */ + } +} + +void rf_osc_shutdown(void) +{ + if (!RF_OSCILLATOR_STAYS_ON) + { + RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) +{ + const xcvr_mode_datarate_config_t * mode_datarate_config; + const xcvr_datarate_config_t * datarate_config ; + const xcvr_mode_config_t * radio_mode_cfg; + const xcvr_common_config_t * radio_common_config; + + xcvrStatus_t status; + + IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = + { + {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/ + {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/ + }; + const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T); + +#ifndef SIMULATION + +#if (EXTERNAL_CLOCK_GEN) + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */ +#endif /* EXTERNAL_CLOCK_GEN */ + +#if RADIO_IS_GEN_2P0 + RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */ + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ +#endif /* RADIO_IS_GEN_2P0 */ + + /* Check that this is the proper radio version */ + { + uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT); + + if ( +#if RADIO_IS_GEN_3P0 + (radio_id != 0x5) /* KW3 Gen3 */ +#elif RADIO_IS_GEN_2P1 + (radio_id != 0x5) /* KW35 Gen2.1 */ +#else + (radio_id != 0x3) && /* KW41/31/21 v1 */ + (radio_id != 0xB) /* KW41/31/21 v1.1 */ +#endif /* RADIO_IS_GEN_3P0 */ + ) + { + XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init); + } + } + +#if RADIO_IS_GEN_3P0 + /* Assert Radio Run Request and wait for ack from SPM. */ + RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK; + while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0) + { + } + RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; + rf_osc_startup(); /* Start RF_OSC to allow radio registers access */ +#else + SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; + + /* Load IFR trim values */ + handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); +#endif /* RADIO_IS_GEN_3P0 */ + +#endif /* ifndef SIMULATION */ + + /* Perform the desired XCVR initialization and configuration */ + status = XCVR_GetDefaultConfig(radio_mode, data_rate, + (const xcvr_common_config_t **)&radio_common_config, + (const xcvr_mode_config_t **)&radio_mode_cfg, + (const xcvr_mode_datarate_config_t **)&mode_datarate_config, + (const xcvr_datarate_config_t **)&datarate_config); + + if (status == gXcvrSuccess_c) + { + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, + (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT); + current_xcvr_config.radio_mode = radio_mode; + current_xcvr_config.data_rate = data_rate; + } + + return status; +} + +void XCVR_Deinit(void) +{ +#if RADIO_IS_GEN_3P0 + rf_osc_shutdown(); + RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */ + RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */ +#else + +#endif /* RADIO_IS_GEN_3P0 */ +} + +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, + const xcvr_datarate_config_t ** datarate_config) +{ + xcvrStatus_t status = gXcvrSuccess_c; + /* Common configuration pointer */ + *com_config = (const xcvr_common_config_t *)&xcvr_common_config; + + /* Mode dependent configuration pointer */ + switch (radio_mode) + { +#if !RADIO_IS_GEN_2P1 + case ZIGBEE_MODE: + *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */ + break; + case ANT_MODE: + *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */ + break; +#endif /* !RADIO_IS_GEN_2P1 */ + case BLE_MODE: + *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */ + break; + case GFSK_BT_0p5_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */ + break; + case GFSK_BT_0p5_h_0p32: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */ + break; + case GFSK_BT_0p5_h_0p7: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */ + break; + case GFSK_BT_0p5_h_1p0: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */ + break; + case GFSK_BT_0p3_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */ + break; + case GFSK_BT_0p7_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */ + break; + case MSK: + *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */ + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + + /* Data rate dependent and modeXdatarate dependent configuration pointers */ + if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ + { + switch (data_rate) + { +#if RADIO_IS_GEN_3P0 + case DR_2MBPS: + if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE)) + { + status = gXcvrInvalidParameters_c; + } + else + { + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode]; + } + break; +#endif /* RADIO_IS_GEN_3P0 */ + case DR_1MBPS: + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode]; + break; + case DR_500KBPS: + if (radio_mode == ZIGBEE_MODE) + { + /* See fsl_xcvr_zgbe_config.c for settings */ +#if !RADIO_IS_GEN_2P1 + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */ +#endif /* !RADIO_IS_GEN_2P1 */ + } + else + { + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */ + } + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode]; + break; + case DR_250KBPS: + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode]; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + return status; +} + +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, + XCVR_INIT_MODE_CHG_T first_init) +{ + xcvrStatus_t config_status = gXcvrSuccess_c; + uint32_t temp; + + /* Turn on the module clocks before doing anything */ +#if RADIO_IS_GEN_3P0 + RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */ +#else + SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_ANA configs */ + /*******************************************************************************/ + + /* Configure PLL Loop Filter */ + if (first_init) + { + XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask; + XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init; + } + + /* Configure VCO KVM */ + XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask; + XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init; + + /* Configure analog filter bandwidth */ + XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask; + XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init; + XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask; + XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init; + +#if RADIO_IS_GEN_2P0 + if (first_init) + { + temp = XCVR_ANA->TX_DAC_PA; + temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; + temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); + XCVR_ANA->TX_DAC_PA = temp; + + temp = XCVR_ANA->BB_LDO_2; + temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); + XCVR_ANA->BB_LDO_2 = temp; + + temp = XCVR_ANA->RX_LNA; + temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK; + temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1); + XCVR_ANA->RX_LNA = temp; + + temp = XCVR_ANA->BB_LDO_1; + temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1); + XCVR_ANA->BB_LDO_1 = temp; + } +#endif /* RADIO_IS_GEN_2P0 */ + + /*******************************************************************************/ + /* XCVR_MISC configs */ + /*******************************************************************************/ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); + temp |= mode_config->xcvr_ctrl.init; + +#if RF_OSC_26MHZ == 1 + { + temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_MISC->XCVR_CTRL = temp; + +#if RADIO_IS_GEN_2P1 + XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK; +#endif /* RADIO_IS_GEN_2P1 */ + + /*******************************************************************************/ + /* XCVR_PHY configs */ + /*******************************************************************************/ +#if RADIO_IS_GEN_3P0 + XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0; + XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1; + XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg; + XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate; + XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl; +#else + XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init; + XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init; + XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init; + XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; + XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init; + XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */ +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_PLL_DIG configs */ + /*******************************************************************************/ + if (first_init) + { + XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump; + XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl; + XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map; + XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect; + XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl; +#if !RADIO_IS_GEN_2P1 + XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl; +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res; + XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl; + XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1; + XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match; + XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl; + } + + /*******************************************************************************/ + /* XCVR_RX_DIG configs */ + /*******************************************************************************/ + + /* Configure RF Aux PLL for proper operation based on external clock frequency */ + if (first_init) + { + temp = XCVR_ANA->RX_AUXPLL; + temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK; +#if RF_OSC_26MHZ == 1 + { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4); + } +#else + { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7); + } +#endif /* RF_OSC_26MHZ == 1 */ + XCVR_ANA->RX_AUXPLL = temp; + } + + /* Configure RX_DIG_CTRL */ +#if RF_OSC_26MHZ == 1 + { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */ + } +#else + { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + 0; /* Always disable the sample rate converter for 32MHz */ + } +#endif /* RF_OSC_26MHZ == 1 */ + + temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + /* DCOC_CAL_IIR */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz; + } +#else + { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* DC_RESID_CTRL */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; + } +#else + { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* DCOC_CTRL_0 & _1 */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz; +#endif /* RADIO_IS_GEN_3P0 */ + + /* customize DCOC_CTRL_0 settings for Gen2 GFSK BT=0.5, h=0.32 */ +#if RADIO_IS_GEN_2P0 + if ((mode_config->radio_mode == ANT_MODE) || (mode_config->radio_mode == GFSK_BT_0p5_h_0p32)) + { + if (datarate_config->data_rate == DR_1MBPS) /* only apply fix to 1Mbps data rates */ + { + /* apply the changes to the DCOC_CTRL_0 register XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp &= ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(0x10) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(0x0C); + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + } + } +#endif /* RADIO_IS_GEN_2P0 */ + + } +#else + { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz; +#endif /* RADIO_IS_GEN_3P0 */ + } +#endif /* RF_OSC_26MHZ == 1 */ + if (first_init) + { + /* DCOC_CAL_GAIN */ + XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init; + + /* DCOC_CAL_RCP */ + XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init; + XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0; + XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4; + XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8; + + /* LNA_GAIN_LIN_VAL */ + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init; + + /* BBA_RES_TUNE_LIN_VAL */ + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init; + + /* BBA_STEP */ + XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init; + + /* DCOC_TZA_STEP */ + XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init; + +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + /* DCOC_CAL_FAIL and DCOC_CAL_PASS */ + XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init; + XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init; +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + } + + /* AGC_CTRL_0 .. _3 */ + XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init; + +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz; + } +#else + { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + if (first_init) + { + XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init; + + /* AGC_GAIN_TBL_** */ + XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init; + XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init; + XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init; + XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init; + XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init; + XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init; + XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init; + + /* RSSI_CTRL_0 */ + XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init; + +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init; +#endif /* RADIO_IS_GEN_3P0 */ + + /* CCA_ED_LQI_0 and _1 */ + XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init; + XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init; + } + + /* Channel filter coefficients */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11; + } +#else + { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11; + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0; + XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1; + + /*******************************************************************************/ + /* XCVR_TSM configs */ + /*******************************************************************************/ + XCVR_TSM->CTRL = com_config->tsm_ctrl; + +#if RADIO_IS_GEN_2P0 + if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE)) + { + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; + } +#endif /* RADIO_IS_GEN_2P0 */ + + if (first_init) + { +#if !RADIO_IS_GEN_2P1 + XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */ +#endif /* !RADIO_IS_GEN_2P1 */ + + XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init; + /* TSM registers and timings - dependent upon clock frequency */ +#if RF_OSC_26MHZ == 1 + { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz; + } +#else + { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* TSM timings independent of clock frequency */ + XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init; + XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init; + XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init; + XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init; + XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init; + XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init; + XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init; + XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init; + XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init; + XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init; + XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init; + XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init; + XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init; + XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init; + XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init; + XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init; + XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init; + XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init; + XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init; + XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; + XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init; + XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init; + XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init; + XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init; + XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init; + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init; + XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init; + XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init; + XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; + XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; + XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; + +#if RF_OSC_26MHZ == 1 + { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ); + } +#else + { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD); + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; + XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; + +#if RADIO_IS_GEN_3P0 + XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init; + XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init; + + /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */ +#if (PA_RAMP_TIME == 4) + XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */ + XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */ + XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */ + XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */ + XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */ + XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */ + XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */ + XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */ + XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */ + XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */ + XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */ + XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */ + XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ + XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */ + XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ + XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */ + XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */ + XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */ + XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */ + temp = XCVR_TSM->TIMING14; + temp &= 0xFFFF0000; + temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ + XCVR_TSM->TIMING14 = temp; +#endif /* (PA_RAMP_TIME == 4) */ +#endif /* RADIO_IS_GEN_3P0 */ + } + +#if RADIO_IS_GEN_3P0 + if (mode_config->radio_mode == ZIGBEE_MODE) + { + temp = XCVR_TSM->TIMING35; + temp &= ~(B0(0xFF)); + if (DATA_PADDING_EN == 1) + { + temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */ + } + else + { + temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */ + } + XCVR_TSM->TIMING35 = temp; + } +#else + + if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS))) + { + /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */ + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */ + } + else + { + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ + } +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_TX_DIG configs */ + /*******************************************************************************/ +#if RF_OSC_26MHZ == 1 + { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz; + } +#else + { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + if (first_init) + { + XCVR_TX_DIG->CTRL = com_config->tx_ctrl; + XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; + XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; + +#if !RADIO_IS_GEN_2P1 + XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; + XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; +#endif /* !RADIO_IS_GEN_2P1 */ + } + + XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; + +#ifndef SIMULATION +#if (TRIM_BBA_DCOC_DAC_AT_INIT) + if (first_init) + { + uint32_t end_of_rx_wu = 0; + XCVR_ForceRxWu(); + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + +// if (!rx_bba_dcoc_dac_trim_shortIQ()) + if (!rx_bba_dcoc_dac_trim_DCest()) + { + config_status = gXcvrTrimFailure_c; + } + DCOC_DAC_INIT_Cal(0); + XCVR_ForceRxWd(); + } +#endif /* TRIM_BBA_DCOC_DAC_AT_INIT */ +#endif /* ifndef SIMULATION */ + return config_status; +} + +void XCVR_Reset(void) +{ +#if RADIO_IS_GEN_3P0 +#else + RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */ +#endif /* RADIO_IS_GEN_3P0 */ +} + +xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */ +{ + xcvrStatus_t status; + const xcvr_mode_datarate_config_t * mode_datarate_config; + const xcvr_datarate_config_t * datarate_config ; + const xcvr_mode_config_t * radio_mode_cfg; + const xcvr_common_config_t * radio_common_config; + + status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config ); + + if (status == gXcvrSuccess_c) + { + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, + (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE); + current_xcvr_config.radio_mode = new_radio_mode; + current_xcvr_config.data_rate = new_data_rate; + } + + return status; +} + +void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable ) +{ + if (IIRnbEnable) + { + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; + } + else + { + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; + } +} + +xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) +{ + double integer_used_in_Hz, + integer_used_in_LSB, + numerator_fraction, + numerator_in_Hz, + numerator_in_LSB, + numerator_unrounded, + real_int_and_fraction, + real_fraction, + requested_freq_in_LSB, + sdm_lsb; + uint32_t temp; + static uint32_t integer_truncated, + integer_to_use; + static int32_t numerator_rounded; + + /* Configure for Coarse Tune */ + uint32_t coarse_tune_target = freq / 1000000; + + temp = XCVR_PLL_DIG->CTUNE_CTRL; + temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK; + temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target); + XCVR_PLL_DIG->CTUNE_CTRL = temp; + + /* Calculate the Low Port values */ + sdm_lsb = refOsc / 131072.0; + + real_int_and_fraction = freq / (refOsc * 2.0); + + integer_truncated = (uint32_t) trunc(real_int_and_fraction); + + real_fraction = real_int_and_fraction - integer_truncated; + + if (real_fraction > 0.5) + { + integer_to_use = integer_truncated + 1; + } + else + { + integer_to_use = integer_truncated; + } + + numerator_fraction = real_int_and_fraction - integer_to_use; + + integer_used_in_Hz = integer_to_use * refOsc * 2; + integer_used_in_LSB = integer_used_in_Hz / sdm_lsb; + + numerator_in_Hz = numerator_fraction * refOsc * 2; + numerator_in_LSB = numerator_in_Hz / sdm_lsb; + + requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB; + + numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256; + + numerator_rounded = (int32_t)round(numerator_unrounded); + + /* Write the Low Port Integer and Numerator */ + temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; + temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; + temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK); + XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; + + XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded; + + return gXcvrSuccess_c; +} + +void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */ +{ + s_PanicFunctionPtr = fptr; +} + +void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address) +{ + if ( s_PanicFunctionPtr != NULL) + { + s_PanicFunctionPtr(panic_id, panic_address, 0, 0); + } + else + { + uint8_t dummy; + + while(1) + { + dummy = dummy; + } + } +} + +healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */ +{ + return (healthStatus_t)NO_ERRORS; +} + +void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control) +{ + +} + +/* Helper function to map radio mode to LL usage */ +link_layer_t map_mode_to_ll(radio_mode_t mode) +{ + link_layer_t llret; + switch (mode) + { + case BLE_MODE: + llret = BLE_LL; + break; + case ZIGBEE_MODE: + llret = ZIGBEE_LL; + break; + case ANT_MODE: + llret = ANT_LL; + break; + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + case MSK: + llret = GENFSK_LL; + break; + default: + llret = UNASSIGNED_LL; + break; + } + return llret; +} + +#if RADIO_IS_GEN_3P0 +void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address) +{ + XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address; +} + +uint32_t XCVR_GetBSM_NTW_Address(void) +{ + return XCVR_PHY->NTW_ADR_BSM; +} +#endif /* RADIO_IS_GEN_3P0 */ + +/* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */ +xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping) +{ + link_layer_t int0 = map_mode_to_ll(irq0_mapping); + link_layer_t int1 = map_mode_to_ll(irq1_mapping); + xcvrStatus_t statusret; + /* Make sure the two LL's requested aren't the same */ + if (int0 == int1) + { + statusret = gXcvrInvalidParameters_c; + } + else + { + uint32_t temp; + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK); + temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1)); + XCVR_MISC->XCVR_CTRL = temp; + statusret = gXcvrSuccess_c; + } + return statusret; +} + +/* Get current state of IRQ mapping for either radio INT0 or INT1 */ +link_layer_t XCVR_GetIRQMapping(uint8_t int_num) +{ + if (int_num == 0) + { + return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT); + } + else + { + return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT); + } +} + +/* Get current state of radio mode and data rate */ +xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config) +{ + xcvrStatus_t status = gXcvrInvalidParameters_c; + if (curr_config != NULL) + { + curr_config->radio_mode = current_xcvr_config.radio_mode; + curr_config->data_rate = current_xcvr_config.data_rate; + status = gXcvrSuccess_c; + } + return status; +} + +/* Customer level trim functions */ +xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim) +{ + xcvrStatus_t status = gXcvrInvalidParameters_c; + + if ((xtalTrim & 0x80) == 0) + { + uint32_t temp; + temp = RSIM->ANA_TRIM; + temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK; + RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim); + status = gXcvrSuccess_c; + } + return status; +} + +uint8_t XCVR_GetXtalTrim(void) +{ + uint8_t temp_xtal; + temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT); + return temp_xtal; +} + +/* RSSI adjustment */ +xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj) +{ + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj); + return gXcvrSuccess_c; +} + +int8_t XCVR_GetRssiAdjustment(void) +{ + int8_t adj; + adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT; + return adj; +} + +/* Radio debug functions */ +xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) +{ + uint32_t temp; + + if (channel == 0xFF) + { + /* Clear all of the overrides and restore to LL channel control */ + temp = XCVR_PLL_DIG->CHAN_MAP; + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ +#if RADIO_IS_GEN_3P0 + | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK +#endif /* RADIO_IS_GEN_3P0 */ + ); + + XCVR_PLL_DIG->CHAN_MAP = temp; + + /* Stop using the manual frequency setting */ + XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; + + return gXcvrSuccess_c; + } + + if (channel >= 128) + { + return gXcvrInvalidParameters_c; + } + + if (useMappedChannel) + { + temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */ + + switch (temp) + { +#if !RADIO_IS_GEN_2P1 + case 0x3: /* ANT protocol */ + ANT->CHANNEL_NUM = channel; + break; +#endif /* !RADIO_IS_GEN_2P1 */ + case 0x8: /* GENFSK protocol */ + case 0x9: /* MSK protocol */ + GENFSK->CHANNEL_NUM = channel; + break; + default: /* All other protocols */ + temp = XCVR_PLL_DIG->CHAN_MAP; + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK +#if RADIO_IS_GEN_3P0 + | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK +#endif /* RADIO_IS_GEN_3P0 */ + ); + temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + ); + XCVR_PLL_DIG->CHAN_MAP = temp; + break; + } + } + else + { + XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + ); + + XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c); + XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); + + temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; + temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; + temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer); + XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; + + /* Stop using the LL channel map and use the manual frequency setting */ + XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; + } + + return gXcvrSuccess_c; +} + +uint32_t XCVR_GetFreq ( void ) +{ + uint32_t pll_int; + uint32_t pll_num_unsigned; + int32_t pll_num; + uint32_t pll_denom; + float freq_float; + + if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */ + { + pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >> + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT; + + pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2; + pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3; + } + else + { + /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */ + pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >> + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT; + + pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1; + pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2; + } + + uint32_t freq = 0; + +#if RF_OSC_26MHZ == 1 + uint32_t ref_clk = 26U; +#else + uint32_t ref_clk = 32U; +#endif /* RF_OSC_26MHZ == 1 */ + + /* Check if sign bit is asserted */ + if (pll_num_unsigned & 0x04000000U) + { + /* Sign extend the numerator */ + pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; + + /* Calculate the frequency in MHz */ + freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); + } + else + { + /* Calculate the frequency in MHz */ + pll_num = pll_num_unsigned; + freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); + } + + freq = (uint32_t)freq_float; + + return freq; +} + +void XCVR_ForceRxWu(void) +{ + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK; +} + +void XCVR_ForceRxWd(void) +{ + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK; +} + +void XCVR_ForceTxWu(void) +{ + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +void XCVR_ForceTxWd(void) +{ + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol) +{ + uint32_t temp; + if ((protocol != 6) && (protocol != 7)) + { + return gXcvrInvalidParameters_c; /* Failure */ + } + + if ((rf_channel_freq < 2360) || (rf_channel_freq >2487)) + { + return gXcvrInvalidParameters_c; /* failure */ + } + + /* Set the DFT Mode */ + temp = XCVR_TX_DIG->CTRL; + temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK; + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1); + XCVR_TX_DIG->CTRL = temp; + + /* Choose Protocol 6 or 7 if using the Channel Number register */ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK; + temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol); + XCVR_MISC->XCVR_CTRL = temp; + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(rf_channel_freq-2360,1); + + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + + return gXcvrSuccess_c; /* Success */ +} + +xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern) +{ + uint32_t temp; + uint8_t dft_mode = 0; + uint8_t dft_clk_sel = 0; + xcvrStatus_t status = gXcvrSuccess_c; + + XCVR_ChangeMode(radio_mode, data_rate); + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(channel_num, 1); + + switch (radio_mode) + { + case ZIGBEE_MODE: + dft_mode = 6; /* OQPSK configuration */ + break; + case ANT_MODE: + case BLE_MODE: + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + dft_mode = 2; /* GFSK configuration */ + break; + case MSK: + dft_mode = 4; /* MSK configuration */ + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + + if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ + { + switch (data_rate) + { + case DR_1MBPS: + dft_clk_sel = 4; + break; + case DR_500KBPS: + dft_clk_sel = 3; + break; + case DR_250KBPS: + dft_clk_sel = 2; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + temp = XCVR_TX_DIG->CTRL; + temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK); + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(1) | + XCVR_TX_DIG_CTRL_LFSR_EN(0); + XCVR_TX_DIG->CTRL = temp; + + XCVR_TX_DIG->DFT_PATTERN = tx_pattern; + + if (status == gXcvrSuccess_c) + { + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + } + + return status; +} + +xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length) +{ + uint32_t temp; + uint8_t dft_mode = 0; + uint8_t dft_clk_sel = 0; + xcvrStatus_t status = gXcvrSuccess_c; + uint8_t bitrate_setting = 0xFF; + + if (lfsr_length > 5) + { + return gXcvrInvalidParameters_c; + } + + XCVR_ChangeMode(radio_mode, data_rate); + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(channel_num, 1); + + switch (radio_mode) + { + case ZIGBEE_MODE: + dft_mode = 7; /* OQPSK configuration */ + break; + case ANT_MODE: + case BLE_MODE: + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + dft_mode = 3; /* GFSK configuration */ + bitrate_setting = data_rate; + break; + case MSK: + dft_mode = 5; /* MSK configuration */ + break; + + default: + status = gXcvrInvalidParameters_c; + break; + } + + if (status == gXcvrSuccess_c) + { + switch (data_rate) + { + case DR_1MBPS: + dft_clk_sel = 4; + break; + case DR_500KBPS: + dft_clk_sel = 3; + break; + case DR_250KBPS: + dft_clk_sel = 2; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + if (bitrate_setting < 4) + { + GENFSK->BITRATE = bitrate_setting; + } + + temp = XCVR_TX_DIG->CTRL; + temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | + XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | + XCVR_TX_DIG_CTRL_LFSR_EN_MASK); + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(0) | + XCVR_TX_DIG_CTRL_LFSR_EN(1); + XCVR_TX_DIG->CTRL = temp; + + if (status == gXcvrSuccess_c) + { + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + } + + return status; +} + +void XCVR_DftTxOff(void) +{ + XCVR_ForceTxWd(); + XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */ + /* Clear the RF Channel over-ride */ + XCVR_OverrideChannel(0xFF,1); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */ + XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */ + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */ + XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */ +} + +xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) +{ + if (pa_power > 0x3F) + { + return gXcvrInvalidParameters_c; /* Failure */ + } + + if (pa_power != 1) + { + pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */ + } + + XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */ + XCVR_TSM->PA_POWER = pa_power; + + return gXcvrSuccess_c; /* Success */ +} + +xcvrStatus_t XCVR_CoexistenceInit(void) +{ +#if gMWS_UseCoexistence_d + uint32_t temp = 0x00U; + uint32_t end_of_tx_wu = 0x00U; + uint32_t end_of_rx_wu = 0x00U; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + uint32_t tsm_timing47 = 0x00U; +#else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */ + uint32_t tsm_timing48 = 0x00U; +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + uint32_t tsm_timing50 = 0x00U; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en) + uint32_t tsm_timing48 = 0x00U; + // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en) + uint32_t tsm_timing47 = 0x00U; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + uint16_t tsm_timing43_rx = 0x00; + uint16_t tsm_timing43_tx = 0x00; + + /* Select GPIO mode for FAD pins */ + temp = XCVR_MISC->FAD_CTRL; + temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK); + XCVR_MISC->FAD_CTRL = temp; + + /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ + end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + +/***************** + * TX SEQUENCE * + *****************/ + + if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_tx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Save the TX RF_ACTIVE start time. */ + tsm_timing43_tx = end_of_tx_wu - temp; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#else + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + +/***************** + * RX SEQUENCE * + *****************/ + + if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_rx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Save the RX RF_ACTIVE start time. */ + tsm_timing43_rx = end_of_rx_wu - temp; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); +#else + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ + tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); + +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; +#else + temp = XCVR_TSM->TIMING48; + temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing48; + XCVR_TSM->TIMING48 = temp; +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + temp = XCVR_TSM->TIMING50; + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing50; + XCVR_TSM->TIMING50 = temp; + +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + GPIOC->PDDR |= 0x18; + PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#else + GPIOC->PDDR |= 0x0A; + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + + /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + + /* RF_ACTIVE */ + temp = XCVR_TSM->TIMING48; + temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing48; + XCVR_TSM->TIMING48 = temp; + + /* RF_PRIORITY */ + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; + + /* Overwrite pins settings */ + GPIOC->PDDR |= 0x12; + PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d; + + if (tsm_timing43_tx > end_of_tx_wu - 1) + { + tsm_timing43_tx = end_of_tx_wu - 1; + } + + tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d; + + if (tsm_timing43_rx > end_of_rx_wu - 1) + { + tsm_timing43_rx = end_of_rx_wu - 1; + } + + XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) | + (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | + (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) | + (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)); + + BTLE_RF->MISC_CTRL = 0x02; + + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK; + + /* Save the updated registers values. */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + +xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority) +{ +#if gMWS_UseCoexistence_d + uint32_t temp = 0x00U; + uint32_t end_of_tx_wu = 0x00U; + uint32_t end_of_rx_wu = 0x00U; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + uint32_t tsm_timing50 = 0x00U; +#endif +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + uint32_t tsm_timing47 = 0x00U; +#endif + + /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ + end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + +/***************** + * RX * + *****************/ + + if (XCVR_COEX_HIGH_PRIO == rxPriority) + { + if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_rx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */ + tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */ + tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + else + { + /* Low priority RX */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + +/***************** + * TX * + *****************/ + if (XCVR_COEX_HIGH_PRIO == txPriority) + { + if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_tx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + else + { +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + temp = XCVR_TSM->TIMING50; + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing50; + XCVR_TSM->TIMING50 = temp; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + /* Save the updated registers values. */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + +xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) +{ +#if gMWS_UseCoexistence_d + static uint32_t tsm_ovrd0_saved = 0x00; + static uint32_t tsm_ovrd1_saved = 0x00; + static uint32_t tsm_ovrd2_saved = 0x00; + static uint32_t tsm_ovrd3_saved = 0x00; + static uint32_t tsm_timing47_saved = 0x00; + static uint32_t tsm_timing48_saved = 0x00; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + static uint32_t tsm_timing49_saved = 0x00; + static uint32_t tsm_timing50_saved = 0x00; +#endif + + if (saveTimings == 0) + { + /* Restore registers values. */ + XCVR_TSM->OVRD0 = tsm_ovrd0_saved; + XCVR_TSM->OVRD1 = tsm_ovrd1_saved; + XCVR_TSM->OVRD2 = tsm_ovrd2_saved; + XCVR_TSM->OVRD3 = tsm_ovrd3_saved; + + XCVR_TSM->TIMING47 = tsm_timing47_saved; + XCVR_TSM->TIMING48 = tsm_timing48_saved; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + XCVR_TSM->TIMING49 = tsm_timing49_saved; + XCVR_TSM->TIMING50 = tsm_timing50_saved; +#endif + } + else + { + /* Save registers values. */ + tsm_ovrd0_saved = XCVR_TSM->OVRD0; + tsm_ovrd1_saved = XCVR_TSM->OVRD1; + tsm_ovrd2_saved = XCVR_TSM->OVRD2; + tsm_ovrd3_saved = XCVR_TSM->OVRD3; + tsm_timing47_saved = XCVR_TSM->TIMING47; + tsm_timing48_saved = XCVR_TSM->TIMING48; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing49_saved = XCVR_TSM->TIMING49; + tsm_timing50_saved = XCVR_TSM->TIMING50; +#endif + } +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h new file mode 100644 index 000000000000..c7b7c2b681f8 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -0,0 +1,1247 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _FSL_XCVR_H_ +/* clang-format off */ +#define _FSL_XCVR_H_ +/* clang-format on */ + +#include "fsl_device_registers.h" +#include "fsl_xcvr_trim.h" +#if defined(gMWS_UseCoexistence_d) +#if gMWS_UseCoexistence_d +#include "MWS.h" +#endif /* gMWS_UseCoexistence_d */ +#else +#define gMWS_UseCoexistence_d 0 +#endif /* defined(gMWS_UseCoexistence_d) */ +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* KW4xZ/KW3xZ/KW2xZ Radio type */ +#define RADIO_IS_GEN_2P0 (1) + +/* Default RF OSC definition. Allows for compile time clock frequency definition */ +#ifdef CLOCK_MAIN + +#else +#if RF_OSC_26MHZ == 1 +#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */ +#else +#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ +#endif /* RF_OSC_26MHZ == 1 */ +#endif /* CLOCK_MAIN */ + +#define TBD_ZERO (0) +#define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) + +#define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU) +#define B1(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U) +#define B2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U) +#define B3(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U) + +#define USE_DEFAULT_PRE_REF (0) +#define TRIM_BBA_DCOC_DAC_AT_INIT (1) +#define PRESLOW_ENA (1) + +/* GEN3 TSM defines */ +#if RADIO_IS_GEN_3P0 + +/* TSM timings initializations for Gen3 radio */ +/* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */ +/* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */ +/* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */ +#if RF_OSC_26MHZ == 1 +#define TSM_TIMING00init (0x6d006f00U) /* (bb_ldo_hf_en) */ +#define TSM_TIMING01init (0x6d006f00U) /* (bb_ldo_adcdac_en) */ +#define TSM_TIMING02init (0x6d00ffffU) /* (bb_ldo_bba_en) */ +#define TSM_TIMING03init (0x6d006f00U) /* (bb_ldo_pd_en) */ +#define TSM_TIMING04init (0x6d006f00U) /* (bb_ldo_fdbk_en) */ +#define TSM_TIMING05init (0x6d006f00U) /* (bb_ldo_vcolo_en) */ +#define TSM_TIMING06init (0x6d006f00U) /* (bb_ldo_vtref_en) */ +#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ +#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ +#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ +#define TSM_TIMING10init (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */ +#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ +#define TSM_TIMING12init (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ +#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ +#define TSM_TIMING14init (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */ +#define TSM_TIMING15init (0x6d036f03U) /* (sy_vco_en) */ +#define TSM_TIMING16init (0x6d20ffffU) /* (sy_lo_rx_buf_en) */ +#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ +#define TSM_TIMING18init (0x6d056f05U) /* (sy_divn_en) */ +#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ +#define TSM_TIMING20init (0x6d036f03U) /* (sy_pd_en) */ +#define TSM_TIMING21init (0x6d046f04U) /* (sy_lo_divn_en) */ +#define TSM_TIMING22init (0x6d04ffffU) /* (sy_lo_rx_en) */ +#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ +#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ +#define TSM_TIMING25init (0x6d21ffffU) /* (rx_lna_mixer_en) */ +#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ +#define TSM_TIMING27init (0x6d24ffffU) /* (rx_adc_i_q_en) */ +#define TSM_TIMING28init (0x2524ffffU) /* (rx_adc_reset_en) */ +#define TSM_TIMING29init (0x6d22ffffU) /* (rx_bba_i_q_en) */ +#define TSM_TIMING30init (0x6d24ffffU) /* (rx_bba_pdet_en) */ +#define TSM_TIMING31init (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */ +#define TSM_TIMING32init (0x6d21ffffU) /* (rx_tza_i_q_en) */ +#define TSM_TIMING33init (0x6d24ffffU) /* (rx_tza_pdet_en) */ +#define TSM_TIMING34init (0x6d076f07U) /* (pll_dig_en) */ +#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ +#define TSM_TIMING36init (0x6d6affffU) /* (rx_dig_en) */ +#define TSM_TIMING37init (0x6b6affffU) /* (rx_init) */ +#define TSM_TIMING38init (0x6d0e6f42U) /* (sigma_delta_en) */ +#define TSM_TIMING39init (0x6d6affffU) /* (rx_phy_en) */ +#define TSM_TIMING40init (0x6d2affffU) /* (dcoc_en) */ +#define TSM_TIMING41init (0x2b2affffU) /* (dcoc_init) */ +#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ +#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ +#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ +#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ +#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ +#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ +#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ +#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ +#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ +#define TSM_TIMING51init (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */ +#define TSM_TIMING52init (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */ +#define TSM_TIMING53init (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */ +#define TSM_TIMING54init (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ +#define TSM_TIMING55init (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */ +#define TSM_TIMING56init (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */ +#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ +#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ +#define END_OF_SEQinit (0x6d6c6f67U) /* */ +#define TX_RX_ON_DELinit (0x00008a86U) /* */ +#define TX_RX_SYNTH_init (0x00002318U) /* */ +#else +#define TSM_TIMING00init (0x69006f00U) /* (bb_ldo_hf_en) */ +#define TSM_TIMING01init (0x69006f00U) /* (bb_ldo_adcdac_en) */ +#define TSM_TIMING02init (0x6900ffffU) /* (bb_ldo_bba_en) */ +#define TSM_TIMING03init (0x69006f00U) /* (bb_ldo_pd_en) */ +#define TSM_TIMING04init (0x69006f00U) /* (bb_ldo_fdbk_en) */ +#define TSM_TIMING05init (0x69006f00U) /* (bb_ldo_vcolo_en) */ +#define TSM_TIMING06init (0x69006f00U) /* (bb_ldo_vtref_en) */ +#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ +#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ +#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ +#define TSM_TIMING10init (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */ +#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ +#define TSM_TIMING12init (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ +#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ +#define TSM_TIMING14init (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */ +#define TSM_TIMING15init (0x69036f03U) /* (sy_vco_en) */ +#define TSM_TIMING16init (0x691cffffU) /* (sy_lo_rx_buf_en) */ +#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ +#define TSM_TIMING18init (0x69056f05U) /* (sy_divn_en) */ +#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ +#define TSM_TIMING20init (0x69036f03U) /* (sy_pd_en) */ +#define TSM_TIMING21init (0x69046f04U) /* (sy_lo_divn_en) */ +#define TSM_TIMING22init (0x6904ffffU) /* (sy_lo_rx_en) */ +#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ +#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ +#define TSM_TIMING25init (0x691dffffU) /* (rx_lna_mixer_en) */ +#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ +#define TSM_TIMING27init (0x6920ffffU) /* (rx_adc_i_q_en) */ +#define TSM_TIMING28init (0x2120ffffU) /* (rx_adc_reset_en) */ +#define TSM_TIMING29init (0x691effffU) /* (rx_bba_i_q_en) */ +#define TSM_TIMING30init (0x6920ffffU) /* (rx_bba_pdet_en) */ +#define TSM_TIMING31init (0x691fffffU) /* (rx_bba_tza_dcoc_en) */ +#define TSM_TIMING32init (0x691dffffU) /* (rx_tza_i_q_en) */ +#define TSM_TIMING33init (0x6920ffffU) /* (rx_tza_pdet_en) */ +#define TSM_TIMING34init (0x69076f07U) /* (pll_dig_en) */ +#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ +#define TSM_TIMING36init (0x6966ffffU) /* (rx_dig_en) */ +#define TSM_TIMING37init (0x6766ffffU) /* (rx_init) */ +#define TSM_TIMING38init (0x690e6f42U) /* (sigma_delta_en) */ +#define TSM_TIMING39init (0x6966ffffU) /* (rx_phy_en) */ +#define TSM_TIMING40init (0x6926ffffU) /* (dcoc_en) */ +#define TSM_TIMING41init (0x2726ffffU) /* (dcoc_init) */ +#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ +#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ +#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ +#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ +#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ +#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ +#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ +#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ +#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ +#define TSM_TIMING51init (0x6903ffffU) /* (rxtx_auxpll_bias_en) */ +#define TSM_TIMING52init (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */ +#define TSM_TIMING53init (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */ +#define TSM_TIMING54init (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ +#define TSM_TIMING55init (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */ +#define TSM_TIMING56init (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */ +#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ +#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ +#define END_OF_SEQinit (0x69686f67U) /* */ +#define TX_RX_ON_DELinit (0x00008a86U) /* */ +#define TX_RX_SYNTH_init (0x00002318U) /* */ +#endif /* RF_OSC_26MHZ == 1 */ + +#define AUX_PLL_DELAY (0) +/* TSM bitfield shift and value definitions */ +#define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */ +#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ +/* EDIT THIS LINE TO CONTROL PA_RAMP! */ +#define PA_RAMP_TIME (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */ +#define PA_RAMP_SEL_0US (0) +#define PA_RAMP_SEL_1US (1) +#define PA_RAMP_SEL_2US (2) +#define PA_RAMP_SEL_4US (3) +#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4)) +#error "Invalid value for PA_RAMP_TIME macro" +#endif /* Error check of PA RAMP TIME */ + +#define ADD_FOR_26MHZ (4) +#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ +/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ +#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) + #if (PA_RAMP_TIME == 0) + #define PA_RAMP_SEL PA_RAMP_SEL_0US + #define DATA_PADDING_EN (0) + #else + #define DATA_PADDING_EN (1) + #if (PA_RAMP_TIME == 1) + #define PA_RAMP_SEL PA_RAMP_SEL_1US + #else + #define PA_RAMP_SEL PA_RAMP_SEL_2US + #endif /* (PA_RAMP_TIME == 1) */ + #endif /* (PA_RAMP_TIME == 0) */ +#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */ + #if (PA_RAMP_TIME == 4) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) + #define PA_RAMP_SEL PA_RAMP_SEL_4US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME == 4) */ + #error "Invalid value for PA_RAMP_TIME macro" + #endif /* (PA_RAMP_TIME == 4) */ +#endif/* (PA_RAMP_TIME == 4) */ + +#define END_OF_RX_WU (104 + AUX_PLL_DELAY) + +#if RF_OSC_26MHZ == 1 +#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ +#else +#define END_OF_RX_WD (END_OF_RX_WU + 1) +#endif /* RF_OSC_26MHZ == 1 */ + +#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) +#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) + +/* PA Bias Table - Gen3 version */ +#define PA_RAMP_0 0x1 +#define PA_RAMP_1 0x2 +#define PA_RAMP_2 0x4 +#define PA_RAMP_3 0x6 +#define PA_RAMP_4 0x8 +#define PA_RAMP_5 0xc +#define PA_RAMP_6 0x10 +#define PA_RAMP_7 0x14 +#define PA_RAMP_8 0x18 +#define PA_RAMP_9 0x1c +#define PA_RAMP_10 0x22 +#define PA_RAMP_11 0x28 +#define PA_RAMP_12 0x2c +#define PA_RAMP_13 0x30 +#define PA_RAMP_14 0x36 +#define PA_RAMP_15 0x3c + +#else /* Gen2 TSM definitions */ +/* GEN2 TSM defines */ +#define AUX_PLL_DELAY (0) +/* TSM bitfield shift and value definitions */ +#define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */ +#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ +/* EDIT THIS LINE TO CONTROL PA_RAMP! */ +#define PA_RAMP_TIME (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */ +#define PA_RAMP_SEL_0US (0) +#define PA_RAMP_SEL_2US (1) +#define PA_RAMP_SEL_4US (2) +#define PA_RAMP_SEL_8US (3) + +#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8)) +#error "Invalid value for PA_RAMP_TIME macro" +#endif /* Error check of PA RAMP TIME */ +#define ADD_FOR_26MHZ (4) +#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ +/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ +#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) + #define TX_SYNTH_DELAY_ADJ (0) + #define PD_CYCLE_SLIP_TX_HI_ADJ (0) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */ + #if (PA_RAMP_TIME == 0) + #define PA_RAMP_SEL PA_RAMP_SEL_0US + #define DATA_PADDING_EN (0) + #define TX_DIG_EN_TX_HI_ADJ (-2) + #else + #define DATA_PADDING_EN (1) + #define TX_DIG_EN_TX_HI_ADJ (0) + #define PA_RAMP_SEL PA_RAMP_SEL_2US + #endif /* (PA_RAMP_TIME == 0) */ +#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ + #if (PA_RAMP_TIME == 4) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) + #define TX_SYNTH_DELAY_ADJ (2) + #define PD_CYCLE_SLIP_TX_HI_ADJ (2) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define TX_DIG_EN_TX_HI_ADJ (0) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */ + #define PA_RAMP_SEL PA_RAMP_SEL_4US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME==4) */ + #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 6) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 12) + #define TX_SYNTH_DELAY_ADJ (6) + #define PD_CYCLE_SLIP_TX_HI_ADJ (6) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define TX_DIG_EN_TX_HI_ADJ (4) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */ + #define PA_RAMP_SEL PA_RAMP_SEL_8US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME == 8) */ + #error "Invalid value for PA_RAMP_TIME macro" + #endif /* (PA_RAMP_TIME == 8) */ + #endif/* (PA_RAMP_TIME == 4) */ +#endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ + +#define TX_DIG_EN_ASSERT_MSK500 (END_OF_TX_WU - 3) + +#define END_OF_RX_WU (104 + AUX_PLL_DELAY) +#if RF_OSC_26MHZ == 1 +#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ +#else +#define END_OF_RX_WD (END_OF_RX_WU + 1) +#endif /* RF_OSC_26MHZ == 1 */ +#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) +#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) + +/* PA Bias Table */ +#define PA_RAMP_0 0x1 +#define PA_RAMP_1 0x2 +#define PA_RAMP_2 0x4 +#define PA_RAMP_3 0x8 +#define PA_RAMP_4 0xe +#define PA_RAMP_5 0x16 +#define PA_RAMP_6 0x22 +#define PA_RAMP_7 0x2e + +/* BLE LL timing definitions */ +#define TX_ON_DELAY (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */ +#define RX_ON_DELAY (29 + END_OF_RX_WU+4) +#define RX_ON_DELAY_26MHZ (29 + END_OF_RX_WU_26MHZ+4) +#define TX_RX_ON_DELAY_VAL (TX_ON_DELAY << 8 | RX_ON_DELAY) +#define TX_RX_ON_DELAY_VAL_26MHZ (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ) +#define TX_SYNTH_DELAY (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */ +#define RX_SYNTH_DELAY (0x18) +#define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY) + +/* PHY reference waveform assembly */ +#define RW0PS(loc, val) (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */ +#define RW1PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */ +#define RW2PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */ +#endif /* RADIO_IS_GEN_3P0 */ + +/*! @brief Error codes for the XCVR driver. */ +typedef enum _xcvrStatus +{ + gXcvrSuccess_c = 0, + gXcvrInvalidParameters_c, + gXcvrUnsupportedOperation_c, + gXcvrTrimFailure_c +} xcvrStatus_t; + +/*! @brief Health status returned from PHY upon status check function return. */ +typedef enum _healthStatus +{ + NO_ERRORS = 0, + PLL_CTUNE_FAIL = 1, + PLL_CYCLE_SLIP_FAIL = 2, + PLL_FREQ_TARG_FAIL = 4, + PLL_TSM_ABORT_FAIL = 8, +} healthStatus_t; + +/*! @brief Health status returned from PHY upon status check function return. */ +typedef enum _ext_clock_config +{ + EXT_CLK_32_MHZ = 0, + EXT_CLK_26_MHZ = 1, +} ext_clock_config_t; + +/*! @brief Radio operating mode setting types. */ +typedef enum _radio_mode +{ + BLE_MODE = 0, + ZIGBEE_MODE = 1, + ANT_MODE = 2, + + /* BT=0.5, h=** */ + GFSK_BT_0p5_h_0p5 = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */ + GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/ + GFSK_BT_0p5_h_0p7 = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */ + GFSK_BT_0p5_h_1p0 = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */ + + /* BT=** h=0.5 */ + GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */ + GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */ + + MSK = 9, + NUM_RADIO_MODES = 10, +} radio_mode_t; + +/*! @brief Link layer types. */ +typedef enum _link_layer +{ + BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */ + ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */ + ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */ + GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */ + UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */ +} link_layer_t; + +/*! @brief Data rate selections. */ +typedef enum _data_rate +{ + DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ + DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ + DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */ +#if RADIO_IS_GEN_3P0 + DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */ +#endif /* RADIO_IS_GEN_3P0 */ + DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ +} data_rate_t; + +/*! @brief Control settings for Fast Antenna Diversity */ +typedef enum _FAD_LPPS_CTRL +{ + NONE = 0, + FAD_ENABLED = 1, + LPPS_ENABLED = 2 +} FAD_LPPS_CTRL_T; + +/*! @brief XCVR Panic codes for indicating panic reason. */ +typedef enum _XCVR_PANIC_ID +{ + WRONG_RADIO_ID_DETECTED = 1, + CALIBRATION_INVALID = 2, + RADIO_INIT_FAILURE = 3, +} XCVR_PANIC_ID_T; + +/*! @brief Initialization or mode change selection for config routine. */ +typedef enum _XCVR_INIT_MODE_CHG +{ + XCVR_MODE_CHANGE = 0, + XCVR_FIRST_INIT = 1, +} XCVR_INIT_MODE_CHG_T; + +/*! @brief Coexistence arbitration priority settings. */ +typedef enum _XCVR_COEX_PRIORITY +{ + XCVR_COEX_LOW_PRIO = 0, + XCVR_COEX_HIGH_PRIO = 1 +} XCVR_COEX_PRIORITY_T; + +/*! @brief Current configuration of the radio. */ +typedef struct xcvr_currConfig_tag +{ + radio_mode_t radio_mode; + data_rate_t data_rate; +} xcvr_currConfig_t; + +/*! + * @brief XCVR RX_DIG channel filter coefficient storage + * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage. + */ +typedef struct _xcvr_rx_chf_coeffs +{ + uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */ +} xcvr_rx_chf_coeffs_t; + +/*! + * @brief XCVR masked init type for 32 bit registers + * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position. + */ +typedef struct _xcvr_masked_init_32 +{ + uint32_t mask; + uint32_t init; +} xcvr_masked_init_32_t; + +/*! + * @brief XCVR common configure structure + */ +typedef struct _xcvr_common_config +{ + /* XCVR_ANA configs */ + xcvr_masked_init_32_t ana_sy_ctrl1; + + /* XCVR_PLL_DIG configs */ + uint32_t pll_hpm_bump; + uint32_t pll_mod_ctrl; + uint32_t pll_chan_map; + uint32_t pll_lock_detect; + uint32_t pll_hpm_ctrl; +#if !RADIO_IS_GEN_2P1 + uint32_t pll_hpmcal_ctrl; +#endif /* !RADIO_IS_GEN_2P1 */ + uint32_t pll_hpm_sdm_res; + uint32_t pll_lpm_ctrl; + uint32_t pll_lpm_sdm_ctrl1; + uint32_t pll_delay_match; + uint32_t pll_ctune_ctrl; + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init; + uint32_t dcoc_cal_gain_init; + uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */ + uint32_t dcoc_cal_rcp_init; + uint32_t lna_gain_val_3_0; + uint32_t lna_gain_val_7_4; + uint32_t lna_gain_val_8; + uint32_t bba_res_tune_val_7_0; + uint32_t bba_res_tune_val_10_8; + uint32_t lna_gain_lin_val_2_0_init; + uint32_t lna_gain_lin_val_5_3_init; + uint32_t lna_gain_lin_val_8_6_init; + uint32_t lna_gain_lin_val_9_init; + uint32_t bba_res_tune_lin_val_3_0_init; + uint32_t bba_res_tune_lin_val_7_4_init; + uint32_t bba_res_tune_lin_val_10_8_init; + uint32_t dcoc_bba_step_init; + uint32_t dcoc_tza_step_00_init; + uint32_t dcoc_tza_step_01_init; + uint32_t dcoc_tza_step_02_init; + uint32_t dcoc_tza_step_03_init; + uint32_t dcoc_tza_step_04_init; + uint32_t dcoc_tza_step_05_init; + uint32_t dcoc_tza_step_06_init; + uint32_t dcoc_tza_step_07_init; + uint32_t dcoc_tza_step_08_init; + uint32_t dcoc_tza_step_09_init; + uint32_t dcoc_tza_step_10_init; +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + uint32_t dcoc_cal_fail_th_init; + uint32_t dcoc_cal_pass_th_init; +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ + uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ + uint32_t agc_ctrl_3_init; + /* Other agc config inits are in the modeXdatarate config table */ + uint32_t agc_gain_tbl_03_00_init; + uint32_t agc_gain_tbl_07_04_init; + uint32_t agc_gain_tbl_11_08_init; + uint32_t agc_gain_tbl_15_12_init; + uint32_t agc_gain_tbl_19_16_init; + uint32_t agc_gain_tbl_23_20_init; + uint32_t agc_gain_tbl_26_24_init; + uint32_t rssi_ctrl_0_init; +#if RADIO_IS_GEN_3P0 + uint32_t rssi_ctrl_1_init; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t cca_ed_lqi_ctrl_0_init; + uint32_t cca_ed_lqi_ctrl_1_init; + + /* XCVR_TSM configs */ + uint32_t tsm_ctrl; + uint32_t tsm_ovrd2_init; + uint32_t end_of_seq_init_26mhz; + uint32_t end_of_seq_init_32mhz; +#if !RADIO_IS_GEN_2P1 + uint32_t lpps_ctrl_init; +#endif /* !RADIO_IS_GEN_2P1 */ + uint32_t tsm_fast_ctrl2_init_26mhz; + uint32_t tsm_fast_ctrl2_init_32mhz; + uint32_t recycle_count_init_26mhz; + uint32_t recycle_count_init_32mhz; + uint32_t pa_ramp_tbl_0_init; + uint32_t pa_ramp_tbl_1_init; +#if RADIO_IS_GEN_3P0 + uint32_t pa_ramp_tbl_2_init; + uint32_t pa_ramp_tbl_3_init; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t tsm_timing_00_init; + uint32_t tsm_timing_01_init; + uint32_t tsm_timing_02_init; + uint32_t tsm_timing_03_init; + uint32_t tsm_timing_04_init; + uint32_t tsm_timing_05_init; + uint32_t tsm_timing_06_init; + uint32_t tsm_timing_07_init; + uint32_t tsm_timing_08_init; + uint32_t tsm_timing_09_init; + uint32_t tsm_timing_10_init; + uint32_t tsm_timing_11_init; + uint32_t tsm_timing_12_init; + uint32_t tsm_timing_13_init; + uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ + uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ + uint32_t tsm_timing_15_init; + uint32_t tsm_timing_16_init_26mhz; + uint32_t tsm_timing_16_init_32mhz; + uint32_t tsm_timing_17_init; + uint32_t tsm_timing_18_init; + uint32_t tsm_timing_19_init; + uint32_t tsm_timing_20_init; + uint32_t tsm_timing_21_init; + uint32_t tsm_timing_22_init; + uint32_t tsm_timing_23_init; + uint32_t tsm_timing_24_init; + uint32_t tsm_timing_25_init_26mhz; + uint32_t tsm_timing_25_init_32mhz; + uint32_t tsm_timing_26_init; + uint32_t tsm_timing_27_init_26mhz; + uint32_t tsm_timing_27_init_32mhz; + uint32_t tsm_timing_28_init_26mhz; + uint32_t tsm_timing_28_init_32mhz; + uint32_t tsm_timing_29_init_26mhz; + uint32_t tsm_timing_29_init_32mhz; + uint32_t tsm_timing_30_init_26mhz; + uint32_t tsm_timing_30_init_32mhz; + uint32_t tsm_timing_31_init_26mhz; + uint32_t tsm_timing_31_init_32mhz; + uint32_t tsm_timing_32_init_26mhz; + uint32_t tsm_timing_32_init_32mhz; + uint32_t tsm_timing_33_init_26mhz; + uint32_t tsm_timing_33_init_32mhz; + uint32_t tsm_timing_34_init; + uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/ + uint32_t tsm_timing_36_init_26mhz; + uint32_t tsm_timing_36_init_32mhz; + uint32_t tsm_timing_37_init_26mhz; + uint32_t tsm_timing_37_init_32mhz; + uint32_t tsm_timing_38_init; + uint32_t tsm_timing_39_init_26mhz; + uint32_t tsm_timing_39_init_32mhz; + uint32_t tsm_timing_40_init_26mhz; + uint32_t tsm_timing_40_init_32mhz; + uint32_t tsm_timing_41_init_26mhz; + uint32_t tsm_timing_41_init_32mhz; + uint32_t tsm_timing_51_init; + uint32_t tsm_timing_52_init_26mhz; + uint32_t tsm_timing_52_init_32mhz; + uint32_t tsm_timing_53_init; + uint32_t tsm_timing_54_init_26mhz; + uint32_t tsm_timing_54_init_32mhz; + uint32_t tsm_timing_55_init_26mhz; + uint32_t tsm_timing_55_init_32mhz; + uint32_t tsm_timing_56_init_26mhz; + uint32_t tsm_timing_56_init_32mhz; + uint32_t tsm_timing_57_init; + uint32_t tsm_timing_58_init; + + /* XCVR_TX_DIG configs */ + uint32_t tx_ctrl; + uint32_t tx_data_padding; + uint32_t tx_dft_pattern; +#if !RADIO_IS_GEN_2P1 + uint32_t rf_dft_bist_1; + uint32_t rf_dft_bist_2; +#endif /* !RADIO_IS_GEN_2P1 */ +} xcvr_common_config_t; + +/*! @brief XCVR mode specific configure structure (varies by radio mode) */ +typedef struct _xcvr_mode_config +{ + radio_mode_t radio_mode; + uint32_t scgc5_clock_ena_bits; + + /* XCVR_MISC configs */ + xcvr_masked_init_32_t xcvr_ctrl; + + /* XCVR_PHY configs */ +#if RADIO_IS_GEN_3P0 + uint32_t phy_fsk_pd_cfg0; + uint32_t phy_fsk_pd_cfg1; + uint32_t phy_fsk_cfg; + uint32_t phy_fsk_misc; + uint32_t phy_fad_ctrl; +#else + uint32_t phy_pre_ref0_init; + uint32_t phy_pre_ref1_init; + uint32_t phy_pre_ref2_init; + uint32_t phy_cfg1_init; + uint32_t phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are in the data_rate specific configuration */ +#endif /* RADIO_IS_GEN_3P0 */ + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + + /* XCVR_TSM configs */ +#if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) + uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */ +#endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */ + + /* XCVR_TX_DIG configs */ + uint32_t tx_gfsk_ctrl; + uint32_t tx_gfsk_coeff1_26mhz; + uint32_t tx_gfsk_coeff2_26mhz; + uint32_t tx_gfsk_coeff1_32mhz; + uint32_t tx_gfsk_coeff2_32mhz; +} xcvr_mode_config_t; + +/*! + * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate) + * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay + * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. + */ +typedef struct _xcvr_mode_datarate_config +{ + radio_mode_t radio_mode; + data_rate_t data_rate; + + /* XCVR_ANA configs */ + xcvr_masked_init_32_t ana_sy_ctrl2; + xcvr_masked_init_32_t ana_rx_bba; + xcvr_masked_init_32_t ana_rx_tza; + + /* XCVR_PHY configs */ +#if RADIO_IS_GEN_3P0 + uint32_t phy_fsk_misc_mode_datarate; +#else + uint32_t phy_cfg2_init; +#endif /* RADIO_IS_GEN_3P0 */ + + uint32_t agc_ctrl_2_init_26mhz; + uint32_t agc_ctrl_2_init_32mhz; + xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */ + xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */ + uint32_t rx_rccal_ctrl_0; + uint32_t rx_rccal_ctrl_1; + + /* XCVR_TX_DIG configs */ + uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */ + uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */ +} xcvr_mode_datarate_config_t; + +/*! + * @brief XCVR datarate specific configure structure (varies by data rate) + * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay + * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. + */ +typedef struct _xcvr_datarate_config +{ + data_rate_t data_rate; + + /* XCVR_PHY configs */ + uint32_t phy_el_cfg_init; /* Note: EL_ENABLE is set in xcvr_mode_config_t settings */ + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t agc_ctrl_1_init_26mhz; + uint32_t agc_ctrl_1_init_32mhz; + uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ + uint32_t dcoc_ctrl_2_init_26mhz; + uint32_t dcoc_ctrl_2_init_32mhz; + uint32_t dcoc_cal_iir_init_26mhz; + uint32_t dcoc_cal_iir_init_32mhz; + uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ + uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ +} xcvr_datarate_config_t; + +/*! + * @brief LPUART callback function type + * + * The panic callback function is defined by system if system need to be informed of XCVR fatal errors. + * refer to #XCVR_RegisterPanicCb + */ +typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2); + +/* Make available const structures from config files */ +extern const xcvr_common_config_t xcvr_common_config; +extern const xcvr_mode_config_t zgbe_mode_config; +extern const xcvr_mode_config_t ble_mode_config; +extern const xcvr_mode_config_t ant_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config; +extern const xcvr_mode_config_t msk_mode_config; + +#if RADIO_IS_GEN_3P0 +extern const xcvr_datarate_config_t xcvr_2mbps_config; +#endif /* RADIO_IS_GEN_3P0 */ +extern const xcvr_datarate_config_t xcvr_1mbps_config; +extern const xcvr_datarate_config_t xcvr_500kbps_config; +extern const xcvr_datarate_config_t xcvr_250kbps_config; +extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */ + +#if RADIO_IS_GEN_3P0 +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config; +#endif /* RADIO_IS_GEN_3P0 */ +extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name XCVR functional Operation + * @{ + */ + +/*! + * @brief Initializes an XCVR instance. + * + * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to + * start up the XCVR in most situations. + * + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions. + */ +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); + +/*! + * @brief Deinitializes an XCVR instance. + * + * This function gate the XCVR module clock and set all register value to reset value. + * + */ +void XCVR_Deinit(void); + +/*! + * @brief Initializes XCVR configure structure. + * + * This function updates pointers to the XCVR configure structures with default values. + * The configurations are divided into a common structure, a set of radio mode specific + * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at + * each datarate), and a set of data rate specific structures. + * The pointers provided by this routine point to const structures which can be + * copied to variable structures if changes to settings are required. + * + * @param radio_mode [in] The radio mode for which the configuration structures are requested. + * @param data_rate [in] The data rate for which the configuration structures are requested. + * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure. + * @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure. + * @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure. + * @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure. + * @return 0 success, others failure + * @see XCVR_Configure + */ +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, + const xcvr_datarate_config_t ** datarate_config); + +/*! + * @brief Initializes an XCVR instance. + * + * This function initializes the XCVR module with user-defined settings. + * + * @param com_config Pointer to the common configuration settings structure. + * @param mode_config Pointer to the mode specific configuration settings structure. + * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure. + * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure. + * @param tempDegC temperature of the die in degrees C. + * @param ext_clk indicates the external clock setting, 32MHz or 26MHz. + * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) + * @return 0 succeed, others failed + */ +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, + XCVR_INIT_MODE_CHG_T first_init); + +/*! + * @brief Set XCVR register to reset value. + * + * This function set XCVR register to the reset value. + * + */ +void XCVR_Reset(void); + +/*! + * @brief Change the operating mode of the radio. + * + * This function changes the XCVR to a new radio operating mode. + * + * @param new_radio_mode The radio mode for which the XCVR should be configured. + * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @return status of the mode change. + */ + xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate); + +/*! + * @brief Enable Narrowband RSSI measurement. + * + * This function enables the narrowband RSSI measurement + * + * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled. + */ +void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable); + +/*! + * @brief Set an arbitrary frequency for RX and TX for the radio. + * + * This function sets the radio frequency used for RX and RX.. + * + * @param freq target frequency setting in Hz. + * @param refOsc reference oscillator setting in Hz. + * @return status of the frequency change. + * @details + */ + xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc); + +/*! + * @brief Register a callback from upper layers. + * + * This function registers a callback from the upper layers for the radio to call in case of fatal errors. + * + * @param fptr The function pointer to a panic callback. + */ +void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */ + +/*! + * @brief Read the health status of the XCVR to detect errors. + * + * This function enables the upper layers to request the current radio health. + * + * @return The health status of the radio.. + */ +healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */ + +/*! + * @brief Control FAD and LPPS features. + * + * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search. + * + * @param fptr control the FAD and LPPS settings. + * + */ + void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control); + +/*! + * @brief Change the mapping of the radio IRQs. + * + * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. + * + * @param irq0_mapping the LL which should be mapped to the INT0 line. + * @param irq1_mapping the LL which should be mapped to the INT1 line. + * @return status of the mapping request. + * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line. + * @warning + * The same LL must NOT be mapped to both INT lines. + */ + xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping); + +#if RADIO_IS_GEN_3P0 +/*! + * @brief Sets the network address used by the PHY during BLE Bit Streaming Mode. + * + * This function programs the register in the PHY which contains the network address used during BSM. + * + * @param bsm_ntw_address the address to be used during BSM. + * @ note This routine does NOT enable BSM. + */ +void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address); + +/*! + * @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode. + * + * This function reads the register in the PHY which contains the network address used during BSM. + * + * @return bsm_ntw_address the address to be used during BSM. + * @ note This routine does NOT enable BSM. + */ +uint32_t XCVR_GetBSM_NTW_Address(void); +#endif /* RADIO_IS_GEN_3P0 */ + +/*! + * @brief Get the mapping of the one of the radio IRQs. + * + * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. + * + * @param int_num the number, 0 or 1, of the INT line to fetched. + * @return the mapping setting of the specified line. + * @note Any value passed into this routine other than 0 will be treated as a 1. + */ + link_layer_t XCVR_GetIRQMapping(uint8_t int_num); + +/*! + * @brief Get the current configuration of the XCVR. + * + * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc + * + * @param curr_config pointer to a structure to be updated with the current mode and data rate. + * @return the status of the request, success or invalid parameter (null pointer). + * @note This API will return meaningless results if called before the radio is initialized... + */ +xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config); + +/******************************************************************************* + * Customer level trim functions + ******************************************************************************/ +/*! + * @brief Controls setting the XTAL trim value.. + * + * This function enables the upper layers set a crystal trim compensation facor + * + * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error. + * @return The health status of the radio.. + */ +xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); + +/*! + * @brief Controls getting the XTAL trim value.. + * + * This function enables the upper layers to read the current XTAL compensation factors. + * The returned value is in the range 0..127 (7 bits). + * + * @return The XTAL trim compensation factors.. + */ +uint8_t XCVR_GetXtalTrim(void); + +/*! + * @brief Controls setting the RSSI adjustment.. + * + * This function enables the upper layers to set an RSSI adjustment value. + * + * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step. + * @return The health status of the radio.. + */ +xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); + +/*! + * @brief Controls getting the RSSI adjustment.. + * + * This function enables the upper layers to read the current XCVR RSSI adjustment value. + * The returned value is a signed 8-bit value, in 1/4 dBm step. + * + * @return The RSSI adjustment value.. + */ +int8_t XCVR_GetRssiAdjustment(void); + +/*! + * @brief Controls setting the PLL to a particular channel. + * + * This function enables setting the radio channel for TX and RX. + * + * @param channel the channel number to set + * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. + * @return The status of the channel over-ride. + */ +xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); + +/*! + * @brief Reads the current frequency for RX and TX for the radio. + * + * This function reads the radio frequency used for RX and RX.. + * + * @return Current radio frequency setting. + */ +uint32_t XCVR_GetFreq(void); + +/*! + * @brief Force receiver warmup. + * + * This function forces the initiation of a receiver warmup sequence. + * + */ +void XCVR_ForceRxWu(void); + +/*! + * @brief Force receiver warmdown. + * + * This function forces the initiation of a receiver warmdown sequence. + * + */ + void XCVR_ForceRxWd(void); + +/*! + * @brief Force transmitter warmup. + * + * This function forces the initiation of a transmit warmup sequence. + * + */ +void XCVR_ForceTxWu(void); + +/*! + * @brief Force transmitter warmdown. + * + * This function forces the initiation of a transmit warmdown sequence. + * + */ +void XCVR_ForceTxWd(void); + +/*! + * @brief Starts transmit with a TX pattern register data sequence. + * + * This function starts transmitting using the DFT pattern register mode. + * + * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @param tx_pattern - the data pattern to transmit on. + * @return The status of the pattern reg transmit. + * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode + * and data rate. + */ +xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); + +/*! + * @brief Starts transmit with a TX LFSR register data sequence. + * + * This function starts transmitting using the DFT LFSR register mode. + * + * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @param lfsr_length - the length of the LFSR sequence to use. + * @return The status of the LFSR reg transmit. + * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode + * and data rate. + */ +xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); + +/*! + * @brief Controls clearing all TX DFT settings. + * + * This function reverts all TX DFT settings from the test modes to normal operating mode. + * + */ +void XCVR_DftTxOff(void); + +/*! + * @brief Controls setting the PA power level. + * + * This function enables setting the PA power level to a specific setting, overriding any link layer settings. + * + * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. + * @return The status of the PA power over-ride. + */ +xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); + +/*! + * @brief Starts CW TX. + * + * This function starts transmitting CW (no modulation). + * + * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. + * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). + * @return The status of the CW transmit. + */ +xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); + +xcvrStatus_t XCVR_CoexistenceInit(void); +xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority); +xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_XCVR_H_ */ + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c new file mode 100644 index 000000000000..40486b1d18d6 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c @@ -0,0 +1,213 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t ant_mode_config = +{ + .radio_mode = ANT_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK +#if !RADIO_IS_GEN_2P1 + | SIM_SCGC5_ANT_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = RW0PS(0, 0x1B) | + RW0PS(1, 0x1CU) | + RW0PS(2, 0x1CU) | + RW0PS(3, 0x1CU) | + RW0PS(4, 0x1DU) | + RW0PS(5, 0x1DU) | + RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/ + .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1EU) | + RW1PS(11, 0x1DU) | + RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */ + RW2PS(13, 0x1CU) | + RW2PS(14, 0x1CU) | + RW2PS(15, 0x1CU), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xF8) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = +{ + .radio_mode = ANT_MODE, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, + + /* ANT 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c new file mode 100644 index 000000000000..c38f50831903 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c @@ -0,0 +1,207 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t ble_mode_config = +{ + .radio_mode = BLE_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = RW0PS(0, 0x19) | + RW0PS(1, 0x19U) | + RW0PS(2, 0x1AU) | + RW0PS(3, 0x1BU) | + RW0PS(4, 0x1CU) | + RW0PS(5, 0x1CU) | + RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ + .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1DU) | + RW1PS(11, 0x1CU) | + RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ + RW2PS(13, 0x1BU) | + RW2PS(14, 0x1AU) | + RW2PS(15, 0x19U), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(220) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = +{ + .radio_mode = BLE_MODE, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* BLE 26MHz Channel Filter */ + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, + + /* BLE 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c new file mode 100644 index 000000000000..305b5e466f91 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c @@ -0,0 +1,629 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_common_config_t xcvr_common_config = +{ + /* XCVR_ANA configs */ + .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK, + .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */ + +#define hpm_vcm_tx 0 +#define hpm_vcm_cal 1 +#define hpm_fdb_res_tx 0 +#define hpm_fdb_res_cal 1 +#define modulation_word_manual 0 +#define mod_disable 0 +#define hpm_mod_manual 0 +#define hpm_mod_disable 0 +#define hpm_sdm_out_manual 0 +#define hpm_sdm_out_disable 0 +#define channel_num 0 +#define boc 0 +#define bmr 1 +#define zoc 0 +#define ctune_ldf_lev 8 +#define ftf_rx_thrsh 33 +#define ftw_rx 0 +#define ftf_tx_thrsh 6 +#define ftw_tx 0 +#define freq_count_go 0 +#define freq_count_time 0 +#define hpm_sdm_in_manual 0 +#define hpm_sdm_out_invert 0 +#define hpm_sdm_in_disable 0 +#define hpm_lfsr_size 4 +#define hpm_dth_scl 0 +#define hpm_dth_en 1 +#define hpm_integer_scale 0 +#define hpm_integer_invert 0 +#define hpm_cal_invert 1 +#define hpm_mod_in_invert 1 +#define hpm_cal_not_bumped 0 +#define hpm_cal_count_scale 0 +#define hp_cal_disable 0 +#define hpm_cal_factor_manual 0 +#define hpm_cal_array_size 1 +#define hpm_cal_time 0 +#define hpm_sdm_denom 256 +#define hpm_count_adjust 0 +#define pll_ld_manual 0 +#define pll_ld_disable 0 +#define lpm_sdm_inv 0 +#define lpm_disable 0 +#define lpm_dth_scl 8 +#define lpm_d_ctrl 1 +#define lpm_d_ovrd 1 +#define lpm_scale 8 +#define lpm_sdm_use_neg 0 +#define hpm_array_bias 0 +#define lpm_intg 38 +#define sdm_map_disable 0 +#define lpm_sdm_delay 4 +#define hpm_sdm_delay 0 +#define hpm_integer_delay 0 +#define ctune_target_manual 0 +#define ctune_target_disable 0 +#define ctune_adjust 0 +#define ctune_manual 0 +#define ctune_disable 0 + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) | + XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) | + XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) | + XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) | + XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | + XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) | + XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) | + XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) | + XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) | + XCVR_PLL_DIG_CHAN_MAP_BOC(boc) | + XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num) +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc) +#endif /* !RADIO_IS_GEN_2P1 */ + , + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) | + XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) | + XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) | + XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) | + XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) | + XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) | + XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) | + XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) | + XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) | + XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) | + XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert), +/*-------------------------------------------------------------------------------------------------*/ +#if !RADIO_IS_GEN_2P1 + .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time), +#endif /* !RADIO_IS_GEN_2P1 */ +/*-------------------------------------------------------------------------------------------------*/ + .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) | + XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom), +/*-------------------------------------------------------------------------------------------------*/ + .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) | + XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) | + XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) | + XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) | + XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) | + XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual), +/*-------------------------------------------------------------------------------------------------*/ + .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable), +/*-------------------------------------------------------------------------------------------------*/ + .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) | + XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) | + XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay), +/*-------------------------------------------------------------------------------------------------*/ + .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual), +/*-------------------------------------------------------------------------------------------------*/ + + /* XCVR_RX_DIG configs */ + /* NOTE: Clock specific settings are embedded in the mode dependent configs */ + .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1), + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7), + + .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), + + /* DCOC configs */ + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ +#if (RADIO_IS_GEN_2P1) + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | +#endif /* (RADIO_IS_GEN_2P1) */ + XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | + XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ +#if (RADIO_IS_GEN_2P1) + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | +#endif /* (RADIO_IS_GEN_2P1) */ + XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | + XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), + + .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26), + + .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(5) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26), + + .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) , + + .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) | + XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711), + + .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U), + + .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU), + .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) | + XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U), + + .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF), + .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2), + + .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1), + + .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7), + + .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50), + + .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91), + + .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22), + + .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */ + + .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288), + + .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279), + + .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404), + .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) | + XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439), + .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) | + XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691), + .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) | + XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192), + .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) | + XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835), + .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) | + XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601), + .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) | + XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427), + .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) | + XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310), + .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) | + XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209), + .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) | + XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145), + .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) | + XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99), +#if (RADIO_IS_GEN_2P1) + .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) | + XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10), + .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) | + XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2), +#endif /* (RADIO_IS_GEN_2P1) */ + /* AGC Configs */ + .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2), + + .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2), + + .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4), + + .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5), + + .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7), + + .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7), + + .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10), + + .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) | +#else + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) , + + .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0), + + .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2), + + /* XCVR_TSM configs */ + .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) | + XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) | + XCVR_TSM_CTRL_TSM_IRQ0_EN(0) | + XCVR_TSM_CTRL_TSM_IRQ1_EN(0) | + XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) | + XCVR_TSM_CTRL_TX_ABORT_DIS(0) | + XCVR_TSM_CTRL_RX_ABORT_DIS(0) | + XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) | + XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) | + XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) | + XCVR_TSM_CTRL_BKPT(0xFF) , + + .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK, + .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), + .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), + +#if !RADIO_IS_GEN_2P1 + .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0), +#endif /* !RADIO_IS_GEN_2P1 */ + + .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8), + .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8), + + .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) | + XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3), + .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) | + XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7), + + .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ), + .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), + + .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */ + .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */ + .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */ + .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */ + .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */ + .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */ + .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */ + .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */ + .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */ + .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */ + + .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */ + .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */ + .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */ + .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */ + .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */ + .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), + .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */ + .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */ + .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */ + .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */ + .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */ + + .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */ + .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */ + .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_en */ + .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en */ + .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */ + .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */ + .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */ + .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */ + .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */ + .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */ + .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + + .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */ + .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */ + .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */ + .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */ + .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */ + .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */ + .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */ + .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */ + .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */ + .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */ + .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + + .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */ + .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */ + .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */ + .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */ + .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */ + .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */ + .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */ + .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */ + .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en */ + .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */ + +/* XCVR_TX_DIG configs */ +#define radio_dft_mode 0 +#define lfsr_length 4 +#define lfsr_en 0 +#define dft_clk_sel 4 +#define tx_dft_en 0 +#define soc_test_sel 0 +#define tx_capture_pol 0 +#define freq_word_adj 0 +#define lrm 0 +#define data_padding_pat_1 0x55 +#define data_padding_pat_0 0xAA +#define gfsk_multiply_table_manual 0 +#define gfsk_mi 1 +#define gfsk_mld 0 +#define gfsk_fld 0 +#define gfsk_mod_index_scaling 0 +#define tx_image_filter_ovrd_en 0 +#define tx_image_filter_0_ovrd 0 +#define tx_image_filter_1_ovrd 0 +#define tx_image_filter_2_ovrd 0 +#define gfsk_filter_coeff_manual2 0xC0630401 +#define gfsk_filter_coeff_manual1 0xBB29960D +#define fsk_modulation_scale_0 0x1800 +#define fsk_modulation_scale_1 0x0800 +#define dft_mod_patternval 0 +#define ctune_bist_go 0 +#define ctune_bist_thrshld 0 +#define pa_am_mod_freq 0 +#define pa_am_mod_entries 0 +#define pa_am_mod_en 0 +#define syn_bist_go 0 +#define syn_bist_all_channels 0 +#define freq_count_threshold 0 +#define hpm_inl_bist_go 0 +#define hpm_dnl_bist_go 0 +#define dft_max_ram_size 0 + + .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | + XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) | + XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) | + XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) | + XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj), +/*-------------------------------------------------------------------------------------------------*/ + .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) | + XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) | + XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0), +/*-------------------------------------------------------------------------------------------------*/ + .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval), +#if !RADIO_IS_GEN_2P1 +/*-------------------------------------------------------------------------------------------------*/ + .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en), +/*-------------------------------------------------------------------------------------------------*/ + .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) | + XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) | + XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size), +#endif /* !RADIO_IS_GEN_2P1 */ +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c new file mode 100644 index 000000000000..cd897071bc78 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c @@ -0,0 +1,418 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x7BCDEB39, + .phy_pre_ref1_init = 0xCEF7DEF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xda) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */ + (164U) << 7 | /* coeff 6/9 */ + (125U) << 16 | /* coef 3/12 */ + (169U) << 23, /* coeff 7/8 */ + .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */ + (90U) << 8 | /* coeff 1/14 */ + (141U) << 16 | /* coeff 4/11 */ + (155U) << 24, /* coeff 5/10 */ + .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */ + (216U) << 7 | /* coeff 6/9 */ + (105U) << 16 | /* coef 3/12 */ + (233U) << 23, /* coeff 7/8 */ + .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */ + (44U) << 8 | /* coeff 1/14 */ + (145U) << 16 | /* coeff 4/11 */ + (184U) << 24, /* coeff 5/10 */ +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1), + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c new file mode 100644 index 000000000000..3c56c638e2d7 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c @@ -0,0 +1,403 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0xBBDE739B, + .phy_pre_ref1_init = 0xDEFBDEF7, + .phy_pre_ref2_init = 0x0000E739, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xF0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c new file mode 100644 index 000000000000..11c7192a6d23 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c @@ -0,0 +1,422 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + .phy_pre_ref0_init = RW0PS(0, 0x19) | + RW0PS(1, 0x19U) | + RW0PS(2, 0x1AU) | + RW0PS(3, 0x1BU) | + RW0PS(4, 0x1CU) | + RW0PS(5, 0x1CU) | + RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ + .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1DU) | + RW1PS(11, 0x1CU) | + RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ + RW2PS(13, 0x1BU) | + RW2PS(14, 0x1AU) | + RW2PS(15, 0x19U), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(205) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* BLE 26MHz Channel Filter */ + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, + + /* BLE 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, + + /* 32MHz */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c new file mode 100644 index 000000000000..d6d82660988a --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c @@ -0,0 +1,404 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x37ACE2F7, + .phy_pre_ref1_init = 0xADF3BDEF, + .phy_pre_ref2_init = 0x0000BE33, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xCD) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c new file mode 100644 index 000000000000..871de5c3c170 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c @@ -0,0 +1,404 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0xF38B5273, + .phy_pre_ref1_init = 0x8CEF9CE6, + .phy_pre_ref2_init = 0x00009D2D, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xb0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c new file mode 100644 index 000000000000..d58064004f1c --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c @@ -0,0 +1,418 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x79CDEB39, + .phy_pre_ref1_init = 0xCE77DEF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xb0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */ + (276U) << 7 | /* Coeff 6/9 */ + (62U) << 16 | /* Coef 3/12 */ + (326U) << 23, /* Coeff 7/8 */ + .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */ + (10U) << 8 | /* Coeff 1/14 */ + (121U) << 16 | /* Coeff 4/11 */ + (198U) << 24, /* Coeff 5/10 */ + .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */ + (330U) << 7 | /* Coeff 6/9 */ + (7U) << 16 | /* Coef 3/12 */ + (510U) << 23, /* Coeff 7/8 */ + .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */ + (0U) << 8 | /* Coeff 1/14 */ + (37U) << 16 | /* Coeff 4/11 */ + (138U) << 24, /* Coeff 5/10 */ +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c new file mode 100644 index 000000000000..1a593141f9bc --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c @@ -0,0 +1,218 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* ========================= DATA RATE ONLY settings ===============*/ +/*! + * @brief XCVR 1Mbps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_1mbps_config = +{ + .data_rate = DR_1MBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(3), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(4), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(5), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6), +}; + +/*! + * @brief XCVR 500K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_500kbps_config = +{ + .data_rate = DR_500KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x10), + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), +}; + +/*! + * @brief XCVR 250K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_250kbps_config = +{ + .data_rate = DR_250KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c new file mode 100644 index 000000000000..3212db299cfb --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c @@ -0,0 +1,407 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t msk_mode_config = +{ + .radio_mode = MSK, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x79CDEB38, + .phy_pre_ref1_init = 0xCE77DFF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(208U) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + +#if RADIO_IS_GEN_2P0 + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), +#else + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), +#endif + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + /* MSK 1MBPS channel filter @ 26MHz RF OSC */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, + + /* MSK 1MBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + /* MSK 500KBPS channel filter @ 26MHz RF OSC */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, + + /* MSK 500KBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ +#if RADIO_IS_GEN_2P1 + .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), +#endif + + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | +#if RADIO_IS_GEN_2P0 + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), +#else + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), +#endif + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, + + /* MSK 250KBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c new file mode 100644 index 000000000000..c6ae1b3958c2 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -0,0 +1,1002 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_xcvr.h" +#include "fsl_xcvr_trim.h" +#include "dbg_ram_capture.h" +#include "math.h" + +/******************************************************************************* +* Definitions +******************************************************************************/ + + +/******************************************************************************* +* Prototypes +******************************************************************************/ +void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val); +float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ); +extern float roundf (float); + +/******************************************************************************* +* Variables +******************************************************************************/ +const int8_t TsettleCal = 10; +static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; +static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = +{ + 0, /* Baseline entry is first and not used in this table */ + -16, + +16, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4 +}; + +/******************************************************************************* + * Macros + ******************************************************************************/ +#define ISIGN(x) !((uint16_t)x & 0x8000) +#define ABS(x) ((x) > 0 ? (x) : -(x)) + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! ********************************************************************************* + * \brief This function performs a trim of the BBA DCOC DAC on the DUT + * + * \return status - 1 if passed, 0 if failed. + * + * \ingroup PublicAPIs + * + * \details + * Requires the RX to be warmed up before this function is called. + * + ***********************************************************************************/ +uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) +{ + uint8_t i; + float temp_mi = 0; + float temp_mq = 0; + float temp_pi = 0; + float temp_pq = 0; + float temp_step = 0; + uint8_t bbf_dacinit_i, bbf_dacinit_q; + + uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */ + uint32_t bbf_dcoc_step; + uint32_t bbf_dcoc_step_rcp; + TZAdcocstep_t tza_dcoc_step[11]; + uint8_t status = 0; + + /* Save register values. */ + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + + XcvrCalDelay(1000); + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */ + + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */ + XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */ + + XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */ + XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */ + + XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */ + XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); + /* Set DCOC Tracking State. */ + XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */ + /* Apply Manual Gain. */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ; + XcvrCalDelay(TsettleCal); + + dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */ + + bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; + + DC_Measure_short(I_CHANNEL, NOMINAL2); + DC_Measure_short(Q_CHANNEL, NOMINAL2); + + /* SWEEP Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(Q_CHANNEL, BBF_NEG); + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(Q_CHANNEL, BBF_POS); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */ + XcvrCalDelay(TsettleCal); + + /* SWEEP I CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(I_CHANNEL, BBF_NEG); + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(I_CHANNEL, BBF_POS); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */ + XcvrCalDelay(TsettleCal); + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + + temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4; + + bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + { + bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + + /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */ + for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ + switch(i){ + case TZA_STEP_N0: + temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + break; + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); + break; + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); + break; + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); + break; + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); + break; + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); + break; + case TZA_STEP_N6: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); + break; + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); + break; + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); + break; + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); + break; + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); + break; + default: + break; + } + + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + } + + /* Make the trims active. */ + XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ; + + status = 1; /* Success */ + } + else + { + status = 0; /* Failure */ + } + + /* Restore Registers. */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */ + + return status; +} + +/*! ********************************************************************************* + * \brief This function performs one point of the DC GAIN calibration process on the DUT + * + * \param[in] chan - whether the I or Q channel is being tested. + * \param[in] stage - whether the BBF or TZA gain stage is being tested. + * \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent. + * \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup. + * + * \ingroup PublicAPIs + * + * \details + * Relies on a static array to store each point of data for later processing in ::DC_GainCalc(). + * + ***********************************************************************************/ +void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) +{ + int16_t dc_meas_i = 0; + int16_t dc_meas_q = 0; + int16_t sum_dc_meas_i = 0; + int16_t sum_dc_meas_q = 0; + + { + int8_t i; + const int8_t iterations = 1; + sum_dc_meas_i = 0; + sum_dc_meas_q = 0; + + for (i = 0; i < iterations; i++) + { + rx_dc_sample_average(&dc_meas_i, &dc_meas_q); + sum_dc_meas_i = sum_dc_meas_i + dc_meas_i; + sum_dc_meas_q = sum_dc_meas_q + dc_meas_q; + } + sum_dc_meas_i = sum_dc_meas_i / iterations; + sum_dc_meas_q = sum_dc_meas_q / iterations; + } + + measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val]; + + if (chan == I_CHANNEL) + { + measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i; + } + else + { + measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q; + } +} + +/*! ********************************************************************************* + * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. + * + * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. + * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. + * + * \return result of the calculation, the measurement DCOC DAC step value for this measurement point. + * + ***********************************************************************************/ +float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) +{ + static int16_t norm_dc_code; + static float dc_step; + + /* Normalize internal measurement */ + norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; + dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value); + dc_step = (dc_step < 0)? -dc_step: dc_step; + + return dc_step; +} + +/*! ********************************************************************************* + * \brief Temporary delay function + * + * \param[in] none. + * + * \return none. + * + * \details + * + ***********************************************************************************/ +void XcvrCalDelay(uint32_t time) +{ + while(time * 32 > 0) /* Time delay is roughly in uSec. */ + { + time--; + } +} + +/*! ********************************************************************************* + * \brief This function calculates the average (DC value) based on a smaller set of digital samples of I and Q. + * + * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. + * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. + * + ***********************************************************************************/ +void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) +{ + static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */ + uint16_t i; + uint32_t rx_sample; + uint16_t * sample_ptr; + uint32_t temp, end_of_rx_wu; + uint32_t num_iq_samples; + float avg_i = 0; + float avg_q = 0; + + num_iq_samples = 128; + + /* Clear the entire allocated sample buffer */ + for (i = 0; i < num_iq_samples; i++) + { + samples[i]=0; + } + + /* Assume this has been called *AFTER* RxWu has completed. */ + /* XCVR_ForceRxWu(); */ + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + dbg_ram_init(); + /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ +#if RADIO_IS_GEN_3P0 + dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); + dbg_ram_wait_for_complete(); + dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); + dbg_ram_release(); +#else + (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); +#endif /* RADIO_IS_GEN_3P0 */ + + /* Sign extend the IQ samples in place in the sample buffer. */ + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i++) + { + rx_sample = *sample_ptr; + rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + *sample_ptr = rx_sample; + sample_ptr++; + } + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i += 2) + { + static int16_t i_value; + static int16_t q_value; + + /* Average I & Q channels separately. */ + i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */ + q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */ + avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ + avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ + } + XcvrCalDelay(10); + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * \brief This function calculates the average (DC value) based on a larger set of digital samples of I and Q. + * + * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. + * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. + * + ***********************************************************************************/ +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) +{ + static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */ + uint16_t i; + uint32_t rx_sample; + uint16_t * sample_ptr; + uint32_t temp, end_of_rx_wu; + uint32_t num_iq_samples; + float avg_i = 0; + float avg_q = 0; + + num_iq_samples = 512; + + /* Clear the entire allocated sample buffer. */ + for (i = 0; i < num_iq_samples; i++) + { + samples[i]=0; + } + + /* Assume this has been called *AFTER* RxWu has completed. */ + /* XCVR_ForceRxWu(); */ + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + dbg_ram_init(); + /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ +#if RADIO_IS_GEN_3P0 + dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); + dbg_ram_wait_for_complete(); + dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]); + dbg_ram_release(); +#else + (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); +#endif /* RADIO_IS_GEN_3P0 */ + + /* Sign extend the IQ samples in place in the sample buffer. */ + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i++) + { + rx_sample = *sample_ptr; + rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + *sample_ptr = rx_sample; + sample_ptr++; + } + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i += 2) + { + static int16_t i_value; + static int16_t q_value; + + /* Average I & Q channels separately. */ + i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */ + q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */ + avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ + avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ + } + + XcvrCalDelay(10); + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * rx_dc_est_average : Get DC EST values and return the Average + ***********************************************************************************/ +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber) +{ + float avg_i = 0; + float avg_q = 0; + uint16_t i = 0; + static uint32_t dc_temp, temp; + uint32_t end_of_rx_wu = 0; + static int16_t dc_meas_i; + static int16_t dc_meas_q; + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + /* Read DCOC DC EST register. */ + for (i = 0; i < SampleNumber; i++) + { + dc_temp = XCVR_RX_DIG->DCOC_DC_EST; + dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK; + temp = dc_meas_i; + temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_i = temp; + avg_i += (float) dc_meas_i; + + dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; + temp = dc_meas_q; + temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_q = temp; + avg_q += (float) dc_meas_q; + } + + avg_i /= (float) SampleNumber; + avg_q /= (float) SampleNumber; + + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * \brief This function performs a trim of the BBA DCOC DAC on the DUT + * + * \return status - 1 if passed, 0 if failed. + * + * \ingroup PublicAPIs + * + * \details + * Requires the RX to be warmed up before this function is called. + * + ***********************************************************************************/ +uint8_t rx_bba_dcoc_dac_trim_DCest(void) +{ + uint8_t i; + float temp_mi = 0; + float temp_mq = 0; + float temp_pi = 0; + float temp_pq = 0; + float temp_step = 0; + + uint32_t bbf_dcoc_step; + uint32_t bbf_dcoc_step_rcp; + TZAdcocstep_t tza_dcoc_step[11]; + uint8_t status = 0; + + uint8_t bbf_dacinit_i, bbf_dacinit_q; + uint8_t tza_dacinit_i, tza_dacinit_q; + int16_t dc_meas_i; + int16_t dc_meas_q; + uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */ + uint32_t temp; + + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + + /* Save register */ + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); + + XcvrCalDelay(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ + bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; + tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; + tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; + + XcvrCalDelay(TsettleCal * 4); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; + measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; + measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q; + + /* SWEEP I/Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 2); + + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16; + measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16; + measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q; + + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16; + measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16; + measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q; + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + + temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; + bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + { + bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + + /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ + for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ + switch(i){ + case TZA_STEP_N0: + temp_step = (bbf_dcoc_step>>3U) / 3.6F; + break; + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16); + break; + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16); + break; + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16); + break; + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16); + break; + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16); + break; + case TZA_STEP_N6: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16); + break; + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16); + break; + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16); + break; + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16); + break; + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16); + break; + default: + break; + } + + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + } + + /* Make the trims active */ + XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step*10) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp/10) ; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); + + status = 1; /* Success */ + } + else + { + status = 0; /* Failure */ + } + + /* Restore Registers */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ + + return status; +} + +/*! ********************************************************************************* + * DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign + ***********************************************************************************/ +void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) +{ + int16_t dc_meas_i = 2000, dc_meas_i_p = 2000; + int16_t dc_meas_q = 2000, dc_meas_q_p = 2000; + uint8_t curr_tza_dac_i, curr_tza_dac_q; + uint8_t curr_bba_dac_i, curr_bba_dac_q; + uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0; + uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0; + uint8_t i = 0; + uint8_t bba_gain = 11; + bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; + + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + uint32_t xcvr_ctrl_stack = 0; + + uint32_t temp; + + /* Save registers */ + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* WarmUp */ + if (standalone_operation) + { + temp = XCVR_MISC->XCVR_CTRL; + xcvr_ctrl_stack = temp; + temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK); + temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0); + XCVR_MISC->XCVR_CTRL = temp; + XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */ + XCVR_ForceRxWu(); + XcvrCalDelay(2000); + } + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + XcvrCalDelay(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + /* LNA and BBA DAC Sweep */ + curr_bba_dac_i = 0x20; + curr_bba_dac_q = 0x20; + curr_tza_dac_i = 0x80; + curr_tza_dac_q = 0x80; + + /* Perform a first DC measurement to ensure that measurement is not clipping */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + do + { + bba_gain--; + /* Set DAC user gain */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); + + for (i = 0; i < 0x0F; i++) + { + /* I channel : */ + if (!TZA_I_OK) + { + if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0)) + { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) + { + curr_tza_dac_i = p_tza_dac_i; + } + + TZA_I_OK = 1; + } + else + { + p_tza_dac_i = curr_tza_dac_i; + + if (ISIGN(dc_meas_i)) /* If positif */ + { + curr_tza_dac_i--; + } + else + { + curr_tza_dac_i++; + } + } + } + else /* Sweep BBA I */ + { + if (!BBA_I_OK) + { + if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20)) + { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) + { + curr_bba_dac_i = p_bba_dac_i; + } + + BBA_I_OK = 1; + } + else + { + p_bba_dac_i = curr_bba_dac_i; + if (ISIGN(dc_meas_i)) /* If positif */ + { + curr_bba_dac_i--; + } + else + { + curr_bba_dac_i++; + } + } + } + } + + /* Q channel : */ + if (!TZA_Q_OK) + { + if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0)) + { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) + { + curr_tza_dac_q = p_tza_dac_q; + } + TZA_Q_OK = 1; + } + else + { + p_tza_dac_q = curr_tza_dac_q; + if (ISIGN(dc_meas_q)) /* If positif */ + { + curr_tza_dac_q--; + } + else + { + curr_tza_dac_q++; + } + } + } + else /* Sweep BBA Q */ + { + if (!BBA_Q_OK) + { + if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20)) + { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) + { + curr_bba_dac_q = p_bba_dac_q; + } + BBA_Q_OK = 1; + } + else + { + p_bba_dac_q = curr_bba_dac_q; + if (ISIGN(dc_meas_q)) /* If positif */ + { + curr_bba_dac_q--; + } + else + { + curr_bba_dac_q++; + } + } + } + } + + /* DC OK break : */ + if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK) + { + break; + } + + dc_meas_i_p = dc_meas_i; /* Store as previous value */ + dc_meas_q_p = dc_meas_q; /* Store as previous value */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + } + + /* Apply optimized DCOC DAC INIT : */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + /* WarmDown */ + if (standalone_operation) + { + XCVR_ForceRxWd(); /* Don't leave the receiver running. */ + XcvrCalDelay(200); + XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */ + XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack; + } + + /* Restore register */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ +} + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h new file mode 100644 index 000000000000..04eda1320192 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -0,0 +1,139 @@ +/* +* The Clear BSD License +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _FSL_XCVR_TRIM_H_ +/* Clang-format off. */ +#define _FSL_XCVR_TRIM_H_ +/* Clang-format on. */ + +//#include "fsl_common.h" +#include "fsl_device_registers.h" +#include "fsl_xcvr.h" + +/*! +* @addtogroup xcvr +* @{ +*/ + +/*! @file*/ + +/************************************************************************************ +************************************************************************************* +* Public constant definitions +************************************************************************************* +************************************************************************************/ + +/************************************************************************************ +************************************************************************************* +* Public type definitions +************************************************************************************* +************************************************************************************/ + +/* \brief The enumerations used to define the I & Q channel selections. */ +typedef enum +{ + I_CHANNEL = 0, + Q_CHANNEL = 1, + NUM_I_Q_CHAN = 2 +} IQ_t; + +typedef enum /* Enumeration of ADC_GAIN_CAL 2 */ +{ + NOMINAL2 = 0, + BBF_NEG = 1, + BBF_POS = 2, + TZA_STEP_N0 = 3, + TZA_STEP_N1 = 4, + TZA_STEP_N2 = 5, + TZA_STEP_N3 = 6, + TZA_STEP_N4 = 7, + TZA_STEP_N5 = 8, + TZA_STEP_N6 = 9, + TZA_STEP_N7 = 10, + TZA_STEP_N8 = 11, + TZA_STEP_N9 = 12, + TZA_STEP_N10 = 13, + TZA_STEP_P0 = 14, + TZA_STEP_P1 = 15, + TZA_STEP_P2 = 16, + TZA_STEP_P3 = 17, + TZA_STEP_P4 = 18, + TZA_STEP_P5 = 19, + TZA_STEP_P6 = 20, + TZA_STEP_P7 = 21, + TZA_STEP_P8 = 22, + TZA_STEP_P9 = 23, + TZA_STEP_P10 = 24, + + NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */ +} DAC_SWEEP_STEP2_t; + +/* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */ +typedef struct +{ + uint16_t dcoc_step; + uint16_t dcoc_step_rcp; +} TZAdcocstep_t; + +typedef struct +{ + int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */ + int16_t internal_measurement; /* The value (average code) measured from DMA samples. */ +// uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */ +} GAIN_CALC_TBL_ENTRY2_T; + +/******************************************************************************* +* Definitions +******************************************************************************/ +void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); +uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); +void XcvrCalDelay(uint32_t time); +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber); +uint8_t rx_bba_dcoc_dac_trim_DCest(void); +void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); + + + + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_XCVR_TRIM_H_ */ + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c new file mode 100644 index 000000000000..1d2787a416c9 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c @@ -0,0 +1,250 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t zgbe_mode_config = +{ + .radio_mode = ZIGBEE_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */ + .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */ + .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */ + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xC0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_PLL_DIG configs */ + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ +#else + .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) , + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config = +{ + .radio_mode = ZIGBEE_MODE, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2, + + /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +/* CUSTOM datarate dependent config structure for ONLY 802.15.4 */ +/*! + * @brief XCVR 500K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config = +{ + .data_rate = DR_500KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | + XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | + XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0), +}; + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c new file mode 100644 index 000000000000..b613212af132 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c @@ -0,0 +1,536 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_device_registers.h" +#include "fsl_xcvr.h" +#include "ifr_radio.h" +#include "fsl_os_abstraction.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define IFR_RAM (0) + +#if RADIO_IS_GEN_3P0 +#define RDINDX (0x41U) +#define K3_BASE_INDEX (0x11U) /* Based for read index */ +#else +#define RDRSRC (0x03U) +#define KW4x_512_BASE (0x20000U) +#define KW4x_256_BASE (0x10000U) +#endif /* RADIO_IS_GEN_3P0 */ + +#if RADIO_IS_GEN_2P1 +#define FTFA (FTFE) +#endif /* RADIO_IS_GEN_2P1 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +uint32_t read_another_ifr_word(void); +uint32_t read_first_ifr_word(uint32_t read_addr); + +#if RADIO_IS_GEN_3P0 +uint64_t read_index_ifr(uint32_t read_addr); +#else +/*! ********************************************************************************* + * @brief Reads a location in block 1 IFR for use by the radio. + * + * This function handles reading IFR data from flash memory for trim loading. + * + * @param read_addr the address in the IFR to be read. + * + * @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index +***********************************************************************************/ +#if RADIO_IS_GEN_2P1 +uint64_t read_resource_ifr(uint32_t read_addr); +#else +uint32_t read_resource_ifr(uint32_t read_addr); +#endif /* RADIO_IS_GEN_2P1 */ +#endif /* RADIO_IS_GEN_3P0 */ + +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t ifr_read_addr; + +#if RADIO_IS_GEN_3P0 +static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ +static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + /* Trim table is empty for Gen3 by default */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#else +#if RADIO_IS_GEN_2P0 +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + 0x4005912CU, /* RSIM_ANA_TRIM address */ + 0x784B0000U, /* RSIM_ANA_TRIM default value */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#else +static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ +static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + 0x4005912CU, /* RSIM_ANA_TRIM address */ + 0x784B0000U, /* RSIM_ANA_TRIM default value */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#endif /* RADIO_IS_GEN_2P0 */ +#endif /* RADIO_IS_GEN_3P0 */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! ********************************************************************************* + * \brief Read command for reading the first 32bit word from IFR, encapsulates different + * flash IFR read mechanisms for multiple generations of SOC + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * +***********************************************************************************/ +uint32_t read_first_ifr_word(uint32_t read_addr) +{ + ifr_read_addr = read_addr; + return read_another_ifr_word(); +} + +/*! ********************************************************************************* + * \brief Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms. + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * + * \remarks PRE-CONDITIONS: + * The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use. + * +***********************************************************************************/ +uint32_t read_another_ifr_word(void) +{ + uint32_t packed_data; + +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + /* Using some static storage and alternating reads to read_index_ifr to replace read_resource_ifr */ + if (num_words_avail == 0) + { +#if RADIO_IS_GEN_3P0 + packed_data_long = read_index_ifr(ifr_read_addr); +#else /* Use 64 bit return version of read_resource */ + packed_data_long = read_resource_ifr(ifr_read_addr); +#endif /* RADIO_IS_GEN_3P0 */ + + num_words_avail = 2; + ifr_read_addr++; /* Read index addresses increment by 1 */ + } + + packed_data = (uint32_t)(packed_data_long & 0xFFFFFFFF); + packed_data_long = packed_data_long >> 32; + num_words_avail--; +#else + packed_data = read_resource_ifr(ifr_read_addr); + ifr_read_addr += 4; /* Read resource addresses increment by 4 */ +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + + return packed_data; +} + +#if RADIO_IS_GEN_3P0 +/*! ********************************************************************************* + * \brief Read command for reading from IFR using RDINDEX command + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * +***********************************************************************************/ +uint64_t read_index_ifr(uint32_t read_addr) +{ + uint8_t rdindex = read_addr; + uint64_t read_data; + uint8_t i; + + while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */ + + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + { + FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */ + } + + FTFE->FCCOB[0] = RDINDX; + FTFE->FCCOB[1] = rdindex; + + OSA_InterrupDisable(); + FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; + while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Pack read data back into 64 bit type */ + read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */ + for (i = 10; i > 3; i--) + { + read_data = read_data << 8; + read_data |= FTFE->FCCOB[i]; + } + + return read_data; +} +#else + +/*! ********************************************************************************* + * \brief Read command for reading from IFR + * + * \param read_addr flash address + * + * \return packed data containing radio trims only + * +***********************************************************************************/ +#if RADIO_IS_GEN_2P0 +uint32_t read_resource_ifr(uint32_t read_addr) +{ + + uint32_t packed_data; + uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; + uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + + while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ + + if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK ) + { + FTFA->FSTAT = (1<FCCOB0 = RDRSRC; + FTFA->FCCOB1 = flash_addr23_16; + FTFA->FCCOB2 = flash_addr15_8; + FTFA->FCCOB3 = flash_addr7_0; + FTFA->FCCOB8 = 0x00; + + OSA_InterruptDisable(); + FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK; + while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */ + read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */ + read_data15_8 = FTFA->FCCOB6; /* FTFA->FCCOB[6] */ + read_data7_0 = FTFA->FCCOB7; /* FTFA->FCCOB[7] */ + + packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0); + + return packed_data; +} +#else +uint64_t read_resource_ifr(uint32_t read_addr) +{ + + uint64_t packed_data; + uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; + uint8_t read_data[8]; + uint64_t temp_64; + uint8_t i; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + { + FTFE->FSTAT = (1<FCCOB0 = RDRSRC; + FTFE->FCCOB1 = flash_addr23_16; + FTFE->FCCOB2 = flash_addr15_8; + FTFE->FCCOB3 = flash_addr7_0; + FTFE->FCCOB4 = 0x00; + + OSA_InterruptDisable(); + FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; + while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data[7] = FTFE->FCCOB4; + read_data[6] = FTFE->FCCOB5; + read_data[5] = FTFE->FCCOB6; + read_data[4] = FTFE->FCCOB7; + read_data[3] = FTFE->FCCOB8; + read_data[2] = FTFE->FCCOB9; + read_data[1] = FTFE->FCCOBA; + read_data[0] = FTFE->FCCOBB; + + packed_data = 0; + for (i = 0; i < 8; i++) + { + temp_64 = read_data[i]; + packed_data |= temp_64 << (i * 8); + } + + return packed_data; +} + +#endif /* RADIO_IS_GEN_2P0 */ +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief Store a SW trim value in the table passed in from calling function. + * + * \param sw_trim_tbl pointer to the software trim table to hold SW trim values + * \param num_entries the number of entries in the SW trim table + * \param addr the software trim ID + * \param data the value of the software trim + * +***********************************************************************************/ +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) +{ + uint16_t i; + + if (sw_trim_tbl != NULL) + { + for (i = 0; i < num_entries; i++) + { + if (addr == sw_trim_tbl[i].trim_id) + { + sw_trim_tbl[i].trim_value = data; + sw_trim_tbl[i].valid = 1; + break; /* Don't need to scan the array any further... */ + } + } + } +} + +/*! ********************************************************************************* + * \brief Process block 1 IFR data. + * + * \param sw_trim_tbl pointer to the software trim table to hold SW trim values + * \param num_entries the number of entries in the SW trim table + * + * \remarks + * Uses a IFR v2 formatted default array if the IFR is blank or corrupted. + * Stores SW trim values to an array passed into this function. + * +***********************************************************************************/ +void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) +{ + uint32_t dest_addr; + uint32_t read_addr; + uint32_t dest_data; + uint32_t packed_data; + const uint32_t *ifr_ptr; + +#if RADIO_IS_GEN_3P0 + num_words_avail = 0; /* Prep for handling 64 bit words from flash */ +#endif /* RADIO_IS_GEN_3P0 */ + +#if RADIO_IS_GEN_3P0 + read_addr = K3_BASE_INDEX; +#else +#ifdef CPU_MKW41Z256VHT4 + read_addr = KW4x_256_BASE; +#else + read_addr = KW4x_512_BASE; +#endif /* CPU_MKW41Z256VHT4 */ +#endif /* RADIO_IS_GEN_3P0 */ + + /* Read first entry in IFR table */ + packed_data = read_first_ifr_word(read_addr); + if ((packed_data&~IFR_VERSION_MASK) == IFR_VERSION_HDR) + { + /* Valid header was found, process real IFR data */ + XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); + store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array*/ + packed_data = read_another_ifr_word(); + + while (packed_data !=IFR_EOF_SYMBOL) + { + if (IS_A_SW_ID(packed_data)) /* SW Trim case (non_reg writes) */ + { + dest_addr = packed_data; + packed_data = read_another_ifr_word(); + dest_data = packed_data; + /* Place SW trim in array for driver SW to use */ + store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); + } + else + { + if (IS_VALID_REG_ADDR(packed_data)) /* Valid register write address */ + { + dest_addr = packed_data; + packed_data = read_another_ifr_word(); + dest_data = packed_data; + *(uint32_t *)(dest_addr) = dest_data; + } + else + { /* Invalid address case */ + + } + } + + packed_data=read_another_ifr_word(); + } + } + else + { + /* Valid header is not present, use blind IFR trim table */ + ifr_ptr = BLOCK_1_IFR; + packed_data = *ifr_ptr; + XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); + store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array */ + ifr_ptr++; + packed_data= *ifr_ptr; + + while (packed_data != IFR_EOF_SYMBOL) + { + if (IS_A_SW_ID(packed_data)) + { + /* SW Trim case (non_reg writes) */ + dest_addr = packed_data; + ifr_ptr++; + packed_data = *(ifr_ptr); + dest_data = packed_data; + /* Place SW trim in array for driver SW to use */ + store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); + } + else + { + dest_addr = packed_data; + ifr_ptr++; + packed_data = *ifr_ptr; + dest_data = packed_data; + + /* Valid register write address */ + if (IS_VALID_REG_ADDR(dest_addr)) + { + *(uint32_t *)(dest_addr) = dest_data; + } + else + { + /* Invalid address case */ + } + } + + ifr_ptr++; + packed_data= *ifr_ptr; + } + } +} + +#if RADIO_IS_GEN_3P0 + +#else +uint32_t handle_ifr_die_id(void) +{ + uint32_t id_x, id_y; + uint32_t id; + + id = read_resource_ifr(0x90); + id_x = id & 0x00FF0000; + id_y = id & 0x000000FF; + + return (id_x | id_y); +} + +uint32_t handle_ifr_die_kw_type(void) +{ + uint32_t zb, ble; + + zb = read_resource_ifr(0x80) & 0x8000; + ble= read_resource_ifr(0x88) & 0x100000; + + return (zb | ble); +} + +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief Dumps block 1 IFR data to an array. + * + * \param dump_tbl pointer to the table to hold the dumped IFR values + * \param num_entries the number of entries to dump + * + * \remarks + * Starts at the first address in IFR and dumps sequential entries. + * +***********************************************************************************/ +void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries) +{ +#if RADIO_IS_GEN_3P0 + uint32_t ifr_address = 0x20000; +#else + uint32_t ifr_address = 0x20000; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t * dump_ptr = dump_tbl; + uint8_t i; + + *dump_ptr = read_first_ifr_word(ifr_address); + dump_ptr++; + + for (i = 0; i < num_entries - 1; i++) + { + *dump_ptr = read_another_ifr_word(); + dump_ptr++; + } +} + diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h new file mode 100644 index 000000000000..aa2294e5135e --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h @@ -0,0 +1,186 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef __IFR_RADIO_H__ +/* clang-format off */ +#define __IFR_RADIO_H__ +/* clang-format on */ + +#include +#include "fsl_xcvr.h" + +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define IFR_EOF_SYMBOL (0xFEED0E0FU) /* < Denotes the "End of File" for IFR data */ +#define IFR_VERSION_HDR (0xABCD0000U) /* < Constant value for upper 16 bits of IFR data header */ +#define IFR_VERSION_MASK (0x0000FFFFU) /* < Mask for version number (lower 16 bits) of IFR data header */ +#define IFR_SW_ID_MIN (0x00000000U) /* < Lower limit of SW trim IDs */ +#define IFR_SW_ID_MAX (0x0000FFFFU) /* < Lower limit of SW trim IDs */ + +#define IS_A_SW_ID(x) ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x))) + +/* K3 valid registers support */ +#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) +#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */ +#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */ +/* KW41 and KW35/36 valid registers support */ +#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) || \ + defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) || \ + defined(CPU_MKW21Z256VHT4) || defined(CPU_MKW21Z512VHT4) || \ + defined(CPU_MKW35A512VFP4) || defined(CPU_MKW36A512VFP4) ) + +#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */ +#endif + +#define MAKE_MASK(size) ((1 << (size)) - 1) +#define MAKE_MASKSHFT(size, bitpos) (MAKE_MASK(size) << (bitpos)) + +#define IFR_TZA_CAP_TUNE_MASK (0x0000000FU) +#define IFR_TZA_CAP_TUNE_SHIFT (0) +#define IFR_BBF_CAP_TUNE_MASK (0x000F0000U) +#define IFR_BBF_CAP_TUNE_SHIFT (16) +#define IFR_RES_TUNE2_MASK (0x00F00000U) +#define IFR_RES_TUNE2_SHIFT (20) + +/* \var typedef uint8_t IFR_ERROR_T */ +/* \brief The IFR error reporting type. */ +/* See #IFR_ERROR_T_enum for the enumeration definitions. */ +typedef uint8_t IFR_ERROR_T; + +/* \brief The enumerations used to describe IFR errors. */ +enum IFR_ERROR_T_enum +{ + IFR_SUCCESS = 0, + INVALID_POINTER = 1, /* < NULL pointer error */ + INVALID_DEST_SIZE_SHIFT = 2, /* < the bits won't fit as specified in the destination */ +}; + +/* \var typedef uint16_t SW_TRIM_ID_T */ +/* \brief The SW trim ID type. */ +/* See #SW_TRIM_ID_T_enum for the enumeration definitions. */ +typedef uint16_t SW_TRIM_ID_T; + +/* \brief The enumerations used to define SW trim IDs. */ +enum SW_TRIM_ID_T_enum +{ + Q_RELATIVE_GAIN_BY_PART = 0, /* < Q vs I relative gain trim ID */ + ADC_GAIN = 1, /* < ADC gain trim ID */ + ZB_FILT_TRIM = 2, /* < Baseband Bandwidth filter trim ID for BLE */ + BLE_FILT_TRIM = 3, /* < Baseband Bandwidth filter trim ID for BLE */ + TRIM_STATUS = 4, /* < Status result of the trim process (error indications) */ + TRIM_VERSION = 0xABCD, /* < Version number of the IFR trim algorithm/format. */ +}; + +/* \var typedef uint32_t IFR_TRIM_STATUS_T */ +/* \brief The definition of failure bits stored in IFR trim status word. */ +/* See #IFR_TRIM_STATUS_T_enum for the enumeration definitions. */ +typedef uint32_t IFR_TRIM_STATUS_T; + +/* \brief The enumerations used to describe trim algorithm failures in the status entry in IFR. */ +/* This enum represents multiple values which can be OR'd together in a single status word. */ +enum IFR_TRIM_STATUS_T_enum +{ + TRIM_ALGORITHM_SUCCESS = 0, + BGAP_VOLTAGE_TRIM_FAILED = 1, /* < algorithm failure in BGAP voltagetrim */ + IQMC_GAIN_ADJ_FAILED = 2, /* < algorithm failure in IQMC gain trim */ + IQMC_PHASE_ADJ_FAILED = 4, /* < algorithm failure in IQMC phase trim */ + IQMC_DC_GAIN_ADJ_FAILED = 8, /* < IQMC DC gain trim failure */ + ADC_GAIN_TRIM_FAILED = 10, /* < Trim failure for ADC Gain Trim */ + ZB_FILT_TRIM_FAILED = 20, /* < Filter trim failure for 802.15.4 */ + BLE_FILT_TRIM_FAILED = 40, /* < Filter trim failure for BLE */ +}; + +/* \var typedef struct IFR_SW_TRIM_TBL_ENTRY_T */ +/* \brief Structure defining an entry in a table used to contain values to be passed back from IFR */ +/* handling routine to XCVR driver software. */ +typedef struct +{ + SW_TRIM_ID_T trim_id; /* < The assigned ID */ + uint32_t trim_value; /* < The value fetched from IFR.*/ + uint8_t valid; /* < validity of the trim_value field after IFR processing is complete (TRUE/FALSE).*/ +} IFR_SW_TRIM_TBL_ENTRY_T; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Main IFR handler function called by XCVR driver software to process trim table. + * + * This function handles reading data from IFR and either loading to registers or storing to a SW trim values table. + * + * @param sw_trim_tbl pointer to the table used to store software trim values. + * @param num_entries the number of entries that can be stored in the SW trim table. + */ +void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries); + +/*! + * @brief Handler function to read die_id from IFR locations.. + * + * This function handles reading die ID value for debug and testing usage. + * + * @return the value of the die ID field. + */ +uint32_t handle_ifr_die_id(void); + +/*! + * @brief Handler function to read KW chip version from IFR locations.. + * + * This function handles reading KW chip version for debug and testing usage. + * + * @return the value of the KW version field. + */ +uint32_t handle_ifr_die_kw_type(void); + +/*! + * @brief Debug function to dump the IFR contents to a RAM array. + * + * This function handles reading data from IFR and storing to a RAM array for debug. + * + * @param dump_tbl pointer to the table used to store IFR entry values. + * @param num_entries the number of entries that can be stored in the dump table. + */ +void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries); + +#endif /*__IFR_RADIO_H__ */ + diff --git a/sys/auto_init/auto_init.c b/sys/auto_init/auto_init.c index 0ee699c4d43d..aa1cf0a0a673 100644 --- a/sys/auto_init/auto_init.c +++ b/sys/auto_init/auto_init.c @@ -256,6 +256,11 @@ void auto_init(void) auto_init_kw2xrf(); #endif +#ifdef MODULE_KW41ZRF + extern void auto_init_kw41zrf(void); + auto_init_kw41zrf(); +#endif + #ifdef MODULE_NETDEV_TAP extern void auto_init_netdev_tap(void); auto_init_netdev_tap(); diff --git a/sys/auto_init/netif/auto_init_kw41zrf.c b/sys/auto_init/netif/auto_init_kw41zrf.c new file mode 100644 index 000000000000..9ed7846ec837 --- /dev/null +++ b/sys/auto_init/netif/auto_init_kw41zrf.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2017 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + * + */ + +/* + * @ingroup auto_init_gnrc_netif + * @{ + * + * @file + * @brief Auto initialization for kw41zrf network interfaces + * + * @author Joakim Nohlgård + */ + +#ifdef MODULE_KW41ZRF + +#include "log.h" +#include "board.h" +#include "net/gnrc/netif/ieee802154.h" +#include "net/gnrc.h" + +#include "kw41zrf.h" + +/** + * @brief Define stack parameters for the MAC layer thread + * @{ + */ +#ifndef KW41ZRF_MAC_STACKSIZE +#define KW41ZRF_MAC_STACKSIZE (THREAD_STACKSIZE_DEFAULT) +#endif +#ifndef KW41ZRF_MAC_PRIO +#define KW41ZRF_MAC_PRIO (GNRC_NETIF_PRIO) +#endif + +/* There is only one memory mapped transceiver in the supported SoCs, the driver + * does not try to take into account multiple instances of the hardware module */ +#define KW41ZRF_NUMOF 1 + +static kw41zrf_t kw41zrf_devs[KW41ZRF_NUMOF]; +static char _kw41zrf_stacks[KW41ZRF_NUMOF][KW41ZRF_MAC_STACKSIZE]; + +void auto_init_kw41zrf(void) +{ + for (unsigned i = 0; i < KW41ZRF_NUMOF; i++) { + LOG_DEBUG("[auto_init_netif] initializing kw41zrf #%u\n", i); + kw41zrf_setup(&kw41zrf_devs[i]); + gnrc_netif_ieee802154_create(_kw41zrf_stacks[i], KW41ZRF_MAC_STACKSIZE, + KW41ZRF_MAC_PRIO, "kw41zrf", + (netdev_t *)&kw41zrf_devs[i]); + } +} +#else +typedef int dont_be_pedantic; +#endif /* MODULE_KW41ZRF */ + +/** @} */ From f8dfec75a0aecf9bc0c35e81c8e2648bee98363d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 22 Mar 2018 13:39:42 +0100 Subject: [PATCH 02/82] squash kw41zrf fix warnings unused arguments --- drivers/kw41zrf/include/kw41zrf_intern.h | 2 ++ drivers/kw41zrf/kw41zrf_getset.c | 2 ++ drivers/kw41zrf/kw41zrf_intern.c | 3 +++ drivers/kw41zrf/kw41zrf_netdev.c | 1 + 4 files changed, 8 insertions(+) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index d5801b56f839..2bf7c8ee39e9 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -117,6 +117,7 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq); */ static inline void kw41zrf_abort_sequence(kw41zrf_t *dev) { + (void) dev; /* Writing IDLE to XCVSEQ aborts any ongoing sequence */ ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | @@ -201,6 +202,7 @@ static inline void kw41zrf_timer_init(kw41zrf_t *dev, kw41zrf_timer_timebase_t t */ static inline uint32_t kw41zrf_get_timestamp(kw41zrf_t *dev) { + (void) dev; return ZLL->TIMESTAMP; } diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index a56cc2fd4d56..6d2da5f370bf 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -76,6 +76,7 @@ uint16_t kw41zrf_get_txpower(kw41zrf_t *dev) uint8_t kw41zrf_get_channel(kw41zrf_t *dev) { + (void) dev; return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK); } @@ -283,5 +284,6 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value) { + (void) dev; ZLL->RX_WTR_MARK = ZLL_RX_WTR_MARK_RX_WTR_MARK(value); } diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 3de296d23add..2ca00756c055 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -54,6 +54,7 @@ void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg) void kw41zrf_disable_interrupts(kw41zrf_t *dev) { + (void) dev; DEBUG("[kw41zrf] disable interrupts\n"); /* Clear and disable all interrupts */ ZLL->PHY_CTRL |= @@ -151,6 +152,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) { + (void) dev; DEBUG("[kw41zrf] set sequence to %u\n", (unsigned int)seq); assert((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) == XCVSEQ_IDLE); while ((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) == 0) { @@ -165,6 +167,7 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) int kw41zrf_can_switch_to_idle(kw41zrf_t *dev) { + (void) dev; uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; DEBUG("[kw41zrf] XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 ", SEQ_CTRL_STS=0x%" PRIx32 "\n", seq, diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 642603e96ba5..cf20a823c26a 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -371,6 +371,7 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) static netopt_state_t kw41zrf_netdev_get_state(kw41zrf_t *dev) { + (void) dev; if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { return NETOPT_STATE_SLEEP; } From ff79569d7f4f09abca6434f43de8bef73c7f23cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 10 Jun 2018 08:27:24 +0200 Subject: [PATCH 03/82] squash kw41zrf vendor whitespace fixes --- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 279 +++++++++--------- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 63 ++-- .../vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c | 19 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c | 17 +- .../XCVR/MKW41Z4/fsl_xcvr_common_config.c | 29 +- .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 39 ++- .../fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c | 39 ++- .../fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c | 51 ++-- .../fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c | 39 ++- .../fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c | 37 ++- .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 41 ++- .../MKW41Z4/fsl_xcvr_mode_datarate_config.c | 9 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c | 31 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 135 +++++---- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 13 +- .../XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c | 21 +- .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c | 55 ++-- .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h | 17 +- 18 files changed, 458 insertions(+), 476 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index 5701713df20a..59670742590d 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -326,7 +326,7 @@ void rf_osc_shutdown(void) RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; } } - + /******************************************************************************* * Code ******************************************************************************/ @@ -354,7 +354,7 @@ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) #if RADIO_IS_GEN_2P0 RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */ - RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ #endif /* RADIO_IS_GEN_2P0 */ /* Check that this is the proper radio version */ @@ -382,7 +382,7 @@ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0) { } - RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; + RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; rf_osc_startup(); /* Start RF_OSC to allow radio registers access */ #else SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; @@ -394,17 +394,17 @@ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) #endif /* ifndef SIMULATION */ /* Perform the desired XCVR initialization and configuration */ - status = XCVR_GetDefaultConfig(radio_mode, data_rate, - (const xcvr_common_config_t **)&radio_common_config, - (const xcvr_mode_config_t **)&radio_mode_cfg, - (const xcvr_mode_datarate_config_t **)&mode_datarate_config, + status = XCVR_GetDefaultConfig(radio_mode, data_rate, + (const xcvr_common_config_t **)&radio_common_config, + (const xcvr_mode_config_t **)&radio_mode_cfg, + (const xcvr_mode_datarate_config_t **)&mode_datarate_config, (const xcvr_datarate_config_t **)&datarate_config); - + if (status == gXcvrSuccess_c) { - status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, - (const xcvr_mode_config_t *)radio_mode_cfg, - (const xcvr_mode_datarate_config_t *)mode_datarate_config, + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT); current_xcvr_config.radio_mode = radio_mode; current_xcvr_config.data_rate = data_rate; @@ -424,11 +424,11 @@ void XCVR_Deinit(void) #endif /* RADIO_IS_GEN_3P0 */ } -xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, - data_rate_t data_rate, - const xcvr_common_config_t ** com_config, - const xcvr_mode_config_t ** mode_config, - const xcvr_mode_datarate_config_t ** mode_datarate_config, +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, const xcvr_datarate_config_t ** datarate_config) { xcvrStatus_t status = gXcvrSuccess_c; @@ -470,7 +470,7 @@ xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, case MSK: *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */ break; - default: + default: status = gXcvrInvalidParameters_c; break; } @@ -524,15 +524,15 @@ xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, return status; } -xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, - const xcvr_mode_config_t *mode_config, - const xcvr_mode_datarate_config_t *mode_datarate_config, - const xcvr_datarate_config_t *datarate_config, - int16_t tempDegC, +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, XCVR_INIT_MODE_CHG_T first_init) { xcvrStatus_t config_status = gXcvrSuccess_c; - uint32_t temp; + uint32_t temp; /* Turn on the module clocks before doing anything */ #if RADIO_IS_GEN_3P0 @@ -593,7 +593,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, temp = XCVR_MISC->XCVR_CTRL; temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); temp |= mode_config->xcvr_ctrl.init; - + #if RF_OSC_26MHZ == 1 { temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); @@ -664,7 +664,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, #endif /* RF_OSC_26MHZ == 1 */ XCVR_ANA->RX_AUXPLL = temp; } - + /* Configure RX_DIG_CTRL */ #if RF_OSC_26MHZ == 1 { @@ -715,7 +715,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, #if RADIO_IS_GEN_3P0 XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz; #endif /* RADIO_IS_GEN_3P0 */ - + /* customize DCOC_CTRL_0 settings for Gen2 GFSK BT=0.5, h=0.32 */ #if RADIO_IS_GEN_2P0 if ((mode_config->radio_mode == ANT_MODE) || (mode_config->radio_mode == GFSK_BT_0p5_h_0p32)) @@ -968,7 +968,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; - + #if RF_OSC_26MHZ == 1 { XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | @@ -987,7 +987,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; - + #if RADIO_IS_GEN_3P0 XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init; XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init; @@ -1008,19 +1008,19 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */ XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */ - XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ + XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */ XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */ XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */ XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */ temp = XCVR_TSM->TIMING14; - temp &= 0xFFFF0000; + temp &= 0xFFFF0000; temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ XCVR_TSM->TIMING14 = temp; #endif /* (PA_RAMP_TIME == 4) */ #endif /* RADIO_IS_GEN_3P0 */ } - + #if RADIO_IS_GEN_3P0 if (mode_config->radio_mode == ZIGBEE_MODE) { @@ -1048,7 +1048,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ } #endif /* RADIO_IS_GEN_3P0 */ - + /*******************************************************************************/ /* XCVR_TX_DIG configs */ /*******************************************************************************/ @@ -1071,7 +1071,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, XCVR_TX_DIG->CTRL = com_config->tx_ctrl; XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; - + #if !RADIO_IS_GEN_2P1 XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; @@ -1123,12 +1123,12 @@ xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_ const xcvr_common_config_t * radio_common_config; status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config ); - + if (status == gXcvrSuccess_c) { - status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, - (const xcvr_mode_config_t *)radio_mode_cfg, - (const xcvr_mode_datarate_config_t *)mode_datarate_config, + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE); current_xcvr_config.radio_mode = new_radio_mode; current_xcvr_config.data_rate = new_data_rate; @@ -1151,14 +1151,14 @@ void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable ) xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) { - double integer_used_in_Hz, - integer_used_in_LSB, - numerator_fraction, - numerator_in_Hz, - numerator_in_LSB, + double integer_used_in_Hz, + integer_used_in_LSB, + numerator_fraction, + numerator_in_Hz, + numerator_in_LSB, numerator_unrounded, - real_int_and_fraction, - real_fraction, + real_int_and_fraction, + real_fraction, requested_freq_in_LSB, sdm_lsb; uint32_t temp; @@ -1183,11 +1183,11 @@ xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) real_fraction = real_int_and_fraction - integer_truncated; - if (real_fraction > 0.5) + if (real_fraction > 0.5) { integer_to_use = integer_truncated + 1; - } - else + } + else { integer_to_use = integer_truncated; } @@ -1209,7 +1209,7 @@ xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) /* Write the Low Port Integer and Numerator */ temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; - temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | + temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK); XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; @@ -1271,7 +1271,7 @@ link_layer_t map_mode_to_ll(radio_mode_t mode) case GFSK_BT_0p5_h_1p0: case GFSK_BT_0p3_h_0p5: case GFSK_BT_0p7_h_0p5: - case MSK: + case MSK: llret = GENFSK_LL; break; default: @@ -1389,7 +1389,7 @@ xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) { /* Clear all of the overrides and restore to LL channel control */ temp = XCVR_PLL_DIG->CHAN_MAP; - temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK #if !RADIO_IS_GEN_2P1 | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK #endif /* !RADIO_IS_GEN_2P1 */ @@ -1398,7 +1398,7 @@ xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) #endif /* RADIO_IS_GEN_3P0 */ ); - XCVR_PLL_DIG->CHAN_MAP = temp; + XCVR_PLL_DIG->CHAN_MAP = temp; /* Stop using the manual frequency setting */ XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; @@ -1438,7 +1438,7 @@ xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK #endif /* !RADIO_IS_GEN_2P1 */ ); - XCVR_PLL_DIG->CHAN_MAP = temp; + XCVR_PLL_DIG->CHAN_MAP = temp; break; } } @@ -1448,7 +1448,7 @@ xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) #if !RADIO_IS_GEN_2P1 | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK #endif /* !RADIO_IS_GEN_2P1 */ - ); + ); XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c); XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); @@ -1503,16 +1503,16 @@ uint32_t XCVR_GetFreq ( void ) if (pll_num_unsigned & 0x04000000U) { /* Sign extend the numerator */ - pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; + pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; /* Calculate the frequency in MHz */ - freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); + freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); } else { /* Calculate the frequency in MHz */ pll_num = pll_num_unsigned; - freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); + freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); } freq = (uint32_t)freq_float; @@ -1580,9 +1580,9 @@ xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, uint8_t dft_mode = 0; uint8_t dft_clk_sel = 0; xcvrStatus_t status = gXcvrSuccess_c; - + XCVR_ChangeMode(radio_mode, data_rate); - + /* Select the RF Channel, using the Channel Number register */ XCVR_OverrideChannel(channel_num, 1); @@ -1659,9 +1659,9 @@ xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, da { return gXcvrInvalidParameters_c; } - + XCVR_ChangeMode(radio_mode, data_rate); - + /* Select the RF Channel, using the Channel Number register */ XCVR_OverrideChannel(channel_num, 1); @@ -1754,12 +1754,12 @@ xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) { return gXcvrInvalidParameters_c; /* Failure */ } - + if (pa_power != 1) { pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */ } - + XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */ XCVR_TSM->PA_POWER = pa_power; @@ -1768,29 +1768,29 @@ xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) xcvrStatus_t XCVR_CoexistenceInit(void) { -#if gMWS_UseCoexistence_d +#if gMWS_UseCoexistence_d uint32_t temp = 0x00U; uint32_t end_of_tx_wu = 0x00U; uint32_t end_of_rx_wu = 0x00U; - + #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) uint32_t tsm_timing47 = 0x00U; #else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */ uint32_t tsm_timing48 = 0x00U; #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - uint32_t tsm_timing50 = 0x00U; + uint32_t tsm_timing50 = 0x00U; #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - + #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en) uint32_t tsm_timing48 = 0x00U; // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en) - uint32_t tsm_timing47 = 0x00U; + uint32_t tsm_timing47 = 0x00U; #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - + uint16_t tsm_timing43_rx = 0x00; - uint16_t tsm_timing43_tx = 0x00; + uint16_t tsm_timing43_tx = 0x00; /* Select GPIO mode for FAD pins */ temp = XCVR_MISC->FAD_CTRL; @@ -1802,10 +1802,10 @@ xcvrStatus_t XCVR_CoexistenceInit(void) XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - + /***************** * TX SEQUENCE * - *****************/ + *****************/ if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) { @@ -1815,35 +1815,35 @@ xcvrStatus_t XCVR_CoexistenceInit(void) { temp = gMWS_CoexRfActiveAssertTime_d; } - + /* Save the TX RF_ACTIVE start time. */ - tsm_timing43_tx = end_of_tx_wu - temp; + tsm_timing43_tx = end_of_tx_wu - temp; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); #else - tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + /***************** * RX SEQUENCE * *****************/ @@ -1858,22 +1858,22 @@ xcvrStatus_t XCVR_CoexistenceInit(void) } /* Save the RX RF_ACTIVE start time. */ - tsm_timing43_rx = end_of_rx_wu - temp; + tsm_timing43_rx = end_of_rx_wu - temp; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); #else - tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ - tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) @@ -1885,11 +1885,11 @@ xcvrStatus_t XCVR_CoexistenceInit(void) temp = XCVR_TSM->TIMING48; temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); temp |= tsm_timing48; - XCVR_TSM->TIMING48 = temp; + XCVR_TSM->TIMING48 = temp; #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ temp = XCVR_TSM->TIMING50; - temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); temp |= tsm_timing50; @@ -1905,32 +1905,32 @@ xcvrStatus_t XCVR_CoexistenceInit(void) PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ - tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - + /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ - tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - + /* RF_ACTIVE */ temp = XCVR_TSM->TIMING48; temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); temp |= tsm_timing48; XCVR_TSM->TIMING48 = temp; - + /* RF_PRIORITY */ temp = XCVR_TSM->TIMING47; temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); temp |= tsm_timing47; XCVR_TSM->TIMING47 = temp; - + /* Overwrite pins settings */ GPIOC->PDDR |= 0x12; PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d; @@ -1941,14 +1941,14 @@ xcvrStatus_t XCVR_CoexistenceInit(void) } tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d; - + if (tsm_timing43_rx > end_of_rx_wu - 1) { tsm_timing43_rx = end_of_rx_wu - 1; } XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) | - (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | + (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) | (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)); @@ -1957,8 +1957,8 @@ xcvrStatus_t XCVR_CoexistenceInit(void) XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK; /* Save the updated registers values. */ - XCVR_CoexistenceSaveRestoreTimings(1); -#endif /* gMWS_UseCoexistence_d */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ return gXcvrSuccess_c; } @@ -1971,21 +1971,21 @@ xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_C uint32_t end_of_rx_wu = 0x00U; #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) uint32_t tsm_timing50 = 0x00U; -#endif +#endif #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) uint32_t tsm_timing47 = 0x00U; -#endif +#endif /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; /***************** * RX * *****************/ - + if (XCVR_COEX_HIGH_PRIO == rxPriority) { if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) @@ -1999,30 +1999,30 @@ xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_C #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */ - tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */ - tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ } else { /* Low priority RX */ #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ } @@ -2043,26 +2043,26 @@ xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_C /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */ #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ } else - { + { #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ - tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ - tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)); #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ } @@ -2082,9 +2082,9 @@ xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_C XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK); temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; + XCVR_TSM->TIMING47 = temp; #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - + /* Save the updated registers values. */ XCVR_CoexistenceSaveRestoreTimings(1); #endif /* gMWS_UseCoexistence_d */ @@ -2101,25 +2101,25 @@ xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) static uint32_t tsm_ovrd3_saved = 0x00; static uint32_t tsm_timing47_saved = 0x00; static uint32_t tsm_timing48_saved = 0x00; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) static uint32_t tsm_timing49_saved = 0x00; static uint32_t tsm_timing50_saved = 0x00; -#endif +#endif if (saveTimings == 0) { /* Restore registers values. */ - XCVR_TSM->OVRD0 = tsm_ovrd0_saved; + XCVR_TSM->OVRD0 = tsm_ovrd0_saved; XCVR_TSM->OVRD1 = tsm_ovrd1_saved; XCVR_TSM->OVRD2 = tsm_ovrd2_saved; XCVR_TSM->OVRD3 = tsm_ovrd3_saved; XCVR_TSM->TIMING47 = tsm_timing47_saved; XCVR_TSM->TIMING48 = tsm_timing48_saved; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) XCVR_TSM->TIMING49 = tsm_timing49_saved; XCVR_TSM->TIMING50 = tsm_timing50_saved; -#endif +#endif } else { @@ -2130,13 +2130,12 @@ xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) tsm_ovrd3_saved = XCVR_TSM->OVRD3; tsm_timing47_saved = XCVR_TSM->TIMING47; tsm_timing48_saved = XCVR_TSM->TIMING48; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) tsm_timing49_saved = XCVR_TSM->TIMING49; tsm_timing50_saved = XCVR_TSM->TIMING50; -#endif +#endif } #endif /* gMWS_UseCoexistence_d */ return gXcvrSuccess_c; } - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h index c7b7c2b681f8..f67292a75629 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -70,7 +70,7 @@ #define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ #endif /* RF_OSC_26MHZ == 1 */ #endif /* CLOCK_MAIN */ - + #define TBD_ZERO (0) #define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) @@ -712,7 +712,7 @@ typedef struct _xcvr_mode_config uint32_t scgc5_clock_ena_bits; /* XCVR_MISC configs */ - xcvr_masked_init_32_t xcvr_ctrl; + xcvr_masked_init_32_t xcvr_ctrl; /* XCVR_PHY configs */ #if RADIO_IS_GEN_3P0 @@ -732,7 +732,7 @@ typedef struct _xcvr_mode_config /* XCVR_RX_DIG configs */ uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ - uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ /* XCVR_TSM configs */ #if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) @@ -887,8 +887,8 @@ extern "C" { /*! * @brief Initializes an XCVR instance. * - * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to - * start up the XCVR in most situations. + * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to + * start up the XCVR in most situations. * * @param radio_mode The radio mode for which the XCVR should be configured. * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. @@ -907,8 +907,8 @@ void XCVR_Deinit(void); /*! * @brief Initializes XCVR configure structure. * - * This function updates pointers to the XCVR configure structures with default values. - * The configurations are divided into a common structure, a set of radio mode specific + * This function updates pointers to the XCVR configure structures with default values. + * The configurations are divided into a common structure, a set of radio mode specific * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at * each datarate), and a set of data rate specific structures. * The pointers provided by this routine point to const structures which can be @@ -923,11 +923,11 @@ void XCVR_Deinit(void); * @return 0 success, others failure * @see XCVR_Configure */ -xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, - data_rate_t data_rate, - const xcvr_common_config_t ** com_config, - const xcvr_mode_config_t ** mode_config, - const xcvr_mode_datarate_config_t ** mode_datarate_config, +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, const xcvr_datarate_config_t ** datarate_config); /*! @@ -944,11 +944,11 @@ xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) * @return 0 succeed, others failed */ -xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, - const xcvr_mode_config_t *mode_config, - const xcvr_mode_datarate_config_t *mode_datarate_config, - const xcvr_datarate_config_t *datarate_config, - int16_t tempDegC, +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, XCVR_INIT_MODE_CHG_T first_init); /*! @@ -1097,7 +1097,7 @@ xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); * The returned value is in the range 0..127 (7 bits). * * @return The XTAL trim compensation factors.. - */ + */ uint8_t XCVR_GetXtalTrim(void); /*! @@ -1117,7 +1117,7 @@ xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); * The returned value is a signed 8-bit value, in 1/4 dBm step. * * @return The RSSI adjustment value.. - */ + */ int8_t XCVR_GetRssiAdjustment(void); /*! @@ -1128,7 +1128,7 @@ int8_t XCVR_GetRssiAdjustment(void); * @param channel the channel number to set * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. * @return The status of the channel over-ride. - */ + */ xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); /*! @@ -1183,8 +1183,8 @@ void XCVR_ForceTxWd(void); * @param tx_pattern - the data pattern to transmit on. * @return The status of the pattern reg transmit. * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode - * and data rate. - */ + * and data rate. + */ xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); /*! @@ -1198,8 +1198,8 @@ xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, * @param lfsr_length - the length of the LFSR sequence to use. * @return The status of the LFSR reg transmit. * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode - * and data rate. - */ + * and data rate. + */ xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); /*! @@ -1207,7 +1207,7 @@ xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, da * * This function reverts all TX DFT settings from the test modes to normal operating mode. * - */ + */ void XCVR_DftTxOff(void); /*! @@ -1217,7 +1217,7 @@ void XCVR_DftTxOff(void); * * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. * @return The status of the PA power over-ride. - */ + */ xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); /*! @@ -1228,7 +1228,7 @@ xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). * @return The status of the CW transmit. - */ + */ xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); xcvrStatus_t XCVR_CoexistenceInit(void); @@ -1244,4 +1244,3 @@ xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); /*! @}*/ #endif /* _FSL_XCVR_H_ */ - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c index 40486b1d18d6..d036e20bea18 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -54,7 +54,7 @@ const xcvr_mode_config_t ant_mode_config = { .radio_mode = ANT_MODE, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK #if !RADIO_IS_GEN_2P1 | SIM_SCGC5_ANT_MASK #endif /* !RADIO_IS_GEN_2P1 */ @@ -89,14 +89,14 @@ const xcvr_mode_config_t ant_mode_config = RW2PS(15, 0x1CU), .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | XCVR_PHY_CFG1_CTS_THRESH(0xF8) | XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) #if !RADIO_IS_GEN_2P1 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) #endif /* !RADIO_IS_GEN_2P1 */ @@ -143,9 +143,9 @@ const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , @@ -210,4 +210,3 @@ const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c index c38f50831903..25a07f4b3a67 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -85,7 +85,7 @@ const xcvr_mode_config_t ble_mode_config = RW2PS(15, 0x19U), .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -135,13 +135,13 @@ const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = { .radio_mode = BLE_MODE, .data_rate = DR_1MBPS, - + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , @@ -204,4 +204,3 @@ const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c index 305b5e466f91..a47c4e1f9bbe 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -127,7 +127,7 @@ const xcvr_common_config_t xcvr_common_config = /*-------------------------------------------------------------------------------------------------*/ .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) | - XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | + XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) | XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) | XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) | @@ -234,7 +234,7 @@ const xcvr_common_config_t xcvr_common_config = XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) | XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) | XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) | - XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), + XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), /* DCOC configs */ .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ @@ -244,7 +244,7 @@ const xcvr_common_config_t xcvr_common_config = XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | - XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ #if (RADIO_IS_GEN_2P1) @@ -253,9 +253,9 @@ const xcvr_common_config_t xcvr_common_config = XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | - XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), - + .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26), .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(5) | @@ -356,13 +356,13 @@ const xcvr_common_config_t xcvr_common_config = .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) | XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2), #endif /* (RADIO_IS_GEN_2P1) */ - /* AGC Configs */ + /* AGC Configs */ .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) | - XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) | XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2), @@ -417,7 +417,7 @@ const xcvr_common_config_t xcvr_common_config = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) | XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) | XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10), - + .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) | XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) | XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) | @@ -626,4 +626,3 @@ const xcvr_common_config_t xcvr_common_config = XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size), #endif /* !RADIO_IS_GEN_2P1 */ }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c index cd897071bc78..e79e0c6d5385 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -91,12 +91,12 @@ const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), #endif - + /* XCVR_TSM configs */ #if (DATA_PADDING_EN) .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), @@ -141,9 +141,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , @@ -153,9 +153,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif - + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | @@ -235,9 +235,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , @@ -247,7 +247,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -324,14 +324,14 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = { .radio_mode = GFSK_BT_0p3_h_0p5, .data_rate = DR_250KBPS, - + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , @@ -340,11 +340,11 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | #if RADIO_IS_GEN_2P0 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | @@ -415,4 +415,3 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c index 3c56c638e2d7..7f00f1e6f920 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -63,14 +63,14 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - + /* XCVR_PHY configs */ .phy_pre_ref0_init = 0xBBDE739B, .phy_pre_ref1_init = 0xDEFBDEF7, .phy_pre_ref2_init = 0x0000E739, .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -90,7 +90,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), @@ -128,19 +128,19 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - + /* AGC configs */ #if RADIO_IS_GEN_2P1 .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | @@ -179,7 +179,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, - + /* 32MHz Channel Filter */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, @@ -217,13 +217,13 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = { .radio_mode = GFSK_BT_0p5_h_0p32, .data_rate = DR_500KBPS, - + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , @@ -233,7 +233,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -314,9 +314,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , @@ -326,7 +326,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | @@ -400,4 +400,3 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c index 11c7192a6d23..8b7d7cb01c3c 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -84,7 +84,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = RW2PS(15, 0x19U), .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -104,7 +104,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), @@ -143,9 +143,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , @@ -155,7 +155,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | @@ -169,7 +169,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), #endif - + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | @@ -238,9 +238,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , @@ -250,7 +250,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -290,7 +290,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, - + /* 32MHz */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, @@ -328,23 +328,23 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = { .radio_mode = GFSK_BT_0p5_h_0p5, .data_rate = DR_250KBPS, - + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - /* AGC configs */ + /* AGC configs */ #if RADIO_IS_GEN_2P1 .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | @@ -352,24 +352,24 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | #if RADIO_IS_GEN_2P0 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), #else XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), #endif .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | #if RADIO_IS_GEN_2P0 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else +#else XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), #endif @@ -419,4 +419,3 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c index d6d82660988a..6ba9e7d59158 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -70,7 +70,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = .phy_pre_ref2_init = 0x0000BE33, .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -91,7 +91,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), @@ -103,7 +103,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = #else .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), #endif /* (DATA_PADDING_EN) */ - + /* XCVR_TX_DIG configs */ .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) | @@ -129,9 +129,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , @@ -141,7 +141,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | @@ -218,13 +218,13 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = { .radio_mode = GFSK_BT_0p5_h_0p7, .data_rate = DR_500KBPS, - + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , @@ -234,7 +234,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -315,9 +315,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , @@ -327,7 +327,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | @@ -343,7 +343,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), #endif .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | #if RADIO_IS_GEN_2P0 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | @@ -369,7 +369,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, - /* 32MHz Channel Filter */ + /* 32MHz Channel Filter */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, @@ -401,4 +401,3 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c index 871de5c3c170..74f404ce8499 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -64,13 +64,13 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - /* XCVR_PHY configs */ + /* XCVR_PHY configs */ .phy_pre_ref0_init = 0xF38B5273, .phy_pre_ref1_init = 0x8CEF9CE6, .phy_pre_ref2_init = 0x00009D2D, .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -90,7 +90,7 @@ const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), @@ -128,9 +128,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , @@ -140,7 +140,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | @@ -221,9 +221,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , @@ -233,7 +233,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -272,7 +272,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E, .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F, - + /* 32MHz Channel Filter */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011, @@ -314,9 +314,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , @@ -326,7 +326,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | @@ -368,7 +368,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A, .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E, - + /* 32MHz Channel Filter */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9, @@ -401,4 +401,3 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c index d58064004f1c..d2ccf8d36522 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -63,14 +63,14 @@ const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - + /* XCVR_PHY configs */ .phy_pre_ref0_init = 0x79CDEB39, .phy_pre_ref1_init = 0xCE77DEF7, .phy_pre_ref2_init = 0x0000CEB7, .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -91,7 +91,7 @@ const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), @@ -141,20 +141,20 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , /* AGC configs */ - + #if RADIO_IS_GEN_2P1 .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | @@ -235,20 +235,20 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , /* AGC configs */ - + #if RADIO_IS_GEN_2P1 .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -329,9 +329,9 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , @@ -341,7 +341,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | @@ -357,7 +357,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), #endif .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | #if RADIO_IS_GEN_2P0 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | @@ -382,7 +382,7 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, - + /* 32MHz Channel Filter */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, @@ -415,4 +415,3 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c index 1a593141f9bc..7347abad4c6e 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_mode_datarate_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -215,4 +215,3 @@ const xcvr_datarate_config_t xcvr_250kbps_config = .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c index 3212db299cfb..17baa297064d 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -91,7 +91,7 @@ const xcvr_mode_config_t msk_mode_config = .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 +#if RADIO_IS_GEN_2P0 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), #else .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), @@ -129,7 +129,7 @@ const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ @@ -141,7 +141,7 @@ const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | @@ -223,9 +223,9 @@ const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , @@ -235,7 +235,7 @@ const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | @@ -276,7 +276,7 @@ const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, - /* MSK 500KBPS channel filter @ 32MHz RF OSC */ + /* MSK 500KBPS channel filter @ 32MHz RF OSC */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, @@ -317,9 +317,9 @@ const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , @@ -329,7 +329,7 @@ const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), #endif .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | @@ -372,7 +372,7 @@ const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, - /* MSK 250KBPS channel filter @ 32MHz RF OSC */ + /* MSK 250KBPS channel filter @ 32MHz RF OSC */ .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, @@ -404,4 +404,3 @@ const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index c6ae1b3958c2..360269966501 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -56,9 +56,9 @@ extern float roundf (float); * Variables ******************************************************************************/ const int8_t TsettleCal = 10; -static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; -static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = -{ +static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; +static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = +{ 0, /* Baseline entry is first and not used in this table */ -16, +16, @@ -104,7 +104,7 @@ static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = * * \details * Requires the RX to be warmed up before this function is called. - * + * ***********************************************************************************/ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) { @@ -121,8 +121,8 @@ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) uint32_t bbf_dcoc_step_rcp; TZAdcocstep_t tza_dcoc_step[11]; uint8_t status = 0; - - /* Save register values. */ + + /* Save register values. */ uint32_t dcoc_ctrl_0_stack; uint32_t dcoc_ctrl_1_stack; uint32_t agc_ctrl_1_stack; @@ -172,15 +172,15 @@ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) DC_Measure_short(Q_CHANNEL, BBF_POS); XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */ - XcvrCalDelay(TsettleCal); + XcvrCalDelay(TsettleCal); /* SWEEP I CHANNEL */ /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); XcvrCalDelay(TsettleCal); DC_Measure_short(I_CHANNEL, BBF_NEG); /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); XcvrCalDelay(TsettleCal); DC_Measure_short(I_CHANNEL, BBF_POS); @@ -197,7 +197,7 @@ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); - if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) { bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); @@ -206,38 +206,38 @@ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) { /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ switch(i){ - case TZA_STEP_N0: + case TZA_STEP_N0: temp_step = (bbf_dcoc_step >> 3U) / 3.6F; break; - case TZA_STEP_N1: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); break; - case TZA_STEP_N2: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); break; - case TZA_STEP_N3: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); break; - case TZA_STEP_N4: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); break; - case TZA_STEP_N5: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); break; - case TZA_STEP_N6: + case TZA_STEP_N6: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); break; - case TZA_STEP_N7: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); break; - case TZA_STEP_N8: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); break; - case TZA_STEP_N9: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); break; - case TZA_STEP_N10: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); break; default: break; @@ -290,7 +290,7 @@ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) * * \details * Relies on a static array to store each point of data for later processing in ::DC_GainCalc(). - * + * ***********************************************************************************/ void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) { @@ -304,7 +304,7 @@ void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) const int8_t iterations = 1; sum_dc_meas_i = 0; sum_dc_meas_q = 0; - + for (i = 0; i < iterations; i++) { rx_dc_sample_average(&dc_meas_i, &dc_meas_q); @@ -325,7 +325,7 @@ void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) { measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q; } -} +} /*! ********************************************************************************* * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. @@ -334,7 +334,7 @@ void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. * * \return result of the calculation, the measurement DCOC DAC step value for this measurement point. - * + * ***********************************************************************************/ float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) { @@ -350,7 +350,7 @@ float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2 } /*! ********************************************************************************* - * \brief Temporary delay function + * \brief Temporary delay function * * \param[in] none. * @@ -412,7 +412,7 @@ void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); #endif /* RADIO_IS_GEN_3P0 */ - /* Sign extend the IQ samples in place in the sample buffer. */ + /* Sign extend the IQ samples in place in the sample buffer. */ sample_ptr = (uint16_t *)(&samples[0]); for (i = 0; i < num_iq_samples * 2; i++) { @@ -421,7 +421,7 @@ void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) *sample_ptr = rx_sample; sample_ptr++; } - + sample_ptr = (uint16_t *)(&samples[0]); for (i = 0; i < num_iq_samples * 2; i += 2) { @@ -446,7 +446,7 @@ void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. * ***********************************************************************************/ -void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) { static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */ uint16_t i; @@ -494,7 +494,7 @@ void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) *sample_ptr = rx_sample; sample_ptr++; } - + sample_ptr = (uint16_t *)(&samples[0]); for (i = 0; i < num_iq_samples * 2; i += 2) { @@ -564,9 +564,9 @@ void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber) * * \details * Requires the RX to be warmed up before this function is called. - * + * ***********************************************************************************/ -uint8_t rx_bba_dcoc_dac_trim_DCest(void) +uint8_t rx_bba_dcoc_dac_trim_DCest(void) { uint8_t i; float temp_mi = 0; @@ -732,7 +732,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) /* Make the trims active */ XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step*10) | + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step*10) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp/10) ; XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); @@ -804,7 +804,7 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */ XCVR_ForceRxWu(); XcvrCalDelay(2000); - } + } /* Register config */ /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ @@ -829,7 +829,7 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XcvrCalDelay(TsettleCal); - /* Set default DCOC DAC INIT Value */ + /* Set default DCOC DAC INIT Value */ /* LNA and BBA DAC Sweep */ curr_bba_dac_i = 0x20; curr_bba_dac_q = 0x20; @@ -858,17 +858,17 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) { /* I channel : */ if (!TZA_I_OK) - { + { if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0)) - { + { if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { - curr_tza_dac_i = p_tza_dac_i; + curr_tza_dac_i = p_tza_dac_i; } TZA_I_OK = 1; } - else + else { p_tza_dac_i = curr_tza_dac_i; @@ -876,7 +876,7 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) { curr_tza_dac_i--; } - else + else { curr_tza_dac_i++; } @@ -885,9 +885,9 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) else /* Sweep BBA I */ { if (!BBA_I_OK) - { + { if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20)) - { + { if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { curr_bba_dac_i = p_bba_dac_i; @@ -895,14 +895,14 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) BBA_I_OK = 1; } - else + else { p_bba_dac_i = curr_bba_dac_i; if (ISIGN(dc_meas_i)) /* If positif */ { curr_bba_dac_i--; } - else + else { curr_bba_dac_i++; } @@ -912,9 +912,9 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) /* Q channel : */ if (!TZA_Q_OK) - { + { if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0)) - { + { if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { curr_tza_dac_q = p_tza_dac_q; @@ -928,32 +928,32 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) { curr_tza_dac_q--; } - else + else { curr_tza_dac_q++; - } + } } - } + } else /* Sweep BBA Q */ { if (!BBA_Q_OK) - { + { if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20)) - { + { if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { curr_bba_dac_q = p_bba_dac_q; } BBA_Q_OK = 1; } - else + else { p_bba_dac_q = curr_bba_dac_q; if (ISIGN(dc_meas_q)) /* If positif */ - { + { curr_bba_dac_q--; } - else + else { curr_bba_dac_q++; } @@ -999,4 +999,3 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ } - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h index 04eda1320192..13cbd3805f83 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -6,18 +6,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -102,8 +102,8 @@ typedef enum /* Enumeration of ADC_GAIN_CAL 2 */ /* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */ typedef struct { - uint16_t dcoc_step; - uint16_t dcoc_step_rcp; + uint16_t dcoc_step; + uint16_t dcoc_step_rcp; } TZAdcocstep_t; typedef struct @@ -136,4 +136,3 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); /*! @}*/ #endif /* _FSL_XCVR_TRIM_H_ */ - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c index 1d2787a416c9..41890c45561d 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_zgbe_config.c @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -70,7 +70,7 @@ const xcvr_mode_config_t zgbe_mode_config = .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */ .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | XCVR_PHY_CFG1_BSM_EN_BLE(0) | XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | @@ -96,7 +96,7 @@ const xcvr_mode_config_t zgbe_mode_config = .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), /* XCVR_TSM configs */ #if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ #else .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT), #endif /* (DATA_PADDING_EN) */ @@ -121,18 +121,18 @@ const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config = { .radio_mode = ZIGBEE_MODE, .data_rate = DR_500KBPS, - + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - + /* AGC configs */ .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | @@ -247,4 +247,3 @@ const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config = .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) | XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0), }; - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c index b613212af132..4c3b59a165ec 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -44,10 +44,10 @@ #define IFR_RAM (0) #if RADIO_IS_GEN_3P0 -#define RDINDX (0x41U) +#define RDINDX (0x41U) #define K3_BASE_INDEX (0x11U) /* Based for read index */ #else -#define RDRSRC (0x03U) +#define RDRSRC (0x03U) #define KW4x_512_BASE (0x20000U) #define KW4x_256_BASE (0x10000U) #endif /* RADIO_IS_GEN_3P0 */ @@ -136,11 +136,11 @@ const uint32_t BLOCK_1_IFR[]= ******************************************************************************/ /*! ********************************************************************************* - * \brief Read command for reading the first 32bit word from IFR, encapsulates different + * \brief Read command for reading the first 32bit word from IFR, encapsulates different * flash IFR read mechanisms for multiple generations of SOC - * + * * \param read_addr flash address - * + * * \return 8 bytes of packed data containing radio trims only * ***********************************************************************************/ @@ -152,9 +152,9 @@ uint32_t read_first_ifr_word(uint32_t read_addr) /*! ********************************************************************************* * \brief Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms. - * + * * \param read_addr flash address - * + * * \return 8 bytes of packed data containing radio trims only * * \remarks PRE-CONDITIONS: @@ -193,9 +193,9 @@ uint32_t read_another_ifr_word(void) #if RADIO_IS_GEN_3P0 /*! ********************************************************************************* * \brief Read command for reading from IFR using RDINDEX command - * + * * \param read_addr flash address - * + * * \return 8 bytes of packed data containing radio trims only * ***********************************************************************************/ @@ -207,7 +207,7 @@ uint64_t read_index_ifr(uint32_t read_addr) while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */ - if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) { FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */ } @@ -234,15 +234,15 @@ uint64_t read_index_ifr(uint32_t read_addr) /*! ********************************************************************************* * \brief Read command for reading from IFR - * + * * \param read_addr flash address - * + * * \return packed data containing radio trims only * ***********************************************************************************/ #if RADIO_IS_GEN_2P0 uint32_t read_resource_ifr(uint32_t read_addr) -{ +{ uint32_t packed_data; uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; @@ -282,7 +282,7 @@ uint32_t read_resource_ifr(uint32_t read_addr) } #else uint64_t read_resource_ifr(uint32_t read_addr) -{ +{ uint64_t packed_data; uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; @@ -336,7 +336,7 @@ uint64_t read_resource_ifr(uint32_t read_addr) /*! ********************************************************************************* * \brief Store a SW trim value in the table passed in from calling function. - * + * * \param sw_trim_tbl pointer to the software trim table to hold SW trim values * \param num_entries the number of entries in the SW trim table * \param addr the software trim ID @@ -363,11 +363,11 @@ void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, /*! ********************************************************************************* * \brief Process block 1 IFR data. - * + * * \param sw_trim_tbl pointer to the software trim table to hold SW trim values * \param num_entries the number of entries in the SW trim table * - * \remarks + * \remarks * Uses a IFR v2 formatted default array if the IFR is blank or corrupted. * Stores SW trim values to an array passed into this function. * @@ -426,12 +426,12 @@ void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) { /* Invalid address case */ } - } + } packed_data=read_another_ifr_word(); } - } - else + } + else { /* Valid header is not present, use blind IFR trim table */ ifr_ptr = BLOCK_1_IFR; @@ -453,7 +453,7 @@ void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) /* Place SW trim in array for driver SW to use */ store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); } - else + else { dest_addr = packed_data; ifr_ptr++; @@ -506,11 +506,11 @@ uint32_t handle_ifr_die_kw_type(void) /*! ********************************************************************************* * \brief Dumps block 1 IFR data to an array. - * + * * \param dump_tbl pointer to the table to hold the dumped IFR values * \param num_entries the number of entries to dump * - * \remarks + * \remarks * Starts at the first address in IFR and dumps sequential entries. * ***********************************************************************************/ @@ -533,4 +533,3 @@ void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries) dump_ptr++; } } - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h index aa2294e5135e..345dc9f090e2 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h @@ -7,18 +7,18 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted (subject to the limitations in the * disclaimer below) provided that the following conditions are met: -* +* * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. -* +* * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. -* +* * * Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. -* +* * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED @@ -151,7 +151,7 @@ typedef struct * * @param sw_trim_tbl pointer to the table used to store software trim values. * @param num_entries the number of entries that can be stored in the SW trim table. - */ + */ void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries); /*! @@ -160,7 +160,7 @@ void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries); * This function handles reading die ID value for debug and testing usage. * * @return the value of the die ID field. - */ + */ uint32_t handle_ifr_die_id(void); /*! @@ -169,7 +169,7 @@ uint32_t handle_ifr_die_id(void); * This function handles reading KW chip version for debug and testing usage. * * @return the value of the KW version field. - */ + */ uint32_t handle_ifr_die_kw_type(void); /*! @@ -179,8 +179,7 @@ uint32_t handle_ifr_die_kw_type(void); * * @param dump_tbl pointer to the table used to store IFR entry values. * @param num_entries the number of entries that can be stored in the dump table. - */ + */ void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries); #endif /*__IFR_RADIO_H__ */ - From a83c963847bcb60d6d79c715038503813c1a2d08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 22 Mar 2018 13:38:36 +0100 Subject: [PATCH 04/82] squash kw41zrf vendor code fix warnings --- drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index 59670742590d..a0cdf36c86de 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -531,6 +531,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, int16_t tempDegC, XCVR_INIT_MODE_CHG_T first_init) { + (void) tempDegC; xcvrStatus_t config_status = gXcvrSuccess_c; uint32_t temp; @@ -1247,7 +1248,7 @@ healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control) { - + (void) control; } /* Helper function to map radio mode to LL usage */ @@ -2087,6 +2088,9 @@ xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_C /* Save the updated registers values. */ XCVR_CoexistenceSaveRestoreTimings(1); +#else /* gMWS_UseCoexistence_d */ + (void) rxPriority; + (void) txPriority; #endif /* gMWS_UseCoexistence_d */ return gXcvrSuccess_c; @@ -2135,6 +2139,8 @@ xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) tsm_timing50_saved = XCVR_TSM->TIMING50; #endif } +#else /* gMWS_UseCoexistence_d */ + (void) saveTimings; #endif /* gMWS_UseCoexistence_d */ return gXcvrSuccess_c; From 0c35238db6341cac27e0ea4fe6a80d2554366d30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 11 Jun 2018 06:56:59 +0200 Subject: [PATCH 05/82] squash kw41zrf vendor driver RIOT fixes --- drivers/kw41zrf/vendor/Common/EmbeddedTypes.h | 221 ------------------ .../Interface/fsl_os_abstraction.h | 22 +- .../vendor/XCVR/MKW41Z4/dbg_ram_capture.c | 165 +++++++++++++ .../vendor/XCVR/MKW41Z4/dbg_ram_capture.h | 210 +++++++++++++++++ .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 8 +- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 2 +- .../XCVR/MKW41Z4/fsl_xcvr_common_config.c | 2 +- .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 1 - .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 2 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 11 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 3 +- .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c | 6 +- .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h | 12 +- 13 files changed, 413 insertions(+), 252 deletions(-) delete mode 100644 drivers/kw41zrf/vendor/Common/EmbeddedTypes.h create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c create mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h diff --git a/drivers/kw41zrf/vendor/Common/EmbeddedTypes.h b/drivers/kw41zrf/vendor/Common/EmbeddedTypes.h deleted file mode 100644 index 6a0ffd325de4..000000000000 --- a/drivers/kw41zrf/vendor/Common/EmbeddedTypes.h +++ /dev/null @@ -1,221 +0,0 @@ -/*! -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* \file -* -* This file holds type definitions that maps the standard c-types into types -* with guaranteed sizes. The types are target/platform specific and must be edited -* for each new target/platform. -* The header file also provides definitions for TRUE, FALSE and NULL. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _EMBEDDEDTYPES_H_ -#define _EMBEDDEDTYPES_H_ - - -/************************************************************************************ -* -* INCLUDES -* -************************************************************************************/ - -#include - - -/************************************************************************************ -* -* TYPE DEFINITIONS -* -************************************************************************************/ - -/* boolean types */ -typedef uint8_t bool_t; - -typedef uint8_t index_t; - -/* TRUE/FALSE definition*/ -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/* null pointer definition*/ -#ifndef NULL -#define NULL (( void * )( 0x0UL )) -#endif - -#if defined(__GNUC__) -#define PACKED_STRUCT struct __attribute__ ((__packed__)) -#define PACKED_UNION union __attribute__ ((__packed__)) -#elif defined(__IAR_SYSTEMS_ICC__) -#define PACKED_STRUCT __packed struct -#define PACKED_UNION __packed union -#else -#define PACKED_STRUCT struct -#define PACKED_UNION union -#endif - -typedef unsigned char uintn8_t; -typedef unsigned long uintn32_t; - -typedef unsigned char uchar_t; - -#if !defined(MIN) -#define MIN(a,b) (((a) < (b))?(a):(b)) -#endif - -#if !defined(MAX) -#define MAX(a,b) (((a) > (b))?(a):(b)) -#endif - -/* Compute the number of elements of an array */ -#define NumberOfElements(x) (sizeof(x)/sizeof((x)[0])) - -/* Compute the size of a string initialized with quotation marks */ -#define SizeOfString(string) (sizeof(string) - 1) - -#define GetRelAddr(strct, member) ((uint32_t)&(((strct*)(void *)0)->member)) -#define GetSizeOfMember(strct, member) sizeof(((strct*)(void *)0)->member) - -/* Type definitions for link configuration of instantiable layers */ -#define gInvalidInstanceId_c (instanceId_t)(-1) -typedef uint32_t instanceId_t; - -/* Bit shift definitions */ -#define BIT0 0x01 -#define BIT1 0x02 -#define BIT2 0x04 -#define BIT3 0x08 -#define BIT4 0x10 -#define BIT5 0x20 -#define BIT6 0x40 -#define BIT7 0x80 -#define BIT8 0x100 -#define BIT9 0x200 -#define BIT10 0x400 -#define BIT11 0x800 -#define BIT12 0x1000 -#define BIT13 0x2000 -#define BIT14 0x4000 -#define BIT15 0x8000 -#define BIT16 0x10000 -#define BIT17 0x20000 -#define BIT18 0x40000 -#define BIT19 0x80000 -#define BIT20 0x100000 -#define BIT21 0x200000 -#define BIT22 0x400000 -#define BIT23 0x800000 -#define BIT24 0x1000000 -#define BIT25 0x2000000 -#define BIT26 0x4000000 -#define BIT27 0x8000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -/* Shift definitions */ -#define SHIFT0 (0) -#define SHIFT1 (1) -#define SHIFT2 (2) -#define SHIFT3 (3) -#define SHIFT4 (4) -#define SHIFT5 (5) -#define SHIFT6 (6) -#define SHIFT7 (7) -#define SHIFT8 (8) -#define SHIFT9 (9) -#define SHIFT10 (10) -#define SHIFT11 (11) -#define SHIFT12 (12) -#define SHIFT13 (13) -#define SHIFT14 (14) -#define SHIFT15 (15) -#define SHIFT16 (16) -#define SHIFT17 (17) -#define SHIFT18 (18) -#define SHIFT19 (19) -#define SHIFT20 (20) -#define SHIFT21 (21) -#define SHIFT22 (22) -#define SHIFT23 (23) -#define SHIFT24 (24) -#define SHIFT25 (25) -#define SHIFT26 (26) -#define SHIFT27 (27) -#define SHIFT28 (28) -#define SHIFT29 (29) -#define SHIFT30 (30) -#define SHIFT31 (31) - -#define SHIFT32 (32) -#define SHIFT33 (33) -#define SHIFT34 (34) -#define SHIFT35 (35) -#define SHIFT36 (36) -#define SHIFT37 (37) -#define SHIFT38 (38) -#define SHIFT39 (39) -#define SHIFT40 (40) -#define SHIFT41 (41) -#define SHIFT42 (42) -#define SHIFT43 (43) -#define SHIFT44 (44) -#define SHIFT45 (45) -#define SHIFT46 (46) -#define SHIFT47 (47) -#define SHIFT48 (48) -#define SHIFT49 (49) -#define SHIFT50 (50) -#define SHIFT51 (51) -#define SHIFT52 (52) -#define SHIFT53 (53) -#define SHIFT54 (54) -#define SHIFT55 (55) -#define SHIFT56 (56) -#define SHIFT57 (57) -#define SHIFT58 (58) -#define SHIFT59 (59) -#define SHIFT60 (60) -#define SHIFT61 (61) -#define SHIFT62 (62) -#define SHIFT63 (63) - - -#endif /* _EMBEDDEDTYPES_H_ */ diff --git a/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h index fd07180f73d8..defb6fa76276 100644 --- a/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h +++ b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction.h @@ -40,7 +40,9 @@ #ifndef _FSL_OS_ABSTRACTION_H_ #define _FSL_OS_ABSTRACTION_H_ -#include "EmbeddedTypes.h" +#include +#include +#include #include "fsl_os_abstraction_config.h" #ifdef __cplusplus @@ -85,14 +87,14 @@ extern "C" typedef void (*osaTimerFctPtr_t) (void const *argument); /*! @brief Thread Definition structure contains startup information of a thread.*/ typedef struct osaThreadDef_tag { - osaTaskPtr_t pthread; /*!< start address of thread function*/ - uint32_t tpriority; /*!< initial thread priority*/ - uint32_t instances; /*!< maximum number of instances of that thread function*/ - uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ - uint32_t *tstack; + osaTaskPtr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; void *tlink; - uint8_t *tname; - bool_t useFloat; + uint8_t *tname; + bool useFloat; } osaThreadDef_t; /*! @brief Thread Link Definition structure .*/ typedef struct osaThreadLink_tag{ @@ -444,7 +446,7 @@ osaStatus_t OSA_MutexDestroy(osaMutexId_t mutexId); * @retval handler to the new event if the event is created successfully. * @retval NULL if the event can not be created. */ -osaEventId_t OSA_EventCreate(bool_t autoClear); +osaEventId_t OSA_EventCreate(bool autoClear); /*! * @brief Sets one or more event flags. @@ -498,7 +500,7 @@ osaStatus_t OSA_EventClear(osaEventId_t eventId, osaEventFlags_t flagsToClear); * FreeRTOS. * */ -osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool_t waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags); +osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags); /*! * @brief Destroys a previously created event object. diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c new file mode 100644 index 000000000000..a727780af524 --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c @@ -0,0 +1,165 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#include "cpu.h" +#include "fsl_xcvr.h" +#include "dbg_ram_capture.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if RADIO_IS_GEN_3P0 +#define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */ +#else +#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */ +#endif /* RADIO_IS_GEN_3P0 */ +#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0)) +#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0)) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void dbg_ram_init(void) +{ + XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */ + XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */ + + /* Some external code must perform the RX warmup request. */ +} + + +dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer) +{ + dbgRamStatus_t status = DBG_RAM_SUCCESS; + uint32_t temp; + volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1; + uint8_t * output_ptr; + uint16_t i; + + /* Some external code must perform the RX warmup request after the dbg_ram_init() call */ + + if (result_buffer == NULL) + { + status = DBG_RAM_FAIL_NULL_POINTER; + } + else + { + if (buffer_sz_bytes > (544*2*2)) + { + status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT; + } + else + { + temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; + switch (dbg_page) + { + case DBG_PAGE_RXDIGIQ: + case DBG_PAGE_RAWADCIQ: + case DBG_PAGE_DCESTIQ: + XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); + + while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) + { + /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ + } + /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ + output_ptr = result_buffer; +#if !RADIO_IS_GEN_2P1 + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); + pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]); +#else + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); + pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */ +#endif /* !RADIO_IS_GEN_2P1 */ + /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */ + for (i = 0; i < buffer_sz_bytes / 4; i++) + { + *output_ptr++ = *pkt_ram_ptr0++; + *output_ptr++ = *pkt_ram_ptr0++; + *output_ptr++ = *pkt_ram_ptr1++; + *output_ptr++ = *pkt_ram_ptr1++; + } + + break; + case DBG_PAGE_RXINPH: + case DBG_PAGE_DEMOD_HARD: + case DBG_PAGE_DEMOD_SOFT: + case DBG_PAGE_DEMOD_DATA: + case DBG_PAGE_DEMOD_CFO_PH: + XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); + while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) + { + /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ + } + /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ + output_ptr = result_buffer; +#if !RADIO_IS_GEN_2P1 + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); +#else + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); +#endif /* !RADIO_IS_GEN_2P1 */ + /* This is for non I/Q */ + for (i = 0; i < buffer_sz_bytes; i++) + { + *output_ptr = *pkt_ram_ptr0; + pkt_ram_ptr0++; + output_ptr++; + } + break; + case DBG_PAGE_IDLE: + default: + status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */ + break; + } + } + } + + XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */ + + /* Process the samples and copy to output pointer */ + + XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */ + XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */ + + return status; +} diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h new file mode 100644 index 000000000000..6f3458c5f99c --- /dev/null +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h @@ -0,0 +1,210 @@ +/* +* The Clear BSD License +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted (subject to the limitations in the +* disclaimer below) provided that the following conditions are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _DBG_RAM_CAPTURE_H_ +/* clang-format off */ +#define _DBG_RAM_CAPTURE_H_ +/* clang-format on */ + +#include "fsl_xcvr.h" + +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Page definitions */ +#define DBG_PAGE_IDLE (0x00) +#define DBG_PAGE_RXDIGIQ (0x01) +#define DBG_PAGE_RAWADCIQ (0x04) +#define DBG_PAGE_DCESTIQ (0x07) +#define DBG_PAGE_RXINPH (0x0A) +#define DBG_PAGE_DEMOD_HARD (0x0B) +#define DBG_PAGE_DEMOD_SOFT (0x0C) +#define DBG_PAGE_DEMOD_DATA (0x0D) +#define DBG_PAGE_DEMOD_CFO_PH (0x0E) + +typedef enum _dbgRamStatus +{ + DBG_RAM_SUCCESS = 0, + DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1, + DBG_RAM_FAIL_PAGE_ERROR = 2, + DBG_RAM_FAIL_NULL_POINTER = 3, + DBG_RAM_INVALID_TRIG_SETTING = 4, + DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5, + DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */ +} dbgRamStatus_t; + +#if RADIO_IS_GEN_3P0 +typedef enum _dbgRamStartTriggerType +{ + NO_START_TRIG = 0, + START_ON_FSK_PREAMBLE_FOUND = 1, + START_ON_FSK_AA_MATCH = 2, + START_ON_ZBDEMOD_PREAMBLE_FOUND = 3, + START_ON_ZBDEMOD_SFD_MATCH = 4, + START_ON_AGC_DCOC_GAIN_CHG = 5, + START_ON_TSM_RX_DIG_EN = 6, + START_ON_TSM_SPARE2_EN = 7, + INVALID_START_TRIG = 8 +} dbgRamStartTriggerType; + +typedef enum _dbgRamStopTriggerType +{ + NO_STOP_TRIG = 0, + STOP_ON_FSK_PREAMBLE_FOUND = 1, + STOP_ON_FSK_AA_MATCH = 2, + STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3, + STOP_ON_ZBDEMOD_SFD_MATCH = 4, + STOP_ON_AGC_DCOC_GAIN_CHG = 5, + STOP_ON_TSM_RX_DIG_EN = 6, + STOP_ON_TSM_SPARE3_EN = 7, + STOP_ON_TSM_PLL_UNLOCK = 8, + STOP_ON_BLE_CRC_ERROR_INC = 9, + STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10, + STOP_ON_GENFSK_HEADER_FAIL = 11, + INVALID_STOP_TRIG = 12 +} dbgRamStopTriggerType; +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief This function prepares for sample capture to packet RAM. + * + * \return None. + * + * \details + * This routine assumes that some other functions in the calling routine both set + * the channel and force RX warmup before calling ::dbg_ram_capture(). + ***********************************************************************************/ +void dbg_ram_init(void); + +/*! ********************************************************************************* + * \brief This function performs any state restoration at the completion of PKT RAM capture. + * + * \details + * Any clocks enabled to the packet RAM capture circuitry are disabled. + ***********************************************************************************/ +void dbg_ram_release(void); + +#if RADIO_IS_GEN_3P0 +/*! ********************************************************************************* + * \brief This function initiates the capture of transceiver data to the transceiver packet RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled). + * \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled). + * + * \return Status of the request. + * + * \details + * This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger + * settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to + * perform a blocking wait for completion or allow polling for completion of the capture. + * After any capture has completed, a separate routine must be called to postprocess the capture and copy all + * data out of the packet RAM into a normal RAM buffer. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig); + +/*! ********************************************************************************* + * \brief This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM. + * + * \return Status of the request, DBG_RAM_SUCCESS if capture is complete. + * + * \details + * This function performs a wait loop for capture completion and may take an indeterminate amount of time for + * some capture trigger types. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */ + +/*! ********************************************************************************* + * \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM. + * + * \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete. + * + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */ + +/*! ********************************************************************************* + * \brief This function processes the captured data into a usable order and copies from packet RAM to normal RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) + * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. + * + * \return None. + * + * \details + * Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM + * (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM. + * If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out. + * If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */ + +#else +/*! ********************************************************************************* + * \brief This function captures transceiver data to the transceiver packet RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) + * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. + * + * \return None. + * + * \details + * The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be + * copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have + * been copied. Data will be copied + * NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has + * not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is + * intended to be used with manually triggered RX where RX data will continue as long as needed. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); +#endif /* RADIO_IS_GEN_3P0 */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _DBG_RAM_CAPTURE_H_ */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index a0cdf36c86de..3d9f0b339777 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -33,11 +33,13 @@ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "fsl_device_registers.h" -#include "fsl_common.h" +#include +#include +#include +#include +#include "cpu.h" #include "fsl_xcvr.h" #include "fsl_xcvr_trim.h" -#include #include "ifr_radio.h" /******************************************************************************* diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h index f67292a75629..295c73e0cc31 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -38,7 +38,7 @@ #define _FSL_XCVR_H_ /* clang-format on */ -#include "fsl_device_registers.h" +#include "cpu.h" #include "fsl_xcvr_trim.h" #if defined(gMWS_UseCoexistence_d) #if gMWS_UseCoexistence_d diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c index a47c4e1f9bbe..2220b86d8af5 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_common_config.c @@ -482,7 +482,7 @@ const xcvr_common_config_t xcvr_common_config = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7), .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ), - .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), + .recycle_count_init_32mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */ .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c index e79e0c6d5385..bd975a21680b 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c @@ -167,7 +167,6 @@ const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), #endif - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c index d2ccf8d36522..1977c6311c20 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c @@ -85,7 +85,7 @@ const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = /* XCVR_RX_DIG configs */ .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index 360269966501..4ab38c31a88e 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -33,17 +33,22 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "fsl_device_registers.h" -#include "fsl_common.h" +#include +#include "cpu.h" #include "fsl_xcvr.h" #include "fsl_xcvr_trim.h" #include "dbg_ram_capture.h" -#include "math.h" /******************************************************************************* * Definitions ******************************************************************************/ +#ifndef MIN +#define MIN(a,b) \ + ({ __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a < _b ? _a : _b; }) +#endif /******************************************************************************* * Prototypes diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h index 13cbd3805f83..eb32afae42fd 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -37,8 +37,7 @@ #define _FSL_XCVR_TRIM_H_ /* Clang-format on. */ -//#include "fsl_common.h" -#include "fsl_device_registers.h" +#include "cpu.h" #include "fsl_xcvr.h" /*! diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c index 4c3b59a165ec..4a2a58067b50 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c @@ -34,7 +34,7 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "fsl_device_registers.h" +#include "cpu.h" #include "fsl_xcvr.h" #include "ifr_radio.h" #include "fsl_os_abstraction.h" @@ -387,11 +387,11 @@ void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) #if RADIO_IS_GEN_3P0 read_addr = K3_BASE_INDEX; #else -#ifdef CPU_MKW41Z256VHT4 +#ifdef CPU_MODEL_MKW41Z256VHT4 read_addr = KW4x_256_BASE; #else read_addr = KW4x_512_BASE; -#endif /* CPU_MKW41Z256VHT4 */ +#endif /* CPU_MODEL_MKW41Z256VHT4 */ #endif /* RADIO_IS_GEN_3P0 */ /* Read first entry in IFR table */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h index 345dc9f090e2..8580b928f8e2 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h @@ -60,14 +60,14 @@ #define IS_A_SW_ID(x) ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x))) /* K3 valid registers support */ -#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) +#if (defined(CPU_MODEL_K32W042S1M2CAx_M0P) || defined(CPU_MODEL_K32W042S1M2VPJ_M0P)) #define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */ -#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */ +#endif /* (defined(CPU_MODEL_K32W042S1M2CAx_M0P) || defined(CPU_MODEL_K32W042S1M2VPJ_M0P)) */ /* KW41 and KW35/36 valid registers support */ -#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) || \ - defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) || \ - defined(CPU_MKW21Z256VHT4) || defined(CPU_MKW21Z512VHT4) || \ - defined(CPU_MKW35A512VFP4) || defined(CPU_MKW36A512VFP4) ) +#if (defined(CPU_MODEL_MKW41Z256VHT4) || defined(CPU_MODEL_MKW41Z512VHT4) || \ + defined(CPU_MODEL_MKW31Z256VHT4) || defined(CPU_MODEL_MKW31Z512VHT4) || \ + defined(CPU_MODEL_MKW21Z256VHT4) || defined(CPU_MODEL_MKW21Z512VHT4) || \ + defined(CPU_MODEL_MKW35A512VFP4) || defined(CPU_MODEL_MKW36A512VFP4) ) #define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */ #endif From 63c244b66d5ecbe5888edc0d14dc42027e202a30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 14 Jun 2018 17:14:31 +0200 Subject: [PATCH 06/82] squash kw41zrf fix vendor LLVM warnings --- drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index 3d9f0b339777..6b15959cf2dd 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -1234,11 +1234,11 @@ void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address) } else { - uint8_t dummy; + volatile uint8_t dummy = 0; while(1) { - dummy = dummy; + ++dummy; } } } From 907ae8ec951ecf2e199d71d8f8aedb7d41b4d34d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 29 Oct 2017 01:28:31 +0200 Subject: [PATCH 07/82] squash kw41zrf wait for OSC ready before accessing the link layer in wait_idle --- drivers/kw41zrf/kw41zrf_netdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index cf20a823c26a..c83e4f3882ba 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -180,6 +180,8 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) */ static void kw41zrf_wait_idle(kw41zrf_t *dev) { + /* Wait for oscillator ready signal when coming out of sleep mode */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} /* make sure any ongoing T or TR sequence is finished */ if (kw41zrf_can_switch_to_idle(dev) == 0) { DEBUG("[kw41zrf] TX already in progress\n"); From b1ed075f1f2191df06b370e50fb194fcae3b01ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 25 Sep 2017 08:06:39 +0200 Subject: [PATCH 08/82] kw41zrf: Disable VLPS+LLS when radio is active --- drivers/include/kw41zrf.h | 1 + drivers/kw41zrf/kw41zrf.c | 1 + drivers/kw41zrf/kw41zrf_intern.c | 13 +++++++++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 573ed22465cc..195dc5fda8d4 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -133,6 +133,7 @@ typedef struct { uint8_t csma_be; /**< Counter used internally by send implementation */ uint8_t csma_num_backoffs; /**< Counter used internally by send implementation */ uint8_t num_retrans; /**< Counter used internally by send implementation */ + bool pm_blocked; /**< true if we have blocked a low power mode in the CPU */ /** @} */ } kw41zrf_t; diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 42e37a9e8cb2..d4ec0417185c 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -70,6 +70,7 @@ void kw41zrf_setup(kw41zrf_t *dev) netdev->driver = &kw41zrf_driver; /* initialize device descriptor */ dev->idle_seq = XCVSEQ_RECEIVE; + dev->pm_blocked = false; /* Set default parameters according to STD IEEE802.15.4-2015 */ dev->csma_max_be = 5; dev->csma_min_be = 3; diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 2ca00756c055..a016dee447de 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -21,6 +21,7 @@ #include "kw41zrf.h" #include "kw41zrf_getset.h" #include "kw41zrf_intern.h" +#include "pm_layered.h" #define ENABLE_DEBUG (0) #include "debug.h" @@ -113,6 +114,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Convert DSM ticks (32.768 kHz) to event timer ticks (1 MHz) */ uint64_t tmp = (uint64_t)(RSIM->ZIG_WAKE - RSIM->ZIG_SLEEP) * 15625ul; uint32_t usec = (tmp >> 9); /* equivalent to (usec / 512) */ + /* Add the offset */ ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK | ZLL_EVENT_TMR_EVENT_TMR(usec); break; @@ -158,6 +160,17 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) while ((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) == 0) { kw41zrf_abort_sequence(dev); } + /* Disable some CPU power management if we need to be active, otherwise the + * radio will be stuck in state retention mode. */ + if (!dev->pm_blocked && ((seq & ZLL_PHY_CTRL_XCVSEQ_MASK) != XCVSEQ_IDLE)) { + pm_block(KINETIS_PM_LLS); + dev->pm_blocked = true; + } + else if (dev->pm_blocked && ((seq & ZLL_PHY_CTRL_XCVSEQ_MASK) != XCVSEQ_IDLE)) { + pm_unblock(KINETIS_PM_LLS); + dev->pm_blocked = false; + } + /* Clear interrupt flags, sometimes the sequence complete flag is immediately set */ ZLL->IRQSTS = ZLL->IRQSTS; ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | ZLL_PHY_CTRL_SEQMSK_MASK)) | seq; From 18c625af3678f069def4b92cd155c7259afd4580 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 29 Oct 2017 01:27:23 +0200 Subject: [PATCH 09/82] squash kw41zrf LLS fixes --- drivers/kw41zrf/include/kw41zrf_intern.h | 1 + drivers/kw41zrf/kw41zrf.c | 8 +++++--- drivers/kw41zrf/kw41zrf_intern.c | 22 ++++++++++++---------- drivers/kw41zrf/kw41zrf_netdev.c | 11 ++++++++++- 4 files changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 2bf7c8ee39e9..00602af9a956 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -57,6 +57,7 @@ typedef enum kw41zrf_timer_timebase { static inline void kw41zrf_mask_irqs(void) { NVIC_DisableIRQ(Radio_1_IRQn); + NVIC_ClearPendingIRQ(Radio_1_IRQn); } /** diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index d4ec0417185c..39f3d90e6232 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -87,9 +87,11 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) return -ENODEV; } - /* Enable RSIM oscillator in Run mode, in order to be able to access the XCVR - * registers if using the internal reference clock for the CPU core */ - bit_set32(&RSIM->CONTROL, RSIM_CONTROL_RF_OSC_EN_SHIFT); + /* Enable RSIM oscillator in all power modes >LLS, in order to be able to + * access the XCVR and ZLL registers when using the internal reference clock + * for the CPU core */ + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; + /* Wait for oscillator ready signal */ while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index a016dee447de..0a07d0677f8f 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -101,6 +101,14 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Already awake */ break; } + /* Disable some CPU power management if we need to be active, otherwise the + * radio will be stuck in state retention mode. */ + if (!dev->pm_blocked) { + pm_block(KINETIS_PM_LLS); + dev->pm_blocked = true; + } + /* Wait for oscillator ready signal before attempting to recover from DSM */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} /* Assume DSM timer has been running since we entered sleep mode */ /* In case it was not already running, however, we still set the * enable flag here. */ @@ -125,6 +133,10 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Already asleep */ break; } + if (dev->pm_blocked) { + pm_unblock(KINETIS_PM_LLS); + dev->pm_blocked = false; + } /* Clear IRQ flags */ RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; /* Enable timer triggered sleep */ @@ -160,16 +172,6 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) while ((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) == 0) { kw41zrf_abort_sequence(dev); } - /* Disable some CPU power management if we need to be active, otherwise the - * radio will be stuck in state retention mode. */ - if (!dev->pm_blocked && ((seq & ZLL_PHY_CTRL_XCVSEQ_MASK) != XCVSEQ_IDLE)) { - pm_block(KINETIS_PM_LLS); - dev->pm_blocked = true; - } - else if (dev->pm_blocked && ((seq & ZLL_PHY_CTRL_XCVSEQ_MASK) != XCVSEQ_IDLE)) { - pm_unblock(KINETIS_PM_LLS); - dev->pm_blocked = false; - } /* Clear interrupt flags, sometimes the sequence complete flag is immediately set */ ZLL->IRQSTS = ZLL->IRQSTS; diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index c83e4f3882ba..9dd0a1e10380 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -28,6 +28,7 @@ #include "net/ieee802154.h" #include "net/netdev.h" #include "net/netdev/ieee802154.h" +#include "pm_layered.h" #include "kw41zrf.h" #include "kw41zrf_netdev.h" @@ -180,7 +181,7 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) */ static void kw41zrf_wait_idle(kw41zrf_t *dev) { - /* Wait for oscillator ready signal when coming out of sleep mode */ + /* Wait for oscillator ready signal if coming out of sleep mode */ while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} /* make sure any ongoing T or TR sequence is finished */ if (kw41zrf_can_switch_to_idle(dev) == 0) { @@ -188,6 +189,7 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) num_irqs_handled = num_irqs_queued; spinning_for_irq = 1; thread_flags_clear(KW41ZRF_THREAD_FLAG_ISR); + pm_block(KINETIS_PM_LLS); while (1) { /* TX in progress */ /* Handle any outstanding IRQ first */ @@ -201,6 +203,7 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) thread_flags_wait_any(KW41ZRF_THREAD_FLAG_ISR); DEBUG("[kw41zrf] waited ISR\n"); } + pm_unblock(KINETIS_PM_LLS); spinning_for_irq = 0; DEBUG("[kw41zrf] previous TX done\n"); } @@ -414,6 +417,9 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -ENODEV; } + /* Wait for oscillator ready signal if coming out of sleep mode */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + switch (opt) { case NETOPT_MAX_PACKET_SIZE: if (len < sizeof(int16_t)) { @@ -587,6 +593,9 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, return -ENODEV; } + /* Wait for oscillator ready signal if coming out of sleep mode */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + switch (opt) { case NETOPT_ADDRESS: if (len > sizeof(uint16_t)) { From 66f8575ccc3c461c11432363814d4ca680d7706d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 3 Dec 2017 22:45:11 +0100 Subject: [PATCH 10/82] squash kw41zrf Improve RF_OSC_CTRL handling --- drivers/include/kw41zrf.h | 1 + drivers/kw41zrf/kw41zrf.c | 11 +++-------- drivers/kw41zrf/kw41zrf_intern.c | 29 +++++++++++++++++++++++------ 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 195dc5fda8d4..147df313d877 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -134,6 +134,7 @@ typedef struct { uint8_t csma_num_backoffs; /**< Counter used internally by send implementation */ uint8_t num_retrans; /**< Counter used internally by send implementation */ bool pm_blocked; /**< true if we have blocked a low power mode in the CPU */ + uint32_t rf_osc_en_idle; /**< RF_OSC_EN bits setting when RF module is in standby */ /** @} */ } kw41zrf_t; diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 39f3d90e6232..43fc2a300640 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -87,14 +87,9 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) return -ENODEV; } - /* Enable RSIM oscillator in all power modes >LLS, in order to be able to - * access the XCVR and ZLL registers when using the internal reference clock - * for the CPU core */ - RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; - - - /* Wait for oscillator ready signal */ - while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + /* Save a copy of the RF_OSC_EN setting, the vendor XCVR_Init function + * modifies these bits */ + dev->rf_osc_en_idle = RSIM->CONTROL & RSIM_CONTROL_RF_OSC_EN_MASK; xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); if (xcvrStatus != gXcvrSuccess_c) { diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 0a07d0677f8f..5ffe7054fe3f 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -97,23 +97,33 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) switch (pm) { case KW41ZRF_POWER_IDLE: { - if (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) { - /* Already awake */ - break; - } /* Disable some CPU power management if we need to be active, otherwise the * radio will be stuck in state retention mode. */ if (!dev->pm_blocked) { pm_block(KINETIS_PM_LLS); dev->pm_blocked = true; } - /* Wait for oscillator ready signal before attempting to recover from DSM */ - while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + /* Restore saved RF oscillator settings, enable oscillator in RUN mode + * to allow register access */ + /* This is also where the oscillator is enabled during kw41zrf_init: + * kw41zrf_init -> kw41zrf_reset_phy -> kw41zrf_set_power_mode + * => Do not return before this line during init */ + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN(1); /* Assume DSM timer has been running since we entered sleep mode */ /* In case it was not already running, however, we still set the * enable flag here. */ + /* RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN lets the link layer + * request the RF oscillator to remain on during STOP and VLPS, to + * allow stopping the CPU core without affecting TX or RX operations */ RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK | RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK); + /* Wait for oscillator ready signal before attempting to recover from DSM */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + /* If we are already awake we can just return now. */ + if (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) { + /* Already awake */ + break; + } /* The wake target must be at least (4 + RSIM_DSM_OSC_OFFSET) ticks * into the future, to let the oscillator stabilize before switching * on the clocks */ @@ -154,6 +164,13 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK | RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK); while (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) {} + /* Restore saved RF_OSC_EN bits (from kw41zrf_init) + * This will disable the RF oscillator unless the system was + * configured to use the RF oscillator before kw41zrf_init() was + * called, for example when using the RF oscillator for the CPU core + * clock. */ + RSIM->CONTROL = (RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) | + dev->rf_osc_en_idle; /* Let the DSM timer run until we exit deep sleep mode */ break; } From bcce5cd60564196134525fc1351e2a50809ff95e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 3 Dec 2017 22:46:29 +0100 Subject: [PATCH 11/82] squash kw41zrf Check that radio is awake before attempting to set options --- drivers/kw41zrf/kw41zrf_getset.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 6d2da5f370bf..bc640eb39cc8 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -187,6 +187,24 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) { DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state); + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Transceiver is sleeping */ + switch (option) { + /* Modifying these options require that the transceiver is not in + * deep sleep mode */ + case KW41ZRF_OPT_CSMA: + case KW41ZRF_OPT_PROMISCUOUS: + case KW41ZRF_OPT_AUTOACK: + case KW41ZRF_OPT_ACK_REQ: + case KW41ZRF_OPT_TELL_RX_START: + LOG_ERROR("[kw41zrf] Attempt to modify option %04x while radio is sleeping\n", (unsigned) option); + return; + + default: + break; + } + } + /* set option field */ if (state) { dev->netdev.flags |= option; @@ -230,6 +248,7 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) case KW41ZRF_OPT_TELL_TX_START: LOG_DEBUG("[kw41zrf] enable: TELL_TX_START (ignored)\n"); + default: /* do nothing */ break; From a9ba20d62d00c63170c5c5ac04c127fc19c6c314 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 3 Dec 2017 23:43:33 +0100 Subject: [PATCH 12/82] squash kw41zrf ignore IRQ while in DSM --- drivers/kw41zrf/kw41zrf_netdev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 9dd0a1e10380..8d57265fda8a 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -1045,6 +1045,13 @@ static void kw41zrf_netdev_isr(netdev_t *netdev) if (!spinning_for_irq) { num_irqs_handled = num_irqs_queued; } + + /* ZLL register access requires that the transceiver is not in deep sleep mode */ + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Transceiver is sleeping, the IRQ must have occurred before entering + * sleep, discard the call */ + return; + } uint32_t irqsts = ZLL->IRQSTS; /* Clear all IRQ flags now */ From 461768d9e1c1de58e9681e5e4e7f7e0490ca194d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 3 Dec 2017 23:45:06 +0100 Subject: [PATCH 13/82] squash kw41zrf Turn power on for netdev get/set if necessary --- drivers/kw41zrf/kw41zrf_netdev.c | 305 +++++++++++++++++++------------ 1 file changed, 192 insertions(+), 113 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 8d57265fda8a..d1cdcf15a6d5 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include @@ -377,7 +378,10 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) static netopt_state_t kw41zrf_netdev_get_state(kw41zrf_t *dev) { (void) dev; + /* ZLL register access require that the transceiver is powered on and not in + * deep sleep mode */ if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Transceiver is in deep sleep mode */ return NETOPT_STATE_SLEEP; } uint32_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; @@ -386,25 +390,32 @@ static netopt_state_t kw41zrf_netdev_get_state(kw41zrf_t *dev) case XCVSEQ_TRANSMIT: case XCVSEQ_TX_RX: return NETOPT_STATE_TX; + case XCVSEQ_CCA: case XCVSEQ_CONTINUOUS_CCA: return NETOPT_STATE_RX; + case XCVSEQ_RECEIVE: { uint32_t seq_state = ZLL->SEQ_STATE; if (seq_state & ZLL_SEQ_STATE_SFD_DET_MASK) { + /* SFD detection has been triggered */ if (seq_state & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK) { + /* packet reception is in progress */ return NETOPT_STATE_RX; } } - /* IDLE in netopt means on, and listening for incoming packets */ + /* NETOPT_STATE_IDLE means on, and listening for incoming packets */ return NETOPT_STATE_IDLE; } + case XCVSEQ_IDLE: /* SEQ_IDLE in kw41z means on, but not listening for incoming traffic */ return NETOPT_STATE_STANDBY; + default: /* Unknown state */ + LOG_ERROR("[kw41z] in unknown sequence: 0x%02" PRIx32 "\n", seq); return NETOPT_STATE_OFF; } } @@ -417,10 +428,15 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -ENODEV; } - /* Wait for oscillator ready signal if coming out of sleep mode */ - while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} - + /* These settings do not require the transceiver to be powered on */ switch (opt) { + case NETOPT_STATE: + if (len < sizeof(netopt_state_t)) { + return -EOVERFLOW; + } + *((netopt_state_t *)value) = kw41zrf_netdev_get_state(dev); + return sizeof(netopt_state_t); + case NETOPT_MAX_PACKET_SIZE: if (len < sizeof(int16_t)) { return -EOVERFLOW; @@ -429,13 +445,6 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) *((uint16_t *)value) = KW41ZRF_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD; return sizeof(uint16_t); - case NETOPT_STATE: - if (len < sizeof(netopt_state_t)) { - return -EOVERFLOW; - } - *((netopt_state_t *)value) = kw41zrf_netdev_get_state(dev); - return sizeof(netopt_state_t); - case NETOPT_PRELOADING: if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { *((netopt_enable_t *)value) = NETOPT_ENABLE; @@ -507,6 +516,54 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) *((uint8_t *)value) = dev->max_retrans; return sizeof(uint8_t); + case NETOPT_TX_RETRIES_NEEDED: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + else { + *(uint8_t *)value = dev->num_retrans; + } + return sizeof(uint8_t); + + case NETOPT_CHANNEL_PAGE: + if (len < sizeof(uint16_t)) { + return -EOVERFLOW; + } + else { + *(uint16_t *)value = 0; + } + return sizeof(uint16_t); + + default: + break; + } + + /* The below settings require the transceiver to be powered on */ + bool put_to_sleep_when_done = false; + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Transceiver is in deep sleep mode */ + switch (opt) { + case NETOPT_TX_POWER: + case NETOPT_IS_CHANNEL_CLR: + case NETOPT_CCA_THRESHOLD: + case NETOPT_CCA_MODE: + case NETOPT_LAST_ED_LEVEL: + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + DEBUG("[kw41zrf] Wake to get %s\n", netopt2str(opt)); + put_to_sleep_when_done = true; + break; + + default: + break; + } + } + else { + /* Wait for oscillator ready signal if the CPU is coming out of low + * power mode */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + } + + switch (opt) { case NETOPT_TX_POWER: if (len < sizeof(int16_t)) { return -EOVERFLOW; @@ -559,28 +616,15 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) } return sizeof(int8_t); - case NETOPT_TX_RETRIES_NEEDED: - if (len < sizeof(uint8_t)) { - return -EOVERFLOW; - } - else { - *(uint8_t *)value = dev->num_retrans; - } - return sizeof(uint8_t); - - case NETOPT_CHANNEL_PAGE: - if (len < sizeof(uint16_t)) { - return -EOVERFLOW; - } - else { - *(uint16_t *)value = 0; - } - return sizeof(uint16_t); - default: break; } + if (put_to_sleep_when_done) { + DEBUG("[kw41zrf] Go back to sleep\n"); + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); + } + return netdev_ieee802154_get((netdev_ieee802154_t *)netdev, opt, value, len); } @@ -593,78 +637,116 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, return -ENODEV; } - /* Wait for oscillator ready signal if coming out of sleep mode */ - while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} - + /* These settings do not require the transceiver to be awake */ switch (opt) { - case NETOPT_ADDRESS: - if (len > sizeof(uint16_t)) { + case NETOPT_CHANNEL_PAGE: + res = -EINVAL; + break; + + case NETOPT_STATE: + if (len > sizeof(netopt_state_t)) { res = -EOVERFLOW; } else { - kw41zrf_set_addr_short(dev, *((const uint16_t *)value)); - /* don't set res to set netdev_ieee802154_t::short_addr */ + res = kw41zrf_netdev_set_state(dev, *((const netopt_state_t *)value)); } break; - case NETOPT_ADDRESS_LONG: - if (len > sizeof(uint64_t)) { - return -EOVERFLOW; - } - else { - kw41zrf_set_addr_long(dev, *((const uint64_t *)value)); - /* don't set res to set netdev_ieee802154_t::short_addr */ - } + case NETOPT_PRELOADING: + kw41zrf_set_option(dev, KW41ZRF_OPT_PRELOADING, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); break; - case NETOPT_NID: - if (len > sizeof(uint16_t)) { - return -EOVERFLOW; - } + case NETOPT_RX_END_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; - else { - kw41zrf_set_pan(dev, *((const uint16_t *)value)); - /* don't set res to set netdev_ieee802154_t::pan */ - } + case NETOPT_TX_START_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_START, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); break; - case NETOPT_CHANNEL: + case NETOPT_TX_END_IRQ: + kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, + ((const netopt_enable_t *)value)[0]); + res = sizeof(netopt_enable_t); + break; + + case NETOPT_CSMA_RETRIES: if (len < sizeof(uint8_t)) { - res = -EINVAL; + res = -EOVERFLOW; } else { - uint8_t chan = ((const uint8_t *)value)[0]; - if (kw41zrf_set_channel(dev, chan)) { - res = -EINVAL; - break; - } - /* don't set res to set netdev_ieee802154_t::chan */ + dev->csma_max_backoffs = *((const uint8_t*)value); + res = sizeof(uint8_t); } break; - case NETOPT_CHANNEL_PAGE: - res = -EINVAL; - break; - - case NETOPT_TX_POWER: - if (len < sizeof(int16_t)) { + case NETOPT_CSMA_MAXBE: + if (len < sizeof(uint8_t)) { res = -EOVERFLOW; } else { - kw41zrf_set_tx_power(dev, *(const int16_t *)value); - res = sizeof(int16_t); + dev->csma_max_be = *((const uint8_t*)value); + res = sizeof(uint8_t); } break; - case NETOPT_STATE: - if (len > sizeof(netopt_state_t)) { + case NETOPT_CSMA_MINBE: + if (len < sizeof(uint8_t)) { res = -EOVERFLOW; } else { - res = kw41zrf_netdev_set_state(dev, *((const netopt_state_t *)value)); + dev->csma_min_be = *((const uint8_t*)value); + res = sizeof(uint8_t); } break; + case NETOPT_RETRANS: + if (len < sizeof(uint8_t)) { + return -EOVERFLOW; + } + dev->max_retrans = *((const uint8_t *)value); + res = sizeof(uint8_t); + break; + + default: + break; + } + + bool put_to_sleep_when_done = false; + + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Transceiver is in deep sleep mode, check if setting the option + * requires the radio powered on */ + switch (opt) { + case NETOPT_AUTOACK: + case NETOPT_ACK_REQ: + case NETOPT_PROMISCUOUSMODE: + case NETOPT_RX_START_IRQ: + case NETOPT_CSMA: + case NETOPT_ADDRESS: + case NETOPT_ADDRESS_LONG: + case NETOPT_NID: + case NETOPT_CHANNEL: + case NETOPT_TX_POWER: + case NETOPT_CCA_THRESHOLD: + case NETOPT_CCA_MODE: + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + DEBUG("[kw41zrf] Wake to set %s\n", netopt2str(opt)); + put_to_sleep_when_done = true; + break; + + default: + break; + } + } + + switch (opt) { case NETOPT_AUTOACK: /* Set up HW generated automatic ACK after Receive */ kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, @@ -678,12 +760,6 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, /* don't set res to set netdev_ieee802154_t::flags */ break; - case NETOPT_PRELOADING: - kw41zrf_set_option(dev, KW41ZRF_OPT_PRELOADING, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); - break; - case NETOPT_PROMISCUOUSMODE: kw41zrf_set_option(dev, KW41ZRF_OPT_PROMISCUOUS, ((const netopt_enable_t *)value)[0]); @@ -696,66 +772,64 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, res = sizeof(netopt_enable_t); break; - case NETOPT_RX_END_IRQ: - kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); - break; - - case NETOPT_TX_START_IRQ: - kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_START, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); - break; - - case NETOPT_TX_END_IRQ: - kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); - break; - case NETOPT_CSMA: kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, ((const netopt_enable_t *)value)[0]); res = sizeof(netopt_enable_t); break; - case NETOPT_CSMA_RETRIES: - if (len < sizeof(uint8_t)) { + case NETOPT_ADDRESS: + if (len > sizeof(uint16_t)) { res = -EOVERFLOW; } else { - dev->csma_max_backoffs = *((const uint8_t*)value); - res = sizeof(uint8_t); + kw41zrf_set_addr_short(dev, *((const uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ } break; - case NETOPT_CSMA_MAXBE: - if (len < sizeof(uint8_t)) { - res = -EOVERFLOW; + case NETOPT_ADDRESS_LONG: + if (len > sizeof(uint64_t)) { + return -EOVERFLOW; } else { - dev->csma_max_be = *((const uint8_t*)value); - res = sizeof(uint8_t); + kw41zrf_set_addr_long(dev, *((const uint64_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ } break; - case NETOPT_CSMA_MINBE: - if (len < sizeof(uint8_t)) { - res = -EOVERFLOW; + case NETOPT_NID: + if (len > sizeof(uint16_t)) { + return -EOVERFLOW; } else { - dev->csma_min_be = *((const uint8_t*)value); - res = sizeof(uint8_t); + kw41zrf_set_pan(dev, *((const uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::pan */ } break; - case NETOPT_RETRANS: + case NETOPT_CHANNEL: if (len < sizeof(uint8_t)) { - return -EOVERFLOW; + res = -EINVAL; + } + else { + uint8_t chan = ((const uint8_t *)value)[0]; + if (kw41zrf_set_channel(dev, chan)) { + res = -EINVAL; + break; + } + /* don't set res to set netdev_ieee802154_t::chan */ + } + break; + + case NETOPT_TX_POWER: + if (len < sizeof(int16_t)) { + res = -EOVERFLOW; + } + else { + kw41zrf_set_tx_power(dev, *(const int16_t *)value); + res = sizeof(int16_t); } - dev->max_retrans = *((const uint8_t *)value); - res = sizeof(uint8_t); break; case NETOPT_CCA_THRESHOLD: @@ -793,6 +867,11 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; } + if (put_to_sleep_when_done) { + DEBUG("[kw41zrf] Go back to sleep\n"); + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); + } + if (res == -ENOTSUP) { res = netdev_ieee802154_set((netdev_ieee802154_t *)netdev, opt, value, len); From 8de0889a2b0c820493abaf2d7ffc501800b5dd2a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 4 Dec 2017 00:34:48 +0100 Subject: [PATCH 14/82] squash kw41zrf fix init error RF_OSC_EN --- drivers/kw41zrf/kw41zrf.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 43fc2a300640..3a855ebf8f26 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -87,12 +87,23 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) return -ENODEV; } - /* Save a copy of the RF_OSC_EN setting, the vendor XCVR_Init function - * modifies these bits */ + /* Save a copy of the RF_OSC_EN setting to use when the radio is in deep sleep */ dev->rf_osc_en_idle = RSIM->CONTROL & RSIM_CONTROL_RF_OSC_EN_MASK; + /* Enable RSIM oscillator in RUN and WAIT modes, in order to be able to + * access the XCVR and ZLL registers when using the internal reference clock + * for the CPU core */ + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN(1); + + /* Wait for oscillator ready signal */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); + if (xcvrStatus != gXcvrSuccess_c) { + /* initialization error signaled from vendor driver */ + /* Restore saved RF_OSC_EN setting */ + RSIM->CONTROL = (RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) | dev->rf_osc_en_idle; return -EIO; } From 35ad28c6b1c3da8def7e704cb83d472d991883e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 29 Nov 2017 17:38:38 +0100 Subject: [PATCH 15/82] squash kw41zrf set idle_state on sleep --- drivers/kw41zrf/kw41zrf_netdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index d1cdcf15a6d5..8457e8353680 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -344,6 +344,7 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) case NETOPT_STATE_SLEEP: kw41zrf_abort_sequence(dev); kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); + dev->idle_seq = XCVSEQ_IDLE; break; case NETOPT_STATE_STANDBY: kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); From 4f5c067ca4058341b9061af2179114c6c6a269d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 4 Dec 2017 06:39:38 +0100 Subject: [PATCH 16/82] squash kw41zrf fix race in DSM sleep --- drivers/kw41zrf/kw41zrf_intern.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 5ffe7054fe3f..caa69ffde703 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -128,13 +128,19 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * into the future, to let the oscillator stabilize before switching * on the clocks */ RSIM->ZIG_WAKE = KW41ZRF_DSM_EXIT_DELAY + RSIM->DSM_TIMER + RSIM->DSM_OSC_OFFSET; + /* Wait to come out of DSM */ while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) {} + /* Convert DSM ticks (32.768 kHz) to event timer ticks (1 MHz) */ uint64_t tmp = (uint64_t)(RSIM->ZIG_WAKE - RSIM->ZIG_SLEEP) * 15625ul; uint32_t usec = (tmp >> 9); /* equivalent to (usec / 512) */ /* Add the offset */ ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK | ZLL_EVENT_TMR_EVENT_TMR(usec); + + /* Disable DSM timer triggered sleep */ + ZLL->DSM_CTRL &= ~ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; + break; } case KW41ZRF_POWER_DSM: @@ -147,17 +153,23 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) pm_unblock(KINETIS_PM_LLS); dev->pm_blocked = false; } + /* Race condition: if sleep is re-triggered after wake before the + * DSM_ZIG_FINISHED flag has been switched off, then the RSIM + * becomes stuck and never enters DSM. + * The time from ZIG_WAKE until DSM_ZIG_FINISHED is turned off seem + * to be constant at 2 DSM ticks */ + while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK) {} /* Clear IRQ flags */ RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; /* Enable timer triggered sleep */ - ZLL->DSM_CTRL = ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; - /* Set sleep start time */ - /* The target time must be at least 4 DSM_TIMER ticks into the future */ - RSIM->ZIG_SLEEP = RSIM->DSM_TIMER + KW41ZRF_DSM_ENTER_DELAY; + ZLL->DSM_CTRL |= ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; /* The device will automatically wake up 8.5 minutes from now if not * awoken sooner by software */ /* TODO handle automatic wake in the ISR if it becomes an issue */ - RSIM->ZIG_WAKE = RSIM->DSM_TIMER - 1; + RSIM->ZIG_WAKE = RSIM->DSM_TIMER - KW41ZRF_DSM_EXIT_DELAY - RSIM->DSM_OSC_OFFSET; + /* Set sleep start time */ + /* The target time must be at least 4 DSM_TIMER ticks into the future */ + RSIM->ZIG_SLEEP = RSIM->DSM_TIMER + KW41ZRF_DSM_ENTER_DELAY; /* Start the 32.768 kHz DSM timer in case it was not already running */ /* If ZIG_SYSCLK_REQUEST_EN is not set then the hardware will not * enter DSM and we get stuck in the while() below */ From fb0f55196b77f34494ad65aa796414ed2aeb3426 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 5 Dec 2017 20:28:07 +0100 Subject: [PATCH 17/82] squash kw41zrf avoid crash if transceiver is already in DSM --- drivers/kw41zrf/kw41zrf_netdev.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 8457e8353680..c3ffd13a20c2 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -342,6 +342,10 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) /* There is no deeper 'off' mode than deep sleep mode */ /* fall through */ case NETOPT_STATE_SLEEP: + if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + /* Transceiver is already in deep sleep mode */ + break;; + } kw41zrf_abort_sequence(dev); kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); dev->idle_seq = XCVSEQ_IDLE; From dd04c4fb2879706f73527ef8c27d49337135e125 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 5 Dec 2017 20:28:44 +0100 Subject: [PATCH 18/82] squash kw41zrf fix netdev_get when in DSM --- drivers/kw41zrf/kw41zrf_netdev.c | 60 ++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index c3ffd13a20c2..cccaf1f7e88e 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -568,13 +568,17 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} } + int res = -ENOTSUP; + switch (opt) { case NETOPT_TX_POWER: if (len < sizeof(int16_t)) { - return -EOVERFLOW; + res = -EOVERFLOW; + break; } *((uint16_t *)value) = kw41zrf_get_txpower(dev); - return sizeof(uint16_t); + res = sizeof(uint16_t); + break; case NETOPT_IS_CHANNEL_CLR: if (kw41zrf_cca(dev) == 0) { @@ -583,43 +587,44 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) else { *((netopt_enable_t *)value) = NETOPT_DISABLE; } - return sizeof(netopt_enable_t); + res = sizeof(netopt_enable_t); + break; case NETOPT_CCA_THRESHOLD: if (len < sizeof(uint8_t)) { - return -EOVERFLOW; - } - else { - *(int8_t *)value = kw41zrf_get_cca_threshold(dev); + res = -EOVERFLOW; + break; } - return sizeof(int8_t); + *(int8_t *)value = kw41zrf_get_cca_threshold(dev); + res = sizeof(int8_t); + break; case NETOPT_CCA_MODE: if (len < sizeof(uint8_t)) { - return -EOVERFLOW; + res = -EOVERFLOW; + break; } - else { - *(uint8_t *)value = kw41zrf_get_cca_mode(dev); - switch (*((int8_t *)value)) { - case NETDEV_IEEE802154_CCA_MODE_1: - case NETDEV_IEEE802154_CCA_MODE_2: - case NETDEV_IEEE802154_CCA_MODE_3: - return sizeof(uint8_t); - default: - break; - } - return -EOVERFLOW; + *(uint8_t *)value = kw41zrf_get_cca_mode(dev); + switch (*((int8_t *)value)) { + case NETDEV_IEEE802154_CCA_MODE_1: + case NETDEV_IEEE802154_CCA_MODE_2: + case NETDEV_IEEE802154_CCA_MODE_3: + res = sizeof(uint8_t); + break; + default: + res = -EINVAL; + break; } break; case NETOPT_LAST_ED_LEVEL: if (len < sizeof(int8_t)) { - return -EOVERFLOW; - } - else { - *(int8_t *)value = kw41zrf_get_ed_level(dev); + res = -EOVERFLOW; + break; } - return sizeof(int8_t); + *(int8_t *)value = kw41zrf_get_ed_level(dev); + res = sizeof(int8_t); + break; default: break; @@ -630,7 +635,10 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); } - return netdev_ieee802154_get((netdev_ieee802154_t *)netdev, opt, value, len); + if (res == -ENOTSUP) { + res = netdev_ieee802154_get((netdev_ieee802154_t *)netdev, opt, value, len); + } + return res; } static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, size_t len) From 26b7dfc48e9154c0b92ff75a36a743e4ca7501d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 5 Jun 2018 20:54:05 +0200 Subject: [PATCH 19/82] squash kw41zrf clean up --- drivers/kw41zrf/include/kw41zrf_intern.h | 11 ++ drivers/kw41zrf/kw41zrf_getset.c | 2 +- drivers/kw41zrf/kw41zrf_intern.c | 8 +- drivers/kw41zrf/kw41zrf_netdev.c | 216 +++++++++++++---------- 4 files changed, 136 insertions(+), 101 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 00602af9a956..1318a1427342 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -133,6 +133,17 @@ static inline void kw41zrf_abort_sequence(kw41zrf_t *dev) ZLL->IRQSTS = ZLL->IRQSTS; } +/** + * @brief Check if the radio is in deep sleep mode + * + * @return non-zero if radio is in deep sleep + * @return 0 if radio is not in deep sleep mode + */ +static inline uint32_t kw41zrf_is_dsm(void) +{ + return (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK); +} + /** * @brief Set event timer counter value * diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index bc640eb39cc8..2e709c4ed942 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -187,7 +187,7 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) { DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state); - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Transceiver is sleeping */ switch (option) { /* Modifying these options require that the transceiver is not in diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index caa69ffde703..c2a30349c293 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -120,7 +120,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Wait for oscillator ready signal before attempting to recover from DSM */ while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} /* If we are already awake we can just return now. */ - if (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) { + if (!(kw41zrf_is_dsm())) { /* Already awake */ break; } @@ -129,7 +129,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * on the clocks */ RSIM->ZIG_WAKE = KW41ZRF_DSM_EXIT_DELAY + RSIM->DSM_TIMER + RSIM->DSM_OSC_OFFSET; /* Wait to come out of DSM */ - while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) {} + while (kw41zrf_is_dsm()) {} /* Convert DSM ticks (32.768 kHz) to event timer ticks (1 MHz) */ uint64_t tmp = (uint64_t)(RSIM->ZIG_WAKE - RSIM->ZIG_SLEEP) * 15625ul; @@ -145,7 +145,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) } case KW41ZRF_POWER_DSM: { - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Already asleep */ break; } @@ -175,7 +175,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * enter DSM and we get stuck in the while() below */ RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK | RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK); - while (!(RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)) {} + while (!(kw41zrf_is_dsm())) {} /* Restore saved RF_OSC_EN bits (from kw41zrf_init) * This will disable the RF oscillator unless the system was * configured to use the RF oscillator before kw41zrf_init() was diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index cccaf1f7e88e..c95435437e98 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -342,9 +342,9 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) /* There is no deeper 'off' mode than deep sleep mode */ /* fall through */ case NETOPT_STATE_SLEEP: - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Transceiver is already in deep sleep mode */ - break;; + break; } kw41zrf_abort_sequence(dev); kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); @@ -385,7 +385,7 @@ static netopt_state_t kw41zrf_netdev_get_state(kw41zrf_t *dev) (void) dev; /* ZLL register access require that the transceiver is powered on and not in * deep sleep mode */ - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Transceiver is in deep sleep mode */ return NETOPT_STATE_SLEEP; } @@ -545,7 +545,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) /* The below settings require the transceiver to be powered on */ bool put_to_sleep_when_done = false; - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Transceiver is in deep sleep mode */ switch (opt) { case NETOPT_TX_POWER: @@ -657,74 +657,86 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; case NETOPT_STATE: - if (len > sizeof(netopt_state_t)) { + if (len != sizeof(const netopt_state_t)) { res = -EOVERFLOW; + break; } - else { - res = kw41zrf_netdev_set_state(dev, *((const netopt_state_t *)value)); - } + res = kw41zrf_netdev_set_state(dev, *((const netopt_state_t *)value)); break; case NETOPT_PRELOADING: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_PRELOADING, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_RX_END_IRQ: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_TX_START_IRQ: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_START, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_TX_END_IRQ: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_CSMA_RETRIES: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { res = -EOVERFLOW; + break; } - else { - dev->csma_max_backoffs = *((const uint8_t*)value); - res = sizeof(uint8_t); - } + dev->csma_max_backoffs = *((const uint8_t*)value); + res = len; break; case NETOPT_CSMA_MAXBE: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { res = -EOVERFLOW; + break; } - else { - dev->csma_max_be = *((const uint8_t*)value); - res = sizeof(uint8_t); - } + dev->csma_max_be = *((const uint8_t*)value); + res = len; break; case NETOPT_CSMA_MINBE: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { res = -EOVERFLOW; + break; } - else { - dev->csma_min_be = *((const uint8_t*)value); - res = sizeof(uint8_t); - } + dev->csma_min_be = *((const uint8_t*)value); + res = len; break; case NETOPT_RETRANS: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { return -EOVERFLOW; } dev->max_retrans = *((const uint8_t *)value); - res = sizeof(uint8_t); + res = len; break; default: @@ -733,7 +745,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, bool put_to_sleep_when_done = false; - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Transceiver is in deep sleep mode, check if setting the option * requires the radio powered on */ switch (opt) { @@ -762,117 +774,130 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, switch (opt) { case NETOPT_AUTOACK: /* Set up HW generated automatic ACK after Receive */ + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_ACK_REQ: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, - ((const netopt_enable_t *)value)[0]); + *((const netopt_enable_t *)value)); /* don't set res to set netdev_ieee802154_t::flags */ break; case NETOPT_PROMISCUOUSMODE: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_PROMISCUOUS, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_RX_START_IRQ: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, - ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + *((const netopt_enable_t *)value)); + res = len; break; case NETOPT_CSMA: + if (len != sizeof(const netopt_enable_t)) { + res = -EOVERFLOW; + break; + } kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, ((const netopt_enable_t *)value)[0]); - res = sizeof(netopt_enable_t); + res = len; break; case NETOPT_ADDRESS: - if (len > sizeof(uint16_t)) { + if (len != sizeof(const uint16_t)) { res = -EOVERFLOW; + break; } - else { - kw41zrf_set_addr_short(dev, *((const uint16_t *)value)); - /* don't set res to set netdev_ieee802154_t::short_addr */ - } + kw41zrf_set_addr_short(dev, *((const uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ break; case NETOPT_ADDRESS_LONG: - if (len > sizeof(uint64_t)) { - return -EOVERFLOW; - } - else { - kw41zrf_set_addr_long(dev, *((const uint64_t *)value)); - /* don't set res to set netdev_ieee802154_t::short_addr */ + if (len != sizeof(const uint64_t)) { + res = -EOVERFLOW; + break; } + kw41zrf_set_addr_long(dev, *((const uint64_t *)value)); + /* don't set res to set netdev_ieee802154_t::short_addr */ break; case NETOPT_NID: - if (len > sizeof(uint16_t)) { - return -EOVERFLOW; - } - else { - kw41zrf_set_pan(dev, *((const uint16_t *)value)); - /* don't set res to set netdev_ieee802154_t::pan */ + if (len != sizeof(const uint16_t)) { + res = -EOVERFLOW; + break; } + kw41zrf_set_pan(dev, *((const uint16_t *)value)); + /* don't set res to set netdev_ieee802154_t::pan */ break; case NETOPT_CHANNEL: - if (len < sizeof(uint8_t)) { - res = -EINVAL; + if (len != sizeof(const uint8_t)) { + res = -EOVERFLOW; + break; } - else { - uint8_t chan = ((const uint8_t *)value)[0]; - if (kw41zrf_set_channel(dev, chan)) { - res = -EINVAL; - break; - } - /* don't set res to set netdev_ieee802154_t::chan */ + if (kw41zrf_set_channel(dev, *((const uint8_t *)value))) { + res = -EINVAL; + break; } + /* don't set res to set netdev_ieee802154_t::chan */ break; case NETOPT_TX_POWER: - if (len < sizeof(int16_t)) { + if (len != sizeof(const uint16_t)) { res = -EOVERFLOW; + break; } - else { - kw41zrf_set_tx_power(dev, *(const int16_t *)value); - res = sizeof(int16_t); - } + kw41zrf_set_tx_power(dev, *(const int16_t *)value); + res = len; break; case NETOPT_CCA_THRESHOLD: - if (len < sizeof(uint8_t)) { + if (len != sizeof(const uint8_t)) { res = -EOVERFLOW; + break; } - else { - kw41zrf_set_cca_threshold(dev, *((const uint8_t*)value)); - res = sizeof(uint8_t); - } + kw41zrf_set_cca_threshold(dev, *((const uint8_t*)value)); + res = len; break; case NETOPT_CCA_MODE: - if (len < sizeof(uint8_t)) { + if (len != sizeof(const uint8_t)) { res = -EOVERFLOW; + break; } - else { - switch (*((const uint8_t*)value)) { - case NETDEV_IEEE802154_CCA_MODE_1: - case NETDEV_IEEE802154_CCA_MODE_2: - case NETDEV_IEEE802154_CCA_MODE_3: - kw41zrf_set_cca_mode(dev, *((const uint8_t*)value)); - res = sizeof(uint8_t); - break; - case NETDEV_IEEE802154_CCA_MODE_4: - case NETDEV_IEEE802154_CCA_MODE_5: - case NETDEV_IEEE802154_CCA_MODE_6: - default: - break; - } + uint8_t mode = *((const uint8_t*)value); + switch (mode) { + case NETDEV_IEEE802154_CCA_MODE_1: + case NETDEV_IEEE802154_CCA_MODE_2: + case NETDEV_IEEE802154_CCA_MODE_3: + kw41zrf_set_cca_mode(dev, mode); + res = len; + break; + case NETDEV_IEEE802154_CCA_MODE_4: + case NETDEV_IEEE802154_CCA_MODE_5: + case NETDEV_IEEE802154_CCA_MODE_6: + default: + break; } break; @@ -886,8 +911,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, } if (res == -ENOTSUP) { - res = netdev_ieee802154_set((netdev_ieee802154_t *)netdev, opt, - value, len); + res = netdev_ieee802154_set((netdev_ieee802154_t *)netdev, opt, value, len); } return res; @@ -1139,7 +1163,7 @@ static void kw41zrf_netdev_isr(netdev_t *netdev) } /* ZLL register access requires that the transceiver is not in deep sleep mode */ - if (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK) { + if (kw41zrf_is_dsm()) { /* Transceiver is sleeping, the IRQ must have occurred before entering * sleep, discard the call */ return; From a0d72b1bd2205607cc0c5f976079cbe967fd46f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 5 Jun 2018 20:56:18 +0200 Subject: [PATCH 20/82] squash kw41zrf EINVAL on invalid CCA mode --- drivers/kw41zrf/kw41zrf_netdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index c95435437e98..fc15c3352653 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -897,6 +897,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, case NETDEV_IEEE802154_CCA_MODE_5: case NETDEV_IEEE802154_CCA_MODE_6: default: + res = -EINVAL; break; } break; From a9eabaf2014d4c6ad4800adcc656a2ee8f1ae80b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 5 Jun 2018 21:20:38 +0200 Subject: [PATCH 21/82] squash kw41zrf clean up netdev get --- drivers/kw41zrf/kw41zrf_netdev.c | 124 ++++++++++++++++--------------- 1 file changed, 66 insertions(+), 58 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index fc15c3352653..a1ff8fb44af9 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -436,108 +436,116 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) /* These settings do not require the transceiver to be powered on */ switch (opt) { case NETOPT_STATE: - if (len < sizeof(netopt_state_t)) { + if (len != sizeof(netopt_state_t)) { return -EOVERFLOW; } *((netopt_state_t *)value) = kw41zrf_netdev_get_state(dev); - return sizeof(netopt_state_t); + return len; case NETOPT_MAX_PACKET_SIZE: - if (len < sizeof(int16_t)) { + if (len != sizeof(int16_t)) { return -EOVERFLOW; } - *((uint16_t *)value) = KW41ZRF_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD; - return sizeof(uint16_t); + return len; case NETOPT_PRELOADING: - if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { - *((netopt_enable_t *)value) = NETOPT_ENABLE; - } - else { - *((netopt_enable_t *)value) = NETOPT_DISABLE; + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; } - return sizeof(netopt_enable_t); + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_PRELOADING); + return len; case NETOPT_PROMISCUOUSMODE: - if (dev->netdev.flags & KW41ZRF_OPT_PROMISCUOUS) { - *((netopt_enable_t *)value) = NETOPT_ENABLE; - } - else { - *((netopt_enable_t *)value) = NETOPT_DISABLE; + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; } - return sizeof(netopt_enable_t); + *((netopt_enable_t *)value) = + !!(dev->netdev.flags & KW41ZRF_OPT_PROMISCUOUS); + return len; case NETOPT_RX_START_IRQ: + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; + } *((netopt_enable_t *)value) = !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START); - return sizeof(netopt_enable_t); + return len; case NETOPT_RX_END_IRQ: + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; + } *((netopt_enable_t *)value) = !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END); - return sizeof(netopt_enable_t); + return len; case NETOPT_TX_START_IRQ: + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; + } *((netopt_enable_t *)value) = !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START); - return sizeof(netopt_enable_t); + return len; case NETOPT_TX_END_IRQ: + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; + } *((netopt_enable_t *)value) = !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END); - return sizeof(netopt_enable_t); + return len; case NETOPT_CSMA: + if (len != sizeof(netopt_enable_t)) { + return -EOVERFLOW; + } *((netopt_enable_t *)value) = !!(dev->netdev.flags & KW41ZRF_OPT_CSMA); - return sizeof(netopt_enable_t); + return len; case NETOPT_CSMA_RETRIES: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { return -EOVERFLOW; } *((uint8_t *)value) = dev->csma_max_backoffs; - return sizeof(uint8_t); + return len; case NETOPT_CSMA_MAXBE: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { return -EOVERFLOW; } *((uint8_t *)value) = dev->csma_max_be; - return sizeof(uint8_t); + return len; case NETOPT_CSMA_MINBE: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { return -EOVERFLOW; } *((uint8_t *)value) = dev->csma_min_be; - return sizeof(uint8_t); + return len; case NETOPT_RETRANS: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { return -EOVERFLOW; } *((uint8_t *)value) = dev->max_retrans; - return sizeof(uint8_t); + return len; case NETOPT_TX_RETRIES_NEEDED: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { return -EOVERFLOW; } - else { - *(uint8_t *)value = dev->num_retrans; - } - return sizeof(uint8_t); + *((uint8_t *)value) = dev->num_retrans; + return len; case NETOPT_CHANNEL_PAGE: - if (len < sizeof(uint16_t)) { + if (len != sizeof(uint16_t)) { return -EOVERFLOW; } - else { - *(uint16_t *)value = 0; - } - return sizeof(uint16_t); + *((uint16_t *)value) = 0; + return len; default: break; @@ -572,44 +580,44 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) switch (opt) { case NETOPT_TX_POWER: - if (len < sizeof(int16_t)) { + if (len != sizeof(int16_t)) { res = -EOVERFLOW; break; } *((uint16_t *)value) = kw41zrf_get_txpower(dev); - res = sizeof(uint16_t); + res = len; break; case NETOPT_IS_CHANNEL_CLR: - if (kw41zrf_cca(dev) == 0) { - *((netopt_enable_t *)value) = NETOPT_ENABLE; - } - else { - *((netopt_enable_t *)value) = NETOPT_DISABLE; + if (len != sizeof(netopt_enable_t)) { + res = -EOVERFLOW; + break; } - res = sizeof(netopt_enable_t); + *((netopt_enable_t *)value) = !(kw41zrf_cca(dev)); + res = len; break; case NETOPT_CCA_THRESHOLD: - if (len < sizeof(uint8_t)) { + if (len != sizeof(int8_t)) { res = -EOVERFLOW; break; } - *(int8_t *)value = kw41zrf_get_cca_threshold(dev); - res = sizeof(int8_t); + *((int8_t *)value) = kw41zrf_get_cca_threshold(dev); + res = len; break; case NETOPT_CCA_MODE: - if (len < sizeof(uint8_t)) { + if (len != sizeof(uint8_t)) { res = -EOVERFLOW; break; } - *(uint8_t *)value = kw41zrf_get_cca_mode(dev); - switch (*((int8_t *)value)) { + uint8_t mode = kw41zrf_get_cca_mode(dev); + switch (mode) { case NETDEV_IEEE802154_CCA_MODE_1: case NETDEV_IEEE802154_CCA_MODE_2: case NETDEV_IEEE802154_CCA_MODE_3: - res = sizeof(uint8_t); + *((uint8_t *)value) = mode; + res = len; break; default: res = -EINVAL; @@ -618,12 +626,12 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) break; case NETOPT_LAST_ED_LEVEL: - if (len < sizeof(int8_t)) { + if (len != sizeof(int8_t)) { res = -EOVERFLOW; break; } - *(int8_t *)value = kw41zrf_get_ed_level(dev); - res = sizeof(int8_t); + *((int8_t *)value) = kw41zrf_get_ed_level(dev); + res = len; break; default: From 2e1a25845b0877b0eadc1087c1425dd97871d1b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 5 Jun 2018 21:28:18 +0200 Subject: [PATCH 22/82] squash kw41zrf init null return value --- drivers/kw41zrf/kw41zrf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 3a855ebf8f26..3c6fcdf090cb 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -84,7 +84,7 @@ void kw41zrf_setup(kw41zrf_t *dev) int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) { if (dev == NULL) { - return -ENODEV; + return -EINVAL; } /* Save a copy of the RF_OSC_EN setting to use when the radio is in deep sleep */ From 1cf9fb68711f112371e37286f0112826bc5b6761 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 7 Jun 2018 21:24:20 +0200 Subject: [PATCH 23/82] squash kw41zrf send while sleeping stability improvements --- drivers/include/kw41zrf.h | 37 ++++++++++--------- drivers/kw41zrf/include/kw41zrf_getset.h | 14 ++++---- drivers/kw41zrf/kw41zrf.c | 2 +- drivers/kw41zrf/kw41zrf_intern.c | 45 ++++++++++++++++-------- drivers/kw41zrf/kw41zrf_netdev.c | 24 +++++++++---- 5 files changed, 76 insertions(+), 46 deletions(-) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 147df313d877..9682e1146e09 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -118,23 +118,26 @@ typedef struct { * @name device specific fields * @{ */ - thread_t *thread; /**< Network driver thread, for providing feedback from IRQ handler */ - uint32_t tx_warmup_time; /**< TX warmup time, in event timer ticks */ - uint32_t rx_warmup_time; /**< RX warmup time, in event timer ticks */ - uint8_t max_retrans; /**< Maximum number of frame retransmissions - * when no Ack frame is received (macMaxFrameRetries) */ - uint8_t csma_max_backoffs; /**< Maximum number of CSMA backoffs when - * waiting for channel clear (macMaxCsmaBackoffs) */ - uint8_t csma_min_be; /**< Minimum backoff exponent (macMinBe) */ - uint8_t csma_max_be; /**< Maximum backoff exponent (macMaxBe) */ - int16_t tx_power; /**< The current tx-power setting of the device */ - uint8_t idle_seq; /**< state to return to after sending */ - uint8_t cca_result; /**< Used for passing CCA result from ISR to user */ - uint8_t csma_be; /**< Counter used internally by send implementation */ - uint8_t csma_num_backoffs; /**< Counter used internally by send implementation */ - uint8_t num_retrans; /**< Counter used internally by send implementation */ - bool pm_blocked; /**< true if we have blocked a low power mode in the CPU */ - uint32_t rf_osc_en_idle; /**< RF_OSC_EN bits setting when RF module is in standby */ + thread_t *thread; /**< Network driver thread, for providing feedback from IRQ handler */ + uint32_t tx_warmup_time; /**< TX warmup time, in event timer ticks */ + uint32_t rx_warmup_time; /**< RX warmup time, in event timer ticks */ + uint32_t rf_osc_en_idle; /**< RF_OSC_EN bits setting when RF module is in standby */ + uint8_t max_retrans; /**< Maximum number of frame retransmissions + * when no Ack frame is received (macMaxFrameRetries) */ + uint8_t csma_max_backoffs; /**< Maximum number of CSMA backoffs when + * waiting for channel clear (macMaxCsmaBackoffs) */ + uint8_t csma_min_be; /**< Minimum backoff exponent (macMinBe) */ + uint8_t csma_max_be; /**< Maximum backoff exponent (macMaxBe) */ + int16_t tx_power; /**< The current tx-power setting of the device */ + uint8_t idle_seq; /**< state to return to after sending */ + uint8_t cca_result; /**< Used for passing CCA result from ISR to user */ + uint8_t csma_be; /**< Counter used internally by send implementation */ + uint8_t csma_num_backoffs; /**< Counter used internally by send implementation */ + uint8_t num_retrans; /**< Counter used internally by send implementation */ + bool pm_blocked; /**< true if we have blocked a low power mode in the CPU */ + bool recv_blocked; /**< blocks moving to XCVSEQ_RECEIVE to prevent + * overwriting the RX buffer before the higher + * layers have copied it to system RAM */ /** @} */ } kw41zrf_t; diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h index c5e84cc82174..7847ae8ff101 100644 --- a/drivers/kw41zrf/include/kw41zrf_getset.h +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -28,13 +28,15 @@ extern "C" { /** @brief Transceiver sequence identifiers */ enum kw41zrf_xcvseq { - XCVSEQ_IDLE = 0b000, - XCVSEQ_RECEIVE = 0b001, - XCVSEQ_TRANSMIT = 0b010, - XCVSEQ_CCA = 0b011, - XCVSEQ_TX_RX = 0b100, - XCVSEQ_CONTINUOUS_CCA = 0b101, + XCVSEQ_IDLE = 0b000, + XCVSEQ_RECEIVE = 0b001, + XCVSEQ_TRANSMIT = 0b010, + XCVSEQ_CCA = 0b011, + XCVSEQ_TX_RX = 0b100, + XCVSEQ_CONTINUOUS_CCA = 0b101, /* Other values are reserved */ + /* Special value for idle_seq when sleeping */ + XCVSEQ_DSM_IDLE = 0b1000, }; /** diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 3c6fcdf090cb..62963625b8ce 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -71,13 +71,13 @@ void kw41zrf_setup(kw41zrf_t *dev) /* initialize device descriptor */ dev->idle_seq = XCVSEQ_RECEIVE; dev->pm_blocked = false; + dev->recv_blocked = false; /* Set default parameters according to STD IEEE802.15.4-2015 */ dev->csma_max_be = 5; dev->csma_min_be = 3; dev->max_retrans = 3; dev->csma_max_backoffs = 4; -// kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); DEBUG("[kw41zrf] setup finished\n"); } diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index c2a30349c293..df42528a9c08 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -197,6 +197,16 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) { (void) dev; DEBUG("[kw41zrf] set sequence to %u\n", (unsigned int)seq); + bool back_to_sleep = false; + if (seq == XCVSEQ_DSM_IDLE) { + back_to_sleep = true; + seq = XCVSEQ_IDLE; + } + else if ((seq == XCVSEQ_RECEIVE) && dev->recv_blocked) { + /* Wait in standby until recv has been called to avoid corrupting the RX + * buffer before the frame has been received by the higher layers */ + seq = XCVSEQ_IDLE; + } assert((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) == XCVSEQ_IDLE); while ((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) == 0) { kw41zrf_abort_sequence(dev); @@ -207,26 +217,31 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | ZLL_PHY_CTRL_SEQMSK_MASK)) | seq; while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != (ZLL_PHY_CTRL_XCVSEQ_MASK & seq)) {} + if (back_to_sleep) { + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); + } } int kw41zrf_can_switch_to_idle(kw41zrf_t *dev) { (void) dev; - uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; - - DEBUG("[kw41zrf] XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 ", SEQ_CTRL_STS=0x%" PRIx32 "\n", seq, - ZLL->SEQ_STATE, ZLL->SEQ_CTRL_STS); - - switch (seq) - { - case XCVSEQ_TRANSMIT: - case XCVSEQ_TX_RX: - case XCVSEQ_CCA: - /* We should wait until TX or CCA has finished before moving to - * another mode */ - return 0; - default: - break; + if (!kw41zrf_is_dsm()) { + uint8_t seq = (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; + + DEBUG("[kw41zrf] XCVSEQ=0x%x, SEQ_STATE=0x%" PRIx32 ", SEQ_CTRL_STS=0x%" PRIx32 "\n", seq, + ZLL->SEQ_STATE, ZLL->SEQ_CTRL_STS); + + switch (seq) + { + case XCVSEQ_TRANSMIT: + case XCVSEQ_TX_RX: + case XCVSEQ_CCA: + /* We should wait until TX or CCA has finished before moving to + * another mode */ + return 0; + default: + break; + } } return 1; diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index a1ff8fb44af9..acb17dda7ef1 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -182,8 +182,6 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) */ static void kw41zrf_wait_idle(kw41zrf_t *dev) { - /* Wait for oscillator ready signal if coming out of sleep mode */ - while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} /* make sure any ongoing T or TR sequence is finished */ if (kw41zrf_can_switch_to_idle(dev) == 0) { DEBUG("[kw41zrf] TX already in progress\n"); @@ -213,6 +211,10 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) int kw41zrf_cca(kw41zrf_t *dev) { kw41zrf_wait_idle(dev); + if (kw41zrf_is_dsm()) { + /* bring the device out of DSM */ + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + } kw41zrf_abort_sequence(dev); kw41zrf_unmask_irqs(); kw41zrf_set_sequence(dev, XCVSEQ_CCA); @@ -229,6 +231,10 @@ static int kw41zrf_netdev_send(netdev_t *netdev, const iolist_t *iolist) size_t len = 0; kw41zrf_wait_idle(dev); + if (kw41zrf_is_dsm()) { + /* bring the device out of DSM */ + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + } /* load packet data into buffer */ for (const iolist_t *iol = iolist; iol; iol = iol->iol_next) { @@ -285,7 +291,7 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in if (buf == NULL) { if (len > 0) { /* discard what we have stored in the buffer, go back to RX mode */ - dev->idle_seq = XCVSEQ_RECEIVE; + dev->recv_blocked = false; if (kw41zrf_can_switch_to_idle(dev)) { kw41zrf_abort_sequence(dev); kw41zrf_set_sequence(dev, dev->idle_seq); @@ -326,7 +332,7 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in } /* Go back to RX mode */ - dev->idle_seq = XCVSEQ_RECEIVE; + dev->recv_blocked = false; if (kw41zrf_can_switch_to_idle(dev)) { kw41zrf_abort_sequence(dev); kw41zrf_set_sequence(dev, dev->idle_seq); @@ -348,7 +354,7 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) } kw41zrf_abort_sequence(dev); kw41zrf_set_power_mode(dev, KW41ZRF_POWER_DSM); - dev->idle_seq = XCVSEQ_IDLE; + dev->idle_seq = XCVSEQ_DSM_IDLE; break; case NETOPT_STATE_STANDBY: kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); @@ -365,6 +371,10 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) case NETOPT_STATE_TX: if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { kw41zrf_wait_idle(dev); + if (kw41zrf_is_dsm()) { + /* bring the device out of DSM */ + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + } dev->csma_be = dev->csma_min_be; dev->csma_num_backoffs = 0; dev->num_retrans = 0; @@ -1020,8 +1030,8 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) else { /* No error reported */ DEBUG("[kw41zrf] success (R)\n"); - /* Wait in SEQ_IDLE until recv has been called */ - dev->idle_seq = XCVSEQ_IDLE; + /* Block XCVSEQ_RECEIVE until netdev->recv has been called */ + dev->recv_blocked = true; kw41zrf_set_sequence(dev, dev->idle_seq); if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_COMPLETE); From 4dacd861dc941694da2029e0dc7b04f284078314 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 8 Jun 2018 22:57:23 +0200 Subject: [PATCH 24/82] squash kw41zrf ifdef MODULE_NETOPT --- drivers/kw41zrf/kw41zrf_netdev.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index acb17dda7ef1..bab18397f1ec 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -572,7 +572,11 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) case NETOPT_CCA_MODE: case NETOPT_LAST_ED_LEVEL: kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); - DEBUG("[kw41zrf] Wake to get %s\n", netopt2str(opt)); +#ifdef MODULE_NETOPT + DEBUG("[kw41zrf] Wake to get opt %s\n", netopt2str(opt)); +#else + DEBUG("[kw41zrf] Wake to get opt %d\n", (int)opt); +#endif put_to_sleep_when_done = true; break; @@ -780,7 +784,11 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, case NETOPT_CCA_THRESHOLD: case NETOPT_CCA_MODE: kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); - DEBUG("[kw41zrf] Wake to set %s\n", netopt2str(opt)); +#ifdef MODULE_NETOPT + DEBUG("[kw41zrf] Wake to set opt %s\n", netopt2str(opt)); +#else + DEBUG("[kw41zrf] Wake to set opt %d\n", (int)opt); +#endif put_to_sleep_when_done = true; break; From f5dcf23a8a750ae49d6eb6c095c2012185ec432f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 29 Jun 2018 21:47:57 +0200 Subject: [PATCH 25/82] squash kw41zrf allow recv during DSM --- drivers/kw41zrf/kw41zrf_netdev.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index bab18397f1ec..cf94fbc3302b 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -277,10 +277,18 @@ static int kw41zrf_netdev_send(netdev_t *netdev, const iolist_t *iolist) static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *info) { + kw41zrf_t *dev = (kw41zrf_t *)netdev; + if (kw41zrf_is_dsm()) { + /* bring the device out of DSM, sleep will be restored before returning */ + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + } /* get size of the received packet */ uint8_t pkt_len = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; - kw41zrf_t *dev = (kw41zrf_t *)netdev; if (pkt_len < IEEE802154_FCS_LEN) { + if (kw41zrf_can_switch_to_idle(dev)) { + kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); + } return -EAGAIN; } /* skip FCS */ @@ -290,13 +298,16 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in /* just return length when buf == NULL */ if (buf == NULL) { if (len > 0) { - /* discard what we have stored in the buffer, go back to RX mode */ + /* discard what we have stored in the buffer, unblock RX */ dev->recv_blocked = false; if (kw41zrf_can_switch_to_idle(dev)) { kw41zrf_abort_sequence(dev); kw41zrf_set_sequence(dev, dev->idle_seq); } } + /* No set_sequence(idle_seq) here, keep transceiver turned on if the + * buffer was not discarded, we expect the higher layer to call again + * shortly with a proper buffer */ return pkt_len; } @@ -314,6 +325,10 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in if (pkt_len > len) { /* not enough space in buf */ + if (kw41zrf_can_switch_to_idle(dev)) { + kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); + } return -ENOBUFS; } memcpy(buf, (const void *)&ZLL->PKT_BUFFER_RX[0], pkt_len); From 7c9ec710c77614718567ff42fbfd1563ac95db26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 30 Jun 2018 20:16:59 +0200 Subject: [PATCH 26/82] squash kw41zrf auto-init --- sys/auto_init/netif/auto_init_kw41zrf.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/sys/auto_init/netif/auto_init_kw41zrf.c b/sys/auto_init/netif/auto_init_kw41zrf.c index 9ed7846ec837..761ad6a587e4 100644 --- a/sys/auto_init/netif/auto_init_kw41zrf.c +++ b/sys/auto_init/netif/auto_init_kw41zrf.c @@ -7,7 +7,7 @@ * */ -/* +/** * @ingroup auto_init_gnrc_netif * @{ * @@ -27,15 +27,16 @@ #include "kw41zrf.h" /** - * @brief Define stack parameters for the MAC layer thread + * @name Stack parameters for the MAC layer thread * @{ */ -#ifndef KW41ZRF_MAC_STACKSIZE -#define KW41ZRF_MAC_STACKSIZE (THREAD_STACKSIZE_DEFAULT) +#ifndef KW41ZRF_NETIF_STACKSIZE +#define KW41ZRF_NETIF_STACKSIZE (THREAD_STACKSIZE_DEFAULT) #endif -#ifndef KW41ZRF_MAC_PRIO -#define KW41ZRF_MAC_PRIO (GNRC_NETIF_PRIO) +#ifndef KW41ZRF_NETIF_PRIO +#define KW41ZRF_NETIF_PRIO (GNRC_NETIF_PRIO) #endif +/** @} */ /* There is only one memory mapped transceiver in the supported SoCs, the driver * does not try to take into account multiple instances of the hardware module */ From 48e99160701ddafafed9103015dccaf52dbfedac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 11 Aug 2018 08:17:53 +0200 Subject: [PATCH 27/82] fixup! squash kw41zrf auto-init --- sys/auto_init/netif/auto_init_kw41zrf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/auto_init/netif/auto_init_kw41zrf.c b/sys/auto_init/netif/auto_init_kw41zrf.c index 761ad6a587e4..5072de906a18 100644 --- a/sys/auto_init/netif/auto_init_kw41zrf.c +++ b/sys/auto_init/netif/auto_init_kw41zrf.c @@ -43,15 +43,15 @@ #define KW41ZRF_NUMOF 1 static kw41zrf_t kw41zrf_devs[KW41ZRF_NUMOF]; -static char _kw41zrf_stacks[KW41ZRF_NUMOF][KW41ZRF_MAC_STACKSIZE]; +static char _kw41zrf_stacks[KW41ZRF_NUMOF][KW41ZRF_NETIF_STACKSIZE]; void auto_init_kw41zrf(void) { for (unsigned i = 0; i < KW41ZRF_NUMOF; i++) { LOG_DEBUG("[auto_init_netif] initializing kw41zrf #%u\n", i); kw41zrf_setup(&kw41zrf_devs[i]); - gnrc_netif_ieee802154_create(_kw41zrf_stacks[i], KW41ZRF_MAC_STACKSIZE, - KW41ZRF_MAC_PRIO, "kw41zrf", + gnrc_netif_ieee802154_create(_kw41zrf_stacks[i], KW41ZRF_NETIF_STACKSIZE, + KW41ZRF_NETIF_PRIO, "kw41zrf", (netdev_t *)&kw41zrf_devs[i]); } } From 7a33172d9b38b519d25fdee61af0224076dad553 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 24 Aug 2018 12:42:04 +0200 Subject: [PATCH 28/82] squash fix cppcheck comments --- drivers/kw41zrf/include/kw41zrf_intern.h | 1 + drivers/kw41zrf/kw41zrf_getset.c | 1 - drivers/kw41zrf/kw41zrf_intern.c | 2 ++ 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 1318a1427342..9ac8758a6596 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -130,6 +130,7 @@ static inline void kw41zrf_abort_sequence(kw41zrf_t *dev) ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != XCVSEQ_IDLE) {} /* Clear interrupt flags */ + /* cppcheck-suppress selfAssignment */ ZLL->IRQSTS = ZLL->IRQSTS; } diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 2e709c4ed942..bdaaecec7319 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -102,7 +102,6 @@ void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan) ZLL_MACSHORTADDRS0_MACPANID0(pan); LOG_DEBUG("[kw41zrf] set pan to: 0x%x\n", pan); - dev->netdev.pan = pan; } void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr) diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index df42528a9c08..c458d7dcd387 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -160,6 +160,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * to be constant at 2 DSM ticks */ while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK) {} /* Clear IRQ flags */ + /* cppcheck-suppress selfAssignment */ RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; /* Enable timer triggered sleep */ ZLL->DSM_CTRL |= ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; @@ -213,6 +214,7 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) } /* Clear interrupt flags, sometimes the sequence complete flag is immediately set */ + /* cppcheck-suppress selfAssignment */ ZLL->IRQSTS = ZLL->IRQSTS; ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | ZLL_PHY_CTRL_SEQMSK_MASK)) | seq; while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> From 82856a9b6559850405985335b6192c39fe5eaa83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 13 Sep 2018 11:30:27 +0200 Subject: [PATCH 29/82] squash fsl_xcvr extern C --- drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h index eb32afae42fd..a83c2ea5515b 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -40,6 +40,10 @@ #include "cpu.h" #include "fsl_xcvr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*! * @addtogroup xcvr * @{ @@ -128,7 +132,7 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); /* @} */ -#if defined(__cplusplus) +#ifdef __cplusplus } #endif From 26718a4fd7f1faf9cc1146a15a868431798b7062 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 13 Sep 2018 11:36:56 +0200 Subject: [PATCH 30/82] fixup! squash fsl_xcvr extern C --- .../Interface/fsl_os_abstraction_config.h | 9 +++++++++ .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h | 17 ++++++++++++----- .../vendor/XCVR/MKW41Z4/dbg_ram_capture.h | 6 +++++- drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 4 ++-- drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h | 8 ++++++++ 5 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h index 9cb94012eb8a..41fed342127e 100644 --- a/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h +++ b/drivers/kw41zrf/vendor/OSAbstraction/Interface/fsl_os_abstraction_config.h @@ -40,6 +40,10 @@ #ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ #define _FSL_OS_ABSTRACTION_CONFIG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #ifndef osNumberOfSemaphores #define osNumberOfSemaphores 5 #endif @@ -66,4 +70,9 @@ #ifndef gTaskMultipleInstancesManagement_c #define gTaskMultipleInstancesManagement_c 0 #endif + +#ifdef __cplusplus +} +#endif + #endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h index a3be92c53c2e..41ecd2e1db15 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h @@ -32,6 +32,10 @@ #ifndef __XCVR_TEST_FSK_H__ #define __XCVR_TEST_FSK_H__ +#ifdef __cplusplus +extern "C" { +#endif + /*! ********************************************************************************* ************************************************************************************* * Public type definitions @@ -75,7 +79,7 @@ extern void XcvrFskModTx(void); * * \ingroup TestFunctions * -* \details +* \details * ***********************************************************************************/ extern void XcvrFskNoModTx(void); @@ -87,7 +91,7 @@ extern void XcvrFskNoModTx(void); * * \ingroup TestFunctions * -* \details +* \details * ***********************************************************************************/ extern void XcvrFskIdle(void); @@ -111,7 +115,7 @@ extern void XcvrFskTxRand(void); * * \ingroup TestFunctions * -* \details +* \details * ***********************************************************************************/ extern void XcvrFskLoadPattern(uint32_t u32Pattern); @@ -123,7 +127,7 @@ extern void XcvrFskLoadPattern(uint32_t u32Pattern); * * \ingroup TestFunctions * -* \details +* \details * ***********************************************************************************/ extern void XcvrFskSetTxPower(uint8_t u8TxPow); @@ -135,7 +139,7 @@ extern void XcvrFskSetTxPower(uint8_t u8TxPow); * * \ingroup TestFunctions * -* \details +* \details * ***********************************************************************************/ extern void XcvrFskSetTxChannel(uint8_t u8TxChan); @@ -153,5 +157,8 @@ extern void XcvrFskSetTxChannel(uint8_t u8TxChan); ***********************************************************************************/ extern void XcvrFskRestoreTXControl(void); +#ifdef __cplusplus +} #endif +#endif diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h index 6f3458c5f99c..3d8933e93384 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h @@ -40,6 +40,10 @@ #include "fsl_xcvr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*! * @addtogroup xcvr * @{ @@ -201,7 +205,7 @@ dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void /* @} */ -#if defined(__cplusplus) +#ifdef __cplusplus } #endif diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h index 295c73e0cc31..d5faa10d1ad7 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -875,7 +875,7 @@ extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; * API ******************************************************************************/ -#if defined(__cplusplus) +#ifdef __cplusplus extern "C" { #endif @@ -1237,7 +1237,7 @@ xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); /* @} */ -#if defined(__cplusplus) +#ifdef __cplusplus } #endif diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h index 8580b928f8e2..e7fbb6039830 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.h @@ -41,6 +41,10 @@ #include #include "fsl_xcvr.h" +#ifdef __cplusplus +extern "C" { +#endif + /*! * @addtogroup xcvr * @{ @@ -182,4 +186,8 @@ uint32_t handle_ifr_die_kw_type(void); */ void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries); +#ifdef __cplusplus +} +#endif + #endif /*__IFR_RADIO_H__ */ From 2f7fed66985ab231d1529cc28d3b9461bccaddfa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 13 Sep 2018 11:38:10 +0200 Subject: [PATCH 31/82] squash auto init doxygen typo --- sys/auto_init/netif/auto_init_kw41zrf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/auto_init/netif/auto_init_kw41zrf.c b/sys/auto_init/netif/auto_init_kw41zrf.c index 5072de906a18..a391f162e9a3 100644 --- a/sys/auto_init/netif/auto_init_kw41zrf.c +++ b/sys/auto_init/netif/auto_init_kw41zrf.c @@ -8,7 +8,7 @@ */ /** - * @ingroup auto_init_gnrc_netif + * @ingroup sys_auto_init_gnrc_netif * @{ * * @file From f6ecb7c22146c883eb2399ca8296c0924f02f275 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 10 Oct 2018 14:32:24 +0200 Subject: [PATCH 32/82] squash kw41zrf clean up init --- drivers/kw41zrf/kw41zrf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 62963625b8ce..8a8c52d4f9d3 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -122,7 +122,7 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) dev->rx_warmup_time = (dev->rx_warmup_time + 15) / 16; dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16; - /* Configre Radio IRQ */ + /* Configure Radio IRQ */ kw41zrf_set_irq_callback(cb, dev); NVIC_ClearPendingIRQ(Radio_1_IRQn); NVIC_EnableIRQ(Radio_1_IRQn); @@ -189,7 +189,7 @@ void kw41zrf_reset_phy(kw41zrf_t *dev) /* Set CCA threshold to -75 dBm */ ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | - ZLL_CCA_LQI_CTRL_CCA1_THRESH(0xB5); + ZLL_CCA_LQI_CTRL_CCA1_THRESH(-75); /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */ ZLL->ACKDELAY = (ZLL->ACKDELAY & ~ZLL_ACKDELAY_ACKDELAY_MASK) | ZLL_ACKDELAY_ACKDELAY(-8); From 2ba09114ca31105d857534479a84fd28f410d46e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 10 Oct 2018 15:14:55 +0200 Subject: [PATCH 33/82] squash kw41zrf clean up SEQ_IDLE handling Possibly fixes unresolved driver hangs in ContikiMAC tx code path. --- drivers/kw41zrf/include/kw41zrf_intern.h | 6 +++--- drivers/kw41zrf/kw41zrf_intern.c | 7 +------ drivers/kw41zrf/kw41zrf_netdev.c | 13 +++++++------ 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 9ac8758a6596..9004ea06cd6d 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -126,11 +126,11 @@ static inline void kw41zrf_abort_sequence(kw41zrf_t *dev) ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE) | ZLL_PHY_CTRL_SEQMSK_MASK; /* Spin until the sequence manager has acknowledged the sequence abort, this * should not take many cycles */ - while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> - ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != XCVSEQ_IDLE) {} + while (!(ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK)) {} /* Clear interrupt flags */ - /* cppcheck-suppress selfAssignment */ + /* cppcheck-suppress selfAssignment + * (reason: IRQ flags are write-1-to-clear) */ ZLL->IRQSTS = ZLL->IRQSTS; } diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index c458d7dcd387..ce39380acc55 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -209,13 +209,8 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) seq = XCVSEQ_IDLE; } assert((ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) == XCVSEQ_IDLE); - while ((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) == 0) { - kw41zrf_abort_sequence(dev); - } + kw41zrf_abort_sequence(dev); - /* Clear interrupt flags, sometimes the sequence complete flag is immediately set */ - /* cppcheck-suppress selfAssignment */ - ZLL->IRQSTS = ZLL->IRQSTS; ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~(ZLL_PHY_CTRL_XCVSEQ_MASK | ZLL_PHY_CTRL_SEQMSK_MASK)) | seq; while (((ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT) != (ZLL_PHY_CTRL_XCVSEQ_MASK & seq)) {} diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index cf94fbc3302b..9c305e4722da 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -184,22 +184,21 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) { /* make sure any ongoing T or TR sequence is finished */ if (kw41zrf_can_switch_to_idle(dev) == 0) { - DEBUG("[kw41zrf] TX already in progress\n"); + DEBUG("[kw41zrf] waiting for idle\n"); num_irqs_handled = num_irqs_queued; spinning_for_irq = 1; - thread_flags_clear(KW41ZRF_THREAD_FLAG_ISR); pm_block(KINETIS_PM_LLS); while (1) { - /* TX in progress */ - /* Handle any outstanding IRQ first */ + /* TX or CCA in progress */ + /* Block until we get an IRQ */ + thread_flags_wait_any(KW41ZRF_THREAD_FLAG_ISR); + /* Handle the IRQ */ kw41zrf_netdev_isr((netdev_t *)dev); /* kw41zrf_netdev_isr() will switch the transceiver back to idle after * handling the TX complete IRQ */ if (kw41zrf_can_switch_to_idle(dev)) { break; } - /* Block until we get another IRQ */ - thread_flags_wait_any(KW41ZRF_THREAD_FLAG_ISR); DEBUG("[kw41zrf] waited ISR\n"); } pm_unblock(KINETIS_PM_LLS); @@ -1202,12 +1201,14 @@ static void kw41zrf_netdev_isr(netdev_t *netdev) kw41zrf_t *dev = (kw41zrf_t *)netdev; if (!spinning_for_irq) { num_irqs_handled = num_irqs_queued; + thread_flags_clear(KW41ZRF_THREAD_FLAG_ISR); } /* ZLL register access requires that the transceiver is not in deep sleep mode */ if (kw41zrf_is_dsm()) { /* Transceiver is sleeping, the IRQ must have occurred before entering * sleep, discard the call */ + DEBUG("kw41zrf: unexpected IRQ while sleeping\n"); return; } uint32_t irqsts = ZLL->IRQSTS; From c226f93bbca2977fb9bc41f87577aef654cfc76d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 16 Oct 2018 08:40:33 +0200 Subject: [PATCH 34/82] squash kw41zrf correct NETOPT_CHANNEL width check --- drivers/kw41zrf/kw41zrf_netdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 9c305e4722da..b2e11a2e9154 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -891,11 +891,11 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; case NETOPT_CHANNEL: - if (len != sizeof(const uint8_t)) { + if (len != sizeof(const uint16_t)) { res = -EOVERFLOW; break; } - if (kw41zrf_set_channel(dev, *((const uint8_t *)value))) { + if (kw41zrf_set_channel(dev, *((const uint16_t *)value))) { res = -EINVAL; break; } From 2940893c958d7de33a97c4941ade9f2f67668e25 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 16 Oct 2018 08:40:56 +0200 Subject: [PATCH 35/82] squash kw41zrf add comment on CCA threshold --- drivers/kw41zrf/kw41zrf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 8a8c52d4f9d3..8f5fda043627 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -188,6 +188,7 @@ void kw41zrf_reset_phy(kw41zrf_t *dev) kw41zrf_timer_init(dev, KW41ZRF_TIMEBASE_62500HZ); /* Set CCA threshold to -75 dBm */ + /* The hardware default for this register is +75 dBm (0x4b), which is nonsense */ ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | ZLL_CCA_LQI_CTRL_CCA1_THRESH(-75); From b0a4353866062f540a5fb7bc7ceabadc4f77b277 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 16 Oct 2018 09:27:48 +0200 Subject: [PATCH 36/82] squash kw41zrf add cppcheck suppression reason --- drivers/kw41zrf/kw41zrf_intern.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index ce39380acc55..2a04c2ba4c23 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -160,7 +160,8 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * to be constant at 2 DSM ticks */ while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK) {} /* Clear IRQ flags */ - /* cppcheck-suppress selfAssignment */ + /* cppcheck-suppress selfAssignment + * (reason: IRQ flags are write-1-to-clear) */ RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; /* Enable timer triggered sleep */ ZLL->DSM_CTRL |= ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; From 1f46ef31da583f52b57441fcf0876ef6a58f5f59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 27 Oct 2018 14:36:37 +0200 Subject: [PATCH 37/82] squash kw41zrf refactor tx_exec to avoid races --- drivers/kw41zrf/kw41zrf_intern.c | 2 +- drivers/kw41zrf/kw41zrf_netdev.c | 61 +++++++++++++++++--------------- 2 files changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 2a04c2ba4c23..bb5030502315 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -198,7 +198,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) { (void) dev; - DEBUG("[kw41zrf] set sequence to %u\n", (unsigned int)seq); + DEBUG("[kw41zrf] set sequence to %x\n", (unsigned)seq); bool back_to_sleep = false; if (seq == XCVSEQ_DSM_IDLE) { back_to_sleep = true; diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index b2e11a2e9154..7659630b005c 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -126,51 +126,54 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) /* Check FCF field in the TX buffer to see if the ACK_REQ flag was set in * the packet that is queued for transmission */ uint8_t fcf = (len_fcf >> 8) & 0xff; - uint32_t backoff_delay; + uint32_t backoff_delay = 0; if (dev->netdev.flags & KW41ZRF_OPT_CSMA) { /* Use CSMA/CA random delay in the interval [0, 2**dev->csma_be) */ backoff_delay = kw41zrf_csma_random_delay(dev); } - else { - /* No CSMA */ - backoff_delay = 0; - } - if ((dev->netdev.flags & KW41ZRF_OPT_ACK_REQ) && - (fcf & IEEE802154_FCF_ACK_REQ)) { + uint32_t tx_timeout = 0; + if ((fcf & IEEE802154_FCF_ACK_REQ) && + (dev->netdev.flags & KW41ZRF_OPT_ACK_REQ)) { uint8_t payload_len = len_fcf & 0xff; - uint32_t tx_timeout = backoff_delay + dev->tx_warmup_time + + tx_timeout = backoff_delay + dev->tx_warmup_time + KW41ZRF_SHR_PHY_TIME + payload_len * KW41ZRF_PER_BYTE_TIME + KW41ZRF_ACK_WAIT_TIME; + } + if (backoff_delay > 0) { + /* Avoid risk of setting a timer in the past */ + kw41zrf_timer_set(dev, &ZLL->T2CMP, ~0ul); + bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); + } + else { + bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); + } + + /* This is quite timing sensitive, as interrupts may lead to setting a timer + * target which has already passed */ + unsigned mask = irq_disable(); + if (tx_timeout > 0) { + /* Set a long timeout to avoid timer races while setting up the TX sequence. + * By setting the timeout to now - 1 we get 267 seconds to set up everything + * before the timer rolls over */ + kw41zrf_timer_set(dev, &ZLL->T3CMP, ~0ul); DEBUG("[kw41zrf] Start TR\n"); - /* This is quite timing sensitive, as interrupts may lead to delays - * causing the timeout or trigger timers to expire before we have had a - * chance to write the new autosequence to the PHY_CTRL register. */ - unsigned mask = irq_disable(); - if (backoff_delay > 0) { - /* Avoid risk of setting a timer in the past */ - /* Set trigger time for CSMA */ - kw41zrf_timer_set(dev, &ZLL->T2CMP, backoff_delay); - bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); - } - /* Set timeout for RX ACK */ - kw41zrf_timer_set(dev, &ZLL->T3CMP, tx_timeout); /* Initiate transmission, with timeout */ kw41zrf_set_sequence(dev, XCVSEQ_TX_RX | ZLL_PHY_CTRL_TC3TMOUT_MASK); - irq_restore(mask); } else { DEBUG("[kw41zrf] Start T\n"); - unsigned mask = irq_disable(); - if (backoff_delay > 0) { - /* Avoid risk of setting a timer in the past */ - /* Set trigger time for CSMA */ - kw41zrf_timer_set(dev, &ZLL->T2CMP, backoff_delay); - bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_TMRTRIGEN_SHIFT); - } /* Initiate transmission */ kw41zrf_set_sequence(dev, XCVSEQ_TRANSMIT); - irq_restore(mask); } + if (backoff_delay > 0) { + /* Set real trigger time for CSMA */ + kw41zrf_timer_set(dev, &ZLL->T2CMP, backoff_delay); + } + if (tx_timeout > 0) { + /* Set real timeout for RX ACK */ + kw41zrf_timer_set(dev, &ZLL->T3CMP, tx_timeout); + } + irq_restore(mask); } /** From d07734abef4f83cd61e2bd7ed246c9692d8b76c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 27 Oct 2018 18:38:33 +0200 Subject: [PATCH 38/82] squash kw41zrf refactor IRQ flags with DSM --- drivers/kw41zrf/kw41zrf.c | 3 +-- drivers/kw41zrf/kw41zrf_intern.c | 14 ++++++++++++-- drivers/kw41zrf/kw41zrf_netdev.c | 8 ++++---- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 8f5fda043627..2cf95b78b044 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -123,9 +123,8 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16; /* Configure Radio IRQ */ + kw41zrf_mask_irqs(); kw41zrf_set_irq_callback(cb, dev); - NVIC_ClearPendingIRQ(Radio_1_IRQn); - NVIC_EnableIRQ(Radio_1_IRQn); kw41zrf_abort_sequence(dev); kw41zrf_unmask_irqs(); diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index bb5030502315..dca0f20c9df3 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -138,8 +138,13 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) ZLL->EVENT_TMR = ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK | ZLL_EVENT_TMR_EVENT_TMR(usec); + /* Clear IRQ flags */ + uint32_t irqsts = ZLL->IRQSTS; + DEBUG("[kw41zrf] wake IRQSTS=%" PRIx32 "\n", irqsts); + ZLL->IRQSTS = irqsts; + /* Disable DSM timer triggered sleep */ - ZLL->DSM_CTRL &= ~ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; + ZLL->DSM_CTRL = 0; break; } @@ -163,8 +168,13 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* cppcheck-suppress selfAssignment * (reason: IRQ flags are write-1-to-clear) */ RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; + uint32_t irqsts = ZLL->IRQSTS; + DEBUG("[kw41zrf] sleep IRQSTS=%" PRIx32 "\n", irqsts); + ZLL->IRQSTS = irqsts; + NVIC_ClearPendingIRQ(Radio_1_IRQn); + /* Enable timer triggered sleep */ - ZLL->DSM_CTRL |= ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; + ZLL->DSM_CTRL = ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK; /* The device will automatically wake up 8.5 minutes from now if not * awoken sooner by software */ /* TODO handle automatic wake in the ISR if it becomes an issue */ diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 7659630b005c..e54d53c7c774 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -1219,8 +1219,6 @@ static void kw41zrf_netdev_isr(netdev_t *netdev) /* Clear all IRQ flags now */ ZLL->IRQSTS = irqsts; - kw41zrf_unmask_irqs(); - uint32_t handled_irqs = 0; DEBUG("[kw41zrf] CTRL %08" PRIx32 ", IRQSTS %08" PRIx32 ", FILTERFAIL %08" PRIx32 "\n", ZLL->PHY_CTRL, irqsts, ZLL->FILTERFAIL_CODE); @@ -1265,10 +1263,12 @@ static void kw41zrf_netdev_isr(netdev_t *netdev) irqsts &= ~handled_irqs; - if (irqsts & 0x000f017f) { + if (irqsts & 0x000f017ful) { DEBUG("[kw41zrf] Unhandled IRQs: 0x%08"PRIx32"\n", - (irqsts & 0x000f017f)); + (irqsts & 0x000f017ful)); } + + kw41zrf_unmask_irqs(); } const netdev_driver_t kw41zrf_driver = { From 30ee23306335ae0c623a87baa32e20a672163667 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 27 Oct 2018 18:39:47 +0200 Subject: [PATCH 39/82] squash kw41zrf prevent dead lock when ISR is run while DSM --- drivers/kw41zrf/kw41zrf_netdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index e54d53c7c774..16333bec11cf 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -1212,6 +1212,7 @@ static void kw41zrf_netdev_isr(netdev_t *netdev) /* Transceiver is sleeping, the IRQ must have occurred before entering * sleep, discard the call */ DEBUG("kw41zrf: unexpected IRQ while sleeping\n"); + kw41zrf_unmask_irqs(); return; } uint32_t irqsts = ZLL->IRQSTS; From c0606ce4424282b18cecae6066eec89e0971798a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 28 Oct 2018 09:46:50 +0100 Subject: [PATCH 40/82] REMOVE kw41zrf deugging calibration failures --- drivers/kw41zrf/kw41zrf.c | 7 ++- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 2 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 52 +++++++++++++++++-- 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 2cf95b78b044..f1823d76bc29 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -29,6 +29,7 @@ #include "kw41zrf_getset.h" #include "kw41zrf_intern.h" #include "vendor/XCVR/MKW41Z4/fsl_xcvr.h" +#include "periph/timer.h" #define ENABLE_DEBUG (0) #include "debug.h" @@ -98,8 +99,12 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) /* Wait for oscillator ready signal */ while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + timer_init(TIMER_PIT_DEV(0), 1000000ul, NULL, NULL); + uint32_t before = timer_read(TIMER_PIT_DEV(0)); + printf("[kw41zrf] start init\n"); xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); - + uint32_t after = timer_read(TIMER_PIT_DEV(0)); + printf("[kw41zrf] took %" PRIu32 " us\n", (after - before)); if (xcvrStatus != gXcvrSuccess_c) { /* initialization error signaled from vendor driver */ /* Restore saved RF_OSC_EN setting */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index 6b15959cf2dd..f759636cf9c7 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -1094,7 +1094,7 @@ xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; -// if (!rx_bba_dcoc_dac_trim_shortIQ()) + //~ if (!rx_bba_dcoc_dac_trim_shortIQ()) if (!rx_bba_dcoc_dac_trim_DCest()) { config_status = gXcvrTrimFailure_c; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index 4ab38c31a88e..795584f76e90 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -38,6 +38,8 @@ #include "fsl_xcvr.h" #include "fsl_xcvr_trim.h" #include "dbg_ram_capture.h" +#include +#include /******************************************************************************* * Definitions @@ -113,7 +115,6 @@ static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = ***********************************************************************************/ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) { - uint8_t i; float temp_mi = 0; float temp_mq = 0; float temp_pi = 0; @@ -202,54 +203,75 @@ uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + printf("temp_mi = %f\n", temp_mi); + printf("temp_mq = %f\n", temp_mq); + printf("temp_pi = %f\n", temp_pi); + printf("temp_pq = %f\n", temp_pq); + printf("temp_step = %f\n", temp_step); + printf("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) { bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + printf("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */ - for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ + for (unsigned i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ { /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ switch(i){ case TZA_STEP_N0: temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + printf("temp_step0 = %f\n", temp_step); break; case TZA_STEP_N1: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); + printf("temp_step1 = %f\n", temp_step); break; case TZA_STEP_N2: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); + printf("temp_step2 = %f\n", temp_step); break; case TZA_STEP_N3: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); + printf("temp_step3 = %f\n", temp_step); break; case TZA_STEP_N4: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); + printf("temp_step4 = %f\n", temp_step); break; case TZA_STEP_N5: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); + printf("temp_step5 = %f\n", temp_step); break; case TZA_STEP_N6: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); + printf("temp_step6 = %f\n", temp_step); break; case TZA_STEP_N7: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); + printf("temp_step7 = %f\n", temp_step); break; case TZA_STEP_N8: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); + printf("temp_step8 = %f\n", temp_step); break; case TZA_STEP_N9: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); + printf("temp_step9 = %f\n", temp_step); break; case TZA_STEP_N10: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); + printf("temp_step10 = %f\n", temp_step); break; default: break; } tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + printf("tza_dcoc_step[%u].dcoc_step = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step); tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + printf("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp); } /* Make the trims active. */ @@ -682,12 +704,20 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; + temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + printf("temp_mi = %f\n", temp_mi); + printf("temp_mq = %f\n", temp_mq); + printf("temp_pi = %f\n", temp_pi); + printf("temp_pq = %f\n", temp_pq); + printf("temp_step = %f\n", temp_step); + printf("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) { bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + printf("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) @@ -695,44 +725,57 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ switch(i){ case TZA_STEP_N0: - temp_step = (bbf_dcoc_step>>3U) / 3.6F; + temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + printf("temp_step0 = %f\n", temp_step); break; case TZA_STEP_N1: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16); + printf("temp_step1 = %f\n", temp_step); break; case TZA_STEP_N2: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16); + printf("temp_step2 = %f\n", temp_step); break; case TZA_STEP_N3: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16); + printf("temp_step3 = %f\n", temp_step); break; case TZA_STEP_N4: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16); + printf("temp_step4 = %f\n", temp_step); break; case TZA_STEP_N5: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16); + printf("temp_step5 = %f\n", temp_step); break; case TZA_STEP_N6: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16); + printf("temp_step6 = %f\n", temp_step); break; case TZA_STEP_N7: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16); + printf("temp_step7 = %f\n", temp_step); break; case TZA_STEP_N8: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16); + printf("temp_step8 = %f\n", temp_step); break; case TZA_STEP_N9: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16); + printf("temp_step9 = %f\n", temp_step); break; case TZA_STEP_N10: temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16); + printf("temp_step10 = %f\n", temp_step); break; default: break; } tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + printf("tza_dcoc_step[%u].dcoc_step = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step); tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + printf("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp); } /* Make the trims active */ @@ -754,6 +797,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) } else { + printf("!!! XCVR trim failed: bbf_dcoc_step = %"PRIu32"!\n", bbf_dcoc_step); status = 0; /* Failure */ } From 90a2ffa55fe3fbde7f4d1cfb8d7b727f15104946 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 28 Oct 2018 11:33:14 +0100 Subject: [PATCH 41/82] squash kw41zrf Clean up unused vendor code --- .../vendor/XCVR/MKW41Z4/dbg_ram_capture.c | 165 ------- .../vendor/XCVR/MKW41Z4/dbg_ram_capture.h | 214 -------- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 28 +- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 466 ++---------------- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 2 +- 5 files changed, 39 insertions(+), 836 deletions(-) delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c deleted file mode 100644 index a727780af524..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.c +++ /dev/null @@ -1,165 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#include "cpu.h" -#include "fsl_xcvr.h" -#include "dbg_ram_capture.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#if RADIO_IS_GEN_3P0 -#define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */ -#else -#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */ -#endif /* RADIO_IS_GEN_3P0 */ -#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0)) -#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0)) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -void dbg_ram_init(void) -{ - XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */ - XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */ - - /* Some external code must perform the RX warmup request. */ -} - - -dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer) -{ - dbgRamStatus_t status = DBG_RAM_SUCCESS; - uint32_t temp; - volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1; - uint8_t * output_ptr; - uint16_t i; - - /* Some external code must perform the RX warmup request after the dbg_ram_init() call */ - - if (result_buffer == NULL) - { - status = DBG_RAM_FAIL_NULL_POINTER; - } - else - { - if (buffer_sz_bytes > (544*2*2)) - { - status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT; - } - else - { - temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; - switch (dbg_page) - { - case DBG_PAGE_RXDIGIQ: - case DBG_PAGE_RAWADCIQ: - case DBG_PAGE_DCESTIQ: - XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); - - while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) - { - /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ - } - /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ - output_ptr = result_buffer; -#if !RADIO_IS_GEN_2P1 - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); - pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]); -#else - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); - pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */ -#endif /* !RADIO_IS_GEN_2P1 */ - /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */ - for (i = 0; i < buffer_sz_bytes / 4; i++) - { - *output_ptr++ = *pkt_ram_ptr0++; - *output_ptr++ = *pkt_ram_ptr0++; - *output_ptr++ = *pkt_ram_ptr1++; - *output_ptr++ = *pkt_ram_ptr1++; - } - - break; - case DBG_PAGE_RXINPH: - case DBG_PAGE_DEMOD_HARD: - case DBG_PAGE_DEMOD_SOFT: - case DBG_PAGE_DEMOD_DATA: - case DBG_PAGE_DEMOD_CFO_PH: - XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); - while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) - { - /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ - } - /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ - output_ptr = result_buffer; -#if !RADIO_IS_GEN_2P1 - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); -#else - pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); -#endif /* !RADIO_IS_GEN_2P1 */ - /* This is for non I/Q */ - for (i = 0; i < buffer_sz_bytes; i++) - { - *output_ptr = *pkt_ram_ptr0; - pkt_ram_ptr0++; - output_ptr++; - } - break; - case DBG_PAGE_IDLE: - default: - status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */ - break; - } - } - } - - XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */ - - /* Process the samples and copy to output pointer */ - - XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */ - XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */ - - return status; -} diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h deleted file mode 100644 index 3d8933e93384..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/dbg_ram_capture.h +++ /dev/null @@ -1,214 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#ifndef _DBG_RAM_CAPTURE_H_ -/* clang-format off */ -#define _DBG_RAM_CAPTURE_H_ -/* clang-format on */ - -#include "fsl_xcvr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - * @addtogroup xcvr - * @{ - */ - -/*! @file*/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Page definitions */ -#define DBG_PAGE_IDLE (0x00) -#define DBG_PAGE_RXDIGIQ (0x01) -#define DBG_PAGE_RAWADCIQ (0x04) -#define DBG_PAGE_DCESTIQ (0x07) -#define DBG_PAGE_RXINPH (0x0A) -#define DBG_PAGE_DEMOD_HARD (0x0B) -#define DBG_PAGE_DEMOD_SOFT (0x0C) -#define DBG_PAGE_DEMOD_DATA (0x0D) -#define DBG_PAGE_DEMOD_CFO_PH (0x0E) - -typedef enum _dbgRamStatus -{ - DBG_RAM_SUCCESS = 0, - DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1, - DBG_RAM_FAIL_PAGE_ERROR = 2, - DBG_RAM_FAIL_NULL_POINTER = 3, - DBG_RAM_INVALID_TRIG_SETTING = 4, - DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5, - DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */ -} dbgRamStatus_t; - -#if RADIO_IS_GEN_3P0 -typedef enum _dbgRamStartTriggerType -{ - NO_START_TRIG = 0, - START_ON_FSK_PREAMBLE_FOUND = 1, - START_ON_FSK_AA_MATCH = 2, - START_ON_ZBDEMOD_PREAMBLE_FOUND = 3, - START_ON_ZBDEMOD_SFD_MATCH = 4, - START_ON_AGC_DCOC_GAIN_CHG = 5, - START_ON_TSM_RX_DIG_EN = 6, - START_ON_TSM_SPARE2_EN = 7, - INVALID_START_TRIG = 8 -} dbgRamStartTriggerType; - -typedef enum _dbgRamStopTriggerType -{ - NO_STOP_TRIG = 0, - STOP_ON_FSK_PREAMBLE_FOUND = 1, - STOP_ON_FSK_AA_MATCH = 2, - STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3, - STOP_ON_ZBDEMOD_SFD_MATCH = 4, - STOP_ON_AGC_DCOC_GAIN_CHG = 5, - STOP_ON_TSM_RX_DIG_EN = 6, - STOP_ON_TSM_SPARE3_EN = 7, - STOP_ON_TSM_PLL_UNLOCK = 8, - STOP_ON_BLE_CRC_ERROR_INC = 9, - STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10, - STOP_ON_GENFSK_HEADER_FAIL = 11, - INVALID_STOP_TRIG = 12 -} dbgRamStopTriggerType; -#endif /* RADIO_IS_GEN_3P0 */ - -/*! ********************************************************************************* - * \brief This function prepares for sample capture to packet RAM. - * - * \return None. - * - * \details - * This routine assumes that some other functions in the calling routine both set - * the channel and force RX warmup before calling ::dbg_ram_capture(). - ***********************************************************************************/ -void dbg_ram_init(void); - -/*! ********************************************************************************* - * \brief This function performs any state restoration at the completion of PKT RAM capture. - * - * \details - * Any clocks enabled to the packet RAM capture circuitry are disabled. - ***********************************************************************************/ -void dbg_ram_release(void); - -#if RADIO_IS_GEN_3P0 -/*! ********************************************************************************* - * \brief This function initiates the capture of transceiver data to the transceiver packet RAM. - * - * \param[in] dbg_page - The page selector (DBG_PAGE). - * \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled). - * \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled). - * - * \return Status of the request. - * - * \details - * This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger - * settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to - * perform a blocking wait for completion or allow polling for completion of the capture. - * After any capture has completed, a separate routine must be called to postprocess the capture and copy all - * data out of the packet RAM into a normal RAM buffer. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig); - -/*! ********************************************************************************* - * \brief This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM. - * - * \return Status of the request, DBG_RAM_SUCCESS if capture is complete. - * - * \details - * This function performs a wait loop for capture completion and may take an indeterminate amount of time for - * some capture trigger types. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */ - -/*! ********************************************************************************* - * \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM. - * - * \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete. - * - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */ - -/*! ********************************************************************************* - * \brief This function processes the captured data into a usable order and copies from packet RAM to normal RAM. - * - * \param[in] dbg_page - The page selector (DBG_PAGE). - * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) - * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. - * - * \return None. - * - * \details - * Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM - * (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM. - * If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out. - * If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */ - -#else -/*! ********************************************************************************* - * \brief This function captures transceiver data to the transceiver packet RAM. - * - * \param[in] dbg_page - The page selector (DBG_PAGE). - * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) - * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. - * - * \return None. - * - * \details - * The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be - * copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have - * been copied. Data will be copied - * NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has - * not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is - * intended to be used with manually triggered RX where RX data will continue as long as needed. - ***********************************************************************************/ -dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); -#endif /* RADIO_IS_GEN_3P0 */ - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* _DBG_RAM_CAPTURE_H_ */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index f759636cf9c7..39fefa08d7b4 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -396,18 +396,13 @@ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) #endif /* ifndef SIMULATION */ /* Perform the desired XCVR initialization and configuration */ - status = XCVR_GetDefaultConfig(radio_mode, data_rate, - (const xcvr_common_config_t **)&radio_common_config, - (const xcvr_mode_config_t **)&radio_mode_cfg, - (const xcvr_mode_datarate_config_t **)&mode_datarate_config, - (const xcvr_datarate_config_t **)&datarate_config); + status = XCVR_GetDefaultConfig(radio_mode, data_rate, &radio_common_config, + &radio_mode_cfg, &mode_datarate_config, &datarate_config); if (status == gXcvrSuccess_c) { - status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, - (const xcvr_mode_config_t *)radio_mode_cfg, - (const xcvr_mode_datarate_config_t *)mode_datarate_config, - (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT); + status = XCVR_Configure(radio_common_config, radio_mode_cfg, + mode_datarate_config, datarate_config, 25, XCVR_FIRST_INIT); current_xcvr_config.radio_mode = radio_mode; current_xcvr_config.data_rate = data_rate; } @@ -415,17 +410,6 @@ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) return status; } -void XCVR_Deinit(void) -{ -#if RADIO_IS_GEN_3P0 - rf_osc_shutdown(); - RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */ - RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */ -#else - -#endif /* RADIO_IS_GEN_3P0 */ -} - xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, data_rate_t data_rate, const xcvr_common_config_t ** com_config, @@ -1502,11 +1486,13 @@ uint32_t XCVR_GetFreq ( void ) uint32_t ref_clk = 32U; #endif /* RF_OSC_26MHZ == 1 */ + printf("pll_num_unsigned = %08" PRIx32 "\n", pll_num_unsigned); /* Check if sign bit is asserted */ if (pll_num_unsigned & 0x04000000U) { /* Sign extend the numerator */ pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; + printf("pll_num = %" PRIu32 ", pll_denom = %" PRIu32 "\n", pll_num, pll_denom); /* Calculate the frequency in MHz */ freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); @@ -1515,8 +1501,10 @@ uint32_t XCVR_GetFreq ( void ) { /* Calculate the frequency in MHz */ pll_num = pll_num_unsigned; + printf("pll_num = %" PRIu32 ", pll_denom = %" PRIu32 "\n", pll_num, pll_denom); freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); } + printf("freq_float = %f\n", freq_float); freq = (uint32_t)freq_float; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index 795584f76e90..c1e82deb071d 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -33,11 +33,9 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include #include "cpu.h" #include "fsl_xcvr.h" #include "fsl_xcvr_trim.h" -#include "dbg_ram_capture.h" #include #include @@ -102,257 +100,6 @@ static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = /******************************************************************************* * Code ******************************************************************************/ -/*! ********************************************************************************* - * \brief This function performs a trim of the BBA DCOC DAC on the DUT - * - * \return status - 1 if passed, 0 if failed. - * - * \ingroup PublicAPIs - * - * \details - * Requires the RX to be warmed up before this function is called. - * - ***********************************************************************************/ -uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) -{ - float temp_mi = 0; - float temp_mq = 0; - float temp_pi = 0; - float temp_pq = 0; - float temp_step = 0; - uint8_t bbf_dacinit_i, bbf_dacinit_q; - - uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */ - uint32_t bbf_dcoc_step; - uint32_t bbf_dcoc_step_rcp; - TZAdcocstep_t tza_dcoc_step[11]; - uint8_t status = 0; - - /* Save register values. */ - uint32_t dcoc_ctrl_0_stack; - uint32_t dcoc_ctrl_1_stack; - uint32_t agc_ctrl_1_stack; - uint32_t rx_dig_ctrl_stack; - uint32_t dcoc_cal_gain_state; - - XcvrCalDelay(1000); - dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */ - dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */ - rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */ - agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */ - dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */ - - /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */ - XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */ - - XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */ - XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */ - - XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */ - XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ - /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); - /* Set DCOC Tracking State. */ - XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */ - /* Apply Manual Gain. */ - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ; - XcvrCalDelay(TsettleCal); - - dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */ - - bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); - bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; - - DC_Measure_short(I_CHANNEL, NOMINAL2); - DC_Measure_short(Q_CHANNEL, NOMINAL2); - - /* SWEEP Q CHANNEL */ - /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(Q_CHANNEL, BBF_NEG); - - /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(Q_CHANNEL, BBF_POS); - - XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */ - XcvrCalDelay(TsettleCal); - - /* SWEEP I CHANNEL */ - /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(I_CHANNEL, BBF_NEG); - /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); - XcvrCalDelay(TsettleCal); - DC_Measure_short(I_CHANNEL, BBF_POS); - - XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */ - XcvrCalDelay(TsettleCal); - - /* Calculate BBF DCOC STEPS, RECIPROCALS */ - temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - - temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4; - - bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); - - printf("temp_mi = %f\n", temp_mi); - printf("temp_mq = %f\n", temp_mq); - printf("temp_pi = %f\n", temp_pi); - printf("temp_pq = %f\n", temp_pq); - printf("temp_step = %f\n", temp_step); - printf("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); - - if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) - { - bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); - printf("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); - - /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */ - for (unsigned i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ - { - /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ - switch(i){ - case TZA_STEP_N0: - temp_step = (bbf_dcoc_step >> 3U) / 3.6F; - printf("temp_step0 = %f\n", temp_step); - break; - case TZA_STEP_N1: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); - printf("temp_step1 = %f\n", temp_step); - break; - case TZA_STEP_N2: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); - printf("temp_step2 = %f\n", temp_step); - break; - case TZA_STEP_N3: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); - printf("temp_step3 = %f\n", temp_step); - break; - case TZA_STEP_N4: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); - printf("temp_step4 = %f\n", temp_step); - break; - case TZA_STEP_N5: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); - printf("temp_step5 = %f\n", temp_step); - break; - case TZA_STEP_N6: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); - printf("temp_step6 = %f\n", temp_step); - break; - case TZA_STEP_N7: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); - printf("temp_step7 = %f\n", temp_step); - break; - case TZA_STEP_N8: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); - printf("temp_step8 = %f\n", temp_step); - break; - case TZA_STEP_N9: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); - printf("temp_step9 = %f\n", temp_step); - break; - case TZA_STEP_N10: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); - printf("temp_step10 = %f\n", temp_step); - break; - default: - break; - } - - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); - printf("tza_dcoc_step[%u].dcoc_step = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step); - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); - printf("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp); - } - - /* Make the trims active. */ - XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ; - - status = 1; /* Success */ - } - else - { - status = 0; /* Failure */ - } - - /* Restore Registers. */ - XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */ - XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */ - XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */ - XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */ - XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */ - - return status; -} - -/*! ********************************************************************************* - * \brief This function performs one point of the DC GAIN calibration process on the DUT - * - * \param[in] chan - whether the I or Q channel is being tested. - * \param[in] stage - whether the BBF or TZA gain stage is being tested. - * \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent. - * \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup. - * - * \ingroup PublicAPIs - * - * \details - * Relies on a static array to store each point of data for later processing in ::DC_GainCalc(). - * - ***********************************************************************************/ -void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) -{ - int16_t dc_meas_i = 0; - int16_t dc_meas_q = 0; - int16_t sum_dc_meas_i = 0; - int16_t sum_dc_meas_q = 0; - - { - int8_t i; - const int8_t iterations = 1; - sum_dc_meas_i = 0; - sum_dc_meas_q = 0; - - for (i = 0; i < iterations; i++) - { - rx_dc_sample_average(&dc_meas_i, &dc_meas_q); - sum_dc_meas_i = sum_dc_meas_i + dc_meas_i; - sum_dc_meas_q = sum_dc_meas_q + dc_meas_q; - } - sum_dc_meas_i = sum_dc_meas_i / iterations; - sum_dc_meas_q = sum_dc_meas_q / iterations; - } - - measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val]; - - if (chan == I_CHANNEL) - { - measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i; - } - else - { - measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q; - } -} /*! ********************************************************************************* * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. @@ -360,20 +107,22 @@ void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. * - * \return result of the calculation, the measurement DCOC DAC step value for this measurement point. + * \return Q15.16 result of the calculation, the measurement DCOC DAC step value for this measurement point. * ***********************************************************************************/ float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) { - static int16_t norm_dc_code; - static float dc_step; + int32_t norm_dc_code; + float dc_step; /* Normalize internal measurement */ - norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; - dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value); - dc_step = (dc_step < 0)? -dc_step: dc_step; + norm_dc_code = (int32_t)meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; + dc_step = (norm_dc_code << 16) / meas_ptr->step_value; + if (dc_step < 0) { + dc_step = -dc_step; + } - return dc_step; + return (float)dc_step / (1 << 16); } /*! ********************************************************************************* @@ -394,189 +143,34 @@ void XcvrCalDelay(uint32_t time) } } -/*! ********************************************************************************* - * \brief This function calculates the average (DC value) based on a smaller set of digital samples of I and Q. - * - * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. - * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. - * - ***********************************************************************************/ -void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) -{ - static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */ - uint16_t i; - uint32_t rx_sample; - uint16_t * sample_ptr; - uint32_t temp, end_of_rx_wu; - uint32_t num_iq_samples; - float avg_i = 0; - float avg_q = 0; - - num_iq_samples = 128; - - /* Clear the entire allocated sample buffer */ - for (i = 0; i < num_iq_samples; i++) - { - samples[i]=0; - } - - /* Assume this has been called *AFTER* RxWu has completed. */ - /* XCVR_ForceRxWu(); */ - - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - - dbg_ram_init(); - /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ -#if RADIO_IS_GEN_3P0 - dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); - dbg_ram_wait_for_complete(); - dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); - dbg_ram_release(); -#else - (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); -#endif /* RADIO_IS_GEN_3P0 */ - - /* Sign extend the IQ samples in place in the sample buffer. */ - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i++) - { - rx_sample = *sample_ptr; - rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - *sample_ptr = rx_sample; - sample_ptr++; - } - - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i += 2) - { - static int16_t i_value; - static int16_t q_value; - - /* Average I & Q channels separately. */ - i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */ - q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */ - avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ - avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ - } - XcvrCalDelay(10); - *i_avg = (int16_t)avg_i; - *q_avg = (int16_t)avg_q; -} - -/*! ********************************************************************************* - * \brief This function calculates the average (DC value) based on a larger set of digital samples of I and Q. - * - * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. - * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. - * - ***********************************************************************************/ -void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) -{ - static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */ - uint16_t i; - uint32_t rx_sample; - uint16_t * sample_ptr; - uint32_t temp, end_of_rx_wu; - uint32_t num_iq_samples; - float avg_i = 0; - float avg_q = 0; - - num_iq_samples = 512; - - /* Clear the entire allocated sample buffer. */ - for (i = 0; i < num_iq_samples; i++) - { - samples[i]=0; - } - - /* Assume this has been called *AFTER* RxWu has completed. */ - /* XCVR_ForceRxWu(); */ - - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - - dbg_ram_init(); - /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ -#if RADIO_IS_GEN_3P0 - dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); - dbg_ram_wait_for_complete(); - dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]); - dbg_ram_release(); -#else - (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); -#endif /* RADIO_IS_GEN_3P0 */ - - /* Sign extend the IQ samples in place in the sample buffer. */ - - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i++) - { - rx_sample = *sample_ptr; - rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - *sample_ptr = rx_sample; - sample_ptr++; - } - - sample_ptr = (uint16_t *)(&samples[0]); - for (i = 0; i < num_iq_samples * 2; i += 2) - { - static int16_t i_value; - static int16_t q_value; - - /* Average I & Q channels separately. */ - i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */ - q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */ - avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ - avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ - } - - XcvrCalDelay(10); - *i_avg = (int16_t)avg_i; - *q_avg = (int16_t)avg_q; -} - /*! ********************************************************************************* * rx_dc_est_average : Get DC EST values and return the Average ***********************************************************************************/ -void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber) +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg) { - float avg_i = 0; - float avg_q = 0; - uint16_t i = 0; - static uint32_t dc_temp, temp; - uint32_t end_of_rx_wu = 0; - static int16_t dc_meas_i; - static int16_t dc_meas_q; + static const unsigned nsamples = 64; + int32_t avg_i = 0; + int32_t avg_q = 0; /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + uint32_t end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; /* Read DCOC DC EST register. */ - for (i = 0; i < SampleNumber; i++) + for (unsigned k = 0; k < nsamples; k++) { - dc_temp = XCVR_RX_DIG->DCOC_DC_EST; - dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK; - temp = dc_meas_i; - temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - dc_meas_i = temp; - avg_i += (float) dc_meas_i; - - dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; - temp = dc_meas_q; - temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ - dc_meas_q = temp; - avg_q += (float) dc_meas_q; + uint32_t dc_temp = XCVR_RX_DIG->DCOC_DC_EST; + int16_t dc_meas_i = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT; + dc_meas_i |= ((dc_meas_i & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + avg_i += dc_meas_i; + + int16_t dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; + dc_meas_q |= ((dc_meas_q & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + avg_q += dc_meas_q; } - avg_i /= (float) SampleNumber; - avg_q /= (float) SampleNumber; + avg_i /= nsamples; + avg_q /= nsamples; *i_avg = (int16_t)avg_i; *q_avg = (int16_t)avg_q; @@ -663,7 +257,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; XcvrCalDelay(TsettleCal * 4); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + rx_dc_est_average(&dc_meas_i, &dc_meas_q); measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i; @@ -677,7 +271,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + rx_dc_est_average(&dc_meas_i, &dc_meas_q); measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16; measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16; measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i; @@ -690,7 +284,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + rx_dc_est_average(&dc_meas_i, &dc_meas_q); measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16; measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16; measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i; @@ -900,7 +494,7 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + rx_dc_est_average(&dc_meas_i, &dc_meas_q); } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); for (i = 0; i < 0x0F; i++) @@ -1023,7 +617,7 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + rx_dc_est_average(&dc_meas_i, &dc_meas_q); } /* Apply optimized DCOC DAC INIT : */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h index a83c2ea5515b..f633f76828ca 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -123,7 +123,7 @@ void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); void XcvrCalDelay(uint32_t time); -void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber); +void rx_dc_est_average(int16_t *i_avg, int16_t *q_avg); uint8_t rx_bba_dcoc_dac_trim_DCest(void); void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); From fff23d097d7d413ead3bfcb9e5b5eff4e21c9e26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sun, 28 Oct 2018 13:03:08 +0100 Subject: [PATCH 42/82] squash kw41zrf slimmer vendor init --- drivers/kw41zrf/kw41zrf.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index f1823d76bc29..688904371593 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -82,6 +82,33 @@ void kw41zrf_setup(kw41zrf_t *dev) DEBUG("[kw41zrf] setup finished\n"); } +static int kw41zrf_xcvr_init(kw41zrf_t *dev) +{ + (void) dev; + uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK) >> RSIM_MISC_RADIO_VERSION_SHIFT); + switch (radio_id) { + case 0x3: /* KW41/31/21 v1 */ + case 0xb: /* KW41/31/21 v1.1 */ + break; + default: + return -ENODEV; + } + + RSIM->RF_OSC_CTRL = (RSIM->RF_OSC_CTRL & + ~(RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)) | /* Set EXT_OSC_OVRD value to zero */ + RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ + bit_set32(&SIM->SCGC5, SIM_SCGC5_PHYDIG_SHIFT); /* Enable PHY clock gate */ + + /* We only use 802.15.4 mode in this driver */ + xcvrStatus_t status = XCVR_Configure(&xcvr_common_config, &zgbe_mode_config, + &xcvr_ZIGBEE_500kbps_config, &xcvr_802_15_4_500kbps_config, 25, XCVR_FIRST_INIT); + + if (status != gXcvrSuccess_c) { + return -EIO; + } + return 0; +} + int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) { if (dev == NULL) { @@ -100,18 +127,17 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} timer_init(TIMER_PIT_DEV(0), 1000000ul, NULL, NULL); - uint32_t before = timer_read(TIMER_PIT_DEV(0)); printf("[kw41zrf] start init\n"); - xcvrStatus_t xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); + uint32_t before = timer_read(TIMER_PIT_DEV(0)); + int res = kw41zrf_xcvr_init(dev); uint32_t after = timer_read(TIMER_PIT_DEV(0)); printf("[kw41zrf] took %" PRIu32 " us\n", (after - before)); - if (xcvrStatus != gXcvrSuccess_c) { + if (res < 0) { /* initialization error signaled from vendor driver */ /* Restore saved RF_OSC_EN setting */ RSIM->CONTROL = (RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) | dev->rf_osc_en_idle; - return -EIO; + return res; } - /* Software reset of most settings */ kw41zrf_reset_phy(dev); From 9eec35b7547eeb65a4aa0dc518a4192ebe0a0430 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 29 Oct 2018 12:59:21 +0100 Subject: [PATCH 43/82] squash kw41zrf vendor clean up exports --- .../kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c index 4a2a58067b50..92a8786c94e6 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/ifr_radio.c @@ -59,11 +59,11 @@ /******************************************************************************* * Prototypes ******************************************************************************/ -uint32_t read_another_ifr_word(void); -uint32_t read_first_ifr_word(uint32_t read_addr); +static uint32_t read_another_ifr_word(void); +static uint32_t read_first_ifr_word(uint32_t read_addr); #if RADIO_IS_GEN_3P0 -uint64_t read_index_ifr(uint32_t read_addr); +static uint64_t read_index_ifr(uint32_t read_addr); #else /*! ********************************************************************************* * @brief Reads a location in block 1 IFR for use by the radio. @@ -75,13 +75,13 @@ uint64_t read_index_ifr(uint32_t read_addr); * @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index ***********************************************************************************/ #if RADIO_IS_GEN_2P1 -uint64_t read_resource_ifr(uint32_t read_addr); +static uint64_t read_resource_ifr(uint32_t read_addr); #else -uint32_t read_resource_ifr(uint32_t read_addr); +static uint32_t read_resource_ifr(uint32_t read_addr); #endif /* RADIO_IS_GEN_2P1 */ #endif /* RADIO_IS_GEN_3P0 */ -void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); +static void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); /******************************************************************************* * Variables @@ -144,7 +144,7 @@ const uint32_t BLOCK_1_IFR[]= * \return 8 bytes of packed data containing radio trims only * ***********************************************************************************/ -uint32_t read_first_ifr_word(uint32_t read_addr) +static uint32_t read_first_ifr_word(uint32_t read_addr) { ifr_read_addr = read_addr; return read_another_ifr_word(); @@ -161,7 +161,7 @@ uint32_t read_first_ifr_word(uint32_t read_addr) * The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use. * ***********************************************************************************/ -uint32_t read_another_ifr_word(void) +static uint32_t read_another_ifr_word(void) { uint32_t packed_data; @@ -199,7 +199,7 @@ uint32_t read_another_ifr_word(void) * \return 8 bytes of packed data containing radio trims only * ***********************************************************************************/ -uint64_t read_index_ifr(uint32_t read_addr) +static uint64_t read_index_ifr(uint32_t read_addr) { uint8_t rdindex = read_addr; uint64_t read_data; @@ -241,7 +241,7 @@ uint64_t read_index_ifr(uint32_t read_addr) * ***********************************************************************************/ #if RADIO_IS_GEN_2P0 -uint32_t read_resource_ifr(uint32_t read_addr) +static uint32_t read_resource_ifr(uint32_t read_addr) { uint32_t packed_data; @@ -281,7 +281,7 @@ uint32_t read_resource_ifr(uint32_t read_addr) return packed_data; } #else -uint64_t read_resource_ifr(uint32_t read_addr) +static uint64_t read_resource_ifr(uint32_t read_addr) { uint64_t packed_data; @@ -343,7 +343,7 @@ uint64_t read_resource_ifr(uint32_t read_addr) * \param data the value of the software trim * ***********************************************************************************/ -void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) +static void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) { uint16_t i; From acbfb17c29390ec0eb55b7c85eb539304b3010d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 29 Oct 2018 13:00:01 +0100 Subject: [PATCH 44/82] squash kw41zrf vendor slimming WIP --- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 7 + .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 8 - .../vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c | 212 --------- .../vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c | 206 --------- .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 416 ----------------- .../fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c | 402 ----------------- .../fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c | 421 ------------------ .../fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c | 403 ----------------- .../fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c | 403 ----------------- .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 417 ----------------- .../vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c | 406 ----------------- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 227 ++++------ 12 files changed, 90 insertions(+), 3438 deletions(-) delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c index 39fefa08d7b4..ac1b843a6219 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c @@ -391,6 +391,13 @@ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) /* Load IFR trim values */ handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); + printf("sw_trim_tbl:\n"); + for (unsigned k = 0; k < NUM_TRIM_TBL_ENTRIES; ++k) { + printf("[%u] id=0x%04x, trim=%" PRIu32 ", valid=%u\n", k, + (unsigned)sw_trim_tbl[k].trim_id, + sw_trim_tbl[k].trim_value, + (unsigned)sw_trim_tbl[k].valid); + } #endif /* RADIO_IS_GEN_3P0 */ #endif /* ifndef SIMULATION */ diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h index d5faa10d1ad7..1994e59a8a88 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -896,14 +896,6 @@ extern "C" { */ xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); -/*! - * @brief Deinitializes an XCVR instance. - * - * This function gate the XCVR module clock and set all register value to reset value. - * - */ -void XCVR_Deinit(void); - /*! * @brief Initializes XCVR configure structure. * diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c deleted file mode 100644 index d036e20bea18..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ant_config.c +++ /dev/null @@ -1,212 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -const xcvr_mode_config_t ant_mode_config = -{ - .radio_mode = ANT_MODE, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK -#if !RADIO_IS_GEN_2P1 - | SIM_SCGC5_ANT_MASK -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = RW0PS(0, 0x1B) | - RW0PS(1, 0x1CU) | - RW0PS(2, 0x1CU) | - RW0PS(3, 0x1CU) | - RW0PS(4, 0x1DU) | - RW0PS(5, 0x1DU) | - RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/ - .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */ - RW1PS(7, 0x1EU) | - RW1PS(8, 0x1EU) | - RW1PS(9, 0x1EU) | - RW1PS(10, 0x1EU) | - RW1PS(11, 0x1DU) | - RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */ - .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */ - RW2PS(13, 0x1CU) | - RW2PS(14, 0x1CU) | - RW2PS(15, 0x1CU), - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xF8) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = -{ - .radio_mode = ANT_MODE, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, - - /* ANT 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c deleted file mode 100644 index 25a07f4b3a67..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_ble_config.c +++ /dev/null @@ -1,206 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -const xcvr_mode_config_t ble_mode_config = -{ - .radio_mode = BLE_MODE, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = RW0PS(0, 0x19) | - RW0PS(1, 0x19U) | - RW0PS(2, 0x1AU) | - RW0PS(3, 0x1BU) | - RW0PS(4, 0x1CU) | - RW0PS(5, 0x1CU) | - RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ - .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ - RW1PS(7, 0x1EU) | - RW1PS(8, 0x1EU) | - RW1PS(9, 0x1EU) | - RW1PS(10, 0x1DU) | - RW1PS(11, 0x1CU) | - RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ - .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ - RW2PS(13, 0x1BU) | - RW2PS(14, 0x1AU) | - RW2PS(15, 0x19U), - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(220) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = -{ - .radio_mode = BLE_MODE, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), - - /* BLE 26MHz Channel Filter */ - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, - - /* BLE 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c deleted file mode 100644 index bd975a21680b..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c +++ /dev/null @@ -1,416 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x7BCDEB39, - .phy_pre_ref1_init = 0xCEF7DEF7, - .phy_pre_ref2_init = 0x0000CEB7, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xda) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */ - (164U) << 7 | /* coeff 6/9 */ - (125U) << 16 | /* coef 3/12 */ - (169U) << 23, /* coeff 7/8 */ - .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */ - (90U) << 8 | /* coeff 1/14 */ - (141U) << 16 | /* coeff 4/11 */ - (155U) << 24, /* coeff 5/10 */ - .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */ - (216U) << 7 | /* coeff 6/9 */ - (105U) << 16 | /* coef 3/12 */ - (233U) << 23, /* coeff 7/8 */ - .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */ - (44U) << 8 | /* coeff 1/14 */ - (145U) << 16 | /* coeff 4/11 */ - (184U) << 24, /* coeff 5/10 */ -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = -{ - .radio_mode = GFSK_BT_0p3_h_0p5, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1), - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c deleted file mode 100644 index 7f00f1e6f920..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c +++ /dev/null @@ -1,402 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0xBBDE739B, - .phy_pre_ref1_init = 0xDEFBDEF7, - .phy_pre_ref2_init = 0x0000E739, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xF0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p32, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c deleted file mode 100644 index 8b7d7cb01c3c..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c +++ /dev/null @@ -1,421 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - .phy_pre_ref0_init = RW0PS(0, 0x19) | - RW0PS(1, 0x19U) | - RW0PS(2, 0x1AU) | - RW0PS(3, 0x1BU) | - RW0PS(4, 0x1CU) | - RW0PS(5, 0x1CU) | - RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ - .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ - RW1PS(7, 0x1EU) | - RW1PS(8, 0x1EU) | - RW1PS(9, 0x1EU) | - RW1PS(10, 0x1DU) | - RW1PS(11, 0x1CU) | - RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ - .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ - RW2PS(13, 0x1BU) | - RW2PS(14, 0x1AU) | - RW2PS(15, 0x19U), - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(205) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* BLE 26MHz Channel Filter */ - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, - - /* BLE 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, - - /* 32MHz */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p5, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c deleted file mode 100644 index 6ba9e7d59158..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c +++ /dev/null @@ -1,403 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x37ACE2F7, - .phy_pre_ref1_init = 0xADF3BDEF, - .phy_pre_ref2_init = 0x0000BE33, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xCD) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_0p7, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c deleted file mode 100644 index 74f404ce8499..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c +++ /dev/null @@ -1,403 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0xF38B5273, - .phy_pre_ref1_init = 0x8CEF9CE6, - .phy_pre_ref2_init = 0x00009D2D, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xb0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = -{ - .radio_mode = GFSK_BT_0p5_h_1p0, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c deleted file mode 100644 index 1977c6311c20..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c +++ /dev/null @@ -1,417 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x79CDEB39, - .phy_pre_ref1_init = 0xCE77DEF7, - .phy_pre_ref2_init = 0x0000CEB7, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(0xb0) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */ - (276U) << 7 | /* Coeff 6/9 */ - (62U) << 16 | /* Coef 3/12 */ - (326U) << 23, /* Coeff 7/8 */ - .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */ - (10U) << 8 | /* Coeff 1/14 */ - (121U) << 16 | /* Coeff 4/11 */ - (198U) << 24, /* Coeff 5/10 */ - .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */ - (330U) << 7 | /* Coeff 6/9 */ - (7U) << 16 | /* Coef 3/12 */ - (510U) << 23, /* Coeff 7/8 */ - .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */ - (0U) << 8 | /* Coeff 1/14 */ - (37U) << 16 | /* Coeff 4/11 */ - (138U) << 24, /* Coeff 5/10 */ -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ - -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ - -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = -{ - .radio_mode = GFSK_BT_0p7_h_0p5, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, - - /* 32MHz Channel Filter */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c deleted file mode 100644 index 17baa297064d..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_msk_config.c +++ /dev/null @@ -1,406 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/* MODE only configuration */ -const xcvr_mode_config_t msk_mode_config = -{ - .radio_mode = MSK, - .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, - - /* XCVR_MISC configs */ - .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, - .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) | - XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) | - XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), - - /* XCVR_PHY configs */ - .phy_pre_ref0_init = 0x79CDEB38, - .phy_pre_ref1_init = 0xCE77DFF7, - .phy_pre_ref2_init = 0x0000CEB7, - - .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | - XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | - XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | - XCVR_PHY_CFG1_BSM_EN_BLE(0) | - XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | - XCVR_PHY_CFG1_CTS_THRESH(208U) | - XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), - - .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) -#if !RADIO_IS_GEN_2P1 - | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) -#endif /* !RADIO_IS_GEN_2P1 */ - , - - /* XCVR_RX_DIG configs */ - .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), - - .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ - -#if RADIO_IS_GEN_2P0 - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), -#else - .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0x05), -#endif - - /* XCVR_TSM configs */ -#if (DATA_PADDING_EN) - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), -#else - .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), -#endif /* (DATA_PADDING_EN) */ - - /* XCVR_TX_DIG configs */ - .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | - XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | - XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), - .tx_gfsk_coeff1_26mhz = 0, - .tx_gfsk_coeff2_26mhz = 0, - .tx_gfsk_coeff1_32mhz = 0, - .tx_gfsk_coeff2_32mhz = 0, -}; - -/* MODE & DATA RATE combined configuration */ -const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = -{ - .radio_mode = MSK, - .data_rate = DR_1MBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(16), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - /* MSK 1MBPS channel filter @ 26MHz RF OSC */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, - - /* MSK 1MBPS channel filter @ 32MHz RF OSC */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = -{ - .radio_mode = MSK, - .data_rate = DR_500KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(24), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - /* MSK 500KBPS channel filter @ 26MHz RF OSC */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, - - /* MSK 500KBPS channel filter @ 32MHz RF OSC */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; - -const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = -{ - .radio_mode = MSK, - .data_rate = DR_250KBPS, - - .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, - .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ - .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, - .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ - .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, - .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ - - .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | - XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , - - /* AGC configs */ -#if RADIO_IS_GEN_2P1 - .agc_ctrl_0_init_26mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), - .agc_ctrl_0_init_32mhz = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | - XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(0), -#endif - - .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | -#if RADIO_IS_GEN_2P0 - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), -#else - XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | - XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | - XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(48), -#endif - - /* All constant values are represented as 16 bits, register writes will remove unused bits */ - .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, - .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, - .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, - .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, - .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, - .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, - .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, - .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, - .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, - .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, - .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, - - /* MSK 250KBPS channel filter @ 32MHz RF OSC */ - .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, - .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, - .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, - .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, - .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, - .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, - .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, - .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, - .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, - .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, - .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, - .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, - - .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , - .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | - XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , - - .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), - .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), -}; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index c1e82deb071d..3561b7ad2442 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -39,21 +39,17 @@ #include #include +#define ENABLE_DEBUG (1) +#include "debug.h" + /******************************************************************************* * Definitions ******************************************************************************/ - -#ifndef MIN -#define MIN(a,b) \ - ({ __typeof__ (a) _a = (a); \ - __typeof__ (b) _b = (b); \ - _a < _b ? _a : _b; }) -#endif +#define DCOC_DAC_BBF_STEP (16) /******************************************************************************* * Prototypes ******************************************************************************/ -void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val); float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ); extern float roundf (float); @@ -62,40 +58,19 @@ extern float roundf (float); ******************************************************************************/ const int8_t TsettleCal = 10; static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; -static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = -{ - 0, /* Baseline entry is first and not used in this table */ - -16, - +16, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - -4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4, - +4 -}; /******************************************************************************* * Macros ******************************************************************************/ #define ISIGN(x) !((uint16_t)x & 0x8000) #define ABS(x) ((x) > 0 ? (x) : -(x)) +#ifndef MIN +#define MIN(a,b) \ + ({ __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a < _b ? _a : _b; }) +#endif + /******************************************************************************* * Code @@ -125,6 +100,17 @@ float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2 return (float)dc_step / (1 << 16); } +float calc_dcoc_dac_step2(int16_t meas, int16_t baseline) +{ + /* Normalize internal measurement */ + int16_t norm_dc_code = meas - baseline; + int32_t dc_step = ((int32_t)norm_dc_code << 16) / DCOC_DAC_BBF_STEP; + if (dc_step < 0) { + dc_step = -dc_step; + } + return (float)dc_step / (1 << 16); +} + /*! ********************************************************************************* * \brief Temporary delay function * @@ -143,6 +129,18 @@ void XcvrCalDelay(uint32_t time) } } +void dump_measurement_tbl2(void) +{ + DEBUG("dump_measurement_tbl2:\n"); + for (unsigned chan = 0; chan < NUM_I_Q_CHAN; ++chan) { + for (unsigned step = 0; step < NUM_SWEEP_STEP_ENTRIES2; ++step) { + const GAIN_CALC_TBL_ENTRY2_T *ptr = &measurement_tbl2[chan][step]; + DEBUG("[%u][%u] %6d, %4d\n", chan, step, ptr->internal_measurement, ptr->step_value); + } + } + DEBUG("end of dump\n"); +} + /*! ********************************************************************************* * rx_dc_est_average : Get DC EST values and return the Average ***********************************************************************************/ @@ -189,7 +187,6 @@ void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg) ***********************************************************************************/ uint8_t rx_bba_dcoc_dac_trim_DCest(void) { - uint8_t i; float temp_mi = 0; float temp_mq = 0; float temp_pi = 0; @@ -201,25 +198,14 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) TZAdcocstep_t tza_dcoc_step[11]; uint8_t status = 0; - uint8_t bbf_dacinit_i, bbf_dacinit_q; - uint8_t tza_dacinit_i, tza_dacinit_q; - int16_t dc_meas_i; - int16_t dc_meas_q; - uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */ uint32_t temp; - uint32_t dcoc_ctrl_0_stack; - uint32_t dcoc_ctrl_1_stack; - uint32_t agc_ctrl_1_stack; - uint32_t rx_dig_ctrl_stack; - uint32_t dcoc_cal_gain_state; - /* Save register */ - dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ - dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ - rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ - agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ - dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + uint32_t dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + uint32_t dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + uint32_t rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + uint32_t agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + uint32_t dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ /* Register config */ /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ @@ -250,126 +236,79 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XcvrCalDelay(TsettleCal); /* Set default DCOC DAC INIT Value */ - dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ - bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); - bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; - tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; - tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; - + uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ + uint8_t bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + uint8_t bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; + uint8_t tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; + uint8_t tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; + + int16_t dc_meas_i_nominal = 0; + int16_t dc_meas_q_nominal = 0; XcvrCalDelay(TsettleCal * 4); - rx_dc_est_average(&dc_meas_i, &dc_meas_q); - measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; - measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; - measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i; - measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q; + rx_dc_est_average(&dc_meas_i_nominal, &dc_meas_q_nominal); /* SWEEP I/Q CHANNEL */ + int16_t dc_meas_i = 0; + int16_t dc_meas_q = 0; /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) | + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - DCOC_DAC_BBF_STEP) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - DCOC_DAC_BBF_STEP) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); rx_dc_est_average(&dc_meas_i, &dc_meas_q); - measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16; - measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16; - measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i; - measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q; + temp_mi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); + temp_mq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) | + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + DCOC_DAC_BBF_STEP) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + DCOC_DAC_BBF_STEP) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); rx_dc_est_average(&dc_meas_i, &dc_meas_q); - measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16; - measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16; - measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i; - measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q; + temp_pi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); + temp_pq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ /* Calculate BBF DCOC STEPS, RECIPROCALS */ - temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); - temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); - temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); - printf("temp_mi = %f\n", temp_mi); - printf("temp_mq = %f\n", temp_mq); - printf("temp_pi = %f\n", temp_pi); - printf("temp_pq = %f\n", temp_pq); - printf("temp_step = %f\n", temp_step); - printf("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); + DEBUG("temp_mi = %f\n", temp_mi); + DEBUG("temp_mq = %f\n", temp_mq); + DEBUG("temp_pi = %f\n", temp_pi); + DEBUG("temp_pq = %f\n", temp_pq); + DEBUG("temp_step = %f\n", temp_step); + DEBUG("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) { bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); - printf("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); + DEBUG("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ - for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) + temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + DEBUG("temp_step0 = %f\n", temp_step); + tza_dcoc_step[0].dcoc_step = (uint32_t)roundf(temp_step * 8); + DEBUG("tza_dcoc_step[0].dcoc_step = %u\n", (unsigned)tza_dcoc_step[0].dcoc_step); + tza_dcoc_step[0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + DEBUG("tza_dcoc_step[0].dcoc_step_rcp = %u\n", (unsigned)tza_dcoc_step[0].dcoc_step_rcp); + const uint32_t *dcoc_tza_step_ptr = &xcvr_common_config.dcoc_tza_step_00_init; + temp_step /= (dcoc_tza_step_ptr[0] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); + for (unsigned k = 1; k < 11; ++k) { + float scratch = temp_step * + (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); + DEBUG("temp_step%u = %f\n", k, scratch); /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ - switch(i){ - case TZA_STEP_N0: - temp_step = (bbf_dcoc_step >> 3U) / 3.6F; - printf("temp_step0 = %f\n", temp_step); - break; - case TZA_STEP_N1: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16); - printf("temp_step1 = %f\n", temp_step); - break; - case TZA_STEP_N2: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16); - printf("temp_step2 = %f\n", temp_step); - break; - case TZA_STEP_N3: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16); - printf("temp_step3 = %f\n", temp_step); - break; - case TZA_STEP_N4: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16); - printf("temp_step4 = %f\n", temp_step); - break; - case TZA_STEP_N5: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16); - printf("temp_step5 = %f\n", temp_step); - break; - case TZA_STEP_N6: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16); - printf("temp_step6 = %f\n", temp_step); - break; - case TZA_STEP_N7: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16); - printf("temp_step7 = %f\n", temp_step); - break; - case TZA_STEP_N8: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16); - printf("temp_step8 = %f\n", temp_step); - break; - case TZA_STEP_N9: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16); - printf("temp_step9 = %f\n", temp_step); - break; - case TZA_STEP_N10: - temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16); - printf("temp_step10 = %f\n", temp_step); - break; - default: - break; - } - - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); - printf("tza_dcoc_step[%u].dcoc_step = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step); - tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); - printf("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", i-TZA_STEP_N0, (unsigned)tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp); + tza_dcoc_step[k].dcoc_step = (uint32_t)roundf(scratch * 8); + DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step); + tza_dcoc_step[k].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / scratch); + DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step_rcp); } /* Make the trims active */ @@ -391,7 +330,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) } else { - printf("!!! XCVR trim failed: bbf_dcoc_step = %"PRIu32"!\n", bbf_dcoc_step); + DEBUG("!!! XCVR trim failed: bbf_dcoc_step = %"PRIu32"!\n", bbf_dcoc_step); status = 0; /* Failure */ } @@ -402,7 +341,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ - return status; + return status; } /*! ********************************************************************************* From 61e5bc0c3d645ddf29fc89d583ebf40f04253194 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 29 Oct 2018 16:00:05 +0100 Subject: [PATCH 45/82] squash kw41zrf add back handle_ifr --- drivers/kw41zrf/kw41zrf.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 688904371593..caf68c512854 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -29,6 +29,7 @@ #include "kw41zrf_getset.h" #include "kw41zrf_intern.h" #include "vendor/XCVR/MKW41Z4/fsl_xcvr.h" +#include "vendor/XCVR/MKW41Z4/ifr_radio.h" #include "periph/timer.h" #define ENABLE_DEBUG (0) @@ -99,6 +100,27 @@ static int kw41zrf_xcvr_init(kw41zrf_t *dev) RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ bit_set32(&SIM->SCGC5, SIM_SCGC5_PHYDIG_SHIFT); /* Enable PHY clock gate */ + /* Load IFR trim values */ + IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = + { + {TRIM_STATUS, 0, 0}, /*< Fetch the trim status word if available.*/ + {TRIM_VERSION, 0, 0} /*< Fetch the trim version number if available.*/ + }; + handle_ifr(&sw_trim_tbl[0], sizeof(sw_trim_tbl) / sizeof(sw_trim_tbl[0])); + DEBUG("[kw41zrf] sw_trim_tbl:\n"); + + for (unsigned k = 0; k < sizeof(sw_trim_tbl) / sizeof(sw_trim_tbl[0]); ++k) { + DEBUG("[kw41zrf] [%u] id=0x%04x ", k, (unsigned)sw_trim_tbl[k].trim_id); + if (sw_trim_tbl[k].trim_id == TRIM_STATUS) { + DEBUG("(TRIM_STATUS) "); + } + else if (sw_trim_tbl[k].trim_id == TRIM_VERSION) { + DEBUG("(TRIM_VERSION) "); + } + DEBUG("value=%" PRIu32 ", valid=%u\n", sw_trim_tbl[k].trim_value, + (unsigned)sw_trim_tbl[k].valid); + } + /* We only use 802.15.4 mode in this driver */ xcvrStatus_t status = XCVR_Configure(&xcvr_common_config, &zgbe_mode_config, &xcvr_ZIGBEE_500kbps_config, &xcvr_802_15_4_500kbps_config, 25, XCVR_FIRST_INIT); From 89bd80391364006b39adc3451dccc305af78c760 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 29 Oct 2018 16:00:29 +0100 Subject: [PATCH 46/82] squash kw41zrf WIP eliminate float --- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 123 ++++++++---------- 1 file changed, 54 insertions(+), 69 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index 3561b7ad2442..0f4751904867 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -50,14 +50,11 @@ /******************************************************************************* * Prototypes ******************************************************************************/ -float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ); -extern float roundf (float); /******************************************************************************* * Variables ******************************************************************************/ const int8_t TsettleCal = 10; -static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; /******************************************************************************* * Macros @@ -82,33 +79,26 @@ static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTR * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. * - * \return Q15.16 result of the calculation, the measurement DCOC DAC step value for this measurement point. + * \return Q16 result of the calculation, the measurement DCOC DAC step value for this measurement point. * ***********************************************************************************/ -float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) +uint32_t calc_dcoc_dac_step2(int16_t meas, int16_t baseline) { - int32_t norm_dc_code; - float dc_step; - /* Normalize internal measurement */ - norm_dc_code = (int32_t)meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; - dc_step = (norm_dc_code << 16) / meas_ptr->step_value; + int16_t norm_dc_code = meas - baseline; + int32_t dc_step = ((int32_t)norm_dc_code << 16) / DCOC_DAC_BBF_STEP; if (dc_step < 0) { dc_step = -dc_step; } - - return (float)dc_step / (1 << 16); + return dc_step; } -float calc_dcoc_dac_step2(int16_t meas, int16_t baseline) +void calc_tza_step_rcp_reg(TZAdcocstep_t *out, uint32_t base_step, uint16_t gain, uint16_t gain0) { - /* Normalize internal measurement */ - int16_t norm_dc_code = meas - baseline; - int32_t dc_step = ((int32_t)norm_dc_code << 16) / DCOC_DAC_BBF_STEP; - if (dc_step < 0) { - dc_step = -dc_step; - } - return (float)dc_step / (1 << 16); + uint32_t step = (base_step * gain + (gain0 >> 1)) / gain0; + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ + out->dcoc_step = (step + (1u << 12)) >> 13; + out->dcoc_step_rcp = (0x80000000ul + (step >> 1)) / step; } /*! ********************************************************************************* @@ -129,18 +119,6 @@ void XcvrCalDelay(uint32_t time) } } -void dump_measurement_tbl2(void) -{ - DEBUG("dump_measurement_tbl2:\n"); - for (unsigned chan = 0; chan < NUM_I_Q_CHAN; ++chan) { - for (unsigned step = 0; step < NUM_SWEEP_STEP_ENTRIES2; ++step) { - const GAIN_CALC_TBL_ENTRY2_T *ptr = &measurement_tbl2[chan][step]; - DEBUG("[%u][%u] %6d, %4d\n", chan, step, ptr->internal_measurement, ptr->step_value); - } - } - DEBUG("end of dump\n"); -} - /*! ********************************************************************************* * rx_dc_est_average : Get DC EST values and return the Average ***********************************************************************************/ @@ -159,11 +137,11 @@ void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg) { uint32_t dc_temp = XCVR_RX_DIG->DCOC_DC_EST; int16_t dc_meas_i = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT; - dc_meas_i |= ((dc_meas_i & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_i = (int16_t)(dc_meas_i << 4) / 16; /* Sign extend from 12 to 16 bits. */ avg_i += dc_meas_i; int16_t dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; - dc_meas_q |= ((dc_meas_q & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_q = (int16_t)(dc_meas_q << 4) / 16; /* Sign extend from 12 to 16 bits. */ avg_q += dc_meas_q; } @@ -187,14 +165,6 @@ void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg) ***********************************************************************************/ uint8_t rx_bba_dcoc_dac_trim_DCest(void) { - float temp_mi = 0; - float temp_mq = 0; - float temp_pi = 0; - float temp_pq = 0; - float temp_step = 0; - - uint32_t bbf_dcoc_step; - uint32_t bbf_dcoc_step_rcp; TZAdcocstep_t tza_dcoc_step[11]; uint8_t status = 0; @@ -238,8 +208,8 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) /* Set default DCOC DAC INIT Value */ uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ uint8_t bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); - uint8_t bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; - uint8_t tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; + uint8_t bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; + uint8_t tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U) >> 16; uint8_t tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; int16_t dc_meas_i_nominal = 0; @@ -255,11 +225,11 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - DCOC_DAC_BBF_STEP) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 2); + XcvrCalDelay(TsettleCal * 4); rx_dc_est_average(&dc_meas_i, &dc_meas_q); - temp_mi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); - temp_mq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); + uint32_t temp_mi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); + uint32_t temp_mq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); /* BBF POS STEP */ @@ -269,52 +239,67 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); rx_dc_est_average(&dc_meas_i, &dc_meas_q); - temp_pi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); - temp_pq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); + uint32_t temp_pi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); + uint32_t temp_pq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ /* Calculate BBF DCOC STEPS, RECIPROCALS */ - temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; - bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); - - DEBUG("temp_mi = %f\n", temp_mi); - DEBUG("temp_mq = %f\n", temp_mq); - DEBUG("temp_pi = %f\n", temp_pi); - DEBUG("temp_pq = %f\n", temp_pq); - DEBUG("temp_step = %f\n", temp_step); + /* calc_dcoc_dac_step2 divides by 16 internally, no risk of overflow, temp_xy < (1 << 28) */ + uint32_t meas_sum = (temp_mi + temp_pi + temp_mq + temp_pq); + float temp_step = ((float)meas_sum / 4) / (1 << 16); + /* rounded result, (temp_step * 8) == (meas_sum * 2) */ + uint32_t bbf_dcoc_step = (meas_sum + (1u << 14)) >> 15; + + DEBUG("temp_mi = %f\n", (float)temp_mi / (1 << 16)); + DEBUG("temp_mq = %f\n", (float)temp_mq / (1 << 16)); + DEBUG("temp_pi = %f\n", (float)temp_pi / (1 << 16)); + DEBUG("temp_pq = %f\n", (float)temp_pq / (1 << 16)); + DEBUG("temp_step = %f\n", (float)temp_step); DEBUG("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) { - bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + /* rounded result, (0x8000 / temp_step) */ + uint32_t bbf_dcoc_step_rcp = (0x80000000ul + (meas_sum >> 3)) / (meas_sum >> 2); DEBUG("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ - temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + /* (bbf_dcoc_step >> 3U) / 3.6F */ + uint32_t base_step = (((bbf_dcoc_step * 5u) << 13) / 18u); + temp_step = (float)base_step / (1u << 16); DEBUG("temp_step0 = %f\n", temp_step); - tza_dcoc_step[0].dcoc_step = (uint32_t)roundf(temp_step * 8); + /* rounded result, (temp_step * 8) */ + tza_dcoc_step[0].dcoc_step = (base_step + (1u << 12)) >> 13; DEBUG("tza_dcoc_step[0].dcoc_step = %u\n", (unsigned)tza_dcoc_step[0].dcoc_step); - tza_dcoc_step[0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + /* rounded result, (0x8000 / temp_step) */ + tza_dcoc_step[0].dcoc_step_rcp = (0x80000000ul + (base_step >> 1)) / base_step; DEBUG("tza_dcoc_step[0].dcoc_step_rcp = %u\n", (unsigned)tza_dcoc_step[0].dcoc_step_rcp); const uint32_t *dcoc_tza_step_ptr = &xcvr_common_config.dcoc_tza_step_00_init; - temp_step /= (dcoc_tza_step_ptr[0] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); + uint16_t gain0 = (dcoc_tza_step_ptr[0] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); + temp_step /= gain0; + DEBUG("base step = %" PRIx32 " %f\n", base_step, temp_step); for (unsigned k = 1; k < 11; ++k) { - float scratch = temp_step * - (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); - DEBUG("temp_step%u = %f\n", k, scratch); + uint16_t gain = (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); + calc_tza_step_rcp_reg(&tza_dcoc_step[k], base_step, gain, gain0); + //~ uint32_t step = (base_step * gain); + //~ DEBUG("[%u] gain=%u, step=%"PRIu32"\n", k, (unsigned)gain, step); + //~ step /= gain0; + //~ float scratch = temp_step * + //~ (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); + //~ DEBUG("temp_step%u = %f\n", k, scratch); /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ - tza_dcoc_step[k].dcoc_step = (uint32_t)roundf(scratch * 8); + //~ tza_dcoc_step[k].dcoc_step = (step + (1u << 12)) >> 13; DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step); - tza_dcoc_step[k].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / scratch); + //~ tza_dcoc_step[k].dcoc_step_rcp = (0x80000000ul + (step >> 1)) / step; DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step_rcp); } /* Make the trims active */ XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step*10) | - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp/10) ; + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); From 4ec4d5d5f1dbba310ba5dc0c34cd059e2a5e7413 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 09:02:31 +0100 Subject: [PATCH 47/82] squash kw41zrf split xcvr stuff into separate file --- drivers/kw41zrf/kw41zrf.c | 65 +--------------------------- drivers/kw41zrf/kw41zrf_xcvr.c | 78 ++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 63 deletions(-) create mode 100644 drivers/kw41zrf/kw41zrf_xcvr.c diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index caf68c512854..e12f5c601a9a 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -17,6 +17,7 @@ */ #include #include +#include #include "log.h" #include "msg.h" @@ -35,22 +36,6 @@ #define ENABLE_DEBUG (0) #include "debug.h" -enum { - KW41Z_CCA_ED, - KW41Z_CCA_MODE1, - KW41Z_CCA_MODE2, - KW41Z_CCA_MODE3 -}; - -enum { - KW41Z_STATE_IDLE, - KW41Z_STATE_RX, - KW41Z_STATE_TX, - KW41Z_STATE_CCA, - KW41Z_STATE_TXRX, - KW41Z_STATE_CCCA -}; - static void kw41zrf_set_address(kw41zrf_t *dev) { DEBUG("[kw41zrf] Set MAC address\n"); @@ -83,53 +68,7 @@ void kw41zrf_setup(kw41zrf_t *dev) DEBUG("[kw41zrf] setup finished\n"); } -static int kw41zrf_xcvr_init(kw41zrf_t *dev) -{ - (void) dev; - uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK) >> RSIM_MISC_RADIO_VERSION_SHIFT); - switch (radio_id) { - case 0x3: /* KW41/31/21 v1 */ - case 0xb: /* KW41/31/21 v1.1 */ - break; - default: - return -ENODEV; - } - - RSIM->RF_OSC_CTRL = (RSIM->RF_OSC_CTRL & - ~(RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)) | /* Set EXT_OSC_OVRD value to zero */ - RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ - bit_set32(&SIM->SCGC5, SIM_SCGC5_PHYDIG_SHIFT); /* Enable PHY clock gate */ - - /* Load IFR trim values */ - IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = - { - {TRIM_STATUS, 0, 0}, /*< Fetch the trim status word if available.*/ - {TRIM_VERSION, 0, 0} /*< Fetch the trim version number if available.*/ - }; - handle_ifr(&sw_trim_tbl[0], sizeof(sw_trim_tbl) / sizeof(sw_trim_tbl[0])); - DEBUG("[kw41zrf] sw_trim_tbl:\n"); - - for (unsigned k = 0; k < sizeof(sw_trim_tbl) / sizeof(sw_trim_tbl[0]); ++k) { - DEBUG("[kw41zrf] [%u] id=0x%04x ", k, (unsigned)sw_trim_tbl[k].trim_id); - if (sw_trim_tbl[k].trim_id == TRIM_STATUS) { - DEBUG("(TRIM_STATUS) "); - } - else if (sw_trim_tbl[k].trim_id == TRIM_VERSION) { - DEBUG("(TRIM_VERSION) "); - } - DEBUG("value=%" PRIu32 ", valid=%u\n", sw_trim_tbl[k].trim_value, - (unsigned)sw_trim_tbl[k].valid); - } - - /* We only use 802.15.4 mode in this driver */ - xcvrStatus_t status = XCVR_Configure(&xcvr_common_config, &zgbe_mode_config, - &xcvr_ZIGBEE_500kbps_config, &xcvr_802_15_4_500kbps_config, 25, XCVR_FIRST_INIT); - - if (status != gXcvrSuccess_c) { - return -EIO; - } - return 0; -} +int kw41zrf_xcvr_init(kw41zrf_t *dev); int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) { diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c new file mode 100644 index 000000000000..2f2736ea5be3 --- /dev/null +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2018 SKF AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_kw41zrf + * @{ + * @file + * @brief NXP KW41Z XCVR module initialization and calibration of kw41zrf driver + * + * @author Joakim Nohlgård + * @} + */ +#include +#include +#include + +#include "log.h" + +#include "kw41zrf.h" +#include "bit.h" +#include "vendor/XCVR/MKW41Z4/fsl_xcvr.h" +#include "vendor/XCVR/MKW41Z4/ifr_radio.h" + +#define ENABLE_DEBUG (1) +#include "debug.h" + +int kw41zrf_xcvr_init(kw41zrf_t *dev) +{ + (void) dev; + uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK) >> RSIM_MISC_RADIO_VERSION_SHIFT); + switch (radio_id) { + case 0x3: /* KW41/31/21 v1 */ + case 0xb: /* KW41/31/21 v1.1 */ + break; + default: + return -ENODEV; + } + + RSIM->RF_OSC_CTRL = (RSIM->RF_OSC_CTRL & + ~(RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)) | /* Set EXT_OSC_OVRD value to zero */ + RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ + bit_set32(&SIM->SCGC5, SIM_SCGC5_PHYDIG_SHIFT); /* Enable PHY clock gate */ + + /* Load IFR trim values */ + IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = + { + {TRIM_STATUS, 0, 0}, /*< Fetch the trim status word if available.*/ + {TRIM_VERSION, 0, 0} /*< Fetch the trim version number if available.*/ + }; + handle_ifr(&sw_trim_tbl[0], sizeof(sw_trim_tbl) / sizeof(sw_trim_tbl[0])); + DEBUG("[kw41zrf] sw_trim_tbl:\n"); + + for (unsigned k = 0; k < sizeof(sw_trim_tbl) / sizeof(sw_trim_tbl[0]); ++k) { + DEBUG("[kw41zrf] [%u] id=0x%04x ", k, (unsigned)sw_trim_tbl[k].trim_id); + if (sw_trim_tbl[k].trim_id == TRIM_STATUS) { + DEBUG("(TRIM_STATUS) "); + } + else if (sw_trim_tbl[k].trim_id == TRIM_VERSION) { + DEBUG("(TRIM_VERSION) "); + } + DEBUG("value=%" PRIu32 ", valid=%u\n", sw_trim_tbl[k].trim_value, + (unsigned)sw_trim_tbl[k].valid); + } + + /* We only use 802.15.4 mode in this driver */ + xcvrStatus_t status = XCVR_Configure(&xcvr_common_config, &zgbe_mode_config, + &xcvr_ZIGBEE_500kbps_config, &xcvr_802_15_4_500kbps_config, 25, XCVR_FIRST_INIT); + + if (status != gXcvrSuccess_c) { + return -EIO; + } + return 0; +} From 8faf15ef3244e6d50017faf524e9866009c75602 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 09:03:00 +0100 Subject: [PATCH 48/82] squash kw41zrf clean up xcvr trim --- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 141 +++++++++--------- 1 file changed, 74 insertions(+), 67 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index 0f4751904867..c2fc5d0806f4 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -73,23 +73,15 @@ const int8_t TsettleCal = 10; * Code ******************************************************************************/ -/*! ********************************************************************************* - * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. - * - * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. - * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. - * - * \return Q16 result of the calculation, the measurement DCOC DAC step value for this measurement point. - * - ***********************************************************************************/ -uint32_t calc_dcoc_dac_step2(int16_t meas, int16_t baseline) +static uint32_t calc_dcoc_dac_slope(int16_t lower, int16_t upper) { /* Normalize internal measurement */ - int16_t norm_dc_code = meas - baseline; - int32_t dc_step = ((int32_t)norm_dc_code << 16) / DCOC_DAC_BBF_STEP; - if (dc_step < 0) { - dc_step = -dc_step; + int16_t norm_dc_code = upper - lower; + if (norm_dc_code < 0) { + norm_dc_code = -norm_dc_code; } + uint32_t dc_step = ((uint32_t)norm_dc_code << 16) / DCOC_DAC_BBF_STEP; + printf("slope: %d, %d -> %f\n", (int) lower, (int)upper, (float)dc_step / (1 << 16)); return dc_step; } @@ -113,7 +105,8 @@ void calc_tza_step_rcp_reg(TZAdcocstep_t *out, uint32_t base_step, uint16_t gain ***********************************************************************************/ void XcvrCalDelay(uint32_t time) { - while(time * 32 > 0) /* Time delay is roughly in uSec. */ + time *= 32; /* Time delay is roughly in uSec. */ + while(time > 0) { time--; } @@ -165,11 +158,10 @@ void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg) ***********************************************************************************/ uint8_t rx_bba_dcoc_dac_trim_DCest(void) { + /* Estimate the actual gain by measuring three points and approximating a line */ TZAdcocstep_t tza_dcoc_step[11]; uint8_t status = 0; - uint32_t temp; - /* Save register */ uint32_t dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ uint32_t dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ @@ -179,11 +171,10 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) /* Register config */ /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ - temp = XCVR_RX_DIG->RX_DIG_CTRL; - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ - XCVR_RX_DIG->RX_DIG_CTRL = temp; + XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG->RX_DIG_CTRL & + ~(XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK | /* Turn OFF AGC */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK | /* Disable for SW control of DCOC */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK); /* Disable for SW control of DCOC */ XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ @@ -191,30 +182,32 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ - temp = XCVR_RX_DIG->DCOC_CTRL_0; - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ - XCVR_RX_DIG->DCOC_CTRL_0 = temp; - - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); - - XcvrCalDelay(TsettleCal); + XCVR_RX_DIG->DCOC_CTRL_0 = XCVR_RX_DIG->DCOC_CTRL_0 | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1) | /* Enable Manual DCOC */ + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1) | /* Ensure DCOC Tracking is enabled */ + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1) | /* Enable DC Estimator */ + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + + /* Use reset defaults */ + uint8_t bbf_dacinit_i = 0x20; + uint8_t bbf_dacinit_q = 0x20; + uint8_t tza_dacinit_i = 0x80; + uint8_t tza_dacinit_q = 0x80; /* Set default DCOC DAC INIT Value */ - uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ - uint8_t bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); - uint8_t bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; - uint8_t tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U) >> 16; - uint8_t tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; + XCVR_RX_DIG->DCOC_DAC_INIT = + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + /* Store DCOC_DAC_INIT value */ + uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; + + XcvrCalDelay(TsettleCal * 2); int16_t dc_meas_i_nominal = 0; int16_t dc_meas_q_nominal = 0; - XcvrCalDelay(TsettleCal * 4); + /* TODO: remove this since it cancels out in the calculations below */ rx_dc_est_average(&dc_meas_i_nominal, &dc_meas_q_nominal); /* SWEEP I/Q CHANNEL */ @@ -228,9 +221,8 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XcvrCalDelay(TsettleCal * 4); rx_dc_est_average(&dc_meas_i, &dc_meas_q); - uint32_t temp_mi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); - uint32_t temp_mq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); - + uint32_t temp_mi = calc_dcoc_dac_slope(dc_meas_i, dc_meas_i_nominal); + uint32_t temp_mq = calc_dcoc_dac_slope(dc_meas_q, dc_meas_q_nominal); /* BBF POS STEP */ XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + DCOC_DAC_BBF_STEP) | @@ -239,8 +231,8 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); rx_dc_est_average(&dc_meas_i, &dc_meas_q); - uint32_t temp_pi = calc_dcoc_dac_step2(dc_meas_i, dc_meas_i_nominal); - uint32_t temp_pq = calc_dcoc_dac_step2(dc_meas_q, dc_meas_q_nominal); + uint32_t temp_pi = calc_dcoc_dac_slope(dc_meas_i_nominal, dc_meas_i); + uint32_t temp_pq = calc_dcoc_dac_slope(dc_meas_q_nominal, dc_meas_q); XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ @@ -284,32 +276,47 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) { uint16_t gain = (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); calc_tza_step_rcp_reg(&tza_dcoc_step[k], base_step, gain, gain0); - //~ uint32_t step = (base_step * gain); - //~ DEBUG("[%u] gain=%u, step=%"PRIu32"\n", k, (unsigned)gain, step); - //~ step /= gain0; - //~ float scratch = temp_step * - //~ (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); - //~ DEBUG("temp_step%u = %f\n", k, scratch); - /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ - //~ tza_dcoc_step[k].dcoc_step = (step + (1u << 12)) >> 13; DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step); - //~ tza_dcoc_step[k].dcoc_step_rcp = (0x80000000ul + (step >> 1)) / step; DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step_rcp); } /* Make the trims active */ - XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_BBA_STEP = + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_0 = + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = + XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_2 = + XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_3 = + XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_4 = + XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_5 = + XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_6 = + XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_7 = + XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_8 = + XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_9 = + XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_10 = + XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); status = 1; /* Success */ } From 5936c3f773f50d8b82748fbf844dec034bd47818 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 11:58:30 +0100 Subject: [PATCH 49/82] squash kw41zrf disable debug --- drivers/kw41zrf/kw41zrf_xcvr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c index 2f2736ea5be3..84a40ef6290a 100644 --- a/drivers/kw41zrf/kw41zrf_xcvr.c +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -26,7 +26,7 @@ #include "vendor/XCVR/MKW41Z4/fsl_xcvr.h" #include "vendor/XCVR/MKW41Z4/ifr_radio.h" -#define ENABLE_DEBUG (1) +#define ENABLE_DEBUG (0) #include "debug.h" int kw41zrf_xcvr_init(kw41zrf_t *dev) From d4fc730bd6be9c580582e0714e24c019aaf686e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 11:58:44 +0100 Subject: [PATCH 50/82] squash kw41zrf slim vendor calibration --- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 163 ++++++++++-------- 1 file changed, 87 insertions(+), 76 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index c2fc5d0806f4..188349681be6 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -39,13 +39,14 @@ #include #include -#define ENABLE_DEBUG (1) +#define ENABLE_DEBUG (0) #include "debug.h" /******************************************************************************* * Definitions ******************************************************************************/ #define DCOC_DAC_BBF_STEP (16) +#define RX_DC_EST_SAMPLES (64) /******************************************************************************* * Prototypes @@ -73,15 +74,15 @@ const int8_t TsettleCal = 10; * Code ******************************************************************************/ -static uint32_t calc_dcoc_dac_slope(int16_t lower, int16_t upper) +static uint32_t calc_dcoc_dac_slope(int32_t lower, int32_t upper) { /* Normalize internal measurement */ - int16_t norm_dc_code = upper - lower; + int32_t norm_dc_code = upper - lower; if (norm_dc_code < 0) { norm_dc_code = -norm_dc_code; } - uint32_t dc_step = ((uint32_t)norm_dc_code << 16) / DCOC_DAC_BBF_STEP; - printf("slope: %d, %d -> %f\n", (int) lower, (int)upper, (float)dc_step / (1 << 16)); + uint32_t dc_step = (uint32_t)norm_dc_code / DCOC_DAC_BBF_STEP; + DEBUG("slope: %d, %d -> %f\n", (int) lower, (int)upper, (float)dc_step / (1 << 16)); return dc_step; } @@ -113,36 +114,39 @@ void XcvrCalDelay(uint32_t time) } /*! ********************************************************************************* - * rx_dc_est_average : Get DC EST values and return the Average + * rx_dc_est_samples : Get nsamples DC EST values and return the sums ***********************************************************************************/ -void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg) +void rx_dc_est_samples(int32_t *i_sum, int32_t *q_sum, unsigned nsamples) { - static const unsigned nsamples = 64; - int32_t avg_i = 0; - int32_t avg_q = 0; - - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ - uint32_t end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + uint32_t end_of_rx_wu = XCVR_CTRL_XCVR_STATUS_TSM_COUNT( + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT); + while ((XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) != end_of_rx_wu) {}; + + int32_t sum_i = 0; + int32_t sum_q = 0; /* Read DCOC DC EST register. */ for (unsigned k = 0; k < nsamples; k++) { uint32_t dc_temp = XCVR_RX_DIG->DCOC_DC_EST; int16_t dc_meas_i = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT; dc_meas_i = (int16_t)(dc_meas_i << 4) / 16; /* Sign extend from 12 to 16 bits. */ - avg_i += dc_meas_i; + sum_i += dc_meas_i; int16_t dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; dc_meas_q = (int16_t)(dc_meas_q << 4) / 16; /* Sign extend from 12 to 16 bits. */ - avg_q += dc_meas_q; + sum_q += dc_meas_q; } - avg_i /= nsamples; - avg_q /= nsamples; + *i_sum = sum_i; + *q_sum = sum_q; +} - *i_avg = (int16_t)avg_i; - *q_avg = (int16_t)avg_q; +/* Unsigned integer division, rounded to nearest integer */ +static inline uint32_t calc_div_rounded(uint32_t num, uint32_t den) +{ + return (num + (den / 2)) / den; } /*! ********************************************************************************* @@ -205,14 +209,14 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XcvrCalDelay(TsettleCal * 2); - int16_t dc_meas_i_nominal = 0; - int16_t dc_meas_q_nominal = 0; + int32_t dc_meas_i_nominal = 0; + int32_t dc_meas_q_nominal = 0; /* TODO: remove this since it cancels out in the calculations below */ - rx_dc_est_average(&dc_meas_i_nominal, &dc_meas_q_nominal); + rx_dc_est_samples(&dc_meas_i_nominal, &dc_meas_q_nominal, RX_DC_EST_SAMPLES); /* SWEEP I/Q CHANNEL */ - int16_t dc_meas_i = 0; - int16_t dc_meas_q = 0; + int32_t dc_meas_i = 0; + int32_t dc_meas_q = 0; /* BBF NEG STEP */ XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - DCOC_DAC_BBF_STEP) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - DCOC_DAC_BBF_STEP) | @@ -220,9 +224,10 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 4); - rx_dc_est_average(&dc_meas_i, &dc_meas_q); - uint32_t temp_mi = calc_dcoc_dac_slope(dc_meas_i, dc_meas_i_nominal); - uint32_t temp_mq = calc_dcoc_dac_slope(dc_meas_q, dc_meas_q_nominal); + rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); + uint32_t meas_sum = 0; + meas_sum += calc_dcoc_dac_slope(dc_meas_i, dc_meas_i_nominal); + meas_sum += calc_dcoc_dac_slope(dc_meas_q, dc_meas_q_nominal); /* BBF POS STEP */ XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + DCOC_DAC_BBF_STEP) | @@ -230,60 +235,62 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q); - uint32_t temp_pi = calc_dcoc_dac_slope(dc_meas_i_nominal, dc_meas_i); - uint32_t temp_pq = calc_dcoc_dac_slope(dc_meas_q_nominal, dc_meas_q); + rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); + meas_sum += calc_dcoc_dac_slope(dc_meas_i_nominal, dc_meas_i); + meas_sum += calc_dcoc_dac_slope(dc_meas_q_nominal, dc_meas_q); XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ - /* Calculate BBF DCOC STEPS, RECIPROCALS */ - /* calc_dcoc_dac_step2 divides by 16 internally, no risk of overflow, temp_xy < (1 << 28) */ - uint32_t meas_sum = (temp_mi + temp_pi + temp_mq + temp_pq); - float temp_step = ((float)meas_sum / 4) / (1 << 16); - /* rounded result, (temp_step * 8) == (meas_sum * 2) */ - uint32_t bbf_dcoc_step = (meas_sum + (1u << 14)) >> 15; + /* Compute the average sampled gain for the measured steps */ - DEBUG("temp_mi = %f\n", (float)temp_mi / (1 << 16)); - DEBUG("temp_mq = %f\n", (float)temp_mq / (1 << 16)); - DEBUG("temp_pi = %f\n", (float)temp_pi / (1 << 16)); - DEBUG("temp_pq = %f\n", (float)temp_pq / (1 << 16)); - DEBUG("temp_step = %f\n", (float)temp_step); - DEBUG("bbf_dcoc_step = %"PRIu32"\n", bbf_dcoc_step); - - - if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + /* meas_sum here is the average gain multiplied by (4 * RX_DC_EST_SAMPLES) */ + /* Compute the gain average as a Q6.3 number */ + /* rounded result, Q6.3 number */ + uint16_t bbf_dcoc_gain_measured = calc_div_rounded(meas_sum, (4 * RX_DC_EST_SAMPLES / (1 << 3))); + + DEBUG("temp_step = %f\n", (float)meas_sum / (4 * RX_DC_EST_SAMPLES)); + DEBUG("bbf_dcoc_gain_measured = %u\n", (unsigned)bbf_dcoc_gain_measured); + + /* Check the measured value for validity. Should be in the range: + * 250 < bbf_dcoc_gain_measured < 305, according to NXP wireless framework v5.4.3 (MCUXpresso KW36 SDK) + */ + if ((250 < bbf_dcoc_gain_measured) & (bbf_dcoc_gain_measured < 305)) { - /* rounded result, (0x8000 / temp_step) */ - uint32_t bbf_dcoc_step_rcp = (0x80000000ul + (meas_sum >> 3)) / (meas_sum >> 2); - DEBUG("bbf_dcoc_step_rcp = %"PRIu32"\n", bbf_dcoc_step_rcp); - - /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ - /* (bbf_dcoc_step >> 3U) / 3.6F */ - uint32_t base_step = (((bbf_dcoc_step * 5u) << 13) / 18u); - temp_step = (float)base_step / (1u << 16); - DEBUG("temp_step0 = %f\n", temp_step); - /* rounded result, (temp_step * 8) */ - tza_dcoc_step[0].dcoc_step = (base_step + (1u << 12)) >> 13; - DEBUG("tza_dcoc_step[0].dcoc_step = %u\n", (unsigned)tza_dcoc_step[0].dcoc_step); - /* rounded result, (0x8000 / temp_step) */ - tza_dcoc_step[0].dcoc_step_rcp = (0x80000000ul + (base_step >> 1)) / base_step; - DEBUG("tza_dcoc_step[0].dcoc_step_rcp = %u\n", (unsigned)tza_dcoc_step[0].dcoc_step_rcp); + /* Compute reciprocal, as Q15 number, but only the 13 lowest bits are programmable */ + /* rounded result, ((2**15) / slope) */ + uint32_t bbf_dcoc_gain_measured_rcp = calc_div_rounded((1u << 15) * (4u * RX_DC_EST_SAMPLES), meas_sum); + DEBUG("bbf_dcoc_gain_measured_rcp = %"PRIu32"\n", bbf_dcoc_gain_measured_rcp); + + uint16_t bbf_dcoc_gain_default = + (xcvr_common_config.dcoc_bba_step_init & + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK) >> + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT; + /* Rescale all default TZA DCOC gains according to the measured BBF gain, + * using (bbf_dcoc_gain_measured / bbf_dcoc_gain_default) as the implicit + * scale factor, but rewrite it to use + * (meas_sum / (bbf_dcoc_gain_default * (4u * RX_DC_EST_SAMPLES / (1u << 3)))) + * for better numeric precision */ + /* rounded result, Q9.3 number */ + bbf_dcoc_gain_default *= (4u * RX_DC_EST_SAMPLES / (1u << 3)); const uint32_t *dcoc_tza_step_ptr = &xcvr_common_config.dcoc_tza_step_00_init; - uint16_t gain0 = (dcoc_tza_step_ptr[0] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); - temp_step /= gain0; - DEBUG("base step = %" PRIx32 " %f\n", base_step, temp_step); - for (unsigned k = 1; k < 11; ++k) + for (unsigned k = 0; k <= 10; ++k) { - uint16_t gain = (dcoc_tza_step_ptr[k] >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT); - calc_tza_step_rcp_reg(&tza_dcoc_step[k], base_step, gain, gain0); + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ + uint16_t tza_gain_default = + (dcoc_tza_step_ptr[k] & + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK) >> + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT; + /* Using meas_sum for higher precision */ + tza_dcoc_step[k].dcoc_step = calc_div_rounded(tza_gain_default * meas_sum, bbf_dcoc_gain_default); + tza_dcoc_step[k].dcoc_step_rcp = calc_div_rounded(0x8000ul * bbf_dcoc_gain_default, tza_gain_default * meas_sum); DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step); DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step_rcp); } - /* Make the trims active */ XCVR_RX_DIG->DCOC_BBA_STEP = - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_gain_measured) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_gain_measured_rcp); XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; @@ -322,7 +329,7 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) } else { - DEBUG("!!! XCVR trim failed: bbf_dcoc_step = %"PRIu32"!\n", bbf_dcoc_step); + DEBUG("!!! XCVR trim failed: bbf_dcoc_step = %u!\n", (unsigned)bbf_dcoc_gain_measured); status = 0; /* Failure */ } @@ -341,8 +348,6 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) ***********************************************************************************/ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) { - int16_t dc_meas_i = 2000, dc_meas_i_p = 2000; - int16_t dc_meas_q = 2000, dc_meas_q_p = 2000; uint8_t curr_tza_dac_i, curr_tza_dac_q; uint8_t curr_bba_dac_i, curr_bba_dac_q; uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0; @@ -416,6 +421,8 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + int32_t dc_meas_i = 2000, dc_meas_i_p = 2000; + int32_t dc_meas_q = 2000, dc_meas_q_p = 2000; do { bba_gain--; @@ -425,7 +432,9 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q); + rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); + dc_meas_i /= RX_DC_EST_SAMPLES; + dc_meas_q /= RX_DC_EST_SAMPLES; } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); for (i = 0; i < 0x0F; i++) @@ -548,7 +557,9 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); XcvrCalDelay(TsettleCal * 2); - rx_dc_est_average(&dc_meas_i, &dc_meas_q); + rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); + dc_meas_i /= RX_DC_EST_SAMPLES; + dc_meas_q /= RX_DC_EST_SAMPLES; } /* Apply optimized DCOC DAC INIT : */ From 5f7c54fa5d54ba279f9d35a7bbde385cd6674a05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 13:08:59 +0100 Subject: [PATCH 51/82] squash kw41zrf vendor clean up --- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 156 ++++++------------ 1 file changed, 51 insertions(+), 105 deletions(-) diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c index 188349681be6..0e7b548340e5 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -163,7 +163,6 @@ static inline uint32_t calc_div_rounded(uint32_t num, uint32_t den) uint8_t rx_bba_dcoc_dac_trim_DCest(void) { /* Estimate the actual gain by measuring three points and approximating a line */ - TZAdcocstep_t tza_dcoc_step[11]; uint8_t status = 0; /* Save register */ @@ -273,58 +272,29 @@ uint8_t rx_bba_dcoc_dac_trim_DCest(void) * for better numeric precision */ /* rounded result, Q9.3 number */ bbf_dcoc_gain_default *= (4u * RX_DC_EST_SAMPLES / (1u << 3)); - const uint32_t *dcoc_tza_step_ptr = &xcvr_common_config.dcoc_tza_step_00_init; + /* Make the trims active */ + XCVR_RX_DIG->DCOC_BBA_STEP = + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_gain_measured) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_gain_measured_rcp); + const uint32_t *dcoc_tza_step_config_ptr = &xcvr_common_config.dcoc_tza_step_00_init; + /* All tza_step_* configuration registers use sequential memory addresses */ + volatile uint32_t *xcvr_rx_dig_dcoc_tza_step_ptr = &XCVR_RX_DIG->DCOC_TZA_STEP_0; for (unsigned k = 0; k <= 10; ++k) { /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ uint16_t tza_gain_default = - (dcoc_tza_step_ptr[k] & + (dcoc_tza_step_config_ptr[k] & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK) >> XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT; /* Using meas_sum for higher precision */ - tza_dcoc_step[k].dcoc_step = calc_div_rounded(tza_gain_default * meas_sum, bbf_dcoc_gain_default); - tza_dcoc_step[k].dcoc_step_rcp = calc_div_rounded(0x8000ul * bbf_dcoc_gain_default, tza_gain_default * meas_sum); - DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step); - DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)tza_dcoc_step[k].dcoc_step_rcp); + uint32_t dcoc_step = calc_div_rounded(tza_gain_default * meas_sum, bbf_dcoc_gain_default); + uint32_t dcoc_step_rcp = calc_div_rounded(0x8000ul * bbf_dcoc_gain_default, tza_gain_default * meas_sum); + DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)dcoc_step); + DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)dcoc_step_rcp); + xcvr_rx_dig_dcoc_tza_step_ptr[k] = + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(dcoc_step_rcp) ; } - /* Make the trims active */ - XCVR_RX_DIG->DCOC_BBA_STEP = - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_gain_measured) | - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_gain_measured_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_0 = - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; - XCVR_RX_DIG->DCOC_TZA_STEP_1 = - XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_2 = - XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_3 = - XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_4 = - XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_5 = - XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_6 = - XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_7 = - XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_8 = - XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_9 = - XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); - XCVR_RX_DIG->DCOC_TZA_STEP_10 = - XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); - status = 1; /* Success */ } else @@ -435,58 +405,46 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); dc_meas_i /= RX_DC_EST_SAMPLES; dc_meas_q /= RX_DC_EST_SAMPLES; - } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); + } while ((ABS(dc_meas_i) > 1900) || (ABS(dc_meas_q) > 1900)); for (i = 0; i < 0x0F; i++) { /* I channel : */ - if (!TZA_I_OK) - { - if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0)) - { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) - { + if (!TZA_I_OK) { + if ((i > 0) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { curr_tza_dac_i = p_tza_dac_i; } TZA_I_OK = 1; } - else - { + else { p_tza_dac_i = curr_tza_dac_i; - if (ISIGN(dc_meas_i)) /* If positif */ - { + if (dc_meas_i > 0) { curr_tza_dac_i--; } - else - { + else { curr_tza_dac_i++; } } } - else /* Sweep BBA I */ - { - if (!BBA_I_OK) - { - if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20)) - { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) - { + else { + /* Sweep BBA I */ + if (!BBA_I_OK) { + if ((curr_bba_dac_i != 0x20) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { curr_bba_dac_i = p_bba_dac_i; } BBA_I_OK = 1; } - else - { + else { p_bba_dac_i = curr_bba_dac_i; - if (ISIGN(dc_meas_i)) /* If positif */ - { + if (dc_meas_i > 0) { curr_bba_dac_i--; } - else - { + else { curr_bba_dac_i++; } } @@ -494,53 +452,41 @@ void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) } /* Q channel : */ - if (!TZA_Q_OK) - { - if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0)) - { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) - { + if (!TZA_Q_OK) { + if ((i > 0) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { curr_tza_dac_q = p_tza_dac_q; } TZA_Q_OK = 1; } - else - { + else { p_tza_dac_q = curr_tza_dac_q; - if (ISIGN(dc_meas_q)) /* If positif */ - { + if (dc_meas_q > 0) { curr_tza_dac_q--; } - else - { + else { curr_tza_dac_q++; } } } - else /* Sweep BBA Q */ - { - if (!BBA_Q_OK) - { - if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20)) - { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) - { + else { + /* Sweep BBA Q */ + if (!BBA_Q_OK) { + if ((curr_bba_dac_q != 0x20) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { curr_bba_dac_q = p_bba_dac_q; } BBA_Q_OK = 1; - } - else - { - p_bba_dac_q = curr_bba_dac_q; - if (ISIGN(dc_meas_q)) /* If positif */ - { - curr_bba_dac_q--; - } - else - { - curr_bba_dac_q++; - } - } + } + else { + p_bba_dac_q = curr_bba_dac_q; + if (dc_meas_q > 0) { + curr_bba_dac_q--; + } + else { + curr_bba_dac_q++; + } + } } } From 7c7aae972066947926466266d84d090377e7cc42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 14:52:51 +0100 Subject: [PATCH 52/82] squash kw41zrf refactor RESET --- drivers/include/kw41zrf.h | 7 +- drivers/kw41zrf/include/kw41zrf_intern.h | 7 -- drivers/kw41zrf/kw41zrf.c | 152 ++++++++++++++--------- drivers/kw41zrf/kw41zrf_intern.c | 37 ------ drivers/kw41zrf/kw41zrf_netdev.c | 7 +- 5 files changed, 100 insertions(+), 110 deletions(-) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 9682e1146e09..720cd8f0dc6c 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -160,11 +160,14 @@ void kw41zrf_setup(kw41zrf_t *dev); int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb); /** - * @brief Configure radio with default values + * @brief Reset radio hardware and restore default settings * * @param[in] dev device to reset + * + * @return 0 on success + * @return <0 on initialization failure */ -void kw41zrf_reset_phy(kw41zrf_t *dev); +int kw41zrf_reset(kw41zrf_t *dev); #ifdef __cplusplus } diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 9004ea06cd6d..6aa7e58f6b61 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -78,13 +78,6 @@ static inline void kw41zrf_unmask_irqs(void) */ void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg); -/** - * @brief Disable all interrupts on transceiver - * - * @param[in] dev kw41zrf device descriptor - */ -void kw41zrf_disable_interrupts(kw41zrf_t *dev); - /** * @brief Set power mode for device * diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index e12f5c601a9a..24906eba9cb3 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -78,47 +78,20 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) /* Save a copy of the RF_OSC_EN setting to use when the radio is in deep sleep */ dev->rf_osc_en_idle = RSIM->CONTROL & RSIM_CONTROL_RF_OSC_EN_MASK; + kw41zrf_mask_irqs(); + kw41zrf_set_irq_callback(cb, dev); - /* Enable RSIM oscillator in RUN and WAIT modes, in order to be able to - * access the XCVR and ZLL registers when using the internal reference clock - * for the CPU core */ - RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN(1); - - /* Wait for oscillator ready signal */ - while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} - - timer_init(TIMER_PIT_DEV(0), 1000000ul, NULL, NULL); - printf("[kw41zrf] start init\n"); - uint32_t before = timer_read(TIMER_PIT_DEV(0)); - int res = kw41zrf_xcvr_init(dev); - uint32_t after = timer_read(TIMER_PIT_DEV(0)); - printf("[kw41zrf] took %" PRIu32 " us\n", (after - before)); + /* Perform clean reset of the radio modules. */ + int res = kw41zrf_reset(dev); if (res < 0) { /* initialization error signaled from vendor driver */ /* Restore saved RF_OSC_EN setting */ RSIM->CONTROL = (RSIM->CONTROL & ~RSIM_CONTROL_RF_OSC_EN_MASK) | dev->rf_osc_en_idle; return res; } - /* Software reset of most settings */ - kw41zrf_reset_phy(dev); + /* Radio is now on and idle */ - /* Compute warmup times (scaled to 16us) */ - dev->rx_warmup_time = - (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - dev->tx_warmup_time = - (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; - - /* divide by 16 and round up */ - dev->rx_warmup_time = (dev->rx_warmup_time + 15) / 16; - dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16; - - /* Configure Radio IRQ */ - kw41zrf_mask_irqs(); - kw41zrf_set_irq_callback(cb, dev); - - kw41zrf_abort_sequence(dev); + /* Allow radio interrupts */ kw41zrf_unmask_irqs(); DEBUG("[kw41zrf] init finished\n"); @@ -126,28 +99,41 @@ int kw41zrf_init(kw41zrf_t *dev, kw41zrf_cb_t cb) return 0; } -void kw41zrf_reset_phy(kw41zrf_t *dev) +int kw41zrf_reset_hardware(kw41zrf_t *dev) { - /* reset options and sequence number */ - dev->netdev.seq = 0; - dev->netdev.flags = 0; + /* Enable RSIM oscillator in RUN and WAIT modes, in order to be able to + * access the XCVR and ZLL registers when using the internal reference clock + * for the CPU core */ + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN(1); - /* set default protocol */ -#ifdef MODULE_GNRC_SIXLOWPAN - dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN; -#elif MODULE_GNRC - dev->netdev.proto = GNRC_NETTYPE_UNDEF; -#endif + /* Wait for oscillator ready signal */ + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0) {} + + /* Assert radio software reset */ + RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; + /* De-assert radio software reset twice to follow recommendations in the + * reference manual */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; + + timer_init(TIMER_PIT_DEV(0), 1000000ul, NULL, NULL); + DEBUG("[kw41zrf] start xcvr init\n"); + uint32_t before = timer_read(TIMER_PIT_DEV(0)); + int res = kw41zrf_xcvr_init(dev); + uint32_t after = timer_read(TIMER_PIT_DEV(0)); + DEBUG("[kw41zrf] took %" PRIu32 " us\n", (after - before)); + if (res < 0) { + /* Most likely a calibration failure in XCVR driver */ + return res; + } /* Configure DSM exit oscillator stabilization delay */ uint32_t tmp = (RSIM->RF_OSC_CTRL & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK) >> RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT; /* Stabilization time is 1024 * 2^x radio crystal clocks, 0 <= x <= 3 */ - RSIM->DSM_OSC_OFFSET = (1024ul << tmp) / (CLOCK_RADIOXTAL / 32768) + 1; /* round up */ - - /* Bring the device out of low power mode */ - kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + RSIM->DSM_OSC_OFFSET = (1024ul << tmp) / (CLOCK_RADIOXTAL / 32768u) + 1u; /* round up */ + /* Clear and disable all interrupts */ /* Reset PHY_CTRL to the default value of mask all interrupts and all other * settings disabled */ ZLL->PHY_CTRL = @@ -164,8 +150,24 @@ void kw41zrf_reset_phy(kw41zrf_t *dev) ZLL_PHY_CTRL_SEQMSK_MASK | ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE); - /* Clear and disable all interrupts */ - kw41zrf_disable_interrupts(dev); + /* Mask all timer interrupts and clear all interrupt flags */ + ZLL->IRQSTS = + ZLL_IRQSTS_TMR1MSK_MASK | + ZLL_IRQSTS_TMR2MSK_MASK | + ZLL_IRQSTS_TMR3MSK_MASK | + ZLL_IRQSTS_TMR4MSK_MASK | + ZLL_IRQSTS_TMR1IRQ_MASK | + ZLL_IRQSTS_TMR2IRQ_MASK | + ZLL_IRQSTS_TMR3IRQ_MASK | + ZLL_IRQSTS_TMR4IRQ_MASK | + ZLL_IRQSTS_WAKE_IRQ_MASK | + ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | + ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | + ZLL_IRQSTS_RXWTRMRKIRQ_MASK | + ZLL_IRQSTS_CCAIRQ_MASK | + ZLL_IRQSTS_RXIRQ_MASK | + ZLL_IRQSTS_TXIRQ_MASK | + ZLL_IRQSTS_SEQIRQ_MASK; /* Clear source address cache */ ZLL->SAM_TABLE |= ZLL_SAM_TABLE_INVALIDATE_ALL_MASK; @@ -178,23 +180,54 @@ void kw41zrf_reset_phy(kw41zrf_t *dev) /* Set prescaler to obtain 1 symbol (16us) timebase */ kw41zrf_timer_init(dev, KW41ZRF_TIMEBASE_62500HZ); - /* Set CCA threshold to -75 dBm */ + /* Set CCA threshold to -70 dBm */ /* The hardware default for this register is +75 dBm (0x4b), which is nonsense */ ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) | - ZLL_CCA_LQI_CTRL_CCA1_THRESH(-75); + ZLL_CCA_LQI_CTRL_CCA1_THRESH(-70); - /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */ - ZLL->ACKDELAY = (ZLL->ACKDELAY & ~ZLL_ACKDELAY_ACKDELAY_MASK) | ZLL_ACKDELAY_ACKDELAY(-8); + /* IEEE 802.15.4 requires that ACK transmission commences 12 symbol periods + * (192 us) after the reception of the last octet of the frame being acknowledged. */ + //~ ZLL->ACKDELAY = (ZLL->ACKDELAY & ~ZLL_ACKDELAY_ACKDELAY_MASK) | ZLL_ACKDELAY_ACKDELAY(-8); - /* Adjust LQI compensation */ + /* Set default LQI compensation */ /* Hardware reset default is 102 */ ZLL->CCA_LQI_CTRL = (ZLL->CCA_LQI_CTRL & ~ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) | - ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(96); + ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(102); /* set defaults */ ZLL->SEQ_CTRL_STS = ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK; + return 0; +} + +int kw41zrf_reset(kw41zrf_t *dev) +{ + kw41zrf_mask_irqs(); + + int res = kw41zrf_reset_hardware(dev); + if (res < 0) { + /* Most likely a calibration failure in XCVR driver */ + kw41zrf_unmask_irqs(); + return res; + } + + /* Compute warmup times (scaled to 16us) */ + dev->rx_warmup_time = + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + dev->tx_warmup_time = + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + + /* divide by 16 and round up */ + dev->rx_warmup_time = (dev->rx_warmup_time + 15) / 16; + dev->tx_warmup_time = (dev->tx_warmup_time + 15) / 16; + + /* Reset software link layer driver state */ + netdev_ieee802154_reset(&dev->netdev); + dev->tx_power = KW41ZRF_DEFAULT_TX_POWER; + dev->idle_seq = XCVSEQ_RECEIVE; kw41zrf_set_tx_power(dev, dev->tx_power); kw41zrf_set_channel(dev, KW41ZRF_DEFAULT_CHANNEL); @@ -213,11 +246,12 @@ void kw41zrf_reset_phy(kw41zrf_t *dev) kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); kw41zrf_set_sequence(dev, dev->idle_seq); - kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_START, true); - kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_RX_END, true); - kw41zrf_set_option(dev, KW41ZRF_OPT_TELL_TX_END, true); bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_SEQMSK_SHIFT); - DEBUG("[kw41zrf] reset PHY and (re)set to channel %d and pan %d.\n", + kw41zrf_abort_sequence(dev); + kw41zrf_unmask_irqs(); + + DEBUG("[kw41zrf] reset radio and set to channel %d and pan %d.\n", KW41ZRF_DEFAULT_CHANNEL, KW41ZRF_DEFAULT_PANID); + return 0; } diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index dca0f20c9df3..0e78dc16559d 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -53,43 +53,6 @@ void kw41zrf_set_irq_callback(void (*cb)(void *arg), void *arg) irq_restore(mask); } -void kw41zrf_disable_interrupts(kw41zrf_t *dev) -{ - (void) dev; - DEBUG("[kw41zrf] disable interrupts\n"); - /* Clear and disable all interrupts */ - ZLL->PHY_CTRL |= - ZLL_PHY_CTRL_TSM_MSK_MASK | - ZLL_PHY_CTRL_WAKE_MSK_MASK | - ZLL_PHY_CTRL_CRC_MSK_MASK | - ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | - ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK | - ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | - ZLL_PHY_CTRL_CCAMSK_MASK | - ZLL_PHY_CTRL_RXMSK_MASK | - ZLL_PHY_CTRL_TXMSK_MASK | - ZLL_PHY_CTRL_SEQMSK_MASK; - - /* Mask all timer interrupts and clear all interrupt flags */ - ZLL->IRQSTS = - ZLL_IRQSTS_TMR1MSK_MASK | - ZLL_IRQSTS_TMR2MSK_MASK | - ZLL_IRQSTS_TMR3MSK_MASK | - ZLL_IRQSTS_TMR4MSK_MASK | - ZLL_IRQSTS_TMR1IRQ_MASK | - ZLL_IRQSTS_TMR2IRQ_MASK | - ZLL_IRQSTS_TMR3IRQ_MASK | - ZLL_IRQSTS_TMR4IRQ_MASK | - ZLL_IRQSTS_WAKE_IRQ_MASK | - ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | - ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | - ZLL_IRQSTS_RXWTRMRKIRQ_MASK | - ZLL_IRQSTS_CCAIRQ_MASK | - ZLL_IRQSTS_RXIRQ_MASK | - ZLL_IRQSTS_TXIRQ_MASK | - ZLL_IRQSTS_SEQIRQ_MASK; -} - void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) { DEBUG("[kw41zrf] set power mode to %u\n", pm); diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 16333bec11cf..f6e52b9e1e09 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -84,7 +84,7 @@ static int kw41zrf_netdev_init(netdev_t *netdev) kw41zrf_t *dev = (kw41zrf_t *)netdev; dev->thread = (thread_t *)thread_get(thread_getpid()); - /* initialise SPI and GPIOs */ + /* initialize hardware */ if (kw41zrf_init(dev, kw41zrf_irq_handler)) { LOG_ERROR("[kw41zrf] unable to initialize device\n"); return -1; @@ -94,9 +94,6 @@ static int kw41zrf_netdev_init(netdev_t *netdev) memset(&netdev->stats, 0, sizeof(netstats_t)); #endif - /* reset device to default values and put it into RX state */ - kw41zrf_reset_phy(dev); - return 0; } @@ -399,7 +396,7 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) } break; case NETOPT_STATE_RESET: - kw41zrf_reset_phy(dev); + kw41zrf_reset(dev); break; default: return -ENOTSUP; From 71a243e2ebe0f1a2fba7e1dd4fcaef8206e53eaa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 30 Oct 2018 16:19:25 +0100 Subject: [PATCH 53/82] squash kw41zrf refactor vendor code --- drivers/kw41zrf/kw41zrf.c | 2 +- drivers/kw41zrf/kw41zrf_getset.c | 2 +- drivers/kw41zrf/kw41zrf_xcvr.c | 656 +++++++++++++++++- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 1 - 4 files changed, 652 insertions(+), 9 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 24906eba9cb3..a13ae98f8f72 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -33,7 +33,7 @@ #include "vendor/XCVR/MKW41Z4/ifr_radio.h" #include "periph/timer.h" -#define ENABLE_DEBUG (0) +#define ENABLE_DEBUG (1) #include "debug.h" static void kw41zrf_set_address(kw41zrf_t *dev) diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index bdaaecec7319..702624d28723 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -24,7 +24,7 @@ #include "kw41zrf_intern.h" #include "kw41zrf_getset.h" -#define ENABLE_DEBUG (0) +#define ENABLE_DEBUG (1) #include "debug.h" #define KW41ZRF_NUM_CHANNEL (KW41ZRF_MAX_CHANNEL - KW41ZRF_MIN_CHANNEL + 1) diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c index 84a40ef6290a..7e0e64c2720e 100644 --- a/drivers/kw41zrf/kw41zrf_xcvr.c +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -1,9 +1,36 @@ /* - * Copyright (C) 2018 SKF AB + * The Clear BSD License + * Copyright 2016-2017 NXP + * All rights reserved. * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** @@ -29,6 +56,623 @@ #define ENABLE_DEBUG (0) #include "debug.h" +/* The implementations for these functions are taken from the vendor provided XCVR + * driver from NXP MCUXpresso. The code has been refactored to eliminate a lot + * of preprocessor conditionals. */ + +#define TsettleCal 10 +#define DCOC_DAC_BBF_STEP (16u) +#define RX_DC_EST_SAMPLES (64u) +#define RX_DC_EST_TOTAL_SAMPLES (2u * (RX_DC_EST_SAMPLES)) + +/* dumb spin delay used in the calibration functions */ +static void XcvrCalDelay(uint32_t time) +{ + time *= 32; /* Time delay is roughly in uSec. */ + while(time > 0) + { + __asm__ volatile ("" ::: "memory"); + --time; + } +} + +/* Collect RX DC estimation samples */ +static void rx_dc_est_samples(int32_t *i_sum, int32_t *q_sum, unsigned nsamples) +{ + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + uint32_t end_of_rx_wu = XCVR_CTRL_XCVR_STATUS_TSM_COUNT( + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT); + while ((XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) != end_of_rx_wu) {}; + + int32_t sum_i = 0; + int32_t sum_q = 0; + /* Read DCOC DC EST register. */ + for (unsigned k = 0; k < nsamples; k++) + { + uint32_t dc_temp = XCVR_RX_DIG->DCOC_DC_EST; + int16_t dc_meas_i = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT; + dc_meas_i = (int16_t)(dc_meas_i << 4) / 16; /* Sign extend from 12 to 16 bits. */ + sum_i += dc_meas_i; + + int16_t dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; + dc_meas_q = (int16_t)(dc_meas_q << 4) / 16; /* Sign extend from 12 to 16 bits. */ + sum_q += dc_meas_q; + } + + *i_sum = sum_i; + *q_sum = sum_q; +} + +/* Unsigned integer division, rounded to nearest integer */ +static inline uint32_t calc_div_rounded(uint32_t num, uint32_t den) +{ + return (num + (den / 2)) / den; +} + +int kw41zrf_rx_bba_dcoc_dac_trim_DCest(void) +{ + /* Estimate the actual gain by measuring three points and approximating a line */ + int status = 0; + + /* Save register */ + uint32_t dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + uint32_t dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + uint32_t rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + uint32_t agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + uint32_t dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG->RX_DIG_CTRL & + ~(XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK | /* Turn OFF AGC */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK | /* Disable for SW control of DCOC */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK); /* Disable for SW control of DCOC */ + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + XCVR_RX_DIG->DCOC_CTRL_0 = XCVR_RX_DIG->DCOC_CTRL_0 | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1) | /* Enable Manual DCOC */ + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1) | /* Ensure DCOC Tracking is enabled */ + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1) | /* Enable DC Estimator */ + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + + /* Use reset defaults */ + uint8_t bbf_dacinit_i = 0x20; + uint8_t bbf_dacinit_q = 0x20; + uint8_t tza_dacinit_i = 0x80; + uint8_t tza_dacinit_q = 0x80; + + /* Set default DCOC DAC INIT Value */ + XCVR_RX_DIG->DCOC_DAC_INIT = + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + /* Store DCOC_DAC_INIT value */ + uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; + + XcvrCalDelay(TsettleCal * 2); + + uint32_t meas_sum = 0; + /* SWEEP I/Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - DCOC_DAC_BBF_STEP) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - DCOC_DAC_BBF_STEP) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 4); + + int32_t dc_meas_im = 0; + int32_t dc_meas_qm = 0; + rx_dc_est_samples(&dc_meas_im, &dc_meas_qm, RX_DC_EST_SAMPLES); + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + DCOC_DAC_BBF_STEP) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + DCOC_DAC_BBF_STEP) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 4); + int32_t dc_meas_ip = 0; + int32_t dc_meas_qp = 0; + rx_dc_est_samples(&dc_meas_ip, &dc_meas_qp, RX_DC_EST_SAMPLES); + DEBUG("dc_meas_i- = %" PRId32 "\n", dc_meas_im); + DEBUG("dc_meas_q- = %" PRId32 "\n", dc_meas_qm); + DEBUG("dc_meas_i+ = %" PRId32 "\n", dc_meas_ip); + DEBUG("dc_meas_q+ = %" PRId32 "\n", dc_meas_qp); + meas_sum += dc_meas_ip - dc_meas_im; + DEBUG("meas_sum = %" PRIu32 "\n", meas_sum); + meas_sum += dc_meas_qp - dc_meas_qm; + DEBUG("meas_sum = %" PRIu32 "\n", meas_sum); + meas_sum /= 2 * DCOC_DAC_BBF_STEP; + DEBUG("meas_sum = %" PRIu32 "\n", meas_sum); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ + + /* Compute the average sampled gain for the measured steps */ + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + /* meas_sum here is the average gain multiplied by (4 * RX_DC_EST_SAMPLES) */ + /* Compute the gain average as a Q6.3 number */ + /* rounded result, Q6.3 number */ + uint16_t bbf_dcoc_gain_measured = calc_div_rounded(meas_sum, (RX_DC_EST_TOTAL_SAMPLES / (1 << 3))); + + DEBUG("temp_step = %f\n", (float)meas_sum / RX_DC_EST_TOTAL_SAMPLES); + DEBUG("bbf_dcoc_gain_measured = %u\n", (unsigned)bbf_dcoc_gain_measured); + + /* Check the measured value for validity. Should be in the range: + * 250 < bbf_dcoc_gain_measured < 305, according to NXP wireless framework v5.4.3 (MCUXpresso KW36 SDK) + */ + if ((250 < bbf_dcoc_gain_measured) & (bbf_dcoc_gain_measured < 305)) + { + /* Compute reciprocal, as Q15 number, but only the 13 lowest bits are programmable */ + /* rounded result, ((2**15) / slope) */ + uint32_t bbf_dcoc_gain_measured_rcp = calc_div_rounded((1u << 15) * RX_DC_EST_TOTAL_SAMPLES, meas_sum); + DEBUG("bbf_dcoc_gain_measured_rcp = %"PRIu32"\n", bbf_dcoc_gain_measured_rcp); + + uint32_t bbf_dcoc_gain_default = + (xcvr_common_config.dcoc_bba_step_init & + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK) >> + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT; + /* Rescale all default TZA DCOC gains according to the measured BBF gain, + * using (bbf_dcoc_gain_measured / bbf_dcoc_gain_default) as the implicit + * scale factor, but rewrite it to use + * (meas_sum / (bbf_dcoc_gain_default * RX_DC_EST_TOTAL_SAMPLES / (1u << 3)))) + * for better numeric precision */ + /* rounded result, Q9.3 number */ + bbf_dcoc_gain_default *= (RX_DC_EST_TOTAL_SAMPLES / (1u << 3)); + DEBUG("base gain = %u\n", (unsigned)bbf_dcoc_gain_default); + /* Make the trims active */ + XCVR_RX_DIG->DCOC_BBA_STEP = + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_gain_measured) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_gain_measured_rcp); + const uint32_t *dcoc_tza_step_config_ptr = &xcvr_common_config.dcoc_tza_step_00_init; + /* All tza_step_* configuration registers use sequential memory addresses */ + volatile uint32_t *xcvr_rx_dig_dcoc_tza_step_ptr = &XCVR_RX_DIG->DCOC_TZA_STEP_0; + for (unsigned k = 0; k <= 10; ++k) + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ + uint16_t tza_gain_default = + (dcoc_tza_step_config_ptr[k] & + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK) >> + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT; + /* Using meas_sum for higher precision */ + DEBUG("tza_gain_default[%u] = %u\n", k, (unsigned)tza_gain_default); + uint32_t dcoc_step = calc_div_rounded(tza_gain_default * meas_sum, bbf_dcoc_gain_default); + uint32_t dcoc_step_rcp = calc_div_rounded((0x8000ul << 3) * bbf_dcoc_gain_default, tza_gain_default * meas_sum); + DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)dcoc_step); + DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)dcoc_step_rcp); + xcvr_rx_dig_dcoc_tza_step_ptr[k] = + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(dcoc_step) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(dcoc_step_rcp) ; + } + } + else + { + LOG_ERROR("!!! XCVR trim failed: bbf_dcoc_step = %u!\n", (unsigned)bbf_dcoc_gain_measured); + status = -EAGAIN; /* Failure */ + } + + /* Restore Registers */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ + + return status; +} + +static int kw41zrf_xcvr_configure(kw41zrf_t *dev, + const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config) +{ + (void)dev; + int config_status = 0; + uint32_t temp; + + /* Turn on the module clocks before doing anything */ + SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; + + /* XCVR_ANA configs */ + + /* Configure PLL Loop Filter */ + XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask; + XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init; + + /* Configure VCO KVM */ + XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask; + XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init; + + /* Configure analog filter bandwidth */ + XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask; + XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init; + XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask; + XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init; + + temp = XCVR_ANA->TX_DAC_PA; + temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; + temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); + XCVR_ANA->TX_DAC_PA = temp; + + temp = XCVR_ANA->BB_LDO_2; + temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); + XCVR_ANA->BB_LDO_2 = temp; + + temp = XCVR_ANA->RX_LNA; + temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK; + temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1); + XCVR_ANA->RX_LNA = temp; + + temp = XCVR_ANA->BB_LDO_1; + temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1); + XCVR_ANA->BB_LDO_1 = temp; + + /* XCVR_MISC configs */ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); + temp |= mode_config->xcvr_ctrl.init; + if (CLOCK_RADIOXTAL == 26000000ul) { + temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); + } + + XCVR_MISC->XCVR_CTRL = temp; + + /* XCVR_PHY configs */ + XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init; + XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init; + XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init; + XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; + XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init; + XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */ + + /* XCVR_PLL_DIG configs */ + XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump; + XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl; + XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map; + XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect; + XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl; + XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl; + XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res; + XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl; + XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1; + XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match; + XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl; + + /* XCVR_RX_DIG configs */ + + /* Configure RF Aux PLL for proper operation based on external clock frequency */ + temp = XCVR_ANA->RX_AUXPLL; + temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK; + if (CLOCK_RADIOXTAL == 26000000ul) { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4); + } + else { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7); + } + XCVR_ANA->RX_AUXPLL = temp; + + /* Configure RX_DIG_CTRL */ + if (CLOCK_RADIOXTAL == 26000000ul) { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */ + } + else { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + 0; /* Always disable the sample rate converter for 32MHz */ + } + + temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + /* DCOC_CAL_IIR */ + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz; + } + else { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz; + } + + /* DC_RESID_CTRL */ + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; + } + else { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; + } + + /* DCOC_CTRL_0 & _1 */ + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ + + /* customize DCOC_CTRL_0 settings for Gen2 GFSK BT=0.5, h=0.32 */ + if ((mode_config->radio_mode == ANT_MODE) || (mode_config->radio_mode == GFSK_BT_0p5_h_0p32)) + { + if (datarate_config->data_rate == DR_1MBPS) /* only apply fix to 1Mbps data rates */ + { + /* apply the changes to the DCOC_CTRL_0 register XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp &= ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(0x10) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(0x0C); + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + } + } + } + else { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ + } + + /* DCOC_CAL_GAIN */ + XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init; + + /* DCOC_CAL_RCP */ + XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init; + XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0; + XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4; + XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8; + + /* LNA_GAIN_LIN_VAL */ + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init; + + /* BBA_RES_TUNE_LIN_VAL */ + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init; + + /* BBA_STEP */ + XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init; + + /* DCOC_TZA_STEP */ + XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init; + + /* AGC_CTRL_0 .. _3 */ + XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init; + + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz; + } + else { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz; + } + + XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init; + + /* AGC_GAIN_TBL_** */ + XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init; + XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init; + XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init; + XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init; + XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init; + XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init; + XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init; + + /* RSSI_CTRL_0 */ + XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init; + + /* CCA_ED_LQI_0 and _1 */ + XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init; + XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init; + + /* Channel filter coefficients */ + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11; + } + else { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11; + } + + XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0; + XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1; + + /* XCVR_TSM configs */ + XCVR_TSM->CTRL = com_config->tsm_ctrl; + + if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE)) + { + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; + } + + XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */ + + XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init; + /* TSM registers and timings - dependent upon clock frequency */ + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz; + } + else { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz; + } + + /* TSM timings independent of clock frequency */ + XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init; + XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init; + XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init; + XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init; + XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init; + XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init; + XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init; + XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init; + XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init; + XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init; + XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init; + XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init; + XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init; + XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init; + XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init; + XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init; + XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init; + XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init; + XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init; + XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; + XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init; + XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init; + XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init; + XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init; + XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init; + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init; + XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init; + XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init; + XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; + XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; + XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; + + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ); + } + else { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD); + } + + XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; + XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; + + if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS))) { + /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */ + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */ + } + else { + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ + } + + /* XCVR_TX_DIG configs */ + if (CLOCK_RADIOXTAL == 26000000ul) { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz; + } + else { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz; + } + + XCVR_TX_DIG->CTRL = com_config->tx_ctrl; + XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; + XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; + + XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; + XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; + + XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; + + uint32_t end_of_rx_wu = 0; + XCVR_ForceRxWu(); + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + int res = kw41zrf_rx_bba_dcoc_dac_trim_DCest(); + if (res < 0) { + config_status = res; + } + DCOC_DAC_INIT_Cal(0); + XCVR_ForceRxWd(); + + return config_status; +} + int kw41zrf_xcvr_init(kw41zrf_t *dev) { (void) dev; @@ -68,8 +712,8 @@ int kw41zrf_xcvr_init(kw41zrf_t *dev) } /* We only use 802.15.4 mode in this driver */ - xcvrStatus_t status = XCVR_Configure(&xcvr_common_config, &zgbe_mode_config, - &xcvr_ZIGBEE_500kbps_config, &xcvr_802_15_4_500kbps_config, 25, XCVR_FIRST_INIT); + xcvrStatus_t status = kw41zrf_xcvr_configure(dev, &xcvr_common_config, + &zgbe_mode_config, &xcvr_ZIGBEE_500kbps_config, &xcvr_802_15_4_500kbps_config); if (status != gXcvrSuccess_c) { return -EIO; diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h index f633f76828ca..9c9472333ff8 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -122,7 +122,6 @@ typedef struct void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); -void XcvrCalDelay(uint32_t time); void rx_dc_est_average(int16_t *i_avg, int16_t *q_avg); uint8_t rx_bba_dcoc_dac_trim_DCest(void); void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); From e356de67e94b85cd1c737b3acc99b1c57bc7c3d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 08:14:07 +0100 Subject: [PATCH 54/82] squash kw41zrf refactor vendor code --- drivers/kw41zrf/kw41zrf_xcvr.c | 224 ++++++++++++++++++++++++++++++--- 1 file changed, 210 insertions(+), 14 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c index 7e0e64c2720e..6bd2ff870e36 100644 --- a/drivers/kw41zrf/kw41zrf_xcvr.c +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -61,12 +61,20 @@ * of preprocessor conditionals. */ #define TsettleCal 10 -#define DCOC_DAC_BBF_STEP (16u) -#define RX_DC_EST_SAMPLES (64u) -#define RX_DC_EST_TOTAL_SAMPLES (2u * (RX_DC_EST_SAMPLES)) +#define DCOC_DAC_BBF_STEP (16) +#define RX_DC_EST_SAMPLES (64) +#define RX_DC_EST_TOTAL_SAMPLES (2 * (RX_DC_EST_SAMPLES)) +#define ISIGN(x) !((uint16_t)x & 0x8000) +#define ABS(x) ((x) > 0 ? (x) : -(x)) +#ifndef MIN +#define MIN(a,b) \ + ({ __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a < _b ? _a : _b; }) +#endif /* dumb spin delay used in the calibration functions */ -static void XcvrCalDelay(uint32_t time) +static void kw41zrf_xcvr_spin(uint32_t time) { time *= 32; /* Time delay is roughly in uSec. */ while(time > 0) @@ -156,7 +164,7 @@ int kw41zrf_rx_bba_dcoc_dac_trim_DCest(void) /* Store DCOC_DAC_INIT value */ uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; - XcvrCalDelay(TsettleCal * 2); + kw41zrf_xcvr_spin(TsettleCal * 2); uint32_t meas_sum = 0; /* SWEEP I/Q CHANNEL */ @@ -165,7 +173,7 @@ int kw41zrf_rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - DCOC_DAC_BBF_STEP) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 4); + kw41zrf_xcvr_spin(TsettleCal * 4); int32_t dc_meas_im = 0; int32_t dc_meas_qm = 0; @@ -176,7 +184,7 @@ int kw41zrf_rx_bba_dcoc_dac_trim_DCest(void) XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + DCOC_DAC_BBF_STEP) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 4); + kw41zrf_xcvr_spin(TsettleCal * 4); int32_t dc_meas_ip = 0; int32_t dc_meas_qp = 0; rx_dc_est_samples(&dc_meas_ip, &dc_meas_qp, RX_DC_EST_SAMPLES); @@ -267,6 +275,191 @@ int kw41zrf_rx_bba_dcoc_dac_trim_DCest(void) return status; } +static void kw41zrf_dcoc_dac_init_cal(void) +{ + uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0; + uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0; + uint8_t i = 0; + uint8_t bba_gain = 11; + bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; + + uint32_t temp; + + /* Save registers */ + uint32_t dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + uint32_t dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + uint32_t rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + uint32_t agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + uint32_t dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + kw41zrf_xcvr_spin(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + /* LNA and BBA DAC Sweep */ + uint8_t curr_bba_dac_i = 0x20; + uint8_t curr_bba_dac_q = 0x20; + uint8_t curr_tza_dac_i = 0x80; + uint8_t curr_tza_dac_q = 0x80; + + /* Perform a first DC measurement to ensure that measurement is not clipping */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + int32_t dc_meas_i = 2000, dc_meas_i_p = 2000; + int32_t dc_meas_q = 2000, dc_meas_q_p = 2000; + do { + bba_gain--; + /* Set DAC user gain */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ + kw41zrf_xcvr_spin(TsettleCal * 2); + rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); + DEBUG("rx i=%d q=%d\n", (int)dc_meas_i, (int)dc_meas_q); + dc_meas_i /= RX_DC_EST_SAMPLES; + dc_meas_q /= RX_DC_EST_SAMPLES; + DEBUG("rx i=%d q=%d\n", (int)dc_meas_i, (int)dc_meas_q); + DEBUG("[kw41zrf] bba_gain=%u, meas I=%" PRId32 ", Q=%" PRId32 "\n", (unsigned)bba_gain, dc_meas_i, dc_meas_q); + } while ((ABS(dc_meas_i) > 1900) || (ABS(dc_meas_q) > 1900)); + + for (i = 0; i < 0x0F; i++) + { + /* I channel : */ + if (!TZA_I_OK) { + if ((i > 0) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { + curr_tza_dac_i = p_tza_dac_i; + } + + TZA_I_OK = 1; + } + else { + p_tza_dac_i = curr_tza_dac_i; + + if (dc_meas_i > 0) { + curr_tza_dac_i--; + } + else { + curr_tza_dac_i++; + } + } + } + else { + /* Sweep BBA I */ + if (!BBA_I_OK) { + if ((curr_bba_dac_i != 0x20) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { + curr_bba_dac_i = p_bba_dac_i; + } + + BBA_I_OK = 1; + } + else { + p_bba_dac_i = curr_bba_dac_i; + if (dc_meas_i > 0) { + curr_bba_dac_i--; + } + else { + curr_bba_dac_i++; + } + } + } + } + + /* Q channel : */ + if (!TZA_Q_OK) { + if ((i > 0) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { + curr_tza_dac_q = p_tza_dac_q; + } + TZA_Q_OK = 1; + } + else { + p_tza_dac_q = curr_tza_dac_q; + if (dc_meas_q > 0) { + curr_tza_dac_q--; + } + else { + curr_tza_dac_q++; + } + } + } + else { + /* Sweep BBA Q */ + if (!BBA_Q_OK) { + if ((curr_bba_dac_q != 0x20) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { + curr_bba_dac_q = p_bba_dac_q; + } + BBA_Q_OK = 1; + } + else { + p_bba_dac_q = curr_bba_dac_q; + if (dc_meas_q > 0) { + curr_bba_dac_q--; + } + else { + curr_bba_dac_q++; + } + } + } + } + + /* DC OK break : */ + if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK) { + break; + } + + dc_meas_i_p = dc_meas_i; /* Store as previous value */ + dc_meas_q_p = dc_meas_q; /* Store as previous value */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + kw41zrf_xcvr_spin(TsettleCal * 2); + rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); + dc_meas_i /= RX_DC_EST_SAMPLES; + dc_meas_q /= RX_DC_EST_SAMPLES; + } + + /* Apply optimized DCOC DAC INIT : */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + /* Restore register */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ +} + static int kw41zrf_xcvr_configure(kw41zrf_t *dev, const xcvr_common_config_t *com_config, const xcvr_mode_config_t *mode_config, @@ -656,19 +849,22 @@ static int kw41zrf_xcvr_configure(kw41zrf_t *dev, XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; - uint32_t end_of_rx_wu = 0; - XCVR_ForceRxWu(); + /* Force receiver warmup */ + bit_set32(&XCVR_TSM->CTRL, XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT); /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + uint32_t end_of_rx_wu = XCVR_CTRL_XCVR_STATUS_TSM_COUNT( + (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT); + while ((XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) != end_of_rx_wu) {}; int res = kw41zrf_rx_bba_dcoc_dac_trim_DCest(); if (res < 0) { config_status = res; } - DCOC_DAC_INIT_Cal(0); - XCVR_ForceRxWd(); + //~ DCOC_DAC_INIT_Cal(0); + kw41zrf_dcoc_dac_init_cal(); + /* Force receiver warmdown */ + bit_clear32(&XCVR_TSM->CTRL, XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT); return config_status; } From 03e39ef5ddeb2717b1c389f4862f9e3b8ed73107 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 08:38:16 +0100 Subject: [PATCH 55/82] squash kw41zrf refactor vendor code, eliminate dead paths --- drivers/kw41zrf/kw41zrf.c | 2 +- drivers/kw41zrf/kw41zrf_getset.c | 2 +- drivers/kw41zrf/kw41zrf_xcvr.c | 73 +- .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c | 212 -- .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h | 164 -- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c | 2144 ----------------- .../kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h | 499 +--- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c | 532 ---- .../vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h | 140 -- 9 files changed, 83 insertions(+), 3685 deletions(-) delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c delete mode 100644 drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index a13ae98f8f72..24906eba9cb3 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -33,7 +33,7 @@ #include "vendor/XCVR/MKW41Z4/ifr_radio.h" #include "periph/timer.h" -#define ENABLE_DEBUG (1) +#define ENABLE_DEBUG (0) #include "debug.h" static void kw41zrf_set_address(kw41zrf_t *dev) diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 702624d28723..bdaaecec7319 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -24,7 +24,7 @@ #include "kw41zrf_intern.h" #include "kw41zrf_getset.h" -#define ENABLE_DEBUG (1) +#define ENABLE_DEBUG (0) #include "debug.h" #define KW41ZRF_NUM_CHANNEL (KW41ZRF_MAX_CHANNEL - KW41ZRF_MIN_CHANNEL + 1) diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c index 6bd2ff870e36..e9179ed98d60 100644 --- a/drivers/kw41zrf/kw41zrf_xcvr.c +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -64,14 +64,10 @@ #define DCOC_DAC_BBF_STEP (16) #define RX_DC_EST_SAMPLES (64) #define RX_DC_EST_TOTAL_SAMPLES (2 * (RX_DC_EST_SAMPLES)) -#define ISIGN(x) !((uint16_t)x & 0x8000) + +/* Macros used by the calibration routine */ +#define SAME_SIGN(a, b) (((a) ^ (b)) >= 0) #define ABS(x) ((x) > 0 ? (x) : -(x)) -#ifndef MIN -#define MIN(a,b) \ - ({ __typeof__ (a) _a = (a); \ - __typeof__ (b) _b = (b); \ - _a < _b ? _a : _b; }) -#endif /* dumb spin delay used in the calibration functions */ static void kw41zrf_xcvr_spin(uint32_t time) @@ -348,10 +344,11 @@ static void kw41zrf_dcoc_dac_init_cal(void) for (i = 0; i < 0x0F; i++) { + DEBUG("rx i=%d q=%d\n", (int)dc_meas_i, (int)dc_meas_q); /* I channel : */ if (!TZA_I_OK) { - if ((i > 0) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { + if ((i > 0) && (!SAME_SIGN(dc_meas_i, dc_meas_i_p))) { + if (ABS(dc_meas_i) > ABS(dc_meas_i_p)) { curr_tza_dac_i = p_tza_dac_i; } @@ -368,32 +365,30 @@ static void kw41zrf_dcoc_dac_init_cal(void) } } } - else { + else if (!BBA_I_OK) { /* Sweep BBA I */ - if (!BBA_I_OK) { - if ((curr_bba_dac_i != 0x20) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { - curr_bba_dac_i = p_bba_dac_i; - } + if ((curr_bba_dac_i != 0x20) && (!SAME_SIGN(dc_meas_i, dc_meas_i_p))) { + if (ABS(dc_meas_i) > ABS(dc_meas_i_p)) { + curr_bba_dac_i = p_bba_dac_i; + } - BBA_I_OK = 1; + BBA_I_OK = 1; + } + else { + p_bba_dac_i = curr_bba_dac_i; + if (dc_meas_i > 0) { + curr_bba_dac_i--; } else { - p_bba_dac_i = curr_bba_dac_i; - if (dc_meas_i > 0) { - curr_bba_dac_i--; - } - else { - curr_bba_dac_i++; - } + curr_bba_dac_i++; } } } /* Q channel : */ if (!TZA_Q_OK) { - if ((i > 0) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { + if ((i > 0) && (!SAME_SIGN(dc_meas_q, dc_meas_q_p))) { + if (ABS(dc_meas_q) > ABS(dc_meas_q_p)) { curr_tza_dac_q = p_tza_dac_q; } TZA_Q_OK = 1; @@ -408,23 +403,21 @@ static void kw41zrf_dcoc_dac_init_cal(void) } } } - else { + else if (!BBA_Q_OK) { /* Sweep BBA Q */ - if (!BBA_Q_OK) { - if ((curr_bba_dac_q != 0x20) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { - curr_bba_dac_q = p_bba_dac_q; - } - BBA_Q_OK = 1; + if ((curr_bba_dac_q != 0x20) && (!SAME_SIGN(dc_meas_q, dc_meas_q_p))) { + if (ABS(dc_meas_q) > ABS(dc_meas_q_p)) { + curr_bba_dac_q = p_bba_dac_q; + } + BBA_Q_OK = 1; + } + else { + p_bba_dac_q = curr_bba_dac_q; + if (dc_meas_q > 0) { + curr_bba_dac_q--; } else { - p_bba_dac_q = curr_bba_dac_q; - if (dc_meas_q > 0) { - curr_bba_dac_q--; - } - else { - curr_bba_dac_q++; - } + curr_bba_dac_q++; } } } @@ -436,6 +429,8 @@ static void kw41zrf_dcoc_dac_init_cal(void) dc_meas_i_p = dc_meas_i; /* Store as previous value */ dc_meas_q_p = dc_meas_q; /* Store as previous value */ + DEBUG("curr_bba_dac i=%d q=%d\n", (int)curr_bba_dac_i, (int)curr_bba_dac_q); + DEBUG("curr_tza_dac i=%d q=%d\n", (int)curr_tza_dac_i, (int)curr_tza_dac_q); XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c deleted file mode 100644 index 7a5c118ce0c4..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c +++ /dev/null @@ -1,212 +0,0 @@ -/*! -* Copyright 2016-2017 NXP -* -* \file -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "fsl_xcvr.h" -#include "xcvr_test_fsk.h" - -/*! ********************************************************************************* -************************************************************************************* -* Private type definitions -************************************************************************************* -********************************************************************************** */ -enum { - gDftNormal_c = 0, - gDftTxNoMod_Carrier_c = 1, - gDftTxPattern_c = 2, - gDftTxRandom_c = 3, -}; - -/*! ********************************************************************************* -************************************************************************************* -* Private memory declarations -************************************************************************************* -********************************************************************************** */ - -/*! ********************************************************************************* -************************************************************************************* -* Public prototypes -************************************************************************************* -********************************************************************************** */ -void XcvrFskModTx(void); -void XcvrFskNoModTx(void); -void XcvrFskIdle(void); -void XcvrFskTxRand(void); -void XcvrFskLoadPattern(uint32_t u32Pattern); -void XcvrFskSetTxPower(uint8_t u8TxPow); -void XcvrFskSetTxChannel(uint8_t u8TxChan); -void XcvrFskRestoreTXControl(void); -uint8_t XcvrFskGetInstantRssi(void); - -/*! ********************************************************************************* -* XcvrFskModTx -***********************************************************************************/ -void XcvrFskModTx(void) -{ - XcvrFskIdle(); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); - XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxPattern_c) | - XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK; - XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskNoModTx -***********************************************************************************/ -void XcvrFskNoModTx(void) -{ - XcvrFskIdle(); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); - XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxNoMod_Carrier_c); - XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskIdle -***********************************************************************************/ -void XcvrFskIdle(void) -{ - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | - XCVR_TX_DIG_CTRL_LFSR_EN_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; - XCVR_MISC->DTEST_CTRL &= ~XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskTxRand -***********************************************************************************/ -void XcvrFskTxRand(void) -{ - XcvrFskIdle(); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | - XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK); - XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxRandom_c) | - XCVR_TX_DIG_CTRL_LFSR_LENGTH(0) | /* length 9 */ - XCVR_TX_DIG_CTRL_LFSR_EN_MASK; - XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -/*! ********************************************************************************* -* XcvrFskLoadPattern -***********************************************************************************/ -void XcvrFskLoadPattern(uint32_t u32Pattern) -{ - XCVR_TX_DIG->DFT_PATTERN = u32Pattern; -} - -/*! ********************************************************************************* -* XcvrFskGetInstantRssi -***********************************************************************************/ -uint8_t XcvrFskGetInstantRssi(void) -{ - uint8_t u8Rssi; - uint32_t t1,t2,t3; - t1 = XCVR_RX_DIG->RX_DIG_CTRL; - t2 = XCVR_RX_DIG->RSSI_CTRL_0; - t3 = XCVR_PHY->CFG1; - XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate == 0 */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ; - - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK; - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5); - - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK; - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); - - uint32_t temp = XCVR_PHY->CFG1; - temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK; - temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF); - XCVR_PHY->CFG1 = temp; - - XCVR_ForceRxWu(); - for(uint32_t i = 0; i < 10000; i++) - { - __asm("nop"); - } - u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & - XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> - XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT); - XCVR_ForceRxWd(); - - XCVR_RX_DIG->RX_DIG_CTRL = t1; - XCVR_RX_DIG->RSSI_CTRL_0 = t2; - XCVR_PHY->CFG1 = t3; - return u8Rssi; -} - -/*! ********************************************************************************* -* XcvrFskSetTxPower -***********************************************************************************/ -void XcvrFskSetTxPower(uint8_t u8TxPow) -{ - return; -} - -/*! ********************************************************************************* -* XcvrFskSetTxChannel -***********************************************************************************/ -void XcvrFskSetTxChannel(uint8_t u8TxChan) -{ - return; -} - -/*! ********************************************************************************* -* XcvrFskRestoreTXControl -* After calling this function user should switch to -* previous protocol and set the protocol channel to default -***********************************************************************************/ -void XcvrFskRestoreTXControl(void) -{ - return; -} - diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h deleted file mode 100644 index 41ecd2e1db15..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h +++ /dev/null @@ -1,164 +0,0 @@ -/*! -* Copyright 2016-2017 NXP -* -* \file -* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* -* o Redistributions of source code must retain the above copyright notice, this list -* of conditions and the following disclaimer. -* -* o Redistributions in binary form must reproduce the above copyright notice, this -* list of conditions and the following disclaimer in the documentation and/or -* other materials provided with the distribution. -* -* o Neither the name of Freescale Semiconductor, Inc. nor the names of its -* contributors may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef __XCVR_TEST_FSK_H__ -#define __XCVR_TEST_FSK_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! ********************************************************************************* -************************************************************************************* -* Public type definitions -************************************************************************************* -********************************************************************************** */ - -/*! ********************************************************************************* -************************************************************************************* -* Public prototypes -************************************************************************************* -********************************************************************************** */ -/*! ********************************************************************************* -* \brief This function returns instant RSSI value and returns it as unsigned byte. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details Initialization of the xcvr is necessary prior to calling this function -* -***********************************************************************************/ -extern uint8_t XcvrFskGetInstantRssi(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into continuous modulated transmission. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details Initialization of the xcvr and calling XcvrFskLoadPattern are necessary -* prior to calling this function -* -***********************************************************************************/ -extern void XcvrFskModTx(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into continuous unmodulated transmission. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskNoModTx(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into idle. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskIdle(void); - -/*! ********************************************************************************* -* \brief This function sets the transceiver into continuous modulated transmission. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details The modulation used is a pseudo-random pattern generated using a LFSR. -* -***********************************************************************************/ -extern void XcvrFskTxRand(void); - -/*! ********************************************************************************* -* \brief This function loads a 32 bit value into the pattern register used by XcvrFskModTx. -* -* \param[in] u32Pattern The pattern to be loaded. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskLoadPattern(uint32_t u32Pattern); - -/*! ********************************************************************************* -* \brief This function gives tx power control to xcvr and sets the power to u8TxPow. -* -* \param[in] u8TxPow Values should be between 0x00 and 0x0F. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskSetTxPower(uint8_t u8TxPow); - -/*! ********************************************************************************* -* \brief This function gives tx channel control to xcvr and sets the channel to u8TxChan. -* -* \param[in] u8TxChan Values should be between 0 and 39. -* -* \ingroup TestFunctions -* -* \details -* -***********************************************************************************/ -extern void XcvrFskSetTxChannel(uint8_t u8TxChan); - -/*! ********************************************************************************* -* \brief This function gives tx channel control and power to the upper layer. -* -* \param[in] None. -* -* \ingroup TestFunctions -* -* \details Call this function only if XcvrFskSetTxChannel or XcvrFskSetTxPower were called -* previously. -* -***********************************************************************************/ -extern void XcvrFskRestoreTXControl(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c deleted file mode 100644 index ac1b843a6219..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.c +++ /dev/null @@ -1,2144 +0,0 @@ -/* -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#include -#include -#include -#include -#include "cpu.h" -#include "fsl_xcvr.h" -#include "fsl_xcvr_trim.h" -#include "ifr_radio.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define channelMapTableSize (128U) -#define gPllDenom_c 0x02000000U /* Denominator is a constant value */ -#define ABS(x) ((x) > 0 ? (x) : -(x)) - -#ifndef TRUE -#define TRUE (true) -#endif - -#ifndef FALSE -#define FALSE (false) -#endif -#define RF_OSCILLATOR_STAYS_ON (false) /* Control whether RF_OSC can be left on all the time. */ -#define RF_OSCILLATOR_READY ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U) - -#ifndef EXTERNAL_CLOCK_GEN -#define EXTERNAL_CLOCK_GEN 0 -#endif - -#define ANT_A 1 -#define ANT_B 0 - -#ifndef XCVR_COEX_RF_ACTIVE_PIN -#define XCVR_COEX_RF_ACTIVE_PIN ANT_B -#endif /* XCVR_COEX_RF_ACTIVE_PIN */ - -typedef struct xcvr_pllChannel_tag -{ - unsigned int integer; - unsigned int numerator; -} xcvr_pllChannel_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address); -void rf_osc_startup(void); -void rf_osc_shutdown(void); -extern double trunc (double); -extern double round (double); - -/******************************************************************************* - * Variables - ******************************************************************************/ -static panic_fptr s_PanicFunctionPtr = NULL; -const xcvr_pllChannel_t mapTable [channelMapTableSize] = -{ - {0x00000025, 0x07C00000}, /* 0 */ - {0x00000025, 0x07C80000}, /* 1 */ - {0x00000025, 0x07D00000}, /* 2 */ - {0x00000025, 0x07D80000}, /* 3 */ - {0x00000025, 0x07E00000}, /* 4 */ - {0x00000025, 0x07E80000}, /* 5 */ - {0x00000025, 0x07F00000}, /* 6 */ - {0x00000025, 0x07F80000}, /* 7 */ - {0x00000025, 0x00000000}, /* 8 */ - {0x00000025, 0x00080000}, /* 9 */ - {0x00000025, 0x00100000}, /* 10 */ - {0x00000025, 0x00180000}, /* 11 */ - {0x00000025, 0x00200000}, /* 12 */ - {0x00000025, 0x00280000}, /* 13 */ - {0x00000025, 0x00300000}, /* 14 */ - {0x00000025, 0x00380000}, /* 15 */ - {0x00000025, 0x00400000}, /* 16 */ - {0x00000025, 0x00480000}, /* 17 */ - {0x00000025, 0x00500000}, /* 18 */ - {0x00000025, 0x00580000}, /* 19 */ - {0x00000025, 0x00600000}, /* 20 */ - {0x00000025, 0x00680000}, /* 21 */ - {0x00000025, 0x00700000}, /* 22 */ - {0x00000025, 0x00780000}, /* 23 */ - {0x00000025, 0x00800000}, /* 24 */ - {0x00000025, 0x00880000}, /* 25 */ - {0x00000025, 0x00900000}, /* 26 */ - {0x00000025, 0x00980000}, /* 27 */ - {0x00000025, 0x00A00000}, /* 28 */ - {0x00000025, 0x00A80000}, /* 29 */ - {0x00000025, 0x00B00000}, /* 30 */ - {0x00000025, 0x00B80000}, /* 31 */ - {0x00000025, 0x00C00000}, /* 32 */ - {0x00000025, 0x00C80000}, /* 33 */ - {0x00000025, 0x00D00000}, /* 34 */ - {0x00000025, 0x00D80000}, /* 35 */ - {0x00000025, 0x00E00000}, /* 36 */ - {0x00000025, 0x00E80000}, /* 37 */ - {0x00000025, 0x00F00000}, /* 38 */ - {0x00000025, 0x00F80000}, /* 39 */ - {0x00000025, 0x01000000}, /* 40 */ - {0x00000026, 0x07080000}, /* 41 */ - {0x00000026, 0x07100000}, /* 42 */ - {0x00000026, 0x07180000}, /* 43 */ - {0x00000026, 0x07200000}, /* 44 */ - {0x00000026, 0x07280000}, /* 45 */ - {0x00000026, 0x07300000}, /* 46 */ - {0x00000026, 0x07380000}, /* 47 */ - {0x00000026, 0x07400000}, /* 48 */ - {0x00000026, 0x07480000}, /* 49 */ - {0x00000026, 0x07500000}, /* 50 */ - {0x00000026, 0x07580000}, /* 51 */ - {0x00000026, 0x07600000}, /* 52 */ - {0x00000026, 0x07680000}, /* 53 */ - {0x00000026, 0x07700000}, /* 54 */ - {0x00000026, 0x07780000}, /* 55 */ - {0x00000026, 0x07800000}, /* 56 */ - {0x00000026, 0x07880000}, /* 57 */ - {0x00000026, 0x07900000}, /* 58 */ - {0x00000026, 0x07980000}, /* 59 */ - {0x00000026, 0x07A00000}, /* 60 */ - {0x00000026, 0x07A80000}, /* 61 */ - {0x00000026, 0x07B00000}, /* 62 */ - {0x00000026, 0x07B80000}, /* 63 */ - {0x00000026, 0x07C00000}, /* 64 */ - {0x00000026, 0x07C80000}, /* 65 */ - {0x00000026, 0x07D00000}, /* 66 */ - {0x00000026, 0x07D80000}, /* 67 */ - {0x00000026, 0x07E00000}, /* 68 */ - {0x00000026, 0x07E80000}, /* 69 */ - {0x00000026, 0x07F00000}, /* 70 */ - {0x00000026, 0x07F80000}, /* 71 */ - {0x00000026, 0x00000000}, /* 72 */ - {0x00000026, 0x00080000}, /* 73 */ - {0x00000026, 0x00100000}, /* 74 */ - {0x00000026, 0x00180000}, /* 75 */ - {0x00000026, 0x00200000}, /* 76 */ - {0x00000026, 0x00280000}, /* 77 */ - {0x00000026, 0x00300000}, /* 78 */ - {0x00000026, 0x00380000}, /* 79 */ - {0x00000026, 0x00400000}, /* 80 */ - {0x00000026, 0x00480000}, /* 81 */ - {0x00000026, 0x00500000}, /* 82 */ - {0x00000026, 0x00580000}, /* 83 */ - {0x00000026, 0x00600000}, /* 84 */ - {0x00000026, 0x00680000}, /* 85 */ - {0x00000026, 0x00700000}, /* 86 */ - {0x00000026, 0x00780000}, /* 87 */ - {0x00000026, 0x00800000}, /* 88 */ - {0x00000026, 0x00880000}, /* 89 */ - {0x00000026, 0x00900000}, /* 90 */ - {0x00000026, 0x00980000}, /* 91 */ - {0x00000026, 0x00A00000}, /* 92 */ - {0x00000026, 0x00A80000}, /* 93 */ - {0x00000026, 0x00B00000}, /* 94 */ - {0x00000026, 0x00B80000}, /* 95 */ - {0x00000026, 0x00C00000}, /* 96 */ - {0x00000026, 0x00C80000}, /* 97 */ - {0x00000026, 0x00D00000}, /* 98 */ - {0x00000026, 0x00D80000}, /* 99 */ - {0x00000026, 0x00E00000}, /* 100 */ - {0x00000026, 0x00E80000}, /* 101 */ - {0x00000026, 0x00F00000}, /* 102 */ - {0x00000026, 0x00F80000}, /* 103 */ - {0x00000026, 0x01000000}, /* 104 */ - {0x00000027, 0x07080000}, /* 105 */ - {0x00000027, 0x07100000}, /* 106 */ - {0x00000027, 0x07180000}, /* 107 */ - {0x00000027, 0x07200000}, /* 108 */ - {0x00000027, 0x07280000}, /* 109 */ - {0x00000027, 0x07300000}, /* 110 */ - {0x00000027, 0x07380000}, /* 111 */ - {0x00000027, 0x07400000}, /* 112 */ - {0x00000027, 0x07480000}, /* 113 */ - {0x00000027, 0x07500000}, /* 114 */ - {0x00000027, 0x07580000}, /* 115 */ - {0x00000027, 0x07600000}, /* 116 */ - {0x00000027, 0x07680000}, /* 117 */ - {0x00000027, 0x07700000}, /* 118 */ - {0x00000027, 0x07780000}, /* 119 */ - {0x00000027, 0x07800000}, /* 120 */ - {0x00000027, 0x07880000}, /* 121 */ - {0x00000027, 0x07900000}, /* 122 */ - {0x00000027, 0x07980000}, /* 123 */ - {0x00000027, 0x07A00000}, /* 124 */ - {0x00000027, 0x07A80000}, /* 125 */ - {0x00000027, 0x07B00000}, /* 126 */ - {0x00000027, 0x07B80000} /* 127 */ -}; - -/* Registers for timing of TX & RX */ -#if RADIO_IS_GEN_3P0 -uint16_t tx_rx_on_delay = TX_RX_ON_DELinit; -uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init; -#else -#if RF_OSC_26MHZ == 1 -uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ; -#else -uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL; -#endif /* RF_OSC_26MHZ == 1 */ -uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL; -#endif /* RADIO_IS_GEN_3P0 */ - -/* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */ -#if RADIO_IS_GEN_3P0 -const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] = -{ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config, - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ - &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config, - &xcvr_MSK_2mbps_config, -}; -#endif /* RADIO_IS_GEN_3P0 */ - -const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] = -{ - &xcvr_BLE_1mbps_config, -#if RADIO_IS_GEN_2P1 - NULL, - NULL, -#else - &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ - &xcvr_ANT_1mbps_config, -#endif /* RADIO_IS_GEN_2P1 */ - &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config, - &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config, - &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config, - &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config, - &xcvr_MSK_1mbps_config, -}; - -const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] = -{ - &xcvr_BLE_1mbps_config, /* Invalid option */ -#if RADIO_IS_GEN_2P1 - NULL, - NULL, -#else - &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */ - &xcvr_ANT_1mbps_config, /* Invalid option */ -#endif /* RADIO_IS_GEN_2P1 */ - &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config, - &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config, - &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config, - &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config, - &xcvr_MSK_500kbps_config, -}; -const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] = -{ - &xcvr_BLE_1mbps_config, /* Invalid option */ -#if RADIO_IS_GEN_2P1 - NULL, - NULL, -#else - &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ - &xcvr_ANT_1mbps_config, /* Invalid option */ -#endif /* RADIO_IS_GEN_2P1 */ - &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config, - &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config, - &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config, - &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config, - &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config, - &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config, - &xcvr_MSK_250kbps_config, -}; - -static xcvr_currConfig_t current_xcvr_config; - -void rf_osc_startup(void) -{ - if (!RF_OSCILLATOR_READY) - { - RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; - } - while (!RF_OSCILLATOR_READY) - { - /* Wait for RF_OSC_READY to be asserted before continuing */ - } -} - -void rf_osc_shutdown(void) -{ - if (!RF_OSCILLATOR_STAYS_ON) - { - RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; - } -} - -/******************************************************************************* - * Code - ******************************************************************************/ -xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) -{ - const xcvr_mode_datarate_config_t * mode_datarate_config; - const xcvr_datarate_config_t * datarate_config ; - const xcvr_mode_config_t * radio_mode_cfg; - const xcvr_common_config_t * radio_common_config; - - xcvrStatus_t status; - - IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = - { - {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/ - {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/ - }; - const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T); - -#ifndef SIMULATION - -#if (EXTERNAL_CLOCK_GEN) - RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */ -#endif /* EXTERNAL_CLOCK_GEN */ - -#if RADIO_IS_GEN_2P0 - RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */ - RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ -#endif /* RADIO_IS_GEN_2P0 */ - - /* Check that this is the proper radio version */ - { - uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT); - - if ( -#if RADIO_IS_GEN_3P0 - (radio_id != 0x5) /* KW3 Gen3 */ -#elif RADIO_IS_GEN_2P1 - (radio_id != 0x5) /* KW35 Gen2.1 */ -#else - (radio_id != 0x3) && /* KW41/31/21 v1 */ - (radio_id != 0xB) /* KW41/31/21 v1.1 */ -#endif /* RADIO_IS_GEN_3P0 */ - ) - { - XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init); - } - } - -#if RADIO_IS_GEN_3P0 - /* Assert Radio Run Request and wait for ack from SPM. */ - RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK; - while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0) - { - } - RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; - rf_osc_startup(); /* Start RF_OSC to allow radio registers access */ -#else - SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; - - /* Load IFR trim values */ - handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); - printf("sw_trim_tbl:\n"); - for (unsigned k = 0; k < NUM_TRIM_TBL_ENTRIES; ++k) { - printf("[%u] id=0x%04x, trim=%" PRIu32 ", valid=%u\n", k, - (unsigned)sw_trim_tbl[k].trim_id, - sw_trim_tbl[k].trim_value, - (unsigned)sw_trim_tbl[k].valid); - } -#endif /* RADIO_IS_GEN_3P0 */ - -#endif /* ifndef SIMULATION */ - - /* Perform the desired XCVR initialization and configuration */ - status = XCVR_GetDefaultConfig(radio_mode, data_rate, &radio_common_config, - &radio_mode_cfg, &mode_datarate_config, &datarate_config); - - if (status == gXcvrSuccess_c) - { - status = XCVR_Configure(radio_common_config, radio_mode_cfg, - mode_datarate_config, datarate_config, 25, XCVR_FIRST_INIT); - current_xcvr_config.radio_mode = radio_mode; - current_xcvr_config.data_rate = data_rate; - } - - return status; -} - -xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, - data_rate_t data_rate, - const xcvr_common_config_t ** com_config, - const xcvr_mode_config_t ** mode_config, - const xcvr_mode_datarate_config_t ** mode_datarate_config, - const xcvr_datarate_config_t ** datarate_config) -{ - xcvrStatus_t status = gXcvrSuccess_c; - /* Common configuration pointer */ - *com_config = (const xcvr_common_config_t *)&xcvr_common_config; - - /* Mode dependent configuration pointer */ - switch (radio_mode) - { -#if !RADIO_IS_GEN_2P1 - case ZIGBEE_MODE: - *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */ - break; - case ANT_MODE: - *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */ - break; -#endif /* !RADIO_IS_GEN_2P1 */ - case BLE_MODE: - *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */ - break; - case GFSK_BT_0p5_h_0p5: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */ - break; - case GFSK_BT_0p5_h_0p32: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */ - break; - case GFSK_BT_0p5_h_0p7: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */ - break; - case GFSK_BT_0p5_h_1p0: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */ - break; - case GFSK_BT_0p3_h_0p5: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */ - break; - case GFSK_BT_0p7_h_0p5: - *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */ - break; - case MSK: - *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */ - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - - /* Data rate dependent and modeXdatarate dependent configuration pointers */ - if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ - { - switch (data_rate) - { -#if RADIO_IS_GEN_3P0 - case DR_2MBPS: - if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE)) - { - status = gXcvrInvalidParameters_c; - } - else - { - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */ - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode]; - } - break; -#endif /* RADIO_IS_GEN_3P0 */ - case DR_1MBPS: - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */ - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode]; - break; - case DR_500KBPS: - if (radio_mode == ZIGBEE_MODE) - { - /* See fsl_xcvr_zgbe_config.c for settings */ -#if !RADIO_IS_GEN_2P1 - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */ -#endif /* !RADIO_IS_GEN_2P1 */ - } - else - { - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */ - } - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode]; - break; - case DR_250KBPS: - *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */ - *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode]; - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - } - - return status; -} - -xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, - const xcvr_mode_config_t *mode_config, - const xcvr_mode_datarate_config_t *mode_datarate_config, - const xcvr_datarate_config_t *datarate_config, - int16_t tempDegC, - XCVR_INIT_MODE_CHG_T first_init) -{ - (void) tempDegC; - xcvrStatus_t config_status = gXcvrSuccess_c; - uint32_t temp; - - /* Turn on the module clocks before doing anything */ -#if RADIO_IS_GEN_3P0 - RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */ -#else - SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; -#endif /* RADIO_IS_GEN_3P0 */ - - /*******************************************************************************/ - /* XCVR_ANA configs */ - /*******************************************************************************/ - - /* Configure PLL Loop Filter */ - if (first_init) - { - XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask; - XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init; - } - - /* Configure VCO KVM */ - XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask; - XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init; - - /* Configure analog filter bandwidth */ - XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask; - XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init; - XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask; - XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init; - -#if RADIO_IS_GEN_2P0 - if (first_init) - { - temp = XCVR_ANA->TX_DAC_PA; - temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; - temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); - XCVR_ANA->TX_DAC_PA = temp; - - temp = XCVR_ANA->BB_LDO_2; - temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; - temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); - XCVR_ANA->BB_LDO_2 = temp; - - temp = XCVR_ANA->RX_LNA; - temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK; - temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1); - XCVR_ANA->RX_LNA = temp; - - temp = XCVR_ANA->BB_LDO_1; - temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK; - temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1); - XCVR_ANA->BB_LDO_1 = temp; - } -#endif /* RADIO_IS_GEN_2P0 */ - - /*******************************************************************************/ - /* XCVR_MISC configs */ - /*******************************************************************************/ - temp = XCVR_MISC->XCVR_CTRL; - temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); - temp |= mode_config->xcvr_ctrl.init; - -#if RF_OSC_26MHZ == 1 - { - temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); - } -#endif /* RF_OSC_26MHZ == 1 */ - - XCVR_MISC->XCVR_CTRL = temp; - -#if RADIO_IS_GEN_2P1 - XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK; -#endif /* RADIO_IS_GEN_2P1 */ - - /*******************************************************************************/ - /* XCVR_PHY configs */ - /*******************************************************************************/ -#if RADIO_IS_GEN_3P0 - XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0; - XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1; - XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg; - XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate; - XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl; -#else - XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init; - XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init; - XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init; - XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; - XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init; - XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */ -#endif /* RADIO_IS_GEN_3P0 */ - - /*******************************************************************************/ - /* XCVR_PLL_DIG configs */ - /*******************************************************************************/ - if (first_init) - { - XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump; - XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl; - XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map; - XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect; - XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl; -#if !RADIO_IS_GEN_2P1 - XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl; -#endif /* !RADIO_IS_GEN_2P1 */ - XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res; - XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl; - XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1; - XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match; - XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl; - } - - /*******************************************************************************/ - /* XCVR_RX_DIG configs */ - /*******************************************************************************/ - - /* Configure RF Aux PLL for proper operation based on external clock frequency */ - if (first_init) - { - temp = XCVR_ANA->RX_AUXPLL; - temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK; -#if RF_OSC_26MHZ == 1 - { - temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4); - } -#else - { - temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7); - } -#endif /* RF_OSC_26MHZ == 1 */ - XCVR_ANA->RX_AUXPLL = temp; - } - - /* Configure RX_DIG_CTRL */ -#if RF_OSC_26MHZ == 1 - { - temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ - mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */ - datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */ - } -#else - { - temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ - mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */ - datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */ - 0; /* Always disable the sample rate converter for 32MHz */ - } -#endif /* RF_OSC_26MHZ == 1 */ - - temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */ - XCVR_RX_DIG->RX_DIG_CTRL = temp; - - /* DCOC_CAL_IIR */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz; - } -#else - { - XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - /* DC_RESID_CTRL */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; - } -#else - { - XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - /* DCOC_CTRL_0 & _1 */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ -#if RADIO_IS_GEN_3P0 - XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz; -#endif /* RADIO_IS_GEN_3P0 */ - - /* customize DCOC_CTRL_0 settings for Gen2 GFSK BT=0.5, h=0.32 */ -#if RADIO_IS_GEN_2P0 - if ((mode_config->radio_mode == ANT_MODE) || (mode_config->radio_mode == GFSK_BT_0p5_h_0p32)) - { - if (datarate_config->data_rate == DR_1MBPS) /* only apply fix to 1Mbps data rates */ - { - /* apply the changes to the DCOC_CTRL_0 register XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME */ - temp = XCVR_RX_DIG->DCOC_CTRL_0; - temp &= ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK; - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(0x10) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(0x0C); - XCVR_RX_DIG->DCOC_CTRL_0 = temp; - } - } -#endif /* RADIO_IS_GEN_2P0 */ - - } -#else - { - XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ -#if RADIO_IS_GEN_3P0 - XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz; -#endif /* RADIO_IS_GEN_3P0 */ - } -#endif /* RF_OSC_26MHZ == 1 */ - if (first_init) - { - /* DCOC_CAL_GAIN */ - XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init; - - /* DCOC_CAL_RCP */ - XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init; - XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0; - XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4; - XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8; - XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0; - XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8; - - /* LNA_GAIN_LIN_VAL */ - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init; - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init; - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init; - XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init; - - /* BBA_RES_TUNE_LIN_VAL */ - XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init; - XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init; - XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init; - - /* BBA_STEP */ - XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init; - - /* DCOC_TZA_STEP */ - XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init; - XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init; - XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init; - XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init; - XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init; - XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init; - XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init; - XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init; - XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init; - XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init; - XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init; - -#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) - /* DCOC_CAL_FAIL and DCOC_CAL_PASS */ - XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init; - XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init; -#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ - } - - /* AGC_CTRL_0 .. _3 */ - XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init; - -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz; - } -#else - { - XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ - XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - if (first_init) - { - XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init; - - /* AGC_GAIN_TBL_** */ - XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init; - XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init; - XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init; - XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init; - XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init; - XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init; - XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init; - - /* RSSI_CTRL_0 */ - XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init; - -#if RADIO_IS_GEN_3P0 - XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init; -#endif /* RADIO_IS_GEN_3P0 */ - - /* CCA_ED_LQI_0 and _1 */ - XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init; - XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init; - } - - /* Channel filter coefficients */ -#if RF_OSC_26MHZ == 1 - { - XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0; - XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1; - XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2; - XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3; - XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4; - XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5; - XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6; - XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7; - XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8; - XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9; - XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10; - XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11; - } -#else - { - XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0; - XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1; - XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2; - XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3; - XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4; - XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5; - XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6; - XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7; - XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8; - XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9; - XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10; - XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11; - } -#endif /* RF_OSC_26MHZ == 1 */ - - XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0; - XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1; - - /*******************************************************************************/ - /* XCVR_TSM configs */ - /*******************************************************************************/ - XCVR_TSM->CTRL = com_config->tsm_ctrl; - -#if RADIO_IS_GEN_2P0 - if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE)) - { - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; - } -#endif /* RADIO_IS_GEN_2P0 */ - - if (first_init) - { -#if !RADIO_IS_GEN_2P1 - XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */ -#endif /* !RADIO_IS_GEN_2P1 */ - - XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init; - /* TSM registers and timings - dependent upon clock frequency */ -#if RF_OSC_26MHZ == 1 - { - XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz; - XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz; - XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz; - XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz; - XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz; - XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz; - XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz; - XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz; - XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz; - XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz; - XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz; - XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz; - XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz; - XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz; - XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz; - XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz; - XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz; - XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz; - XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz; - XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz; - XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz; - XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz; - } -#else - { - XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz; - XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz; - XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz; - XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz; - XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz; - XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz; - XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz; - XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz; - XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz; - XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz; - XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz; - XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz; - XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz; - XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz; - XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz; - XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz; - XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz; - XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz; - XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz; - XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz; - XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz; - XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - /* TSM timings independent of clock frequency */ - XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init; - XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init; - XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init; - XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init; - XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init; - XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init; - XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init; - XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init; - XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init; - XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init; - XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init; - XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init; - XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init; - XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init; - XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init; - XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init; - XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init; - XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init; - XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init; - XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; - XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init; - XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init; - XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init; - XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init; - XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init; - XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init; - XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init; - XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init; - XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; - XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; - XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; - -#if RF_OSC_26MHZ == 1 - { - XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | - XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ); - } -#else - { - XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | - XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) | - XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD); - } -#endif /* RF_OSC_26MHZ == 1 */ - - XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; - XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; - -#if RADIO_IS_GEN_3P0 - XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init; - XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init; - - /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */ -#if (PA_RAMP_TIME == 4) - XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */ - XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */ - XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */ - XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */ - XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */ - XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */ - XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */ - XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */ - XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */ - XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */ - XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */ - XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */ - XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ - XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */ - XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ - XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */ - XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */ - XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */ - XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */ - temp = XCVR_TSM->TIMING14; - temp &= 0xFFFF0000; - temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ - XCVR_TSM->TIMING14 = temp; -#endif /* (PA_RAMP_TIME == 4) */ -#endif /* RADIO_IS_GEN_3P0 */ - } - -#if RADIO_IS_GEN_3P0 - if (mode_config->radio_mode == ZIGBEE_MODE) - { - temp = XCVR_TSM->TIMING35; - temp &= ~(B0(0xFF)); - if (DATA_PADDING_EN == 1) - { - temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */ - } - else - { - temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */ - } - XCVR_TSM->TIMING35 = temp; - } -#else - - if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS))) - { - /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */ - XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */ - } - else - { - XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ - } -#endif /* RADIO_IS_GEN_3P0 */ - - /*******************************************************************************/ - /* XCVR_TX_DIG configs */ - /*******************************************************************************/ -#if RF_OSC_26MHZ == 1 - { - XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ - XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz; - XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz; - } -#else - { - XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ - XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz; - XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz; - } -#endif /* RF_OSC_26MHZ == 1 */ - - if (first_init) - { - XCVR_TX_DIG->CTRL = com_config->tx_ctrl; - XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; - XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; - -#if !RADIO_IS_GEN_2P1 - XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; - XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; -#endif /* !RADIO_IS_GEN_2P1 */ - } - - XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; - -#ifndef SIMULATION -#if (TRIM_BBA_DCOC_DAC_AT_INIT) - if (first_init) - { - uint32_t end_of_rx_wu = 0; - XCVR_ForceRxWu(); - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ - temp = XCVR_TSM->END_OF_SEQ; - end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; - - //~ if (!rx_bba_dcoc_dac_trim_shortIQ()) - if (!rx_bba_dcoc_dac_trim_DCest()) - { - config_status = gXcvrTrimFailure_c; - } - DCOC_DAC_INIT_Cal(0); - XCVR_ForceRxWd(); - } -#endif /* TRIM_BBA_DCOC_DAC_AT_INIT */ -#endif /* ifndef SIMULATION */ - return config_status; -} - -void XCVR_Reset(void) -{ -#if RADIO_IS_GEN_3P0 -#else - RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */ - RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */ - RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */ -#endif /* RADIO_IS_GEN_3P0 */ -} - -xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */ -{ - xcvrStatus_t status; - const xcvr_mode_datarate_config_t * mode_datarate_config; - const xcvr_datarate_config_t * datarate_config ; - const xcvr_mode_config_t * radio_mode_cfg; - const xcvr_common_config_t * radio_common_config; - - status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config ); - - if (status == gXcvrSuccess_c) - { - status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, - (const xcvr_mode_config_t *)radio_mode_cfg, - (const xcvr_mode_datarate_config_t *)mode_datarate_config, - (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE); - current_xcvr_config.radio_mode = new_radio_mode; - current_xcvr_config.data_rate = new_data_rate; - } - - return status; -} - -void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable ) -{ - if (IIRnbEnable) - { - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; - } - else - { - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; - } -} - -xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) -{ - double integer_used_in_Hz, - integer_used_in_LSB, - numerator_fraction, - numerator_in_Hz, - numerator_in_LSB, - numerator_unrounded, - real_int_and_fraction, - real_fraction, - requested_freq_in_LSB, - sdm_lsb; - uint32_t temp; - static uint32_t integer_truncated, - integer_to_use; - static int32_t numerator_rounded; - - /* Configure for Coarse Tune */ - uint32_t coarse_tune_target = freq / 1000000; - - temp = XCVR_PLL_DIG->CTUNE_CTRL; - temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK; - temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target); - XCVR_PLL_DIG->CTUNE_CTRL = temp; - - /* Calculate the Low Port values */ - sdm_lsb = refOsc / 131072.0; - - real_int_and_fraction = freq / (refOsc * 2.0); - - integer_truncated = (uint32_t) trunc(real_int_and_fraction); - - real_fraction = real_int_and_fraction - integer_truncated; - - if (real_fraction > 0.5) - { - integer_to_use = integer_truncated + 1; - } - else - { - integer_to_use = integer_truncated; - } - - numerator_fraction = real_int_and_fraction - integer_to_use; - - integer_used_in_Hz = integer_to_use * refOsc * 2; - integer_used_in_LSB = integer_used_in_Hz / sdm_lsb; - - numerator_in_Hz = numerator_fraction * refOsc * 2; - numerator_in_LSB = numerator_in_Hz / sdm_lsb; - - requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB; - - numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256; - - numerator_rounded = (int32_t)round(numerator_unrounded); - - /* Write the Low Port Integer and Numerator */ - temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; - temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; - temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | - XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK); - XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; - - XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded; - - return gXcvrSuccess_c; -} - -void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */ -{ - s_PanicFunctionPtr = fptr; -} - -void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address) -{ - if ( s_PanicFunctionPtr != NULL) - { - s_PanicFunctionPtr(panic_id, panic_address, 0, 0); - } - else - { - volatile uint8_t dummy = 0; - - while(1) - { - ++dummy; - } - } -} - -healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */ -{ - return (healthStatus_t)NO_ERRORS; -} - -void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control) -{ - (void) control; -} - -/* Helper function to map radio mode to LL usage */ -link_layer_t map_mode_to_ll(radio_mode_t mode) -{ - link_layer_t llret; - switch (mode) - { - case BLE_MODE: - llret = BLE_LL; - break; - case ZIGBEE_MODE: - llret = ZIGBEE_LL; - break; - case ANT_MODE: - llret = ANT_LL; - break; - case GFSK_BT_0p5_h_0p5: - case GFSK_BT_0p5_h_0p32: - case GFSK_BT_0p5_h_0p7: - case GFSK_BT_0p5_h_1p0: - case GFSK_BT_0p3_h_0p5: - case GFSK_BT_0p7_h_0p5: - case MSK: - llret = GENFSK_LL; - break; - default: - llret = UNASSIGNED_LL; - break; - } - return llret; -} - -#if RADIO_IS_GEN_3P0 -void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address) -{ - XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address; -} - -uint32_t XCVR_GetBSM_NTW_Address(void) -{ - return XCVR_PHY->NTW_ADR_BSM; -} -#endif /* RADIO_IS_GEN_3P0 */ - -/* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */ -xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping) -{ - link_layer_t int0 = map_mode_to_ll(irq0_mapping); - link_layer_t int1 = map_mode_to_ll(irq1_mapping); - xcvrStatus_t statusret; - /* Make sure the two LL's requested aren't the same */ - if (int0 == int1) - { - statusret = gXcvrInvalidParameters_c; - } - else - { - uint32_t temp; - temp = XCVR_MISC->XCVR_CTRL; - temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK); - temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1)); - XCVR_MISC->XCVR_CTRL = temp; - statusret = gXcvrSuccess_c; - } - return statusret; -} - -/* Get current state of IRQ mapping for either radio INT0 or INT1 */ -link_layer_t XCVR_GetIRQMapping(uint8_t int_num) -{ - if (int_num == 0) - { - return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT); - } - else - { - return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT); - } -} - -/* Get current state of radio mode and data rate */ -xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config) -{ - xcvrStatus_t status = gXcvrInvalidParameters_c; - if (curr_config != NULL) - { - curr_config->radio_mode = current_xcvr_config.radio_mode; - curr_config->data_rate = current_xcvr_config.data_rate; - status = gXcvrSuccess_c; - } - return status; -} - -/* Customer level trim functions */ -xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim) -{ - xcvrStatus_t status = gXcvrInvalidParameters_c; - - if ((xtalTrim & 0x80) == 0) - { - uint32_t temp; - temp = RSIM->ANA_TRIM; - temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK; - RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim); - status = gXcvrSuccess_c; - } - return status; -} - -uint8_t XCVR_GetXtalTrim(void) -{ - uint8_t temp_xtal; - temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT); - return temp_xtal; -} - -/* RSSI adjustment */ -xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj) -{ - XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK; - XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj); - return gXcvrSuccess_c; -} - -int8_t XCVR_GetRssiAdjustment(void) -{ - int8_t adj; - adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT; - return adj; -} - -/* Radio debug functions */ -xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) -{ - uint32_t temp; - - if (channel == 0xFF) - { - /* Clear all of the overrides and restore to LL channel control */ - temp = XCVR_PLL_DIG->CHAN_MAP; - temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK -#endif /* !RADIO_IS_GEN_2P1 */ -#if RADIO_IS_GEN_3P0 - | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK -#endif /* RADIO_IS_GEN_3P0 */ - ); - - XCVR_PLL_DIG->CHAN_MAP = temp; - - /* Stop using the manual frequency setting */ - XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; - - return gXcvrSuccess_c; - } - - if (channel >= 128) - { - return gXcvrInvalidParameters_c; - } - - if (useMappedChannel) - { - temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */ - - switch (temp) - { -#if !RADIO_IS_GEN_2P1 - case 0x3: /* ANT protocol */ - ANT->CHANNEL_NUM = channel; - break; -#endif /* !RADIO_IS_GEN_2P1 */ - case 0x8: /* GENFSK protocol */ - case 0x9: /* MSK protocol */ - GENFSK->CHANNEL_NUM = channel; - break; - default: /* All other protocols */ - temp = XCVR_PLL_DIG->CHAN_MAP; - temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK -#if RADIO_IS_GEN_3P0 - | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK -#endif /* RADIO_IS_GEN_3P0 */ - ); - temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK -#endif /* !RADIO_IS_GEN_2P1 */ - ); - XCVR_PLL_DIG->CHAN_MAP = temp; - break; - } - } - else - { - XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK -#if !RADIO_IS_GEN_2P1 - | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK -#endif /* !RADIO_IS_GEN_2P1 */ - ); - - XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c); - XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); - - temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; - temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; - temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer); - XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; - - /* Stop using the LL channel map and use the manual frequency setting */ - XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; - } - - return gXcvrSuccess_c; -} - -uint32_t XCVR_GetFreq ( void ) -{ - uint32_t pll_int; - uint32_t pll_num_unsigned; - int32_t pll_num; - uint32_t pll_denom; - float freq_float; - - if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */ - { - pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >> - XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT; - - pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2; - pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3; - } - else - { - /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */ - pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >> - XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT; - - pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1; - pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2; - } - - uint32_t freq = 0; - -#if RF_OSC_26MHZ == 1 - uint32_t ref_clk = 26U; -#else - uint32_t ref_clk = 32U; -#endif /* RF_OSC_26MHZ == 1 */ - - printf("pll_num_unsigned = %08" PRIx32 "\n", pll_num_unsigned); - /* Check if sign bit is asserted */ - if (pll_num_unsigned & 0x04000000U) - { - /* Sign extend the numerator */ - pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; - printf("pll_num = %" PRIu32 ", pll_denom = %" PRIu32 "\n", pll_num, pll_denom); - - /* Calculate the frequency in MHz */ - freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); - } - else - { - /* Calculate the frequency in MHz */ - pll_num = pll_num_unsigned; - printf("pll_num = %" PRIu32 ", pll_denom = %" PRIu32 "\n", pll_num, pll_denom); - freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); - } - printf("freq_float = %f\n", freq_float); - - freq = (uint32_t)freq_float; - - return freq; -} - -void XCVR_ForceRxWu(void) -{ - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK; -} - -void XCVR_ForceRxWd(void) -{ - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK; -} - -void XCVR_ForceTxWu(void) -{ - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -void XCVR_ForceTxWd(void) -{ - XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; -} - -xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol) -{ - uint32_t temp; - if ((protocol != 6) && (protocol != 7)) - { - return gXcvrInvalidParameters_c; /* Failure */ - } - - if ((rf_channel_freq < 2360) || (rf_channel_freq >2487)) - { - return gXcvrInvalidParameters_c; /* failure */ - } - - /* Set the DFT Mode */ - temp = XCVR_TX_DIG->CTRL; - temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK; - temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1); - XCVR_TX_DIG->CTRL = temp; - - /* Choose Protocol 6 or 7 if using the Channel Number register */ - temp = XCVR_MISC->XCVR_CTRL; - temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK; - temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol); - XCVR_MISC->XCVR_CTRL = temp; - - /* Select the RF Channel, using the Channel Number register */ - XCVR_OverrideChannel(rf_channel_freq-2360,1); - - /* Warm-up the Radio */ - XCVR_ForceTxWu(); - - return gXcvrSuccess_c; /* Success */ -} - -xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern) -{ - uint32_t temp; - uint8_t dft_mode = 0; - uint8_t dft_clk_sel = 0; - xcvrStatus_t status = gXcvrSuccess_c; - - XCVR_ChangeMode(radio_mode, data_rate); - - /* Select the RF Channel, using the Channel Number register */ - XCVR_OverrideChannel(channel_num, 1); - - switch (radio_mode) - { - case ZIGBEE_MODE: - dft_mode = 6; /* OQPSK configuration */ - break; - case ANT_MODE: - case BLE_MODE: - case GFSK_BT_0p5_h_0p5: - case GFSK_BT_0p5_h_0p32: - case GFSK_BT_0p5_h_0p7: - case GFSK_BT_0p5_h_1p0: - case GFSK_BT_0p3_h_0p5: - case GFSK_BT_0p7_h_0p5: - dft_mode = 2; /* GFSK configuration */ - break; - case MSK: - dft_mode = 4; /* MSK configuration */ - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - - if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ - { - switch (data_rate) - { - case DR_1MBPS: - dft_clk_sel = 4; - break; - case DR_500KBPS: - dft_clk_sel = 3; - break; - case DR_250KBPS: - dft_clk_sel = 2; - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - } - - temp = XCVR_TX_DIG->CTRL; - temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK); - temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | - XCVR_TX_DIG_CTRL_TX_DFT_EN(1) | - XCVR_TX_DIG_CTRL_LFSR_EN(0); - XCVR_TX_DIG->CTRL = temp; - - XCVR_TX_DIG->DFT_PATTERN = tx_pattern; - - if (status == gXcvrSuccess_c) - { - /* Warm-up the Radio */ - XCVR_ForceTxWu(); - } - - return status; -} - -xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length) -{ - uint32_t temp; - uint8_t dft_mode = 0; - uint8_t dft_clk_sel = 0; - xcvrStatus_t status = gXcvrSuccess_c; - uint8_t bitrate_setting = 0xFF; - - if (lfsr_length > 5) - { - return gXcvrInvalidParameters_c; - } - - XCVR_ChangeMode(radio_mode, data_rate); - - /* Select the RF Channel, using the Channel Number register */ - XCVR_OverrideChannel(channel_num, 1); - - switch (radio_mode) - { - case ZIGBEE_MODE: - dft_mode = 7; /* OQPSK configuration */ - break; - case ANT_MODE: - case BLE_MODE: - case GFSK_BT_0p5_h_0p5: - case GFSK_BT_0p5_h_0p32: - case GFSK_BT_0p5_h_0p7: - case GFSK_BT_0p5_h_1p0: - case GFSK_BT_0p3_h_0p5: - case GFSK_BT_0p7_h_0p5: - dft_mode = 3; /* GFSK configuration */ - bitrate_setting = data_rate; - break; - case MSK: - dft_mode = 5; /* MSK configuration */ - break; - - default: - status = gXcvrInvalidParameters_c; - break; - } - - if (status == gXcvrSuccess_c) - { - switch (data_rate) - { - case DR_1MBPS: - dft_clk_sel = 4; - break; - case DR_500KBPS: - dft_clk_sel = 3; - break; - case DR_250KBPS: - dft_clk_sel = 2; - break; - default: - status = gXcvrInvalidParameters_c; - break; - } - } - - if (bitrate_setting < 4) - { - GENFSK->BITRATE = bitrate_setting; - } - - temp = XCVR_TX_DIG->CTRL; - temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | - XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | - XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | - XCVR_TX_DIG_CTRL_LFSR_EN_MASK); - temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | - XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | - XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | - XCVR_TX_DIG_CTRL_TX_DFT_EN(0) | - XCVR_TX_DIG_CTRL_LFSR_EN(1); - XCVR_TX_DIG->CTRL = temp; - - if (status == gXcvrSuccess_c) - { - /* Warm-up the Radio */ - XCVR_ForceTxWu(); - } - - return status; -} - -void XCVR_DftTxOff(void) -{ - XCVR_ForceTxWd(); - XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */ - /* Clear the RF Channel over-ride */ - XCVR_OverrideChannel(0xFF,1); - XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */ - XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */ - XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */ - XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */ -} - -xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) -{ - if (pa_power > 0x3F) - { - return gXcvrInvalidParameters_c; /* Failure */ - } - - if (pa_power != 1) - { - pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */ - } - - XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */ - XCVR_TSM->PA_POWER = pa_power; - - return gXcvrSuccess_c; /* Success */ -} - -xcvrStatus_t XCVR_CoexistenceInit(void) -{ -#if gMWS_UseCoexistence_d - uint32_t temp = 0x00U; - uint32_t end_of_tx_wu = 0x00U; - uint32_t end_of_rx_wu = 0x00U; - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - uint32_t tsm_timing47 = 0x00U; -#else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */ - uint32_t tsm_timing48 = 0x00U; -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - uint32_t tsm_timing50 = 0x00U; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en) - uint32_t tsm_timing48 = 0x00U; - // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en) - uint32_t tsm_timing47 = 0x00U; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - - uint16_t tsm_timing43_rx = 0x00; - uint16_t tsm_timing43_tx = 0x00; - - /* Select GPIO mode for FAD pins */ - temp = XCVR_MISC->FAD_CTRL; - temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK); - XCVR_MISC->FAD_CTRL = temp; - - /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ - end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; - end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - -/***************** - * TX SEQUENCE * - *****************/ - - if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_tx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - - /* Save the TX RF_ACTIVE start time. */ - tsm_timing43_tx = end_of_tx_wu - temp; - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#else - tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ - tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - -/***************** - * RX SEQUENCE * - *****************/ - - if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_rx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - - /* Save the RX RF_ACTIVE start time. */ - tsm_timing43_rx = end_of_rx_wu - temp; - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); -#else - tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ - tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); - -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - temp = XCVR_TSM->TIMING47; - temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; -#else - temp = XCVR_TSM->TIMING48; - temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing48; - XCVR_TSM->TIMING48 = temp; -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ - - temp = XCVR_TSM->TIMING50; - temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); - temp |= tsm_timing50; - XCVR_TSM->TIMING50 = temp; - -#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) - GPIOC->PDDR |= 0x18; - PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); -#else - GPIOC->PDDR |= 0x0A; - PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); -#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ - -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ - tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - - /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ - tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - - /* RF_ACTIVE */ - temp = XCVR_TSM->TIMING48; - temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing48; - XCVR_TSM->TIMING48 = temp; - - /* RF_PRIORITY */ - temp = XCVR_TSM->TIMING47; - temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); - temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; - - /* Overwrite pins settings */ - GPIOC->PDDR |= 0x12; - PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); - PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - - tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d; - - if (tsm_timing43_tx > end_of_tx_wu - 1) - { - tsm_timing43_tx = end_of_tx_wu - 1; - } - - tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d; - - if (tsm_timing43_rx > end_of_rx_wu - 1) - { - tsm_timing43_rx = end_of_rx_wu - 1; - } - - XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) | - (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | - (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) | - (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)); - - BTLE_RF->MISC_CTRL = 0x02; - - XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK; - - /* Save the updated registers values. */ - XCVR_CoexistenceSaveRestoreTimings(1); -#endif /* gMWS_UseCoexistence_d */ - - return gXcvrSuccess_c; -} - -xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority) -{ -#if gMWS_UseCoexistence_d - uint32_t temp = 0x00U; - uint32_t end_of_tx_wu = 0x00U; - uint32_t end_of_rx_wu = 0x00U; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - uint32_t tsm_timing50 = 0x00U; -#endif -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - uint32_t tsm_timing47 = 0x00U; -#endif - - /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ - end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; - end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; - -/***************** - * RX * - *****************/ - - if (XCVR_COEX_HIGH_PRIO == rxPriority) - { - if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_rx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */ - tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */ - tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - else - { - /* Low priority RX */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - -/***************** - * TX * - *****************/ - if (XCVR_COEX_HIGH_PRIO == txPriority) - { - if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) - { - temp = end_of_tx_wu; - } - else - { - temp = gMWS_CoexRfActiveAssertTime_d; - } - - /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - else - { -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ - tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ - tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) | - ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)); -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - } - -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - temp = XCVR_TSM->TIMING50; - temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | - XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); - temp |= tsm_timing50; - XCVR_TSM->TIMING50 = temp; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ -#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) - temp = XCVR_TSM->TIMING47; - temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK | - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK | - XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK); - temp |= tsm_timing47; - XCVR_TSM->TIMING47 = temp; -#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ - - /* Save the updated registers values. */ - XCVR_CoexistenceSaveRestoreTimings(1); -#else /* gMWS_UseCoexistence_d */ - (void) rxPriority; - (void) txPriority; -#endif /* gMWS_UseCoexistence_d */ - - return gXcvrSuccess_c; -} - -xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) -{ -#if gMWS_UseCoexistence_d - static uint32_t tsm_ovrd0_saved = 0x00; - static uint32_t tsm_ovrd1_saved = 0x00; - static uint32_t tsm_ovrd2_saved = 0x00; - static uint32_t tsm_ovrd3_saved = 0x00; - static uint32_t tsm_timing47_saved = 0x00; - static uint32_t tsm_timing48_saved = 0x00; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - static uint32_t tsm_timing49_saved = 0x00; - static uint32_t tsm_timing50_saved = 0x00; -#endif - - if (saveTimings == 0) - { - /* Restore registers values. */ - XCVR_TSM->OVRD0 = tsm_ovrd0_saved; - XCVR_TSM->OVRD1 = tsm_ovrd1_saved; - XCVR_TSM->OVRD2 = tsm_ovrd2_saved; - XCVR_TSM->OVRD3 = tsm_ovrd3_saved; - - XCVR_TSM->TIMING47 = tsm_timing47_saved; - XCVR_TSM->TIMING48 = tsm_timing48_saved; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - XCVR_TSM->TIMING49 = tsm_timing49_saved; - XCVR_TSM->TIMING50 = tsm_timing50_saved; -#endif - } - else - { - /* Save registers values. */ - tsm_ovrd0_saved = XCVR_TSM->OVRD0; - tsm_ovrd1_saved = XCVR_TSM->OVRD1; - tsm_ovrd2_saved = XCVR_TSM->OVRD2; - tsm_ovrd3_saved = XCVR_TSM->OVRD3; - tsm_timing47_saved = XCVR_TSM->TIMING47; - tsm_timing48_saved = XCVR_TSM->TIMING48; -#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) - tsm_timing49_saved = XCVR_TSM->TIMING49; - tsm_timing50_saved = XCVR_TSM->TIMING50; -#endif - } -#else /* gMWS_UseCoexistence_d */ - (void) saveTimings; -#endif /* gMWS_UseCoexistence_d */ - - return gXcvrSuccess_c; -} diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h index 1994e59a8a88..02e3c96b4fd0 100644 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h +++ b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr.h @@ -1,52 +1,45 @@ /* -* The Clear BSD License -* Copyright (c) 2015, Freescale Semiconductor, Inc. -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #ifndef _FSL_XCVR_H_ /* clang-format off */ #define _FSL_XCVR_H_ /* clang-format on */ #include "cpu.h" -#include "fsl_xcvr_trim.h" -#if defined(gMWS_UseCoexistence_d) -#if gMWS_UseCoexistence_d -#include "MWS.h" -#endif /* gMWS_UseCoexistence_d */ -#else -#define gMWS_UseCoexistence_d 0 -#endif /* defined(gMWS_UseCoexistence_d) */ + /*! * @addtogroup xcvr * @{ @@ -60,16 +53,9 @@ /* KW4xZ/KW3xZ/KW2xZ Radio type */ #define RADIO_IS_GEN_2P0 (1) -/* Default RF OSC definition. Allows for compile time clock frequency definition */ -#ifdef CLOCK_MAIN - -#else -#if RF_OSC_26MHZ == 1 -#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */ -#else -#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ -#endif /* RF_OSC_26MHZ == 1 */ -#endif /* CLOCK_MAIN */ +#if (CLOCK_RADIOXTAL == 26000000ul) +#define RF_OSC_26MHZ 1 +#endif #define TBD_ZERO (0) #define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) @@ -420,7 +406,7 @@ typedef enum _ext_clock_config } ext_clock_config_t; /*! @brief Radio operating mode setting types. */ -typedef enum _radio_mode +typedef enum { BLE_MODE = 0, ZIGBEE_MODE = 1, @@ -441,7 +427,7 @@ typedef enum _radio_mode } radio_mode_t; /*! @brief Link layer types. */ -typedef enum _link_layer +typedef enum { BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */ ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */ @@ -451,7 +437,7 @@ typedef enum _link_layer } link_layer_t; /*! @brief Data rate selections. */ -typedef enum _data_rate +typedef enum { DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ @@ -462,48 +448,11 @@ typedef enum _data_rate DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ } data_rate_t; -/*! @brief Control settings for Fast Antenna Diversity */ -typedef enum _FAD_LPPS_CTRL -{ - NONE = 0, - FAD_ENABLED = 1, - LPPS_ENABLED = 2 -} FAD_LPPS_CTRL_T; - -/*! @brief XCVR Panic codes for indicating panic reason. */ -typedef enum _XCVR_PANIC_ID -{ - WRONG_RADIO_ID_DETECTED = 1, - CALIBRATION_INVALID = 2, - RADIO_INIT_FAILURE = 3, -} XCVR_PANIC_ID_T; - -/*! @brief Initialization or mode change selection for config routine. */ -typedef enum _XCVR_INIT_MODE_CHG -{ - XCVR_MODE_CHANGE = 0, - XCVR_FIRST_INIT = 1, -} XCVR_INIT_MODE_CHG_T; - -/*! @brief Coexistence arbitration priority settings. */ -typedef enum _XCVR_COEX_PRIORITY -{ - XCVR_COEX_LOW_PRIO = 0, - XCVR_COEX_HIGH_PRIO = 1 -} XCVR_COEX_PRIORITY_T; - -/*! @brief Current configuration of the radio. */ -typedef struct xcvr_currConfig_tag -{ - radio_mode_t radio_mode; - data_rate_t data_rate; -} xcvr_currConfig_t; - /*! * @brief XCVR RX_DIG channel filter coefficient storage * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage. */ -typedef struct _xcvr_rx_chf_coeffs +typedef struct { uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */ uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */ @@ -523,7 +472,7 @@ typedef struct _xcvr_rx_chf_coeffs * @brief XCVR masked init type for 32 bit registers * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position. */ -typedef struct _xcvr_masked_init_32 +typedef struct { uint32_t mask; uint32_t init; @@ -532,7 +481,7 @@ typedef struct _xcvr_masked_init_32 /*! * @brief XCVR common configure structure */ -typedef struct _xcvr_common_config +typedef struct { /* XCVR_ANA configs */ xcvr_masked_init_32_t ana_sy_ctrl1; @@ -706,7 +655,7 @@ typedef struct _xcvr_common_config } xcvr_common_config_t; /*! @brief XCVR mode specific configure structure (varies by radio mode) */ -typedef struct _xcvr_mode_config +typedef struct { radio_mode_t radio_mode; uint32_t scgc5_clock_ena_bits; @@ -752,7 +701,7 @@ typedef struct _xcvr_mode_config * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. */ -typedef struct _xcvr_mode_datarate_config +typedef struct { radio_mode_t radio_mode; data_rate_t data_rate; @@ -786,7 +735,7 @@ typedef struct _xcvr_mode_datarate_config * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. */ -typedef struct _xcvr_datarate_config +typedef struct { data_rate_t data_rate; @@ -871,364 +820,10 @@ extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config; extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config; extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; -/******************************************************************************* - * API - ******************************************************************************/ - #ifdef __cplusplus extern "C" { #endif -/*! - * @name XCVR functional Operation - * @{ - */ - -/*! - * @brief Initializes an XCVR instance. - * - * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to - * start up the XCVR in most situations. - * - * @param radio_mode The radio mode for which the XCVR should be configured. - * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions. - */ -xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); - -/*! - * @brief Initializes XCVR configure structure. - * - * This function updates pointers to the XCVR configure structures with default values. - * The configurations are divided into a common structure, a set of radio mode specific - * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at - * each datarate), and a set of data rate specific structures. - * The pointers provided by this routine point to const structures which can be - * copied to variable structures if changes to settings are required. - * - * @param radio_mode [in] The radio mode for which the configuration structures are requested. - * @param data_rate [in] The data rate for which the configuration structures are requested. - * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure. - * @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure. - * @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure. - * @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure. - * @return 0 success, others failure - * @see XCVR_Configure - */ -xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, - data_rate_t data_rate, - const xcvr_common_config_t ** com_config, - const xcvr_mode_config_t ** mode_config, - const xcvr_mode_datarate_config_t ** mode_datarate_config, - const xcvr_datarate_config_t ** datarate_config); - -/*! - * @brief Initializes an XCVR instance. - * - * This function initializes the XCVR module with user-defined settings. - * - * @param com_config Pointer to the common configuration settings structure. - * @param mode_config Pointer to the mode specific configuration settings structure. - * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure. - * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure. - * @param tempDegC temperature of the die in degrees C. - * @param ext_clk indicates the external clock setting, 32MHz or 26MHz. - * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) - * @return 0 succeed, others failed - */ -xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, - const xcvr_mode_config_t *mode_config, - const xcvr_mode_datarate_config_t *mode_datarate_config, - const xcvr_datarate_config_t *datarate_config, - int16_t tempDegC, - XCVR_INIT_MODE_CHG_T first_init); - -/*! - * @brief Set XCVR register to reset value. - * - * This function set XCVR register to the reset value. - * - */ -void XCVR_Reset(void); - -/*! - * @brief Change the operating mode of the radio. - * - * This function changes the XCVR to a new radio operating mode. - * - * @param new_radio_mode The radio mode for which the XCVR should be configured. - * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @return status of the mode change. - */ - xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate); - -/*! - * @brief Enable Narrowband RSSI measurement. - * - * This function enables the narrowband RSSI measurement - * - * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled. - */ -void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable); - -/*! - * @brief Set an arbitrary frequency for RX and TX for the radio. - * - * This function sets the radio frequency used for RX and RX.. - * - * @param freq target frequency setting in Hz. - * @param refOsc reference oscillator setting in Hz. - * @return status of the frequency change. - * @details - */ - xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc); - -/*! - * @brief Register a callback from upper layers. - * - * This function registers a callback from the upper layers for the radio to call in case of fatal errors. - * - * @param fptr The function pointer to a panic callback. - */ -void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */ - -/*! - * @brief Read the health status of the XCVR to detect errors. - * - * This function enables the upper layers to request the current radio health. - * - * @return The health status of the radio.. - */ -healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */ - -/*! - * @brief Control FAD and LPPS features. - * - * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search. - * - * @param fptr control the FAD and LPPS settings. - * - */ - void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control); - -/*! - * @brief Change the mapping of the radio IRQs. - * - * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. - * - * @param irq0_mapping the LL which should be mapped to the INT0 line. - * @param irq1_mapping the LL which should be mapped to the INT1 line. - * @return status of the mapping request. - * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line. - * @warning - * The same LL must NOT be mapped to both INT lines. - */ - xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping); - -#if RADIO_IS_GEN_3P0 -/*! - * @brief Sets the network address used by the PHY during BLE Bit Streaming Mode. - * - * This function programs the register in the PHY which contains the network address used during BSM. - * - * @param bsm_ntw_address the address to be used during BSM. - * @ note This routine does NOT enable BSM. - */ -void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address); - -/*! - * @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode. - * - * This function reads the register in the PHY which contains the network address used during BSM. - * - * @return bsm_ntw_address the address to be used during BSM. - * @ note This routine does NOT enable BSM. - */ -uint32_t XCVR_GetBSM_NTW_Address(void); -#endif /* RADIO_IS_GEN_3P0 */ - -/*! - * @brief Get the mapping of the one of the radio IRQs. - * - * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. - * - * @param int_num the number, 0 or 1, of the INT line to fetched. - * @return the mapping setting of the specified line. - * @note Any value passed into this routine other than 0 will be treated as a 1. - */ - link_layer_t XCVR_GetIRQMapping(uint8_t int_num); - -/*! - * @brief Get the current configuration of the XCVR. - * - * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc - * - * @param curr_config pointer to a structure to be updated with the current mode and data rate. - * @return the status of the request, success or invalid parameter (null pointer). - * @note This API will return meaningless results if called before the radio is initialized... - */ -xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config); - -/******************************************************************************* - * Customer level trim functions - ******************************************************************************/ -/*! - * @brief Controls setting the XTAL trim value.. - * - * This function enables the upper layers set a crystal trim compensation facor - * - * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error. - * @return The health status of the radio.. - */ -xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); - -/*! - * @brief Controls getting the XTAL trim value.. - * - * This function enables the upper layers to read the current XTAL compensation factors. - * The returned value is in the range 0..127 (7 bits). - * - * @return The XTAL trim compensation factors.. - */ -uint8_t XCVR_GetXtalTrim(void); - -/*! - * @brief Controls setting the RSSI adjustment.. - * - * This function enables the upper layers to set an RSSI adjustment value. - * - * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step. - * @return The health status of the radio.. - */ -xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); - -/*! - * @brief Controls getting the RSSI adjustment.. - * - * This function enables the upper layers to read the current XCVR RSSI adjustment value. - * The returned value is a signed 8-bit value, in 1/4 dBm step. - * - * @return The RSSI adjustment value.. - */ -int8_t XCVR_GetRssiAdjustment(void); - -/*! - * @brief Controls setting the PLL to a particular channel. - * - * This function enables setting the radio channel for TX and RX. - * - * @param channel the channel number to set - * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. - * @return The status of the channel over-ride. - */ -xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); - -/*! - * @brief Reads the current frequency for RX and TX for the radio. - * - * This function reads the radio frequency used for RX and RX.. - * - * @return Current radio frequency setting. - */ -uint32_t XCVR_GetFreq(void); - -/*! - * @brief Force receiver warmup. - * - * This function forces the initiation of a receiver warmup sequence. - * - */ -void XCVR_ForceRxWu(void); - -/*! - * @brief Force receiver warmdown. - * - * This function forces the initiation of a receiver warmdown sequence. - * - */ - void XCVR_ForceRxWd(void); - -/*! - * @brief Force transmitter warmup. - * - * This function forces the initiation of a transmit warmup sequence. - * - */ -void XCVR_ForceTxWu(void); - -/*! - * @brief Force transmitter warmdown. - * - * This function forces the initiation of a transmit warmdown sequence. - * - */ -void XCVR_ForceTxWd(void); - -/*! - * @brief Starts transmit with a TX pattern register data sequence. - * - * This function starts transmitting using the DFT pattern register mode. - * - * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. - * @param radio_mode The radio mode for which the XCVR should be configured. - * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @param tx_pattern - the data pattern to transmit on. - * @return The status of the pattern reg transmit. - * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode - * and data rate. - */ -xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); - -/*! - * @brief Starts transmit with a TX LFSR register data sequence. - * - * This function starts transmitting using the DFT LFSR register mode. - * - * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. - * @param radio_mode The radio mode for which the XCVR should be configured. - * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. - * @param lfsr_length - the length of the LFSR sequence to use. - * @return The status of the LFSR reg transmit. - * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode - * and data rate. - */ -xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); - -/*! - * @brief Controls clearing all TX DFT settings. - * - * This function reverts all TX DFT settings from the test modes to normal operating mode. - * - */ -void XCVR_DftTxOff(void); - -/*! - * @brief Controls setting the PA power level. - * - * This function enables setting the PA power level to a specific setting, overriding any link layer settings. - * - * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. - * @return The status of the PA power over-ride. - */ -xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); - -/*! - * @brief Starts CW TX. - * - * This function starts transmitting CW (no modulation). - * - * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. - * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). - * @return The status of the CW transmit. - */ -xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); - -xcvrStatus_t XCVR_CoexistenceInit(void); -xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority); -xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); - -/* @} */ - #ifdef __cplusplus } #endif diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c deleted file mode 100644 index 0e7b548340e5..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.c +++ /dev/null @@ -1,532 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "cpu.h" -#include "fsl_xcvr.h" -#include "fsl_xcvr_trim.h" -#include -#include - -#define ENABLE_DEBUG (0) -#include "debug.h" - -/******************************************************************************* -* Definitions -******************************************************************************/ -#define DCOC_DAC_BBF_STEP (16) -#define RX_DC_EST_SAMPLES (64) - -/******************************************************************************* -* Prototypes -******************************************************************************/ - -/******************************************************************************* -* Variables -******************************************************************************/ -const int8_t TsettleCal = 10; - -/******************************************************************************* - * Macros - ******************************************************************************/ -#define ISIGN(x) !((uint16_t)x & 0x8000) -#define ABS(x) ((x) > 0 ? (x) : -(x)) -#ifndef MIN -#define MIN(a,b) \ - ({ __typeof__ (a) _a = (a); \ - __typeof__ (b) _b = (b); \ - _a < _b ? _a : _b; }) -#endif - - -/******************************************************************************* - * Code - ******************************************************************************/ - -static uint32_t calc_dcoc_dac_slope(int32_t lower, int32_t upper) -{ - /* Normalize internal measurement */ - int32_t norm_dc_code = upper - lower; - if (norm_dc_code < 0) { - norm_dc_code = -norm_dc_code; - } - uint32_t dc_step = (uint32_t)norm_dc_code / DCOC_DAC_BBF_STEP; - DEBUG("slope: %d, %d -> %f\n", (int) lower, (int)upper, (float)dc_step / (1 << 16)); - return dc_step; -} - -void calc_tza_step_rcp_reg(TZAdcocstep_t *out, uint32_t base_step, uint16_t gain, uint16_t gain0) -{ - uint32_t step = (base_step * gain + (gain0 >> 1)) / gain0; - /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ - out->dcoc_step = (step + (1u << 12)) >> 13; - out->dcoc_step_rcp = (0x80000000ul + (step >> 1)) / step; -} - -/*! ********************************************************************************* - * \brief Temporary delay function - * - * \param[in] none. - * - * \return none. - * - * \details - * - ***********************************************************************************/ -void XcvrCalDelay(uint32_t time) -{ - time *= 32; /* Time delay is roughly in uSec. */ - while(time > 0) - { - time--; - } -} - -/*! ********************************************************************************* - * rx_dc_est_samples : Get nsamples DC EST values and return the sums - ***********************************************************************************/ -void rx_dc_est_samples(int32_t *i_sum, int32_t *q_sum, unsigned nsamples) -{ - /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ - uint32_t end_of_rx_wu = XCVR_CTRL_XCVR_STATUS_TSM_COUNT( - (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> - XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT); - while ((XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) != end_of_rx_wu) {}; - - int32_t sum_i = 0; - int32_t sum_q = 0; - /* Read DCOC DC EST register. */ - for (unsigned k = 0; k < nsamples; k++) - { - uint32_t dc_temp = XCVR_RX_DIG->DCOC_DC_EST; - int16_t dc_meas_i = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT; - dc_meas_i = (int16_t)(dc_meas_i << 4) / 16; /* Sign extend from 12 to 16 bits. */ - sum_i += dc_meas_i; - - int16_t dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; - dc_meas_q = (int16_t)(dc_meas_q << 4) / 16; /* Sign extend from 12 to 16 bits. */ - sum_q += dc_meas_q; - } - - *i_sum = sum_i; - *q_sum = sum_q; -} - -/* Unsigned integer division, rounded to nearest integer */ -static inline uint32_t calc_div_rounded(uint32_t num, uint32_t den) -{ - return (num + (den / 2)) / den; -} - -/*! ********************************************************************************* - * \brief This function performs a trim of the BBA DCOC DAC on the DUT - * - * \return status - 1 if passed, 0 if failed. - * - * \ingroup PublicAPIs - * - * \details - * Requires the RX to be warmed up before this function is called. - * - ***********************************************************************************/ -uint8_t rx_bba_dcoc_dac_trim_DCest(void) -{ - /* Estimate the actual gain by measuring three points and approximating a line */ - uint8_t status = 0; - - /* Save register */ - uint32_t dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ - uint32_t dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ - uint32_t rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ - uint32_t agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ - uint32_t dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ - - /* Register config */ - /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ - XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG->RX_DIG_CTRL & - ~(XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK | /* Turn OFF AGC */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK | /* Disable for SW control of DCOC */ - XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK); /* Disable for SW control of DCOC */ - - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ - - /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ - XCVR_RX_DIG->DCOC_CTRL_0 = XCVR_RX_DIG->DCOC_CTRL_0 | - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1) | /* Enable Manual DCOC */ - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1) | /* Ensure DCOC Tracking is enabled */ - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1) | /* Enable DC Estimator */ - XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ - - /* Use reset defaults */ - uint8_t bbf_dacinit_i = 0x20; - uint8_t bbf_dacinit_q = 0x20; - uint8_t tza_dacinit_i = 0x80; - uint8_t tza_dacinit_q = 0x80; - - /* Set default DCOC DAC INIT Value */ - XCVR_RX_DIG->DCOC_DAC_INIT = - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - /* Store DCOC_DAC_INIT value */ - uint32_t dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; - - XcvrCalDelay(TsettleCal * 2); - - int32_t dc_meas_i_nominal = 0; - int32_t dc_meas_q_nominal = 0; - /* TODO: remove this since it cancels out in the calculations below */ - rx_dc_est_samples(&dc_meas_i_nominal, &dc_meas_q_nominal, RX_DC_EST_SAMPLES); - - /* SWEEP I/Q CHANNEL */ - int32_t dc_meas_i = 0; - int32_t dc_meas_q = 0; - /* BBF NEG STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - DCOC_DAC_BBF_STEP) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - DCOC_DAC_BBF_STEP) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 4); - - rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); - uint32_t meas_sum = 0; - meas_sum += calc_dcoc_dac_slope(dc_meas_i, dc_meas_i_nominal); - meas_sum += calc_dcoc_dac_slope(dc_meas_q, dc_meas_q_nominal); - - /* BBF POS STEP */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + DCOC_DAC_BBF_STEP) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + DCOC_DAC_BBF_STEP) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); - XcvrCalDelay(TsettleCal * 2); - rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); - meas_sum += calc_dcoc_dac_slope(dc_meas_i_nominal, dc_meas_i); - meas_sum += calc_dcoc_dac_slope(dc_meas_q_nominal, dc_meas_q); - - XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ - - /* Compute the average sampled gain for the measured steps */ - - /* Calculate BBF DCOC STEPS, RECIPROCALS */ - /* meas_sum here is the average gain multiplied by (4 * RX_DC_EST_SAMPLES) */ - /* Compute the gain average as a Q6.3 number */ - /* rounded result, Q6.3 number */ - uint16_t bbf_dcoc_gain_measured = calc_div_rounded(meas_sum, (4 * RX_DC_EST_SAMPLES / (1 << 3))); - - DEBUG("temp_step = %f\n", (float)meas_sum / (4 * RX_DC_EST_SAMPLES)); - DEBUG("bbf_dcoc_gain_measured = %u\n", (unsigned)bbf_dcoc_gain_measured); - - /* Check the measured value for validity. Should be in the range: - * 250 < bbf_dcoc_gain_measured < 305, according to NXP wireless framework v5.4.3 (MCUXpresso KW36 SDK) - */ - if ((250 < bbf_dcoc_gain_measured) & (bbf_dcoc_gain_measured < 305)) - { - /* Compute reciprocal, as Q15 number, but only the 13 lowest bits are programmable */ - /* rounded result, ((2**15) / slope) */ - uint32_t bbf_dcoc_gain_measured_rcp = calc_div_rounded((1u << 15) * (4u * RX_DC_EST_SAMPLES), meas_sum); - DEBUG("bbf_dcoc_gain_measured_rcp = %"PRIu32"\n", bbf_dcoc_gain_measured_rcp); - - uint16_t bbf_dcoc_gain_default = - (xcvr_common_config.dcoc_bba_step_init & - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK) >> - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT; - /* Rescale all default TZA DCOC gains according to the measured BBF gain, - * using (bbf_dcoc_gain_measured / bbf_dcoc_gain_default) as the implicit - * scale factor, but rewrite it to use - * (meas_sum / (bbf_dcoc_gain_default * (4u * RX_DC_EST_SAMPLES / (1u << 3)))) - * for better numeric precision */ - /* rounded result, Q9.3 number */ - bbf_dcoc_gain_default *= (4u * RX_DC_EST_SAMPLES / (1u << 3)); - /* Make the trims active */ - XCVR_RX_DIG->DCOC_BBA_STEP = - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_gain_measured) | - XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_gain_measured_rcp); - const uint32_t *dcoc_tza_step_config_ptr = &xcvr_common_config.dcoc_tza_step_00_init; - /* All tza_step_* configuration registers use sequential memory addresses */ - volatile uint32_t *xcvr_rx_dig_dcoc_tza_step_ptr = &XCVR_RX_DIG->DCOC_TZA_STEP_0; - for (unsigned k = 0; k <= 10; ++k) - { - /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ - uint16_t tza_gain_default = - (dcoc_tza_step_config_ptr[k] & - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK) >> - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT; - /* Using meas_sum for higher precision */ - uint32_t dcoc_step = calc_div_rounded(tza_gain_default * meas_sum, bbf_dcoc_gain_default); - uint32_t dcoc_step_rcp = calc_div_rounded(0x8000ul * bbf_dcoc_gain_default, tza_gain_default * meas_sum); - DEBUG("tza_dcoc_step[%u].dcoc_step = %u\n", k, (unsigned)dcoc_step); - DEBUG("tza_dcoc_step[%u].dcoc_step_rcp = %u\n", k, (unsigned)dcoc_step_rcp); - xcvr_rx_dig_dcoc_tza_step_ptr[k] = - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(dcoc_step) | - XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(dcoc_step_rcp) ; - } - status = 1; /* Success */ - } - else - { - DEBUG("!!! XCVR trim failed: bbf_dcoc_step = %u!\n", (unsigned)bbf_dcoc_gain_measured); - status = 0; /* Failure */ - } - - /* Restore Registers */ - XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ - XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ - XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ - XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ - - return status; -} - -/*! ********************************************************************************* - * DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign - ***********************************************************************************/ -void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) -{ - uint8_t curr_tza_dac_i, curr_tza_dac_q; - uint8_t curr_bba_dac_i, curr_bba_dac_q; - uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0; - uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0; - uint8_t i = 0; - uint8_t bba_gain = 11; - bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; - - uint32_t dcoc_ctrl_0_stack; - uint32_t dcoc_ctrl_1_stack; - uint32_t agc_ctrl_1_stack; - uint32_t rx_dig_ctrl_stack; - uint32_t dcoc_cal_gain_state; - uint32_t xcvr_ctrl_stack = 0; - - uint32_t temp; - - /* Save registers */ - dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ - dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ - rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ - agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ - dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ - - /* WarmUp */ - if (standalone_operation) - { - temp = XCVR_MISC->XCVR_CTRL; - xcvr_ctrl_stack = temp; - temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK); - temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0); - XCVR_MISC->XCVR_CTRL = temp; - XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */ - XCVR_ForceRxWu(); - XcvrCalDelay(2000); - } - - /* Register config */ - /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ - temp = XCVR_RX_DIG->RX_DIG_CTRL; - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ - temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ - XCVR_RX_DIG->RX_DIG_CTRL = temp; - - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ - XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ - - /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ - temp = XCVR_RX_DIG->DCOC_CTRL_0; - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ - temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ - XCVR_RX_DIG->DCOC_CTRL_0 = temp; - - XcvrCalDelay(TsettleCal); - - /* Set default DCOC DAC INIT Value */ - /* LNA and BBA DAC Sweep */ - curr_bba_dac_i = 0x20; - curr_bba_dac_q = 0x20; - curr_tza_dac_i = 0x80; - curr_tza_dac_q = 0x80; - - /* Perform a first DC measurement to ensure that measurement is not clipping */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); - - int32_t dc_meas_i = 2000, dc_meas_i_p = 2000; - int32_t dc_meas_q = 2000, dc_meas_q_p = 2000; - do - { - bba_gain--; - /* Set DAC user gain */ - XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | - XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */ - XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | - XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ - XcvrCalDelay(TsettleCal * 2); - rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); - dc_meas_i /= RX_DC_EST_SAMPLES; - dc_meas_q /= RX_DC_EST_SAMPLES; - } while ((ABS(dc_meas_i) > 1900) || (ABS(dc_meas_q) > 1900)); - - for (i = 0; i < 0x0F; i++) - { - /* I channel : */ - if (!TZA_I_OK) { - if ((i > 0) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { - curr_tza_dac_i = p_tza_dac_i; - } - - TZA_I_OK = 1; - } - else { - p_tza_dac_i = curr_tza_dac_i; - - if (dc_meas_i > 0) { - curr_tza_dac_i--; - } - else { - curr_tza_dac_i++; - } - } - } - else { - /* Sweep BBA I */ - if (!BBA_I_OK) { - if ((curr_bba_dac_i != 0x20) && (ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p))) { - if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) { - curr_bba_dac_i = p_bba_dac_i; - } - - BBA_I_OK = 1; - } - else { - p_bba_dac_i = curr_bba_dac_i; - if (dc_meas_i > 0) { - curr_bba_dac_i--; - } - else { - curr_bba_dac_i++; - } - } - } - } - - /* Q channel : */ - if (!TZA_Q_OK) { - if ((i > 0) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { - curr_tza_dac_q = p_tza_dac_q; - } - TZA_Q_OK = 1; - } - else { - p_tza_dac_q = curr_tza_dac_q; - if (dc_meas_q > 0) { - curr_tza_dac_q--; - } - else { - curr_tza_dac_q++; - } - } - } - else { - /* Sweep BBA Q */ - if (!BBA_Q_OK) { - if ((curr_bba_dac_q != 0x20) && (ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p))) { - if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) { - curr_bba_dac_q = p_bba_dac_q; - } - BBA_Q_OK = 1; - } - else { - p_bba_dac_q = curr_bba_dac_q; - if (dc_meas_q > 0) { - curr_bba_dac_q--; - } - else { - curr_bba_dac_q++; - } - } - } - } - - /* DC OK break : */ - if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK) - { - break; - } - - dc_meas_i_p = dc_meas_i; /* Store as previous value */ - dc_meas_q_p = dc_meas_q; /* Store as previous value */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); - XcvrCalDelay(TsettleCal * 2); - rx_dc_est_samples(&dc_meas_i, &dc_meas_q, RX_DC_EST_SAMPLES); - dc_meas_i /= RX_DC_EST_SAMPLES; - dc_meas_q /= RX_DC_EST_SAMPLES; - } - - /* Apply optimized DCOC DAC INIT : */ - XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | - XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); - - /* WarmDown */ - if (standalone_operation) - { - XCVR_ForceRxWd(); /* Don't leave the receiver running. */ - XcvrCalDelay(200); - XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */ - XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack; - } - - /* Restore register */ - XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ - XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ - XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ - XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ - XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ -} diff --git a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h b/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h deleted file mode 100644 index 9c9472333ff8..000000000000 --- a/drivers/kw41zrf/vendor/XCVR/MKW41Z4/fsl_xcvr_trim.h +++ /dev/null @@ -1,140 +0,0 @@ -/* -* The Clear BSD License -* Copyright 2016-2017 NXP -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted (subject to the limitations in the -* disclaimer below) provided that the following conditions are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ -#ifndef _FSL_XCVR_TRIM_H_ -/* Clang-format off. */ -#define _FSL_XCVR_TRIM_H_ -/* Clang-format on. */ - -#include "cpu.h" -#include "fsl_xcvr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*! -* @addtogroup xcvr -* @{ -*/ - -/*! @file*/ - -/************************************************************************************ -************************************************************************************* -* Public constant definitions -************************************************************************************* -************************************************************************************/ - -/************************************************************************************ -************************************************************************************* -* Public type definitions -************************************************************************************* -************************************************************************************/ - -/* \brief The enumerations used to define the I & Q channel selections. */ -typedef enum -{ - I_CHANNEL = 0, - Q_CHANNEL = 1, - NUM_I_Q_CHAN = 2 -} IQ_t; - -typedef enum /* Enumeration of ADC_GAIN_CAL 2 */ -{ - NOMINAL2 = 0, - BBF_NEG = 1, - BBF_POS = 2, - TZA_STEP_N0 = 3, - TZA_STEP_N1 = 4, - TZA_STEP_N2 = 5, - TZA_STEP_N3 = 6, - TZA_STEP_N4 = 7, - TZA_STEP_N5 = 8, - TZA_STEP_N6 = 9, - TZA_STEP_N7 = 10, - TZA_STEP_N8 = 11, - TZA_STEP_N9 = 12, - TZA_STEP_N10 = 13, - TZA_STEP_P0 = 14, - TZA_STEP_P1 = 15, - TZA_STEP_P2 = 16, - TZA_STEP_P3 = 17, - TZA_STEP_P4 = 18, - TZA_STEP_P5 = 19, - TZA_STEP_P6 = 20, - TZA_STEP_P7 = 21, - TZA_STEP_P8 = 22, - TZA_STEP_P9 = 23, - TZA_STEP_P10 = 24, - - NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */ -} DAC_SWEEP_STEP2_t; - -/* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */ -typedef struct -{ - uint16_t dcoc_step; - uint16_t dcoc_step_rcp; -} TZAdcocstep_t; - -typedef struct -{ - int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */ - int16_t internal_measurement; /* The value (average code) measured from DMA samples. */ -// uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */ -} GAIN_CALC_TBL_ENTRY2_T; - -/******************************************************************************* -* Definitions -******************************************************************************/ -void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); -void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); -uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); -void rx_dc_est_average(int16_t *i_avg, int16_t *q_avg); -uint8_t rx_bba_dcoc_dac_trim_DCest(void); -void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); - - - - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*! @}*/ - -#endif /* _FSL_XCVR_TRIM_H_ */ From 56108a7996fdf394d4fddf43435bb9f3f0e72c99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 08:45:25 +0100 Subject: [PATCH 56/82] squash kw41zrf remove debug timing --- drivers/kw41zrf/kw41zrf.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 24906eba9cb3..fb923217eb9a 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -31,7 +31,6 @@ #include "kw41zrf_intern.h" #include "vendor/XCVR/MKW41Z4/fsl_xcvr.h" #include "vendor/XCVR/MKW41Z4/ifr_radio.h" -#include "periph/timer.h" #define ENABLE_DEBUG (0) #include "debug.h" @@ -116,12 +115,8 @@ int kw41zrf_reset_hardware(kw41zrf_t *dev) RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; - timer_init(TIMER_PIT_DEV(0), 1000000ul, NULL, NULL); DEBUG("[kw41zrf] start xcvr init\n"); - uint32_t before = timer_read(TIMER_PIT_DEV(0)); int res = kw41zrf_xcvr_init(dev); - uint32_t after = timer_read(TIMER_PIT_DEV(0)); - DEBUG("[kw41zrf] took %" PRIu32 " us\n", (after - before)); if (res < 0) { /* Most likely a calibration failure in XCVR driver */ return res; From 10dcf8fcbed2e2b90cb787cfe2a4d86ab6e394cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 09:55:34 +0100 Subject: [PATCH 57/82] squash kw41zrf Clean up options --- drivers/include/kw41zrf.h | 4 ---- drivers/kw41zrf/include/kw41zrf_intern.h | 5 ++--- drivers/kw41zrf/kw41zrf.c | 7 ++++--- drivers/kw41zrf/kw41zrf_getset.c | 12 +----------- drivers/kw41zrf/kw41zrf_netdev.c | 8 +++----- 5 files changed, 10 insertions(+), 26 deletions(-) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 720cd8f0dc6c..21cf7313a6d3 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -86,10 +86,6 @@ extern "C" { * @{ */ enum kw41zrf_opt { - KW41ZRF_OPT_SRC_ADDR_LONG = NETDEV_IEEE802154_SRC_MODE_LONG, /**< legacy define */ - KW41ZRF_OPT_RAWDUMP = NETDEV_IEEE802154_RAW, /**< legacy define */ - KW41ZRF_OPT_ACK_REQ = NETDEV_IEEE802154_ACK_REQ, /**< legacy define */ - KW41ZRF_OPT_CSMA = (0x0100), /**< use CSMA/CA algorithm for sending */ KW41ZRF_OPT_PROMISCUOUS = (0x0200), /**< promiscuous mode active */ KW41ZRF_OPT_PRELOADING = (0x0400), /**< preloading enabled */ diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 6aa7e58f6b61..5297db2accfb 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -122,9 +122,8 @@ static inline void kw41zrf_abort_sequence(kw41zrf_t *dev) while (!(ZLL->SEQ_CTRL_STS & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK)) {} /* Clear interrupt flags */ - /* cppcheck-suppress selfAssignment - * (reason: IRQ flags are write-1-to-clear) */ - ZLL->IRQSTS = ZLL->IRQSTS; + uint32_t irqsts = ZLL->IRQSTS; + ZLL->IRQSTS = irqsts; } /** diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index fb923217eb9a..4a8e84f982db 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -129,8 +129,8 @@ int kw41zrf_reset_hardware(kw41zrf_t *dev) RSIM->DSM_OSC_OFFSET = (1024ul << tmp) / (CLOCK_RADIOXTAL / 32768u) + 1u; /* round up */ /* Clear and disable all interrupts */ - /* Reset PHY_CTRL to the default value of mask all interrupts and all other - * settings disabled */ + /* Reset PHY_CTRL to the default values, mask all interrupts, + * enable RXACKRQD, we only use TR mode for receiving acknowledgements */ ZLL->PHY_CTRL = ZLL_PHY_CTRL_CCATYPE(1) | ZLL_PHY_CTRL_TSM_MSK_MASK | @@ -143,6 +143,7 @@ int kw41zrf_reset_hardware(kw41zrf_t *dev) ZLL_PHY_CTRL_RXMSK_MASK | ZLL_PHY_CTRL_TXMSK_MASK | ZLL_PHY_CTRL_SEQMSK_MASK | + ZLL_PHY_CTRL_RXACKRQD_MASK | ZLL_PHY_CTRL_XCVSEQ(XCVSEQ_IDLE); /* Mask all timer interrupts and clear all interrupt flags */ @@ -235,7 +236,7 @@ int kw41zrf_reset(kw41zrf_t *dev) kw41zrf_set_rx_watermark(dev, 1); kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, true); - kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, true); + kw41zrf_set_option(dev, NETDEV_IEEE802154_ACK_REQ, true); kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, true); kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index bdaaecec7319..bd453ab4cdc3 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -194,7 +194,7 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) case KW41ZRF_OPT_CSMA: case KW41ZRF_OPT_PROMISCUOUS: case KW41ZRF_OPT_AUTOACK: - case KW41ZRF_OPT_ACK_REQ: + case NETDEV_IEEE802154_ACK_REQ: case KW41ZRF_OPT_TELL_RX_START: LOG_ERROR("[kw41zrf] Attempt to modify option %04x while radio is sleeping\n", (unsigned) option); return; @@ -227,11 +227,6 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT); break; - case KW41ZRF_OPT_ACK_REQ: - LOG_DEBUG("[kw41zrf] enable: ACK_REQ\n"); - bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT); - break; - case KW41ZRF_OPT_TELL_RX_START: LOG_DEBUG("[kw41zrf] enable: TELL_RX_START\n"); bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT); @@ -273,11 +268,6 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_AUTOACK_SHIFT); break; - case KW41ZRF_OPT_ACK_REQ: - LOG_DEBUG("[kw41zrf] disable: ACK_REQ\n"); - bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RXACKRQD_SHIFT); - break; - case KW41ZRF_OPT_TELL_RX_START: LOG_DEBUG("[kw41zrf] disable: TELL_RX_START\n"); bit_set32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT); diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index f6e52b9e1e09..32ada7aeda81 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -130,7 +130,7 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) } uint32_t tx_timeout = 0; if ((fcf & IEEE802154_FCF_ACK_REQ) && - (dev->netdev.flags & KW41ZRF_OPT_ACK_REQ)) { + (dev->netdev.flags & NETDEV_IEEE802154_ACK_REQ)) { uint8_t payload_len = len_fcf & 0xff; tx_timeout = backoff_delay + dev->tx_warmup_time + KW41ZRF_SHR_PHY_TIME + payload_len * KW41ZRF_PER_BYTE_TIME + @@ -828,7 +828,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, res = -EOVERFLOW; break; } - kw41zrf_set_option(dev, KW41ZRF_OPT_ACK_REQ, + kw41zrf_set_option(dev, NETDEV_IEEE802154_ACK_REQ, *((const netopt_enable_t *)value)); /* don't set res to set netdev_ieee802154_t::flags */ break; @@ -1118,9 +1118,7 @@ static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { DEBUG("[kw41zrf] finished TX (TR)\n"); handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; - if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_RXACKRQD_MASK) { - DEBUG("[kw41zrf] wait for RX ACK\n"); - } + DEBUG("[kw41zrf] wait for RX ACK\n"); } if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { From 28638a6cfbbc8268e53c9ad1c95874ac731ca58d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 10:05:33 +0100 Subject: [PATCH 58/82] squash kw41zrf set the correct state at init --- drivers/kw41zrf/kw41zrf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 4a8e84f982db..12eff70bb634 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -240,11 +240,11 @@ int kw41zrf_reset(kw41zrf_t *dev) kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, true); kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); - kw41zrf_set_sequence(dev, dev->idle_seq); + kw41zrf_abort_sequence(dev); bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_SEQMSK_SHIFT); - kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); kw41zrf_unmask_irqs(); DEBUG("[kw41zrf] reset radio and set to channel %d and pan %d.\n", From d77dae43d42e8166d6df285132590f0b96a9aa93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 14:33:32 +0100 Subject: [PATCH 59/82] squash kw41zrf silence codacy --- drivers/kw41zrf/kw41zrf_intern.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 0e78dc16559d..2d9fc79a91df 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -128,10 +128,9 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * to be constant at 2 DSM ticks */ while (RSIM->DSM_CONTROL & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK) {} /* Clear IRQ flags */ - /* cppcheck-suppress selfAssignment - * (reason: IRQ flags are write-1-to-clear) */ - RSIM->DSM_CONTROL = RSIM->DSM_CONTROL; - uint32_t irqsts = ZLL->IRQSTS; + uint32_t irqsts = RSIM->DSM_CONTROL; + RSIM->DSM_CONTROL = irqsts; + irqsts = ZLL->IRQSTS; DEBUG("[kw41zrf] sleep IRQSTS=%" PRIx32 "\n", irqsts); ZLL->IRQSTS = irqsts; NVIC_ClearPendingIRQ(Radio_1_IRQn); From e3fb55ba44ff25871ff2bfa52e611fe5ac88c5c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 13 Nov 2018 11:19:58 +0100 Subject: [PATCH 60/82] squash kw41zrf perform CSMA retry even without NETOPT TELL TX END --- drivers/kw41zrf/kw41zrf_netdev.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 32ada7aeda81..e2e6d53fcf84 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -1137,20 +1137,22 @@ static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) DEBUG("[kw41zrf] SEQIRQ (TR)\n"); handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { + if (dev->num_retrans < dev->max_retrans) { + /* Perform frame retransmission */ + ++dev->num_retrans; + DEBUG("[kw41zrf] TX retry %u\n", (unsigned)dev->num_retrans); + /* Reset CSMA counters for backoff handling */ + dev->csma_be = dev->csma_min_be; + dev->csma_num_backoffs = 0; + /* Resubmit the frame for transmission */ + kw41zrf_tx_exec(dev); + return handled_irqs; + } + } if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { DEBUG("[kw41zrf] RXACK timeout (TR)\n"); - if (dev->num_retrans < dev->max_retrans) { - /* Perform frame retransmission */ - ++dev->num_retrans; - DEBUG("[kw41zrf] retry %u\n", (unsigned)dev->num_retrans); - /* Reset CSMA counters for backoff handling */ - dev->csma_be = dev->csma_min_be; - dev->csma_num_backoffs = 0; - /* Resubmit the frame for transmission */ - kw41zrf_tx_exec(dev); - return handled_irqs; - } dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_NOACK); } else if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) { From dc5cf26579344b38780387746420b91128c2b83c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 13 Nov 2018 11:21:31 +0100 Subject: [PATCH 61/82] squash kw41zrf add support for debug LEDs --- drivers/kw41zrf/include/kw41zrf_intern.h | 28 ++++++++++++++++++++++++ drivers/kw41zrf/kw41zrf_netdev.c | 12 +++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 5297db2accfb..1eeac7d89bbc 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -27,6 +27,33 @@ /* For ZLL CPU registers */ #include "cpu.h" +#define ENABLE_LEDS (1) + +#if ENABLE_LEDS +/* For LED macros */ +#include "board.h" +#ifdef LED0_ON +#define LED_TX_ON LED1_ON +#define LED_TX_OFF LED1_OFF +#endif +#ifdef LED1_ON +#define LED_RX_ON LED2_ON +#define LED_RX_OFF LED2_OFF +#endif +#ifdef LED2_ON +#define LED_IRQ_ON LED3_ON +#define LED_IRQ_OFF LED3_OFF +#endif +#else /* ENABLE_LEDS */ +#define LED_TX_ON +#define LED_TX_OFF +#define LED_RX_ON +#define LED_RX_OFF +#define LED_IRQ_ON +#define LED_IRQ_OFF +#endif /* ENABLE_LEDS */ + + #ifdef __cplusplus extern "C" { #endif @@ -66,6 +93,7 @@ static inline void kw41zrf_mask_irqs(void) static inline void kw41zrf_unmask_irqs(void) { NVIC_EnableIRQ(Radio_1_IRQn); + LED_IRQ_OFF; } /** diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index e2e6d53fcf84..4847479962e8 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -65,7 +65,7 @@ static void kw41zrf_irq_handler(void *arg) { netdev_t *netdev = arg; kw41zrf_t *dev = (kw41zrf_t *)netdev; - + LED_IRQ_ON; kw41zrf_mask_irqs(); /* Signal to the thread that an IRQ has arrived, if it is waiting */ thread_flags_set(dev->thread, KW41ZRF_THREAD_FLAG_ISR); @@ -148,6 +148,7 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) /* This is quite timing sensitive, as interrupts may lead to setting a timer * target which has already passed */ unsigned mask = irq_disable(); + LED_TX_ON; if (tx_timeout > 0) { /* Set a long timeout to avoid timer races while setting up the TX sequence. * By setting the timeout to now - 1 we get 267 seconds to set up everything @@ -1004,6 +1005,7 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) uint32_t handled_irqs = 0; if (irqsts & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) { + LED_RX_ON; DEBUG("[kw41zrf] RXWTRMRKIRQ (R)\n"); handled_irqs |= ZLL_IRQSTS_RXWTRMRKIRQ_MASK; if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START) { @@ -1023,11 +1025,13 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) (unsigned int)((ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)); if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_AUTOACK_MASK) { + LED_TX_ON; DEBUG("[kw41zrf] perform TXACK\n"); } } if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + LED_TX_OFF; DEBUG("[kw41zrf] finished TXACK\n"); handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; } @@ -1037,6 +1041,7 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) kw41zrf_abort_sequence(dev); DEBUG("[kw41zrf] SEQIRQ (R)\n"); handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + LED_RX_OFF; if ((irqsts & ZLL_IRQSTS_CRCVALID_MASK) == 0) { LOG_ERROR("[kw41zrf] CRC failure (R)\n"); } @@ -1082,6 +1087,7 @@ static uint32_t _isr_event_seq_t(kw41zrf_t *dev, uint32_t irqsts) dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); } /* Go back to being idle */ + LED_TX_OFF; kw41zrf_set_sequence(dev, dev->idle_seq); } @@ -1116,12 +1122,14 @@ static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) { uint32_t handled_irqs = 0; if (irqsts & ZLL_IRQSTS_TXIRQ_MASK) { + LED_RX_ON; DEBUG("[kw41zrf] finished TX (TR)\n"); handled_irqs |= ZLL_IRQSTS_TXIRQ_MASK; DEBUG("[kw41zrf] wait for RX ACK\n"); } if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { + LED_RX_OFF; DEBUG("[kw41zrf] got RX ACK\n"); handled_irqs |= ZLL_IRQSTS_RXIRQ_MASK; } @@ -1137,6 +1145,8 @@ static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) DEBUG("[kw41zrf] SEQIRQ (TR)\n"); handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + LED_TX_OFF; + LED_RX_OFF; if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { if (dev->num_retrans < dev->max_retrans) { /* Perform frame retransmission */ From 7f1e47277a45f25242c7481a8945d3f1a46f13fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 13 Nov 2018 15:50:56 +0100 Subject: [PATCH 62/82] squash kw41zrf debug LED updates --- drivers/kw41zrf/include/kw41zrf_intern.h | 10 ++++++++-- drivers/kw41zrf/kw41zrf_intern.c | 2 ++ drivers/kw41zrf/kw41zrf_netdev.c | 4 +++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 1eeac7d89bbc..b06309bf32c1 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -33,18 +33,24 @@ /* For LED macros */ #include "board.h" #ifdef LED0_ON +#define LED_NDSM_ON LED0_ON +#define LED_NDSM_OFF LED0_OFF +#endif +#ifdef LED1_ON #define LED_TX_ON LED1_ON #define LED_TX_OFF LED1_OFF #endif -#ifdef LED1_ON +#ifdef LED2_ON #define LED_RX_ON LED2_ON #define LED_RX_OFF LED2_OFF #endif -#ifdef LED2_ON +#ifdef LED3_ON #define LED_IRQ_ON LED3_ON #define LED_IRQ_OFF LED3_OFF #endif #else /* ENABLE_LEDS */ +#define LED_NDSM_ON +#define LED_NDSM_OFF #define LED_TX_ON #define LED_TX_OFF #define LED_RX_ON diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index 2d9fc79a91df..e19e4a41864d 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -87,6 +87,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Already awake */ break; } + LED_NDSM_ON; /* The wake target must be at least (4 + RSIM_DSM_OSC_OFFSET) ticks * into the future, to let the oscillator stabilize before switching * on the clocks */ @@ -150,6 +151,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) RSIM->DSM_CONTROL = (RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK | RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK); while (!(kw41zrf_is_dsm())) {} + LED_NDSM_OFF; /* Restore saved RF_OSC_EN bits (from kw41zrf_init) * This will disable the RF oscillator unless the system was * configured to use the RF oscillator before kw41zrf_init() was diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 4847479962e8..f714c8a1a861 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -217,9 +217,11 @@ int kw41zrf_cca(kw41zrf_t *dev) } kw41zrf_abort_sequence(dev); kw41zrf_unmask_irqs(); + LED_RX_ON; kw41zrf_set_sequence(dev, XCVSEQ_CCA); /* Wait for the CCA to finish, it will take exactly RX warmup time + 128 µs */ kw41zrf_wait_idle(dev); + LED_RX_OFF; DEBUG("[kw41zrf] CCA: %u RSSI: %d\n", (unsigned)dev->cca_result, kw41zrf_get_ed_level(dev)); return dev->cca_result; @@ -1083,11 +1085,11 @@ static uint32_t _isr_event_seq_t(kw41zrf_t *dev, uint32_t irqsts) kw41zrf_abort_sequence(dev); DEBUG("[kw41zrf] SEQIRQ (T)\n"); handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + LED_TX_OFF; if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); } /* Go back to being idle */ - LED_TX_OFF; kw41zrf_set_sequence(dev, dev->idle_seq); } From 6c7ef37e2932925e190d9c3812f872e7917f70d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 13 Nov 2018 18:29:28 +0100 Subject: [PATCH 63/82] squash kw41zrf Update flags handling to match changes in #9581 --- drivers/include/kw41zrf.h | 24 ++----------- drivers/kw41zrf/include/kw41zrf_getset.h | 15 +++++++++ drivers/kw41zrf/kw41zrf.c | 7 ++-- drivers/kw41zrf/kw41zrf_getset.c | 5 ++- drivers/kw41zrf/kw41zrf_netdev.c | 43 +++++++++--------------- 5 files changed, 40 insertions(+), 54 deletions(-) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 21cf7313a6d3..6f5b1e7b5eb8 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -77,27 +77,6 @@ extern "C" { */ #define KW41ZRF_OUTPUT_POWER_MIN (-19) -/** - * @brief Internal device option flags - * - * `0x00ff` is reserved for general IEEE 802.15.4 flags - * (see @ref netdev_ieee802154_t) - * - * @{ - */ -enum kw41zrf_opt { - KW41ZRF_OPT_CSMA = (0x0100), /**< use CSMA/CA algorithm for sending */ - KW41ZRF_OPT_PROMISCUOUS = (0x0200), /**< promiscuous mode active */ - KW41ZRF_OPT_PRELOADING = (0x0400), /**< preloading enabled */ - KW41ZRF_OPT_TELL_TX_START = (0x0800), /**< notify MAC layer on TX start */ - KW41ZRF_OPT_TELL_TX_END = (0x1000), /**< notify MAC layer on TX finished */ - KW41ZRF_OPT_TELL_RX_START = (0x2000), /**< notify MAC layer on RX start */ - KW41ZRF_OPT_TELL_RX_END = (0x4000), /**< notify MAC layer on RX finished */ - KW41ZRF_OPT_AUTOACK = (0x8000), /**< enable automatic sending of - * ACKs for incoming packet */ -}; -/** @} */ - /** * @brief ISR callback function type */ @@ -118,13 +97,14 @@ typedef struct { uint32_t tx_warmup_time; /**< TX warmup time, in event timer ticks */ uint32_t rx_warmup_time; /**< RX warmup time, in event timer ticks */ uint32_t rf_osc_en_idle; /**< RF_OSC_EN bits setting when RF module is in standby */ + int16_t tx_power; /**< The current tx-power setting of the device */ + uint8_t flags; /**< Internal driver option flags */ uint8_t max_retrans; /**< Maximum number of frame retransmissions * when no Ack frame is received (macMaxFrameRetries) */ uint8_t csma_max_backoffs; /**< Maximum number of CSMA backoffs when * waiting for channel clear (macMaxCsmaBackoffs) */ uint8_t csma_min_be; /**< Minimum backoff exponent (macMinBe) */ uint8_t csma_max_be; /**< Maximum backoff exponent (macMaxBe) */ - int16_t tx_power; /**< The current tx-power setting of the device */ uint8_t idle_seq; /**< state to return to after sending */ uint8_t cca_result; /**< Used for passing CCA result from ISR to user */ uint8_t csma_be; /**< Counter used internally by send implementation */ diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h index 7847ae8ff101..8771d6aabd29 100644 --- a/drivers/kw41zrf/include/kw41zrf_getset.h +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -26,6 +26,21 @@ extern "C" { #endif + +/** + * @name Internal device option flags + * @{ + */ +#define KW41ZRF_OPT_CSMA (0x01u) /**< use CSMA/CA algorithm for sending */ +#define KW41ZRF_OPT_PROMISCUOUS (0x02u) /**< promiscuous mode active */ +#define KW41ZRF_OPT_PRELOADING (0x04u) /**< preloading enabled */ +#define KW41ZRF_OPT_TELL_TX_START (0x08u) /**< notify MAC layer on TX start */ +#define KW41ZRF_OPT_TELL_TX_END (0x10u) /**< notify MAC layer on TX finished */ +#define KW41ZRF_OPT_TELL_RX_START (0x20u) /**< notify MAC layer on RX start */ +#define KW41ZRF_OPT_TELL_RX_END (0x40u) /**< notify MAC layer on RX finished */ +#define KW41ZRF_OPT_AUTOACK (0x80u) /**< automatic sending of ACKs */ +/** @} */ + /** @brief Transceiver sequence identifiers */ enum kw41zrf_xcvseq { XCVSEQ_IDLE = 0b000, diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index 12eff70bb634..c00cf3d07390 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -224,6 +224,8 @@ int kw41zrf_reset(kw41zrf_t *dev) dev->tx_power = KW41ZRF_DEFAULT_TX_POWER; dev->idle_seq = XCVSEQ_RECEIVE; + kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + kw41zrf_abort_sequence(dev); kw41zrf_set_tx_power(dev, dev->tx_power); kw41zrf_set_channel(dev, KW41ZRF_DEFAULT_CHANNEL); @@ -236,10 +238,11 @@ int kw41zrf_reset(kw41zrf_t *dev) kw41zrf_set_rx_watermark(dev, 1); kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, true); - kw41zrf_set_option(dev, NETDEV_IEEE802154_ACK_REQ, true); kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, true); - kw41zrf_set_power_mode(dev, KW41ZRF_POWER_IDLE); + static const netopt_enable_t enable = NETOPT_ENABLE; + netdev_ieee802154_set(&dev->netdev, NETOPT_ACK_REQ, + &enable, sizeof(enable)); kw41zrf_abort_sequence(dev); bit_clear32(&ZLL->PHY_CTRL, ZLL_PHY_CTRL_SEQMSK_SHIFT); diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index bd453ab4cdc3..41ebf70ff568 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -194,7 +194,6 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) case KW41ZRF_OPT_CSMA: case KW41ZRF_OPT_PROMISCUOUS: case KW41ZRF_OPT_AUTOACK: - case NETDEV_IEEE802154_ACK_REQ: case KW41ZRF_OPT_TELL_RX_START: LOG_ERROR("[kw41zrf] Attempt to modify option %04x while radio is sleeping\n", (unsigned) option); return; @@ -206,7 +205,7 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) /* set option field */ if (state) { - dev->netdev.flags |= option; + dev->flags |= option; /* trigger option specific actions */ switch (option) { @@ -249,7 +248,7 @@ void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) } } else { - dev->netdev.flags &= ~(option); + dev->flags &= ~(option); /* trigger option specific actions */ switch (option) { case KW41ZRF_OPT_CSMA: diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index f714c8a1a861..1f457407cf13 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -124,7 +124,7 @@ static void kw41zrf_tx_exec(kw41zrf_t *dev) * the packet that is queued for transmission */ uint8_t fcf = (len_fcf >> 8) & 0xff; uint32_t backoff_delay = 0; - if (dev->netdev.flags & KW41ZRF_OPT_CSMA) { + if (dev->flags & KW41ZRF_OPT_CSMA) { /* Use CSMA/CA random delay in the interval [0, 2**dev->csma_be) */ backoff_delay = kw41zrf_csma_random_delay(dev); } @@ -267,7 +267,7 @@ static int kw41zrf_netdev_send(netdev_t *netdev, const iolist_t *iolist) #endif /* send data out directly if pre-loading is disabled */ - if (!(dev->netdev.flags & KW41ZRF_OPT_PRELOADING)) { + if (!(dev->flags & KW41ZRF_OPT_PRELOADING)) { dev->csma_be = dev->csma_min_be; dev->csma_num_backoffs = 0; dev->num_retrans = 0; @@ -386,7 +386,7 @@ static int kw41zrf_netdev_set_state(kw41zrf_t *dev, netopt_state_t state) kw41zrf_set_sequence(dev, dev->idle_seq); break; case NETOPT_STATE_TX: - if (dev->netdev.flags & KW41ZRF_OPT_PRELOADING) { + if (dev->flags & KW41ZRF_OPT_PRELOADING) { kw41zrf_wait_idle(dev); if (kw41zrf_is_dsm()) { /* bring the device out of DSM */ @@ -481,7 +481,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_PRELOADING); + !!(dev->flags & KW41ZRF_OPT_PRELOADING); return len; case NETOPT_PROMISCUOUSMODE: @@ -489,7 +489,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_PROMISCUOUS); + !!(dev->flags & KW41ZRF_OPT_PROMISCUOUS); return len; case NETOPT_RX_START_IRQ: @@ -497,7 +497,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START); + !!(dev->flags & KW41ZRF_OPT_TELL_RX_START); return len; case NETOPT_RX_END_IRQ: @@ -505,7 +505,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END); + !!(dev->flags & KW41ZRF_OPT_TELL_RX_END); return len; case NETOPT_TX_START_IRQ: @@ -513,7 +513,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START); + !!(dev->flags & KW41ZRF_OPT_TELL_TX_START); return len; case NETOPT_TX_END_IRQ: @@ -521,7 +521,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END); + !!(dev->flags & KW41ZRF_OPT_TELL_TX_END); return len; case NETOPT_CSMA: @@ -529,7 +529,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) return -EOVERFLOW; } *((netopt_enable_t *)value) = - !!(dev->netdev.flags & KW41ZRF_OPT_CSMA); + !!(dev->flags & KW41ZRF_OPT_CSMA); return len; case NETOPT_CSMA_RETRIES: @@ -789,7 +789,6 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, * requires the radio powered on */ switch (opt) { case NETOPT_AUTOACK: - case NETOPT_ACK_REQ: case NETOPT_PROMISCUOUSMODE: case NETOPT_RX_START_IRQ: case NETOPT_CSMA: @@ -826,16 +825,6 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, res = len; break; - case NETOPT_ACK_REQ: - if (len != sizeof(const netopt_enable_t)) { - res = -EOVERFLOW; - break; - } - kw41zrf_set_option(dev, NETDEV_IEEE802154_ACK_REQ, - *((const netopt_enable_t *)value)); - /* don't set res to set netdev_ieee802154_t::flags */ - break; - case NETOPT_PROMISCUOUSMODE: if (len != sizeof(const netopt_enable_t)) { res = -EOVERFLOW; @@ -984,7 +973,7 @@ static uint32_t _isr_event_seq_t_ccairq(kw41zrf_t *dev, uint32_t irqsts) kw41zrf_tx_exec(dev); return handled_irqs; } - if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + if (dev->flags & KW41ZRF_OPT_TELL_TX_END) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_MEDIUM_BUSY); } } @@ -993,7 +982,7 @@ static uint32_t _isr_event_seq_t_ccairq(kw41zrf_t *dev, uint32_t irqsts) DEBUG("[kw41zrf] CCA ch idle (RSSI: %d)\n", (int8_t)((ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)); - if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_START) { + if (dev->flags & KW41ZRF_OPT_TELL_TX_START) { /* TX will start automatically after CCA check succeeded */ dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_STARTED); } @@ -1010,7 +999,7 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) LED_RX_ON; DEBUG("[kw41zrf] RXWTRMRKIRQ (R)\n"); handled_irqs |= ZLL_IRQSTS_RXWTRMRKIRQ_MASK; - if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_START) { + if (dev->flags & KW41ZRF_OPT_TELL_RX_START) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_STARTED); } } @@ -1062,7 +1051,7 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) /* Block XCVSEQ_RECEIVE until netdev->recv has been called */ dev->recv_blocked = true; kw41zrf_set_sequence(dev, dev->idle_seq); - if (dev->netdev.flags & KW41ZRF_OPT_TELL_RX_END) { + if (dev->flags & KW41ZRF_OPT_TELL_RX_END) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_COMPLETE); } return handled_irqs; @@ -1086,7 +1075,7 @@ static uint32_t _isr_event_seq_t(kw41zrf_t *dev, uint32_t irqsts) DEBUG("[kw41zrf] SEQIRQ (T)\n"); handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; LED_TX_OFF; - if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + if (dev->flags & KW41ZRF_OPT_TELL_TX_END) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_COMPLETE); } /* Go back to being idle */ @@ -1162,7 +1151,7 @@ static uint32_t _isr_event_seq_tr(kw41zrf_t *dev, uint32_t irqsts) return handled_irqs; } } - if (dev->netdev.flags & KW41ZRF_OPT_TELL_TX_END) { + if (dev->flags & KW41ZRF_OPT_TELL_TX_END) { if (seq_ctrl_sts & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) { DEBUG("[kw41zrf] RXACK timeout (TR)\n"); dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_TX_NOACK); From f31a2c4555d7d81a13a2dad9df9d713de53a9e73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 13 Nov 2018 18:34:36 +0100 Subject: [PATCH 64/82] squash kw41zrf fixup signed bitmask literals --- drivers/kw41zrf/kw41zrf_netdev.c | 2 +- drivers/kw41zrf/kw41zrf_xcvr.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 1f457407cf13..1e08345ccbf9 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -59,7 +59,7 @@ static volatile unsigned int num_irqs_handled = 0; static unsigned int spinning_for_irq = 0; /* Set this to a flag bit that is not used by the MAC implementation */ -#define KW41ZRF_THREAD_FLAG_ISR (1 << 8) +#define KW41ZRF_THREAD_FLAG_ISR (1u << 8) static void kw41zrf_irq_handler(void *arg) { diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c index e9179ed98d60..8e65b28b5579 100644 --- a/drivers/kw41zrf/kw41zrf_xcvr.c +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -203,7 +203,7 @@ int kw41zrf_rx_bba_dcoc_dac_trim_DCest(void) /* meas_sum here is the average gain multiplied by (4 * RX_DC_EST_SAMPLES) */ /* Compute the gain average as a Q6.3 number */ /* rounded result, Q6.3 number */ - uint16_t bbf_dcoc_gain_measured = calc_div_rounded(meas_sum, (RX_DC_EST_TOTAL_SAMPLES / (1 << 3))); + uint16_t bbf_dcoc_gain_measured = calc_div_rounded(meas_sum, (RX_DC_EST_TOTAL_SAMPLES / (1u << 3))); DEBUG("temp_step = %f\n", (float)meas_sum / RX_DC_EST_TOTAL_SAMPLES); DEBUG("bbf_dcoc_gain_measured = %u\n", (unsigned)bbf_dcoc_gain_measured); From ae975b42da01c4a05100431f6fc772c83698cd91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 15 Nov 2018 10:23:44 +0100 Subject: [PATCH 65/82] fixup! squash kw41zrf debug LED updates --- drivers/kw41zrf/kw41zrf_netdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 1e08345ccbf9..ab9a40f8c470 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -1032,6 +1032,7 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) kw41zrf_abort_sequence(dev); DEBUG("[kw41zrf] SEQIRQ (R)\n"); handled_irqs |= ZLL_IRQSTS_SEQIRQ_MASK; + LED_TX_OFF; LED_RX_OFF; if ((irqsts & ZLL_IRQSTS_CRCVALID_MASK) == 0) { LOG_ERROR("[kw41zrf] CRC failure (R)\n"); From 8e90d22e497014efcc964eba130e23cf0b80ddf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 16 Nov 2018 12:07:54 +0100 Subject: [PATCH 66/82] squash kw41zrf minor clean ups and variable types refactor --- drivers/include/kw41zrf.h | 4 +-- drivers/kw41zrf/include/kw41zrf_getset.h | 2 +- drivers/kw41zrf/kw41zrf.c | 8 +++--- drivers/kw41zrf/kw41zrf_getset.c | 2 +- drivers/kw41zrf/kw41zrf_intern.c | 8 +++--- drivers/kw41zrf/kw41zrf_netdev.c | 32 ++++++++++++------------ drivers/kw41zrf/kw41zrf_xcvr.c | 2 +- 7 files changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/include/kw41zrf.h b/drivers/include/kw41zrf.h index 6f5b1e7b5eb8..de832824ab73 100644 --- a/drivers/include/kw41zrf.h +++ b/drivers/include/kw41zrf.h @@ -110,8 +110,8 @@ typedef struct { uint8_t csma_be; /**< Counter used internally by send implementation */ uint8_t csma_num_backoffs; /**< Counter used internally by send implementation */ uint8_t num_retrans; /**< Counter used internally by send implementation */ - bool pm_blocked; /**< true if we have blocked a low power mode in the CPU */ - bool recv_blocked; /**< blocks moving to XCVSEQ_RECEIVE to prevent + uint8_t pm_blocked; /**< true if we have blocked a low power mode in the CPU */ + uint8_t recv_blocked; /**< blocks moving to XCVSEQ_RECEIVE to prevent * overwriting the RX buffer before the higher * layers have copied it to system RAM */ /** @} */ diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h index 8771d6aabd29..38353f4d2b6c 100644 --- a/drivers/kw41zrf/include/kw41zrf_getset.h +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -193,7 +193,7 @@ void kw41zrf_set_rx_watermark(kw41zrf_t *dev, uint8_t value); * @param[in] option Netopt option type * @param[in] state state */ -void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state); +void kw41zrf_set_option(kw41zrf_t *dev, uint8_t option, uint8_t state); #ifdef __cplusplus } diff --git a/drivers/kw41zrf/kw41zrf.c b/drivers/kw41zrf/kw41zrf.c index c00cf3d07390..a9c6983ff676 100644 --- a/drivers/kw41zrf/kw41zrf.c +++ b/drivers/kw41zrf/kw41zrf.c @@ -56,8 +56,8 @@ void kw41zrf_setup(kw41zrf_t *dev) netdev->driver = &kw41zrf_driver; /* initialize device descriptor */ dev->idle_seq = XCVSEQ_RECEIVE; - dev->pm_blocked = false; - dev->recv_blocked = false; + dev->pm_blocked = 0; + dev->recv_blocked = 0; /* Set default parameters according to STD IEEE802.15.4-2015 */ dev->csma_max_be = 5; dev->csma_min_be = 3; @@ -237,8 +237,8 @@ int kw41zrf_reset(kw41zrf_t *dev) kw41zrf_set_rx_watermark(dev, 1); - kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, true); - kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, true); + kw41zrf_set_option(dev, KW41ZRF_OPT_AUTOACK, 1); + kw41zrf_set_option(dev, KW41ZRF_OPT_CSMA, 1); static const netopt_enable_t enable = NETOPT_ENABLE; netdev_ieee802154_set(&dev->netdev, NETOPT_ACK_REQ, diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 41ebf70ff568..86e399cb893f 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -182,7 +182,7 @@ int8_t kw41zrf_get_ed_level(kw41zrf_t *dev) return (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT; } -void kw41zrf_set_option(kw41zrf_t *dev, uint16_t option, bool state) +void kw41zrf_set_option(kw41zrf_t *dev, uint8_t option, uint8_t state) { DEBUG("[kw41zrf] set option 0x%04x to %x\n", option, state); diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index e19e4a41864d..f1934f3a164a 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -64,7 +64,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) * radio will be stuck in state retention mode. */ if (!dev->pm_blocked) { pm_block(KINETIS_PM_LLS); - dev->pm_blocked = true; + dev->pm_blocked = 1; } /* Restore saved RF oscillator settings, enable oscillator in RUN mode * to allow register access */ @@ -120,7 +120,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) } if (dev->pm_blocked) { pm_unblock(KINETIS_PM_LLS); - dev->pm_blocked = false; + dev->pm_blocked = 0; } /* Race condition: if sleep is re-triggered after wake before the * DSM_ZIG_FINISHED flag has been switched off, then the RSIM @@ -173,9 +173,9 @@ void kw41zrf_set_sequence(kw41zrf_t *dev, uint32_t seq) { (void) dev; DEBUG("[kw41zrf] set sequence to %x\n", (unsigned)seq); - bool back_to_sleep = false; + unsigned back_to_sleep = 0; if (seq == XCVSEQ_DSM_IDLE) { - back_to_sleep = true; + back_to_sleep = 1; seq = XCVSEQ_IDLE; } else if ((seq == XCVSEQ_RECEIVE) && dev->recv_blocked) { diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index ab9a40f8c470..05cba26960f2 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include @@ -277,6 +276,15 @@ static int kw41zrf_netdev_send(netdev_t *netdev, const iolist_t *iolist) return (int)len; } +static inline void kw41zrf_unblock_rx(kw41zrf_t *dev) +{ + dev->recv_blocked = 0; + if (kw41zrf_can_switch_to_idle(dev)) { + kw41zrf_abort_sequence(dev); + kw41zrf_set_sequence(dev, dev->idle_seq); + } +} + static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *info) { kw41zrf_t *dev = (kw41zrf_t *)netdev; @@ -301,11 +309,7 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in if (buf == NULL) { if (len > 0) { /* discard what we have stored in the buffer, unblock RX */ - dev->recv_blocked = false; - if (kw41zrf_can_switch_to_idle(dev)) { - kw41zrf_abort_sequence(dev); - kw41zrf_set_sequence(dev, dev->idle_seq); - } + kw41zrf_unblock_rx(dev); } /* No set_sequence(idle_seq) here, keep transceiver turned on if the * buffer was not discarded, we expect the higher layer to call again @@ -349,11 +353,7 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in } /* Go back to RX mode */ - dev->recv_blocked = false; - if (kw41zrf_can_switch_to_idle(dev)) { - kw41zrf_abort_sequence(dev); - kw41zrf_set_sequence(dev, dev->idle_seq); - } + kw41zrf_unblock_rx(dev); return pkt_len; } @@ -579,7 +579,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) } /* The below settings require the transceiver to be powered on */ - bool put_to_sleep_when_done = false; + unsigned put_to_sleep_when_done = 0; if (kw41zrf_is_dsm()) { /* Transceiver is in deep sleep mode */ switch (opt) { @@ -594,7 +594,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) #else DEBUG("[kw41zrf] Wake to get opt %d\n", (int)opt); #endif - put_to_sleep_when_done = true; + put_to_sleep_when_done = 1; break; default: @@ -782,7 +782,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; } - bool put_to_sleep_when_done = false; + unsigned put_to_sleep_when_done = 0; if (kw41zrf_is_dsm()) { /* Transceiver is in deep sleep mode, check if setting the option @@ -805,7 +805,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, #else DEBUG("[kw41zrf] Wake to set opt %d\n", (int)opt); #endif - put_to_sleep_when_done = true; + put_to_sleep_when_done = 1; break; default: @@ -1050,7 +1050,7 @@ static uint32_t _isr_event_seq_r(kw41zrf_t *dev, uint32_t irqsts) /* No error reported */ DEBUG("[kw41zrf] success (R)\n"); /* Block XCVSEQ_RECEIVE until netdev->recv has been called */ - dev->recv_blocked = true; + dev->recv_blocked = 1; kw41zrf_set_sequence(dev, dev->idle_seq); if (dev->flags & KW41ZRF_OPT_TELL_RX_END) { dev->netdev.netdev.event_callback(&dev->netdev.netdev, NETDEV_EVENT_RX_COMPLETE); diff --git a/drivers/kw41zrf/kw41zrf_xcvr.c b/drivers/kw41zrf/kw41zrf_xcvr.c index 8e65b28b5579..fcb9d816c43e 100644 --- a/drivers/kw41zrf/kw41zrf_xcvr.c +++ b/drivers/kw41zrf/kw41zrf_xcvr.c @@ -277,7 +277,7 @@ static void kw41zrf_dcoc_dac_init_cal(void) uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0; uint8_t i = 0; uint8_t bba_gain = 11; - bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; + uint8_t TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; uint32_t temp; From 9dffa28d0d1242937ca6d2403305c0c2a8e93d8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 31 Oct 2018 14:33:56 +0100 Subject: [PATCH 67/82] examples/default: Add frdm-kw41z to netif boards list --- examples/default/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/default/Makefile b/examples/default/Makefile index a8425efae824..2fefb55d3998 100644 --- a/examples/default/Makefile +++ b/examples/default/Makefile @@ -36,7 +36,7 @@ USEMODULE += ps # include and auto-initialize all available sensors USEMODULE += saul_default -BOARD_PROVIDES_NETIF := acd52832 airfy-beacon b-l072z-lrwan1 cc2538dk fox iotlab-m3 iotlab-a8-m3 mulle \ +BOARD_PROVIDES_NETIF := acd52832 airfy-beacon b-l072z-lrwan1 cc2538dk fox frdm-kw41z iotlab-m3 iotlab-a8-m3 mulle \ microbit native nrf51dk nrf51dongle nrf52dk nrf6310 openmote-cc2538 pba-d-01-kw2x \ remote-pa remote-reva samr21-xpro \ spark-core telosb yunjia-nrf51822 z1 From 063b038e69953ddd3d92fbe91c8d4b98344601a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 1 Dec 2018 14:49:26 +0100 Subject: [PATCH 68/82] usb-kw41z: Add settings for SoC radio --- boards/usb-kw41z/Makefile.dep | 4 ++++ examples/default/Makefile | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/boards/usb-kw41z/Makefile.dep b/boards/usb-kw41z/Makefile.dep index 72bad09a7217..f8c30fb386b6 100644 --- a/boards/usb-kw41z/Makefile.dep +++ b/boards/usb-kw41z/Makefile.dep @@ -3,4 +3,8 @@ ifneq (,$(filter saul_default,$(USEMODULE))) USEMODULE += saul_gpio endif +ifneq (,$(filter netdev_default gnrc_netdev_default,$(USEMODULE))) + USEMODULE += kw41zrf +endif + include $(RIOTCPU)/kinetis/Makefile.dep diff --git a/examples/default/Makefile b/examples/default/Makefile index 2fefb55d3998..d9e5ae39dc98 100644 --- a/examples/default/Makefile +++ b/examples/default/Makefile @@ -39,7 +39,7 @@ USEMODULE += saul_default BOARD_PROVIDES_NETIF := acd52832 airfy-beacon b-l072z-lrwan1 cc2538dk fox frdm-kw41z iotlab-m3 iotlab-a8-m3 mulle \ microbit native nrf51dk nrf51dongle nrf52dk nrf6310 openmote-cc2538 pba-d-01-kw2x \ remote-pa remote-reva samr21-xpro \ - spark-core telosb yunjia-nrf51822 z1 + spark-core telosb usb-kw41z yunjia-nrf51822 z1 ifneq (,$(filter $(BOARD),$(BOARD_PROVIDES_NETIF))) # Use modules for networking From 767f6ebc320f792d360ae42dd6e2b1a357474b35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Sat, 1 Dec 2018 14:56:56 +0100 Subject: [PATCH 69/82] usb-kw41z: kw41zrf LED settings --- drivers/kw41zrf/include/kw41zrf_intern.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index b06309bf32c1..2cbd620fefe9 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -32,6 +32,24 @@ #if ENABLE_LEDS /* For LED macros */ #include "board.h" +#ifdef BOARD_USB_KW41Z +/* Combine LED functions for this board */ +#ifdef LED0_ON +#define LED_RX_ON LED0_ON +#define LED_RX_OFF LED0_OFF +#define LED_TX_ON LED0_ON +#define LED_TX_OFF LED0_OFF +#else +#define LED_TX_ON +#define LED_TX_OFF +#define LED_RX_ON +#define LED_RX_OFF +#endif +#define LED_NDSM_ON +#define LED_NDSM_OFF +#define LED_IRQ_ON +#define LED_IRQ_OFF +#else #ifdef LED0_ON #define LED_NDSM_ON LED0_ON #define LED_NDSM_OFF LED0_OFF @@ -48,6 +66,7 @@ #define LED_IRQ_ON LED3_ON #define LED_IRQ_OFF LED3_OFF #endif +#endif #else /* ENABLE_LEDS */ #define LED_NDSM_ON #define LED_NDSM_OFF From e30291e1792253092d31ae6b67ddc3fbadc14850 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Thu, 6 Dec 2018 14:38:59 +0100 Subject: [PATCH 70/82] squash kw41zrf: Refactor power management to make pm_layered optional --- drivers/kw41zrf/include/kw41zrf_intern.h | 9 +++++++++ drivers/kw41zrf/kw41zrf_intern.c | 5 ++--- drivers/kw41zrf/kw41zrf_netdev.c | 5 ++--- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 2cbd620fefe9..193d766fa28c 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -27,6 +27,15 @@ /* For ZLL CPU registers */ #include "cpu.h" +#ifdef MODULE_PM_LAYERED +#include "pm_layered.h" +#define PM_BLOCK(x) pm_block(x) +#define PM_UNBLOCK(x) pm_unblock(x) +#else +#define PM_BLOCK(x) +#define PM_UNBLOCK(x) +#endif + #define ENABLE_LEDS (1) #if ENABLE_LEDS diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index f1934f3a164a..bad138db6c51 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -21,7 +21,6 @@ #include "kw41zrf.h" #include "kw41zrf_getset.h" #include "kw41zrf_intern.h" -#include "pm_layered.h" #define ENABLE_DEBUG (0) #include "debug.h" @@ -63,7 +62,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Disable some CPU power management if we need to be active, otherwise the * radio will be stuck in state retention mode. */ if (!dev->pm_blocked) { - pm_block(KINETIS_PM_LLS); + PM_BLOCK(KINETIS_PM_LLS); dev->pm_blocked = 1; } /* Restore saved RF oscillator settings, enable oscillator in RUN mode @@ -119,7 +118,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) break; } if (dev->pm_blocked) { - pm_unblock(KINETIS_PM_LLS); + PM_UNBLOCK(KINETIS_PM_LLS); dev->pm_blocked = 0; } /* Race condition: if sleep is re-triggered after wake before the diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 05cba26960f2..abb6983e9445 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -28,7 +28,6 @@ #include "net/ieee802154.h" #include "net/netdev.h" #include "net/netdev/ieee802154.h" -#include "pm_layered.h" #include "kw41zrf.h" #include "kw41zrf_netdev.h" @@ -187,7 +186,7 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) DEBUG("[kw41zrf] waiting for idle\n"); num_irqs_handled = num_irqs_queued; spinning_for_irq = 1; - pm_block(KINETIS_PM_LLS); + PM_BLOCK(KINETIS_PM_LLS); while (1) { /* TX or CCA in progress */ /* Block until we get an IRQ */ @@ -201,7 +200,7 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) } DEBUG("[kw41zrf] waited ISR\n"); } - pm_unblock(KINETIS_PM_LLS); + PM_UNBLOCK(KINETIS_PM_LLS); spinning_for_irq = 0; DEBUG("[kw41zrf] previous TX done\n"); } From 4f561b9fdce899eed8125854b9b21bc66f8f22d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 7 Dec 2018 14:46:09 +0100 Subject: [PATCH 71/82] squash kw41zrf clean up LED configuration --- drivers/kw41zrf/include/kw41zrf_intern.h | 65 +++++++++++++----------- 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 193d766fa28c..a0c1fb8e3a2b 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -36,46 +36,53 @@ #define PM_UNBLOCK(x) #endif +/* Set to 1 to use on board LEDs to show RX/TX activity */ #define ENABLE_LEDS (1) #if ENABLE_LEDS /* For LED macros */ #include "board.h" -#ifdef BOARD_USB_KW41Z -/* Combine LED functions for this board */ -#ifdef LED0_ON -#define LED_RX_ON LED0_ON -#define LED_RX_OFF LED0_OFF -#define LED_TX_ON LED0_ON -#define LED_TX_OFF LED0_OFF -#else -#define LED_TX_ON -#define LED_TX_OFF +#if !defined(LED_RX_ON) +#if defined(LED0_ON) +#define LED_RX_ON LED0_ON +#define LED_RX_OFF LED0_OFF +#else /* defined(LED0_ON) */ #define LED_RX_ON #define LED_RX_OFF -#endif +#endif /* defined(LED0_ON) */ +#endif /* !defined(LED_RX_ON) */ +#if !defined(LED_TX_ON) +#if defined(LED1_ON) +/* Separate TX LED */ +#define LED_TX_ON LED1_ON +#define LED_TX_OFF LED1_OFF +#elif defined(LED0_ON) +/* Combined RX+TX in one LED */ +#define LED_TX_ON LED0_ON +#define LED_TX_OFF LED0_OFF +#else /* defined(LEDx_ON) */ +#define LED_TX_ON +#define LED_TX_OFF +#endif /* defined(LEDx_ON) */ +#endif /* !defined(LED_TX_ON) */ +#if !defined(LED_NDSM_ON) +#if defined(LED2_ON) +#define LED_NDSM_ON LED2_ON +#define LED_NDSM_OFF LED2_OFF +#else /* defined(LEDx_ON) */ #define LED_NDSM_ON #define LED_NDSM_OFF +#endif /* defined(LEDx_ON) */ +#endif /* !defined(LED_NDSM_ON) */ +#if !defined(LED_IRQ_ON) +#if defined(LED3_ON) +#define LED_IRQ_ON LED3_ON +#define LED_IRQ_OFF LED3_OFF +#else /* defined(LEDx_ON) */ #define LED_IRQ_ON #define LED_IRQ_OFF -#else -#ifdef LED0_ON -#define LED_NDSM_ON LED0_ON -#define LED_NDSM_OFF LED0_OFF -#endif -#ifdef LED1_ON -#define LED_TX_ON LED1_ON -#define LED_TX_OFF LED1_OFF -#endif -#ifdef LED2_ON -#define LED_RX_ON LED2_ON -#define LED_RX_OFF LED2_OFF -#endif -#ifdef LED3_ON -#define LED_IRQ_ON LED3_ON -#define LED_IRQ_OFF LED3_OFF -#endif -#endif +#endif /* defined(LEDx_ON) */ +#endif /* !defined(LED_IRQ_ON) */ #else /* ENABLE_LEDS */ #define LED_NDSM_ON #define LED_NDSM_OFF From fc7c841f1c0cddc129d865aa4e236d49c55f0b6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 10 Dec 2018 11:35:39 +0100 Subject: [PATCH 72/82] fixup! squash kw41zrf: Refactor power management to make pm_layered optional --- drivers/kw41zrf/include/kw41zrf_intern.h | 4 ++++ drivers/kw41zrf/kw41zrf_intern.c | 4 ++-- drivers/kw41zrf/kw41zrf_netdev.c | 4 ++-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index a0c1fb8e3a2b..c907860dd880 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -31,6 +31,10 @@ #include "pm_layered.h" #define PM_BLOCK(x) pm_block(x) #define PM_UNBLOCK(x) pm_unblock(x) +/* When the transceiver is not in DSM, this power mode will be blocked. + * TODO: Change this to symbolic name KINETIS_PM_LLS when Kinetis power + * management is merged (https://github.com/RIOT-OS/RIOT/pull/7897) */ +#define KW41ZRF_PM_BLOCKER 0 #else #define PM_BLOCK(x) #define PM_UNBLOCK(x) diff --git a/drivers/kw41zrf/kw41zrf_intern.c b/drivers/kw41zrf/kw41zrf_intern.c index bad138db6c51..7b265828d76a 100644 --- a/drivers/kw41zrf/kw41zrf_intern.c +++ b/drivers/kw41zrf/kw41zrf_intern.c @@ -62,7 +62,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) /* Disable some CPU power management if we need to be active, otherwise the * radio will be stuck in state retention mode. */ if (!dev->pm_blocked) { - PM_BLOCK(KINETIS_PM_LLS); + PM_BLOCK(KW41ZRF_PM_BLOCKER); dev->pm_blocked = 1; } /* Restore saved RF oscillator settings, enable oscillator in RUN mode @@ -118,7 +118,7 @@ void kw41zrf_set_power_mode(kw41zrf_t *dev, kw41zrf_powermode_t pm) break; } if (dev->pm_blocked) { - PM_UNBLOCK(KINETIS_PM_LLS); + PM_UNBLOCK(KW41ZRF_PM_BLOCKER); dev->pm_blocked = 0; } /* Race condition: if sleep is re-triggered after wake before the diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index abb6983e9445..3b31eac4ee67 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -186,7 +186,7 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) DEBUG("[kw41zrf] waiting for idle\n"); num_irqs_handled = num_irqs_queued; spinning_for_irq = 1; - PM_BLOCK(KINETIS_PM_LLS); + PM_BLOCK(KW41ZRF_PM_BLOCKER); while (1) { /* TX or CCA in progress */ /* Block until we get an IRQ */ @@ -200,7 +200,7 @@ static void kw41zrf_wait_idle(kw41zrf_t *dev) } DEBUG("[kw41zrf] waited ISR\n"); } - PM_UNBLOCK(KINETIS_PM_LLS); + PM_UNBLOCK(KW41ZRF_PM_BLOCKER); spinning_for_irq = 0; DEBUG("[kw41zrf] previous TX done\n"); } From e4af47c0b5886a57f4688439d06f700789ab209d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 10 Dec 2018 14:44:03 +0100 Subject: [PATCH 73/82] squash kw41zrf rm old vendor headers --- cpu/kw41z/include/vendor/MKW21Z4_features.h | 1781 ---------------- cpu/kw41z/include/vendor/MKW31Z4_features.h | 2016 ------------------ cpu/kw41z/include/vendor/MKW41Z4_features.h | 2020 ------------------- 3 files changed, 5817 deletions(-) delete mode 100644 cpu/kw41z/include/vendor/MKW21Z4_features.h delete mode 100644 cpu/kw41z/include/vendor/MKW31Z4_features.h delete mode 100644 cpu/kw41z/include/vendor/MKW41Z4_features.h diff --git a/cpu/kw41z/include/vendor/MKW21Z4_features.h b/cpu/kw41z/include/vendor/MKW21Z4_features.h deleted file mode 100644 index f9e93c01dc69..000000000000 --- a/cpu/kw41z/include/vendor/MKW21Z4_features.h +++ /dev/null @@ -1,1781 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2015-09-23 -** Build: b170228 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _MKW21Z4_FEATURES_H_ -#define _MKW21Z4_FEATURES_H_ - -/* SOC module features */ - -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (1) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (1) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (1) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (1) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (2) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (0) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_ENET_COUNT (0) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (0) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (3) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (1) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (3) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (2) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (0) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (1) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (0) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (0) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (1) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (1) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (1) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (1) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief SYSMPU availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (1) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (3) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (0) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (1) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (1) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (0) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (3) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (1) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBHS availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHS_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (1) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (0) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (0) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (1) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (1) - -/* ADC16 module features */ - -/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ -#define FSL_FEATURE_ADC16_HAS_PGA (0) -/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) -/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) -/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ -#define FSL_FEATURE_ADC16_HAS_DMA (1) -/* @brief Has differential mode (bitfield SC1x[DIFF]). */ -#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) -/* @brief Has FIFO (bit SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_HAS_FIFO (0) -/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_FIFO_SIZE (0) -/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ -#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) -/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ -#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) -/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ -#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) -/* @brief Has HW averaging (bit SC3[AVGE]). */ -#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) -/* @brief Has offset correction (register OFS). */ -#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) -/* @brief Maximum ADC resolution. */ -#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) -/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ -#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) - -/* CMP module features */ - -/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ -#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) -/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ -#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) -/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ -#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) -/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ -#define FSL_FEATURE_CMP_HAS_DMA (1) -/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ -#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) -/* @brief Has DAC Test function in CMP (register DACTEST). */ -#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) - -/* COP module features */ - -/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ -#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) -/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ -#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) -/* @brief Has more clock sources like MCGIRC */ -#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) -/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ -#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) - -/* DAC module features */ - -/* @brief Define the size of hardware buffer */ -#define FSL_FEATURE_DAC_BUFFER_SIZE (2) -/* @brief Define whether the buffer supports watermark event detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) -/* @brief Define whether the buffer supports watermark selection detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) -/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) -/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) -/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) -/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) -/* @brief Define whether FIFO buffer mode is available or not. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) -/* @brief Define whether swing buffer mode is available or not.. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) - -/* DCDC module features */ - -/* @brief Has VDD1P5 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) -/* @brief Has VDD1P45 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) - -/* FLASH module features */ - -#if defined(CPU_MKW21Z256VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#elif defined(CPU_MKW21Z512VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#endif /* defined(CPU_MKW21Z256VHT4) */ - -/* GENFSK module features */ - -/* No feature definitions */ - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* I2C module features */ - -/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ -#define FSL_FEATURE_I2C_HAS_SMBUS (1) -/* @brief Maximum supported baud rate in kilobit per second. */ -#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) -/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ -#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) -/* @brief Has DMA support (register bit C1[DMAEN]). */ -#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) -/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) -/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) -/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ -#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) -/* @brief Maximum width of the glitch filter in number of bus clocks. */ -#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) -/* @brief Has control of the drive capability of the I2C pins. */ -#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) -/* @brief Has double buffering support (register S2). */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) -/* @brief Has double buffer enable. */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) - -/* LLWU module features */ - -/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) -/* @brief Has pins 8-15 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) -/* @brief Maximum number of internal modules connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) -/* @brief Number of digital filters. */ -#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) -/* @brief Has MF register. */ -#define FSL_FEATURE_LLWU_HAS_MF (0) -/* @brief Has PF register. */ -#define FSL_FEATURE_LLWU_HAS_PF (0) -/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ -#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) -/* @brief Has no internal module wakeup flag register. */ -#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) -/* @brief Has external pin 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) -/* @brief Has external pin 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) -/* @brief Has external pin 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) -/* @brief Has external pin 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) -/* @brief Has external pin 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) -/* @brief Has external pin 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) -/* @brief Has external pin 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) -/* @brief Has external pin 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) -/* @brief Has external pin 8 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) -/* @brief Has external pin 9 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) -/* @brief Has external pin 10 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) -/* @brief Has external pin 11 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) -/* @brief Has external pin 12 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) -/* @brief Has external pin 13 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) -/* @brief Has external pin 14 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) -/* @brief Has external pin 15 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) -/* @brief Has external pin 16 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) -/* @brief Has external pin 17 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) -/* @brief Has external pin 18 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) -/* @brief Has external pin 19 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) -/* @brief Has external pin 20 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) -/* @brief Has external pin 21 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) -/* @brief Has external pin 22 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) -/* @brief Has external pin 23 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) -/* @brief Has external pin 24 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) -/* @brief Has external pin 25 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) -/* @brief Has external pin 26 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) -/* @brief Has external pin 27 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) -/* @brief Has external pin 28 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) -/* @brief Has external pin 29 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) -/* @brief Has external pin 30 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) -/* @brief Has external pin 31 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) -/* @brief Index of port of external pin. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) -/* @brief Number of external pin port on specified port. */ -#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) -/* @brief Has internal module 0 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) -/* @brief Has internal module 1 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) -/* @brief Has internal module 2 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) -/* @brief Has internal module 3 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) -/* @brief Has internal module 4 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) -/* @brief Has internal module 5 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) -/* @brief Has internal module 6 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) -/* @brief Has internal module 7 connected to LLWU device. */ -#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) -/* @brief Has Version ID Register (LLWU_VERID). */ -#define FSL_FEATURE_LLWU_HAS_VERID (0) -/* @brief Has Parameter Register (LLWU_PARAM). */ -#define FSL_FEATURE_LLWU_HAS_PARAM (0) -/* @brief Width of registers of the LLWU. */ -#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) -/* @brief Has DMA Enable register (LLWU_DE). */ -#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) -/* @brief Whether LPTMR counter is 32 bits width. */ -#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) -/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ -#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) - -/* LPUART module features */ - -/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ -#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (0) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (0) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (0) - -/* LTC module features */ - -/* @brief LTC module supports DES algorithm. */ -#define FSL_FEATURE_LTC_HAS_DES (0) -/* @brief LTC module supports PKHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_PKHA (0) -/* @brief LTC module supports SHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_SHA (0) -/* @brief LTC module supports AES GCM mode. */ -#define FSL_FEATURE_LTC_HAS_GCM (0) -/* @brief LTC module supports DPAMS registers. */ -#define FSL_FEATURE_LTC_HAS_DPAMS (0) -/* @brief LTC module supports AES with 24 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES192 (0) -/* @brief LTC module supports AES with 32 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES256 (0) - -/* MCG module features */ - -/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) -/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) -/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) -/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MIN (0) -/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MAX (0) -/* @brief The PLL clock is divided by 2 before VCO divider. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) -/* @brief FRDIV supports 1280. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) -/* @brief FRDIV supports 1536. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) -/* @brief MCGFFCLK divider. */ -#define FSL_FEATURE_MCG_FFCLK_DIV (1) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ -#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) -/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ -#define FSL_FEATURE_MCG_HAS_RTC_32K (1) -/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_PLL1 (0) -/* @brief Has 48MHz internal oscillator. */ -#define FSL_FEATURE_MCG_HAS_IRC_48M (0) -/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_OSC1 (0) -/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ -#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) -/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ -#define FSL_FEATURE_MCG_HAS_LOLRE (0) -/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ -#define FSL_FEATURE_MCG_USE_OSCSEL (1) -/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ -#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) -/* @brief TBD */ -#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) -/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ -#define FSL_FEATURE_MCG_HAS_PLL (0) -/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) -/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) -/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ -#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) -/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ -#define FSL_FEATURE_MCG_HAS_FLL (1) -/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) -/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ -#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) -/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) -/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) -/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ -#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) -/* @brief Has external clock monitor (register bit C6[CME]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) -/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ -#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) -/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ -#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -/* @brief Has PEI mode or PBI mode. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) -/* @brief Reset clock mode is BLPI. */ -#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) - -/* PIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_PIT_TIMER_COUNT (2) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) - -/* PMC module features */ - -/* @brief Has Bandgap Enable In VLPx Operation support. */ -#define FSL_FEATURE_PMC_HAS_BGEN (0) -/* @brief Has Bandgap Buffer Enable. */ -#define FSL_FEATURE_PMC_HAS_BGBE (1) -/* @brief Has Bandgap Buffer Drive Select. */ -#define FSL_FEATURE_PMC_HAS_BGBDS (0) -/* @brief Has Low-Voltage Detect Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVDV (1) -/* @brief Has Low-Voltage Warning Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVWV (1) -/* @brief Has LPO. */ -#define FSL_FEATURE_PMC_HAS_LPO (0) -/* @brief Has VLPx option PMC_REGSC[VLPO]. */ -#define FSL_FEATURE_PMC_HAS_VLPO (1) -/* @brief Has acknowledge isolation support. */ -#define FSL_FEATURE_PMC_HAS_ACKISO (1) -/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ -#define FSL_FEATURE_PMC_HAS_REGFPM (0) -/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ -#define FSL_FEATURE_PMC_HAS_REGONS (1) -/* @brief Has PMC_HVDSC1. */ -#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) -/* @brief Has PMC_PARAM. */ -#define FSL_FEATURE_PMC_HAS_PARAM (0) -/* @brief Has PMC_VERID. */ -#define FSL_FEATURE_PMC_HAS_VERID (0) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) -/* @brief Has DMA request (register bit field PCR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Has separate drive strength register (HDRVE). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) -/* @brief Has glitch filter (register IOFLT). */ -#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ -#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) - -/* RADIO module features */ - -/* @brief Zigbee availability. */ -#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) -/* @brief Bluetooth availability. */ -#define FSL_FEATURE_RADIO_HAS_BLE (0) -/* @brief ANT availability */ -#define FSL_FEATURE_RADIO_HAS_ANT (1) -/* @brief Generic FSK module availability */ -#define FSL_FEATURE_RADIO_HAS_GENFSK (1) -/* @brief Major version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) -/* @brief Minor version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MINOR (0) - -/* RCM module features */ - -/* @brief Has Loss-of-Lock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOL (0) -/* @brief Has Loss-of-Clock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOC (1) -/* @brief Has JTAG generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_JTAG (0) -/* @brief Has EzPort generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_EZPORT (0) -/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ -#define FSL_FEATURE_RCM_HAS_EZPMS (0) -/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ -#define FSL_FEATURE_RCM_HAS_BOOTROM (0) -/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ -#define FSL_FEATURE_RCM_HAS_SSRS (0) -/* @brief Has Version ID Register (RCM_VERID). */ -#define FSL_FEATURE_RCM_HAS_VERID (0) -/* @brief Has Parameter Register (RCM_PARAM). */ -#define FSL_FEATURE_RCM_HAS_PARAM (0) -/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ -#define FSL_FEATURE_RCM_HAS_SRIE (0) -/* @brief Width of registers of the RCM. */ -#define FSL_FEATURE_RCM_REG_WIDTH (8) -/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ -#define FSL_FEATURE_RCM_HAS_CORE1 (0) -/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ -#define FSL_FEATURE_RCM_HAS_MDM_AP (1) -/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ -#define FSL_FEATURE_RCM_HAS_WAKEUP (1) - -/* RSIM module features */ - -/* No feature definitions */ - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (0) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (0) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (0) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (1) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (1) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (1) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (0) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (0) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (0) -/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ -#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) -/* @brief Has tamper reset (register bit SRS[TAMPER]). */ -#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) -/* @brief Has security violation reset (register bit SRS[SECVIO]). */ -#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) - -/* DSPI module features */ - -/* @brief Receive/transmit FIFO size in number of items. */ -#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) -/* @brief Maximum transfer data width in bits. */ -#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) -/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ -#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) -/* @brief Number of chip select pins. */ -#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) -/* @brief Has chip select strobe capability on the PCS5 pin. */ -#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) -/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) -/* @brief Has 16-bit data transfer support. */ -#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) - -/* TPM module features */ - -/* @brief Bus clock is the source clock for the module. */ -#define FSL_FEATURE_TPM_BUS_CLOCK (0) -/* @brief Number of channels. */ -#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ - ((x) == TPM0 ? (4) : \ - ((x) == TPM1 ? (2) : \ - ((x) == TPM2 ? (2) : (-1)))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Has TPM_PARAM. */ -#define FSL_FEATURE_TPM_HAS_PARAM (0) -/* @brief Has TPM_VERID. */ -#define FSL_FEATURE_TPM_HAS_VERID (0) -/* @brief Has TPM_GLOBAL. */ -#define FSL_FEATURE_TPM_HAS_GLOBAL (0) -/* @brief Has TPM_TRIG. */ -#define FSL_FEATURE_TPM_HAS_TRIG (0) -/* @brief Has counter pause on trigger. */ -#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) -/* @brief Has external trigger selection. */ -#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) -/* @brief Has TPM_COMBINE register. */ -#define FSL_FEATURE_TPM_HAS_COMBINE (1) -/* @brief Whether COMBINE register has effect. */ -#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_POL. */ -#define FSL_FEATURE_TPM_HAS_POL (1) -/* @brief Has TPM_FILTER register. */ -#define FSL_FEATURE_TPM_HAS_FILTER (1) -/* @brief Whether FILTER register has effect. */ -#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_QDCTRL register. */ -#define FSL_FEATURE_TPM_HAS_QDCTRL (1) -/* @brief Whether QDCTRL register has effect. */ -#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) - -/* TRNG module features */ - -/* No feature definitions */ - -/* TSI module features */ - -/* @brief TSI module version. */ -#define FSL_FEATURE_TSI_VERSION (4) -/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ -#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) -/* @brief Number of TSI channels. */ -#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (0) - -/* XCVR_ANALOG module features */ - -/* No feature definitions */ - -/* XCVR_PHY module features */ - -/* No feature definitions */ - -/* ZLL module features */ - -/* No feature definitions */ - -#endif /* _MKW21Z4_FEATURES_H_ */ - diff --git a/cpu/kw41z/include/vendor/MKW31Z4_features.h b/cpu/kw41z/include/vendor/MKW31Z4_features.h deleted file mode 100644 index 56b14a01a5b4..000000000000 --- a/cpu/kw41z/include/vendor/MKW31Z4_features.h +++ /dev/null @@ -1,2016 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2015-09-23 -** Build: b170228 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _MKW31Z4_FEATURES_H_ -#define _MKW31Z4_FEATURES_H_ - -/* SOC module features */ - -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (1) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (1) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (1) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (1) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (2) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (0) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_ENET_COUNT (0) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (0) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (3) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (1) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (3) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (2) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (0) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (1) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (0) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (0) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (1) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (1) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (1) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (1) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief SYSMPU availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (1) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (3) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (0) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (1) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (1) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (0) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (3) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (1) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBHS availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHS_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (1) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (0) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (0) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (1) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (1) - -/* ADC16 module features */ - -/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ -#define FSL_FEATURE_ADC16_HAS_PGA (0) -/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) -/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) -/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ -#define FSL_FEATURE_ADC16_HAS_DMA (1) -/* @brief Has differential mode (bitfield SC1x[DIFF]). */ -#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) -/* @brief Has FIFO (bit SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_HAS_FIFO (0) -/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_FIFO_SIZE (0) -/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ -#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) -/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ -#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) -/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ -#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) -/* @brief Has HW averaging (bit SC3[AVGE]). */ -#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) -/* @brief Has offset correction (register OFS). */ -#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) -/* @brief Maximum ADC resolution. */ -#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) -/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ -#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) - -/* BTLE_RF module features */ - -/* No feature definitions */ - -/* CMP module features */ - -/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ -#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) -/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ -#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) -/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ -#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) -/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ -#define FSL_FEATURE_CMP_HAS_DMA (1) -/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ -#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) -/* @brief Has DAC Test function in CMP (register DACTEST). */ -#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) - -/* COP module features */ - -/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ -#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) -/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ -#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) -/* @brief Has more clock sources like MCGIRC */ -#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) -/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ -#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) - -/* DAC module features */ - -/* @brief Define the size of hardware buffer */ -#define FSL_FEATURE_DAC_BUFFER_SIZE (2) -/* @brief Define whether the buffer supports watermark event detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) -/* @brief Define whether the buffer supports watermark selection detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) -/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) -/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) -/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) -/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) -/* @brief Define whether FIFO buffer mode is available or not. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) -/* @brief Define whether swing buffer mode is available or not.. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) - -/* DCDC module features */ - -/* @brief Has VDD1P5 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) -/* @brief Has VDD1P45 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) - -/* FLASH module features */ - -#if defined(CPU_MKW31Z256VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#elif defined(CPU_MKW31Z512CAT4) || defined(CPU_MKW31Z512VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#endif /* defined(CPU_MKW31Z256VHT4) */ - -/* GENFSK module features */ - -/* No feature definitions */ - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* I2C module features */ - -/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ -#define FSL_FEATURE_I2C_HAS_SMBUS (1) -/* @brief Maximum supported baud rate in kilobit per second. */ -#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) -/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ -#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) -/* @brief Has DMA support (register bit C1[DMAEN]). */ -#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) -/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) -/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) -/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ -#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) -/* @brief Maximum width of the glitch filter in number of bus clocks. */ -#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) -/* @brief Has control of the drive capability of the I2C pins. */ -#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) -/* @brief Has double buffering support (register S2). */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) -/* @brief Has double buffer enable. */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) - -/* LLWU module features */ - -#if defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) - /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Has pins 8-15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has MF register. */ - #define FSL_FEATURE_LLWU_HAS_MF (0) - /* @brief Has PF register. */ - #define FSL_FEATURE_LLWU_HAS_PF (0) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) - /* @brief Has no internal module wakeup flag register. */ - #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) - /* @brief Has external pin 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) - /* @brief Has external pin 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) - /* @brief Has external pin 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) - /* @brief Has external pin 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) - /* @brief Has external pin 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) - /* @brief Has external pin 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) - /* @brief Has external pin 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) - /* @brief Has external pin 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) - /* @brief Has external pin 8 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) - /* @brief Has external pin 9 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) - /* @brief Has external pin 10 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) - /* @brief Has external pin 11 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) - /* @brief Has external pin 12 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) - /* @brief Has external pin 13 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) - /* @brief Has external pin 14 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) - /* @brief Has external pin 15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) - /* @brief Has external pin 16 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) - /* @brief Has external pin 17 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) - /* @brief Has external pin 18 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) - /* @brief Has external pin 19 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) - /* @brief Has external pin 20 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) - /* @brief Has external pin 21 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) - /* @brief Has external pin 22 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) - /* @brief Has external pin 23 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) - /* @brief Has external pin 24 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) - /* @brief Has external pin 25 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) - /* @brief Has external pin 26 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) - /* @brief Has external pin 27 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) - /* @brief Has external pin 28 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) - /* @brief Has external pin 29 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) - /* @brief Has external pin 30 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) - /* @brief Has external pin 31 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) - /* @brief Has internal module 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) - /* @brief Has internal module 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) - /* @brief Has internal module 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) - /* @brief Has internal module 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) - /* @brief Has internal module 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) - /* @brief Has internal module 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) - /* @brief Has internal module 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) - /* @brief Has internal module 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) - /* @brief Has Version ID Register (LLWU_VERID). */ - #define FSL_FEATURE_LLWU_HAS_VERID (0) - /* @brief Has Parameter Register (LLWU_PARAM). */ - #define FSL_FEATURE_LLWU_HAS_PARAM (0) - /* @brief Width of registers of the LLWU. */ - #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) - /* @brief Has DMA Enable register (LLWU_DE). */ - #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) -#elif defined(CPU_MKW31Z512CAT4) - /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Has pins 8-15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has MF register. */ - #define FSL_FEATURE_LLWU_HAS_MF (0) - /* @brief Has PF register. */ - #define FSL_FEATURE_LLWU_HAS_PF (0) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) - /* @brief Has no internal module wakeup flag register. */ - #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) - /* @brief Has external pin 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) - /* @brief Has external pin 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) - /* @brief Has external pin 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) - /* @brief Has external pin 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) - /* @brief Has external pin 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) - /* @brief Has external pin 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) - /* @brief Has external pin 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) - /* @brief Has external pin 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) - /* @brief Has external pin 8 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) - /* @brief Has external pin 9 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) - /* @brief Has external pin 10 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) - /* @brief Has external pin 11 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) - /* @brief Has external pin 12 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) - /* @brief Has external pin 13 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) - /* @brief Has external pin 14 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) - /* @brief Has external pin 15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) - /* @brief Has external pin 16 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) - /* @brief Has external pin 17 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) - /* @brief Has external pin 18 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) - /* @brief Has external pin 19 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) - /* @brief Has external pin 20 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) - /* @brief Has external pin 21 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) - /* @brief Has external pin 22 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) - /* @brief Has external pin 23 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) - /* @brief Has external pin 24 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) - /* @brief Has external pin 25 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) - /* @brief Has external pin 26 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) - /* @brief Has external pin 27 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) - /* @brief Has external pin 28 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) - /* @brief Has external pin 29 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) - /* @brief Has external pin 30 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) - /* @brief Has external pin 31 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) - /* @brief Has internal module 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) - /* @brief Has internal module 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) - /* @brief Has internal module 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) - /* @brief Has internal module 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) - /* @brief Has internal module 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) - /* @brief Has internal module 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) - /* @brief Has internal module 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) - /* @brief Has internal module 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) - /* @brief Has Version ID Register (LLWU_VERID). */ - #define FSL_FEATURE_LLWU_HAS_VERID (0) - /* @brief Has Parameter Register (LLWU_PARAM). */ - #define FSL_FEATURE_LLWU_HAS_PARAM (0) - /* @brief Width of registers of the LLWU. */ - #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) - /* @brief Has DMA Enable register (LLWU_DE). */ - #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) -#endif /* defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) */ - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) -/* @brief Whether LPTMR counter is 32 bits width. */ -#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) -/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ -#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) - -/* LPUART module features */ - -/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ -#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (0) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (0) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (0) - -/* LTC module features */ - -/* @brief LTC module supports DES algorithm. */ -#define FSL_FEATURE_LTC_HAS_DES (0) -/* @brief LTC module supports PKHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_PKHA (0) -/* @brief LTC module supports SHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_SHA (0) -/* @brief LTC module supports AES GCM mode. */ -#define FSL_FEATURE_LTC_HAS_GCM (0) -/* @brief LTC module supports DPAMS registers. */ -#define FSL_FEATURE_LTC_HAS_DPAMS (0) -/* @brief LTC module supports AES with 24 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES192 (0) -/* @brief LTC module supports AES with 32 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES256 (0) - -/* MCG module features */ - -/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) -/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) -/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) -/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MIN (0) -/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MAX (0) -/* @brief The PLL clock is divided by 2 before VCO divider. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) -/* @brief FRDIV supports 1280. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) -/* @brief FRDIV supports 1536. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) -/* @brief MCGFFCLK divider. */ -#define FSL_FEATURE_MCG_FFCLK_DIV (1) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ -#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) -/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ -#define FSL_FEATURE_MCG_HAS_RTC_32K (1) -/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_PLL1 (0) -/* @brief Has 48MHz internal oscillator. */ -#define FSL_FEATURE_MCG_HAS_IRC_48M (0) -/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_OSC1 (0) -/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ -#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) -/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ -#define FSL_FEATURE_MCG_HAS_LOLRE (0) -/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ -#define FSL_FEATURE_MCG_USE_OSCSEL (1) -/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ -#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) -/* @brief TBD */ -#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) -/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ -#define FSL_FEATURE_MCG_HAS_PLL (0) -/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) -/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) -/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ -#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) -/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ -#define FSL_FEATURE_MCG_HAS_FLL (1) -/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) -/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ -#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) -/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) -/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) -/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ -#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) -/* @brief Has external clock monitor (register bit C6[CME]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) -/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ -#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) -/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ -#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -/* @brief Has PEI mode or PBI mode. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) -/* @brief Reset clock mode is BLPI. */ -#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) - -/* PIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_PIT_TIMER_COUNT (2) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) - -/* PMC module features */ - -/* @brief Has Bandgap Enable In VLPx Operation support. */ -#define FSL_FEATURE_PMC_HAS_BGEN (0) -/* @brief Has Bandgap Buffer Enable. */ -#define FSL_FEATURE_PMC_HAS_BGBE (1) -/* @brief Has Bandgap Buffer Drive Select. */ -#define FSL_FEATURE_PMC_HAS_BGBDS (0) -/* @brief Has Low-Voltage Detect Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVDV (1) -/* @brief Has Low-Voltage Warning Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVWV (1) -/* @brief Has LPO. */ -#define FSL_FEATURE_PMC_HAS_LPO (0) -/* @brief Has VLPx option PMC_REGSC[VLPO]. */ -#define FSL_FEATURE_PMC_HAS_VLPO (1) -/* @brief Has acknowledge isolation support. */ -#define FSL_FEATURE_PMC_HAS_ACKISO (1) -/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ -#define FSL_FEATURE_PMC_HAS_REGFPM (0) -/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ -#define FSL_FEATURE_PMC_HAS_REGONS (1) -/* @brief Has PMC_HVDSC1. */ -#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) -/* @brief Has PMC_PARAM. */ -#define FSL_FEATURE_PMC_HAS_PARAM (0) -/* @brief Has PMC_VERID. */ -#define FSL_FEATURE_PMC_HAS_VERID (0) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) -/* @brief Has DMA request (register bit field PCR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Has separate drive strength register (HDRVE). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) -/* @brief Has glitch filter (register IOFLT). */ -#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ -#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) - -/* RADIO module features */ - -/* @brief Zigbee availability. */ -#define FSL_FEATURE_RADIO_HAS_ZIGBEE (0) -/* @brief Bluetooth availability. */ -#define FSL_FEATURE_RADIO_HAS_BLE (1) -/* @brief ANT availability */ -#define FSL_FEATURE_RADIO_HAS_ANT (1) -/* @brief Generic FSK module availability */ -#define FSL_FEATURE_RADIO_HAS_GENFSK (1) -/* @brief Major version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) -/* @brief Minor version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MINOR (0) - -/* RCM module features */ - -/* @brief Has Loss-of-Lock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOL (0) -/* @brief Has Loss-of-Clock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOC (1) -/* @brief Has JTAG generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_JTAG (0) -/* @brief Has EzPort generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_EZPORT (0) -/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ -#define FSL_FEATURE_RCM_HAS_EZPMS (0) -/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ -#define FSL_FEATURE_RCM_HAS_BOOTROM (0) -/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ -#define FSL_FEATURE_RCM_HAS_SSRS (0) -/* @brief Has Version ID Register (RCM_VERID). */ -#define FSL_FEATURE_RCM_HAS_VERID (0) -/* @brief Has Parameter Register (RCM_PARAM). */ -#define FSL_FEATURE_RCM_HAS_PARAM (0) -/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ -#define FSL_FEATURE_RCM_HAS_SRIE (0) -/* @brief Width of registers of the RCM. */ -#define FSL_FEATURE_RCM_REG_WIDTH (8) -/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ -#define FSL_FEATURE_RCM_HAS_CORE1 (0) -/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ -#define FSL_FEATURE_RCM_HAS_MDM_AP (1) -/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ -#define FSL_FEATURE_RCM_HAS_WAKEUP (1) - -/* RSIM module features */ - -/* No feature definitions */ - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (0) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (0) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (0) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (1) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (1) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (1) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (0) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (0) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (0) -/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ -#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) -/* @brief Has tamper reset (register bit SRS[TAMPER]). */ -#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) -/* @brief Has security violation reset (register bit SRS[SECVIO]). */ -#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) - -/* DSPI module features */ - -/* @brief Receive/transmit FIFO size in number of items. */ -#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) -/* @brief Maximum transfer data width in bits. */ -#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) -/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ -#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) -/* @brief Number of chip select pins. */ -#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) -/* @brief Has chip select strobe capability on the PCS5 pin. */ -#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) -/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) -/* @brief Has 16-bit data transfer support. */ -#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) - -/* TPM module features */ - -/* @brief Bus clock is the source clock for the module. */ -#define FSL_FEATURE_TPM_BUS_CLOCK (0) -/* @brief Number of channels. */ -#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ - ((x) == TPM0 ? (4) : \ - ((x) == TPM1 ? (2) : \ - ((x) == TPM2 ? (2) : (-1)))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Has TPM_PARAM. */ -#define FSL_FEATURE_TPM_HAS_PARAM (0) -/* @brief Has TPM_VERID. */ -#define FSL_FEATURE_TPM_HAS_VERID (0) -/* @brief Has TPM_GLOBAL. */ -#define FSL_FEATURE_TPM_HAS_GLOBAL (0) -/* @brief Has TPM_TRIG. */ -#define FSL_FEATURE_TPM_HAS_TRIG (0) -/* @brief Has counter pause on trigger. */ -#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) -/* @brief Has external trigger selection. */ -#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) -/* @brief Has TPM_COMBINE register. */ -#define FSL_FEATURE_TPM_HAS_COMBINE (1) -/* @brief Whether COMBINE register has effect. */ -#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_POL. */ -#define FSL_FEATURE_TPM_HAS_POL (1) -/* @brief Has TPM_FILTER register. */ -#define FSL_FEATURE_TPM_HAS_FILTER (1) -/* @brief Whether FILTER register has effect. */ -#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_QDCTRL register. */ -#define FSL_FEATURE_TPM_HAS_QDCTRL (1) -/* @brief Whether QDCTRL register has effect. */ -#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) - -/* TRNG module features */ - -/* No feature definitions */ - -/* TSI module features */ - -/* @brief TSI module version. */ -#define FSL_FEATURE_TSI_VERSION (4) -/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ -#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) -/* @brief Number of TSI channels. */ -#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (0) - -/* XCVR_ANALOG module features */ - -/* No feature definitions */ - -/* XCVR_PHY module features */ - -/* No feature definitions */ - -#endif /* _MKW31Z4_FEATURES_H_ */ - diff --git a/cpu/kw41z/include/vendor/MKW41Z4_features.h b/cpu/kw41z/include/vendor/MKW41Z4_features.h deleted file mode 100644 index 7e7fee364b5c..000000000000 --- a/cpu/kw41z/include/vendor/MKW41Z4_features.h +++ /dev/null @@ -1,2020 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2015-09-23 -** Build: b170228 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2015-09-23) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _MKW41Z4_FEATURES_H_ -#define _MKW41Z4_FEATURES_H_ - -/* SOC module features */ - -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (1) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (1) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (1) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (0) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (1) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (1) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (0) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (2) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (0) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_ENET_COUNT (0) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (0) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (3) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (0) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (1) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (3) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (2) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (0) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (1) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (0) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (0) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (1) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (1) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (1) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (1) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (1) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief SYSMPU availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSMPU_COUNT (0) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (1) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (1) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (1) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (1) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (3) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (0) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (1) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (1) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_RNG_COUNT (0) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (1) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (1) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (0) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (0) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (3) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (1) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (1) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (0) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) -/* @brief USBHS availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHS_COUNT (0) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (1) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (0) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (0) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (0) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (1) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (1) - -/* ADC16 module features */ - -/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ -#define FSL_FEATURE_ADC16_HAS_PGA (0) -/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) -/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ -#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) -/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ -#define FSL_FEATURE_ADC16_HAS_DMA (1) -/* @brief Has differential mode (bitfield SC1x[DIFF]). */ -#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) -/* @brief Has FIFO (bit SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_HAS_FIFO (0) -/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ -#define FSL_FEATURE_ADC16_FIFO_SIZE (0) -/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ -#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) -/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ -#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) -/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ -#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) -/* @brief Has HW averaging (bit SC3[AVGE]). */ -#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) -/* @brief Has offset correction (register OFS). */ -#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) -/* @brief Maximum ADC resolution. */ -#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) -/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ -#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) - -/* BTLE_RF module features */ - -/* No feature definitions */ - -/* CMP module features */ - -/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ -#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) -/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ -#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) -/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ -#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) -/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ -#define FSL_FEATURE_CMP_HAS_DMA (1) -/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ -#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) -/* @brief Has DAC Test function in CMP (register DACTEST). */ -#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) - -/* COP module features */ - -/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ -#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) -/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ -#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) -/* @brief Has more clock sources like MCGIRC */ -#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) -/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ -#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) - -/* DAC module features */ - -/* @brief Define the size of hardware buffer */ -#define FSL_FEATURE_DAC_BUFFER_SIZE (2) -/* @brief Define whether the buffer supports watermark event detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) -/* @brief Define whether the buffer supports watermark selection detection or not. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) -/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) -/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) -/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) -/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ -#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) -/* @brief Define whether FIFO buffer mode is available or not. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) -/* @brief Define whether swing buffer mode is available or not.. */ -#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) - -/* DCDC module features */ - -/* @brief Has VDD1P5 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) -/* @brief Has VDD1P45 bits in DCDC REG3. */ -#define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) - -/* EDMA module features */ - -/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 4) -/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) -/* @brief Has DMA_Error interrupt vector. */ -#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) -/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ -#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) - -/* DMAMUX module features */ - -/* @brief Number of DMA channels (related to number of register CHCFGn). */ -#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) -/* @brief Total number of DMA channels on all modules. */ -#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) -/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ -#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) - -/* FLASH module features */ - -#if defined(CPU_MKW41Z256VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#elif defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4) - /* @brief Is of type FTFA. */ - #define FSL_FEATURE_FLASH_IS_FTFA (1) - /* @brief Is of type FTFE. */ - #define FSL_FEATURE_FLASH_IS_FTFE (0) - /* @brief Is of type FTFL. */ - #define FSL_FEATURE_FLASH_IS_FTFL (0) - /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) - /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) - /* @brief Has EEPROM region protection (register FEPROT). */ - #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) - /* @brief Has data flash region protection (register FDPROT). */ - #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) - /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ - #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) - /* @brief Has flash cache control in FMC module. */ - #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) - /* @brief Has flash cache control in MCM module. */ - #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) - /* @brief Has flash cache control in MSCM module. */ - #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) - /* @brief Has prefetch speculation control in flash, such as kv5x. */ - #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) - /* @brief P-Flash start address. */ - #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) - /* @brief P-Flash block count. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) - /* @brief P-Flash block size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) - /* @brief P-Flash sector size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) - /* @brief P-Flash write unit size. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) - /* @brief P-Flash data path width. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) - /* @brief P-Flash block swap feature. */ - #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) - /* @brief P-Flash protection region count. */ - #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) - /* @brief Has FlexNVM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) - /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) - /* @brief FlexNVM block count. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) - /* @brief FlexNVM block size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) - /* @brief FlexNVM sector size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) - /* @brief FlexNVM write unit size. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) - /* @brief FlexNVM data path width. */ - #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) - /* @brief Has FlexRAM memory. */ - #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) - /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ - #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) - /* @brief FlexRAM size. */ - #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) - /* @brief Has 0x00 Read 1s Block command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) - /* @brief Has 0x01 Read 1s Section command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) - /* @brief Has 0x02 Program Check command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) - /* @brief Has 0x03 Read Resource command. */ - #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) - /* @brief Has 0x06 Program Longword command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) - /* @brief Has 0x07 Program Phrase command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) - /* @brief Has 0x08 Erase Flash Block command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) - /* @brief Has 0x09 Erase Flash Sector command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) - /* @brief Has 0x0B Program Section command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) - /* @brief Has 0x40 Read 1s All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) - /* @brief Has 0x41 Read Once command. */ - #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) - /* @brief Has 0x43 Program Once command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) - /* @brief Has 0x44 Erase All Blocks command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) - /* @brief Has 0x45 Verify Backdoor Access Key command. */ - #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) - /* @brief Has 0x46 Swap Control command. */ - #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) - /* @brief Has 0x49 Erase All Blocks Unsecure command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) - /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x4B Erase All Execute-only Segments command. */ - #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) - /* @brief Has 0x80 Program Partition command. */ - #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) - /* @brief Has 0x81 Set FlexRAM Function command. */ - #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) - /* @brief P-Flash Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) - /* @brief P-Flash Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) - /* @brief P-Flash Program check command address alignment. */ - #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Erase sector command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Rrogram/Verify section command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Read resource command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM Program check command address alignment. */ - #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) - /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) - /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) - /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) - /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) - /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) - /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) - /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) - /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) - /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) - /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) - /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) - /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) - /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) - /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) - /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) - /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) - /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) - /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ - #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) -#endif /* defined(CPU_MKW41Z256VHT4) */ - -/* GENFSK module features */ - -/* No feature definitions */ - -/* GPIO module features */ - -/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ -#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) -/* @brief Has port input disable register (PIDR). */ -#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) - -/* I2C module features */ - -/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ -#define FSL_FEATURE_I2C_HAS_SMBUS (1) -/* @brief Maximum supported baud rate in kilobit per second. */ -#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) -/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ -#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) -/* @brief Has DMA support (register bit C1[DMAEN]). */ -#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) -/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) -/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ -#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) -/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ -#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) -/* @brief Maximum width of the glitch filter in number of bus clocks. */ -#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) -/* @brief Has control of the drive capability of the I2C pins. */ -#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) -/* @brief Has double buffering support (register S2). */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) -/* @brief Has double buffer enable. */ -#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) - -/* LLWU module features */ - -#if defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) - /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Has pins 8-15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has MF register. */ - #define FSL_FEATURE_LLWU_HAS_MF (0) - /* @brief Has PF register. */ - #define FSL_FEATURE_LLWU_HAS_PF (0) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) - /* @brief Has no internal module wakeup flag register. */ - #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) - /* @brief Has external pin 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) - /* @brief Has external pin 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) - /* @brief Has external pin 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) - /* @brief Has external pin 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) - /* @brief Has external pin 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) - /* @brief Has external pin 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) - /* @brief Has external pin 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) - /* @brief Has external pin 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) - /* @brief Has external pin 8 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) - /* @brief Has external pin 9 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) - /* @brief Has external pin 10 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) - /* @brief Has external pin 11 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) - /* @brief Has external pin 12 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) - /* @brief Has external pin 13 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) - /* @brief Has external pin 14 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) - /* @brief Has external pin 15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) - /* @brief Has external pin 16 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) - /* @brief Has external pin 17 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) - /* @brief Has external pin 18 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) - /* @brief Has external pin 19 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) - /* @brief Has external pin 20 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) - /* @brief Has external pin 21 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) - /* @brief Has external pin 22 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) - /* @brief Has external pin 23 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) - /* @brief Has external pin 24 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) - /* @brief Has external pin 25 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) - /* @brief Has external pin 26 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) - /* @brief Has external pin 27 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) - /* @brief Has external pin 28 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) - /* @brief Has external pin 29 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) - /* @brief Has external pin 30 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) - /* @brief Has external pin 31 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) - /* @brief Has internal module 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) - /* @brief Has internal module 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) - /* @brief Has internal module 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) - /* @brief Has internal module 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) - /* @brief Has internal module 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) - /* @brief Has internal module 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) - /* @brief Has internal module 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) - /* @brief Has internal module 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) - /* @brief Has Version ID Register (LLWU_VERID). */ - #define FSL_FEATURE_LLWU_HAS_VERID (0) - /* @brief Has Parameter Register (LLWU_PARAM). */ - #define FSL_FEATURE_LLWU_HAS_PARAM (0) - /* @brief Width of registers of the LLWU. */ - #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) - /* @brief Has DMA Enable register (LLWU_DE). */ - #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) -#elif defined(CPU_MKW41Z512CAT4) - /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) - /* @brief Has pins 8-15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) - /* @brief Maximum number of internal modules connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) - /* @brief Number of digital filters. */ - #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) - /* @brief Has MF register. */ - #define FSL_FEATURE_LLWU_HAS_MF (0) - /* @brief Has PF register. */ - #define FSL_FEATURE_LLWU_HAS_PF (0) - /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ - #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) - /* @brief Has no internal module wakeup flag register. */ - #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) - /* @brief Has external pin 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) - /* @brief Has external pin 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) - /* @brief Has external pin 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) - /* @brief Has external pin 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) - /* @brief Has external pin 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) - /* @brief Has external pin 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) - /* @brief Has external pin 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) - /* @brief Has external pin 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) - /* @brief Has external pin 8 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) - /* @brief Has external pin 9 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) - /* @brief Has external pin 10 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) - /* @brief Has external pin 11 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) - /* @brief Has external pin 12 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) - /* @brief Has external pin 13 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) - /* @brief Has external pin 14 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) - /* @brief Has external pin 15 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) - /* @brief Has external pin 16 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) - /* @brief Has external pin 17 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) - /* @brief Has external pin 18 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) - /* @brief Has external pin 19 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) - /* @brief Has external pin 20 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) - /* @brief Has external pin 21 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) - /* @brief Has external pin 22 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) - /* @brief Has external pin 23 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) - /* @brief Has external pin 24 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) - /* @brief Has external pin 25 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) - /* @brief Has external pin 26 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) - /* @brief Has external pin 27 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) - /* @brief Has external pin 28 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) - /* @brief Has external pin 29 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) - /* @brief Has external pin 30 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) - /* @brief Has external pin 31 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) - /* @brief Index of port of external pin. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) - /* @brief Number of external pin port on specified port. */ - #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) - /* @brief Has internal module 0 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) - /* @brief Has internal module 1 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) - /* @brief Has internal module 2 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) - /* @brief Has internal module 3 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) - /* @brief Has internal module 4 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) - /* @brief Has internal module 5 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) - /* @brief Has internal module 6 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) - /* @brief Has internal module 7 connected to LLWU device. */ - #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) - /* @brief Has Version ID Register (LLWU_VERID). */ - #define FSL_FEATURE_LLWU_HAS_VERID (0) - /* @brief Has Parameter Register (LLWU_PARAM). */ - #define FSL_FEATURE_LLWU_HAS_PARAM (0) - /* @brief Width of registers of the LLWU. */ - #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) - /* @brief Has DMA Enable register (LLWU_DE). */ - #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) -#endif /* defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) */ - -/* LPTMR module features */ - -/* @brief Has shared interrupt handler with another LPTMR module. */ -#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) -/* @brief Whether LPTMR counter is 32 bits width. */ -#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) -/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ -#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) - -/* LPUART module features */ - -/* @brief LPUART0 and LPUART1 has shared interrupt vector. */ -#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) -/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ -#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) -/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) -/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_HAS_FIFO (0) -/* @brief Has 32-bit register MODIR */ -#define FSL_FEATURE_LPUART_HAS_MODIR (1) -/* @brief Hardware flow control (RTS, CTS) is supported. */ -#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) -/* @brief Infrared (modulation) is supported. */ -#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) -/* @brief 2 bits long stop bit is available. */ -#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) -/* @brief If 10-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) -/* @brief If 7-bit mode is supported. */ -#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) -/* @brief Baud rate fine adjustment is available. */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) -/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) -/* @brief Baud rate oversampling is available. */ -#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) -/* @brief Peripheral type. */ -#define FSL_FEATURE_LPUART_IS_SCI (1) -/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ -#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) -/* @brief Maximal data width without parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) -/* @brief Maximal data width with parity bit. */ -#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) -/* @brief Supports two match addresses to filter incoming frames. */ -#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) -/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) -/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ -#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) -/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ -#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) -/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ -#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) -/* @brief Has improved smart card (ISO7816 protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) -/* @brief Has local operation network (CEA709.1-B protocol) support. */ -#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) -/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ -#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) -/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ -#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) -/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ -#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) -/* @brief Has separate RX and TX interrupts. */ -#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) -/* @brief Has LPAURT_PARAM. */ -#define FSL_FEATURE_LPUART_HAS_PARAM (0) -/* @brief Has LPUART_VERID. */ -#define FSL_FEATURE_LPUART_HAS_VERID (0) -/* @brief Has LPUART_GLOBAL. */ -#define FSL_FEATURE_LPUART_HAS_GLOBAL (0) -/* @brief Has LPUART_PINCFG. */ -#define FSL_FEATURE_LPUART_HAS_PINCFG (0) - -/* LTC module features */ - -/* @brief LTC module supports DES algorithm. */ -#define FSL_FEATURE_LTC_HAS_DES (0) -/* @brief LTC module supports PKHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_PKHA (0) -/* @brief LTC module supports SHA algorithm. */ -#define FSL_FEATURE_LTC_HAS_SHA (0) -/* @brief LTC module supports AES GCM mode. */ -#define FSL_FEATURE_LTC_HAS_GCM (0) -/* @brief LTC module supports DPAMS registers. */ -#define FSL_FEATURE_LTC_HAS_DPAMS (0) -/* @brief LTC module supports AES with 24 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES192 (0) -/* @brief LTC module supports AES with 32 bytes key. */ -#define FSL_FEATURE_LTC_HAS_AES256 (0) - -/* MCG module features */ - -/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) -/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ -#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) -/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ -#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) -/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MIN (0) -/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ -#define FSL_FEATURE_MCG_PLL_REF_MAX (0) -/* @brief The PLL clock is divided by 2 before VCO divider. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) -/* @brief FRDIV supports 1280. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) -/* @brief FRDIV supports 1536. */ -#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) -/* @brief MCGFFCLK divider. */ -#define FSL_FEATURE_MCG_FFCLK_DIV (1) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ -#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) -/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ -#define FSL_FEATURE_MCG_HAS_RTC_32K (1) -/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_PLL1 (0) -/* @brief Has 48MHz internal oscillator. */ -#define FSL_FEATURE_MCG_HAS_IRC_48M (0) -/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ -#define FSL_FEATURE_MCG_HAS_OSC1 (0) -/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ -#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) -/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ -#define FSL_FEATURE_MCG_HAS_LOLRE (0) -/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ -#define FSL_FEATURE_MCG_USE_OSCSEL (1) -/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ -#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) -/* @brief TBD */ -#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) -/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ -#define FSL_FEATURE_MCG_HAS_PLL (0) -/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) -/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ -#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) -/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ -#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) -/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ -#define FSL_FEATURE_MCG_HAS_FLL (1) -/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) -/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ -#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) -/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) -/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ -#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) -/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ -#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) -/* @brief Has external clock monitor (register bit C6[CME]). */ -#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) -/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ -#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) -/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ -#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) -/* @brief Has PEI mode or PBI mode. */ -#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) -/* @brief Reset clock mode is BLPI. */ -#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) - -/* PIT module features */ - -/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ -#define FSL_FEATURE_PIT_TIMER_COUNT (2) -/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ -#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) -/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ -#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) -/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ -#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) - -/* PMC module features */ - -/* @brief Has Bandgap Enable In VLPx Operation support. */ -#define FSL_FEATURE_PMC_HAS_BGEN (0) -/* @brief Has Bandgap Buffer Enable. */ -#define FSL_FEATURE_PMC_HAS_BGBE (1) -/* @brief Has Bandgap Buffer Drive Select. */ -#define FSL_FEATURE_PMC_HAS_BGBDS (0) -/* @brief Has Low-Voltage Detect Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVDV (1) -/* @brief Has Low-Voltage Warning Voltage Select support. */ -#define FSL_FEATURE_PMC_HAS_LVWV (1) -/* @brief Has LPO. */ -#define FSL_FEATURE_PMC_HAS_LPO (0) -/* @brief Has VLPx option PMC_REGSC[VLPO]. */ -#define FSL_FEATURE_PMC_HAS_VLPO (1) -/* @brief Has acknowledge isolation support. */ -#define FSL_FEATURE_PMC_HAS_ACKISO (1) -/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ -#define FSL_FEATURE_PMC_HAS_REGFPM (0) -/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ -#define FSL_FEATURE_PMC_HAS_REGONS (1) -/* @brief Has PMC_HVDSC1. */ -#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) -/* @brief Has PMC_PARAM. */ -#define FSL_FEATURE_PMC_HAS_PARAM (0) -/* @brief Has PMC_VERID. */ -#define FSL_FEATURE_PMC_HAS_VERID (0) - -/* PORT module features */ - -/* @brief Has control lock (register bit PCR[LK]). */ -#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) -/* @brief Has open drain control (register bit PCR[ODE]). */ -#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) -/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ -#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) -/* @brief Has DMA request (register bit field PCR[IRQC] values). */ -#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) -/* @brief Has pull resistor selection available. */ -#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) -/* @brief Has pull resistor enable (register bit PCR[PE]). */ -#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) -/* @brief Has slew rate control (register bit PCR[SRE]). */ -#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) -/* @brief Has passive filter (register bit field PCR[PFE]). */ -#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) -/* @brief Has drive strength control (register bit PCR[DSE]). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) -/* @brief Has separate drive strength register (HDRVE). */ -#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) -/* @brief Has glitch filter (register IOFLT). */ -#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) -/* @brief Defines width of PCR[MUX] field. */ -#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) -/* @brief Has dedicated interrupt vector. */ -#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) -/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ -#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) -/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) -/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ -#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) - -/* RADIO module features */ - -/* @brief Zigbee availability. */ -#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) -/* @brief Bluetooth availability. */ -#define FSL_FEATURE_RADIO_HAS_BLE (1) -/* @brief ANT availability */ -#define FSL_FEATURE_RADIO_HAS_ANT (1) -/* @brief Generic FSK module availability */ -#define FSL_FEATURE_RADIO_HAS_GENFSK (1) -/* @brief Major version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MAJOR (2) -/* @brief Minor version of the radio submodule */ -#define FSL_FEATURE_RADIO_VERSION_MINOR (0) - -/* RCM module features */ - -/* @brief Has Loss-of-Lock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOL (0) -/* @brief Has Loss-of-Clock Reset support. */ -#define FSL_FEATURE_RCM_HAS_LOC (1) -/* @brief Has JTAG generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_JTAG (0) -/* @brief Has EzPort generated Reset support. */ -#define FSL_FEATURE_RCM_HAS_EZPORT (0) -/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ -#define FSL_FEATURE_RCM_HAS_EZPMS (0) -/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ -#define FSL_FEATURE_RCM_HAS_BOOTROM (0) -/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ -#define FSL_FEATURE_RCM_HAS_SSRS (0) -/* @brief Has Version ID Register (RCM_VERID). */ -#define FSL_FEATURE_RCM_HAS_VERID (0) -/* @brief Has Parameter Register (RCM_PARAM). */ -#define FSL_FEATURE_RCM_HAS_PARAM (0) -/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ -#define FSL_FEATURE_RCM_HAS_SRIE (0) -/* @brief Width of registers of the RCM. */ -#define FSL_FEATURE_RCM_REG_WIDTH (8) -/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ -#define FSL_FEATURE_RCM_HAS_CORE1 (0) -/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ -#define FSL_FEATURE_RCM_HAS_MDM_AP (1) -/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ -#define FSL_FEATURE_RCM_HAS_WAKEUP (1) - -/* RSIM module features */ - -/* No feature definitions */ - -/* RTC module features */ - -/* @brief Has wakeup pin. */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) -/* @brief Has wakeup pin selection (bit field CR[WPS]). */ -#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) -/* @brief Has low power features (registers MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) -/* @brief Has read/write access control (registers WAR and RAR). */ -#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) -/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ -#define FSL_FEATURE_RTC_HAS_SECURITY (0) -/* @brief Has RTC_CLKIN available. */ -#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) -/* @brief Has prescaler adjust for LPO. */ -#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) -/* @brief Has Clock Pin Enable field. */ -#define FSL_FEATURE_RTC_HAS_CPE (0) -/* @brief Has Timer Seconds Interrupt Configuration field. */ -#define FSL_FEATURE_RTC_HAS_TSIC (0) -/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ -#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) - -/* SIM module features */ - -/* @brief Has USB FS divider. */ -#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) -/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ -#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) -/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) -/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) -/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) -/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ -#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) -/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) -/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) -/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) -/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) -/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) -/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) -/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) -/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ -#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) -/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ -#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) -/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ -#define FSL_FEATURE_SIM_OPT_UART_COUNT (0) -/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) -/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) -/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) -/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) -/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) -/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ -#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) -/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) -/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) -/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) -/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) -/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) -/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) -/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) -/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) -/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) -/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) -/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ -#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) -/* @brief Has FTM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM (0) -/* @brief Number of FTM modules. */ -#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) -/* @brief Number of FTM triggers with selectable source. */ -#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) -/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) -/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) -/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) -/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) -/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) -/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) -/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) -/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) -/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) -/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ -#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) -/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) -/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ -#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) -/* @brief Has TPM module(s) configuration. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM (1) -/* @brief The highest TPM module index. */ -#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) -/* @brief Has TPM module with index 0. */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) -/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) -/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) -/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) -/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) -/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) -/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) -/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) -/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) -/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ -#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) -/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) -/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) -/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) -/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) -/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) -/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) -/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) -/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) -/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) -/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) -/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) -/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) -/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) -/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) -/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) -/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ -#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) -/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ -#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) -/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) -/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) -/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) -/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) -/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) -/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) -/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) -/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ -#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) -/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) -/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) -/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) -/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ -#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) -/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) -/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) -/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) -/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) -/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) -/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) -/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) -/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ -#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) -/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) -/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) -/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) -/* @brief Has device die ID (register bit field SDID[DIEID]). */ -#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) -/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ -#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) -/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) -/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) -/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) -/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) -/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) -/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) -/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) -/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) -/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) -/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) -/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) -/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ -#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) -/* @brief Has miscellanious control register (register MCR). */ -#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) -/* @brief Has COP watchdog (registers COPC and SRVCOP). */ -#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) -/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ -#define FSL_FEATURE_SIM_HAS_COP_STOP (1) -/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ -#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) - -/* SMC module features */ - -/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ -#define FSL_FEATURE_SMC_HAS_PSTOPO (1) -/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ -#define FSL_FEATURE_SMC_HAS_LPOPO (0) -/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ -#define FSL_FEATURE_SMC_HAS_PORPO (1) -/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ -#define FSL_FEATURE_SMC_HAS_LPWUI (0) -/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ -#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) -/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) -/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ -#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) -/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ -#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) -/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ -#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) -/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ -#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ -#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) -/* @brief Has stop submode. */ -#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) -/* @brief Has stop submode 0(VLLS0). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) -/* @brief Has stop submode 2(VLLS2). */ -#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) -/* @brief Has SMC_PARAM. */ -#define FSL_FEATURE_SMC_HAS_PARAM (0) -/* @brief Has SMC_VERID. */ -#define FSL_FEATURE_SMC_HAS_VERID (0) -/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ -#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) -/* @brief Has tamper reset (register bit SRS[TAMPER]). */ -#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) -/* @brief Has security violation reset (register bit SRS[SECVIO]). */ -#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) - -/* DSPI module features */ - -/* @brief Receive/transmit FIFO size in number of items. */ -#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) -/* @brief Maximum transfer data width in bits. */ -#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) -/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ -#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) -/* @brief Number of chip select pins. */ -#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) -/* @brief Has chip select strobe capability on the PCS5 pin. */ -#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) -/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) -/* @brief Has 16-bit data transfer support. */ -#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) -/* @brief Has separate DMA RX and TX requests. */ -#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) - -/* TPM module features */ - -/* @brief Bus clock is the source clock for the module. */ -#define FSL_FEATURE_TPM_BUS_CLOCK (0) -/* @brief Number of channels. */ -#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ - ((x) == TPM0 ? (4) : \ - ((x) == TPM1 ? (2) : \ - ((x) == TPM2 ? (2) : (-1)))) -/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ -#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) -/* @brief Has TPM_PARAM. */ -#define FSL_FEATURE_TPM_HAS_PARAM (0) -/* @brief Has TPM_VERID. */ -#define FSL_FEATURE_TPM_HAS_VERID (0) -/* @brief Has TPM_GLOBAL. */ -#define FSL_FEATURE_TPM_HAS_GLOBAL (0) -/* @brief Has TPM_TRIG. */ -#define FSL_FEATURE_TPM_HAS_TRIG (0) -/* @brief Has counter pause on trigger. */ -#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) -/* @brief Has external trigger selection. */ -#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) -/* @brief Has TPM_COMBINE register. */ -#define FSL_FEATURE_TPM_HAS_COMBINE (1) -/* @brief Whether COMBINE register has effect. */ -#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_POL. */ -#define FSL_FEATURE_TPM_HAS_POL (1) -/* @brief Has TPM_FILTER register. */ -#define FSL_FEATURE_TPM_HAS_FILTER (1) -/* @brief Whether FILTER register has effect. */ -#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) -/* @brief Has TPM_QDCTRL register. */ -#define FSL_FEATURE_TPM_HAS_QDCTRL (1) -/* @brief Whether QDCTRL register has effect. */ -#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ - ((x) == TPM0 ? (0) : \ - ((x) == TPM1 ? (1) : \ - ((x) == TPM2 ? (1) : (-1)))) - -/* TRNG module features */ - -/* No feature definitions */ - -/* TSI module features */ - -/* @brief TSI module version. */ -#define FSL_FEATURE_TSI_VERSION (4) -/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ -#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) -/* @brief Number of TSI channels. */ -#define FSL_FEATURE_TSI_CHANNEL_COUNT (16) - -/* VREF module features */ - -/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ -#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) -/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ -#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) -/* @brief If high/low buffer mode supported */ -#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) -/* @brief Module has also low reference (registers VREFL/VREFH) */ -#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) -/* @brief Has VREF_TRM4. */ -#define FSL_FEATURE_VREF_HAS_TRM4 (0) - -/* XCVR_ANALOG module features */ - -/* No feature definitions */ - -/* XCVR_PHY module features */ - -/* No feature definitions */ - -/* ZLL module features */ - -/* No feature definitions */ - -#endif /* _MKW41Z4_FEATURES_H_ */ - From bef0d8d4ef59d6c4fbf5a3ac39b21803c30cf434 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 10 Dec 2018 14:58:07 +0100 Subject: [PATCH 74/82] squash kw41zrf: Remove references to netdev_t::stats, required by #9793 --- drivers/kw41zrf/kw41zrf_netdev.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 3b31eac4ee67..03f1eedf57ae 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -88,10 +88,6 @@ static int kw41zrf_netdev_init(netdev_t *netdev) return -1; } -#ifdef MODULE_NETSTATS_L2 - memset(&netdev->stats, 0, sizeof(netstats_t)); -#endif - return 0; } @@ -260,10 +256,6 @@ static int kw41zrf_netdev_send(netdev_t *netdev, const iolist_t *iolist) od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_TX, len, OD_WIDTH_DEFAULT); #endif -#ifdef MODULE_NETSTATS_L2 - netdev->stats.tx_bytes += len; -#endif - /* send data out directly if pre-loading is disabled */ if (!(dev->flags & KW41ZRF_OPT_PRELOADING)) { dev->csma_be = dev->csma_min_be; @@ -321,13 +313,6 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in od_hex_dump((const uint8_t *)ZLL->PKT_BUFFER_RX, pkt_len, OD_WIDTH_DEFAULT); #endif -#ifdef MODULE_NETSTATS_L2 - netdev->stats.rx_count++; - netdev->stats.rx_bytes += pkt_len; -#else - (void)netdev; -#endif - if (pkt_len > len) { /* not enough space in buf */ if (kw41zrf_can_switch_to_idle(dev)) { From 5a362bd26730605497fc80345aa996d93071af1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 10 Dec 2018 15:11:49 +0100 Subject: [PATCH 75/82] squash kw41zrf remove netdev_t accesses in getset --- drivers/kw41zrf/kw41zrf_getset.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 86e399cb893f..8fb9d3d894a6 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -82,13 +82,13 @@ uint8_t kw41zrf_get_channel(kw41zrf_t *dev) int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel) { + (void) dev; if (channel < KW41ZRF_MIN_CHANNEL || channel > KW41ZRF_MAX_CHANNEL) { LOG_ERROR("[kw41zrf] Invalid channel %u\n", channel); return -EINVAL; } ZLL->CHANNEL_NUM0 = channel; - dev->netdev.chan = channel; LOG_DEBUG("[kw41zrf] set channel to %u\n", channel); return 0; @@ -96,8 +96,7 @@ int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel) void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan) { - dev->netdev.pan = pan; - + (void) dev; ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACPANID0_MASK) | ZLL_MACSHORTADDRS0_MACPANID0(pan); @@ -106,15 +105,12 @@ void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan) void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr) { + (void) dev; #ifdef MODULE_SIXLOWPAN /* https://tools.ietf.org/html/rfc4944#section-12 requires the first bit to * 0 for unicast addresses */ addr &= 0x7fff; #endif - /* Network byte order */ - /* TODO use byteorder.h */ - dev->netdev.short_addr[0] = (addr & 0xff); - dev->netdev.short_addr[1] = (addr >> 8); ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) | ZLL_MACSHORTADDRS0_MACSHORTADDRS0(addr); } @@ -122,9 +118,6 @@ void kw41zrf_set_addr_short(kw41zrf_t *dev, uint16_t addr) void kw41zrf_set_addr_long(kw41zrf_t *dev, uint64_t addr) { (void) dev; - for (unsigned i = 0; i < IEEE802154_LONG_ADDRESS_LEN; i++) { - dev->netdev.long_addr[i] = (uint8_t)(addr >> (i * 8)); - } /* Network byte order */ addr = byteorder_swapll(addr); ZLL->MACLONGADDRS0_LSB = (uint32_t)addr; From 27f83eea27d0884fcf09b244c336289854b29b56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 10 Dec 2018 15:39:03 +0100 Subject: [PATCH 76/82] squash kw41zrf fix _get_txpower declaration --- drivers/kw41zrf/include/kw41zrf_getset.h | 2 +- drivers/kw41zrf/kw41zrf_getset.c | 2 +- drivers/kw41zrf/kw41zrf_netdev.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h index 38353f4d2b6c..9a76185b5ff0 100644 --- a/drivers/kw41zrf/include/kw41zrf_getset.h +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -69,7 +69,7 @@ void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower); * * @return current tx power value */ -uint16_t kw41zrf_get_txpower(kw41zrf_t *dev); +int16_t kw41zrf_get_txpower(kw41zrf_t *dev); /** * @brief Set channel of given device diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 8fb9d3d894a6..7076d941a0f0 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -69,7 +69,7 @@ void kw41zrf_set_tx_power(kw41zrf_t *dev, int16_t txpower_dbm) dev->tx_power = txpower_dbm; } -uint16_t kw41zrf_get_txpower(kw41zrf_t *dev) +int16_t kw41zrf_get_txpower(kw41zrf_t *dev) { return dev->tx_power; } diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 03f1eedf57ae..db6808f660bd 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -599,7 +599,7 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) res = -EOVERFLOW; break; } - *((uint16_t *)value) = kw41zrf_get_txpower(dev); + *((int16_t *)value) = kw41zrf_get_txpower(dev); res = len; break; From 43515a84c5a0aff08cfd026094753df688eefcb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 10 Dec 2018 15:39:37 +0100 Subject: [PATCH 77/82] squash kw41zrf Refactor addr,chan,nid getters/setters --- drivers/kw41zrf/include/kw41zrf_getset.h | 9 +++++ drivers/kw41zrf/kw41zrf_getset.c | 8 +++- drivers/kw41zrf/kw41zrf_netdev.c | 48 ++++++++++++++++++++++-- 3 files changed, 60 insertions(+), 5 deletions(-) diff --git a/drivers/kw41zrf/include/kw41zrf_getset.h b/drivers/kw41zrf/include/kw41zrf_getset.h index 9a76185b5ff0..2344c8446417 100644 --- a/drivers/kw41zrf/include/kw41zrf_getset.h +++ b/drivers/kw41zrf/include/kw41zrf_getset.h @@ -96,6 +96,15 @@ uint8_t kw41zrf_get_channel(kw41zrf_t *dev); */ void kw41zrf_set_pan(kw41zrf_t *dev, uint16_t pan); +/** + * @brief Get PAN ID of given device + * + * @param[in] dev kw41zrf device descriptor + * + * @return current PAN ID + */ +uint16_t kw41zrf_get_pan(kw41zrf_t *dev); + /** * @brief Set short address of a given device * diff --git a/drivers/kw41zrf/kw41zrf_getset.c b/drivers/kw41zrf/kw41zrf_getset.c index 7076d941a0f0..42e06624bc84 100644 --- a/drivers/kw41zrf/kw41zrf_getset.c +++ b/drivers/kw41zrf/kw41zrf_getset.c @@ -77,7 +77,13 @@ int16_t kw41zrf_get_txpower(kw41zrf_t *dev) uint8_t kw41zrf_get_channel(kw41zrf_t *dev) { (void) dev; - return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK); + return (ZLL->CHANNEL_NUM0 & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK) >> ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT; +} + +uint16_t kw41zrf_get_pan(kw41zrf_t *dev) +{ + (void) dev; + return (ZLL->MACSHORTADDRS0 & ZLL_MACSHORTADDRS0_MACPANID0_MASK) >> ZLL_MACSHORTADDRS0_MACPANID0_SHIFT; } int kw41zrf_set_channel(kw41zrf_t *dev, uint8_t channel) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index db6808f660bd..0eb3f8020a76 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -567,6 +567,10 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) if (kw41zrf_is_dsm()) { /* Transceiver is in deep sleep mode */ switch (opt) { + case NETOPT_CHANNEL: + case NETOPT_NID: + case NETOPT_ADDRESS: + case NETOPT_ADDRESS_LONG: case NETOPT_TX_POWER: case NETOPT_IS_CHANNEL_CLR: case NETOPT_CCA_THRESHOLD: @@ -594,6 +598,42 @@ int kw41zrf_netdev_get(netdev_t *netdev, netopt_t opt, void *value, size_t len) int res = -ENOTSUP; switch (opt) { + case NETOPT_CHANNEL: + if (len != sizeof(uint16_t)) { + res = -EOVERFLOW; + break; + } + *((uint16_t *)value) = (uint16_t)kw41zrf_get_channel(dev); + res = len; + break; + + case NETOPT_NID: + if (len != sizeof(uint16_t)) { + res = -EOVERFLOW; + break; + } + *((uint16_t *)value) = kw41zrf_get_pan(dev); + res = len; + break; + + case NETOPT_ADDRESS: + if (len != sizeof(uint16_t)) { + res = -EOVERFLOW; + break; + } + *((uint16_t *)value) = kw41zrf_get_addr_short(dev); + res = len; + break; + + case NETOPT_ADDRESS_LONG: + if (len != sizeof(uint64_t)) { + res = -EOVERFLOW; + break; + } + *((uint64_t *)value) = kw41zrf_get_addr_long(dev); + res = len; + break; + case NETOPT_TX_POWER: if (len != sizeof(int16_t)) { res = -EOVERFLOW; @@ -845,7 +885,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; } kw41zrf_set_addr_short(dev, *((const uint16_t *)value)); - /* don't set res to set netdev_ieee802154_t::short_addr */ + res = len; break; case NETOPT_ADDRESS_LONG: @@ -854,7 +894,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; } kw41zrf_set_addr_long(dev, *((const uint64_t *)value)); - /* don't set res to set netdev_ieee802154_t::short_addr */ + res = len; break; case NETOPT_NID: @@ -863,7 +903,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; } kw41zrf_set_pan(dev, *((const uint16_t *)value)); - /* don't set res to set netdev_ieee802154_t::pan */ + res = len; break; case NETOPT_CHANNEL: @@ -875,7 +915,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, res = -EINVAL; break; } - /* don't set res to set netdev_ieee802154_t::chan */ + res = len; break; case NETOPT_TX_POWER: From d3e202dcd2a064b16deff56a245ecca9430845b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Tue, 11 Dec 2018 09:31:03 +0100 Subject: [PATCH 78/82] squash kw41zrf workaround for netdev_t::pan updating until upper layer is refactored --- drivers/kw41zrf/kw41zrf_netdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 0eb3f8020a76..943ac00ad74a 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -903,7 +903,7 @@ static int kw41zrf_netdev_set(netdev_t *netdev, netopt_t opt, const void *value, break; } kw41zrf_set_pan(dev, *((const uint16_t *)value)); - res = len; + //~ res = len; /* uncomment this when the upper layer code is refactored to not need netdev_t::pan */ break; case NETOPT_CHANNEL: From 6d3b252061b9ebbe3c7a7780d491bbe23ce6d3a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 16 Nov 2018 13:58:15 +0100 Subject: [PATCH 79/82] fixup! squash kw41zrf minor clean ups and variable types refactor --- drivers/kw41zrf/kw41zrf_netdev.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/kw41zrf/kw41zrf_netdev.c b/drivers/kw41zrf/kw41zrf_netdev.c index 943ac00ad74a..c79173c352ff 100644 --- a/drivers/kw41zrf/kw41zrf_netdev.c +++ b/drivers/kw41zrf/kw41zrf_netdev.c @@ -286,10 +286,7 @@ static int kw41zrf_netdev_recv(netdev_t *netdev, void *buf, size_t len, void *in /* get size of the received packet */ uint8_t pkt_len = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; if (pkt_len < IEEE802154_FCS_LEN) { - if (kw41zrf_can_switch_to_idle(dev)) { - kw41zrf_abort_sequence(dev); - kw41zrf_set_sequence(dev, dev->idle_seq); - } + kw41zrf_unblock_rx(dev); return -EAGAIN; } /* skip FCS */ From 75cab70e49d517bf4988b9e6303cd16bcab641b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Wed, 12 Dec 2018 15:41:58 +0100 Subject: [PATCH 80/82] squash kw41zrf disable LEDs by default --- drivers/kw41zrf/include/kw41zrf_intern.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index c907860dd880..09bfb40e8e07 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -41,7 +41,7 @@ #endif /* Set to 1 to use on board LEDs to show RX/TX activity */ -#define ENABLE_LEDS (1) +#define ENABLE_LEDS (0) #if ENABLE_LEDS /* For LED macros */ From 1944a5894a94349dca71c4c6223e9c2d88ab1826 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 14 Dec 2018 08:32:14 +0100 Subject: [PATCH 81/82] phynode-kw41z: Add settings for SoC radio --- boards/phynode-kw41z/Makefile.dep | 4 ++++ examples/default/Makefile | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/boards/phynode-kw41z/Makefile.dep b/boards/phynode-kw41z/Makefile.dep index a73981801a5e..234721f5fb16 100644 --- a/boards/phynode-kw41z/Makefile.dep +++ b/boards/phynode-kw41z/Makefile.dep @@ -3,4 +3,8 @@ ifneq (,$(filter saul_default,$(USEMODULE))) USEMODULE += saul_adc endif +ifneq (,$(filter netdev_default gnrc_netdev_default,$(USEMODULE))) + USEMODULE += kw41zrf +endif + include $(RIOTCPU)/kinetis/Makefile.dep diff --git a/examples/default/Makefile b/examples/default/Makefile index d9e5ae39dc98..4f0400f76561 100644 --- a/examples/default/Makefile +++ b/examples/default/Makefile @@ -38,7 +38,7 @@ USEMODULE += saul_default BOARD_PROVIDES_NETIF := acd52832 airfy-beacon b-l072z-lrwan1 cc2538dk fox frdm-kw41z iotlab-m3 iotlab-a8-m3 mulle \ microbit native nrf51dk nrf51dongle nrf52dk nrf6310 openmote-cc2538 pba-d-01-kw2x \ - remote-pa remote-reva samr21-xpro \ + phynode-kw41z remote-pa remote-reva samr21-xpro \ spark-core telosb usb-kw41z yunjia-nrf51822 z1 ifneq (,$(filter $(BOARD),$(BOARD_PROVIDES_NETIF))) From 09ad33f05f458d93d150c6c34501615e63e39fd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 17 Dec 2018 22:58:43 +0100 Subject: [PATCH 82/82] squash kw41zrf correct PM name in comment --- drivers/kw41zrf/include/kw41zrf_intern.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/kw41zrf/include/kw41zrf_intern.h b/drivers/kw41zrf/include/kw41zrf_intern.h index 09bfb40e8e07..d080be4e1184 100644 --- a/drivers/kw41zrf/include/kw41zrf_intern.h +++ b/drivers/kw41zrf/include/kw41zrf_intern.h @@ -32,7 +32,7 @@ #define PM_BLOCK(x) pm_block(x) #define PM_UNBLOCK(x) pm_unblock(x) /* When the transceiver is not in DSM, this power mode will be blocked. - * TODO: Change this to symbolic name KINETIS_PM_LLS when Kinetis power + * TODO: Change this to symbolic name KINETIS_PM_VLPS when Kinetis power * management is merged (https://github.com/RIOT-OS/RIOT/pull/7897) */ #define KW41ZRF_PM_BLOCKER 0 #else