pcap_regs_ands.h

#ifndef pcap_regs_ands
#define pcap_regs_ands

#define CFG0_I2C_A_AND 0xC0
#define CFG0_OLF_FTUNE_AND 0x3C
#define CFG0_OLF_CTUNE_AND 0x03
#define CFG1_OX_DIS_AND 0x80
#define CFG1_OX_DIV4_AND 0x20
#define CFG1_OX_AUTOSTOP_DIS_AND 0x10
#define CFG1_OX_STOP_AND 0x08
#define CFG1_OX_RUN_AND 0x07
#define CFG2_RDCHG_INT_SEL1_AND 0xC0
#define CFG2_RDCHG_INT_SEL0_AND 0x30
#define CFG2_RDCHG_INT_EN_AND 0x08
#define CFG2_RDCHG_EXT_EN_AND 0x02
#define CFG3_AUX_PD_DIS_AND 0x40
#define CFG3_AUX_CINT_AND 0x20
#define CFG3_RDCHG_OPEN_AND 0x18
#define CFG3_RDCHG_PERM_EN_AND 0x04
#define CFG3_RDCHG_EXT_PERM_AND 0x02
#define CFG3_RCHG_SEL_AND 0x01
#define CFG4_C_REF_INT_AND 0x80
#define CFG4_C_COMP_EXT_AND 0x20
#define CFG4_C_COMP_INT_AND 0x10
#define CFG4_C_DIFFERENTIAL_AND 0x02
#define CFG4_C_FLOATING_AND 0x01
#define CFG5_CY_PRE_MR1_SHORT_AND 0x80
#define CFG5_C_PORT_PAT_AND 0x20
#define CFG5_CY_HFCLK_SEL_AND 0x08
#define CFG5_CY_DIV4_DIS_AND 0x04
#define CFG5_CY_PRE_LONG_AND 0x02
#define CFG5_C_DC_BALANCE_AND 0x01
#define CFG6_C_PORT_EN_AND 0x3F
#define CFG7_C_AVRG_LOW_AND 0xFF
#define CFG8_C_AVRG_HIGH_AND 0x1F
#define CFG9_CONV_TIME_LOW_AND 0xFF
#define CFG10_CONV_TIME_MID_AND 0xFF
#define CFG11_CONV_TIME_HIGH_AND 0x7F
#define CFG12_DISCHARGE_TIME_LOW_AND 0xFF
#define CFG13_C_STARTONPIN_AND 0xC0
#define CFG13_C_TRIG_SEL_AND 0x1C
#define CFG13_DISCHARGE_TIME_HIGH_AND 0x03
#define CFG14_PRECHARGE_TIME_LOW_AND 0xFF
#define CFG15_C_FAKE_AND 0x3C
#define CFG15_PRECHARGE_TIME_HIGH_AND 0x03
#define CFG16_FULLCHARGE_TIME_LOW_AND 0xFF
#define CFG17_C_REF_SEL_AND 0x7C
#define CFG17_FULLCHARGE_TIME_HIGH_AND 0x03
#define CFG18_C_G_OP_RUN_AND 0x80
#define CFG18_C_G_OP_EXT_AND 0x40
#define CFG18_C_G_EN_AND 0x3F
#define CFG19_C_G_OP_VU_AND 0xC0
#define CFG19_C_G_OP_ATTN_AND 0x30
#define CFG19_C_G_TIME_AND 0x0F
#define CFG20_R_CY_AND 0x80
#define CFG20_C_G_OP_TR_AND 0x07
#define CFG21_R_TRIG_PREDIV_LOW_AND 0xFF
#define CFG22_R_TRIG_SEL_AND 0x70
#define CFG22_R_AVRG_AND 0x0C
#define CFG22_R_TRIG_PREDIV_HIGH_AND 0x03
#define CFG23_R_PORT_EN_AND 0xC0
#define CFG23_R_PORT_EN_IMES_AND 0x20
#define CFG23_R_PORT_EN_IREF_AND 0x10
#define CFG23_R_FAKE_AND 0x04
#define CFG23_R_STARTONPIN_AND 0x03
#define CFG24_TDC_CHAN_EN_AND 0x30
#define CFG24_TDC_ALUPERMOPEN_AND 0x08
#define CFG24_TDC_NOISE_DIS_AND 0x04
#define CFG24_TDC_MUPU_SPEED_AND 0x03
#define CFG25_TDC_MUPU_NO_AND 0xFC
#define CFG26_TDC_QHA_SEL_AND 0xFC
#define CFG26_TDC_NOISE_CY_DIS_AND 0x02
#define CFG27_DSP_MOFLO_EN_AND 0xC0
#define CFG27_DSP_SPEED_AND 0x0C
#define CFG27_PG1xPG3_AND 0x02
#define CFG27_PG0xPG2_AND 0x01
#define CFG28_WD_DIS_AND 0xFF
#define CFG29_DSP_STARTONPIN_AND 0xF0
#define CFG29_DSP_FF_IN_AND 0x0F
#define CFG30_PG5_INTN_EN_AND 0x80
#define CFG30_PG4_INTN_EN_AND 0x40
#define CFG30_DSP_START_EN_AND 0x0F
#define CFG31_PI1_TOGGLE_EN_AND 0x80
#define CFG31_PI0_TOGGLE_EN_AND 0x40
#define CFG31_PI0_RES_AND 0x30
#define CFG31_PI0_PDM_SEL_AND 0x08
#define CFG31_PI0_CLK_SEL_AND 0x07
#define CFG32_PI1_RES_AND 0x20
#define CFG32_PI1_PDM_SEL_AND 0x08
#define CFG32_PI1_CLK_SEL_AND 0x07
#define CFG33_PG_DIR_IN_AND 0xF0
#define CFG33_PG_PU_AND 0x0F
#define CFG34_INT_TRIG_BG_AND 0x80
#define CFG34_DSP_TRIG_BG_AND 0x40
#define CFG34_BG_PERM_AND 0x20
#define CFG34_AUTOSTART_AND 0x10
#define CFG35_CDC_GAIN_CORR_LOW_AND 0xFF
#define CFG38_BG_TIME_AND 0xFF
#define CFG39_PULSE_SEL1_AND 0xF0
#define CFG39_PULSE_SEL0_AND 0x0F
#define CFG40_C_SENSE_SEL_AND 0xFF
#define CFG41_R_SENSE_SEL_AND 0xFF
#define CFG42_ALARM1_SELECT_AND 0x40
#define CFG42_ALARM0_SELECT_AND 0x10
#define CFG42_EN_ASYNC_RD_AND 0x08
#define CFG42_HS_MODE_SEL_AND 0x04
#define CFG42_R_MEDIAN_EN_AND 0x02
#define CFG42_C_MEDIAN_EN_AND 0x01
#define CFG47_RUNBIT_AND 0x01
#define CFG48_MEM_LOCK_AND 0x0F
#define CFG49_SERIAL_NUMBER_LOW_AND 0xFF
#define CFG50_SERIAL_NUMBER_HIGH_AND 0xFF
#define CFG54_MEM_CTRL_AND 0xFF
#define CFG62_CHARGE_PUMP_LOW_AND 0xFF
#define CFG63_CHARGE_PUMP_HIGH_AND 0xFF

#endif