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aiutils.c
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/*
* Misc utility routines for accessing chip-specific features
* of the SiliconBackplane-based Broadcom chips.
*
* Copyright (C) 2022, Broadcom.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
*
* <<Broadcom-WL-IPTag/Dual:>>
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <pcie_core.h>
#include "siutils_priv.h"
#include <bcmdevs.h>
#if defined(ETD)
#include <etd.h>
#endif
#if !defined(BCMDONGLEHOST)
#define PMU_DMP() (cores_info->coreid[sii->curidx] == PMU_CORE_ID)
#define GCI_DMP() (cores_info->coreid[sii->curidx] == GCI_CORE_ID)
#else
#define PMU_DMP() (0)
#define GCI_DMP() (0)
#endif /* !defined(BCMDONGLEHOST) */
#if defined(AXI_TIMEOUTS_NIC)
static bool ai_get_apb_bridge(const si_t *sih, uint32 coreidx, uint32 *apb_id,
uint32 *apb_coreunit);
#endif /* AXI_TIMEOUTS_NIC */
#if defined(AXI_TIMEOUTS) || defined(AXI_TIMEOUTS_NIC)
static void ai_reset_axi_to(const si_info_t *sii, aidmp_t *ai);
#endif /* defined (AXI_TIMEOUTS) || defined (AXI_TIMEOUTS_NIC) */
#ifdef DONGLEBUILD
static uint32 ai_get_sizeof_wrapper_offsets_to_dump(void);
static uint32 ai_get_wrapper_base_addr(uint32 **offset);
#endif /* DONGLEBUILD */
/* AXI ID to CoreID + unit mappings */
typedef struct axi_to_coreidx {
uint coreid;
uint coreunit;
} axi_to_coreidx_t;
static const axi_to_coreidx_t axi2coreidx_4369[] = {
{CC_CORE_ID, 0}, /* 00 Chipcommon */
{PCIE2_CORE_ID, 0}, /* 01 PCIe */
{D11_CORE_ID, 0}, /* 02 D11 Main */
{ARMCR4_CORE_ID, 0}, /* 03 ARM */
{BT_CORE_ID, 0}, /* 04 BT AHB */
{D11_CORE_ID, 1}, /* 05 D11 Aux */
{D11_CORE_ID, 0}, /* 06 D11 Main l1 */
{D11_CORE_ID, 1}, /* 07 D11 Aux l1 */
{D11_CORE_ID, 0}, /* 08 D11 Main l2 */
{D11_CORE_ID, 1}, /* 09 D11 Aux l2 */
{NODEV_CORE_ID, 0}, /* 10 M2M DMA */
{NODEV_CORE_ID, 0}, /* 11 unused */
{NODEV_CORE_ID, 0}, /* 12 unused */
{NODEV_CORE_ID, 0}, /* 13 unused */
{NODEV_CORE_ID, 0}, /* 14 unused */
{NODEV_CORE_ID, 0} /* 15 unused */
};
/* EROM parsing */
static uint32
get_erom_ent(const si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
{
uint32 ent;
uint inv = 0, nom = 0;
uint32 size = 0;
while (TRUE) {
ent = R_REG(SI_INFO(sih)->osh, *eromptr);
(*eromptr)++;
if (mask == 0)
break;
if ((ent & ER_VALID) == 0) {
inv++;
continue;
}
if (ent == (ER_END | ER_VALID))
break;
if ((ent & mask) == match)
break;
/* escape condition related EROM size if it has invalid values */
size += sizeof(*eromptr);
if (size >= ER_SZ_MAX) {
SI_ERROR(("Failed to find end of EROM marker\n"));
break;
}
nom++;
}
SI_VMSG(("get_erom_ent: Returning ent 0x%08x\n", ent));
if (inv + nom) {
SI_VMSG((" after %d invalid and %d non-matching entries\n", inv, nom));
}
return ent;
}
static uint32
get_asd(const si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
uint32 *sizel, uint32 *sizeh)
{
uint32 asd, sz, szd;
BCM_REFERENCE(ad);
asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
if (((asd & ER_TAG1) != ER_ADD) ||
(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
((asd & AD_ST_MASK) != st)) {
/* This is not what we want, "push" it back */
(*eromptr)--;
return 0;
}
*addrl = asd & AD_ADDR_MASK;
if (asd & AD_AG32)
*addrh = get_erom_ent(sih, eromptr, 0, 0);
else
*addrh = 0;
*sizeh = 0;
sz = asd & AD_SZ_MASK;
if (sz == AD_SZ_SZD) {
szd = get_erom_ent(sih, eromptr, 0, 0);
*sizel = szd & SD_SZ_MASK;
if (szd & SD_SG32)
*sizeh = get_erom_ent(sih, eromptr, 0, 0);
} else
*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
return asd;
}
/* Parse the enumeration rom to identify all cores */
void
ai_scan(si_t *sih, void *regs, uint devid)
{
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
chipcregs_t *cc = (chipcregs_t *)regs;
uint32 erombase, *eromptr, *eromlim;
axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
SI_MSG_DBG_REG(("%s: Enter\n", __FUNCTION__));
BCM_REFERENCE(devid);
erombase = R_REG(sii->osh, &cc->eromptr);
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
break;
case PCI_BUS:
/* Set wrappers address */
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* Now point the window at the erom */
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
eromptr = regs;
break;
#ifdef BCMSDIO
case SPI_BUS:
case SDIO_BUS:
eromptr = (uint32 *)(uintptr)erombase;
break;
#endif /* BCMSDIO */
default:
SI_ERROR(("Don't know how to do AXI enumeration on bus %d\n", sih->bustype));
ASSERT(0);
return;
}
eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
sii->axi_num_wrappers = 0;
SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n",
OSL_OBFUSCATE_BUF(regs), erombase,
OSL_OBFUSCATE_BUF(eromptr), OSL_OBFUSCATE_BUF(eromlim)));
while (eromptr < eromlim) {
uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
uint32 mpd, asd, addrl, addrh, sizel, sizeh;
uint i, j, idx;
bool br;
br = FALSE;
/* Grok a component */
cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
if (cia == (ER_END | ER_VALID)) {
SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
SI_MSG_DBG_REG(("%s: Exit\n", __FUNCTION__));
return;
}
cib = get_erom_ent(sih, &eromptr, 0, 0);
if ((cib & ER_TAG) != ER_CI) {
SI_ERROR(("CIA not followed by CIB\n"));
goto error;
}
cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
#ifdef BCMDBG_SI
SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, "
"nsw = %d, nmp = %d & nsp = %d\n",
mfg, cid, crev, OSL_OBFUSCATE_BUF(eromptr - 1), nmw, nsw, nmp, nsp));
#else
BCM_REFERENCE(crev);
#endif
/* Include Default slave wrapper for timeout monitoring */
if ((nsp == 0 && nsw == 0) ||
#if !defined(AXI_TIMEOUTS) && !defined(AXI_TIMEOUTS_NIC)
((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) ||
#else
((CHIPTYPE(sii->pub.socitype) == SOCI_NAI) &&
(mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) ||
#endif /* !defined(AXI_TIMEOUTS) && !defined(AXI_TIMEOUTS_NIC) */
FALSE) {
continue;
}
if ((nmw + nsw == 0)) {
/* A component which is not a core */
/* Should record some info */
if (cid == OOB_ROUTER_CORE_ID) {
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
&addrl, &addrh, &sizel, &sizeh);
if (asd != 0) {
if ((sii->oob_router != 0) && (sii->oob_router != addrl)) {
sii->oob_router1 = addrl;
} else {
sii->oob_router = addrl;
}
}
}
if ((cid != NS_CCB_CORE_ID) && (cid != PMU_CORE_ID) &&
(cid != GCI_CORE_ID) && (cid != SR_CORE_ID) &&
(cid != HUB_CORE_ID) && (cid != HND_OOBR_CORE_ID) &&
(cid != CCI400_CORE_ID) && (cid != SPMI_SLAVE_CORE_ID)) {
continue;
}
}
idx = sii->numcores;
cores_info->cia[idx] = cia;
cores_info->cib[idx] = cib;
cores_info->coreid[idx] = cid;
/* workaround the fact the variable buscoretype is used in _ai_set_coreidx()
* when checking PCIE_GEN2() for PCI_BUS case before it is setup later...,
* both use and setup happen in si_buscore_setup().
*/
if (BUSTYPE(sih->bustype) == PCI_BUS &&
(cid == PCI_CORE_ID || cid == PCIE_CORE_ID || cid == PCIE2_CORE_ID)) {
sii->pub.buscoretype = (uint16)cid;
}
for (i = 0; i < nmp; i++) {
mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
if ((mpd & ER_TAG) != ER_MP) {
SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
goto error;
}
/* Record something? */
SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
(mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
(mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
}
/* First Slave Address Descriptor should be port 0:
* the main register space for the core
*/
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
if (asd == 0) {
do {
/* Try again to see if it is a bridge */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
&sizel, &sizeh);
if (asd != 0)
br = TRUE;
else {
break;
}
} while (1);
} else {
if (addrl == 0 || sizel == 0) {
SI_ERROR((" Invalid ASD %x for slave port \n", asd));
goto error;
}
cores_info->coresba[idx] = addrl;
cores_info->coresba_size[idx] = sizel;
}
/* Get any more ASDs in first port */
j = 1;
do {
asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
/* Support ARM debug core ASD with address space > 4K */
if ((asd != 0) && (j == 1)) {
SI_VMSG(("Warning: sizel > 0x1000\n"));
cores_info->coresba2[idx] = addrl;
cores_info->coresba2_size[idx] = sizel;
}
j++;
} while (asd != 0);
/* Go through the ASDs for other slave ports */
for (i = 1; i < nsp; i++) {
j = 0;
do {
asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
/* To get the first base address of second slave port */
if ((asd != 0) && (i == 1) && (j == 0)) {
cores_info->csp2ba[idx] = addrl;
cores_info->csp2ba_size[idx] = sizel;
}
if (asd == 0)
break;
j++;
} while (1);
if (j == 0) {
SI_ERROR((" SP %d has no address descriptors\n", i));
goto error;
}
}
/* Now get master wrappers */
for (i = 0; i < nmw; i++) {
asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0) {
SI_ERROR(("Missing descriptor for MW %d\n", i));
goto error;
}
if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("Master wrapper %d is not 4KB\n", i));
goto error;
}
if (i == 0) {
cores_info->wrapba[idx] = addrl;
} else if (i == 1) {
cores_info->wrapba2[idx] = addrl;
} else if (i == 2) {
cores_info->wrapba3[idx] = addrl;
}
if (axi_wrapper && (sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS)) {
axi_wrapper[sii->axi_num_wrappers].mfg = mfg;
axi_wrapper[sii->axi_num_wrappers].cid = cid;
axi_wrapper[sii->axi_num_wrappers].rev = crev;
axi_wrapper[sii->axi_num_wrappers].wrapper_type = AI_MASTER_WRAPPER;
axi_wrapper[sii->axi_num_wrappers].wrapper_addr = addrl;
sii->axi_num_wrappers++;
SI_VMSG(("MASTER WRAPPER: %d, mfg:%x, cid:%x,"
"rev:%x, addr:%x, size:%x\n",
sii->axi_num_wrappers, mfg, cid, crev, addrl, sizel));
}
}
/* And finally slave wrappers */
for (i = 0; i < nsw; i++) {
uint fwp = (nsp <= 1) ? 0 : 1;
asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0) {
SI_ERROR(("Missing descriptor for SW %d cid %x eromp %p fwp %d \n",
i, cid, eromptr, fwp));
goto error;
}
if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
goto error;
}
/* cache APB bridge wrapper address for set/clear timeout */
if ((mfg == MFGID_ARM) && (cid == APB_BRIDGE_ID)) {
ASSERT(sii->num_br < SI_MAXBR);
if (sii->num_br >= SI_MAXBR) {
SI_ERROR(("bridge number %d is overflowed\n", sii->num_br));
goto error;
}
sii->br_wrapba[sii->num_br++] = addrl;
}
if ((mfg == MFGID_ARM) && (cid == ADB_BRIDGE_ID)) {
br = TRUE;
}
BCM_REFERENCE(br);
if ((nmw == 0) && (i == 0)) {
cores_info->wrapba[idx] = addrl;
} else if ((nmw == 0) && (i == 1)) {
cores_info->wrapba2[idx] = addrl;
} else if ((nmw == 0) && (i == 2)) {
cores_info->wrapba3[idx] = addrl;
}
/* Include all slave wrappers to the list to
* enable and monitor watchdog timeouts
*/
if (axi_wrapper && (sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS)) {
axi_wrapper[sii->axi_num_wrappers].mfg = mfg;
axi_wrapper[sii->axi_num_wrappers].cid = cid;
axi_wrapper[sii->axi_num_wrappers].rev = crev;
axi_wrapper[sii->axi_num_wrappers].wrapper_type = AI_SLAVE_WRAPPER;
axi_wrapper[sii->axi_num_wrappers].wrapper_addr = addrl;
sii->axi_num_wrappers++;
SI_VMSG(("SLAVE WRAPPER: %d, mfg:%x, cid:%x,"
"rev:%x, addr:%x, size:%x\n",
sii->axi_num_wrappers, mfg, cid, crev, addrl, sizel));
}
}
#ifndef AXI_TIMEOUTS_NIC
/* Don't record bridges and core with 0 slave ports */
if (br || (nsp == 0)) {
continue;
}
#endif
/* Done with core */
sii->numcores++;
}
SI_ERROR(("Reached end of erom without finding END\n"));
error:
sii->numcores = 0;
SI_MSG_DBG_REG(("%s: Exit\n", __FUNCTION__));
return;
}
#define AI_SETCOREIDX_MAPSIZE(coreid) \
(((coreid) == NS_CCB_CORE_ID) ? 15 * SI_CORE_SIZE : SI_CORE_SIZE)
/* This function changes the logical "focus" to the indicated core.
* Return the current core's virtual address.
*/
static volatile void *
BCMPOSTTRAPFN(_ai_setcoreidx)(si_t *sih, uint coreidx, uint use_wrapn)
{
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint32 addr, wrap, wrap2, wrap3;
volatile void *regs;
if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
return (NULL);
addr = cores_info->coresba[coreidx];
wrap = cores_info->wrapba[coreidx];
wrap2 = cores_info->wrapba2[coreidx];
wrap3 = cores_info->wrapba3[coreidx];
#ifdef AXI_TIMEOUTS_NIC
/* No need to disable interrupts while entering/exiting APB bridge core */
if ((cores_info->coreid[coreidx] != APB_BRIDGE_CORE_ID) &&
(cores_info->coreid[sii->curidx] != APB_BRIDGE_CORE_ID))
#endif /* AXI_TIMEOUTS_NIC */
{
/*
* If the user has provided an interrupt mask enabled function,
* then assert interrupts are disabled before switching the core.
*/
ASSERT((sii->intrsenabled_fn == NULL) ||
!(*(sii)->intrsenabled_fn)((sii)->intr_arg));
}
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
/* map new one */
if (!cores_info->regs[coreidx]) {
cores_info->regs[coreidx] = REG_MAP(addr,
AI_SETCOREIDX_MAPSIZE(cores_info->coreid[coreidx]));
ASSERT(GOODREGS(cores_info->regs[coreidx]));
}
sii->curmap = regs = cores_info->regs[coreidx];
if (!cores_info->wrappers[coreidx] && (wrap != 0)) {
cores_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->wrappers[coreidx]));
}
if (!cores_info->wrappers2[coreidx] && (wrap2 != 0)) {
cores_info->wrappers2[coreidx] = REG_MAP(wrap2, SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->wrappers2[coreidx]));
}
if (!cores_info->wrappers3[coreidx] && (wrap3 != 0)) {
cores_info->wrappers3[coreidx] = REG_MAP(wrap3, SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->wrappers3[coreidx]));
}
if (use_wrapn == 2) {
sii->curwrap = cores_info->wrappers3[coreidx];
} else if (use_wrapn == 1) {
sii->curwrap = cores_info->wrappers2[coreidx];
} else {
sii->curwrap = cores_info->wrappers[coreidx];
}
break;
case PCI_BUS:
regs = sii->curmap;
/* point bar0 2nd 4KB window to the primary wrapper */
if (use_wrapn == 2) {
wrap = wrap3;
} else if (use_wrapn == 1) {
wrap = wrap2;
}
/* Use BAR0 Window to support dual mac chips... */
/* TODO: the other mac unit can't be supportd by the current BAR0 window.
* need to find other ways to access these cores.
*/
switch (sii->slice) {
case 0: /* main/first slice */
#ifdef AXI_TIMEOUTS_NIC
/* No need to set the BAR0 if core is APB Bridge.
* This is to reduce 2 PCI writes while checkng for errlog
*/
if (cores_info->coreid[coreidx] != APB_BRIDGE_CORE_ID)
#endif /* AXI_TIMEOUTS_NIC */
{
/* point bar0 window */
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
}
if (PCIE_GEN2(sii))
OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2, 4, wrap);
else
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
break;
case 1: /* aux/second slice */
/* PCIE GEN2 only for other slices */
if (!PCIE_GEN2(sii)) {
/* other slices not supported */
SI_ERROR(("PCI GEN not supported for slice %d\n", sii->slice));
ASSERT(0);
break;
}
/* 0x4000 - 0x4fff: enum space 0x5000 - 0x5fff: wrapper space */
regs = (volatile uint8 *)regs + PCI_SEC_BAR0_WIN_OFFSET;
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* point bar0 window */
OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, addr);
OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN2, 4, wrap);
break;
case 2: /* scan/third slice */
/* PCIE GEN2 only for other slices */
if (!PCIE_GEN2(sii)) {
/* other slices not supported */
SI_ERROR(("PCI GEN not supported for slice %d\n", sii->slice));
ASSERT(0);
break;
}
/* 0x9000 - 0x9fff: enum space 0xa000 - 0xafff: wrapper space */
regs = (volatile uint8 *)regs + PCI_TER_BAR0_WIN_OFFSET;
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* point bar0 window */
ai_corereg(sih, sih->buscoreidx,
PCIE_TER_BAR0_WIN_REG(sih->buscorerev), ~0, addr);
ai_corereg(sih, sih->buscoreidx,
PCIE_TER_BAR0_WRAPPER_REG(sih->buscorerev), ~0, wrap);
break;
default: /* other slices */
SI_ERROR(("BAR0 Window not supported for slice %d\n", sii->slice));
ASSERT(0);
break;
}
break;
#ifdef BCMSDIO
case SPI_BUS:
case SDIO_BUS:
sii->curmap = regs = (void *)((uintptr)addr);
if (use_wrapn)
sii->curwrap = (void *)((uintptr)wrap2);
else
sii->curwrap = (void *)((uintptr)wrap);
break;
#endif /* BCMSDIO */
default:
ASSERT(0);
sii->curmap = regs = NULL;
break;
}
sii->curidx = coreidx;
if (regs) {
SI_MSG_DBG_REG(("%s: %d\n", __FUNCTION__, coreidx));
}
return regs;
}
volatile void *
BCMPOSTTRAPFN(ai_setcoreidx)(si_t *sih, uint coreidx)
{
return _ai_setcoreidx(sih, coreidx, 0);
}
volatile void *
BCMPOSTTRAPFN(ai_setcoreidx_2ndwrap)(si_t *sih, uint coreidx)
{
return _ai_setcoreidx(sih, coreidx, 1);
}
volatile void *
BCMPOSTTRAPFN(ai_setcoreidx_3rdwrap)(si_t *sih, uint coreidx)
{
return _ai_setcoreidx(sih, coreidx, 2);
}
void
ai_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
chipcregs_t *cc = NULL;
uint32 erombase, *eromptr, *eromlim;
uint i, j, cidx;
uint32 cia, cib, nmp, nsp;
uint32 asd, addrl, addrh, sizel, sizeh;
for (i = 0; i < sii->numcores; i++) {
if (cores_info->coreid[i] == CC_CORE_ID) {
cc = (chipcregs_t *)cores_info->regs[i];
break;
}
}
if (cc == NULL)
goto error;
BCM_REFERENCE(erombase);
erombase = R_REG(sii->osh, &cc->eromptr);
eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
cidx = sii->curidx;
cia = cores_info->cia[cidx];
cib = cores_info->cib[cidx];
nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
/* scan for cores */
while (eromptr < eromlim) {
if ((get_erom_ent(sih, &eromptr, ER_TAG, ER_CI) == cia) &&
(get_erom_ent(sih, &eromptr, 0, 0) == cib)) {
break;
}
}
/* skip master ports */
for (i = 0; i < nmp; i++)
get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
/* Skip ASDs in port 0 */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
if (asd == 0) {
/* Try again to see if it is a bridge */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
&sizel, &sizeh);
}
j = 1;
do {
asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
j++;
} while (asd != 0);
/* Go through the ASDs for other slave ports */
for (i = 1; i < nsp; i++) {
j = 0;
do {
asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0)
break;
if (!asidx--) {
*addr = addrl;
*size = sizel;
return;
}
j++;
} while (1);
if (j == 0) {
SI_ERROR((" SP %d has no address descriptors\n", i));
break;
}
}
error:
*size = 0;
return;
}
/* Return the number of address spaces in current core */
int
ai_numaddrspaces(const si_t *sih)
{
/* TODO: Either save it or parse the EROM on demand, currently hardcode 2 */
BCM_REFERENCE(sih);
return 2;
}
/* Return the address of the nth address space in the current core
* Arguments:
* sih : Pointer to struct si_t
* spidx : slave port index
* baidx : base address index
*/
uint32
ai_addrspace(const si_t *sih, uint spidx, uint baidx)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint cidx;
cidx = sii->curidx;
if (spidx == CORE_SLAVE_PORT_0) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->coresba[cidx];
else if (baidx == CORE_BASE_ADDR_1)
return cores_info->coresba2[cidx];
}
else if (spidx == CORE_SLAVE_PORT_1) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->csp2ba[cidx];
}
SI_ERROR(("ai_addrspace: Need to parse the erom again to find %d base addr"
" in %d slave port\n",
baidx, spidx));
return 0;
}
/* Return the size of the nth address space in the current core
* Arguments:
* sih : Pointer to struct si_t
* spidx : slave port index
* baidx : base address index
*/
uint32
ai_addrspacesize(const si_t *sih, uint spidx, uint baidx)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint cidx;
cidx = sii->curidx;
if (spidx == CORE_SLAVE_PORT_0) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->coresba_size[cidx];
else if (baidx == CORE_BASE_ADDR_1)
return cores_info->coresba2_size[cidx];
}
else if (spidx == CORE_SLAVE_PORT_1) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->csp2ba_size[cidx];
}
SI_ERROR(("ai_addrspacesize: Need to parse the erom again to find %d"
" base addr in %d slave port\n",
baidx, spidx));
return 0;
}
uint
ai_flag(si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
#if !defined(BCMDONGLEHOST)
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
#endif
aidmp_t *ai;
if (PMU_DMP()) {
uint idx, flag;
idx = sii->curidx;
ai_setcoreidx(sih, SI_CC_IDX);
flag = ai_flag_alt(sih);
ai_setcoreidx(sih, idx);
return flag;
}
ai = sii->curwrap;
ASSERT(ai != NULL);
return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
}
uint
ai_flag_alt(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
aidmp_t *ai = sii->curwrap;
return ((R_REG(sii->osh, &ai->oobselouta30) >> AI_OOBSEL_1_SHIFT) & AI_OOBSEL_MASK);
}
void
ai_setint(const si_t *sih, int siflag)
{
BCM_REFERENCE(sih);
BCM_REFERENCE(siflag);
/* TODO: Figure out how to set interrupt mask in ai */
}
uint
BCMPOSTTRAPFN(ai_wrap_reg)(const si_t *sih, uint32 offset, uint32 mask, uint32 val)
{
const si_info_t *sii = SI_INFO(sih);
uint32 *addr = (uint32 *) ((uchar *)(sii->curwrap) + offset);
if (mask || val) {
uint32 w = R_REG(sii->osh, addr);
w &= ~mask;
w |= val;
W_REG(sii->osh, addr, w);
}
return (R_REG(sii->osh, addr));
}
uint
ai_corevendor(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint32 cia;
cia = cores_info->cia[sii->curidx];
return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
}
uint
BCMPOSTTRAPFN(ai_corerev)(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint32 cib;
cib = cores_info->cib[sii->curidx];
return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
}
uint
ai_corerev_minor(const si_t *sih)
{
return (ai_core_sflags(sih, 0, 0) >> SISF_MINORREV_D11_SHIFT) &
SISF_MINORREV_D11_MASK;
}
bool
BCMPOSTTRAPFN(ai_iscoreup)(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
aidmp_t *ai = sii->curwrap;
return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
}
/*
* Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
* switch back to the original core, and return the new value.
*
* When using the silicon backplane, no fiddling with interrupts or core switches is needed.
*
* Also, when using pci/pcie, we can optimize away the core switching for pci registers
* and (on newer pci cores) chipcommon registers.
*/
uint
BCMPOSTTRAPFN(ai_corereg)(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
volatile uint32 *r = NULL;
uint w;
bcm_int_bitmask_t intr_val;
bool fast = FALSE;
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
ASSERT(GOODIDX(coreidx, sii->numcores));
ASSERT(regoff < SI_CORE_SIZE);
ASSERT((val & ~mask) == 0);
if (coreidx >= SI_MAXCORES)
return 0;
if (BUSTYPE(sih->bustype) == SI_BUS) {
/* If internal bus, we can always get at everything */
fast = TRUE;
/* map if does not exist */
if (!cores_info->regs[coreidx]) {
cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->regs[coreidx]));
}
r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
/* Chipc registers are mapped at 12KB */
fast = TRUE;
r = (volatile uint32 *)((volatile char *)sii->curmap +
PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) {
/* pci registers are at either in the last 2KB of an 8KB window
* or, in pcie and pci rev 13 at 8KB
*/
fast = TRUE;
if (SI_FAST(sii))
r = (volatile uint32 *)((volatile char *)sii->curmap +
PCI_16KB0_PCIREGS_OFFSET + regoff);
else
r = (volatile uint32 *)((volatile char *)sii->curmap +
((regoff >= SBCONFIGOFF) ?
PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
regoff);
}
}