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hndpmu.c
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/*
* Misc utility routines for accessing PMU corerev specific features
* of the SiliconBackplane-based Broadcom chips.
*
* Copyright (C) 2022, Broadcom.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
*
* <<Broadcom-WL-IPTag/Dual:>>
*/
/**
* @file
* Note: this file contains PLL/FLL related functions. A chip can contain multiple PLLs/FLLs.
* However, in the context of this file the baseband ('BB') PLL/FLL is referred to.
*
* Throughout this code, the prefixes 'pmu1_' and 'pmu2_' are used.
* They refer to different revisions of the PMU (which is at revision 18 @ Apr 25, 2012)
* pmu1_ marks the transition from PLL to ADFLL (Digital Frequency Locked Loop). It supports
* fractional frequency generation. pmu2_ does not support fractional frequency generation.
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <bcmdevs.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <hndchipc.h>
#include <hndpmu.h>
#if defined DONGLEBUILD
#include <hndcpu.h>
#ifdef __arm__
#include <hndarm.h>
#endif
#endif /* DONGLEBUILD */
#if !defined(BCMDONGLEHOST)
#include <bcm_math.h>
#include <bcmotp.h>
#ifdef BCM_OTP_API
#include <bcm_otp_api.h>
#endif /* BCM_OTP_API */
#endif /* !BCMDONGLEHOST */
#if !defined(BCMDONGLEHOST)
#include <saverestore.h>
#endif
#include <hndlhl.h>
#include <sbgci.h>
#ifdef EVENT_LOG_COMPILE
#include <event_log.h>
#endif
#include <sbgci.h>
#include <lpflags.h>
#include "siutils_priv.h"
#ifdef BCM_AVS
#include <bcm_avs.h>
#endif
#if defined(EVENT_LOG_COMPILE) && defined(BCMDBG_ERR) && defined(ERR_USE_EVENT_LOG)
#if defined(ERR_USE_EVENT_LOG_RA)
#define PMU_ERROR(args) EVENT_LOG_RA(EVENT_LOG_TAG_PMU_ERROR, args)
#else
#define PMU_ERROR(args) EVENT_LOG_COMPACT_CAST_PAREN_ARGS(EVENT_LOG_TAG_PMU_ERROR, args)
#endif /* ERR_USE_EVENT_LOG_RA */
#elif defined(BCMDBG_ERR)
#define PMU_ERROR(args) printf args
#else
#define PMU_ERROR(args)
#endif /* defined(BCMDBG_ERR) && defined(ERR_USE_EVENT_LOG) */
#ifdef BCMDBG
//#define BCMDBG_PMU
#endif
#ifdef BCMDBG_PMU
#define PMU_MSG(args) printf args
#else
#define PMU_MSG(args)
#endif /* BCMDBG_MPU */
/* To check in verbose debugging messages not intended
* to be on except on private builds.
*/
#define PMU_NONE(args)
#define flags_shift 14
/** contains resource bit positions for a specific chip */
struct rsc_per_chip {
uint8 ht_avail;
uint8 macphy_clkavail;
uint8 ht_start;
uint8 otp_pu;
uint8 macphy_aux_clkavail;
uint8 macphy_scan_clkavail;
uint8 cb_ready;
uint8 dig_ready;
};
typedef struct rsc_per_chip rsc_per_chip_t;
#if defined(BCMPMU_STATS) && !defined(BCMPMU_STATS_DISABLED)
bool _pmustatsenab = TRUE;
#else
bool _pmustatsenab = FALSE;
#endif /* BCMPMU_STATS */
/* 1MHz lpo enable */
/* PLEASE USE THIS MACRO IN ATTACH PATH ONLY! */
#if defined(BCM_FASTLPO) && !defined(BCM_FASTLPO_DISABLED)
#define FASTLPO_ENAB() (TRUE)
#else
#define FASTLPO_ENAB() (FALSE)
#endif
/* Disable the power optimization feature */
bool _bcm_pwr_opt_dis = FALSE;
#ifdef BCMSRTOPOFF
bool _srtopoff_enab = FALSE;
#endif
pmuregs_t *hnd_pmur = NULL; /* PMU core regs */
#if !defined(BCMDONGLEHOST)
static void si_pmu_chipcontrol_xtal_settings_4369(si_t *sih);
static void si_pmu_chipcontrol_xtal_settings_4362(si_t *sih);
static void si_pmu_chipcontrol_xtal_settings_4378(si_t *sih);
/* PLL controls/clocks */
static void si_pmu1_pllinit1(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 xtal);
static void si_pmu_pll_off(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *min_mask,
uint32 *max_mask, uint32 *clk_ctl_st);
static void si_pmu_pll_on(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 min_mask,
uint32 max_mask, uint32 clk_ctl_st);
static void si_pmu_otp_pllcontrol(si_t *sih, osl_t *osh);
static void si_pmu_otp_vreg_control(si_t *sih, osl_t *osh);
static void si_pmu_otp_chipcontrol(si_t *sih, osl_t *osh);
static uint32 si_pmu_def_alp_clock(si_t *sih, osl_t *osh);
static bool si_pmu_update_pllcontrol(si_t *sih, osl_t *osh, uint32 xtal, bool update_required);
static uint32 si_pmu_htclk_mask(si_t *sih);
static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, pmuregs_t *pmu);
static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, pmuregs_t *pmu);
static uint32 si_pmu1_cpuclk0_pll2(si_t *sih);
/* PMU resources */
static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 rsrcs, bool all);
static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, pmuregs_t *pmu,
uint8 rsrc, bool pmu_fast_trans_en);
static void si_pmu_res_masks(si_t *sih, uint32 *pmin, uint32 *pmax);
uint32 si_pmu_get_pmutime_diff(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint32 *prev);
bool si_pmu_wait_for_res_pending(si_t *sih, osl_t *osh, pmuregs_t *pmu, uint usec,
bool cond, uint32 *elapsed_time);
#ifdef __ARM_ARCH_7A__
static uint32 si_pmu_mem_ca7clock(si_t *sih, osl_t *osh);
#endif
static uint8 fastlpo_dis_get(void);
static uint8 fastlpo_pcie_dis_get(void);
static uint32 si_pmu_bpclk_4387(si_t *sih);
static int si_pmu_openloop_cal_43012(si_t *sih, uint16 currtemp);
static uint32 si_pmu_pll6val_armclk_calc(osl_t *osh, pmuregs_t *pmu, uint32 armclk, uint32 xtal,
bool write);
static bool si_pmu_armpll_write_required(si_t *sih, uint32 xtal);
uint8 si_pmu_pll28nm_calc_ndiv(uint32 fvco, uint32 xtal, uint32 *ndiv_int, uint32 *ndiv_frac);
void si_pmu_armpll_freq_upd(si_t *sih, uint8 p1div, uint32 ndiv_int, uint32 ndiv_frac);
void si_pmu_bbpll_freq_upd(si_t *sih, uint8 p1div, uint32 ndiv_int, uint32 ndiv_frac);
void si_pmu_armpll_chmdiv_upd(si_t *sih, uint32 ch0_mdiv, uint32 ch1_mdiv);
#ifdef BCM_LDO3P3_SOFTSTART
static int si_pmu_ldo3p3_soft_start_get(si_t *sih, osl_t *osh, uint32 bt_or_wl, int *res);
static int si_pmu_ldo3p3_soft_start_set(si_t *sih, osl_t *osh, uint32 bt_or_wl, uint32 slew_rate);
#endif /* BCM_LDO3P3_SOFTSTART */
#ifdef XTAL_BIAS_FROM_OTP
static void si_pmu_chipcontrol_xtal_bias_from_otp(si_t *sih, uint8* flag, uint8* val);
#ifndef BCM_OTP_API
static void si_pmu_chipcontrol_xtal_bias_cal_done_offsets(si_t *sih, uint16* wrd_offset,
uint8* wrd_shift, uint8* wrd_mask);
static void si_pmu_chipcontrol_xtal_bias_val_offsets(si_t *sih, uint16* wrd_offset,
uint8* wrd_shift, uint8* wrd_mask);
#endif /* !BCM_OTP_API */
#endif /* XTAL_BIAS_FROM_OTP */
/* PMU timer ticks once in 32uS */
#define PMU_US_STEPS (32)
void *g_si_pmutmr_lock_arg = NULL;
si_pmu_callback_t g_si_pmutmr_lock_cb = NULL, g_si_pmutmr_unlock_cb = NULL;
/* FVCO frequency in [KHz] */
#define FVCO_640 640000 /**< 640MHz */
#define FVCO_880 880000 /**< 880MHz */
#define FVCO_1760 1760000 /**< 1760MHz */
#define FVCO_1440 1440000 /**< 1440MHz */
#define FVCO_960 960000 /**< 960MHz */
#define FVCO_960p1 960100 /**< 960.1MHz */
#define FVCO_960010 960010 /**< 960.0098MHz */
#define FVCO_961 961000 /**< 961MHz */
#define FVCO_960p5 960500 /**< 960.5MHz */
#define FVCO_963 963000 /**< 963MHz */
#define FVCO_963p01 963010 /**< 963.01MHz */
#define FVCO_1000 1000000 /**< 1000MHz */
#define FVCO_1600 1600000 /**< 1600MHz */
#define FVCO_1920 1920000 /**< 1920MHz */
#define FVCO_1938 1938000 /* 1938MHz */
#define FVCO_385 385000 /**< 385MHz */
#define FVCO_400 400000 /**< 400MHz */
#define FVCO_720 720000 /**< 720MHz */
#define FVCO_2880 2880000 /**< 2880 MHz */
#define FVCO_2946 2946000 /**< 2946 MHz */
#define FVCO_3000 3000000 /**< 3000 MHz */
#define FVCO_3200 3200000 /**< 3200 MHz */
#define FVCO_1002p8 1002823 /**< 1002.823MHz */
/* defines to make the code more readable */
/* But 0 is a valid resource number! */
#define NO_SUCH_RESOURCE 0 /**< means: chip does not have such a PMU resource */
/* uses these defines instead of 'magic' values when writing to register pllcontrol_addr */
#define PMU_PLL_CTRL_REG0 0
#define PMU_PLL_CTRL_REG1 1
#define PMU_PLL_CTRL_REG2 2
#define PMU_PLL_CTRL_REG3 3
#define PMU_PLL_CTRL_REG4 4
#define PMU_PLL_CTRL_REG5 5
#define PMU_PLL_CTRL_REG6 6
#define PMU_PLL_CTRL_REG7 7
#define PMU_PLL_CTRL_REG8 8
#define PMU_PLL_CTRL_REG9 9
#define PMU_PLL_CTRL_REG10 10
#define PMU_PLL_CTRL_REG11 11
#define PMU_PLL_CTRL_REG12 12
#define PMU_PLL_CTRL_REG13 13
#define PMU_PLL_CTRL_REG14 14
#define PMU_PLL_CTRL_REG15 15
#ifndef BCM_OTP_API
#define OTP_XTAL_BIAS_CAL_DONE_4378_WRD_OFFSET 743
#define OTP_XTAL_BIAS_CAL_DONE_4378_WRD_SHIFT 8
#define OTP_XTAL_BIAS_CAL_DONE_4378_WRD_MASK 0x1
#define OTP_XTAL_BIAS_VAL_4378_WRD_OFFSET 743
#define OTP_XTAL_BIAS_VAL_4378_WRD_SHIFT 0
#define OTP_XTAL_BIAS_VAL_4378_WRD_MASK 0xFF
#endif /* !BCM_OTP_API */
/* changes the drive strength of gpio_12 and gpio_14 from 0x3 to 0x01 */
#define GPIO_DRIVE_4378_MASK 0x3Fu
#define GPIO_DRIVE_4378_VAL 0x09u
/**
* The chip has one or more PLLs/FLLs (e.g. baseband PLL, USB PHY PLL). The settings of each PLL are
* contained within one or more 'PLL control' registers. Since the PLL hardware requires that
* changes for one PLL are committed at once, the PMU has a provision for 'updating' all PLL control
* registers at once.
*
* When software wants to change the any PLL parameters, it withdraws requests for that PLL clock,
* updates the PLL control registers being careful not to alter any control signals for the other
* PLLs, and then writes a 1 to PMUCtl.PllCtnlUpdate to commit the changes. Best usage model would
* be bring PLL down then update the PLL control register.
*/
void
si_pmu_pllupd(si_t *sih)
{
pmu_corereg(sih, SI_CC_IDX, pmucontrol,
PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
}
/* 4360_OTP_PU is used for 4352, not a typo */
static rsc_per_chip_t rsc_4352 = {NO_SUCH_RESOURCE, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, RES4360_OTP_PU, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE};
static rsc_per_chip_t rsc_4360 = {RES4360_HT_AVAIL, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, RES4360_OTP_PU, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE};
static rsc_per_chip_t rsc_43602 = {RES43602_HT_AVAIL, RES43602_MACPHY_CLKAVAIL,
RES43602_HT_START, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE};
static rsc_per_chip_t rsc_43012 = {RES43012_HT_AVAIL, RES43012_MACPHY_CLK_AVAIL,
RES43012_HT_START, RES43012_OTP_PU, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE};
/* As per the chip team OTP doesn't have the resource in 4369 */
static rsc_per_chip_t rsc_4369 = {RES4369_HT_AVAIL, RES4369_MACPHY_MAIN_CLK_AVAIL,
RES4369_HT_AVAIL, NO_SUCH_RESOURCE, RES4369_MACPHY_AUX_CLK_AVAIL,
NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, RES4369_DIG_CORE_RDY};
static rsc_per_chip_t rsc_4378 = {RES4378_HT_AVAIL, RES4378_MACPHY_MAIN_CLK_AVAIL,
RES4378_HT_AVAIL, RES4378_PMU_SLEEP, RES4378_MACPHY_AUX_CLK_AVAIL,
NO_SUCH_RESOURCE, RES4378_CORE_RDY_CB, RES4378_CORE_RDY_DIG};
static rsc_per_chip_t rsc_4381 = {RES4387_HT_AVAIL, RES4387_MACPHY_CLK_MAIN,
RES4387_HT_AVAIL, RES4387_PMU_SLEEP, NO_SUCH_RESOURCE,
NO_SUCH_RESOURCE, RES4387_CORE_RDY_CB, RES4387_CORE_RDY_DIG};
static rsc_per_chip_t rsc_4387 = {RES4387_HT_AVAIL, RES4387_MACPHY_CLK_MAIN,
RES4387_HT_AVAIL, RES4387_PMU_SLEEP, RES4387_MACPHY_CLK_AUX,
RES4387_MACPHY_CLK_SCAN, RES4387_CORE_RDY_CB, RES4387_CORE_RDY_DIG};
static rsc_per_chip_t rsc_4388 = {RES4388_HT_AVAIL, RES4388_MACPHY_CLK_MAIN,
RES4388_HT_AVAIL, RES4388_PMU_LP, RES4388_MACPHY_CLK_AUX,
RES4388_MACPHY_CLK_SCAN, RES4388_CORE_RDY_CB, RES4388_CORE_RDY_DIG};
static rsc_per_chip_t rsc_4389 = {RES4389_HT_AVAIL, RES4389_MACPHY_CLK_MAIN,
RES4389_HT_AVAIL, RES4389_PMU_LP, RES4389_MACPHY_CLK_AUX,
RES4389_MACPHY_CLK_SCAN, RES4389_CORE_RDY_CB, RES4389_CORE_RDY_DIG};
static rsc_per_chip_t rsc_4397 = {RES4397_HT_AVAIL, RES4397_MACPHY_CLK_MAIN,
RES4397_HT_AVAIL, RES4397_PMU_LP, RES4397_MACPHY_CLK_AUX,
RES4397_MACPHY_CLK_SCAN, RES4397_CORE_RDY_CB, RES4397_CORE_RDY_DIG};
static rsc_per_chip_t rsc_4362 = {RES4362_HT_AVAIL, RES4362_MACPHY_MAIN_CLK_AVAIL,
RES4362_HT_AVAIL, /* macphy aux clk */
NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE, NO_SUCH_RESOURCE,
RES4362_DIG_CORE_RDY};
/**
* For each chip, location of resource bits (e.g., ht bit) in resource mask registers may differ.
* This function abstracts the bit position of commonly used resources, thus making the rest of the
* code in hndpmu.c cleaner.
*/
static rsc_per_chip_t* BCMRAMFN(si_pmu_get_rsc_positions)(si_t *sih)
{
rsc_per_chip_t *rsc = NULL;
switch (CHIPID(sih->chip)) {
case BCM4352_CHIP_ID:
case BCM43526_CHIP_ID: /* usb variant of 4352 */
rsc = &rsc_4352;
break;
case BCM4360_CHIP_ID:
case BCM43460_CHIP_ID:
rsc = &rsc_4360;
break;
CASE_BCM43602_CHIP:
rsc = &rsc_43602;
break;
case BCM43012_CHIP_ID:
case BCM43013_CHIP_ID:
case BCM43014_CHIP_ID:
rsc = &rsc_43012;
break;
case BCM4369_CHIP_GRPID:
rsc = &rsc_4369;
break;
case BCM4362_CHIP_GRPID:
rsc = &rsc_4362;
break;
case BCM4376_CHIP_GRPID:
case BCM4378_CHIP_GRPID:
rsc = &rsc_4378;
break;
case BCM4381_CHIP_GRPID:
rsc = &rsc_4381; /* TBD */
break;
case BCM4385_CHIP_GRPID:
case BCM4387_CHIP_GRPID:
rsc = &rsc_4387;
break;
case BCM4388_CHIP_GRPID:
rsc = &rsc_4388;
break;
case BCM4389_CHIP_GRPID:
rsc = &rsc_4389;
break;
case BCM4397_CHIP_GRPID:
rsc = &rsc_4397;
break;
default:
ASSERT(0);
break;
}
return rsc;
}; /* si_pmu_get_rsc_positions */
static const char rstr_pllD[] = "pll%d";
static const char rstr_regD[] = "reg%d";
static const char rstr_chipcD[] = "chipc%d";
static const char rstr_rDt[] = "r%dt";
static const char rstr_rDd[] = "r%dd";
static const char rstr_Invalid_Unsupported_xtal_value_D[] =
"Invalid/Unsupported xtal value %d";
static const char rstr_xtalfreq[] = "xtalfreq";
#if defined(SAVERESTORE) && defined(LDO3P3_MIN_RES_MASK)
static const char rstr_ldo_prot[] = "ldo_prot";
#endif /* SAVERESTORE && LDO3P3_MIN_RES_MASK */
static const char rstr_btldo3p3pu[] = "btldopu";
#if defined(BCM_FASTLPO_PMU) && !defined(BCM_FASTLPO_PMU_DISABLED)
static const char rstr_fastlpo_dis[] = "fastlpo_dis";
#endif /* BCM_FASTLPO_PMU */
static const char rstr_fastlpo_pcie_dis[] = "fastlpo_pcie_dis";
static const char rstr_memlpldo_volt[] = "memlpldo_volt";
static const char rstr_lpldo_volt[] = "lpldo_volt";
static const char rstr_dyn_clksw_en[] = "dyn_clksw_en";
static const char rstr_abuck_volt[] = "abuck_volt";
static const char rstr_cbuck_volt[] = "cbuck_volt";
static const char rstr_csrtune[] = "csr_tune";
/* The check for OTP parameters for the PLL control registers is done and if found the
* registers are updated accordingly.
*/
/**
* As a hardware bug workaround, OTP can contain variables in the form 'pll%d=%d'.
* If these variables are present, the corresponding PLL control register(s) are
* overwritten, but not yet 'updated'.
*/
static void
si_pmu_otp_pllcontrol(si_t *sih, osl_t *osh)
{
char name[16];
const char *otp_val;
uint8 i;
uint32 val;
uint8 pll_ctrlcnt = 0;
if (PMUREV(sih->pmurev) >= 5) {
pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT;
} else {
pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT;
}
for (i = 0; i < pll_ctrlcnt; i++) {
snprintf(name, sizeof(name), rstr_pllD, i);
if ((otp_val = getvar(NULL, name)) == NULL)
continue;
val = (uint32)bcm_strtoul(otp_val, NULL, 0);
si_pmu_pllcontrol(sih, i, ~0, val);
}
}
/**
* The check for OTP parameters for the Voltage Regulator registers is done and if found the
* registers are updated accordingly.
*/
static void
si_pmu_otp_vreg_control(si_t *sih, osl_t *osh)
{
char name[16];
const char *otp_val;
uint8 i;
uint32 val;
uint8 vreg_ctrlcnt = 0;
if (PMUREV(sih->pmurev) >= 5) {
vreg_ctrlcnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT;
} else {
vreg_ctrlcnt = (sih->pmucaps & PCAP_VC_MASK) >> PCAP_VC_SHIFT;
}
for (i = 0; i < vreg_ctrlcnt; i++) {
snprintf(name, sizeof(name), rstr_regD, i);
if ((otp_val = getvar(NULL, name)) == NULL)
continue;
val = (uint32)bcm_strtoul(otp_val, NULL, 0);
si_pmu_vreg_control(sih, i, ~0, val);
}
}
/**
* The check for OTP parameters for the chip control registers is done and if found the
* registers are updated accordingly.
*/
static void
si_pmu_otp_chipcontrol(si_t *sih, osl_t *osh)
{
uint32 val, cc_ctrlcnt, i;
char name[16];
const char *otp_val;
if (PMUREV(sih->pmurev) >= 5) {
cc_ctrlcnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT;
} else {
cc_ctrlcnt = (sih->pmucaps & PCAP_CC_MASK) >> PCAP_CC_SHIFT;
}
for (i = 0; i < cc_ctrlcnt; i++) {
snprintf(name, sizeof(name), rstr_chipcD, i);
if ((otp_val = getvar(NULL, name)) == NULL)
continue;
val = (uint32)bcm_strtoul(otp_val, NULL, 0);
si_pmu_chipcontrol(sih, i, 0xFFFFFFFF, val); /* writes to PMU chipctrl reg 'i' */
}
}
/**
* A chip contains one or more LDOs (Low Drop Out regulators). During chip bringup, it can turn out
* that the default (POR) voltage of a regulator is not right or optimal.
* This function is called only by si_pmu_swreg_init() for specific chips
*/
void
si_pmu_set_ldo_voltage(si_t *sih, osl_t *osh, uint8 ldo, uint8 voltage)
{
uint8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
uint8 addr = 0;
uint8 do_reg2 = 0, rshift2 = 0, rc_shift2 = 0, mask2 = 0, addr2 = 0;
BCM_REFERENCE(osh);
ASSERT(sih->cccaps & CC_CAP_PMU);
switch (CHIPID(sih->chip)) {
case BCM4360_CHIP_ID:
case BCM43460_CHIP_ID:
case BCM4352_CHIP_ID:
case BCM43526_CHIP_ID:
switch (ldo) {
case SET_LDO_VOLTAGE_PAREF:
addr = 1;
rc_shift = 0;
mask = 0xf;
break;
default:
ASSERT(FALSE);
break;
}
break;
CASE_BCM43602_CHIP:
switch (ldo) {
case SET_LDO_VOLTAGE_PAREF:
addr = 0;
rc_shift = 29;
mask = 0x7;
do_reg2 = 1;
addr2 = 1;
rshift2 = 3;
mask2 = 0x8;
break;
default:
ASSERT(FALSE);
break;
}
break;
default:
ASSERT(FALSE);
return;
}
shift = sr_cntl_shift + rc_shift;
pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, /* PMU VREG register */
~0, addr);
pmu_corereg(sih, SI_CC_IDX, regcontrol_data,
mask << shift, (voltage & mask) << shift);
if (do_reg2) {
/* rshift2 - right shift moves mask2 to bit 0, rc_shift2 - left shift in reg */
si_pmu_vreg_control(sih, addr2, (mask2 >> rshift2) << rc_shift2,
((voltage & mask2) >> rshift2) << rc_shift2);
}
} /* si_pmu_set_ldo_voltage */
/* d11 slow to fast clock transition time in slow clock cycles */
#define D11SCC_SLOW2FAST_TRANSITION 2
/* For legacy chips only, will be discarded eventually */
static uint16
si_pmu_fast_pwrup_delay_legacy(si_t *sih, osl_t *osh, pmuregs_t *pmu)
{
uint pmudelay = PMU_MAX_TRANSITION_DLY;
uint32 ilp; /* ILP clock frequency in [Hz] */
rsc_per_chip_t *rsc; /* chip specific resource bit positions */
/* Should be calculated based on the PMU updown/depend tables */
switch (CHIPID(sih->chip)) {
case BCM43460_CHIP_ID:
case BCM43526_CHIP_ID:
pmudelay = 3700;
break;
case BCM4360_CHIP_ID:
case BCM4352_CHIP_ID:
if (CHIPREV(sih->chiprev) < 4) {
pmudelay = 1500;
} else {
pmudelay = 3000;
}
break;
case BCM43012_CHIP_ID:
case BCM43013_CHIP_ID:
case BCM43014_CHIP_ID:
pmudelay = 1500; /* In micro seconds for 43012 chip */
break;
CASE_BCM43602_CHIP:
rsc = si_pmu_get_rsc_positions(sih);
/* Retrieve time by reading it out of the hardware */
ilp = si_ilp_clock(sih);
if (ilp != 0) {
pmudelay = (si_pmu_res_uptime(sih, osh, pmu, rsc->macphy_clkavail, FALSE) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 1) / ilp);
pmudelay = (11 * pmudelay) / 10;
}
break;
case BCM4362_CHIP_GRPID:
rsc = si_pmu_get_rsc_positions(sih);
/* Retrieve time by reading it out of the hardware */
ilp = si_ilp_clock(sih);
if (ilp != 0) {
pmudelay = si_pmu_res_uptime(sih, osh, pmu, rsc->ht_avail, FALSE) +
D11SCC_SLOW2FAST_TRANSITION;
pmudelay = (11 * pmudelay) / 10;
/* With PWR SW optimization, Need to add this addtional
time to fast power up delay to avoid beacon loss
*/
pmudelay += 600;
}
break;
default:
break;
}
return (uint16)pmudelay;
} /* si_pmu_fast_pwrup_delay_legacy */
/**
* d11 core has a 'fastpwrup_dly' register that must be written to.
* This function returns d11 slow to fast clock transition time in [us] units.
* It does not write to the d11 core.
*/
uint16
si_pmu_fast_pwrup_delay(si_t *sih, osl_t *osh)
{
uint pmudelay = PMU_MAX_TRANSITION_DLY;
pmuregs_t *pmu;
uint origidx;
rsc_per_chip_t *rsc; /* chip specific resource bit positions */
uint macunit;
bool pmu_fast_trans_en;
ASSERT(sih->cccaps & CC_CAP_PMU);
if (ISSIM_ENAB(sih)) {
pmudelay = 1000;
goto exit;
}
macunit = si_coreunit(sih);
origidx = si_coreidx(sih);
/* Still support 43602 so need AOB check,
* 43602 is the only non-AOB chip supported now
*/
if (AOB_ENAB(sih)) {
pmu = si_setcore(sih, PMU_CORE_ID, 0);
} else {
pmu = si_setcoreidx(sih, SI_CC_IDX);
}
ASSERT(pmu != NULL);
pmu_fast_trans_en = (R_REG(osh, &pmu->pmucontrol_ext) & PCTL_EXT_FAST_TRANS_ENAB) ?
TRUE : FALSE;
rsc = si_pmu_get_rsc_positions(sih);
switch (CHIPID(sih->chip)) {
case BCM4369_CHIP_GRPID:
case BCM4376_CHIP_GRPID:
case BCM4378_CHIP_GRPID:
case BCM4385_CHIP_GRPID:
if (macunit == 0) {
pmudelay = si_pmu_res_uptime(sih, osh, pmu,
rsc->macphy_clkavail, pmu_fast_trans_en);
} else if (macunit == 1) {
pmudelay = si_pmu_res_uptime(sih, osh, pmu,
rsc->macphy_aux_clkavail, pmu_fast_trans_en);
} else {
ASSERT(0);
}
break;
case BCM4387_CHIP_GRPID:
case BCM4388_CHIP_GRPID:
case BCM4389_CHIP_GRPID:
case BCM4397_CHIP_GRPID:
if (macunit == 0) {
pmudelay = si_pmu_res_uptime(sih, osh, pmu,
rsc->macphy_clkavail, pmu_fast_trans_en);
} else if (macunit == 1) {
pmudelay = si_pmu_res_uptime(sih, osh, pmu,
rsc->macphy_aux_clkavail, pmu_fast_trans_en);
} else if (macunit == 2) {
pmudelay = si_pmu_res_uptime(sih, osh, pmu,
rsc->macphy_scan_clkavail, pmu_fast_trans_en);
} else {
ASSERT(0);
}
break;
default:
pmudelay = si_pmu_fast_pwrup_delay_legacy(sih, osh, pmu);
break;
}
/* Return to original core */
si_setcoreidx(sih, origidx);
exit:
return (uint16)pmudelay;
} /* si_pmu_fast_pwrup_delay */
/*
* Get fast pwrup delay for given resource
*/
static uint
si_pmu_fast_pwrup_delay_rsrc(si_t *sih, osl_t *osh, uint8 rsrc)
{
uint pmudelay = PMU_MAX_TRANSITION_DLY;
pmuregs_t *pmu = NULL;
bool pmu_fast_trans_en = TRUE;
uint origidx;
origidx = si_coreidx(sih);
pmu = si_setcore(sih, PMU_CORE_ID, 0);
ASSERT(pmu != NULL);
pmu_fast_trans_en = (R_REG(osh, &pmu->pmucontrol_ext) & PCTL_EXT_FAST_TRANS_ENAB) ?
TRUE : FALSE;
pmudelay = si_pmu_res_uptime(sih, osh, pmu, rsrc, pmu_fast_trans_en);
/* Return to original core */
si_setcoreidx(sih, origidx);
return pmudelay;
}
/*
* Get fast pwrup delay for given DIG_READY resource
*/
uint
si_pmu_fast_pwrup_delay_dig(si_t *sih, osl_t *osh)
{
uint delay = 0;
rsc_per_chip_t *rsc = si_pmu_get_rsc_positions(sih);
ASSERT(rsc);
if (rsc) {
delay = si_pmu_fast_pwrup_delay_rsrc(sih, osh, rsc->dig_ready);
}
return delay;
}
/*
* During chip bringup, it can turn out that the 'hard wired' PMU dependencies are not fully
* correct, or that up/down time values can be optimized. The following data structures and arrays
* deal with that.
*/
/* Setup resource up/down timers */
typedef struct {
uint8 resnum;
uint32 updown;
} pmu_res_updown_t;
#define PMU_RES_SUBSTATE_SHIFT 8
/* Setup resource substate transition timer value */
typedef struct {
uint8 resnum;
uint8 substate;
uint32 tmr;
} pmu_res_subst_trans_tmr_t;
/* Change resource dependencies masks */
typedef struct {
uint32 res_mask; /* resources (chip specific) */
int8 action; /* action, e.g. RES_DEPEND_SET */
uint32 depend_mask; /* changes to the dependencies mask */
bool (*filter)(si_t *sih); /* action is taken when filter is NULL or return TRUE */
} pmu_res_depend_t;
/* Resource dependencies mask change action */
#define RES_DEPEND_SET 0 /* Override the dependencies mask */
#define RES_DEPEND_ADD 1 /* Add to the dependencies mask */
#define RES_DEPEND_REMOVE -1 /* Remove from the dependencies mask */
/* Using a safe SAVE_RESTORE up/down time, it will get updated after openloop cal */
static const pmu_res_updown_t bcm43012a0_res_updown_ds0[] = {
{RES43012_MEMLPLDO_PU, 0x00200020},
{RES43012_PMU_SLEEP, 0x00a600a6},
{RES43012_FAST_LPO, 0x00D20000},
{RES43012_BTLPO_3P3, 0x007D0000},
{RES43012_SR_POK, 0x00c80000},
{RES43012_DUMMY_PWRSW, 0x01400000},
{RES43012_DUMMY_LDO3P3, 0x00000000},
{RES43012_DUMMY_BT_LDO3P3, 0x00000000},
{RES43012_DUMMY_RADIO, 0x00000000},
{RES43012_VDDB_VDDRET, 0x0020000a},
{RES43012_HV_LDO3P3, 0x002C0000},
{RES43012_XTAL_PU, 0x04000000},
{RES43012_SR_CLK_START, 0x00080000},
{RES43012_XTAL_STABLE, 0x00000000},
{RES43012_FCBS, 0x00000000},
{RES43012_CBUCK_MODE, 0x00000000},
{RES43012_CORE_READY, 0x00000000},
{RES43012_ILP_REQ, 0x00000000},
{RES43012_ALP_AVAIL, 0x00280008},
{RES43012_RADIOLDO_1P8, 0x00220000},
{RES43012_MINI_PMU, 0x00220000},
{RES43012_SR_SAVE_RESTORE, 0x02600260},
{RES43012_PHY_PWRSW, 0x00800005},
{RES43012_VDDB_CLDO, 0x0020000a},
{RES43012_SUBCORE_PWRSW, 0x0060000a},
{RES43012_SR_SLEEP, 0x00000000},
{RES43012_HT_START, 0x00A00000},
{RES43012_HT_AVAIL, 0x00000000},
{RES43012_MACPHY_CLK_AVAIL, 0x00000000},
};
static const pmu_res_updown_t bcm4360_res_updown[] = {
{RES4360_BBPLLPWRSW_PU, 0x00200001}
};
static const pmu_res_updown_t bcm43602_res_updown[] = {
{RES43602_SR_SAVE_RESTORE, 0x00190019},
{RES43602_XTAL_PU, 0x00280002},
{RES43602_RFLDO_PU, 0x00430005}
};
static pmu_res_depend_t bcm43012a0_res_depend_ds0[] = {
{0, 0, 0, NULL}
};
static pmu_res_depend_t bcm43602_res_depend[] = {
/* JIRA HW43602-131 : PCIe SERDES dependency problem */
{
PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_SR_CLK_STABLE) |
PMURES_BIT(RES43602_SR_SAVE_RESTORE) | PMURES_BIT(RES43602_SR_SLEEP) |
PMURES_BIT(RES43602_LQ_START) | PMURES_BIT(RES43602_LQ_AVAIL) |
PMURES_BIT(RES43602_WL_CORE_RDY) | PMURES_BIT(RES43602_ILP_REQ) |
PMURES_BIT(RES43602_ALP_AVAIL) | PMURES_BIT(RES43602_RFLDO_PU) |
PMURES_BIT(RES43602_HT_START) | PMURES_BIT(RES43602_HT_AVAIL) |
PMURES_BIT(RES43602_MACPHY_CLKAVAIL),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_SERDES_PU),
NULL
},
/* set rsrc 7, 8, 9, 12, 13, 14 & 17 add (1<<10 | 1<<4 )] */
{
PMURES_BIT(RES43602_SR_CLK_START) | PMURES_BIT(RES43602_SR_PHY_PWRSW) |
PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_SR_CLK_STABLE) |
PMURES_BIT(RES43602_SR_SAVE_RESTORE) | PMURES_BIT(RES43602_SR_SLEEP) |
PMURES_BIT(RES43602_WL_CORE_RDY),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_XTALLDO_PU) | PMURES_BIT(RES43602_XTAL_PU),
NULL
},
/* set rsrc 11 add (1<<13 | 1<<12 | 1<<9 | 1<<8 | 1<<7 )] */
{
PMURES_BIT(RES43602_PERST_OVR),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_SR_CLK_START) | PMURES_BIT(RES43602_SR_PHY_PWRSW) |
PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_SR_CLK_STABLE) |
PMURES_BIT(RES43602_SR_SAVE_RESTORE),
NULL
},
/* set rsrc 19, 21, 22, 23 & 24 remove ~(1<<16 | 1<<15 )] */
{
PMURES_BIT(RES43602_ALP_AVAIL) | PMURES_BIT(RES43602_RFLDO_PU) |
PMURES_BIT(RES43602_HT_START) | PMURES_BIT(RES43602_HT_AVAIL) |
PMURES_BIT(RES43602_MACPHY_CLKAVAIL),
RES_DEPEND_REMOVE,
PMURES_BIT(RES43602_LQ_START) | PMURES_BIT(RES43602_LQ_AVAIL),
NULL
}
};
#ifndef BCM_BOOTLOADER
/** switch off LPLDO for 12x12 package because it can cause a problem when chip is reset */
static const pmu_res_depend_t bcm43602_12x12_res_depend[] = {
/* set rsrc 19, 21, 22, 23 & 24 remove ~(1<<16 | 1<<15 )] */
{ /* resources no longer dependent on resource that is going to be removed */
PMURES_BIT(RES43602_LPLDO_PU) | PMURES_BIT(RES43602_REGULATOR) |
PMURES_BIT(RES43602_PMU_SLEEP) | PMURES_BIT(RES43602_RSVD_3) |
PMURES_BIT(RES43602_XTALLDO_PU) | PMURES_BIT(RES43602_SERDES_PU) |
PMURES_BIT(RES43602_BBPLL_PWRSW_PU) | PMURES_BIT(RES43602_SR_CLK_START) |
PMURES_BIT(RES43602_SR_PHY_PWRSW) | PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) |
PMURES_BIT(RES43602_XTAL_PU) | PMURES_BIT(RES43602_PERST_OVR) |
PMURES_BIT(RES43602_SR_CLK_STABLE) | PMURES_BIT(RES43602_SR_SAVE_RESTORE) |
PMURES_BIT(RES43602_SR_SLEEP) | PMURES_BIT(RES43602_LQ_START) |
PMURES_BIT(RES43602_LQ_AVAIL) | PMURES_BIT(RES43602_WL_CORE_RDY) |
PMURES_BIT(RES43602_ILP_REQ) | PMURES_BIT(RES43602_ALP_AVAIL) |
PMURES_BIT(RES43602_RADIO_PU) | PMURES_BIT(RES43602_RFLDO_PU) |
PMURES_BIT(RES43602_HT_START) | PMURES_BIT(RES43602_HT_AVAIL) |
PMURES_BIT(RES43602_MACPHY_CLKAVAIL) | PMURES_BIT(RES43602_PARLDO_PU) |
PMURES_BIT(RES43602_RSVD_26),
RES_DEPEND_REMOVE,
/* resource that is going to be removed */
PMURES_BIT(RES43602_LPLDO_PU),
NULL
}
};
static const pmu_res_depend_t bcm43602_res_pciewar[] = {
{
PMURES_BIT(RES43602_PERST_OVR),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_REGULATOR) |
PMURES_BIT(RES43602_PMU_SLEEP) |
PMURES_BIT(RES43602_XTALLDO_PU) |
PMURES_BIT(RES43602_XTAL_PU) |
PMURES_BIT(RES43602_RADIO_PU),
NULL
},
{
PMURES_BIT(RES43602_WL_CORE_RDY),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
},
{
PMURES_BIT(RES43602_LQ_START),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
},
{
PMURES_BIT(RES43602_LQ_AVAIL),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
},
{
PMURES_BIT(RES43602_ALP_AVAIL),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
},
{
PMURES_BIT(RES43602_HT_START),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
},
{
PMURES_BIT(RES43602_HT_AVAIL),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
},
{
PMURES_BIT(RES43602_MACPHY_CLKAVAIL),
RES_DEPEND_ADD,
PMURES_BIT(RES43602_PERST_OVR),
NULL
}
};
#endif /* BCM_BOOTLOADER */
static const pmu_res_updown_t bcm4360B1_res_updown[] = {
/* Need to change elements here, should get default values for this - 4360B1 */
{RES4360_XTAL_PU, 0x00430002}, /* Changed for 4360B1 */
};
static pmu_res_depend_t bcm4369a0_res_depend[] = {
{PMURES_BIT(RES4369_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
{PMURES_BIT(RES4369_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
{PMURES_BIT(RES4369_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
{PMURES_BIT(RES4369_MISCLDO), RES_DEPEND_SET, 0x00000007, NULL},
{PMURES_BIT(RES4369_LDO3P3), RES_DEPEND_SET, 0x00000001, NULL},
{PMURES_BIT(RES4369_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
{PMURES_BIT(RES4369_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
{PMURES_BIT(RES4369_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
{PMURES_BIT(RES4369_PWRSW_DIG), RES_DEPEND_SET, 0x060000cf, NULL},
{PMURES_BIT(RES4369_SR_DIG), RES_DEPEND_SET, 0x060001cf, NULL},
{PMURES_BIT(RES4369_SLEEP_DIG), RES_DEPEND_SET, 0x060003cf, NULL},
{PMURES_BIT(RES4369_PWRSW_AUX), RES_DEPEND_SET, 0x040000cf, NULL},
{PMURES_BIT(RES4369_SR_AUX), RES_DEPEND_SET, 0x040008cf, NULL},
{PMURES_BIT(RES4369_SLEEP_AUX), RES_DEPEND_SET, 0x040018cf, NULL},
{PMURES_BIT(RES4369_PWRSW_MAIN), RES_DEPEND_SET, 0x040000cf, NULL},
{PMURES_BIT(RES4369_SR_MAIN), RES_DEPEND_SET, 0x040040cf, NULL},
{PMURES_BIT(RES4369_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0cf, NULL},
{PMURES_BIT(RES4369_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007cf, NULL},
{PMURES_BIT(RES4369_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038cf, NULL},
{PMURES_BIT(RES4369_ALP_AVAIL), RES_DEPEND_SET, 0x060207cf, NULL},
{PMURES_BIT(RES4369_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438df, NULL},
{PMURES_BIT(RES4369_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438df, NULL},
{PMURES_BIT(RES4369_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0cf, NULL},
{PMURES_BIT(RES4369_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0df, NULL},
{PMURES_BIT(RES4369_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0df, NULL},
{PMURES_BIT(RES4369_PCIE_EP_PU), RES_DEPEND_SET, 0x040000cf, NULL},