From 2755d877cfec8f4f1dedc42b8f185ea0e6a8a55f Mon Sep 17 00:00:00 2001 From: qarlosalberto Date: Mon, 16 Jan 2023 19:07:41 +0100 Subject: [PATCH] Add tools installation path to osvvm and fix test templates --- src/config/config_declaration.ts | 48 ++++++++++- src/config/config_web.ts | 86 ++++++++++++++++++- .../helpers/configs/tools/activehdl.yml | 4 + src/config/helpers/configs/tools/nvc.yml | 4 + src/config/helpers/configs/tools/osvvm.yml | 2 +- src/config/helpers/configs/tools/questa.yml | 4 + src/config/helpers/skeleton.yml | 15 ++++ src/config/web_config.html | 86 ++++++++++++++++++- src/project_manager/tool/osvvm/osvvm.ts | 11 ++- src/project_manager/tool/vunit/vunit.ts | 18 ++-- .../helpers/verilog/testbench_normal.nj | 6 +- .../helpers/verilog/testbench_vunit.nj | 6 +- .../helpers/vhdl/hdl_element_signal.nj | 6 +- src/template/helpers/vhdl/testbench_normal.nj | 8 +- src/template/helpers/vhdl/testbench_vunit.nj | 8 +- src/template/manager.ts | 25 ++++++ tests/{TODO => TODO.md} | 78 +++++++++++------ .../vhdl_hdl_element_signal.vhdl | 12 +-- .../vhdl_testbench_normal.vhdl | 12 +-- .../vhdl_testbench_vunit.vhdl | 12 +-- tests/template/template.spec.ts | 11 +-- 21 files changed, 378 insertions(+), 84 deletions(-) create mode 100644 src/config/helpers/configs/tools/activehdl.yml create mode 100644 src/config/helpers/configs/tools/nvc.yml create mode 100644 src/config/helpers/configs/tools/questa.yml rename tests/{TODO => TODO.md} (88%) diff --git a/src/config/config_declaration.ts b/src/config/config_declaration.ts index cba5f2e9..742af631 100644 --- a/src/config/config_declaration.ts +++ b/src/config/config_declaration.ts @@ -81,6 +81,9 @@ export type e_config = { "xsim" : e_tools_xsim, "yosys" : e_tools_yosys, "openfpga" : e_tools_openfpga, + "activehdl" : e_tools_activehdl, + "nvc" : e_tools_nvc, + "questa" : e_tools_questa, } }; export type e_general_general = { @@ -428,6 +431,18 @@ export type e_tools_openfpga = { yosys_synth_options : any[], }; +export type e_tools_activehdl = { + installation_path : string, +}; + +export type e_tools_nvc = { + installation_path : string, +}; + +export type e_tools_questa = { + installation_path : string, +}; + export enum e_documentation_general_language { english = "english", russian = "russian", @@ -590,7 +605,7 @@ export enum e_tools_osvvm_simulator_name { activehdl = "activehdl", ghdl = "ghdl", nvc = "nvc", - riviera = "riviera", + rivierapro = "rivierapro", questa = "questa", modelsim = "modelsim", vcs = "vcs", @@ -1007,6 +1022,15 @@ export function get_default_config(): e_config { script_name : "", yosys_synth_options : [], }, + activehdl: { + installation_path : "", + }, + nvc: { + installation_path : "", + }, + questa: { + installation_path : "", + }, }, }; } @@ -1647,8 +1671,8 @@ export function get_config_from_json(json_config: any): e_config { if ( current_value_68 === "nvc"){ default_config['tools']['osvvm']['simulator_name'] = e_tools_osvvm_simulator_name.nvc; } - if ( current_value_68 === "riviera"){ - default_config['tools']['osvvm']['simulator_name'] = e_tools_osvvm_simulator_name.riviera; + if ( current_value_68 === "rivierapro"){ + default_config['tools']['osvvm']['simulator_name'] = e_tools_osvvm_simulator_name.rivierapro; } if ( current_value_68 === "questa"){ default_config['tools']['osvvm']['simulator_name'] = e_tools_osvvm_simulator_name.questa; @@ -2581,6 +2605,24 @@ export function get_config_from_json(json_config: any): e_config { default_config['tools']['openfpga']['yosys_synth_options'] = current_value_200; } + // tools -> activehdl -> installation_path + const current_value_201 = json_config['tools']['activehdl']['installation_path']; + if (typeof current_value_201 === 'string'){ + default_config['tools']['activehdl']['installation_path'] = current_value_201; + } + + // tools -> nvc -> installation_path + const current_value_202 = json_config['tools']['nvc']['installation_path']; + if (typeof current_value_202 === 'string'){ + default_config['tools']['nvc']['installation_path'] = current_value_202; + } + + // tools -> questa -> installation_path + const current_value_203 = json_config['tools']['questa']['installation_path']; + if (typeof current_value_203 === 'string'){ + default_config['tools']['questa']['installation_path'] = current_value_203; + } + return default_config; } \ No newline at end of file diff --git a/src/config/config_web.ts b/src/config/config_web.ts index 34724781..63ce57f5 100644 --- a/src/config/config_web.ts +++ b/src/config/config_web.ts @@ -359,6 +359,9 @@ input[type='input'] { XSIM Yosys OpenFPGA + Active-HDL + NVC + Questa Advanced Simulator @@ -936,7 +939,7 @@ input[type='input'] { - + @@ -1745,6 +1748,45 @@ input[type='input'] {

+
+

Tools: Active-HDL

+
+

Active-HDL™ is a Windows based, integrated FPGA Design Creation and Simulation solution for team-based environments.

+ +
+ +

+ +

+ +

+
+
+

Tools: NVC

+
+

NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2002 and it has been successfully used to simulate several real-world designs.

+ +
+ +

+ +

+ +

+
+
+

Tools: Questa Advanced Simulator

+
+

The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution.

+ +
+ +

+ +

+ +

+
@@ -2048,6 +2090,24 @@ input[type='input'] { else{ document.getElementById("tools-openfpga").style.visibility = "hidden"; } + if ("tools" == tp0 && "activehdl" == tp1){ + document.getElementById("tools-activehdl").style.visibility = "visible"; + } + else{ + document.getElementById("tools-activehdl").style.visibility = "hidden"; + } + if ("tools" == tp0 && "nvc" == tp1){ + document.getElementById("tools-nvc").style.visibility = "visible"; + } + else{ + document.getElementById("tools-nvc").style.visibility = "hidden"; + } + if ("tools" == tp0 && "questa" == tp1){ + document.getElementById("tools-questa").style.visibility = "visible"; + } + else{ + document.getElementById("tools-questa").style.visibility = "hidden"; + } } enable_tab('general', 'general'); @@ -2244,6 +2304,18 @@ input[type='input'] { enable_tab("tools","openfpga") }); + document.getElementById("btn-tools-activehdl").addEventListener("click", function() { + enable_tab("tools","activehdl") + }); + + document.getElementById("btn-tools-nvc").addEventListener("click", function() { + enable_tab("tools","nvc") + }); + + document.getElementById("btn-tools-questa").addEventListener("click", function() { + enable_tab("tools","questa") + }); + /* Loop through all dropdown buttons to toggle between hiding and showing its dropdown content - This allows the user to have multiple dropdowns without any conflict */ var dropdown = document.getElementsByClassName("dropdown-btn"); @@ -2769,6 +2841,15 @@ input[type='input'] { config["tools"]["openfpga"]["script_name"] = element_value element_value = document.getElementById("tools-openfpga-yosys_synth_options").value.split(','); config["tools"]["openfpga"]["yosys_synth_options"] = element_value + config["tools"]["activehdl"] = {} + element_value = document.getElementById("tools-activehdl-installation_path").value; + config["tools"]["activehdl"]["installation_path"] = element_value + config["tools"]["nvc"] = {} + element_value = document.getElementById("tools-nvc-installation_path").value; + config["tools"]["nvc"]["installation_path"] = element_value + config["tools"]["questa"] = {} + element_value = document.getElementById("tools-questa-installation_path").value; + config["tools"]["questa"]["installation_path"] = element_value return config; } @@ -2974,6 +3055,9 @@ input[type='input'] { document.getElementById("tools-openfpga-makefile_name").value = config["tools"]["openfpga"]["makefile_name"]; document.getElementById("tools-openfpga-script_name").value = config["tools"]["openfpga"]["script_name"]; element_value = document.getElementById("tools-openfpga-yosys_synth_options").value = String(config["tools"]["openfpga"]["yosys_synth_options"]); + document.getElementById("tools-activehdl-installation_path").value = config["tools"]["activehdl"]["installation_path"]; + document.getElementById("tools-nvc-installation_path").value = config["tools"]["nvc"]["installation_path"]; + document.getElementById("tools-questa-installation_path").value = config["tools"]["questa"]["installation_path"]; } function open_submenu_icon(x) { diff --git a/src/config/helpers/configs/tools/activehdl.yml b/src/config/helpers/configs/tools/activehdl.yml new file mode 100644 index 00000000..e3f7edb6 --- /dev/null +++ b/src/config/helpers/configs/tools/activehdl.yml @@ -0,0 +1,4 @@ +installation_path: + description: "Installation path:" + type: string + value: "" diff --git a/src/config/helpers/configs/tools/nvc.yml b/src/config/helpers/configs/tools/nvc.yml new file mode 100644 index 00000000..e3f7edb6 --- /dev/null +++ b/src/config/helpers/configs/tools/nvc.yml @@ -0,0 +1,4 @@ +installation_path: + description: "Installation path:" + type: string + value: "" diff --git a/src/config/helpers/configs/tools/osvvm.yml b/src/config/helpers/configs/tools/osvvm.yml index 05f201c5..6df3a0e6 100644 --- a/src/config/helpers/configs/tools/osvvm.yml +++ b/src/config/helpers/configs/tools/osvvm.yml @@ -15,7 +15,7 @@ simulator_name: activehdl: "Aldec Active-HDL" ghdl: "GHDL" nvc: "NVC" - riviera: "Aldec Riviera-PRO" + rivierapro: "Aldec Riviera-PRO" questa: "Mentor/Siemens EDA Questa" modelsim: "Mentor/Siemens EDA ModelSim" vcs: "VCS" diff --git a/src/config/helpers/configs/tools/questa.yml b/src/config/helpers/configs/tools/questa.yml new file mode 100644 index 00000000..e3f7edb6 --- /dev/null +++ b/src/config/helpers/configs/tools/questa.yml @@ -0,0 +1,4 @@ +installation_path: + description: "Installation path:" + type: string + value: "" diff --git a/src/config/helpers/skeleton.yml b/src/config/helpers/skeleton.yml index c6e47406..0a6f1d98 100644 --- a/src/config/helpers/skeleton.yml +++ b/src/config/helpers/skeleton.yml @@ -255,3 +255,18 @@ tools: title: OpenFPGA description: "The award-winning OpenFPGA framework is the first open-source FPGA IP generator with silicon proofs supporting highly-customizable FPGA architectures." page: ./configs/tools/yosys.yml + + activehdl: + title: Active-HDL + description: "Active-HDL™ is a Windows based, integrated FPGA Design Creation and Simulation solution for team-based environments." + page: ./configs/tools/activehdl.yml + + nvc: + title: NVC + description: "NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2002 and it has been successfully used to simulate several real-world designs." + page: ./configs/tools/nvc.yml + + questa: + title: Questa Advanced Simulator + description: "The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution." + page: ./configs/tools/questa.yml diff --git a/src/config/web_config.html b/src/config/web_config.html index 447ca0f2..081fb8bf 100644 --- a/src/config/web_config.html +++ b/src/config/web_config.html @@ -339,6 +339,9 @@ XSIM Yosys OpenFPGA + Active-HDL + NVC + Questa Advanced Simulator @@ -916,7 +919,7 @@

Tools: OSVVM

- + @@ -1725,6 +1728,45 @@

Tools: OpenFPGA



+
+

Tools: Active-HDL

+
+

Active-HDL™ is a Windows based, integrated FPGA Design Creation and Simulation solution for team-based environments.

+ +
+ +

+ +

+ +

+
+
+

Tools: NVC

+
+

NVC is a VHDL compiler and simulator. NVC supports almost all of VHDL-2002 and it has been successfully used to simulate several real-world designs.

+ +
+ +

+ +

+ +

+
+
+

Tools: Questa Advanced Simulator

+
+

The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution.

+ +
+ +

+ +

+ +

+
@@ -2028,6 +2070,24 @@

Tools: OpenFPGA

else{ document.getElementById("tools-openfpga").style.visibility = "hidden"; } + if ("tools" == tp0 && "activehdl" == tp1){ + document.getElementById("tools-activehdl").style.visibility = "visible"; + } + else{ + document.getElementById("tools-activehdl").style.visibility = "hidden"; + } + if ("tools" == tp0 && "nvc" == tp1){ + document.getElementById("tools-nvc").style.visibility = "visible"; + } + else{ + document.getElementById("tools-nvc").style.visibility = "hidden"; + } + if ("tools" == tp0 && "questa" == tp1){ + document.getElementById("tools-questa").style.visibility = "visible"; + } + else{ + document.getElementById("tools-questa").style.visibility = "hidden"; + } } enable_tab('general', 'general'); @@ -2224,6 +2284,18 @@

Tools: OpenFPGA

enable_tab("tools","openfpga") }); + document.getElementById("btn-tools-activehdl").addEventListener("click", function() { + enable_tab("tools","activehdl") + }); + + document.getElementById("btn-tools-nvc").addEventListener("click", function() { + enable_tab("tools","nvc") + }); + + document.getElementById("btn-tools-questa").addEventListener("click", function() { + enable_tab("tools","questa") + }); + /* Loop through all dropdown buttons to toggle between hiding and showing its dropdown content - This allows the user to have multiple dropdowns without any conflict */ var dropdown = document.getElementsByClassName("dropdown-btn"); @@ -2749,6 +2821,15 @@

Tools: OpenFPGA

config["tools"]["openfpga"]["script_name"] = element_value element_value = document.getElementById("tools-openfpga-yosys_synth_options").value.split(','); config["tools"]["openfpga"]["yosys_synth_options"] = element_value + config["tools"]["activehdl"] = {} + element_value = document.getElementById("tools-activehdl-installation_path").value; + config["tools"]["activehdl"]["installation_path"] = element_value + config["tools"]["nvc"] = {} + element_value = document.getElementById("tools-nvc-installation_path").value; + config["tools"]["nvc"]["installation_path"] = element_value + config["tools"]["questa"] = {} + element_value = document.getElementById("tools-questa-installation_path").value; + config["tools"]["questa"]["installation_path"] = element_value return config; } @@ -2954,6 +3035,9 @@

Tools: OpenFPGA

document.getElementById("tools-openfpga-makefile_name").value = config["tools"]["openfpga"]["makefile_name"]; document.getElementById("tools-openfpga-script_name").value = config["tools"]["openfpga"]["script_name"]; element_value = document.getElementById("tools-openfpga-yosys_synth_options").value = String(config["tools"]["openfpga"]["yosys_synth_options"]); + document.getElementById("tools-activehdl-installation_path").value = config["tools"]["activehdl"]["installation_path"]; + document.getElementById("tools-nvc-installation_path").value = config["tools"]["nvc"]["installation_path"]; + document.getElementById("tools-questa-installation_path").value = config["tools"]["questa"]["installation_path"]; } function open_submenu_icon(x) { diff --git a/src/project_manager/tool/osvvm/osvvm.ts b/src/project_manager/tool/osvvm/osvvm.ts index 50409728..2b27b5b2 100644 --- a/src/project_manager/tool/osvvm/osvvm.ts +++ b/src/project_manager/tool/osvvm/osvvm.ts @@ -248,7 +248,6 @@ exit callback_stream(exec_i); } - get_test_result(working_folder: string, project_name: string, toplevel: string): t_yaml_result[] { const result_path = path_lib.join(working_folder, `${project_name}.yml`); const result: t_yaml_result[] = []; @@ -312,4 +311,14 @@ exit return result; } + get_simulator_installation_path(prj: t_project_definition): string { + const config = prj.config_manager.get_config(); + const simulator_name = prj.config_manager.get_config().tools.osvvm.simulator_name; + + let installation_path = ""; + try { + installation_path = (config.tools)[simulator_name].installation_path; + } catch (error) { /* empty */ } + return installation_path; + } } \ No newline at end of file diff --git a/src/project_manager/tool/vunit/vunit.ts b/src/project_manager/tool/vunit/vunit.ts index 125685b4..37dbc2d3 100644 --- a/src/project_manager/tool/vunit/vunit.ts +++ b/src/project_manager/tool/vunit/vunit.ts @@ -175,18 +175,14 @@ export class Vunit extends Generic_tool_handler { return exec_i; } - get_simulator_installation_path(_prj: t_project_definition): string { - // const config = prj.config_manager.get_config(); - // const simulator_name = config.tools.vunit.simulator_name; - // const tools = config.tools; - const installation_path = ""; - - // Object.entries(tools).forEach(([key, value]) => { - // if ((installation_path in value) && key === simulator_name) { - // installation_path = value.installation_path; - // } - // }); + get_simulator_installation_path(prj: t_project_definition): string { + const config = prj.config_manager.get_config(); + const simulator_name = prj.config_manager.get_config().tools.vunit.simulator_name; + let installation_path = ""; + try { + installation_path = (config.tools)[simulator_name].installation_path; + } catch (error) { /* empty */ } return installation_path; } diff --git a/src/template/helpers/verilog/testbench_normal.nj b/src/template/helpers/verilog/testbench_normal.nj index 616a6ee4..30880dba 100644 --- a/src/template/helpers/verilog/testbench_normal.nj +++ b/src/template/helpers/verilog/testbench_normal.nj @@ -3,11 +3,7 @@ module {{ name }}_tb; {{ indent[1] }}// Parameters {% for generic_inst in generic -%} -{% if generic_inst['default_value'] == "" -%} -{{ indent[1] }}localparam {{generic_inst['type']}} {{generic_inst['info']['name']}}; -{% else -%} -{{ indent[1] }}localparam {{generic_inst['type']}} {{generic_inst['info']['name']}} = {{generic_inst['default_value']}}; -{% endif -%} +{{ indent[1] }}localparam {{generic_inst['type']}} {{generic_inst['info']['name']}} = 0; {% endfor %} {{ indent[1] }}//Ports {% for port_inst in port -%} diff --git a/src/template/helpers/verilog/testbench_vunit.nj b/src/template/helpers/verilog/testbench_vunit.nj index 2803fed3..c800d738 100644 --- a/src/template/helpers/verilog/testbench_vunit.nj +++ b/src/template/helpers/verilog/testbench_vunit.nj @@ -5,11 +5,7 @@ module {{ name }}_tb; {{ indent[1] }}// Parameters {% for generic_inst in generic -%} -{% if generic_inst['default_value'] == "" -%} -{{ indent[1] }}localparam {{generic_inst['type']}} {{generic_inst['info']['name']}}; -{% else -%} -{{ indent[1] }}localparam {{generic_inst['type']}} {{generic_inst['info']['name']}} = {{generic_inst['default_value']}}; -{% endif -%} +{{ indent[1] }}localparam {{generic_inst['type']}} {{generic_inst['info']['name']}} = 0; {% endfor %} {{ indent[1] }}//Ports {% for port_inst in port -%} diff --git a/src/template/helpers/vhdl/hdl_element_signal.nj b/src/template/helpers/vhdl/hdl_element_signal.nj index e76bb233..09e1361a 100644 --- a/src/template/helpers/vhdl/hdl_element_signal.nj +++ b/src/template/helpers/vhdl/hdl_element_signal.nj @@ -1,5 +1,9 @@ {% for element in generic -%} -{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}} := {{element['default_value']}}; +{% if element['default_value'] != "" -%} +{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}} := {{element['default_value']|safe}}; +{% else -%} +{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}}; +{% endif -%} {% endfor -%} {% for element in port -%} diff --git a/src/template/helpers/vhdl/testbench_normal.nj b/src/template/helpers/vhdl/testbench_normal.nj index 4a387d21..3f1ba4e0 100644 --- a/src/template/helpers/vhdl/testbench_normal.nj +++ b/src/template/helpers/vhdl/testbench_normal.nj @@ -10,8 +10,12 @@ architecture bench of {{ name }}_tb is {{ indent[1] }}-- Clock period {{ indent[1] }}constant clk_period : time := 5 ns; {{ indent[1] }}-- Generics -{% for generic_inst in generic -%} -{{ indent[1] }}constant {{generic_inst['info']['name']}} : {{generic_inst['type']}}; +{% for element in generic -%} +{% if element['default_value'] != "" -%} +{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}} := {{element['default_value']|safe}}; +{% else -%} +{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}}; +{% endif -%} {% endfor -%} {{ indent[1] }}-- Ports {% for port_inst in port -%} diff --git a/src/template/helpers/vhdl/testbench_vunit.nj b/src/template/helpers/vhdl/testbench_vunit.nj index 995ad031..1b3f3ac4 100644 --- a/src/template/helpers/vhdl/testbench_vunit.nj +++ b/src/template/helpers/vhdl/testbench_vunit.nj @@ -18,8 +18,12 @@ architecture bench of {{ name }}_tb is {{ indent[1] }}-- Clock period {{ indent[1] }}constant clk_period : time := 5 ns; {{ indent[1] }}-- Generics -{% for generic_inst in generic -%} -{{ indent[1] }}constant {{generic_inst['info']['name']}} : {{generic_inst['type']}}; +{% for element in generic -%} +{% if element['default_value'] != "" -%} +{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}} := {{element['default_value']|safe}}; +{% else -%} +{{ indent[1] }}constant {{element['info']['name']}} : {{element['type']}}; +{% endif -%} {% endfor -%} {{ indent[1] }}-- Ports {% for port_inst in port -%} diff --git a/src/template/manager.ts b/src/template/manager.ts index dcccd6c1..45995a62 100644 --- a/src/template/manager.ts +++ b/src/template/manager.ts @@ -129,6 +129,31 @@ export class Template_manager { const name = code_tree.name; const generic = this.adapt_port(code_tree.get_generic_array(), template_type, true); + // Set default value to generics + for (let i = 0; i < generic.length; i++) { + const element = generic[i]; + if (element.default_value.trim() === "") { + const normalized_type = element.type.replace(/\s/g, '').toLowerCase(); + if (normalized_type === "integer") { + element.default_value = "0"; + } + else if (normalized_type === "signed" || normalized_type === "unsigned") { + element.default_value = "(others => '0')"; + } + else if (normalized_type === "string") { + element.default_value = '""'; + } + else if (normalized_type === "boolean") { + element.default_value = "false"; + } + else if (normalized_type.includes("std_logic_vector")) { + element.default_value = "(others => '0')"; + } + else if (normalized_type === "std_logic") { + element.default_value = "'0'"; + } + } + } const port = this.adapt_port(code_tree.get_port_array(), template_type, false); template = nunjucks.render(template_path, { diff --git a/tests/TODO b/tests/TODO.md similarity index 88% rename from tests/TODO rename to tests/TODO.md index 42bb8e69..cbcaccd9 100644 --- a/tests/TODO +++ b/tests/TODO.md @@ -1,42 +1,64 @@ -- Project examples como submodulo -- Borrar las carpetas de out de los tests -- Default value para generics en los tests de templates. +# More tests +## Parser - Diferentes versiones de puertos ANSI y no ANSI. -- Types elements. -- Interfaces en entity y package. -- Doxygen parser debería funcionar con múltiples labels sin que haya un doble \n. - State machines. -- Itroducir un estado de error en hdl_element -- Modelsim linter falla con path con espacio -- En documenter revisar todos el svg_path -- Mensaje de error en el documentenr si falla el parser +- Interfaces en entity y package. +## Documenter - Documenter section test fsm - Documenter section test custom section -- Verilog template check -- GHDL linter falla cuando la descripción tiene ":" -- En las templates comprobar que el generic no está vacío y el ports también. -- En las templates cuando falla el parser todo continua y se genera una template vacía. -- Custom indent en templates dependiendo del lenguaje. -- Logger para vscode -- Repasar: - "activationEvents": [ - "*", -https://code.visualstudio.com/api/references/activation-events#Start-up +- En documenter revisar todos el svg_path + + + + -- Comprobar que todo se actualiza cuando cambia la configuración. -- Comprobar que hay log cuando hay acciones en vscode. -- Schematic con project maanger -- Revisar todos los paths para ficheros para windows -- En vscode-teroshdl está fija la configuración -- console.log en todas las cosas de vscode +# Bugs +## Linter +- GHDL linter falla cuando la descripción tiene ":" +``` /home/carlos/repo/colibri2/tests/command/linter/helpers/sample_0.vhd:13:19:error: ':' is expected instead of ';' /home/carlos/repo/colibri2/tests/command/linter/helpers/sample_0.vhd:13:19:error: type mark expected in a subtype indication /home/carlos/repo/colibri2/tests/command/linter/helpers/sample_0.vhd:18:1:error: '<=' is expected instead of 'end' /home/carlos/repo/colibri2/tests/command/linter/helpers/sample_0.vhd:18:1:error: primary expression expected /home/carlos/repo/colibri2/tests/command/linter/helpers/sample_0.vhd:16:20:error: ';' expected at end of signal assignment /home/carlos/repo/colibri2/tests/command/linter/helpers/sample_0.vhd:16:20:error: (found: 'end') +``` +- Modelsim linter falla con path con espacio +## Project manager +- Project manager no acepta nombres con espacio? +- Los tools cuando se ejecutan debeŕian coger en installation path de la configuración + + + + + +# Features +## Parser +- Itroducir un estado de error en hdl_element +- Doxygen parser debería funcionar con múltiples labels sin que haya un doble \n. +# Templates +- En las templates cuando falla el parser todo continua y se genera una template vacía. +- Custom indent en templates dependiendo del lenguaje. +- Default value para generics con Verilog. +# Documenter +- Mensaje de error en el documentenr si falla el parser +# VSCode +- Project examples como submodulo +- Borrar las carpetas de out de los tests +- Logger para vscode +- console.log en todas las cosas de vscode +- Revisar todos los paths para ficheros para windows +- Comprobar que hay log cuando hay acciones en vscode. +- Comprobar que todo se actualiza cuando cambia la configuración. +- Repasar: +``` + "activationEvents": [ + "*", +https://code.visualstudio.com/api/references/activation-events#Start-up +``` - Añadir un logger global -- Project manager no acepta nombres con espacio? -- Los tools cuando se ejecutan debeŕian coger en installation path de la configuración \ No newline at end of file +# Project manager +- Project documentation +- Schematic con project maanger diff --git a/tests/template/expected_with_generic/vhdl_hdl_element_signal.vhdl b/tests/template/expected_with_generic/vhdl_hdl_element_signal.vhdl index 041ea92b..b520626d 100644 --- a/tests/template/expected_with_generic/vhdl_hdl_element_signal.vhdl +++ b/tests/template/expected_with_generic/vhdl_hdl_element_signal.vhdl @@ -1,9 +1,9 @@ - constant a : integer := ; - constant b : unsigned := ; - constant c : signed := ; - constant d : std_logic := ; - constant e : std_logic_vector := ; - constant f : std_logic_vector(5 downto 0) := ; + constant a : integer := 0; + constant b : unsigned := (others => '0'); + constant c : signed := (others => '0'); + constant d : std_logic := '1'; + constant e : std_logic_vector := "10001"; + constant f : std_logic_vector(5 downto 0) := (others => '0'); signal g : std_logic; signal h : std_logic; signal i : std_logic; diff --git a/tests/template/expected_with_generic/vhdl_testbench_normal.vhdl b/tests/template/expected_with_generic/vhdl_testbench_normal.vhdl index 007891c4..3439e90c 100644 --- a/tests/template/expected_with_generic/vhdl_testbench_normal.vhdl +++ b/tests/template/expected_with_generic/vhdl_testbench_normal.vhdl @@ -9,12 +9,12 @@ architecture bench of test_entity_name_tb is -- Clock period constant clk_period : time := 5 ns; -- Generics - constant a : integer; - constant b : unsigned; - constant c : signed; - constant d : std_logic; - constant e : std_logic_vector; - constant f : std_logic_vector(5 downto 0); + constant a : integer := 0; + constant b : unsigned := (others => '0'); + constant c : signed := (others => '0'); + constant d : std_logic := '1'; + constant e : std_logic_vector := "10001"; + constant f : std_logic_vector(5 downto 0) := (others => '0'); -- Ports signal g : std_logic; signal h : std_logic; diff --git a/tests/template/expected_with_generic/vhdl_testbench_vunit.vhdl b/tests/template/expected_with_generic/vhdl_testbench_vunit.vhdl index 2dbb6164..635b49eb 100644 --- a/tests/template/expected_with_generic/vhdl_testbench_vunit.vhdl +++ b/tests/template/expected_with_generic/vhdl_testbench_vunit.vhdl @@ -17,12 +17,12 @@ architecture bench of test_entity_name_tb is -- Clock period constant clk_period : time := 5 ns; -- Generics - constant a : integer; - constant b : unsigned; - constant c : signed; - constant d : std_logic; - constant e : std_logic_vector; - constant f : std_logic_vector(5 downto 0); + constant a : integer := 0; + constant b : unsigned := (others => '0'); + constant c : signed := (others => '0'); + constant d : std_logic := '1'; + constant e : std_logic_vector := "10001"; + constant f : std_logic_vector(5 downto 0) := (others => '0'); -- Ports signal g : std_logic; signal h : std_logic; diff --git a/tests/template/template.spec.ts b/tests/template/template.spec.ts index faaee8ad..17870b7a 100644 --- a/tests/template/template.spec.ts +++ b/tests/template/template.spec.ts @@ -26,7 +26,8 @@ import { equal } from "assert"; import * as paht_lib from 'path'; import * as fs from 'fs'; -const language_array = [HDL_LANG.VHDL, HDL_LANG.VERILOG]; +const language_array = [HDL_LANG.VHDL]; +// const language_array = [HDL_LANG.VHDL, HDL_LANG.VERILOG]; async function generate_template_manager(language: HDL_LANG) { const template_manager = new Template_manager(language); @@ -46,11 +47,11 @@ use ieee.numeric_std.all; entity test_entity_name is generic ( - a : integer; + a : integer := 0; b : unsigned; c : signed; - d : std_logic; - e : std_logic_vector; + d : std_logic := '1'; + e : std_logic_vector := "10001"; f : std_logic_vector(5 downto 0) ); port( @@ -108,7 +109,7 @@ TEST_TYPE_LIST.forEach(TEST_TYPE => { const C_OUTPUT_BASE_PATH = create_output(TEST_TYPE); language_array.forEach(language => { - describe(`Check template ${language} element`, function () { + describe(`Check template ${language} element ${TEST_TYPE}`, function () { const values = Object.values(common.get_template_names(language)); values.forEach(template_type => { it(`Check ${template_type.id}`, async function () {