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assignments in vhdl := and <= #61

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JulienCa opened this issue Jun 18, 2020 · 3 comments
Open

assignments in vhdl := and <= #61

JulienCa opened this issue Jun 18, 2020 · 3 comments

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@JulienCa
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Hello
Could you add the assignments := and <=
They are used in VHDL

@Brandon-Valley
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I would like this as well

@wleoncio
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I could work on this, add at least another one (<- used in R) and issue a PR, but I'm not sure this project is even active anymore. :-\

@Brandon-Valley
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Making the change and issuing a PR could be a good way to find out. Worst case scenario, you could always make your own fork. :)

@JulienCa JulienCa changed the title assignment := assignments in vhdl := and <= Jul 21, 2020
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3 participants