From 747e9d44e04757fc84664d07d1181793d15d5742 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Oct 2023 10:25:39 -0700 Subject: [PATCH 1/4] Add testGetConnected{Cells,BELPins}() Signed-off-by: Eddie Hung --- .../rapidwright/design/TestDesignTools.java | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java index 049956171..14a69772f 100644 --- a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java +++ b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java @@ -1224,4 +1224,64 @@ public void testGetConnectionPIPsBiDir() { Assertions.assertNotNull(pips); Assertions.assertEquals(9, pips.size()); } + + @Test + public void testGetConnectedCells() { + Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp"); + SiteInst si = design.getSiteInstFromSiteName("SLICE_X15Y238"); + { + SitePinInst spi = si.getSitePinInst("E3"); + Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT), processor/data_path_loop[4].arith_logical_lut/LUT5(BEL: E5LUT)]", + DesignTools.getConnectedCells(spi).toString()); + } + { + SitePinInst spi = si.getSitePinInst("E6"); + Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT)]", DesignTools.getConnectedCells(spi).toString()); + } + { + SitePinInst spi = si.getSitePinInst("D_I"); + Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", DesignTools.getConnectedCells(spi).toString()); + } + { + SitePinInst spi = si.getSitePinInst("CKEN2"); + Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", DesignTools.getConnectedCells(spi).toString()); + } + { + DesignTools.createMissingSitePinInsts(design, design.getNet("clk")); + SitePinInst spi = si.getSitePinInst("CLK2"); + Assertions.assertEquals("[processor/data_path_loop[7].arith_logical_flop(BEL: HFF), output_port_z_reg[0](BEL: HFF2), " + + "output_port_z_reg[1](BEL: GFF2), processor/data_path_loop[5].arith_logical_flop(BEL: FFF), output_port_z_reg[2](BEL: FFF2), " + + "processor/data_path_loop[4].arith_logical_flop(BEL: EFF), processor/data_path_loop[6].arith_logical_flop(BEL: GFF)]", + DesignTools.getConnectedCells(spi).toString()); + } + } + + @Test + public void testGetConnectedBELPins() { + Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp"); + SiteInst si = design.getSiteInstFromSiteName("SLICE_X15Y238"); + { + SitePinInst spi = si.getSitePinInst("E3"); + Assertions.assertEquals("[E6LUT.A3, E5LUT.A3]", + DesignTools.getConnectedBELPins(spi).toString()); + } + { + SitePinInst spi = si.getSitePinInst("E6"); + Assertions.assertEquals("[E6LUT.A6]", DesignTools.getConnectedBELPins(spi).toString()); + } + { + SitePinInst spi = si.getSitePinInst("D_I"); + Assertions.assertEquals("[DFF2.D]", DesignTools.getConnectedBELPins(spi).toString()); + } + { + SitePinInst spi = si.getSitePinInst("CKEN2"); + Assertions.assertEquals("[DFF2.CE]", DesignTools.getConnectedBELPins(spi).toString()); + } + { + DesignTools.createMissingSitePinInsts(design, design.getNet("clk")); + SitePinInst spi = si.getSitePinInst("CLK2"); + Assertions.assertEquals("[EFF.CLK, GFF2.CLK, GFF.CLK, FFF.CLK, HFF2.CLK, HFF.CLK, EFF2.CLK, FFF2.CLK]", + DesignTools.getConnectedBELPins(spi).toString()); + } + } } From 2181f32a4f0caefd377f51ee02b7f7084c3f5409 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Oct 2023 10:26:59 -0700 Subject: [PATCH 2/4] Add DesignTools.getConnectedBELPins() By refactoring DesignTools.getConnectedCells() Signed-off-by: Eddie Hung --- .../rapidwright/design/DesignTools.java | 49 ++++++++++++++----- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java index 1770c6252..e955ee0d3 100644 --- a/src/com/xilinx/rapidwright/design/DesignTools.java +++ b/src/com/xilinx/rapidwright/design/DesignTools.java @@ -50,6 +50,7 @@ import java.util.PriorityQueue; import java.util.Queue; import java.util.Set; +import java.util.function.Consumer; import java.util.stream.Collectors; import com.xilinx.rapidwright.design.blocks.PBlock; @@ -1996,38 +1997,64 @@ public static boolean stampPlacement(Design design, Module stamp, Map getConnectedCells(SitePinInst pin) { - HashSet cells = new HashSet(); + private static void foreachConnectedBELPin(SitePinInst pin, Consumer action) { SiteInst si = pin.getSiteInst(); - if (si == null) return cells; + if (si == null) { + return; + } for (BELPin p : pin.getBELPin().getSiteConns()) { if (p.getBEL().getBELClass() == BELClass.RBEL) { SitePIP pip = si.getUsedSitePIP(p.getBELName()); if (pip == null) continue; if (p.isOutput()) { p = pip.getInputPin().getSiteConns().get(0); - Cell c = si.getCell(p.getBELName()); - if (c != null) cells.add(c); + action.accept(p); } else { for (BELPin snk : pip.getOutputPin().getSiteConns()) { - Cell c = si.getCell(snk.getBELName()); - if (c != null) cells.add(c); + action.accept(snk); } } } else { Cell c = si.getCell(p.getBELName()); if (c != null && c.getLogicalPinMapping(p.getName()) != null) { - cells.add(c); + action.accept(p); } } } + } + + /** + * Looks in the site instance for cells connected to this site pin. + * @param pin The SitePinInst to examine for connected cells + * @return Set of connected cells to this pin + */ + public static Set getConnectedCells(SitePinInst pin) { + final HashSet cells = new HashSet<>(); + SiteInst si = pin.getSiteInst(); + foreachConnectedBELPin(pin, (p) -> { + Cell c = si.getCell(p.getBELName()); + if (c != null) { + cells.add(c); + } + }); return cells; } + /** + * Looks in the site instance for BEL pins connected to this site pin. + * @param pin The SitePinInst to examine for connected BEL pins + * @return Set of BEL pins to this site pin + */ + public static Set getConnectedBELPins(SitePinInst pin) { + HashSet pins = new HashSet<>(); + foreachConnectedBELPin(pin, pins::add); + return pins; + } + /** * Quick and dumb placement of a cell. Does not attempt * any optimization and will not change the placement From 4f3efcbc7bb3356f648a15db1cceaf7c63b81dcb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Oct 2023 11:06:30 -0700 Subject: [PATCH 3/4] Sort results Signed-off-by: Eddie Hung --- .../rapidwright/design/TestDesignTools.java | 39 +++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java index 14a69772f..9c8cb7ac3 100644 --- a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java +++ b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java @@ -33,6 +33,7 @@ import java.util.Map; import java.util.Map.Entry; import java.util.Set; +import java.util.stream.Collectors; import org.junit.jupiter.api.Assertions; import org.junit.jupiter.api.Test; @@ -1231,28 +1232,31 @@ public void testGetConnectedCells() { SiteInst si = design.getSiteInstFromSiteName("SLICE_X15Y238"); { SitePinInst spi = si.getSitePinInst("E3"); - Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT), processor/data_path_loop[4].arith_logical_lut/LUT5(BEL: E5LUT)]", - DesignTools.getConnectedCells(spi).toString()); + Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT5(BEL: E5LUT), processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT)]", + DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); } { SitePinInst spi = si.getSitePinInst("E6"); - Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT)]", DesignTools.getConnectedCells(spi).toString()); + Assertions.assertEquals("[processor/data_path_loop[4].arith_logical_lut/LUT6(BEL: E6LUT)]", + DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); } { SitePinInst spi = si.getSitePinInst("D_I"); - Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", DesignTools.getConnectedCells(spi).toString()); + Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", + DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); } { SitePinInst spi = si.getSitePinInst("CKEN2"); - Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", DesignTools.getConnectedCells(spi).toString()); + Assertions.assertEquals("[output_port_z_reg[4](BEL: DFF2)]", + DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); } { DesignTools.createMissingSitePinInsts(design, design.getNet("clk")); SitePinInst spi = si.getSitePinInst("CLK2"); - Assertions.assertEquals("[processor/data_path_loop[7].arith_logical_flop(BEL: HFF), output_port_z_reg[0](BEL: HFF2), " + - "output_port_z_reg[1](BEL: GFF2), processor/data_path_loop[5].arith_logical_flop(BEL: FFF), output_port_z_reg[2](BEL: FFF2), " + - "processor/data_path_loop[4].arith_logical_flop(BEL: EFF), processor/data_path_loop[6].arith_logical_flop(BEL: GFF)]", - DesignTools.getConnectedCells(spi).toString()); + Assertions.assertEquals("[output_port_z_reg[0](BEL: HFF2), output_port_z_reg[1](BEL: GFF2), output_port_z_reg[2](BEL: FFF2), " + + "processor/data_path_loop[4].arith_logical_flop(BEL: EFF), processor/data_path_loop[5].arith_logical_flop(BEL: FFF), " + + "processor/data_path_loop[6].arith_logical_flop(BEL: GFF), processor/data_path_loop[7].arith_logical_flop(BEL: HFF)]", + DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); } } @@ -1262,26 +1266,29 @@ public void testGetConnectedBELPins() { SiteInst si = design.getSiteInstFromSiteName("SLICE_X15Y238"); { SitePinInst spi = si.getSitePinInst("E3"); - Assertions.assertEquals("[E6LUT.A3, E5LUT.A3]", - DesignTools.getConnectedBELPins(spi).toString()); + Assertions.assertEquals("[E5LUT.A3, E6LUT.A3]", + DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); } { SitePinInst spi = si.getSitePinInst("E6"); - Assertions.assertEquals("[E6LUT.A6]", DesignTools.getConnectedBELPins(spi).toString()); + Assertions.assertEquals("[E6LUT.A6]", + DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); } { SitePinInst spi = si.getSitePinInst("D_I"); - Assertions.assertEquals("[DFF2.D]", DesignTools.getConnectedBELPins(spi).toString()); + Assertions.assertEquals("[DFF2.D]", + DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); } { SitePinInst spi = si.getSitePinInst("CKEN2"); - Assertions.assertEquals("[DFF2.CE]", DesignTools.getConnectedBELPins(spi).toString()); + Assertions.assertEquals("[DFF2.CE]", + DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); } { DesignTools.createMissingSitePinInsts(design, design.getNet("clk")); SitePinInst spi = si.getSitePinInst("CLK2"); - Assertions.assertEquals("[EFF.CLK, GFF2.CLK, GFF.CLK, FFF.CLK, HFF2.CLK, HFF.CLK, EFF2.CLK, FFF2.CLK]", - DesignTools.getConnectedBELPins(spi).toString()); + Assertions.assertEquals("[EFF.CLK, EFF2.CLK, FFF.CLK, FFF2.CLK, GFF.CLK, GFF2.CLK, HFF.CLK, HFF2.CLK]", + DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); } } } From f4083a743376f943e98216b135f87e785c7dafba Mon Sep 17 00:00:00 2001 From: eddieh-xlnx Date: Mon, 30 Oct 2023 11:10:39 -0700 Subject: [PATCH 4/4] Apply suggestions from code review Co-authored-by: Chris Lavin Signed-off-by: eddieh-xlnx --- src/com/xilinx/rapidwright/design/DesignTools.java | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java index e955ee0d3..93890827f 100644 --- a/src/com/xilinx/rapidwright/design/DesignTools.java +++ b/src/com/xilinx/rapidwright/design/DesignTools.java @@ -2033,7 +2033,7 @@ private static void foreachConnectedBELPin(SitePinInst pin, Consumer act * @return Set of connected cells to this pin */ public static Set getConnectedCells(SitePinInst pin) { - final HashSet cells = new HashSet<>(); + final Set cells = new HashSet<>(); SiteInst si = pin.getSiteInst(); foreachConnectedBELPin(pin, (p) -> { Cell c = si.getCell(p.getBELName()); @@ -2050,7 +2050,7 @@ public static Set getConnectedCells(SitePinInst pin) { * @return Set of BEL pins to this site pin */ public static Set getConnectedBELPins(SitePinInst pin) { - HashSet pins = new HashSet<>(); + Set pins = new HashSet<>(); foreachConnectedBELPin(pin, pins::add); return pins; }