diff --git a/dlk/python/dlk/templates/include/de10_nano.h b/dlk/python/dlk/templates/include/de10_nano.h index 7de4b37bd..055cb5a76 100644 --- a/dlk/python/dlk/templates/include/de10_nano.h +++ b/dlk/python/dlk/templates/include/de10_nano.h @@ -18,67 +18,68 @@ limitations under the License. #include "memdriver.h" #include "time_measurement.h" #include +#include namespace de10_nano { // // TCA // -struct Csr { - static constexpr uint32_t start = 0; - static constexpr uint32_t admaInputAddress = 1; - static constexpr uint32_t admaInputHCount = 2; - static constexpr uint32_t admaInputWCount = 3; - static constexpr uint32_t admaInputCCount = 4; - static constexpr uint32_t admaTopTileH = 5; - static constexpr uint32_t admaMiddleTileH = 6; - static constexpr uint32_t admaBottomTileH = 7; - static constexpr uint32_t admaLeftTileW = 8; - static constexpr uint32_t admaMiddleTileW = 9; - static constexpr uint32_t admaRightTileW = 10; - static constexpr uint32_t admaLeftRowToRowDistance = 11; - static constexpr uint32_t admaMiddleRowToRowDistance = 12; - static constexpr uint32_t admaRightRowToRowDistance = 13; - static constexpr uint32_t admaLeftStep = 14; - static constexpr uint32_t admaMiddleStep = 15; - static constexpr uint32_t admaTopRowDistance = 16; - static constexpr uint32_t admaMidRowDistance = 17; - static constexpr uint32_t admaInputSpace = 18; - static constexpr uint32_t admaTopBottomLeftPad = 19; - static constexpr uint32_t admaTopBottomMiddlePad = 20; - static constexpr uint32_t admaTopBottomRightPad = 21; - static constexpr uint32_t admaSidePad = 22; - static constexpr uint32_t wdmaStartAddress = 23; - static constexpr uint32_t wdmaOutputHCount = 24; - static constexpr uint32_t wdmaOutputWCount = 25; - static constexpr uint32_t wdmaKernelBlockCount = 26; - static constexpr uint32_t fdmaOutputAddress = 27; - static constexpr uint32_t fdmaOutputHCount = 28; - static constexpr uint32_t fdmaOutputWCount = 29; - static constexpr uint32_t fdmaOutputCCount = 30; - static constexpr uint32_t fdmaRegularTileH = 31; - static constexpr uint32_t fdmaLastTileH = 32; - static constexpr uint32_t fdmaRegularTileW = 33; - static constexpr uint32_t fdmaLastTileW = 34; - static constexpr uint32_t fdmaRegularRowToRowDistance = 35; - static constexpr uint32_t fdmaLastRowToRowDistance = 36; - static constexpr uint32_t fdmaOutputSpace = 37; - static constexpr uint32_t fdmaRowDistance = 38; - static constexpr uint32_t a2fInputCCount = 39; - static constexpr uint32_t a2fKernelVCount = 40; - static constexpr uint32_t a2fKernelHCount = 41; - static constexpr uint32_t a2fTileStep = 42; - static constexpr uint32_t a2fTileGap = 43; - static constexpr uint32_t a2fOutputHCount = 44; - static constexpr uint32_t a2fOutputWCount = 45; - static constexpr uint32_t a2fRegularTileH = 46; - static constexpr uint32_t a2fLastTileH = 47; - static constexpr uint32_t a2fRegularTileW = 48; - static constexpr uint32_t a2fLastTileW = 49; - static constexpr uint32_t qdmaStartAddress = 50; - static constexpr uint32_t bnqEnable = 51; - - static constexpr uint32_t statusRegister = 52; +enum class Csr { + start = 0, + admaInputAddress = 1, + admaInputHCount = 2, + admaInputWCount = 3, + admaInputCCount = 4, + admaTopTileH = 5, + admaMiddleTileH = 6, + admaBottomTileH = 7, + admaLeftTileW = 8, + admaMiddleTileW = 9, + admaRightTileW = 10, + admaLeftRowToRowDistance = 11, + admaMiddleRowToRowDistance = 12, + admaRightRowToRowDistance = 13, + admaLeftStep = 14, + admaMiddleStep = 15, + admaTopRowDistance = 16, + admaMidRowDistance = 17, + admaInputSpace = 18, + admaTopBottomLeftPad = 19, + admaTopBottomMiddlePad = 20, + admaTopBottomRightPad = 21, + admaSidePad = 22, + wdmaStartAddress = 23, + wdmaOutputHCount = 24, + wdmaOutputWCount = 25, + wdmaKernelBlockCount = 26, + fdmaOutputAddress = 27, + fdmaOutputHCount = 28, + fdmaOutputWCount = 29, + fdmaOutputCCount = 30, + fdmaRegularTileH = 31, + fdmaLastTileH = 32, + fdmaRegularTileW = 33, + fdmaLastTileW = 34, + fdmaRegularRowToRowDistance = 35, + fdmaLastRowToRowDistance = 36, + fdmaOutputSpace = 37, + fdmaRowDistance = 38, + a2fInputCCount = 39, + a2fKernelVCount = 40, + a2fKernelHCount = 41, + a2fTileStep = 42, + a2fTileGap = 43, + a2fOutputHCount = 44, + a2fOutputWCount = 45, + a2fRegularTileH = 46, + a2fLastTileH = 47, + a2fRegularTileW = 48, + a2fLastTileW = 49, + qdmaStartAddress = 50, + bnqEnable = 51, + + statusRegister = 52, }; struct Parameters { @@ -270,63 +271,63 @@ void RunTCA(unsigned long input_addr, unsigned long output_addr, unsigned long k auto tileHeight = 32u; auto p = calcParameters(in_h, in_w, in_c, tileWidth, tileHeight, out_c, k_h, k_w, input_addr, kernel_addr, thresholds_addr, output_addr, use_threshold == 1); - csr[Csr::admaInputAddress] = p.admaInputAddress; - csr[Csr::admaInputHCount] = p.admaInputHCount; - csr[Csr::admaInputWCount] = p.admaInputWCount; - csr[Csr::admaInputCCount] = p.admaInputCCount; - csr[Csr::admaTopTileH] = p.admaTopTileH; - csr[Csr::admaMiddleTileH] = p.admaMiddleTileH; - csr[Csr::admaBottomTileH] = p.admaBottomTileH; - csr[Csr::admaLeftTileW] = p.admaLeftTileW; - csr[Csr::admaMiddleTileW] = p.admaMiddleTileW; - csr[Csr::admaRightTileW] = p.admaRightTileW; - csr[Csr::admaLeftRowToRowDistance] = p.admaLeftRowToRowDistance; - csr[Csr::admaMiddleRowToRowDistance] = p.admaMiddleRowToRowDistance; - csr[Csr::admaRightRowToRowDistance] = p.admaRightRowToRowDistance; - csr[Csr::admaLeftStep] = p.admaLeftStep; - csr[Csr::admaMiddleStep] = p.admaMiddleStep; - csr[Csr::admaTopRowDistance] = p.admaTopRowDistance; - csr[Csr::admaMidRowDistance] = p.admaMidRowDistance; - csr[Csr::admaInputSpace] = p.admaInputSpace; - csr[Csr::admaTopBottomLeftPad] = p.admaTopBottomLeftPad; - csr[Csr::admaTopBottomMiddlePad] = p.admaTopBottomMiddlePad; - csr[Csr::admaTopBottomRightPad] = p.admaTopBottomRightPad; - csr[Csr::admaSidePad] = p.admaSidePad; - csr[Csr::wdmaStartAddress] = p.wdmaStartAddress; - csr[Csr::wdmaOutputHCount] = p.wdmaOutputHCount; - csr[Csr::wdmaOutputWCount] = p.wdmaOutputWCount; - csr[Csr::wdmaKernelBlockCount] = p.wdmaKernelBlockCount; - csr[Csr::fdmaOutputAddress] = p.fdmaOutputAddress; - csr[Csr::fdmaOutputHCount] = p.fdmaOutputHCount; - csr[Csr::fdmaOutputWCount] = p.fdmaOutputWCount; - csr[Csr::fdmaOutputCCount] = p.fdmaOutputCCount; - csr[Csr::fdmaRegularTileH] = p.fdmaRegularTileH; - csr[Csr::fdmaLastTileH] = p.fdmaLastTileH; - csr[Csr::fdmaRegularTileW] = p.fdmaRegularTileW; - csr[Csr::fdmaLastTileW] = p.fdmaLastTileW; - csr[Csr::fdmaRegularRowToRowDistance] = p.fdmaRegularRowToRowDistance; - csr[Csr::fdmaLastRowToRowDistance] = p.fdmaLastRowToRowDistance; - csr[Csr::fdmaOutputSpace] = p.fdmaOutputSpace; - csr[Csr::fdmaRowDistance] = p.fdmaRowDistance; - csr[Csr::a2fInputCCount] = p.a2fInputCCount; - csr[Csr::a2fKernelVCount] = p.a2fKernelVCount; - csr[Csr::a2fKernelHCount] = p.a2fKernelHCount; - csr[Csr::a2fTileStep] = p.a2fTileStep; - csr[Csr::a2fTileGap] = p.a2fTileGap; - csr[Csr::a2fOutputHCount] = p.a2fOutputHCount; - csr[Csr::a2fOutputWCount] = p.a2fOutputWCount; - csr[Csr::a2fRegularTileH] = p.a2fRegularTileH; - csr[Csr::a2fLastTileH] = p.a2fLastTileH; - csr[Csr::a2fRegularTileW] = p.a2fRegularTileW; - csr[Csr::a2fLastTileW] = p.a2fLastTileW; - csr[Csr::qdmaStartAddress] = p.qdmaStartAddress; - csr[Csr::bnqEnable] = p.bnqEnable; - - // std::cout << "Status " << csr[Csr::statusRegister] << std::endl; - csr[Csr::start] = 1; - - // std::cout << "Status " << csr[Csr::statusRegister] << std::endl; - while (csr[Csr::statusRegister] != 127) { + csr[static_cast(Csr::admaInputAddress)] = p.admaInputAddress; + csr[static_cast(Csr::admaInputHCount)] = p.admaInputHCount; + csr[static_cast(Csr::admaInputWCount)] = p.admaInputWCount; + csr[static_cast(Csr::admaInputCCount)] = p.admaInputCCount; + csr[static_cast(Csr::admaTopTileH)] = p.admaTopTileH; + csr[static_cast(Csr::admaMiddleTileH)] = p.admaMiddleTileH; + csr[static_cast(Csr::admaBottomTileH)] = p.admaBottomTileH; + csr[static_cast(Csr::admaLeftTileW)] = p.admaLeftTileW; + csr[static_cast(Csr::admaMiddleTileW)] = p.admaMiddleTileW; + csr[static_cast(Csr::admaRightTileW)] = p.admaRightTileW; + csr[static_cast(Csr::admaLeftRowToRowDistance)] = p.admaLeftRowToRowDistance; + csr[static_cast(Csr::admaMiddleRowToRowDistance)] = p.admaMiddleRowToRowDistance; + csr[static_cast(Csr::admaRightRowToRowDistance)] = p.admaRightRowToRowDistance; + csr[static_cast(Csr::admaLeftStep)] = p.admaLeftStep; + csr[static_cast(Csr::admaMiddleStep)] = p.admaMiddleStep; + csr[static_cast(Csr::admaTopRowDistance)] = p.admaTopRowDistance; + csr[static_cast(Csr::admaMidRowDistance)] = p.admaMidRowDistance; + csr[static_cast(Csr::admaInputSpace)] = p.admaInputSpace; + csr[static_cast(Csr::admaTopBottomLeftPad)] = p.admaTopBottomLeftPad; + csr[static_cast(Csr::admaTopBottomMiddlePad)] = p.admaTopBottomMiddlePad; + csr[static_cast(Csr::admaTopBottomRightPad)] = p.admaTopBottomRightPad; + csr[static_cast(Csr::admaSidePad)] = p.admaSidePad; + csr[static_cast(Csr::wdmaStartAddress)] = p.wdmaStartAddress; + csr[static_cast(Csr::wdmaOutputHCount)] = p.wdmaOutputHCount; + csr[static_cast(Csr::wdmaOutputWCount)] = p.wdmaOutputWCount; + csr[static_cast(Csr::wdmaKernelBlockCount)] = p.wdmaKernelBlockCount; + csr[static_cast(Csr::fdmaOutputAddress)] = p.fdmaOutputAddress; + csr[static_cast(Csr::fdmaOutputHCount)] = p.fdmaOutputHCount; + csr[static_cast(Csr::fdmaOutputWCount)] = p.fdmaOutputWCount; + csr[static_cast(Csr::fdmaOutputCCount)] = p.fdmaOutputCCount; + csr[static_cast(Csr::fdmaRegularTileH)] = p.fdmaRegularTileH; + csr[static_cast(Csr::fdmaLastTileH)] = p.fdmaLastTileH; + csr[static_cast(Csr::fdmaRegularTileW)] = p.fdmaRegularTileW; + csr[static_cast(Csr::fdmaLastTileW)] = p.fdmaLastTileW; + csr[static_cast(Csr::fdmaRegularRowToRowDistance)] = p.fdmaRegularRowToRowDistance; + csr[static_cast(Csr::fdmaLastRowToRowDistance)] = p.fdmaLastRowToRowDistance; + csr[static_cast(Csr::fdmaOutputSpace)] = p.fdmaOutputSpace; + csr[static_cast(Csr::fdmaRowDistance)] = p.fdmaRowDistance; + csr[static_cast(Csr::a2fInputCCount)] = p.a2fInputCCount; + csr[static_cast(Csr::a2fKernelVCount)] = p.a2fKernelVCount; + csr[static_cast(Csr::a2fKernelHCount)] = p.a2fKernelHCount; + csr[static_cast(Csr::a2fTileStep)] = p.a2fTileStep; + csr[static_cast(Csr::a2fTileGap)] = p.a2fTileGap; + csr[static_cast(Csr::a2fOutputHCount)] = p.a2fOutputHCount; + csr[static_cast(Csr::a2fOutputWCount)] = p.a2fOutputWCount; + csr[static_cast(Csr::a2fRegularTileH)] = p.a2fRegularTileH; + csr[static_cast(Csr::a2fLastTileH)] = p.a2fLastTileH; + csr[static_cast(Csr::a2fRegularTileW)] = p.a2fRegularTileW; + csr[static_cast(Csr::a2fLastTileW)] = p.a2fLastTileW; + csr[static_cast(Csr::qdmaStartAddress)] = p.qdmaStartAddress; + csr[static_cast(Csr::bnqEnable)] = p.bnqEnable; + + // std::cout << "Status " << csr[Csr::statusRegister)] << std::endl; + csr[static_cast(Csr::start)] = 1; + + // std::cout << "Status " << csr[Csr::statusRegister)] << std::endl; + while (csr[static_cast(Csr::statusRegister)] != 127) { // std::cout << "Status " << csr[Csr::statusRegister] << std::endl; continue; }