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caravel_fpga.hwh
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue May 23 17:10:22 2023" VIVADOVERSION="2022.1">
<SYSTEMINFO ARCH="zynq" BOARD="tul.com.tw:pynq-z2:part0:1.0" DEVICE="7z020" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
<PORT DIR="IO" NAME="DDR_0_cas_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CAS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_0_cke" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CKE">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_0_ck_n" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_0_ck_p" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_0_cs_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_0_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_0_odt" SIGIS="undef" SIGNAME="processing_system7_0_DDR_ODT">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_ODT"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_0_ras_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_RAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_0_we_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_WEB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_WEB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="2" NAME="DDR_0_ba" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_BankAddr">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_BankAddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="14" NAME="DDR_0_addr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_Addr">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Addr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR_0_dm" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DM">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DM"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="31" NAME="DDR_0_dq" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQ">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQ"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR_0_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR_0_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQS"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="53" NAME="FIXED_IO_0_mio" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_MIO">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="MIO"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_0_ddr_vrn" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRN">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_VRN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_0_ddr_vrp" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRP">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_VRP"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_0_ps_srstb" SIGIS="undef" SIGNAME="processing_system7_0_PS_SRSTB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="PS_SRSTB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_0_ps_clk" SIGIS="undef" SIGNAME="processing_system7_0_PS_CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="PS_CLK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_0_ps_porb" SIGIS="undef" SIGNAME="processing_system7_0_PS_PORB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="PS_PORB"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
<BUSINTERFACE BUSNAME="processing_system7_0_DDR" DATAWIDTH="8" NAME="DDR_0" TYPE="INITIATOR">
<PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
<PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
<PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
<PARAMETER NAME="MEMORY_PART"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
<PARAMETER NAME="CS_ENABLED" VALUE="true"/>
<PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
<PARAMETER NAME="SLOT" VALUE="Single"/>
<PARAMETER NAME="CUSTOM_PARTS"/>
<PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
<PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
<PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
<PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
<PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
<PORTMAPS>
<PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_0_cas_n"/>
<PORTMAP LOGICAL="CKE" PHYSICAL="DDR_0_cke"/>
<PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_0_ck_n"/>
<PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_0_ck_p"/>
<PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_0_cs_n"/>
<PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_0_reset_n"/>
<PORTMAP LOGICAL="ODT" PHYSICAL="DDR_0_odt"/>
<PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_0_ras_n"/>
<PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_0_we_n"/>
<PORTMAP LOGICAL="BA" PHYSICAL="DDR_0_ba"/>
<PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_0_addr"/>
<PORTMAP LOGICAL="DM" PHYSICAL="DDR_0_dm"/>
<PORTMAP LOGICAL="DQ" PHYSICAL="DDR_0_dq"/>
<PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_0_dqs_n"/>
<PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_0_dqs_p"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="processing_system7_0_FIXED_IO" NAME="FIXED_IO_0" TYPE="INITIATOR">
<PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
<PORTMAPS>
<PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_0_mio"/>
<PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_0_ddr_vrn"/>
<PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_0_ddr_vrp"/>
<PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_0_ps_srstb"/>
<PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_0_ps_clk"/>
<PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_0_ps_porb"/>
</PORTMAPS>
</BUSINTERFACE>
</EXTERNALINTERFACES>
<MODULES>
<MODULE COREREVISION="27" FULLNAME="/axi_mem_intercon" HWVERSION="2.1" INSTANCE="axi_mem_intercon" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
</DOCUMENTS>
<PARAMETERS>
<PARAMETER NAME="NUM_SI" VALUE="1"/>
<PARAMETER NAME="NUM_MI" VALUE="1"/>
<PARAMETER NAME="STRATEGY" VALUE="0"/>
<PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
<PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
<PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
<PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
<PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
<PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
<PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
<PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M00_SECURE" VALUE="0"/>
<PARAMETER NAME="M01_SECURE" VALUE="0"/>
<PARAMETER NAME="M02_SECURE" VALUE="0"/>
<PARAMETER NAME="M03_SECURE" VALUE="0"/>
<PARAMETER NAME="M04_SECURE" VALUE="0"/>
<PARAMETER NAME="M05_SECURE" VALUE="0"/>
<PARAMETER NAME="M06_SECURE" VALUE="0"/>
<PARAMETER NAME="M07_SECURE" VALUE="0"/>
<PARAMETER NAME="M08_SECURE" VALUE="0"/>
<PARAMETER NAME="M09_SECURE" VALUE="0"/>
<PARAMETER NAME="M10_SECURE" VALUE="0"/>
<PARAMETER NAME="M11_SECURE" VALUE="0"/>
<PARAMETER NAME="M12_SECURE" VALUE="0"/>
<PARAMETER NAME="M13_SECURE" VALUE="0"/>
<PARAMETER NAME="M14_SECURE" VALUE="0"/>
<PARAMETER NAME="M15_SECURE" VALUE="0"/>
<PARAMETER NAME="M16_SECURE" VALUE="0"/>
<PARAMETER NAME="M17_SECURE" VALUE="0"/>
<PARAMETER NAME="M18_SECURE" VALUE="0"/>
<PARAMETER NAME="M19_SECURE" VALUE="0"/>
<PARAMETER NAME="M20_SECURE" VALUE="0"/>
<PARAMETER NAME="M21_SECURE" VALUE="0"/>
<PARAMETER NAME="M22_SECURE" VALUE="0"/>
<PARAMETER NAME="M23_SECURE" VALUE="0"/>
<PARAMETER NAME="M24_SECURE" VALUE="0"/>
<PARAMETER NAME="M25_SECURE" VALUE="0"/>
<PARAMETER NAME="M26_SECURE" VALUE="0"/>
<PARAMETER NAME="M27_SECURE" VALUE="0"/>
<PARAMETER NAME="M28_SECURE" VALUE="0"/>
<PARAMETER NAME="M29_SECURE" VALUE="0"/>
<PARAMETER NAME="M30_SECURE" VALUE="0"/>
<PARAMETER NAME="M31_SECURE" VALUE="0"/>
<PARAMETER NAME="M32_SECURE" VALUE="0"/>
<PARAMETER NAME="M33_SECURE" VALUE="0"/>
<PARAMETER NAME="M34_SECURE" VALUE="0"/>
<PARAMETER NAME="M35_SECURE" VALUE="0"/>
<PARAMETER NAME="M36_SECURE" VALUE="0"/>
<PARAMETER NAME="M37_SECURE" VALUE="0"/>
<PARAMETER NAME="M38_SECURE" VALUE="0"/>
<PARAMETER NAME="M39_SECURE" VALUE="0"/>
<PARAMETER NAME="M40_SECURE" VALUE="0"/>
<PARAMETER NAME="M41_SECURE" VALUE="0"/>
<PARAMETER NAME="M42_SECURE" VALUE="0"/>
<PARAMETER NAME="M43_SECURE" VALUE="0"/>
<PARAMETER NAME="M44_SECURE" VALUE="0"/>
<PARAMETER NAME="M45_SECURE" VALUE="0"/>
<PARAMETER NAME="M46_SECURE" VALUE="0"/>
<PARAMETER NAME="M47_SECURE" VALUE="0"/>
<PARAMETER NAME="M48_SECURE" VALUE="0"/>
<PARAMETER NAME="M49_SECURE" VALUE="0"/>
<PARAMETER NAME="M50_SECURE" VALUE="0"/>
<PARAMETER NAME="M51_SECURE" VALUE="0"/>
<PARAMETER NAME="M52_SECURE" VALUE="0"/>
<PARAMETER NAME="M53_SECURE" VALUE="0"/>
<PARAMETER NAME="M54_SECURE" VALUE="0"/>
<PARAMETER NAME="M55_SECURE" VALUE="0"/>
<PARAMETER NAME="M56_SECURE" VALUE="0"/>
<PARAMETER NAME="M57_SECURE" VALUE="0"/>
<PARAMETER NAME="M58_SECURE" VALUE="0"/>
<PARAMETER NAME="M59_SECURE" VALUE="0"/>
<PARAMETER NAME="M60_SECURE" VALUE="0"/>
<PARAMETER NAME="M61_SECURE" VALUE="0"/>
<PARAMETER NAME="M62_SECURE" VALUE="0"/>
<PARAMETER NAME="M63_SECURE" VALUE="0"/>
<PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_axi_mem_intercon_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
</PARAMETERS>
<PORTS>
<PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_10M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="rst_ps7_0_10M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_10M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="rst_ps7_0_10M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_10M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="rst_ps7_0_10M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="63" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S00_AXI_arregion" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arregion">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARREGION"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARQOS"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="m_axi_BUS0_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="63" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARQOS"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="read_romcode_0_m_axi_BUS0" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
<PORTMAP LOGICAL="ARREGION" PHYSICAL="S00_AXI_arregion"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" DATAWIDTH="64" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="5" FULLNAME="/blk_mem_gen_0" HWVERSION="8.4" INSTANCE="blk_mem_gen_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY" MODTYPE="blk_mem_gen" VLNV="xilinx.com:ip:blk_mem_gen:8.4">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=blk_mem_gen;v=v8_4;d=pg058-blk-mem-gen.pdf"/>
</DOCUMENTS>
<PARAMETERS>
<PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
<PARAMETER NAME="C_XDEVICEFAMILY" VALUE="zynq"/>
<PARAMETER NAME="C_ELABORATION_DIR" VALUE="./"/>
<PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
<PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
<PARAMETER NAME="C_AXI_SLAVE_TYPE" VALUE="0"/>
<PARAMETER NAME="C_USE_BRAM_BLOCK" VALUE="1"/>
<PARAMETER NAME="C_ENABLE_32BIT_ADDRESS" VALUE="1"/>
<PARAMETER NAME="C_CTRL_ECC_ALGO" VALUE="NONE"/>
<PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
<PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="4"/>
<PARAMETER NAME="C_MEM_TYPE" VALUE="2"/>
<PARAMETER NAME="C_BYTE_SIZE" VALUE="8"/>
<PARAMETER NAME="C_ALGORITHM" VALUE="1"/>
<PARAMETER NAME="C_PRIM_TYPE" VALUE="1"/>
<PARAMETER NAME="C_LOAD_INIT_FILE" VALUE="0"/>
<PARAMETER NAME="C_INIT_FILE_NAME" VALUE="no_coe_file_loaded"/>
<PARAMETER NAME="C_INIT_FILE" VALUE="NONE"/>
<PARAMETER NAME="C_USE_DEFAULT_DATA" VALUE="0"/>
<PARAMETER NAME="C_DEFAULT_DATA" VALUE="0"/>
<PARAMETER NAME="C_HAS_RSTA" VALUE="1"/>
<PARAMETER NAME="C_RST_PRIORITY_A" VALUE="CE"/>
<PARAMETER NAME="C_RSTRAM_A" VALUE="0"/>
<PARAMETER NAME="C_INITA_VAL" VALUE="0"/>
<PARAMETER NAME="C_HAS_ENA" VALUE="1"/>
<PARAMETER NAME="C_HAS_REGCEA" VALUE="0"/>
<PARAMETER NAME="C_USE_BYTE_WEA" VALUE="1"/>
<PARAMETER NAME="C_WEA_WIDTH" VALUE="4"/>
<PARAMETER NAME="C_WRITE_MODE_A" VALUE="WRITE_FIRST"/>
<PARAMETER NAME="C_WRITE_WIDTH_A" VALUE="32"/>
<PARAMETER NAME="C_READ_WIDTH_A" VALUE="32"/>
<PARAMETER NAME="C_WRITE_DEPTH_A" VALUE="2048"/>
<PARAMETER NAME="C_READ_DEPTH_A" VALUE="2048"/>
<PARAMETER NAME="C_ADDRA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_HAS_RSTB" VALUE="1"/>
<PARAMETER NAME="C_RST_PRIORITY_B" VALUE="CE"/>
<PARAMETER NAME="C_RSTRAM_B" VALUE="0"/>
<PARAMETER NAME="C_INITB_VAL" VALUE="0"/>
<PARAMETER NAME="C_HAS_ENB" VALUE="1"/>
<PARAMETER NAME="C_HAS_REGCEB" VALUE="0"/>
<PARAMETER NAME="C_USE_BYTE_WEB" VALUE="1"/>
<PARAMETER NAME="C_WEB_WIDTH" VALUE="4"/>
<PARAMETER NAME="C_WRITE_MODE_B" VALUE="WRITE_FIRST"/>
<PARAMETER NAME="C_WRITE_WIDTH_B" VALUE="32"/>
<PARAMETER NAME="C_READ_WIDTH_B" VALUE="32"/>
<PARAMETER NAME="C_WRITE_DEPTH_B" VALUE="2048"/>
<PARAMETER NAME="C_READ_DEPTH_B" VALUE="2048"/>
<PARAMETER NAME="C_ADDRB_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_A" VALUE="0"/>
<PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_B" VALUE="0"/>
<PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_A" VALUE="0"/>
<PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_B" VALUE="0"/>
<PARAMETER NAME="C_MUX_PIPELINE_STAGES" VALUE="0"/>
<PARAMETER NAME="C_HAS_SOFTECC_INPUT_REGS_A" VALUE="0"/>
<PARAMETER NAME="C_HAS_SOFTECC_OUTPUT_REGS_B" VALUE="0"/>
<PARAMETER NAME="C_USE_SOFTECC" VALUE="0"/>
<PARAMETER NAME="C_USE_ECC" VALUE="0"/>
<PARAMETER NAME="C_EN_ECC_PIPE" VALUE="0"/>
<PARAMETER NAME="C_READ_LATENCY_A" VALUE="1"/>
<PARAMETER NAME="C_READ_LATENCY_B" VALUE="1"/>
<PARAMETER NAME="C_HAS_INJECTERR" VALUE="0"/>
<PARAMETER NAME="C_SIM_COLLISION_CHECK" VALUE="ALL"/>
<PARAMETER NAME="C_COMMON_CLK" VALUE="0"/>
<PARAMETER NAME="C_DISABLE_WARN_BHV_COLL" VALUE="0"/>
<PARAMETER NAME="C_EN_SLEEP_PIN" VALUE="0"/>
<PARAMETER NAME="C_USE_URAM" VALUE="0"/>
<PARAMETER NAME="C_EN_RDADDRA_CHG" VALUE="0"/>
<PARAMETER NAME="C_EN_RDADDRB_CHG" VALUE="0"/>
<PARAMETER NAME="C_EN_DEEPSLEEP_PIN" VALUE="0"/>
<PARAMETER NAME="C_EN_SHUTDOWN_PIN" VALUE="0"/>
<PARAMETER NAME="C_EN_SAFETY_CKT" VALUE="1"/>
<PARAMETER NAME="C_DISABLE_WARN_BHV_RANGE" VALUE="0"/>
<PARAMETER NAME="C_COUNT_36K_BRAM" VALUE="2"/>
<PARAMETER NAME="C_COUNT_18K_BRAM" VALUE="0"/>
<PARAMETER NAME="C_EST_POWER_SUMMARY" VALUE="Estimated Power for IP : 10.7492 mW"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_blk_mem_gen_0_0"/>
<PARAMETER NAME="Interface_Type" VALUE="Native"/>
<PARAMETER NAME="AXI_Type" VALUE="AXI4_Full"/>
<PARAMETER NAME="AXI_Slave_Type" VALUE="Memory_Slave"/>
<PARAMETER NAME="Use_AXI_ID" VALUE="false"/>
<PARAMETER NAME="AXI_ID_Width" VALUE="4"/>
<PARAMETER NAME="Memory_Type" VALUE="True_Dual_Port_RAM"/>
<PARAMETER NAME="PRIM_type_to_Implement" VALUE="BRAM"/>
<PARAMETER NAME="Enable_32bit_Address" VALUE="true"/>
<PARAMETER NAME="ecctype" VALUE="No_ECC"/>
<PARAMETER NAME="ECC" VALUE="false"/>
<PARAMETER NAME="softecc" VALUE="false"/>
<PARAMETER NAME="EN_SLEEP_PIN" VALUE="false"/>
<PARAMETER NAME="EN_DEEPSLEEP_PIN" VALUE="false"/>
<PARAMETER NAME="EN_SHUTDOWN_PIN" VALUE="false"/>
<PARAMETER NAME="EN_ECC_PIPE" VALUE="false"/>
<PARAMETER NAME="RD_ADDR_CHNG_A" VALUE="false"/>
<PARAMETER NAME="RD_ADDR_CHNG_B" VALUE="false"/>
<PARAMETER NAME="Use_Error_Injection_Pins" VALUE="false"/>
<PARAMETER NAME="Error_Injection_Type" VALUE="Single_Bit_Error_Injection"/>
<PARAMETER NAME="Use_Byte_Write_Enable" VALUE="true"/>
<PARAMETER NAME="Byte_Size" VALUE="8"/>
<PARAMETER NAME="Algorithm" VALUE="Minimum_Area"/>
<PARAMETER NAME="Primitive" VALUE="8kx2"/>
<PARAMETER NAME="Assume_Synchronous_Clk" VALUE="false"/>
<PARAMETER NAME="Write_Width_A" VALUE="32"/>
<PARAMETER NAME="Write_Depth_A" VALUE="2048"/>
<PARAMETER NAME="Read_Width_A" VALUE="32"/>
<PARAMETER NAME="Operating_Mode_A" VALUE="WRITE_FIRST"/>
<PARAMETER NAME="Enable_A" VALUE="Use_ENA_Pin"/>
<PARAMETER NAME="Write_Width_B" VALUE="32"/>
<PARAMETER NAME="Read_Width_B" VALUE="32"/>
<PARAMETER NAME="Operating_Mode_B" VALUE="WRITE_FIRST"/>
<PARAMETER NAME="Enable_B" VALUE="Use_ENB_Pin"/>
<PARAMETER NAME="Register_PortA_Output_of_Memory_Primitives" VALUE="false"/>
<PARAMETER NAME="Register_PortA_Output_of_Memory_Core" VALUE="false"/>
<PARAMETER NAME="Use_REGCEA_Pin" VALUE="false"/>
<PARAMETER NAME="Register_PortB_Output_of_Memory_Primitives" VALUE="false"/>
<PARAMETER NAME="Register_PortB_Output_of_Memory_Core" VALUE="false"/>
<PARAMETER NAME="Use_REGCEB_Pin" VALUE="false"/>
<PARAMETER NAME="register_porta_input_of_softecc" VALUE="false"/>
<PARAMETER NAME="register_portb_output_of_softecc" VALUE="false"/>
<PARAMETER NAME="Pipeline_Stages" VALUE="0"/>
<PARAMETER NAME="Load_Init_File" VALUE="false"/>
<PARAMETER NAME="Coe_File" VALUE="no_coe_file_loaded"/>
<PARAMETER NAME="Fill_Remaining_Memory_Locations" VALUE="false"/>
<PARAMETER NAME="Remaining_Memory_Locations" VALUE="0"/>
<PARAMETER NAME="Use_RSTA_Pin" VALUE="true"/>
<PARAMETER NAME="Reset_Memory_Latch_A" VALUE="false"/>
<PARAMETER NAME="Reset_Priority_A" VALUE="CE"/>
<PARAMETER NAME="Output_Reset_Value_A" VALUE="0"/>
<PARAMETER NAME="Use_RSTB_Pin" VALUE="true"/>
<PARAMETER NAME="Reset_Memory_Latch_B" VALUE="false"/>
<PARAMETER NAME="Reset_Priority_B" VALUE="CE"/>
<PARAMETER NAME="Output_Reset_Value_B" VALUE="0"/>
<PARAMETER NAME="Reset_Type" VALUE="SYNC"/>
<PARAMETER NAME="Additional_Inputs_for_Power_Estimation" VALUE="false"/>
<PARAMETER NAME="Port_A_Clock" VALUE="100"/>
<PARAMETER NAME="Port_A_Write_Rate" VALUE="50"/>
<PARAMETER NAME="Port_B_Clock" VALUE="100"/>
<PARAMETER NAME="Port_B_Write_Rate" VALUE="50"/>
<PARAMETER NAME="Port_A_Enable_Rate" VALUE="100"/>
<PARAMETER NAME="Port_B_Enable_Rate" VALUE="100"/>
<PARAMETER NAME="Collision_Warnings" VALUE="ALL"/>
<PARAMETER NAME="Disable_Collision_Warnings" VALUE="false"/>
<PARAMETER NAME="Disable_Out_of_Range_Warnings" VALUE="false"/>
<PARAMETER NAME="use_bram_block" VALUE="BRAM_Controller"/>
<PARAMETER NAME="MEM_FILE" VALUE="NONE"/>
<PARAMETER NAME="CTRL_ECC_ALGO" VALUE="NONE"/>
<PARAMETER NAME="EN_SAFETY_CKT" VALUE="true"/>
<PARAMETER NAME="READ_LATENCY_A" VALUE="1"/>
<PARAMETER NAME="READ_LATENCY_B" VALUE="1"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT DIR="I" NAME="clka" SIGIS="clk" SIGNAME="spiflash_0_romcode_Clk_A">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_Clk_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="rsta" SIGIS="rst" SIGNAME="spiflash_0_romcode_Rst_A">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_Rst_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ena" SIGIS="undef" SIGNAME="spiflash_0_romcode_EN_A">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_EN_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="wea" RIGHT="0" SIGIS="undef" SIGNAME="spiflash_0_romcode_WEN_A">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_WEN_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="addra" RIGHT="0" SIGIS="undef" SIGNAME="spiflash_0_romcode_Addr_A">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_Addr_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="dina" RIGHT="0" SIGIS="undef" SIGNAME="spiflash_0_romcode_Din_A">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_Din_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="douta" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_douta">
<CONNECTIONS>
<CONNECTION INSTANCE="spiflash_0" PORT="romcode_Dout_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="clkb" SIGIS="clk" SIGNAME="blk_mem_gen_0_clkb">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_Clk_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="rstb" SIGIS="rst" SIGNAME="blk_mem_gen_0_rstb">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_Rst_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="enb" SIGIS="undef" SIGNAME="blk_mem_gen_0_enb">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_EN_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="web" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_web">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_WEN_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="addrb" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_addrb">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_Addr_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="dinb" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_dinb">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_Din_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="doutb" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_doutb">
<CONNECTIONS>
<CONNECTION INSTANCE="read_romcode_0" PORT="internal_bram_Dout_A"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="rsta_busy" SIGIS="undef"/>
<PORT DIR="O" NAME="rstb_busy" SIGIS="undef"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="__NOC__" NAME="BRAM_PORTA" TYPE="TARGET" VLNV="xilinx.com:interface:bram:1.0">
<PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
<PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
<PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
<PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="READ_LATENCY" VALUE="1"/>
<PORTMAPS>
<PORTMAP LOGICAL="ADDR" PHYSICAL="addra"/>
<PORTMAP LOGICAL="CLK" PHYSICAL="clka"/>
<PORTMAP LOGICAL="DIN" PHYSICAL="dina"/>
<PORTMAP LOGICAL="DOUT" PHYSICAL="douta"/>
<PORTMAP LOGICAL="EN" PHYSICAL="ena"/>
<PORTMAP LOGICAL="RST" PHYSICAL="rsta"/>
<PORTMAP LOGICAL="WE" PHYSICAL="wea"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="read_romcode_0_internal_bram_PORTA" NAME="BRAM_PORTB" TYPE="TARGET" VLNV="xilinx.com:interface:bram:1.0">
<PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
<PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
<PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
<PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="READ_LATENCY" VALUE="1"/>
<PORTMAPS>
<PORTMAP LOGICAL="ADDR" PHYSICAL="addrb"/>
<PORTMAP LOGICAL="CLK" PHYSICAL="clkb"/>
<PORTMAP LOGICAL="DIN" PHYSICAL="dinb"/>
<PORTMAP LOGICAL="DOUT" PHYSICAL="doutb"/>
<PORTMAP LOGICAL="EN" PHYSICAL="enb"/>
<PORTMAP LOGICAL="RST" PHYSICAL="rstb"/>
<PORTMAP LOGICAL="WE" PHYSICAL="web"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="1" FULLNAME="/caravel_0" HWVERSION="1.0" INSTANCE="caravel_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="caravel" VLNV="xilinx.com:module_ref:caravel:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="USER_PROJECT_ID" VALUE="0x00000000"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_caravel_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT DIR="IO" NAME="gpio" SIGIS="undef"/>
<PORT DIR="I" LEFT="37" NAME="mprj_i" RIGHT="0" SIGIS="undef" SIGNAME="caravel_ps_0_mprj_in">
<CONNECTIONS>
<CONNECTION INSTANCE="caravel_ps_0" PORT="mprj_in"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="37" NAME="mprj_o" RIGHT="0" SIGIS="undef" SIGNAME="caravel_0_mprj_o">
<CONNECTIONS>
<CONNECTION INSTANCE="caravel_ps_0" PORT="mprj_out"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="37" NAME="mprj_en" RIGHT="0" SIGIS="undef" SIGNAME="caravel_0_mprj_en">
<CONNECTIONS>
<CONNECTION INSTANCE="caravel_ps_0" PORT="mprj_en"/>
</CONNECTIONS>