diff --git a/README.md b/README.md
index 985e7c8f1b98dc..822c8ae9c6f707 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,7 @@
 # 欢迎来到 Lean 的 LEDE 源码仓库
 
+为国产龙芯 LOONGSON SoC loongarch64 / 飞腾 Phytium 腾锐2000 系列架构添加支持
+
 I18N: [English](README_EN.md) | [简体中文](README.md) | [日本語](README_JA.md)
 
 ## 官方讨论群
diff --git a/config/Config-images.in b/config/Config-images.in
index 50b88755621517..40b322474a142f 100644
--- a/config/Config-images.in
+++ b/config/Config-images.in
@@ -198,20 +198,21 @@ menu "Target Images"
 			default ""
 
 	config GRUB_IMAGES
-		bool "Build GRUB images (Linux x86 or x86_64 host only)"
+		bool "Build GRUB images"
 		depends on TARGET_x86
 		depends on TARGET_ROOTFS_EXT4FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS
 		select PACKAGE_grub2
 		default n
 
 	config GRUB_EFI_IMAGES
-		bool "Build GRUB EFI images (Linux x86 or x86_64 host only)"
-		depends on TARGET_x86 || TARGET_armvirt
+		bool "Build GRUB EFI images"
+		depends on TARGET_x86 || TARGET_armvirt || TARGET_loongarch64 || TARGET_phytium_armv8
 		depends on TARGET_ROOTFS_EXT4FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS
 		select PACKAGE_grub2 if TARGET_x86
 		select PACKAGE_grub2-efi if TARGET_x86
 		select PACKAGE_grub2-bios-setup if TARGET_x86
 		select PACKAGE_grub2-efi-arm if TARGET_armvirt
+		select PACKAGE_grub2-efi-arm if TARGET_phytium_armv8
 		select PACKAGE_kmod-fs-vfat
 		default y
 
@@ -276,7 +277,7 @@ menu "Target Images"
 
 	config VMDK_IMAGES
 		bool "Build VMware image files (VMDK)"
-		depends on TARGET_x86 || TARGET_armvirt
+		depends on TARGET_x86 || TARGET_armvirt || TARGET_loongarch64
 		depends on GRUB_IMAGES || GRUB_EFI_IMAGES
 		default y
 		select PACKAGE_kmod-e1000
@@ -289,7 +290,7 @@ menu "Target Images"
 
 	config TARGET_IMAGES_GZIP
 		bool "GZip images"
-		depends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armvirt || TARGET_malta
+		depends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armvirt || TARGET_loongarch64 || TARGET_malta
 		default y
 
 	comment "Image Options"
@@ -308,6 +309,7 @@ menu "Target Images"
 	config TARGET_ROOTFS_PARTSIZE
 		int "Root filesystem partition size (in MiB)"
 		depends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS
+		default 232 if TARGET_loongarch64
 		default 400 if TARGET_x86
 		default 160
 		help
diff --git a/include/kernel-5.10 b/include/kernel-5.10
index 0a36292558efbf..bf9a21a7bd67e6 100644
--- a/include/kernel-5.10
+++ b/include/kernel-5.10
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.10 = .205
-LINUX_KERNEL_HASH-5.10.205 = c55217a80d74f81b83116289a8bfe4302293390b45aeabb76f64814920788863
+LINUX_VERSION-5.10 = .209
+LINUX_KERNEL_HASH-5.10.209 = 44e22fad647c638726a8eae23703c4263bead612d17c89ca7ad7ab32b5ce88d5
diff --git a/include/kernel-5.15 b/include/kernel-5.15
index 2948d10bdc34b5..d93ae194b8aa1c 100644
--- a/include/kernel-5.15
+++ b/include/kernel-5.15
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.15 = .145
-LINUX_KERNEL_HASH-5.15.145 = b2a49d87605f3a9491581150315e22337c1afb599efc1e2737481be3a2d6d620
+LINUX_VERSION-5.15 = .148
+LINUX_KERNEL_HASH-5.15.148 = c48575c97fd9f4767cbe50a13b1b2b40ee42830aba3182fabd35a03259a6e5d8
diff --git a/include/kernel-5.4 b/include/kernel-5.4
index a6b44269ca33d2..fa9a64ed94100f 100644
--- a/include/kernel-5.4
+++ b/include/kernel-5.4
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.4 = .265
-LINUX_KERNEL_HASH-5.4.265 = 4dae99e49f466d4689e128ec023754908147159d7462019a83c7da1f25df9b15
+LINUX_VERSION-5.4 = .268
+LINUX_KERNEL_HASH-5.4.268 = afc8aca6cb56fea489f6508bc24357df1cf8a8f3d7dcfbcccd94b7f968492620
diff --git a/include/kernel-6.1 b/include/kernel-6.1
index b42886811e3be7..b6c55613b654a9 100644
--- a/include/kernel-6.1
+++ b/include/kernel-6.1
@@ -1,2 +1,2 @@
-LINUX_VERSION-6.1 = .69
-LINUX_KERNEL_HASH-6.1.69 = 7e3d2694d18ce502068cc88a430da809abbd17d0773268524ebece442612b541
+LINUX_VERSION-6.1 = .75
+LINUX_KERNEL_HASH-6.1.75 = 6cd19410330c13ec4c18fd28a83d3e40fc12a152815fb7c3e1b0764329093a56
diff --git a/include/kernel-6.6 b/include/kernel-6.6
new file mode 100644
index 00000000000000..3036dc4b32cc6e
--- /dev/null
+++ b/include/kernel-6.6
@@ -0,0 +1,2 @@
+LINUX_VERSION-6.6 = .14
+LINUX_KERNEL_HASH-6.6.14 = fbe96b2db3f962cd2a96a849d554300e7a4555995160082d4f323c2a1dfa1584
diff --git a/include/kernel.mk b/include/kernel.mk
index 3012eb899352e2..9bac47718a3768 100644
--- a/include/kernel.mk
+++ b/include/kernel.mk
@@ -86,6 +86,8 @@ else ifneq (,$(findstring $(ARCH) , arceb ))
   LINUX_KARCH := arc
 else ifneq (,$(findstring $(ARCH) , armeb ))
   LINUX_KARCH := arm
+else ifneq (,$(findstring $(ARCH) , loongarch64 ))
+  LINUX_KARCH := loongarch
 else ifneq (,$(findstring $(ARCH) , mipsel mips64 mips64el ))
   LINUX_KARCH := mips
 else ifneq (,$(findstring $(ARCH) , powerpc64 ))
diff --git a/include/site/loongarch64 b/include/site/loongarch64
new file mode 100644
index 00000000000000..b8d581d448edc9
--- /dev/null
+++ b/include/site/loongarch64
@@ -0,0 +1,30 @@
+#!/bin/sh
+. $TOPDIR/include/site/linux
+ac_cv_c_littleendian=${ac_cv_c_littleendian=yes}
+ac_cv_c_bigendian=${ac_cv_c_bigendian=no}
+
+ac_cv_sizeof___int64=0
+ac_cv_sizeof_char=1
+ac_cv_sizeof_int=4
+ac_cv_sizeof_int16_t=2
+ac_cv_sizeof_int32_t=4
+ac_cv_sizeof_int64_t=8
+ac_cv_sizeof_long_int=8
+ac_cv_sizeof_long_long=8
+ac_cv_sizeof_long=8
+ac_cv_sizeof_off_t=8
+ac_cv_sizeof_short_int=2
+ac_cv_sizeof_short=2
+ac_cv_sizeof_size_t=8
+ac_cv_sizeof_ssize_t=8
+ac_cv_sizeof_u_int16_t=2
+ac_cv_sizeof_u_int32_t=4
+ac_cv_sizeof_u_int64_t=8
+ac_cv_sizeof_uint16_t=2
+ac_cv_sizeof_uint32_t=4
+ac_cv_sizeof_uint64_t=8
+ac_cv_sizeof_unsigned_int=4
+ac_cv_sizeof_unsigned_long=8
+ac_cv_sizeof_unsigned_long_long=8
+ac_cv_sizeof_unsigned_short=2
+ac_cv_sizeof_void_p=8
diff --git a/include/target.mk b/include/target.mk
index e579fdb1c904d9..426801b922fac4 100644
--- a/include/target.mk
+++ b/include/target.mk
@@ -262,6 +262,11 @@ ifeq ($(DUMP),1)
     CPU_TYPE ?= riscv64
     CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc
   endif
+  ifeq ($(ARCH),loongarch64)
+    CPU_TYPE ?= generic
+    CPU_CFLAGS := -O2 -pipe
+    CPU_CFLAGS_generic:=-march=loongarch64
+  endif
   ifneq ($(CPU_TYPE),)
     ifndef CPU_CFLAGS_$(CPU_TYPE)
       $(warning CPU_TYPE "$(CPU_TYPE)" doesn't correspond to a known type)
diff --git a/package/boot/grub2/Makefile b/package/boot/grub2/Makefile
index 97466dbb9c3e9a..a33470b3a5eba3 100644
--- a/package/boot/grub2/Makefile
+++ b/package/boot/grub2/Makefile
@@ -6,12 +6,12 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=grub
-PKG_VERSION:=2.06
-PKG_RELEASE:=$(AUTORELEASE)
+PKG_VERSION:=2.12
+PKG_RELEASE:=6
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@GNU/grub
-PKG_HASH:=b79ea44af91b93d17cd3fe80bdae6ed43770678a9a5ae192ccea803ebb657ee1
+PKG_HASH:=f3c97391f7c4eaa677a78e090c7e97e6dc47b16f655f04683ebd37bef7fe0faa
 
 PKG_LICENSE:=GPL-3.0-or-later
 PKG_CPE_ID:=cpe:/a:gnu:grub2
@@ -25,6 +25,7 @@ ifneq ($(BUILD_VARIANT),none)
 endif
 
 PKG_FLAGS:=nonshared
+PKG_BUILD_FLAGS:=no-gc-sections no-lto no-mold
 
 include $(INCLUDE_DIR)/host-build.mk
 include $(INCLUDE_DIR)/package.mk
@@ -40,7 +41,9 @@ endef
 
 Package/grub2=$(call Package/grub2/Default,x86,pc)
 Package/grub2-efi=$(call Package/grub2/Default,x86,efi)
-Package/grub2-efi-arm=$(call Package/grub2/Default,armvirt,efi)
+Package/grub2-efi-arm=$(call Package/grub2/Default,armsr,efi)
+Package/grub2-efi-arm=$(call Package/grub2/Default,phytium_armv8,efi)
+Package/grub2-efi-loongarch64=$(call Package/grub2/Default,loongarch64,efi)
 
 define Package/grub2-editenv
   CATEGORY:=Utilities
@@ -127,14 +130,14 @@ define Package/grub2/install
 		-O i386-pc \
 		-c $(PKG_BUILD_DIR)/grub-early.cfg \
 		-o $(STAGING_DIR_IMAGE)/grub2/gpt-core.img \
-		at_keyboard biosdisk boot chain configfile fat linux ls part_gpt reboot search serial vga
+		at_keyboard biosdisk boot chain configfile fat linux ls part_gpt reboot search serial test vga
 	$(STAGING_DIR_HOST)/bin/grub-mkimage \
 		-d $(PKG_BUILD_DIR)/grub-core \
 		-p /boot/grub \
 		-O i386-pc \
 		-c ./files/grub-early.cfg \
 		-o $(STAGING_DIR_IMAGE)/grub2/generic-core.img \
-		at_keyboard biosdisk boot chain configfile ext2 linux ls part_msdos reboot search serial vga
+		at_keyboard biosdisk boot chain configfile ext2 linux ls part_msdos reboot search serial test vga
 	$(STAGING_DIR_HOST)/bin/grub-mkimage \
 		-d $(PKG_BUILD_DIR)/grub-core \
 		-p /boot/grub \
@@ -159,7 +162,7 @@ define Package/grub2-efi/install
 		-O $(CONFIG_ARCH)-efi \
 		-c $(PKG_BUILD_DIR)/grub-early.cfg \
 		-o $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_x86_64),x64,ia32).efi \
-		at_keyboard boot chain configfile fat linux ls part_gpt reboot serial efi_gop efi_uga
+		at_keyboard boot chain configfile fat linux ls part_gpt reboot serial test efi_gop efi_uga
 	$(STAGING_DIR_HOST)/bin/grub-mkimage \
 		-d $(PKG_BUILD_DIR)/grub-core \
 		-p /boot/grub \
@@ -178,14 +181,29 @@ define Package/grub2-efi-arm/install
 		-O arm$(if $(CONFIG_aarch64),64,)-efi \
 		-c $(PKG_BUILD_DIR)/grub-early.cfg \
 		-o $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_aarch64),aa64,arm).efi \
-		boot chain configfile fat linux ls part_gpt reboot search search_fs_uuid search_label serial efi_gop lsefi minicmd
+		boot chain configfile fat linux ls part_gpt part_msdos reboot search \
+		search_fs_uuid search_label serial efi_gop lsefi minicmd ext2
 	$(STAGING_DIR_HOST)/bin/grub-mkimage \
 		-d $(PKG_BUILD_DIR)/grub-core \
 		-p /boot/grub \
 		-O arm$(if $(CONFIG_aarch64),64,)-efi \
 		-c ./files/grub-early.cfg \
 		-o $(STAGING_DIR_IMAGE)/grub2/iso-bootaa$(if $(CONFIG_aarch64),aa64,arm).efi \
-		boot chain configfile fat iso9660 linux ls lsefi minicmd part_msdos part_gpt reboot serial test efi_gop
+		boot chain configfile fat iso9660 linux ls lsefi minicmd part_msdos part_gpt \
+		reboot serial test efi_gop
+endef
+
+define Package/grub2-efi-loongarch64/install
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2
+	cp ./files/grub-early-gpt.cfg $(PKG_BUILD_DIR)/grub-early.cfg
+	$(STAGING_DIR_HOST)/bin/grub-mkimage \
+		-d $(PKG_BUILD_DIR)/grub-core \
+		-p /boot/grub \
+		-O loongarch64-efi \
+		-c $(PKG_BUILD_DIR)/grub-early.cfg \
+		-o $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi \
+		boot chain configfile fat linux ls lsefi minicmd part_gpt part_msdos reboot search \
+		search_fs_uuid search_label serial efi_gop all_video gfxterm ext2
 endef
 
 
@@ -203,5 +221,6 @@ $(eval $(call HostBuild))
 $(eval $(call BuildPackage,grub2))
 $(eval $(call BuildPackage,grub2-efi))
 $(eval $(call BuildPackage,grub2-efi-arm))
+$(eval $(call BuildPackage,grub2-efi-loongarch64))
 $(eval $(call BuildPackage,grub2-editenv))
 $(eval $(call BuildPackage,grub2-bios-setup))
diff --git a/package/boot/grub2/files/grub-early-gpt.cfg b/package/boot/grub2/files/grub-early-gpt.cfg
index 483e2de5aac5b6..c295d1f7d775ec 100644
--- a/package/boot/grub2/files/grub-early-gpt.cfg
+++ b/package/boot/grub2/files/grub-early-gpt.cfg
@@ -1,2 +1,2 @@
 search --set=root --label kernel
-configfile ($root)/boot/grub/grub.cfg
+configfile ($root)/efi/openwrt/grub.cfg
diff --git a/package/boot/grub2/patches/001-add-missing-extra_deps-list.patch b/package/boot/grub2/patches/001-add-missing-extra_deps-list.patch
new file mode 100644
index 00000000000000..6261d7ad34e912
--- /dev/null
+++ b/package/boot/grub2/patches/001-add-missing-extra_deps-list.patch
@@ -0,0 +1,36 @@
+From 4d4dae6a52b1749642261a15f5dcc1e3d4150b36 Mon Sep 17 00:00:00 2001
+From: Julien Olivain <ju.o@free.fr>
+Date: Fri, 22 Dec 2023 19:02:53 +0100
+Subject: [PATCH] Add missing grub-core/extra_deps.lst file in release tarball
+
+A file is missing in the grub-2.12 release tarballs (both .gz and .xz).
+See [1]. The issue was reported in [2] and fixed upstream in [3].
+
+This patch adds the missing file, on top of the release tarball. This
+patch won't apply on upstream git, since the file is present in the
+source repository. Since the issue is fixed upstream in [3], it is
+expected upcoming releases tarballs will include the file.
+
+The file content was fetched from the upstream git repo:
+https://git.savannah.gnu.org/gitweb/?p=grub.git;a=blob_plain;f=grub-core/extra_deps.lst;hb=refs/tags/grub-2.12
+
+[1] https://ftp.gnu.org/gnu/grub/grub-2.12.tar.xz
+[2] https://lists.gnu.org/archive/html/grub-devel/2023-12/msg00054.html
+[3] https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
+
+Signed-off-by: Julien Olivain <ju.o@free.fr>
+Upstream: Fixed by: https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
+---
+ grub-core/extra_deps.lst | 1 +
+ 1 file changed, 1 insertion(+)
+ create mode 100644 grub-core/extra_deps.lst
+
+diff --git a/grub-core/extra_deps.lst b/grub-core/extra_deps.lst
+new file mode 100644
+index 0000000..f44ad6a
+--- /dev/null
++++ b/grub-core/extra_deps.lst
+@@ -0,0 +1 @@
++depends bli part_gpt
+-- 
+2.43.0
diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic
index d797bfc1f12584..17c8141810c84a 100644
--- a/package/boot/uboot-envtools/files/mediatek_filogic
+++ b/package/boot/uboot-envtools/files/mediatek_filogic
@@ -34,6 +34,10 @@ bananapi,bpi-r3)
 		;;
 	esac
 	;;
+cetron,ct3003|\
+imou,lc-hx3001)
+	ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
+	;;
 glinet,gl-mt2500|\
 glinet,gl-mt6000)
 	local envdev=$(find_mmc_part "u-boot-env")
diff --git a/package/devel/binutils/Makefile b/package/devel/binutils/Makefile
index 75fdd320cdbb98..5166f267347f73 100644
--- a/package/devel/binutils/Makefile
+++ b/package/devel/binutils/Makefile
@@ -8,16 +8,16 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=binutils
-PKG_VERSION:=2.38
+PKG_VERSION:=2.40
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=@GNU/binutils
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_VERSION:=$(PKG_VERSION)
-PKG_HASH:=e316477a914f567eccc34d5d29785b8b0f5a10208d36bbacedcc39048ecfe024
+PKG_HASH:=0f8a4c272d7f17f369ded10a4aca28b8e304828e95526da482b0ccc4dfc9d8e1
 
 PKG_FIXUP:=patch-libtool
-PKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof binutils ld libiberty gold intl
+PKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof gprofng binutils ld libiberty gold intl libctf libsframe
 PKG_REMOVE_FILES:=libtool.m4
 PKG_INSTALL:=1
 
@@ -87,7 +87,11 @@ CONFIGURE_ARGS += \
 	--enable-shared \
 	--enable-install-libiberty \
 	--enable-install-libbfd \
-	--enable-install-libctf
+	--enable-install-libctf \
+	--with-system-zlib \
+	--without-zstd \
+	--without-msgpack \
+	--disable-gprofng
 
 define Build/Install
 	$(call Build/Install/Default)
@@ -105,6 +109,7 @@ endef
 define Package/libbfd/install
 	$(INSTALL_DIR) $(1)/usr/lib
 	$(CP) $(PKG_INSTALL_DIR)/usr/lib/libbfd*.so* $(1)/usr/lib/
+	$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsframe*.so* $(1)/usr/lib/
 endef
 
 define Package/libctf/install
diff --git a/package/devel/binutils/patches/001-replace-attribute_const.patch b/package/devel/binutils/patches/001-replace-attribute_const.patch
new file mode 100644
index 00000000000000..5fd855efd16423
--- /dev/null
+++ b/package/devel/binutils/patches/001-replace-attribute_const.patch
@@ -0,0 +1,88 @@
+Fix this compile error:
+----------------------
+./../common/cpuid.c:27:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '__get_cpuid'
+   27 | __get_cpuid (unsigned int op ATTRIBUTE_UNUSED, unsigned int *eax,
+      | ^~~~~~~~~~~
+----------------------
+
+and this error:
+----------------------
+unwind.c: In function '__collector_ext_return_address':
+unwind.c:236:34: error: '__u64' undeclared (first use in this function)
+  236 |       context->uc_mcontext.sp = (__u64) __builtin_frame_address(0); \
+      |                                  ^~~~~
+unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
+  490 |   FILL_CONTEXT ((&context));
+
+----------------------
+--- a/gprofng/common/cpuid.c
++++ b/gprofng/common/cpuid.c
+@@ -23,7 +23,7 @@
+ #elif defined(__aarch64__)
+ #define ATTRIBUTE_UNUSED __attribute__((unused))
+ 
+-static inline uint_t __attribute_const__
++static inline uint_t __attribute__((__const__))
+ __get_cpuid (unsigned int op ATTRIBUTE_UNUSED, unsigned int *eax,
+ 	     unsigned int *ebx ATTRIBUTE_UNUSED,
+ 	     unsigned int *ecx ATTRIBUTE_UNUSED, unsigned int *edx ATTRIBUTE_UNUSED)
+--- a/gprofng/libcollector/unwind.c
++++ b/gprofng/libcollector/unwind.c
+@@ -233,7 +233,7 @@ memory_error_func (int status ATTRIBUTE_
+ #elif ARCH(Aarch64)
+ #define FILL_CONTEXT(context) \
+     { CALL_UTIL (getcontext) (context);  \
+-      context->uc_mcontext.sp = (__u64) __builtin_frame_address(0); \
++      context->uc_mcontext.sp = (uint64_t) __builtin_frame_address(0); \
+     }
+ 
+ #endif /* ARCH() */
+@@ -4579,11 +4579,11 @@ stack_unwind (char *buf, int size, void
+   if (buf && bptr && eptr && context && size + mode > 0)
+     getByteInstruction ((unsigned char *) eptr);
+   int ind = 0;
+-  __u64 *lbuf = (void *) buf;
+-  int lsize = size / sizeof (__u64);
+-  __u64 pc = context->uc_mcontext.pc;
+-  __u64 sp = context->uc_mcontext.sp;
+-  __u64 stack_base;
++  uint64_t *lbuf = (void *) buf;
++  int lsize = size / sizeof (uint64_t);
++  uint64_t pc = context->uc_mcontext.pc;
++  uint64_t sp = context->uc_mcontext.sp;
++  uint64_t stack_base;
+   unsigned long tbgn = 0;
+   unsigned long tend = 0;
+ 
+@@ -4594,7 +4594,7 @@ stack_unwind (char *buf, int size, void
+     {
+       stack_base = sp + 0x100000;
+       if (stack_base < sp)  // overflow
+-	stack_base = (__u64) -1;
++	stack_base = (uint64_t) -1;
+     }
+   DprintfT (SP_DUMP_UNWIND,
+     "unwind.c:%d stack_unwind %2d pc=0x%llx  sp=0x%llx  stack_base=0x%llx\n",
+@@ -4625,17 +4625,17 @@ stack_unwind (char *buf, int size, void
+ 		      __LINE__, (unsigned long) sp);
+ 	    break;
+ 	  }
+-      pc = ((__u64 *) sp)[1];
+-      __u64 old_sp = sp;
+-      sp = ((__u64 *) sp)[0];
++      pc = ((uint64_t *) sp)[1];
++      uint64_t old_sp = sp;
++      sp = ((uint64_t *) sp)[0];
+       if (sp < old_sp)
+ 	break;
+     }
+   if (ind >= lsize)
+     {
+       ind = lsize - 1;
+-      lbuf[ind++] = (__u64) SP_TRUNC_STACK_MARKER;
++      lbuf[ind++] = (uint64_t) SP_TRUNC_STACK_MARKER;
+     }
+-  return ind * sizeof (__u64);
++  return ind * sizeof (uint64_t);
+ }
+ #endif /* ARCH() */
diff --git a/package/firmware/linux-firmware/Makefile b/package/firmware/linux-firmware/Makefile
index ef6cd075de4548..79341c30cb4a68 100644
--- a/package/firmware/linux-firmware/Makefile
+++ b/package/firmware/linux-firmware/Makefile
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=linux-firmware
-PKG_VERSION:=20230804
+PKG_VERSION:=20231211
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
-PKG_HASH:=88d46c543847ee3b03404d4941d91c92974690ee1f6fdcbee9cef3e5f97db688
+PKG_HASH:=96af7e4b5eabd37869cdb3dcbb7ab36911106d39b76e799fa1caab16a9dbe8bb
 
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 
diff --git a/package/firmware/linux-firmware/airoha.mk b/package/firmware/linux-firmware/airoha.mk
new file mode 100644
index 00000000000000..627541ba9600bb
--- /dev/null
+++ b/package/firmware/linux-firmware/airoha.mk
@@ -0,0 +1,8 @@
+Package/en8811h-firmware = $(call Package/firmware-default,Airoha EN8811H PHY firmware)
+define Package/en8811h-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/airoha
+	$(CP) \
+		$(PKG_BUILD_DIR)/airoha/*.bin \
+		$(1)/lib/firmware/airoha
+endef
+$(eval $(call BuildPackage,en8811h-firmware))
diff --git a/package/firmware/linux-firmware/broadcom.mk b/package/firmware/linux-firmware/broadcom.mk
index 83fbb7da1f21ba..683576d5a4e438 100644
--- a/package/firmware/linux-firmware/broadcom.mk
+++ b/package/firmware/linux-firmware/broadcom.mk
@@ -1,3 +1,16 @@
+Package/brcmfmac-firmware-4339-sdio = $(call Package/firmware-default,Broadcom 4339 FullMAC SDIO firmware)
+define Package/brcmfmac-firmware-4339-sdio/install
+	$(INSTALL_DIR) $(1)/lib/firmware/cypress
+	$(INSTALL_DATA) \
+		$(PKG_BUILD_DIR)/cypress/cyfmac4339-sdio.bin \
+		$(1)/lib/firmware/cypress/
+	$(INSTALL_DIR) $(1)/lib/firmware/brcm
+	$(LN) \
+		../cypress/cyfmac4339-sdio.bin \
+		$(1)/lib/firmware/brcm/brcmfmac4339-sdio.bin
+endef
+$(eval $(call BuildPackage,brcmfmac-firmware-4339-sdio))
+
 Package/brcmfmac-firmware-43602a1-pcie = $(call Package/firmware-default,Broadcom 43602a1 FullMAC PCIe firmware)
 define Package/brcmfmac-firmware-43602a1-pcie/install
 	$(INSTALL_DIR) $(1)/lib/firmware/brcm
diff --git a/package/firmware/linux-firmware/mellanox.mk b/package/firmware/linux-firmware/mellanox.mk
new file mode 100644
index 00000000000000..039c7deb105651
--- /dev/null
+++ b/package/firmware/linux-firmware/mellanox.mk
@@ -0,0 +1,9 @@
+Package/mlxsw_spectrum-firmware = $(call Package/firmware-default,Mellanox Spectrum firmware)
+define Package/mlxsw_spectrum-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/mellanox
+	$(CP) \
+		$(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum-*.mfa2 \
+		$(1)/lib/firmware/mellanox
+endef
+
+$(eval $(call BuildPackage,mlxsw_spectrum-firmware))
diff --git a/package/firmware/linux-firmware/realtek.mk b/package/firmware/linux-firmware/realtek.mk
index 37ce22938b1958..88d44a2b4ae899 100644
--- a/package/firmware/linux-firmware/realtek.mk
+++ b/package/firmware/linux-firmware/realtek.mk
@@ -146,6 +146,13 @@ define Package/rtl8822ce-firmware/install
 endef
 $(eval $(call BuildPackage,rtl8822ce-firmware))
 
+Package/rtl8851be-firmware = $(call Package/firmware-default,RealTek RTL8851BE firmware)
+define Package/rtl8851be-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/rtw89
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8851b_fw.bin $(1)/lib/firmware/rtw89
+endef
+$(eval $(call BuildPackage,rtl8851be-firmware))
+
 Package/rtl8852ae-firmware = $(call Package/firmware-default,RealTek RTL8852AE firmware)
 define Package/rtl8852ae-firmware/install
 	$(INSTALL_DIR) $(1)/lib/firmware/rtw89
@@ -157,6 +164,7 @@ Package/rtl8852be-firmware = $(call Package/firmware-default,RealTek RTL8852BE f
 define Package/rtl8852be-firmware/install
 	$(INSTALL_DIR) $(1)/lib/firmware/rtw89
 	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852b_fw.bin $(1)/lib/firmware/rtw89
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852b_fw-1.bin $(1)/lib/firmware/rtw89
 endef
 $(eval $(call BuildPackage,rtl8852be-firmware))
 
diff --git a/package/firmware/photonicat-firmware/Makefile b/package/firmware/photonicat-firmware/Makefile
new file mode 100644
index 00000000000000..2245c0f1cfe7e5
--- /dev/null
+++ b/package/firmware/photonicat-firmware/Makefile
@@ -0,0 +1,28 @@
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=photonicat-firmware
+PKG_RELEASE:=1
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/photonicat-firmware
+  SECTION:=firmware
+  CATEGORY:=Firmware
+  TITLE:=Photonicat WiFi Firmware
+  DEPENDS:=@TARGET_rockchip_armv8
+endef
+
+define Build/Compile
+endef
+
+define Package/photonicat-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9377/hw1.0
+	$(INSTALL_DATA) \
+		./files/board.bin \
+		$(1)/lib/firmware/ath10k/QCA9377/hw1.0/board.bin
+	$(INSTALL_DATA) \
+		./files/firmware-sdio-5.bin \
+		$(1)/lib/firmware/ath10k/QCA9377/hw1.0/firmware-sdio-5.bin
+endef
+
+$(eval $(call BuildPackage,photonicat-firmware))
diff --git a/package/firmware/photonicat-firmware/files/board.bin b/package/firmware/photonicat-firmware/files/board.bin
new file mode 100644
index 00000000000000..cab5157872c4a8
Binary files /dev/null and b/package/firmware/photonicat-firmware/files/board.bin differ
diff --git a/package/firmware/photonicat-firmware/files/firmware-sdio-5.bin b/package/firmware/photonicat-firmware/files/firmware-sdio-5.bin
new file mode 100644
index 00000000000000..c90f7229bc3431
Binary files /dev/null and b/package/firmware/photonicat-firmware/files/firmware-sdio-5.bin differ
diff --git a/package/kernel/bpf-headers/Makefile b/package/kernel/bpf-headers/Makefile
index 733f3586727082..5efd2e1cf0fb74 100644
--- a/package/kernel/bpf-headers/Makefile
+++ b/package/kernel/bpf-headers/Makefile
@@ -19,7 +19,7 @@ include $(INCLUDE_DIR)/kernel-$(PKG_PATCHVER)
 
 PKG_VERSION:=$(PKG_PATCHVER)$(strip $(LINUX_VERSION-$(PKG_PATCHVER)))
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
-PKG_SOURCE_URL:=$(LINUX_SITE)
+PKG_SOURCE_URL:=@KERNEL/linux/kernel/v$(word 1,$(subst ., ,$(PKG_PATCHVER))).x
 PKG_HASH:=$(LINUX_KERNEL_HASH-$(strip $(PKG_VERSION)))
 PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/bpf-headers/$(PKG_NAME)-$(PKG_VERSION)
 
diff --git a/package/kernel/cryptodev-linux/Makefile b/package/kernel/cryptodev-linux/Makefile
index 0c1f63a6055a93..0b794a3cd9801f 100644
--- a/package/kernel/cryptodev-linux/Makefile
+++ b/package/kernel/cryptodev-linux/Makefile
@@ -10,12 +10,12 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=cryptodev-linux
-PKG_VERSION:=1.12
+PKG_VERSION:=1.13
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=https://codeload.github.com/$(PKG_NAME)/$(PKG_NAME)/tar.gz/$(PKG_NAME)-$(PKG_VERSION)?
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_HASH:=f51c2254749233b1b1d7ec9445158bd709f124f88e1c650fe2faac83c3a81938
+PKG_HASH:=33b7915c46eb39a37110e88c681423c0dd0df25d784b6e1475ac3196367f0db5
 PKG_LICENSE:=GPL-2.0
 PKG_LICENSE_FILES:=COPYING
 
diff --git a/package/kernel/cryptodev-linux/patches/0001-cryptodev_verbosity-fix-build-for-linux-6.4.patch b/package/kernel/cryptodev-linux/patches/0001-cryptodev_verbosity-fix-build-for-linux-6.4.patch
new file mode 100644
index 00000000000000..390faec9c29c1b
--- /dev/null
+++ b/package/kernel/cryptodev-linux/patches/0001-cryptodev_verbosity-fix-build-for-linux-6.4.patch
@@ -0,0 +1,41 @@
+From 99ae2a39ddc3f89c66d9f09783b591c0f2dbf2e9 Mon Sep 17 00:00:00 2001
+From: Gaurav Jain <gaurav.jain@nxp.com>
+Date: Wed, 28 Jun 2023 12:44:32 +0530
+Subject: [PATCH] cryptodev_verbosity: Fix build for Linux 6.4
+
+register_sysctl_table api is removed in kernel.
+migrate to the new api register_sysctl.
+
+child is also removed in linux 6.4 ctl_table struct.
+
+Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
+---
+ ioctl.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/ioctl.c b/ioctl.c
+index 8f241b86..4262bbd5 100644
+--- a/ioctl.c
++++ b/ioctl.c
+@@ -1246,7 +1246,9 @@ static struct ctl_table verbosity_ctl_root[] = {
+ 	{
+ 		.procname       = "ioctl",
+ 		.mode           = 0555,
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0))
+ 		.child          = verbosity_ctl_dir,
++#endif
+ 	},
+ 	{},
+ };
+@@ -1267,7 +1269,11 @@ static int __init init_cryptodev(void)
+ 		return rc;
+ 	}
+ 
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0))
+ 	verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root);
++#else
++	verbosity_sysctl_header = register_sysctl(verbosity_ctl_root->procname, verbosity_ctl_dir);
++#endif
+ 
+ 	pr_info(PFX "driver %s loaded.\n", VERSION);
+ 
diff --git a/package/kernel/cryptodev-linux/patches/0001-zero-copy-fix-build-for-linux-6.4.patch b/package/kernel/cryptodev-linux/patches/0001-zero-copy-fix-build-for-linux-6.4.patch
new file mode 100644
index 00000000000000..0b8147d56ef792
--- /dev/null
+++ b/package/kernel/cryptodev-linux/patches/0001-zero-copy-fix-build-for-linux-6.4.patch
@@ -0,0 +1,34 @@
+From 592017c3a910a3905b1925aee88c4674e9a596b7 Mon Sep 17 00:00:00 2001
+From: Gaurav Jain <gaurav.jain@nxp.com>
+Date: Tue, 30 May 2023 17:09:42 +0530
+Subject: [PATCH] zero copy: Fix build for Linux 6.4
+
+get_user_pages_remote api prototype is changed in kernel.
+struct vm_area_struct **vmas argument is removed.
+Migrate to the new API.
+
+Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
+---
+ zc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/zc.c b/zc.c
+index fdf7da17..6637945a 100644
+--- a/zc.c
++++ b/zc.c
+@@ -80,10 +80,14 @@ int __get_userbuf(uint8_t __user *addr, uint32_t len, int write,
+ 	ret = get_user_pages_remote(task, mm,
+ 			(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
+ 			pg, NULL, NULL);
+-#else
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0))
+ 	ret = get_user_pages_remote(mm,
+ 			(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
+ 			pg, NULL, NULL);
++#else
++	ret = get_user_pages_remote(mm,
++			(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
++			pg, NULL);
+ #endif
+ #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
+ 	up_read(&mm->mmap_sem);
diff --git a/package/kernel/cryptodev-linux/patches/0003-move-recent-linux-version-ifdefs-from-v6.4-to-v6.5.patch b/package/kernel/cryptodev-linux/patches/0003-move-recent-linux-version-ifdefs-from-v6.4-to-v6.5.patch
new file mode 100644
index 00000000000000..baf5b805cdd824
--- /dev/null
+++ b/package/kernel/cryptodev-linux/patches/0003-move-recent-linux-version-ifdefs-from-v6.4-to-v6.5.patch
@@ -0,0 +1,60 @@
+From bb8bc7cf60d2c0b097c8b3b0e807f805b577a53f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Joan=20Bruguera=20Mic=C3=B3?= <joanbrugueram@gmail.com>
+Date: Mon, 3 Jul 2023 00:46:02 +0000
+Subject: [PATCH] Move recent Linux version #ifdefs from v6.4 to v6.5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The latest commits, meant to fix the build on Linux 6.4, are actually
+fixing the build for API changes introduced in the merge window of the
+yet-unreleased Linux 6.5, and actually break the build for Linux 6.4.
+
+In particular, the upstream commits introducing the API changes are the
+following, which are *not* included in the Linux v6.4 tag:
+* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=19c4e618a1bc3d0cad1f04c857be8076cb05bbb2
+* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca5e863233e8f6acd1792fd85d6bc2729a1b2c10
+
+Change to #ifdef's to v6.5, where they will most likely be included.
+
+Signed-off-by: Joan Bruguera Micó <joanbrugueram@gmail.com>
+---
+ ioctl.c | 4 ++--
+ zc.c    | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/ioctl.c b/ioctl.c
+index 4262bbd..e3eefe1 100644
+--- a/ioctl.c
++++ b/ioctl.c
+@@ -1246,7 +1246,7 @@ static struct ctl_table verbosity_ctl_root[] = {
+ 	{
+ 		.procname       = "ioctl",
+ 		.mode           = 0555,
+-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0))
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 5, 0))
+ 		.child          = verbosity_ctl_dir,
+ #endif
+ 	},
+@@ -1269,7 +1269,7 @@ static int __init init_cryptodev(void)
+ 		return rc;
+ 	}
+ 
+-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0))
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 5, 0))
+ 	verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root);
+ #else
+ 	verbosity_sysctl_header = register_sysctl(verbosity_ctl_root->procname, verbosity_ctl_dir);
+diff --git a/zc.c b/zc.c
+index 6637945..00e00c1 100644
+--- a/zc.c
++++ b/zc.c
+@@ -80,7 +80,7 @@ int __get_userbuf(uint8_t __user *addr, uint32_t len, int write,
+ 	ret = get_user_pages_remote(task, mm,
+ 			(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
+ 			pg, NULL, NULL);
+-#elif (LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0))
++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(6, 5, 0))
+ 	ret = get_user_pages_remote(mm,
+ 			(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
+ 			pg, NULL, NULL);
diff --git a/package/kernel/cryptodev-linux/patches/0004-fix-build-for-linux-6.7-rc1.patch b/package/kernel/cryptodev-linux/patches/0004-fix-build-for-linux-6.7-rc1.patch
new file mode 100644
index 00000000000000..3ef9e28ce70875
--- /dev/null
+++ b/package/kernel/cryptodev-linux/patches/0004-fix-build-for-linux-6.7-rc1.patch
@@ -0,0 +1,35 @@
+From 5e7121e45ff283d30097da381fd7e97c4bb61364 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Joan=20Bruguera=20Mic=C3=B3?= <joanbrugueram@gmail.com>
+Date: Sun, 10 Dec 2023 13:57:55 +0000
+Subject: [PATCH] Fix build for Linux 6.7-rc1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since Linux 6.7-rc1, no ahash algorithms set a nonzero alignmask,
+and therefore `crypto_ahash_alignmask` has been removed.
+
+See also: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0f8660c82b79af595b056f6b9f4f227edeb88574
+          https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c626910f3f1bbce6ad18bc613d895d2a089ed95e
+
+Signed-off-by: Joan Bruguera Micó <joanbrugueram@gmail.com>
+---
+ cryptlib.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/cryptlib.c b/cryptlib.c
+index 4d739e5..0e59d4c 100644
+--- a/cryptlib.c
++++ b/cryptlib.c
+@@ -381,7 +381,11 @@ int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name,
+ 	}
+ 
+ 	hdata->digestsize = crypto_ahash_digestsize(hdata->async.s);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 7, 0))
+ 	hdata->alignmask = crypto_ahash_alignmask(hdata->async.s);
++#else
++	hdata->alignmask = 0;
++#endif
+ 
+ 	init_completion(&hdata->async.result.completion);
+ 
diff --git a/package/kernel/gpio-button-hotplug/Makefile b/package/kernel/gpio-button-hotplug/Makefile
index 7ca6195a03ecff..bb2c35119710ae 100644
--- a/package/kernel/gpio-button-hotplug/Makefile
+++ b/package/kernel/gpio-button-hotplug/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2008-2012 OpenWrt.org
+# Copyright (C) 2008-2024 OpenWrt.org
 #
 # This is free software, licensed under the GNU General Public License v2.
 # See /LICENSE for more information.
diff --git a/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c b/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c
index f086c8217472db..f3705344a7a09f 100644
--- a/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c
+++ b/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c
@@ -242,11 +242,11 @@ static int gpio_button_get_value(struct gpio_keys_button_data *bdata)
 	int val;
 
 	if (bdata->can_sleep)
-		val = !!gpio_get_value_cansleep(bdata->b->gpio);
+		val = !!gpiod_get_value_cansleep(bdata->gpiod);
 	else
-		val = !!gpio_get_value(bdata->b->gpio);
+		val = !!gpiod_get_value(bdata->gpiod);
 
-	return val ^ bdata->b->active_low;
+	return val;
 }
 
 static void gpio_keys_handle_button(struct gpio_keys_button_data *bdata)
@@ -365,7 +365,6 @@ gpio_keys_get_devtree_pdata(struct device *dev)
 	struct device_node *node, *pp;
 	struct gpio_keys_platform_data *pdata;
 	struct gpio_keys_button *button;
-	int error;
 	int nbuttons;
 	int i = 0;
 
@@ -375,14 +374,12 @@ gpio_keys_get_devtree_pdata(struct device *dev)
 
 	nbuttons = of_get_child_count(node);
 	if (nbuttons == 0)
-		return NULL;
+		return ERR_PTR(-EINVAL);
 
 	pdata = devm_kzalloc(dev, sizeof(*pdata) + nbuttons * (sizeof *button),
 		GFP_KERNEL);
-	if (!pdata) {
-		error = -ENOMEM;
-		goto err_out;
-	}
+	if (!pdata)
+		return ERR_PTR(-ENOMEM);
 
 	pdata->buttons = (struct gpio_keys_button *)(pdata + 1);
 	pdata->nbuttons = nbuttons;
@@ -391,37 +388,13 @@ gpio_keys_get_devtree_pdata(struct device *dev)
 	of_property_read_u32(node, "poll-interval", &pdata->poll_interval);
 
 	for_each_child_of_node(node, pp) {
-		enum of_gpio_flags flags;
-
-		if (!of_find_property(pp, "gpios", NULL)) {
-			pdata->nbuttons--;
-			dev_warn(dev, "Found button without gpios\n");
-			continue;
-		}
-
 		button = (struct gpio_keys_button *)(&pdata->buttons[i++]);
 
-		button->irq = irq_of_parse_and_map(pp, 0);
-
-		button->gpio = of_get_gpio_flags(pp, 0, &flags);
-		if (button->gpio < 0) {
-			error = button->gpio;
-			if (error != -ENOENT) {
-				if (error != -EPROBE_DEFER)
-					dev_err(dev,
-						"Failed to get gpio flags, error: %d\n",
-						error);
-				return ERR_PTR(error);
-			}
-		} else {
-			button->active_low = !!(flags & OF_GPIO_ACTIVE_LOW);
-		}
-
 		if (of_property_read_u32(pp, "linux,code", &button->code)) {
-			dev_err(dev, "Button without keycode: 0x%x\n",
-				button->gpio);
-			error = -EINVAL;
-			goto err_out;
+			dev_err(dev, "Button node '%s' without keycode\n",
+				pp->full_name);
+			of_node_put(pp);
+			return ERR_PTR(-EINVAL);
 		}
 
 		button->desc = of_get_property(pp, "label", NULL);
@@ -434,17 +407,12 @@ gpio_keys_get_devtree_pdata(struct device *dev)
 		if (of_property_read_u32(pp, "debounce-interval",
 					&button->debounce_interval))
 			button->debounce_interval = 5;
-	}
 
-	if (pdata->nbuttons == 0) {
-		error = -EINVAL;
-		goto err_out;
+		button->irq = irq_of_parse_and_map(pp, 0);
+		button->gpio = -ENOENT; /* mark this as device-tree */
 	}
 
 	return pdata;
-
-err_out:
-	return ERR_PTR(error);
 }
 
 static struct of_device_id gpio_keys_of_match[] = {
@@ -471,11 +439,12 @@ gpio_keys_get_devtree_pdata(struct device *dev)
 static int gpio_keys_button_probe(struct platform_device *pdev,
 		struct gpio_keys_button_dev **_bdev, int polled)
 {
-	struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
 	struct device *dev = &pdev->dev;
+	struct gpio_keys_platform_data *pdata = dev_get_platdata(dev);
 	struct gpio_keys_button_dev *bdev;
 	struct gpio_keys_button *buttons;
-	int error;
+	struct device_node *prev = NULL;
+	int error = 0;
 	int i;
 
 	if (!pdata) {
@@ -514,46 +483,79 @@ static int gpio_keys_button_probe(struct platform_device *pdev,
 	for (i = 0; i < pdata->nbuttons; i++) {
 		struct gpio_keys_button *button = &buttons[i];
 		struct gpio_keys_button_data *bdata = &bdev->data[i];
-		unsigned int gpio = button->gpio;
+		const char *desc = button->desc ? button->desc : DRV_NAME;
 
 		if (button->wakeup) {
 			dev_err(dev, "does not support wakeup\n");
-			return -EINVAL;
+			error = -EINVAL;
+			goto out;
 		}
 
 		bdata->map_entry = button_get_index(button->code);
 		if (bdata->map_entry < 0) {
-			dev_warn(dev, "does not support key code:%u\n",
+			dev_err(dev, "does not support key code:%u\n",
 				button->code);
-			continue;
+			error = -EINVAL;
+			goto out;
 		}
 
 		if (!(button->type == 0 || button->type == EV_KEY ||
 		      button->type == EV_SW)) {
-			dev_warn(dev, "only supports buttons or switches\n");
+			dev_err(dev, "only supports buttons or switches\n");
+			error = -EINVAL;
+			goto out;
+		}
+
+		if (button->irq) {
+			dev_err(dev, "skipping button %s (only gpio buttons supported)\n",
+				button->desc);
+			bdata->b = &pdata->buttons[i];
 			continue;
 		}
 
-		error = devm_gpio_request(dev, gpio,
-				     button->desc ? button->desc : DRV_NAME);
-		if (error) {
-			dev_err(dev, "unable to claim gpio %u, err=%d\n",
-				gpio, error);
-			return error;
+		if (gpio_is_valid(button->gpio)) {
+			/* legacy platform data... but is it the lookup table? */
+			bdata->gpiod = devm_gpiod_get_index(dev, desc, i,
+							    GPIOD_IN);
+			if (IS_ERR(bdata->gpiod)) {
+				/* or the legacy (button->gpio is good) way? */
+				error = devm_gpio_request_one(dev,
+					button->gpio, GPIOF_IN | (
+					button->active_low ? GPIOF_ACTIVE_LOW :
+					0), desc);
+				if (error) {
+					if (error != -EPROBE_DEFER) {
+						dev_err(dev, "unable to claim gpio %d, err=%d\n",
+							button->gpio, error);
+					}
+					goto out;
+				}
+
+				bdata->gpiod = gpio_to_desc(button->gpio);
+			}
+		} else {
+			/* Device-tree */
+			struct device_node *child =
+				of_get_next_child(dev->of_node, prev);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
+			bdata->gpiod = devm_fwnode_gpiod_get(dev,
+				of_fwnode_handle(child), "gpios", GPIOD_IN,
+				desc);
+#else
+			bdata->gpiod = devm_gpiod_get_from_of_node(dev,
+				child, "gpios", 0, GPIOD_IN, desc);
+#endif
+			prev = child;
 		}
-		bdata->gpiod = gpio_to_desc(gpio);
-		if (!bdata->gpiod)
-			return -EINVAL;
 
-		error = gpio_direction_input(gpio);
-		if (error) {
-			dev_err(dev,
-				"unable to set direction on gpio %u, err=%d\n",
-				gpio, error);
-			return error;
+		if (IS_ERR_OR_NULL(bdata->gpiod)) {
+			error = IS_ERR(bdata->gpiod) ? PTR_ERR(bdata->gpiod) :
+				-EINVAL;
+			goto out;
 		}
 
-		bdata->can_sleep = gpio_cansleep(gpio);
+		bdata->can_sleep = gpiod_cansleep(bdata->gpiod);
 		bdata->last_state = -1; /* Unknown state on boot */
 
 		if (bdev->polled) {
@@ -584,8 +586,11 @@ static int gpio_keys_button_probe(struct platform_device *pdev,
 	platform_set_drvdata(pdev, bdev);
 
 	*_bdev = bdev;
+	error = 0;
 
-	return 0;
+out:
+	of_node_put(prev);
+	return error;
 }
 
 static int gpio_keys_probe(struct platform_device *pdev)
@@ -594,9 +599,7 @@ static int gpio_keys_probe(struct platform_device *pdev)
 	struct gpio_keys_button_dev *bdev;
 	int ret, i;
 
-
 	ret = gpio_keys_button_probe(pdev, &bdev, 0);
-
 	if (ret)
 		return ret;
 
@@ -608,12 +611,8 @@ static int gpio_keys_probe(struct platform_device *pdev)
 
 		INIT_DELAYED_WORK(&bdata->work, gpio_keys_irq_work_func);
 
-		if (!bdata->gpiod)
-			continue;
-
 		if (!button->irq) {
-			bdata->irq = gpio_to_irq(button->gpio);
-
+			bdata->irq = gpiod_to_irq(bdata->gpiod);
 			if (bdata->irq < 0) {
 				dev_err(&pdev->dev, "failed to get irq for gpio:%d\n",
 					button->gpio);
@@ -631,7 +630,6 @@ static int gpio_keys_probe(struct platform_device *pdev)
 		ret = devm_request_threaded_irq(&pdev->dev,
 			bdata->irq, NULL, button_handle_irq,
 			irqflags, dev_name(&pdev->dev), bdata);
-
 		if (ret < 0) {
 			bdata->irq = 0;
 			dev_err(&pdev->dev, "failed to request irq:%d for gpio:%d\n",
@@ -653,14 +651,12 @@ static int gpio_keys_polled_probe(struct platform_device *pdev)
 	int ret;
 
 	ret = gpio_keys_button_probe(pdev, &bdev, 1);
-
 	if (ret)
 		return ret;
 
 	INIT_DELAYED_WORK(&bdev->work, gpio_keys_polled_poll);
 
 	pdata = bdev->pdata;
-
 	if (pdata->enable)
 		pdata->enable(bdev->dev);
 
diff --git a/package/kernel/ksmbd/Makefile b/package/kernel/ksmbd/Makefile
index 674e816186457d..7c4e01449f8682 100644
--- a/package/kernel/ksmbd/Makefile
+++ b/package/kernel/ksmbd/Makefile
@@ -1,12 +1,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ksmbd
-PKG_VERSION:=3.4.8
+PKG_VERSION:=2023.12.22
 PKG_RELEASE:=1
 
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=https://github.com/cifsd-team/ksmbd/releases/download/$(PKG_VERSION)
-PKG_HASH:=209bfba4dc5c50007942a3ec24f86a7f7c628618ac07f79c62e3404dc247d495
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL:=https://github.com/cifsd-team/ksmbd
+PKG_SOURCE_VERSION:=0590dfae7a6e0a50eda6584286b2c6215aaddea1
+PKG_MIRROR_HASH:=95415120722db35ca599ab6ca36fd6310fc11ca50acf7d6235d4b0f397c46dd4
 
 PKG_LICENSE:=GPL-2.0-or-later
 PKG_LICENSE_FILES:=COPYING
@@ -40,6 +41,7 @@ define KernelPackage/fs-ksmbd
 		+kmod-oid-registry
 endef
 
+
 # The last two DEPENDS are hacks in order to get CONFIG_ASN1 and CONFIG_OID_REGISTRY
 # which it seems can't be selected independently. Some bug in either base or upstream.
 
diff --git a/package/kernel/ksmbd/patches/02-fix-build-with-kernel-6.6.patch b/package/kernel/ksmbd/patches/02-fix-build-with-kernel-6.6.patch
new file mode 100644
index 00000000000000..82135f41b32ee4
--- /dev/null
+++ b/package/kernel/ksmbd/patches/02-fix-build-with-kernel-6.6.patch
@@ -0,0 +1,121 @@
+From ab78eb9095c3b508dc1dceaf5757e56877a5a02e Mon Sep 17 00:00:00 2001
+From: W_Y_CPP <383152993@qq.com>
+Date: Thu, 25 Jan 2024 05:15:13 -0500
+Subject: [PATCH] fix build with kernel 6.6
+
+---
+ compat.c  |  6 ++++++
+ smb1pdu.c | 32 ++++++++++++++++++++++++++++++--
+ 2 files changed, 36 insertions(+), 2 deletions(-)
+
+diff --git a/compat.c b/compat.c
+index cd48401..47fe647 100644
+--- a/compat.c
++++ b/compat.c
+@@ -8,6 +8,12 @@
+ #endif
+ 
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
++int compat_inode_permission(struct path *path, struct inode *inode, int mask)
++{
++	return inode_permission(mnt_idmap(path->mnt), inode, mask);
++
++}
++
+ void compat_generic_fillattr(struct path *path, u32 request_mask,
+ 			     struct inode *inode, struct kstat *kstat)
+ {
+diff --git a/smb1pdu.c b/smb1pdu.c
+index 7501a53..6d9d204 100644
+--- a/smb1pdu.c
++++ b/smb1pdu.c
+@@ -825,7 +825,12 @@ int smb_rename(struct ksmbd_work *work)
+ 	char *oldname, *newname;
+ 	struct ksmbd_file *fp = NULL;
+ 	int oldname_len;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++	struct path path, parent_path;
++	int flags = 0;
++#else
+ 	struct path path;
++#endif
+ 	bool file_present = true;
+ 	int rc = 0;
+ 
+@@ -858,8 +863,12 @@ int smb_rename(struct ksmbd_work *work)
+ 		newname = NULL;
+ 		goto out;
+ 	}
+-
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++	rc = ksmbd_vfs_kern_path_locked(work, newname, LOOKUP_NO_SYMLINKS,
++					&parent_path, &path, 1);
++#else
+ 	rc = ksmbd_vfs_kern_path(work, newname, LOOKUP_NO_SYMLINKS, &path, 1);
++#endif
+ 	if (rc)
+ 		file_present = false;
+ 	else
+@@ -873,7 +882,12 @@ int smb_rename(struct ksmbd_work *work)
+ 	}
+ 
+ 	ksmbd_debug(SMB, "rename %s -> %s\n", oldname, newname);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++	rc = ksmbd_vfs_kern_path_locked(work, oldname, LOOKUP_NO_SYMLINKS,
++					&parent_path, &path, 1);
++#else
+ 	rc = ksmbd_vfs_kern_path(work, oldname, LOOKUP_NO_SYMLINKS, &path, 1);
++#endif
+ 	if (rc)
+ 		goto out;
+ 
+@@ -883,8 +897,11 @@ int smb_rename(struct ksmbd_work *work)
+ 		path_put(&path);
+ 		goto out;
+ 	}
+-
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++	rc = ksmbd_vfs_rename(work, &fp->filp->f_path, newname, flags);
++#else
+ 	rc = ksmbd_vfs_fp_rename(work, fp, newname);
++#endif
+ 	if (rc) {
+ 		rsp->hdr.Status.CifsError = STATUS_NO_MEMORY;
+ 		path_put(&path);
+@@ -7344,6 +7361,9 @@ static int smb_fileinfo_rename(struct ksmbd_work *work)
+ 	struct ksmbd_file *fp;
+ 	char *newname;
+ 	int rc = 0;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++	int flags = 0;
++#endif
+ 
+ 	req = (struct smb_com_trans2_sfi_req *)work->request_buf;
+ 	rsp = (struct smb_com_trans2_sfi_rsp *)work->response_buf;
+@@ -7381,7 +7401,11 @@ static int smb_fileinfo_rename(struct ksmbd_work *work)
+ 	}
+ 
+ 	ksmbd_debug(SMB, "new name(%s)\n", newname);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++	rc = ksmbd_vfs_rename(work, &fp->filp->f_path, newname, flags);
++#else
+ 	rc = ksmbd_vfs_fp_rename(work, fp, newname);
++#endif
+ 	if (rc) {
+ 		rsp->hdr.Status.CifsError = STATUS_UNEXPECTED_IO_ERROR;
+ 		goto out;
+@@ -8380,7 +8404,11 @@ int smb_open_andx(struct ksmbd_work *work)
+ 		}
+ 
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
++		generic_fillattr(mnt_idmap(path.mnt), STATX_BASIC_STATS, d_inode(path.dentry),&stat);
++#else
+ 		generic_fillattr(mnt_idmap(path.mnt), d_inode(path.dentry), &stat);
++#endif
+ #else
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)
+ 		generic_fillattr(mnt_user_ns(path.mnt), d_inode(path.dentry), &stat);
+-- 
+2.17.1
+
diff --git a/package/kernel/linux/modules/crypto.mk b/package/kernel/linux/modules/crypto.mk
index f21ec5dcefae46..27705472f7c817 100644
--- a/package/kernel/linux/modules/crypto.mk
+++ b/package/kernel/linux/modules/crypto.mk
@@ -39,7 +39,8 @@ define KernelPackage/crypto-aead
   TITLE:=CryptoAPI AEAD support
   KCONFIG:= \
 	CONFIG_CRYPTO_AEAD \
-	CONFIG_CRYPTO_AEAD2
+	CONFIG_CRYPTO_AEAD2 \
+	CONFIG_CRYPTO_GENIV
   FILES:= \
 	  $(LINUX_DIR)/crypto/aead.ko \
 	  $(LINUX_DIR)/crypto/geniv.ko@ge5.10
diff --git a/package/kernel/linux/modules/fs.mk b/package/kernel/linux/modules/fs.mk
index b1bfde2c68097f..86137c7a757faf 100644
--- a/package/kernel/linux/modules/fs.mk
+++ b/package/kernel/linux/modules/fs.mk
@@ -10,7 +10,7 @@ FS_MENU:=Filesystems
 define KernelPackage/fs-9p
   SUBMENU:=$(FS_MENU)
   TITLE:=Plan 9 Resource Sharing Support
-  DEPENDS:=+kmod-9pnet +LINUX_6_1:kmod-fs-netfs
+  DEPENDS:=+kmod-9pnet +LINUX_6_1:kmod-fs-netfs +LINUX_6_6:kmod-fs-netfs
   KCONFIG:=\
 	CONFIG_9P_FS \
 	CONFIG_9P_FS_POSIX_ACL=n \
@@ -91,6 +91,7 @@ define KernelPackage/fs-smbfs-common
 	CONFIG_SMBFS_COMMON@lt6.1 \
 	CONFIG_SMBFS@ge6.1
   DEPENDS:= \
+  +LINUX_6_6:kmod-fs-netfs +LINUX_6_6:kmod-nls-ucs2-utils \
 	+(LINUX_5_4||LINUX_5_10):kmod-crypto-arc4 \
 	+(LINUX_5_4||LINUX_5_10):kmod-crypto-md4
   FILES:= \
@@ -349,6 +350,7 @@ define KernelPackage/fs-jfs
   FILES:=$(LINUX_DIR)/fs/jfs/jfs.ko
   AUTOLOAD:=$(call AutoLoad,30,jfs,1)
   $(call AddDepends/nls)
+  DEPENDS:=+LINUX_6_6:kmod-nls-ucs2-utils
 endef
 
 define KernelPackage/fs-jfs/description
@@ -438,8 +440,7 @@ define KernelPackage/fs-nfs-common
   FILES:= \
 	$(LINUX_DIR)/fs/lockd/lockd.ko \
 	$(LINUX_DIR)/net/sunrpc/sunrpc.ko \
-	$(LINUX_DIR)/fs/nfs_common/grace.ko \
-	$(LINUX_DIR)/fs/nfs_common/nfs_ssc.ko@ge5.10
+	$(LINUX_DIR)/fs/nfs_common/grace.ko
   AUTOLOAD:=$(call AutoLoad,30,grace sunrpc lockd)
 endef
 
@@ -683,3 +684,24 @@ define KernelPackage/fuse/description
 endef
 
 $(eval $(call KernelPackage,fuse))
+
+define KernelPackage/pstore
+  SUBMENU:=$(FS_MENU)
+  TITLE:=Pstore file system
+  DEFAULT:=m if ALL_KMODS
+  KCONFIG:= \
+	CONFIG_PSTORE \
+	CONFIG_PSTORE_COMPRESS=y \
+	CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" \
+	CONFIG_PSTORE_DEFLATE_COMPRESS=y \
+	CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
+  FILES:= $(LINUX_DIR)/fs/pstore/pstore.ko
+  AUTOLOAD:=$(call AutoLoad,30,pstore,1)
+  DEPENDS:=+LINUX_6_6:kmod-lib-zlib-deflate +LINUX_6_6:kmod-lib-zlib-inflate
+endef
+
+define KernelPackage/pstore/description
+ Kernel module for pstore filesystem support
+endef
+
+$(eval $(call KernelPackage,pstore))
diff --git a/package/kernel/linux/modules/leds.mk b/package/kernel/linux/modules/leds.mk
index a84e23971dbefe..11d0ed5f3a3dc9 100644
--- a/package/kernel/linux/modules/leds.mk
+++ b/package/kernel/linux/modules/leds.mk
@@ -246,3 +246,37 @@ define KernelPackage/input-leds/description
 endef
 
 $(eval $(call KernelPackage,input-leds))
+
+
+define KernelPackage/leds-lp55xx-common
+  SUBMENU:=$(LEDS_MENU)
+  TITLE:=LED common driver for LP5521/LP5523/LP55231/LP5562 controllers
+  DEPENDS:=+kmod-i2c-core
+  KCONFIG:=CONFIG_LEDS_LP55XX_COMMON
+  FILES:=$(LINUX_DIR)/drivers/leds/leds-lp55xx-common.ko
+  AUTOLOAD:=$(call AutoLoad,60,leds-lp55xx-common,1)
+endef
+
+define KernelPackage/leds-lp55xx-common/description
+ This option enables support for Texas Instruments
+ LP5521/LP5523/LP55231/LP5562 common driver.
+endef
+
+$(eval $(call KernelPackage,leds-lp55xx-common))
+
+
+define KernelPackage/leds-lp5562
+  SUBMENU:=$(LEDS_MENU)
+  TITLE:=LED driver for LP5562 controllers
+  DEPENDS:=+kmod-i2c-core +kmod-leds-lp55xx-common
+  KCONFIG:=CONFIG_LEDS_LP5562
+  FILES:=$(LINUX_DIR)/drivers/leds/leds-lp5562.ko
+  AUTOLOAD:=$(call AutoLoad,60,leds-lp5562,1)
+endef
+
+define KernelPackage/leds-lp5562/description
+ This option enables support for Texas Instruments LP5562
+ LED controllers.
+endef
+
+$(eval $(call KernelPackage,leds-lp5562))
diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
index ac8c591a98facb..25e92cb98135d4 100644
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -142,7 +142,7 @@ $(eval $(call KernelPackage,mii))
 define KernelPackage/mdio-devres
   SUBMENU:=$(NETWORK_DEVICES_MENU)
   TITLE:=Supports MDIO device registration
-  DEPENDS:=@!LINUX_5_4 +kmod-libphy +(TARGET_armvirt||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio
+  DEPENDS:=@!LINUX_5_4 +kmod-libphy +(TARGET_armvirt||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio
   KCONFIG:=CONFIG_MDIO_DEVRES
   HIDDEN:=1
   FILES:=$(LINUX_DIR)/drivers/net/phy/mdio_devres.ko
diff --git a/package/kernel/linux/modules/netsupport.mk b/package/kernel/linux/modules/netsupport.mk
index 428b3b40b690d2..0a64cc319e9907 100644
--- a/package/kernel/linux/modules/netsupport.mk
+++ b/package/kernel/linux/modules/netsupport.mk
@@ -907,11 +907,25 @@ endef
 
 $(eval $(call KernelPackage,sched-ipset))
 
+define KernelPackage/sched-mqprio-common
+  SUBMENU:=$(NETWORK_SUPPORT_MENU)
+  TITLE:=mqprio queue common dependencies support
+  DEPENDS:=@LINUX_6_6
+  HIDDEN:=1
+  KCONFIG:=CONFIG_NET_SCH_MQPRIO_LIB
+  FILES:=$(LINUX_DIR)/net/sched/sch_mqprio_lib.ko
+endef
+
+define KernelPackage/sched-mqprio-common/description
+ Common library for manipulating mqprio queue configurations
+endef
+
+$(eval $(call KernelPackage,sched-mqprio-common))
 
 define KernelPackage/sched-mqprio
   SUBMENU:=$(NETWORK_SUPPORT_MENU)
   TITLE:=Multi-queue priority scheduler (MQPRIO)
-  DEPENDS:=+kmod-sched-core
+  DEPENDS:=+kmod-sched-core +LINUX_6_6:kmod-sched-mqprio-common
   KCONFIG:=CONFIG_NET_SCH_MQPRIO
   FILES:=$(LINUX_DIR)/net/sched/sch_mqprio.ko
   AUTOLOAD:=$(call AutoProbe, sch_mqprio)
@@ -982,7 +996,7 @@ endef
 $(eval $(call KernelPackage,bpf-test))
 
 
-SCHED_MODULES_EXTRA = sch_codel sch_dsmark sch_gred sch_multiq sch_sfq sch_teql sch_fq act_pedit act_simple act_csum em_cmp em_nbyte em_meta em_text
+SCHED_MODULES_EXTRA = sch_codel sch_gred sch_multiq sch_sfq sch_teql sch_fq act_pedit act_simple act_skbmod act_csum em_cmp em_nbyte em_meta em_text
 SCHED_FILES_EXTRA = $(foreach mod,$(SCHED_MODULES_EXTRA),$(LINUX_DIR)/net/sched/$(mod).ko)
 
 define KernelPackage/sched
@@ -991,7 +1005,7 @@ define KernelPackage/sched
   DEPENDS:=+kmod-sched-core +kmod-lib-crc32c +kmod-lib-textsearch
   KCONFIG:= \
 	CONFIG_NET_SCH_CODEL \
-	CONFIG_NET_SCH_DSMARK \
+	CONFIG_NET_SCH_DSMARK@lt6.2 \
 	CONFIG_NET_SCH_GRED \
 	CONFIG_NET_SCH_MULTIQ \
 	CONFIG_NET_SCH_SFQ \
@@ -999,13 +1013,15 @@ define KernelPackage/sched
 	CONFIG_NET_SCH_FQ \
 	CONFIG_NET_ACT_PEDIT \
 	CONFIG_NET_ACT_SIMP \
+	CONFIG_NET_ACT_SKBMOD \
 	CONFIG_NET_ACT_CSUM \
 	CONFIG_NET_EMATCH_CMP \
 	CONFIG_NET_EMATCH_NBYTE \
 	CONFIG_NET_EMATCH_META \
 	CONFIG_NET_EMATCH_TEXT
   FILES:=$(SCHED_FILES_EXTRA)
-  AUTOLOAD:=$(call AutoLoad,73, $(SCHED_MODULES_EXTRA))
+  FILES+=$(LINUX_DIR)/net/sched/sch_dsmark.ko@lt6.2
+  AUTOLOAD:=$(call AutoLoad,73, $(SCHED_MODULES_EXTRA) sch_dsmark@lt6.2)
 endef
 
 define KernelPackage/sched/description
diff --git a/package/kernel/linux/modules/nls.mk b/package/kernel/linux/modules/nls.mk
index 7450ed1ce56754..3ef0d43e100511 100644
--- a/package/kernel/linux/modules/nls.mk
+++ b/package/kernel/linux/modules/nls.mk
@@ -339,3 +339,19 @@ define KernelPackage/nls-utf8/description
 endef
 
 $(eval $(call KernelPackage,nls-utf8))
+
+define KernelPackage/nls-ucs2-utils
+  SUBMENU:=Native Language Support
+  TITLE:=UCS-2 common library
+  DEPENDS+=@LINUX_6_6
+  HIDDEN:=1
+  KCONFIG:=CONFIG_NLS_UCS2_UTILS
+  FILES:=$(LINUX_DIR)/fs/nls/nls_ucs2_utils.ko
+  $(call AddDepends/nls)
+endef
+
+define KernelPackage/nls-ucs2-utils/description
+ UCS-2 common library
+endef
+
+$(eval $(call KernelPackage,nls-ucs2-utils))
diff --git a/package/kernel/linux/modules/other.mk b/package/kernel/linux/modules/other.mk
index 65065c6f9a4695..8ab2738c5beeb7 100644
--- a/package/kernel/linux/modules/other.mk
+++ b/package/kernel/linux/modules/other.mk
@@ -1336,7 +1336,7 @@ $(eval $(call KernelPackage,itco-wdt))
 define KernelPackage/mhi-bus
   SUBMENU:=$(OTHER_MENU)
   TITLE:=MHI bus
-  DEPENDS:=@(LINUX_5_15||LINUX_6_1)
+  DEPENDS:=@(LINUX_5_15||LINUX_6_1||LINUX_6_6)
   KCONFIG:=CONFIG_MHI_BUS \
            CONFIG_MHI_BUS_DEBUG=y
   FILES:=$(LINUX_DIR)/drivers/bus/mhi/host/mhi.ko
diff --git a/package/kernel/linux/modules/usb.mk b/package/kernel/linux/modules/usb.mk
index e0bebc46d27022..b1ae500c02a533 100644
--- a/package/kernel/linux/modules/usb.mk
+++ b/package/kernel/linux/modules/usb.mk
@@ -1155,9 +1155,9 @@ $(eval $(call KernelPackage,usb-net-aqc111))
 
 define KernelPackage/usb-net-asix
   TITLE:=Kernel module for USB-to-Ethernet Asix convertors
-  DEPENDS:=+kmod-phy-ax88796b +LINUX_6_1:kmod-phylink \
-	+(LINUX_5_15||LINUX_6_1):kmod-mdio-devres \
-	+(LINUX_5_15||LINUX_6_1):kmod-net-selftests
+  DEPENDS:=+kmod-phy-ax88796b +(LINUX_6_1||LINUX_6_6):kmod-phylink \
+	+(LINUX_5_15||LINUX_6_1||LINUX_6_6):kmod-mdio-devres \
+	+(LINUX_5_15||LINUX_6_1||LINUX_6_6):kmod-net-selftests
   KCONFIG:=CONFIG_USB_NET_AX8817X
   FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/asix.ko
   AUTOLOAD:=$(call AutoProbe,asix)
@@ -1285,7 +1285,7 @@ $(eval $(call KernelPackage,usb-net-smsc75xx))
 
 define KernelPackage/usb-net-smsc95xx
   TITLE:=SMSC LAN95XX based USB 2.0 10/100 ethernet devices
-  DEPENDS:=+kmod-phy-smsc +LINUX_6_1:kmod-net-selftests
+  DEPENDS:=+kmod-phy-smsc +(LINUX_6_1||LINUX_6_6):kmod-net-selftests
   KCONFIG:=CONFIG_USB_NET_SMSC95XX
   FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/smsc95xx.ko
   AUTOLOAD:=$(call AutoProbe,smsc95xx)
@@ -1578,7 +1578,7 @@ define KernelPackage/usb-hid-mcp2221
   SUBMENU:=$(USB_MENU)
   TITLE:=Microchip USB 2.0 to I2C/UART Protocol Converter with GPIO
   KCONFIG:=CONFIG_HID_MCP2221
-  DEPENDS:=@GPIO_SUPPORT +kmod-usb-hid +kmod-i2c-core
+  DEPENDS:=@GPIO_SUPPORT +kmod-usb-hid +kmod-i2c-core +LINUX_6_6:kmod-iio-core
   FILES:=$(LINUX_DIR)/drivers/hid/hid-mcp2221.ko
   AUTOLOAD:=$(call AutoProbe,hid-mcp2221)
 endef
diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk
index ae2cc36f25033a..abe8be2e73a4c3 100644
--- a/package/kernel/linux/modules/video.mk
+++ b/package/kernel/linux/modules/video.mk
@@ -57,20 +57,23 @@ $(eval $(call KernelPackage,backlight-pwm))
 define KernelPackage/acpi-video
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=ACPI Extensions For Display Adapters
-  DEPENDS:=@TARGET_x86 +kmod-backlight
+  DEPENDS:=@TARGET_x86||TARGET_loongarch64||TARGET_phytium +kmod-backlight
   HIDDEN:=1
-  KCONFIG:= \
-	CONFIG_ACPI_WMI \
-	CONFIG_ACPI_VIDEO
-  FILES:=$(LINUX_DIR)/drivers/acpi/video.ko \
-	$(LINUX_DIR)/drivers/platform/x86/wmi.ko
-  AUTOLOAD:=$(call AutoProbe,wmi video)
+  KCONFIG:=CONFIG_ACPI_VIDEO
+  FILES:=$(LINUX_DIR)/drivers/acpi/video.ko
+  AUTOLOAD:=$(call AutoProbe,video)
 endef
 
 define KernelPackage/acpi-video/description
  Kernel support for integrated graphics devices
 endef
 
+define KernelPackage/acpi-video/x86
+  KCONFIG+=CONFIG_ACPI_WMI
+  FILES+=$(LINUX_DIR)/drivers/platform/x86/wmi.ko
+  AUTOLOAD:=$(call AutoProbe,wmi video)
+endef
+
 $(eval $(call KernelPackage,acpi-video))
 
 
@@ -281,16 +284,19 @@ define KernelPackage/drm
   TITLE:=Direct Rendering Manager (DRM) support
   HIDDEN:=1
   DEPENDS:=+kmod-dma-buf +kmod-i2c-core +kmod-backlight \
-	+(LINUX_5_15||LINUX_6_1):kmod-fb
-  KCONFIG:=	\
-	CONFIG_DRM \
+	+(LINUX_5_15||LINUX_6_1||LINUX_6_6):kmod-fb
+  KCONFIG:=CONFIG_DRM \
+	CONFIG_DRM_EXEC@ge6.6 \
+	CONFIG_DRM_SUBALLOC_HELPER@ge6.4
 	CONFIG_DRM_FBDEV_EMULATION=y \
 	CONFIG_DRM_FBDEV_OVERALLOC=100 \
 	CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
   FILES:= \
 	$(LINUX_DIR)/drivers/gpu/drm/drm.ko \
-	$(LINUX_DIR)/drivers/gpu/drm/drm_panel_orientation_quirks.ko
-  AUTOLOAD:=$(call AutoLoad,05,drm)
+	$(LINUX_DIR)/drivers/gpu/drm/drm_panel_orientation_quirks.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/drm_exec.ko@ge6.6 \
+	$(LINUX_DIR)/drivers/gpu/drm/drm_suballoc_helper.ko@ge6.4
+  AUTOLOAD:=$(call AutoLoad,05,drm_exec@ge6.6 drm_suballoc_helper@ge6.4 drm)
 endef
 
 define KernelPackage/drm/description
@@ -302,12 +308,16 @@ $(eval $(call KernelPackage,drm))
 define KernelPackage/drm-buddy
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=A page based buddy allocator
-  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-drm @LINUX_6_1
+  DEPENDS:=@DISPLAY_SUPPORT +kmod-drm @LINUX_6_1||LINUX_6_6
   KCONFIG:=CONFIG_DRM_BUDDY
   FILES:= $(LINUX_DIR)/drivers/gpu/drm/drm_buddy.ko
   AUTOLOAD:=$(call AutoProbe,drm_buddy)
 endef
 
+define KernelPackage/drm-buddy/description
+  A page based buddy allocator
+endef
+
 $(eval $(call KernelPackage,drm-buddy))
 
 define KernelPackage/drm-ttm
@@ -361,7 +371,7 @@ $(eval $(call KernelPackage,drm-kms-helper))
 define KernelPackage/drm-display-helper
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=DRM helpers for display adapters drivers
-  DEPENDS:=@DISPLAY_SUPPORT +kmod-drm +TARGET_x86:kmod-drm-buddy @LINUX_6_1
+  DEPENDS:=@DISPLAY_SUPPORT +kmod-drm +(TARGET_x86||TARGET_loongarch64):kmod-drm-buddy @LINUX_6_1||LINUX_6_6
   KCONFIG:=CONFIG_DRM_DISPLAY_HELPER
   FILES:=$(LINUX_DIR)/drivers/gpu/drm/display/drm_display_helper.ko
   AUTOLOAD:=$(call AutoProbe,drm_display_helper)
@@ -376,15 +386,16 @@ $(eval $(call KernelPackage,drm-display-helper))
 define KernelPackage/drm-amdgpu
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=AMDGPU DRM support
-  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \
-	+kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware \
-	+LINUX_6_1:kmod-drm-display-helper +LINUX_6_1:kmod-acpi-video
+  DEPENDS:=@TARGET_x86||TARGET_loongarch64||TARGET_phytium @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \
+	+kmod-drm-ttm-helper +kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware \
+	+kmod-drm-display-helper +kmod-drm-buddy +kmod-acpi-video
   KCONFIG:=CONFIG_DRM_AMDGPU \
 	CONFIG_DRM_AMDGPU_SI=y \
 	CONFIG_DRM_AMDGPU_CIK=y \
 	CONFIG_DRM_AMD_DC=y \
 	CONFIG_DEBUG_KERNEL_DC=n
   FILES:=$(LINUX_DIR)/drivers/gpu/drm/amd/amdgpu/amdgpu.ko \
+  $(LINUX_DIR)/drivers/gpu/drm/amd/amdxcp/amdxcp.ko@ge6.5 \
 	$(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko
   AUTOLOAD:=$(call AutoProbe,amdgpu)
 endef
@@ -393,6 +404,15 @@ define KernelPackage/drm-amdgpu/description
   Direct Rendering Manager (DRM) support for AMDGPU Cards
 endef
 
+define KernelPackage/drm-amdgpu/loongarch64
+  KCONFIG+=CONFIG_DRM_AMDGPU_USERPTR=y \
+	CONFIG_DRM_AMD_DC=y \
+	CONFIG_DRM_AMD_DC_FP=y \
+	CONFIG_DRM_AMD_DC_SI=y
+  FILES+=$(LINUX_DIR)/drivers/gpu/drm/amd/amdxcp/amdxcp.ko
+  AUTOLOAD:=$(call AutoProbe,amdxcp amdgpu)
+endef
+
 $(eval $(call KernelPackage,drm-amdgpu))
 
 
@@ -506,8 +526,8 @@ $(eval $(call KernelPackage,drm-panfrost))
 define KernelPackage/drm-radeon
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=Radeon DRM support
-  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-kms-helper \
-	+kmod-drm-ttm +kmod-i2c-algo-bit +LINUX_6_1:kmod-acpi-video +radeon-firmware
+  DEPENDS:=@TARGET_x86||TARGET_phytium @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-kms-helper \
+	+kmod-drm-ttm +kmod-i2c-algo-bit +(LINUX_6_1||LINUX_6_6):kmod-acpi-video +radeon-firmware
   KCONFIG:=CONFIG_DRM_RADEON
   FILES:=$(LINUX_DIR)/drivers/gpu/drm/radeon/radeon.ko
   AUTOLOAD:=$(call AutoProbe,radeon)
@@ -536,7 +556,7 @@ $(eval $(call KernelPackage,drm-sched))
 define KernelPackage/drm-nouveau
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=nouveau DRM support
-  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-drm-kms-helper +LINUX_6_1:kmod-acpi-video
+  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-drm-kms-helper +(LINUX_6_1||LINUX_6_6):kmod-acpi-video
   KCONFIG:=CONFIG_DRM_NOUVEAU \
 	NOUVEAU_DEBUG=5 \
 	NOUVEAU_DEBUG_DEFAULT=3 \
@@ -560,7 +580,7 @@ define KernelPackage/video-core
   SUBMENU:=$(VIDEO_MENU)
   TITLE=Video4Linux support
   DEPENDS:=+PACKAGE_kmod-i2c-core:kmod-i2c-core \
-	+LINUX_6_1:kmod-media-core
+	+LINUX_6_1||LINUX_6_6:kmod-media-core
   KCONFIG:= \
 	CONFIG_VIDEO_DEV \
 	CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -648,9 +668,10 @@ $(eval $(call KernelPackage,video-pwc))
 define KernelPackage/video-uvc
   TITLE:=USB Video Class (UVC) support
   DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-video-videobuf2 +kmod-input-core
-  KCONFIG:= CONFIG_USB_VIDEO_CLASS
-  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/uvc/uvcvideo.ko
-  AUTOLOAD:=$(call AutoProbe,uvcvideo)
+  KCONFIG:= CONFIG_USB_VIDEO_CLASS CONFIG_UVC_COMMON@ge6.3
+  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/uvc/uvcvideo.ko \
+	$(LINUX_DIR)/drivers/media/common/uvc.ko@ge6.3
+  AUTOLOAD:=$(call AutoProbe,uvc@ge6.3 uvcvideo)
   $(call AddDepends/camera)
 endef
 
@@ -1198,7 +1219,7 @@ define KernelPackage/drm-i915
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=Intel GPU drm support
   DEPENDS:=@TARGET_x86 +kmod-drm-ttm +kmod-drm-kms-helper +i915-firmware \
-	+LINUX_6_1:kmod-drm-display-helper +LINUX_6_1:kmod-acpi-video
+	+(LINUX_6_1||LINUX_6_6):kmod-drm-display-helper +(LINUX_6_1||LINUX_6_6):kmod-acpi-video
   KCONFIG:= \
 	CONFIG_INTEL_GTT \
 	CONFIG_DRM_I915 \
diff --git a/package/kernel/mac80211/patches/build/990-add_kernel_6.6_support.patch b/package/kernel/mac80211/patches/build/990-add_kernel_6.6_support.patch
new file mode 100644
index 00000000000000..074c23b6e68c0b
--- /dev/null
+++ b/package/kernel/mac80211/patches/build/990-add_kernel_6.6_support.patch
@@ -0,0 +1,113 @@
+--- a/net/wireless/sysfs.c
++++ b/net/wireless/sysfs.c
+@@ -165,12 +165,21 @@
+ #define WIPHY_PM_OPS NULL
+ #endif
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++static const void *wiphy_namespace(const struct device *d)
++{
++	struct wiphy *wiphy = container_of(d, struct wiphy, dev);
++
++	return wiphy_net(wiphy);
++}
++#else
+ static const void *wiphy_namespace(struct device *d)
+ {
+ 	struct wiphy *wiphy = container_of(d, struct wiphy, dev);
+ 
+ 	return wiphy_net(wiphy);
+ }
++#endif
+ 
+ struct class ieee80211_class = {
+ 	.name = "ieee80211",
+--- a/net/wireless/nl80211.c
++++ b/net/wireless/nl80211.c
+@@ -16175,8 +16175,14 @@
+ #undef SELECTOR
+ };
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++static int nl80211_pre_doit(const struct genl_split_ops *ops,
++			    struct sk_buff *skb,
++			    struct genl_info *info)
++#else
+ static int nl80211_pre_doit(const struct genl_ops *ops, struct sk_buff *skb,
+ 			    struct genl_info *info)
++#endif
+ {
+ 	struct cfg80211_registered_device *rdev = NULL;
+ 	struct wireless_dev *wdev = NULL;
+@@ -16276,8 +16282,14 @@
+ 	return err;
+ }
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++static void nl80211_post_doit(const struct genl_split_ops *ops,
++			      struct sk_buff *skb,
++			      struct genl_info *info)
++#else
+ static void nl80211_post_doit(const struct genl_ops *ops, struct sk_buff *skb,
+ 			      struct genl_info *info)
++#endif
+ {
+ 	u32 internal_flags = nl80211_internal_flags[ops->internal_flags];
+ 
+--- a/net/mac80211/tx.c
++++ b/net/mac80211/tx.c
+@@ -27,6 +27,10 @@
+ #include <asm/unaligned.h>
+ #include <net/fq_impl.h>
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++#include <net/gso.h>
++#endif
++
+ #include "ieee80211_i.h"
+ #include "driver-ops.h"
+ #include "led.h"
+--- a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c
++++ b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c
+@@ -10,6 +10,10 @@
+ #include <net/ip.h>
+ #include <net/ipv6.h>
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
++#include <net/gso.h>
++#endif
++
+ #include "iwl-trans.h"
+ #include "iwl-eeprom-parse.h"
+ #include "mvm.h"
+--- a/include/net/mac80211.h
++++ b/include/net/mac80211.h
+@@ -1468,6 +1468,7 @@
+ 	RX_ENC_HT,
+ 	RX_ENC_VHT,
+ 	RX_ENC_HE,
++	RX_ENC_EHT,
+ };
+ 
+ /**
+@@ -1530,8 +1531,18 @@
+ 	u32 flag;
+ 	u16 freq: 13, freq_offset: 1;
+ 	u8 enc_flags;
+-	u8 encoding:2, bw:3, he_ru:3;
+-	u8 he_gi:2, he_dcm:1;
++	u8 encoding:3, bw:4;
++	union {
++		struct {
++			u8 he_ru:3;
++			u8 he_gi:2;
++			u8 he_dcm:1;
++		};
++		struct {
++			u8 ru:4;
++			u8 gi:2;
++		} eht;
++	};
+ 	u8 rate_idx;
+ 	u8 nss;
+ 	u8 rx_flags;
diff --git a/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch b/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch
new file mode 100644
index 00000000000000..2bc11efd0047c7
--- /dev/null
+++ b/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch
@@ -0,0 +1,34 @@
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 Nov 2023 07:32:52 +0100
+Subject: [PATCH] mac80211: avoid crashing on invalid band info
+
+Frequent crashes have been observed on MT7916 based platforms. While the
+root of these crashes are currently unknown, they happen when decoding
+rate information of connected STAs in AP mode. The rate-information is
+associated with a band which is not available on the PHY.
+
+Check for this condition in order to avoid crashing the whole system.
+This patch should be removed once the roout cause has been found and
+fixed.
+
+Link: https://github.com/freifunk-gluon/gluon/issues/2980
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+
+--- a/net/mac80211/sta_info.c
++++ b/net/mac80211/sta_info.c
+@@ -2422,6 +2422,13 @@ static void sta_stats_decode_rate(struct
+ 
+ 		sband = local->hw.wiphy->bands[band];
+ 
++		if (!sband) {
++			wiphy_warn(local->hw.wiphy,
++				    "Invalid band %d\n",
++				    band);
++			break;
++		}
++
+ 		if (WARN_ON_ONCE(!sband->bitrates))
+ 			break;
+ 
diff --git a/package/kernel/mt76/patches/002-fix-page-pool.patch b/package/kernel/mt76/patches/002-fix-page-pool.patch
new file mode 100644
index 00000000000000..b8d552ffdcfe22
--- /dev/null
+++ b/package/kernel/mt76/patches/002-fix-page-pool.patch
@@ -0,0 +1,24 @@
+--- a/mac80211.c
++++ b/mac80211.c
+@@ -4,7 +4,9 @@
+  */
+ #include <linux/sched.h>
+ #include <linux/of.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0)
+ #include <net/page_pool.h>
++#endif
+ #include "mt76.h"
+ 
+ #define CHAN2G(_idx, _freq) {			\
+--- a/mt76.h
++++ b/mt76.h
+@@ -15,6 +15,9 @@
+ #include <linux/average.h>
+ #include <linux/soc/mediatek/mtk_wed.h>
+ #include <net/mac80211.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,0)
++#include <net/page_pool/helpers.h>
++#endif
+ #include "util.h"
+ #include "testmode.h"
+ 
diff --git a/package/lean/default-settings/Makefile b/package/lean/default-settings/Makefile
index 0d674ca75613c1..ee3740ef20905e 100644
--- a/package/lean/default-settings/Makefile
+++ b/package/lean/default-settings/Makefile
@@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=default-settings
 PKG_VERSION:=3
-PKG_RELEASE:=8
+PKG_RELEASE:=9
 PKG_LICENSE:=GPLv3
 PKG_LICENSE_FILES:=LICENSE
 
diff --git a/package/lean/default-settings/files/zzz-default-settings b/package/lean/default-settings/files/zzz-default-settings
index a7cd5d3a27c204..262bd05cef5502 100755
--- a/package/lean/default-settings/files/zzz-default-settings
+++ b/package/lean/default-settings/files/zzz-default-settings
@@ -51,7 +51,7 @@ sed -i '/option disabled/d' /etc/config/wireless
 sed -i '/set wireless.radio${devidx}.disabled/d' /lib/wifi/mac80211.sh
 
 sed -i '/DISTRIB_REVISION/d' /etc/openwrt_release
-echo "DISTRIB_REVISION='R23.11.11'" >> /etc/openwrt_release
+echo "DISTRIB_REVISION='R24.1.13'" >> /etc/openwrt_release
 sed -i '/DISTRIB_DESCRIPTION/d' /etc/openwrt_release
 echo "DISTRIB_DESCRIPTION='OpenWrt '" >> /etc/openwrt_release
 
diff --git a/package/libs/libbsd/Makefile b/package/libs/libbsd/Makefile
index 92c7054e3bd3fa..1872e3ce30f3b5 100644
--- a/package/libs/libbsd/Makefile
+++ b/package/libs/libbsd/Makefile
@@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libbsd
 PKG_VERSION:=0.11.7
-PKG_RELEASE:=1
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://libbsd.freedesktop.org/releases
@@ -29,6 +29,8 @@ define Package/libbsd/description
  This library provides useful functions commonly found on BSD systems, and lacking on others like GNU systems, thus making it easier to port projects with strong BSD origins, without needing to embed the same code over and over again on each project.
 endef
 
+TARGET_CFLAGS += -D_LARGEFILE64_SOURCE
+
 define Build/InstallDev
 	$(INSTALL_DIR) $(1)/usr/lib
 	$(INSTALL_DIR) $(1)/usr/lib/pkgconfig
diff --git a/package/libs/libselinux/Makefile b/package/libs/libselinux/Makefile
index 7246d855668dd8..f90d4993c836be 100644
--- a/package/libs/libselinux/Makefile
+++ b/package/libs/libselinux/Makefile
@@ -6,20 +6,21 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libselinux
-PKG_VERSION:=3.3
-PKG_RELEASE:=2
+PKG_VERSION:=3.5
+PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)
-PKG_HASH:=acfdee27633d2496508c28727c3d41d3748076f66d42fccde2e6b9f3463a7057
-HOST_BUILD_DEPENDS:=libsepol/host pcre/host
+PKG_HASH:=9a3a3705ac13a2ccca2de6d652b6356fead10f36fb33115c185c5ccdf29eec19
 
 PKG_LICENSE:=libselinux-1.0
 PKG_LICENSE_FILES:=LICENSE
 PKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 PKG_CPE_ID:=cpe:/a:selinuxproject:libselinux
 
-HOST_BUILD_DEPENDS:=libsepol/host musl-fts/host pcre/host
+PKG_BUILD_FLAGS:=no-lto
+
+HOST_BUILD_DEPENDS:=libsepol/host musl-fts/host pcre2/host
 
 include $(INCLUDE_DIR)/package.mk
 include $(INCLUDE_DIR)/host-build.mk
@@ -72,7 +73,7 @@ define Package/libselinux
   $(call Package/libselinux/Default)
   SECTION:=libs
   CATEGORY:=Libraries
-  DEPENDS:=+libsepol +libpcre +USE_MUSL:musl-fts
+  DEPENDS:=+libsepol +libpcre2 +USE_MUSL:musl-fts
 endef
 
 define Package/libselinux/description
@@ -104,7 +105,7 @@ endef
 $(foreach a,$(LIBSELINUX_UTILS),$(eval $(call GenUtilPkg,libselinux-$(a),$(a))))
 
 # Needed to link libselinux utilities, which link against
-# libselinux.so, which indirectly depends on libpcre.so, installed in
+# libselinux.so, which indirectly depends on libpcre2.so, installed in
 # $(STAGING_DIR_HOSTPKG).
 HOST_LDFLAGS += -Wl,-rpath="$(STAGING_DIR_HOSTPKG)/lib"
 
@@ -115,6 +116,7 @@ HOST_MAKE_FLAGS += \
 
 ifeq ($(CONFIG_USE_MUSL),y)
 MAKE_FLAGS += FTS_LDLIBS=-lfts
+TARGET_CFLAGS += -D_LARGEFILE64_SOURCE
 endif
 
 MAKE_FLAGS += \
diff --git a/package/libs/openssl/patches/110-openwrt_targets.patch b/package/libs/openssl/patches/110-openwrt_targets.patch
index a97c603fa7c224..d02bc03fb89f78 100644
--- a/package/libs/openssl/patches/110-openwrt_targets.patch
+++ b/package/libs/openssl/patches/110-openwrt_targets.patch
@@ -9,7 +9,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
 
 --- /dev/null
 +++ b/Configurations/25-openwrt.conf
-@@ -0,0 +1,56 @@
+@@ -0,0 +1,59 @@
 +## Openwrt "CONFIG_ARCH" matching targets.
 +
 +# The targets need to end in '-openwrt' for the AFALG patch to work
@@ -34,6 +34,9 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
 +    "linux-i386-openwrt" => {
 +        inherit_from    => [ "linux-x86", "openwrt" ],
 +    },
++    "linux-loongarch64-openwrt" => {
++        inherit_from    => [ "linux64-loongarch64", "openwrt" ],
++    },
 +    "linux-mips-openwrt" => {
 +        inherit_from    => [ "linux-mips32", "openwrt" ],
 +    },
diff --git a/package/network/services/hostapd/Makefile b/package/network/services/hostapd/Makefile
index fcf853ba79e46d..d91ba3dbef887c 100644
--- a/package/network/services/hostapd/Makefile
+++ b/package/network/services/hostapd/Makefile
@@ -141,7 +141,7 @@ ifneq ($(LOCAL_TYPE),hostapd)
   endif
 endif
 
-DRV_DEPENDS:=+PACKAGE_kmod-cfg80211:libnl-tiny
+DRV_DEPENDS:=+PACKAGE_kmod-cfg80211:libnl-tiny +kmod-cfg80211
 
 
 define Package/hostapd/Default
diff --git a/package/network/utils/umbim/Makefile b/package/network/utils/umbim/Makefile
index d408f562555136..ac14f4896161be 100644
--- a/package/network/utils/umbim/Makefile
+++ b/package/network/utils/umbim/Makefile
@@ -1,13 +1,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=umbim
-PKG_RELEASE:=3
+PKG_RELEASE:=24
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/umbim.git
-PKG_SOURCE_DATE:=2019-09-11
-PKG_SOURCE_VERSION:=184b707ddaa0acee84d02e0ffe599cb8b67782bd
-PKG_MIRROR_HASH:=482ff69144f81fafed99035840f5a24e772472f2df2f3ac0219d6de791ac5835
+PKG_SOURCE_DATE:=2022-08-13
+PKG_SOURCE_VERSION:=146bc77c98ace3d1cc672986669650d2e1da71f3
+PKG_MIRROR_HASH:=3cf04858ff5c3f529904f9789b094aa9645ad41c91f553e6fc3fcd3cb341d359
 PKG_MAINTAINER:=John Crispin <john@phrozen.org>
 
 PKG_LICENSE:=GPL-2.0
@@ -32,7 +32,7 @@ define Package/umbim/description
 endef
 
 TARGET_CFLAGS += \
-	-I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections -Wno-address-of-packed-member
+	-I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections
 
 TARGET_LDFLAGS += -Wl,--gc-sections
 
diff --git a/package/network/utils/umbim/files/lib/netifd/proto/mbim.sh b/package/network/utils/umbim/files/lib/netifd/proto/mbim.sh
index 11d0d70e072946..ad7b2347c74bd6 100755
--- a/package/network/utils/umbim/files/lib/netifd/proto/mbim.sh
+++ b/package/network/utils/umbim/files/lib/netifd/proto/mbim.sh
@@ -11,36 +11,47 @@ proto_mbim_init_config() {
 	available=1
 	no_device=1
 	proto_config_add_string "device:device"
-	proto_config_add_string pdptype
 	proto_config_add_string apn
 	proto_config_add_string pincode
 	proto_config_add_string delay
+	proto_config_add_boolean allow_roaming
+	proto_config_add_boolean allow_partner
 	proto_config_add_string auth
 	proto_config_add_string username
 	proto_config_add_string password
+	[ -e /proc/sys/net/ipv6 ] && proto_config_add_string ipv6
+	proto_config_add_string dhcp
+	proto_config_add_string dhcpv6
+	proto_config_add_string pdptype
+	proto_config_add_int mtu
 	proto_config_add_defaults
 }
 
+_proto_mbim_get_field() {
+	local field="$1"
+	shift
+	local mbimconfig="$@"
+	echo "$mbimconfig" | while read -r line; do
+		variable=${line%%:*}
+		[ "$variable" = "$field" ] || continue;
+		value=${line##* }
+		echo -n "$value "
+	done
+}
+
 _proto_mbim_setup() {
 	local interface="$1"
 	local tid=2
+	local ret
 
-	local device pdptype apn pincode delay auth username password $PROTO_DEFAULT_OPTIONS
-	json_get_vars device pdptype apn pincode delay auth username password $PROTO_DEFAULT_OPTIONS
+	local device apn pincode delay auth username password allow_roaming allow_partner
+	local dhcp dhcpv6 pdptype ip4table ip6table mtu $PROTO_DEFAULT_OPTIONS
+	json_get_vars device apn pincode delay auth username password allow_roaming allow_partner
+	json_get_vars dhcp dhcpv6 pdptype ip4table ip6table mtu $PROTO_DEFAULT_OPTIONS
 
-	[ -n "$ctl_device" ] && device=$ctl_device
+	[ ! -e /proc/sys/net/ipv6 ] && ipv6=0 || json_get_var ipv6 ipv6
 
-	pdptype=$(echo "$pdptype" | awk '{print tolower($0)}')
-	case "$pdptype" in
-		ip )
-			pdptype="ipv4"
-			;;
-		ipv4 | ipv6 | ipv4v6 | ipv4-and-ipv6 )
-			;;
-		* )
-			pdptype="default"
-			;;
-	esac
+	[ -n "$ctl_device" ] && device=$ctl_device
 
 	[ -n "$device" ] || {
 		echo "mbim[$$]" "No control device specified"
@@ -77,6 +88,8 @@ _proto_mbim_setup() {
 	echo "mbim[$$]" "Reading capabilities"
 	umbim $DBG -n -d $device caps || {
 		echo "mbim[$$]" "Failed to read modem caps"
+		tid=$((tid + 1))
+		umbim $DBG -t $tid -d "$device" disconnect
 		proto_notify_error "$interface" PIN_FAILED
 		return 1
 	}
@@ -86,6 +99,8 @@ _proto_mbim_setup() {
 		echo "mbim[$$]" "Sending pin"
 		umbim $DBG -n -t $tid -d $device unlock "$pincode" || {
 			echo "mbim[$$]" "Unable to verify PIN"
+			tid=$((tid + 1))
+			umbim $DBG -t $tid -d "$device" disconnect
 			proto_notify_error "$interface" PIN_FAILED
 			proto_block_restart "$interface"
 			return 1
@@ -94,129 +109,199 @@ _proto_mbim_setup() {
 	tid=$((tid + 1))
 
 	echo "mbim[$$]" "Checking pin"
-	local pinstate="/var/run/mbim.$$.pinstate"
-	umbim $DBG -n -t $tid -d $device pinstate > "$pinstate" 2>&1 || {
-		local pin
-		pin=$(awk '$2=="pin:" {print $5}' "$pinstate")
-		# we only need pin1 (the SIM pin) to connect
-		[ "$pin" = "pin1" ] && {
-			echo "mbim[$$]" "PIN required"
-			proto_notify_error "$interface" PIN_FAILED
-			proto_block_restart "$interface"
-			return 1
-		}
+	umbim $DBG -n -t $tid -d $device pinstate
+	[ $? -eq 2 ] && {
+		echo "mbim[$$]" "PIN required"
+		tid=$((tid + 1))
+		umbim $DBG -t $tid -d "$device" disconnect
+		proto_notify_error "$interface" PIN_FAILED
+		proto_block_restart "$interface"
+		return 1
 	}
 	tid=$((tid + 1))
 
 	echo "mbim[$$]" "Checking subscriber"
 	umbim $DBG -n -t $tid -d $device subscriber || {
 		echo "mbim[$$]" "Subscriber init failed"
+		tid=$((tid + 1))
+		umbim $DBG -t $tid -d "$device" disconnect
 		proto_notify_error "$interface" NO_SUBSCRIBER
 		return 1
 	}
 	tid=$((tid + 1))
 
 	echo "mbim[$$]" "Register with network"
-	umbim $DBG -n -t $tid -d $device registration || {
-		echo "mbim[$$]" "Subscriber registration failed"
+	connected=0
+	umbim $DBG -n -t $tid -d $device registration
+	reg_status=$?
+	case $reg_status in
+		0)	echo "mbim[$$]" "Registered in home mode"
+			tid=$((tid + 1))
+			connected=1;;
+		4)	if [ "$allow_roaming" = "1" ]; then
+				echo "mbim[$$]" "Registered in roaming mode"
+				tid=$((tid + 1))
+				connected=1
+			fi;;
+		5) 	if [ "$allow_partner" = "1" ]; then
+				echo "mbim[$$]" "Registered in partner mode"
+				tid=$((tid + 1))
+				connected=1
+			fi;;
+	esac
+	if [ $connected -ne 1 ]; then
+		echo "mbim[$$]" "Subscriber registration failed (code $reg_status)"
+		tid=$((tid + 1))
+		umbim $DBG -t $tid -d "$device" disconnect
 		proto_notify_error "$interface" NO_REGISTRATION
 		return 1
-	}
-	tid=$((tid + 1))
+	fi
 
 	echo "mbim[$$]" "Attach to network"
 	umbim $DBG -n -t $tid -d $device attach || {
 		echo "mbim[$$]" "Failed to attach to network"
+		tid=$((tid + 1))
+		umbim $DBG -t $tid -d "$device" disconnect
 		proto_notify_error "$interface" ATTACH_FAILED
 		return 1
 	}
 	tid=$((tid + 1))
 
+	pdptype=$(echo "$pdptype" | awk '{print tolower($0)}')
+	[ "$ipv6" = 0 ] && pdptype="ipv4"
+
+	local req_pdptype="" # Pass "default" PDP type to umbim if unconfigured
+	[ "$pdptype" = "ipv4" -o "$pdptype" = "ipv6" -o "$pdptype" = "ipv4v6" ] && req_pdptype="$pdptype:"
+
+	local connect_state
 	echo "mbim[$$]" "Connect to network"
-	while ! umbim $DBG -n -t $tid -d $device connect "$pdptype:$apn" "$auth" "$username" "$password"; do
+	connect_state=$(umbim $DBG -n -t $tid -d $device connect "$req_pdptype$apn" "$auth" "$username" "$password") || {
+		echo "mbim[$$]" "Failed to connect bearer"
 		tid=$((tid + 1))
-		sleep 1;
-	done
-	tid=$((tid + 1))
-
-	echo "mbim[$$]" "Connected, obtain IP address and configure interface"
-	local config="/var/run/mbim.$$.config"
-	umbim $DBG -n -t $tid -d $device config > "$config" || {
-		echo "mbim[$$]" "Failed to obtain IP address"
-		proto_notify_error "$interface" CONFIG_FAILED
+		umbim $DBG -t $tid -d "$device" disconnect
+		proto_notify_error "$interface" CONNECT_FAILED
 		return 1
 	}
 	tid=$((tid + 1))
 
+	echo "$connect_state"
+	local iptype="$(echo "$connect_state" | grep iptype: | awk '{print $4}')"
+
+	echo "mbim[$$]" "Connected"
+
+	local zone="$(fw3 -q network "$interface" 2>/dev/null)"
+
+	echo "mbim[$$]" "Setting up $ifname"
+	local mbimconfig="$(umbim $DBG -n -t $tid -d $device config)"
+	echo "$mbimconfig"
+	tid=$((tid + 1))
+
 	proto_init_update "$ifname" 1
-	proto_add_data
-	json_add_int tid $tid
-	proto_close_data
 	proto_send_update "$interface"
 
-	local ip_4 ip_6
-	ip_4=$(awk '$1=="ipv4address:" {print $2}' "$config")
-	ip_6=$(awk '$1=="ipv6address:" {print $2}' "$config")
-	[ -n "$ip_4" ] || [ -n "$ip_6" ] || {
-		echo "mbim[$$]" "Failed to obtain IP addresses"
-		proto_notify_error "$interface" CONFIG_FAILED
-		return 1
-	}
+	[ -z "$dhcp" ] && dhcp="auto"
+	[ -z "$dhcpv6" ] && dhcpv6="auto"
 
-	proto_init_update "$ifname" 1
-	proto_set_keep 1
-	local ip mask gateway mtu dns dns_servers
-
-	[ -n "$ip_4" ] && {
-		echo "mbim[$$]" "Configure IPv4 on $ifname"
-		ip=${ip_4%%/*}
-		mask=${ip_4##*/}
-		gateway=$(awk '$1=="ipv4gateway:" {print $2}' "$config")
-		mtu=$(awk '$1=="ipv4mtu:" {print $2}' "$config")
-		[ "$mtu" ] && ip link set "$ifname" mtu "$mtu"
-
-		proto_add_ipv4_address "$ip" "$mask"
-		[ "$defaultroute" = 0 ] || proto_add_ipv4_route 0.0.0.0 0 "$gateway" "$ip_4" "$metric"
-		[ "$peerdns" = 0 ] || {
-			dns_servers=$(awk '$1=="ipv4dnsserver:" {printf "%s ",$2}' "$config")
-			for dns in $dns_servers; do
-				proto_add_dns_server "$dns"
+	[ "$iptype" != "ipv6" ] && {
+		json_init
+		json_add_string name "${interface}_4"
+		json_add_string ifname "@$interface"
+		ipv4address=$(_proto_mbim_get_field ipv4address "$mbimconfig")
+		if [ -n "$ipv4address" -a "$dhcp" != 1 ]; then
+			json_add_string proto "static"
+
+			json_add_array ipaddr
+			for address in $ipv4address; do
+				json_add_string "" "$address"
 			done
+			json_close_array
+
+			json_add_string gateway $(_proto_mbim_get_field ipv4gateway "$mbimconfig")
+		elif [ "$dhcp" != 0 ]; then
+			echo "mbim[$$]" "Starting DHCP on $ifname"
+			json_add_string proto "dhcp"
+		fi
+
+		[ "$peerdns" = 0 -a "$dhcp" != 1 ] || {
+			json_add_array dns
+			for server in $(_proto_mbim_get_field ipv4dnsserver "$mbimconfig"); do
+				json_add_string "" "$server"
+			done
+			json_close_array
 		}
 
+		proto_add_dynamic_defaults
+		[ -n "$zone" ] && json_add_string zone "$zone"
+		[ -n "$ip4table" ] && json_add_string ip4table "$ip4table"
+		json_close_object
+		ubus call network add_dynamic "$(json_dump)"
 	}
-	[ -n "$ip_6" ] && {
-		echo "mbim[$$]" "Configure IPv6 on $ifname"
-		ip=${ip_6%%/*}
-		mask=${ip_6##*/}
-		gateway=$(awk '$1=="ipv6gateway:" {print $2}' "$config")
-		mtu=$(awk '$1=="ipv6mtu:" {print $2}' "$config")
-		[ "$mtu" ] && ip -6 link set "$ifname" mtu "$mtu"
-
-		proto_add_ipv6_address "$ip" "128"
-		proto_add_ipv6_prefix "$ip_6"
-		proto_add_ipv6_route "$gateway" "128"
-		[ "$defaultroute" = 0 ] || proto_add_ipv6_route "::" 0 "$gateway" "$metric" "" "$ip_6"
-		[ "$peerdns" = 0 ] || {
-			dns_servers=$(awk '$1=="ipv6dnsserver:" {printf "%s ",$2}' "$config")
-			for dns in $dns_servers; do
-				proto_add_dns_server "$dns"
+
+	[ "$iptype" != "ipv4" ] && {
+		json_init
+		json_add_string name "${interface}_6"
+		json_add_string ifname "@$interface"
+		ipv6address=$(_proto_mbim_get_field ipv6address "$mbimconfig")
+		if [ -n "$ipv6address" -a "$dhcpv6" != 1 ]; then
+			json_add_string proto "static"
+
+			json_add_array ip6addr
+			for address in $ipv6address; do
+				json_add_string "" "$address"
 			done
+			json_close_array
+
+			json_add_array ip6prefix
+			for address in $ipv6address; do
+				json_add_string "" "$address"
+			done
+			json_close_array
+
+			json_add_string ip6gw $(_proto_mbim_get_field ipv6gateway "$mbimconfig")
+
+		elif [ "$dhcpv6" != 0 ]; then
+			echo "mbim[$$]" "Starting DHCPv6 on $ifname"
+			json_add_string proto "dhcpv6"
+			json_add_string extendprefix 1
+		fi
+
+		[ "$peerdns" = 0 -a "$dhcpv6" != 1 ] || {
+			json_add_array dns
+			for server in $(_proto_mbim_get_field ipv6dnsserver "$mbimconfig"); do
+				json_add_string "" "$server"
+			done
+			json_close_array
 		}
+
+		proto_add_dynamic_defaults
+		[ -n "$zone" ] && json_add_string zone "$zone"
+		[ -n "$ip6table" ] && json_add_string ip6table "$ip6table"
+		json_close_object
+		ubus call network add_dynamic "$(json_dump)"
 	}
 
-	proto_send_update "$interface"
-	echo "mbim[$$]" "Connection setup complete"
+	[ -z "$mtu" ] && {
+		local ipv4mtu=$(_proto_mbim_get_field ipv4mtu "$mbimconfig")
+		ipv4mtu="${ipv4mtu:-0}"
+		local ipv6mtu=$(_proto_mbim_get_field ipv6mtu "$mbimconfig")
+		ipv6mtu="${ipv6mtu:-0}"
+
+		mtu=$((ipv6mtu > ipv4mtu ? ipv6mtu : ipv4mtu))
+	}
+	[ -n "$mtu" -a "$mtu" != 0 ] && {
+		echo Setting MTU of $ifname to $mtu
+		/sbin/ip link set dev $ifname mtu $mtu
+	}
+
+	uci_set_state network $interface tid "$tid"
 }
 
 proto_mbim_setup() {
 	local ret
 
-	_proto_mbim_setup "$@"
+	_proto_mbim_setup $@
 	ret=$?
 
-	rm -f "/var/run/mbim.$$."*
-
 	[ "$ret" = 0 ] || {
 		logger "mbim bringup failed, retry in 15s"
 		sleep 15
@@ -228,13 +313,17 @@ proto_mbim_setup() {
 proto_mbim_teardown() {
 	local interface="$1"
 
-	local device tid
-	json_get_vars device tid
+	local device
+	json_get_vars device
+	local tid=$(uci_get_state network $interface tid)
 
 	[ -n "$ctl_device" ] && device=$ctl_device
 
 	echo "mbim[$$]" "Stopping network"
-	[ -n "$tid" ] && umbim $DBG -t$tid -d "$device" disconnect
+	[ -n "$tid" ] && {
+		umbim $DBG -t $tid -d "$device" disconnect
+		uci_revert_state network $interface tid
+	}
 
 	proto_init_update "*" 0
 	proto_send_update "$interface"
diff --git a/package/network/utils/uqmi/Makefile b/package/network/utils/uqmi/Makefile
index c4ca98012a0fbc..26eeee12a630e7 100644
--- a/package/network/utils/uqmi/Makefile
+++ b/package/network/utils/uqmi/Makefile
@@ -1,7 +1,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=uqmi
-PKG_RELEASE:=$(AUTORELEASE)
+PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/uqmi.git
@@ -31,8 +31,11 @@ define Package/uqmi/description
   the QMI-protocol.
 endef
 
-TARGET_CFLAGS += \
-	-I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections
+TARGET_CFLAGS += -I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections
+
+ifneq (,$(findstring $(GCC_MAJOR_VERSION), 12 13))
+	TARGET_CFLAGS += -Wno-error=dangling-pointer -Wno-error=maybe-uninitialized
+endif
 
 TARGET_LDFLAGS += -Wl,--gc-sections
 
diff --git a/package/utils/e2fsprogs/Makefile b/package/utils/e2fsprogs/Makefile
index 94f22a53cc8138..2657077a16be29 100644
--- a/package/utils/e2fsprogs/Makefile
+++ b/package/utils/e2fsprogs/Makefile
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=e2fsprogs
-PKG_VERSION:=1.46.5
+PKG_VERSION:=1.47.0
 PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/linux/kernel/people/tytso/e2fsprogs/v$(PKG_VERSION)/
-PKG_HASH:=2f16c9176704cf645dc69d5b15ff704ae722d665df38b2ed3cfc249757d8d81e
+PKG_HASH:=144af53f2bbd921cef6f8bea88bb9faddca865da3fbc657cc9b4d2001097d5db
 
 PKG_LICENSE:=GPL-2.0
 PKG_LICENSE_FILES:=NOTICE
@@ -23,6 +23,7 @@ PKG_BUILD_DEPENDS:=util-linux e2fsprogs/host
 PKG_INSTALL:=1
 
 PKG_BUILD_PARALLEL:=1
+PKG_BUILD_FLAGS:=gc-sections lto
 
 include $(INCLUDE_DIR)/package.mk
 include $(INCLUDE_DIR)/host-build.mk
@@ -142,9 +143,7 @@ $(call Package/e2fsprogs)
   DEPENDS:= +e2fsprogs
 endef
 
-TARGET_CFLAGS += $(FPIC) -ffunction-sections -fdata-sections -flto
-
-TARGET_LDFLAGS += -flto
+TARGET_CFLAGS += $(FPIC)
 
 CONFIGURE_ARGS += \
 	--disable-testio-debug \
@@ -157,6 +156,10 @@ CONFIGURE_ARGS += \
 	--disable-rpath		\
 	--disable-fuse2fs
 
+ifneq ($(CONFIG_USE_MUSL),)
+  CONFIGURE_VARS += ac_cv_func_lseek64=yes
+endif
+
 define Build/Prepare
 	$(call Build/Prepare/Default)
 	$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(PKG_BUILD_DIR)/config/
@@ -171,7 +174,6 @@ define Build/Compile
 		V=$(if $(findstring c,$(OPENWRT_VERBOSE)),1,) \
 		subst
 	+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
-		LDFLAGS=-Wl,--gc-sections \
 		BUILDCC="$(HOSTCC)" \
 		DESTDIR="$(PKG_INSTALL_DIR)" \
 		ELF_OTHER_LIBS="$(TARGET_LDFLAGS) -luuid" \
@@ -265,7 +267,6 @@ endef
 define Package/tune2fs/install
 	$(INSTALL_DIR) $(1)/usr/sbin
 	$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/tune2fs $(1)/usr/sbin/
-	$(LN) tune2fs $(1)/usr/sbin/findfs
 endef
 
 define Package/resize2fs/install
diff --git a/package/utils/e2fsprogs/patches/004-CVE-2022-1304-libext2fs-add-sanity-check-to-extent-manipulation.patch b/package/utils/e2fsprogs/patches/004-CVE-2022-1304-libext2fs-add-sanity-check-to-extent-manipulation.patch
deleted file mode 100644
index e5a76161f210dd..00000000000000
--- a/package/utils/e2fsprogs/patches/004-CVE-2022-1304-libext2fs-add-sanity-check-to-extent-manipulation.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From ab51d587bb9b229b1fade1afd02e1574c1ba5c76 Mon Sep 17 00:00:00 2001
-From: Lukas Czerner <lczerner@redhat.com>
-Date: Thu, 21 Apr 2022 19:31:48 +0200
-Subject: libext2fs: add sanity check to extent manipulation
-
-It is possible to have a corrupted extent tree in such a way that a leaf
-node contains zero extents in it. Currently if that happens and we try
-to traverse the tree we can end up accessing wrong data, or possibly
-even uninitialized memory. Make sure we don't do that.
-
-Additionally make sure that we have a sane number of bytes passed to
-memmove() in ext2fs_extent_delete().
-
-Note that e2fsck is currently unable to spot and fix such corruption in
-pass1.
-
-Signed-off-by: Lukas Czerner <lczerner@redhat.com>
-Reported-by: Nils Bars <nils_bars@t-online.de>
-Addresses: https://bugzilla.redhat.com/show_bug.cgi?id=2068113
-Addresses: CVE-2022-1304
-Addresses-Debian-Bug: #1010263
-Signed-off-by: Theodore Ts'o <tytso@mit.edu>
----
- lib/ext2fs/extent.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/lib/ext2fs/extent.c
-+++ b/lib/ext2fs/extent.c
-@@ -495,6 +495,10 @@ retry:
- 			ext2fs_le16_to_cpu(eh->eh_entries);
- 		newpath->max_entries = ext2fs_le16_to_cpu(eh->eh_max);
- 
-+		/* Make sure there is at least one extent present */
-+		if (newpath->left <= 0)
-+			return EXT2_ET_EXTENT_NO_DOWN;
-+
- 		if (path->left > 0) {
- 			ix++;
- 			newpath->end_blk = ext2fs_le32_to_cpu(ix->ei_block);
-@@ -1630,6 +1634,10 @@ errcode_t ext2fs_extent_delete(ext2_exte
- 
- 	cp = path->curr;
- 
-+	/* Sanity check before memmove() */
-+	if (path->left < 0)
-+		return EXT2_ET_EXTENT_LEAF_BAD;
-+
- 	if (path->left) {
- 		memmove(cp, cp + sizeof(struct ext3_extent_idx),
- 			path->left * sizeof(struct ext3_extent_idx));
diff --git a/package/utils/f2fs-tools/Makefile b/package/utils/f2fs-tools/Makefile
index 99d402af6ca552..d5dc1a6d7824a1 100644
--- a/package/utils/f2fs-tools/Makefile
+++ b/package/utils/f2fs-tools/Makefile
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=f2fs-tools
-PKG_VERSION:=1.15.0
-PKG_RELEASE:=1
+PKG_VERSION:=1.16.0
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git/snapshot/
-PKG_HASH:=147d471040b44900283ce2c935f1d35d13d7f40008e7cb8fab2b69f54da01a4f
+PKG_HASH:=208c7a07e95383fbd7b466b5681590789dcb41f41bf197369c41a95383b57c5e
 
 PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
 PKG_LICENSE:=GPL-2.0-only
@@ -111,6 +111,10 @@ endif
 CONFIGURE_VARS += \
 	ac_cv_file__git=no
 
+ifneq ($(CONFIG_USE_MUSL),)
+  CONFIGURE_VARS += ac_cv_func_lseek64=yes
+endif
+
 define Package/libf2fs/install
 	$(INSTALL_DIR) $(1)/usr/lib
 	$(CP) \
@@ -129,17 +133,16 @@ Package/mkf2fs-selinux/install = $(Package/mkf2fs/install)
 define Package/f2fsck/install
 	$(INSTALL_DIR) $(1)/usr/sbin
 	$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fsck.f2fs $(1)/usr/sbin
-	ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/defrag.f2fs
-	ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/dump.f2fs
-	ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/sload.f2fs
-	ln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/resize.f2fs
+	$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/defrag.f2fs
+	$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/dump.f2fs
+	$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/sload.f2fs
+	$(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/resize.f2fs
 endef
 
 Package/f2fsck-selinux/install = $(Package/f2fsck/install)
 
 define Package/f2fs-tools/install
 	$(INSTALL_DIR) $(1)/usr/sbin
-	$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/f2fstat $(1)/usr/sbin
 	$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fibmap.f2fs $(1)/usr/sbin
 	$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/parse.f2fs $(1)/usr/sbin
 endef
diff --git a/package/utils/f2fs-tools/patches/100-configure.ac-fix-AC_ARG_WITH.patch b/package/utils/f2fs-tools/patches/100-configure.ac-fix-AC_ARG_WITH.patch
deleted file mode 100644
index a7fb50a63d1fe4..00000000000000
--- a/package/utils/f2fs-tools/patches/100-configure.ac-fix-AC_ARG_WITH.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 9af8ee5baceab59d46154c96da62b52935f363fe Mon Sep 17 00:00:00 2001
-From: Nick Hainke <vincent@systemli.org>
-Date: Mon, 27 Jun 2022 20:43:11 +0200
-Subject: [PATCH] configure.ac: fix AC_ARG_WITH
-
-In the new version the configuration no longer respects the
---without/--with blkid/selinux parameters. Add the tests for
-"with_blkid" and "with_selinux" back to configure.ac as described
-in the manual.
-
-Link: https://www.gnu.org/software/autoconf/manual/autoconf-2.60/html_node/External-Software.html
-
-Fixes: 	c48335416a09 ("configure.ac: Enable cross-compilation")
-
-Signed-off-by: Nick Hainke <vincent@systemli.org>
----
- configure.ac | 44 ++++++++++++++++++++++++++++++--------------
- 1 file changed, 30 insertions(+), 14 deletions(-)
-
---- a/configure.ac
-+++ b/configure.ac
-@@ -39,12 +39,16 @@ AM_INIT_AUTOMAKE([-Wall -Werror foreign
- 
- # Test configure options.
- AC_ARG_WITH([selinux],
--	AS_HELP_STRING([--without-selinux],
--	  [Ignore presence of libselinux and disable selinux support]))
-+	[AS_HELP_STRING([--without-selinux],
-+	  [Ignore presence of libselinux and disable selinux support])],
-+	[],
-+	[with_selinux=check])
- 
- AC_ARG_WITH([blkid],
--	AS_HELP_STRING([--without-blkid],
--	  [Ignore presence of libblkid and disable blkid support]))
-+	[AS_HELP_STRING([--without-blkid],
-+	  [Ignore presence of libblkid and disable blkid support])],
-+	[],
-+	[with_blkid=check])
- 
- # Checks for programs.
- AC_PROG_CC
-@@ -55,11 +59,17 @@ AC_PATH_PROG([LDCONFIG], [ldconfig],
-        [$PATH:/sbin])
- 
- # Checks for libraries.
--AC_CHECK_LIB([blkid], [blkid_probe_all],
--	[AC_SUBST([libblkid_LIBS], ["-lblkid"])
--		AC_DEFINE([HAVE_LIBBLKID], [1],
--		[Define if you have libblkid])
--	], [], [])
-+AS_IF([test "x$with_blkid" != xno],
-+	[AC_CHECK_LIB([blkid], [blkid_probe_all],
-+		[AC_SUBST([libblkid_LIBS], ["-lblkid"])
-+			AC_DEFINE([HAVE_LIBBLKID], [1],
-+			[Define if you have libblkid])
-+		],
-+		[if test "x$with_blkid" != xcheck; then
-+			AC_MSG_FAILURE(
-+                [--with-blkid was given, but test for blkid failed])
-+        fi
-+	], -lblkid)])
- 
- AC_CHECK_LIB([lzo2], [main],
- 	[AC_SUBST([liblzo2_LIBS], ["-llzo2"])
-@@ -73,11 +83,17 @@ AC_CHECK_LIB([lz4], [main],
- 		[Define if you have liblz4])
- 	], [], [])
- 
--AC_CHECK_LIB([selinux], [getcon],
--	[AC_SUBST([libselinux_LIBS], ["-lselinux"])
--		AC_DEFINE([HAVE_LIBSELINUX], [1],
--		[Define if you have libselinux])
--	], [], [])
-+AS_IF([test "x$with_selinux" != xno],
-+	[AC_CHECK_LIB([selinux], [getcon],
-+		[AC_SUBST([libselinux_LIBS], ["-lselinux"])
-+			AC_DEFINE([HAVE_LIBSELINUX], [1],
-+			[Define if you have libselinux])
-+		],
-+		[if test "x$with_selinux" != xcheck; then
-+			AC_MSG_FAILURE(
-+				[--with-selinux was given, but test for selinux failed])
-+		fi
-+	], -lselinux)])
- 
- AC_CHECK_LIB([uuid], [uuid_clear],
- 	[AC_SUBST([libuuid_LIBS], ["-luuid"])
diff --git a/package/utils/f2fs-tools/patches/101-configure.ac-fix-cross-compilation.patch b/package/utils/f2fs-tools/patches/101-configure.ac-fix-cross-compilation.patch
deleted file mode 100644
index b9edd6634b8c93..00000000000000
--- a/package/utils/f2fs-tools/patches/101-configure.ac-fix-cross-compilation.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 821a1d3fcce31c234512a8f4dc4fc97dfbd7ae32 Mon Sep 17 00:00:00 2001
-From: Nick Hainke <vincent@systemli.org>
-Date: Mon, 4 Jul 2022 09:46:10 +0200
-Subject: [PATCH] configure.ac: fix cross compilation
-
-AC_CHECK_LIB seems to not work correctly with OpenWrt. Add possibility
-to disable lz4 and lzo2 manually.
-
-Fixes errors in the form of:
-  Package f2fsck is missing dependencies for the following libraries:
-  liblz4.so.1
-  liblzo2.so.2
-
-Signed-off-by: Nick Hainke <vincent@systemli.org>
----
- configure.ac | 44 ++++++++++++++++++++++++++++++++++----------
- 1 file changed, 34 insertions(+), 10 deletions(-)
-
---- a/configure.ac
-+++ b/configure.ac
-@@ -50,6 +50,18 @@ AC_ARG_WITH([blkid],
- 	[],
- 	[with_blkid=check])
- 
-+AC_ARG_WITH([lzo2],
-+	[AS_HELP_STRING([--without-lzo2],
-+	  [Ignore presence of liblzo2 and disable lzo2 support])],
-+	[],
-+	[with_lzo2=check])
-+
-+AC_ARG_WITH([lz4],
-+	[AS_HELP_STRING([--without-lz4],
-+	  [Ignore presence of liblz4 and disable lz4 support])],
-+	[],
-+	[with_lz4=check])
-+
- # Checks for programs.
- AC_PROG_CC
- AM_PROG_AR
-@@ -71,17 +83,29 @@ AS_IF([test "x$with_blkid" != xno],
-         fi
- 	], -lblkid)])
- 
--AC_CHECK_LIB([lzo2], [main],
--	[AC_SUBST([liblzo2_LIBS], ["-llzo2"])
--		AC_DEFINE([HAVE_LIBLZO2], [1],
--		[Define if you have liblzo2])
--	], [], [])
--
--AC_CHECK_LIB([lz4], [main],
--	[AC_SUBST([liblz4_LIBS], ["-llz4"])
--		AC_DEFINE([HAVE_LIBLZ4], [1],
--		[Define if you have liblz4])
--	], [], [])
-+AS_IF([test "x$with_lzo2" != xno],
-+	[AC_CHECK_LIB([lzo2], [main],
-+		[AC_SUBST([liblzo2_LIBS], ["-llzo2"])
-+			AC_DEFINE([HAVE_LIBLZO2], [1],
-+			[Define if you have liblzo2])
-+		],
-+		[if test "x$with_lzo2" != xcheck; then
-+			AC_MSG_FAILURE(
-+                [--with-lzo2 was given, but test for lzo2 failed])
-+        fi
-+	], -llzo2)])
-+
-+AS_IF([test "x$with_lz4" != xno],
-+	[AC_CHECK_LIB([lz4], [main],
-+		[AC_SUBST([liblz4_LIBS], ["-llz4"])
-+			AC_DEFINE([HAVE_LIBLZ4], [1],
-+			[Define if you have liblz4])
-+		],
-+		[if test "x$with_lz4" != xcheck; then
-+			AC_MSG_FAILURE(
-+                [--with-lz4 was given, but test for lz4 failed])
-+        fi
-+	], -llz4)])
- 
- AS_IF([test "x$with_selinux" != xno],
- 	[AC_CHECK_LIB([selinux], [getcon],
diff --git a/package/utils/mdadm/Makefile b/package/utils/mdadm/Makefile
index 553728194ec44e..9a56eff8a3dbc0 100644
--- a/package/utils/mdadm/Makefile
+++ b/package/utils/mdadm/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=mdadm
 PKG_VERSION:=4.2
-PKG_RELEASE:=1
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/linux/utils/raid/mdadm
@@ -49,7 +49,8 @@ TARGET_CFLAGS += \
 	-DMAP_DIR='\"/var/run/mdadm\"' \
 	-DMDMON_DIR='\"/var/run/mdadm\"' \
 	-DFAILED_SLOTS_DIR='\"/var/run/mdadm/failed-slots\"' \
-	-DNO_LIBUDEV
+	-DNO_LIBUDEV \
+	-D_LARGEFILE64_SOURCE
 
 TARGET_CXFLAGS = -DNO_LIBUDEV
 
diff --git a/target/Config.in b/target/Config.in
index ac0f1f9826bf9d..c2395923d4d361 100644
--- a/target/Config.in
+++ b/target/Config.in
@@ -156,6 +156,10 @@ config i386
 config i686
 	bool 
 
+config loongarch64
+	select ARCH_64BIT
+	bool
+
 config m68k
 	bool
 
@@ -220,6 +224,7 @@ config ARCH
 	default "armeb"     if armeb
 	default "i386"      if i386
 	default "i686"      if i686
+	default "loongarch64" if loongarch64
 	default "m68k"      if m68k
 	default "mips"      if mips
 	default "mipsel"    if mipsel
diff --git a/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch
index 68b831036576c2..4ca7abdd470d36 100644
--- a/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch
+++ b/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch
@@ -13,7 +13,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -929,6 +929,17 @@ config LEDS_ACER_A500
+@@ -930,6 +930,17 @@ config LEDS_ACER_A500
  	  This option enables support for the Power Button LED of
  	  Acer Iconia Tab A500.
  
diff --git a/target/linux/ath79/patches-5.15/0003-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-5.15/0003-leds-add-reset-controller-based-driver.patch
index 7122756c526687..9daea4c95ab4b5 100644
--- a/target/linux/ath79/patches-5.15/0003-leds-add-reset-controller-based-driver.patch
+++ b/target/linux/ath79/patches-5.15/0003-leds-add-reset-controller-based-driver.patch
@@ -13,7 +13,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -876,6 +876,17 @@ source "drivers/leds/blink/Kconfig"
+@@ -877,6 +877,17 @@ source "drivers/leds/blink/Kconfig"
  comment "Flash and Torch LED drivers"
  source "drivers/leds/flash/Kconfig"
  
diff --git a/target/linux/bcm27xx/patches-5.15/950-0030-Revert-Bluetooth-Always-request-for-user-confirmatio.patch b/target/linux/bcm27xx/patches-5.15/950-0030-Revert-Bluetooth-Always-request-for-user-confirmatio.patch
index 9541eb149f457d..c1925ba890c1d0 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0030-Revert-Bluetooth-Always-request-for-user-confirmatio.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0030-Revert-Bluetooth-Always-request-for-user-confirmatio.patch
@@ -24,7 +24,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/net/bluetooth/smp.c
 +++ b/net/bluetooth/smp.c
-@@ -2207,7 +2207,7 @@ mackey_and_ltk:
+@@ -2214,7 +2214,7 @@ mackey_and_ltk:
  	if (err)
  		return SMP_UNSPECIFIED;
  
@@ -33,7 +33,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  		if (hcon->out) {
  			sc_dhkey_check(smp);
  			SMP_ALLOW_CMD(smp, SMP_CMD_DHKEY_CHECK);
-@@ -2222,9 +2222,6 @@ mackey_and_ltk:
+@@ -2229,9 +2229,6 @@ mackey_and_ltk:
  	confirm_hint = 0;
  
  confirm:
diff --git a/target/linux/bcm27xx/patches-5.15/950-0043-watchdog-bcm2835-Support-setting-reboot-partition.patch b/target/linux/bcm27xx/patches-5.15/950-0043-watchdog-bcm2835-Support-setting-reboot-partition.patch
index fde67981807a9b..44cfcd64e1cc64 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0043-watchdog-bcm2835-Support-setting-reboot-partition.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0043-watchdog-bcm2835-Support-setting-reboot-partition.patch
@@ -36,7 +36,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  
  #define SECS_TO_WDOG_TICKS(x) ((x) << 16)
  #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
-@@ -97,9 +91,24 @@ static unsigned int bcm2835_wdt_get_time
+@@ -98,9 +92,24 @@ static unsigned int bcm2835_wdt_get_time
  	return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
  }
  
@@ -63,7 +63,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  
  	/* use a timeout of 10 ticks (~150us) */
  	writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
-@@ -117,7 +126,13 @@ static int bcm2835_restart(struct watchd
+@@ -118,7 +127,13 @@ static int bcm2835_restart(struct watchd
  {
  	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  
@@ -78,7 +78,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  
  	return 0;
  }
-@@ -152,19 +167,9 @@ static struct watchdog_device bcm2835_wd
+@@ -153,19 +168,9 @@ static struct watchdog_device bcm2835_wd
  static void bcm2835_power_off(void)
  {
  	struct bcm2835_wdt *wdt = bcm2835_power_off_wdt;
diff --git a/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch b/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch
index 2f8829398588e1..848ac83e3a0618 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch
@@ -244,7 +244,7 @@ bcm2835-mmc: uninitialized_var is no more
  static inline int mmc_blk_part_switch(struct mmc_card *card,
  				      unsigned int part_type);
  static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
-@@ -2944,6 +2951,8 @@ static int mmc_blk_probe(struct mmc_card
+@@ -2946,6 +2953,8 @@ static int mmc_blk_probe(struct mmc_card
  {
  	struct mmc_blk_data *md;
  	int ret = 0;
@@ -253,7 +253,7 @@ bcm2835-mmc: uninitialized_var is no more
  
  	/*
  	 * Check that the card supports the command class(es) we need.
-@@ -2951,7 +2960,16 @@ static int mmc_blk_probe(struct mmc_card
+@@ -2953,7 +2962,16 @@ static int mmc_blk_probe(struct mmc_card
  	if (!(card->csd.cmdclass & CCC_BLOCK_READ))
  		return -ENODEV;
  
@@ -271,7 +271,7 @@ bcm2835-mmc: uninitialized_var is no more
  
  	card->complete_wq = alloc_workqueue("mmc_complete",
  					WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
-@@ -2966,6 +2984,17 @@ static int mmc_blk_probe(struct mmc_card
+@@ -2968,6 +2986,17 @@ static int mmc_blk_probe(struct mmc_card
  		goto out_free;
  	}
  
diff --git a/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch b/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch
index 711bd0025f3de4..f2016a48ad7c3c 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch
@@ -12,7 +12,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
 
 --- a/drivers/tty/serial/sc16is7xx.c
 +++ b/drivers/tty/serial/sc16is7xx.c
-@@ -708,6 +708,8 @@ static bool sc16is7xx_port_irq(struct sc
+@@ -709,6 +709,8 @@ static bool sc16is7xx_port_irq(struct sc
  
  			if (rxlen)
  				sc16is7xx_handle_rx(port, rxlen, iir);
diff --git a/target/linux/bcm27xx/patches-5.15/950-0144-bcmgenet-Better-coalescing-parameter-defaults.patch b/target/linux/bcm27xx/patches-5.15/950-0144-bcmgenet-Better-coalescing-parameter-defaults.patch
index 69e99c5f99b84a..ebffb634cd5625 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0144-bcmgenet-Better-coalescing-parameter-defaults.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0144-bcmgenet-Better-coalescing-parameter-defaults.patch
@@ -18,7 +18,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
 
 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
 +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -2616,7 +2616,7 @@ static void bcmgenet_init_tx_ring(struct
+@@ -2618,7 +2618,7 @@ static void bcmgenet_init_tx_ring(struct
  
  	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
  	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
@@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
  	/* Disable rate control for now */
  	bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
  				  TDMA_FLOW_PERIOD);
-@@ -4084,9 +4084,12 @@ static int bcmgenet_probe(struct platfor
+@@ -4086,9 +4086,12 @@ static int bcmgenet_probe(struct platfor
  	netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
  
  	/* Set default coalescing parameters */
diff --git a/target/linux/bcm27xx/patches-5.15/950-0165-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch b/target/linux/bcm27xx/patches-5.15/950-0165-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch
index b18208276378e5..318681ff9101a0 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0165-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0165-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch
@@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
  
  static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  {
-@@ -2447,6 +2450,11 @@ static void reset_umac(struct bcmgenet_p
+@@ -2449,6 +2452,11 @@ static void reset_umac(struct bcmgenet_p
  	bcmgenet_rbuf_ctrl_set(priv, 0);
  	udelay(10);
  
diff --git a/target/linux/bcm27xx/patches-5.15/950-0208-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch b/target/linux/bcm27xx/patches-5.15/950-0208-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
index b668a94790f9d2..c26aa9f1d2ca35 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0208-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0208-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
@@ -32,7 +32,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -3480,6 +3480,7 @@ static int __spi_validate_bits_per_word(
+@@ -3492,6 +3492,7 @@ static int __spi_validate_bits_per_word(
   */
  int spi_setup(struct spi_device *spi)
  {
@@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	unsigned	bad_bits, ugly_bits;
  	int		status;
  
-@@ -3501,6 +3502,14 @@ int spi_setup(struct spi_device *spi)
+@@ -3513,6 +3514,14 @@ int spi_setup(struct spi_device *spi)
  		(SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
  		 SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
  		return -EINVAL;
diff --git a/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch b/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch
index 88b3a6125efe77..ce66193e7744f2 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch
@@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/tty/serial/sc16is7xx.c
 +++ b/drivers/tty/serial/sc16is7xx.c
-@@ -523,8 +523,9 @@ static int sc16is7xx_set_baud(struct uar
+@@ -524,8 +524,9 @@ static int sc16is7xx_set_baud(struct uar
  
  	/* Enable enhanced features */
  	regcache_cache_bypass(s->regmap, true);
@@ -38,7 +38,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	regcache_cache_bypass(s->regmap, false);
  
  	/* Put LCR back to the normal mode */
-@@ -854,7 +855,7 @@ static unsigned int sc16is7xx_get_mctrl(
+@@ -855,7 +856,7 @@ static unsigned int sc16is7xx_get_mctrl(
  	/* DCD and DSR are not wired and CTS/RTS is handled automatically
  	 * so just indicate DSR and CAR asserted
  	 */
@@ -47,7 +47,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  }
  
  static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
-@@ -941,14 +942,19 @@ static void sc16is7xx_set_termios(struct
+@@ -942,14 +943,19 @@ static void sc16is7xx_set_termios(struct
  	regcache_cache_bypass(s->regmap, true);
  	sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
  	sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
diff --git a/target/linux/bcm27xx/patches-5.15/950-0292-net-bcmgenet-Reset-RBUF-on-first-open.patch b/target/linux/bcm27xx/patches-5.15/950-0292-net-bcmgenet-Reset-RBUF-on-first-open.patch
index 254376ee052a69..21cd9dfc039849 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0292-net-bcmgenet-Reset-RBUF-on-first-open.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0292-net-bcmgenet-Reset-RBUF-on-first-open.patch
@@ -24,7 +24,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
 +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -3265,7 +3265,7 @@ static void bcmgenet_get_hw_addr(struct
+@@ -3267,7 +3267,7 @@ static void bcmgenet_get_hw_addr(struct
  }
  
  /* Returns a reusable dma control register value */
@@ -33,7 +33,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  {
  	unsigned int i;
  	u32 reg;
-@@ -3290,6 +3290,14 @@ static u32 bcmgenet_dma_disable(struct b
+@@ -3292,6 +3292,14 @@ static u32 bcmgenet_dma_disable(struct b
  	udelay(10);
  	bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
  
@@ -48,7 +48,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	return dma_ctrl;
  }
  
-@@ -3353,8 +3361,8 @@ static int bcmgenet_open(struct net_devi
+@@ -3355,8 +3363,8 @@ static int bcmgenet_open(struct net_devi
  
  	bcmgenet_set_hw_addr(priv, dev->dev_addr);
  
@@ -59,7 +59,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  
  	/* Reinitialize TDMA and RDMA and SW housekeeping */
  	ret = bcmgenet_init_dma(priv);
-@@ -4213,7 +4221,7 @@ static int bcmgenet_resume(struct device
+@@ -4215,7 +4223,7 @@ static int bcmgenet_resume(struct device
  			bcmgenet_hfb_create_rxnfc_filter(priv, rule);
  
  	/* Disable RX/TX DMA and flush TX queues */
diff --git a/target/linux/bcm27xx/patches-5.15/950-0310-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch b/target/linux/bcm27xx/patches-5.15/950-0310-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch
index 9f8eb271e7039c..48be442befef85 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0310-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0310-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch
@@ -12,7 +12,7 @@ which are only relevant to other reboot notifiers.
 
 --- a/drivers/watchdog/bcm2835_wdt.c
 +++ b/drivers/watchdog/bcm2835_wdt.c
-@@ -126,10 +126,12 @@ static int bcm2835_restart(struct watchd
+@@ -127,10 +127,12 @@ static int bcm2835_restart(struct watchd
  {
  	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
  
diff --git a/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch b/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch
index 2741660ee2ae9b..604acfacc0f3d6 100644
--- a/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch
+++ b/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch
@@ -23,7 +23,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
 
 --- a/drivers/mmc/core/block.c
 +++ b/drivers/mmc/core/block.c
-@@ -1888,7 +1888,11 @@ static void mmc_blk_mq_rw_recovery(struc
+@@ -1890,7 +1890,11 @@ static void mmc_blk_mq_rw_recovery(struc
  		return;
  	}
  
diff --git a/target/linux/bcm63xx/patches-5.10/144-add-removed-syscon_regmap_lookup_by_pdevname.patch b/target/linux/bcm63xx/patches-5.10/144-add-removed-syscon_regmap_lookup_by_pdevname.patch
index 683b1bbfce1c2d..bf1c4186218c96 100644
--- a/target/linux/bcm63xx/patches-5.10/144-add-removed-syscon_regmap_lookup_by_pdevname.patch
+++ b/target/linux/bcm63xx/patches-5.10/144-add-removed-syscon_regmap_lookup_by_pdevname.patch
@@ -16,7 +16,7 @@ Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
 
 --- a/drivers/mfd/syscon.c
 +++ b/drivers/mfd/syscon.c
-@@ -205,6 +205,27 @@ struct regmap *syscon_regmap_lookup_by_c
+@@ -209,6 +209,27 @@ struct regmap *syscon_regmap_lookup_by_c
  }
  EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
  
diff --git a/target/linux/bmips/patches-5.15/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch b/target/linux/bmips/patches-5.15/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
index 8b91cac173281d..c6d2df9f8c133b 100644
--- a/target/linux/bmips/patches-5.15/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
+++ b/target/linux/bmips/patches-5.15/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
@@ -17,7 +17,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -288,6 +288,15 @@ config LEDS_COBALT_RAQ
+@@ -289,6 +289,15 @@ config LEDS_COBALT_RAQ
  	help
  	  This option enables support for the Cobalt Raq series LEDs.
  
diff --git a/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
index 937c9824f4d501..a52fa65a85d15e 100644
--- a/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
+++ b/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
@@ -43,7 +43,7 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  
  #include <asm/byteorder.h>
  #include <asm/irq.h>
-@@ -5553,6 +5557,72 @@ static void fotg210_init(struct fotg210_
+@@ -5550,6 +5554,72 @@ static void fotg210_init(struct fotg210_
  }
  
  /*
@@ -116,7 +116,7 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
   * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
   *
   * Allocates basic resources for this USB host controller, and
-@@ -5629,6 +5699,12 @@ static int fotg210_hcd_probe(struct plat
+@@ -5626,6 +5696,12 @@ static int fotg210_hcd_probe(struct plat
  
  	fotg210_init(fotg210);
  
diff --git a/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
index df68adc66b342f..adccc56e2b7fdb 100644
--- a/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
+++ b/target/linux/gemini/patches-5.4/0001-usb-host-fotg2-add-Gemini-specific-handling.patch
@@ -43,7 +43,7 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  
  #include <asm/byteorder.h>
  #include <asm/irq.h>
-@@ -5555,6 +5559,72 @@ static void fotg210_init(struct fotg210_
+@@ -5552,6 +5556,72 @@ static void fotg210_init(struct fotg210_
  	iowrite32(value, &fotg210->regs->otgcsr);
  }
  
@@ -116,7 +116,7 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  /**
   * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
   *
-@@ -5632,6 +5702,12 @@ static int fotg210_hcd_probe(struct plat
+@@ -5629,6 +5699,12 @@ static int fotg210_hcd_probe(struct plat
  
  	fotg210_init(fotg210);
  
diff --git a/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch b/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch
index aa88f610d39f8e..e451a49ac2dc1e 100644
--- a/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch
+++ b/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch
@@ -25,7 +25,7 @@ Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
 
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -2091,7 +2091,7 @@ config CPU_MIPS32
+@@ -2089,7 +2089,7 @@ config CPU_MIPS32
  config CPU_MIPS64
  	bool
  	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
diff --git a/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch b/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch
index 45a93bcce51850..dc1884c2825fea 100644
--- a/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch
+++ b/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6817,15 +6817,10 @@ void __netif_napi_del(struct napi_struct
+@@ -6825,15 +6825,10 @@ void __netif_napi_del(struct napi_struct
  }
  EXPORT_SYMBOL(__netif_napi_del);
  
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	weight = n->weight;
  
  	/* This NAPI_STATE_SCHED test is for avoiding a race
-@@ -6845,7 +6840,7 @@ static int napi_poll(struct napi_struct
+@@ -6853,7 +6848,7 @@ static int napi_poll(struct napi_struct
  			    n->poll, work, weight);
  
  	if (likely(work < weight))
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/* Drivers must not modify the NAPI state if they
  	 * consume the entire weight.  In such cases this code
-@@ -6854,7 +6849,7 @@ static int napi_poll(struct napi_struct
+@@ -6862,7 +6857,7 @@ static int napi_poll(struct napi_struct
  	 */
  	if (unlikely(napi_disable_pending(n))) {
  		napi_complete(n);
@@ -53,7 +53,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	if (n->gro_bitmask) {
-@@ -6872,12 +6867,29 @@ static int napi_poll(struct napi_struct
+@@ -6880,12 +6875,29 @@ static int napi_poll(struct napi_struct
  	if (unlikely(!list_empty(&n->poll_list))) {
  		pr_warn_once("%s: Budget exhausted after napi rescheduled\n",
  			     n->dev ? n->dev->name : "backlog");
diff --git a/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch b/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch
index 529fd9260493a6..b566ce541a7fb0 100644
--- a/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch
+++ b/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch
@@ -131,7 +131,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int __dev_open(struct net_device *dev, struct netlink_ext_ack *extack)
  {
  	const struct net_device_ops *ops = dev->netdev_ops;
-@@ -4276,6 +4298,21 @@ int gro_normal_batch __read_mostly = 8;
+@@ -4284,6 +4306,21 @@ int gro_normal_batch __read_mostly = 8;
  static inline void ____napi_schedule(struct softnet_data *sd,
  				     struct napi_struct *napi)
  {
@@ -153,7 +153,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	list_add_tail(&napi->poll_list, &sd->poll_list);
  	__raise_softirq_irqoff(NET_RX_SOFTIRQ);
  }
-@@ -6770,6 +6807,12 @@ void netif_napi_add(struct net_device *d
+@@ -6778,6 +6815,12 @@ void netif_napi_add(struct net_device *d
  	set_bit(NAPI_STATE_NPSVC, &napi->state);
  	list_add_rcu(&napi->dev_list, &dev->napi_list);
  	napi_hash_add(napi);
@@ -166,7 +166,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  EXPORT_SYMBOL(netif_napi_add);
  
-@@ -6786,9 +6829,28 @@ void napi_disable(struct napi_struct *n)
+@@ -6794,9 +6837,28 @@ void napi_disable(struct napi_struct *n)
  	hrtimer_cancel(&n->timer);
  
  	clear_bit(NAPI_STATE_DISABLE, &n->state);
@@ -195,7 +195,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void flush_gro_hash(struct napi_struct *napi)
  {
  	int i;
-@@ -6814,6 +6876,11 @@ void __netif_napi_del(struct napi_struct
+@@ -6822,6 +6884,11 @@ void __netif_napi_del(struct napi_struct
  
  	flush_gro_hash(napi);
  	napi->gro_bitmask = 0;
@@ -207,7 +207,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  EXPORT_SYMBOL(__netif_napi_del);
  
-@@ -6895,6 +6962,51 @@ static int napi_poll(struct napi_struct
+@@ -6903,6 +6970,51 @@ static int napi_poll(struct napi_struct
  	return work;
  }
  
diff --git a/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch b/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch
index f7a500fd60fad8..6d726f4a632ef1 100644
--- a/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch
+++ b/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch
@@ -57,7 +57,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   *	@n: NAPI context
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -4302,8 +4302,9 @@ static inline void ____napi_schedule(str
+@@ -4310,8 +4310,9 @@ static inline void ____napi_schedule(str
  
  	if (test_bit(NAPI_STATE_THREADED, &napi->state)) {
  		/* Paired with smp_mb__before_atomic() in
@@ -69,7 +69,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		 * wake_up_process() when it's not NULL.
  		 */
  		thread = READ_ONCE(napi->thread);
-@@ -6780,6 +6781,49 @@ static void init_gro_hash(struct napi_st
+@@ -6788,6 +6789,49 @@ static void init_gro_hash(struct napi_st
  	napi->gro_bitmask = 0;
  }
  
diff --git a/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch b/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch
index d39a0cb40eb1fb..be8f89d4d6f7c7 100644
--- a/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch
+++ b/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch
@@ -45,7 +45,7 @@ Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
  enum gro_result {
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -4309,6 +4309,8 @@ static inline void ____napi_schedule(str
+@@ -4317,6 +4317,8 @@ static inline void ____napi_schedule(str
  		 */
  		thread = READ_ONCE(napi->thread);
  		if (thread) {
@@ -54,7 +54,7 @@ Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
  			wake_up_process(thread);
  			return;
  		}
-@@ -6572,7 +6574,8 @@ bool napi_complete_done(struct napi_stru
+@@ -6580,7 +6582,8 @@ bool napi_complete_done(struct napi_stru
  
  		WARN_ON_ONCE(!(val & NAPIF_STATE_SCHED));
  
@@ -64,7 +64,7 @@ Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
  
  		/* If STATE_MISSED was set, leave STATE_SCHED set,
  		 * because we will call napi->poll() one more time.
-@@ -7008,16 +7011,25 @@ static int napi_poll(struct napi_struct
+@@ -7016,16 +7019,25 @@ static int napi_poll(struct napi_struct
  
  static int napi_thread_wait(struct napi_struct *napi)
  {
diff --git a/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch b/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch
index 3ec3446db406e4..8fe89464941660 100644
--- a/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch
+++ b/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch
@@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -7015,7 +7015,7 @@ static int napi_thread_wait(struct napi_
+@@ -7023,7 +7023,7 @@ static int napi_thread_wait(struct napi_
  
  	set_current_state(TASK_INTERRUPTIBLE);
  
@@ -43,7 +43,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* Testing SCHED_THREADED bit here to make sure the current
  		 * kthread owns this napi and could poll on this napi.
  		 * Testing SCHED bit is not enough because SCHED bit might be
-@@ -7033,6 +7033,7 @@ static int napi_thread_wait(struct napi_
+@@ -7041,6 +7041,7 @@ static int napi_thread_wait(struct napi_
  		set_current_state(TASK_INTERRUPTIBLE);
  	}
  	__set_current_state(TASK_RUNNING);
diff --git a/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch b/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch
index f080cb2fd62c47..2308f6d59dc75b 100644
--- a/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch
+++ b/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch
@@ -14,7 +14,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6826,6 +6826,7 @@ int dev_set_threaded(struct net_device *
+@@ -6834,6 +6834,7 @@ int dev_set_threaded(struct net_device *
  
  	return err;
  }
diff --git a/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch b/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch
index 063c52785536e4..bececca21490d3 100644
--- a/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch
+++ b/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch
@@ -27,16 +27,16 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2303,15 +2303,20 @@ static int mtk_open(struct net_device *d
+@@ -2303,14 +2303,20 @@ static int mtk_open(struct net_device *d
  
  	/* we run 2 netdevs on the same dma ring so we only bring it up once */
  	if (!refcount_read(&eth->dma_refcnt)) {
 -		int err = mtk_start_dma(eth);
 +		u32 gdm_config = MTK_GDMA_TO_PDMA;
 +		int err;
- 
++
 +		err = mtk_start_dma(eth);
- 		if (err)
+ 
  		if (err) {
  			phylink_disconnect_phy(mac->phylink);
  			return err;
@@ -50,7 +50,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  
  		napi_enable(&eth->tx_napi);
  		napi_enable(&eth->rx_napi);
-@@ -2378,6 +2383,9 @@ static int mtk_stop(struct net_device *d
+@@ -2377,6 +2383,9 @@ static int mtk_stop(struct net_device *d
  
  	mtk_dma_free(eth);
  
@@ -60,7 +60,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	return 0;
  }
  
-@@ -3106,6 +3114,13 @@ static int mtk_probe(struct platform_dev
+@@ -3105,6 +3114,13 @@ static int mtk_probe(struct platform_dev
  			goto err_free_dev;
  	}
  
@@ -74,7 +74,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
-@@ -3180,6 +3195,7 @@ static const struct mtk_soc_data mt7621_
+@@ -3179,6 +3195,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -82,7 +82,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  };
  
  static const struct mtk_soc_data mt7622_data = {
-@@ -3188,6 +3204,7 @@ static const struct mtk_soc_data mt7622_
+@@ -3187,6 +3204,7 @@ static const struct mtk_soc_data mt7622_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7622_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
index 3c10819b681375..931c589cfa3908 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, chan);
  	stmmac_start_tx_dma(priv, chan);
-@@ -3782,6 +3773,8 @@ static int stmmac_open(struct net_device
+@@ -3783,6 +3774,8 @@ static int stmmac_open(struct net_device
  		}
  	}
  
@@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	ret = stmmac_hw_setup(dev, true);
  	if (ret < 0) {
  		netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
-@@ -6429,6 +6422,7 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6430,6 +6423,7 @@ void stmmac_enable_rx_queue(struct stmma
  		return;
  	}
  
@@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_clear_rx_descriptors(priv, queue);
  
  	stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
-@@ -6490,6 +6484,7 @@ void stmmac_enable_tx_queue(struct stmma
+@@ -6491,6 +6485,7 @@ void stmmac_enable_tx_queue(struct stmma
  		return;
  	}
  
@@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_clear_tx_descriptors(priv, queue);
  
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
-@@ -7414,6 +7409,25 @@ int stmmac_suspend(struct device *dev)
+@@ -7415,6 +7410,25 @@ int stmmac_suspend(struct device *dev)
  }
  EXPORT_SYMBOL_GPL(stmmac_suspend);
  
@@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  /**
   * stmmac_reset_queues_param - reset queue parameters
   * @priv: device pointer
-@@ -7424,22 +7438,11 @@ static void stmmac_reset_queues_param(st
+@@ -7425,22 +7439,11 @@ static void stmmac_reset_queues_param(st
  	u32 tx_cnt = priv->plat->tx_queues_to_use;
  	u32 queue;
  
diff --git a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
index 6e115834eb8911..8bdeef7a696f71 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3834,8 +3834,6 @@ static int stmmac_release(struct net_dev
+@@ -3835,8 +3835,6 @@ static int stmmac_release(struct net_dev
  	struct stmmac_priv *priv = netdev_priv(dev);
  	u32 chan;
  
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (device_may_wakeup(priv->device))
  		phylink_speed_down(priv->phylink, false);
  	/* Stop and disconnect the PHY */
-@@ -3847,6 +3845,8 @@ static int stmmac_release(struct net_dev
+@@ -3848,6 +3846,8 @@ static int stmmac_release(struct net_dev
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
  		hrtimer_cancel(&priv->tx_queue[chan].txtimer);
  
diff --git a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
index 99518b11a040ef..c59a5d1fe1782d 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
@@ -719,7 +719,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			}
  		}
  
-@@ -3575,7 +3575,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3576,7 +3576,7 @@ static int stmmac_request_irq_multi_msi(
  		sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
  		ret = request_irq(priv->rx_irq[i],
  				  stmmac_msi_intr_rx,
@@ -728,7 +728,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (unlikely(ret < 0)) {
  			netdev_err(priv->dev,
  				   "%s: alloc rx-%d  MSI %d (error: %d)\n",
-@@ -3598,7 +3598,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3599,7 +3599,7 @@ static int stmmac_request_irq_multi_msi(
  		sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
  		ret = request_irq(priv->tx_irq[i],
  				  stmmac_msi_intr_tx,
@@ -737,7 +737,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (unlikely(ret < 0)) {
  			netdev_err(priv->dev,
  				   "%s: alloc tx-%d  MSI %d (error: %d)\n",
-@@ -3729,21 +3729,21 @@ static int stmmac_open(struct net_device
+@@ -3730,21 +3730,21 @@ static int stmmac_open(struct net_device
  		bfsize = 0;
  
  	if (bfsize < BUF_SIZE_16KiB)
@@ -766,7 +766,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
  
  		/* Setup per-TXQ tbs flag before TX descriptor alloc */
-@@ -3801,7 +3801,7 @@ irq_error:
+@@ -3802,7 +3802,7 @@ irq_error:
  	phylink_stop(priv->phylink);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -775,7 +775,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_hw_teardown(dev);
  init_error:
-@@ -3843,7 +3843,7 @@ static int stmmac_release(struct net_dev
+@@ -3844,7 +3844,7 @@ static int stmmac_release(struct net_dev
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	netif_tx_disable(dev);
  
-@@ -3907,7 +3907,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3908,7 +3908,7 @@ static bool stmmac_vlan_insert(struct st
  		return false;
  
  	stmmac_set_tx_owner(priv, p);
@@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return true;
  }
  
-@@ -3925,7 +3925,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3926,7 +3926,7 @@ static bool stmmac_vlan_insert(struct st
  static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
  				 int total_len, bool last_segment, u32 queue)
  {
@@ -802,7 +802,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct dma_desc *desc;
  	u32 buff_size;
  	int tmp_len;
-@@ -3936,7 +3936,7 @@ static void stmmac_tso_allocator(struct
+@@ -3937,7 +3937,7 @@ static void stmmac_tso_allocator(struct
  		dma_addr_t curr_addr;
  
  		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
@@ -811,7 +811,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
  
  		if (tx_q->tbs & STMMAC_TBS_AVAIL)
-@@ -3964,7 +3964,7 @@ static void stmmac_tso_allocator(struct
+@@ -3965,7 +3965,7 @@ static void stmmac_tso_allocator(struct
  
  static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
  {
@@ -820,7 +820,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int desc_size;
  
  	if (likely(priv->extend_desc))
-@@ -4026,7 +4026,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4027,7 +4027,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  	dma_addr_t des;
  	int i;
  
@@ -829,7 +829,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	first_tx = tx_q->cur_tx;
  
  	/* Compute header lengths */
-@@ -4066,7 +4066,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4067,7 +4067,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  		stmmac_set_mss(priv, mss_desc, mss);
  		tx_q->mss = mss;
  		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
@@ -838,7 +838,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
  	}
  
-@@ -4178,7 +4178,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4179,7 +4179,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  	 * ndo_start_xmit will fill this descriptor the next time it's
  	 * called and stmmac_tx_clean may clean up to this descriptor.
  	 */
@@ -847,7 +847,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
  		netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
-@@ -4266,7 +4266,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4267,7 +4267,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  	int entry, first_tx;
  	dma_addr_t des;
  
@@ -856,7 +856,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	first_tx = tx_q->cur_tx;
  
  	if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
-@@ -4329,7 +4329,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4330,7 +4330,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  		int len = skb_frag_size(frag);
  		bool last_segment = (i == (nfrags - 1));
  
@@ -865,7 +865,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[entry]);
  
  		if (likely(priv->extend_desc))
-@@ -4400,7 +4400,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4401,7 +4401,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  	 * ndo_start_xmit will fill this descriptor the next time it's
  	 * called and stmmac_tx_clean may clean up to this descriptor.
  	 */
@@ -874,7 +874,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_q->cur_tx = entry;
  
  	if (netif_msg_pktdata(priv)) {
-@@ -4512,7 +4512,7 @@ static void stmmac_rx_vlan(struct net_de
+@@ -4513,7 +4513,7 @@ static void stmmac_rx_vlan(struct net_de
   */
  static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
  {
@@ -883,7 +883,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int entry = rx_q->dirty_rx;
  
-@@ -4562,7 +4562,7 @@ static inline void stmmac_rx_refill(stru
+@@ -4563,7 +4563,7 @@ static inline void stmmac_rx_refill(stru
  		dma_wmb();
  		stmmac_set_rx_owner(priv, p, use_rx_wd);
  
@@ -892,7 +892,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	rx_q->dirty_rx = entry;
  	rx_q->rx_tail_addr = rx_q->dma_rx_phy +
-@@ -4590,12 +4590,12 @@ static unsigned int stmmac_rx_buf1_len(s
+@@ -4591,12 +4591,12 @@ static unsigned int stmmac_rx_buf1_len(s
  
  	/* First descriptor, not last descriptor and not split header */
  	if (status & rx_not_ls)
@@ -907,7 +907,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
-@@ -4611,7 +4611,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4612,7 +4612,7 @@ static unsigned int stmmac_rx_buf2_len(s
  
  	/* Not last descriptor */
  	if (status & rx_not_ls)
@@ -916,7 +916,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	plen = stmmac_get_rx_frame_len(priv, p, coe);
  
-@@ -4622,7 +4622,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4623,7 +4623,7 @@ static unsigned int stmmac_rx_buf2_len(s
  static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
  				struct xdp_frame *xdpf, bool dma_map)
  {
@@ -925,7 +925,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int entry = tx_q->cur_tx;
  	struct dma_desc *tx_desc;
  	dma_addr_t dma_addr;
-@@ -4685,7 +4685,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
+@@ -4686,7 +4686,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
  
  	stmmac_enable_dma_transmission(priv, priv->ioaddr);
  
@@ -934,7 +934,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_q->cur_tx = entry;
  
  	return STMMAC_XDP_TX;
-@@ -4859,7 +4859,7 @@ static void stmmac_dispatch_skb_zc(struc
+@@ -4860,7 +4860,7 @@ static void stmmac_dispatch_skb_zc(struc
  
  static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
  {
@@ -943,7 +943,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int entry = rx_q->dirty_rx;
  	struct dma_desc *rx_desc = NULL;
  	bool ret = true;
-@@ -4902,7 +4902,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4903,7 +4903,7 @@ static bool stmmac_rx_refill_zc(struct s
  		dma_wmb();
  		stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
  
@@ -952,7 +952,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	if (rx_desc) {
-@@ -4917,7 +4917,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4918,7 +4918,7 @@ static bool stmmac_rx_refill_zc(struct s
  
  static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
  {
@@ -961,7 +961,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int count = 0, error = 0, len = 0;
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int next_entry = rx_q->cur_rx;
-@@ -4939,7 +4939,7 @@ static int stmmac_rx_zc(struct stmmac_pr
+@@ -4940,7 +4940,7 @@ static int stmmac_rx_zc(struct stmmac_pr
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -970,7 +970,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  	while (count < limit) {
-@@ -4986,7 +4986,7 @@ read_again:
+@@ -4987,7 +4987,7 @@ read_again:
  
  		/* Prefetch the next RX descriptor */
  		rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
@@ -979,7 +979,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		next_entry = rx_q->cur_rx;
  
  		if (priv->extend_desc)
-@@ -5107,7 +5107,7 @@ read_again:
+@@ -5108,7 +5108,7 @@ read_again:
   */
  static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
  {
@@ -988,7 +988,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned int count = 0, error = 0, len = 0;
  	int status = 0, coe = priv->hw->rx_csum;
-@@ -5120,7 +5120,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5121,7 +5121,7 @@ static int stmmac_rx(struct stmmac_priv
  	int buf_sz;
  
  	dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
@@ -997,7 +997,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (netif_msg_rx_status(priv)) {
  		void *rx_head;
-@@ -5134,7 +5134,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5135,7 +5135,7 @@ static int stmmac_rx(struct stmmac_priv
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -1006,7 +1006,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  	while (count < limit) {
-@@ -5178,7 +5178,7 @@ read_again:
+@@ -5179,7 +5179,7 @@ read_again:
  			break;
  
  		rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
@@ -1015,7 +1015,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		next_entry = rx_q->cur_rx;
  
  		if (priv->extend_desc)
-@@ -5312,7 +5312,7 @@ read_again:
+@@ -5313,7 +5313,7 @@ read_again:
  						buf1_len, dma_dir);
  			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
  					buf->page, buf->page_offset, buf1_len,
@@ -1024,7 +1024,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			/* Data payload appended into SKB */
  			page_pool_release_page(rx_q->page_pool, buf->page);
-@@ -5324,7 +5324,7 @@ read_again:
+@@ -5325,7 +5325,7 @@ read_again:
  						buf2_len, dma_dir);
  			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
  					buf->sec_page, 0, buf2_len,
@@ -1033,7 +1033,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			/* Data payload appended into SKB */
  			page_pool_release_page(rx_q->page_pool, buf->sec_page);
-@@ -5767,11 +5767,13 @@ static irqreturn_t stmmac_safety_interru
+@@ -5768,11 +5768,13 @@ static irqreturn_t stmmac_safety_interru
  static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
  {
  	struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
@@ -1048,7 +1048,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(!data)) {
  		netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
-@@ -5811,10 +5813,12 @@ static irqreturn_t stmmac_msi_intr_tx(in
+@@ -5812,10 +5814,12 @@ static irqreturn_t stmmac_msi_intr_tx(in
  static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
  {
  	struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
@@ -1062,7 +1062,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(!data)) {
  		netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
-@@ -5845,10 +5849,10 @@ static void stmmac_poll_controller(struc
+@@ -5846,10 +5850,10 @@ static void stmmac_poll_controller(struc
  
  	if (priv->plat->multi_msi_en) {
  		for (i = 0; i < priv->plat->rx_queues_to_use; i++)
@@ -1075,7 +1075,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	} else {
  		disable_irq(dev->irq);
  		stmmac_interrupt(dev->irq, dev);
-@@ -6029,34 +6033,34 @@ static int stmmac_rings_status_show(stru
+@@ -6030,34 +6034,34 @@ static int stmmac_rings_status_show(stru
  		return 0;
  
  	for (queue = 0; queue < rx_count; queue++) {
@@ -1116,7 +1116,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		}
  	}
  
-@@ -6403,7 +6407,7 @@ void stmmac_disable_rx_queue(struct stmm
+@@ -6404,7 +6408,7 @@ void stmmac_disable_rx_queue(struct stmm
  
  void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1125,7 +1125,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned long flags;
  	u32 buf_size;
-@@ -6440,7 +6444,7 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6441,7 +6445,7 @@ void stmmac_enable_rx_queue(struct stmma
  				      rx_q->queue_index);
  	} else {
  		stmmac_set_dma_bfsize(priv, priv->ioaddr,
@@ -1134,7 +1134,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				      rx_q->queue_index);
  	}
  
-@@ -6466,7 +6470,7 @@ void stmmac_disable_tx_queue(struct stmm
+@@ -6467,7 +6471,7 @@ void stmmac_disable_tx_queue(struct stmm
  
  void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1143,7 +1143,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned long flags;
  	int ret;
-@@ -6516,7 +6520,7 @@ void stmmac_xdp_release(struct net_devic
+@@ -6517,7 +6521,7 @@ void stmmac_xdp_release(struct net_devic
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1152,7 +1152,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Free the IRQ lines */
  	stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
-@@ -6575,7 +6579,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6576,7 +6580,7 @@ int stmmac_xdp_open(struct net_device *d
  
  	/* DMA RX Channel Configuration */
  	for (chan = 0; chan < rx_cnt; chan++) {
@@ -1161,7 +1161,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  				    rx_q->dma_rx_phy, chan);
-@@ -6593,7 +6597,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6594,7 +6598,7 @@ int stmmac_xdp_open(struct net_device *d
  					      rx_q->queue_index);
  		} else {
  			stmmac_set_dma_bfsize(priv, priv->ioaddr,
@@ -1170,7 +1170,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					      rx_q->queue_index);
  		}
  
-@@ -6602,7 +6606,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6603,7 +6607,7 @@ int stmmac_xdp_open(struct net_device *d
  
  	/* DMA TX Channel Configuration */
  	for (chan = 0; chan < tx_cnt; chan++) {
@@ -1179,7 +1179,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  				    tx_q->dma_tx_phy, chan);
-@@ -6635,7 +6639,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6636,7 +6640,7 @@ int stmmac_xdp_open(struct net_device *d
  
  irq_error:
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1188,7 +1188,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_hw_teardown(dev);
  init_error:
-@@ -6662,8 +6666,8 @@ int stmmac_xsk_wakeup(struct net_device
+@@ -6663,8 +6667,8 @@ int stmmac_xsk_wakeup(struct net_device
  	    queue >= priv->plat->tx_queues_to_use)
  		return -EINVAL;
  
@@ -1199,7 +1199,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	ch = &priv->channel[queue];
  
  	if (!rx_q->xsk_pool && !tx_q->xsk_pool)
-@@ -6923,8 +6927,8 @@ int stmmac_reinit_ringparam(struct net_d
+@@ -6924,8 +6928,8 @@ int stmmac_reinit_ringparam(struct net_d
  	if (netif_running(dev))
  		stmmac_release(dev);
  
@@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (netif_running(dev))
  		ret = stmmac_open(dev);
-@@ -7359,7 +7363,7 @@ int stmmac_suspend(struct device *dev)
+@@ -7360,7 +7364,7 @@ int stmmac_suspend(struct device *dev)
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->eee_enabled) {
  		priv->tx_path_in_lpi_mode = false;
-@@ -7411,7 +7415,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
+@@ -7412,7 +7416,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
  
  static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	rx_q->cur_rx = 0;
  	rx_q->dirty_rx = 0;
-@@ -7419,7 +7423,7 @@ static void stmmac_reset_rx_queue(struct
+@@ -7420,7 +7424,7 @@ static void stmmac_reset_rx_queue(struct
  
  static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
  {
diff --git a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
index 7336456c0c0e9b..bdf8b8585e214e 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
@@ -860,7 +860,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_reset_tx_queue(priv, chan);
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, chan);
-@@ -3685,19 +3748,93 @@ static int stmmac_request_irq(struct net
+@@ -3686,19 +3749,93 @@ static int stmmac_request_irq(struct net
  }
  
  /**
@@ -957,7 +957,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u32 chan;
  	int ret;
  
-@@ -3724,45 +3861,10 @@ static int stmmac_open(struct net_device
+@@ -3725,45 +3862,10 @@ static int stmmac_open(struct net_device
  	memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
  	priv->xstats.threshold = tc;
  
@@ -1005,7 +1005,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->plat->serdes_powerup) {
  		ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
-@@ -3805,14 +3907,28 @@ irq_error:
+@@ -3806,14 +3908,28 @@ irq_error:
  
  	stmmac_hw_teardown(dev);
  init_error:
@@ -1036,7 +1036,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
  {
  	set_bit(__FPE_REMOVING, &priv->fpe_task_state);
-@@ -3859,7 +3975,7 @@ static int stmmac_release(struct net_dev
+@@ -3860,7 +3976,7 @@ static int stmmac_release(struct net_dev
  	stmmac_stop_all_dma(priv);
  
  	/* Release and free the Rx/Tx resources */
@@ -1045,7 +1045,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Disable the MAC Rx/Tx */
  	stmmac_mac_set(priv, priv->ioaddr, false);
-@@ -6402,7 +6518,7 @@ void stmmac_disable_rx_queue(struct stmm
+@@ -6403,7 +6519,7 @@ void stmmac_disable_rx_queue(struct stmm
  	spin_unlock_irqrestore(&ch->lock, flags);
  
  	stmmac_stop_rx_dma(priv, queue);
@@ -1054,7 +1054,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
-@@ -6413,21 +6529,21 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6414,21 +6530,21 @@ void stmmac_enable_rx_queue(struct stmma
  	u32 buf_size;
  	int ret;
  
@@ -1080,7 +1080,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    rx_q->dma_rx_phy, rx_q->queue_index);
-@@ -6465,7 +6581,7 @@ void stmmac_disable_tx_queue(struct stmm
+@@ -6466,7 +6582,7 @@ void stmmac_disable_tx_queue(struct stmm
  	spin_unlock_irqrestore(&ch->lock, flags);
  
  	stmmac_stop_tx_dma(priv, queue);
@@ -1089,7 +1089,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
-@@ -6475,21 +6591,21 @@ void stmmac_enable_tx_queue(struct stmma
+@@ -6476,21 +6592,21 @@ void stmmac_enable_tx_queue(struct stmma
  	unsigned long flags;
  	int ret;
  
@@ -1115,7 +1115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, tx_q->queue_index);
-@@ -6529,7 +6645,7 @@ void stmmac_xdp_release(struct net_devic
+@@ -6530,7 +6646,7 @@ void stmmac_xdp_release(struct net_devic
  	stmmac_stop_all_dma(priv);
  
  	/* Release and free the Rx/Tx resources */
@@ -1124,7 +1124,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Disable the MAC Rx/Tx */
  	stmmac_mac_set(priv, priv->ioaddr, false);
-@@ -6554,14 +6670,14 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6555,14 +6671,14 @@ int stmmac_xdp_open(struct net_device *d
  	u32 chan;
  	int ret;
  
@@ -1141,7 +1141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (ret < 0) {
  		netdev_err(dev, "%s: DMA descriptors initialization failed\n",
  			   __func__);
-@@ -6643,7 +6759,7 @@ irq_error:
+@@ -6644,7 +6760,7 @@ irq_error:
  
  	stmmac_hw_teardown(dev);
  init_error:
@@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  dma_desc_error:
  	return ret;
  }
-@@ -7506,7 +7622,7 @@ int stmmac_resume(struct device *dev)
+@@ -7507,7 +7623,7 @@ int stmmac_resume(struct device *dev)
  	stmmac_reset_queues_param(priv);
  
  	stmmac_free_tx_skbufs(priv);
diff --git a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
index 6ebb527726e440..2576df45224db1 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
@@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -5624,18 +5624,15 @@ static int stmmac_change_mtu(struct net_
+@@ -5625,18 +5625,15 @@ static int stmmac_change_mtu(struct net_
  {
  	struct stmmac_priv *priv = netdev_priv(dev);
  	int txfifosz = priv->plat->tx_fifo_size;
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
  		netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
  		return -EINVAL;
-@@ -5647,8 +5644,29 @@ static int stmmac_change_mtu(struct net_
+@@ -5648,8 +5645,29 @@ static int stmmac_change_mtu(struct net_
  	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
  		return -EINVAL;
  
diff --git a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
index a2168aaba5f645..698e524c3565ef 100644
--- a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
+++ b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/usb/ax88179_178a.c
 +++ b/drivers/net/usb/ax88179_178a.c
-@@ -1377,11 +1377,12 @@ static int ax88179_bind(struct usbnet *d
+@@ -1333,11 +1333,12 @@ static int ax88179_bind(struct usbnet *d
  	dev->mii.phy_id = 0x03;
  	dev->mii.supports_gmii = 1;
  
@@ -33,9 +33,9 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +
 +	netif_set_gso_max_size(dev->net, 16384);
  
- 	/* Enable checksum offload */
- 	*tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
-@@ -1587,17 +1588,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
+ 	ax88179_reset(dev);
+ 
+@@ -1507,17 +1508,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
  {
  	u32 tx_hdr1, tx_hdr2;
  	int frame_size = dev->maxpacket;
@@ -57,7 +57,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if ((skb_header_cloned(skb) || headroom < 0) &&
  	    pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  		dev_kfree_skb_any(skb);
-@@ -1608,6 +1611,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
+@@ -1528,6 +1531,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
  	put_unaligned_le32(tx_hdr1, ptr);
  	put_unaligned_le32(tx_hdr2, ptr + 4);
  
diff --git a/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch b/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch
index ecf6a73bf4d482..c46e560a1596bb 100644
--- a/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch
+++ b/target/linux/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch
@@ -66,7 +66,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -5442,8 +5442,7 @@ static inline void skb_gro_reset_offset(
+@@ -5450,8 +5450,7 @@ static inline void skb_gro_reset_offset(
  	NAPI_GRO_CB(skb)->frag0 = NULL;
  	NAPI_GRO_CB(skb)->frag0_len = 0;
  
diff --git a/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch b/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch
index a9ecc290321e0d..f596793764d108 100644
--- a/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch
+++ b/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch
@@ -1833,7 +1833,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
 +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -3460,10 +3460,11 @@ static int bcmgenet_probe(struct platfor
+@@ -3462,10 +3462,11 @@ static int bcmgenet_probe(struct platfor
  	const struct of_device_id *of_id = NULL;
  	struct bcmgenet_priv *priv;
  	struct net_device *dev;
@@ -1846,7 +1846,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
  	dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
-@@ -3490,14 +3491,15 @@ static int bcmgenet_probe(struct platfor
+@@ -3492,14 +3493,15 @@ static int bcmgenet_probe(struct platfor
  	}
  
  	if (dn) {
@@ -1865,7 +1865,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	priv->base = devm_platform_ioremap_resource(pdev, 0);
-@@ -3510,7 +3512,6 @@ static int bcmgenet_probe(struct platfor
+@@ -3512,7 +3514,6 @@ static int bcmgenet_probe(struct platfor
  
  	SET_NETDEV_DEV(dev, &pdev->dev);
  	dev_set_drvdata(&pdev->dev, dev);
diff --git a/target/linux/generic/backport-6.1/200-v6.3-bitfield-add-FIELD_PREP_CONST.patch b/target/linux/generic/backport-6.1/200-v6.3-bitfield-add-FIELD_PREP_CONST.patch
new file mode 100644
index 00000000000000..2e6d881fe9f15a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/200-v6.3-bitfield-add-FIELD_PREP_CONST.patch
@@ -0,0 +1,58 @@
+From e2192de59e457aef8d1f055a452131f0b3e5d097 Mon Sep 17 00:00:00 2001
+From: Johannes Berg <johannes.berg@intel.com>
+Date: Wed, 18 Jan 2023 14:26:53 +0100
+Subject: [PATCH] bitfield: add FIELD_PREP_CONST()
+
+Neither FIELD_PREP() nor *_encode_bits() can be used
+in constant contexts (such as initializers), but we
+don't want to define shift constants for all masks
+just for use in initializers, and having checks that
+the values fit is also useful.
+
+Therefore, add FIELD_PREP_CONST() which is a smaller
+version of FIELD_PREP() that can only take constant
+arguments and has less friendly (but not less strict)
+error checks, and expands to a constant value.
+
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Link: https://lore.kernel.org/r/20230118142652.53f20593504b.Iaeea0aee77a6493d70e573b4aa55c91c00e01e4b@changeid
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+---
+ include/linux/bitfield.h | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/include/linux/bitfield.h
++++ b/include/linux/bitfield.h
+@@ -115,6 +115,32 @@
+ 		((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask);	\
+ 	})
+ 
++#define __BF_CHECK_POW2(n)	BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0)
++
++/**
++ * FIELD_PREP_CONST() - prepare a constant bitfield element
++ * @_mask: shifted mask defining the field's length and position
++ * @_val:  value to put in the field
++ *
++ * FIELD_PREP_CONST() masks and shifts up the value.  The result should
++ * be combined with other fields of the bitfield using logical OR.
++ *
++ * Unlike FIELD_PREP() this is a constant expression and can therefore
++ * be used in initializers. Error checking is less comfortable for this
++ * version, and non-constant masks cannot be used.
++ */
++#define FIELD_PREP_CONST(_mask, _val)					\
++	(								\
++		/* mask must be non-zero */				\
++		BUILD_BUG_ON_ZERO((_mask) == 0) +			\
++		/* check if value fits */				\
++		BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \
++		/* check if mask is contiguous */			\
++		__BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) +	\
++		/* and create the value */				\
++		(((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask))	\
++	)
++
+ /**
+  * FIELD_GET() - extract a bitfield element
+  * @_mask: shifted mask defining the field's length and position
diff --git a/target/linux/generic/backport-6.1/707-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch b/target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
similarity index 99%
rename from target/linux/generic/backport-6.1/707-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
rename to target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
index 980cb0f9147a6f..d56a142451cd86 100644
--- a/target/linux/generic/backport-6.1/707-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
+++ b/target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -12926,6 +12926,14 @@ L:	netdev@vger.kernel.org
+@@ -12928,6 +12928,14 @@ L:	netdev@vger.kernel.org
  S:	Maintained
  F:	drivers/net/ethernet/mediatek/
  
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0001-net-dsa-mt7530-make-some-noise-if-register-read-fail.patch b/target/linux/generic/backport-6.1/790-v6.4-0001-net-dsa-mt7530-make-some-noise-if-register-read-fail.patch
new file mode 100644
index 00000000000000..4d024b063ab544
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0001-net-dsa-mt7530-make-some-noise-if-register-read-fail.patch
@@ -0,0 +1,32 @@
+From c3552d3f85f06cf4b4818bd84c4fcc09d8d45165 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:19 +0100
+Subject: [PATCH 01/13] net: dsa: mt7530: make some noise if register read
+ fails
+
+Simply returning the negative error value instead of the read value
+doesn't seem like a good idea. Return 0 instead and add WARN_ON_ONCE(1)
+so this kind of error will not go unnoticed.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -224,9 +224,10 @@ mt7530_mii_read(struct mt7530_priv *priv
+ 	/* MT7530 uses 31 as the pseudo port */
+ 	ret = bus->write(bus, 0x1f, 0x1f, page);
+ 	if (ret < 0) {
++		WARN_ON_ONCE(1);
+ 		dev_err(&bus->dev,
+ 			"failed to read mt7530 register\n");
+-		return ret;
++		return 0;
+ 	}
+ 
+ 	lo = bus->read(bus, 0x1f, r);
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
new file mode 100644
index 00000000000000..56674492967b53
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
@@ -0,0 +1,111 @@
+From b896355fc4988216d4f38582d07add9252a795ae Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:30 +0100
+Subject: [PATCH 02/13] net: dsa: mt7530: refactor SGMII PCS creation
+
+Instead of macro templates use a dedidated function and allocated
+regmap_config when creating the regmaps for the pcs-mtk-lynxi
+instances.
+This is in preparation to switching to use unlocked regmap accessors
+and have regmap's locking API handle locking for us.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 74 +++++++++++++++++++++++++++-------------
+ 1 file changed, 50 insertions(+), 24 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2968,26 +2968,56 @@ static const struct regmap_bus mt7531_re
+ 	.reg_update_bits = mt7530_regmap_update_bits,
+ };
+ 
+-#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \
+-	{				\
+-		.name = _name,		\
+-		.reg_bits = 16,		\
+-		.val_bits = 32,		\
+-		.reg_stride = 4,	\
+-		.reg_base = _reg_base,	\
+-		.max_register = 0x17c,	\
++static int
++mt7531_create_sgmii(struct mt7530_priv *priv)
++{
++	struct regmap_config *mt7531_pcs_config[2];
++	struct phylink_pcs *pcs;
++	struct regmap *regmap;
++	int i, ret = 0;
++
++	for (i = 0; i < 2; i++) {
++		mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
++						    sizeof(struct regmap_config),
++						    GFP_KERNEL);
++		if (!mt7531_pcs_config[i]) {
++			ret = -ENOMEM;
++			break;
++		}
++
++		mt7531_pcs_config[i]->name = i ? "port6" : "port5";
++		mt7531_pcs_config[i]->reg_bits = 16;
++		mt7531_pcs_config[i]->val_bits = 32;
++		mt7531_pcs_config[i]->reg_stride = 4;
++		mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
++		mt7531_pcs_config[i]->max_register = 0x17c;
++
++		regmap = devm_regmap_init(priv->dev,
++					  &mt7531_regmap_bus, priv,
++					  mt7531_pcs_config[i]);
++		if (IS_ERR(regmap)) {
++			ret = PTR_ERR(regmap);
++			break;
++		}
++		pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
++					   MT7531_PHYA_CTRL_SIGNAL3, 0);
++		if (!pcs) {
++			ret = -ENXIO;
++			break;
++		}
++		priv->ports[5 + i].sgmii_pcs = pcs;
+ 	}
+ 
+-static const struct regmap_config mt7531_pcs_config[] = {
+-	MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)),
+-	MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)),
+-};
++	if (ret && i)
++		mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
++
++	return ret;
++}
+ 
+ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+-	struct regmap *regmap;
+ 	int i, ret;
+ 
+ 	/* Initialise the PCS devices */
+@@ -3009,15 +3039,11 @@ mt753x_setup(struct dsa_switch *ds)
+ 	if (ret && priv->irq)
+ 		mt7530_free_irq_common(priv);
+ 
+-	if (priv->id == ID_MT7531)
+-		for (i = 0; i < 2; i++) {
+-			regmap = devm_regmap_init(ds->dev,
+-						  &mt7531_regmap_bus, priv,
+-						  &mt7531_pcs_config[i]);
+-			priv->ports[5 + i].sgmii_pcs =
+-				mtk_pcs_lynxi_create(ds->dev, regmap,
+-						     MT7531_PHYA_CTRL_SIGNAL3, 0);
+-		}
++	if (priv->id == ID_MT7531) {
++		ret = mt7531_create_sgmii(priv);
++		if (ret && priv->irq)
++			mt7530_free_irq_common(priv);
++	}
+ 
+ 	return ret;
+ }
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
new file mode 100644
index 00000000000000..3b4689fb1947b1
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
@@ -0,0 +1,74 @@
+From 33396408776385f3d2f6069646169a6b5b28e3b3 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:40 +0100
+Subject: [PATCH 03/13] net: dsa: mt7530: use unlocked regmap accessors
+
+Instead of wrapping the locked register accessor functions, use the
+unlocked variants and add locking wrapper functions to let regmap
+handle the locking.
+
+This is a preparation towards being able to always use regmap to
+access switch registers instead of open-coded accessor functions.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 23 ++++++++++++++---------
+ 1 file changed, 14 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2941,7 +2941,7 @@ static int mt7530_regmap_read(void *cont
+ {
+ 	struct mt7530_priv *priv = context;
+ 
+-	*val = mt7530_read(priv, reg);
++	*val = mt7530_mii_read(priv, reg);
+ 	return 0;
+ };
+ 
+@@ -2949,23 +2949,25 @@ static int mt7530_regmap_write(void *con
+ {
+ 	struct mt7530_priv *priv = context;
+ 
+-	mt7530_write(priv, reg, val);
++	mt7530_mii_write(priv, reg, val);
+ 	return 0;
+ };
+ 
+-static int mt7530_regmap_update_bits(void *context, unsigned int reg,
+-				     unsigned int mask, unsigned int val)
++static void
++mt7530_mdio_regmap_lock(void *mdio_lock)
+ {
+-	struct mt7530_priv *priv = context;
++	mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
++}
+ 
+-	mt7530_rmw(priv, reg, mask, val);
+-	return 0;
+-};
++static void
++mt7530_mdio_regmap_unlock(void *mdio_lock)
++{
++	mutex_unlock(mdio_lock);
++}
+ 
+ static const struct regmap_bus mt7531_regmap_bus = {
+ 	.reg_write = mt7530_regmap_write,
+ 	.reg_read = mt7530_regmap_read,
+-	.reg_update_bits = mt7530_regmap_update_bits,
+ };
+ 
+ static int
+@@ -2991,6 +2993,9 @@ mt7531_create_sgmii(struct mt7530_priv *
+ 		mt7531_pcs_config[i]->reg_stride = 4;
+ 		mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
+ 		mt7531_pcs_config[i]->max_register = 0x17c;
++		mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
++		mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
++		mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+ 
+ 		regmap = devm_regmap_init(priv->dev,
+ 					  &mt7531_regmap_bus, priv,
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
new file mode 100644
index 00000000000000..04033f14f47632
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
@@ -0,0 +1,224 @@
+From 743cba4345cb366248f9d375c6a9e50243dc0677 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:52 +0100
+Subject: [PATCH 04/13] net: dsa: mt7530: use regmap to access switch register
+ space
+
+Use regmap API to access the switch register space.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 99 ++++++++++++++++++++++++----------------
+ drivers/net/dsa/mt7530.h |  2 +
+ 2 files changed, 62 insertions(+), 39 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -183,9 +183,9 @@ core_clear(struct mt7530_priv *priv, u32
+ }
+ 
+ static int
+-mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
++mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+ {
+-	struct mii_bus *bus = priv->bus;
++	struct mii_bus *bus = context;
+ 	u16 page, r, lo, hi;
+ 	int ret;
+ 
+@@ -197,24 +197,34 @@ mt7530_mii_write(struct mt7530_priv *pri
+ 	/* MT7530 uses 31 as the pseudo port */
+ 	ret = bus->write(bus, 0x1f, 0x1f, page);
+ 	if (ret < 0)
+-		goto err;
++		return ret;
+ 
+ 	ret = bus->write(bus, 0x1f, r,  lo);
+ 	if (ret < 0)
+-		goto err;
++		return ret;
+ 
+ 	ret = bus->write(bus, 0x1f, 0x10, hi);
+-err:
++	return ret;
++}
++
++static int
++mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
++{
++	int ret;
++
++	ret = regmap_write(priv->regmap, reg, val);
++
+ 	if (ret < 0)
+-		dev_err(&bus->dev,
++		dev_err(priv->dev,
+ 			"failed to write mt7530 register\n");
++
+ 	return ret;
+ }
+ 
+-static u32
+-mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
++static int
++mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+ {
+-	struct mii_bus *bus = priv->bus;
++	struct mii_bus *bus = context;
+ 	u16 page, r, lo, hi;
+ 	int ret;
+ 
+@@ -223,17 +233,32 @@ mt7530_mii_read(struct mt7530_priv *priv
+ 
+ 	/* MT7530 uses 31 as the pseudo port */
+ 	ret = bus->write(bus, 0x1f, 0x1f, page);
+-	if (ret < 0) {
++	if (ret < 0)
++		return ret;
++
++	lo = bus->read(bus, 0x1f, r);
++	hi = bus->read(bus, 0x1f, 0x10);
++
++	*val = (hi << 16) | (lo & 0xffff);
++
++	return 0;
++}
++
++static u32
++mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
++{
++	int ret;
++	u32 val;
++
++	ret = regmap_read(priv->regmap, reg, &val);
++	if (ret) {
+ 		WARN_ON_ONCE(1);
+-		dev_err(&bus->dev,
++		dev_err(priv->dev,
+ 			"failed to read mt7530 register\n");
+ 		return 0;
+ 	}
+ 
+-	lo = bus->read(bus, 0x1f, r);
+-	hi = bus->read(bus, 0x1f, 0x10);
+-
+-	return (hi << 16) | (lo & 0xffff);
++	return val;
+ }
+ 
+ static void
+@@ -283,14 +308,10 @@ mt7530_rmw(struct mt7530_priv *priv, u32
+ 	   u32 mask, u32 set)
+ {
+ 	struct mii_bus *bus = priv->bus;
+-	u32 val;
+ 
+ 	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ 
+-	val = mt7530_mii_read(priv, reg);
+-	val &= ~mask;
+-	val |= set;
+-	mt7530_mii_write(priv, reg, val);
++	regmap_update_bits(priv->regmap, reg, mask, set);
+ 
+ 	mutex_unlock(&bus->mdio_lock);
+ }
+@@ -298,7 +319,7 @@ mt7530_rmw(struct mt7530_priv *priv, u32
+ static void
+ mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+-	mt7530_rmw(priv, reg, 0, val);
++	mt7530_rmw(priv, reg, val, val);
+ }
+ 
+ static void
+@@ -2937,22 +2958,6 @@ static const struct phylink_pcs_ops mt75
+ 	.pcs_an_restart = mt7530_pcs_an_restart,
+ };
+ 
+-static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+-{
+-	struct mt7530_priv *priv = context;
+-
+-	*val = mt7530_mii_read(priv, reg);
+-	return 0;
+-};
+-
+-static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+-{
+-	struct mt7530_priv *priv = context;
+-
+-	mt7530_mii_write(priv, reg, val);
+-	return 0;
+-};
+-
+ static void
+ mt7530_mdio_regmap_lock(void *mdio_lock)
+ {
+@@ -2965,7 +2970,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
+ 	mutex_unlock(mdio_lock);
+ }
+ 
+-static const struct regmap_bus mt7531_regmap_bus = {
++static const struct regmap_bus mt7530_regmap_bus = {
+ 	.reg_write = mt7530_regmap_write,
+ 	.reg_read = mt7530_regmap_read,
+ };
+@@ -2998,7 +3003,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+ 		mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+ 
+ 		regmap = devm_regmap_init(priv->dev,
+-					  &mt7531_regmap_bus, priv,
++					  &mt7530_regmap_bus, priv->bus,
+ 					  mt7531_pcs_config[i]);
+ 		if (IS_ERR(regmap)) {
+ 			ret = PTR_ERR(regmap);
+@@ -3163,6 +3168,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
+ static int
+ mt7530_probe(struct mdio_device *mdiodev)
+ {
++	static struct regmap_config *regmap_config;
+ 	struct mt7530_priv *priv;
+ 	struct device_node *dn;
+ 
+@@ -3242,6 +3248,21 @@ mt7530_probe(struct mdio_device *mdiodev
+ 	mutex_init(&priv->reg_mutex);
+ 	dev_set_drvdata(&mdiodev->dev, priv);
+ 
++	regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
++				     GFP_KERNEL);
++	if (!regmap_config)
++		return -ENOMEM;
++
++	regmap_config->reg_bits = 16;
++	regmap_config->val_bits = 32;
++	regmap_config->reg_stride = 4;
++	regmap_config->max_register = MT7530_CREV;
++	regmap_config->disable_locking = true;
++	priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
++					priv->bus, regmap_config);
++	if (IS_ERR(priv->regmap))
++		return PTR_ERR(priv->regmap);
++
+ 	return dsa_register_switch(priv->ds);
+ }
+ 
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -754,6 +754,7 @@ struct mt753x_info {
+  * @dev:		The device pointer
+  * @ds:			The pointer to the dsa core structure
+  * @bus:		The bus used for the device and built-in PHY
++ * @regmap:		The regmap instance representing all switch registers
+  * @rstc:		The pointer to reset control used by MCM
+  * @core_pwr:		The power supplied into the core
+  * @io_pwr:		The power supplied into the I/O
+@@ -774,6 +775,7 @@ struct mt7530_priv {
+ 	struct device		*dev;
+ 	struct dsa_switch	*ds;
+ 	struct mii_bus		*bus;
++	struct regmap		*regmap;
+ 	struct reset_control	*rstc;
+ 	struct regulator	*core_pwr;
+ 	struct regulator	*io_pwr;
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
new file mode 100644
index 00000000000000..6c5bebdd8024df
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
@@ -0,0 +1,54 @@
+From f3cf1d06e2aef644b426c23b4bb570780b1f8d47 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:04 +0100
+Subject: [PATCH 05/13] net: dsa: mt7530: move SGMII PCS creation to
+ mt7530_probe function
+
+Move creating the SGMII PCS from mt753x_setup() to the more appropriate
+mt7530_probe() function.
+This is done also in preparation of moving all functions related to
+MDIO-connected MT753x switches to a separate module.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3049,12 +3049,6 @@ mt753x_setup(struct dsa_switch *ds)
+ 	if (ret && priv->irq)
+ 		mt7530_free_irq_common(priv);
+ 
+-	if (priv->id == ID_MT7531) {
+-		ret = mt7531_create_sgmii(priv);
+-		if (ret && priv->irq)
+-			mt7530_free_irq_common(priv);
+-	}
+-
+ 	return ret;
+ }
+ 
+@@ -3171,6 +3165,7 @@ mt7530_probe(struct mdio_device *mdiodev
+ 	static struct regmap_config *regmap_config;
+ 	struct mt7530_priv *priv;
+ 	struct device_node *dn;
++	int ret;
+ 
+ 	dn = mdiodev->dev.of_node;
+ 
+@@ -3263,6 +3258,12 @@ mt7530_probe(struct mdio_device *mdiodev
+ 	if (IS_ERR(priv->regmap))
+ 		return PTR_ERR(priv->regmap);
+ 
++	if (priv->id == ID_MT7531) {
++		ret = mt7531_create_sgmii(priv);
++		if (ret)
++			return ret;
++	}
++
+ 	return dsa_register_switch(priv->ds);
+ }
+ 
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch
new file mode 100644
index 00000000000000..a8933d2cf4e9a2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch
@@ -0,0 +1,273 @@
+From e4729ae7c095c0c87794bff47ea43e35d69de986 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:16 +0100
+Subject: [PATCH 06/13] net: dsa: mt7530: introduce mutex helpers
+
+As the MDIO bus lock only needs to be involved if actually operating
+on an MDIO-connected switch we will need to skip locking for built-in
+switches which are accessed via MMIO.
+Create helper functions which simplify that upcoming change.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 73 ++++++++++++++++++++--------------------
+ 1 file changed, 36 insertions(+), 37 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -143,31 +143,40 @@ err:
+ }
+ 
+ static void
+-core_write(struct mt7530_priv *priv, u32 reg, u32 val)
++mt7530_mutex_lock(struct mt7530_priv *priv)
+ {
+-	struct mii_bus *bus = priv->bus;
++	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++}
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++static void
++mt7530_mutex_unlock(struct mt7530_priv *priv)
++{
++	mutex_unlock(&priv->bus->mdio_lock);
++}
++
++static void
++core_write(struct mt7530_priv *priv, u32 reg, u32 val)
++{
++	mt7530_mutex_lock(priv);
+ 
+ 	core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+ 
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ }
+ 
+ static void
+ core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+ {
+-	struct mii_bus *bus = priv->bus;
+ 	u32 val;
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
+ 	val &= ~mask;
+ 	val |= set;
+ 	core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+ 
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ }
+ 
+ static void
+@@ -264,13 +273,11 @@ mt7530_mii_read(struct mt7530_priv *priv
+ static void
+ mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+-	struct mii_bus *bus = priv->bus;
+-
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	mt7530_mii_write(priv, reg, val);
+ 
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ }
+ 
+ static u32
+@@ -282,14 +289,13 @@ _mt7530_unlocked_read(struct mt7530_dumm
+ static u32
+ _mt7530_read(struct mt7530_dummy_poll *p)
+ {
+-	struct mii_bus		*bus = p->priv->bus;
+ 	u32 val;
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(p->priv);
+ 
+ 	val = mt7530_mii_read(p->priv, p->reg);
+ 
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(p->priv);
+ 
+ 	return val;
+ }
+@@ -307,13 +313,11 @@ static void
+ mt7530_rmw(struct mt7530_priv *priv, u32 reg,
+ 	   u32 mask, u32 set)
+ {
+-	struct mii_bus *bus = priv->bus;
+-
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	regmap_update_bits(priv->regmap, reg, mask, set);
+ 
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ }
+ 
+ static void
+@@ -645,14 +649,13 @@ static int
+ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
+ 			int regnum)
+ {
+-	struct mii_bus *bus = priv->bus;
+ 	struct mt7530_dummy_poll p;
+ 	u32 reg, val;
+ 	int ret;
+ 
+ 	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -685,7 +688,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
+ 
+ 	ret = val & MT7531_MDIO_RW_DATA_MASK;
+ out:
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ 
+ 	return ret;
+ }
+@@ -694,14 +697,13 @@ static int
+ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
+ 			 int regnum, u32 data)
+ {
+-	struct mii_bus *bus = priv->bus;
+ 	struct mt7530_dummy_poll p;
+ 	u32 val, reg;
+ 	int ret;
+ 
+ 	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -733,7 +735,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
+ 	}
+ 
+ out:
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ 
+ 	return ret;
+ }
+@@ -741,14 +743,13 @@ out:
+ static int
+ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
+ {
+-	struct mii_bus *bus = priv->bus;
+ 	struct mt7530_dummy_poll p;
+ 	int ret;
+ 	u32 val;
+ 
+ 	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -771,7 +772,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
+ 
+ 	ret = val & MT7531_MDIO_RW_DATA_MASK;
+ out:
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ 
+ 	return ret;
+ }
+@@ -780,14 +781,13 @@ static int
+ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
+ 			 u16 data)
+ {
+-	struct mii_bus *bus = priv->bus;
+ 	struct mt7530_dummy_poll p;
+ 	int ret;
+ 	u32 reg;
+ 
+ 	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
+ 				 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -809,7 +809,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
+ 	}
+ 
+ out:
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ 
+ 	return ret;
+ }
+@@ -1125,7 +1125,6 @@ static int
+ mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+-	struct mii_bus *bus = priv->bus;
+ 	int length;
+ 	u32 val;
+ 
+@@ -1136,7 +1135,7 @@ mt7530_port_change_mtu(struct dsa_switch
+ 	if (!dsa_is_cpu_port(ds, port))
+ 		return 0;
+ 
+-	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 
+ 	val = mt7530_mii_read(priv, MT7530_GMACCR);
+ 	val &= ~MAX_RX_PKT_LEN_MASK;
+@@ -1157,7 +1156,7 @@ mt7530_port_change_mtu(struct dsa_switch
+ 
+ 	mt7530_mii_write(priv, MT7530_GMACCR, val);
+ 
+-	mutex_unlock(&bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ 
+ 	return 0;
+ }
+@@ -1958,10 +1957,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
+ 	u32 val;
+ 	int p;
+ 
+-	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ 	val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
+ 	mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
+-	mutex_unlock(&priv->bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ 
+ 	for (p = 0; p < MT7530_NUM_PHYS; p++) {
+ 		if (BIT(p) & val) {
+@@ -1997,7 +1996,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
+ {
+ 	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
+ 
+-	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++	mt7530_mutex_lock(priv);
+ }
+ 
+ static void
+@@ -2006,7 +2005,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
+ 	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
+ 
+ 	mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
+-	mutex_unlock(&priv->bus->mdio_lock);
++	mt7530_mutex_unlock(priv);
+ }
+ 
+ static struct irq_chip mt7530_irq_chip = {
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
new file mode 100644
index 00000000000000..6c68dc0c4fd3d3
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
@@ -0,0 +1,75 @@
+From 0d7ae94a0c581f86939bebec0b6ccd66e640d1d8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:28 +0100
+Subject: [PATCH 07/13] net: dsa: mt7530: move p5_intf_modes() function to
+ mt7530.c
+
+In preparation of splitting mt7530.c into a driver for MDIO-connected
+as well as MDIO-accessed built-in switches on one hand and MMIO-accessed
+built-in switches move the p5_inft_modes() function from mt7530.h to
+mt7530.c. The function is only needed there and will trigger a compiler
+warning about a defined but unused function otherwise when including
+mt7530.h in the to-be-introduced bus-specific drivers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 18 ++++++++++++++++++
+ drivers/net/dsa/mt7530.h | 18 ------------------
+ 2 files changed, 18 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -950,6 +950,24 @@ mt7530_set_ageing_time(struct dsa_switch
+ 	return 0;
+ }
+ 
++static const char *p5_intf_modes(unsigned int p5_interface)
++{
++	switch (p5_interface) {
++	case P5_DISABLED:
++		return "DISABLED";
++	case P5_INTF_SEL_PHY_P0:
++		return "PHY P0";
++	case P5_INTF_SEL_PHY_P4:
++		return "PHY P4";
++	case P5_INTF_SEL_GMAC5:
++		return "GMAC5";
++	case P5_INTF_SEL_GMAC5_SGMII:
++		return "GMAC5_SGMII";
++	default:
++		return "unknown";
++	}
++}
++
+ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -689,24 +689,6 @@ enum p5_interface_select {
+ 	P5_INTF_SEL_GMAC5_SGMII,
+ };
+ 
+-static const char *p5_intf_modes(unsigned int p5_interface)
+-{
+-	switch (p5_interface) {
+-	case P5_DISABLED:
+-		return "DISABLED";
+-	case P5_INTF_SEL_PHY_P0:
+-		return "PHY P0";
+-	case P5_INTF_SEL_PHY_P4:
+-		return "PHY P4";
+-	case P5_INTF_SEL_GMAC5:
+-		return "GMAC5";
+-	case P5_INTF_SEL_GMAC5_SGMII:
+-		return "GMAC5_SGMII";
+-	default:
+-		return "unknown";
+-	}
+-}
+-
+ struct mt7530_priv;
+ 
+ struct mt753x_pcs {
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
new file mode 100644
index 00000000000000..dc4fcb6aa11fdc
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
@@ -0,0 +1,155 @@
+From 4d632005c90e253c000d0db73b7cdb9d8dc2e2dd Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:39 +0100
+Subject: [PATCH 08/13] net: dsa: mt7530: introduce mt7530_probe_common helper
+ function
+
+Move commonly used parts from mt7530_probe into new mt7530_probe_common
+helper function which will be used by both, mt7530_probe and the
+to-be-introduced mt7988_probe.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 98 ++++++++++++++++++++++------------------
+ 1 file changed, 54 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3177,44 +3177,21 @@ static const struct of_device_id mt7530_
+ MODULE_DEVICE_TABLE(of, mt7530_of_match);
+ 
+ static int
+-mt7530_probe(struct mdio_device *mdiodev)
++mt7530_probe_common(struct mt7530_priv *priv)
+ {
+-	static struct regmap_config *regmap_config;
+-	struct mt7530_priv *priv;
+-	struct device_node *dn;
+-	int ret;
++	struct device *dev = priv->dev;
+ 
+-	dn = mdiodev->dev.of_node;
+-
+-	priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+-
+-	priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
++	priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
+ 	if (!priv->ds)
+ 		return -ENOMEM;
+ 
+-	priv->ds->dev = &mdiodev->dev;
++	priv->ds->dev = dev;
+ 	priv->ds->num_ports = MT7530_NUM_PORTS;
+ 
+-	/* Use medatek,mcm property to distinguish hardware type that would
+-	 * casues a little bit differences on power-on sequence.
+-	 */
+-	priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
+-	if (priv->mcm) {
+-		dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
+-
+-		priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
+-		if (IS_ERR(priv->rstc)) {
+-			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
+-			return PTR_ERR(priv->rstc);
+-		}
+-	}
+-
+ 	/* Get the hardware identifier from the devicetree node.
+ 	 * We will need it for some of the clock and regulator setup.
+ 	 */
+-	priv->info = of_device_get_match_data(&mdiodev->dev);
++	priv->info = of_device_get_match_data(dev);
+ 	if (!priv->info)
+ 		return -EINVAL;
+ 
+@@ -3228,23 +3205,53 @@ mt7530_probe(struct mdio_device *mdiodev
+ 		return -EINVAL;
+ 
+ 	priv->id = priv->info->id;
++	priv->dev = dev;
++	priv->ds->priv = priv;
++	priv->ds->ops = &mt7530_switch_ops;
++	mutex_init(&priv->reg_mutex);
++	dev_set_drvdata(dev, priv);
+ 
+-	if (priv->id == ID_MT7530) {
+-		priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
+-		if (IS_ERR(priv->core_pwr))
+-			return PTR_ERR(priv->core_pwr);
++	return 0;
++}
+ 
+-		priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
+-		if (IS_ERR(priv->io_pwr))
+-			return PTR_ERR(priv->io_pwr);
+-	}
++static int
++mt7530_probe(struct mdio_device *mdiodev)
++{
++	static struct regmap_config *regmap_config;
++	struct mt7530_priv *priv;
++	struct device_node *dn;
++	int ret;
++
++	dn = mdiodev->dev.of_node;
++
++	priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
+ 
+-	/* Not MCM that indicates switch works as the remote standalone
++	priv->bus = mdiodev->bus;
++	priv->dev = &mdiodev->dev;
++
++	ret = mt7530_probe_common(priv);
++	if (ret)
++		return ret;
++
++	/* Use medatek,mcm property to distinguish hardware type that would
++	 * cause a little bit differences on power-on sequence.
++	 * Not MCM that indicates switch works as the remote standalone
+ 	 * integrated circuit so the GPIO pin would be used to complete
+ 	 * the reset, otherwise memory-mapped register accessing used
+ 	 * through syscon provides in the case of MCM.
+ 	 */
+-	if (!priv->mcm) {
++	priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
++	if (priv->mcm) {
++		dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
++
++		priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
++		if (IS_ERR(priv->rstc)) {
++			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
++			return PTR_ERR(priv->rstc);
++		}
++	} else {
+ 		priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
+ 						      GPIOD_OUT_LOW);
+ 		if (IS_ERR(priv->reset)) {
+@@ -3253,12 +3260,15 @@ mt7530_probe(struct mdio_device *mdiodev
+ 		}
+ 	}
+ 
+-	priv->bus = mdiodev->bus;
+-	priv->dev = &mdiodev->dev;
+-	priv->ds->priv = priv;
+-	priv->ds->ops = &mt7530_switch_ops;
+-	mutex_init(&priv->reg_mutex);
+-	dev_set_drvdata(&mdiodev->dev, priv);
++	if (priv->id == ID_MT7530) {
++		priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
++		if (IS_ERR(priv->core_pwr))
++			return PTR_ERR(priv->core_pwr);
++
++		priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
++		if (IS_ERR(priv->io_pwr))
++			return PTR_ERR(priv->io_pwr);
++	}
+ 
+ 	regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
+ 				     GFP_KERNEL);
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
new file mode 100644
index 00000000000000..5df859d2dff26c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
@@ -0,0 +1,54 @@
+From 69b838d2629e6b82bcd9e0ab3c1c03f46e5e01d3 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:50 +0100
+Subject: [PATCH 09/13] net: dsa: mt7530: introduce mt7530_remove_common helper
+ function
+
+Move commonly used parts from mt7530_remove into new
+mt7530_remove_common helper function which will be used by both,
+mt7530_remove and the to-be-introduced mt7988_remove.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3295,6 +3295,17 @@ mt7530_probe(struct mdio_device *mdiodev
+ }
+ 
+ static void
++mt7530_remove_common(struct mt7530_priv *priv)
++{
++	if (priv->irq)
++		mt7530_free_irq(priv);
++
++	dsa_unregister_switch(priv->ds);
++
++	mutex_destroy(&priv->reg_mutex);
++}
++
++static void
+ mt7530_remove(struct mdio_device *mdiodev)
+ {
+ 	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+@@ -3313,15 +3324,10 @@ mt7530_remove(struct mdio_device *mdiode
+ 		dev_err(priv->dev, "Failed to disable io pwr: %d\n",
+ 			ret);
+ 
+-	if (priv->irq)
+-		mt7530_free_irq(priv);
+-
+-	dsa_unregister_switch(priv->ds);
++	mt7530_remove_common(priv);
+ 
+ 	for (i = 0; i < 2; ++i)
+ 		mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
+-
+-	mutex_destroy(&priv->reg_mutex);
+ }
+ 
+ static void mt7530_shutdown(struct mdio_device *mdiodev)
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
new file mode 100644
index 00000000000000..d2037118849b2b
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
@@ -0,0 +1,691 @@
+From 8eceed6dbd74067dbf4d8e39f14734f4d2f35176 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:19:13 +0100
+Subject: [PATCH 10/13] net: dsa: mt7530: introduce separate MDIO driver
+
+Split MT7530 switch driver into a common part and a part specific
+for MDIO connected switches and multi-chip modules.
+Move MDIO-specific functions to newly introduced mt7530-mdio.c while
+keeping the common parts in mt7530.c.
+Introduce new Kconfig symbol CONFIG_NET_DSA_MT7530_MDIO which is
+implied by CONFIG_NET_DSA_MT7530.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS                   |   1 +
+ drivers/net/dsa/Kconfig       |  16 +-
+ drivers/net/dsa/Makefile      |   1 +
+ drivers/net/dsa/mt7530-mdio.c | 271 ++++++++++++++++++++++++++++++++++
+ drivers/net/dsa/mt7530.c      | 264 +--------------------------------
+ drivers/net/dsa/mt7530.h      |   6 +
+ 6 files changed, 301 insertions(+), 258 deletions(-)
+ create mode 100644 drivers/net/dsa/mt7530-mdio.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -13062,6 +13062,7 @@ M:	Landen Chao <Landen.Chao@mediatek.com
+ M:	DENG Qingfang <dqfext@gmail.com>
+ L:	netdev@vger.kernel.org
+ S:	Maintained
++F:	drivers/net/dsa/mt7530-mdio.c
+ F:	drivers/net/dsa/mt7530.*
+ F:	net/dsa/tag_mtk.c
+ 
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -37,10 +37,22 @@ config NET_DSA_MT7530
+ 	tristate "MediaTek MT753x and MT7621 Ethernet switch support"
+ 	select NET_DSA_TAG_MTK
+ 	select MEDIATEK_GE_PHY
++	imply NET_DSA_MT7530_MDIO
++	help
++	  This enables support for the MediaTek MT7530 and MT7531 Ethernet
++	  switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
++	  MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
++	  supported as well.
++
++config NET_DSA_MT7530_MDIO
++	tristate "MediaTek MT7530 MDIO interface driver"
++	depends on NET_DSA_MT7530
+ 	select PCS_MTK_LYNXI
+ 	help
+-	  This enables support for the MediaTek MT7530, MT7531, and MT7621
+-	  Ethernet switch chips.
++	  This enables support for the MediaTek MT7530 and MT7531 switch
++	  chips which are connected via MDIO, as well as multi-chip
++	  module MT7530 which can be found in the MT7621AT, MT7621DAT,
++	  MT7621ST and MT7623AI SoCs.
+ 
+ config NET_DSA_MV88E6060
+ 	tristate "Marvell 88E6060 ethernet switch chip support"
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_FIXED_PHY)		+= dsa_loop_bdi
+ endif
+ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
+ obj-$(CONFIG_NET_DSA_MT7530)	+= mt7530.o
++obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+ obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
+ obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
+--- /dev/null
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -0,0 +1,271 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/gpio/consumer.h>
++#include <linux/mdio.h>
++#include <linux/module.h>
++#include <linux/pcs/pcs-mtk-lynxi.h>
++#include <linux/of_irq.h>
++#include <linux/of_mdio.h>
++#include <linux/of_net.h>
++#include <linux/of_platform.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/regulator/consumer.h>
++#include <net/dsa.h>
++
++#include "mt7530.h"
++
++static int
++mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
++{
++	struct mii_bus *bus = context;
++	u16 page, r, lo, hi;
++	int ret;
++
++	page = (reg >> 6) & 0x3ff;
++	r  = (reg >> 2) & 0xf;
++	lo = val & 0xffff;
++	hi = val >> 16;
++
++	/* MT7530 uses 31 as the pseudo port */
++	ret = bus->write(bus, 0x1f, 0x1f, page);
++	if (ret < 0)
++		return ret;
++
++	ret = bus->write(bus, 0x1f, r,  lo);
++	if (ret < 0)
++		return ret;
++
++	ret = bus->write(bus, 0x1f, 0x10, hi);
++	return ret;
++}
++
++static int
++mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
++{
++	struct mii_bus *bus = context;
++	u16 page, r, lo, hi;
++	int ret;
++
++	page = (reg >> 6) & 0x3ff;
++	r = (reg >> 2) & 0xf;
++
++	/* MT7530 uses 31 as the pseudo port */
++	ret = bus->write(bus, 0x1f, 0x1f, page);
++	if (ret < 0)
++		return ret;
++
++	lo = bus->read(bus, 0x1f, r);
++	hi = bus->read(bus, 0x1f, 0x10);
++
++	*val = (hi << 16) | (lo & 0xffff);
++
++	return 0;
++}
++
++static void
++mt7530_mdio_regmap_lock(void *mdio_lock)
++{
++	mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
++}
++
++static void
++mt7530_mdio_regmap_unlock(void *mdio_lock)
++{
++	mutex_unlock(mdio_lock);
++}
++
++static const struct regmap_bus mt7530_regmap_bus = {
++	.reg_write = mt7530_regmap_write,
++	.reg_read = mt7530_regmap_read,
++};
++
++static int
++mt7531_create_sgmii(struct mt7530_priv *priv)
++{
++	struct regmap_config *mt7531_pcs_config[2];
++	struct phylink_pcs *pcs;
++	struct regmap *regmap;
++	int i, ret = 0;
++
++	for (i = 0; i < 2; i++) {
++		mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
++						    sizeof(struct regmap_config),
++						    GFP_KERNEL);
++		if (!mt7531_pcs_config[i]) {
++			ret = -ENOMEM;
++			break;
++		}
++
++		mt7531_pcs_config[i]->name = i ? "port6" : "port5";
++		mt7531_pcs_config[i]->reg_bits = 16;
++		mt7531_pcs_config[i]->val_bits = 32;
++		mt7531_pcs_config[i]->reg_stride = 4;
++		mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
++		mt7531_pcs_config[i]->max_register = 0x17c;
++		mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
++		mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
++		mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
++
++		regmap = devm_regmap_init(priv->dev,
++					  &mt7530_regmap_bus, priv->bus,
++					  mt7531_pcs_config[i]);
++		if (IS_ERR(regmap)) {
++			ret = PTR_ERR(regmap);
++			break;
++		}
++		pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
++					   MT7531_PHYA_CTRL_SIGNAL3, 0);
++		if (!pcs) {
++			ret = -ENXIO;
++			break;
++		}
++		priv->ports[5 + i].sgmii_pcs = pcs;
++	}
++
++	if (ret && i)
++		mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
++
++	return ret;
++}
++
++static const struct of_device_id mt7530_of_match[] = {
++	{ .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
++	{ .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
++	{ .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mt7530_of_match);
++
++static int
++mt7530_probe(struct mdio_device *mdiodev)
++{
++	static struct regmap_config *regmap_config;
++	struct mt7530_priv *priv;
++	struct device_node *dn;
++	int ret;
++
++	dn = mdiodev->dev.of_node;
++
++	priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->bus = mdiodev->bus;
++	priv->dev = &mdiodev->dev;
++
++	ret = mt7530_probe_common(priv);
++	if (ret)
++		return ret;
++
++	/* Use medatek,mcm property to distinguish hardware type that would
++	 * cause a little bit differences on power-on sequence.
++	 * Not MCM that indicates switch works as the remote standalone
++	 * integrated circuit so the GPIO pin would be used to complete
++	 * the reset, otherwise memory-mapped register accessing used
++	 * through syscon provides in the case of MCM.
++	 */
++	priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
++	if (priv->mcm) {
++		dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
++
++		priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
++		if (IS_ERR(priv->rstc)) {
++			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
++			return PTR_ERR(priv->rstc);
++		}
++	} else {
++		priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
++						      GPIOD_OUT_LOW);
++		if (IS_ERR(priv->reset)) {
++			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
++			return PTR_ERR(priv->reset);
++		}
++	}
++
++	if (priv->id == ID_MT7530) {
++		priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
++		if (IS_ERR(priv->core_pwr))
++			return PTR_ERR(priv->core_pwr);
++
++		priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
++		if (IS_ERR(priv->io_pwr))
++			return PTR_ERR(priv->io_pwr);
++	}
++
++	regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
++				     GFP_KERNEL);
++	if (!regmap_config)
++		return -ENOMEM;
++
++	regmap_config->reg_bits = 16;
++	regmap_config->val_bits = 32;
++	regmap_config->reg_stride = 4;
++	regmap_config->max_register = MT7530_CREV;
++	regmap_config->disable_locking = true;
++	priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
++					priv->bus, regmap_config);
++	if (IS_ERR(priv->regmap))
++		return PTR_ERR(priv->regmap);
++
++	if (priv->id == ID_MT7531) {
++		ret = mt7531_create_sgmii(priv);
++		if (ret)
++			return ret;
++	}
++
++	return dsa_register_switch(priv->ds);
++}
++
++static void
++mt7530_remove(struct mdio_device *mdiodev)
++{
++	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
++	int ret = 0, i;
++
++	if (!priv)
++		return;
++
++	ret = regulator_disable(priv->core_pwr);
++	if (ret < 0)
++		dev_err(priv->dev,
++			"Failed to disable core power: %d\n", ret);
++
++	ret = regulator_disable(priv->io_pwr);
++	if (ret < 0)
++		dev_err(priv->dev, "Failed to disable io pwr: %d\n",
++			ret);
++
++	mt7530_remove_common(priv);
++
++	for (i = 0; i < 2; ++i)
++		mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
++}
++
++static void mt7530_shutdown(struct mdio_device *mdiodev)
++{
++	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
++
++	if (!priv)
++		return;
++
++	dsa_switch_shutdown(priv->ds);
++
++	dev_set_drvdata(&mdiodev->dev, NULL);
++}
++
++static struct mdio_driver mt7530_mdio_driver = {
++	.probe  = mt7530_probe,
++	.remove = mt7530_remove,
++	.shutdown = mt7530_shutdown,
++	.mdiodrv.driver = {
++		.name = "mt7530-mdio",
++		.of_match_table = mt7530_of_match,
++	},
++};
++
++mdio_module_driver(mt7530_mdio_driver);
++
++MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
++MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MDIO)");
++MODULE_LICENSE("GPL");
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -14,7 +14,6 @@
+ #include <linux/of_mdio.h>
+ #include <linux/of_net.h>
+ #include <linux/of_platform.h>
+-#include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+@@ -192,31 +191,6 @@ core_clear(struct mt7530_priv *priv, u32
+ }
+ 
+ static int
+-mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+-{
+-	struct mii_bus *bus = context;
+-	u16 page, r, lo, hi;
+-	int ret;
+-
+-	page = (reg >> 6) & 0x3ff;
+-	r  = (reg >> 2) & 0xf;
+-	lo = val & 0xffff;
+-	hi = val >> 16;
+-
+-	/* MT7530 uses 31 as the pseudo port */
+-	ret = bus->write(bus, 0x1f, 0x1f, page);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = bus->write(bus, 0x1f, r,  lo);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = bus->write(bus, 0x1f, 0x10, hi);
+-	return ret;
+-}
+-
+-static int
+ mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+ 	int ret;
+@@ -230,29 +204,6 @@ mt7530_mii_write(struct mt7530_priv *pri
+ 	return ret;
+ }
+ 
+-static int
+-mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+-{
+-	struct mii_bus *bus = context;
+-	u16 page, r, lo, hi;
+-	int ret;
+-
+-	page = (reg >> 6) & 0x3ff;
+-	r = (reg >> 2) & 0xf;
+-
+-	/* MT7530 uses 31 as the pseudo port */
+-	ret = bus->write(bus, 0x1f, 0x1f, page);
+-	if (ret < 0)
+-		return ret;
+-
+-	lo = bus->read(bus, 0x1f, r);
+-	hi = bus->read(bus, 0x1f, 0x10);
+-
+-	*val = (hi << 16) | (lo & 0xffff);
+-
+-	return 0;
+-}
+-
+ static u32
+ mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
+ {
+@@ -2975,72 +2926,6 @@ static const struct phylink_pcs_ops mt75
+ 	.pcs_an_restart = mt7530_pcs_an_restart,
+ };
+ 
+-static void
+-mt7530_mdio_regmap_lock(void *mdio_lock)
+-{
+-	mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
+-}
+-
+-static void
+-mt7530_mdio_regmap_unlock(void *mdio_lock)
+-{
+-	mutex_unlock(mdio_lock);
+-}
+-
+-static const struct regmap_bus mt7530_regmap_bus = {
+-	.reg_write = mt7530_regmap_write,
+-	.reg_read = mt7530_regmap_read,
+-};
+-
+-static int
+-mt7531_create_sgmii(struct mt7530_priv *priv)
+-{
+-	struct regmap_config *mt7531_pcs_config[2];
+-	struct phylink_pcs *pcs;
+-	struct regmap *regmap;
+-	int i, ret = 0;
+-
+-	for (i = 0; i < 2; i++) {
+-		mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
+-						    sizeof(struct regmap_config),
+-						    GFP_KERNEL);
+-		if (!mt7531_pcs_config[i]) {
+-			ret = -ENOMEM;
+-			break;
+-		}
+-
+-		mt7531_pcs_config[i]->name = i ? "port6" : "port5";
+-		mt7531_pcs_config[i]->reg_bits = 16;
+-		mt7531_pcs_config[i]->val_bits = 32;
+-		mt7531_pcs_config[i]->reg_stride = 4;
+-		mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
+-		mt7531_pcs_config[i]->max_register = 0x17c;
+-		mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
+-		mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
+-		mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+-
+-		regmap = devm_regmap_init(priv->dev,
+-					  &mt7530_regmap_bus, priv->bus,
+-					  mt7531_pcs_config[i]);
+-		if (IS_ERR(regmap)) {
+-			ret = PTR_ERR(regmap);
+-			break;
+-		}
+-		pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
+-					   MT7531_PHYA_CTRL_SIGNAL3, 0);
+-		if (!pcs) {
+-			ret = -ENXIO;
+-			break;
+-		}
+-		priv->ports[5 + i].sgmii_pcs = pcs;
+-	}
+-
+-	if (ret && i)
+-		mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
+-
+-	return ret;
+-}
+-
+ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+@@ -3099,7 +2984,7 @@ static int mt753x_set_mac_eee(struct dsa
+ 	return 0;
+ }
+ 
+-static const struct dsa_switch_ops mt7530_switch_ops = {
++const struct dsa_switch_ops mt7530_switch_ops = {
+ 	.get_tag_protocol	= mtk_get_tag_protocol,
+ 	.setup			= mt753x_setup,
+ 	.get_strings		= mt7530_get_strings,
+@@ -3133,8 +3018,9 @@ static const struct dsa_switch_ops mt753
+ 	.get_mac_eee		= mt753x_get_mac_eee,
+ 	.set_mac_eee		= mt753x_set_mac_eee,
+ };
++EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+ 
+-static const struct mt753x_info mt753x_table[] = {
++const struct mt753x_info mt753x_table[] = {
+ 	[ID_MT7621] = {
+ 		.id = ID_MT7621,
+ 		.pcs_ops = &mt7530_pcs_ops,
+@@ -3167,16 +3053,9 @@ static const struct mt753x_info mt753x_t
+ 		.mac_port_config = mt7531_mac_config,
+ 	},
+ };
++EXPORT_SYMBOL_GPL(mt753x_table);
+ 
+-static const struct of_device_id mt7530_of_match[] = {
+-	{ .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
+-	{ .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
+-	{ .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
+-	{ /* sentinel */ },
+-};
+-MODULE_DEVICE_TABLE(of, mt7530_of_match);
+-
+-static int
++int
+ mt7530_probe_common(struct mt7530_priv *priv)
+ {
+ 	struct device *dev = priv->dev;
+@@ -3213,88 +3092,9 @@ mt7530_probe_common(struct mt7530_priv *
+ 
+ 	return 0;
+ }
++EXPORT_SYMBOL_GPL(mt7530_probe_common);
+ 
+-static int
+-mt7530_probe(struct mdio_device *mdiodev)
+-{
+-	static struct regmap_config *regmap_config;
+-	struct mt7530_priv *priv;
+-	struct device_node *dn;
+-	int ret;
+-
+-	dn = mdiodev->dev.of_node;
+-
+-	priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+-
+-	priv->bus = mdiodev->bus;
+-	priv->dev = &mdiodev->dev;
+-
+-	ret = mt7530_probe_common(priv);
+-	if (ret)
+-		return ret;
+-
+-	/* Use medatek,mcm property to distinguish hardware type that would
+-	 * cause a little bit differences on power-on sequence.
+-	 * Not MCM that indicates switch works as the remote standalone
+-	 * integrated circuit so the GPIO pin would be used to complete
+-	 * the reset, otherwise memory-mapped register accessing used
+-	 * through syscon provides in the case of MCM.
+-	 */
+-	priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
+-	if (priv->mcm) {
+-		dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
+-
+-		priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
+-		if (IS_ERR(priv->rstc)) {
+-			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
+-			return PTR_ERR(priv->rstc);
+-		}
+-	} else {
+-		priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
+-						      GPIOD_OUT_LOW);
+-		if (IS_ERR(priv->reset)) {
+-			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
+-			return PTR_ERR(priv->reset);
+-		}
+-	}
+-
+-	if (priv->id == ID_MT7530) {
+-		priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
+-		if (IS_ERR(priv->core_pwr))
+-			return PTR_ERR(priv->core_pwr);
+-
+-		priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
+-		if (IS_ERR(priv->io_pwr))
+-			return PTR_ERR(priv->io_pwr);
+-	}
+-
+-	regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
+-				     GFP_KERNEL);
+-	if (!regmap_config)
+-		return -ENOMEM;
+-
+-	regmap_config->reg_bits = 16;
+-	regmap_config->val_bits = 32;
+-	regmap_config->reg_stride = 4;
+-	regmap_config->max_register = MT7530_CREV;
+-	regmap_config->disable_locking = true;
+-	priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+-					priv->bus, regmap_config);
+-	if (IS_ERR(priv->regmap))
+-		return PTR_ERR(priv->regmap);
+-
+-	if (priv->id == ID_MT7531) {
+-		ret = mt7531_create_sgmii(priv);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	return dsa_register_switch(priv->ds);
+-}
+-
+-static void
++void
+ mt7530_remove_common(struct mt7530_priv *priv)
+ {
+ 	if (priv->irq)
+@@ -3304,55 +3104,7 @@ mt7530_remove_common(struct mt7530_priv
+ 
+ 	mutex_destroy(&priv->reg_mutex);
+ }
+-
+-static void
+-mt7530_remove(struct mdio_device *mdiodev)
+-{
+-	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+-	int ret = 0, i;
+-
+-	if (!priv)
+-		return;
+-
+-	ret = regulator_disable(priv->core_pwr);
+-	if (ret < 0)
+-		dev_err(priv->dev,
+-			"Failed to disable core power: %d\n", ret);
+-
+-	ret = regulator_disable(priv->io_pwr);
+-	if (ret < 0)
+-		dev_err(priv->dev, "Failed to disable io pwr: %d\n",
+-			ret);
+-
+-	mt7530_remove_common(priv);
+-
+-	for (i = 0; i < 2; ++i)
+-		mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
+-}
+-
+-static void mt7530_shutdown(struct mdio_device *mdiodev)
+-{
+-	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+-
+-	if (!priv)
+-		return;
+-
+-	dsa_switch_shutdown(priv->ds);
+-
+-	dev_set_drvdata(&mdiodev->dev, NULL);
+-}
+-
+-static struct mdio_driver mt7530_mdio_driver = {
+-	.probe  = mt7530_probe,
+-	.remove = mt7530_remove,
+-	.shutdown = mt7530_shutdown,
+-	.mdiodrv.driver = {
+-		.name = "mt7530",
+-		.of_match_table = mt7530_of_match,
+-	},
+-};
+-
+-mdio_module_driver(mt7530_mdio_driver);
++EXPORT_SYMBOL_GPL(mt7530_remove_common);
+ 
+ MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
+ MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -814,4 +814,10 @@ static inline void INIT_MT7530_DUMMY_POL
+ 	p->reg = reg;
+ }
+ 
++int mt7530_probe_common(struct mt7530_priv *priv);
++void mt7530_remove_common(struct mt7530_priv *priv);
++
++extern const struct dsa_switch_ops mt7530_switch_ops;
++extern const struct mt753x_info mt753x_table[];
++
+ #endif /* __MT7530_H */
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0011-net-dsa-mt7530-skip-locking-if-MDIO-bus-isn-t-presen.patch b/target/linux/generic/backport-6.1/790-v6.4-0011-net-dsa-mt7530-skip-locking-if-MDIO-bus-isn-t-presen.patch
new file mode 100644
index 00000000000000..01011ed1a001c4
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0011-net-dsa-mt7530-skip-locking-if-MDIO-bus-isn-t-presen.patch
@@ -0,0 +1,47 @@
+From a52cadbf76593f8fcb2f4f62cb006e3f2a22ad06 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:19:28 +0100
+Subject: [PATCH 11/13] net: dsa: mt7530: skip locking if MDIO bus isn't
+ present
+
+As MT7530 and MT7531 internally use 32-bit wide registers, each access
+to any register of the switch requires several operations on the MDIO
+bus. Hence if there is congruent access, e.g. due to PCS or PHY
+polling, this can mess up and interfere with another ongoing register
+access sequence.
+
+However, the MDIO bus mutex is only relevant for MDIO-connected
+switches. Prepare switches which have there registers directly mapped
+into the SoCs register space via MMIO which do not require such
+locking. There we can simply use regmap's default locking mechanism.
+
+Hence guard mutex operations to only be performed in case of MDIO
+connected switches.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -144,13 +144,15 @@ err:
+ static void
+ mt7530_mutex_lock(struct mt7530_priv *priv)
+ {
+-	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++	if (priv->bus)
++		mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+ }
+ 
+ static void
+ mt7530_mutex_unlock(struct mt7530_priv *priv)
+ {
+-	mutex_unlock(&priv->bus->mdio_lock);
++	if (priv->bus)
++		mutex_unlock(&priv->bus->mdio_lock);
+ }
+ 
+ static void
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
new file mode 100644
index 00000000000000..da6d3c22c81f00
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
@@ -0,0 +1,421 @@
+From b361015763fedea439f13b336b15ef7bdf1f7d4f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:19:40 +0100
+Subject: [PATCH 12/13] net: dsa: mt7530: introduce driver for MT7988 built-in
+ switch
+
+Add driver for the built-in Gigabit Ethernet switch which can be found
+in the MediaTek MT7988 SoC.
+
+The switch shares most of its design with MT7530 and MT7531, but has
+it's registers mapped into the SoCs register space rather than being
+connected externally or internally via MDIO.
+
+Introduce a new platform driver to support that.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS                   |   2 +
+ drivers/net/dsa/Kconfig       |  12 +++
+ drivers/net/dsa/Makefile      |   1 +
+ drivers/net/dsa/mt7530-mmio.c | 101 +++++++++++++++++++++++++
+ drivers/net/dsa/mt7530.c      | 137 +++++++++++++++++++++++++++++++++-
+ drivers/net/dsa/mt7530.h      |  12 +--
+ 6 files changed, 255 insertions(+), 10 deletions(-)
+ create mode 100644 drivers/net/dsa/mt7530-mmio.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -13060,9 +13060,11 @@ MEDIATEK SWITCH DRIVER
+ M:	Sean Wang <sean.wang@mediatek.com>
+ M:	Landen Chao <Landen.Chao@mediatek.com>
+ M:	DENG Qingfang <dqfext@gmail.com>
++M:	Daniel Golle <daniel@makrotopia.org>
+ L:	netdev@vger.kernel.org
+ S:	Maintained
+ F:	drivers/net/dsa/mt7530-mdio.c
++F:	drivers/net/dsa/mt7530-mmio.c
+ F:	drivers/net/dsa/mt7530.*
+ F:	net/dsa/tag_mtk.c
+ 
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -38,6 +38,7 @@ config NET_DSA_MT7530
+ 	select NET_DSA_TAG_MTK
+ 	select MEDIATEK_GE_PHY
+ 	imply NET_DSA_MT7530_MDIO
++	imply NET_DSA_MT7530_MMIO
+ 	help
+ 	  This enables support for the MediaTek MT7530 and MT7531 Ethernet
+ 	  switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
+@@ -54,6 +55,17 @@ config NET_DSA_MT7530_MDIO
+ 	  module MT7530 which can be found in the MT7621AT, MT7621DAT,
+ 	  MT7621ST and MT7623AI SoCs.
+ 
++config NET_DSA_MT7530_MMIO
++	tristate "MediaTek MT7530 MMIO interface driver"
++	depends on NET_DSA_MT7530
++	depends on HAS_IOMEM
++	help
++	  This enables support for the built-in Ethernet switch found
++	  in the MediaTek MT7988 SoC.
++	  The switch is a similar design as MT7531, but the switch registers
++	  are directly mapped into the SoCs register space rather than being
++	  accessible via MDIO.
++
+ config NET_DSA_MV88E6060
+ 	tristate "Marvell 88E6060 ethernet switch chip support"
+ 	select NET_DSA_TAG_TRAILER
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -8,6 +8,7 @@ endif
+ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
+ obj-$(CONFIG_NET_DSA_MT7530)	+= mt7530.o
+ obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
++obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+ obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
+ obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
+--- /dev/null
++++ b/drivers/net/dsa/mt7530-mmio.c
+@@ -0,0 +1,101 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <net/dsa.h>
++
++#include "mt7530.h"
++
++static const struct of_device_id mt7988_of_match[] = {
++	{ .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mt7988_of_match);
++
++static int
++mt7988_probe(struct platform_device *pdev)
++{
++	static struct regmap_config *sw_regmap_config;
++	struct mt7530_priv *priv;
++	void __iomem *base_addr;
++	int ret;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->bus = NULL;
++	priv->dev = &pdev->dev;
++
++	ret = mt7530_probe_common(priv);
++	if (ret)
++		return ret;
++
++	priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->rstc)) {
++		dev_err(&pdev->dev, "Couldn't get our reset line\n");
++		return PTR_ERR(priv->rstc);
++	}
++
++	base_addr = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(base_addr)) {
++		dev_err(&pdev->dev, "cannot request I/O memory space\n");
++		return -ENXIO;
++	}
++
++	sw_regmap_config = devm_kzalloc(&pdev->dev, sizeof(*sw_regmap_config), GFP_KERNEL);
++	if (!sw_regmap_config)
++		return -ENOMEM;
++
++	sw_regmap_config->name = "switch";
++	sw_regmap_config->reg_bits = 16;
++	sw_regmap_config->val_bits = 32;
++	sw_regmap_config->reg_stride = 4;
++	sw_regmap_config->max_register = MT7530_CREV;
++	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base_addr, sw_regmap_config);
++	if (IS_ERR(priv->regmap))
++		return PTR_ERR(priv->regmap);
++
++	return dsa_register_switch(priv->ds);
++}
++
++static int
++mt7988_remove(struct platform_device *pdev)
++{
++	struct mt7530_priv *priv = platform_get_drvdata(pdev);
++
++	if (priv)
++		mt7530_remove_common(priv);
++
++	return 0;
++}
++
++static void mt7988_shutdown(struct platform_device *pdev)
++{
++	struct mt7530_priv *priv = platform_get_drvdata(pdev);
++
++	if (!priv)
++		return;
++
++	dsa_switch_shutdown(priv->ds);
++
++	dev_set_drvdata(&pdev->dev, NULL);
++}
++
++static struct platform_driver mt7988_platform_driver = {
++	.probe  = mt7988_probe,
++	.remove = mt7988_remove,
++	.shutdown = mt7988_shutdown,
++	.driver = {
++		.name = "mt7530-mmio",
++		.of_match_table = mt7988_of_match,
++	},
++};
++module_platform_driver(mt7988_platform_driver);
++
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MMIO)");
++MODULE_LICENSE("GPL");
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2005,6 +2005,47 @@ static const struct irq_domain_ops mt753
+ };
+ 
+ static void
++mt7988_irq_mask(struct irq_data *d)
++{
++	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
++
++	priv->irq_enable &= ~BIT(d->hwirq);
++	mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
++}
++
++static void
++mt7988_irq_unmask(struct irq_data *d)
++{
++	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
++
++	priv->irq_enable |= BIT(d->hwirq);
++	mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
++}
++
++static struct irq_chip mt7988_irq_chip = {
++	.name = KBUILD_MODNAME,
++	.irq_mask = mt7988_irq_mask,
++	.irq_unmask = mt7988_irq_unmask,
++};
++
++static int
++mt7988_irq_map(struct irq_domain *domain, unsigned int irq,
++	       irq_hw_number_t hwirq)
++{
++	irq_set_chip_data(irq, domain->host_data);
++	irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq);
++	irq_set_nested_thread(irq, true);
++	irq_set_noprobe(irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops mt7988_irq_domain_ops = {
++	.map = mt7988_irq_map,
++	.xlate = irq_domain_xlate_onecell,
++};
++
++static void
+ mt7530_setup_mdio_irq(struct mt7530_priv *priv)
+ {
+ 	struct dsa_switch *ds = priv->ds;
+@@ -2038,8 +2079,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
+ 		return priv->irq ? : -EINVAL;
+ 	}
+ 
+-	priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
+-						 &mt7530_irq_domain_ops, priv);
++	if (priv->id == ID_MT7988)
++		priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
++							 &mt7988_irq_domain_ops,
++							 priv);
++	else
++		priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
++							 &mt7530_irq_domain_ops,
++							 priv);
++
+ 	if (!priv->irq_domain) {
+ 		dev_err(dev, "failed to create IRQ domain\n");
+ 		return -ENOMEM;
+@@ -2538,6 +2586,25 @@ static void mt7531_mac_port_get_caps(str
+ 	}
+ }
+ 
++static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
++				     struct phylink_config *config)
++{
++	phy_interface_zero(config->supported_interfaces);
++
++	switch (port) {
++	case 0 ... 4: /* Internal phy */
++		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
++			  config->supported_interfaces);
++		break;
++
++	case 6:
++		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
++			  config->supported_interfaces);
++		config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
++					   MAC_10000FD;
++	}
++}
++
+ static int
+ mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
+ {
+@@ -2614,6 +2681,17 @@ static bool mt753x_is_mac_port(u32 port)
+ }
+ 
+ static int
++mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++		  phy_interface_t interface)
++{
++	if (dsa_is_cpu_port(ds, port) &&
++	    interface == PHY_INTERFACE_MODE_INTERNAL)
++		return 0;
++
++	return -EINVAL;
++}
++
++static int
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ 		  phy_interface_t interface)
+ {
+@@ -2683,7 +2761,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+ 
+ 	switch (port) {
+ 	case 0 ... 4: /* Internal phy */
+-		if (state->interface != PHY_INTERFACE_MODE_GMII)
++		if (state->interface != PHY_INTERFACE_MODE_GMII &&
++		    state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ 			goto unsupported;
+ 		break;
+ 	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
+@@ -2761,7 +2840,8 @@ static void mt753x_phylink_mac_link_up(s
+ 	/* MT753x MAC works in 1G full duplex mode for all up-clocked
+ 	 * variants.
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_TRGMII ||
++	if (interface == PHY_INTERFACE_MODE_INTERNAL ||
++	    interface == PHY_INTERFACE_MODE_TRGMII ||
+ 	    (phy_interface_mode_is_8023z(interface))) {
+ 		speed = SPEED_1000;
+ 		duplex = DUPLEX_FULL;
+@@ -2841,6 +2921,21 @@ mt7531_cpu_port_config(struct dsa_switch
+ 	return 0;
+ }
+ 
++static int
++mt7988_cpu_port_config(struct dsa_switch *ds, int port)
++{
++	struct mt7530_priv *priv = ds->priv;
++
++	mt7530_write(priv, MT7530_PMCR_P(port),
++		     PMCR_CPU_PORT_SETTING(priv->id));
++
++	mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
++				   PHY_INTERFACE_MODE_INTERNAL, NULL,
++				   SPEED_10000, DUPLEX_FULL, true, true);
++
++	return 0;
++}
++
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+ 				    struct phylink_config *config)
+ {
+@@ -2986,6 +3081,27 @@ static int mt753x_set_mac_eee(struct dsa
+ 	return 0;
+ }
+ 
++static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
++{
++	return 0;
++}
++
++static int mt7988_setup(struct dsa_switch *ds)
++{
++	struct mt7530_priv *priv = ds->priv;
++
++	/* Reset the switch */
++	reset_control_assert(priv->rstc);
++	usleep_range(20, 50);
++	reset_control_deassert(priv->rstc);
++	usleep_range(20, 50);
++
++	/* Reset the switch PHYs */
++	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
++
++	return mt7531_setup_common(ds);
++}
++
+ const struct dsa_switch_ops mt7530_switch_ops = {
+ 	.get_tag_protocol	= mtk_get_tag_protocol,
+ 	.setup			= mt753x_setup,
+@@ -3054,6 +3170,17 @@ const struct mt753x_info mt753x_table[]
+ 		.mac_port_get_caps = mt7531_mac_port_get_caps,
+ 		.mac_port_config = mt7531_mac_config,
+ 	},
++	[ID_MT7988] = {
++		.id = ID_MT7988,
++		.pcs_ops = &mt7530_pcs_ops,
++		.sw_setup = mt7988_setup,
++		.phy_read = mt7531_ind_phy_read,
++		.phy_write = mt7531_ind_phy_write,
++		.pad_setup = mt7988_pad_setup,
++		.cpu_port_config = mt7988_cpu_port_config,
++		.mac_port_get_caps = mt7988_mac_port_get_caps,
++		.mac_port_config = mt7988_mac_config,
++	},
+ };
+ EXPORT_SYMBOL_GPL(mt753x_table);
+ 
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -18,6 +18,7 @@ enum mt753x_id {
+ 	ID_MT7530 = 0,
+ 	ID_MT7621 = 1,
+ 	ID_MT7531 = 2,
++	ID_MT7988 = 3,
+ };
+ 
+ #define	NUM_TRGMII_CTRL			5
+@@ -54,11 +55,11 @@ enum mt753x_id {
+ #define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
+ #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
+ 
+-#define MT753X_MIRROR_REG(id)		(((id) == ID_MT7531) ? \
++#define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+ 					 MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id)		(((id) == ID_MT7531) ? \
++#define MT753X_MIRROR_EN(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+ 					 MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id)		(((id) == ID_MT7531) ? \
++#define MT753X_MIRROR_MASK(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+ 					 MT7531_MIRROR_MASK : MIRROR_MASK)
+ 
+ /* Registers for BPDU and PAE frame control*/
+@@ -302,9 +303,8 @@ enum mt7530_vlan_port_acc_frm {
+ 					 MT7531_FORCE_DPX | \
+ 					 MT7531_FORCE_RX_FC | \
+ 					 MT7531_FORCE_TX_FC)
+-#define  PMCR_FORCE_MODE_ID(id)		(((id) == ID_MT7531) ? \
+-					 MT7531_FORCE_MODE : \
+-					 PMCR_FORCE_MODE)
++#define  PMCR_FORCE_MODE_ID(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
++					 MT7531_FORCE_MODE : PMCR_FORCE_MODE)
+ #define  PMCR_LINK_SETTINGS_MASK	(PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ 					 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ 					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
diff --git a/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch
new file mode 100644
index 00000000000000..5b5f25e7afaf10
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch
@@ -0,0 +1,118 @@
+From eb1dd407b4be7ca38166a38c56c8edf52c6a399f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 16 Apr 2023 13:08:14 +0100
+Subject: [PATCH 13/13] net: dsa: mt7530: fix support for MT7531BE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are two variants of the MT7531 switch IC which got different
+features (and pins) regarding port 5:
+ * MT7531AE: SGMII/1000Base-X/2500Base-X SerDes PCS
+ * MT7531BE: RGMII
+
+Moving the creation of the SerDes PCS from mt753x_setup to mt7530_probe
+with commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation
+to mt7530_probe function") works fine for MT7531AE which got two
+instances of mtk-pcs-lynxi, however, MT7531BE requires mt7531_pll_setup
+to setup clocks before the single PCS on port 6 (usually used as CPU
+port) starts to work and hence the PCS creation failed on MT7531BE.
+
+Fix this by introducing a pointer to mt7531_create_sgmii function in
+struct mt7530_priv and call it again at the end of mt753x_setup like it
+was before commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS
+creation to mt7530_probe function").
+
+Fixes: 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation to mt7530_probe function")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/ZDvlLhhqheobUvOK@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530-mdio.c | 16 ++++++++--------
+ drivers/net/dsa/mt7530.c      |  6 ++++++
+ drivers/net/dsa/mt7530.h      |  4 ++--
+ 3 files changed, 16 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -81,14 +81,17 @@ static const struct regmap_bus mt7530_re
+ };
+ 
+ static int
+-mt7531_create_sgmii(struct mt7530_priv *priv)
++mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)
+ {
+-	struct regmap_config *mt7531_pcs_config[2];
++	struct regmap_config *mt7531_pcs_config[2] = {};
+ 	struct phylink_pcs *pcs;
+ 	struct regmap *regmap;
+ 	int i, ret = 0;
+ 
+-	for (i = 0; i < 2; i++) {
++	/* MT7531AE has two SGMII units for port 5 and port 6
++	 * MT7531BE has only one SGMII unit for port 6
++	 */
++	for (i = dual_sgmii ? 0 : 1; i < 2; i++) {
+ 		mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
+ 						    sizeof(struct regmap_config),
+ 						    GFP_KERNEL);
+@@ -208,11 +211,8 @@ mt7530_probe(struct mdio_device *mdiodev
+ 	if (IS_ERR(priv->regmap))
+ 		return PTR_ERR(priv->regmap);
+ 
+-	if (priv->id == ID_MT7531) {
+-		ret = mt7531_create_sgmii(priv);
+-		if (ret)
+-			return ret;
+-	}
++	if (priv->id == ID_MT7531)
++		priv->create_sgmii = mt7531_create_sgmii;
+ 
+ 	return dsa_register_switch(priv->ds);
+ }
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3048,6 +3048,12 @@ mt753x_setup(struct dsa_switch *ds)
+ 	if (ret && priv->irq)
+ 		mt7530_free_irq_common(priv);
+ 
++	if (priv->create_sgmii) {
++		ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
++		if (ret && priv->irq)
++			mt7530_free_irq(priv);
++	}
++
+ 	return ret;
+ }
+ 
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -748,10 +748,10 @@ struct mt753x_info {
+  *			registers
+  * @p6_interface	Holding the current port 6 interface
+  * @p5_intf_sel:	Holding the current port 5 interface select
+- *
+  * @irq:		IRQ number of the switch
+  * @irq_domain:		IRQ domain of the switch irq_chip
+  * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN
++ * @create_sgmii:	Pointer to function creating SGMII PCS instance(s)
+  */
+ struct mt7530_priv {
+ 	struct device		*dev;
+@@ -770,7 +770,6 @@ struct mt7530_priv {
+ 	unsigned int		p5_intf_sel;
+ 	u8			mirror_rx;
+ 	u8			mirror_tx;
+-
+ 	struct mt7530_port	ports[MT7530_NUM_PORTS];
+ 	struct mt753x_pcs	pcs[MT7530_NUM_PORTS];
+ 	/* protect among processes for registers access*/
+@@ -778,6 +777,7 @@ struct mt7530_priv {
+ 	int irq;
+ 	struct irq_domain *irq_domain;
+ 	u32 irq_enable;
++	int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
+ };
+ 
+ struct mt7530_hw_vlan_entry {
diff --git a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
index f82dc1428aa552..15af039a16f01d 100644
--- a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
+++ b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
@@ -148,7 +148,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
   * of_find_node_by_phandle - Find a node given a phandle
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -2315,8 +2315,8 @@ of_register_spi_device(struct spi_contro
+@@ -2326,8 +2326,8 @@ of_register_spi_device(struct spi_contro
  	}
  
  	/* Select device driver */
diff --git a/target/linux/generic/backport-6.6/001-CONFIG_INITRAMFS_PRESERVE_MTIME.patch b/target/linux/generic/backport-6.6/001-CONFIG_INITRAMFS_PRESERVE_MTIME.patch
new file mode 100644
index 00000000000000..a9bf15d6ed9667
--- /dev/null
+++ b/target/linux/generic/backport-6.6/001-CONFIG_INITRAMFS_PRESERVE_MTIME.patch
@@ -0,0 +1,75 @@
+--- a/init/Kconfig
++++ b/init/Kconfig
+@@ -1347,16 +1347,6 @@ config BOOT_CONFIG_EMBED_FILE
+ 	  This bootconfig will be used if there is no initrd or no other
+ 	  bootconfig in the initrd.
+ 
+-config INITRAMFS_PRESERVE_MTIME
+-	bool "Preserve cpio archive mtimes in initramfs"
+-	default y
+-	help
+-	  Each entry in an initramfs cpio archive carries an mtime value. When
+-	  enabled, extracted cpio items take this mtime, with directory mtime
+-	  setting deferred until after creation of any child entries.
+-
+-	  If unsure, say Y.
+-
+ choice
+ 	prompt "Compiler optimization level"
+ 	default CC_OPTIMIZE_FOR_PERFORMANCE
+--- a/init/initramfs.c
++++ b/init/initramfs.c
+@@ -121,17 +121,15 @@ static void __init free_hash(void)
+ 	}
+ }
+ 
+-#ifdef CONFIG_INITRAMFS_PRESERVE_MTIME
+-static void __init do_utime(char *filename, time64_t mtime)
++static long __init do_utime(char *filename, time64_t mtime)
+ {
+-	struct timespec64 t[2] = { { .tv_sec = mtime }, { .tv_sec = mtime } };
+-	init_utimes(filename, t);
+-}
++	struct timespec64 t[2];
+ 
+-static void __init do_utime_path(const struct path *path, time64_t mtime)
+-{
+-	struct timespec64 t[2] = { { .tv_sec = mtime }, { .tv_sec = mtime } };
+-	vfs_utimes(path, t);
++	t[0].tv_sec = mtime;
++	t[0].tv_nsec = 0;
++	t[1].tv_sec = mtime;
++	t[1].tv_nsec = 0;
++	return init_utimes(filename, t);
+ }
+ 
+ static __initdata LIST_HEAD(dir_list);
+@@ -164,12 +162,6 @@ static void __init dir_utime(void)
+ 		kfree(de);
+ 	}
+ }
+-#else
+-static void __init do_utime(char *filename, time64_t mtime) {}
+-static void __init do_utime_path(const struct path *path, time64_t mtime) {}
+-static void __init dir_add(const char *name, time64_t mtime) {}
+-static void __init dir_utime(void) {}
+-#endif
+ 
+ static __initdata time64_t mtime;
+ 
+@@ -401,10 +393,14 @@ static int __init do_name(void)
+ static int __init do_copy(void)
+ {
+ 	if (byte_count >= body_len) {
++		struct timespec64 t[2] = { };
+ 		if (xwrite(wfile, victim, body_len, &wfile_pos) != body_len)
+ 			error("write error");
+ 
+-		do_utime_path(&wfile->f_path, mtime);
++		t[0].tv_sec = mtime;
++		t[1].tv_sec = mtime;
++		vfs_utimes(&wfile->f_path, t);
++
+ 		fput(wfile);
+ 		if (csum_present && io_csum != hdr_csum)
+ 			error("bad data checksum");
diff --git a/target/linux/generic/backport-6.6/002-struct-net_device.patch b/target/linux/generic/backport-6.6/002-struct-net_device.patch
new file mode 100644
index 00000000000000..caff802ebbb82b
--- /dev/null
+++ b/target/linux/generic/backport-6.6/002-struct-net_device.patch
@@ -0,0 +1,146 @@
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -576,8 +576,8 @@ static inline bool napi_if_scheduled_mar
+ {
+ 	unsigned long val, new;
+ 
+-	val = READ_ONCE(n->state);
+ 	do {
++		val = READ_ONCE(n->state);
+ 		if (val & NAPIF_STATE_DISABLE)
+ 			return true;
+ 
+@@ -585,7 +585,7 @@ static inline bool napi_if_scheduled_mar
+ 			return false;
+ 
+ 		new = val | NAPIF_STATE_MISSED;
+-	} while (!try_cmpxchg(&n->state, &val, new));
++	} while (cmpxchg(&n->state, val, new) != val);
+ 
+ 	return true;
+ }
+@@ -1906,6 +1906,7 @@ enum netdev_stat_type {
+  *	@tipc_ptr:	TIPC specific data
+  *	@atalk_ptr:	AppleTalk link
+  *	@ip_ptr:	IPv4 specific data
++ *	@dn_ptr:	DECnet specific data
+  *	@ip6_ptr:	IPv6 specific data
+  *	@ax25_ptr:	AX.25 specific data
+  *	@ieee80211_ptr:	IEEE 802.11 specific data, assign before registering
+@@ -2202,8 +2203,6 @@ struct net_device {
+ 
+ 	/* Protocol-specific pointers */
+ 
+-	struct in_device __rcu	*ip_ptr;
+-	struct inet6_dev __rcu	*ip6_ptr;
+ #if IS_ENABLED(CONFIG_VLAN_8021Q)
+ 	struct vlan_info __rcu	*vlan_info;
+ #endif
+@@ -2216,15 +2215,16 @@ struct net_device {
+ #if IS_ENABLED(CONFIG_ATALK)
+ 	void 			*atalk_ptr;
+ #endif
++	struct in_device __rcu	*ip_ptr;
++#if IS_ENABLED(CONFIG_DECNET)
++	struct dn_dev __rcu     *dn_ptr;
++#endif
++	struct inet6_dev __rcu	*ip6_ptr;
+ #if IS_ENABLED(CONFIG_AX25)
+ 	void			*ax25_ptr;
+ #endif
+-#if IS_ENABLED(CONFIG_CFG80211)
+ 	struct wireless_dev	*ieee80211_ptr;
+-#endif
+-#if IS_ENABLED(CONFIG_IEEE802154) || IS_ENABLED(CONFIG_6LOWPAN)
+ 	struct wpan_dev		*ieee802154_ptr;
+-#endif
+ #if IS_ENABLED(CONFIG_MPLS_ROUTING)
+ 	struct mpls_dev __rcu	*mpls_ptr;
+ #endif
+@@ -2655,6 +2655,8 @@ netif_napi_add_tx_weight(struct net_devi
+ 	netif_napi_add_weight(dev, napi, poll, weight);
+ }
+ 
++#define netif_tx_napi_add netif_napi_add_tx_weight
++
+ /**
+  * netif_napi_add_tx() - initialize a NAPI context to be used for Tx only
+  * @dev:  network device
+--- a/include/net/cfg802154.h
++++ b/include/net/cfg802154.h
+@@ -482,7 +482,6 @@ struct wpan_dev {
+ 
+ #define to_phy(_dev)	container_of(_dev, struct wpan_phy, dev)
+ 
+-#if IS_ENABLED(CONFIG_IEEE802154) || IS_ENABLED(CONFIG_6LOWPAN)
+ static inline int
+ wpan_dev_hard_header(struct sk_buff *skb, struct net_device *dev,
+ 		     const struct ieee802154_addr *daddr,
+@@ -493,7 +492,6 @@ wpan_dev_hard_header(struct sk_buff *skb
+ 
+ 	return wpan_dev->header_ops->create(skb, dev, daddr, saddr, len);
+ }
+-#endif
+ 
+ struct wpan_phy *
+ wpan_phy_new(const struct cfg802154_ops *ops, size_t priv_size);
+--- a/net/batman-adv/hard-interface.c
++++ b/net/batman-adv/hard-interface.c
+@@ -309,11 +309,9 @@ static bool batadv_is_cfg80211_netdev(st
+ 	if (!net_device)
+ 		return false;
+ 
+-#if IS_ENABLED(CONFIG_CFG80211)
+ 	/* cfg80211 drivers have to set ieee80211_ptr */
+ 	if (net_device->ieee80211_ptr)
+ 		return true;
+-#endif
+ 
+ 	return false;
+ }
+--- a/net/core/net-sysfs.c
++++ b/net/core/net-sysfs.c
+@@ -748,6 +748,7 @@ static const struct attribute_group nets
+ 	.attrs  = netstat_attrs,
+ };
+ 
++#if IS_ENABLED(CONFIG_WIRELESS_EXT) || IS_ENABLED(CONFIG_CFG80211)
+ static struct attribute *wireless_attrs[] = {
+ 	NULL
+ };
+@@ -756,19 +757,7 @@ static const struct attribute_group wire
+ 	.name = "wireless",
+ 	.attrs = wireless_attrs,
+ };
+-
+-static bool wireless_group_needed(struct net_device *ndev)
+-{
+-#if IS_ENABLED(CONFIG_CFG80211)
+-	if (ndev->ieee80211_ptr)
+-		return true;
+ #endif
+-#if IS_ENABLED(CONFIG_WIRELESS_EXT)
+-	if (ndev->wireless_handlers)
+-		return true;
+-#endif
+-	return false;
+-}
+ 
+ #else /* CONFIG_SYSFS */
+ #define net_class_groups	NULL
+@@ -2037,8 +2026,14 @@ int netdev_register_kobject(struct net_d
+ 
+ 	*groups++ = &netstat_group;
+ 
+-	if (wireless_group_needed(ndev))
++#if IS_ENABLED(CONFIG_WIRELESS_EXT) || IS_ENABLED(CONFIG_CFG80211)
++	if (ndev->ieee80211_ptr)
++		*groups++ = &wireless_group;
++#if IS_ENABLED(CONFIG_WIRELESS_EXT)
++	else if (ndev->wireless_handlers)
+ 		*groups++ = &wireless_group;
++#endif
++#endif
+ #endif /* CONFIG_SYSFS */
+ 
+ 	error = device_add(dev);
diff --git a/target/linux/generic/backport-6.6/005-Revert-genetlink-remove-userhdr-from-struct-genl_inf.patch b/target/linux/generic/backport-6.6/005-Revert-genetlink-remove-userhdr-from-struct-genl_inf.patch
new file mode 100644
index 00000000000000..2815ba78fecf9d
--- /dev/null
+++ b/target/linux/generic/backport-6.6/005-Revert-genetlink-remove-userhdr-from-struct-genl_inf.patch
@@ -0,0 +1,279 @@
+From ca31fb1ed58c293b3f02b1aa46aa672866aff540 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Thu, 17 Aug 2023 17:06:55 -0400
+Subject: [PATCH 7/8] Revert "genetlink: remove userhdr from struct genl_info"
+
+This reverts commit bffcc6882a1bb2be8c9420184966f4c2c822078e.
+---
+ drivers/block/drbd/drbd_nl.c |  9 ++++-----
+ include/net/genetlink.h      |  7 ++-----
+ net/netlink/genetlink.c      |  1 +
+ net/openvswitch/conntrack.c  |  2 +-
+ net/openvswitch/datapath.c   | 29 +++++++++++++----------------
+ net/openvswitch/meter.c      | 10 +++++-----
+ net/tipc/netlink_compat.c    |  2 +-
+ 7 files changed, 27 insertions(+), 33 deletions(-)
+
+--- a/drivers/block/drbd/drbd_nl.c
++++ b/drivers/block/drbd/drbd_nl.c
+@@ -159,7 +159,7 @@ static int drbd_msg_sprintf_info(struct
+ static int drbd_adm_prepare(struct drbd_config_context *adm_ctx,
+ 	struct sk_buff *skb, struct genl_info *info, unsigned flags)
+ {
+-	struct drbd_genlmsghdr *d_in = genl_info_userhdr(info);
++	struct drbd_genlmsghdr *d_in = info->userhdr;
+ 	const u8 cmd = info->genlhdr->cmd;
+ 	int err;
+ 
+@@ -1396,9 +1396,8 @@ static void drbd_suspend_al(struct drbd_
+ 
+ static bool should_set_defaults(struct genl_info *info)
+ {
+-	struct drbd_genlmsghdr *dh = genl_info_userhdr(info);
+-
+-	return 0 != (dh->flags & DRBD_GENL_F_SET_DEFAULTS);
++	unsigned flags = ((struct drbd_genlmsghdr*)info->userhdr)->flags;
++	return 0 != (flags & DRBD_GENL_F_SET_DEFAULTS);
+ }
+ 
+ static unsigned int drbd_al_extents_max(struct drbd_backing_dev *bdev)
+@@ -4277,7 +4276,7 @@ static void device_to_info(struct device
+ int drbd_adm_new_minor(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct drbd_config_context adm_ctx;
+-	struct drbd_genlmsghdr *dh = genl_info_userhdr(info);
++	struct drbd_genlmsghdr *dh = info->userhdr;
+ 	enum drbd_ret_code retcode;
+ 
+ 	retcode = drbd_adm_prepare(&adm_ctx, skb, info, DRBD_ADM_NEED_RESOURCE);
+--- a/include/net/genetlink.h
++++ b/include/net/genetlink.h
+@@ -98,6 +98,7 @@ struct genl_family {
+  * @family: generic netlink family
+  * @nlhdr: netlink message header
+  * @genlhdr: generic netlink message header
++ * @userhdr: user specific header
+  * @attrs: netlink attributes
+  * @_net: network namespace
+  * @user_ptr: user pointers
+@@ -109,6 +110,7 @@ struct genl_info {
+ 	const struct genl_family *family;
+ 	const struct nlmsghdr *	nlhdr;
+ 	struct genlmsghdr *	genlhdr;
++	void *			userhdr;
+ 	struct nlattr **	attrs;
+ 	possible_net_t		_net;
+ 	void *			user_ptr[2];
+@@ -125,11 +127,6 @@ static inline void genl_info_net_set(str
+ 	write_pnet(&info->_net, net);
+ }
+ 
+-static inline void *genl_info_userhdr(const struct genl_info *info)
+-{
+-	return (u8 *)info->genlhdr + GENL_HDRLEN;
+-}
+-
+ #define GENL_SET_ERR_MSG(info, msg) NL_SET_ERR_MSG((info)->extack, msg)
+ 
+ #define GENL_SET_ERR_MSG_FMT(info, msg, args...) \
+--- a/net/netlink/genetlink.c
++++ b/net/netlink/genetlink.c
+@@ -957,6 +957,7 @@ static int genl_family_rcv_msg_doit(cons
+ 	info.family = family;
+ 	info.nlhdr = nlh;
+ 	info.genlhdr = nlmsg_data(nlh);
++	info.userhdr = nlmsg_data(nlh) + GENL_HDRLEN;
+ 	info.attrs = attrbuf;
+ 	info.extack = extack;
+ 	genl_info_net_set(&info, net);
+--- a/net/openvswitch/conntrack.c
++++ b/net/openvswitch/conntrack.c
+@@ -1605,7 +1605,7 @@ static struct sk_buff *
+ ovs_ct_limit_cmd_reply_start(struct genl_info *info, u8 cmd,
+ 			     struct ovs_header **ovs_reply_header)
+ {
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct sk_buff *skb;
+ 
+ 	skb = genlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+--- a/net/openvswitch/datapath.c
++++ b/net/openvswitch/datapath.c
+@@ -590,7 +590,7 @@ out:
+ 
+ static int ovs_packet_cmd_execute(struct sk_buff *skb, struct genl_info *info)
+ {
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct net *net = sock_net(skb->sk);
+ 	struct nlattr **a = info->attrs;
+ 	struct sw_flow_actions *acts;
+@@ -967,7 +967,7 @@ static int ovs_flow_cmd_new(struct sk_bu
+ {
+ 	struct net *net = sock_net(skb->sk);
+ 	struct nlattr **a = info->attrs;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct sw_flow *flow = NULL, *new_flow;
+ 	struct sw_flow_mask mask;
+ 	struct sk_buff *reply;
+@@ -1214,7 +1214,7 @@ static int ovs_flow_cmd_set(struct sk_bu
+ {
+ 	struct net *net = sock_net(skb->sk);
+ 	struct nlattr **a = info->attrs;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct sw_flow_key key;
+ 	struct sw_flow *flow;
+ 	struct sk_buff *reply = NULL;
+@@ -1315,7 +1315,7 @@ error:
+ static int ovs_flow_cmd_get(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct nlattr **a = info->attrs;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct net *net = sock_net(skb->sk);
+ 	struct sw_flow_key key;
+ 	struct sk_buff *reply;
+@@ -1374,7 +1374,7 @@ unlock:
+ static int ovs_flow_cmd_del(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct nlattr **a = info->attrs;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct net *net = sock_net(skb->sk);
+ 	struct sw_flow_key key;
+ 	struct sk_buff *reply;
+@@ -1642,7 +1642,7 @@ static void ovs_dp_reset_user_features(s
+ {
+ 	struct datapath *dp;
+ 
+-	dp = lookup_datapath(sock_net(skb->sk), genl_info_userhdr(info),
++	dp = lookup_datapath(sock_net(skb->sk), info->userhdr,
+ 			     info->attrs);
+ 	if (IS_ERR(dp))
+ 		return;
+@@ -1935,8 +1935,7 @@ static int ovs_dp_cmd_del(struct sk_buff
+ 		return -ENOMEM;
+ 
+ 	ovs_lock();
+-	dp = lookup_datapath(sock_net(skb->sk), genl_info_userhdr(info),
+-			     info->attrs);
++	dp = lookup_datapath(sock_net(skb->sk), info->userhdr, info->attrs);
+ 	err = PTR_ERR(dp);
+ 	if (IS_ERR(dp))
+ 		goto err_unlock_free;
+@@ -1969,8 +1968,7 @@ static int ovs_dp_cmd_set(struct sk_buff
+ 		return -ENOMEM;
+ 
+ 	ovs_lock();
+-	dp = lookup_datapath(sock_net(skb->sk), genl_info_userhdr(info),
+-			     info->attrs);
++	dp = lookup_datapath(sock_net(skb->sk), info->userhdr, info->attrs);
+ 	err = PTR_ERR(dp);
+ 	if (IS_ERR(dp))
+ 		goto err_unlock_free;
+@@ -2005,8 +2003,7 @@ static int ovs_dp_cmd_get(struct sk_buff
+ 		return -ENOMEM;
+ 
+ 	ovs_lock();
+-	dp = lookup_datapath(sock_net(skb->sk), genl_info_userhdr(info),
+-			     info->attrs);
++	dp = lookup_datapath(sock_net(skb->sk), info->userhdr, info->attrs);
+ 	if (IS_ERR(dp)) {
+ 		err = PTR_ERR(dp);
+ 		goto err_unlock_free;
+@@ -2249,7 +2246,7 @@ static void ovs_update_headroom(struct d
+ static int ovs_vport_cmd_new(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct nlattr **a = info->attrs;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct vport_parms parms;
+ 	struct sk_buff *reply;
+ 	struct vport *vport;
+@@ -2351,7 +2348,7 @@ static int ovs_vport_cmd_set(struct sk_b
+ 		return -ENOMEM;
+ 
+ 	ovs_lock();
+-	vport = lookup_vport(sock_net(skb->sk), genl_info_userhdr(info), a);
++	vport = lookup_vport(sock_net(skb->sk), info->userhdr, a);
+ 	err = PTR_ERR(vport);
+ 	if (IS_ERR(vport))
+ 		goto exit_unlock_free;
+@@ -2407,7 +2404,7 @@ static int ovs_vport_cmd_del(struct sk_b
+ 		return -ENOMEM;
+ 
+ 	ovs_lock();
+-	vport = lookup_vport(sock_net(skb->sk), genl_info_userhdr(info), a);
++	vport = lookup_vport(sock_net(skb->sk), info->userhdr, a);
+ 	err = PTR_ERR(vport);
+ 	if (IS_ERR(vport))
+ 		goto exit_unlock_free;
+@@ -2450,7 +2447,7 @@ exit_unlock_free:
+ static int ovs_vport_cmd_get(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct nlattr **a = info->attrs;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct sk_buff *reply;
+ 	struct vport *vport;
+ 	int err;
+--- a/net/openvswitch/meter.c
++++ b/net/openvswitch/meter.c
+@@ -211,7 +211,7 @@ ovs_meter_cmd_reply_start(struct genl_in
+ 			  struct ovs_header **ovs_reply_header)
+ {
+ 	struct sk_buff *skb;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 
+ 	skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_ATOMIC);
+ 	if (!skb)
+@@ -272,7 +272,7 @@ error:
+ 
+ static int ovs_meter_cmd_features(struct sk_buff *skb, struct genl_info *info)
+ {
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct ovs_header *ovs_reply_header;
+ 	struct nlattr *nla, *band_nla;
+ 	struct sk_buff *reply;
+@@ -409,7 +409,7 @@ static int ovs_meter_cmd_set(struct sk_b
+ 	struct dp_meter *meter, *old_meter;
+ 	struct sk_buff *reply;
+ 	struct ovs_header *ovs_reply_header;
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct dp_meter_table *meter_tbl;
+ 	struct datapath *dp;
+ 	int err;
+@@ -482,7 +482,7 @@ exit_free_meter:
+ 
+ static int ovs_meter_cmd_get(struct sk_buff *skb, struct genl_info *info)
+ {
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct ovs_header *ovs_reply_header;
+ 	struct nlattr **a = info->attrs;
+ 	struct dp_meter *meter;
+@@ -535,7 +535,7 @@ exit_unlock:
+ 
+ static int ovs_meter_cmd_del(struct sk_buff *skb, struct genl_info *info)
+ {
+-	struct ovs_header *ovs_header = genl_info_userhdr(info);
++	struct ovs_header *ovs_header = info->userhdr;
+ 	struct ovs_header *ovs_reply_header;
+ 	struct nlattr **a = info->attrs;
+ 	struct dp_meter *old_meter;
+--- a/net/tipc/netlink_compat.c
++++ b/net/tipc/netlink_compat.c
+@@ -1295,7 +1295,7 @@ static int tipc_nl_compat_recv(struct sk
+ 	struct tipc_nl_compat_msg msg;
+ 	struct nlmsghdr *req_nlh;
+ 	struct nlmsghdr *rep_nlh;
+-	struct tipc_genlmsghdr *req_userhdr = genl_info_userhdr(info);
++	struct tipc_genlmsghdr *req_userhdr = info->userhdr;
+ 
+ 	memset(&msg, 0, sizeof(msg));
+ 
diff --git a/target/linux/generic/backport-6.6/011-kbuild-export-SUBARCH.patch b/target/linux/generic/backport-6.6/011-kbuild-export-SUBARCH.patch
new file mode 100644
index 00000000000000..ea7a25d8a0c284
--- /dev/null
+++ b/target/linux/generic/backport-6.6/011-kbuild-export-SUBARCH.patch
@@ -0,0 +1,21 @@
+From 173019b66dcc9d68ad9333aa744dad1e369b5aa8 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 9 Jul 2017 00:26:53 +0200
+Subject: [PATCH 34/34] kernel: add compile fix for linux 4.9 on x86
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ Makefile | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/Makefile
++++ b/Makefile
+@@ -599,7 +599,7 @@ endif
+ # Allows the usage of unstable features in stable compilers.
+ export RUSTC_BOOTSTRAP := 1
+ 
+-export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC HOSTPKG_CONFIG
++export ARCH SRCARCH SUBARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC HOSTPKG_CONFIG
+ export RUSTC RUSTDOC RUSTFMT RUSTC_OR_CLIPPY_QUIET RUSTC_OR_CLIPPY BINDGEN CARGO
+ export HOSTRUSTC KBUILD_HOSTRUSTFLAGS
+ export CPP AR NM STRIP OBJCOPY OBJDUMP READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL
diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6
new file mode 100644
index 00000000000000..3113beb8c2e977
--- /dev/null
+++ b/target/linux/generic/config-6.6
@@ -0,0 +1,7863 @@
+# CONFIG_104_QUAD_8 is not set
+CONFIG_32BIT=y
+CONFIG_64BIT_TIME=y
+# CONFIG_6LOWPAN is not set
+# CONFIG_6LOWPAN_DEBUGFS is not set
+# CONFIG_6PACK is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_9P_FS is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_AB8500_CORE is not set
+# CONFIG_ABP060MG is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_ACENIC is not set
+# CONFIG_ACERHDF is not set
+# CONFIG_ACER_WIRELESS is not set
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_ACPI_ALS is not set
+# CONFIG_ACPI_APEI is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_CONFIGFS is not set
+# CONFIG_ACPI_CUSTOM_METHOD is not set
+# CONFIG_ACPI_EXTLOG is not set
+# CONFIG_ACPI_HED is not set
+# CONFIG_ACPI_NFIT is not set
+# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
+# CONFIG_ACPI_TABLE_UPGRADE is not set
+# CONFIG_ACPI_VIDEO is not set
+# CONFIG_AD2S1200 is not set
+# CONFIG_AD2S1210 is not set
+# CONFIG_AD2S90 is not set
+# CONFIG_AD3552R is not set
+# CONFIG_AD4130 is not set
+# CONFIG_AD5064 is not set
+# CONFIG_AD5110 is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_AD5272 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5380 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5593R is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5686 is not set
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5696_I2C is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5758 is not set
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5766 is not set
+# CONFIG_AD5770R is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD5933 is not set
+# CONFIG_AD7091R5 is not set
+# CONFIG_AD7124 is not set
+# CONFIG_AD7150 is not set
+# CONFIG_AD7152 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7266 is not set
+# CONFIG_AD7280 is not set
+# CONFIG_AD7291 is not set
+# CONFIG_AD7292 is not set
+# CONFIG_AD7293 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD74115 is not set
+# CONFIG_AD74413R is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606 is not set
+# CONFIG_AD7606_IFACE_PARALLEL is not set
+# CONFIG_AD7606_IFACE_SPI is not set
+# CONFIG_AD7746 is not set
+# CONFIG_AD7766 is not set
+# CONFIG_AD7768_1 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7816 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7949 is not set
+# CONFIG_AD799X is not set
+# CONFIG_AD8366 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_AD9467 is not set
+# CONFIG_AD9523 is not set
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# CONFIG_ADA4250 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_ADE7854 is not set
+# CONFIG_ADF4350 is not set
+# CONFIG_ADF4371 is not set
+# CONFIG_ADF4377 is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADIN1100_PHY is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_ADI_AXI_ADC is not set
+# CONFIG_ADJD_S311 is not set
+# CONFIG_ADM6996_PHY is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADMV1014 is not set
+# CONFIG_ADMV4420 is not set
+# CONFIG_ADMV8818 is not set
+# CONFIG_ADRF6780 is not set
+# CONFIG_ADT7316 is not set
+# CONFIG_ADUX1020 is not set
+CONFIG_ADVISE_SYSCALLS=y
+# CONFIG_ADV_SWBUTTON is not set
+# CONFIG_ADXL313_I2C is not set
+# CONFIG_ADXL313_SPI is not set
+# CONFIG_ADXL345_I2C is not set
+# CONFIG_ADXL345_SPI is not set
+# CONFIG_ADXL355_I2C is not set
+# CONFIG_ADXL355_SPI is not set
+# CONFIG_ADXL367_I2C is not set
+# CONFIG_ADXL367_SPI is not set
+# CONFIG_ADXL372_I2C is not set
+# CONFIG_ADXL372_SPI is not set
+# CONFIG_ADXRS290 is not set
+# CONFIG_ADXRS450 is not set
+CONFIG_AEABI=y
+# CONFIG_AFE4403 is not set
+# CONFIG_AFE4404 is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_AFS_DEBUG_CURSOR is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_RXRPC_INJECT_LOSS is not set
+# CONFIG_AF_RXRPC_IPV6 is not set
+# CONFIG_AF_UNIX_OOB is not set
+# CONFIG_AGP is not set
+# CONFIG_AHCI_CEVA is not set
+# CONFIG_AHCI_DWC is not set
+# CONFIG_AHCI_IMX is not set
+# CONFIG_AHCI_MVEBU is not set
+# CONFIG_AHCI_QORIQ is not set
+CONFIG_AIO=y
+# CONFIG_AIRO is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_AIX_PARTITION is not set
+# CONFIG_AK09911 is not set
+# CONFIG_AK8974 is not set
+# CONFIG_AK8975 is not set
+# CONFIG_AL3010 is not set
+# CONFIG_AL3320A is not set
+# CONFIG_ALIM7101_WDT is not set
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_ALX is not set
+# CONFIG_AL_FIC is not set
+# CONFIG_AM2315 is not set
+# CONFIG_AM335X_PHY_USB is not set
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_AMD_MEM_ENCRYPT is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_AMD_XGBE is not set
+# CONFIG_AMD_XGBE_HAVE_ECC is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_AMILO_RFKILL is not set
+# CONFIG_AMT is not set
+# CONFIG_ANDROID is not set
+# CONFIG_ANDROID_BINDER_IPC is not set
+CONFIG_ANON_INODES=y
+# CONFIG_ANON_VMA_NAME is not set
+# CONFIG_APDS9300 is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_APDS9960 is not set
+# CONFIG_APM8018X is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_APPLE_AIC is not set
+# CONFIG_APPLE_GMUX is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_APPLE_PROPERTIES is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_AQTION is not set
+# CONFIG_AQUANTIA_PHY is not set
+# CONFIG_AR5523 is not set
+# CONFIG_AR7 is not set
+# CONFIG_AR8216_PHY is not set
+# CONFIG_AR8216_PHY_LEDS is not set
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_AGILEX is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_APPLE is not set
+# CONFIG_ARCH_ARTPEC is not set
+# CONFIG_ARCH_ASPEED is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_AXXIA is not set
+# CONFIG_ARCH_BCM is not set
+# CONFIG_ARCH_BCM2835 is not set
+# CONFIG_ARCH_BCM4908 is not set
+# CONFIG_ARCH_BCMBCA is not set
+# CONFIG_ARCH_BCM_21664 is not set
+# CONFIG_ARCH_BCM_23550 is not set
+# CONFIG_ARCH_BCM_281XX is not set
+# CONFIG_ARCH_BCM_5301X is not set
+# CONFIG_ARCH_BCM_53573 is not set
+# CONFIG_ARCH_BCM_63XX is not set
+# CONFIG_ARCH_BCM_CYGNUS is not set
+# CONFIG_ARCH_BCM_IPROC is not set
+# CONFIG_ARCH_BCM_NSP is not set
+# CONFIG_ARCH_BERLIN is not set
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+# CONFIG_ARCH_BITMAIN is not set
+# CONFIG_ARCH_BRCMSTB is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_DIGICOLOR is not set
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_EXYNOS is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_HI3xxx is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_INTEL_SOCFPGA is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_KEEMBAY is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_LAYERSCAPE is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MA35 is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE is not set
+# CONFIG_ARCH_MILBEAUT is not set
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSTARV7 is not set
+# CONFIG_ARCH_MULTIPLATFORM is not set
+# CONFIG_ARCH_MULTI_V6 is not set
+# CONFIG_ARCH_MULTI_V7 is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_NPCM is not set
+# CONFIG_ARCH_NSPIRE is not set
+# CONFIG_ARCH_NXP is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP2PLUS is not set
+# CONFIG_ARCH_OMAP3 is not set
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_OXNAS is not set
+# CONFIG_ARCH_PICOXCELL is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_RANDOM is not set
+# CONFIG_ARCH_RDA is not set
+# CONFIG_ARCH_REALTEK is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_RENESAS is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_S32 is not set
+# CONFIG_ARCH_S3C24XX is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_SIRF is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_ARCH_SPARX5 is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_STI is not set
+# CONFIG_ARCH_STM32 is not set
+# CONFIG_ARCH_STRATIX10 is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TANGO is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VIRT is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_VULCAN is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_WANTS_NO_INSTR is not set
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+# CONFIG_ARCH_WM8505 is not set
+# CONFIG_ARCH_WM8750 is not set
+# CONFIG_ARCH_WM8850 is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZX is not set
+# CONFIG_ARCH_ZYNQ is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# CONFIG_ARCNET is not set
+# CONFIG_ARC_EMAC is not set
+# CONFIG_ARC_IRQ_NO_AUTOSAVE is not set
+# CONFIG_ARM64_16K_PAGES is not set
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_AMU_EXTN is not set
+# CONFIG_ARM64_BTI is not set
+# CONFIG_ARM64_CRYPTO is not set
+# CONFIG_ARM64_E0PD is not set
+# CONFIG_ARM64_EPAN is not set
+# CONFIG_ARM64_ERRATUM_1024718 is not set
+# CONFIG_ARM64_ERRATUM_1165522 is not set
+# CONFIG_ARM64_ERRATUM_1286807 is not set
+# CONFIG_ARM64_ERRATUM_1319367 is not set
+# CONFIG_ARM64_ERRATUM_1418040 is not set
+# CONFIG_ARM64_ERRATUM_1463225 is not set
+# CONFIG_ARM64_ERRATUM_1508412 is not set
+# CONFIG_ARM64_ERRATUM_1530923 is not set
+# CONFIG_ARM64_ERRATUM_1542419 is not set
+# CONFIG_ARM64_ERRATUM_1742098 is not set
+# CONFIG_ARM64_ERRATUM_2051678 is not set
+# CONFIG_ARM64_ERRATUM_2054223 is not set
+# CONFIG_ARM64_ERRATUM_2067961 is not set
+# CONFIG_ARM64_ERRATUM_2077057 is not set
+# CONFIG_ARM64_ERRATUM_2441007 is not set
+# CONFIG_ARM64_ERRATUM_2441009 is not set
+# CONFIG_ARM64_ERRATUM_2645198 is not set
+# CONFIG_ARM64_ERRATUM_2658417 is not set
+# CONFIG_ARM64_ERRATUM_2966298 is not set
+# CONFIG_ARM64_ERRATUM_819472 is not set
+# CONFIG_ARM64_ERRATUM_824069 is not set
+# CONFIG_ARM64_ERRATUM_826319 is not set
+# CONFIG_ARM64_ERRATUM_827319 is not set
+# CONFIG_ARM64_ERRATUM_832075 is not set
+# CONFIG_ARM64_ERRATUM_834220 is not set
+# CONFIG_ARM64_ERRATUM_843419 is not set
+# CONFIG_ARM64_ERRATUM_845719 is not set
+# CONFIG_ARM64_ERRATUM_858921 is not set
+# CONFIG_ARM64_HW_AFDBM is not set
+# CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419 is not set
+# CONFIG_ARM64_LSE_ATOMICS is not set
+# CONFIG_ARM64_MODULE_PLTS is not set
+# CONFIG_ARM64_MTE is not set
+# CONFIG_ARM64_PAN is not set
+# CONFIG_ARM64_PMEM is not set
+# CONFIG_ARM64_PSEUDO_NMI is not set
+# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
+# CONFIG_ARM64_PTR_AUTH is not set
+# CONFIG_ARM64_PTR_AUTH_KERNEL is not set
+# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
+# CONFIG_ARM64_RAS_EXTN is not set
+# CONFIG_ARM64_RELOC_TEST is not set
+# CONFIG_ARM64_SVE is not set
+# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
+# CONFIG_ARM64_TLB_RANGE is not set
+# CONFIG_ARM64_UAO is not set
+# CONFIG_ARM64_USE_LSE_ATOMICS is not set
+CONFIG_ARM64_VA_BITS_39=y
+# CONFIG_ARM64_VA_BITS_48 is not set
+# CONFIG_ARM64_VHE is not set
+# CONFIG_ARM_APPENDED_DTB is not set
+# CONFIG_ARM_ARCH_TIMER is not set
+# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
+# CONFIG_ARM_CCI is not set
+# CONFIG_ARM_CCI400_PMU is not set
+# CONFIG_ARM_CCI5xx_PMU is not set
+# CONFIG_ARM_CCI_PMU is not set
+# CONFIG_ARM_CCN is not set
+# CONFIG_ARM_CMN is not set
+# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
+# CONFIG_ARM_CPUIDLE is not set
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_ARM_CRYPTO is not set
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+# CONFIG_ARM_DSU_PMU is not set
+# CONFIG_ARM_ERRATA_326103 is not set
+# CONFIG_ARM_ERRATA_364296 is not set
+# CONFIG_ARM_ERRATA_411920 is not set
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_643719 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_742230 is not set
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_ARM_ERRATA_773022 is not set
+# CONFIG_ARM_ERRATA_775420 is not set
+# CONFIG_ARM_ERRATA_798181 is not set
+# CONFIG_ARM_ERRATA_814220 is not set
+# CONFIG_ARM_ERRATA_818325 is not set
+# CONFIG_ARM_ERRATA_821420 is not set
+# CONFIG_ARM_ERRATA_825619 is not set
+# CONFIG_ARM_ERRATA_852421 is not set
+# CONFIG_ARM_ERRATA_852423 is not set
+# CONFIG_ARM_ERRATA_857271 is not set
+# CONFIG_ARM_ERRATA_857272 is not set
+# CONFIG_ARM_FFA_TRANSPORT is not set
+CONFIG_ARM_GIC_MAX_NR=1
+# CONFIG_ARM_GT_INITIAL_PRESCALER_VAL is not set
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+# CONFIG_ARM_KPROBES_TEST is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARM_MHU is not set
+# CONFIG_ARM_MHU_V2 is not set
+# CONFIG_ARM_MODULE_PLTS is not set
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+# CONFIG_ARM_PSCI is not set
+# CONFIG_ARM_PSCI_CHECKER is not set
+# CONFIG_ARM_PSCI_CPUIDLE is not set
+# CONFIG_ARM_PTDUMP_DEBUGFS is not set
+# CONFIG_ARM_SBSA_WATCHDOG is not set
+# CONFIG_ARM_SCMI_AVOID_FASTCHANNELS is not set
+# CONFIG_ARM_SCMI_POWER_CONTROL is not set
+# CONFIG_ARM_SCMI_PROTOCOL is not set
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+# CONFIG_ARM_SCPI_PROTOCOL is not set
+# CONFIG_ARM_SDE_INTERFACE is not set
+# CONFIG_ARM_SMCCC_SOC_ID is not set
+# CONFIG_ARM_SMC_WATCHDOG is not set
+# CONFIG_ARM_SMMU_V3_PMU is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+# CONFIG_ARM_SPE_PMU is not set
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_ARM_TIMER_SP804 is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_ARM_VIRT_EXT is not set
+# CONFIG_AS3935 is not set
+# CONFIG_AS73211 is not set
+# CONFIG_ASM9260_TIMER is not set
+# CONFIG_ASN1 is not set
+# CONFIG_ASUS_LAPTOP is not set
+# CONFIG_ASUS_WIRELESS is not set
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+# CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE is not set
+# CONFIG_ASYNC_RAID6_TEST is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_AT803X_PHY is not set
+# CONFIG_AT91_SAMA5D2_ADC is not set
+# CONFIG_ATA is not set
+# CONFIG_ATAGS is not set
+CONFIG_ATAGS_PROC=y
+# CONFIG_ATALK is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_ATA_ACPI is not set
+CONFIG_ATA_BMDMA=y
+# CONFIG_ATA_FORCE is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_ATA_LEDS is not set
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_ATA_SFF=y
+# CONFIG_ATA_VERBOSE_ERROR is not set
+# CONFIG_ATH10K is not set
+# CONFIG_ATH25 is not set
+# CONFIG_ATH5K is not set
+# CONFIG_ATH6KL is not set
+# CONFIG_ATH79 is not set
+# CONFIG_ATH9K is not set
+# CONFIG_ATH9K_HTC is not set
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL2 is not set
+# CONFIG_ATLAS_EZO_SENSOR is not set
+# CONFIG_ATLAS_PH_SENSOR is not set
+# CONFIG_ATM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ATM_AMBASSADOR is not set
+# CONFIG_ATM_BR2684 is not set
+CONFIG_ATM_BR2684_IPFILTER=y
+# CONFIG_ATM_CLIP is not set
+CONFIG_ATM_CLIP_NO_ICMP=y
+# CONFIG_ATM_DRIVERS is not set
+# CONFIG_ATM_DUMMY is not set
+# CONFIG_ATM_ENI is not set
+# CONFIG_ATM_FIRESTREAM is not set
+# CONFIG_ATM_FORE200E is not set
+# CONFIG_ATM_HE is not set
+# CONFIG_ATM_HORIZON is not set
+# CONFIG_ATM_IA is not set
+# CONFIG_ATM_IDT77252 is not set
+# CONFIG_ATM_LANAI is not set
+# CONFIG_ATM_LANE is not set
+# CONFIG_ATM_MPOA is not set
+# CONFIG_ATM_NICSTAR is not set
+# CONFIG_ATM_SOLOS is not set
+# CONFIG_ATM_TCP is not set
+# CONFIG_ATM_ZATM is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_ATP is not set
+# CONFIG_AUDIT is not set
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+# CONFIG_AURORA_NB8800 is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTO_ZRELADDR is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_AX25 is not set
+# CONFIG_AX25_DAMA_SLAVE is not set
+# CONFIG_AX88796 is not set
+# CONFIG_AX88796B_PHY is not set
+# CONFIG_AXP20X_ADC is not set
+# CONFIG_AXP20X_POWER is not set
+# CONFIG_AXP288_ADC is not set
+# CONFIG_AXP288_FUEL_GAUGE is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_B44 is not set
+# CONFIG_B53 is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_APPLE is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_KTD253 is not set
+# CONFIG_BACKLIGHT_KTZ8866 is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_BACKLIGHT_LED is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_PANDORA is not set
+# CONFIG_BACKLIGHT_PM8941_WLED is not set
+# CONFIG_BACKLIGHT_PWM is not set
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_RPI is not set
+# CONFIG_BACKLIGHT_SAHARA is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_BAREUDP is not set
+CONFIG_BASE_FULL=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_BQ27XXX_HDQ is not set
+# CONFIG_BATTERY_CW2015 is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_LEGO_EV3 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_BATTERY_MAX1721X is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_BATTERY_SAMSUNG_SDI is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_UG3105 is not set
+# CONFIG_BAYCOM_EPP is not set
+# CONFIG_BAYCOM_PAR is not set
+# CONFIG_BAYCOM_SER_FDX is not set
+# CONFIG_BAYCOM_SER_HDX is not set
+# CONFIG_BCACHE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM54140_PHY is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_BCM7038_WDT is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_BCMA is not set
+# CONFIG_BCMA_DRIVER_GPIO is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMGENET is not set
+# CONFIG_BCM_IPROC_ADC is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_BCM_SBA_RAID is not set
+# CONFIG_BCM_VK is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BE2NET is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_BGMAC is not set
+# CONFIG_BH1750 is not set
+# CONFIG_BH1780 is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_BIG_LITTLE is not set
+# CONFIG_BINARY_PRINTF is not set
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_ELF_FDPIC is not set
+# CONFIG_BINFMT_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+# CONFIG_BLK_DEBUG_FS is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_BLK_DEV_4DRIVES is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI14XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_ATIIXP is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_BSG_COMMON is not set
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_CS5535 is not set
+# CONFIG_BLK_DEV_CS5536 is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_DTC2278 is not set
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_HT6560B is not set
+# CONFIG_BLK_DEV_IDEACPI is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_BLK_DEV_IDEPNP is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDE_AU1XXX is not set
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_PMEM is not set
+# CONFIG_BLK_DEV_QD65XX is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SKD is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_UBLK is not set
+# CONFIG_BLK_DEV_UMC8672 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+# CONFIG_BLK_SED_OPAL is not set
+# CONFIG_BLK_USE_PIN_USER_PAGES_FOR_DIO is not set
+# CONFIG_BLK_WBT is not set
+CONFIG_BLOCK=y
+# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
+# CONFIG_BMA180 is not set
+# CONFIG_BMA220 is not set
+# CONFIG_BMA400 is not set
+# CONFIG_BMC150_ACCEL is not set
+# CONFIG_BMC150_MAGN is not set
+# CONFIG_BMC150_MAGN_I2C is not set
+# CONFIG_BMC150_MAGN_SPI is not set
+# CONFIG_BME680 is not set
+# CONFIG_BMG160 is not set
+# CONFIG_BMI088_ACCEL is not set
+# CONFIG_BMI160_I2C is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_BMIPS_GENERIC is not set
+# CONFIG_BMP280 is not set
+# CONFIG_BNA is not set
+# CONFIG_BNX2 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_BNX2X_SRIOV is not set
+# CONFIG_BNXT is not set
+# CONFIG_BONDING is not set
+# CONFIG_BOOKE_WDT is not set
+CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+# CONFIG_BOOTTIME_TRACING is not set
+# CONFIG_BOOT_CONFIG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+CONFIG_BOOT_RAW=y
+# CONFIG_BOSCH_BNO055_I2C is not set
+# CONFIG_BOSCH_BNO055_SERIAL is not set
+# CONFIG_BOUNCE is not set
+CONFIG_BPF=y
+# CONFIG_BPFILTER is not set
+CONFIG_BPF_JIT=y
+# CONFIG_BPF_JIT_ALWAYS_ON is not set
+CONFIG_BPF_JIT_DEFAULT_ON=y
+# CONFIG_BPF_PRELOAD is not set
+# CONFIG_BPF_STREAM_PARSER is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
+# CONFIG_BPQETHER is not set
+CONFIG_BQL=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_BRCMFMAC is not set
+# CONFIG_BRCMSMAC is not set
+# CONFIG_BRCMSTB_GISB_ARB is not set
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_CFM is not set
+# CONFIG_BRIDGE_EBT_802_3 is not set
+# CONFIG_BRIDGE_EBT_AMONG is not set
+# CONFIG_BRIDGE_EBT_ARP is not set
+# CONFIG_BRIDGE_EBT_ARPREPLY is not set
+# CONFIG_BRIDGE_EBT_BROUTE is not set
+# CONFIG_BRIDGE_EBT_DNAT is not set
+# CONFIG_BRIDGE_EBT_IP is not set
+# CONFIG_BRIDGE_EBT_IP6 is not set
+# CONFIG_BRIDGE_EBT_LIMIT is not set
+# CONFIG_BRIDGE_EBT_LOG is not set
+# CONFIG_BRIDGE_EBT_MARK is not set
+# CONFIG_BRIDGE_EBT_MARK_T is not set
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+# CONFIG_BRIDGE_EBT_PKTTYPE is not set
+# CONFIG_BRIDGE_EBT_REDIRECT is not set
+# CONFIG_BRIDGE_EBT_SNAT is not set
+# CONFIG_BRIDGE_EBT_STP is not set
+# CONFIG_BRIDGE_EBT_T_FILTER is not set
+# CONFIG_BRIDGE_EBT_T_NAT is not set
+# CONFIG_BRIDGE_EBT_VLAN is not set
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_BRIDGE_MRP is not set
+# CONFIG_BRIDGE_NETFILTER is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+CONFIG_BRIDGE_VLAN_FILTERING=y
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_BROKEN_ON_SMP=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_BT is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BT_AOSPEXT is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_BT_BNEP is not set
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+# CONFIG_BT_BREDR is not set
+# CONFIG_BT_CMTP is not set
+# CONFIG_BT_FEATURE_DEBUG is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBCM4377 is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
+# CONFIG_BT_HCIBTUSB_MTK is not set
+# CONFIG_BT_HCIBTUSB_POLL_SYNC is not set
+# CONFIG_BT_HCIBTUSB_RTL is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIUART_3WIRE is not set
+# CONFIG_BT_HCIUART_AG6XX is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIUART_MRVL is not set
+# CONFIG_BT_HCIUART_QCA is not set
+# CONFIG_BT_HCIUART_RTL is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_HIDP is not set
+# CONFIG_BT_HS is not set
+# CONFIG_BT_LE is not set
+# CONFIG_BT_LEDS is not set
+# CONFIG_BT_LE_L2CAP_ECRED is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_MSFTEXT is not set
+# CONFIG_BT_MTKSDIO is not set
+# CONFIG_BT_MTKUART is not set
+# CONFIG_BT_NXPUART is not set
+# CONFIG_BT_RFCOMM is not set
+CONFIG_BT_RFCOMM_TTY=y
+# CONFIG_BT_SELFTEST is not set
+CONFIG_BUG=y
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+# CONFIG_BUILD_BIN2C is not set
+CONFIG_BUILD_SALT=""
+# CONFIG_C2PORT is not set
+# CONFIG_CACHESTAT_SYSCALL is not set
+CONFIG_CACHE_L2X0_PMU=y
+# CONFIG_CADENCE_WATCHDOG is not set
+# CONFIG_CAIF is not set
+# CONFIG_CAN is not set
+# CONFIG_CAN_BCM is not set
+# CONFIG_CAN_CAN327 is not set
+# CONFIG_CAN_CTUCANFD_PCI is not set
+# CONFIG_CAN_CTUCANFD_PLATFORM is not set
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# CONFIG_CAN_DEV is not set
+# CONFIG_CAN_ESD_USB is not set
+# CONFIG_CAN_ETAS_ES58X is not set
+# CONFIG_CAN_GS_USB is not set
+# CONFIG_CAN_GW is not set
+# CONFIG_CAN_HI311X is not set
+# CONFIG_CAN_IFI_CANFD is not set
+# CONFIG_CAN_ISOTP is not set
+# CONFIG_CAN_J1939 is not set
+# CONFIG_CAN_KVASER_PCIEFD is not set
+# CONFIG_CAN_MCBA_USB is not set
+# CONFIG_CAN_MCP251XFD is not set
+# CONFIG_CAN_M_CAN is not set
+# CONFIG_CAN_NETLINK is not set
+# CONFIG_CAN_PEAK_PCIEFD is not set
+# CONFIG_CAN_RAW is not set
+# CONFIG_CAN_RCAR is not set
+# CONFIG_CAN_RCAR_CANFD is not set
+# CONFIG_CAN_SLCAN is not set
+# CONFIG_CAN_SUN4I is not set
+# CONFIG_CAN_UCAN is not set
+# CONFIG_CAN_VCAN is not set
+# CONFIG_CAN_VXCAN is not set
+# CONFIG_CAPI_AVM is not set
+# CONFIG_CAPI_EICON is not set
+# CONFIG_CAPI_TRACE is not set
+CONFIG_CARDBUS=y
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_CARL9170 is not set
+# CONFIG_CASSINI is not set
+# CONFIG_CAVIUM_CPT is not set
+# CONFIG_CAVIUM_ERRATUM_22375 is not set
+# CONFIG_CAVIUM_ERRATUM_23144 is not set
+# CONFIG_CAVIUM_ERRATUM_23154 is not set
+# CONFIG_CAVIUM_ERRATUM_27456 is not set
+# CONFIG_CAVIUM_ERRATUM_30115 is not set
+# CONFIG_CAVIUM_OCTEON_SOC is not set
+# CONFIG_CAVIUM_PTP is not set
+# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_CC10001_ADC is not set
+# CONFIG_CCS811 is not set
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_CDX_BUS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_CFG80211 is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_CGROUP_FAVOR_DYNMODS is not set
+# CONFIG_CGROUP_MISC is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_CHARGER_BD99954 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24257 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_BQ2515X is not set
+# CONFIG_CHARGER_BQ256XX is not set
+# CONFIG_CHARGER_BQ25890 is not set
+# CONFIG_CHARGER_BQ25980 is not set
+# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_LT3651 is not set
+# CONFIG_CHARGER_LTC3651 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_MAX77976 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_RK817 is not set
+# CONFIG_CHARGER_RT9455 is not set
+# CONFIG_CHARGER_RT9467 is not set
+# CONFIG_CHARGER_RT9471 is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_CHARGER_TWL4030 is not set
+# CONFIG_CHARGER_UCS1002 is not set
+# CONFIG_CHASH_SELFTEST is not set
+# CONFIG_CHASH_STATS is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CIFS is not set
+# CONFIG_CIFS_ACL is not set
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+# CONFIG_CIFS_DEBUG is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_FSCACHE is not set
+# CONFIG_CIFS_NFSD_EXPORT is not set
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_SMB2 is not set
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_STATS2 is not set
+# CONFIG_CIFS_SWN_UPCALL is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+CONFIG_CIFS_XATTR=y
+# CONFIG_CIO_DAC is not set
+# CONFIG_CLEANCACHE is not set
+# CONFIG_CLKSRC_VERSATILE is not set
+# CONFIG_CLK_HSDK is not set
+# CONFIG_CLK_ICST is not set
+# CONFIG_CLK_QORIQ is not set
+# CONFIG_CLK_SP810 is not set
+# CONFIG_CLOCK_THERMAL is not set
+CONFIG_CLS_U32_MARK=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CM32181 is not set
+# CONFIG_CM3232 is not set
+# CONFIG_CM3323 is not set
+# CONFIG_CM3605 is not set
+# CONFIG_CM36651 is not set
+# CONFIG_CMA is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_CMDLINE_FROM_BOOTLOADER is not set
+# CONFIG_CMDLINE_PARTITION is not set
+# CONFIG_CNIC is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_COMEDI is not set
+# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CDCE925 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+# CONFIG_COMMON_CLK_IPROC is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
+# CONFIG_COMMON_CLK_MAX9485 is not set
+# CONFIG_COMMON_CLK_MT6765 is not set
+# CONFIG_COMMON_CLK_MT8167 is not set
+# CONFIG_COMMON_CLK_MT8167_AUDSYS is not set
+# CONFIG_COMMON_CLK_MT8167_IMGSYS is not set
+# CONFIG_COMMON_CLK_MT8167_MFGCFG is not set
+# CONFIG_COMMON_CLK_MT8167_MMSYS is not set
+# CONFIG_COMMON_CLK_MT8167_VDECSYS is not set
+# CONFIG_COMMON_CLK_NXP is not set
+# CONFIG_COMMON_CLK_PIC32 is not set
+# CONFIG_COMMON_CLK_PWM is not set
+# CONFIG_COMMON_CLK_PXA is not set
+# CONFIG_COMMON_CLK_QCOM is not set
+# CONFIG_COMMON_CLK_RK808 is not set
+# CONFIG_COMMON_CLK_ROCKCHIP is not set
+# CONFIG_COMMON_CLK_SI514 is not set
+# CONFIG_COMMON_CLK_SI521XX is not set
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_VC5 is not set
+# CONFIG_COMMON_CLK_VC7 is not set
+# CONFIG_COMMON_CLK_XGENE is not set
+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
+CONFIG_COMPACTION=y
+# CONFIG_COMPAL_LAPTOP is not set
+# CONFIG_COMPAT is not set
+# CONFIG_COMPAT_32BIT_TIME is not set
+# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_CONFIG_KVM_AMD_SEV is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_CONSTRUCTORS=y
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_COPS is not set
+# CONFIG_CORDIC is not set
+# CONFIG_COREDUMP is not set
+# CONFIG_CORESIGHT is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_COUNTER is not set
+# CONFIG_CPA_DEBUG is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_THERMAL is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
+# CONFIG_CPU_IDLE is not set
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+# CONFIG_CPU_IDLE_GOV_MENU is not set
+# CONFIG_CPU_IDLE_GOV_TEO is not set
+# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
+# CONFIG_CPU_ISOLATION is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_NO_EFFICIENT_FFS is not set
+CONFIG_CPU_SW_DOMAIN_PAN=y
+# CONFIG_CPU_THERMAL is not set
+# CONFIG_CRAMFS is not set
+CONFIG_CRAMFS_BLOCKDEV=y
+# CONFIG_CRAMFS_MTD is not set
+CONFIG_CRASHLOG=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC32_SARWATE=y
+# CONFIG_CRC32_SELFTEST is not set
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SLICEBY8 is not set
+# CONFIG_CRC4 is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC64_ROCKSOFT is not set
+# CONFIG_CRC7 is not set
+# CONFIG_CRC8 is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CROSS_COMPILE=""
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_842 is not set
+CONFIG_CRYPTO_ACOMP2=y
+# CONFIG_CRYPTO_ADIANTUM is not set
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_AEGIS128L is not set
+# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set
+# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set
+# CONFIG_CRYPTO_AEGIS256 is not set
+# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_586 is not set
+# CONFIG_CRYPTO_AES_ARM is not set
+# CONFIG_CRYPTO_AES_ARM64 is not set
+# CONFIG_CRYPTO_AES_ARM64_BS is not set
+# CONFIG_CRYPTO_AES_ARM64_CE is not set
+# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set
+# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
+# CONFIG_CRYPTO_AES_ARM_BS is not set
+# CONFIG_CRYPTO_AES_ARM_CE is not set
+# CONFIG_CRYPTO_AES_NI_INTEL is not set
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S is not set
+# CONFIG_CRYPTO_ARIA is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_BLAKE2B is not set
+CONFIG_CRYPTO_BLAKE2B_NEON=y
+# CONFIG_CRYPTO_BLAKE2S is not set
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+# CONFIG_CRYPTO_BLAKE2S_X86 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_CBC is not set
+CONFIG_CRYPTO_CCM=y
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_CHACHA20_NEON is not set
+# CONFIG_CRYPTO_CHACHA20_X86_64 is not set
+# CONFIG_CRYPTO_CHACHA_MIPS is not set
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CRC32C_INTEL is not set
+# CONFIG_CRYPTO_CRC32_ARM_CE is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+# CONFIG_CRYPTO_CURVE25519_NEON is not set
+# CONFIG_CRYPTO_CURVE25519_X86 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
+# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
+# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set
+# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
+# CONFIG_CRYPTO_DEV_CCP is not set
+# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC is not set
+# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
+# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
+# CONFIG_CRYPTO_DEV_MARVELL_CESA is not set
+# CONFIG_CRYPTO_DEV_MV_CESA is not set
+# CONFIG_CRYPTO_DEV_MXC_SCC is not set
+# CONFIG_CRYPTO_DEV_MXS_DCP is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C62X is not set
+# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
+# CONFIG_CRYPTO_DEV_QCE is not set
+# CONFIG_CRYPTO_DEV_S5P is not set
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DEV_SAHARA is not set
+# CONFIG_CRYPTO_DEV_SP_PSP is not set
+# CONFIG_CRYPTO_DEV_TALITOS is not set
+# CONFIG_CRYPTO_DEV_VIRTIO is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_DRBG_CTR is not set
+# CONFIG_CRYPTO_DRBG_HASH is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECDSA is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_ESSIV is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_GHASH_ARM64_CE is not set
+# CONFIG_CRYPTO_GHASH_ARM_CE is not set
+# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+# CONFIG_CRYPTO_HCTR2 is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=y
+# CONFIG_CRYPTO_LIB_BLAKE2S is not set
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+# CONFIG_CRYPTO_LIB_CHACHA is not set
+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_LIB_CURVE25519 is not set
+# CONFIG_CRYPTO_LIB_POLY1305 is not set
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+# CONFIG_CRYPTO_LIB_SHA256 is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MCRYPTD is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_MORUS1280 is not set
+# CONFIG_CRYPTO_MORUS1280_AVX2 is not set
+# CONFIG_CRYPTO_MORUS1280_SSE2 is not set
+# CONFIG_CRYPTO_MORUS640 is not set
+# CONFIG_CRYPTO_MORUS640_SSE2 is not set
+# CONFIG_CRYPTO_NHPOLY1305_NEON is not set
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_PCOMP is not set
+# CONFIG_CRYPTO_PCOMP2 is not set
+CONFIG_CRYPTO_PCRYPT=y
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_POLY1305_ARM is not set
+# CONFIG_CRYPTO_POLY1305_MIPS is not set
+# CONFIG_CRYPTO_POLY1305_NEON is not set
+# CONFIG_CRYPTO_POLY1305_X86_64 is not set
+# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_RNG is not set
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SALSA20_586 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA1_ARM is not set
+# CONFIG_CRYPTO_SHA1_ARM64 is not set
+# CONFIG_CRYPTO_SHA1_ARM64_CE is not set
+# CONFIG_CRYPTO_SHA1_ARM_CE is not set
+# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA256_ARM64 is not set
+# CONFIG_CRYPTO_SHA256_SSSE3 is not set
+# CONFIG_CRYPTO_SHA2_ARM64_CE is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SHA3_ARM64 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA512_ARM is not set
+# CONFIG_CRYPTO_SHA512_ARM64 is not set
+# CONFIG_CRYPTO_SHA512_ARM64_CE is not set
+# CONFIG_CRYPTO_SIMD is not set
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM3_ARM64_CE is not set
+# CONFIG_CRYPTO_SM3_GENERIC is not set
+# CONFIG_CRYPTO_SM3_NEON is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
+# CONFIG_CRYPTO_SM4_GENERIC is not set
+# CONFIG_CRYPTO_SPECK is not set
+# CONFIG_CRYPTO_STATS is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_TWOFISH_586 is not set
+# CONFIG_CRYPTO_TWOFISH_COMMON is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_ZSTD is not set
+# CONFIG_CS5535_MFGPT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_CS89x0_PLATFORM is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# CONFIG_CURRENT_POINTER_IN_TPIDRURO is not set
+# CONFIG_CUSE is not set
+# CONFIG_CW1200 is not set
+# CONFIG_CXD2880_SPI_DRV is not set
+# CONFIG_CXL_AFU_DRIVER_OPS is not set
+# CONFIG_CXL_BASE is not set
+# CONFIG_CXL_BUS is not set
+# CONFIG_CXL_EEH is not set
+# CONFIG_CXL_KERNEL_API is not set
+# CONFIG_CXL_LIB is not set
+# CONFIG_CYPRESS_FIRMWARE is not set
+# CONFIG_DA280 is not set
+# CONFIG_DA311 is not set
+# CONFIG_DAMON is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DAX is not set
+# CONFIG_DCB is not set
+# CONFIG_DDR is not set
+# CONFIG_DEBUG_ALIGN_RODATA is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_EFI is not set
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_INFO_BTF is not set
+# CONFIG_DEBUG_INFO_COMPRESSED is not set
+CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
+# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+CONFIG_DEBUG_INFO_DWARF5=y
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_NONE is not set
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_DEBUG_INFO_SPLIT is not set
+# CONFIG_DEBUG_IRQFLAGS is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_KMAP_LOCAL is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_KOBJECT_RELEASE is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_LL_UART_8250 is not set
+# CONFIG_DEBUG_LL_UART_PL01X is not set
+# CONFIG_DEBUG_LOCKDEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_MAPLE_TREE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_MISC is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_NET is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_NX_TEST is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_PAGE_REF is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_DEBUG_PI_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+# CONFIG_DEBUG_RSEQ is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_SEMIHOSTING is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+# CONFIG_DEBUG_UART_8250_PALMCHIP is not set
+# CONFIG_DEBUG_UART_8250_WORD is not set
+# CONFIG_DEBUG_UART_BCM63XX is not set
+# CONFIG_DEBUG_UART_FLOW_CONTROL is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_VIRTUAL is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGFLAGS is not set
+# CONFIG_DEBUG_VM_PGTABLE is not set
+# CONFIG_DEBUG_VM_RB is not set
+# CONFIG_DEBUG_VM_VMACACHE is not set
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_WX is not set
+# CONFIG_DEBUG_ZBOOT is not set
+# CONFIG_DECNET is not set
+CONFIG_DEFAULT_CUBIC=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_PFIFO_FAST=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_DEFAULT_SECURITY_DAC=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+# CONFIG_DELL_LAPTOP is not set
+# CONFIG_DELL_RBTN is not set
+# CONFIG_DELL_SMBIOS is not set
+# CONFIG_DELL_SMO8800 is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_DEVMEM is not set
+CONFIG_DEVPORT=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_DEVTMPFS is not set
+# CONFIG_DEVTMPFS_MOUNT is not set
+# CONFIG_DEV_DAX is not set
+# CONFIG_DGAP is not set
+# CONFIG_DGNC is not set
+# CONFIG_DHT11 is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set
+# CONFIG_DISPLAY_CONNECTOR_DVI is not set
+# CONFIG_DISPLAY_CONNECTOR_HDMI is not set
+# CONFIG_DISPLAY_ENCODER_TFP410 is not set
+# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set
+# CONFIG_DISPLAY_PANEL_DPI is not set
+# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set
+# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DL2K is not set
+# CONFIG_DLHL60D is not set
+# CONFIG_DLM is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_DMADEVICES_DEBUG is not set
+# CONFIG_DMAPOOL_TEST is not set
+# CONFIG_DMARD06 is not set
+# CONFIG_DMARD09 is not set
+# CONFIG_DMARD10 is not set
+# CONFIG_DMASCC is not set
+# CONFIG_DMATEST is not set
+# CONFIG_DMA_API_DEBUG is not set
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DECLARE_COHERENT=y
+# CONFIG_DMA_ENGINE is not set
+# CONFIG_DMA_FENCE_TRACE is not set
+# CONFIG_DMA_JZ4780 is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_DMA_NONCOHERENT_MMAP=y
+# CONFIG_DMA_NOOP_OPS is not set
+# CONFIG_DMA_NUMA_CMA is not set
+# CONFIG_DMA_PERNUMA_CMA is not set
+# CONFIG_DMA_RESTRICTED_POOL is not set
+# CONFIG_DMA_SHARED_BUFFER is not set
+# CONFIG_DMA_VIRT_OPS is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_CLONE is not set
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_DUST is not set
+# CONFIG_DM_EBS is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_INTEGRITY is not set
+# CONFIG_DM_LOG_USERSPACE is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_DM_MQ_DEFAULT is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_SWITCH is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_UNSTRIPED is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_DM_WRITECACHE is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DNET is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_DNS_RESOLVER is not set
+CONFIG_DOUBLEFAULT=y
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83TD510_PHY is not set
+# CONFIG_DPOT_DAC is not set
+# CONFIG_DPS310 is not set
+CONFIG_DQL=y
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_DRM is not set
+# CONFIG_DRM_ACCEL is not set
+# CONFIG_DRM_AMDGPU is not set
+# CONFIG_DRM_AMDGPU_CIK is not set
+# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
+# CONFIG_DRM_AMDGPU_SI is not set
+# CONFIG_DRM_AMDGPU_USERPTR is not set
+# CONFIG_DRM_AMD_ACP is not set
+# CONFIG_DRM_AMD_DC_DCN2_0 is not set
+# CONFIG_DRM_AMD_DC_DCN3_0 is not set
+# CONFIG_DRM_AMD_DC_HDCP is not set
+# CONFIG_DRM_AMD_DC_SI is not set
+# CONFIG_DRM_ANALOGIX_ANX6345 is not set
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_ARMADA is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_BOCHS is not set
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MM is not set
+# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DP_CEC is not set
+# CONFIG_DRM_DUMB_VGA_DAC is not set
+# CONFIG_DRM_DW_HDMI_CEC is not set
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_EXYNOS is not set
+# CONFIG_DRM_FBDEV_EMULATION is not set
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+# CONFIG_DRM_FSL_DCU is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_GMA500 is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_HDLCD is not set
+# CONFIG_DRM_HISI_HIBMC is not set
+# CONFIG_DRM_HISI_KIRIN is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I915 is not set
+CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
+# CONFIG_DRM_IMX8QM_LDB is not set
+# CONFIG_DRM_IMX8QXP_LDB is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
+# CONFIG_DRM_IMX_LCDIF is not set
+# CONFIG_DRM_ITE_IT6505 is not set
+# CONFIG_DRM_ITE_IT66121 is not set
+# CONFIG_DRM_KOMEDA is not set
+# CONFIG_DRM_LEGACY is not set
+# CONFIG_DRM_LIB_RANDOM is not set
+# CONFIG_DRM_LIMA is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_DRM_LOGICVC is not set
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9211 is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
+# CONFIG_DRM_LONTIUM_LT9611UXC is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_LVDS_ENCODER is not set
+# CONFIG_DRM_MALI_DISPLAY is not set
+# CONFIG_DRM_MCDE is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_NWL_MIPI_DSI is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_OMAP is not set
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
+# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
+# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
+# CONFIG_DRM_PANEL_DSI_CM is not set
+# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
+# CONFIG_DRM_PANEL_EDP is not set
+# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
+# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
+# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
+# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
+# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
+# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
+# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
+# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
+# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
+# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
+# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
+# CONFIG_DRM_PANEL_MIPI_DBI is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
+# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
+# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
+# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
+# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
+# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
+# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
+# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set
+# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
+# CONFIG_DRM_PANEL_SIMPLE is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
+# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
+# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
+# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
+# CONFIG_DRM_PANFROST is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_PARADE_PS8640 is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_QXL is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_RADEON_USERPTR is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
+# CONFIG_DRM_SAMSUNG_DSIM is not set
+# CONFIG_DRM_SII902X is not set
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_DRM_SIMPLE_BRIDGE is not set
+# CONFIG_DRM_SSD130X is not set
+# CONFIG_DRM_STI is not set
+# CONFIG_DRM_STM is not set
+# CONFIG_DRM_SUN4I is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_TILCDC is not set
+# CONFIG_DRM_TINYDRM is not set
+# CONFIG_DRM_TI_DLPC3433 is not set
+# CONFIG_DRM_TI_SN65DSI83 is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_TPD12S015 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TVE200 is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_USE_DYNAMIC_DEBUG is not set
+# CONFIG_DRM_VBOXVIDEO is not set
+# CONFIG_DRM_VC4_HDMI_CEC is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VIRTIO_GPU is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_DRM_VMWGFX is not set
+# CONFIG_DRM_XEN is not set
+# CONFIG_DRM_XEN_FRONTEND is not set
+# CONFIG_DS1682 is not set
+# CONFIG_DS1803 is not set
+# CONFIG_DS4424 is not set
+# CONFIG_DST_CACHE is not set
+# CONFIG_DTLK is not set
+# CONFIG_DUMMY is not set
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_DVB_A8293 is not set
+# CONFIG_DVB_AF9013 is not set
+# CONFIG_DVB_AF9033 is not set
+# CONFIG_DVB_AS102 is not set
+# CONFIG_DVB_ASCOT2E is not set
+# CONFIG_DVB_ATBM8830 is not set
+# CONFIG_DVB_AU8522_DTV is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_B2C2_FLEXCOP_USB is not set
+# CONFIG_DVB_BCM3510 is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DVB_CX22700 is not set
+# CONFIG_DVB_CX22702 is not set
+# CONFIG_DVB_CX24110 is not set
+# CONFIG_DVB_CX24116 is not set
+# CONFIG_DVB_CX24117 is not set
+# CONFIG_DVB_CX24120 is not set
+# CONFIG_DVB_CX24123 is not set
+# CONFIG_DVB_CXD2099 is not set
+# CONFIG_DVB_CXD2820R is not set
+# CONFIG_DVB_CXD2841ER is not set
+# CONFIG_DVB_CXD2880 is not set
+# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
+# CONFIG_DVB_DIB3000MB is not set
+# CONFIG_DVB_DIB3000MC is not set
+# CONFIG_DVB_DIB7000M is not set
+# CONFIG_DVB_DIB7000P is not set
+# CONFIG_DVB_DIB8000 is not set
+# CONFIG_DVB_DIB9000 is not set
+# CONFIG_DVB_DRX39XYJ is not set
+# CONFIG_DVB_DRXD is not set
+# CONFIG_DVB_DRXK is not set
+# CONFIG_DVB_DS3000 is not set
+# CONFIG_DVB_DUMMY_FE is not set
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+# CONFIG_DVB_EC100 is not set
+# CONFIG_DVB_FIREDTV is not set
+# CONFIG_DVB_HELENE is not set
+# CONFIG_DVB_HORUS3A is not set
+# CONFIG_DVB_ISL6405 is not set
+# CONFIG_DVB_ISL6421 is not set
+# CONFIG_DVB_ISL6423 is not set
+# CONFIG_DVB_IX2505V is not set
+# CONFIG_DVB_L64781 is not set
+# CONFIG_DVB_LG2160 is not set
+# CONFIG_DVB_LGDT3305 is not set
+# CONFIG_DVB_LGDT3306A is not set
+# CONFIG_DVB_LGDT330X is not set
+# CONFIG_DVB_LGS8GL5 is not set
+# CONFIG_DVB_LGS8GXX is not set
+# CONFIG_DVB_LNBH25 is not set
+# CONFIG_DVB_LNBH29 is not set
+# CONFIG_DVB_LNBP21 is not set
+# CONFIG_DVB_LNBP22 is not set
+# CONFIG_DVB_M88DS3103 is not set
+# CONFIG_DVB_M88RS2000 is not set
+CONFIG_DVB_MAX_ADAPTERS=16
+# CONFIG_DVB_MB86A16 is not set
+# CONFIG_DVB_MB86A20S is not set
+# CONFIG_DVB_MMAP is not set
+# CONFIG_DVB_MN88443X is not set
+# CONFIG_DVB_MN88472 is not set
+# CONFIG_DVB_MN88473 is not set
+# CONFIG_DVB_MT312 is not set
+# CONFIG_DVB_MT352 is not set
+# CONFIG_DVB_MXL5XX is not set
+# CONFIG_DVB_MXL692 is not set
+# CONFIG_DVB_NET is not set
+# CONFIG_DVB_NXT200X is not set
+# CONFIG_DVB_NXT6000 is not set
+# CONFIG_DVB_OR51132 is not set
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_PLATFORM_DRIVERS is not set
+# CONFIG_DVB_PLL is not set
+# CONFIG_DVB_RTL2830 is not set
+# CONFIG_DVB_RTL2832 is not set
+# CONFIG_DVB_RTL2832_SDR is not set
+# CONFIG_DVB_S5H1409 is not set
+# CONFIG_DVB_S5H1411 is not set
+# CONFIG_DVB_S5H1420 is not set
+# CONFIG_DVB_S5H1432 is not set
+# CONFIG_DVB_S921 is not set
+# CONFIG_DVB_SI2165 is not set
+# CONFIG_DVB_SI2168 is not set
+# CONFIG_DVB_SI21XX is not set
+# CONFIG_DVB_SP2 is not set
+# CONFIG_DVB_SP8870 is not set
+# CONFIG_DVB_SP887X is not set
+# CONFIG_DVB_STB0899 is not set
+# CONFIG_DVB_STB6000 is not set
+# CONFIG_DVB_STB6100 is not set
+# CONFIG_DVB_STV0288 is not set
+# CONFIG_DVB_STV0297 is not set
+# CONFIG_DVB_STV0299 is not set
+# CONFIG_DVB_STV0367 is not set
+# CONFIG_DVB_STV0900 is not set
+# CONFIG_DVB_STV090x is not set
+# CONFIG_DVB_STV0910 is not set
+# CONFIG_DVB_STV6110 is not set
+# CONFIG_DVB_STV6110x is not set
+# CONFIG_DVB_STV6111 is not set
+# CONFIG_DVB_TC90522 is not set
+# CONFIG_DVB_TDA10021 is not set
+# CONFIG_DVB_TDA10023 is not set
+# CONFIG_DVB_TDA10048 is not set
+# CONFIG_DVB_TDA1004X is not set
+# CONFIG_DVB_TDA10071 is not set
+# CONFIG_DVB_TDA10086 is not set
+# CONFIG_DVB_TDA18271C2DD is not set
+# CONFIG_DVB_TDA665x is not set
+# CONFIG_DVB_TDA8083 is not set
+# CONFIG_DVB_TDA8261 is not set
+# CONFIG_DVB_TDA826X is not set
+# CONFIG_DVB_TEST_DRIVERS is not set
+# CONFIG_DVB_TS2020 is not set
+# CONFIG_DVB_TTUSB_BUDGET is not set
+# CONFIG_DVB_TTUSB_DEC is not set
+# CONFIG_DVB_TUA6100 is not set
+# CONFIG_DVB_TUNER_CX24113 is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+# CONFIG_DVB_TUNER_ITD1000 is not set
+# CONFIG_DVB_ULE_DEBUG is not set
+# CONFIG_DVB_USB_V2 is not set
+# CONFIG_DVB_VES1820 is not set
+# CONFIG_DVB_VES1X93 is not set
+# CONFIG_DVB_ZD1301_DEMOD is not set
+# CONFIG_DVB_ZL10036 is not set
+# CONFIG_DVB_ZL10039 is not set
+# CONFIG_DVB_ZL10353 is not set
+# CONFIG_DWC_XLGMAC is not set
+# CONFIG_DWMAC_DWC_QOS_ETH is not set
+# CONFIG_DWMAC_INTEL_PLAT is not set
+# CONFIG_DWMAC_IPQ806X is not set
+# CONFIG_DWMAC_LOONGSON is not set
+# CONFIG_DWMAC_LPC18XX is not set
+# CONFIG_DWMAC_MESON is not set
+# CONFIG_DWMAC_ROCKCHIP is not set
+# CONFIG_DWMAC_SOCFPGA is not set
+# CONFIG_DWMAC_STI is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_DMAC_PCI is not set
+# CONFIG_DW_EDMA is not set
+# CONFIG_DW_EDMA_PCIE is not set
+# CONFIG_DW_WATCHDOG is not set
+# CONFIG_DW_XDATA_PCIE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DYNAMIC_DEBUG_CORE is not set
+# CONFIG_E100 is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_HWTS is not set
+# CONFIG_EARLY_PRINTK_8250 is not set
+# CONFIG_EARLY_PRINTK_USB_XDBC is not set
+# CONFIG_EBC_C384_WDT is not set
+# CONFIG_ECHO is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_EDAC is not set
+# CONFIG_EEEPC_LAPTOP is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_DIGSY_MTC_CFG is not set
+# CONFIG_EEPROM_EE1004 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EFI is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_EFS_FS is not set
+CONFIG_ELFCORE=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_EMAC_ROCKCHIP is not set
+CONFIG_EMBEDDED=y
+# CONFIG_EM_TIMER_STI is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENA_ETHERNET is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_ENCX24J600 is not set
+# CONFIG_ENERGY_MODEL is not set
+# CONFIG_ENIC is not set
+# CONFIG_ENVELOPE_DETECTOR is not set
+# CONFIG_EPAPR_PARAVIRT is not set
+# CONFIG_EPIC100 is not set
+CONFIG_EPOLL=y
+# CONFIG_EQUALIZER is not set
+# CONFIG_EROFS_FS is not set
+# CONFIG_ET131X is not set
+CONFIG_ETHERNET=y
+# CONFIG_ETHOC is not set
+CONFIG_ETHTOOL_NETLINK=y
+CONFIG_EVENTFD=y
+# CONFIG_EVM is not set
+# CONFIG_EXCLUSIVE_SYSTEM_RAM is not set
+# CONFIG_EXFAT_FS is not set
+CONFIG_EXPERT=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+# CONFIG_EXT2_FS is not set
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_DEBUG is not set
+# CONFIG_EXT4_ENCRYPTION is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_EXT4_USE_FOR_EXT2=y
+# CONFIG_EXTCON is not set
+# CONFIG_EXTCON_ADC_JACK is not set
+# CONFIG_EXTCON_ARIZONA is not set
+# CONFIG_EXTCON_AXP288 is not set
+# CONFIG_EXTCON_FSA9480 is not set
+# CONFIG_EXTCON_GPIO is not set
+# CONFIG_EXTCON_INTEL_INT3496 is not set
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_QCOM_SPMI_MISC is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+# CONFIG_EXTCON_USBC_TUSB320 is not set
+# CONFIG_EXTCON_USB_GPIO is not set
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_EXYNOS_ADC is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_FAULT_INJECTION is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_F2FS_FS_COMPRESSION is not set
+# CONFIG_F2FS_FS_ENCRYPTION is not set
+# CONFIG_F2FS_FS_POSIX_ACL is not set
+# CONFIG_F2FS_FS_SECURITY is not set
+CONFIG_F2FS_FS_XATTR=y
+# CONFIG_F2FS_IOSTAT is not set
+# CONFIG_F2FS_IO_TRACE is not set
+CONFIG_F2FS_STAT_FS=y
+# CONFIG_F2FS_UNFAIR_RWSEM is not set
+# CONFIG_FAILOVER is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_FANOTIFY is not set
+# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_FB is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_BIG_ENDIAN is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_BOTH_ENDIAN is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_DA8XX is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_FLEX is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_GEODE is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_IMX is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_LITTLE_ENDIAN is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_MXS is not set
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_NEOMAGIC is not set
+CONFIG_FB_NOTIFY=y
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_OF is not set
+# CONFIG_FB_OMAP2 is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_PS3 is not set
+# CONFIG_FB_PXA is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_SM712 is not set
+# CONFIG_FB_SM750 is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_SSD1307 is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_FB_TFT_AGM1264K_FL is not set
+# CONFIG_FB_TFT_BD663474 is not set
+# CONFIG_FB_TFT_FBTFT_DEVICE is not set
+# CONFIG_FB_TFT_HX8340BN is not set
+# CONFIG_FB_TFT_HX8347D is not set
+# CONFIG_FB_TFT_HX8353D is not set
+# CONFIG_FB_TFT_HX8357D is not set
+# CONFIG_FB_TFT_ILI9163 is not set
+# CONFIG_FB_TFT_ILI9320 is not set
+# CONFIG_FB_TFT_ILI9325 is not set
+# CONFIG_FB_TFT_ILI9340 is not set
+# CONFIG_FB_TFT_ILI9341 is not set
+# CONFIG_FB_TFT_ILI9481 is not set
+# CONFIG_FB_TFT_ILI9486 is not set
+# CONFIG_FB_TFT_PCD8544 is not set
+# CONFIG_FB_TFT_RA8875 is not set
+# CONFIG_FB_TFT_S6D02A1 is not set
+# CONFIG_FB_TFT_S6D1121 is not set
+# CONFIG_FB_TFT_SEPS525 is not set
+# CONFIG_FB_TFT_SH1106 is not set
+# CONFIG_FB_TFT_SSD1289 is not set
+# CONFIG_FB_TFT_SSD1305 is not set
+# CONFIG_FB_TFT_SSD1306 is not set
+# CONFIG_FB_TFT_SSD1325 is not set
+# CONFIG_FB_TFT_SSD1331 is not set
+# CONFIG_FB_TFT_SSD1351 is not set
+# CONFIG_FB_TFT_ST7735R is not set
+# CONFIG_FB_TFT_ST7789V is not set
+# CONFIG_FB_TFT_TINYLCD is not set
+# CONFIG_FB_TFT_TLS8204 is not set
+# CONFIG_FB_TFT_UC1611 is not set
+# CONFIG_FB_TFT_UC1701 is not set
+# CONFIG_FB_TFT_UPD161704 is not set
+# CONFIG_FB_TFT_WATTEROTT is not set
+# CONFIG_FB_TILEBLITTING is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_VIA is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_XGI is not set
+# CONFIG_FCOE is not set
+# CONFIG_FCOE_FNIC is not set
+# CONFIG_FDDI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_FENCE_TRACE is not set
+# CONFIG_FHANDLE is not set
+CONFIG_FIB_RULES=y
+# CONFIG_FIELDBUS_DEV is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FIND_BIT_BENCHMARK is not set
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_FIREWIRE_SERIAL is not set
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_FIT_PARTITION is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_FLATMEM=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_FM10K is not set
+# CONFIG_FMC is not set
+# CONFIG_FONTS is not set
+# CONFIG_FONT_6x8 is not set
+# CONFIG_FONT_TER16x32 is not set
+# CONFIG_FORCEDETH is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_FORCE_NR_CPUS is not set
+CONFIG_FORTIFY_SOURCE=y
+# CONFIG_FPGA is not set
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# CONFIG_FRAME_POINTER is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_FREEZER is not set
+# CONFIG_FRONTSWAP is not set
+# CONFIG_FSCACHE is not set
+# CONFIG_FSI is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_FSL_ERRATUM_A008585 is not set
+# CONFIG_FSL_MC_BUS is not set
+# CONFIG_FSL_PQ_MDIO is not set
+# CONFIG_FSL_QDMA is not set
+# CONFIG_FSL_RCPM is not set
+# CONFIG_FSL_XGMAC_MDIO is not set
+CONFIG_FSNOTIFY=y
+# CONFIG_FS_DAX is not set
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_FS_VERITY is not set
+# CONFIG_FTGMAC100 is not set
+# CONFIG_FTL is not set
+# CONFIG_FTMAC100 is not set
+# CONFIG_FTRACE is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_FTWDT010_WATCHDOG is not set
+# CONFIG_FUJITSU_ERRATUM_010001 is not set
+# CONFIG_FUJITSU_ES is not set
+# CONFIG_FUJITSU_LAPTOP is not set
+# CONFIG_FUJITSU_TABLET is not set
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_FUSE_FS is not set
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+# CONFIG_FUSION_SPI is not set
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+# CONFIG_FWNODE_MDIO is not set
+# CONFIG_FW_CFG_SYSFS is not set
+# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
+CONFIG_FW_LOADER=y
+# CONFIG_FW_LOADER_COMPRESS is not set
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_FW_UPLOAD is not set
+# CONFIG_FXAS21002C is not set
+# CONFIG_FXLS8962AF_I2C is not set
+# CONFIG_FXLS8962AF_SPI is not set
+# CONFIG_FXOS8700_I2C is not set
+# CONFIG_FXOS8700_SPI is not set
+CONFIG_GACT_PROB=y
+# CONFIG_GADGET_UAC1 is not set
+# CONFIG_GAMEPORT is not set
+# CONFIG_GATEWORKS_GW16083 is not set
+# CONFIG_GCC_PLUGINS is not set
+# CONFIG_GCOV is not set
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_GDB_SCRIPTS is not set
+# CONFIG_GEMINI_ETHERNET is not set
+# CONFIG_GENERIC_ADC_BATTERY is not set
+# CONFIG_GENERIC_ADC_THERMAL is not set
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+# CONFIG_GENERIC_CPU_DEVICES is not set
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_HWEIGHT=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_IRQ_PROBE=y
+# CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED is not set
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_GENERIC_PHY is not set
+# CONFIG_GENERIC_PINCONF is not set
+# CONFIG_GENERIC_PINCTRL_GROUPS is not set
+# CONFIG_GENERIC_PINMUX_FUNCTIONS is not set
+CONFIG_GENERIC_PTDUMP=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+# CONFIG_GENEVE is not set
+# CONFIG_GENWQE is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_GIGASET_CAPI is not set
+# CONFIG_GIGASET_DEBUG is not set
+# CONFIG_GIGASET_DUMMYLL is not set
+# CONFIG_GLOB_SELFTEST is not set
+# CONFIG_GNSS is not set
+# CONFIG_GOLDFISH is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+# CONFIG_GP2AP002 is not set
+# CONFIG_GP2AP020A00F is not set
+# CONFIG_GPD_POCKET_FAN is not set
+# CONFIG_GPIOLIB is not set
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+# CONFIG_GPIO_104_DIO_48E is not set
+# CONFIG_GPIO_104_IDIO_16 is not set
+# CONFIG_GPIO_104_IDI_48 is not set
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ADNP is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_AMD8111 is not set
+# CONFIG_GPIO_AMDPT is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# CONFIG_GPIO_BCM_KONA is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_CADENCE is not set
+# CONFIG_GPIO_CDEV is not set
+# CONFIG_GPIO_CDEV_V1 is not set
+# CONFIG_GPIO_CS5535 is not set
+# CONFIG_GPIO_DELAY is not set
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_EM is not set
+# CONFIG_GPIO_EXAR is not set
+# CONFIG_GPIO_F7188X is not set
+# CONFIG_GPIO_FTGPIO010 is not set
+# CONFIG_GPIO_FXL6408 is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_GPIO_MM is not set
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_GW_PLD is not set
+# CONFIG_GPIO_HISI is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_ICH is not set
+# CONFIG_GPIO_IT87 is not set
+# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_LOGICVC is not set
+# CONFIG_GPIO_LYNXPOINT is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_MB86S7X is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_MPC8XXX is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCA9570 is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_PCH is not set
+# CONFIG_GPIO_PCIE_IDIO_24 is not set
+# CONFIG_GPIO_PCI_IDIO_16 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_PL061 is not set
+# CONFIG_GPIO_RCAR is not set
+# CONFIG_GPIO_RDC321X is not set
+# CONFIG_GPIO_ROCKCHIP is not set
+# CONFIG_GPIO_SAMA5D2_PIOBU is not set
+# CONFIG_GPIO_SCH is not set
+# CONFIG_GPIO_SCH311X is not set
+# CONFIG_GPIO_SIFIVE is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_SYSCON is not set
+# CONFIG_GPIO_SYSFS is not set
+# CONFIG_GPIO_TPIC2810 is not set
+# CONFIG_GPIO_TS4900 is not set
+# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_VX855 is not set
+# CONFIG_GPIO_WATCHDOG is not set
+# CONFIG_GPIO_WINBOND is not set
+# CONFIG_GPIO_WS16C48 is not set
+# CONFIG_GPIO_XGENE is not set
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_XRA1403 is not set
+# CONFIG_GPIO_ZEVIO is not set
+# CONFIG_GPIO_ZX is not set
+# CONFIG_GP_PCI1XXXX is not set
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_GREYBUS is not set
+# CONFIG_GS_FPGABOOT is not set
+# CONFIG_GTP is not set
+# CONFIG_GUP_BENCHMARK is not set
+# CONFIG_GUP_TEST is not set
+# CONFIG_GVE is not set
+# CONFIG_HABANA_AI is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_HARDENED_USERCOPY_FALLBACK is not set
+# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
+CONFIG_HARDEN_EL2_VECTORS=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_HAVE_ARM_ARCH_TIMER is not set
+# CONFIG_HCALL_STATS is not set
+# CONFIG_HDC100X is not set
+# CONFIG_HDC2010 is not set
+# CONFIG_HDLC is not set
+# CONFIG_HDLC_CISCO is not set
+# CONFIG_HDLC_FR is not set
+# CONFIG_HDLC_PPP is not set
+# CONFIG_HDLC_RAW is not set
+# CONFIG_HDLC_RAW_ETH is not set
+# CONFIG_HDMI_LPE_AUDIO is not set
+# CONFIG_HDQ_MASTER_OMAP is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_HEADER_TEST is not set
+# CONFIG_HERMES is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_HFSPLUS_FS_POSIX_ACL is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFS_FS_POSIX_ACL is not set
+# CONFIG_HI8435 is not set
+# CONFIG_HIBERNATION is not set
+# CONFIG_HID is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_ACRUX_FF is not set
+# CONFIG_HID_ALPS is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_ASUS is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_BIGBEN_FF is not set
+# CONFIG_HID_BPF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CORSAIR is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_CP2112 is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_ELAN is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_EVISION is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_FT260 is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GENERIC is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_GLORIOUS is not set
+# CONFIG_HID_GOOGLE_HAMMER is not set
+# CONFIG_HID_GOOGLE_STADIA_FF is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_GT683R is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LED is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_LOGITECH_DJ is not set
+# CONFIG_HID_LOGITECH_HIDPP is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_MCP2221 is not set
+# CONFIG_HID_MEGAWORLD_FF is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NINTENDO is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PID is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PLAYSTATION is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_PXRC is not set
+# CONFIG_HID_RAZER is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SEMITEK is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_SIGMAMICRO is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_HID_THINGM is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPRE is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_U2FZERO is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_VIVALDI is not set
+# CONFIG_HID_VRC2 is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_WIIMOTE is not set
+# CONFIG_HID_XIAOM is not set
+# CONFIG_HID_XIAOMI is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_HINIC is not set
+# CONFIG_HIP04_ETH is not set
+# CONFIG_HIPPI is not set
+# CONFIG_HISILICON_ERRATUM_161010101 is not set
+# CONFIG_HISILICON_ERRATUM_161600802 is not set
+# CONFIG_HISI_DMA is not set
+# CONFIG_HISI_FEMAC is not set
+# CONFIG_HISI_HIKEY_USB is not set
+# CONFIG_HISI_PCIE_PMU is not set
+# CONFIG_HISI_PTT is not set
+# CONFIG_HIST_TRIGGERS_DEBUG is not set
+# CONFIG_HIX5HD2_GMAC is not set
+# CONFIG_HMC425 is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_HNS is not set
+# CONFIG_HNS3 is not set
+# CONFIG_HNS3_PMU is not set
+# CONFIG_HNS_DSAF is not set
+# CONFIG_HNS_ENET is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_HOSTAP_CS is not set
+# CONFIG_HOSTAP_PCI is not set
+# CONFIG_HOSTAP_PLX is not set
+# CONFIG_HOTPLUG_CPU is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+# CONFIG_HP03 is not set
+# CONFIG_HP100 is not set
+# CONFIG_HP206C is not set
+CONFIG_HPET_MMAP_DEFAULT=y
+# CONFIG_HPFS_FS is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_HP_WIRELESS is not set
+# CONFIG_HSA_AMD is not set
+# CONFIG_HSI is not set
+# CONFIG_HSR is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTE is not set
+# CONFIG_HTS221 is not set
+# CONFIG_HTU21 is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_HVC_UDBG is not set
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWSPINLOCK is not set
+# CONFIG_HWSPINLOCK_OMAP is not set
+CONFIG_HW_PERF_EVENTS=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HW_RANDOM_AMD is not set
+# CONFIG_HW_RANDOM_ARM_SMCCC_TRNG is not set
+# CONFIG_HW_RANDOM_ATMEL is not set
+# CONFIG_HW_RANDOM_BA431 is not set
+# CONFIG_HW_RANDOM_CAVIUM is not set
+# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_CN10K is not set
+# CONFIG_HW_RANDOM_EXYNOS is not set
+# CONFIG_HW_RANDOM_GEODE is not set
+# CONFIG_HW_RANDOM_INTEL is not set
+# CONFIG_HW_RANDOM_IPROC_RNG200 is not set
+# CONFIG_HW_RANDOM_MTK is not set
+# CONFIG_HW_RANDOM_OMAP is not set
+# CONFIG_HW_RANDOM_OMAP3_ROM is not set
+# CONFIG_HW_RANDOM_PPC4XX is not set
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_TPM=y
+# CONFIG_HW_RANDOM_VIA is not set
+# CONFIG_HW_RANDOM_VIRTIO is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+# CONFIG_HX711 is not set
+# CONFIG_HYPERV is not set
+# CONFIG_HYPERV_TSCPAGE is not set
+# CONFIG_HYSDN is not set
+CONFIG_HZ=100
+CONFIG_HZ_100=y
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_200 is not set
+# CONFIG_HZ_24 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_500 is not set
+# CONFIG_HZ_PERIODIC is not set
+# CONFIG_I2C is not set
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCA is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
+# CONFIG_I2C_AU1550 is not set
+# CONFIG_I2C_BCM2835 is not set
+# CONFIG_I2C_BCM_IPROC is not set
+# CONFIG_I2C_CADENCE is not set
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_CHARDEV is not set
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEMUX_PINCTRL is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_SLAVE is not set
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_EMEV2 is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_HID is not set
+# CONFIG_I2C_HID_OF is not set
+# CONFIG_I2C_HID_OF_ELAN is not set
+# CONFIG_I2C_HID_OF_GOODIX is not set
+# CONFIG_I2C_HISI is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_IBM_IIC is not set
+# CONFIG_I2C_IMG is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_ISMT is not set
+# CONFIG_I2C_JZ4780 is not set
+# CONFIG_I2C_MLXCPLD is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_MT65XX is not set
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_MUX_GPIO is not set
+# CONFIG_I2C_MUX_GPMUX is not set
+# CONFIG_I2C_MUX_LTC4306 is not set
+# CONFIG_I2C_MUX_MLXCPLD is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+# CONFIG_I2C_MUX_PCA954x is not set
+# CONFIG_I2C_MUX_PINCTRL is not set
+# CONFIG_I2C_MUX_REG is not set
+# CONFIG_I2C_MV64XXX is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_NOMADIK is not set
+# CONFIG_I2C_NVIDIA_GPU is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_OCTEON is not set
+# CONFIG_I2C_PARPORT is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_RCAR is not set
+# CONFIG_I2C_RK3X is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_S3C2410 is not set
+# CONFIG_I2C_SCMI is not set
+# CONFIG_I2C_SH_MOBILE is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_I2C_SLAVE_EEPROM is not set
+# CONFIG_I2C_SMBUS is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_THUNDERX is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VERSATILE is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VIRTIO is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I3C is not set
+# CONFIG_I40E is not set
+# CONFIG_I40EVF is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_IAQCORE is not set
+# CONFIG_IBM_ASM is not set
+# CONFIG_IBM_EMAC_DEBUG is not set
+# CONFIG_IBM_EMAC_EMAC4 is not set
+# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_EMAC_RGMII is not set
+# CONFIG_IBM_EMAC_TAH is not set
+# CONFIG_IBM_EMAC_ZMII is not set
+# CONFIG_ICE is not set
+# CONFIG_ICP10100 is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ICST is not set
+# CONFIG_IDE is not set
+# CONFIG_IDEAPAD_LAPTOP is not set
+# CONFIG_IDE_GD is not set
+# CONFIG_IDE_PROC_FS is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_IEEE802154_ADF7242 is not set
+# CONFIG_IEEE802154_ATUSB is not set
+# CONFIG_IEEE802154_CA8210 is not set
+# CONFIG_IEEE802154_HWSIM is not set
+# CONFIG_IEEE802154_MCR20A is not set
+# CONFIG_IFB is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IGB_HWMON is not set
+# CONFIG_IGC is not set
+# CONFIG_IIO is not set
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_BUFFER_CB is not set
+# CONFIG_IIO_BUFFER_DMA is not set
+# CONFIG_IIO_BUFFER_DMAENGINE is not set
+# CONFIG_IIO_BUFFER_HDC2010 is not set
+# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
+# CONFIG_IIO_CONFIGFS is not set
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set
+# CONFIG_IIO_INTERRUPT_TRIGGER is not set
+# CONFIG_IIO_KX022A_I2C is not set
+# CONFIG_IIO_KX022A_SPI is not set
+# CONFIG_IIO_MUX is not set
+# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
+# CONFIG_IIO_RESCALE is not set
+# CONFIG_IIO_SIMPLE_DUMMY is not set
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# CONFIG_IIO_ST_ACCEL_3AXIS is not set
+# CONFIG_IIO_ST_GYRO_3AXIS is not set
+# CONFIG_IIO_ST_LSM6DSX is not set
+# CONFIG_IIO_ST_LSM9DS0 is not set
+# CONFIG_IIO_ST_MAGN_3AXIS is not set
+# CONFIG_IIO_ST_PRESS is not set
+# CONFIG_IIO_SW_DEVICE is not set
+# CONFIG_IIO_SW_TRIGGER is not set
+# CONFIG_IIO_SYSFS_TRIGGER is not set
+# CONFIG_IIO_TRIGGER is not set
+# CONFIG_IIO_TRIGGERED_EVENT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_IKCONFIG_PROC is not set
+# CONFIG_IKHEADERS is not set
+# CONFIG_IMA is not set
+# CONFIG_IMAGE_CMDLINE_HACK is not set
+# CONFIG_IMGPDC_WDT is not set
+# CONFIG_IMG_MDC_DMA is not set
+# CONFIG_IMX7D_ADC is not set
+# CONFIG_IMX_IPUV3_CORE is not set
+# CONFIG_IMX_MU_MSI is not set
+# CONFIG_IMX_THERMAL is not set
+# CONFIG_INA2XX_ADC is not set
+# CONFIG_INDIRECT_PIO is not set
+CONFIG_INET=y
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_ESPINTCP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_ESPINTCP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_TABLE_PERTURB_ORDER=16
+# CONFIG_INET_TCP_DIAG is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_INFTL is not set
+# CONFIG_INGENIC_ADC is not set
+# CONFIG_INGENIC_CGU_JZ4725B is not set
+# CONFIG_INGENIC_CGU_JZ4740 is not set
+# CONFIG_INGENIC_CGU_JZ4770 is not set
+# CONFIG_INGENIC_CGU_JZ4780 is not set
+# CONFIG_INGENIC_CGU_X1000 is not set
+# CONFIG_INGENIC_CGU_X1830 is not set
+# CONFIG_INGENIC_OST is not set
+# CONFIG_INGENIC_SYSOST is not set
+# CONFIG_INGENIC_TCU_CLK is not set
+# CONFIG_INGENIC_TCU_IRQ is not set
+# CONFIG_INGENIC_TIMER is not set
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# CONFIG_INIT_STACK_ALL_PATTERN is not set
+# CONFIG_INIT_STACK_ALL_ZERO is not set
+CONFIG_INIT_STACK_NONE=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_APANEL is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_ATLAS_BTNS is not set
+# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
+# CONFIG_INPUT_AXP20X_PEK is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_DA7280_HAPTICS is not set
+# CONFIG_INPUT_DRV260X_HAPTICS is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_GP2A is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_DECODER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_GPIO_TILT_POLLED is not set
+# CONFIG_INPUT_GPIO_VIBRA is not set
+# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+# CONFIG_INPUT_IQS626A is not set
+# CONFIG_INPUT_IQS7222 is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_LEDS is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+# CONFIG_INPUT_MAX8997_HAPTIC is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_MSM_VIBRATOR is not set
+# CONFIG_INPUT_PALMAS_PWRBUTTON is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PCSPKR is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_PWM_VIBRA is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_TPS65218_PWRBUTTON is not set
+# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
+# CONFIG_INPUT_TWL4030_VIBRA is not set
+# CONFIG_INPUT_TWL6040_VIBRA is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_WISTRON_BTNS is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INT340X_THERMAL is not set
+# CONFIG_INTEGRITY is not set
+# CONFIG_INTEGRITY_AUDIT is not set
+# CONFIG_INTEGRITY_SIGNATURE is not set
+# CONFIG_INTEL_ATOMISP2_LED is not set
+# CONFIG_INTEL_ATOMISP2_PM is not set
+# CONFIG_INTEL_CHT_INT33FE is not set
+# CONFIG_INTEL_HID_EVENT is not set
+# CONFIG_INTEL_IDLE is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_INTEL_INT0002_VGPIO is not set
+# CONFIG_INTEL_IOATDMA is not set
+# CONFIG_INTEL_ISH_HID is not set
+# CONFIG_INTEL_MEI is not set
+# CONFIG_INTEL_MEI_ME is not set
+# CONFIG_INTEL_MEI_TXE is not set
+# CONFIG_INTEL_MIC_CARD is not set
+# CONFIG_INTEL_MIC_HOST is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_INTEL_OAKTRAIL is not set
+# CONFIG_INTEL_PMC_CORE is not set
+# CONFIG_INTEL_PUNIT_IPC is not set
+# CONFIG_INTEL_RST is not set
+# CONFIG_INTEL_SMARTCONNECT is not set
+# CONFIG_INTEL_SOC_PMIC is not set
+# CONFIG_INTEL_SOC_PMIC_CHTDC_TI is not set
+# CONFIG_INTEL_SOC_PMIC_CHTWC is not set
+# CONFIG_INTEL_TCC_COOLING is not set
+# CONFIG_INTEL_TH is not set
+# CONFIG_INTEL_VBTN is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_INV_ICM42600_I2C is not set
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_I2C is not set
+# CONFIG_INV_MPU6050_IIO is not set
+# CONFIG_INV_MPU6050_SPI is not set
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+# CONFIG_IOMMU_DMA_PCI_SAC is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_IONIC is not set
+# CONFIG_IOSCHED_BFQ is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IO_STRICT_DEVMEM=y
+# CONFIG_IO_URING is not set
+CONFIG_IO_WQ=y
+# CONFIG_IP17XX_PHY is not set
+# CONFIG_IP5XXX_POWER is not set
+# CONFIG_IP6_NF_FILTER is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP6_NF_MANGLE is not set
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_RPFILTER is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_MATCH_SRH is not set
+# CONFIG_IP6_NF_NAT is not set
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP6_NF_SECURITY is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+# CONFIG_IP6_NF_TARGET_MASQUERADE is not set
+# CONFIG_IP6_NF_TARGET_REJECT is not set
+# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
+# CONFIG_IPACK_BUS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_IPMB_DEVICE_INTERFACE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPV6 is not set
+# CONFIG_IPV6_FOU is not set
+# CONFIG_IPV6_FOU_TUNNEL is not set
+# CONFIG_IPV6_ILA is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_ROUTE_INFO is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_IPV6_SIT_6RD is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_VTI is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_IPVTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2100_DEBUG is not set
+CONFIG_IPW2100_MONITOR=y
+# CONFIG_IPW2200 is not set
+# CONFIG_IPW2200_DEBUG is not set
+CONFIG_IPW2200_MONITOR=y
+# CONFIG_IPW2200_PROMISCUOUS is not set
+# CONFIG_IPW2200_QOS is not set
+# CONFIG_IPW2200_RADIOTAP is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_IPX is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_FIB_TRIE_STATS is not set
+# CONFIG_IP_MROUTE is not set
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_NF_ARPFILTER is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_ARP_MANGLE is not set
+# CONFIG_IP_NF_FILTER is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_RPFILTER is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_SECURITY is not set
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+# CONFIG_IP_NF_TARGET_ECN is not set
+# CONFIG_IP_NF_TARGET_MASQUERADE is not set
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+# CONFIG_IP_NF_TARGET_REJECT is not set
+# CONFIG_IP_NF_TARGET_SYNPROXY is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_PIMSM_V1 is not set
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_IP_PNP is not set
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_IP_SET is not set
+# CONFIG_IP_SET_HASH_IPMAC is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IP_VS_MH is not set
+CONFIG_IP_VS_MH_TAB_INDEX=10
+# CONFIG_IP_VS_TWOS is not set
+# CONFIG_IRDA is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_IRQ_ALL_CPUS is not set
+# CONFIG_IRQ_DOMAIN_DEBUG is not set
+# CONFIG_IRQ_POLL is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_IR_HIX5HD2 is not set
+# CONFIG_IR_IGORPLUGUSB is not set
+# CONFIG_IR_IGUANA is not set
+# CONFIG_IR_IMG is not set
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_LIRC_CODEC is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_REDRAT3 is not set
+# CONFIG_IR_SONY_DECODER is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_IR_TTUSBIR is not set
+# CONFIG_ISA_BUS is not set
+# CONFIG_ISA_BUS_API is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_ISCSI_TCP is not set
+CONFIG_ISDN=y
+# CONFIG_ISDN_AUDIO is not set
+# CONFIG_ISDN_CAPI is not set
+# CONFIG_ISDN_CAPI_CAPIDRV is not set
+# CONFIG_ISDN_DIVERSION is not set
+# CONFIG_ISDN_DRV_ACT2000 is not set
+# CONFIG_ISDN_DRV_GIGASET is not set
+# CONFIG_ISDN_DRV_HISAX is not set
+# CONFIG_ISDN_DRV_ICN is not set
+# CONFIG_ISDN_DRV_LOOP is not set
+# CONFIG_ISDN_DRV_PCBIT is not set
+# CONFIG_ISDN_DRV_SC is not set
+# CONFIG_ISDN_I4L is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_ISL29125 is not set
+# CONFIG_ISL29501 is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_ISS4xx is not set
+# CONFIG_ITG3200 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGBEVF is not set
+# CONFIG_JAILHOUSE_GUEST is not set
+# CONFIG_JBD2_DEBUG is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_LZMA=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_ZLIB is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_STATISTICS is not set
+# CONFIG_JME is not set
+CONFIG_JOLIET=y
+# CONFIG_JSA1212 is not set
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_JZ4740_WDT is not set
+# CONFIG_JZ4770_PHY is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+# CONFIG_KALLSYMS_SELFTEST is not set
+# CONFIG_KALLSYMS_UNCOMPRESSED is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_KASAN is not set
+# CONFIG_KASAN_MODULE_TEST is not set
+CONFIG_KASAN_STACK=y
+# CONFIG_KCMP is not set
+# CONFIG_KCOV is not set
+CONFIG_KCOV_IRQ_AREA_SIZE=0x40000
+# CONFIG_KCSAN is not set
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_CAT is not set
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_LZ4 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_KERNEL_XZ=y
+# CONFIG_KERNEL_ZSTD is not set
+CONFIG_KERNFS=y
+# CONFIG_KEXEC is not set
+# CONFIG_KEXEC_FILE is not set
+# CONFIG_KEYBOARD_ADC is not set
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_APPLESPI is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_PINEPHONE is not set
+# CONFIG_KEYBOARD_PXA27x is not set
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+# CONFIG_KEYBOARD_SNVS_PWRKEY is not set
+# CONFIG_KEYBOARD_STMPE is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_TEGRA is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYS is not set
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_KFENCE is not set
+# CONFIG_KGDB is not set
+# CONFIG_KMAP_LOCAL is not set
+# CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_KMX61 is not set
+# CONFIG_KPC2000 is not set
+# CONFIG_KPROBES is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
+# CONFIG_KPROBE_EVENT_GEN_TEST is not set
+# CONFIG_KS7010 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_KSM is not set
+# CONFIG_KSZ884X_PCI is not set
+# CONFIG_KUNIT is not set
+CONFIG_KUSER_HELPERS=y
+# CONFIG_KVM_AMD is not set
+# CONFIG_KVM_AMD_SEV is not set
+# CONFIG_KVM_GUEST is not set
+# CONFIG_KVM_INTEL is not set
+# CONFIG_KVM_WERROR is not set
+# CONFIG_KXCJK1013 is not set
+# CONFIG_KXSD9 is not set
+# CONFIG_L2TP is not set
+# CONFIG_L2TP_ETH is not set
+# CONFIG_L2TP_IP is not set
+# CONFIG_L2TP_V3 is not set
+# CONFIG_LAN743X is not set
+# CONFIG_LANMEDIA is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LAPB is not set
+# CONFIG_LASAT is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_LBDAF=y
+# CONFIG_LCD_AMS369FG06 is not set
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_LCD_HX8357 is not set
+# CONFIG_LCD_ILI922X is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LMS501KF03 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_OTM3225A is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LDISC_AUTOLOAD=y
+# CONFIG_LDM_PARTITION is not set
+CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y
+# CONFIG_LEDS_AN30259A is not set
+# CONFIG_LEDS_APU is not set
+# CONFIG_LEDS_AW200XX is not set
+# CONFIG_LEDS_AW2013 is not set
+# CONFIG_LEDS_BCM6328 is not set
+# CONFIG_LEDS_BCM6358 is not set
+# CONFIG_LEDS_BD2606MVV is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_BLINKM is not set
+CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
+CONFIG_LEDS_CLASS=y
+# CONFIG_LEDS_CLASS_FLASH is not set
+CONFIG_LEDS_CLASS_MULTICOLOR=y
+# CONFIG_LEDS_CR0014114 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_EL15203000 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_GROUP_MULTICOLOR is not set
+# CONFIG_LEDS_INTEL_SS4200 is not set
+# CONFIG_LEDS_IS31FL319X is not set
+# CONFIG_LEDS_IS31FL32XX is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_LM3692X is not set
+# CONFIG_LEDS_LM3697 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP3952 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LP5562 is not set
+# CONFIG_LEDS_LP55XX_COMMON is not set
+# CONFIG_LEDS_LP8501 is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_MLXCPLD is not set
+# CONFIG_LEDS_MLXREG is not set
+# CONFIG_LEDS_NIC78BX is not set
+# CONFIG_LEDS_NS2 is not set
+# CONFIG_LEDS_OT200 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_PCA995X is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_SPI_BYTE is not set
+# CONFIG_LEDS_SYSCON is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TI_LMU_COMMON is not set
+# CONFIG_LEDS_TLC591XX is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
+# CONFIG_LEDS_TRIGGER_AUDIO is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_CAMERA is not set
+# CONFIG_LEDS_TRIGGER_CPU is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+# CONFIG_LEDS_TRIGGER_DISK is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_MTD is not set
+CONFIG_LEDS_TRIGGER_NETDEV=y
+# CONFIG_LEDS_TRIGGER_ONESHOT is not set
+# CONFIG_LEDS_TRIGGER_PANIC is not set
+# CONFIG_LEDS_TRIGGER_PATTERN is not set
+CONFIG_LEDS_TRIGGER_TIMER=y
+# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
+# CONFIG_LEDS_TRIGGER_TTY is not set
+# CONFIG_LEDS_TURRIS_OMNIA is not set
+# CONFIG_LEDS_USER is not set
+# CONFIG_LED_TRIGGER_PHY is not set
+# CONFIG_LEGACY_TIOCSTI is not set
+# CONFIG_LGUEST is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_LIB80211_CRYPT_CCMP is not set
+# CONFIG_LIB80211_CRYPT_TKIP is not set
+# CONFIG_LIB80211_CRYPT_WEP is not set
+# CONFIG_LIB80211_DEBUG is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_LIBERTAS_USB is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_LIBIPW_DEBUG is not set
+# CONFIG_LIBNVDIMM is not set
+CONFIG_LIB_MEMNEQ=y
+# CONFIG_LIDAR_LITE_V2 is not set
+CONFIG_LINEAR_RANGES=y
+# CONFIG_LIQUIDIO is not set
+# CONFIG_LIQUIDIO_VF is not set
+# CONFIG_LIS3L02DQ is not set
+# CONFIG_LIST_HARDENED is not set
+# CONFIG_LITEX_LITEETH is not set
+# CONFIG_LITEX_SOC_CONTROLLER is not set
+# CONFIG_LIVEPATCH is not set
+# CONFIG_LKDTM is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_LMK04832 is not set
+# CONFIG_LMP91000 is not set
+# CONFIG_LNET is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_LOCKD is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_LOCKD_V4=y
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_LOCK_EVENT_COUNTS is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_LOGFS is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIWHEELS_FF is not set
+# CONFIG_LOGO is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+# CONFIG_LOONGSON_MC146818 is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_LP_CONSOLE is not set
+CONFIG_LRU_GEN=y
+CONFIG_LRU_GEN_ENABLED=y
+# CONFIG_LRU_GEN_STATS is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity"
+CONFIG_LSM_MMAP_MIN_ADDR=65536
+# CONFIG_LTC1660 is not set
+# CONFIG_LTC2471 is not set
+# CONFIG_LTC2485 is not set
+# CONFIG_LTC2496 is not set
+# CONFIG_LTC2497 is not set
+# CONFIG_LTC2632 is not set
+# CONFIG_LTC2688 is not set
+# CONFIG_LTC2983 is not set
+# CONFIG_LTE_GDM724X is not set
+# CONFIG_LTO_NONE is not set
+# CONFIG_LTPC is not set
+# CONFIG_LTR501 is not set
+# CONFIG_LTRF216A is not set
+# CONFIG_LUSTRE_FS is not set
+# CONFIG_LV0104CS is not set
+# CONFIG_LWTUNNEL is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_LZ4HC_COMPRESS is not set
+# CONFIG_LZ4_COMPRESS is not set
+# CONFIG_LZ4_DECOMPRESS is not set
+CONFIG_LZMA_COMPRESS=y
+CONFIG_LZMA_DECOMPRESS=y
+# CONFIG_LZO_COMPRESS is not set
+# CONFIG_LZO_DECOMPRESS is not set
+# CONFIG_M62332 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+# CONFIG_MACB is not set
+# CONFIG_MACH_ASM9260 is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_INGENIC is not set
+# CONFIG_MACH_INGENIC_SOC is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_MACH_LOONGSON2EF is not set
+# CONFIG_MACH_LOONGSON32 is not set
+# CONFIG_MACH_LOONGSON64 is not set
+# CONFIG_MACH_PIC32 is not set
+# CONFIG_MACH_PISTACHIO is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MACH_XILFPGA is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+# CONFIG_MACSEC is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_MACVTAP is not set
+# CONFIG_MAC_EMUMOUSEBTN is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MAG3110 is not set
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+# CONFIG_MAGIC_SYSRQ_SERIAL is not set
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+# CONFIG_MAILBOX is not set
+# CONFIG_MANAGER_SBS is not set
+# CONFIG_MANDATORY_FILE_LOCKING is not set
+# CONFIG_MANGLE_BOOTARGS is not set
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+# CONFIG_MAX11205 is not set
+# CONFIG_MAX11410 is not set
+# CONFIG_MAX1241 is not set
+# CONFIG_MAX1363 is not set
+# CONFIG_MAX30100 is not set
+# CONFIG_MAX30102 is not set
+# CONFIG_MAX30208 is not set
+# CONFIG_MAX31827 is not set
+# CONFIG_MAX31856 is not set
+# CONFIG_MAX31865 is not set
+# CONFIG_MAX44000 is not set
+# CONFIG_MAX44009 is not set
+# CONFIG_MAX517 is not set
+# CONFIG_MAX5432 is not set
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+# CONFIG_MAX5522 is not set
+# CONFIG_MAX5821 is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_MAX9611 is not set
+# CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_MAXLINEAR_GPHY is not set
+CONFIG_MAX_SKB_FRAGS=17
+CONFIG_MAY_USE_DEVLINK=y
+# CONFIG_MB1232 is not set
+# CONFIG_MC3230 is not set
+# CONFIG_MCB is not set
+# CONFIG_MCP320X is not set
+# CONFIG_MCP3422 is not set
+# CONFIG_MCP3911 is not set
+# CONFIG_MCP4018 is not set
+# CONFIG_MCP41010 is not set
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4531 is not set
+# CONFIG_MCP4725 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_MCPM is not set
+# CONFIG_MCTP is not set
+# CONFIG_MD is not set
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+# CONFIG_MDIO_DEVICE is not set
+# CONFIG_MDIO_DEVRES is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_IPQ4019 is not set
+# CONFIG_MDIO_IPQ8064 is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_OCTEON is not set
+# CONFIG_MDIO_THUNDER is not set
+# CONFIG_MDIO_XPCS is not set
+# CONFIG_MD_BITMAP_FILE is not set
+# CONFIG_MD_FAULTY is not set
+# CONFIG_MEDIATEK_GE_PHY is not set
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_ATTACH is not set
+# CONFIG_MEDIA_CAMERA_SUPPORT is not set
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+# CONFIG_MEDIA_CONTROLLER is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+# CONFIG_MEDIA_PCI_SUPPORT is not set
+# CONFIG_MEDIA_PLATFORM_DRIVERS is not set
+# CONFIG_MEDIA_PLATFORM_SUPPORT is not set
+# CONFIG_MEDIA_RADIO_SUPPORT is not set
+# CONFIG_MEDIA_RC_SUPPORT is not set
+# CONFIG_MEDIA_SDR_SUPPORT is not set
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+# CONFIG_MEDIA_SUPPORT is not set
+# CONFIG_MEDIA_SUPPORT_FILTER is not set
+# CONFIG_MEDIA_TEST_SUPPORT is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_USB_SUPPORT is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+CONFIG_MEMBARRIER=y
+# CONFIG_MEMORY is not set
+# CONFIG_MEMORY_FAILURE is not set
+# CONFIG_MEMORY_HOTPLUG is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_MEMTEST is not set
+# CONFIG_MEN_A21_WDT is not set
+# CONFIG_MESON_SM is not set
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_AC100 is not set
+# CONFIG_MFD_ACT8945A is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_AXP20X is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_MFD_CS42L43_I2C is not set
+# CONFIG_MFD_CS5535 is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_EXYNOS_LPASS is not set
+# CONFIG_MFD_GATEWORKS_GSC is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
+# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_LOCHNAGAR is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX597X is not set
+# CONFIG_MFD_MAX77620 is not set
+# CONFIG_MFD_MAX77650 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_NTXEC is not set
+# CONFIG_MFD_OCELOT is not set
+# CONFIG_MFD_OMAP_USB_HOST is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_PM8921_CORE is not set
+# CONFIG_MFD_PM8XXX is not set
+# CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_RK808 is not set
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_ROHM_BD70528 is not set
+# CONFIG_MFD_ROHM_BD71828 is not set
+# CONFIG_MFD_ROHM_BD718XX is not set
+# CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RTSX_PCI is not set
+# CONFIG_MFD_RTSX_USB is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_SL28CPLD is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SMPRO is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_MFD_STMFX is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_STPMIC1 is not set
+# CONFIG_MFD_SYSCON is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TI_LP87565 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS65219 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS6594_I2C is not set
+# CONFIG_MFD_TPS6594_SPI is not set
+# CONFIG_MFD_TPS68470 is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MHI_BUS is not set
+# CONFIG_MHI_BUS_EP is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_MICROCHIP_KSZ is not set
+# CONFIG_MICROCHIP_PHY is not set
+# CONFIG_MICROCHIP_PIT64B is not set
+# CONFIG_MICROCHIP_T1S_PHY is not set
+# CONFIG_MICROCHIP_T1_PHY is not set
+# CONFIG_MICROSEMI_PHY is not set
+# CONFIG_MICROSOFT_MANA is not set
+# CONFIG_MIGRATION is not set
+CONFIG_MII=y
+# CONFIG_MIKROTIK is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_MIPS_CDMM is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MIPS_FPU_EMULATOR is not set
+# CONFIG_MIPS_FP_SUPPORT is not set
+# CONFIG_MIPS_GENERIC is not set
+# CONFIG_MIPS_GENERIC_KERNEL is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+# CONFIG_MIPS_PARAVIRT is not set
+# CONFIG_MIPS_PLATFORM_DEVICES is not set
+# CONFIG_MIPS_SEAD3 is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_MISDN is not set
+# CONFIG_MISDN_AVMFRITZ is not set
+# CONFIG_MISDN_HFCPCI is not set
+# CONFIG_MISDN_HFCUSB is not set
+# CONFIG_MISDN_INFINEON is not set
+# CONFIG_MISDN_NETJET is not set
+# CONFIG_MISDN_SPEEDFAX is not set
+# CONFIG_MISDN_W6692 is not set
+# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
+# CONFIG_MKISS is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX5_CORE is not set
+# CONFIG_MLX5_EN_MACSEC is not set
+# CONFIG_MLX5_SF is not set
+# CONFIG_MLX90614 is not set
+# CONFIG_MLX90632 is not set
+# CONFIG_MLXFW is not set
+# CONFIG_MLXSW_CORE is not set
+# CONFIG_MLX_CPLD_PLATFORM is not set
+# CONFIG_MLX_PLATFORM is not set
+# CONFIG_MMA7455_I2C is not set
+# CONFIG_MMA7455_SPI is not set
+# CONFIG_MMA7660 is not set
+# CONFIG_MMA8452 is not set
+# CONFIG_MMA9551 is not set
+# CONFIG_MMA9553 is not set
+# CONFIG_MMC is not set
+# CONFIG_MMC35240 is not set
+# CONFIG_MMC_ARMMMCI is not set
+# CONFIG_MMC_AU1X is not set
+# CONFIG_MMC_BLOCK is not set
+CONFIG_MMC_BLOCK_MINORS=8
+# CONFIG_MMC_CAVIUM_THUNDERX is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_DW_ROCKCHIP is not set
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_JZ4740 is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MMC_MVSDIO is not set
+# CONFIG_MMC_S3C is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_ACPI is not set
+# CONFIG_MMC_SDHCI_AM654 is not set
+# CONFIG_MMC_SDHCI_BCM_KONA is not set
+# CONFIG_MMC_SDHCI_CADENCE is not set
+# CONFIG_MMC_SDHCI_F_SDH30 is not set
+# CONFIG_MMC_SDHCI_IPROC is not set
+# CONFIG_MMC_SDHCI_MILBEAUT is not set
+# CONFIG_MMC_SDHCI_MSM is not set
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_OF_ASPEED is not set
+# CONFIG_MMC_SDHCI_OF_AT91 is not set
+# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
+# CONFIG_MMC_SDHCI_OF_ESDHC is not set
+# CONFIG_MMC_SDHCI_OF_HLWD is not set
+# CONFIG_MMC_SDHCI_OMAP is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_S3C is not set
+# CONFIG_MMC_SDHCI_XENON is not set
+# CONFIG_MMC_SDRICOH_CS is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_STM32_SDMMC is not set
+# CONFIG_MMC_TEST is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMIOTRACE is not set
+CONFIG_MMU=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+CONFIG_MODULES=y
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_DEBUG is not set
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_MODULE_STRIPPED=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MOST is not set
+# CONFIG_MOTORCOMM_PHY is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_PS2_FOCALTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_MOXTET is not set
+# CONFIG_MPL115 is not set
+# CONFIG_MPL115_I2C is not set
+# CONFIG_MPL115_SPI is not set
+# CONFIG_MPL3115 is not set
+# CONFIG_MPLS is not set
+# CONFIG_MPTCP is not set
+# CONFIG_MPU3050_I2C is not set
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_MS5611 is not set
+# CONFIG_MS5637 is not set
+# CONFIG_MSA311 is not set
+# CONFIG_MSCC_OCELOT_SWITCH is not set
+# CONFIG_MSDOS_FS is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_MSE102X is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_MSI_LAPTOP is not set
+# CONFIG_MST_IRQ is not set
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_HYPERBUS is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_LATCH_ADDR is not set
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_LPDDR2_NVM is not set
+# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MCHP23K256 is not set
+# CONFIG_MTD_MCHP48L640 is not set
+# CONFIG_MTD_MT81xx_NOR is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_MYLOADER_PARTS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_NAND_AMS_DELTA is not set
+# CONFIG_MTD_NAND_AR934X is not set
+# CONFIG_MTD_NAND_AR934X_HW_ECC is not set
+# CONFIG_MTD_NAND_ARASAN is not set
+# CONFIG_MTD_NAND_ATMEL is not set
+# CONFIG_MTD_NAND_AU1550 is not set
+# CONFIG_MTD_NAND_BCH is not set
+# CONFIG_MTD_NAND_BF5XX is not set
+# CONFIG_MTD_NAND_BRCMNAND is not set
+# CONFIG_MTD_NAND_CADENCE is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_CM_X270 is not set
+# CONFIG_MTD_NAND_CS553X is not set
+# CONFIG_MTD_NAND_DAVINCI is not set
+# CONFIG_MTD_NAND_DENALI is not set
+# CONFIG_MTD_NAND_DENALI_DT is not set
+# CONFIG_MTD_NAND_DENALI_PCI is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_DOCG4 is not set
+# CONFIG_MTD_NAND_ECC is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_NAND_ECC_MXIC is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_ECC_SW_BCH is not set
+# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
+# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+# CONFIG_MTD_NAND_FSL_IFC is not set
+# CONFIG_MTD_NAND_FSL_UPM is not set
+# CONFIG_MTD_NAND_FSMC is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_GPMI_NAND is not set
+# CONFIG_MTD_NAND_HISI504 is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_INTEL_LGM is not set
+# CONFIG_MTD_NAND_JZ4740 is not set
+# CONFIG_MTD_NAND_MPC5121_NFC is not set
+# CONFIG_MTD_NAND_MTK is not set
+# CONFIG_MTD_NAND_MTK_BMT is not set
+# CONFIG_MTD_NAND_MXC is not set
+# CONFIG_MTD_NAND_MXIC is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_NDFC is not set
+# CONFIG_MTD_NAND_NUC900 is not set
+# CONFIG_MTD_NAND_OMAP2 is not set
+# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
+# CONFIG_MTD_NAND_ORION is not set
+# CONFIG_MTD_NAND_PASEMI is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_PXA3xx is not set
+# CONFIG_MTD_NAND_RB4XX is not set
+# CONFIG_MTD_NAND_RB750 is not set
+# CONFIG_MTD_NAND_RB91X is not set
+# CONFIG_MTD_NAND_RICOH is not set
+# CONFIG_MTD_NAND_S3C2410 is not set
+# CONFIG_MTD_NAND_SHARPSL is not set
+# CONFIG_MTD_NAND_SH_FLCTL is not set
+# CONFIG_MTD_NAND_SOCRATES is not set
+# CONFIG_MTD_NAND_TMIO is not set
+# CONFIG_MTD_NAND_TXX9NDFMC is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_PARTITIONED_MASTER is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PCMCIA is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PHYSMAP_GEMINI is not set
+# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
+# CONFIG_MTD_PHYSMAP_IXP4XX is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set
+# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set
+# CONFIG_MTD_PHYSMAP_VERSATILE is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_RAW_NAND is not set
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_ROM is not set
+CONFIG_MTD_ROOTFS_ROOT_DEV=y
+# CONFIG_MTD_ROUTERBOOT_PARTS is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_SPINAND_MT29F is not set
+# CONFIG_MTD_SPI_NAND is not set
+# CONFIG_MTD_SPI_NOR is not set
+CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
+# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
+# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=4096
+CONFIG_MTD_SPLIT=y
+# CONFIG_MTD_SPLIT_BCM63XX_FW is not set
+# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set
+# CONFIG_MTD_SPLIT_BRNIMAGE_FW is not set
+# CONFIG_MTD_SPLIT_ELF_FW is not set
+# CONFIG_MTD_SPLIT_EVA_FW is not set
+# CONFIG_MTD_SPLIT_FIRMWARE is not set
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware"
+# CONFIG_MTD_SPLIT_FIT_FW is not set
+# CONFIG_MTD_SPLIT_H3C_VFS is not set
+# CONFIG_MTD_SPLIT_JIMAGE_FW is not set
+# CONFIG_MTD_SPLIT_LZMA_FW is not set
+# CONFIG_MTD_SPLIT_MINOR_FW is not set
+# CONFIG_MTD_SPLIT_SEAMA_FW is not set
+# CONFIG_MTD_SPLIT_SEIL_FW is not set
+CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y
+CONFIG_MTD_SPLIT_SUPPORT=y
+# CONFIG_MTD_SPLIT_TPLINK_FW is not set
+# CONFIG_MTD_SPLIT_TRX_FW is not set
+# CONFIG_MTD_SPLIT_UIMAGE_FW is not set
+# CONFIG_MTD_SPLIT_WRGG_FW is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SWAP is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UIMAGE_SPLIT is not set
+# CONFIG_MTD_VIRT_CONCAT is not set
+# CONFIG_MTK_MMC is not set
+# CONFIG_MTK_MMSYS is not set
+CONFIG_MULTIUSER=y
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_MUX_ADG792A is not set
+# CONFIG_MUX_ADGS1408 is not set
+# CONFIG_MUX_MMIO is not set
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_MVMDIO is not set
+# CONFIG_MVNETA_BM is not set
+# CONFIG_MVSW61XX_PHY is not set
+# CONFIG_MVSWITCH_PHY is not set
+# CONFIG_MV_XOR_V2 is not set
+# CONFIG_MWAVE is not set
+# CONFIG_MWL8K is not set
+# CONFIG_MXC4005 is not set
+# CONFIG_MXC6255 is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NAU7802 is not set
+# CONFIG_NBPFAXI_DMA is not set
+# CONFIG_NCN26000_PHY is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_ND_BLK is not set
+# CONFIG_NE2000 is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NEC_MARKEINS is not set
+CONFIG_NET=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVSIM is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_EGRESS is not set
+# CONFIG_NETFILTER_INGRESS is not set
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NETFILTER_NETLINK_ACCT is not set
+# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
+# CONFIG_NETFILTER_NETLINK_HOOK is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NETFILTER_NETLINK_OSF is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_NETFILTER_XTABLES_COMPAT is not set
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_BPF is not set
+# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ECN is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_HL is not set
+# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+# CONFIG_NETFILTER_XT_TARGET_LOG is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set
+# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+# CONFIG_NETFS_STATS is not set
+# CONFIG_NETFS_SUPPORT is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_NETLINK_MMAP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NETROM is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NET_9P is not set
+# CONFIG_NET_ACT_BPF is not set
+# CONFIG_NET_ACT_CSUM is not set
+# CONFIG_NET_ACT_CT is not set
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_GATE is not set
+# CONFIG_NET_ACT_IFE is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_MPLS is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_POLICE is not set
+# CONFIG_NET_ACT_SAMPLE is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_ACT_SKBMOD is not set
+# CONFIG_NET_ACT_TUNNEL_KEY is not set
+# CONFIG_NET_ACT_VLAN is not set
+CONFIG_NET_CADENCE=y
+# CONFIG_NET_CALXEDA_XGMAC is not set
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_BPF is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_FLOWER is not set
+# CONFIG_NET_CLS_FW is not set
+CONFIG_NET_CLS_IND=y
+# CONFIG_NET_CLS_MATCHALL is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_U32 is not set
+CONFIG_NET_CORE=y
+# CONFIG_NET_DEVLINK is not set
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_NET_DSA_AR9331 is not set
+# CONFIG_NET_DSA_BCM_SF2 is not set
+# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
+# CONFIG_NET_DSA_LEGACY is not set
+# CONFIG_NET_DSA_LOOP is not set
+# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set
+# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
+# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
+# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
+# CONFIG_NET_DSA_MSCC_SEVILLE is not set
+# CONFIG_NET_DSA_MT7530 is not set
+# CONFIG_NET_DSA_MT7530_MDIO is not set
+# CONFIG_NET_DSA_MT7530_MMIO is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MV88E6123_61_65 is not set
+# CONFIG_NET_DSA_MV88E6131 is not set
+# CONFIG_NET_DSA_MV88E6171 is not set
+# CONFIG_NET_DSA_MV88E6352 is not set
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
+# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
+# CONFIG_NET_DSA_QCA8K is not set
+# CONFIG_NET_DSA_REALTEK_SMI is not set
+# CONFIG_NET_DSA_SJA1105 is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
+# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
+# CONFIG_NET_DSA_TAG_8021Q is not set
+# CONFIG_NET_DSA_TAG_AR9331 is not set
+# CONFIG_NET_DSA_TAG_BRCM is not set
+# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set
+# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set
+# CONFIG_NET_DSA_TAG_DSA is not set
+# CONFIG_NET_DSA_TAG_DSA_COMMON is not set
+# CONFIG_NET_DSA_TAG_EDSA is not set
+# CONFIG_NET_DSA_TAG_GSWIP is not set
+# CONFIG_NET_DSA_TAG_HELLCREEK is not set
+# CONFIG_NET_DSA_TAG_KSZ is not set
+# CONFIG_NET_DSA_TAG_LAN9303 is not set
+# CONFIG_NET_DSA_TAG_MTK is not set
+# CONFIG_NET_DSA_TAG_NONE is not set
+# CONFIG_NET_DSA_TAG_OCELOT is not set
+# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
+# CONFIG_NET_DSA_TAG_QCA is not set
+# CONFIG_NET_DSA_TAG_RTL4_A is not set
+# CONFIG_NET_DSA_TAG_RTL8_4 is not set
+# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
+# CONFIG_NET_DSA_TAG_SJA1105 is not set
+# CONFIG_NET_DSA_TAG_TRAILER is not set
+# CONFIG_NET_DSA_TAG_XRS700X is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
+# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
+# CONFIG_NET_DSA_XRS700X_I2C is not set
+# CONFIG_NET_DSA_XRS700X_MDIO is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_EMATCH_CANID is not set
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_IPT is not set
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_TEXT is not set
+# CONFIG_NET_EMATCH_U32 is not set
+# CONFIG_NET_FAILOVER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_NET_IPGRE_BROADCAST=y
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_IP_TUNNEL is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_NET_KEY_MIGRATE is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_NET_MEDIATEK_STAR_EMAC is not set
+# CONFIG_NET_MPLS_GSO is not set
+# CONFIG_NET_NCSI is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_NET_PTP_CLASSIFY is not set
+CONFIG_NET_RX_BUSY_POLL=y
+# CONFIG_NET_SB1000 is not set
+CONFIG_NET_SCHED=y
+# CONFIG_NET_SCH_ATM is not set
+# CONFIG_NET_SCH_CAKE is not set
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_CBS is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_CODEL is not set
+# CONFIG_NET_SCH_DEFAULT is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_ETF is not set
+# CONFIG_NET_SCH_ETS is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_NET_SCH_FQ is not set
+CONFIG_NET_SCH_FQ_CODEL=y
+# CONFIG_NET_SCH_FQ_PIE is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_HHF is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_INGRESS is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_PIE is not set
+# CONFIG_NET_SCH_PLUG is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_SKBPRIO is not set
+# CONFIG_NET_SCH_TAPRIO is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCTPPROBE is not set
+# CONFIG_NET_SELFTESTS is not set
+# CONFIG_NET_SOCK_MSG is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_TC_SKB_EXT is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_NET_UDP_TUNNEL is not set
+CONFIG_NET_VENDOR_3COM=y
+CONFIG_NET_VENDOR_8390=y
+CONFIG_NET_VENDOR_ADAPTEC=y
+# CONFIG_NET_VENDOR_ADI is not set
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_NET_VENDOR_ALACRITECH=y
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_NET_VENDOR_AMAZON=y
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_NET_VENDOR_AQUANTIA=y
+CONFIG_NET_VENDOR_ARC=y
+CONFIG_NET_VENDOR_ASIX=y
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_NET_VENDOR_AURORA=y
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_NET_VENDOR_BROCADE=y
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_NET_VENDOR_CIRRUS=y
+CONFIG_NET_VENDOR_CISCO=y
+CONFIG_NET_VENDOR_CORTINA=y
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_NET_VENDOR_DEC=y
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_NET_VENDOR_EMULEX=y
+CONFIG_NET_VENDOR_ENGLEDER=y
+CONFIG_NET_VENDOR_EXAR=y
+CONFIG_NET_VENDOR_EZCHIP=y
+CONFIG_NET_VENDOR_FARADAY=y
+CONFIG_NET_VENDOR_FREESCALE=y
+CONFIG_NET_VENDOR_FUJITSU=y
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_NET_VENDOR_GOOGLE=y
+CONFIG_NET_VENDOR_HISILICON=y
+CONFIG_NET_VENDOR_HP=y
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_IBM=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_NET_VENDOR_MICREL=y
+CONFIG_NET_VENDOR_MICROCHIP=y
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_NETERION=y
+CONFIG_NET_VENDOR_NETRONOME=y
+CONFIG_NET_VENDOR_NI=y
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_NET_VENDOR_QLOGIC=y
+CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_NET_VENDOR_RDC=y
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_NET_VENDOR_RENESAS=y
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_NET_VENDOR_SAMSUNG=y
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SILAN=y
+CONFIG_NET_VENDOR_SIS=y
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_NET_VENDOR_SOCIONEXT=y
+CONFIG_NET_VENDOR_SOLARFLARE=y
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_NET_VENDOR_SUN=y
+CONFIG_NET_VENDOR_SYNOPSYS=y
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_NET_VENDOR_TI=y
+CONFIG_NET_VENDOR_TOSHIBA=y
+CONFIG_NET_VENDOR_VERTEXCOM=y
+CONFIG_NET_VENDOR_VIA=y
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_NET_VENDOR_WIZNET=y
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_NET_VENDOR_XIRCOM=y
+# CONFIG_NET_VRF is not set
+# CONFIG_NET_XGENE is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_NFC is not set
+# CONFIG_NFP is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V2 is not set
+# CONFIG_NFSD_V2_ACL is not set
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+# CONFIG_NFS_ACL_SUPPORT is not set
+CONFIG_NFS_COMMON=y
+# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_FSCACHE is not set
+# CONFIG_NFS_SWAP is not set
+# CONFIG_NFS_V2 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_V4_1 is not set
+# CONFIG_NFTL is not set
+# CONFIG_NFT_BRIDGE_META is not set
+# CONFIG_NFT_BRIDGE_REJECT is not set
+# CONFIG_NFT_CONNLIMIT is not set
+# CONFIG_NFT_DUP_IPV4 is not set
+# CONFIG_NFT_DUP_IPV6 is not set
+# CONFIG_NFT_FIB_IPV4 is not set
+# CONFIG_NFT_FIB_IPV6 is not set
+# CONFIG_NFT_FIB_NETDEV is not set
+# CONFIG_NFT_FLOW_OFFLOAD is not set
+# CONFIG_NFT_OBJREF is not set
+# CONFIG_NFT_OSF is not set
+# CONFIG_NFT_REJECT_NETDEV is not set
+# CONFIG_NFT_RT is not set
+# CONFIG_NFT_SET_BITMAP is not set
+# CONFIG_NFT_SOCKET is not set
+# CONFIG_NFT_SYNPROXY is not set
+# CONFIG_NFT_TPROXY is not set
+# CONFIG_NFT_TUNNEL is not set
+# CONFIG_NFT_XFRM is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_BRIDGE is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IPV4 is not set
+# CONFIG_NF_CONNTRACK_IPV6 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_LABELS is not set
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+CONFIG_NF_CONNTRACK_PROCFS=y
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SECMARK is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CONNTRACK_TIMEOUT is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CONNTRACK_ZONES is not set
+# CONFIG_NF_CT_NETLINK is not set
+# CONFIG_NF_CT_NETLINK_HELPER is not set
+# CONFIG_NF_CT_NETLINK_TIMEOUT is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_GRE is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_NF_DUP_IPV4 is not set
+# CONFIG_NF_DUP_IPV6 is not set
+# CONFIG_NF_FLOW_TABLE is not set
+# CONFIG_NF_FLOW_TABLE_PROCFS is not set
+# CONFIG_NF_LOG_ARP is not set
+CONFIG_NF_LOG_IPV4=y
+CONFIG_NF_LOG_IPV6=y
+CONFIG_NF_LOG_SYSLOG=y
+# CONFIG_NF_NAT is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_FTP is not set
+# CONFIG_NF_NAT_H323 is not set
+# CONFIG_NF_NAT_IPV6 is not set
+# CONFIG_NF_NAT_IRC is not set
+CONFIG_NF_NAT_MASQUERADE_IPV4=y
+CONFIG_NF_NAT_MASQUERADE_IPV6=y
+# CONFIG_NF_NAT_NEEDED is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_PROTO_GRE is not set
+# CONFIG_NF_NAT_SIP is not set
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_REJECT_IPV4 is not set
+# CONFIG_NF_REJECT_IPV6 is not set
+# CONFIG_NF_SOCKET_IPV4 is not set
+# CONFIG_NF_SOCKET_IPV6 is not set
+# CONFIG_NF_TABLES is not set
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_TABLES_BRIDGE=y
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NF_TABLES_NETDEV=y
+# CONFIG_NF_TABLES_SET is not set
+# CONFIG_NF_TPROXY_IPV4 is not set
+# CONFIG_NF_TPROXY_IPV6 is not set
+# CONFIG_NGBE is not set
+# CONFIG_NI65 is not set
+# CONFIG_NI903X_WDT is not set
+# CONFIG_NIC7018_WDT is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NIU is not set
+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
+CONFIG_NLATTR=y
+# CONFIG_NLMON is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLS is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+# CONFIG_NLS_UCS2_UTILS is not set
+# CONFIG_NLS_UTF8 is not set
+CONFIG_NMI_LOG_BUF_SHIFT=13
+# CONFIG_NOA1305 is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_NORTEL_HERMES is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_NO_BOOTMEM is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_NO_HZ_FULL is not set
+# CONFIG_NO_HZ_IDLE is not set
+CONFIG_NR_CPUS=256
+CONFIG_NR_LRU_GENS=7
+# CONFIG_NS83820 is not set
+# CONFIG_NTB is not set
+# CONFIG_NTFS3_64BIT_CLUSTER is not set
+# CONFIG_NTFS3_FS is not set
+# CONFIG_NTFS3_LZX_XPRESS is not set
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_NTP_PPS is not set
+# CONFIG_NULL_TTY is not set
+# CONFIG_NUMA is not set
+# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
+# CONFIG_NVM is not set
+# CONFIG_NVMEM is not set
+# CONFIG_NVMEM_BCM_OCOTP is not set
+# CONFIG_NVMEM_IMX_OCOTP is not set
+# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
+# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
+# CONFIG_NVMEM_NINTENDO_OTP is not set
+# CONFIG_NVMEM_REBOOT_MODE is not set
+CONFIG_NVMEM_RMEM=y
+# CONFIG_NVMEM_ROCKCHIP_EFUSE is not set
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+# CONFIG_NVMEM_SYSFS is not set
+# CONFIG_NVME_AUTH is not set
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TARGET is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_VERBOSE_ERRORS is not set
+# CONFIG_NVRAM is not set
+# CONFIG_NV_TCO is not set
+# CONFIG_NXP_C45_TJA11XX_PHY is not set
+# CONFIG_NXP_CBTX_PHY is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_N_GSM is not set
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_OBS600 is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_OCTEONTX2_AF is not set
+# CONFIG_OCTEONTX2_PF is not set
+# CONFIG_OF_MDIO is not set
+# CONFIG_OF_OVERLAY is not set
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_UNITTEST is not set
+# CONFIG_OID_REGISTRY is not set
+# CONFIG_OMAP2_DSS_DEBUG is not set
+# CONFIG_OMAP2_DSS_DEBUGFS is not set
+# CONFIG_OMAP2_DSS_SDI is not set
+# CONFIG_OMAP_OCP2SCP is not set
+# CONFIG_OMAP_USB2 is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_OPEN_DICE is not set
+# CONFIG_OPROFILE is not set
+# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set
+# CONFIG_OPT3001 is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ORION_WATCHDOG is not set
+# CONFIG_OSF_PARTITION is not set
+CONFIG_OVERLAY_FS=y
+# CONFIG_OVERLAY_FS_DEBUG is not set
+# CONFIG_OVERLAY_FS_INDEX is not set
+# CONFIG_OVERLAY_FS_METACOPY is not set
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+# CONFIG_OWL_LOADER is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_PA12203001 is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+# CONFIG_PACKING is not set
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_PAGE_POOL_STATS is not set
+# CONFIG_PAGE_REPORTING is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_LESS_THAN_64KB is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
+# CONFIG_PALMAS_GPADC is not set
+# CONFIG_PANASONIC_LAPTOP is not set
+# CONFIG_PANEL is not set
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_ON_OOPS_VALUE=1
+CONFIG_PANIC_TIMEOUT=1
+# CONFIG_PANTHERLORD_FF is not set
+# CONFIG_PARAVIRT is not set
+# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PARPORT_1284 is not set
+# CONFIG_PARPORT_AX88796 is not set
+# CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_PC is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5535 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IMX is not set
+# CONFIG_PATA_ISAPNP is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OCTEON_CF is not set
+# CONFIG_PATA_OF_PLATFORM is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PARPORT is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PC104 is not set
+# CONFIG_PC300TOO is not set
+# CONFIG_PCCARD is not set
+# CONFIG_PCH_DMA is not set
+# CONFIG_PCH_GBE is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_PCI is not set
+# CONFIG_PCI200SYN is not set
+# CONFIG_PCIEAER is not set
+# CONFIG_PCIEAER_INJECT is not set
+# CONFIG_PCIEASPM is not set
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_PCIE_AL is not set
+# CONFIG_PCIE_ALTERA is not set
+# CONFIG_PCIE_ARMADA_8K is not set
+CONFIG_PCIE_BUS_DEFAULT=y
+# CONFIG_PCIE_BUS_PEER2PEER is not set
+# CONFIG_PCIE_BUS_PERFORMANCE is not set
+# CONFIG_PCIE_BUS_SAFE is not set
+# CONFIG_PCIE_BUS_TUNE_OFF is not set
+# CONFIG_PCIE_BW is not set
+# CONFIG_PCIE_CADENCE_HOST is not set
+# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_DW is not set
+# CONFIG_PCIE_DW_HOST is not set
+# CONFIG_PCIE_DW_PLAT is not set
+# CONFIG_PCIE_DW_PLAT_HOST is not set
+# CONFIG_PCIE_ECRC is not set
+# CONFIG_PCIE_IPROC is not set
+# CONFIG_PCIE_KIRIN is not set
+# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
+# CONFIG_PCIE_MICROCHIP_HOST is not set
+# CONFIG_PCIE_PTM is not set
+# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
+# CONFIG_PCIE_XILINX is not set
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_PCI_ATMEL is not set
+# CONFIG_PCI_CNB20LE_QUIRK is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
+# CONFIG_PCI_DYNAMIC_OF_NODES is not set
+# CONFIG_PCI_ENDPOINT is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
+# CONFIG_PCI_FTPCI100 is not set
+# CONFIG_PCI_HERMES is not set
+# CONFIG_PCI_HISI is not set
+# CONFIG_PCI_HOST_GENERIC is not set
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_J721E_HOST is not set
+# CONFIG_PCI_LAYERSCAPE is not set
+# CONFIG_PCI_MESON is not set
+# CONFIG_PCI_MSI is not set
+# CONFIG_PCI_PASID is not set
+# CONFIG_PCI_PF_STUB is not set
+# CONFIG_PCI_PRI is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_SW_SWITCHTEC is not set
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCI_V3_SEMI is not set
+# CONFIG_PCI_XGENE is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_ATMEL is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_HERMES is not set
+# CONFIG_PCMCIA_LOAD_CIS is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_SPECTRUM is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_XIRCOM is not set
+# CONFIG_PCNET32 is not set
+CONFIG_PCPU_DEV_REFCNT=y
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PCS_XPCS is not set
+# CONFIG_PD6729 is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_PDS_CORE is not set
+# CONFIG_PECI is not set
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_EVENTS_AMD_POWER is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_PER_VMA_LOCK_STATS is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_PHONET is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_PHYLIB_LEDS is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+# CONFIG_PHY_CADENCE_DP is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_DPHY_RX is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+# CONFIG_PHY_CPCAP_USB is not set
+# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
+# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
+# CONFIG_PHY_FSL_IMX8MQ_USB is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
+# CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_MTK_HDMI is not set
+# CONFIG_PHY_MVEBU_CP110_UTMI is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_QCOM_DWC3 is not set
+# CONFIG_PHY_QCOM_USB_HS is not set
+# CONFIG_PHY_QCOM_USB_HSIC is not set
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
+# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+# CONFIG_PHY_SAMSUNG_USB2 is not set
+# CONFIG_PHY_TUSB1210 is not set
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PI433 is not set
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_PID_NS is not set
+CONFIG_PINCONF=y
+# CONFIG_PINCTRL is not set
+# CONFIG_PINCTRL_AMD is not set
+# CONFIG_PINCTRL_AXP209 is not set
+# CONFIG_PINCTRL_CEDARFORK is not set
+# CONFIG_PINCTRL_CY8C95X0 is not set
+# CONFIG_PINCTRL_EXYNOS is not set
+# CONFIG_PINCTRL_EXYNOS5440 is not set
+# CONFIG_PINCTRL_ICELAKE is not set
+# CONFIG_PINCTRL_INGENIC is not set
+# CONFIG_PINCTRL_MCP23S08 is not set
+CONFIG_PINCTRL_MICROCHIP_SGPIO=y
+# CONFIG_PINCTRL_MSM8X74 is not set
+# CONFIG_PINCTRL_MT6779 is not set
+# CONFIG_PINCTRL_MT8167 is not set
+# CONFIG_PINCTRL_MT8192 is not set
+# CONFIG_PINCTRL_MTK_V2 is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_ROCKCHIP is not set
+CONFIG_PINCTRL_SINGLE=y
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
+# CONFIG_PING is not set
+CONFIG_PINMUX=y
+# CONFIG_PKCS7_MESSAGE_PARSER is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_PL310_ERRATA_753970 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+# CONFIG_PL320_MBOX is not set
+# CONFIG_PL330_DMA is not set
+# CONFIG_PLATFORM_MHU is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_PLIP is not set
+# CONFIG_PLX_DMA is not set
+# CONFIG_PLX_HERMES is not set
+# CONFIG_PM is not set
+# CONFIG_PMBUS is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMS7003 is not set
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_DEBUG is not set
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_PM_WAKELOCKS is not set
+# CONFIG_POSIX_CPU_TIMERS_TASK_WORK is not set
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_TIMERS=y
+# CONFIG_POWERCAP is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_RESET_BRCMKONA is not set
+# CONFIG_POWER_RESET_BRCMSTB is not set
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LINKSTATION is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_PIIX4_POWEROFF is not set
+# CONFIG_POWER_RESET_REGULATOR is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
+# CONFIG_POWER_RESET_VERSATILE is not set
+# CONFIG_POWER_RESET_XGENE is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_POWER_SUPPLY_HWMON is not set
+# CONFIG_PPC4xx_GPIO is not set
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+# CONFIG_PPC_EMULATED_STATS is not set
+# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set
+# CONFIG_PPP is not set
+# CONFIG_PPPOATM is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOE_HASH_BITS_4 is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_DEFLATE is not set
+CONFIG_PPP_FILTER=y
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPS is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_PARPORT is not set
+# CONFIG_PPS_DEBUG is not set
+# CONFIG_PPTP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+# CONFIG_PREEMPTIRQ_EVENTS is not set
+# CONFIG_PREEMPT_BUILD is not set
+# CONFIG_PREEMPT_DYNAMIC is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_NONE_BUILD is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PRESTERA is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_PRINTK=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_PRINTK_NMI=y
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_TIME is not set
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_PRISM2_USB is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+# CONFIG_PROC_STRIPPED is not set
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILING is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_PROVE_RAW_LOCK_NESTING is not set
+# CONFIG_PROVE_RCU is not set
+# CONFIG_PROVE_RCU_LIST is not set
+# CONFIG_PROVE_RCU_REPEATEDLY is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_PSB6970_PHY is not set
+# CONFIG_PSE_CONTROLLER is not set
+# CONFIG_PSI is not set
+# CONFIG_PSTORE is not set
+# CONFIG_PSTORE_842_COMPRESS is not set
+# CONFIG_PSTORE_BLK is not set
+# CONFIG_PSTORE_CONSOLE is not set
+# CONFIG_PSTORE_DEFAULT_KMSG_BYTES is not set
+# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+# CONFIG_PSTORE_PMSG is not set
+# CONFIG_PSTORE_ZSTD_COMPRESS is not set
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_PTP_1588_CLOCK is not set
+# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
+# CONFIG_PTP_1588_CLOCK_IDTCM is not set
+# CONFIG_PTP_1588_CLOCK_IXP46X is not set
+# CONFIG_PTP_1588_CLOCK_KVM is not set
+# CONFIG_PTP_1588_CLOCK_MOCK is not set
+# CONFIG_PTP_1588_CLOCK_OCP is not set
+# CONFIG_PTP_1588_CLOCK_OPTIONAL is not set
+# CONFIG_PTP_1588_CLOCK_PCH is not set
+# CONFIG_PTP_1588_CLOCK_VMW is not set
+# CONFIG_PUBLIC_KEY_ALGO_RSA is not set
+# CONFIG_PVPANIC is not set
+# CONFIG_PWM is not set
+# CONFIG_PWM_ATMEL_TCB is not set
+# CONFIG_PWM_CLK is not set
+# CONFIG_PWM_DEBUG is not set
+# CONFIG_PWM_DWC is not set
+# CONFIG_PWM_FSL_FTM is not set
+# CONFIG_PWM_PCA9685 is not set
+# CONFIG_PWM_ROCKCHIP is not set
+CONFIG_PWRSEQ_EMMC=y
+# CONFIG_PWRSEQ_SD8787 is not set
+CONFIG_PWRSEQ_SIMPLE=y
+# CONFIG_QCA7000 is not set
+# CONFIG_QCA7000_SPI is not set
+# CONFIG_QCA7000_UART is not set
+# CONFIG_QCOM_EMAC is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
+# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
+# CONFIG_QCOM_HIDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
+# CONFIG_QCOM_SCM is not set
+# CONFIG_QCOM_SPMI_ADC5 is not set
+# CONFIG_QCOM_SPMI_IADC is not set
+# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
+# CONFIG_QCOM_SPMI_VADC is not set
+# CONFIG_QED is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_QLGE is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_QORIQ_CPUFREQ is not set
+# CONFIG_QORIQ_THERMAL is not set
+# CONFIG_QRTR is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_QUEUED_LOCK_STAT is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_QUOTA_DEBUG is not set
+# CONFIG_R3964 is not set
+# CONFIG_R6040 is not set
+# CONFIG_R8169 is not set
+# CONFIG_R8188EU is not set
+# CONFIG_R8712U is not set
+# CONFIG_R8723AU is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_RADIO_AZTECH is not set
+# CONFIG_RADIO_CADET is not set
+# CONFIG_RADIO_GEMTEK is not set
+# CONFIG_RADIO_MAXIRADIO is not set
+# CONFIG_RADIO_RTRACK is not set
+# CONFIG_RADIO_RTRACK2 is not set
+# CONFIG_RADIO_SF16FMI is not set
+# CONFIG_RADIO_SF16FMR2 is not set
+# CONFIG_RADIO_TERRATEC is not set
+# CONFIG_RADIO_TRUST is not set
+# CONFIG_RADIO_TYPHOON is not set
+# CONFIG_RADIO_ZOLTRIX is not set
+# CONFIG_RAID6_PQ_BENCHMARK is not set
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_RALINK is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+# CONFIG_RANDOMIZE_BASE is not set
+# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_RANDOM_TRUST_BOOTLOADER=y
+CONFIG_RANDOM_TRUST_CPU=y
+# CONFIG_RAPIDIO is not set
+# CONFIG_RAS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_RCU_BOOST is not set
+# CONFIG_RCU_CPU_STALL_CPUTIME is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EQS_DEBUG is not set
+# CONFIG_RCU_EXPEDITE_BOOT is not set
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
+CONFIG_RCU_KTHREAD_PRIO=0
+CONFIG_RCU_NEED_SEGCBLIST=y
+# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+# CONFIG_RCU_SCALE_TEST is not set
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_RCU_STRICT_GRACE_PERIOD is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RC_ATI_REMOTE is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_RC_DECODERS is not set
+# CONFIG_RC_LOOPBACK is not set
+# CONFIG_RC_MAP is not set
+# CONFIG_RDS is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_ZSTD is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_READ_ONLY_THP_FOR_FS is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_REDWOOD is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+# CONFIG_REGMAP is not set
+# CONFIG_REGMAP_I2C is not set
+# CONFIG_REGMAP_MMIO is not set
+# CONFIG_REGMAP_SPI is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_88PG86X is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ANATOP is not set
+# CONFIG_REGULATOR_AW37503 is not set
+# CONFIG_REGULATOR_DA9121 is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_DA9211 is not set
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_REGULATOR_FAN53880 is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_ISL9305 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_LTC3589 is not set
+# CONFIG_REGULATOR_LTC3676 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
+# CONFIG_REGULATOR_MAX20411 is not set
+# CONFIG_REGULATOR_MAX77620 is not set
+# CONFIG_REGULATOR_MAX77826 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8893 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MCP16502 is not set
+# CONFIG_REGULATOR_MP5416 is not set
+# CONFIG_REGULATOR_MP8859 is not set
+# CONFIG_REGULATOR_MP886X is not set
+# CONFIG_REGULATOR_MPQ7920 is not set
+# CONFIG_REGULATOR_MT6311 is not set
+# CONFIG_REGULATOR_PCA9450 is not set
+# CONFIG_REGULATOR_PF8X00 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_PV88060 is not set
+# CONFIG_REGULATOR_PV88080 is not set
+# CONFIG_REGULATOR_PV88090 is not set
+# CONFIG_REGULATOR_PWM is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+# CONFIG_REGULATOR_RT4801 is not set
+# CONFIG_REGULATOR_RT4803 is not set
+# CONFIG_REGULATOR_RT5739 is not set
+# CONFIG_REGULATOR_RT6160 is not set
+# CONFIG_REGULATOR_RT6190 is not set
+# CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
+# CONFIG_REGULATOR_RTQ2208 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
+# CONFIG_REGULATOR_SLG51000 is not set
+# CONFIG_REGULATOR_SY8106A is not set
+# CONFIG_REGULATOR_SY8824X is not set
+# CONFIG_REGULATOR_SY8827N is not set
+# CONFIG_REGULATOR_TI_ABB is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS6287X is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS65132 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_VCTRL is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_FS_POSIX_ACL is not set
+# CONFIG_REISERFS_FS_SECURITY is not set
+CONFIG_REISERFS_FS_XATTR=y
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_RELAY is not set
+# CONFIG_RELOCATABLE is not set
+# CONFIG_REMOTEPROC is not set
+# CONFIG_RENESAS_PHY is not set
+# CONFIG_RESET_ATH79 is not set
+# CONFIG_RESET_BERLIN is not set
+# CONFIG_RESET_BRCMSTB_RESCAL is not set
+# CONFIG_RESET_CONTROLLER is not set
+# CONFIG_RESET_IMX7 is not set
+# CONFIG_RESET_INTEL_GW is not set
+# CONFIG_RESET_LANTIQ is not set
+# CONFIG_RESET_LPC18XX is not set
+# CONFIG_RESET_MCHP_SPARX5 is not set
+# CONFIG_RESET_MESON is not set
+# CONFIG_RESET_PISTACHIO is not set
+# CONFIG_RESET_SIMPLE is not set
+# CONFIG_RESET_SOCFPGA is not set
+# CONFIG_RESET_STM32 is not set
+# CONFIG_RESET_SUNXI is not set
+# CONFIG_RESET_TEGRA_BPMP is not set
+# CONFIG_RESET_TI_SYSCON is not set
+# CONFIG_RESET_TI_TPS380X is not set
+# CONFIG_RESET_ZYNQ is not set
+# CONFIG_RFD77402 is not set
+# CONFIG_RFD_FTL is not set
+CONFIG_RFKILL=y
+# CONFIG_RFKILL_FULL is not set
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_RFKILL_LEDS is not set
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RICHTEK_RTQ6056 is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_RING_BUFFER_STARTUP_TEST is not set
+# CONFIG_RMI4_CORE is not set
+# CONFIG_RMNET is not set
+# CONFIG_ROCKCHIP_DW_HDMI is not set
+# CONFIG_ROCKCHIP_IODOMAIN is not set
+# CONFIG_ROCKCHIP_IOMMU is not set
+# CONFIG_ROCKCHIP_MBOX is not set
+# CONFIG_ROCKCHIP_PHY is not set
+# CONFIG_ROCKCHIP_PM_DOMAINS is not set
+# CONFIG_ROCKCHIP_SARADC is not set
+# CONFIG_ROCKCHIP_THERMAL is not set
+# CONFIG_ROCKCHIP_VOP2 is not set
+# CONFIG_ROCKER is not set
+# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_ROSE is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
+# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RPMSG_VIRTIO is not set
+# CONFIG_RPR0521 is not set
+# CONFIG_RSEQ is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_RTC_DEBUG is not set
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABEOZ9 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_ARMADA38X is not set
+# CONFIG_RTC_DRV_AU1XXX is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_CADENCE is not set
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1307_CENTURY is not set
+# CONFIG_RTC_DRV_DS1307_HWMON is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_EP93XX is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_FTRTC010 is not set
+# CONFIG_RTC_DRV_GENERIC is not set
+# CONFIG_RTC_DRV_GOLDFISH is not set
+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL12026 is not set
+# CONFIG_RTC_DRV_ISL12057 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_JZ4740 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+# CONFIG_RTC_DRV_MOXART is not set
+# CONFIG_RTC_DRV_MPC5121 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_MT2712 is not set
+# CONFIG_RTC_DRV_NCT3018Y is not set
+# CONFIG_RTC_DRV_OMAP is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF85363 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_RTC_DRV_PS3 is not set
+# CONFIG_RTC_DRV_PT7C4338 is not set
+# CONFIG_RTC_DRV_R7301 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RK808  is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_RTC7301 is not set
+# CONFIG_RTC_DRV_RV3028 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RV3032 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_SD3078 is not set
+# CONFIG_RTC_DRV_SNVS is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_SUN6I is not set
+# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_XGENE is not set
+# CONFIG_RTC_DRV_ZYNQMP is not set
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_NVMEM is not set
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_RTL8192E is not set
+# CONFIG_RTL8192U is not set
+# CONFIG_RTL8306_PHY is not set
+# CONFIG_RTL8366RB_PHY is not set
+# CONFIG_RTL8366S_PHY is not set
+# CONFIG_RTL8366_SMI is not set
+# CONFIG_RTL8366_SMI_DEBUG_FS is not set
+# CONFIG_RTL8367B_PHY is not set
+# CONFIG_RTL8367_PHY is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_RTL_CARDS is not set
+# CONFIG_RTS5208 is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_RXKAD=y
+# CONFIG_S2IO is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SAMSUNG_LAPTOP is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_DWC is not set
+# CONFIG_SATA_DWC_OLD_DMA is not set
+# CONFIG_SATA_FSL is not set
+# CONFIG_SATA_HIGHBANK is not set
+# CONFIG_SATA_HOST is not set
+# CONFIG_SATA_INIC162X is not set
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_RCAR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SBC_FITPC2_WATCHDOG is not set
+CONFIG_SBITMAP=y
+# CONFIG_SC92031 is not set
+# CONFIG_SCA3000 is not set
+# CONFIG_SCA3300 is not set
+# CONFIG_SCACHE_DEBUGFS is not set
+# CONFIG_SCC is not set
+# CONFIG_SCD30_CORE is not set
+# CONFIG_SCD4X is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SCHED_CLUSTER is not set
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_MC is not set
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+# CONFIG_SCHED_SMT is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_SCR24X is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CHELSIO_FCOE is not set
+# CONFIG_SCSI_COMMON is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_ESAS2R is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_FDOMAIN_PCI is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_HISI_SAS is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_ISCI is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_LPFC is not set
+CONFIG_SCSI_MOD=y
+# CONFIG_SCSI_MPI3MR is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_MPT3SAS is not set
+# CONFIG_SCSI_MQ_DEFAULT is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_MVSAS_DEBUG is not set
+# CONFIG_SCSI_MVUMI is not set
+# CONFIG_SCSI_MYRB is not set
+# CONFIG_SCSI_MYRS is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_PMCRAID is not set
+CONFIG_SCSI_PROC_FS=y
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+# CONFIG_SCSI_SMARTPQI is not set
+# CONFIG_SCSI_SNIC is not set
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_UFSHCD is not set
+# CONFIG_SCSI_UFS_HWMON is not set
+# CONFIG_SCSI_ULTRASTOR is not set
+# CONFIG_SCSI_VIRTIO is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_SDR_MAX2175 is not set
+# CONFIG_SDR_PLATFORM_DRIVERS is not set
+# CONFIG_SD_ADC_MODULATOR is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_SECCOMP_CACHE_DEBUG is not set
+# CONFIG_SECRETMEM is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_APPARMOR is not set
+CONFIG_SECURITY_DMESG_RESTRICT=y
+# CONFIG_SECURITY_LOADPIN is not set
+# CONFIG_SECURITY_LOCKDOWN_LSM is not set
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_SAFESETID is not set
+# CONFIG_SECURITY_SELINUX_AVC_STATS is not set
+# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
+# CONFIG_SECURITY_SELINUX_DEVELOP is not set
+# CONFIG_SECURITY_SELINUX_DISABLE is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_YAMA is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
+# CONFIG_SENSIRION_SGP30 is not set
+# CONFIG_SENSIRION_SGP40 is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_ACPI_POWER is not set
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM1177 is not set
+# CONFIG_SENSORS_ADM1266 is not set
+# CONFIG_SENSORS_ADM1275 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_SENSORS_APPLESMC is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ASPEED is not set
+# CONFIG_SENSORS_ATK0110 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+# CONFIG_SENSORS_BEL_PFE is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BPA_RS600 is not set
+# CONFIG_SENSORS_CORETEMP is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DELL_SMM is not set
+# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_DPS920AB is not set
+# CONFIG_SENSORS_DRIVETEMP is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC2305 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_FAM15H_POWER is not set
+# CONFIG_SENSORS_FSCHMD is not set
+# CONFIG_SENSORS_FSP_3Y is not set
+# CONFIG_SENSORS_FTSTEUTATES is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_GSC is not set
+# CONFIG_SENSORS_HDAPS is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_HMC5843 is not set
+# CONFIG_SENSORS_HMC5843_I2C is not set
+# CONFIG_SENSORS_HMC5843_SPI is not set
+# CONFIG_SENSORS_HTU21 is not set
+# CONFIG_SENSORS_I5500 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_IBM_CFFPS is not set
+# CONFIG_SENSORS_IIO_HWMON is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA238 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_INSPUR_IPSPS is not set
+# CONFIG_SENSORS_IR35221 is not set
+# CONFIG_SENSORS_IR36021 is not set
+# CONFIG_SENSORS_IR38064 is not set
+# CONFIG_SENSORS_IRPS5401 is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_SENSORS_ISL68137 is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_K10TEMP is not set
+# CONFIG_SENSORS_K8TEMP is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LM25066 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_LT7182S is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2947_SPI is not set
+# CONFIG_SENSORS_LTC2978 is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC2992 is not set
+# CONFIG_SENSORS_LTC3815 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LTQ_CPUTEMP is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX127 is not set
+# CONFIG_SENSORS_MAX15301 is not set
+# CONFIG_SENSORS_MAX16064 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX16601 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX20730 is not set
+# CONFIG_SENSORS_MAX20751 is not set
+# CONFIG_SENSORS_MAX31722 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX31760 is not set
+# CONFIG_SENSORS_MAX31785 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MAX34440 is not set
+# CONFIG_SENSORS_MAX6620 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX8688 is not set
+# CONFIG_SENSORS_MC34VR500 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_MP2888 is not set
+# CONFIG_SENSORS_MP2975 is not set
+# CONFIG_SENSORS_MP5023 is not set
+# CONFIG_SENSORS_MPQ7932 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NSA320 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_PIM4328 is not set
+# CONFIG_SENSORS_PLI1209BC is not set
+# CONFIG_SENSORS_PM6764TR is not set
+# CONFIG_SENSORS_PMBUS is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_PWM_FAN is not set
+# CONFIG_SENSORS_PXE1610 is not set
+# CONFIG_SENSORS_Q54SJ108A2 is not set
+# CONFIG_SENSORS_RM3100_I2C is not set
+# CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_SENSORS_SBRMI is not set
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHT4x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_STPDDC60 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_TDA38640 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TMP513 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_TPS40422 is not set
+# CONFIG_SENSORS_TPS53679 is not set
+# CONFIG_SENSORS_TPS546D24 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_SENSORS_UCD9000 is not set
+# CONFIG_SENSORS_UCD9200 is not set
+# CONFIG_SENSORS_VEXPRESS is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VIA_CPUTEMP is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_XDPE122 is not set
+# CONFIG_SENSORS_XDPE152 is not set
+# CONFIG_SENSORS_XGENE is not set
+# CONFIG_SENSORS_ZL6100 is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+# CONFIG_SERIAL_8250_ACCENT is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+# CONFIG_SERIAL_8250_BOCA is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+CONFIG_SERIAL_8250_DMA=y
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_EM is not set
+# CONFIG_SERIAL_8250_EXAR is not set
+# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_FINTEK is not set
+# CONFIG_SERIAL_8250_FOURPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
+# CONFIG_SERIAL_8250_INGENIC is not set
+# CONFIG_SERIAL_8250_LPSS is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_MID is not set
+# CONFIG_SERIAL_8250_MOXA is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_SERIAL_8250_PCI1XXXX is not set
+# CONFIG_SERIAL_8250_PERICOM is not set
+# CONFIG_SERIAL_8250_RSA is not set
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_DEV_BUS is not set
+CONFIG_SERIAL_EARLYCON=y
+# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
+# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SH_SCI is not set
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SPRD is not set
+# CONFIG_SERIAL_STM32 is not set
+# CONFIG_SERIAL_ST_ASC is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_UARTLITE is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_GPIO_PS2 is not set
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_SUN4I_PS2 is not set
+# CONFIG_SFC is not set
+# CONFIG_SFC_FALCON is not set
+# CONFIG_SFI is not set
+# CONFIG_SFP is not set
+# CONFIG_SF_PDMA is not set
+# CONFIG_SGETMASK_SYSCALL is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP30 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SGI_MFD_IOC3 is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_SG_POOL is not set
+# CONFIG_SG_SPLIT is not set
+# CONFIG_SHADOW_CALL_STACK is not set
+CONFIG_SHMEM=y
+# CONFIG_SHRINKER_DEBUG is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_SH_ETH is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_SI1133 is not set
+# CONFIG_SI1145 is not set
+# CONFIG_SI7005 is not set
+# CONFIG_SI7020 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SIGNALFD=y
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+# CONFIG_SIMPLE_GPIO is not set
+# CONFIG_SIMPLE_PM_BUS is not set
+# CONFIG_SIOX is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SKY2_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLABINFO=y
+# CONFIG_SLAB_DEPRECATED is not set
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLHC is not set
+# CONFIG_SLICOSS is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_SLIP is not set
+# CONFIG_SLOB is not set
+# CONFIG_SLOB_DEPRECATED is not set
+# CONFIG_SLUB is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_SLUB_TINY is not set
+# CONFIG_SMARTJOYPLUS_FF is not set
+# CONFIG_SMB_SERVER is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMC9194 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_SMP is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_SMS_SDIO_DRV is not set
+# CONFIG_SMS_USB_DRV is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_SND is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+# CONFIG_SND_AD1816A is not set
+# CONFIG_SND_AD1848 is not set
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ADLIB is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_ALS100 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_ASIHPI is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_ATMEL_AC97C is not set
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AUDIO_GRAPH_CARD is not set
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT2320 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BCD2000 is not set
+# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMI8330 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_CS4231 is not set
+# CONFIG_SND_CS4236 is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5530 is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_CTL_FAST_LOOKUP is not set
+# CONFIG_SND_CTL_INPUT_VALIDATION is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_EDMA_SOC is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1688 is not set
+# CONFIG_SND_ES18XX is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FIREWIRE is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_GUSCLASSIC is not set
+# CONFIG_SND_GUSEXTREME is not set
+# CONFIG_SND_GUSMAX is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDA_INTEL_DETECT_DMIC is not set
+# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_HWDEP is not set
+# CONFIG_SND_I2S_HI6210_I2S is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_INTERWAVE is not set
+# CONFIG_SND_INTERWAVE_STB is not set
+# CONFIG_SND_ISA is not set
+# CONFIG_SND_JZ4740_SOC_I2S is not set
+# CONFIG_SND_KIRKWOOD_SOC is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_LOLA is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+CONFIG_SND_MAX_CARDS=16
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_MIRO is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MPC52xx_SOC_EFIKA is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_MTS64 is not set
+# CONFIG_SND_MXS_SOC is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_OPL3SA2 is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_OPTI92X_AD1848 is not set
+# CONFIG_SND_OPTI92X_CS4231 is not set
+# CONFIG_SND_OPTI93X is not set
+CONFIG_SND_OSSEMUL=y
+# CONFIG_SND_OXYGEN is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_PCM is not set
+# CONFIG_SND_PCMCIA is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_PCM_TIMER is not set
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_PDAUDIOCF is not set
+# CONFIG_SND_PORTMAN2X4 is not set
+# CONFIG_SND_POWERPC_SOC is not set
+# CONFIG_SND_PPC is not set
+CONFIG_SND_PROC_FS=y
+# CONFIG_SND_RAWMIDI is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_RTCTIMER is not set
+# CONFIG_SND_SB16 is not set
+# CONFIG_SND_SB8 is not set
+# CONFIG_SND_SBAWE is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_SE6X is not set
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_SERIAL_GENERIC is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_SIMPLE_CARD is not set
+# CONFIG_SND_SIMPLE_SCU_CARD is not set
+# CONFIG_SND_SIS7019 is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SND_SOC_AC97_CODEC is not set
+# CONFIG_SND_SOC_ADAU1372_I2C is not set
+# CONFIG_SND_SOC_ADAU1372_SPI is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_ADAU1761_I2C is not set
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_ADAU7002 is not set
+# CONFIG_SND_SOC_ADAU7118_HW is not set
+# CONFIG_SND_SOC_ADAU7118_I2C is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
+# CONFIG_SND_SOC_AK4458 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+# CONFIG_SND_SOC_AK4613 is not set
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_AK5558 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_SOC_AMD_ACP3x is not set
+# CONFIG_SND_SOC_AMD_RENOIR is not set
+# CONFIG_SND_SOC_AU1XAUDIO is not set
+# CONFIG_SND_SOC_AU1XPSC is not set
+# CONFIG_SND_SOC_AW8738 is not set
+# CONFIG_SND_SOC_AW88395 is not set
+# CONFIG_SND_SOC_BD28623 is not set
+# CONFIG_SND_SOC_BT_SCO is not set
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS35L33 is not set
+# CONFIG_SND_SOC_CS35L34 is not set
+# CONFIG_SND_SOC_CS35L35 is not set
+# CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L45_I2C is not set
+# CONFIG_SND_SOC_CS35L45_SPI is not set
+# CONFIG_SND_SOC_CS4234 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42L42 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS42L83 is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_CS43130 is not set
+# CONFIG_SND_SOC_CS4341 is not set
+# CONFIG_SND_SOC_CS4349 is not set
+# CONFIG_SND_SOC_CS53L30 is not set
+# CONFIG_SND_SOC_CX2072X is not set
+# CONFIG_SND_SOC_DA7213 is not set
+# CONFIG_SND_SOC_DIO2125 is not set
+# CONFIG_SND_SOC_DMIC is not set
+# CONFIG_SND_SOC_ES7134 is not set
+# CONFIG_SND_SOC_ES7241 is not set
+# CONFIG_SND_SOC_ES8316 is not set
+# CONFIG_SND_SOC_ES8326 is not set
+# CONFIG_SND_SOC_ES8328 is not set
+# CONFIG_SND_SOC_ES8328_I2C is not set
+# CONFIG_SND_SOC_ES8328_SPI is not set
+# CONFIG_SND_SOC_EUKREA_TLV320 is not set
+# CONFIG_SND_SOC_FSL_ASOC_CARD is not set
+# CONFIG_SND_SOC_FSL_ASRC is not set
+# CONFIG_SND_SOC_FSL_AUDMIX is not set
+# CONFIG_SND_SOC_FSL_ESAI is not set
+# CONFIG_SND_SOC_FSL_MICFIL is not set
+# CONFIG_SND_SOC_FSL_SAI is not set
+# CONFIG_SND_SOC_FSL_SPDIF is not set
+# CONFIG_SND_SOC_FSL_SSI is not set
+# CONFIG_SND_SOC_FSL_XCVR is not set
+# CONFIG_SND_SOC_GTM601 is not set
+# CONFIG_SND_SOC_HDA is not set
+# CONFIG_SND_SOC_ICS43432 is not set
+# CONFIG_SND_SOC_IDT821034 is not set
+# CONFIG_SND_SOC_IMG is not set
+# CONFIG_SND_SOC_IMX_AUDMIX is not set
+# CONFIG_SND_SOC_IMX_AUDMUX is not set
+# CONFIG_SND_SOC_IMX_ES8328 is not set
+# CONFIG_SND_SOC_IMX_SPDIF is not set
+# CONFIG_SND_SOC_IMX_WM8962 is not set
+# CONFIG_SND_SOC_INNO_RK3036 is not set
+# CONFIG_SND_SOC_INTEL_APL is not set
+# CONFIG_SND_SOC_INTEL_BAYTRAIL is not set
+# CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set
+# CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set
+# CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH is not set
+# CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH is not set
+# CONFIG_SND_SOC_INTEL_CATPT is not set
+# CONFIG_SND_SOC_INTEL_CFL is not set
+# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set
+# CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH is not set
+# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set
+# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set
+# CONFIG_SND_SOC_INTEL_CML_H is not set
+# CONFIG_SND_SOC_INTEL_CML_LP is not set
+# CONFIG_SND_SOC_INTEL_CNL is not set
+# CONFIG_SND_SOC_INTEL_GLK is not set
+# CONFIG_SND_SOC_INTEL_HASWELL is not set
+# CONFIG_SND_SOC_INTEL_KBL is not set
+# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set
+# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set
+# CONFIG_SND_SOC_INTEL_KEEMBAY is not set
+# CONFIG_SND_SOC_INTEL_SKL is not set
+# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH is not set
+# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH is not set
+# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set
+# CONFIG_SND_SOC_INTEL_SKYLAKE is not set
+# CONFIG_SND_SOC_INTEL_SST is not set
+CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
+# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set
+# CONFIG_SND_SOC_JZ4725B_CODEC is not set
+# CONFIG_SND_SOC_JZ4740_CODEC is not set
+# CONFIG_SND_SOC_JZ4770_CODEC is not set
+# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
+# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
+# CONFIG_SND_SOC_MA120X0P is not set
+# CONFIG_SND_SOC_MAX9759 is not set
+# CONFIG_SND_SOC_MAX98088 is not set
+# CONFIG_SND_SOC_MAX98357A is not set
+# CONFIG_SND_SOC_MAX98373 is not set
+# CONFIG_SND_SOC_MAX98373_I2C is not set
+# CONFIG_SND_SOC_MAX98390 is not set
+# CONFIG_SND_SOC_MAX98396 is not set
+# CONFIG_SND_SOC_MAX98504 is not set
+# CONFIG_SND_SOC_MAX98520 is not set
+# CONFIG_SND_SOC_MAX9860 is not set
+# CONFIG_SND_SOC_MAX9867 is not set
+# CONFIG_SND_SOC_MAX98927 is not set
+# CONFIG_SND_SOC_MEDIATEK is not set
+# CONFIG_SND_SOC_MPC5200_AC97 is not set
+# CONFIG_SND_SOC_MPC5200_I2S is not set
+# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
+# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
+# CONFIG_SND_SOC_MT2701 is not set
+# CONFIG_SND_SOC_MT6351 is not set
+# CONFIG_SND_SOC_MT6358 is not set
+# CONFIG_SND_SOC_MT6660 is not set
+# CONFIG_SND_SOC_MT6797 is not set
+# CONFIG_SND_SOC_MT8173 is not set
+# CONFIG_SND_SOC_MT8183 is not set
+# CONFIG_SND_SOC_MTK_BTCVSD is not set
+# CONFIG_SND_SOC_NAU8315 is not set
+# CONFIG_SND_SOC_NAU8540 is not set
+# CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
+# CONFIG_SND_SOC_NAU8822 is not set
+# CONFIG_SND_SOC_NAU8824 is not set
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM1789_I2C is not set
+# CONFIG_SND_SOC_PCM1792A is not set
+# CONFIG_SND_SOC_PCM179X_I2C is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_I2C is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_I2C is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+# CONFIG_SND_SOC_PCM3168A_I2C is not set
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_PEB2466 is not set
+# CONFIG_SND_SOC_QCOM is not set
+# CONFIG_SND_SOC_RK3328 is not set
+# CONFIG_SND_SOC_RK817 is not set
+# CONFIG_SND_SOC_ROCKCHIP_SPDIF is not set
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5631 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+# CONFIG_SND_SOC_RT5659 is not set
+# CONFIG_SND_SOC_RT5677_SPI is not set
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_SGTL5000 is not set
+# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
+# CONFIG_SND_SOC_SIMPLE_MUX is not set
+# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
+# CONFIG_SND_SOC_SMA1303 is not set
+# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
+# CONFIG_SND_SOC_SPDIF is not set
+# CONFIG_SND_SOC_SRC4XXX_I2C is not set
+# CONFIG_SND_SOC_SSM2305 is not set
+# CONFIG_SND_SOC_SSM2518 is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+# CONFIG_SND_SOC_STA350 is not set
+# CONFIG_SND_SOC_STI_SAS is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS2562 is not set
+# CONFIG_SND_SOC_TAS2764 is not set
+# CONFIG_SND_SOC_TAS2770 is not set
+# CONFIG_SND_SOC_TAS2780 is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+# CONFIG_SND_SOC_TAS571X is not set
+# CONFIG_SND_SOC_TAS5720 is not set
+# CONFIG_SND_SOC_TAS5805M is not set
+# CONFIG_SND_SOC_TAS6424 is not set
+# CONFIG_SND_SOC_TDA7419 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
+# CONFIG_SND_SOC_TLV320ADCX140 is not set
+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC3X is not set
+# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_SOC_TSCS42XX is not set
+# CONFIG_SND_SOC_TSCS454 is not set
+# CONFIG_SND_SOC_UDA1334 is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8524 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731 is not set
+# CONFIG_SND_SOC_WM8731_I2C is not set
+# CONFIG_SND_SOC_WM8731_SPI is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+# CONFIG_SND_SOC_WM8753 is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8782 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8903 is not set
+# CONFIG_SND_SOC_WM8904 is not set
+# CONFIG_SND_SOC_WM8940 is not set
+# CONFIG_SND_SOC_WM8960 is not set
+# CONFIG_SND_SOC_WM8961 is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_WM8974 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_WM8985 is not set
+# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
+# CONFIG_SND_SOC_XILINX_I2S is not set
+# CONFIG_SND_SOC_XILINX_SPDIF is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SOC_ZX_AUD96P22 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_SSCAPE is not set
+# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI is not set
+# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI is not set
+# CONFIG_SND_SUN4I_CODEC is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_TEST_COMPONENT is not set
+# CONFIG_SND_TIMER is not set
+# CONFIG_SND_TRIDENT is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_HIFACE is not set
+# CONFIG_SND_USB_POD is not set
+# CONFIG_SND_USB_PODHD is not set
+# CONFIG_SND_USB_TONEPORT is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_US122L is not set
+# CONFIG_SND_USB_USX2Y is not set
+# CONFIG_SND_USB_VARIAX is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_WAVEFRONT is not set
+CONFIG_SND_X86=y
+# CONFIG_SND_XEN_FRONTEND is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
+# CONFIG_SOCK_CGROUP_DATA is not set
+# CONFIG_SOCK_RX_QUEUE_MAPPING is not set
+# CONFIG_SOC_AM33XX is not set
+# CONFIG_SOC_AM43XX is not set
+# CONFIG_SOC_BRCMSTB is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_SOC_DRA7XX is not set
+# CONFIG_SOC_HAS_OMAP2_SDRC is not set
+# CONFIG_SOC_OMAP5 is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_SONYPI is not set
+# CONFIG_SONY_LAPTOP is not set
+# CONFIG_SOUND is not set
+# CONFIG_SOUNDWIRE is not set
+# CONFIG_SOUND_OSS_CORE is not set
+# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_SP5100_TCO is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+# CONFIG_SPARSE_IRQ is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_SPEAKUP is not set
+# CONFIG_SPI is not set
+# CONFIG_SPINLOCK_TEST is not set
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_ALTERA_CORE is not set
+# CONFIG_SPI_AMD is not set
+# CONFIG_SPI_AU1550 is not set
+# CONFIG_SPI_AX88796C is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+# CONFIG_SPI_BCM2835 is not set
+# CONFIG_SPI_BCM_QSPI is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_BUTTERFLY is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_CADENCE_XSPI is not set
+# CONFIG_SPI_DEBUG is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_FSL_DSPI is not set
+# CONFIG_SPI_FSL_ESPI is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_GPIO_OLD is not set
+# CONFIG_SPI_IMG_SPFI is not set
+# CONFIG_SPI_LANTIQ_SSC is not set
+# CONFIG_SPI_LM70_LLP is not set
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_SPI_MEM is not set
+# CONFIG_SPI_MICROCHIP_CORE is not set
+# CONFIG_SPI_MPC52xx is not set
+# CONFIG_SPI_MPC52xx_PSC is not set
+# CONFIG_SPI_MTK_QUADSPI is not set
+# CONFIG_SPI_MUX is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+# CONFIG_SPI_OCTEON is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_ORION is not set
+# CONFIG_SPI_PCI1XXXX is not set
+# CONFIG_SPI_PL022 is not set
+# CONFIG_SPI_PPC4xx is not set
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_QCOM_QSPI is not set
+# CONFIG_SPI_ROCKCHIP is not set
+CONFIG_SPI_ROCKCHIP_SFC=y
+# CONFIG_SPI_S3C64XX is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_SLAVE is not set
+# CONFIG_SPI_SN_F_OSPI is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_THUNDERX is not set
+# CONFIG_SPI_TI_QSPI is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_XWAY is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_SPMI is not set
+# CONFIG_SPS30 is not set
+# CONFIG_SPS30_I2C is not set
+# CONFIG_SPS30_SERIAL is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_DECOMP_MULTI is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
+CONFIG_SQUASHFS_EMBEDDED=y
+# CONFIG_SQUASHFS_FILE_CACHE is not set
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_SQUASHFS_LZ4 is not set
+# CONFIG_SQUASHFS_LZO is not set
+# CONFIG_SQUASHFS_XATTR is not set
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_ZLIB is not set
+# CONFIG_SQUASHFS_ZSTD is not set
+# CONFIG_SRAM is not set
+# CONFIG_SRF04 is not set
+# CONFIG_SRF08 is not set
+# CONFIG_SSB is not set
+# CONFIG_SSB_DEBUG is not set
+# CONFIG_SSB_DRIVER_GPIO is not set
+# CONFIG_SSB_HOST_SOC is not set
+# CONFIG_SSB_PCMCIAHOST is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB_SDIOHOST is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSFDC is not set
+# CONFIG_STACKPROTECTOR is not set
+# CONFIG_STACKPROTECTOR_PER_TASK is not set
+# CONFIG_STACKPROTECTOR_STRONG is not set
+# CONFIG_STACKTRACE is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_STACK_HASH_ORDER=20
+# CONFIG_STACK_TRACER is not set
+# CONFIG_STACK_VALIDATION is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_STAGING_GASKET_FRAMEWORK is not set
+# CONFIG_STAGING_MEDIA is not set
+CONFIG_STANDALONE=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_STDBINUTILS=y
+# CONFIG_STE10XP is not set
+# CONFIG_STE_MODEM_RPROC is not set
+# CONFIG_STK3310 is not set
+# CONFIG_STK8312 is not set
+# CONFIG_STK8BA50 is not set
+# CONFIG_STM is not set
+# CONFIG_STMMAC_ETH is not set
+# CONFIG_STMMAC_PCI is not set
+# CONFIG_STMMAC_PLATFORM is not set
+# CONFIG_STM_DUMMY is not set
+# CONFIG_STM_SOURCE_CONSOLE is not set
+CONFIG_STP=y
+# CONFIG_STREAM_PARSER is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+# CONFIG_STRING_SELFTEST is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_STX104 is not set
+# CONFIG_ST_UVIS25 is not set
+# CONFIG_SUN4I_GPADC is not set
+# CONFIG_SUN50I_DE2_BUS is not set
+# CONFIG_SUN50I_ERRATUM_UNKNOWN1 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y
+# CONFIG_SUNRPC_GSS is not set
+# CONFIG_SUNXI_SRAM is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_SURFACE_3_BUTTON is not set
+# CONFIG_SURFACE_PLATFORMS is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_SUSPEND_SKIP_SYNC is not set
+CONFIG_SWAP=y
+# CONFIG_SWCONFIG is not set
+# CONFIG_SWCONFIG_B53 is not set
+# CONFIG_SWCONFIG_B53_MDIO_DRIVER is not set
+# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
+# CONFIG_SWCONFIG_B53_SPI_DRIVER is not set
+# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
+# CONFIG_SWCONFIG_LEDS is not set
+# CONFIG_SWIOTLB_DYNAMIC is not set
+# CONFIG_SW_SYNC is not set
+# CONFIG_SX9310 is not set
+# CONFIG_SX9324 is not set
+# CONFIG_SX9360 is not set
+# CONFIG_SX9500 is not set
+# CONFIG_SXGBE_ETH is not set
+CONFIG_SYMBOLIC_ERRNAME=y
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_SYNC_FILE is not set
+# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set
+# CONFIG_SYNTH_EVENTS is not set
+# CONFIG_SYNTH_EVENT_GEN_TEST is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_SYSCON_REBOOT_MODE is not set
+CONFIG_SYSCTL=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_SYSFS=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_SYSFS_SYSCALL is not set
+# CONFIG_SYSTEMPORT is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# CONFIG_SYSTEM_DATA_VERIFICATION is not set
+# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_T5403 is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_TASKS_RCU is not set
+CONFIG_TASKS_TRACE_RCU_READ_MB=y
+# CONFIG_TASK_XACCT is not set
+# CONFIG_TC35815 is not set
+# CONFIG_TCG_ATMEL is not set
+# CONFIG_TCG_CRB is not set
+# CONFIG_TCG_FTPM_TEE is not set
+# CONFIG_TCG_INFINEON is not set
+# CONFIG_TCG_NSC is not set
+# CONFIG_TCG_ST33_I2C is not set
+# CONFIG_TCG_TIS is not set
+# CONFIG_TCG_TIS_I2C is not set
+# CONFIG_TCG_TIS_I2C_ATMEL is not set
+# CONFIG_TCG_TIS_I2C_CR50 is not set
+# CONFIG_TCG_TIS_I2C_INFINEON is not set
+# CONFIG_TCG_TIS_I2C_NUVOTON is not set
+# CONFIG_TCG_TIS_SPI is not set
+# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
+# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_TCG_VTPM_PROXY is not set
+# CONFIG_TCG_XEN is not set
+# CONFIG_TCIC is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BBR is not set
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CDG is not set
+CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_CONG_DCTCP is not set
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_NV is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_TCS3414 is not set
+# CONFIG_TCS3472 is not set
+# CONFIG_TEE is not set
+# CONFIG_TEGRA_AHB is not set
+# CONFIG_TEGRA_HOST1X is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+# CONFIG_TEST_BITFIELD is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_BITOPS is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_DEBUG_VIRTUAL is not set
+# CONFIG_TEST_DIV64 is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_FREE_PAGES is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_LOCKUP is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_MIN_HEAP is not set
+# CONFIG_TEST_OVERFLOW is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_REF_TRACKER is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_SCANF is not set
+# CONFIG_TEST_SIPHASH is not set
+# CONFIG_TEST_SORT is not set
+# CONFIG_TEST_STACKINIT is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_XARRAY is not set
+CONFIG_TEXTSEARCH=y
+# CONFIG_TEXTSEARCH_BM is not set
+# CONFIG_TEXTSEARCH_FSM is not set
+# CONFIG_TEXTSEARCH_KMP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_EMULATION is not set
+# CONFIG_THERMAL_GOV_BANG_BANG is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_THERMAL_MMIO is not set
+# CONFIG_THERMAL_NETLINK is not set
+# CONFIG_THERMAL_STATISTICS is not set
+# CONFIG_THERMAL_WRITABLE_TRIPS is not set
+# CONFIG_THINKPAD_ACPI is not set
+CONFIG_THIN_ARCHIVES=y
+# CONFIG_THREAD_INFO_IN_TASK is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_THUMB2_KERNEL is not set
+# CONFIG_THUNDERBOLT is not set
+# CONFIG_THUNDER_NIC_BGX is not set
+# CONFIG_THUNDER_NIC_PF is not set
+# CONFIG_THUNDER_NIC_RGX is not set
+# CONFIG_THUNDER_NIC_VF is not set
+# CONFIG_TICK_CPU_ACCOUNTING is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_TIERS_PER_GEN=4
+# CONFIG_TIFM_CORE is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_TIMB_DMA is not set
+CONFIG_TIMERFD=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_TIME_NS is not set
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TIPC is not set
+# CONFIG_TI_ADC081C is not set
+# CONFIG_TI_ADC0832 is not set
+# CONFIG_TI_ADC084S021 is not set
+# CONFIG_TI_ADC108S102 is not set
+# CONFIG_TI_ADC12138 is not set
+# CONFIG_TI_ADC128S052 is not set
+# CONFIG_TI_ADC161S626 is not set
+# CONFIG_TI_ADS1015 is not set
+# CONFIG_TI_ADS124S08 is not set
+# CONFIG_TI_ADS131E08 is not set
+# CONFIG_TI_ADS7924 is not set
+# CONFIG_TI_ADS7950 is not set
+# CONFIG_TI_ADS8344 is not set
+# CONFIG_TI_ADS8688 is not set
+# CONFIG_TI_AM335X_ADC is not set
+# CONFIG_TI_CPSW is not set
+# CONFIG_TI_CPSW_ALE is not set
+# CONFIG_TI_CPSW_PHY_SEL is not set
+# CONFIG_TI_CPTS is not set
+# CONFIG_TI_DAC082S085 is not set
+# CONFIG_TI_DAC5571 is not set
+# CONFIG_TI_DAC7311 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_TI_DAC7612 is not set
+# CONFIG_TI_DAVINCI_CPDMA is not set
+# CONFIG_TI_DAVINCI_MDIO is not set
+# CONFIG_TI_LMP92064 is not set
+# CONFIG_TI_ST is not set
+# CONFIG_TI_SYSCON_RESET is not set
+# CONFIG_TI_TLC4541 is not set
+# CONFIG_TI_TMAG5273 is not set
+# CONFIG_TI_TSC2046 is not set
+# CONFIG_TLAN is not set
+# CONFIG_TLS is not set
+# CONFIG_TMD_HERMES is not set
+# CONFIG_TMP006 is not set
+# CONFIG_TMP007 is not set
+# CONFIG_TMP117 is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_INODE64 is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TOPSTAR_LAPTOP is not set
+# CONFIG_TORTURE_TEST is not set
+# CONFIG_TOSHIBA_HAPS is not set
+# CONFIG_TOUCHSCREEN_88PM860X is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_ADC is not set
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_BU21029 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
+# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set
+# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_I2C is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set
+# CONFIG_TOUCHSCREEN_DA9034 is not set
+# CONFIG_TOUCHSCREEN_DA9052 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
+# CONFIG_TOUCHSCREEN_EKTF2127 is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_EXC3000 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GOODIX is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_HIDEEP is not set
+# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
+# CONFIG_TOUCHSCREEN_HP600 is not set
+# CONFIG_TOUCHSCREEN_HP7XX is not set
+# CONFIG_TOUCHSCREEN_HTCPEN is not set
+# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
+# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_ILITEK is not set
+# CONFIG_TOUCHSCREEN_IMAGIS is not set
+# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_IPAQ_MICRO is not set
+# CONFIG_TOUCHSCREEN_IPROC is not set
+# CONFIG_TOUCHSCREEN_IQS5XX is not set
+# CONFIG_TOUCHSCREEN_LPC32XX is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MC13783 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
+# CONFIG_TOUCHSCREEN_MIGOR is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MSG2638 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MX25 is not set
+# CONFIG_TOUCHSCREEN_MXS_LRADC is not set
+# CONFIG_TOUCHSCREEN_PCAP is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_PROPERTIES is not set
+# CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set
+# CONFIG_TOUCHSCREEN_RM_TS is not set
+# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
+# CONFIG_TOUCHSCREEN_RPI_FT5406 is not set
+# CONFIG_TOUCHSCREEN_S3C2410 is not set
+# CONFIG_TOUCHSCREEN_S6SY761 is not set
+# CONFIG_TOUCHSCREEN_SILEAD is not set
+# CONFIG_TOUCHSCREEN_SIS_I2C is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_STMFTS is not set
+# CONFIG_TOUCHSCREEN_STMPE is not set
+# CONFIG_TOUCHSCREEN_SUN4I is not set
+# CONFIG_TOUCHSCREEN_SUR40 is not set
+# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_TS4800 is not set
+# CONFIG_TOUCHSCREEN_TSC2004 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
+# CONFIG_TOUCHSCREEN_TSC200X_CORE is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_3M is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_USB_DMC_TSC10 is not set
+# CONFIG_TOUCHSCREEN_USB_E2I is not set
+# CONFIG_TOUCHSCREEN_USB_EASYTOUCH is not set
+# CONFIG_TOUCHSCREEN_USB_EGALAX is not set
+# CONFIG_TOUCHSCREEN_USB_ELO is not set
+# CONFIG_TOUCHSCREEN_USB_ETT_TC45USB is not set
+# CONFIG_TOUCHSCREEN_USB_ETURBO is not set
+# CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH is not set
+# CONFIG_TOUCHSCREEN_USB_GOTOP is not set
+# CONFIG_TOUCHSCREEN_USB_GUNZE is not set
+# CONFIG_TOUCHSCREEN_USB_IDEALTEK is not set
+# CONFIG_TOUCHSCREEN_USB_IRTOUCH is not set
+# CONFIG_TOUCHSCREEN_USB_ITM is not set
+# CONFIG_TOUCHSCREEN_USB_JASTEC is not set
+# CONFIG_TOUCHSCREEN_USB_NEXIO is not set
+# CONFIG_TOUCHSCREEN_USB_PANJIT is not set
+# CONFIG_TOUCHSCREEN_USB_ZYTRONIC is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
+# CONFIG_TOUCHSCREEN_WM831X is not set
+# CONFIG_TOUCHSCREEN_WM9705 is not set
+# CONFIG_TOUCHSCREEN_WM9712 is not set
+# CONFIG_TOUCHSCREEN_WM9713 is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
+# CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE is not set
+# CONFIG_TOUCHSCREEN_ZET6223 is not set
+# CONFIG_TOUCHSCREEN_ZFORCE is not set
+# CONFIG_TOUCHSCREEN_ZINITIX is not set
+# CONFIG_TPL0102 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_TRACER_SNAPSHOT is not set
+# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_TRACE_EVAL_MAP_FILE is not set
+# CONFIG_TRACE_EVENT_INJECT is not set
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_TRACE_SINK is not set
+# CONFIG_TRACING_EVENTS_GPIO is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_TRAD_SIGNALS=y
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+# CONFIG_TRANS_TABLE is not set
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+# CONFIG_TRUSTED_FOUNDATIONS is not set
+# CONFIG_TRUSTED_KEYS is not set
+# CONFIG_TRUSTED_KEYS_TPM is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_TSL2591 is not set
+# CONFIG_TSL2772 is not set
+# CONFIG_TSL2x7x is not set
+# CONFIG_TSL4531 is not set
+# CONFIG_TSNEP is not set
+# CONFIG_TSYS01 is not set
+# CONFIG_TSYS02D is not set
+# CONFIG_TTPCI_EEPROM is not set
+CONFIG_TTY=y
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL4030_MADC is not set
+# CONFIG_TWL6030_GPADC is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_TXGBE is not set
+# CONFIG_TYPEC is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_TCPM is not set
+# CONFIG_TYPEC_UCSI is not set
+# CONFIG_TYPHOON is not set
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_UBIFS_ATIME_SUPPORT is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+# CONFIG_UBIFS_FS_ENCRYPTION is not set
+CONFIG_UBIFS_FS_LZO=y
+# CONFIG_UBIFS_FS_SECURITY is not set
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+# CONFIG_UBSAN is not set
+CONFIG_UBSAN_ALIGNMENT=y
+CONFIG_UBSAN_BOOL=y
+# CONFIG_UBSAN_DIV_ZERO is not set
+CONFIG_UBSAN_ENUM=y
+CONFIG_UBSAN_SHIFT=y
+# CONFIG_UBSAN_UNREACHABLE is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_UCSI is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDMABUF is not set
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_UFS_FS is not set
+# CONFIG_UHID is not set
+CONFIG_UID16=y
+# CONFIG_UIO is not set
+# CONFIG_ULTRA is not set
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_UNFORCE_NR_CPUS=y
+# CONFIG_UNICODE is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_UNISYS_VISORBUS is not set
+CONFIG_UNIX=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_UNIX_DIAG is not set
+CONFIG_UNIX_SCM=y
+# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+# CONFIG_UPROBES is not set
+# CONFIG_UPROBE_EVENTS is not set
+# CONFIG_US5182D is not set
+# CONFIG_USB is not set
+# CONFIG_USB4 is not set
+# CONFIG_USBIP_CORE is not set
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+# CONFIG_USBIP_VUDC is not set
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AIRSPY is not set
+CONFIG_USB_ALI_M5632=y
+# CONFIG_USB_AMD5536UDC is not set
+CONFIG_USB_AN2720=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_ATM is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_BDC_UDC is not set
+CONFIG_USB_BELKIN=y
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_CDNS3 is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_CHIPIDEA_GENERIC is not set
+# CONFIG_USB_CHIPIDEA_IMX is not set
+# CONFIG_USB_CHIPIDEA_MSM is not set
+# CONFIG_USB_CHIPIDEA_PCI is not set
+# CONFIG_USB_CHIPIDEA_TEGRA is not set
+# CONFIG_USB_CONFIGFS is not set
+# CONFIG_USB_CONN_GPIO is not set
+# CONFIG_USB_CXACRU is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_DUMMY_HCD is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_DWC2_DEBUG is not set
+# CONFIG_USB_DWC2_DUAL_ROLE is not set
+# CONFIG_USB_DWC2_HOST is not set
+# CONFIG_USB_DWC2_PERIPHERAL is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC3_EXYNOS is not set
+# CONFIG_USB_DWC3_HAPS is not set
+# CONFIG_USB_DWC3_KEYSTONE is not set
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+# CONFIG_USB_DWC3_PCI is not set
+# CONFIG_USB_DWC3_QCOM is not set
+# CONFIG_USB_DWC3_ULPI is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_EG20T is not set
+# CONFIG_USB_EHCI_ATH79 is not set
+# CONFIG_USB_EHCI_FSL is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_EHCI_HCD_AT91 is not set
+# CONFIG_USB_EHCI_HCD_OMAP is not set
+# CONFIG_USB_EHCI_HCD_PPC_OF is not set
+# CONFIG_USB_EHCI_MSM is not set
+# CONFIG_USB_EHCI_MV is not set
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+# CONFIG_USB_FOTG210 is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_FOTG210_UDC is not set
+# CONFIG_USB_FSL_USB2 is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_FUSB300 is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_VBUS_DRAW=2
+# CONFIG_USB_GADGET_XILINX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GOKU is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_GR_UDC is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_DTCS033 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STK1135 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TOUPTEK is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_G_WEBCAM is not set
+# CONFIG_USB_HACKRF is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+# CONFIG_USB_HID is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_IMX21_HCD is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_ISP1760 is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_KC2190 is not set
+# CONFIG_USB_LAN78XX is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
+# CONFIG_USB_LED_TRIG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LGM_PHY is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_MAX3420_UDC is not set
+# CONFIG_USB_MAX3421_HCD is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_MSI2500 is not set
+# CONFIG_USB_MSM_OTG is not set
+# CONFIG_USB_MTU3 is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MV_U3D is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_MXS_PHY is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_NET2280 is not set
+# CONFIG_USB_NET_AQC111 is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_CDCETHER is not set
+# CONFIG_USB_NET_CDC_EEM is not set
+# CONFIG_USB_NET_CDC_MBIM is not set
+# CONFIG_USB_NET_CDC_NCM is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_CH9200 is not set
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_SR9700 is not set
+# CONFIG_USB_NET_SR9800 is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_OHCI_HCD_PCI is not set
+# CONFIG_USB_OHCI_HCD_PPC_OF is not set
+# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set
+# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set
+# CONFIG_USB_OHCI_HCD_SSB is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_ONBOARD_HUB is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+# CONFIG_USB_OTG_FSM is not set
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_PCI is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_PHY is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_RAW_GADGET is not set
+# CONFIG_USB_RCAR_PHY is not set
+# CONFIG_USB_RENESAS_USBHS is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_ROLES_INTEL_XHCI is not set
+# CONFIG_USB_ROLE_SWITCH is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+# CONFIG_USB_RTL8153_ECM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_F81232 is not set
+# CONFIG_USB_SERIAL_F8153X is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_METRO is not set
+# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MXUPORT is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QT2 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SIMPLE is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_UPD78F0730 is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_WISHBONE is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_XR is not set
+# CONFIG_USB_SERIAL_XSENS_MT is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_SNP_UDC_PLAT is not set
+# CONFIG_USB_SPEEDTOUCH is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_TMC is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_UEAGLEATM is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_USB_ULPI_BUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+# CONFIG_USB_VIDEO_CLASS is not set
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_VL600 is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+# CONFIG_USB_XHCI_DBGCAP is not set
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_XHCI_MVEBU is not set
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+# CONFIG_USB_XUSBATM is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USELIB is not set
+# CONFIG_USERFAULTFD is not set
+# CONFIG_USERIO is not set
+# CONFIG_USER_DECRYPTED_DATA is not set
+# CONFIG_USE_OF is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_UWB is not set
+# CONFIG_U_SERIAL_CONSOLE is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+# CONFIG_VALIDATE_FS_PARSER is not set
+# CONFIG_VBOXGUEST is not set
+# CONFIG_VCAP is not set
+# CONFIG_VCNL3020 is not set
+# CONFIG_VCNL4000 is not set
+# CONFIG_VCNL4035 is not set
+# CONFIG_VCPU_STALL_DETECTOR is not set
+# CONFIG_VDPA is not set
+CONFIG_VDSO=y
+# CONFIG_VEML6030 is not set
+# CONFIG_VEML6070 is not set
+# CONFIG_VETH is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_VF610_ADC is not set
+# CONFIG_VF610_DAC is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_VFIO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_VGA_SWITCHEROO is not set
+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
+CONFIG_VHOST_MENU=y
+# CONFIG_VHOST_NET is not set
+# CONFIG_VHOST_VSOCK is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_VIDEO_AD5820 is not set
+# CONFIG_VIDEO_AD9389B is not set
+# CONFIG_VIDEO_ADP1653 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7183 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV7393 is not set
+# CONFIG_VIDEO_ADV748X is not set
+# CONFIG_VIDEO_ADV7511 is not set
+# CONFIG_VIDEO_ADV7604 is not set
+# CONFIG_VIDEO_ADV7842 is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_AK7375 is not set
+# CONFIG_VIDEO_AK881X is not set
+# CONFIG_VIDEO_AR0521 is not set
+# CONFIG_VIDEO_ASPEED is not set
+# CONFIG_VIDEO_AU0828 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_CADENCE is not set
+# CONFIG_VIDEO_CADENCE_CSI2RX is not set
+# CONFIG_VIDEO_CADENCE_CSI2TX is not set
+# CONFIG_VIDEO_CAFE_CCIC is not set
+# CONFIG_VIDEO_CCS is not set
+# CONFIG_VIDEO_CS3308 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_CX2341X is not set
+# CONFIG_VIDEO_CX25840 is not set
+# CONFIG_VIDEO_CX88 is not set
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_DM6446_CCDC is not set
+# CONFIG_VIDEO_DT3155 is not set
+# CONFIG_VIDEO_DW9714 is not set
+# CONFIG_VIDEO_DW9768 is not set
+# CONFIG_VIDEO_DW9807_VCM is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_ET8EK8 is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_VIDEO_GS1662 is not set
+# CONFIG_VIDEO_HANTRO_ROCKCHIP is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_VIDEO_HEXIUM_ORION is not set
+# CONFIG_VIDEO_HI556 is not set
+# CONFIG_VIDEO_HI846 is not set
+# CONFIG_VIDEO_HI847 is not set
+# CONFIG_VIDEO_I2C is not set
+# CONFIG_VIDEO_IMX208 is not set
+# CONFIG_VIDEO_IMX214 is not set
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_IMX258 is not set
+# CONFIG_VIDEO_IMX274 is not set
+# CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX296 is not set
+# CONFIG_VIDEO_IMX319 is not set
+# CONFIG_VIDEO_IMX334 is not set
+# CONFIG_VIDEO_IMX335 is not set
+# CONFIG_VIDEO_IMX355 is not set
+# CONFIG_VIDEO_IMX412 is not set
+# CONFIG_VIDEO_IMX415 is not set
+# CONFIG_VIDEO_IMX477 is not set
+# CONFIG_VIDEO_IRS1125 is not set
+# CONFIG_VIDEO_IR_I2C is not set
+# CONFIG_VIDEO_ISL7998X is not set
+# CONFIG_VIDEO_IVTV is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_LM3560 is not set
+# CONFIG_VIDEO_LM3646 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_M5MOLS is not set
+# CONFIG_VIDEO_MAX9286 is not set
+# CONFIG_VIDEO_ML86V7667 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_MT9M001 is not set
+# CONFIG_VIDEO_MT9M032 is not set
+# CONFIG_VIDEO_MT9M111 is not set
+# CONFIG_VIDEO_MT9P031 is not set
+# CONFIG_VIDEO_MT9T001 is not set
+# CONFIG_VIDEO_MT9T112 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_MT9V032 is not set
+# CONFIG_VIDEO_MT9V111 is not set
+# CONFIG_VIDEO_MUX is not set
+# CONFIG_VIDEO_MXB is not set
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_OG01A1B is not set
+# CONFIG_VIDEO_OMAP2_VOUT is not set
+# CONFIG_VIDEO_OV02A10 is not set
+# CONFIG_VIDEO_OV08D10 is not set
+# CONFIG_VIDEO_OV08X40 is not set
+# CONFIG_VIDEO_OV13858 is not set
+# CONFIG_VIDEO_OV13B10 is not set
+# CONFIG_VIDEO_OV2640 is not set
+# CONFIG_VIDEO_OV2659 is not set
+# CONFIG_VIDEO_OV2680 is not set
+# CONFIG_VIDEO_OV2685 is not set
+# CONFIG_VIDEO_OV2740 is not set
+# CONFIG_VIDEO_OV4689 is not set
+# CONFIG_VIDEO_OV5640 is not set
+# CONFIG_VIDEO_OV5645 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV5648 is not set
+# CONFIG_VIDEO_OV5670 is not set
+# CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
+# CONFIG_VIDEO_OV5695 is not set
+# CONFIG_VIDEO_OV6650 is not set
+# CONFIG_VIDEO_OV7251 is not set
+# CONFIG_VIDEO_OV7640 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_OV772X is not set
+# CONFIG_VIDEO_OV7740 is not set
+# CONFIG_VIDEO_OV8856 is not set
+# CONFIG_VIDEO_OV8858 is not set
+# CONFIG_VIDEO_OV8865 is not set
+# CONFIG_VIDEO_OV9281 is not set
+# CONFIG_VIDEO_OV9282 is not set
+# CONFIG_VIDEO_OV9640 is not set
+# CONFIG_VIDEO_OV9650 is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_RDACM20 is not set
+# CONFIG_VIDEO_RDACM21 is not set
+# CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+# CONFIG_VIDEO_S5K4ECGX is not set
+# CONFIG_VIDEO_S5K5BAF is not set
+# CONFIG_VIDEO_S5K6A3 is not set
+# CONFIG_VIDEO_S5K6AA is not set
+# CONFIG_VIDEO_SAA6588 is not set
+# CONFIG_VIDEO_SAA6752HS is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7134 is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_VIDEO_SMIAPP is not set
+# CONFIG_VIDEO_SONY_BTF_MPX is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_STK1160_COMMON is not set
+# CONFIG_VIDEO_ST_MIPID02 is not set
+# CONFIG_VIDEO_ST_VGXY61 is not set
+# CONFIG_VIDEO_TC358743 is not set
+# CONFIG_VIDEO_TC358746 is not set
+# CONFIG_VIDEO_TDA1997X is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_THS8200 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_TM6000 is not set
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_TW2804 is not set
+# CONFIG_VIDEO_TW9903 is not set
+# CONFIG_VIDEO_TW9906 is not set
+# CONFIG_VIDEO_TW9910 is not set
+# CONFIG_VIDEO_UDA1342 is not set
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_USBTV is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_VIDEO_V4L2 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_VPX3220 is not set
+# CONFIG_VIDEO_VS6624 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_XILINX is not set
+# CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_BLK_SCSI is not set
+# CONFIG_VIRTIO_CONSOLE is not set
+# CONFIG_VIRTIO_FS is not set
+# CONFIG_VIRTIO_INPUT is not set
+CONFIG_VIRTIO_MENU=y
+# CONFIG_VIRTIO_MMIO is not set
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTUALIZATION is not set
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_VL53L0X_I2C is not set
+# CONFIG_VL6180 is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_VLAN_8021Q_MVRP is not set
+# CONFIG_VMAP_STACK is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_VMLINUX_MAP is not set
+# CONFIG_VMSPLIT_1G is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_2G_OPT is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_3G_OPT is not set
+# CONFIG_VMWARE_PVSCSI is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_VOP_BUS is not set
+# CONFIG_VORTEX is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_VSOCKETS_DIAG is not set
+# CONFIG_VT is not set
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_VXGE is not set
+# CONFIG_VXLAN is not set
+# CONFIG_VZ89X is not set
+# CONFIG_W1 is not set
+# CONFIG_W1_CON is not set
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_GPIO is not set
+# CONFIG_W1_MASTER_MATROX is not set
+# CONFIG_W1_MASTER_SGI is not set
+# CONFIG_W1_SLAVE_DS2405 is not set
+# CONFIG_W1_SLAVE_DS2406 is not set
+# CONFIG_W1_SLAVE_DS2408 is not set
+# CONFIG_W1_SLAVE_DS2413 is not set
+# CONFIG_W1_SLAVE_DS2423 is not set
+# CONFIG_W1_SLAVE_DS2430 is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+# CONFIG_W1_SLAVE_DS2438 is not set
+# CONFIG_W1_SLAVE_DS250X is not set
+# CONFIG_W1_SLAVE_DS2780 is not set
+# CONFIG_W1_SLAVE_DS2781 is not set
+# CONFIG_W1_SLAVE_DS2805 is not set
+# CONFIG_W1_SLAVE_DS28E04 is not set
+# CONFIG_W1_SLAVE_DS28E17 is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W83627HF_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_W83977F_WDT is not set
+# CONFIG_WAN is not set
+# CONFIG_WANXL is not set
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_CORE is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+# CONFIG_WATCHDOG_SYSFS is not set
+# CONFIG_WATCH_QUEUE is not set
+# CONFIG_WD80x3 is not set
+# CONFIG_WDAT_WDT is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_WERROR is not set
+# CONFIG_WEXT_CORE is not set
+# CONFIG_WEXT_PRIV is not set
+# CONFIG_WEXT_PROC is not set
+# CONFIG_WEXT_SPY is not set
+CONFIG_WILINK_PLATFORM_DATA=y
+# CONFIG_WIMAX is not set
+# CONFIG_WIREGUARD is not set
+CONFIG_WIRELESS=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_WIRELESS_WDS is not set
+# CONFIG_WIZNET_W5100 is not set
+# CONFIG_WIZNET_W5300 is not set
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_WL18XX is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_MICROCHIP is not set
+# CONFIG_WLAN_VENDOR_PURELIFI is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_SILABS is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLCORE is not set
+# CONFIG_WPCM450_SOC is not set
+# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+# CONFIG_WQ_WATCHDOG is not set
+# CONFIG_WWAN is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_X25 is not set
+# CONFIG_X509_CERTIFICATE_PARSER is not set
+# CONFIG_X86_PKG_TEMP_THERMAL is not set
+CONFIG_X86_SYSFB=y
+# CONFIG_XDP_SOCKETS is not set
+# CONFIG_XEN is not set
+# CONFIG_XEN_GRANT_DMA_ALLOC is not set
+# CONFIG_XEN_PVCALLS_FRONTEND is not set
+CONFIG_XEN_SCRUB_PAGES_DEFAULT=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_INTERFACE is not set
+# CONFIG_XFRM_IPCOMP is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_XFS_ONLINE_SCRUB is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_SUPPORT_ASCII_CI is not set
+# CONFIG_XFS_SUPPORT_V4 is not set
+# CONFIG_XFS_WARN is not set
+# CONFIG_XILINX_AXI_EMAC is not set
+# CONFIG_XILINX_DMA is not set
+# CONFIG_XILINX_EMACLITE is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_XILINX_INTC is not set
+# CONFIG_XILINX_LL_TEMAC is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_XILINX_VCU is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_XILINX_XADC is not set
+# CONFIG_XILINX_XDMA is not set
+# CONFIG_XILINX_ZYNQMP_DMA is not set
+# CONFIG_XILINX_ZYNQMP_DPDMA is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_XMON is not set
+# CONFIG_XXHASH is not set
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_MICROLZMA is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_TEST is not set
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_YAM is not set
+# CONFIG_YAMAHA_YAS530 is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_YENTA is not set
+# CONFIG_YENTA_O2 is not set
+# CONFIG_YENTA_RICOH is not set
+# CONFIG_YENTA_TI is not set
+# CONFIG_YENTA_TOSHIBA is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_ZERO_CALL_USED_REGS is not set
+# CONFIG_ZIIRAVE_WATCHDOG is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_ZLIB_DEFLATE is not set
+# CONFIG_ZLIB_INFLATE is not set
+CONFIG_ZONE_DMA=y
+# CONFIG_ZONE_DMA32 is not set
+# CONFIG_ZOPT2201 is not set
+# CONFIG_ZPA2326 is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZRAM is not set
+# CONFIG_ZRAM_MEMORY_TRACKING is not set
+# CONFIG_ZRAM_MULTI_COMP is not set
+# CONFIG_ZSMALLOC is not set
+# CONFIG_ZSTD_COMPRESS is not set
+# CONFIG_ZSTD_DECOMPRESS is not set
+# CONFIG_ZSWAP is not set
+# CONFIG_ZX_TDM is not set
diff --git a/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch b/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch
index f6b44b2a403b39..ea72094cee02aa 100644
--- a/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch
+++ b/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch
@@ -10,7 +10,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1172,6 +1172,10 @@ config MIPS_MSC
+@@ -1171,6 +1171,10 @@ config MIPS_MSC
  config SYNC_R4K
  	bool
  
diff --git a/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch
index e77b51a31d3281..8f6702e433513f 100644
--- a/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	help
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3658,6 +3658,11 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3666,6 +3666,11 @@ static int xmit_one(struct sk_buff *skb,
  	if (dev_nit_active(dev))
  		dev_queue_xmit_nit(skb, dev);
  
diff --git a/target/linux/generic/hack-5.10/902-debloat_proc.patch b/target/linux/generic/hack-5.10/902-debloat_proc.patch
index a7e3d843159755..d4a77666628754 100644
--- a/target/linux/generic/hack-5.10/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.10/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -3725,6 +3725,8 @@ static __net_initdata struct pernet_oper
+@@ -3726,6 +3726,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-5.10/953-net-patch-linux-kernel-to-support-shortcut-fe.patch b/target/linux/generic/hack-5.10/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
index 505347fb0d1ca3..11a15a6fe499c4 100644
--- a/target/linux/generic/hack-5.10/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
+++ b/target/linux/generic/hack-5.10/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -80,7 +80,7 @@
  	struct net_bridge_port *p;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3654,9 +3654,17 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3662,9 +3662,17 @@ static int xmit_one(struct sk_buff *skb,
  {
  	unsigned int len;
  	int rc;
@@ -99,7 +99,7 @@
  
  #ifdef CONFIG_ETHERNET_PACKET_MANGLE
  	if (dev->eth_mangle_tx && !(skb = dev->eth_mangle_tx(dev, skb)))
-@@ -5210,6 +5218,11 @@ void netdev_rx_handler_unregister(struct
+@@ -5218,6 +5226,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
  
@@ -111,7 +111,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -5258,6 +5271,10 @@ static int __netif_receive_skb_core(stru
+@@ -5266,6 +5279,10 @@ static int __netif_receive_skb_core(stru
  	int ret = NET_RX_DROP;
  	__be16 type;
  
@@ -122,7 +122,7 @@
  	net_timestamp_check(!READ_ONCE(netdev_tstamp_prequeue), skb);
  
  	trace_netif_receive_skb(skb);
-@@ -5297,6 +5314,15 @@ another_round:
+@@ -5305,6 +5322,15 @@ another_round:
  			goto out;
  	}
  
diff --git a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch
deleted file mode 100644
index f1942e2037598d..00000000000000
--- a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
-From: "Alexandros C. Couloumbis" <alex@ozo.com>
-Date: Fri, 7 Jul 2017 17:14:51 +0200
-Subject: hack: arch: powerpc: drop register save/restore library from modules
-
-Upstream GCC uses a libgcc function for saving/restoring registers. This
-makes the code bigger, and upstream kernels need to carry that function
-for every single kernel module. Our GCC is patched to avoid those
-references, so we can drop the extra bloat for modules.
-
-lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
-Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
----
- arch/powerpc/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -44,19 +44,6 @@ machine-$(CONFIG_PPC64) += 64
- machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
- UTS_MACHINE := $(subst $(space),,$(machine-y))
- 
--# XXX This needs to be before we override LD below
--ifdef CONFIG_PPC32
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--else
--ifeq ($(call ld-ifversion, -ge, 22500, y),y)
--# Have the linker provide sfpr if possible.
--# There is a corresponding test in arch/powerpc/lib/Makefile
--KBUILD_LDFLAGS_MODULE += --save-restore-funcs
--else
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--endif
--endif
--
- ifdef CONFIG_CPU_LITTLE_ENDIAN
- KBUILD_CFLAGS	+= -mlittle-endian
- KBUILD_LDFLAGS	+= -EL
diff --git a/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
index 026da362ebeb6c..3f971d654525b8 100644
--- a/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
@@ -116,7 +116,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	help
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3612,6 +3612,11 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3615,6 +3615,11 @@ static int xmit_one(struct sk_buff *skb,
  	if (dev_nit_active(dev))
  		dev_queue_xmit_nit(skb, dev);
  
diff --git a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
index 60f02f71436e6c..0060fbbd2addc2 100644
--- a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
+++ b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
@@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  
  #define QUECTEL_VENDOR_ID			0x2c7c
  /* These Quectel products use Quectel's vendor ID */
-@@ -1146,6 +1151,11 @@ static const struct usb_device_id option
+@@ -1147,6 +1152,11 @@ static const struct usb_device_id option
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
  	  .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  	/* Quectel products using Qualcomm vendor ID */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1187,6 +1197,11 @@ static const struct usb_device_id option
+@@ -1188,6 +1198,11 @@ static const struct usb_device_id option
  	  .driver_info = ZLP },
  	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch b/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch
index cf5b55459b9608..03fb40a4932aca 100644
--- a/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch
@@ -77,7 +77,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -1987,9 +2001,11 @@ static void __sk_free(struct sock *sk)
+@@ -1994,9 +2008,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-5.15/902-debloat_proc.patch b/target/linux/generic/hack-5.15/902-debloat_proc.patch
index 768d3e1f0cfb76..dcdad4ca695df4 100644
--- a/target/linux/generic/hack-5.15/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.15/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -3881,6 +3881,8 @@ static __net_initdata struct pernet_oper
+@@ -3889,6 +3889,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-5.15/953-net-patch-linux-kernel-to-support-shortcut-fe.patch b/target/linux/generic/hack-5.15/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
index 5cdf5d179eceda..a185f603ffe2ae 100644
--- a/target/linux/generic/hack-5.15/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
+++ b/target/linux/generic/hack-5.15/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -92,7 +92,7 @@
  	struct net_bridge_port *p;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3608,9 +3608,17 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3611,9 +3611,17 @@ static int xmit_one(struct sk_buff *skb,
  {
  	unsigned int len;
  	int rc;
@@ -111,7 +111,7 @@
  
  #ifdef CONFIG_ETHERNET_PACKET_MANGLE
  	if (dev->eth_mangle_tx && !(skb = dev->eth_mangle_tx(dev, skb)))
-@@ -5241,6 +5249,11 @@ void netdev_rx_handler_unregister(struct
+@@ -5244,6 +5252,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
  
@@ -123,7 +123,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -5289,6 +5302,10 @@ static int __netif_receive_skb_core(stru
+@@ -5292,6 +5305,10 @@ static int __netif_receive_skb_core(stru
  	int ret = NET_RX_DROP;
  	__be16 type;
  
@@ -134,7 +134,7 @@
  	net_timestamp_check(!READ_ONCE(netdev_tstamp_prequeue), skb);
  
  	trace_netif_receive_skb(skb);
-@@ -5326,6 +5343,15 @@ another_round:
+@@ -5329,6 +5346,15 @@ another_round:
  			goto out;
  	}
  
diff --git a/target/linux/generic/hack-5.4/721-phy_packets.patch b/target/linux/generic/hack-5.4/721-phy_packets.patch
index 6f9742f572420e..89d5b965a2f59b 100644
--- a/target/linux/generic/hack-5.4/721-phy_packets.patch
+++ b/target/linux/generic/hack-5.4/721-phy_packets.patch
@@ -101,7 +101,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	help
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3204,10 +3204,20 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3212,10 +3212,20 @@ static int xmit_one(struct sk_buff *skb,
  	if (dev_nit_active(dev))
  		dev_queue_xmit_nit(skb, dev);
  
diff --git a/target/linux/generic/hack-5.4/902-debloat_proc.patch b/target/linux/generic/hack-5.4/902-debloat_proc.patch
index 07b556e5bd9232..c980dfe411320e 100644
--- a/target/linux/generic/hack-5.4/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.4/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -3672,6 +3672,8 @@ static __net_initdata struct pernet_oper
+@@ -3673,6 +3673,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-5.4/953-net-patch-linux-kernel-to-support-shortcut-fe.patch b/target/linux/generic/hack-5.4/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
index b1a56f253bc810..514f614e448f5f 100644
--- a/target/linux/generic/hack-5.4/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
+++ b/target/linux/generic/hack-5.4/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -80,7 +80,7 @@
  	struct net_bridge_port *p;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3201,9 +3201,17 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3209,9 +3209,17 @@ static int xmit_one(struct sk_buff *skb,
  	unsigned int len;
  	int rc;
  
@@ -99,7 +99,7 @@
  #ifdef CONFIG_ETHERNET_PACKET_MANGLE
  	if (!dev->eth_mangle_tx ||
  	    (skb = dev->eth_mangle_tx(dev, skb)) != NULL)
-@@ -4721,6 +4729,11 @@ void netdev_rx_handler_unregister(struct
+@@ -4729,6 +4737,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
  
@@ -111,7 +111,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -4771,6 +4784,10 @@ static int __netif_receive_skb_core(stru
+@@ -4779,6 +4792,10 @@ static int __netif_receive_skb_core(stru
  	int ret = NET_RX_DROP;
  	__be16 type;
  
@@ -122,7 +122,7 @@
  	net_timestamp_check(!READ_ONCE(netdev_tstamp_prequeue), skb);
  
  	trace_netif_receive_skb(skb);
-@@ -4810,6 +4827,16 @@ another_round:
+@@ -4818,6 +4835,16 @@ another_round:
  			goto out;
  	}
  
diff --git a/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch b/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch
index a6324c0236dcf4..684e85e219461d 100644
--- a/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch
+++ b/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch
@@ -1,6 +1,6 @@
 --- a/drivers/usb/serial/option.c
 +++ b/drivers/usb/serial/option.c
-@@ -277,6 +277,7 @@ static void option_instat_callback(struc
+@@ -278,6 +278,7 @@ static void option_instat_callback(struc
  #define QUECTEL_PRODUCT_EM061K_LWW		0x6008
  #define QUECTEL_PRODUCT_EM061K_LCN		0x6009
  #define QUECTEL_PRODUCT_EC200T			0x6026
@@ -8,11 +8,11 @@
  #define QUECTEL_PRODUCT_RM500K			0x7001
  
  #define CMOTECH_VENDOR_ID			0x16d8
-@@ -1244,6 +1245,7 @@ static const struct usb_device_id option
+@@ -1246,6 +1247,7 @@ static const struct usb_device_id option
  	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200U, 0xff, 0, 0) },
  	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) },
  	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) },
 +	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200A_CN, 0xff, 0, 0) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EG912Y, 0xff, 0, 0) },
  	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500K, 0xff, 0x00, 0x00) },
  
- 	{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) },
diff --git a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
deleted file mode 100644
index 17eba0b354eb80..00000000000000
--- a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
-From: "Alexandros C. Couloumbis" <alex@ozo.com>
-Date: Fri, 7 Jul 2017 17:14:51 +0200
-Subject: hack: arch: powerpc: drop register save/restore library from modules
-
-Upstream GCC uses a libgcc function for saving/restoring registers. This
-makes the code bigger, and upstream kernels need to carry that function
-for every single kernel module. Our GCC is patched to avoid those
-references, so we can drop the extra bloat for modules.
-
-lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
-Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
----
- arch/powerpc/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -42,19 +42,6 @@ machine-$(CONFIG_PPC64) += 64
- machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
- UTS_MACHINE := $(subst $(space),,$(machine-y))
- 
--# XXX This needs to be before we override LD below
--ifdef CONFIG_PPC32
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--else
--ifeq ($(call ld-ifversion, -ge, 22500, y),y)
--# Have the linker provide sfpr if possible.
--# There is a corresponding test in arch/powerpc/lib/Makefile
--KBUILD_LDFLAGS_MODULE += --save-restore-funcs
--else
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--endif
--endif
--
- ifdef CONFIG_CPU_LITTLE_ENDIAN
- KBUILD_CFLAGS	+= -mlittle-endian
- KBUILD_LDFLAGS	+= -EL
diff --git a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index daaebdfb6894af..cecf4c21269b23 100644
--- a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -677,7 +677,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +};
 +
 +static int nf_flow_rule_route_inet(struct net *net,
-+				   const struct flow_offload *flow,
++				   struct flow_offload *flow,
 +				   enum flow_offload_tuple_dir dir,
 +				   struct nf_flow_rule *flow_rule)
 +{
@@ -778,7 +778,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		      void (*iter)(struct nf_flowtable *flowtable,
  				   struct flow_offload *flow, void *data),
  		      void *data)
-@@ -436,6 +434,7 @@ static void nf_flow_offload_gc_step(stru
+@@ -443,6 +441,7 @@ static void nf_flow_offload_gc_step(stru
  		nf_flow_offload_stats(flow_table, flow);
  	}
  }
@@ -808,7 +808,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +#endif /* _XT_FLOWOFFLOAD_H */
 --- a/include/net/netfilter/nf_flow_table.h
 +++ b/include/net/netfilter/nf_flow_table.h
-@@ -280,6 +280,11 @@ void nf_flow_table_free(struct nf_flowta
+@@ -293,6 +293,11 @@ void nf_flow_table_free(struct nf_flowta
  
  void flow_offload_teardown(struct flow_offload *flow);
  
diff --git a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
index 3219d9ec540c4b..6d47bcdb480bb8 100644
--- a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	help
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3619,6 +3619,11 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3622,6 +3622,11 @@ static int xmit_one(struct sk_buff *skb,
  	if (dev_nit_active(dev))
  		dev_queue_xmit_nit(skb, dev);
  
diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
index 51f939356f176b..b4177eea624a96 100644
--- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
+++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
@@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  
  #define QUECTEL_VENDOR_ID			0x2c7c
  /* These Quectel products use Quectel's vendor ID */
-@@ -1147,6 +1152,11 @@ static const struct usb_device_id option
+@@ -1148,6 +1153,11 @@ static const struct usb_device_id option
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
  	  .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  	/* Quectel products using Qualcomm vendor ID */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1188,6 +1198,11 @@ static const struct usb_device_id option
+@@ -1189,6 +1199,11 @@ static const struct usb_device_id option
  	  .driver_info = ZLP },
  	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
index a300dc851862fc..c0322a29ff1a2f 100644
--- a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -2180,9 +2194,11 @@ static void __sk_free(struct sock *sk)
+@@ -2187,9 +2201,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch
index df28c85b694ddc..6db166fb313d8b 100644
--- a/target/linux/generic/hack-6.1/902-debloat_proc.patch
+++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -4105,6 +4105,8 @@ static __net_initdata struct pernet_oper
+@@ -4113,6 +4113,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-6.1/953-net-patch-linux-kernel-to-support-shortcut-fe.patch b/target/linux/generic/hack-6.1/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
index 13f9004cfe628f..985e737aaaa3e4 100644
--- a/target/linux/generic/hack-6.1/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
+++ b/target/linux/generic/hack-6.1/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -92,7 +92,7 @@
  	struct net_bridge_port *p;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3615,9 +3615,17 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3618,9 +3618,17 @@ static int xmit_one(struct sk_buff *skb,
  {
  	unsigned int len;
  	int rc;
@@ -111,7 +111,7 @@
  
  #ifdef CONFIG_ETHERNET_PACKET_MANGLE
  	if (dev->eth_mangle_tx && !(skb = dev->eth_mangle_tx(dev, skb)))
-@@ -5278,6 +5286,11 @@ void netdev_rx_handler_unregister(struct
+@@ -5281,6 +5289,11 @@ void netdev_rx_handler_unregister(struct
  }
  EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
  
@@ -123,7 +123,7 @@
  /*
   * Limit the use of PFMEMALLOC reserves to those protocols that implement
   * the special handling of PFMEMALLOC skbs.
-@@ -5326,6 +5339,10 @@ static int __netif_receive_skb_core(stru
+@@ -5329,6 +5342,10 @@ static int __netif_receive_skb_core(stru
  	int ret = NET_RX_DROP;
  	__be16 type;
  
@@ -134,7 +134,7 @@
  	net_timestamp_check(!READ_ONCE(netdev_tstamp_prequeue), skb);
  
  	trace_netif_receive_skb(skb);
-@@ -5363,6 +5380,15 @@ another_round:
+@@ -5366,6 +5383,15 @@ another_round:
  			goto out;
  	}
  
diff --git a/target/linux/generic/hack-6.6/204-module_strip.patch b/target/linux/generic/hack-6.6/204-module_strip.patch
new file mode 100644
index 00000000000000..850cdeb886c475
--- /dev/null
+++ b/target/linux/generic/hack-6.6/204-module_strip.patch
@@ -0,0 +1,174 @@
+From a779a482fb9b9f8fcdf8b2519c789b4b9bb5dd05 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 16:56:48 +0200
+Subject: build: add a hack for removing non-essential module info
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/linux/module.h      | 13 ++++++++-----
+ include/linux/moduleparam.h | 15 ++++++++++++---
+ init/Kconfig                |  7 +++++++
+ kernel/module.c             |  5 ++++-
+ scripts/mod/modpost.c       | 12 ++++++++++++
+ 5 files changed, 43 insertions(+), 9 deletions(-)
+
+--- a/include/linux/module.h
++++ b/include/linux/module.h
+@@ -164,6 +164,7 @@ extern void cleanup_module(void);
+ 
+ /* Generic info of form tag = "info" */
+ #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info)
++#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info)
+ 
+ /* For userspace: you can also call me... */
+ #define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias)
+@@ -233,12 +234,12 @@ extern void cleanup_module(void);
+  * Author(s), use "Name <email>" or just "Name", for multiple
+  * authors use multiple MODULE_AUTHOR() statements/lines.
+  */
+-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author)
++#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author)
+ 
+ /* What your module does. */
+-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description)
++#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description)
+ 
+-#ifdef MODULE
++#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED)
+ /* Creates an alias so file2alias.c can find device table. */
+ #define MODULE_DEVICE_TABLE(type, name)					\
+ extern typeof(name) __mod_##type##__##name##_device_table		\
+@@ -265,7 +266,9 @@ extern typeof(name) __mod_##type##__##na
+  */
+ 
+ #if defined(MODULE) || !defined(CONFIG_SYSFS)
+-#define MODULE_VERSION(_version) MODULE_INFO(version, _version)
++#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version)
++#elif defined(CONFIG_MODULE_STRIPPED)
++#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version)
+ #else
+ #define MODULE_VERSION(_version)					\
+ 	MODULE_INFO(version, _version);					\
+@@ -288,7 +291,7 @@ extern typeof(name) __mod_##type##__##na
+ /* Optional firmware file (or files) needed by the module
+  * format is simply firmware file name.  Multiple firmware
+  * files require multiple MODULE_FIRMWARE() specifiers */
+-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware)
++#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware)
+ 
+ #define MODULE_IMPORT_NS(ns)	MODULE_INFO(import_ns, __stringify(ns))
+ 
+--- a/include/linux/moduleparam.h
++++ b/include/linux/moduleparam.h
+@@ -20,6 +20,16 @@
+ /* Chosen so that structs with an unsigned long line up. */
+ #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long))
+ 
++/* This struct is here for syntactic coherency, it is not used */
++#define __MODULE_INFO_DISABLED(name)					  \
++  struct __UNIQUE_ID(name) {}
++
++#ifdef CONFIG_MODULE_STRIPPED
++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name)
++#else
++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info)
++#endif
++
+ #define __MODULE_INFO(tag, name, info)					  \
+ 	static const char __UNIQUE_ID(name)[]				  \
+ 		__used __section(".modinfo") __aligned(1)		  \
+@@ -31,7 +41,7 @@
+ /* One for each parameter, describing how to use it.  Some files do
+    multiple of these per line, so can't just use MODULE_INFO. */
+ #define MODULE_PARM_DESC(_parm, desc) \
+-	__MODULE_INFO(parm, _parm, #_parm ":" desc)
++	__MODULE_INFO_STRIP(parm, _parm, #_parm ":" desc)
+ 
+ struct kernel_param;
+ 
+--- a/kernel/module/Kconfig
++++ b/kernel/module/Kconfig
+@@ -385,6 +385,13 @@ config UNUSED_KSYMS_WHITELIST
+ 	  one per line. The path can be absolute, or relative to the kernel
+ 	  source tree.
+ 
++config MODULE_STRIPPED
++	bool "Reduce module size"
++	depends on MODULES
++	help
++	  Remove module parameter descriptions, author info, version, aliases,
++	  device tables, etc.
++
+ config MODULES_TREE_LOOKUP
+ 	def_bool y
+ 	depends on PERF_EVENTS || TRACING || CFI_CLANG
+--- a/kernel/module/main.c
++++ b/kernel/module/main.c
+@@ -2075,9 +2075,11 @@ static void module_augment_kernel_taints
+ 
+ static int check_modinfo(struct module *mod, struct load_info *info, int flags)
+ {
+-	const char *modmagic = get_modinfo(info, "vermagic");
+ 	int err;
+ 
++#ifndef CONFIG_MODULE_STRIPPED
++	const char *modmagic = get_modinfo(info, "vermagic");
++
+ 	if (flags & MODULE_INIT_IGNORE_VERMAGIC)
+ 		modmagic = NULL;
+ 
+@@ -2091,6 +2093,7 @@ static int check_modinfo(struct module *
+ 		       info->name, modmagic, vermagic);
+ 		return -ENOEXEC;
+ 	}
++#endif
+ 
+ 	err = check_modinfo_livepatch(mod, info);
+ 	if (err)
+--- a/scripts/mod/modpost.c
++++ b/scripts/mod/modpost.c
+@@ -1753,7 +1753,9 @@ static void read_symbols(const char *mod
+ 		symname = remove_dot(info.strtab + sym->st_name);
+ 
+ 		handle_symbol(mod, &info, sym, symname);
++#ifndef CONFIG_MODULE_STRIPPED
+ 		handle_moddevtable(mod, &info, sym, symname);
++#endif
+ 	}
+ 
+ 	check_sec_ref(mod, &info);
+@@ -1926,8 +1928,10 @@ static void add_header(struct buffer *b,
+ 	buf_printf(b, "BUILD_SALT;\n");
+ 	buf_printf(b, "BUILD_LTO_INFO;\n");
+ 	buf_printf(b, "\n");
++#ifndef CONFIG_MODULE_STRIPPED
+ 	buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n");
+ 	buf_printf(b, "MODULE_INFO(name, KBUILD_MODNAME);\n");
++#endif
+ 	buf_printf(b, "\n");
+ 	buf_printf(b, "__visible struct module __this_module\n");
+ 	buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n");
+@@ -2061,11 +2065,13 @@ static void add_depends(struct buffer *b
+ 
+ static void add_srcversion(struct buffer *b, struct module *mod)
+ {
++#ifndef CONFIG_MODULE_STRIPPED
+ 	if (mod->srcversion[0]) {
+ 		buf_printf(b, "\n");
+ 		buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n",
+ 			   mod->srcversion);
+ 	}
++#endif
+ }
+ 
+ static void write_buf(struct buffer *b, const char *fname)
+@@ -2148,7 +2154,9 @@ static void write_mod_c_file(struct modu
+ 	add_exported_symbols(&buf, mod);
+ 	add_versions(&buf, mod);
+ 	add_depends(&buf, mod);
++#ifndef CONFIG_MODULE_STRIPPED
+ 	add_moddevtable(&buf, mod);
++#endif
+ 	add_srcversion(&buf, mod);
+ 
+ 	ret = snprintf(fname, sizeof(fname), "%s.mod.c", mod->name);
diff --git a/target/linux/generic/hack-6.6/205-kconfig-exit.patch b/target/linux/generic/hack-6.6/205-kconfig-exit.patch
new file mode 100644
index 00000000000000..f1b50283daa14b
--- /dev/null
+++ b/target/linux/generic/hack-6.6/205-kconfig-exit.patch
@@ -0,0 +1,11 @@
+--- a/scripts/kconfig/conf.c
++++ b/scripts/kconfig/conf.c
+@@ -432,6 +432,8 @@ static int conf_sym(struct menu *menu)
+ 				break;
+ 			continue;
+ 		case 0:
++			if (!sym_has_value(sym) && !tty_stdio && getenv("FAIL_ON_UNCONFIGURED"))
++				exit(1);
+ 			newval = oldval;
+ 			break;
+ 		case '?':
diff --git a/target/linux/generic/hack-6.6/210-darwin_scripts_include.patch b/target/linux/generic/hack-6.6/210-darwin_scripts_include.patch
new file mode 100644
index 00000000000000..c9612536dec6e5
--- /dev/null
+++ b/target/linux/generic/hack-6.6/210-darwin_scripts_include.patch
@@ -0,0 +1,3053 @@
+From db7c30dcd9a0391bf13b62c9f91e144d762ef43a Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Fri, 7 Jul 2017 17:00:49 +0200
+Subject: Add an OSX specific patch to make the kernel be compiled
+
+lede-commit: 3fc2a24f0422b2f55f9ed43f116db3111f700526
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ scripts/kconfig/Makefile   |    3 +
+ scripts/mod/elf.h          | 3007 ++++++++++++++++++++++++++++++++++++++++++++
+ scripts/mod/mk_elfconfig.c |    4 +
+ scripts/mod/modpost.h      |    4 +
+ 4 files changed, 3018 insertions(+)
+ create mode 100644 scripts/mod/elf.h
+
+--- /dev/null
++++ b/scripts/mod/elf.h
+@@ -0,0 +1,3007 @@
++/* This file defines standard ELF types, structures, and macros.
++   Copyright (C) 1995-2012 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, see
++   <http://www.gnu.org/licenses/>.  */
++
++#ifndef _ELF_H
++#define	_ELF_H 1
++
++/* Standard ELF types.  */
++
++#include <stdint.h>
++
++/* Type for a 16-bit quantity.  */
++typedef uint16_t Elf32_Half;
++typedef uint16_t Elf64_Half;
++
++/* Types for signed and unsigned 32-bit quantities.  */
++typedef uint32_t Elf32_Word;
++typedef	int32_t  Elf32_Sword;
++typedef uint32_t Elf64_Word;
++typedef	int32_t  Elf64_Sword;
++
++/* Types for signed and unsigned 64-bit quantities.  */
++typedef uint64_t Elf32_Xword;
++typedef	int64_t  Elf32_Sxword;
++typedef uint64_t Elf64_Xword;
++typedef	int64_t  Elf64_Sxword;
++
++/* Type of addresses.  */
++typedef uint32_t Elf32_Addr;
++typedef uint64_t Elf64_Addr;
++
++/* Type of file offsets.  */
++typedef uint32_t Elf32_Off;
++typedef uint64_t Elf64_Off;
++
++/* Type for section indices, which are 16-bit quantities.  */
++typedef uint16_t Elf32_Section;
++typedef uint16_t Elf64_Section;
++
++/* Type for version symbol information.  */
++typedef Elf32_Half Elf32_Versym;
++typedef Elf64_Half Elf64_Versym;
++
++
++/* The ELF file header.  This appears at the start of every ELF file.  */
++
++#define EI_NIDENT (16)
++
++typedef struct
++{
++  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
++  Elf32_Half	e_type;			/* Object file type */
++  Elf32_Half	e_machine;		/* Architecture */
++  Elf32_Word	e_version;		/* Object file version */
++  Elf32_Addr	e_entry;		/* Entry point virtual address */
++  Elf32_Off	e_phoff;		/* Program header table file offset */
++  Elf32_Off	e_shoff;		/* Section header table file offset */
++  Elf32_Word	e_flags;		/* Processor-specific flags */
++  Elf32_Half	e_ehsize;		/* ELF header size in bytes */
++  Elf32_Half	e_phentsize;		/* Program header table entry size */
++  Elf32_Half	e_phnum;		/* Program header table entry count */
++  Elf32_Half	e_shentsize;		/* Section header table entry size */
++  Elf32_Half	e_shnum;		/* Section header table entry count */
++  Elf32_Half	e_shstrndx;		/* Section header string table index */
++} Elf32_Ehdr;
++
++typedef struct
++{
++  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
++  Elf64_Half	e_type;			/* Object file type */
++  Elf64_Half	e_machine;		/* Architecture */
++  Elf64_Word	e_version;		/* Object file version */
++  Elf64_Addr	e_entry;		/* Entry point virtual address */
++  Elf64_Off	e_phoff;		/* Program header table file offset */
++  Elf64_Off	e_shoff;		/* Section header table file offset */
++  Elf64_Word	e_flags;		/* Processor-specific flags */
++  Elf64_Half	e_ehsize;		/* ELF header size in bytes */
++  Elf64_Half	e_phentsize;		/* Program header table entry size */
++  Elf64_Half	e_phnum;		/* Program header table entry count */
++  Elf64_Half	e_shentsize;		/* Section header table entry size */
++  Elf64_Half	e_shnum;		/* Section header table entry count */
++  Elf64_Half	e_shstrndx;		/* Section header string table index */
++} Elf64_Ehdr;
++
++/* Fields in the e_ident array.  The EI_* macros are indices into the
++   array.  The macros under each EI_* macro are the values the byte
++   may have.  */
++
++#define EI_MAG0		0		/* File identification byte 0 index */
++#define ELFMAG0		0x7f		/* Magic number byte 0 */
++
++#define EI_MAG1		1		/* File identification byte 1 index */
++#define ELFMAG1		'E'		/* Magic number byte 1 */
++
++#define EI_MAG2		2		/* File identification byte 2 index */
++#define ELFMAG2		'L'		/* Magic number byte 2 */
++
++#define EI_MAG3		3		/* File identification byte 3 index */
++#define ELFMAG3		'F'		/* Magic number byte 3 */
++
++/* Conglomeration of the identification bytes, for easy testing as a word.  */
++#define	ELFMAG		"\177ELF"
++#define	SELFMAG		4
++
++#define EI_CLASS	4		/* File class byte index */
++#define ELFCLASSNONE	0		/* Invalid class */
++#define ELFCLASS32	1		/* 32-bit objects */
++#define ELFCLASS64	2		/* 64-bit objects */
++#define ELFCLASSNUM	3
++
++#define EI_DATA		5		/* Data encoding byte index */
++#define ELFDATANONE	0		/* Invalid data encoding */
++#define ELFDATA2LSB	1		/* 2's complement, little endian */
++#define ELFDATA2MSB	2		/* 2's complement, big endian */
++#define ELFDATANUM	3
++
++#define EI_VERSION	6		/* File version byte index */
++					/* Value must be EV_CURRENT */
++
++#define EI_OSABI	7		/* OS ABI identification */
++#define ELFOSABI_NONE		0	/* UNIX System V ABI */
++#define ELFOSABI_SYSV		0	/* Alias.  */
++#define ELFOSABI_HPUX		1	/* HP-UX */
++#define ELFOSABI_NETBSD		2	/* NetBSD.  */
++#define ELFOSABI_GNU		3	/* Object uses GNU ELF extensions.  */
++#define ELFOSABI_LINUX		ELFOSABI_GNU /* Compatibility alias.  */
++#define ELFOSABI_SOLARIS	6	/* Sun Solaris.  */
++#define ELFOSABI_AIX		7	/* IBM AIX.  */
++#define ELFOSABI_IRIX		8	/* SGI Irix.  */
++#define ELFOSABI_FREEBSD	9	/* FreeBSD.  */
++#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX.  */
++#define ELFOSABI_MODESTO	11	/* Novell Modesto.  */
++#define ELFOSABI_OPENBSD	12	/* OpenBSD.  */
++#define ELFOSABI_ARM_AEABI	64	/* ARM EABI */
++#define ELFOSABI_ARM		97	/* ARM */
++#define ELFOSABI_STANDALONE	255	/* Standalone (embedded) application */
++
++#define EI_ABIVERSION	8		/* ABI version */
++
++#define EI_PAD		9		/* Byte index of padding bytes */
++
++/* Legal values for e_type (object file type).  */
++
++#define ET_NONE		0		/* No file type */
++#define ET_REL		1		/* Relocatable file */
++#define ET_EXEC		2		/* Executable file */
++#define ET_DYN		3		/* Shared object file */
++#define ET_CORE		4		/* Core file */
++#define	ET_NUM		5		/* Number of defined types */
++#define ET_LOOS		0xfe00		/* OS-specific range start */
++#define ET_HIOS		0xfeff		/* OS-specific range end */
++#define ET_LOPROC	0xff00		/* Processor-specific range start */
++#define ET_HIPROC	0xffff		/* Processor-specific range end */
++
++/* Legal values for e_machine (architecture).  */
++
++#define EM_NONE		 0		/* No machine */
++#define EM_M32		 1		/* AT&T WE 32100 */
++#define EM_SPARC	 2		/* SUN SPARC */
++#define EM_386		 3		/* Intel 80386 */
++#define EM_68K		 4		/* Motorola m68k family */
++#define EM_88K		 5		/* Motorola m88k family */
++#define EM_860		 7		/* Intel 80860 */
++#define EM_MIPS		 8		/* MIPS R3000 big-endian */
++#define EM_S370		 9		/* IBM System/370 */
++#define EM_MIPS_RS3_LE	10		/* MIPS R3000 little-endian */
++
++#define EM_PARISC	15		/* HPPA */
++#define EM_VPP500	17		/* Fujitsu VPP500 */
++#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
++#define EM_960		19		/* Intel 80960 */
++#define EM_PPC		20		/* PowerPC */
++#define EM_PPC64	21		/* PowerPC 64-bit */
++#define EM_S390		22		/* IBM S390 */
++
++#define EM_V800		36		/* NEC V800 series */
++#define EM_FR20		37		/* Fujitsu FR20 */
++#define EM_RH32		38		/* TRW RH-32 */
++#define EM_RCE		39		/* Motorola RCE */
++#define EM_ARM		40		/* ARM */
++#define EM_FAKE_ALPHA	41		/* Digital Alpha */
++#define EM_SH		42		/* Hitachi SH */
++#define EM_SPARCV9	43		/* SPARC v9 64-bit */
++#define EM_TRICORE	44		/* Siemens Tricore */
++#define EM_ARC		45		/* Argonaut RISC Core */
++#define EM_H8_300	46		/* Hitachi H8/300 */
++#define EM_H8_300H	47		/* Hitachi H8/300H */
++#define EM_H8S		48		/* Hitachi H8S */
++#define EM_H8_500	49		/* Hitachi H8/500 */
++#define EM_IA_64	50		/* Intel Merced */
++#define EM_MIPS_X	51		/* Stanford MIPS-X */
++#define EM_COLDFIRE	52		/* Motorola Coldfire */
++#define EM_68HC12	53		/* Motorola M68HC12 */
++#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
++#define EM_PCP		55		/* Siemens PCP */
++#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
++#define EM_NDR1		57		/* Denso NDR1 microprocessor */
++#define EM_STARCORE	58		/* Motorola Start*Core processor */
++#define EM_ME16		59		/* Toyota ME16 processor */
++#define EM_ST100	60		/* STMicroelectronic ST100 processor */
++#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
++#define EM_X86_64	62		/* AMD x86-64 architecture */
++#define EM_PDSP		63		/* Sony DSP Processor */
++
++#define EM_FX66		66		/* Siemens FX66 microcontroller */
++#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
++#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
++#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
++#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
++#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
++#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
++#define EM_SVX		73		/* Silicon Graphics SVx */
++#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
++#define EM_VAX		75		/* Digital VAX */
++#define EM_CRIS		76		/* Axis Communications 32-bit embedded processor */
++#define EM_JAVELIN	77		/* Infineon Technologies 32-bit embedded processor */
++#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
++#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
++#define EM_MMIX		80		/* Donald Knuth's educational 64-bit processor */
++#define EM_HUANY	81		/* Harvard University machine-independent object files */
++#define EM_PRISM	82		/* SiTera Prism */
++#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
++#define EM_FR30		84		/* Fujitsu FR30 */
++#define EM_D10V		85		/* Mitsubishi D10V */
++#define EM_D30V		86		/* Mitsubishi D30V */
++#define EM_V850		87		/* NEC v850 */
++#define EM_M32R		88		/* Mitsubishi M32R */
++#define EM_MN10300	89		/* Matsushita MN10300 */
++#define EM_MN10200	90		/* Matsushita MN10200 */
++#define EM_PJ		91		/* picoJava */
++#define EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
++#define EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
++#define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
++#define EM_TILEPRO	188		/* Tilera TILEPro */
++#define EM_TILEGX	191		/* Tilera TILE-Gx */
++#define EM_NUM		192
++
++/* If it is necessary to assign new unofficial EM_* values, please
++   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
++   chances of collision with official or non-GNU unofficial values.  */
++
++#define EM_ALPHA	0x9026
++
++/* Legal values for e_version (version).  */
++
++#define EV_NONE		0		/* Invalid ELF version */
++#define EV_CURRENT	1		/* Current version */
++#define EV_NUM		2
++
++/* Section header.  */
++
++typedef struct
++{
++  Elf32_Word	sh_name;		/* Section name (string tbl index) */
++  Elf32_Word	sh_type;		/* Section type */
++  Elf32_Word	sh_flags;		/* Section flags */
++  Elf32_Addr	sh_addr;		/* Section virtual addr at execution */
++  Elf32_Off	sh_offset;		/* Section file offset */
++  Elf32_Word	sh_size;		/* Section size in bytes */
++  Elf32_Word	sh_link;		/* Link to another section */
++  Elf32_Word	sh_info;		/* Additional section information */
++  Elf32_Word	sh_addralign;		/* Section alignment */
++  Elf32_Word	sh_entsize;		/* Entry size if section holds table */
++} Elf32_Shdr;
++
++typedef struct
++{
++  Elf64_Word	sh_name;		/* Section name (string tbl index) */
++  Elf64_Word	sh_type;		/* Section type */
++  Elf64_Xword	sh_flags;		/* Section flags */
++  Elf64_Addr	sh_addr;		/* Section virtual addr at execution */
++  Elf64_Off	sh_offset;		/* Section file offset */
++  Elf64_Xword	sh_size;		/* Section size in bytes */
++  Elf64_Word	sh_link;		/* Link to another section */
++  Elf64_Word	sh_info;		/* Additional section information */
++  Elf64_Xword	sh_addralign;		/* Section alignment */
++  Elf64_Xword	sh_entsize;		/* Entry size if section holds table */
++} Elf64_Shdr;
++
++/* Special section indices.  */
++
++#define SHN_UNDEF	0		/* Undefined section */
++#define SHN_LORESERVE	0xff00		/* Start of reserved indices */
++#define SHN_LOPROC	0xff00		/* Start of processor-specific */
++#define SHN_BEFORE	0xff00		/* Order section before all others
++					   (Solaris).  */
++#define SHN_AFTER	0xff01		/* Order section after all others
++					   (Solaris).  */
++#define SHN_HIPROC	0xff1f		/* End of processor-specific */
++#define SHN_LOOS	0xff20		/* Start of OS-specific */
++#define SHN_HIOS	0xff3f		/* End of OS-specific */
++#define SHN_ABS		0xfff1		/* Associated symbol is absolute */
++#define SHN_COMMON	0xfff2		/* Associated symbol is common */
++#define SHN_XINDEX	0xffff		/* Index is in extra table.  */
++#define SHN_HIRESERVE	0xffff		/* End of reserved indices */
++
++/* Legal values for sh_type (section type).  */
++
++#define SHT_NULL	  0		/* Section header table entry unused */
++#define SHT_PROGBITS	  1		/* Program data */
++#define SHT_SYMTAB	  2		/* Symbol table */
++#define SHT_STRTAB	  3		/* String table */
++#define SHT_RELA	  4		/* Relocation entries with addends */
++#define SHT_HASH	  5		/* Symbol hash table */
++#define SHT_DYNAMIC	  6		/* Dynamic linking information */
++#define SHT_NOTE	  7		/* Notes */
++#define SHT_NOBITS	  8		/* Program space with no data (bss) */
++#define SHT_REL		  9		/* Relocation entries, no addends */
++#define SHT_SHLIB	  10		/* Reserved */
++#define SHT_DYNSYM	  11		/* Dynamic linker symbol table */
++#define SHT_INIT_ARRAY	  14		/* Array of constructors */
++#define SHT_FINI_ARRAY	  15		/* Array of destructors */
++#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
++#define SHT_GROUP	  17		/* Section group */
++#define SHT_SYMTAB_SHNDX  18		/* Extended section indeces */
++#define	SHT_NUM		  19		/* Number of defined types.  */
++#define SHT_LOOS	  0x60000000	/* Start OS-specific.  */
++#define SHT_GNU_ATTRIBUTES 0x6ffffff5	/* Object attributes.  */
++#define SHT_GNU_HASH	  0x6ffffff6	/* GNU-style hash table.  */
++#define SHT_GNU_LIBLIST	  0x6ffffff7	/* Prelink library list */
++#define SHT_CHECKSUM	  0x6ffffff8	/* Checksum for DSO content.  */
++#define SHT_LOSUNW	  0x6ffffffa	/* Sun-specific low bound.  */
++#define SHT_SUNW_move	  0x6ffffffa
++#define SHT_SUNW_COMDAT   0x6ffffffb
++#define SHT_SUNW_syminfo  0x6ffffffc
++#define SHT_GNU_verdef	  0x6ffffffd	/* Version definition section.  */
++#define SHT_GNU_verneed	  0x6ffffffe	/* Version needs section.  */
++#define SHT_GNU_versym	  0x6fffffff	/* Version symbol table.  */
++#define SHT_HISUNW	  0x6fffffff	/* Sun-specific high bound.  */
++#define SHT_HIOS	  0x6fffffff	/* End OS-specific type */
++#define SHT_LOPROC	  0x70000000	/* Start of processor-specific */
++#define SHT_HIPROC	  0x7fffffff	/* End of processor-specific */
++#define SHT_LOUSER	  0x80000000	/* Start of application-specific */
++#define SHT_HIUSER	  0x8fffffff	/* End of application-specific */
++
++/* Legal values for sh_flags (section flags).  */
++
++#define SHF_WRITE	     (1 << 0)	/* Writable */
++#define SHF_ALLOC	     (1 << 1)	/* Occupies memory during execution */
++#define SHF_EXECINSTR	     (1 << 2)	/* Executable */
++#define SHF_MERGE	     (1 << 4)	/* Might be merged */
++#define SHF_STRINGS	     (1 << 5)	/* Contains nul-terminated strings */
++#define SHF_INFO_LINK	     (1 << 6)	/* `sh_info' contains SHT index */
++#define SHF_LINK_ORDER	     (1 << 7)	/* Preserve order after combining */
++#define SHF_OS_NONCONFORMING (1 << 8)	/* Non-standard OS specific handling
++					   required */
++#define SHF_GROUP	     (1 << 9)	/* Section is member of a group.  */
++#define SHF_TLS		     (1 << 10)	/* Section hold thread-local data.  */
++#define SHF_MASKOS	     0x0ff00000	/* OS-specific.  */
++#define SHF_MASKPROC	     0xf0000000	/* Processor-specific */
++#define SHF_ORDERED	     (1 << 30)	/* Special ordering requirement
++					   (Solaris).  */
++#define SHF_EXCLUDE	     (1 << 31)	/* Section is excluded unless
++					   referenced or allocated (Solaris).*/
++
++/* Section group handling.  */
++#define GRP_COMDAT	0x1		/* Mark group as COMDAT.  */
++
++/* Symbol table entry.  */
++
++typedef struct
++{
++  Elf32_Word	st_name;		/* Symbol name (string tbl index) */
++  Elf32_Addr	st_value;		/* Symbol value */
++  Elf32_Word	st_size;		/* Symbol size */
++  unsigned char	st_info;		/* Symbol type and binding */
++  unsigned char	st_other;		/* Symbol visibility */
++  Elf32_Section	st_shndx;		/* Section index */
++} Elf32_Sym;
++
++typedef struct
++{
++  Elf64_Word	st_name;		/* Symbol name (string tbl index) */
++  unsigned char	st_info;		/* Symbol type and binding */
++  unsigned char st_other;		/* Symbol visibility */
++  Elf64_Section	st_shndx;		/* Section index */
++  Elf64_Addr	st_value;		/* Symbol value */
++  Elf64_Xword	st_size;		/* Symbol size */
++} Elf64_Sym;
++
++/* The syminfo section if available contains additional information about
++   every dynamic symbol.  */
++
++typedef struct
++{
++  Elf32_Half si_boundto;		/* Direct bindings, symbol bound to */
++  Elf32_Half si_flags;			/* Per symbol flags */
++} Elf32_Syminfo;
++
++typedef struct
++{
++  Elf64_Half si_boundto;		/* Direct bindings, symbol bound to */
++  Elf64_Half si_flags;			/* Per symbol flags */
++} Elf64_Syminfo;
++
++/* Possible values for si_boundto.  */
++#define SYMINFO_BT_SELF		0xffff	/* Symbol bound to self */
++#define SYMINFO_BT_PARENT	0xfffe	/* Symbol bound to parent */
++#define SYMINFO_BT_LOWRESERVE	0xff00	/* Beginning of reserved entries */
++
++/* Possible bitmasks for si_flags.  */
++#define SYMINFO_FLG_DIRECT	0x0001	/* Direct bound symbol */
++#define SYMINFO_FLG_PASSTHRU	0x0002	/* Pass-thru symbol for translator */
++#define SYMINFO_FLG_COPY	0x0004	/* Symbol is a copy-reloc */
++#define SYMINFO_FLG_LAZYLOAD	0x0008	/* Symbol bound to object to be lazy
++					   loaded */
++/* Syminfo version values.  */
++#define SYMINFO_NONE		0
++#define SYMINFO_CURRENT		1
++#define SYMINFO_NUM		2
++
++
++/* How to extract and insert information held in the st_info field.  */
++
++#define ELF32_ST_BIND(val)		(((unsigned char) (val)) >> 4)
++#define ELF32_ST_TYPE(val)		((val) & 0xf)
++#define ELF32_ST_INFO(bind, type)	(((bind) << 4) + ((type) & 0xf))
++
++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */
++#define ELF64_ST_BIND(val)		ELF32_ST_BIND (val)
++#define ELF64_ST_TYPE(val)		ELF32_ST_TYPE (val)
++#define ELF64_ST_INFO(bind, type)	ELF32_ST_INFO ((bind), (type))
++
++/* Legal values for ST_BIND subfield of st_info (symbol binding).  */
++
++#define STB_LOCAL	0		/* Local symbol */
++#define STB_GLOBAL	1		/* Global symbol */
++#define STB_WEAK	2		/* Weak symbol */
++#define	STB_NUM		3		/* Number of defined types.  */
++#define STB_LOOS	10		/* Start of OS-specific */
++#define STB_GNU_UNIQUE	10		/* Unique symbol.  */
++#define STB_HIOS	12		/* End of OS-specific */
++#define STB_LOPROC	13		/* Start of processor-specific */
++#define STB_HIPROC	15		/* End of processor-specific */
++
++/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
++
++#define STT_NOTYPE	0		/* Symbol type is unspecified */
++#define STT_OBJECT	1		/* Symbol is a data object */
++#define STT_FUNC	2		/* Symbol is a code object */
++#define STT_SECTION	3		/* Symbol associated with a section */
++#define STT_FILE	4		/* Symbol's name is file name */
++#define STT_COMMON	5		/* Symbol is a common data object */
++#define STT_TLS		6		/* Symbol is thread-local data object*/
++#define	STT_NUM		7		/* Number of defined types.  */
++#define STT_LOOS	10		/* Start of OS-specific */
++#define STT_GNU_IFUNC	10		/* Symbol is indirect code object */
++#define STT_HIOS	12		/* End of OS-specific */
++#define STT_LOPROC	13		/* Start of processor-specific */
++#define STT_HIPROC	15		/* End of processor-specific */
++
++
++/* Symbol table indices are found in the hash buckets and chain table
++   of a symbol hash table section.  This special index value indicates
++   the end of a chain, meaning no further symbols are found in that bucket.  */
++
++#define STN_UNDEF	0		/* End of a chain.  */
++
++
++/* How to extract and insert information held in the st_other field.  */
++
++#define ELF32_ST_VISIBILITY(o)	((o) & 0x03)
++
++/* For ELF64 the definitions are the same.  */
++#define ELF64_ST_VISIBILITY(o)	ELF32_ST_VISIBILITY (o)
++
++/* Symbol visibility specification encoded in the st_other field.  */
++#define STV_DEFAULT	0		/* Default symbol visibility rules */
++#define STV_INTERNAL	1		/* Processor specific hidden class */
++#define STV_HIDDEN	2		/* Sym unavailable in other modules */
++#define STV_PROTECTED	3		/* Not preemptible, not exported */
++
++
++/* Relocation table entry without addend (in section of type SHT_REL).  */
++
++typedef struct
++{
++  Elf32_Addr	r_offset;		/* Address */
++  Elf32_Word	r_info;			/* Relocation type and symbol index */
++} Elf32_Rel;
++
++/* I have seen two different definitions of the Elf64_Rel and
++   Elf64_Rela structures, so we'll leave them out until Novell (or
++   whoever) gets their act together.  */
++/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */
++
++typedef struct
++{
++  Elf64_Addr	r_offset;		/* Address */
++  Elf64_Xword	r_info;			/* Relocation type and symbol index */
++} Elf64_Rel;
++
++/* Relocation table entry with addend (in section of type SHT_RELA).  */
++
++typedef struct
++{
++  Elf32_Addr	r_offset;		/* Address */
++  Elf32_Word	r_info;			/* Relocation type and symbol index */
++  Elf32_Sword	r_addend;		/* Addend */
++} Elf32_Rela;
++
++typedef struct
++{
++  Elf64_Addr	r_offset;		/* Address */
++  Elf64_Xword	r_info;			/* Relocation type and symbol index */
++  Elf64_Sxword	r_addend;		/* Addend */
++} Elf64_Rela;
++
++/* How to extract and insert information held in the r_info field.  */
++
++#define ELF32_R_SYM(val)		((val) >> 8)
++#define ELF32_R_TYPE(val)		((val) & 0xff)
++#define ELF32_R_INFO(sym, type)		(((sym) << 8) + ((type) & 0xff))
++
++#define ELF64_R_SYM(i)			((i) >> 32)
++#define ELF64_R_TYPE(i)			((i) & 0xffffffff)
++#define ELF64_R_INFO(sym,type)		((((Elf64_Xword) (sym)) << 32) + (type))
++
++/* Program segment header.  */
++
++typedef struct
++{
++  Elf32_Word	p_type;			/* Segment type */
++  Elf32_Off	p_offset;		/* Segment file offset */
++  Elf32_Addr	p_vaddr;		/* Segment virtual address */
++  Elf32_Addr	p_paddr;		/* Segment physical address */
++  Elf32_Word	p_filesz;		/* Segment size in file */
++  Elf32_Word	p_memsz;		/* Segment size in memory */
++  Elf32_Word	p_flags;		/* Segment flags */
++  Elf32_Word	p_align;		/* Segment alignment */
++} Elf32_Phdr;
++
++typedef struct
++{
++  Elf64_Word	p_type;			/* Segment type */
++  Elf64_Word	p_flags;		/* Segment flags */
++  Elf64_Off	p_offset;		/* Segment file offset */
++  Elf64_Addr	p_vaddr;		/* Segment virtual address */
++  Elf64_Addr	p_paddr;		/* Segment physical address */
++  Elf64_Xword	p_filesz;		/* Segment size in file */
++  Elf64_Xword	p_memsz;		/* Segment size in memory */
++  Elf64_Xword	p_align;		/* Segment alignment */
++} Elf64_Phdr;
++
++/* Special value for e_phnum.  This indicates that the real number of
++   program headers is too large to fit into e_phnum.  Instead the real
++   value is in the field sh_info of section 0.  */
++
++#define PN_XNUM		0xffff
++
++/* Legal values for p_type (segment type).  */
++
++#define	PT_NULL		0		/* Program header table entry unused */
++#define PT_LOAD		1		/* Loadable program segment */
++#define PT_DYNAMIC	2		/* Dynamic linking information */
++#define PT_INTERP	3		/* Program interpreter */
++#define PT_NOTE		4		/* Auxiliary information */
++#define PT_SHLIB	5		/* Reserved */
++#define PT_PHDR		6		/* Entry for header table itself */
++#define PT_TLS		7		/* Thread-local storage segment */
++#define	PT_NUM		8		/* Number of defined types */
++#define PT_LOOS		0x60000000	/* Start of OS-specific */
++#define PT_GNU_EH_FRAME	0x6474e550	/* GCC .eh_frame_hdr segment */
++#define PT_GNU_STACK	0x6474e551	/* Indicates stack executability */
++#define PT_GNU_RELRO	0x6474e552	/* Read-only after relocation */
++#define PT_LOSUNW	0x6ffffffa
++#define PT_SUNWBSS	0x6ffffffa	/* Sun Specific segment */
++#define PT_SUNWSTACK	0x6ffffffb	/* Stack segment */
++#define PT_HISUNW	0x6fffffff
++#define PT_HIOS		0x6fffffff	/* End of OS-specific */
++#define PT_LOPROC	0x70000000	/* Start of processor-specific */
++#define PT_HIPROC	0x7fffffff	/* End of processor-specific */
++
++/* Legal values for p_flags (segment flags).  */
++
++#define PF_X		(1 << 0)	/* Segment is executable */
++#define PF_W		(1 << 1)	/* Segment is writable */
++#define PF_R		(1 << 2)	/* Segment is readable */
++#define PF_MASKOS	0x0ff00000	/* OS-specific */
++#define PF_MASKPROC	0xf0000000	/* Processor-specific */
++
++/* Legal values for note segment descriptor types for core files. */
++
++#define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
++#define NT_FPREGSET	2		/* Contains copy of fpregset struct */
++#define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
++#define NT_PRXREG	4		/* Contains copy of prxregset struct */
++#define NT_TASKSTRUCT	4		/* Contains copy of task structure */
++#define NT_PLATFORM	5		/* String from sysinfo(SI_PLATFORM) */
++#define NT_AUXV		6		/* Contains copy of auxv array */
++#define NT_GWINDOWS	7		/* Contains copy of gwindows struct */
++#define NT_ASRS		8		/* Contains copy of asrset struct */
++#define NT_PSTATUS	10		/* Contains copy of pstatus struct */
++#define NT_PSINFO	13		/* Contains copy of psinfo struct */
++#define NT_PRCRED	14		/* Contains copy of prcred struct */
++#define NT_UTSNAME	15		/* Contains copy of utsname struct */
++#define NT_LWPSTATUS	16		/* Contains copy of lwpstatus struct */
++#define NT_LWPSINFO	17		/* Contains copy of lwpinfo struct */
++#define NT_PRFPXREG	20		/* Contains copy of fprxregset struct */
++#define NT_PRXFPREG	0x46e62b7f	/* Contains copy of user_fxsr_struct */
++#define NT_PPC_VMX	0x100		/* PowerPC Altivec/VMX registers */
++#define NT_PPC_SPE	0x101		/* PowerPC SPE/EVR registers */
++#define NT_PPC_VSX	0x102		/* PowerPC VSX registers */
++#define NT_386_TLS	0x200		/* i386 TLS slots (struct user_desc) */
++#define NT_386_IOPERM	0x201		/* x86 io permission bitmap (1=deny) */
++#define NT_X86_XSTATE	0x202		/* x86 extended state using xsave */
++
++/* Legal values for the note segment descriptor types for object files.  */
++
++#define NT_VERSION	1		/* Contains a version string.  */
++
++
++/* Dynamic section entry.  */
++
++typedef struct
++{
++  Elf32_Sword	d_tag;			/* Dynamic entry type */
++  union
++    {
++      Elf32_Word d_val;			/* Integer value */
++      Elf32_Addr d_ptr;			/* Address value */
++    } d_un;
++} Elf32_Dyn;
++
++typedef struct
++{
++  Elf64_Sxword	d_tag;			/* Dynamic entry type */
++  union
++    {
++      Elf64_Xword d_val;		/* Integer value */
++      Elf64_Addr d_ptr;			/* Address value */
++    } d_un;
++} Elf64_Dyn;
++
++/* Legal values for d_tag (dynamic entry type).  */
++
++#define DT_NULL		0		/* Marks end of dynamic section */
++#define DT_NEEDED	1		/* Name of needed library */
++#define DT_PLTRELSZ	2		/* Size in bytes of PLT relocs */
++#define DT_PLTGOT	3		/* Processor defined value */
++#define DT_HASH		4		/* Address of symbol hash table */
++#define DT_STRTAB	5		/* Address of string table */
++#define DT_SYMTAB	6		/* Address of symbol table */
++#define DT_RELA		7		/* Address of Rela relocs */
++#define DT_RELASZ	8		/* Total size of Rela relocs */
++#define DT_RELAENT	9		/* Size of one Rela reloc */
++#define DT_STRSZ	10		/* Size of string table */
++#define DT_SYMENT	11		/* Size of one symbol table entry */
++#define DT_INIT		12		/* Address of init function */
++#define DT_FINI		13		/* Address of termination function */
++#define DT_SONAME	14		/* Name of shared object */
++#define DT_RPATH	15		/* Library search path (deprecated) */
++#define DT_SYMBOLIC	16		/* Start symbol search here */
++#define DT_REL		17		/* Address of Rel relocs */
++#define DT_RELSZ	18		/* Total size of Rel relocs */
++#define DT_RELENT	19		/* Size of one Rel reloc */
++#define DT_PLTREL	20		/* Type of reloc in PLT */
++#define DT_DEBUG	21		/* For debugging; unspecified */
++#define DT_TEXTREL	22		/* Reloc might modify .text */
++#define DT_JMPREL	23		/* Address of PLT relocs */
++#define	DT_BIND_NOW	24		/* Process relocations of object */
++#define	DT_INIT_ARRAY	25		/* Array with addresses of init fct */
++#define	DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
++#define	DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
++#define	DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
++#define DT_RUNPATH	29		/* Library search path */
++#define DT_FLAGS	30		/* Flags for the object being loaded */
++#define DT_ENCODING	32		/* Start of encoded range */
++#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
++#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
++#define	DT_NUM		34		/* Number used */
++#define DT_LOOS		0x6000000d	/* Start of OS-specific */
++#define DT_HIOS		0x6ffff000	/* End of OS-specific */
++#define DT_LOPROC	0x70000000	/* Start of processor-specific */
++#define DT_HIPROC	0x7fffffff	/* End of processor-specific */
++#define	DT_PROCNUM	DT_MIPS_NUM	/* Most used by any processor */
++
++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
++   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's
++   approach.  */
++#define DT_VALRNGLO	0x6ffffd00
++#define DT_GNU_PRELINKED 0x6ffffdf5	/* Prelinking timestamp */
++#define DT_GNU_CONFLICTSZ 0x6ffffdf6	/* Size of conflict section */
++#define DT_GNU_LIBLISTSZ 0x6ffffdf7	/* Size of library list */
++#define DT_CHECKSUM	0x6ffffdf8
++#define DT_PLTPADSZ	0x6ffffdf9
++#define DT_MOVEENT	0x6ffffdfa
++#define DT_MOVESZ	0x6ffffdfb
++#define DT_FEATURE_1	0x6ffffdfc	/* Feature selection (DTF_*).  */
++#define DT_POSFLAG_1	0x6ffffdfd	/* Flags for DT_* entries, effecting
++					   the following DT_* entry.  */
++#define DT_SYMINSZ	0x6ffffdfe	/* Size of syminfo table (in bytes) */
++#define DT_SYMINENT	0x6ffffdff	/* Entry size of syminfo */
++#define DT_VALRNGHI	0x6ffffdff
++#define DT_VALTAGIDX(tag)	(DT_VALRNGHI - (tag))	/* Reverse order! */
++#define DT_VALNUM 12
++
++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
++   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
++
++   If any adjustment is made to the ELF object after it has been
++   built these entries will need to be adjusted.  */
++#define DT_ADDRRNGLO	0x6ffffe00
++#define DT_GNU_HASH	0x6ffffef5	/* GNU-style hash table.  */
++#define DT_TLSDESC_PLT	0x6ffffef6
++#define DT_TLSDESC_GOT	0x6ffffef7
++#define DT_GNU_CONFLICT	0x6ffffef8	/* Start of conflict section */
++#define DT_GNU_LIBLIST	0x6ffffef9	/* Library list */
++#define DT_CONFIG	0x6ffffefa	/* Configuration information.  */
++#define DT_DEPAUDIT	0x6ffffefb	/* Dependency auditing.  */
++#define DT_AUDIT	0x6ffffefc	/* Object auditing.  */
++#define	DT_PLTPAD	0x6ffffefd	/* PLT padding.  */
++#define	DT_MOVETAB	0x6ffffefe	/* Move table.  */
++#define DT_SYMINFO	0x6ffffeff	/* Syminfo table.  */
++#define DT_ADDRRNGHI	0x6ffffeff
++#define DT_ADDRTAGIDX(tag)	(DT_ADDRRNGHI - (tag))	/* Reverse order! */
++#define DT_ADDRNUM 11
++
++/* The versioning entry types.  The next are defined as part of the
++   GNU extension.  */
++#define DT_VERSYM	0x6ffffff0
++
++#define DT_RELACOUNT	0x6ffffff9
++#define DT_RELCOUNT	0x6ffffffa
++
++/* These were chosen by Sun.  */
++#define DT_FLAGS_1	0x6ffffffb	/* State flags, see DF_1_* below.  */
++#define	DT_VERDEF	0x6ffffffc	/* Address of version definition
++					   table */
++#define	DT_VERDEFNUM	0x6ffffffd	/* Number of version definitions */
++#define	DT_VERNEED	0x6ffffffe	/* Address of table with needed
++					   versions */
++#define	DT_VERNEEDNUM	0x6fffffff	/* Number of needed versions */
++#define DT_VERSIONTAGIDX(tag)	(DT_VERNEEDNUM - (tag))	/* Reverse order! */
++#define DT_VERSIONTAGNUM 16
++
++/* Sun added these machine-independent extensions in the "processor-specific"
++   range.  Be compatible.  */
++#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */
++#define DT_FILTER       0x7fffffff      /* Shared object to get values from */
++#define DT_EXTRATAGIDX(tag)	((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)
++#define DT_EXTRANUM	3
++
++/* Values of `d_un.d_val' in the DT_FLAGS entry.  */
++#define DF_ORIGIN	0x00000001	/* Object may use DF_ORIGIN */
++#define DF_SYMBOLIC	0x00000002	/* Symbol resolutions starts here */
++#define DF_TEXTREL	0x00000004	/* Object contains text relocations */
++#define DF_BIND_NOW	0x00000008	/* No lazy binding for this object */
++#define DF_STATIC_TLS	0x00000010	/* Module uses the static TLS model */
++
++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1
++   entry in the dynamic section.  */
++#define DF_1_NOW	0x00000001	/* Set RTLD_NOW for this object.  */
++#define DF_1_GLOBAL	0x00000002	/* Set RTLD_GLOBAL for this object.  */
++#define DF_1_GROUP	0x00000004	/* Set RTLD_GROUP for this object.  */
++#define DF_1_NODELETE	0x00000008	/* Set RTLD_NODELETE for this object.*/
++#define DF_1_LOADFLTR	0x00000010	/* Trigger filtee loading at runtime.*/
++#define DF_1_INITFIRST	0x00000020	/* Set RTLD_INITFIRST for this object*/
++#define DF_1_NOOPEN	0x00000040	/* Set RTLD_NOOPEN for this object.  */
++#define DF_1_ORIGIN	0x00000080	/* $ORIGIN must be handled.  */
++#define DF_1_DIRECT	0x00000100	/* Direct binding enabled.  */
++#define DF_1_TRANS	0x00000200
++#define DF_1_INTERPOSE	0x00000400	/* Object is used to interpose.  */
++#define DF_1_NODEFLIB	0x00000800	/* Ignore default lib search path.  */
++#define DF_1_NODUMP	0x00001000	/* Object can't be dldump'ed.  */
++#define DF_1_CONFALT	0x00002000	/* Configuration alternative created.*/
++#define DF_1_ENDFILTEE	0x00004000	/* Filtee terminates filters search. */
++#define	DF_1_DISPRELDNE	0x00008000	/* Disp reloc applied at build time. */
++#define	DF_1_DISPRELPND	0x00010000	/* Disp reloc applied at run-time.  */
++
++/* Flags for the feature selection in DT_FEATURE_1.  */
++#define DTF_1_PARINIT	0x00000001
++#define DTF_1_CONFEXP	0x00000002
++
++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */
++#define DF_P1_LAZYLOAD	0x00000001	/* Lazyload following object.  */
++#define DF_P1_GROUPPERM	0x00000002	/* Symbols from next object are not
++					   generally available.  */
++
++/* Version definition sections.  */
++
++typedef struct
++{
++  Elf32_Half	vd_version;		/* Version revision */
++  Elf32_Half	vd_flags;		/* Version information */
++  Elf32_Half	vd_ndx;			/* Version Index */
++  Elf32_Half	vd_cnt;			/* Number of associated aux entries */
++  Elf32_Word	vd_hash;		/* Version name hash value */
++  Elf32_Word	vd_aux;			/* Offset in bytes to verdaux array */
++  Elf32_Word	vd_next;		/* Offset in bytes to next verdef
++					   entry */
++} Elf32_Verdef;
++
++typedef struct
++{
++  Elf64_Half	vd_version;		/* Version revision */
++  Elf64_Half	vd_flags;		/* Version information */
++  Elf64_Half	vd_ndx;			/* Version Index */
++  Elf64_Half	vd_cnt;			/* Number of associated aux entries */
++  Elf64_Word	vd_hash;		/* Version name hash value */
++  Elf64_Word	vd_aux;			/* Offset in bytes to verdaux array */
++  Elf64_Word	vd_next;		/* Offset in bytes to next verdef
++					   entry */
++} Elf64_Verdef;
++
++
++/* Legal values for vd_version (version revision).  */
++#define VER_DEF_NONE	0		/* No version */
++#define VER_DEF_CURRENT	1		/* Current version */
++#define VER_DEF_NUM	2		/* Given version number */
++
++/* Legal values for vd_flags (version information flags).  */
++#define VER_FLG_BASE	0x1		/* Version definition of file itself */
++#define VER_FLG_WEAK	0x2		/* Weak version identifier */
++
++/* Versym symbol index values.  */
++#define	VER_NDX_LOCAL		0	/* Symbol is local.  */
++#define	VER_NDX_GLOBAL		1	/* Symbol is global.  */
++#define	VER_NDX_LORESERVE	0xff00	/* Beginning of reserved entries.  */
++#define	VER_NDX_ELIMINATE	0xff01	/* Symbol is to be eliminated.  */
++
++/* Auxialiary version information.  */
++
++typedef struct
++{
++  Elf32_Word	vda_name;		/* Version or dependency names */
++  Elf32_Word	vda_next;		/* Offset in bytes to next verdaux
++					   entry */
++} Elf32_Verdaux;
++
++typedef struct
++{
++  Elf64_Word	vda_name;		/* Version or dependency names */
++  Elf64_Word	vda_next;		/* Offset in bytes to next verdaux
++					   entry */
++} Elf64_Verdaux;
++
++
++/* Version dependency section.  */
++
++typedef struct
++{
++  Elf32_Half	vn_version;		/* Version of structure */
++  Elf32_Half	vn_cnt;			/* Number of associated aux entries */
++  Elf32_Word	vn_file;		/* Offset of filename for this
++					   dependency */
++  Elf32_Word	vn_aux;			/* Offset in bytes to vernaux array */
++  Elf32_Word	vn_next;		/* Offset in bytes to next verneed
++					   entry */
++} Elf32_Verneed;
++
++typedef struct
++{
++  Elf64_Half	vn_version;		/* Version of structure */
++  Elf64_Half	vn_cnt;			/* Number of associated aux entries */
++  Elf64_Word	vn_file;		/* Offset of filename for this
++					   dependency */
++  Elf64_Word	vn_aux;			/* Offset in bytes to vernaux array */
++  Elf64_Word	vn_next;		/* Offset in bytes to next verneed
++					   entry */
++} Elf64_Verneed;
++
++
++/* Legal values for vn_version (version revision).  */
++#define VER_NEED_NONE	 0		/* No version */
++#define VER_NEED_CURRENT 1		/* Current version */
++#define VER_NEED_NUM	 2		/* Given version number */
++
++/* Auxiliary needed version information.  */
++
++typedef struct
++{
++  Elf32_Word	vna_hash;		/* Hash value of dependency name */
++  Elf32_Half	vna_flags;		/* Dependency specific information */
++  Elf32_Half	vna_other;		/* Unused */
++  Elf32_Word	vna_name;		/* Dependency name string offset */
++  Elf32_Word	vna_next;		/* Offset in bytes to next vernaux
++					   entry */
++} Elf32_Vernaux;
++
++typedef struct
++{
++  Elf64_Word	vna_hash;		/* Hash value of dependency name */
++  Elf64_Half	vna_flags;		/* Dependency specific information */
++  Elf64_Half	vna_other;		/* Unused */
++  Elf64_Word	vna_name;		/* Dependency name string offset */
++  Elf64_Word	vna_next;		/* Offset in bytes to next vernaux
++					   entry */
++} Elf64_Vernaux;
++
++
++/* Legal values for vna_flags.  */
++#define VER_FLG_WEAK	0x2		/* Weak version identifier */
++
++
++/* Auxiliary vector.  */
++
++/* This vector is normally only used by the program interpreter.  The
++   usual definition in an ABI supplement uses the name auxv_t.  The
++   vector is not usually defined in a standard <elf.h> file, but it
++   can't hurt.  We rename it to avoid conflicts.  The sizes of these
++   types are an arrangement between the exec server and the program
++   interpreter, so we don't fully specify them here.  */
++
++typedef struct
++{
++  uint32_t a_type;		/* Entry type */
++  union
++    {
++      uint32_t a_val;		/* Integer value */
++      /* We use to have pointer elements added here.  We cannot do that,
++	 though, since it does not work when using 32-bit definitions
++	 on 64-bit platforms and vice versa.  */
++    } a_un;
++} Elf32_auxv_t;
++
++typedef struct
++{
++  uint64_t a_type;		/* Entry type */
++  union
++    {
++      uint64_t a_val;		/* Integer value */
++      /* We use to have pointer elements added here.  We cannot do that,
++	 though, since it does not work when using 32-bit definitions
++	 on 64-bit platforms and vice versa.  */
++    } a_un;
++} Elf64_auxv_t;
++
++/* Legal values for a_type (entry type).  */
++
++#define AT_NULL		0		/* End of vector */
++#define AT_IGNORE	1		/* Entry should be ignored */
++#define AT_EXECFD	2		/* File descriptor of program */
++#define AT_PHDR		3		/* Program headers for program */
++#define AT_PHENT	4		/* Size of program header entry */
++#define AT_PHNUM	5		/* Number of program headers */
++#define AT_PAGESZ	6		/* System page size */
++#define AT_BASE		7		/* Base address of interpreter */
++#define AT_FLAGS	8		/* Flags */
++#define AT_ENTRY	9		/* Entry point of program */
++#define AT_NOTELF	10		/* Program is not ELF */
++#define AT_UID		11		/* Real uid */
++#define AT_EUID		12		/* Effective uid */
++#define AT_GID		13		/* Real gid */
++#define AT_EGID		14		/* Effective gid */
++#define AT_CLKTCK	17		/* Frequency of times() */
++
++/* Some more special a_type values describing the hardware.  */
++#define AT_PLATFORM	15		/* String identifying platform.  */
++#define AT_HWCAP	16		/* Machine dependent hints about
++					   processor capabilities.  */
++
++/* This entry gives some information about the FPU initialization
++   performed by the kernel.  */
++#define AT_FPUCW	18		/* Used FPU control word.  */
++
++/* Cache block sizes.  */
++#define AT_DCACHEBSIZE	19		/* Data cache block size.  */
++#define AT_ICACHEBSIZE	20		/* Instruction cache block size.  */
++#define AT_UCACHEBSIZE	21		/* Unified cache block size.  */
++
++/* A special ignored value for PPC, used by the kernel to control the
++   interpretation of the AUXV. Must be > 16.  */
++#define AT_IGNOREPPC	22		/* Entry should be ignored.  */
++
++#define	AT_SECURE	23		/* Boolean, was exec setuid-like?  */
++
++#define AT_BASE_PLATFORM 24		/* String identifying real platforms.*/
++
++#define AT_RANDOM	25		/* Address of 16 random bytes.  */
++
++#define AT_EXECFN	31		/* Filename of executable.  */
++
++/* Pointer to the global system page used for system calls and other
++   nice things.  */
++#define AT_SYSINFO	32
++#define AT_SYSINFO_EHDR	33
++
++/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains
++   log2 of line size; mask those to get cache size.  */
++#define AT_L1I_CACHESHAPE	34
++#define AT_L1D_CACHESHAPE	35
++#define AT_L2_CACHESHAPE	36
++#define AT_L3_CACHESHAPE	37
++
++/* Note section contents.  Each entry in the note section begins with
++   a header of a fixed form.  */
++
++typedef struct
++{
++  Elf32_Word n_namesz;			/* Length of the note's name.  */
++  Elf32_Word n_descsz;			/* Length of the note's descriptor.  */
++  Elf32_Word n_type;			/* Type of the note.  */
++} Elf32_Nhdr;
++
++typedef struct
++{
++  Elf64_Word n_namesz;			/* Length of the note's name.  */
++  Elf64_Word n_descsz;			/* Length of the note's descriptor.  */
++  Elf64_Word n_type;			/* Type of the note.  */
++} Elf64_Nhdr;
++
++/* Known names of notes.  */
++
++/* Solaris entries in the note section have this name.  */
++#define ELF_NOTE_SOLARIS	"SUNW Solaris"
++
++/* Note entries for GNU systems have this name.  */
++#define ELF_NOTE_GNU		"GNU"
++
++
++/* Defined types of notes for Solaris.  */
++
++/* Value of descriptor (one word) is desired pagesize for the binary.  */
++#define ELF_NOTE_PAGESIZE_HINT	1
++
++
++/* Defined note types for GNU systems.  */
++
++/* ABI information.  The descriptor consists of words:
++   word 0: OS descriptor
++   word 1: major version of the ABI
++   word 2: minor version of the ABI
++   word 3: subminor version of the ABI
++*/
++#define NT_GNU_ABI_TAG	1
++#define ELF_NOTE_ABI	NT_GNU_ABI_TAG /* Old name.  */
++
++/* Known OSes.  These values can appear in word 0 of an
++   NT_GNU_ABI_TAG note section entry.  */
++#define ELF_NOTE_OS_LINUX	0
++#define ELF_NOTE_OS_GNU		1
++#define ELF_NOTE_OS_SOLARIS2	2
++#define ELF_NOTE_OS_FREEBSD	3
++
++/* Synthetic hwcap information.  The descriptor begins with two words:
++   word 0: number of entries
++   word 1: bitmask of enabled entries
++   Then follow variable-length entries, one byte followed by a
++   '\0'-terminated hwcap name string.  The byte gives the bit
++   number to test if enabled, (1U << bit) & bitmask.  */
++#define NT_GNU_HWCAP	2
++
++/* Build ID bits as generated by ld --build-id.
++   The descriptor consists of any nonzero number of bytes.  */
++#define NT_GNU_BUILD_ID	3
++
++/* Version note generated by GNU gold containing a version string.  */
++#define NT_GNU_GOLD_VERSION	4
++
++
++/* Move records.  */
++typedef struct
++{
++  Elf32_Xword m_value;		/* Symbol value.  */
++  Elf32_Word m_info;		/* Size and index.  */
++  Elf32_Word m_poffset;		/* Symbol offset.  */
++  Elf32_Half m_repeat;		/* Repeat count.  */
++  Elf32_Half m_stride;		/* Stride info.  */
++} Elf32_Move;
++
++typedef struct
++{
++  Elf64_Xword m_value;		/* Symbol value.  */
++  Elf64_Xword m_info;		/* Size and index.  */
++  Elf64_Xword m_poffset;	/* Symbol offset.  */
++  Elf64_Half m_repeat;		/* Repeat count.  */
++  Elf64_Half m_stride;		/* Stride info.  */
++} Elf64_Move;
++
++/* Macro to construct move records.  */
++#define ELF32_M_SYM(info)	((info) >> 8)
++#define ELF32_M_SIZE(info)	((unsigned char) (info))
++#define ELF32_M_INFO(sym, size)	(((sym) << 8) + (unsigned char) (size))
++
++#define ELF64_M_SYM(info)	ELF32_M_SYM (info)
++#define ELF64_M_SIZE(info)	ELF32_M_SIZE (info)
++#define ELF64_M_INFO(sym, size)	ELF32_M_INFO (sym, size)
++
++
++/* Motorola 68k specific definitions.  */
++
++/* Values for Elf32_Ehdr.e_flags.  */
++#define EF_CPU32	0x00810000
++
++/* m68k relocs.  */
++
++#define R_68K_NONE	0		/* No reloc */
++#define R_68K_32	1		/* Direct 32 bit  */
++#define R_68K_16	2		/* Direct 16 bit  */
++#define R_68K_8		3		/* Direct 8 bit  */
++#define R_68K_PC32	4		/* PC relative 32 bit */
++#define R_68K_PC16	5		/* PC relative 16 bit */
++#define R_68K_PC8	6		/* PC relative 8 bit */
++#define R_68K_GOT32	7		/* 32 bit PC relative GOT entry */
++#define R_68K_GOT16	8		/* 16 bit PC relative GOT entry */
++#define R_68K_GOT8	9		/* 8 bit PC relative GOT entry */
++#define R_68K_GOT32O	10		/* 32 bit GOT offset */
++#define R_68K_GOT16O	11		/* 16 bit GOT offset */
++#define R_68K_GOT8O	12		/* 8 bit GOT offset */
++#define R_68K_PLT32	13		/* 32 bit PC relative PLT address */
++#define R_68K_PLT16	14		/* 16 bit PC relative PLT address */
++#define R_68K_PLT8	15		/* 8 bit PC relative PLT address */
++#define R_68K_PLT32O	16		/* 32 bit PLT offset */
++#define R_68K_PLT16O	17		/* 16 bit PLT offset */
++#define R_68K_PLT8O	18		/* 8 bit PLT offset */
++#define R_68K_COPY	19		/* Copy symbol at runtime */
++#define R_68K_GLOB_DAT	20		/* Create GOT entry */
++#define R_68K_JMP_SLOT	21		/* Create PLT entry */
++#define R_68K_RELATIVE	22		/* Adjust by program base */
++#define R_68K_TLS_GD32      25          /* 32 bit GOT offset for GD */
++#define R_68K_TLS_GD16      26          /* 16 bit GOT offset for GD */
++#define R_68K_TLS_GD8       27          /* 8 bit GOT offset for GD */
++#define R_68K_TLS_LDM32     28          /* 32 bit GOT offset for LDM */
++#define R_68K_TLS_LDM16     29          /* 16 bit GOT offset for LDM */
++#define R_68K_TLS_LDM8      30          /* 8 bit GOT offset for LDM */
++#define R_68K_TLS_LDO32     31          /* 32 bit module-relative offset */
++#define R_68K_TLS_LDO16     32          /* 16 bit module-relative offset */
++#define R_68K_TLS_LDO8      33          /* 8 bit module-relative offset */
++#define R_68K_TLS_IE32      34          /* 32 bit GOT offset for IE */
++#define R_68K_TLS_IE16      35          /* 16 bit GOT offset for IE */
++#define R_68K_TLS_IE8       36          /* 8 bit GOT offset for IE */
++#define R_68K_TLS_LE32      37          /* 32 bit offset relative to
++					   static TLS block */
++#define R_68K_TLS_LE16      38          /* 16 bit offset relative to
++					   static TLS block */
++#define R_68K_TLS_LE8       39          /* 8 bit offset relative to
++					   static TLS block */
++#define R_68K_TLS_DTPMOD32  40          /* 32 bit module number */
++#define R_68K_TLS_DTPREL32  41          /* 32 bit module-relative offset */
++#define R_68K_TLS_TPREL32   42          /* 32 bit TP-relative offset */
++/* Keep this the last entry.  */
++#define R_68K_NUM	43
++
++/* Intel 80386 specific definitions.  */
++
++/* i386 relocs.  */
++
++#define R_386_NONE	   0		/* No reloc */
++#define R_386_32	   1		/* Direct 32 bit  */
++#define R_386_PC32	   2		/* PC relative 32 bit */
++#define R_386_GOT32	   3		/* 32 bit GOT entry */
++#define R_386_PLT32	   4		/* 32 bit PLT address */
++#define R_386_COPY	   5		/* Copy symbol at runtime */
++#define R_386_GLOB_DAT	   6		/* Create GOT entry */
++#define R_386_JMP_SLOT	   7		/* Create PLT entry */
++#define R_386_RELATIVE	   8		/* Adjust by program base */
++#define R_386_GOTOFF	   9		/* 32 bit offset to GOT */
++#define R_386_GOTPC	   10		/* 32 bit PC relative offset to GOT */
++#define R_386_32PLT	   11
++#define R_386_TLS_TPOFF	   14		/* Offset in static TLS block */
++#define R_386_TLS_IE	   15		/* Address of GOT entry for static TLS
++					   block offset */
++#define R_386_TLS_GOTIE	   16		/* GOT entry for static TLS block
++					   offset */
++#define R_386_TLS_LE	   17		/* Offset relative to static TLS
++					   block */
++#define R_386_TLS_GD	   18		/* Direct 32 bit for GNU version of
++					   general dynamic thread local data */
++#define R_386_TLS_LDM	   19		/* Direct 32 bit for GNU version of
++					   local dynamic thread local data
++					   in LE code */
++#define R_386_16	   20
++#define R_386_PC16	   21
++#define R_386_8		   22
++#define R_386_PC8	   23
++#define R_386_TLS_GD_32	   24		/* Direct 32 bit for general dynamic
++					   thread local data */
++#define R_386_TLS_GD_PUSH  25		/* Tag for pushl in GD TLS code */
++#define R_386_TLS_GD_CALL  26		/* Relocation for call to
++					   __tls_get_addr() */
++#define R_386_TLS_GD_POP   27		/* Tag for popl in GD TLS code */
++#define R_386_TLS_LDM_32   28		/* Direct 32 bit for local dynamic
++					   thread local data in LE code */
++#define R_386_TLS_LDM_PUSH 29		/* Tag for pushl in LDM TLS code */
++#define R_386_TLS_LDM_CALL 30		/* Relocation for call to
++					   __tls_get_addr() in LDM code */
++#define R_386_TLS_LDM_POP  31		/* Tag for popl in LDM TLS code */
++#define R_386_TLS_LDO_32   32		/* Offset relative to TLS block */
++#define R_386_TLS_IE_32	   33		/* GOT entry for negated static TLS
++					   block offset */
++#define R_386_TLS_LE_32	   34		/* Negated offset relative to static
++					   TLS block */
++#define R_386_TLS_DTPMOD32 35		/* ID of module containing symbol */
++#define R_386_TLS_DTPOFF32 36		/* Offset in TLS block */
++#define R_386_TLS_TPOFF32  37		/* Negated offset in static TLS block */
++/* 38? */
++#define R_386_TLS_GOTDESC  39		/* GOT offset for TLS descriptor.  */
++#define R_386_TLS_DESC_CALL 40		/* Marker of call through TLS
++					   descriptor for
++					   relaxation.  */
++#define R_386_TLS_DESC     41		/* TLS descriptor containing
++					   pointer to code and to
++					   argument, returning the TLS
++					   offset for the symbol.  */
++#define R_386_IRELATIVE	   42		/* Adjust indirectly by program base */
++/* Keep this the last entry.  */
++#define R_386_NUM	   43
++
++/* SUN SPARC specific definitions.  */
++
++/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
++
++#define STT_SPARC_REGISTER	13	/* Global register reserved to app. */
++
++/* Values for Elf64_Ehdr.e_flags.  */
++
++#define EF_SPARCV9_MM		3
++#define EF_SPARCV9_TSO		0
++#define EF_SPARCV9_PSO		1
++#define EF_SPARCV9_RMO		2
++#define EF_SPARC_LEDATA		0x800000 /* little endian data */
++#define EF_SPARC_EXT_MASK	0xFFFF00
++#define EF_SPARC_32PLUS		0x000100 /* generic V8+ features */
++#define EF_SPARC_SUN_US1	0x000200 /* Sun UltraSPARC1 extensions */
++#define EF_SPARC_HAL_R1		0x000400 /* HAL R1 extensions */
++#define EF_SPARC_SUN_US3	0x000800 /* Sun UltraSPARCIII extensions */
++
++/* SPARC relocs.  */
++
++#define R_SPARC_NONE		0	/* No reloc */
++#define R_SPARC_8		1	/* Direct 8 bit */
++#define R_SPARC_16		2	/* Direct 16 bit */
++#define R_SPARC_32		3	/* Direct 32 bit */
++#define R_SPARC_DISP8		4	/* PC relative 8 bit */
++#define R_SPARC_DISP16		5	/* PC relative 16 bit */
++#define R_SPARC_DISP32		6	/* PC relative 32 bit */
++#define R_SPARC_WDISP30		7	/* PC relative 30 bit shifted */
++#define R_SPARC_WDISP22		8	/* PC relative 22 bit shifted */
++#define R_SPARC_HI22		9	/* High 22 bit */
++#define R_SPARC_22		10	/* Direct 22 bit */
++#define R_SPARC_13		11	/* Direct 13 bit */
++#define R_SPARC_LO10		12	/* Truncated 10 bit */
++#define R_SPARC_GOT10		13	/* Truncated 10 bit GOT entry */
++#define R_SPARC_GOT13		14	/* 13 bit GOT entry */
++#define R_SPARC_GOT22		15	/* 22 bit GOT entry shifted */
++#define R_SPARC_PC10		16	/* PC relative 10 bit truncated */
++#define R_SPARC_PC22		17	/* PC relative 22 bit shifted */
++#define R_SPARC_WPLT30		18	/* 30 bit PC relative PLT address */
++#define R_SPARC_COPY		19	/* Copy symbol at runtime */
++#define R_SPARC_GLOB_DAT	20	/* Create GOT entry */
++#define R_SPARC_JMP_SLOT	21	/* Create PLT entry */
++#define R_SPARC_RELATIVE	22	/* Adjust by program base */
++#define R_SPARC_UA32		23	/* Direct 32 bit unaligned */
++
++/* Additional Sparc64 relocs.  */
++
++#define R_SPARC_PLT32		24	/* Direct 32 bit ref to PLT entry */
++#define R_SPARC_HIPLT22		25	/* High 22 bit PLT entry */
++#define R_SPARC_LOPLT10		26	/* Truncated 10 bit PLT entry */
++#define R_SPARC_PCPLT32		27	/* PC rel 32 bit ref to PLT entry */
++#define R_SPARC_PCPLT22		28	/* PC rel high 22 bit PLT entry */
++#define R_SPARC_PCPLT10		29	/* PC rel trunc 10 bit PLT entry */
++#define R_SPARC_10		30	/* Direct 10 bit */
++#define R_SPARC_11		31	/* Direct 11 bit */
++#define R_SPARC_64		32	/* Direct 64 bit */
++#define R_SPARC_OLO10		33	/* 10bit with secondary 13bit addend */
++#define R_SPARC_HH22		34	/* Top 22 bits of direct 64 bit */
++#define R_SPARC_HM10		35	/* High middle 10 bits of ... */
++#define R_SPARC_LM22		36	/* Low middle 22 bits of ... */
++#define R_SPARC_PC_HH22		37	/* Top 22 bits of pc rel 64 bit */
++#define R_SPARC_PC_HM10		38	/* High middle 10 bit of ... */
++#define R_SPARC_PC_LM22		39	/* Low miggle 22 bits of ... */
++#define R_SPARC_WDISP16		40	/* PC relative 16 bit shifted */
++#define R_SPARC_WDISP19		41	/* PC relative 19 bit shifted */
++#define R_SPARC_GLOB_JMP	42	/* was part of v9 ABI but was removed */
++#define R_SPARC_7		43	/* Direct 7 bit */
++#define R_SPARC_5		44	/* Direct 5 bit */
++#define R_SPARC_6		45	/* Direct 6 bit */
++#define R_SPARC_DISP64		46	/* PC relative 64 bit */
++#define R_SPARC_PLT64		47	/* Direct 64 bit ref to PLT entry */
++#define R_SPARC_HIX22		48	/* High 22 bit complemented */
++#define R_SPARC_LOX10		49	/* Truncated 11 bit complemented */
++#define R_SPARC_H44		50	/* Direct high 12 of 44 bit */
++#define R_SPARC_M44		51	/* Direct mid 22 of 44 bit */
++#define R_SPARC_L44		52	/* Direct low 10 of 44 bit */
++#define R_SPARC_REGISTER	53	/* Global register usage */
++#define R_SPARC_UA64		54	/* Direct 64 bit unaligned */
++#define R_SPARC_UA16		55	/* Direct 16 bit unaligned */
++#define R_SPARC_TLS_GD_HI22	56
++#define R_SPARC_TLS_GD_LO10	57
++#define R_SPARC_TLS_GD_ADD	58
++#define R_SPARC_TLS_GD_CALL	59
++#define R_SPARC_TLS_LDM_HI22	60
++#define R_SPARC_TLS_LDM_LO10	61
++#define R_SPARC_TLS_LDM_ADD	62
++#define R_SPARC_TLS_LDM_CALL	63
++#define R_SPARC_TLS_LDO_HIX22	64
++#define R_SPARC_TLS_LDO_LOX10	65
++#define R_SPARC_TLS_LDO_ADD	66
++#define R_SPARC_TLS_IE_HI22	67
++#define R_SPARC_TLS_IE_LO10	68
++#define R_SPARC_TLS_IE_LD	69
++#define R_SPARC_TLS_IE_LDX	70
++#define R_SPARC_TLS_IE_ADD	71
++#define R_SPARC_TLS_LE_HIX22	72
++#define R_SPARC_TLS_LE_LOX10	73
++#define R_SPARC_TLS_DTPMOD32	74
++#define R_SPARC_TLS_DTPMOD64	75
++#define R_SPARC_TLS_DTPOFF32	76
++#define R_SPARC_TLS_DTPOFF64	77
++#define R_SPARC_TLS_TPOFF32	78
++#define R_SPARC_TLS_TPOFF64	79
++#define R_SPARC_GOTDATA_HIX22	80
++#define R_SPARC_GOTDATA_LOX10	81
++#define R_SPARC_GOTDATA_OP_HIX22	82
++#define R_SPARC_GOTDATA_OP_LOX10	83
++#define R_SPARC_GOTDATA_OP	84
++#define R_SPARC_H34		85
++#define R_SPARC_SIZE32		86
++#define R_SPARC_SIZE64		87
++#define R_SPARC_WDISP10		88
++#define R_SPARC_JMP_IREL	248
++#define R_SPARC_IRELATIVE	249
++#define R_SPARC_GNU_VTINHERIT	250
++#define R_SPARC_GNU_VTENTRY	251
++#define R_SPARC_REV32		252
++/* Keep this the last entry.  */
++#define R_SPARC_NUM		253
++
++/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */
++
++#define DT_SPARC_REGISTER 0x70000001
++#define DT_SPARC_NUM	2
++
++/* MIPS R3000 specific definitions.  */
++
++/* Legal values for e_flags field of Elf32_Ehdr.  */
++
++#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
++#define EF_MIPS_PIC	    2		/* Contains PIC code */
++#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
++#define EF_MIPS_XGOT	    8
++#define EF_MIPS_64BIT_WHIRL 16
++#define EF_MIPS_ABI2	    32
++#define EF_MIPS_ABI_ON32    64
++#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
++
++/* Legal values for MIPS architecture level.  */
++
++#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
++#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
++#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
++#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
++#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
++#define EF_MIPS_ARCH_32	    0x60000000	/* MIPS32 code.  */
++#define EF_MIPS_ARCH_64	    0x70000000	/* MIPS64 code.  */
++
++/* The following are non-official names and should not be used.  */
++
++#define E_MIPS_ARCH_1	  0x00000000	/* -mips1 code.  */
++#define E_MIPS_ARCH_2	  0x10000000	/* -mips2 code.  */
++#define E_MIPS_ARCH_3	  0x20000000	/* -mips3 code.  */
++#define E_MIPS_ARCH_4	  0x30000000	/* -mips4 code.  */
++#define E_MIPS_ARCH_5	  0x40000000	/* -mips5 code.  */
++#define E_MIPS_ARCH_32	  0x60000000	/* MIPS32 code.  */
++#define E_MIPS_ARCH_64	  0x70000000	/* MIPS64 code.  */
++
++/* Special section indices.  */
++
++#define SHN_MIPS_ACOMMON    0xff00	/* Allocated common symbols */
++#define SHN_MIPS_TEXT	    0xff01	/* Allocated test symbols.  */
++#define SHN_MIPS_DATA	    0xff02	/* Allocated data symbols.  */
++#define SHN_MIPS_SCOMMON    0xff03	/* Small common symbols */
++#define SHN_MIPS_SUNDEFINED 0xff04	/* Small undefined symbols */
++
++/* Legal values for sh_type field of Elf32_Shdr.  */
++
++#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */
++#define SHT_MIPS_MSYM	       0x70000001
++#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */
++#define SHT_MIPS_GPTAB	       0x70000003 /* Global data area sizes */
++#define SHT_MIPS_UCODE	       0x70000004 /* Reserved for SGI/MIPS compilers */
++#define SHT_MIPS_DEBUG	       0x70000005 /* MIPS ECOFF debugging information*/
++#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */
++#define SHT_MIPS_PACKAGE       0x70000007
++#define SHT_MIPS_PACKSYM       0x70000008
++#define SHT_MIPS_RELD	       0x70000009
++#define SHT_MIPS_IFACE         0x7000000b
++#define SHT_MIPS_CONTENT       0x7000000c
++#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */
++#define SHT_MIPS_SHDR	       0x70000010
++#define SHT_MIPS_FDESC	       0x70000011
++#define SHT_MIPS_EXTSYM	       0x70000012
++#define SHT_MIPS_DENSE	       0x70000013
++#define SHT_MIPS_PDESC	       0x70000014
++#define SHT_MIPS_LOCSYM	       0x70000015
++#define SHT_MIPS_AUXSYM	       0x70000016
++#define SHT_MIPS_OPTSYM	       0x70000017
++#define SHT_MIPS_LOCSTR	       0x70000018
++#define SHT_MIPS_LINE	       0x70000019
++#define SHT_MIPS_RFDESC	       0x7000001a
++#define SHT_MIPS_DELTASYM      0x7000001b
++#define SHT_MIPS_DELTAINST     0x7000001c
++#define SHT_MIPS_DELTACLASS    0x7000001d
++#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */
++#define SHT_MIPS_DELTADECL     0x7000001f
++#define SHT_MIPS_SYMBOL_LIB    0x70000020
++#define SHT_MIPS_EVENTS	       0x70000021 /* Event section.  */
++#define SHT_MIPS_TRANSLATE     0x70000022
++#define SHT_MIPS_PIXIE	       0x70000023
++#define SHT_MIPS_XLATE	       0x70000024
++#define SHT_MIPS_XLATE_DEBUG   0x70000025
++#define SHT_MIPS_WHIRL	       0x70000026
++#define SHT_MIPS_EH_REGION     0x70000027
++#define SHT_MIPS_XLATE_OLD     0x70000028
++#define SHT_MIPS_PDR_EXCEPTION 0x70000029
++
++/* Legal values for sh_flags field of Elf32_Shdr.  */
++
++#define SHF_MIPS_GPREL	 0x10000000	/* Must be part of global data area */
++#define SHF_MIPS_MERGE	 0x20000000
++#define SHF_MIPS_ADDR	 0x40000000
++#define SHF_MIPS_STRINGS 0x80000000
++#define SHF_MIPS_NOSTRIP 0x08000000
++#define SHF_MIPS_LOCAL	 0x04000000
++#define SHF_MIPS_NAMES	 0x02000000
++#define SHF_MIPS_NODUPE	 0x01000000
++
++
++/* Symbol tables.  */
++
++/* MIPS specific values for `st_other'.  */
++#define STO_MIPS_DEFAULT		0x0
++#define STO_MIPS_INTERNAL		0x1
++#define STO_MIPS_HIDDEN			0x2
++#define STO_MIPS_PROTECTED		0x3
++#define STO_MIPS_PLT			0x8
++#define STO_MIPS_SC_ALIGN_UNUSED	0xff
++
++/* MIPS specific values for `st_info'.  */
++#define STB_MIPS_SPLIT_COMMON		13
++
++/* Entries found in sections of type SHT_MIPS_GPTAB.  */
++
++typedef union
++{
++  struct
++    {
++      Elf32_Word gt_current_g_value;	/* -G value used for compilation */
++      Elf32_Word gt_unused;		/* Not used */
++    } gt_header;			/* First entry in section */
++  struct
++    {
++      Elf32_Word gt_g_value;		/* If this value were used for -G */
++      Elf32_Word gt_bytes;		/* This many bytes would be used */
++    } gt_entry;				/* Subsequent entries in section */
++} Elf32_gptab;
++
++/* Entry found in sections of type SHT_MIPS_REGINFO.  */
++
++typedef struct
++{
++  Elf32_Word	ri_gprmask;		/* General registers used */
++  Elf32_Word	ri_cprmask[4];		/* Coprocessor registers used */
++  Elf32_Sword	ri_gp_value;		/* $gp register value */
++} Elf32_RegInfo;
++
++/* Entries found in sections of type SHT_MIPS_OPTIONS.  */
++
++typedef struct
++{
++  unsigned char kind;		/* Determines interpretation of the
++				   variable part of descriptor.  */
++  unsigned char size;		/* Size of descriptor, including header.  */
++  Elf32_Section section;	/* Section header index of section affected,
++				   0 for global options.  */
++  Elf32_Word info;		/* Kind-specific information.  */
++} Elf_Options;
++
++/* Values for `kind' field in Elf_Options.  */
++
++#define ODK_NULL	0	/* Undefined.  */
++#define ODK_REGINFO	1	/* Register usage information.  */
++#define ODK_EXCEPTIONS	2	/* Exception processing options.  */
++#define ODK_PAD		3	/* Section padding options.  */
++#define ODK_HWPATCH	4	/* Hardware workarounds performed */
++#define ODK_FILL	5	/* record the fill value used by the linker. */
++#define ODK_TAGS	6	/* reserve space for desktop tools to write. */
++#define ODK_HWAND	7	/* HW workarounds.  'AND' bits when merging. */
++#define ODK_HWOR	8	/* HW workarounds.  'OR' bits when merging.  */
++
++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */
++
++#define OEX_FPU_MIN	0x1f	/* FPE's which MUST be enabled.  */
++#define OEX_FPU_MAX	0x1f00	/* FPE's which MAY be enabled.  */
++#define OEX_PAGE0	0x10000	/* page zero must be mapped.  */
++#define OEX_SMM		0x20000	/* Force sequential memory mode?  */
++#define OEX_FPDBUG	0x40000	/* Force floating point debug mode?  */
++#define OEX_PRECISEFP	OEX_FPDBUG
++#define OEX_DISMISS	0x80000	/* Dismiss invalid address faults?  */
++
++#define OEX_FPU_INVAL	0x10
++#define OEX_FPU_DIV0	0x08
++#define OEX_FPU_OFLO	0x04
++#define OEX_FPU_UFLO	0x02
++#define OEX_FPU_INEX	0x01
++
++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */
++
++#define OHW_R4KEOP	0x1	/* R4000 end-of-page patch.  */
++#define OHW_R8KPFETCH	0x2	/* may need R8000 prefetch patch.  */
++#define OHW_R5KEOP	0x4	/* R5000 end-of-page patch.  */
++#define OHW_R5KCVTL	0x8	/* R5000 cvt.[ds].l bug.  clean=1.  */
++
++#define OPAD_PREFIX	0x1
++#define OPAD_POSTFIX	0x2
++#define OPAD_SYMBOL	0x4
++
++/* Entry found in `.options' section.  */
++
++typedef struct
++{
++  Elf32_Word hwp_flags1;	/* Extra flags.  */
++  Elf32_Word hwp_flags2;	/* Extra flags.  */
++} Elf_Options_Hw;
++
++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */
++
++#define OHWA0_R4KEOP_CHECKED	0x00000001
++#define OHWA1_R4KEOP_CLEAN	0x00000002
++
++/* MIPS relocs.  */
++
++#define R_MIPS_NONE		0	/* No reloc */
++#define R_MIPS_16		1	/* Direct 16 bit */
++#define R_MIPS_32		2	/* Direct 32 bit */
++#define R_MIPS_REL32		3	/* PC relative 32 bit */
++#define R_MIPS_26		4	/* Direct 26 bit shifted */
++#define R_MIPS_HI16		5	/* High 16 bit */
++#define R_MIPS_LO16		6	/* Low 16 bit */
++#define R_MIPS_GPREL16		7	/* GP relative 16 bit */
++#define R_MIPS_LITERAL		8	/* 16 bit literal entry */
++#define R_MIPS_GOT16		9	/* 16 bit GOT entry */
++#define R_MIPS_PC16		10	/* PC relative 16 bit */
++#define R_MIPS_CALL16		11	/* 16 bit GOT entry for function */
++#define R_MIPS_GPREL32		12	/* GP relative 32 bit */
++
++#define R_MIPS_SHIFT5		16
++#define R_MIPS_SHIFT6		17
++#define R_MIPS_64		18
++#define R_MIPS_GOT_DISP		19
++#define R_MIPS_GOT_PAGE		20
++#define R_MIPS_GOT_OFST		21
++#define R_MIPS_GOT_HI16		22
++#define R_MIPS_GOT_LO16		23
++#define R_MIPS_SUB		24
++#define R_MIPS_INSERT_A		25
++#define R_MIPS_INSERT_B		26
++#define R_MIPS_DELETE		27
++#define R_MIPS_HIGHER		28
++#define R_MIPS_HIGHEST		29
++#define R_MIPS_CALL_HI16	30
++#define R_MIPS_CALL_LO16	31
++#define R_MIPS_SCN_DISP		32
++#define R_MIPS_REL16		33
++#define R_MIPS_ADD_IMMEDIATE	34
++#define R_MIPS_PJUMP		35
++#define R_MIPS_RELGOT		36
++#define R_MIPS_JALR		37
++#define R_MIPS_TLS_DTPMOD32	38	/* Module number 32 bit */
++#define R_MIPS_TLS_DTPREL32	39	/* Module-relative offset 32 bit */
++#define R_MIPS_TLS_DTPMOD64	40	/* Module number 64 bit */
++#define R_MIPS_TLS_DTPREL64	41	/* Module-relative offset 64 bit */
++#define R_MIPS_TLS_GD		42	/* 16 bit GOT offset for GD */
++#define R_MIPS_TLS_LDM		43	/* 16 bit GOT offset for LDM */
++#define R_MIPS_TLS_DTPREL_HI16	44	/* Module-relative offset, high 16 bits */
++#define R_MIPS_TLS_DTPREL_LO16	45	/* Module-relative offset, low 16 bits */
++#define R_MIPS_TLS_GOTTPREL	46	/* 16 bit GOT offset for IE */
++#define R_MIPS_TLS_TPREL32	47	/* TP-relative offset, 32 bit */
++#define R_MIPS_TLS_TPREL64	48	/* TP-relative offset, 64 bit */
++#define R_MIPS_TLS_TPREL_HI16	49	/* TP-relative offset, high 16 bits */
++#define R_MIPS_TLS_TPREL_LO16	50	/* TP-relative offset, low 16 bits */
++#define R_MIPS_GLOB_DAT		51
++#define R_MIPS_COPY		126
++#define R_MIPS_JUMP_SLOT        127
++/* Keep this the last entry.  */
++#define R_MIPS_NUM		128
++
++/* Legal values for p_type field of Elf32_Phdr.  */
++
++#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
++#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
++#define PT_MIPS_OPTIONS 0x70000002
++
++/* Special program header types.  */
++
++#define PF_MIPS_LOCAL	0x10000000
++
++/* Legal values for d_tag field of Elf32_Dyn.  */
++
++#define DT_MIPS_RLD_VERSION  0x70000001	/* Runtime linker interface version */
++#define DT_MIPS_TIME_STAMP   0x70000002	/* Timestamp */
++#define DT_MIPS_ICHECKSUM    0x70000003	/* Checksum */
++#define DT_MIPS_IVERSION     0x70000004	/* Version string (string tbl index) */
++#define DT_MIPS_FLAGS	     0x70000005	/* Flags */
++#define DT_MIPS_BASE_ADDRESS 0x70000006	/* Base address */
++#define DT_MIPS_MSYM	     0x70000007
++#define DT_MIPS_CONFLICT     0x70000008	/* Address of CONFLICT section */
++#define DT_MIPS_LIBLIST	     0x70000009	/* Address of LIBLIST section */
++#define DT_MIPS_LOCAL_GOTNO  0x7000000a	/* Number of local GOT entries */
++#define DT_MIPS_CONFLICTNO   0x7000000b	/* Number of CONFLICT entries */
++#define DT_MIPS_LIBLISTNO    0x70000010	/* Number of LIBLIST entries */
++#define DT_MIPS_SYMTABNO     0x70000011	/* Number of DYNSYM entries */
++#define DT_MIPS_UNREFEXTNO   0x70000012	/* First external DYNSYM */
++#define DT_MIPS_GOTSYM	     0x70000013	/* First GOT entry in DYNSYM */
++#define DT_MIPS_HIPAGENO     0x70000014	/* Number of GOT page table entries */
++#define DT_MIPS_RLD_MAP	     0x70000016	/* Address of run time loader map.  */
++#define DT_MIPS_DELTA_CLASS  0x70000017	/* Delta C++ class definition.  */
++#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in
++						DT_MIPS_DELTA_CLASS.  */
++#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */
++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in
++						DT_MIPS_DELTA_INSTANCE.  */
++#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */
++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in
++					     DT_MIPS_DELTA_RELOC.  */
++#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta
++					   relocations refer to.  */
++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in
++					   DT_MIPS_DELTA_SYM.  */
++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the
++					     class declaration.  */
++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in
++						DT_MIPS_DELTA_CLASSSYM.  */
++#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */
++#define DT_MIPS_PIXIE_INIT   0x70000023
++#define DT_MIPS_SYMBOL_LIB   0x70000024
++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025
++#define DT_MIPS_LOCAL_GOTIDX 0x70000026
++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027
++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028
++#define DT_MIPS_OPTIONS	     0x70000029 /* Address of .options.  */
++#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */
++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve
++						    function stored in GOT.  */
++#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added
++					   by rld on dlopen() calls.  */
++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
++#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */
++#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */
++/* The address of .got.plt in an executable using the new non-PIC ABI.  */
++#define DT_MIPS_PLTGOT	     0x70000032
++/* The base of the PLT in an executable using the new non-PIC ABI if that
++   PLT is writable.  For a non-writable PLT, this is omitted or has a zero
++   value.  */
++#define DT_MIPS_RWPLT        0x70000034
++#define DT_MIPS_NUM	     0x35
++
++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */
++
++#define RHF_NONE		   0		/* No flags */
++#define RHF_QUICKSTART		   (1 << 0)	/* Use quickstart */
++#define RHF_NOTPOT		   (1 << 1)	/* Hash size not power of 2 */
++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)	/* Ignore LD_LIBRARY_PATH */
++#define RHF_NO_MOVE		   (1 << 3)
++#define RHF_SGI_ONLY		   (1 << 4)
++#define RHF_GUARANTEE_INIT	   (1 << 5)
++#define RHF_DELTA_C_PLUS_PLUS	   (1 << 6)
++#define RHF_GUARANTEE_START_INIT   (1 << 7)
++#define RHF_PIXIE		   (1 << 8)
++#define RHF_DEFAULT_DELAY_LOAD	   (1 << 9)
++#define RHF_REQUICKSTART	   (1 << 10)
++#define RHF_REQUICKSTARTED	   (1 << 11)
++#define RHF_CORD		   (1 << 12)
++#define RHF_NO_UNRES_UNDEF	   (1 << 13)
++#define RHF_RLD_ORDER_SAFE	   (1 << 14)
++
++/* Entries found in sections of type SHT_MIPS_LIBLIST.  */
++
++typedef struct
++{
++  Elf32_Word l_name;		/* Name (string table index) */
++  Elf32_Word l_time_stamp;	/* Timestamp */
++  Elf32_Word l_checksum;	/* Checksum */
++  Elf32_Word l_version;		/* Interface version */
++  Elf32_Word l_flags;		/* Flags */
++} Elf32_Lib;
++
++typedef struct
++{
++  Elf64_Word l_name;		/* Name (string table index) */
++  Elf64_Word l_time_stamp;	/* Timestamp */
++  Elf64_Word l_checksum;	/* Checksum */
++  Elf64_Word l_version;		/* Interface version */
++  Elf64_Word l_flags;		/* Flags */
++} Elf64_Lib;
++
++
++/* Legal values for l_flags.  */
++
++#define LL_NONE		  0
++#define LL_EXACT_MATCH	  (1 << 0)	/* Require exact match */
++#define LL_IGNORE_INT_VER (1 << 1)	/* Ignore interface version */
++#define LL_REQUIRE_MINOR  (1 << 2)
++#define LL_EXPORTS	  (1 << 3)
++#define LL_DELAY_LOAD	  (1 << 4)
++#define LL_DELTA	  (1 << 5)
++
++/* Entries found in sections of type SHT_MIPS_CONFLICT.  */
++
++typedef Elf32_Addr Elf32_Conflict;
++
++
++/* HPPA specific definitions.  */
++
++/* Legal values for e_flags field of Elf32_Ehdr.  */
++
++#define EF_PARISC_TRAPNIL	0x00010000 /* Trap nil pointer dereference.  */
++#define EF_PARISC_EXT		0x00020000 /* Program uses arch. extensions. */
++#define EF_PARISC_LSB		0x00040000 /* Program expects little endian. */
++#define EF_PARISC_WIDE		0x00080000 /* Program expects wide mode.  */
++#define EF_PARISC_NO_KABP	0x00100000 /* No kernel assisted branch
++					      prediction.  */
++#define EF_PARISC_LAZYSWAP	0x00400000 /* Allow lazy swapping.  */
++#define EF_PARISC_ARCH		0x0000ffff /* Architecture version.  */
++
++/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */
++
++#define EFA_PARISC_1_0		    0x020b /* PA-RISC 1.0 big-endian.  */
++#define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
++#define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
++
++/* Additional section indeces.  */
++
++#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
++					      symbols in ANSI C.  */
++#define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
++
++/* Legal values for sh_type field of Elf32_Shdr.  */
++
++#define SHT_PARISC_EXT		0x70000000 /* Contains product specific ext. */
++#define SHT_PARISC_UNWIND	0x70000001 /* Unwind information.  */
++#define SHT_PARISC_DOC		0x70000002 /* Debug info for optimized code. */
++
++/* Legal values for sh_flags field of Elf32_Shdr.  */
++
++#define SHF_PARISC_SHORT	0x20000000 /* Section with short addressing. */
++#define SHF_PARISC_HUGE		0x40000000 /* Section far from gp.  */
++#define SHF_PARISC_SBP		0x80000000 /* Static branch prediction code. */
++
++/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
++
++#define STT_PARISC_MILLICODE	13	/* Millicode function entry point.  */
++
++#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
++#define STT_HP_STUB		(STT_LOOS + 0x2)
++
++/* HPPA relocs.  */
++
++#define R_PARISC_NONE		0	/* No reloc.  */
++#define R_PARISC_DIR32		1	/* Direct 32-bit reference.  */
++#define R_PARISC_DIR21L		2	/* Left 21 bits of eff. address.  */
++#define R_PARISC_DIR17R		3	/* Right 17 bits of eff. address.  */
++#define R_PARISC_DIR17F		4	/* 17 bits of eff. address.  */
++#define R_PARISC_DIR14R		6	/* Right 14 bits of eff. address.  */
++#define R_PARISC_PCREL32	9	/* 32-bit rel. address.  */
++#define R_PARISC_PCREL21L	10	/* Left 21 bits of rel. address.  */
++#define R_PARISC_PCREL17R	11	/* Right 17 bits of rel. address.  */
++#define R_PARISC_PCREL17F	12	/* 17 bits of rel. address.  */
++#define R_PARISC_PCREL14R	14	/* Right 14 bits of rel. address.  */
++#define R_PARISC_DPREL21L	18	/* Left 21 bits of rel. address.  */
++#define R_PARISC_DPREL14R	22	/* Right 14 bits of rel. address.  */
++#define R_PARISC_GPREL21L	26	/* GP-relative, left 21 bits.  */
++#define R_PARISC_GPREL14R	30	/* GP-relative, right 14 bits.  */
++#define R_PARISC_LTOFF21L	34	/* LT-relative, left 21 bits.  */
++#define R_PARISC_LTOFF14R	38	/* LT-relative, right 14 bits.  */
++#define R_PARISC_SECREL32	41	/* 32 bits section rel. address.  */
++#define R_PARISC_SEGBASE	48	/* No relocation, set segment base.  */
++#define R_PARISC_SEGREL32	49	/* 32 bits segment rel. address.  */
++#define R_PARISC_PLTOFF21L	50	/* PLT rel. address, left 21 bits.  */
++#define R_PARISC_PLTOFF14R	54	/* PLT rel. address, right 14 bits.  */
++#define R_PARISC_LTOFF_FPTR32	57	/* 32 bits LT-rel. function pointer. */
++#define R_PARISC_LTOFF_FPTR21L	58	/* LT-rel. fct ptr, left 21 bits. */
++#define R_PARISC_LTOFF_FPTR14R	62	/* LT-rel. fct ptr, right 14 bits. */
++#define R_PARISC_FPTR64		64	/* 64 bits function address.  */
++#define R_PARISC_PLABEL32	65	/* 32 bits function address.  */
++#define R_PARISC_PLABEL21L	66	/* Left 21 bits of fdesc address.  */
++#define R_PARISC_PLABEL14R	70	/* Right 14 bits of fdesc address.  */
++#define R_PARISC_PCREL64	72	/* 64 bits PC-rel. address.  */
++#define R_PARISC_PCREL22F	74	/* 22 bits PC-rel. address.  */
++#define R_PARISC_PCREL14WR	75	/* PC-rel. address, right 14 bits.  */
++#define R_PARISC_PCREL14DR	76	/* PC rel. address, right 14 bits.  */
++#define R_PARISC_PCREL16F	77	/* 16 bits PC-rel. address.  */
++#define R_PARISC_PCREL16WF	78	/* 16 bits PC-rel. address.  */
++#define R_PARISC_PCREL16DF	79	/* 16 bits PC-rel. address.  */
++#define R_PARISC_DIR64		80	/* 64 bits of eff. address.  */
++#define R_PARISC_DIR14WR	83	/* 14 bits of eff. address.  */
++#define R_PARISC_DIR14DR	84	/* 14 bits of eff. address.  */
++#define R_PARISC_DIR16F		85	/* 16 bits of eff. address.  */
++#define R_PARISC_DIR16WF	86	/* 16 bits of eff. address.  */
++#define R_PARISC_DIR16DF	87	/* 16 bits of eff. address.  */
++#define R_PARISC_GPREL64	88	/* 64 bits of GP-rel. address.  */
++#define R_PARISC_GPREL14WR	91	/* GP-rel. address, right 14 bits.  */
++#define R_PARISC_GPREL14DR	92	/* GP-rel. address, right 14 bits.  */
++#define R_PARISC_GPREL16F	93	/* 16 bits GP-rel. address.  */
++#define R_PARISC_GPREL16WF	94	/* 16 bits GP-rel. address.  */
++#define R_PARISC_GPREL16DF	95	/* 16 bits GP-rel. address.  */
++#define R_PARISC_LTOFF64	96	/* 64 bits LT-rel. address.  */
++#define R_PARISC_LTOFF14WR	99	/* LT-rel. address, right 14 bits.  */
++#define R_PARISC_LTOFF14DR	100	/* LT-rel. address, right 14 bits.  */
++#define R_PARISC_LTOFF16F	101	/* 16 bits LT-rel. address.  */
++#define R_PARISC_LTOFF16WF	102	/* 16 bits LT-rel. address.  */
++#define R_PARISC_LTOFF16DF	103	/* 16 bits LT-rel. address.  */
++#define R_PARISC_SECREL64	104	/* 64 bits section rel. address.  */
++#define R_PARISC_SEGREL64	112	/* 64 bits segment rel. address.  */
++#define R_PARISC_PLTOFF14WR	115	/* PLT-rel. address, right 14 bits.  */
++#define R_PARISC_PLTOFF14DR	116	/* PLT-rel. address, right 14 bits.  */
++#define R_PARISC_PLTOFF16F	117	/* 16 bits LT-rel. address.  */
++#define R_PARISC_PLTOFF16WF	118	/* 16 bits PLT-rel. address.  */
++#define R_PARISC_PLTOFF16DF	119	/* 16 bits PLT-rel. address.  */
++#define R_PARISC_LTOFF_FPTR64	120	/* 64 bits LT-rel. function ptr.  */
++#define R_PARISC_LTOFF_FPTR14WR	123	/* LT-rel. fct. ptr., right 14 bits. */
++#define R_PARISC_LTOFF_FPTR14DR	124	/* LT-rel. fct. ptr., right 14 bits. */
++#define R_PARISC_LTOFF_FPTR16F	125	/* 16 bits LT-rel. function ptr.  */
++#define R_PARISC_LTOFF_FPTR16WF	126	/* 16 bits LT-rel. function ptr.  */
++#define R_PARISC_LTOFF_FPTR16DF	127	/* 16 bits LT-rel. function ptr.  */
++#define R_PARISC_LORESERVE	128
++#define R_PARISC_COPY		128	/* Copy relocation.  */
++#define R_PARISC_IPLT		129	/* Dynamic reloc, imported PLT */
++#define R_PARISC_EPLT		130	/* Dynamic reloc, exported PLT */
++#define R_PARISC_TPREL32	153	/* 32 bits TP-rel. address.  */
++#define R_PARISC_TPREL21L	154	/* TP-rel. address, left 21 bits.  */
++#define R_PARISC_TPREL14R	158	/* TP-rel. address, right 14 bits.  */
++#define R_PARISC_LTOFF_TP21L	162	/* LT-TP-rel. address, left 21 bits. */
++#define R_PARISC_LTOFF_TP14R	166	/* LT-TP-rel. address, right 14 bits.*/
++#define R_PARISC_LTOFF_TP14F	167	/* 14 bits LT-TP-rel. address.  */
++#define R_PARISC_TPREL64	216	/* 64 bits TP-rel. address.  */
++#define R_PARISC_TPREL14WR	219	/* TP-rel. address, right 14 bits.  */
++#define R_PARISC_TPREL14DR	220	/* TP-rel. address, right 14 bits.  */
++#define R_PARISC_TPREL16F	221	/* 16 bits TP-rel. address.  */
++#define R_PARISC_TPREL16WF	222	/* 16 bits TP-rel. address.  */
++#define R_PARISC_TPREL16DF	223	/* 16 bits TP-rel. address.  */
++#define R_PARISC_LTOFF_TP64	224	/* 64 bits LT-TP-rel. address.  */
++#define R_PARISC_LTOFF_TP14WR	227	/* LT-TP-rel. address, right 14 bits.*/
++#define R_PARISC_LTOFF_TP14DR	228	/* LT-TP-rel. address, right 14 bits.*/
++#define R_PARISC_LTOFF_TP16F	229	/* 16 bits LT-TP-rel. address.  */
++#define R_PARISC_LTOFF_TP16WF	230	/* 16 bits LT-TP-rel. address.  */
++#define R_PARISC_LTOFF_TP16DF	231	/* 16 bits LT-TP-rel. address.  */
++#define R_PARISC_GNU_VTENTRY	232
++#define R_PARISC_GNU_VTINHERIT	233
++#define R_PARISC_TLS_GD21L	234	/* GD 21-bit left.  */
++#define R_PARISC_TLS_GD14R	235	/* GD 14-bit right.  */
++#define R_PARISC_TLS_GDCALL	236	/* GD call to __t_g_a.  */
++#define R_PARISC_TLS_LDM21L	237	/* LD module 21-bit left.  */
++#define R_PARISC_TLS_LDM14R	238	/* LD module 14-bit right.  */
++#define R_PARISC_TLS_LDMCALL	239	/* LD module call to __t_g_a.  */
++#define R_PARISC_TLS_LDO21L	240	/* LD offset 21-bit left.  */
++#define R_PARISC_TLS_LDO14R	241	/* LD offset 14-bit right.  */
++#define R_PARISC_TLS_DTPMOD32	242	/* DTP module 32-bit.  */
++#define R_PARISC_TLS_DTPMOD64	243	/* DTP module 64-bit.  */
++#define R_PARISC_TLS_DTPOFF32	244	/* DTP offset 32-bit.  */
++#define R_PARISC_TLS_DTPOFF64	245	/* DTP offset 32-bit.  */
++#define R_PARISC_TLS_LE21L	R_PARISC_TPREL21L
++#define R_PARISC_TLS_LE14R	R_PARISC_TPREL14R
++#define R_PARISC_TLS_IE21L	R_PARISC_LTOFF_TP21L
++#define R_PARISC_TLS_IE14R	R_PARISC_LTOFF_TP14R
++#define R_PARISC_TLS_TPREL32	R_PARISC_TPREL32
++#define R_PARISC_TLS_TPREL64	R_PARISC_TPREL64
++#define R_PARISC_HIRESERVE	255
++
++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */
++
++#define PT_HP_TLS		(PT_LOOS + 0x0)
++#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
++#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
++#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
++#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
++#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
++#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
++#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
++#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
++#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
++#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
++#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
++#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
++#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
++#define PT_HP_STACK		(PT_LOOS + 0x14)
++
++#define PT_PARISC_ARCHEXT	0x70000000
++#define PT_PARISC_UNWIND	0x70000001
++
++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */
++
++#define PF_PARISC_SBP		0x08000000
++
++#define PF_HP_PAGE_SIZE		0x00100000
++#define PF_HP_FAR_SHARED	0x00200000
++#define PF_HP_NEAR_SHARED	0x00400000
++#define PF_HP_CODE		0x01000000
++#define PF_HP_MODIFY		0x02000000
++#define PF_HP_LAZYSWAP		0x04000000
++#define PF_HP_SBP		0x08000000
++
++
++/* Alpha specific definitions.  */
++
++/* Legal values for e_flags field of Elf64_Ehdr.  */
++
++#define EF_ALPHA_32BIT		1	/* All addresses must be < 2GB.  */
++#define EF_ALPHA_CANRELAX	2	/* Relocations for relaxing exist.  */
++
++/* Legal values for sh_type field of Elf64_Shdr.  */
++
++/* These two are primerily concerned with ECOFF debugging info.  */
++#define SHT_ALPHA_DEBUG		0x70000001
++#define SHT_ALPHA_REGINFO	0x70000002
++
++/* Legal values for sh_flags field of Elf64_Shdr.  */
++
++#define SHF_ALPHA_GPREL		0x10000000
++
++/* Legal values for st_other field of Elf64_Sym.  */
++#define STO_ALPHA_NOPV		0x80	/* No PV required.  */
++#define STO_ALPHA_STD_GPLOAD	0x88	/* PV only used for initial ldgp.  */
++
++/* Alpha relocs.  */
++
++#define R_ALPHA_NONE		0	/* No reloc */
++#define R_ALPHA_REFLONG		1	/* Direct 32 bit */
++#define R_ALPHA_REFQUAD		2	/* Direct 64 bit */
++#define R_ALPHA_GPREL32		3	/* GP relative 32 bit */
++#define R_ALPHA_LITERAL		4	/* GP relative 16 bit w/optimization */
++#define R_ALPHA_LITUSE		5	/* Optimization hint for LITERAL */
++#define R_ALPHA_GPDISP		6	/* Add displacement to GP */
++#define R_ALPHA_BRADDR		7	/* PC+4 relative 23 bit shifted */
++#define R_ALPHA_HINT		8	/* PC+4 relative 16 bit shifted */
++#define R_ALPHA_SREL16		9	/* PC relative 16 bit */
++#define R_ALPHA_SREL32		10	/* PC relative 32 bit */
++#define R_ALPHA_SREL64		11	/* PC relative 64 bit */
++#define R_ALPHA_GPRELHIGH	17	/* GP relative 32 bit, high 16 bits */
++#define R_ALPHA_GPRELLOW	18	/* GP relative 32 bit, low 16 bits */
++#define R_ALPHA_GPREL16		19	/* GP relative 16 bit */
++#define R_ALPHA_COPY		24	/* Copy symbol at runtime */
++#define R_ALPHA_GLOB_DAT	25	/* Create GOT entry */
++#define R_ALPHA_JMP_SLOT	26	/* Create PLT entry */
++#define R_ALPHA_RELATIVE	27	/* Adjust by program base */
++#define R_ALPHA_TLS_GD_HI	28
++#define R_ALPHA_TLSGD		29
++#define R_ALPHA_TLS_LDM		30
++#define R_ALPHA_DTPMOD64	31
++#define R_ALPHA_GOTDTPREL	32
++#define R_ALPHA_DTPREL64	33
++#define R_ALPHA_DTPRELHI	34
++#define R_ALPHA_DTPRELLO	35
++#define R_ALPHA_DTPREL16	36
++#define R_ALPHA_GOTTPREL	37
++#define R_ALPHA_TPREL64		38
++#define R_ALPHA_TPRELHI		39
++#define R_ALPHA_TPRELLO		40
++#define R_ALPHA_TPREL16		41
++/* Keep this the last entry.  */
++#define R_ALPHA_NUM		46
++
++/* Magic values of the LITUSE relocation addend.  */
++#define LITUSE_ALPHA_ADDR	0
++#define LITUSE_ALPHA_BASE	1
++#define LITUSE_ALPHA_BYTOFF	2
++#define LITUSE_ALPHA_JSR	3
++#define LITUSE_ALPHA_TLS_GD	4
++#define LITUSE_ALPHA_TLS_LDM	5
++
++/* Legal values for d_tag of Elf64_Dyn.  */
++#define DT_ALPHA_PLTRO		(DT_LOPROC + 0)
++#define DT_ALPHA_NUM		1
++
++/* PowerPC specific declarations */
++
++/* Values for Elf32/64_Ehdr.e_flags.  */
++#define EF_PPC_EMB		0x80000000	/* PowerPC embedded flag */
++
++/* Cygnus local bits below */
++#define EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag*/
++#define EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib
++						   flag */
++
++/* PowerPC relocations defined by the ABIs */
++#define R_PPC_NONE		0
++#define R_PPC_ADDR32		1	/* 32bit absolute address */
++#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
++#define R_PPC_ADDR16		3	/* 16bit absolute address */
++#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
++#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
++#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
++#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
++#define R_PPC_ADDR14_BRTAKEN	8
++#define R_PPC_ADDR14_BRNTAKEN	9
++#define R_PPC_REL24		10	/* PC relative 26 bit */
++#define R_PPC_REL14		11	/* PC relative 16 bit */
++#define R_PPC_REL14_BRTAKEN	12
++#define R_PPC_REL14_BRNTAKEN	13
++#define R_PPC_GOT16		14
++#define R_PPC_GOT16_LO		15
++#define R_PPC_GOT16_HI		16
++#define R_PPC_GOT16_HA		17
++#define R_PPC_PLTREL24		18
++#define R_PPC_COPY		19
++#define R_PPC_GLOB_DAT		20
++#define R_PPC_JMP_SLOT		21
++#define R_PPC_RELATIVE		22
++#define R_PPC_LOCAL24PC		23
++#define R_PPC_UADDR32		24
++#define R_PPC_UADDR16		25
++#define R_PPC_REL32		26
++#define R_PPC_PLT32		27
++#define R_PPC_PLTREL32		28
++#define R_PPC_PLT16_LO		29
++#define R_PPC_PLT16_HI		30
++#define R_PPC_PLT16_HA		31
++#define R_PPC_SDAREL16		32
++#define R_PPC_SECTOFF		33
++#define R_PPC_SECTOFF_LO	34
++#define R_PPC_SECTOFF_HI	35
++#define R_PPC_SECTOFF_HA	36
++
++/* PowerPC relocations defined for the TLS access ABI.  */
++#define R_PPC_TLS		67 /* none	(sym+add)@tls */
++#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
++#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
++#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
++#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
++#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
++#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
++#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
++#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
++#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
++#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
++#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
++#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
++#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
++#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
++#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
++#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
++#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
++#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
++#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
++#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got@tprel */
++#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got@tprel@l */
++#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
++#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
++#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got@dtprel */
++#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got@dtprel@l */
++#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got@dtprel@h */
++#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got@dtprel@ha */
++
++/* The remaining relocs are from the Embedded ELF ABI, and are not
++   in the SVR4 ELF ABI.  */
++#define R_PPC_EMB_NADDR32	101
++#define R_PPC_EMB_NADDR16	102
++#define R_PPC_EMB_NADDR16_LO	103
++#define R_PPC_EMB_NADDR16_HI	104
++#define R_PPC_EMB_NADDR16_HA	105
++#define R_PPC_EMB_SDAI16	106
++#define R_PPC_EMB_SDA2I16	107
++#define R_PPC_EMB_SDA2REL	108
++#define R_PPC_EMB_SDA21		109	/* 16 bit offset in SDA */
++#define R_PPC_EMB_MRKREF	110
++#define R_PPC_EMB_RELSEC16	111
++#define R_PPC_EMB_RELST_LO	112
++#define R_PPC_EMB_RELST_HI	113
++#define R_PPC_EMB_RELST_HA	114
++#define R_PPC_EMB_BIT_FLD	115
++#define R_PPC_EMB_RELSDA	116	/* 16 bit relative offset in SDA */
++
++/* Diab tool relocations.  */
++#define R_PPC_DIAB_SDA21_LO	180	/* like EMB_SDA21, but lower 16 bit */
++#define R_PPC_DIAB_SDA21_HI	181	/* like EMB_SDA21, but high 16 bit */
++#define R_PPC_DIAB_SDA21_HA	182	/* like EMB_SDA21, adjusted high 16 */
++#define R_PPC_DIAB_RELSDA_LO	183	/* like EMB_RELSDA, but lower 16 bit */
++#define R_PPC_DIAB_RELSDA_HI	184	/* like EMB_RELSDA, but high 16 bit */
++#define R_PPC_DIAB_RELSDA_HA	185	/* like EMB_RELSDA, adjusted high 16 */
++
++/* GNU extension to support local ifunc.  */
++#define R_PPC_IRELATIVE		248
++
++/* GNU relocs used in PIC code sequences.  */
++#define R_PPC_REL16		249	/* half16   (sym+add-.) */
++#define R_PPC_REL16_LO		250	/* half16   (sym+add-.)@l */
++#define R_PPC_REL16_HI		251	/* half16   (sym+add-.)@h */
++#define R_PPC_REL16_HA		252	/* half16   (sym+add-.)@ha */
++
++/* This is a phony reloc to handle any old fashioned TOC16 references
++   that may still be in object files.  */
++#define R_PPC_TOC16		255
++
++/* PowerPC specific values for the Dyn d_tag field.  */
++#define DT_PPC_GOT		(DT_LOPROC + 0)
++#define DT_PPC_NUM		1
++
++/* PowerPC64 relocations defined by the ABIs */
++#define R_PPC64_NONE		R_PPC_NONE
++#define R_PPC64_ADDR32		R_PPC_ADDR32 /* 32bit absolute address */
++#define R_PPC64_ADDR24		R_PPC_ADDR24 /* 26bit address, word aligned */
++#define R_PPC64_ADDR16		R_PPC_ADDR16 /* 16bit absolute address */
++#define R_PPC64_ADDR16_LO	R_PPC_ADDR16_LO	/* lower 16bits of address */
++#define R_PPC64_ADDR16_HI	R_PPC_ADDR16_HI	/* high 16bits of address. */
++#define R_PPC64_ADDR16_HA	R_PPC_ADDR16_HA /* adjusted high 16bits.  */
++#define R_PPC64_ADDR14		R_PPC_ADDR14 /* 16bit address, word aligned */
++#define R_PPC64_ADDR14_BRTAKEN	R_PPC_ADDR14_BRTAKEN
++#define R_PPC64_ADDR14_BRNTAKEN	R_PPC_ADDR14_BRNTAKEN
++#define R_PPC64_REL24		R_PPC_REL24 /* PC-rel. 26 bit, word aligned */
++#define R_PPC64_REL14		R_PPC_REL14 /* PC relative 16 bit */
++#define R_PPC64_REL14_BRTAKEN	R_PPC_REL14_BRTAKEN
++#define R_PPC64_REL14_BRNTAKEN	R_PPC_REL14_BRNTAKEN
++#define R_PPC64_GOT16		R_PPC_GOT16
++#define R_PPC64_GOT16_LO	R_PPC_GOT16_LO
++#define R_PPC64_GOT16_HI	R_PPC_GOT16_HI
++#define R_PPC64_GOT16_HA	R_PPC_GOT16_HA
++
++#define R_PPC64_COPY		R_PPC_COPY
++#define R_PPC64_GLOB_DAT	R_PPC_GLOB_DAT
++#define R_PPC64_JMP_SLOT	R_PPC_JMP_SLOT
++#define R_PPC64_RELATIVE	R_PPC_RELATIVE
++
++#define R_PPC64_UADDR32		R_PPC_UADDR32
++#define R_PPC64_UADDR16		R_PPC_UADDR16
++#define R_PPC64_REL32		R_PPC_REL32
++#define R_PPC64_PLT32		R_PPC_PLT32
++#define R_PPC64_PLTREL32	R_PPC_PLTREL32
++#define R_PPC64_PLT16_LO	R_PPC_PLT16_LO
++#define R_PPC64_PLT16_HI	R_PPC_PLT16_HI
++#define R_PPC64_PLT16_HA	R_PPC_PLT16_HA
++
++#define R_PPC64_SECTOFF		R_PPC_SECTOFF
++#define R_PPC64_SECTOFF_LO	R_PPC_SECTOFF_LO
++#define R_PPC64_SECTOFF_HI	R_PPC_SECTOFF_HI
++#define R_PPC64_SECTOFF_HA	R_PPC_SECTOFF_HA
++#define R_PPC64_ADDR30		37 /* word30 (S + A - P) >> 2 */
++#define R_PPC64_ADDR64		38 /* doubleword64 S + A */
++#define R_PPC64_ADDR16_HIGHER	39 /* half16 #higher(S + A) */
++#define R_PPC64_ADDR16_HIGHERA	40 /* half16 #highera(S + A) */
++#define R_PPC64_ADDR16_HIGHEST	41 /* half16 #highest(S + A) */
++#define R_PPC64_ADDR16_HIGHESTA	42 /* half16 #highesta(S + A) */
++#define R_PPC64_UADDR64		43 /* doubleword64 S + A */
++#define R_PPC64_REL64		44 /* doubleword64 S + A - P */
++#define R_PPC64_PLT64		45 /* doubleword64 L + A */
++#define R_PPC64_PLTREL64	46 /* doubleword64 L + A - P */
++#define R_PPC64_TOC16		47 /* half16* S + A - .TOC */
++#define R_PPC64_TOC16_LO	48 /* half16 #lo(S + A - .TOC.) */
++#define R_PPC64_TOC16_HI	49 /* half16 #hi(S + A - .TOC.) */
++#define R_PPC64_TOC16_HA	50 /* half16 #ha(S + A - .TOC.) */
++#define R_PPC64_TOC		51 /* doubleword64 .TOC */
++#define R_PPC64_PLTGOT16	52 /* half16* M + A */
++#define R_PPC64_PLTGOT16_LO	53 /* half16 #lo(M + A) */
++#define R_PPC64_PLTGOT16_HI	54 /* half16 #hi(M + A) */
++#define R_PPC64_PLTGOT16_HA	55 /* half16 #ha(M + A) */
++
++#define R_PPC64_ADDR16_DS	56 /* half16ds* (S + A) >> 2 */
++#define R_PPC64_ADDR16_LO_DS	57 /* half16ds  #lo(S + A) >> 2 */
++#define R_PPC64_GOT16_DS	58 /* half16ds* (G + A) >> 2 */
++#define R_PPC64_GOT16_LO_DS	59 /* half16ds  #lo(G + A) >> 2 */
++#define R_PPC64_PLT16_LO_DS	60 /* half16ds  #lo(L + A) >> 2 */
++#define R_PPC64_SECTOFF_DS	61 /* half16ds* (R + A) >> 2 */
++#define R_PPC64_SECTOFF_LO_DS	62 /* half16ds  #lo(R + A) >> 2 */
++#define R_PPC64_TOC16_DS	63 /* half16ds* (S + A - .TOC.) >> 2 */
++#define R_PPC64_TOC16_LO_DS	64 /* half16ds  #lo(S + A - .TOC.) >> 2 */
++#define R_PPC64_PLTGOT16_DS	65 /* half16ds* (M + A) >> 2 */
++#define R_PPC64_PLTGOT16_LO_DS	66 /* half16ds  #lo(M + A) >> 2 */
++
++/* PowerPC64 relocations defined for the TLS access ABI.  */
++#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
++#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
++#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
++#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
++#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
++#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
++#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
++#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
++#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
++#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
++#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
++#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
++#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
++#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
++#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
++#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
++#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
++#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
++#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
++#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
++#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got@tprel */
++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
++#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
++#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
++#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got@dtprel */
++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
++#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got@dtprel@h */
++#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got@dtprel@ha */
++#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
++#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel@l */
++#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel@higher */
++#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel@highera */
++#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel@highest */
++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel@highesta */
++#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
++#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel@l */
++#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel@higher */
++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel@highera */
++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel@highest */
++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel@highesta */
++
++/* GNU extension to support local ifunc.  */
++#define R_PPC64_JMP_IREL	247
++#define R_PPC64_IRELATIVE	248
++#define R_PPC64_REL16		249	/* half16   (sym+add-.) */
++#define R_PPC64_REL16_LO	250	/* half16   (sym+add-.)@l */
++#define R_PPC64_REL16_HI	251	/* half16   (sym+add-.)@h */
++#define R_PPC64_REL16_HA	252	/* half16   (sym+add-.)@ha */
++
++/* PowerPC64 specific values for the Dyn d_tag field.  */
++#define DT_PPC64_GLINK  (DT_LOPROC + 0)
++#define DT_PPC64_OPD	(DT_LOPROC + 1)
++#define DT_PPC64_OPDSZ	(DT_LOPROC + 2)
++#define DT_PPC64_NUM    3
++
++
++/* ARM specific declarations */
++
++/* Processor specific flags for the ELF header e_flags field.  */
++#define EF_ARM_RELEXEC		0x01
++#define EF_ARM_HASENTRY		0x02
++#define EF_ARM_INTERWORK	0x04
++#define EF_ARM_APCS_26		0x08
++#define EF_ARM_APCS_FLOAT	0x10
++#define EF_ARM_PIC		0x20
++#define EF_ARM_ALIGN8		0x40 /* 8-bit structure alignment is in use */
++#define EF_ARM_NEW_ABI		0x80
++#define EF_ARM_OLD_ABI		0x100
++#define EF_ARM_SOFT_FLOAT	0x200
++#define EF_ARM_VFP_FLOAT	0x400
++#define EF_ARM_MAVERICK_FLOAT	0x800
++
++
++/* Other constants defined in the ARM ELF spec. version B-01.  */
++/* NB. These conflict with values defined above.  */
++#define EF_ARM_SYMSARESORTED	0x04
++#define EF_ARM_DYNSYMSUSESEGIDX	0x08
++#define EF_ARM_MAPSYMSFIRST	0x10
++#define EF_ARM_EABIMASK		0XFF000000
++
++/* Constants defined in AAELF.  */
++#define EF_ARM_BE8	    0x00800000
++#define EF_ARM_LE8	    0x00400000
++
++#define EF_ARM_EABI_VERSION(flags)	((flags) & EF_ARM_EABIMASK)
++#define EF_ARM_EABI_UNKNOWN	0x00000000
++#define EF_ARM_EABI_VER1	0x01000000
++#define EF_ARM_EABI_VER2	0x02000000
++#define EF_ARM_EABI_VER3	0x03000000
++#define EF_ARM_EABI_VER4	0x04000000
++#define EF_ARM_EABI_VER5	0x05000000
++
++/* Additional symbol types for Thumb.  */
++#define STT_ARM_TFUNC		STT_LOPROC /* A Thumb function.  */
++#define STT_ARM_16BIT		STT_HIPROC /* A Thumb label.  */
++
++/* ARM-specific values for sh_flags */
++#define SHF_ARM_ENTRYSECT	0x10000000 /* Section contains an entry point */
++#define SHF_ARM_COMDEF		0x80000000 /* Section may be multiply defined
++					      in the input to a link step.  */
++
++/* ARM-specific program header flags */
++#define PF_ARM_SB		0x10000000 /* Segment contains the location
++					      addressed by the static base. */
++#define PF_ARM_PI		0x20000000 /* Position-independent segment.  */
++#define PF_ARM_ABS		0x40000000 /* Absolute segment.  */
++
++/* Processor specific values for the Phdr p_type field.  */
++#define PT_ARM_EXIDX		(PT_LOPROC + 1)	/* ARM unwind segment.  */
++
++/* Processor specific values for the Shdr sh_type field.  */
++#define SHT_ARM_EXIDX		(SHT_LOPROC + 1) /* ARM unwind section.  */
++#define SHT_ARM_PREEMPTMAP	(SHT_LOPROC + 2) /* Preemption details.  */
++#define SHT_ARM_ATTRIBUTES	(SHT_LOPROC + 3) /* ARM attributes section.  */
++
++
++/* ARM relocs.  */
++
++#define R_ARM_NONE		0	/* No reloc */
++#define R_ARM_PC24		1	/* PC relative 26 bit branch */
++#define R_ARM_ABS32		2	/* Direct 32 bit  */
++#define R_ARM_REL32		3	/* PC relative 32 bit */
++#define R_ARM_PC13		4
++#define R_ARM_ABS16		5	/* Direct 16 bit */
++#define R_ARM_ABS12		6	/* Direct 12 bit */
++#define R_ARM_THM_ABS5		7
++#define R_ARM_ABS8		8	/* Direct 8 bit */
++#define R_ARM_SBREL32		9
++#define R_ARM_THM_PC22		10
++#define R_ARM_THM_PC8		11
++#define R_ARM_AMP_VCALL9	12
++#define R_ARM_SWI24		13	/* Obsolete static relocation.  */
++#define R_ARM_TLS_DESC		13      /* Dynamic relocation.  */
++#define R_ARM_THM_SWI8		14
++#define R_ARM_XPC25		15
++#define R_ARM_THM_XPC22		16
++#define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
++#define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
++#define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
++#define R_ARM_COPY		20	/* Copy symbol at runtime */
++#define R_ARM_GLOB_DAT		21	/* Create GOT entry */
++#define R_ARM_JUMP_SLOT		22	/* Create PLT entry */
++#define R_ARM_RELATIVE		23	/* Adjust by program base */
++#define R_ARM_GOTOFF		24	/* 32 bit offset to GOT */
++#define R_ARM_GOTPC		25	/* 32 bit PC relative offset to GOT */
++#define R_ARM_GOT32		26	/* 32 bit GOT entry */
++#define R_ARM_PLT32		27	/* 32 bit PLT address */
++#define R_ARM_ALU_PCREL_7_0	32
++#define R_ARM_ALU_PCREL_15_8	33
++#define R_ARM_ALU_PCREL_23_15	34
++#define R_ARM_LDR_SBREL_11_0	35
++#define R_ARM_ALU_SBREL_19_12	36
++#define R_ARM_ALU_SBREL_27_20	37
++#define R_ARM_TLS_GOTDESC	90
++#define R_ARM_TLS_CALL		91
++#define R_ARM_TLS_DESCSEQ	92
++#define R_ARM_THM_TLS_CALL	93
++#define R_ARM_GNU_VTENTRY	100
++#define R_ARM_GNU_VTINHERIT	101
++#define R_ARM_THM_PC11		102	/* thumb unconditional branch */
++#define R_ARM_THM_PC9		103	/* thumb conditional branch */
++#define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic
++					   thread local data */
++#define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic
++					   thread local data */
++#define R_ARM_TLS_LDO32		106	/* 32 bit offset relative to TLS
++					   block */
++#define R_ARM_TLS_IE32		107	/* PC-rel 32 bit for GOT entry of
++					   static TLS block offset */
++#define R_ARM_TLS_LE32		108	/* 32 bit offset relative to static
++					   TLS block */
++#define	R_ARM_THM_TLS_DESCSEQ	129
++#define R_ARM_IRELATIVE		160
++#define R_ARM_RXPC25		249
++#define R_ARM_RSBREL32		250
++#define R_ARM_THM_RPC22		251
++#define R_ARM_RREL32		252
++#define R_ARM_RABS22		253
++#define R_ARM_RPC24		254
++#define R_ARM_RBASE		255
++/* Keep this the last entry.  */
++#define R_ARM_NUM		256
++
++/* IA-64 specific declarations.  */
++
++/* Processor specific flags for the Ehdr e_flags field.  */
++#define EF_IA_64_MASKOS		0x0000000f	/* os-specific flags */
++#define EF_IA_64_ABI64		0x00000010	/* 64-bit ABI */
++#define EF_IA_64_ARCH		0xff000000	/* arch. version mask */
++
++/* Processor specific values for the Phdr p_type field.  */
++#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
++#define PT_IA_64_UNWIND		(PT_LOPROC + 1)	/* ia64 unwind bits */
++#define PT_IA_64_HP_OPT_ANOT	(PT_LOOS + 0x12)
++#define PT_IA_64_HP_HSL_ANOT	(PT_LOOS + 0x13)
++#define PT_IA_64_HP_STACK	(PT_LOOS + 0x14)
++
++/* Processor specific flags for the Phdr p_flags field.  */
++#define PF_IA_64_NORECOV	0x80000000	/* spec insns w/o recovery */
++
++/* Processor specific values for the Shdr sh_type field.  */
++#define SHT_IA_64_EXT		(SHT_LOPROC + 0) /* extension bits */
++#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1) /* unwind bits */
++
++/* Processor specific flags for the Shdr sh_flags field.  */
++#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
++#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
++
++/* Processor specific values for the Dyn d_tag field.  */
++#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
++#define DT_IA_64_NUM		1
++
++/* IA-64 relocations.  */
++#define R_IA64_NONE		0x00	/* none */
++#define R_IA64_IMM14		0x21	/* symbol + addend, add imm14 */
++#define R_IA64_IMM22		0x22	/* symbol + addend, add imm22 */
++#define R_IA64_IMM64		0x23	/* symbol + addend, mov imm64 */
++#define R_IA64_DIR32MSB		0x24	/* symbol + addend, data4 MSB */
++#define R_IA64_DIR32LSB		0x25	/* symbol + addend, data4 LSB */
++#define R_IA64_DIR64MSB		0x26	/* symbol + addend, data8 MSB */
++#define R_IA64_DIR64LSB		0x27	/* symbol + addend, data8 LSB */
++#define R_IA64_GPREL22		0x2a	/* @gprel(sym + add), add imm22 */
++#define R_IA64_GPREL64I		0x2b	/* @gprel(sym + add), mov imm64 */
++#define R_IA64_GPREL32MSB	0x2c	/* @gprel(sym + add), data4 MSB */
++#define R_IA64_GPREL32LSB	0x2d	/* @gprel(sym + add), data4 LSB */
++#define R_IA64_GPREL64MSB	0x2e	/* @gprel(sym + add), data8 MSB */
++#define R_IA64_GPREL64LSB	0x2f	/* @gprel(sym + add), data8 LSB */
++#define R_IA64_LTOFF22		0x32	/* @ltoff(sym + add), add imm22 */
++#define R_IA64_LTOFF64I		0x33	/* @ltoff(sym + add), mov imm64 */
++#define R_IA64_PLTOFF22		0x3a	/* @pltoff(sym + add), add imm22 */
++#define R_IA64_PLTOFF64I	0x3b	/* @pltoff(sym + add), mov imm64 */
++#define R_IA64_PLTOFF64MSB	0x3e	/* @pltoff(sym + add), data8 MSB */
++#define R_IA64_PLTOFF64LSB	0x3f	/* @pltoff(sym + add), data8 LSB */
++#define R_IA64_FPTR64I		0x43	/* @fptr(sym + add), mov imm64 */
++#define R_IA64_FPTR32MSB	0x44	/* @fptr(sym + add), data4 MSB */
++#define R_IA64_FPTR32LSB	0x45	/* @fptr(sym + add), data4 LSB */
++#define R_IA64_FPTR64MSB	0x46	/* @fptr(sym + add), data8 MSB */
++#define R_IA64_FPTR64LSB	0x47	/* @fptr(sym + add), data8 LSB */
++#define R_IA64_PCREL60B		0x48	/* @pcrel(sym + add), brl */
++#define R_IA64_PCREL21B		0x49	/* @pcrel(sym + add), ptb, call */
++#define R_IA64_PCREL21M		0x4a	/* @pcrel(sym + add), chk.s */
++#define R_IA64_PCREL21F		0x4b	/* @pcrel(sym + add), fchkf */
++#define R_IA64_PCREL32MSB	0x4c	/* @pcrel(sym + add), data4 MSB */
++#define R_IA64_PCREL32LSB	0x4d	/* @pcrel(sym + add), data4 LSB */
++#define R_IA64_PCREL64MSB	0x4e	/* @pcrel(sym + add), data8 MSB */
++#define R_IA64_PCREL64LSB	0x4f	/* @pcrel(sym + add), data8 LSB */
++#define R_IA64_LTOFF_FPTR22	0x52	/* @ltoff(@fptr(s+a)), imm22 */
++#define R_IA64_LTOFF_FPTR64I	0x53	/* @ltoff(@fptr(s+a)), imm64 */
++#define R_IA64_LTOFF_FPTR32MSB	0x54	/* @ltoff(@fptr(s+a)), data4 MSB */
++#define R_IA64_LTOFF_FPTR32LSB	0x55	/* @ltoff(@fptr(s+a)), data4 LSB */
++#define R_IA64_LTOFF_FPTR64MSB	0x56	/* @ltoff(@fptr(s+a)), data8 MSB */
++#define R_IA64_LTOFF_FPTR64LSB	0x57	/* @ltoff(@fptr(s+a)), data8 LSB */
++#define R_IA64_SEGREL32MSB	0x5c	/* @segrel(sym + add), data4 MSB */
++#define R_IA64_SEGREL32LSB	0x5d	/* @segrel(sym + add), data4 LSB */
++#define R_IA64_SEGREL64MSB	0x5e	/* @segrel(sym + add), data8 MSB */
++#define R_IA64_SEGREL64LSB	0x5f	/* @segrel(sym + add), data8 LSB */
++#define R_IA64_SECREL32MSB	0x64	/* @secrel(sym + add), data4 MSB */
++#define R_IA64_SECREL32LSB	0x65	/* @secrel(sym + add), data4 LSB */
++#define R_IA64_SECREL64MSB	0x66	/* @secrel(sym + add), data8 MSB */
++#define R_IA64_SECREL64LSB	0x67	/* @secrel(sym + add), data8 LSB */
++#define R_IA64_REL32MSB		0x6c	/* data 4 + REL */
++#define R_IA64_REL32LSB		0x6d	/* data 4 + REL */
++#define R_IA64_REL64MSB		0x6e	/* data 8 + REL */
++#define R_IA64_REL64LSB		0x6f	/* data 8 + REL */
++#define R_IA64_LTV32MSB		0x74	/* symbol + addend, data4 MSB */
++#define R_IA64_LTV32LSB		0x75	/* symbol + addend, data4 LSB */
++#define R_IA64_LTV64MSB		0x76	/* symbol + addend, data8 MSB */
++#define R_IA64_LTV64LSB		0x77	/* symbol + addend, data8 LSB */
++#define R_IA64_PCREL21BI	0x79	/* @pcrel(sym + add), 21bit inst */
++#define R_IA64_PCREL22		0x7a	/* @pcrel(sym + add), 22bit inst */
++#define R_IA64_PCREL64I		0x7b	/* @pcrel(sym + add), 64bit inst */
++#define R_IA64_IPLTMSB		0x80	/* dynamic reloc, imported PLT, MSB */
++#define R_IA64_IPLTLSB		0x81	/* dynamic reloc, imported PLT, LSB */
++#define R_IA64_COPY		0x84	/* copy relocation */
++#define R_IA64_SUB		0x85	/* Addend and symbol difference */
++#define R_IA64_LTOFF22X		0x86	/* LTOFF22, relaxable.  */
++#define R_IA64_LDXMOV		0x87	/* Use of LTOFF22X.  */
++#define R_IA64_TPREL14		0x91	/* @tprel(sym + add), imm14 */
++#define R_IA64_TPREL22		0x92	/* @tprel(sym + add), imm22 */
++#define R_IA64_TPREL64I		0x93	/* @tprel(sym + add), imm64 */
++#define R_IA64_TPREL64MSB	0x96	/* @tprel(sym + add), data8 MSB */
++#define R_IA64_TPREL64LSB	0x97	/* @tprel(sym + add), data8 LSB */
++#define R_IA64_LTOFF_TPREL22	0x9a	/* @ltoff(@tprel(s+a)), imm2 */
++#define R_IA64_DTPMOD64MSB	0xa6	/* @dtpmod(sym + add), data8 MSB */
++#define R_IA64_DTPMOD64LSB	0xa7	/* @dtpmod(sym + add), data8 LSB */
++#define R_IA64_LTOFF_DTPMOD22	0xaa	/* @ltoff(@dtpmod(sym + add)), imm22 */
++#define R_IA64_DTPREL14		0xb1	/* @dtprel(sym + add), imm14 */
++#define R_IA64_DTPREL22		0xb2	/* @dtprel(sym + add), imm22 */
++#define R_IA64_DTPREL64I	0xb3	/* @dtprel(sym + add), imm64 */
++#define R_IA64_DTPREL32MSB	0xb4	/* @dtprel(sym + add), data4 MSB */
++#define R_IA64_DTPREL32LSB	0xb5	/* @dtprel(sym + add), data4 LSB */
++#define R_IA64_DTPREL64MSB	0xb6	/* @dtprel(sym + add), data8 MSB */
++#define R_IA64_DTPREL64LSB	0xb7	/* @dtprel(sym + add), data8 LSB */
++#define R_IA64_LTOFF_DTPREL22	0xba	/* @ltoff(@dtprel(s+a)), imm22 */
++
++/* SH specific declarations */
++
++/* Processor specific flags for the ELF header e_flags field.  */
++#define EF_SH_MACH_MASK		0x1f
++#define EF_SH_UNKNOWN		0x0
++#define EF_SH1			0x1
++#define EF_SH2			0x2
++#define EF_SH3			0x3
++#define EF_SH_DSP		0x4
++#define EF_SH3_DSP		0x5
++#define EF_SH4AL_DSP		0x6
++#define EF_SH3E			0x8
++#define EF_SH4			0x9
++#define EF_SH2E			0xb
++#define EF_SH4A			0xc
++#define EF_SH2A			0xd
++#define EF_SH4_NOFPU		0x10
++#define EF_SH4A_NOFPU		0x11
++#define EF_SH4_NOMMU_NOFPU	0x12
++#define EF_SH2A_NOFPU		0x13
++#define EF_SH3_NOMMU		0x14
++#define EF_SH2A_SH4_NOFPU	0x15
++#define EF_SH2A_SH3_NOFPU	0x16
++#define EF_SH2A_SH4		0x17
++#define EF_SH2A_SH3E		0x18
++
++/* SH relocs.  */
++#define	R_SH_NONE		0
++#define	R_SH_DIR32		1
++#define	R_SH_REL32		2
++#define	R_SH_DIR8WPN		3
++#define	R_SH_IND12W		4
++#define	R_SH_DIR8WPL		5
++#define	R_SH_DIR8WPZ		6
++#define	R_SH_DIR8BP		7
++#define	R_SH_DIR8W		8
++#define	R_SH_DIR8L		9
++#define	R_SH_SWITCH16		25
++#define	R_SH_SWITCH32		26
++#define	R_SH_USES		27
++#define	R_SH_COUNT		28
++#define	R_SH_ALIGN		29
++#define	R_SH_CODE		30
++#define	R_SH_DATA		31
++#define	R_SH_LABEL		32
++#define	R_SH_SWITCH8		33
++#define	R_SH_GNU_VTINHERIT	34
++#define	R_SH_GNU_VTENTRY	35
++#define	R_SH_TLS_GD_32		144
++#define	R_SH_TLS_LD_32		145
++#define	R_SH_TLS_LDO_32		146
++#define	R_SH_TLS_IE_32		147
++#define	R_SH_TLS_LE_32		148
++#define	R_SH_TLS_DTPMOD32	149
++#define	R_SH_TLS_DTPOFF32	150
++#define	R_SH_TLS_TPOFF32	151
++#define	R_SH_GOT32		160
++#define	R_SH_PLT32		161
++#define	R_SH_COPY		162
++#define	R_SH_GLOB_DAT		163
++#define	R_SH_JMP_SLOT		164
++#define	R_SH_RELATIVE		165
++#define	R_SH_GOTOFF		166
++#define	R_SH_GOTPC		167
++/* Keep this the last entry.  */
++#define	R_SH_NUM		256
++
++/* S/390 specific definitions.  */
++
++/* Valid values for the e_flags field.  */
++
++#define EF_S390_HIGH_GPRS    0x00000001  /* High GPRs kernel facility needed.  */
++
++/* Additional s390 relocs */
++
++#define R_390_NONE		0	/* No reloc.  */
++#define R_390_8			1	/* Direct 8 bit.  */
++#define R_390_12		2	/* Direct 12 bit.  */
++#define R_390_16		3	/* Direct 16 bit.  */
++#define R_390_32		4	/* Direct 32 bit.  */
++#define R_390_PC32		5	/* PC relative 32 bit.	*/
++#define R_390_GOT12		6	/* 12 bit GOT offset.  */
++#define R_390_GOT32		7	/* 32 bit GOT offset.  */
++#define R_390_PLT32		8	/* 32 bit PC relative PLT address.  */
++#define R_390_COPY		9	/* Copy symbol at runtime.  */
++#define R_390_GLOB_DAT		10	/* Create GOT entry.  */
++#define R_390_JMP_SLOT		11	/* Create PLT entry.  */
++#define R_390_RELATIVE		12	/* Adjust by program base.  */
++#define R_390_GOTOFF32		13	/* 32 bit offset to GOT.	 */
++#define R_390_GOTPC		14	/* 32 bit PC relative offset to GOT.  */
++#define R_390_GOT16		15	/* 16 bit GOT offset.  */
++#define R_390_PC16		16	/* PC relative 16 bit.	*/
++#define R_390_PC16DBL		17	/* PC relative 16 bit shifted by 1.  */
++#define R_390_PLT16DBL		18	/* 16 bit PC rel. PLT shifted by 1.  */
++#define R_390_PC32DBL		19	/* PC relative 32 bit shifted by 1.  */
++#define R_390_PLT32DBL		20	/* 32 bit PC rel. PLT shifted by 1.  */
++#define R_390_GOTPCDBL		21	/* 32 bit PC rel. GOT shifted by 1.  */
++#define R_390_64		22	/* Direct 64 bit.  */
++#define R_390_PC64		23	/* PC relative 64 bit.	*/
++#define R_390_GOT64		24	/* 64 bit GOT offset.  */
++#define R_390_PLT64		25	/* 64 bit PC relative PLT address.  */
++#define R_390_GOTENT		26	/* 32 bit PC rel. to GOT entry >> 1. */
++#define R_390_GOTOFF16		27	/* 16 bit offset to GOT. */
++#define R_390_GOTOFF64		28	/* 64 bit offset to GOT. */
++#define R_390_GOTPLT12		29	/* 12 bit offset to jump slot.	*/
++#define R_390_GOTPLT16		30	/* 16 bit offset to jump slot.	*/
++#define R_390_GOTPLT32		31	/* 32 bit offset to jump slot.	*/
++#define R_390_GOTPLT64		32	/* 64 bit offset to jump slot.	*/
++#define R_390_GOTPLTENT		33	/* 32 bit rel. offset to jump slot.  */
++#define R_390_PLTOFF16		34	/* 16 bit offset from GOT to PLT. */
++#define R_390_PLTOFF32		35	/* 32 bit offset from GOT to PLT. */
++#define R_390_PLTOFF64		36	/* 16 bit offset from GOT to PLT. */
++#define R_390_TLS_LOAD		37	/* Tag for load insn in TLS code.  */
++#define R_390_TLS_GDCALL	38	/* Tag for function call in general
++					   dynamic TLS code. */
++#define R_390_TLS_LDCALL	39	/* Tag for function call in local
++					   dynamic TLS code. */
++#define R_390_TLS_GD32		40	/* Direct 32 bit for general dynamic
++					   thread local data.  */
++#define R_390_TLS_GD64		41	/* Direct 64 bit for general dynamic
++					  thread local data.  */
++#define R_390_TLS_GOTIE12	42	/* 12 bit GOT offset for static TLS
++					   block offset.  */
++#define R_390_TLS_GOTIE32	43	/* 32 bit GOT offset for static TLS
++					   block offset.  */
++#define R_390_TLS_GOTIE64	44	/* 64 bit GOT offset for static TLS
++					   block offset. */
++#define R_390_TLS_LDM32		45	/* Direct 32 bit for local dynamic
++					   thread local data in LE code.  */
++#define R_390_TLS_LDM64		46	/* Direct 64 bit for local dynamic
++					   thread local data in LE code.  */
++#define R_390_TLS_IE32		47	/* 32 bit address of GOT entry for
++					   negated static TLS block offset.  */
++#define R_390_TLS_IE64		48	/* 64 bit address of GOT entry for
++					   negated static TLS block offset.  */
++#define R_390_TLS_IEENT		49	/* 32 bit rel. offset to GOT entry for
++					   negated static TLS block offset.  */
++#define R_390_TLS_LE32		50	/* 32 bit negated offset relative to
++					   static TLS block.  */
++#define R_390_TLS_LE64		51	/* 64 bit negated offset relative to
++					   static TLS block.  */
++#define R_390_TLS_LDO32		52	/* 32 bit offset relative to TLS
++					   block.  */
++#define R_390_TLS_LDO64		53	/* 64 bit offset relative to TLS
++					   block.  */
++#define R_390_TLS_DTPMOD	54	/* ID of module containing symbol.  */
++#define R_390_TLS_DTPOFF	55	/* Offset in TLS block.	 */
++#define R_390_TLS_TPOFF		56	/* Negated offset in static TLS
++					   block.  */
++#define R_390_20		57	/* Direct 20 bit.  */
++#define R_390_GOT20		58	/* 20 bit GOT offset.  */
++#define R_390_GOTPLT20		59	/* 20 bit offset to jump slot.  */
++#define R_390_TLS_GOTIE20	60	/* 20 bit GOT offset for static TLS
++					   block offset.  */
++#define R_390_IRELATIVE         61      /* STT_GNU_IFUNC relocation.  */
++/* Keep this the last entry.  */
++#define R_390_NUM		62
++
++
++/* CRIS relocations.  */
++#define R_CRIS_NONE		0
++#define R_CRIS_8		1
++#define R_CRIS_16		2
++#define R_CRIS_32		3
++#define R_CRIS_8_PCREL		4
++#define R_CRIS_16_PCREL		5
++#define R_CRIS_32_PCREL		6
++#define R_CRIS_GNU_VTINHERIT	7
++#define R_CRIS_GNU_VTENTRY	8
++#define R_CRIS_COPY		9
++#define R_CRIS_GLOB_DAT		10
++#define R_CRIS_JUMP_SLOT	11
++#define R_CRIS_RELATIVE		12
++#define R_CRIS_16_GOT		13
++#define R_CRIS_32_GOT		14
++#define R_CRIS_16_GOTPLT	15
++#define R_CRIS_32_GOTPLT	16
++#define R_CRIS_32_GOTREL	17
++#define R_CRIS_32_PLT_GOTREL	18
++#define R_CRIS_32_PLT_PCREL	19
++
++#define R_CRIS_NUM		20
++
++
++/* AMD x86-64 relocations.  */
++#define R_X86_64_NONE		0	/* No reloc */
++#define R_X86_64_64		1	/* Direct 64 bit  */
++#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
++#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
++#define R_X86_64_PLT32		4	/* 32 bit PLT address */
++#define R_X86_64_COPY		5	/* Copy symbol at runtime */
++#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
++#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
++#define R_X86_64_RELATIVE	8	/* Adjust by program base */
++#define R_X86_64_GOTPCREL	9	/* 32 bit signed PC relative
++					   offset to GOT */
++#define R_X86_64_32		10	/* Direct 32 bit zero extended */
++#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
++#define R_X86_64_16		12	/* Direct 16 bit zero extended */
++#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
++#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
++#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
++#define R_X86_64_DTPMOD64	16	/* ID of module containing symbol */
++#define R_X86_64_DTPOFF64	17	/* Offset in module's TLS block */
++#define R_X86_64_TPOFF64	18	/* Offset in initial TLS block */
++#define R_X86_64_TLSGD		19	/* 32 bit signed PC relative offset
++					   to two GOT entries for GD symbol */
++#define R_X86_64_TLSLD		20	/* 32 bit signed PC relative offset
++					   to two GOT entries for LD symbol */
++#define R_X86_64_DTPOFF32	21	/* Offset in TLS block */
++#define R_X86_64_GOTTPOFF	22	/* 32 bit signed PC relative offset
++					   to GOT entry for IE symbol */
++#define R_X86_64_TPOFF32	23	/* Offset in initial TLS block */
++#define R_X86_64_PC64		24	/* PC relative 64 bit */
++#define R_X86_64_GOTOFF64	25	/* 64 bit offset to GOT */
++#define R_X86_64_GOTPC32	26	/* 32 bit signed pc relative
++					   offset to GOT */
++#define R_X86_64_GOT64		27	/* 64-bit GOT entry offset */
++#define R_X86_64_GOTPCREL64	28	/* 64-bit PC relative offset
++					   to GOT entry */
++#define R_X86_64_GOTPC64	29	/* 64-bit PC relative offset to GOT */
++#define R_X86_64_GOTPLT64	30 	/* like GOT64, says PLT entry needed */
++#define R_X86_64_PLTOFF64	31	/* 64-bit GOT relative offset
++					   to PLT entry */
++#define R_X86_64_SIZE32		32	/* Size of symbol plus 32-bit addend */
++#define R_X86_64_SIZE64		33	/* Size of symbol plus 64-bit addend */
++#define R_X86_64_GOTPC32_TLSDESC 34	/* GOT offset for TLS descriptor.  */
++#define R_X86_64_TLSDESC_CALL   35	/* Marker for call through TLS
++					   descriptor.  */
++#define R_X86_64_TLSDESC        36	/* TLS descriptor.  */
++#define R_X86_64_IRELATIVE	37	/* Adjust indirectly by program base */
++#define R_X86_64_RELATIVE64	38	/* 64-bit adjust by program base */
++
++#define R_X86_64_NUM		39
++
++
++/* AM33 relocations.  */
++#define R_MN10300_NONE		0	/* No reloc.  */
++#define R_MN10300_32		1	/* Direct 32 bit.  */
++#define R_MN10300_16		2	/* Direct 16 bit.  */
++#define R_MN10300_8		3	/* Direct 8 bit.  */
++#define R_MN10300_PCREL32	4	/* PC-relative 32-bit.  */
++#define R_MN10300_PCREL16	5	/* PC-relative 16-bit signed.  */
++#define R_MN10300_PCREL8	6	/* PC-relative 8-bit signed.  */
++#define R_MN10300_GNU_VTINHERIT	7	/* Ancient C++ vtable garbage... */
++#define R_MN10300_GNU_VTENTRY	8	/* ... collection annotation.  */
++#define R_MN10300_24		9	/* Direct 24 bit.  */
++#define R_MN10300_GOTPC32	10	/* 32-bit PCrel offset to GOT.  */
++#define R_MN10300_GOTPC16	11	/* 16-bit PCrel offset to GOT.  */
++#define R_MN10300_GOTOFF32	12	/* 32-bit offset from GOT.  */
++#define R_MN10300_GOTOFF24	13	/* 24-bit offset from GOT.  */
++#define R_MN10300_GOTOFF16	14	/* 16-bit offset from GOT.  */
++#define R_MN10300_PLT32		15	/* 32-bit PCrel to PLT entry.  */
++#define R_MN10300_PLT16		16	/* 16-bit PCrel to PLT entry.  */
++#define R_MN10300_GOT32		17	/* 32-bit offset to GOT entry.  */
++#define R_MN10300_GOT24		18	/* 24-bit offset to GOT entry.  */
++#define R_MN10300_GOT16		19	/* 16-bit offset to GOT entry.  */
++#define R_MN10300_COPY		20	/* Copy symbol at runtime.  */
++#define R_MN10300_GLOB_DAT	21	/* Create GOT entry.  */
++#define R_MN10300_JMP_SLOT	22	/* Create PLT entry.  */
++#define R_MN10300_RELATIVE	23	/* Adjust by program base.  */
++
++#define R_MN10300_NUM		24
++
++
++/* M32R relocs.  */
++#define R_M32R_NONE		0	/* No reloc. */
++#define R_M32R_16		1	/* Direct 16 bit. */
++#define R_M32R_32		2	/* Direct 32 bit. */
++#define R_M32R_24		3	/* Direct 24 bit. */
++#define R_M32R_10_PCREL		4	/* PC relative 10 bit shifted. */
++#define R_M32R_18_PCREL		5	/* PC relative 18 bit shifted. */
++#define R_M32R_26_PCREL		6	/* PC relative 26 bit shifted. */
++#define R_M32R_HI16_ULO		7	/* High 16 bit with unsigned low. */
++#define R_M32R_HI16_SLO		8	/* High 16 bit with signed low. */
++#define R_M32R_LO16		9	/* Low 16 bit. */
++#define R_M32R_SDA16		10	/* 16 bit offset in SDA. */
++#define R_M32R_GNU_VTINHERIT	11
++#define R_M32R_GNU_VTENTRY	12
++/* M32R relocs use SHT_RELA.  */
++#define R_M32R_16_RELA		33	/* Direct 16 bit. */
++#define R_M32R_32_RELA		34	/* Direct 32 bit. */
++#define R_M32R_24_RELA		35	/* Direct 24 bit. */
++#define R_M32R_10_PCREL_RELA	36	/* PC relative 10 bit shifted. */
++#define R_M32R_18_PCREL_RELA	37	/* PC relative 18 bit shifted. */
++#define R_M32R_26_PCREL_RELA	38	/* PC relative 26 bit shifted. */
++#define R_M32R_HI16_ULO_RELA	39	/* High 16 bit with unsigned low */
++#define R_M32R_HI16_SLO_RELA	40	/* High 16 bit with signed low */
++#define R_M32R_LO16_RELA	41	/* Low 16 bit */
++#define R_M32R_SDA16_RELA	42	/* 16 bit offset in SDA */
++#define R_M32R_RELA_GNU_VTINHERIT	43
++#define R_M32R_RELA_GNU_VTENTRY	44
++#define R_M32R_REL32		45	/* PC relative 32 bit.  */
++
++#define R_M32R_GOT24		48	/* 24 bit GOT entry */
++#define R_M32R_26_PLTREL	49	/* 26 bit PC relative to PLT shifted */
++#define R_M32R_COPY		50	/* Copy symbol at runtime */
++#define R_M32R_GLOB_DAT		51	/* Create GOT entry */
++#define R_M32R_JMP_SLOT		52	/* Create PLT entry */
++#define R_M32R_RELATIVE		53	/* Adjust by program base */
++#define R_M32R_GOTOFF		54	/* 24 bit offset to GOT */
++#define R_M32R_GOTPC24		55	/* 24 bit PC relative offset to GOT */
++#define R_M32R_GOT16_HI_ULO	56	/* High 16 bit GOT entry with unsigned
++					   low */
++#define R_M32R_GOT16_HI_SLO	57	/* High 16 bit GOT entry with signed
++					   low */
++#define R_M32R_GOT16_LO		58	/* Low 16 bit GOT entry */
++#define R_M32R_GOTPC_HI_ULO	59	/* High 16 bit PC relative offset to
++					   GOT with unsigned low */
++#define R_M32R_GOTPC_HI_SLO	60	/* High 16 bit PC relative offset to
++					   GOT with signed low */
++#define R_M32R_GOTPC_LO		61	/* Low 16 bit PC relative offset to
++					   GOT */
++#define R_M32R_GOTOFF_HI_ULO	62	/* High 16 bit offset to GOT
++					   with unsigned low */
++#define R_M32R_GOTOFF_HI_SLO	63	/* High 16 bit offset to GOT
++					   with signed low */
++#define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
++#define R_M32R_NUM		256	/* Keep this the last entry. */
++
++
++/* TILEPro relocations.  */
++#define R_TILEPRO_NONE		0	/* No reloc */
++#define R_TILEPRO_32		1	/* Direct 32 bit */
++#define R_TILEPRO_16		2	/* Direct 16 bit */
++#define R_TILEPRO_8		3	/* Direct 8 bit */
++#define R_TILEPRO_32_PCREL	4	/* PC relative 32 bit */
++#define R_TILEPRO_16_PCREL	5	/* PC relative 16 bit */
++#define R_TILEPRO_8_PCREL	6	/* PC relative 8 bit */
++#define R_TILEPRO_LO16		7	/* Low 16 bit */
++#define R_TILEPRO_HI16		8	/* High 16 bit */
++#define R_TILEPRO_HA16		9	/* High 16 bit, adjusted */
++#define R_TILEPRO_COPY		10	/* Copy relocation */
++#define R_TILEPRO_GLOB_DAT	11	/* Create GOT entry */
++#define R_TILEPRO_JMP_SLOT	12	/* Create PLT entry */
++#define R_TILEPRO_RELATIVE	13	/* Adjust by program base */
++#define R_TILEPRO_BROFF_X1	14	/* X1 pipe branch offset */
++#define R_TILEPRO_JOFFLONG_X1	15	/* X1 pipe jump offset */
++#define R_TILEPRO_JOFFLONG_X1_PLT 16	/* X1 pipe jump offset to PLT */
++#define R_TILEPRO_IMM8_X0	17	/* X0 pipe 8-bit */
++#define R_TILEPRO_IMM8_Y0	18	/* Y0 pipe 8-bit */
++#define R_TILEPRO_IMM8_X1	19	/* X1 pipe 8-bit */
++#define R_TILEPRO_IMM8_Y1	20	/* Y1 pipe 8-bit */
++#define R_TILEPRO_MT_IMM15_X1	21	/* X1 pipe mtspr */
++#define R_TILEPRO_MF_IMM15_X1	22	/* X1 pipe mfspr */
++#define R_TILEPRO_IMM16_X0	23	/* X0 pipe 16-bit */
++#define R_TILEPRO_IMM16_X1	24	/* X1 pipe 16-bit */
++#define R_TILEPRO_IMM16_X0_LO	25	/* X0 pipe low 16-bit */
++#define R_TILEPRO_IMM16_X1_LO	26	/* X1 pipe low 16-bit */
++#define R_TILEPRO_IMM16_X0_HI	27	/* X0 pipe high 16-bit */
++#define R_TILEPRO_IMM16_X1_HI	28	/* X1 pipe high 16-bit */
++#define R_TILEPRO_IMM16_X0_HA	29	/* X0 pipe high 16-bit, adjusted */
++#define R_TILEPRO_IMM16_X1_HA	30	/* X1 pipe high 16-bit, adjusted */
++#define R_TILEPRO_IMM16_X0_PCREL 31	/* X0 pipe PC relative 16 bit */
++#define R_TILEPRO_IMM16_X1_PCREL 32	/* X1 pipe PC relative 16 bit */
++#define R_TILEPRO_IMM16_X0_LO_PCREL 33	/* X0 pipe PC relative low 16 bit */
++#define R_TILEPRO_IMM16_X1_LO_PCREL 34	/* X1 pipe PC relative low 16 bit */
++#define R_TILEPRO_IMM16_X0_HI_PCREL 35	/* X0 pipe PC relative high 16 bit */
++#define R_TILEPRO_IMM16_X1_HI_PCREL 36	/* X1 pipe PC relative high 16 bit */
++#define R_TILEPRO_IMM16_X0_HA_PCREL 37	/* X0 pipe PC relative ha() 16 bit */
++#define R_TILEPRO_IMM16_X1_HA_PCREL 38	/* X1 pipe PC relative ha() 16 bit */
++#define R_TILEPRO_IMM16_X0_GOT	39	/* X0 pipe 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X1_GOT	40	/* X1 pipe 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X0_GOT_LO 41	/* X0 pipe low 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X1_GOT_LO 42	/* X1 pipe low 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X0_GOT_HI 43	/* X0 pipe high 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X1_GOT_HI 44	/* X1 pipe high 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X0_GOT_HA 45	/* X0 pipe ha() 16-bit GOT offset */
++#define R_TILEPRO_IMM16_X1_GOT_HA 46	/* X1 pipe ha() 16-bit GOT offset */
++#define R_TILEPRO_MMSTART_X0	47	/* X0 pipe mm "start" */
++#define R_TILEPRO_MMEND_X0	48	/* X0 pipe mm "end" */
++#define R_TILEPRO_MMSTART_X1	49	/* X1 pipe mm "start" */
++#define R_TILEPRO_MMEND_X1	50	/* X1 pipe mm "end" */
++#define R_TILEPRO_SHAMT_X0	51	/* X0 pipe shift amount */
++#define R_TILEPRO_SHAMT_X1	52	/* X1 pipe shift amount */
++#define R_TILEPRO_SHAMT_Y0	53	/* Y0 pipe shift amount */
++#define R_TILEPRO_SHAMT_Y1	54	/* Y1 pipe shift amount */
++#define R_TILEPRO_DEST_IMM8_X1	55	/* X1 pipe destination 8-bit */
++/* Relocs 56-59 are currently not defined.  */
++#define R_TILEPRO_TLS_GD_CALL	60	/* "jal" for TLS GD */
++#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61	/* X0 pipe "addi" for TLS GD */
++#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62	/* X1 pipe "addi" for TLS GD */
++#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63	/* Y0 pipe "addi" for TLS GD */
++#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64	/* Y1 pipe "addi" for TLS GD */
++#define R_TILEPRO_TLS_IE_LOAD	65	/* "lw_tls" for TLS IE */
++#define R_TILEPRO_IMM16_X0_TLS_GD 66	/* X0 pipe 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X1_TLS_GD 67	/* X1 pipe 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68	/* X0 pipe low 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69	/* X1 pipe low 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70	/* X0 pipe high 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71	/* X1 pipe high 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72	/* X0 pipe ha() 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73	/* X1 pipe ha() 16-bit TLS GD offset */
++#define R_TILEPRO_IMM16_X0_TLS_IE 74	/* X0 pipe 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X1_TLS_IE 75	/* X1 pipe 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76	/* X0 pipe low 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77	/* X1 pipe low 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78	/* X0 pipe high 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79	/* X1 pipe high 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80	/* X0 pipe ha() 16-bit TLS IE offset */
++#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81	/* X1 pipe ha() 16-bit TLS IE offset */
++#define R_TILEPRO_TLS_DTPMOD32	82	/* ID of module containing symbol */
++#define R_TILEPRO_TLS_DTPOFF32	83	/* Offset in TLS block */
++#define R_TILEPRO_TLS_TPOFF32	84	/* Offset in static TLS block */
++#define R_TILEPRO_IMM16_X0_TLS_LE 85	/* X0 pipe 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X1_TLS_LE 86	/* X1 pipe 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87	/* X0 pipe low 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88	/* X1 pipe low 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89	/* X0 pipe high 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90	/* X1 pipe high 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91	/* X0 pipe ha() 16-bit TLS LE offset */
++#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92	/* X1 pipe ha() 16-bit TLS LE offset */
++
++#define R_TILEPRO_GNU_VTINHERIT	128	/* GNU C++ vtable hierarchy */
++#define R_TILEPRO_GNU_VTENTRY	129	/* GNU C++ vtable member usage */
++
++#define R_TILEPRO_NUM		130
++
++
++/* TILE-Gx relocations.  */
++#define R_TILEGX_NONE		0	/* No reloc */
++#define R_TILEGX_64		1	/* Direct 64 bit */
++#define R_TILEGX_32		2	/* Direct 32 bit */
++#define R_TILEGX_16		3	/* Direct 16 bit */
++#define R_TILEGX_8		4	/* Direct 8 bit */
++#define R_TILEGX_64_PCREL	5	/* PC relative 64 bit */
++#define R_TILEGX_32_PCREL	6	/* PC relative 32 bit */
++#define R_TILEGX_16_PCREL	7	/* PC relative 16 bit */
++#define R_TILEGX_8_PCREL	8	/* PC relative 8 bit */
++#define R_TILEGX_HW0		9	/* hword 0 16-bit */
++#define R_TILEGX_HW1		10	/* hword 1 16-bit */
++#define R_TILEGX_HW2		11	/* hword 2 16-bit */
++#define R_TILEGX_HW3		12	/* hword 3 16-bit */
++#define R_TILEGX_HW0_LAST	13	/* last hword 0 16-bit */
++#define R_TILEGX_HW1_LAST	14	/* last hword 1 16-bit */
++#define R_TILEGX_HW2_LAST	15	/* last hword 2 16-bit */
++#define R_TILEGX_COPY		16	/* Copy relocation */
++#define R_TILEGX_GLOB_DAT	17	/* Create GOT entry */
++#define R_TILEGX_JMP_SLOT	18	/* Create PLT entry */
++#define R_TILEGX_RELATIVE	19	/* Adjust by program base */
++#define R_TILEGX_BROFF_X1	20	/* X1 pipe branch offset */
++#define R_TILEGX_JUMPOFF_X1	21	/* X1 pipe jump offset */
++#define R_TILEGX_JUMPOFF_X1_PLT	22	/* X1 pipe jump offset to PLT */
++#define R_TILEGX_IMM8_X0	23	/* X0 pipe 8-bit */
++#define R_TILEGX_IMM8_Y0	24	/* Y0 pipe 8-bit */
++#define R_TILEGX_IMM8_X1	25	/* X1 pipe 8-bit */
++#define R_TILEGX_IMM8_Y1	26	/* Y1 pipe 8-bit */
++#define R_TILEGX_DEST_IMM8_X1	27	/* X1 pipe destination 8-bit */
++#define R_TILEGX_MT_IMM14_X1	28	/* X1 pipe mtspr */
++#define R_TILEGX_MF_IMM14_X1	29	/* X1 pipe mfspr */
++#define R_TILEGX_MMSTART_X0	30	/* X0 pipe mm "start" */
++#define R_TILEGX_MMEND_X0	31	/* X0 pipe mm "end" */
++#define R_TILEGX_SHAMT_X0	32	/* X0 pipe shift amount */
++#define R_TILEGX_SHAMT_X1	33	/* X1 pipe shift amount */
++#define R_TILEGX_SHAMT_Y0	34	/* Y0 pipe shift amount */
++#define R_TILEGX_SHAMT_Y1	35	/* Y1 pipe shift amount */
++#define R_TILEGX_IMM16_X0_HW0	36	/* X0 pipe hword 0 */
++#define R_TILEGX_IMM16_X1_HW0	37	/* X1 pipe hword 0 */
++#define R_TILEGX_IMM16_X0_HW1	38	/* X0 pipe hword 1 */
++#define R_TILEGX_IMM16_X1_HW1	39	/* X1 pipe hword 1 */
++#define R_TILEGX_IMM16_X0_HW2	40	/* X0 pipe hword 2 */
++#define R_TILEGX_IMM16_X1_HW2	41	/* X1 pipe hword 2 */
++#define R_TILEGX_IMM16_X0_HW3	42	/* X0 pipe hword 3 */
++#define R_TILEGX_IMM16_X1_HW3	43	/* X1 pipe hword 3 */
++#define R_TILEGX_IMM16_X0_HW0_LAST 44	/* X0 pipe last hword 0 */
++#define R_TILEGX_IMM16_X1_HW0_LAST 45	/* X1 pipe last hword 0 */
++#define R_TILEGX_IMM16_X0_HW1_LAST 46	/* X0 pipe last hword 1 */
++#define R_TILEGX_IMM16_X1_HW1_LAST 47	/* X1 pipe last hword 1 */
++#define R_TILEGX_IMM16_X0_HW2_LAST 48	/* X0 pipe last hword 2 */
++#define R_TILEGX_IMM16_X1_HW2_LAST 49	/* X1 pipe last hword 2 */
++#define R_TILEGX_IMM16_X0_HW0_PCREL 50	/* X0 pipe PC relative hword 0 */
++#define R_TILEGX_IMM16_X1_HW0_PCREL 51	/* X1 pipe PC relative hword 0 */
++#define R_TILEGX_IMM16_X0_HW1_PCREL 52	/* X0 pipe PC relative hword 1 */
++#define R_TILEGX_IMM16_X1_HW1_PCREL 53	/* X1 pipe PC relative hword 1 */
++#define R_TILEGX_IMM16_X0_HW2_PCREL 54	/* X0 pipe PC relative hword 2 */
++#define R_TILEGX_IMM16_X1_HW2_PCREL 55	/* X1 pipe PC relative hword 2 */
++#define R_TILEGX_IMM16_X0_HW3_PCREL 56	/* X0 pipe PC relative hword 3 */
++#define R_TILEGX_IMM16_X1_HW3_PCREL 57	/* X1 pipe PC relative hword 3 */
++#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */
++#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */
++#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */
++#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */
++#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */
++#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */
++#define R_TILEGX_IMM16_X0_HW0_GOT 64	/* X0 pipe hword 0 GOT offset */
++#define R_TILEGX_IMM16_X1_HW0_GOT 65	/* X1 pipe hword 0 GOT offset */
++/* Relocs 66-71 are currently not defined.  */
++#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */
++#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */
++#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */
++#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */
++/* Relocs 76-77 are currently not defined.  */
++#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78	/* X0 pipe hword 0 TLS GD offset */
++#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79	/* X1 pipe hword 0 TLS GD offset */
++#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80	/* X0 pipe hword 0 TLS LE offset */
++#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81	/* X1 pipe hword 0 TLS LE offset */
++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */
++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */
++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */
++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */
++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */
++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */
++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */
++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */
++/* Relocs 90-91 are currently not defined.  */
++#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92	/* X0 pipe hword 0 TLS IE offset */
++#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93	/* X1 pipe hword 0 TLS IE offset */
++/* Relocs 94-99 are currently not defined.  */
++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */
++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */
++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */
++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */
++/* Relocs 104-105 are currently not defined.  */
++#define R_TILEGX_TLS_DTPMOD64	106	/* 64-bit ID of symbol's module */
++#define R_TILEGX_TLS_DTPOFF64	107	/* 64-bit offset in TLS block */
++#define R_TILEGX_TLS_TPOFF64	108	/* 64-bit offset in static TLS block */
++#define R_TILEGX_TLS_DTPMOD32	109	/* 32-bit ID of symbol's module */
++#define R_TILEGX_TLS_DTPOFF32	110	/* 32-bit offset in TLS block */
++#define R_TILEGX_TLS_TPOFF32	111	/* 32-bit offset in static TLS block */
++#define R_TILEGX_TLS_GD_CALL	112	/* "jal" for TLS GD */
++#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113	/* X0 pipe "addi" for TLS GD */
++#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114	/* X1 pipe "addi" for TLS GD */
++#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115	/* Y0 pipe "addi" for TLS GD */
++#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116	/* Y1 pipe "addi" for TLS GD */
++#define R_TILEGX_TLS_IE_LOAD	117	/* "ld_tls" for TLS IE */
++#define R_TILEGX_IMM8_X0_TLS_ADD 118	/* X0 pipe "addi" for TLS GD/IE */
++#define R_TILEGX_IMM8_X1_TLS_ADD 119	/* X1 pipe "addi" for TLS GD/IE */
++#define R_TILEGX_IMM8_Y0_TLS_ADD 120	/* Y0 pipe "addi" for TLS GD/IE */
++#define R_TILEGX_IMM8_Y1_TLS_ADD 121	/* Y1 pipe "addi" for TLS GD/IE */
++
++#define R_TILEGX_GNU_VTINHERIT	128	/* GNU C++ vtable hierarchy */
++#define R_TILEGX_GNU_VTENTRY	129	/* GNU C++ vtable member usage */
++
++#define R_TILEGX_NUM		130
++
++#endif	/* elf.h */
+--- a/scripts/mod/mk_elfconfig.c
++++ b/scripts/mod/mk_elfconfig.c
+@@ -2,7 +2,11 @@
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
++#ifndef __APPLE__
+ #include <elf.h>
++#else
++#include "elf.h"
++#endif
+ 
+ int
+ main(int argc, char **argv)
+--- a/scripts/mod/modpost.h
++++ b/scripts/mod/modpost.h
+@@ -9,7 +9,11 @@
+ #include <sys/mman.h>
+ #include <fcntl.h>
+ #include <unistd.h>
++#if !(defined(__APPLE__) || defined(__CYGWIN__))
+ #include <elf.h>
++#else
++#include "elf.h"
++#endif
+ 
+ #include "list.h"
+ #include "elfconfig.h"
diff --git a/target/linux/generic/hack-6.6/211-darwin-uuid-typedef-clash.patch b/target/linux/generic/hack-6.6/211-darwin-uuid-typedef-clash.patch
new file mode 100644
index 00000000000000..66f1c3453c5e3f
--- /dev/null
+++ b/target/linux/generic/hack-6.6/211-darwin-uuid-typedef-clash.patch
@@ -0,0 +1,22 @@
+From e44fc2af1ddc452b6659d08c16973d65c73b7d0a Mon Sep 17 00:00:00 2001
+From: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
+Date: Wed, 5 Feb 2020 18:36:43 +0000
+Subject: [PATCH] file2alias: build on macos
+
+Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
+---
+ scripts/mod/file2alias.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/scripts/mod/file2alias.c
++++ b/scripts/mod/file2alias.c
+@@ -40,6 +40,9 @@ typedef struct {
+ 	__u8 b[16];
+ } guid_t;
+ 
++#ifdef __APPLE__
++#define uuid_t compat_uuid_t
++#endif
+ typedef struct {
+ 	__u8 b[16];
+ } uuid_t;
diff --git a/target/linux/generic/hack-6.6/212-tools_portability.patch b/target/linux/generic/hack-6.6/212-tools_portability.patch
new file mode 100644
index 00000000000000..3e74a76f43b55c
--- /dev/null
+++ b/target/linux/generic/hack-6.6/212-tools_portability.patch
@@ -0,0 +1,83 @@
+From 48232d3d931c95953ce2ddfe7da7bb164aef6a73 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 17:03:16 +0200
+Subject: fix portability of some includes files in tools/ used on the host
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ tools/include/tools/be_byteshift.h |  4 ++++
+ tools/include/tools/le_byteshift.h |  4 ++++
+ tools/include/tools/linux_types.h  | 22 ++++++++++++++++++++++
+ 3 files changed, 30 insertions(+)
+ create mode 100644 tools/include/tools/linux_types.h
+
+--- a/tools/include/tools/be_byteshift.h
++++ b/tools/include/tools/be_byteshift.h
+@@ -2,6 +2,10 @@
+ #ifndef _TOOLS_BE_BYTESHIFT_H
+ #define _TOOLS_BE_BYTESHIFT_H
+ 
++#ifndef __linux__
++#include "linux_types.h"
++#endif
++
+ #include <stdint.h>
+ 
+ static inline uint16_t __get_unaligned_be16(const uint8_t *p)
+--- a/tools/include/tools/le_byteshift.h
++++ b/tools/include/tools/le_byteshift.h
+@@ -2,6 +2,10 @@
+ #ifndef _TOOLS_LE_BYTESHIFT_H
+ #define _TOOLS_LE_BYTESHIFT_H
+ 
++#ifndef __linux__
++#include "linux_types.h"
++#endif
++
+ #include <stdint.h>
+ 
+ static inline uint16_t __get_unaligned_le16(const uint8_t *p)
+--- /dev/null
++++ b/tools/include/tools/linux_types.h
+@@ -0,0 +1,26 @@
++#ifndef __LINUX_TYPES_H
++#define __LINUX_TYPES_H
++
++#include <stdint.h>
++
++typedef int8_t __s8;
++typedef uint8_t __u8;
++typedef uint8_t __be8;
++typedef uint8_t __le8;
++
++typedef int16_t __s16;
++typedef uint16_t __u16;
++typedef uint16_t __be16;
++typedef uint16_t __le16;
++
++typedef int32_t __s32;
++typedef uint32_t __u32;
++typedef uint32_t __be32;
++typedef uint32_t __le32;
++
++typedef int64_t __s64;
++typedef uint64_t __u64;
++typedef uint64_t __be64;
++typedef uint64_t __le64;
++
++#endif
+--- a/tools/include/linux/types.h
++++ b/tools/include/linux/types.h
+@@ -10,8 +10,12 @@
+ #define __SANE_USERSPACE_TYPES__	/* For PPC64, to get LL64 types */
+ #endif
+ 
++#ifndef __linux__
++#include <tools/linux_types.h>
++#else
+ #include <asm/types.h>
+ #include <asm/posix_types.h>
++#endif
+ 
+ struct page;
+ struct kmem_cache;
diff --git a/target/linux/generic/hack-6.6/214-spidev_h_portability.patch b/target/linux/generic/hack-6.6/214-spidev_h_portability.patch
new file mode 100644
index 00000000000000..db754a29033c06
--- /dev/null
+++ b/target/linux/generic/hack-6.6/214-spidev_h_portability.patch
@@ -0,0 +1,24 @@
+From be9be95ff10e16a5b4ad36f903978d0cc5747024 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 17:04:08 +0200
+Subject: kernel: fix linux/spi/spidev.h portability issues with musl
+
+Felix will try to get this define included into musl
+
+lede-commit: 795e7cf60de19e7a076a46874fab7bb88b43bbff
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/uapi/linux/spi/spidev.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/include/uapi/linux/spi/spidev.h
++++ b/include/uapi/linux/spi/spidev.h
+@@ -93,7 +93,7 @@ struct spi_ioc_transfer {
+ 
+ /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
+ #define SPI_MSGSIZE(N) \
+-	((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
++	((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \
+ 		? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
+ #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
+ 
diff --git a/target/linux/generic/hack-6.6/220-arm-gc_sections.patch b/target/linux/generic/hack-6.6/220-arm-gc_sections.patch
new file mode 100644
index 00000000000000..d366fdbdc9371d
--- /dev/null
+++ b/target/linux/generic/hack-6.6/220-arm-gc_sections.patch
@@ -0,0 +1,123 @@
+From e3d8676f5722b7622685581e06e8f53e6138e3ab Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 15 Jul 2017 23:42:36 +0200
+Subject: use -ffunction-sections, -fdata-sections and --gc-sections
+
+In combination with kernel symbol export stripping this significantly reduces
+the kernel image size. Used on both ARM and MIPS architectures.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -127,6 +127,7 @@ config ARM
+ 	select HAVE_VIRT_CPU_ACCOUNTING_GEN
+ 	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
+ 	select IRQ_FORCED_THREADING
++	select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
+ 	select LOCK_MM_AND_FIND_VMA
+ 	select MODULES_USE_ELF_REL
+ 	select NEED_DMA_MAP_STATE
+--- a/arch/arm/boot/compressed/Makefile
++++ b/arch/arm/boot/compressed/Makefile
+@@ -92,6 +92,7 @@ endif
+ ifeq ($(CONFIG_USE_OF),y)
+ OBJS	+= $(libfdt_objs) fdt_check_mem_start.o
+ endif
++KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL))
+ 
+ OBJS	+= lib1funcs.o ashldi3.o bswapsdi2.o
+ 
+--- a/arch/arm/kernel/vmlinux.lds.S
++++ b/arch/arm/kernel/vmlinux.lds.S
+@@ -74,7 +74,7 @@ SECTIONS
+ 	. = ALIGN(4);
+ 	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
+ 		__start___ex_table = .;
+-		ARM_MMU_KEEP(*(__ex_table))
++		KEEP(*(__ex_table))
+ 		__stop___ex_table = .;
+ 	}
+ 
+@@ -99,24 +99,24 @@ SECTIONS
+ 	}
+ 	.init.arch.info : {
+ 		__arch_info_begin = .;
+-		*(.arch.info.init)
++		KEEP(*(.arch.info.init))
+ 		__arch_info_end = .;
+ 	}
+ 	.init.tagtable : {
+ 		__tagtable_begin = .;
+-		*(.taglist.init)
++		KEEP(*(.taglist.init))
+ 		__tagtable_end = .;
+ 	}
+ #ifdef CONFIG_SMP_ON_UP
+ 	.init.smpalt : {
+ 		__smpalt_begin = .;
+-		*(.alt.smp.init)
++		KEEP(*(.alt.smp.init))
+ 		__smpalt_end = .;
+ 	}
+ #endif
+ 	.init.pv_table : {
+ 		__pv_table_begin = .;
+-		*(.pv_table)
++		KEEP(*(.pv_table))
+ 		__pv_table_end = .;
+ 	}
+ 
+--- a/arch/arm/include/asm/vmlinux.lds.h
++++ b/arch/arm/include/asm/vmlinux.lds.h
+@@ -42,13 +42,13 @@
+ #define PROC_INFO							\
+ 		. = ALIGN(4);						\
+ 		__proc_info_begin = .;					\
+-		*(.proc.info.init)					\
++		KEEP(*(.proc.info.init))				\
+ 		__proc_info_end = .;
+ 
+ #define IDMAP_TEXT							\
+ 		ALIGN_FUNCTION();					\
+ 		__idmap_text_start = .;					\
+-		*(.idmap.text)						\
++		KEEP(*(.idmap.text))					\
+ 		__idmap_text_end = .;					\
+ 
+ #define ARM_DISCARD							\
+@@ -108,12 +108,12 @@
+ 	. = ALIGN(8);							\
+ 	.ARM.unwind_idx : {						\
+ 		__start_unwind_idx = .;					\
+-		*(.ARM.exidx*)						\
++		KEEP(*(.ARM.exidx*))					\
+ 		__stop_unwind_idx = .;					\
+ 	}								\
+ 	.ARM.unwind_tab : {						\
+ 		__start_unwind_tab = .;					\
+-		*(.ARM.extab*)						\
++		KEEP(*(.ARM.extab*))					\
+ 		__stop_unwind_tab = .;					\
+ 	}
+ 
+@@ -125,7 +125,7 @@
+ 	__vectors_lma = .;						\
+ 	OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) {		\
+ 		.vectors {						\
+-			*(.vectors)					\
++			KEEP(*(.vectors))				\
+ 		}							\
+ 		.vectors.bhb.loop8 {					\
+ 			*(.vectors.bhb.loop8)				\
+@@ -143,7 +143,7 @@
+ 									\
+ 	__stubs_lma = .;						\
+ 	.stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) {		\
+-		*(.stubs)						\
++		KEEP(*(.stubs))						\
+ 	}								\
+ 	ARM_LMA(__stubs, .stubs);					\
+ 	. = __stubs_lma + SIZEOF(.stubs);				\
diff --git a/target/linux/generic/hack-6.6/230-openwrt_lzma_options.patch b/target/linux/generic/hack-6.6/230-openwrt_lzma_options.patch
new file mode 100644
index 00000000000000..f9c1f3dfe0c5e3
--- /dev/null
+++ b/target/linux/generic/hack-6.6/230-openwrt_lzma_options.patch
@@ -0,0 +1,34 @@
+From b3d00b452467f621317953d9e4c6f9ae8dcfd271 Mon Sep 17 00:00:00 2001
+From: Imre Kaloz <kaloz@openwrt.org>
+Date: Fri, 7 Jul 2017 17:06:55 +0200
+Subject: use the openwrt lzma options for now
+
+lede-commit: 548de949f392049420a6a1feeef118b30ab8ea8c
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+---
+ lib/decompress.c              |  1 +
+ scripts/Makefile.lib          |  2 +-
+ usr/gen_initramfs_list.sh | 10 +++++-----
+ 3 files changed, 7 insertions(+), 6 deletions(-)
+
+--- a/lib/decompress.c
++++ b/lib/decompress.c
+@@ -53,6 +53,7 @@ static const struct compress_format comp
+ 	{ {0x1f, 0x9e}, "gzip", gunzip },
+ 	{ {0x42, 0x5a}, "bzip2", bunzip2 },
+ 	{ {0x5d, 0x00}, "lzma", unlzma },
++	{ {0x6d, 0x00}, "lzma-openwrt", unlzma },
+ 	{ {0xfd, 0x37}, "xz", unxz },
+ 	{ {0x89, 0x4c}, "lzo", unlzo },
+ 	{ {0x02, 0x21}, "lz4", unlz4 },
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -456,7 +456,7 @@ quiet_cmd_bzip2_with_size = BZIP2   $@
+ # ---------------------------------------------------------------------------
+ 
+ quiet_cmd_lzma = LZMA    $@
+-      cmd_lzma = cat $(real-prereqs) | $(LZMA) -9 > $@
++      cmd_lzma = { cat $(real-prereqs) | $(LZMA) e -d20 -lc1 -lp2 -pb2 -eos -si -so; $(size_append); } > $@
+ 
+ quiet_cmd_lzma_with_size = LZMA    $@
+       cmd_lzma_with_size = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@
diff --git a/target/linux/generic/hack-6.6/249-udp-tunnel-selection.patch b/target/linux/generic/hack-6.6/249-udp-tunnel-selection.patch
new file mode 100644
index 00000000000000..2c74298dfe99a2
--- /dev/null
+++ b/target/linux/generic/hack-6.6/249-udp-tunnel-selection.patch
@@ -0,0 +1,11 @@
+--- a/net/ipv4/Kconfig
++++ b/net/ipv4/Kconfig
+@@ -315,7 +315,7 @@ config NET_IPVTI
+ 	  on top.
+ 
+ config NET_UDP_TUNNEL
+-	tristate
++	tristate "IP: UDP tunneling support"
+ 	select NET_IP_TUNNEL
+ 	default n
+ 
diff --git a/target/linux/generic/hack-6.6/250-netfilter_depends.patch b/target/linux/generic/hack-6.6/250-netfilter_depends.patch
new file mode 100644
index 00000000000000..43faa9959edf4a
--- /dev/null
+++ b/target/linux/generic/hack-6.6/250-netfilter_depends.patch
@@ -0,0 +1,27 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: hack: net: remove bogus netfilter dependencies
+
+lede-commit: 589d2a377dee27d206fc3725325309cf649e4df6
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ net/netfilter/Kconfig | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/net/netfilter/Kconfig
++++ b/net/netfilter/Kconfig
+@@ -259,7 +259,6 @@ config NF_CONNTRACK_FTP
+ 
+ config NF_CONNTRACK_H323
+ 	tristate "H.323 protocol support"
+-	depends on IPV6 || IPV6=n
+ 	depends on NETFILTER_ADVANCED
+ 	help
+ 	  H.323 is a VoIP signalling protocol from ITU-T. As one of the most
+@@ -1120,7 +1119,6 @@ config NETFILTER_XT_TARGET_SECMARK
+ 
+ config NETFILTER_XT_TARGET_TCPMSS
+ 	tristate '"TCPMSS" target support'
+-	depends on IPV6 || IPV6=n
+ 	default m if NETFILTER_ADVANCED=n
+ 	help
+ 	  This option adds a `TCPMSS' target, which allows you to alter the
diff --git a/target/linux/generic/hack-6.6/251-kconfig.patch b/target/linux/generic/hack-6.6/251-kconfig.patch
new file mode 100644
index 00000000000000..404f9087d879fb
--- /dev/null
+++ b/target/linux/generic/hack-6.6/251-kconfig.patch
@@ -0,0 +1,199 @@
+From da3c50704f14132f4adf80d48e9a4cd5d46e54c9 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 7 Jul 2017 17:09:21 +0200
+Subject: kconfig: owrt specifc dependencies
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ crypto/Kconfig        | 10 +++++-----
+ drivers/bcma/Kconfig  |  1 +
+ drivers/ssb/Kconfig   |  3 ++-
+ lib/Kconfig           |  8 ++++----
+ net/netfilter/Kconfig |  2 +-
+ net/wireless/Kconfig  | 17 ++++++++++-------
+ sound/core/Kconfig    |  4 ++--
+ 7 files changed, 25 insertions(+), 20 deletions(-)
+
+--- a/crypto/Kconfig
++++ b/crypto/Kconfig
+@@ -55,7 +55,7 @@ config CRYPTO_FIPS_VERSION
+ 	  By default the KERNELRELEASE value is used.
+ 
+ config CRYPTO_ALGAPI
+-	tristate
++	tristate "ALGAPI"
+ 	select CRYPTO_ALGAPI2
+ 	help
+ 	  This option provides the API for cryptographic algorithms.
+@@ -64,7 +64,7 @@ config CRYPTO_ALGAPI2
+ 	tristate
+ 
+ config CRYPTO_AEAD
+-	tristate
++	tristate "AEAD"
+ 	select CRYPTO_AEAD2
+ 	select CRYPTO_ALGAPI
+ 
+@@ -82,7 +82,7 @@ config CRYPTO_SIG2
+ 	select CRYPTO_ALGAPI2
+ 
+ config CRYPTO_SKCIPHER
+-	tristate
++	tristate "SKCIPHER"
+ 	select CRYPTO_SKCIPHER2
+ 	select CRYPTO_ALGAPI
+ 
+@@ -91,7 +91,7 @@ config CRYPTO_SKCIPHER2
+ 	select CRYPTO_ALGAPI2
+ 
+ config CRYPTO_HASH
+-	tristate
++	tristate "HASH"
+ 	select CRYPTO_HASH2
+ 	select CRYPTO_ALGAPI
+ 
+@@ -100,7 +100,7 @@ config CRYPTO_HASH2
+ 	select CRYPTO_ALGAPI2
+ 
+ config CRYPTO_RNG
+-	tristate
++	tristate "RNG"
+ 	select CRYPTO_RNG2
+ 	select CRYPTO_ALGAPI
+ 
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -16,6 +16,7 @@ if BCMA
+ # Support for Block-I/O. SELECT this from the driver that needs it.
+ config BCMA_BLOCKIO
+ 	bool
++	default y
+ 
+ config BCMA_HOST_PCI_POSSIBLE
+ 	bool
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -29,6 +29,7 @@ config SSB_SPROM
+ config SSB_BLOCKIO
+ 	bool
+ 	depends on SSB
++	default y
+ 
+ config SSB_PCIHOST_POSSIBLE
+ 	bool
+@@ -49,7 +50,7 @@ config SSB_PCIHOST
+ config SSB_B43_PCI_BRIDGE
+ 	bool
+ 	depends on SSB_PCIHOST
+-	default n
++	default y
+ 
+ config SSB_PCMCIAHOST_POSSIBLE
+ 	bool
+--- a/lib/Kconfig
++++ b/lib/Kconfig
+@@ -460,16 +460,16 @@ config BCH_CONST_T
+ # Textsearch support is select'ed if needed
+ #
+ config TEXTSEARCH
+-	bool
++	bool "Textsearch support"
+ 
+ config TEXTSEARCH_KMP
+-	tristate
++	tristate "Textsearch KMP"
+ 
+ config TEXTSEARCH_BM
+-	tristate
++	tristate "Textsearch BM"
+ 
+ config TEXTSEARCH_FSM
+-	tristate
++	tristate "Textsearch FSM"
+ 
+ config BTREE
+ 	bool
+--- a/net/netfilter/Kconfig
++++ b/net/netfilter/Kconfig
+@@ -22,7 +22,7 @@ config NETFILTER_SKIP_EGRESS
+ 	def_bool NETFILTER_EGRESS && (NET_CLS_ACT || IFB)
+ 
+ config NETFILTER_NETLINK
+-	tristate
++	tristate "Netfilter NFNETLINK interface"
+ 
+ config NETFILTER_FAMILY_BRIDGE
+ 	bool
+--- a/net/wireless/Kconfig
++++ b/net/wireless/Kconfig
+@@ -1,6 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ config WIRELESS_EXT
+-	bool
++	bool "Wireless extensions"
+ 
+ config WEXT_CORE
+ 	def_bool y
+@@ -12,10 +12,10 @@ config WEXT_PROC
+ 	depends on WEXT_CORE
+ 
+ config WEXT_SPY
+-	bool
++	bool "WEXT_SPY"
+ 
+ config WEXT_PRIV
+-	bool
++	bool "WEXT_PRIV"
+ 
+ config CFG80211
+ 	tristate "cfg80211 - wireless configuration API"
+@@ -204,7 +204,7 @@ config CFG80211_WEXT_EXPORT
+ endif # CFG80211
+ 
+ config LIB80211
+-	tristate
++	tristate "LIB80211"
+ 	default n
+ 	help
+ 	  This options enables a library of common routines used
+@@ -213,17 +213,17 @@ config LIB80211
+ 	  Drivers should select this themselves if needed.
+ 
+ config LIB80211_CRYPT_WEP
+-	tristate
++	tristate "LIB80211_CRYPT_WEP"
+ 	select CRYPTO_LIB_ARC4
+ 
+ config LIB80211_CRYPT_CCMP
+-	tristate
++	tristate "LIB80211_CRYPT_CCMP"
+ 	select CRYPTO
+ 	select CRYPTO_AES
+ 	select CRYPTO_CCM
+ 
+ config LIB80211_CRYPT_TKIP
+-	tristate
++	tristate "LIB80211_CRYPT_TKIP"
+ 	select CRYPTO_LIB_ARC4
+ 
+ config LIB80211_DEBUG
+--- a/sound/core/Kconfig
++++ b/sound/core/Kconfig
+@@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM
+ 	tristate
+ 
+ config SND_HWDEP
+-	tristate
++	tristate "Sound hardware support"
+ 
+ config SND_SEQ_DEVICE
+ 	tristate
+@@ -40,7 +40,7 @@ config SND_UMP_LEGACY_RAWMIDI
+ 	  The device contains 16 substreams corresponding to UMP groups.
+ 
+ config SND_COMPRESS_OFFLOAD
+-	tristate
++	tristate "Compression offloading support"
+ 
+ config SND_JACK
+ 	bool
diff --git a/target/linux/generic/hack-6.6/252-SATA_PMP.patch b/target/linux/generic/hack-6.6/252-SATA_PMP.patch
new file mode 100644
index 00000000000000..6502d1d6ed79d8
--- /dev/null
+++ b/target/linux/generic/hack-6.6/252-SATA_PMP.patch
@@ -0,0 +1,23 @@
+From 8c817e33be829c7249c2cfd59ff48ad5fac6a31d Mon Sep 17 00:00:00 2001
+From: Sungbo Eo <mans0n@gorani.run>
+Date: Fri, 7 Jul 2017 17:09:21 +0200
+Subject: [PATCH] kconfig: solidify SATA_PMP config
+
+SATA_PMP option in kernel config file disappears for every kernel_oldconfig refresh.
+To prevent this, SATA_HOST is now selected automatically when SATA_PMP is enabled.
+This patch can be dropped if SATA_MV is ever re-added into the config.
+---
+ drivers/ata/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -112,7 +112,7 @@ config SATA_ZPODD
+ 
+ config SATA_PMP
+ 	bool "SATA Port Multiplier support"
+-	depends on SATA_HOST
++	select SATA_HOST
+ 	default y
+ 	help
+ 	  This option adds support for SATA Port Multipliers
diff --git a/target/linux/generic/hack-6.6/253-ksmbd-config.patch b/target/linux/generic/hack-6.6/253-ksmbd-config.patch
new file mode 100644
index 00000000000000..80c77ddd027e48
--- /dev/null
+++ b/target/linux/generic/hack-6.6/253-ksmbd-config.patch
@@ -0,0 +1,22 @@
+--- a/init/Kconfig
++++ b/init/Kconfig
+@@ -1970,7 +1970,7 @@ config PADATA
+ 	bool
+ 
+ config ASN1
+-	tristate
++	tristate "ASN1"
+ 	help
+ 	  Build a simple ASN.1 grammar compiler that produces a bytecode output
+ 	  that can be interpreted by the ASN.1 stream decoder and used to
+--- a/lib/Kconfig
++++ b/lib/Kconfig
+@@ -647,7 +647,7 @@ config LIBFDT
+ 	bool
+ 
+ config OID_REGISTRY
+-	tristate
++	tristate "OID"
+ 	help
+ 	  Enable fast lookup object identifier registry.
+ 
diff --git a/target/linux/generic/hack-6.6/259-regmap_dynamic.patch b/target/linux/generic/hack-6.6/259-regmap_dynamic.patch
new file mode 100644
index 00000000000000..48678e348b82ef
--- /dev/null
+++ b/target/linux/generic/hack-6.6/259-regmap_dynamic.patch
@@ -0,0 +1,159 @@
+From 811d9e2268a62b830cfe93cd8bc929afcb8b198b Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 15 Jul 2017 21:12:38 +0200
+Subject: kernel: move regmap bloat out of the kernel image if it is only being used in modules
+
+lede-commit: 96f39119815028073583e4fca3a9c5fe9141e998
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/base/regmap/Kconfig  | 15 ++++++++++-----
+ drivers/base/regmap/Makefile | 12 ++++++++----
+ drivers/base/regmap/regmap.c |  3 +++
+ include/linux/regmap.h       |  2 +-
+ 4 files changed, 22 insertions(+), 10 deletions(-)
+
+--- a/drivers/base/regmap/Kconfig
++++ b/drivers/base/regmap/Kconfig
+@@ -5,9 +5,9 @@
+ 
+ config REGMAP
+ 	bool
+-	default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SOUNDWIRE || REGMAP_SOUNDWIRE_MBQ || REGMAP_SCCB || REGMAP_I3C || REGMAP_SPI_AVMM || REGMAP_MDIO || REGMAP_FSI)
+ 	select IRQ_DOMAIN if REGMAP_IRQ
+ 	select MDIO_BUS if REGMAP_MDIO
++	tristate
+ 	help
+ 	  Enable support for the Register Map (regmap) access API.
+ 
+@@ -19,8 +19,9 @@ config REGMAP
+ 
+ config REGMAP_KUNIT
+ 	tristate "KUnit tests for regmap"
+-	depends on KUNIT && REGMAP
++	depends on KUNIT
+ 	default KUNIT_ALL_TESTS
++	select REGMAP
+ 	select REGMAP_RAM
+ 
+ config REGMAP_BUILD
+@@ -34,60 +35,76 @@ config REGMAP_BUILD
+ 	  normally enabled.
+ 
+ config REGMAP_AC97
++	select REGMAP
+ 	tristate
+ 
+ config REGMAP_I2C
++	select REGMAP
+ 	tristate
+ 	depends on I2C
+ 
+ config REGMAP_SLIMBUS
++	select REGMAP
+ 	tristate
+ 	depends on SLIMBUS
+ 
+ config REGMAP_SPI
++	select REGMAP
+ 	tristate
+ 	depends on SPI
+ 
+ config REGMAP_SPMI
++	select REGMAP
+ 	tristate
+ 	depends on SPMI
+ 
+ config REGMAP_W1
++	select REGMAP
+ 	tristate
+ 	depends on W1
+ 
+ config REGMAP_MDIO
++	select REGMAP
+ 	tristate
+ 
+ config REGMAP_MMIO
++	select REGMAP
+ 	tristate
+ 
+ config REGMAP_IRQ
++	select REGMAP
+ 	bool
+ 
+ config REGMAP_RAM
++	select REGMAP
+ 	tristate
+ 
+ config REGMAP_SOUNDWIRE
++	select REGMAP
+ 	tristate
+ 	depends on SOUNDWIRE
+ 
+ config REGMAP_SOUNDWIRE_MBQ
++	select REGMAP
+ 	tristate
+ 	depends on SOUNDWIRE
+ 
+ config REGMAP_SCCB
++	select REGMAP
+ 	tristate
+ 	depends on I2C
+ 
+ config REGMAP_I3C
++	select REGMAP
+ 	tristate
+ 	depends on I3C
+ 
+ config REGMAP_SPI_AVMM
++	select REGMAP
+ 	tristate
+ 	depends on SPI
+ 
+ config REGMAP_FSI
++	select REGMAP
+ 	tristate
+ 	depends on FSI
+--- a/drivers/base/regmap/Makefile
++++ b/drivers/base/regmap/Makefile
+@@ -2,9 +2,11 @@
+ # For include/trace/define_trace.h to include trace.h
+ CFLAGS_regmap.o := -I$(src)
+ 
+-obj-$(CONFIG_REGMAP) += regmap.o regcache.o
+-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-flat.o regcache-maple.o
+-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
++regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-flat.o regcache-maple.o
++ifdef CONFIG_DEBUG_FS
++regmap-core-objs += regmap-debugfs.o
++endif
++obj-$(CONFIG_REGMAP) += regmap-core.o
+ obj-$(CONFIG_REGMAP_KUNIT) += regmap-kunit.o
+ obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o
+ obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
+--- a/drivers/base/regmap/regmap.c
++++ b/drivers/base/regmap/regmap.c
+@@ -9,6 +9,7 @@
+ #include <linux/device.h>
+ #include <linux/slab.h>
+ #include <linux/export.h>
++#include <linux/module.h>
+ #include <linux/mutex.h>
+ #include <linux/err.h>
+ #include <linux/property.h>
+@@ -3433,3 +3434,5 @@ static int __init regmap_initcall(void)
+ 	return 0;
+ }
+ postcore_initcall(regmap_initcall);
++
++MODULE_LICENSE("GPL");
+--- a/include/linux/regmap.h
++++ b/include/linux/regmap.h
+@@ -197,7 +197,7 @@ struct reg_sequence {
+ 	__ret ?: __tmp; \
+ })
+ 
+-#ifdef CONFIG_REGMAP
++#if IS_REACHABLE(CONFIG_REGMAP)
+ 
+ enum regmap_endian {
+ 	/* Unspecified -> 0 -> Backwards compatible default */
diff --git a/target/linux/generic/hack-6.6/261-lib-arc4-unhide.patch b/target/linux/generic/hack-6.6/261-lib-arc4-unhide.patch
new file mode 100644
index 00000000000000..58f89ab8e3ed2c
--- /dev/null
+++ b/target/linux/generic/hack-6.6/261-lib-arc4-unhide.patch
@@ -0,0 +1,15 @@
+This makes it possible to select CONFIG_CRYPTO_LIB_ARC4 directly. We 
+need this to be able to compile this into the kernel and make use of it 
+from backports.
+
+--- a/lib/crypto/Kconfig
++++ b/lib/crypto/Kconfig
+@@ -15,7 +15,7 @@ config CRYPTO_LIB_AESGCM
+ 	select CRYPTO_LIB_UTILS
+ 
+ config CRYPTO_LIB_ARC4
+-	tristate
++	tristate "ARC4 cipher library"
+ 
+ config CRYPTO_LIB_GF128MUL
+ 	tristate
diff --git a/target/linux/generic/hack-6.6/280-rfkill-stubs.patch b/target/linux/generic/hack-6.6/280-rfkill-stubs.patch
new file mode 100644
index 00000000000000..7a650d132eb3ae
--- /dev/null
+++ b/target/linux/generic/hack-6.6/280-rfkill-stubs.patch
@@ -0,0 +1,84 @@
+From 236c1acdfef5958010ac9814a9872e0a46fd78ee Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 7 Jul 2017 17:13:44 +0200
+Subject: rfkill: add fake rfkill support
+
+allow building of modules depending on RFKILL even if RFKILL is not enabled.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ include/linux/rfkill.h |  2 +-
+ net/Makefile           |  2 +-
+ net/rfkill/Kconfig     | 14 +++++++++-----
+ net/rfkill/Makefile    |  2 +-
+ 4 files changed, 12 insertions(+), 8 deletions(-)
+
+--- a/include/linux/rfkill.h
++++ b/include/linux/rfkill.h
+@@ -64,7 +64,7 @@ struct rfkill_ops {
+ 	int	(*set_block)(void *data, bool blocked);
+ };
+ 
+-#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
++#if defined(CONFIG_RFKILL_FULL) || defined(CONFIG_RFKILL_FULL_MODULE)
+ /**
+  * rfkill_alloc - Allocate rfkill structure
+  * @name: name of the struct -- the string is not copied internally
+--- a/net/Makefile
++++ b/net/Makefile
+@@ -52,7 +52,7 @@ obj-$(CONFIG_TIPC)		+= tipc/
+ obj-$(CONFIG_NETLABEL)		+= netlabel/
+ obj-$(CONFIG_IUCV)		+= iucv/
+ obj-$(CONFIG_SMC)		+= smc/
+-obj-$(CONFIG_RFKILL)		+= rfkill/
++obj-$(CONFIG_RFKILL_FULL)	+= rfkill/
+ obj-$(CONFIG_NET_9P)		+= 9p/
+ obj-$(CONFIG_CAIF)		+= caif/
+ obj-$(CONFIG_DCB)		+= dcb/
+--- a/net/rfkill/Kconfig
++++ b/net/rfkill/Kconfig
+@@ -2,7 +2,11 @@
+ #
+ # RF switch subsystem configuration
+ #
+-menuconfig RFKILL
++config RFKILL
++	bool
++	default y
++
++menuconfig RFKILL_FULL
+ 	tristate "RF switch subsystem support"
+ 	help
+ 	  Say Y here if you want to have control over RF switches
+@@ -14,19 +18,19 @@ menuconfig RFKILL
+ # LED trigger support
+ config RFKILL_LEDS
+ 	bool
+-	depends on RFKILL
++	depends on RFKILL_FULL
+ 	depends on LEDS_TRIGGERS = y || RFKILL = LEDS_TRIGGERS
+ 	default y
+ 
+ config RFKILL_INPUT
+ 	bool "RF switch input support" if EXPERT
+-	depends on RFKILL
++	depends on RFKILL_FULL
+ 	depends on INPUT = y || RFKILL = INPUT
+ 	default y if !EXPERT
+ 
+ config RFKILL_GPIO
+ 	tristate "GPIO RFKILL driver"
+-	depends on RFKILL
++	depends on RFKILL_FULL
+ 	depends on GPIOLIB || COMPILE_TEST
+ 	default n
+ 	help
+--- a/net/rfkill/Makefile
++++ b/net/rfkill/Makefile
+@@ -5,5 +5,5 @@
+ 
+ rfkill-y			+= core.o
+ rfkill-$(CONFIG_RFKILL_INPUT)	+= input.o
+-obj-$(CONFIG_RFKILL)		+= rfkill.o
++obj-$(CONFIG_RFKILL_FULL)	+= rfkill.o
+ obj-$(CONFIG_RFKILL_GPIO)	+= rfkill-gpio.o
diff --git a/target/linux/generic/hack-6.6/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch b/target/linux/generic/hack-6.6/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch
new file mode 100644
index 00000000000000..f21f200136f00b
--- /dev/null
+++ b/target/linux/generic/hack-6.6/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch
@@ -0,0 +1,64 @@
+From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
+Date: Fri, 7 Jun 2013 18:35:22 -0500
+Subject: MIPS: r4k_cache: use more efficient cache blast
+
+Optimize the compiler output for larger cache blast cases that are
+common for DMA-based networking.
+
+Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -286,14 +286,46 @@ static inline void prot##extra##blast_##
+ 						    unsigned long end)	\
+ {									\
+ 	unsigned long lsize = cpu_##desc##_line_size();			\
++	unsigned long lsize_2 = lsize * 2;				\
++	unsigned long lsize_3 = lsize * 3;				\
++	unsigned long lsize_4 = lsize * 4;				\
++	unsigned long lsize_5 = lsize * 5;				\
++	unsigned long lsize_6 = lsize * 6;				\
++	unsigned long lsize_7 = lsize * 7;				\
++	unsigned long lsize_8 = lsize * 8;				\
+ 	unsigned long addr = start & ~(lsize - 1);			\
+-	unsigned long aend = (end - 1) & ~(lsize - 1);			\
++	unsigned long aend = (end + lsize - 1) & ~(lsize - 1);		\
++	int lines = (aend - addr) / lsize;				\
+ 									\
+-	while (1) {							\
++	while (lines >= 8) {						\
++		prot##cache_op(hitop, addr);				\
++		prot##cache_op(hitop, addr + lsize);			\
++		prot##cache_op(hitop, addr + lsize_2);			\
++		prot##cache_op(hitop, addr + lsize_3);			\
++		prot##cache_op(hitop, addr + lsize_4);			\
++		prot##cache_op(hitop, addr + lsize_5);			\
++		prot##cache_op(hitop, addr + lsize_6);			\
++		prot##cache_op(hitop, addr + lsize_7);			\
++		addr += lsize_8;					\
++		lines -= 8;						\
++	}								\
++									\
++	if (lines & 0x4) {						\
++		prot##cache_op(hitop, addr);				\
++		prot##cache_op(hitop, addr + lsize);			\
++		prot##cache_op(hitop, addr + lsize_2);			\
++		prot##cache_op(hitop, addr + lsize_3);			\
++		addr += lsize_4;					\
++	}								\
++									\
++	if (lines & 0x2) {						\
++		prot##cache_op(hitop, addr);				\
++		prot##cache_op(hitop, addr + lsize);			\
++		addr += lsize_2;					\
++	}								\
++									\
++	if (lines & 0x1) {						\
+ 		prot##cache_op(hitop, addr);				\
+-		if (addr == aend)					\
+-			break;						\
+-		addr += lsize;						\
+ 	}								\
+ }
+ 
diff --git a/target/linux/generic/hack-6.6/301-mips_image_cmdline_hack.patch b/target/linux/generic/hack-6.6/301-mips_image_cmdline_hack.patch
new file mode 100644
index 00000000000000..5a5cc21808c2fa
--- /dev/null
+++ b/target/linux/generic/hack-6.6/301-mips_image_cmdline_hack.patch
@@ -0,0 +1,38 @@
+From: John Crispin <john@phrozen.org>
+Subject: hack: kernel: add generic image_cmdline hack to MIPS targets
+
+lede-commit: d59f5b3a987a48508257a0ddbaeadc7909f9f976
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/Kconfig       | 4 ++++
+ arch/mips/kernel/head.S | 6 ++++++
+ 2 files changed, 10 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1090,6 +1090,10 @@ config MIPS_MSC
+ config SYNC_R4K
+ 	bool
+ 
++config IMAGE_CMDLINE_HACK
++	bool "OpenWrt specific image command line hack"
++	default n
++
+ config NO_IOPORT_MAP
+ 	def_bool n
+ 
+--- a/arch/mips/kernel/head.S
++++ b/arch/mips/kernel/head.S
+@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry)
+ 	j	kernel_entry
+ #endif /* CONFIG_BOOT_RAW */
+ 
++#ifdef CONFIG_IMAGE_CMDLINE_HACK
++	.ascii	"CMDLINE:"
++EXPORT(__image_cmdline)
++	.fill	0x400
++#endif /* CONFIG_IMAGE_CMDLINE_HACK */
++
+ 	__REF
+ 
+ NESTED(kernel_entry, 16, sp)			# kernel entry point
diff --git a/target/linux/generic/hack-6.6/410-block-fit-partition-parser.patch b/target/linux/generic/hack-6.6/410-block-fit-partition-parser.patch
new file mode 100644
index 00000000000000..1fe63454ebd79a
--- /dev/null
+++ b/target/linux/generic/hack-6.6/410-block-fit-partition-parser.patch
@@ -0,0 +1,196 @@
+--- a/block/blk.h
++++ b/block/blk.h
+@@ -423,6 +423,8 @@ void blk_free_ext_minor(unsigned int min
+ #define ADDPART_FLAG_NONE	0
+ #define ADDPART_FLAG_RAID	1
+ #define ADDPART_FLAG_WHOLEDISK	2
++#define ADDPART_FLAG_READONLY	4
++#define ADDPART_FLAG_ROOTDEV	8
+ int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
+ 		sector_t length);
+ int bdev_del_partition(struct gendisk *disk, int partno);
+--- a/block/partitions/Kconfig
++++ b/block/partitions/Kconfig
+@@ -103,6 +103,13 @@ config ATARI_PARTITION
+ 	  Say Y here if you would like to use hard disks under Linux which
+ 	  were partitioned under the Atari OS.
+ 
++config FIT_PARTITION
++	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
++	default n
++	help
++	  Say Y here if your system needs to mount the filesystem part of
++	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
++
+ config IBM_PARTITION
+ 	bool "IBM disk label and partition support"
+ 	depends on PARTITION_ADVANCED && S390
+--- a/block/partitions/Makefile
++++ b/block/partitions/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
+ obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
+ obj-$(CONFIG_ATARI_PARTITION) += atari.o
+ obj-$(CONFIG_AIX_PARTITION) += aix.o
++obj-$(CONFIG_FIT_PARTITION) += fit.o
+ obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
+ obj-$(CONFIG_MAC_PARTITION) += mac.o
+ obj-$(CONFIG_LDM_PARTITION) += ldm.o
+--- a/block/partitions/check.h
++++ b/block/partitions/check.h
+@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
+ int atari_partition(struct parsed_partitions *state);
+ int cmdline_partition(struct parsed_partitions *state);
+ int efi_partition(struct parsed_partitions *state);
++int fit_partition(struct parsed_partitions *state);
+ int ibm_partition(struct parsed_partitions *);
+ int karma_partition(struct parsed_partitions *state);
+ int ldm_partition(struct parsed_partitions *state);
+@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
+ int sun_partition(struct parsed_partitions *state);
+ int sysv68_partition(struct parsed_partitions *state);
+ int ultrix_partition(struct parsed_partitions *state);
++
++int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
+--- a/block/partitions/core.c
++++ b/block/partitions/core.c
+@@ -10,6 +10,10 @@
+ #include <linux/ctype.h>
+ #include <linux/vmalloc.h>
+ #include <linux/raid/detect.h>
++#ifdef CONFIG_FIT_PARTITION
++#include <linux/root_dev.h>
++#endif
++
+ #include "check.h"
+ 
+ static int (*const check_part[])(struct parsed_partitions *) = {
+@@ -46,6 +50,9 @@ static int (*const check_part[])(struct
+ #ifdef CONFIG_EFI_PARTITION
+ 	efi_partition,		/* this must come before msdos */
+ #endif
++#ifdef CONFIG_FIT_PARTITION
++	fit_partition,
++#endif
+ #ifdef CONFIG_SGI_PARTITION
+ 	sgi_partition,
+ #endif
+@@ -392,6 +399,11 @@ static struct block_device *add_partitio
+ 			goto out_del;
+ 	}
+ 
++#ifdef CONFIG_FIT_PARTITION
++	if (flags & ADDPART_FLAG_READONLY)
++		bdev->bd_read_only = true;
++#endif
++
+ 	/* everything is up and running, commence */
+ 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
+ 	if (err)
+@@ -579,6 +591,11 @@ static bool blk_add_partition(struct gen
+ 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
+ 		md_autodetect_dev(part->bd_dev);
+ 
++#ifdef CONFIG_FIT_PARTITION
++	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
++		ROOT_DEV = part->bd_dev;
++#endif
++
+ 	return true;
+ }
+ 
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -412,6 +412,9 @@ int ubiblock_create(struct ubi_volume_in
+ 	}
+ 	gd->flags |= GENHD_FL_NO_PART;
+ 	gd->private_data = dev;
++#ifdef CONFIG_FIT_PARTITION
++	gd->flags |= GENHD_FL_EXT_DEVT;
++#endif
+ 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
+ 	set_capacity(gd, disk_capacity);
+ 	dev->gd = gd;
+--- a/drivers/mtd/mtd_blkdevs.c
++++ b/drivers/mtd/mtd_blkdevs.c
+@@ -346,6 +346,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
+ 	gd->first_minor = (new->devnum) << tr->part_bits;
+ 	gd->minors = 1 << tr->part_bits;
+ 	gd->fops = &mtd_block_ops;
++#ifdef CONFIG_FIT_PARTITION
++	gd->flags |= GENHD_FL_EXT_DEVT;
++#endif
+ 
+ 	if (tr->part_bits) {
+ 		if (new->devnum < 26)
+--- a/block/partitions/efi.c
++++ b/block/partitions/efi.c
+@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
+ 	gpt_entry *ptes = NULL;
+ 	u32 i;
+ 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
++#ifdef CONFIG_FIT_PARTITION
++	u32 extra_slot = 64;
++#endif
+ 
+ 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
+ 		kfree(gpt);
+@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
+ 				ARRAY_SIZE(ptes[i].partition_name));
+ 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
+ 		state->parts[i + 1].has_info = true;
++#ifdef CONFIG_FIT_PARTITION
++		/* If this is a U-Boot FIT volume it may have subpartitions */
++		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
++			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
++#endif
+ 	}
+ 	kfree(ptes);
+ 	kfree(gpt);
+--- a/block/partitions/efi.h
++++ b/block/partitions/efi.h
+@@ -51,6 +51,9 @@
+ #define PARTITION_LINUX_LVM_GUID \
+     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
+               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
++#define PARTITION_LINUX_FIT_GUID \
++    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
++              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
+ 
+ typedef struct _gpt_header {
+ 	__le64 signature;
+--- a/block/partitions/msdos.c
++++ b/block/partitions/msdos.c
+@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
+ #endif /* CONFIG_MINIX_SUBPARTITION */
+ }
+ 
++static void parse_fit_mbr(struct parsed_partitions *state,
++			  sector_t offset, sector_t size, int origin)
++{
++#ifdef CONFIG_FIT_PARTITION
++	u32 extra_slot = 64;
++	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
++#endif /* CONFIG_FIT_PARTITION */
++}
++
+ static struct {
+ 	unsigned char id;
+ 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
+@@ -575,6 +584,7 @@ static struct {
+ 	{UNIXWARE_PARTITION, parse_unixware},
+ 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
+ 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
++	{FIT_PARTITION, parse_fit_mbr},
+ 	{0, NULL},
+ };
+ 
+--- a/include/linux/msdos_partition.h
++++ b/include/linux/msdos_partition.h
+@@ -31,6 +31,7 @@ enum msdos_sys_ind {
+ 	LINUX_LVM_PARTITION = 0x8e,
+ 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
+ 
++	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
+ 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
+ 	NEW_SOLARIS_X86_PARTITION = 0xbf,
+ 
diff --git a/target/linux/generic/hack-6.6/420-mtd-set-rootfs-to-be-root-dev.patch b/target/linux/generic/hack-6.6/420-mtd-set-rootfs-to-be-root-dev.patch
new file mode 100644
index 00000000000000..eb81b144a641e5
--- /dev/null
+++ b/target/linux/generic/hack-6.6/420-mtd-set-rootfs-to-be-root-dev.patch
@@ -0,0 +1,39 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: kernel/3.1[02]: move MTD root device setup code to mtdcore
+
+The current code only allows to automatically set
+root device on MTD partitions. Move the code to MTD
+core to allow to use it with all MTD devices.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/mtd/mtdcore.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/mtd/mtdcore.c
++++ b/drivers/mtd/mtdcore.c
+@@ -28,6 +28,7 @@
+ #include <linux/reboot.h>
+ #include <linux/leds.h>
+ #include <linux/debugfs.h>
++#include <linux/root_dev.h>
+ #include <linux/nvmem-provider.h>
+ #include <linux/root_dev.h>
+ 
+@@ -782,6 +783,16 @@ int add_mtd_device(struct mtd_info *mtd)
+ 	   of this try_ nonsense, and no bitching about it
+ 	   either. :) */
+ 	__module_get(THIS_MODULE);
++
++	if (!strcmp(mtd->name, "rootfs") &&
++	    IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&
++	    ROOT_DEV == 0) {
++		unsigned int index = mtd->index;
++		pr_notice("mtd: device %d (%s) set to be root filesystem\n",
++			  mtd->index, mtd->name);
++		ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, index);
++	}
++
+ 	return 0;
+ 
+ fail_nvmem_add:
diff --git a/target/linux/generic/hack-6.6/421-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch b/target/linux/generic/hack-6.6/421-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch
new file mode 100644
index 00000000000000..965a331a1905bb
--- /dev/null
+++ b/target/linux/generic/hack-6.6/421-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch
@@ -0,0 +1,120 @@
+From 6fa9e3678eb002246df1280322b6a024853950a5 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 11 Oct 2021 00:53:14 +0200
+Subject: [PATCH] drivers: mtd: parsers: add nvmem support to cmdlinepart
+
+Assuming cmdlinepart is only one level deep partition scheme and that
+static partition are also defined in DTS, we can assign an of_node for
+partition declared from bootargs. cmdlinepart have priority than
+fiexed-partition parser so in this specific case the parser doesn't
+assign an of_node. Fix this by searching a defined of_node using a
+similar fixed_partition parser and if a partition is found with the same
+label, check that it has the same offset and size and return the DT
+of_node to correctly use NVMEM cells.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/mtd/parsers/cmdlinepart.c | 71 +++++++++++++++++++++++++++++++
+ 1 file changed, 71 insertions(+)
+
+--- a/drivers/mtd/parsers/cmdlinepart.c
++++ b/drivers/mtd/parsers/cmdlinepart.c
+@@ -43,6 +43,7 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/module.h>
+ #include <linux/err.h>
++#include <linux/of.h>
+ 
+ /* debug macro */
+ #if 0
+@@ -323,6 +324,68 @@ static int mtdpart_setup_real(char *s)
+ 	return 0;
+ }
+ 
++static int search_fixed_partition(struct mtd_info *master,
++				  struct mtd_partition *target_part,
++				  struct mtd_partition *fixed_part)
++{
++	struct device_node *mtd_node;
++	struct device_node *ofpart_node;
++	struct device_node *pp;
++	struct mtd_partition part;
++	const char *partname;
++
++	mtd_node = mtd_get_of_node(master);
++	if (!mtd_node)
++		return -EINVAL;
++
++	ofpart_node = of_get_child_by_name(mtd_node, "partitions");
++
++	for_each_child_of_node(ofpart_node,  pp) {
++		const __be32 *reg;
++		int len;
++		int a_cells, s_cells;
++
++		reg = of_get_property(pp, "reg", &len);
++		if (!reg) {
++			pr_debug("%s: ofpart partition %pOF (%pOF) missing reg property.\n",
++				 master->name, pp,
++				 mtd_node);
++			continue;
++		}
++
++		a_cells = of_n_addr_cells(pp);
++		s_cells = of_n_size_cells(pp);
++		if (len / 4 != a_cells + s_cells) {
++			pr_debug("%s: ofpart partition %pOF (%pOF) error parsing reg property.\n",
++				 master->name, pp,
++				 mtd_node);
++			continue;
++		}
++
++		part.offset = of_read_number(reg, a_cells);
++		part.size = of_read_number(reg + a_cells, s_cells);
++		part.of_node = pp;
++
++		partname = of_get_property(pp, "label", &len);
++		if (!partname)
++			partname = of_get_property(pp, "name", &len);
++		part.name = partname;
++
++		if (!strncmp(target_part->name, part.name, len)) {
++			if (part.offset != target_part->offset)
++				return -EINVAL;
++
++			if (part.size != target_part->size)
++				return -EINVAL;
++
++			memcpy(fixed_part, &part, sizeof(struct mtd_partition));
++			return 0;
++		}
++	}
++
++	return -EINVAL;
++}
++
+ /*
+  * Main function to be called from the MTD mapping driver/device to
+  * obtain the partitioning information. At this point the command line
+@@ -338,6 +401,7 @@ static int parse_cmdline_partitions(stru
+ 	int i, err;
+ 	struct cmdline_mtd_partition *part;
+ 	const char *mtd_id = master->name;
++	struct mtd_partition fixed_part;
+ 
+ 	/* parse command line */
+ 	if (!cmdline_parsed) {
+@@ -382,6 +446,13 @@ static int parse_cmdline_partitions(stru
+ 				sizeof(*part->parts) * (part->num_parts - i));
+ 			i--;
+ 		}
++
++		err = search_fixed_partition(master, &part->parts[i], &fixed_part);
++		if (!err) {
++			part->parts[i].of_node = fixed_part.of_node;
++			pr_info("Found partition defined in DT for %s. Assigning OF node to support nvmem.",
++				part->parts[i].name);
++		}
+ 	}
+ 
+ 	*pparts = kmemdup(part->parts, sizeof(*part->parts) * part->num_parts,
diff --git a/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch b/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch
new file mode 100644
index 00000000000000..f782e07cd6c6b1
--- /dev/null
+++ b/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch
@@ -0,0 +1,23 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -61,6 +61,10 @@ config MTD_NAND_ECC_MEDIATEK
+ 	help
+ 	  This enables support for the hardware ECC engine from Mediatek.
+ 
++config MTD_NAND_MTK_BMT
++	bool "Support MediaTek NAND Bad-block Management Table"
++	default n
++
+ endmenu
+ 
+ endmenu
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -3,6 +3,7 @@
+ nandcore-objs := core.o bbt.o
+ obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
+ obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
++obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
+ 
+ obj-y	+= onenand/
+ obj-y	+= raw/
diff --git a/target/linux/generic/hack-6.6/531-debloat_lzma.patch b/target/linux/generic/hack-6.6/531-debloat_lzma.patch
new file mode 100644
index 00000000000000..2f70eee3e9040b
--- /dev/null
+++ b/target/linux/generic/hack-6.6/531-debloat_lzma.patch
@@ -0,0 +1,1040 @@
+From 3fd297761ac246c54d7723c57fca95c112b99465 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 15 Jul 2017 21:15:44 +0200
+Subject: lzma: de-bloat the lzma library used by jffs2
+
+lede-commit: 3fd1dd08fbcbb78b34efefd32c3032e5c99108d6
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/linux/lzma/LzFind.h  |  17 ---
+ include/linux/lzma/LzmaDec.h | 101 ---------------
+ include/linux/lzma/LzmaEnc.h |  20 ---
+ lib/lzma/LzFind.c            | 287 ++++---------------------------------------
+ lib/lzma/LzmaDec.c           |  86 +------------
+ lib/lzma/LzmaEnc.c           | 172 ++------------------------
+ 6 files changed, 42 insertions(+), 641 deletions(-)
+
+--- a/include/linux/lzma/LzFind.h
++++ b/include/linux/lzma/LzFind.h
+@@ -55,11 +55,6 @@ typedef struct _CMatchFinder
+ 
+ #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)
+ 
+-int MatchFinder_NeedMove(CMatchFinder *p);
+-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);
+-void MatchFinder_MoveBlock(CMatchFinder *p);
+-void MatchFinder_ReadIfRequired(CMatchFinder *p);
+-
+ void MatchFinder_Construct(CMatchFinder *p);
+ 
+ /* Conditions:
+@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p,
+     UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,
+     ISzAlloc *alloc);
+ void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);
+-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);
+-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);
+-
+-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son,
+-    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue,
+-    UInt32 *distances, UInt32 maxLen);
+ 
+ /*
+ Conditions:
+@@ -102,12 +91,6 @@ typedef struct _IMatchFinder
+ 
+ void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);
+ 
+-void MatchFinder_Init(CMatchFinder *p);
+-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);
+-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);
+-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);
+-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);
+-
+ #ifdef __cplusplus
+ }
+ #endif
+--- a/include/linux/lzma/LzmaDec.h
++++ b/include/linux/lzma/LzmaDec.h
+@@ -31,14 +31,6 @@ typedef struct _CLzmaProps
+   UInt32 dicSize;
+ } CLzmaProps;
+ 
+-/* LzmaProps_Decode - decodes properties
+-Returns:
+-  SZ_OK
+-  SZ_ERROR_UNSUPPORTED - Unsupported properties
+-*/
+-
+-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);
+-
+ 
+ /* ---------- LZMA Decoder state ---------- */
+ 
+@@ -70,8 +62,6 @@ typedef struct
+ 
+ #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }
+ 
+-void LzmaDec_Init(CLzmaDec *p);
+-
+ /* There are two types of LZMA streams:
+      0) Stream with end mark. That end mark adds about 6 bytes to compressed size.
+      1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */
+@@ -108,97 +98,6 @@ typedef enum
+ 
+ /* ELzmaStatus is used only as output value for function call */
+ 
+-
+-/* ---------- Interfaces ---------- */
+-
+-/* There are 3 levels of interfaces:
+-     1) Dictionary Interface
+-     2) Buffer Interface
+-     3) One Call Interface
+-   You can select any of these interfaces, but don't mix functions from different
+-   groups for same object. */
+-
+-
+-/* There are two variants to allocate state for Dictionary Interface:
+-     1) LzmaDec_Allocate / LzmaDec_Free
+-     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs
+-   You can use variant 2, if you set dictionary buffer manually.
+-   For Buffer Interface you must always use variant 1.
+-
+-LzmaDec_Allocate* can return:
+-  SZ_OK
+-  SZ_ERROR_MEM         - Memory allocation error
+-  SZ_ERROR_UNSUPPORTED - Unsupported properties
+-*/
+-
+-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);
+-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);
+-
+-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);
+-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);
+-
+-/* ---------- Dictionary Interface ---------- */
+-
+-/* You can use it, if you want to eliminate the overhead for data copying from
+-   dictionary to some other external buffer.
+-   You must work with CLzmaDec variables directly in this interface.
+-
+-   STEPS:
+-     LzmaDec_Constr()
+-     LzmaDec_Allocate()
+-     for (each new stream)
+-     {
+-       LzmaDec_Init()
+-       while (it needs more decompression)
+-       {
+-         LzmaDec_DecodeToDic()
+-         use data from CLzmaDec::dic and update CLzmaDec::dicPos
+-       }
+-     }
+-     LzmaDec_Free()
+-*/
+-
+-/* LzmaDec_DecodeToDic
+-
+-   The decoding to internal dictionary buffer (CLzmaDec::dic).
+-   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!
+-
+-finishMode:
+-  It has meaning only if the decoding reaches output limit (dicLimit).
+-  LZMA_FINISH_ANY - Decode just dicLimit bytes.
+-  LZMA_FINISH_END - Stream must be finished after dicLimit.
+-
+-Returns:
+-  SZ_OK
+-    status:
+-      LZMA_STATUS_FINISHED_WITH_MARK
+-      LZMA_STATUS_NOT_FINISHED
+-      LZMA_STATUS_NEEDS_MORE_INPUT
+-      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK
+-  SZ_ERROR_DATA - Data error
+-*/
+-
+-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,
+-    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);
+-
+-
+-/* ---------- Buffer Interface ---------- */
+-
+-/* It's zlib-like interface.
+-   See LzmaDec_DecodeToDic description for information about STEPS and return results,
+-   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need
+-   to work with CLzmaDec variables manually.
+-
+-finishMode:
+-  It has meaning only if the decoding reaches output limit (*destLen).
+-  LZMA_FINISH_ANY - Decode just destLen bytes.
+-  LZMA_FINISH_END - Stream must be finished after (*destLen).
+-*/
+-
+-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,
+-    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);
+-
+-
+ /* ---------- One Call Interface ---------- */
+ 
+ /* LzmaDecode
+--- a/include/linux/lzma/LzmaEnc.h
++++ b/include/linux/lzma/LzmaEnc.h
+@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps
+ } CLzmaEncProps;
+ 
+ void LzmaEncProps_Init(CLzmaEncProps *p);
+-void LzmaEncProps_Normalize(CLzmaEncProps *p);
+-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);
+-
+ 
+ /* ---------- CLzmaEncHandle Interface ---------- */
+ 
+@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc *
+ void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);
+ SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);
+ SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);
+-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream,
+-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
+ SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
+     int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
+ 
+-/* ---------- One Call Interface ---------- */
+-
+-/* LzmaEncode
+-Return code:
+-  SZ_OK               - OK
+-  SZ_ERROR_MEM        - Memory allocation error
+-  SZ_ERROR_PARAM      - Incorrect paramater
+-  SZ_ERROR_OUTPUT_EOF - output buffer overflow
+-  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)
+-*/
+-
+-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
+-    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,
+-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
+-
+ #ifdef __cplusplus
+ }
+ #endif
+--- a/lib/lzma/LzFind.c
++++ b/lib/lzma/LzFind.c
+@@ -14,9 +14,15 @@
+ 
+ #define kStartMaxLen 3
+ 
++#if 0
++#define DIRECT_INPUT	p->directInput
++#else
++#define DIRECT_INPUT	1
++#endif
++
+ static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)
+ {
+-  if (!p->directInput)
++  if (!DIRECT_INPUT)
+   {
+     alloc->Free(alloc, p->bufferBase);
+     p->bufferBase = 0;
+@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder
+ static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)
+ {
+   UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;
+-  if (p->directInput)
++  if (DIRECT_INPUT)
+   {
+     p->blockSize = blockSize;
+     return 1;
+@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde
+   return (p->bufferBase != 0);
+ }
+ 
+-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }
+-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }
++static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }
++static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }
+ 
+-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }
++static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }
+ 
+-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)
++static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)
+ {
+   p->posLimit -= subValue;
+   p->pos -= subValue;
+@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch
+ {
+   if (p->streamEndWasReached || p->result != SZ_OK)
+     return;
+-  if (p->directInput)
++  if (DIRECT_INPUT)
+   {
+     UInt32 curSize = 0xFFFFFFFF - p->streamPos;
+     if (curSize > p->directInputRem)
+@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch
+   }
+ }
+ 
+-void MatchFinder_MoveBlock(CMatchFinder *p)
++static void MatchFinder_MoveBlock(CMatchFinder *p)
+ {
+   memmove(p->bufferBase,
+     p->buffer - p->keepSizeBefore,
+@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder
+   p->buffer = p->bufferBase + p->keepSizeBefore;
+ }
+ 
+-int MatchFinder_NeedMove(CMatchFinder *p)
++static int MatchFinder_NeedMove(CMatchFinder *p)
+ {
+-  if (p->directInput)
++  if (DIRECT_INPUT)
+     return 0;
+   /* if (p->streamEndWasReached) return 0; */
+   return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);
+ }
+ 
+-void MatchFinder_ReadIfRequired(CMatchFinder *p)
+-{
+-  if (p->streamEndWasReached)
+-    return;
+-  if (p->keepSizeAfter >= p->streamPos - p->pos)
+-    MatchFinder_ReadBlock(p);
+-}
+-
+ static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)
+ {
+   if (MatchFinder_NeedMove(p))
+@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch
+   p->posLimit = p->pos + limit;
+ }
+ 
+-void MatchFinder_Init(CMatchFinder *p)
++static void MatchFinder_Init(CMatchFinder *p)
+ {
+   UInt32 i;
+   for (i = 0; i < p->hashSizeSum; i++)
+@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM
+   return (p->pos - p->historySize - 1) & kNormalizeMask;
+ }
+ 
+-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)
++static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)
+ {
+   UInt32 i;
+   for (i = 0; i < numItems; i++)
+@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat
+   MatchFinder_SetLimits(p);
+ }
+ 
+-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,
+-    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,
+-    UInt32 *distances, UInt32 maxLen)
+-{
+-  son[_cyclicBufferPos] = curMatch;
+-  for (;;)
+-  {
+-    UInt32 delta = pos - curMatch;
+-    if (cutValue-- == 0 || delta >= _cyclicBufferSize)
+-      return distances;
+-    {
+-      const Byte *pb = cur - delta;
+-      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];
+-      if (pb[maxLen] == cur[maxLen] && *pb == *cur)
+-      {
+-        UInt32 len = 0;
+-        while (++len != lenLimit)
+-          if (pb[len] != cur[len])
+-            break;
+-        if (maxLen < len)
+-        {
+-          *distances++ = maxLen = len;
+-          *distances++ = delta - 1;
+-          if (len == lenLimit)
+-            return distances;
+-        }
+-      }
+-    }
+-  }
+-}
+-
+-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,
++static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,
+     UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,
+     UInt32 *distances, UInt32 maxLen)
+ {
+@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi
+   p->buffer++; \
+   if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);
+ 
+-#define MOVE_POS_RET MOVE_POS return offset;
+-
+ static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }
+ 
++#define MOVE_POS_RET MatchFinder_MovePos(p); return offset;
++
+ #define GET_MATCHES_HEADER2(minLen, ret_op) \
+   UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \
+   lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \
+@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi
+   distances + offset, maxLen) - distances); MOVE_POS_RET;
+ 
+ #define SKIP_FOOTER \
+-  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;
+-
+-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+-{
+-  UInt32 offset;
+-  GET_MATCHES_HEADER(2)
+-  HASH2_CALC;
+-  curMatch = p->hash[hashValue];
+-  p->hash[hashValue] = p->pos;
+-  offset = 0;
+-  GET_MATCHES_FOOTER(offset, 1)
+-}
+-
+-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+-{
+-  UInt32 offset;
+-  GET_MATCHES_HEADER(3)
+-  HASH_ZIP_CALC;
+-  curMatch = p->hash[hashValue];
+-  p->hash[hashValue] = p->pos;
+-  offset = 0;
+-  GET_MATCHES_FOOTER(offset, 2)
+-}
+-
+-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+-{
+-  UInt32 hash2Value, delta2, maxLen, offset;
+-  GET_MATCHES_HEADER(3)
+-
+-  HASH3_CALC;
+-
+-  delta2 = p->pos - p->hash[hash2Value];
+-  curMatch = p->hash[kFix3HashSize + hashValue];
+-
+-  p->hash[hash2Value] =
+-  p->hash[kFix3HashSize + hashValue] = p->pos;
+-
+-
+-  maxLen = 2;
+-  offset = 0;
+-  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)
+-  {
+-    for (; maxLen != lenLimit; maxLen++)
+-      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])
+-        break;
+-    distances[0] = maxLen;
+-    distances[1] = delta2 - 1;
+-    offset = 2;
+-    if (maxLen == lenLimit)
+-    {
+-      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));
+-      MOVE_POS_RET;
+-    }
+-  }
+-  GET_MATCHES_FOOTER(offset, maxLen)
+-}
++  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p);
+ 
+ static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+ {
+@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches
+   GET_MATCHES_FOOTER(offset, maxLen)
+ }
+ 
+-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+-{
+-  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;
+-  GET_MATCHES_HEADER(4)
+-
+-  HASH4_CALC;
+-
+-  delta2 = p->pos - p->hash[                hash2Value];
+-  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];
+-  curMatch = p->hash[kFix4HashSize + hashValue];
+-
+-  p->hash[                hash2Value] =
+-  p->hash[kFix3HashSize + hash3Value] =
+-  p->hash[kFix4HashSize + hashValue] = p->pos;
+-
+-  maxLen = 1;
+-  offset = 0;
+-  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)
+-  {
+-    distances[0] = maxLen = 2;
+-    distances[1] = delta2 - 1;
+-    offset = 2;
+-  }
+-  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)
+-  {
+-    maxLen = 3;
+-    distances[offset + 1] = delta3 - 1;
+-    offset += 2;
+-    delta2 = delta3;
+-  }
+-  if (offset != 0)
+-  {
+-    for (; maxLen != lenLimit; maxLen++)
+-      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])
+-        break;
+-    distances[offset - 2] = maxLen;
+-    if (maxLen == lenLimit)
+-    {
+-      p->son[p->cyclicBufferPos] = curMatch;
+-      MOVE_POS_RET;
+-    }
+-  }
+-  if (maxLen < 3)
+-    maxLen = 3;
+-  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),
+-    distances + offset, maxLen) - (distances));
+-  MOVE_POS_RET
+-}
+-
+-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
+-{
+-  UInt32 offset;
+-  GET_MATCHES_HEADER(3)
+-  HASH_ZIP_CALC;
+-  curMatch = p->hash[hashValue];
+-  p->hash[hashValue] = p->pos;
+-  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),
+-    distances, 2) - (distances));
+-  MOVE_POS_RET
+-}
+-
+-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
+-{
+-  do
+-  {
+-    SKIP_HEADER(2)
+-    HASH2_CALC;
+-    curMatch = p->hash[hashValue];
+-    p->hash[hashValue] = p->pos;
+-    SKIP_FOOTER
+-  }
+-  while (--num != 0);
+-}
+-
+-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
+-{
+-  do
+-  {
+-    SKIP_HEADER(3)
+-    HASH_ZIP_CALC;
+-    curMatch = p->hash[hashValue];
+-    p->hash[hashValue] = p->pos;
+-    SKIP_FOOTER
+-  }
+-  while (--num != 0);
+-}
+-
+-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
+-{
+-  do
+-  {
+-    UInt32 hash2Value;
+-    SKIP_HEADER(3)
+-    HASH3_CALC;
+-    curMatch = p->hash[kFix3HashSize + hashValue];
+-    p->hash[hash2Value] =
+-    p->hash[kFix3HashSize + hashValue] = p->pos;
+-    SKIP_FOOTER
+-  }
+-  while (--num != 0);
+-}
+-
+ static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
+ {
+   do
+@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF
+   while (--num != 0);
+ }
+ 
+-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
+-{
+-  do
+-  {
+-    UInt32 hash2Value, hash3Value;
+-    SKIP_HEADER(4)
+-    HASH4_CALC;
+-    curMatch = p->hash[kFix4HashSize + hashValue];
+-    p->hash[                hash2Value] =
+-    p->hash[kFix3HashSize + hash3Value] =
+-    p->hash[kFix4HashSize + hashValue] = p->pos;
+-    p->son[p->cyclicBufferPos] = curMatch;
+-    MOVE_POS
+-  }
+-  while (--num != 0);
+-}
+-
+-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
+-{
+-  do
+-  {
+-    SKIP_HEADER(3)
+-    HASH_ZIP_CALC;
+-    curMatch = p->hash[hashValue];
+-    p->hash[hashValue] = p->pos;
+-    p->son[p->cyclicBufferPos] = curMatch;
+-    MOVE_POS
+-  }
+-  while (--num != 0);
+-}
+-
+ void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)
+ {
+   vTable->Init = (Mf_Init_Func)MatchFinder_Init;
+   vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;
+   vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;
+   vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;
+-  if (!p->btMode)
+-  {
+-    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;
+-    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;
+-  }
+-  else if (p->numHashBytes == 2)
+-  {
+-    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;
+-    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;
+-  }
+-  else if (p->numHashBytes == 3)
+-  {
+-    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;
+-    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;
+-  }
+-  else
+-  {
+-    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;
+-    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;
+-  }
++  vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;
++  vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;
+ }
+--- a/lib/lzma/LzmaDec.c
++++ b/lib/lzma/LzmaDec.c
+@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p,
+   p->needFlush = 0;
+ }
+ 
+-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)
++static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)
+ {
+   p->needFlush = 1;
+   p->remainLen = 0;
+@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p
+     p->needInitState = 1;
+ }
+ 
+-void LzmaDec_Init(CLzmaDec *p)
++static void LzmaDec_Init(CLzmaDec *p)
+ {
+   p->dicPos = 0;
+   LzmaDec_InitDicAndState(p, True, True);
+@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD
+   p->needInitState = 0;
+ }
+ 
+-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,
++static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,
+     ELzmaFinishMode finishMode, ELzmaStatus *status)
+ {
+   SizeT inSize = *srcLen;
+@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si
+   return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;
+ }
+ 
+-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)
+-{
+-  SizeT outSize = *destLen;
+-  SizeT inSize = *srcLen;
+-  *srcLen = *destLen = 0;
+-  for (;;)
+-  {
+-    SizeT inSizeCur = inSize, outSizeCur, dicPos;
+-    ELzmaFinishMode curFinishMode;
+-    SRes res;
+-    if (p->dicPos == p->dicBufSize)
+-      p->dicPos = 0;
+-    dicPos = p->dicPos;
+-    if (outSize > p->dicBufSize - dicPos)
+-    {
+-      outSizeCur = p->dicBufSize;
+-      curFinishMode = LZMA_FINISH_ANY;
+-    }
+-    else
+-    {
+-      outSizeCur = dicPos + outSize;
+-      curFinishMode = finishMode;
+-    }
+-
+-    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);
+-    src += inSizeCur;
+-    inSize -= inSizeCur;
+-    *srcLen += inSizeCur;
+-    outSizeCur = p->dicPos - dicPos;
+-    memcpy(dest, p->dic + dicPos, outSizeCur);
+-    dest += outSizeCur;
+-    outSize -= outSizeCur;
+-    *destLen += outSizeCur;
+-    if (res != 0)
+-      return res;
+-    if (outSizeCur == 0 || outSize == 0)
+-      return SZ_OK;
+-  }
+-}
+-
+-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)
++static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)
+ {
+   alloc->Free(alloc, p->probs);
+   p->probs = 0;
+ }
+ 
+-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)
+-{
+-  alloc->Free(alloc, p->dic);
+-  p->dic = 0;
+-}
+-
+-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)
+-{
+-  LzmaDec_FreeProbs(p, alloc);
+-  LzmaDec_FreeDict(p, alloc);
+-}
+-
+-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)
++static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)
+ {
+   UInt32 dicSize;
+   Byte d;
+@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma
+   return SZ_OK;
+ }
+ 
+-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
++static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
+ {
+   CLzmaProps propNew;
+   RINOK(LzmaProps_Decode(&propNew, props, propsSize));
+@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p,
+   p->prop = propNew;
+   return SZ_OK;
+ }
+-
+-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
+-{
+-  CLzmaProps propNew;
+-  SizeT dicBufSize;
+-  RINOK(LzmaProps_Decode(&propNew, props, propsSize));
+-  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));
+-  dicBufSize = propNew.dicSize;
+-  if (p->dic == 0 || dicBufSize != p->dicBufSize)
+-  {
+-    LzmaDec_FreeDict(p, alloc);
+-    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);
+-    if (p->dic == 0)
+-    {
+-      LzmaDec_FreeProbs(p, alloc);
+-      return SZ_ERROR_MEM;
+-    }
+-  }
+-  p->dicBufSize = dicBufSize;
+-  p->prop = propNew;
+-  return SZ_OK;
+-}
+ 
+ SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,
+     const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,
+--- a/lib/lzma/LzmaEnc.c
++++ b/lib/lzma/LzmaEnc.c
+@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p)
+   p->writeEndMark = 0;
+ }
+ 
+-void LzmaEncProps_Normalize(CLzmaEncProps *p)
++static void LzmaEncProps_Normalize(CLzmaEncProps *p)
+ {
+   int level = p->level;
+   if (level < 0) level = 5;
+@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp
+       #endif
+ }
+ 
+-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)
++static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)
+ {
+   CLzmaEncProps props = *props2;
+   LzmaEncProps_Normalize(&props);
+@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL
+ 
+ #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }
+ 
+-UInt32 GetPosSlot1(UInt32 pos)
++static UInt32 GetPosSlot1(UInt32 pos)
+ {
+   UInt32 res;
+   BSR2_RET(pos, res);
+@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos)
+ #define kNumLogBits (9 + (int)sizeof(size_t) / 2)
+ #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)
+ 
+-void LzmaEnc_FastPosInit(Byte *g_FastPos)
++static void LzmaEnc_FastPosInit(Byte *g_FastPos)
+ {
+   int c = 2, slotFast;
+   g_FastPos[0] = 0;
+@@ -339,58 +339,6 @@ typedef struct
+   CSaveState saveState;
+ } CLzmaEnc;
+ 
+-void LzmaEnc_SaveState(CLzmaEncHandle pp)
+-{
+-  CLzmaEnc *p = (CLzmaEnc *)pp;
+-  CSaveState *dest = &p->saveState;
+-  int i;
+-  dest->lenEnc = p->lenEnc;
+-  dest->repLenEnc = p->repLenEnc;
+-  dest->state = p->state;
+-
+-  for (i = 0; i < kNumStates; i++)
+-  {
+-    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));
+-    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));
+-  }
+-  for (i = 0; i < kNumLenToPosStates; i++)
+-    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));
+-  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));
+-  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));
+-  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));
+-  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));
+-  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));
+-  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));
+-  memcpy(dest->reps, p->reps, sizeof(p->reps));
+-  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));
+-}
+-
+-void LzmaEnc_RestoreState(CLzmaEncHandle pp)
+-{
+-  CLzmaEnc *dest = (CLzmaEnc *)pp;
+-  const CSaveState *p = &dest->saveState;
+-  int i;
+-  dest->lenEnc = p->lenEnc;
+-  dest->repLenEnc = p->repLenEnc;
+-  dest->state = p->state;
+-
+-  for (i = 0; i < kNumStates; i++)
+-  {
+-    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));
+-    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));
+-  }
+-  for (i = 0; i < kNumLenToPosStates; i++)
+-    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));
+-  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));
+-  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));
+-  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));
+-  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));
+-  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));
+-  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));
+-  memcpy(dest->reps, p->reps, sizeof(p->reps));
+-  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));
+-}
+-
+ SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)
+ {
+   CLzmaEnc *p = (CLzmaEnc *)pp;
+@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE
+   while (symbol < 0x10000);
+ }
+ 
+-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)
++static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)
+ {
+   UInt32 i;
+   for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))
+@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc
+   p->matchPriceCount = 0;
+ }
+ 
+-void LzmaEnc_Construct(CLzmaEnc *p)
++static void LzmaEnc_Construct(CLzmaEnc *p)
+ {
+   RangeEnc_Construct(&p->rc);
+   MatchFinder_Construct(&p->matchFinderBase);
+@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc *
+   return p;
+ }
+ 
+-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)
++static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)
+ {
+   alloc->Free(alloc, p->litProbs);
+   alloc->Free(alloc, p->saveState.litProbs);
+@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl
+   p->saveState.litProbs = 0;
+ }
+ 
+-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)
++static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)
+ {
+   #ifndef _7ZIP_ST
+   MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);
+@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U
+   return SZ_OK;
+ }
+ 
+-void LzmaEnc_Init(CLzmaEnc *p)
++static void LzmaEnc_Init(CLzmaEnc *p)
+ {
+   UInt32 i;
+   p->state = 0;
+@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p)
+   p->lpMask = (1 << p->lp) - 1;
+ }
+ 
+-void LzmaEnc_InitPrices(CLzmaEnc *p)
++static void LzmaEnc_InitPrices(CLzmaEnc *p)
+ {
+   if (!p->fastMode)
+   {
+@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn
+   return SZ_OK;
+ }
+ 
+-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream,
+-    ISzAlloc *alloc, ISzAlloc *allocBig)
+-{
+-  CLzmaEnc *p = (CLzmaEnc *)pp;
+-  p->matchFinderBase.stream = inStream;
+-  p->needInit = 1;
+-  p->rc.outStream = outStream;
+-  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);
+-}
+-
+-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp,
+-    ISeqInStream *inStream, UInt32 keepWindowSize,
+-    ISzAlloc *alloc, ISzAlloc *allocBig)
+-{
+-  CLzmaEnc *p = (CLzmaEnc *)pp;
+-  p->matchFinderBase.stream = inStream;
+-  p->needInit = 1;
+-  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);
+-}
+-
+ static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)
+ {
+   p->matchFinderBase.directInput = 1;
+@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc
+   p->matchFinderBase.directInputRem = srcLen;
+ }
+ 
+-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,
++static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,
+     UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)
+ {
+   CLzmaEnc *p = (CLzmaEnc *)pp;
+@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p
+   return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);
+ }
+ 
+-void LzmaEnc_Finish(CLzmaEncHandle pp)
++static void LzmaEnc_Finish(CLzmaEncHandle pp)
+ {
+   #ifndef _7ZIP_ST
+   CLzmaEnc *p = (CLzmaEnc *)pp;
+@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo
+   return size;
+ }
+ 
+-
+-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)
+-{
+-  const CLzmaEnc *p = (CLzmaEnc *)pp;
+-  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);
+-}
+-
+-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)
+-{
+-  const CLzmaEnc *p = (CLzmaEnc *)pp;
+-  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;
+-}
+-
+-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit,
+-    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)
+-{
+-  CLzmaEnc *p = (CLzmaEnc *)pp;
+-  UInt64 nowPos64;
+-  SRes res;
+-  CSeqOutStreamBuf outStream;
+-
+-  outStream.funcTable.Write = MyWrite;
+-  outStream.data = dest;
+-  outStream.rem = *destLen;
+-  outStream.overflow = False;
+-
+-  p->writeEndMark = False;
+-  p->finished = False;
+-  p->result = SZ_OK;
+-
+-  if (reInit)
+-    LzmaEnc_Init(p);
+-  LzmaEnc_InitPrices(p);
+-  nowPos64 = p->nowPos64;
+-  RangeEnc_Init(&p->rc);
+-  p->rc.outStream = &outStream.funcTable;
+-
+-  res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);
+-
+-  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);
+-  *destLen -= outStream.rem;
+-  if (outStream.overflow)
+-    return SZ_ERROR_OUTPUT_EOF;
+-
+-  return res;
+-}
+-
+ static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress)
+ {
+   SRes res = SZ_OK;
+@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p,
+   return res;
+ }
+ 
+-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,
+-    ISzAlloc *alloc, ISzAlloc *allocBig)
+-{
+-  RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig));
+-  return LzmaEnc_Encode2((CLzmaEnc *)pp, progress);
+-}
+-
+ SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)
+ {
+   CLzmaEnc *p = (CLzmaEnc *)pp;
+@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp
+     return SZ_ERROR_OUTPUT_EOF;
+   return res;
+ }
+-
+-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
+-    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,
+-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)
+-{
+-  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);
+-  SRes res;
+-  if (p == 0)
+-    return SZ_ERROR_MEM;
+-
+-  res = LzmaEnc_SetProps(p, props);
+-  if (res == SZ_OK)
+-  {
+-    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);
+-    if (res == SZ_OK)
+-      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,
+-          writeEndMark, progress, alloc, allocBig);
+-  }
+-
+-  LzmaEnc_Destroy(p, alloc, allocBig);
+-  return res;
+-}
diff --git a/target/linux/generic/hack-6.6/640-bridge-only-accept-EAP-locally.patch b/target/linux/generic/hack-6.6/640-bridge-only-accept-EAP-locally.patch
new file mode 100644
index 00000000000000..4b2f2cc87280ad
--- /dev/null
+++ b/target/linux/generic/hack-6.6/640-bridge-only-accept-EAP-locally.patch
@@ -0,0 +1,41 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 17:18:54 +0200
+Subject: bridge: only accept EAP locally
+
+When bridging, do not forward EAP frames to other ports, only deliver
+them locally, regardless of the state.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+[add disable_eap_hack sysfs attribute]
+Signed-off-by: Etienne Champetier <champetier.etienne@gmail.com>
+---
+
+--- a/net/bridge/br_input.c
++++ b/net/bridge/br_input.c
+@@ -150,10 +150,14 @@ int br_handle_frame_finish(struct net *n
+ 		}
+ 	}
+ 
++	BR_INPUT_SKB_CB(skb)->brdev = br->dev;
++
++	if (skb->protocol == htons(ETH_P_PAE) && !br->disable_eap_hack)
++		return br_pass_frame_up(skb);
++
+ 	if (state == BR_STATE_LEARNING)
+ 		goto drop;
+ 
+-	BR_INPUT_SKB_CB(skb)->brdev = br->dev;
+ 	BR_INPUT_SKB_CB(skb)->src_port_isolated = !!(p->flags & BR_ISOLATED);
+ 
+ 	if (IS_ENABLED(CONFIG_INET) &&
+--- a/net/bridge/br_private.h
++++ b/net/bridge/br_private.h
+@@ -506,6 +506,8 @@ struct net_bridge {
+ 	u16				group_fwd_mask;
+ 	u16				group_fwd_mask_required;
+ 
++	bool				disable_eap_hack;
++
+ 	/* STP */
+ 	bridge_id			designated_root;
+ 	bridge_id			bridge_id;
diff --git a/target/linux/generic/hack-6.6/645-netfilter-connmark-introduce-set-dscpmark.patch b/target/linux/generic/hack-6.6/645-netfilter-connmark-introduce-set-dscpmark.patch
new file mode 100644
index 00000000000000..fde2bb7d38ace5
--- /dev/null
+++ b/target/linux/generic/hack-6.6/645-netfilter-connmark-introduce-set-dscpmark.patch
@@ -0,0 +1,213 @@
+From eda40b8c8c82e0f2789d6bc8bf63846dce2e8f32 Mon Sep 17 00:00:00 2001
+From: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
+Date: Sat, 23 Mar 2019 09:29:49 +0000
+Subject: [PATCH] netfilter: connmark: introduce set-dscpmark
+
+set-dscpmark is a method of storing the DSCP of an ip packet into
+conntrack mark.  In combination with a suitable tc filter action
+(act_ctinfo) DSCP values are able to be stored in the mark on egress and
+restored on ingress across links that otherwise alter or bleach DSCP.
+
+This is useful for qdiscs such as CAKE which are able to shape according
+to policies based on DSCP.
+
+Ingress classification is traditionally a challenging task since
+iptables rules haven't yet run and tc filter/eBPF programs are pre-NAT
+lookups, hence are unable to see internal IPv4 addresses as used on the
+typical home masquerading gateway.
+
+x_tables CONNMARK set-dscpmark target solves the problem of storing the
+DSCP to the conntrack mark in a way suitable for the new act_ctinfo tc
+action to restore.
+
+The set-dscpmark option accepts 2 parameters, a 32bit 'dscpmask' and a
+32bit 'statemask'.  The dscp mask must be 6 contiguous bits and
+represents the area where the DSCP will be stored in the connmark.  The
+state mask is a minimum 1 bit length mask that must not overlap with the
+dscpmask.  It represents a flag which is set when the DSCP has been
+stored in the conntrack mark. This is useful to implement a 'one shot'
+iptables based classification where the 'complicated' iptables rules are
+only run once to classify the connection on initial (egress) packet and
+subsequent packets are all marked/restored with the same DSCP.  A state
+mask of zero disables the setting of a status bit/s.
+
+example syntax with a suitably modified iptables user space application:
+
+iptables -A QOS_MARK_eth0 -t mangle -j CONNMARK --set-dscpmark 0xfc000000/0x01000000
+
+Would store the DSCP in the top 6 bits of the 32bit mark field, and use
+the LSB of the top byte as the 'DSCP has been stored' marker.
+
+|----0xFC----conntrack mark----000000---|
+| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0|
+| DSCP       | unused | flag  |unused   |
+|-----------------------0x01---000000---|
+      ^                   ^
+      |                   |
+      ---|             Conditional flag
+         |             set this when dscp
+|-ip diffserv-|        stored in mark
+| 6 bits      |
+|-------------|
+
+an identically configured tc action to restore looks like:
+
+tc filter show dev eth0 ingress
+filter parent ffff: protocol all pref 10 u32 chain 0
+filter parent ffff: protocol all pref 10 u32 chain 0 fh 800: ht divisor 1
+filter parent ffff: protocol all pref 10 u32 chain 0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 1: not_in_hw
+  match 00000000/00000000 at 0
+	action order 1: ctinfo zone 0 pipe
+	 index 2 ref 1 bind 1 dscp 0xfc000000/0x1000000
+
+	action order 2: mirred (Egress Redirect to device ifb4eth0) stolen
+	index 1 ref 1 bind 1
+
+|----0xFC----conntrack mark----000000---|
+| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0|
+| DSCP       | unused | flag  |unused   |
+|-----------------------0x01---000000---|
+      |                   |
+      |                   |
+      ---|             Conditional flag
+         v             only restore if set
+|-ip diffserv-|
+| 6 bits      |
+|-------------|
+
+Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
+---
+ include/uapi/linux/netfilter/xt_connmark.h | 10 ++++
+ net/netfilter/xt_connmark.c                | 55 ++++++++++++++++++----
+ 2 files changed, 57 insertions(+), 8 deletions(-)
+
+--- a/include/uapi/linux/netfilter/xt_connmark.h
++++ b/include/uapi/linux/netfilter/xt_connmark.h
+@@ -15,6 +15,11 @@ enum {
+ };
+ 
+ enum {
++	XT_CONNMARK_VALUE =	(1 << 0),
++	XT_CONNMARK_DSCP = 	(1 << 1)
++};
++
++enum {
+ 	D_SHIFT_LEFT = 0,
+ 	D_SHIFT_RIGHT,
+ };
+@@ -29,6 +34,11 @@ struct xt_connmark_tginfo2 {
+ 	__u8 shift_dir, shift_bits, mode;
+ };
+ 
++struct xt_connmark_tginfo3 {
++	__u32 ctmark, ctmask, nfmask;
++	__u8 shift_dir, shift_bits, mode, func;
++};
++
+ struct xt_connmark_mtinfo1 {
+ 	__u32 mark, mask;
+ 	__u8 invert;
+--- a/net/netfilter/xt_connmark.c
++++ b/net/netfilter/xt_connmark.c
+@@ -24,13 +24,14 @@ MODULE_ALIAS("ipt_connmark");
+ MODULE_ALIAS("ip6t_connmark");
+ 
+ static unsigned int
+-connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo2 *info)
++connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo3 *info)
+ {
+ 	enum ip_conntrack_info ctinfo;
+ 	u_int32_t new_targetmark;
+ 	struct nf_conn *ct;
+ 	u_int32_t newmark;
+ 	u_int32_t oldmark;
++	u_int8_t dscp;
+ 
+ 	ct = nf_ct_get(skb, &ctinfo);
+ 	if (ct == NULL)
+@@ -39,12 +40,24 @@ connmark_tg_shift(struct sk_buff *skb, c
+ 	switch (info->mode) {
+ 	case XT_CONNMARK_SET:
+ 		oldmark = READ_ONCE(ct->mark);
+-		newmark = (oldmark & ~info->ctmask) ^ info->ctmark;
+-		if (info->shift_dir == D_SHIFT_RIGHT)
+-			newmark >>= info->shift_bits;
+-		else
+-			newmark <<= info->shift_bits;
++		newmark = ct->mark;
++		if (info->func & XT_CONNMARK_VALUE) {
++			newmark = (newmark & ~info->ctmask) ^ info->ctmark;
++			if (info->shift_dir == D_SHIFT_RIGHT)
++				newmark >>= info->shift_bits;
++			else
++				newmark <<= info->shift_bits;
++		} else if (info->func & XT_CONNMARK_DSCP) {
++			if (skb->protocol == htons(ETH_P_IP))
++				dscp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
++			else if (skb->protocol == htons(ETH_P_IPV6))
++				dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
++			else	/* protocol doesn't have diffserv */
++				break;
+ 
++			newmark = (newmark & ~info->ctmark) |
++				  (info->ctmask | (dscp << info->shift_bits));
++		}
+ 		if (READ_ONCE(ct->mark) != newmark) {
+ 			WRITE_ONCE(ct->mark, newmark);
+ 			nf_conntrack_event_cache(IPCT_MARK, ct);
+@@ -83,20 +96,36 @@ static unsigned int
+ connmark_tg(struct sk_buff *skb, const struct xt_action_param *par)
+ {
+ 	const struct xt_connmark_tginfo1 *info = par->targinfo;
+-	const struct xt_connmark_tginfo2 info2 = {
++	const struct xt_connmark_tginfo3 info3 = {
+ 		.ctmark	= info->ctmark,
+ 		.ctmask	= info->ctmask,
+ 		.nfmask	= info->nfmask,
+ 		.mode	= info->mode,
++		.func	= XT_CONNMARK_VALUE
+ 	};
+ 
+-	return connmark_tg_shift(skb, &info2);
++	return connmark_tg_shift(skb, &info3);
+ }
+ 
+ static unsigned int
+ connmark_tg_v2(struct sk_buff *skb, const struct xt_action_param *par)
+ {
+ 	const struct xt_connmark_tginfo2 *info = par->targinfo;
++	const struct xt_connmark_tginfo3 info3 = {
++		.ctmark	= info->ctmark,
++		.ctmask	= info->ctmask,
++		.nfmask	= info->nfmask,
++		.mode	= info->mode,
++		.func	= XT_CONNMARK_VALUE
++	};
++
++	return connmark_tg_shift(skb, &info3);
++}
++
++static unsigned int
++connmark_tg_v3(struct sk_buff *skb, const struct xt_action_param *par)
++{
++	const struct xt_connmark_tginfo3 *info = par->targinfo;
+ 
+ 	return connmark_tg_shift(skb, info);
+ }
+@@ -167,6 +196,16 @@ static struct xt_target connmark_tg_reg[
+ 		.targetsize     = sizeof(struct xt_connmark_tginfo2),
+ 		.destroy        = connmark_tg_destroy,
+ 		.me             = THIS_MODULE,
++	},
++	{
++		.name           = "CONNMARK",
++		.revision       = 3,
++		.family         = NFPROTO_UNSPEC,
++		.checkentry     = connmark_tg_check,
++		.target         = connmark_tg_v3,
++		.targetsize     = sizeof(struct xt_connmark_tginfo3),
++		.destroy        = connmark_tg_destroy,
++		.me             = THIS_MODULE,
+ 	}
+ };
+ 
diff --git a/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
new file mode 100644
index 00000000000000..73c5ec44f15e09
--- /dev/null
+++ b/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -0,0 +1,776 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 20 Feb 2018 15:56:02 +0100
+Subject: [PATCH] netfilter: add xt_FLOWOFFLOAD target
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ create mode 100644 net/netfilter/xt_OFFLOAD.c
+
+--- a/net/netfilter/Kconfig
++++ b/net/netfilter/Kconfig
+@@ -715,8 +715,6 @@ config NFT_REJECT_NETDEV
+ 
+ endif # NF_TABLES_NETDEV
+ 
+-endif # NF_TABLES
+-
+ config NF_FLOW_TABLE_INET
+ 	tristate "Netfilter flow table mixed IPv4/IPv6 module"
+ 	depends on NF_FLOW_TABLE
+@@ -725,11 +723,12 @@ config NF_FLOW_TABLE_INET
+ 
+ 	  To compile it as a module, choose M here.
+ 
++endif # NF_TABLES
++
+ config NF_FLOW_TABLE
+ 	tristate "Netfilter flow table module"
+ 	depends on NETFILTER_INGRESS
+ 	depends on NF_CONNTRACK
+-	depends on NF_TABLES
+ 	help
+ 	  This option adds the flow table core infrastructure.
+ 
+@@ -1025,6 +1024,15 @@ config NETFILTER_XT_TARGET_NOTRACK
+ 	depends on NETFILTER_ADVANCED
+ 	select NETFILTER_XT_TARGET_CT
+ 
++config NETFILTER_XT_TARGET_FLOWOFFLOAD
++	tristate '"FLOWOFFLOAD" target support'
++	depends on NF_FLOW_TABLE
++	depends on NETFILTER_INGRESS
++	help
++	  This option adds a `FLOWOFFLOAD' target, which uses the nf_flow_offload
++	  module to speed up processing of packets by bypassing the usual
++	  netfilter chains
++
+ config NETFILTER_XT_TARGET_RATEEST
+ 	tristate '"RATEEST" target support'
+ 	depends on NETFILTER_ADVANCED
+--- a/net/netfilter/Makefile
++++ b/net/netfilter/Makefile
+@@ -163,6 +163,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF
+ obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o
+ obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o
+ obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o
++obj-$(CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD) += xt_FLOWOFFLOAD.o
+ obj-$(CONFIG_NETFILTER_XT_TARGET_HL) += xt_HL.o
+ obj-$(CONFIG_NETFILTER_XT_TARGET_HMARK) += xt_HMARK.o
+ obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
+--- /dev/null
++++ b/net/netfilter/xt_FLOWOFFLOAD.c
+@@ -0,0 +1,694 @@
++/*
++ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/netfilter.h>
++#include <linux/netfilter/xt_FLOWOFFLOAD.h>
++#include <linux/if_vlan.h>
++#include <net/ip.h>
++#include <net/netfilter/nf_conntrack.h>
++#include <net/netfilter/nf_conntrack_extend.h>
++#include <net/netfilter/nf_conntrack_helper.h>
++#include <net/netfilter/nf_flow_table.h>
++
++struct xt_flowoffload_hook {
++	struct hlist_node list;
++	struct nf_hook_ops ops;
++	struct net *net;
++	bool registered;
++	bool used;
++};
++
++struct xt_flowoffload_table {
++	struct nf_flowtable ft;
++	struct hlist_head hooks;
++	struct delayed_work work;
++};
++
++struct nf_forward_info {
++	const struct net_device *indev;
++	const struct net_device *outdev;
++	const struct net_device *hw_outdev;
++	struct id {
++		__u16	id;
++		__be16	proto;
++	} encap[NF_FLOW_TABLE_ENCAP_MAX];
++	u8 num_encaps;
++	u8 ingress_vlans;
++	u8 h_source[ETH_ALEN];
++	u8 h_dest[ETH_ALEN];
++	enum flow_offload_xmit_type xmit_type;
++};
++
++static DEFINE_SPINLOCK(hooks_lock);
++
++struct xt_flowoffload_table flowtable[2];
++
++static unsigned int
++xt_flowoffload_net_hook(void *priv, struct sk_buff *skb,
++			const struct nf_hook_state *state)
++{
++	struct vlan_ethhdr *veth;
++	__be16 proto;
++
++	switch (skb->protocol) {
++	case htons(ETH_P_8021Q):
++		veth = (struct vlan_ethhdr *)skb_mac_header(skb);
++		proto = veth->h_vlan_encapsulated_proto;
++		break;
++	case htons(ETH_P_PPP_SES):
++		proto = nf_flow_pppoe_proto(skb);
++		break;
++	default:
++		proto = skb->protocol;
++		break;
++	}
++
++	switch (proto) {
++	case htons(ETH_P_IP):
++		return nf_flow_offload_ip_hook(priv, skb, state);
++	case htons(ETH_P_IPV6):
++		return nf_flow_offload_ipv6_hook(priv, skb, state);
++	}
++
++	return NF_ACCEPT;
++}
++
++static int
++xt_flowoffload_create_hook(struct xt_flowoffload_table *table,
++			   struct net_device *dev)
++{
++	struct xt_flowoffload_hook *hook;
++	struct nf_hook_ops *ops;
++
++	hook = kzalloc(sizeof(*hook), GFP_ATOMIC);
++	if (!hook)
++		return -ENOMEM;
++
++	ops = &hook->ops;
++	ops->pf = NFPROTO_NETDEV;
++	ops->hooknum = NF_NETDEV_INGRESS;
++	ops->priority = 10;
++	ops->priv = &table->ft;
++	ops->hook = xt_flowoffload_net_hook;
++	ops->dev = dev;
++
++	hlist_add_head(&hook->list, &table->hooks);
++	mod_delayed_work(system_power_efficient_wq, &table->work, 0);
++
++	return 0;
++}
++
++static struct xt_flowoffload_hook *
++flow_offload_lookup_hook(struct xt_flowoffload_table *table,
++			 struct net_device *dev)
++{
++	struct xt_flowoffload_hook *hook;
++
++	hlist_for_each_entry(hook, &table->hooks, list) {
++		if (hook->ops.dev == dev)
++			return hook;
++	}
++
++	return NULL;
++}
++
++static void
++xt_flowoffload_check_device(struct xt_flowoffload_table *table,
++			    struct net_device *dev)
++{
++	struct xt_flowoffload_hook *hook;
++
++	if (!dev)
++		return;
++
++	spin_lock_bh(&hooks_lock);
++	hook = flow_offload_lookup_hook(table, dev);
++	if (hook)
++		hook->used = true;
++	else
++		xt_flowoffload_create_hook(table, dev);
++	spin_unlock_bh(&hooks_lock);
++}
++
++static void
++xt_flowoffload_register_hooks(struct xt_flowoffload_table *table)
++{
++	struct xt_flowoffload_hook *hook;
++
++restart:
++	hlist_for_each_entry(hook, &table->hooks, list) {
++		if (hook->registered)
++			continue;
++
++		hook->registered = true;
++		hook->net = dev_net(hook->ops.dev);
++		spin_unlock_bh(&hooks_lock);
++		nf_register_net_hook(hook->net, &hook->ops);
++		if (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD)
++			table->ft.type->setup(&table->ft, hook->ops.dev,
++					      FLOW_BLOCK_BIND);
++		spin_lock_bh(&hooks_lock);
++		goto restart;
++	}
++
++}
++
++static bool
++xt_flowoffload_cleanup_hooks(struct xt_flowoffload_table *table)
++{
++	struct xt_flowoffload_hook *hook;
++	bool active = false;
++
++restart:
++	spin_lock_bh(&hooks_lock);
++	hlist_for_each_entry(hook, &table->hooks, list) {
++		if (hook->used || !hook->registered) {
++			active = true;
++			continue;
++		}
++
++		hlist_del(&hook->list);
++		spin_unlock_bh(&hooks_lock);
++		if (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD)
++			table->ft.type->setup(&table->ft, hook->ops.dev,
++					      FLOW_BLOCK_UNBIND);
++		nf_unregister_net_hook(hook->net, &hook->ops);
++		kfree(hook);
++		goto restart;
++	}
++	spin_unlock_bh(&hooks_lock);
++
++	return active;
++}
++
++static void
++xt_flowoffload_check_hook(struct flow_offload *flow, void *data)
++{
++	struct xt_flowoffload_table *table = data;
++	struct flow_offload_tuple *tuple0 = &flow->tuplehash[0].tuple;
++	struct flow_offload_tuple *tuple1 = &flow->tuplehash[1].tuple;
++	struct xt_flowoffload_hook *hook;
++
++	spin_lock_bh(&hooks_lock);
++	hlist_for_each_entry(hook, &table->hooks, list) {
++		if (hook->ops.dev->ifindex != tuple0->iifidx &&
++		    hook->ops.dev->ifindex != tuple1->iifidx)
++			continue;
++
++		hook->used = true;
++	}
++	spin_unlock_bh(&hooks_lock);
++}
++
++static void
++xt_flowoffload_hook_work(struct work_struct *work)
++{
++	struct xt_flowoffload_table *table;
++	struct xt_flowoffload_hook *hook;
++	int err;
++
++	table = container_of(work, struct xt_flowoffload_table, work.work);
++
++	spin_lock_bh(&hooks_lock);
++	xt_flowoffload_register_hooks(table);
++	hlist_for_each_entry(hook, &table->hooks, list)
++		hook->used = false;
++	spin_unlock_bh(&hooks_lock);
++
++
++
++	if (err && err != -EAGAIN)
++		goto out;
++
++	if (!xt_flowoffload_cleanup_hooks(table))
++		return;
++
++out:
++	queue_delayed_work(system_power_efficient_wq, &table->work, HZ);
++}
++
++static bool
++xt_flowoffload_skip(struct sk_buff *skb, int family)
++{
++	if (skb_sec_path(skb))
++		return true;
++
++	if (family == NFPROTO_IPV4) {
++		const struct ip_options *opt = &(IPCB(skb)->opt);
++
++		if (unlikely(opt->optlen))
++			return true;
++	}
++
++	return false;
++}
++
++static enum flow_offload_xmit_type nf_xmit_type(struct dst_entry *dst)
++{
++	if (dst_xfrm(dst))
++		return FLOW_OFFLOAD_XMIT_XFRM;
++
++	return FLOW_OFFLOAD_XMIT_NEIGH;
++}
++
++static void nf_default_forward_path(struct nf_flow_route *route,
++				    struct dst_entry *dst_cache,
++				    enum ip_conntrack_dir dir,
++				    struct net_device **dev)
++{
++	dev[!dir] = dst_cache->dev;
++	route->tuple[!dir].in.ifindex	= dst_cache->dev->ifindex;
++	route->tuple[dir].dst		= dst_cache;
++	route->tuple[dir].xmit_type	= nf_xmit_type(dst_cache);
++}
++
++static bool nf_is_valid_ether_device(const struct net_device *dev)
++{
++	if (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||
++	    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))
++		return false;
++
++	return true;
++}
++
++static void nf_dev_path_info(const struct net_device_path_stack *stack,
++			     struct nf_forward_info *info,
++			     unsigned char *ha)
++{
++	const struct net_device_path *path;
++	int i;
++
++	memcpy(info->h_dest, ha, ETH_ALEN);
++
++	for (i = 0; i < stack->num_paths; i++) {
++		path = &stack->path[i];
++		switch (path->type) {
++		case DEV_PATH_ETHERNET:
++		case DEV_PATH_DSA:
++		case DEV_PATH_VLAN:
++		case DEV_PATH_PPPOE:
++			info->indev = path->dev;
++			if (is_zero_ether_addr(info->h_source))
++				memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);
++
++			if (path->type == DEV_PATH_ETHERNET)
++				break;
++			if (path->type == DEV_PATH_DSA) {
++				i = stack->num_paths;
++				break;
++			}
++
++			/* DEV_PATH_VLAN and DEV_PATH_PPPOE */
++			if (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) {
++				info->indev = NULL;
++				break;
++			}
++			if (!info->outdev)
++				info->outdev = path->dev;
++			info->encap[info->num_encaps].id = path->encap.id;
++			info->encap[info->num_encaps].proto = path->encap.proto;
++			info->num_encaps++;
++			if (path->type == DEV_PATH_PPPOE)
++				memcpy(info->h_dest, path->encap.h_dest, ETH_ALEN);
++			break;
++		case DEV_PATH_BRIDGE:
++			if (is_zero_ether_addr(info->h_source))
++				memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);
++
++			switch (path->bridge.vlan_mode) {
++			case DEV_PATH_BR_VLAN_UNTAG_HW:
++				info->ingress_vlans |= BIT(info->num_encaps - 1);
++				break;
++			case DEV_PATH_BR_VLAN_TAG:
++				info->encap[info->num_encaps].id = path->bridge.vlan_id;
++				info->encap[info->num_encaps].proto = path->bridge.vlan_proto;
++				info->num_encaps++;
++				break;
++			case DEV_PATH_BR_VLAN_UNTAG:
++				info->num_encaps--;
++				break;
++			case DEV_PATH_BR_VLAN_KEEP:
++				break;
++			}
++			break;
++		default:
++			info->indev = NULL;
++			break;
++		}
++	}
++	if (!info->outdev)
++		info->outdev = info->indev;
++
++	info->hw_outdev = info->indev;
++
++	if (nf_is_valid_ether_device(info->indev))
++		info->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;
++}
++
++static int nf_dev_fill_forward_path(const struct nf_flow_route *route,
++				     const struct dst_entry *dst_cache,
++				     const struct nf_conn *ct,
++				     enum ip_conntrack_dir dir, u8 *ha,
++				     struct net_device_path_stack *stack)
++{
++	const void *daddr = &ct->tuplehash[!dir].tuple.src.u3;
++	struct net_device *dev = dst_cache->dev;
++	struct neighbour *n;
++	u8 nud_state;
++
++	if (!nf_is_valid_ether_device(dev))
++		goto out;
++
++	n = dst_neigh_lookup(dst_cache, daddr);
++	if (!n)
++		return -1;
++
++	read_lock_bh(&n->lock);
++	nud_state = n->nud_state;
++	ether_addr_copy(ha, n->ha);
++	read_unlock_bh(&n->lock);
++	neigh_release(n);
++
++	if (!(nud_state & NUD_VALID))
++		return -1;
++
++out:
++	return dev_fill_forward_path(dev, ha, stack);
++}
++
++static void nf_dev_forward_path(struct nf_flow_route *route,
++				const struct nf_conn *ct,
++				enum ip_conntrack_dir dir,
++				struct net_device **devs)
++{
++	const struct dst_entry *dst = route->tuple[dir].dst;
++	struct net_device_path_stack stack;
++	struct nf_forward_info info = {};
++	unsigned char ha[ETH_ALEN];
++	int i;
++
++	if (nf_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0)
++		nf_dev_path_info(&stack, &info, ha);
++
++	devs[!dir] = (struct net_device *)info.indev;
++	if (!info.indev)
++		return;
++
++	route->tuple[!dir].in.ifindex = info.indev->ifindex;
++	for (i = 0; i < info.num_encaps; i++) {
++		route->tuple[!dir].in.encap[i].id = info.encap[i].id;
++		route->tuple[!dir].in.encap[i].proto = info.encap[i].proto;
++	}
++	route->tuple[!dir].in.num_encaps = info.num_encaps;
++	route->tuple[!dir].in.ingress_vlans = info.ingress_vlans;
++
++	if (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) {
++		memcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);
++		memcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN);
++		route->tuple[dir].out.ifindex = info.outdev->ifindex;
++		route->tuple[dir].out.hw_ifindex = info.hw_outdev->ifindex;
++		route->tuple[dir].xmit_type = info.xmit_type;
++	}
++}
++
++static int
++xt_flowoffload_route(struct sk_buff *skb, const struct nf_conn *ct,
++		     const struct xt_action_param *par,
++		     struct nf_flow_route *route, enum ip_conntrack_dir dir,
++		     struct net_device **devs)
++{
++	struct dst_entry *this_dst = skb_dst(skb);
++	struct dst_entry *other_dst = NULL;
++	struct flowi fl;
++
++	memset(&fl, 0, sizeof(fl));
++	switch (xt_family(par)) {
++	case NFPROTO_IPV4:
++		fl.u.ip4.daddr = ct->tuplehash[dir].tuple.src.u3.ip;
++		fl.u.ip4.flowi4_oif = xt_in(par)->ifindex;
++		break;
++	case NFPROTO_IPV6:
++		fl.u.ip6.saddr = ct->tuplehash[!dir].tuple.dst.u3.in6;
++		fl.u.ip6.daddr = ct->tuplehash[dir].tuple.src.u3.in6;
++		fl.u.ip6.flowi6_oif = xt_in(par)->ifindex;
++		break;
++	}
++
++	nf_route(xt_net(par), &other_dst, &fl, false, xt_family(par));
++	if (!other_dst)
++		return -ENOENT;
++
++	nf_default_forward_path(route, this_dst, dir, devs);
++	nf_default_forward_path(route, other_dst, !dir, devs);
++
++	if (route->tuple[dir].xmit_type	== FLOW_OFFLOAD_XMIT_NEIGH &&
++	    route->tuple[!dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) {
++		nf_dev_forward_path(route, ct, dir, devs);
++		nf_dev_forward_path(route, ct, !dir, devs);
++	}
++
++	return 0;
++}
++
++static unsigned int
++flowoffload_tg(struct sk_buff *skb, const struct xt_action_param *par)
++{
++	struct xt_flowoffload_table *table;
++	const struct xt_flowoffload_target_info *info = par->targinfo;
++	struct tcphdr _tcph, *tcph = NULL;
++	enum ip_conntrack_info ctinfo;
++	enum ip_conntrack_dir dir;
++	struct nf_flow_route route = {};
++	struct flow_offload *flow = NULL;
++	struct net_device *devs[2] = {};
++	struct nf_conn *ct;
++	struct net *net;
++
++	if (xt_flowoffload_skip(skb, xt_family(par)))
++		return XT_CONTINUE;
++
++	ct = nf_ct_get(skb, &ctinfo);
++	if (ct == NULL)
++		return XT_CONTINUE;
++
++	switch (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum) {
++	case IPPROTO_TCP:
++		if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED)
++			return XT_CONTINUE;
++
++		tcph = skb_header_pointer(skb, par->thoff,
++					  sizeof(_tcph), &_tcph);
++		if (unlikely(!tcph || tcph->fin || tcph->rst))
++			return XT_CONTINUE;
++		break;
++	case IPPROTO_UDP:
++		break;
++	default:
++		return XT_CONTINUE;
++	}
++
++	if (nf_ct_ext_exist(ct, NF_CT_EXT_HELPER) ||
++	    ct->status & (IPS_SEQ_ADJUST | IPS_NAT_CLASH))
++		return XT_CONTINUE;
++
++	if (!nf_ct_is_confirmed(ct))
++		return XT_CONTINUE;
++
++	devs[dir] = xt_out(par);
++	devs[!dir] = xt_in(par);
++
++	if (!devs[dir] || !devs[!dir])
++		return XT_CONTINUE;
++
++	if (test_and_set_bit(IPS_OFFLOAD_BIT, &ct->status))
++		return XT_CONTINUE;
++
++	dir = CTINFO2DIR(ctinfo);
++
++	if (xt_flowoffload_route(skb, ct, par, &route, dir, devs) < 0)
++		goto err_flow_route;
++
++	flow = flow_offload_alloc(ct);
++	if (!flow)
++		goto err_flow_alloc;
++
++	flow_offload_route_init(flow, &route);
++	
++
++	if (tcph) {
++		ct->proto.tcp.seen[0].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;
++		ct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;
++	}
++
++	table = &flowtable[!!(info->flags & XT_FLOWOFFLOAD_HW)];
++
++	net = read_pnet(&table->ft.net);
++	if (!net)
++		write_pnet(&table->ft.net, xt_net(par));
++
++	if (flow_offload_add(&table->ft, flow) < 0)
++		goto err_flow_add;
++
++	xt_flowoffload_check_device(table, devs[0]);
++	xt_flowoffload_check_device(table, devs[1]);
++
++	dst_release(route.tuple[!dir].dst);
++
++	return XT_CONTINUE;
++
++err_flow_add:
++	flow_offload_free(flow);
++err_flow_alloc:
++	dst_release(route.tuple[!dir].dst);
++err_flow_route:
++	clear_bit(IPS_OFFLOAD_BIT, &ct->status);
++
++	return XT_CONTINUE;
++}
++
++static int flowoffload_chk(const struct xt_tgchk_param *par)
++{
++	struct xt_flowoffload_target_info *info = par->targinfo;
++
++	if (info->flags & ~XT_FLOWOFFLOAD_MASK)
++		return -EINVAL;
++
++	return 0;
++}
++
++static struct xt_target offload_tg_reg __read_mostly = {
++	.family		= NFPROTO_UNSPEC,
++	.name		= "FLOWOFFLOAD",
++	.revision	= 0,
++	.targetsize	= sizeof(struct xt_flowoffload_target_info),
++	.usersize	= sizeof(struct xt_flowoffload_target_info),
++	.checkentry	= flowoffload_chk,
++	.target		= flowoffload_tg,
++	.me		= THIS_MODULE,
++};
++
++static int flow_offload_netdev_event(struct notifier_block *this,
++				     unsigned long event, void *ptr)
++{
++	struct xt_flowoffload_hook *hook0, *hook1;
++	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
++
++	if (event != NETDEV_UNREGISTER)
++		return NOTIFY_DONE;
++
++	spin_lock_bh(&hooks_lock);
++	hook0 = flow_offload_lookup_hook(&flowtable[0], dev);
++	if (hook0)
++		hlist_del(&hook0->list);
++
++	hook1 = flow_offload_lookup_hook(&flowtable[1], dev);
++	if (hook1)
++		hlist_del(&hook1->list);
++	spin_unlock_bh(&hooks_lock);
++
++	if (hook0) {
++		nf_unregister_net_hook(hook0->net, &hook0->ops);
++		kfree(hook0);
++	}
++
++	if (hook1) {
++		nf_unregister_net_hook(hook1->net, &hook1->ops);
++		kfree(hook1);
++	}
++
++	nf_flow_table_cleanup(dev);
++
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block flow_offload_netdev_notifier = {
++	.notifier_call	= flow_offload_netdev_event,
++};
++
++static int nf_flow_rule_route_inet(struct net *net,
++				   struct flow_offload *flow,
++				   enum flow_offload_tuple_dir dir,
++				   struct nf_flow_rule *flow_rule)
++{
++	const struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;
++	int err;
++
++	switch (flow_tuple->l3proto) {
++	case NFPROTO_IPV4:
++		err = nf_flow_rule_route_ipv4(net, flow, dir, flow_rule);
++		break;
++	case NFPROTO_IPV6:
++		err = nf_flow_rule_route_ipv6(net, flow, dir, flow_rule);
++		break;
++	default:
++		err = -1;
++		break;
++	}
++
++	return err;
++}
++
++static struct nf_flowtable_type flowtable_inet = {
++	.family		= NFPROTO_INET,
++	.init		= nf_flow_table_init,
++	.setup		= nf_flow_table_offload_setup,
++	.action		= nf_flow_rule_route_inet,
++	.free		= nf_flow_table_free,
++	.hook		= xt_flowoffload_net_hook,
++	.owner		= THIS_MODULE,
++};
++
++static int init_flowtable(struct xt_flowoffload_table *tbl)
++{
++	INIT_DELAYED_WORK(&tbl->work, xt_flowoffload_hook_work);
++	tbl->ft.type = &flowtable_inet;
++
++	return nf_flow_table_init(&tbl->ft);
++}
++
++static int __init xt_flowoffload_tg_init(void)
++{
++	int ret;
++
++	register_netdevice_notifier(&flow_offload_netdev_notifier);
++
++	ret = init_flowtable(&flowtable[0]);
++	if (ret)
++		return ret;
++
++	ret = init_flowtable(&flowtable[1]);
++	if (ret)
++		goto cleanup;
++
++	flowtable[1].ft.flags = NF_FLOWTABLE_HW_OFFLOAD;
++
++	ret = xt_register_target(&offload_tg_reg);
++	if (ret)
++		goto cleanup2;
++
++	return 0;
++
++cleanup2:
++	nf_flow_table_free(&flowtable[1].ft);
++cleanup:
++	nf_flow_table_free(&flowtable[0].ft);
++	return ret;
++}
++
++static void __exit xt_flowoffload_tg_exit(void)
++{
++	xt_unregister_target(&offload_tg_reg);
++	unregister_netdevice_notifier(&flow_offload_netdev_notifier);
++	nf_flow_table_free(&flowtable[0].ft);
++	nf_flow_table_free(&flowtable[1].ft);
++}
++
++MODULE_LICENSE("GPL");
++module_init(xt_flowoffload_tg_init);
++module_exit(xt_flowoffload_tg_exit);
+--- /dev/null
++++ b/include/uapi/linux/netfilter/xt_FLOWOFFLOAD.h
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
++#ifndef _XT_FLOWOFFLOAD_H
++#define _XT_FLOWOFFLOAD_H
++
++#include <linux/types.h>
++
++enum {
++	XT_FLOWOFFLOAD_HW	= 1 << 0,
++
++	XT_FLOWOFFLOAD_MASK	= XT_FLOWOFFLOAD_HW
++};
++
++struct xt_flowoffload_target_info {
++	__u32 flags;
++};
++
++#endif /* _XT_FLOWOFFLOAD_H */
diff --git a/target/linux/generic/hack-6.6/651-wireless_mesh_header.patch b/target/linux/generic/hack-6.6/651-wireless_mesh_header.patch
new file mode 100644
index 00000000000000..3a2a9970bdc5a5
--- /dev/null
+++ b/target/linux/generic/hack-6.6/651-wireless_mesh_header.patch
@@ -0,0 +1,24 @@
+From 6d3bc769657b0ee7c7506dad9911111c4226a7ea Mon Sep 17 00:00:00 2001
+From: Imre Kaloz <kaloz@openwrt.org>
+Date: Fri, 7 Jul 2017 17:21:05 +0200
+Subject: mac80211: increase wireless mesh header size
+
+lede-commit 3d4466cfd8f75f717efdb1f96fdde3c70d865fc1
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+---
+ include/linux/netdevice.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -157,8 +157,8 @@ static inline bool dev_xmit_complete(int
+ 
+ #if defined(CONFIG_HYPERV_NET)
+ # define LL_MAX_HEADER 128
+-#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25)
+-# if defined(CONFIG_MAC80211_MESH)
++#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) || 1
++# if defined(CONFIG_MAC80211_MESH) || 1
+ #  define LL_MAX_HEADER 128
+ # else
+ #  define LL_MAX_HEADER 96
diff --git a/target/linux/generic/hack-6.6/660-fq_codel_defaults.patch b/target/linux/generic/hack-6.6/660-fq_codel_defaults.patch
new file mode 100644
index 00000000000000..b923a2d206da3c
--- /dev/null
+++ b/target/linux/generic/hack-6.6/660-fq_codel_defaults.patch
@@ -0,0 +1,27 @@
+From a6ccb238939b25851474a279b20367fd24a0e816 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 17:21:53 +0200
+Subject:  hack: net: fq_codel: tune defaults for small devices
+
+Assume that x86_64 devices always have a big memory and do not need this 
+optimization compared to devices with only 32 MB or 64 MB RAM.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ net/sched/sch_fq_codel.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/net/sched/sch_fq_codel.c
++++ b/net/sched/sch_fq_codel.c
+@@ -471,7 +471,11 @@ static int fq_codel_init(struct Qdisc *s
+ 
+ 	sch->limit = 10*1024;
+ 	q->flows_cnt = 1024;
++#ifdef CONFIG_X86_64
+ 	q->memory_limit = 32 << 20; /* 32 MBytes */
++#else
++	q->memory_limit = 4 << 20; /* 4 MBytes */
++#endif
+ 	q->drop_batch_size = 64;
+ 	q->quantum = psched_mtu(qdisc_dev(sch));
+ 	INIT_LIST_HEAD(&q->new_flows);
diff --git a/target/linux/generic/hack-6.6/661-use_fq_codel_by_default.patch b/target/linux/generic/hack-6.6/661-use_fq_codel_by_default.patch
new file mode 100644
index 00000000000000..8ab4199f3427f8
--- /dev/null
+++ b/target/linux/generic/hack-6.6/661-use_fq_codel_by_default.patch
@@ -0,0 +1,100 @@
+From 1d418f7e88035ed7a94073f6354246c66e9193e9 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 17:22:58 +0200
+Subject: fq_codel: switch default qdisc from pfifo_fast to fq_codel and remove pfifo_fast
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/net/sch_generic.h | 3 ++-
+ net/sched/Kconfig         | 3 ++-
+ net/sched/sch_api.c       | 2 +-
+ net/sched/sch_fq_codel.c  | 3 ++-
+ net/sched/sch_generic.c   | 4 ++--
+ 5 files changed, 9 insertions(+), 6 deletions(-)
+
+--- a/include/net/sch_generic.h
++++ b/include/net/sch_generic.h
+@@ -589,12 +589,13 @@ extern struct Qdisc_ops noop_qdisc_ops;
+ extern struct Qdisc_ops pfifo_fast_ops;
+ extern struct Qdisc_ops mq_qdisc_ops;
+ extern struct Qdisc_ops noqueue_qdisc_ops;
++extern struct Qdisc_ops fq_codel_qdisc_ops;
+ extern const struct Qdisc_ops *default_qdisc_ops;
+ static inline const struct Qdisc_ops *
+ get_default_qdisc_ops(const struct net_device *dev, int ntx)
+ {
+ 	return ntx < dev->real_num_tx_queues ?
+-			default_qdisc_ops : &pfifo_fast_ops;
++			default_qdisc_ops : &fq_codel_qdisc_ops;
+ }
+ 
+ struct Qdisc_class_common {
+--- a/net/sched/Kconfig
++++ b/net/sched/Kconfig
+@@ -4,8 +4,9 @@
+ #
+ 
+ menuconfig NET_SCHED
+-	bool "QoS and/or fair queueing"
++	def_bool y
+ 	select NET_SCH_FIFO
++	select NET_SCH_FQ_CODEL
+ 	help
+ 	  When the kernel has several packets to send out over a network
+ 	  device, it has to decide which ones to send first, which ones to
+--- a/net/sched/sch_api.c
++++ b/net/sched/sch_api.c
+@@ -2368,7 +2368,7 @@ static int __init pktsched_init(void)
+ 		return err;
+ 	}
+ 
+-	register_qdisc(&pfifo_fast_ops);
++	register_qdisc(&fq_codel_qdisc_ops);
+ 	register_qdisc(&pfifo_qdisc_ops);
+ 	register_qdisc(&bfifo_qdisc_ops);
+ 	register_qdisc(&pfifo_head_drop_qdisc_ops);
+--- a/net/sched/sch_fq_codel.c
++++ b/net/sched/sch_fq_codel.c
+@@ -712,7 +712,7 @@ static const struct Qdisc_class_ops fq_c
+ 	.walk		=	fq_codel_walk,
+ };
+ 
+-static struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = {
++struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = {
+ 	.cl_ops		=	&fq_codel_class_ops,
+ 	.id		=	"fq_codel",
+ 	.priv_size	=	sizeof(struct fq_codel_sched_data),
+@@ -727,6 +727,7 @@ static struct Qdisc_ops fq_codel_qdisc_o
+ 	.dump_stats =	fq_codel_dump_stats,
+ 	.owner		=	THIS_MODULE,
+ };
++EXPORT_SYMBOL(fq_codel_qdisc_ops);
+ 
+ static int __init fq_codel_module_init(void)
+ {
+--- a/net/sched/sch_generic.c
++++ b/net/sched/sch_generic.c
+@@ -32,7 +32,7 @@
+ #include <net/xfrm.h>
+ 
+ /* Qdisc to use by default */
+-const struct Qdisc_ops *default_qdisc_ops = &pfifo_fast_ops;
++const struct Qdisc_ops *default_qdisc_ops = &fq_codel_qdisc_ops;
+ EXPORT_SYMBOL(default_qdisc_ops);
+ 
+ static void qdisc_maybe_clear_missed(struct Qdisc *q,
+@@ -1149,12 +1149,12 @@ static void attach_one_default_qdisc(str
+ 				     void *_unused)
+ {
+ 	struct Qdisc *qdisc;
+-	const struct Qdisc_ops *ops = default_qdisc_ops;
++	const struct Qdisc_ops *ops = &fq_codel_qdisc_ops;
+ 
+ 	if (dev->priv_flags & IFF_NO_QUEUE)
+ 		ops = &noqueue_qdisc_ops;
+ 	else if(dev->type == ARPHRD_CAN)
+-		ops = &pfifo_fast_ops;
++		ops = &fq_codel_qdisc_ops;
+ 
+ 	qdisc = qdisc_create_dflt(dev_queue, ops, TC_H_ROOT, NULL);
+ 	if (!qdisc)
diff --git a/target/linux/generic/hack-6.6/700-swconfig_switch_drivers.patch b/target/linux/generic/hack-6.6/700-swconfig_switch_drivers.patch
new file mode 100644
index 00000000000000..64102e606e8abb
--- /dev/null
+++ b/target/linux/generic/hack-6.6/700-swconfig_switch_drivers.patch
@@ -0,0 +1,129 @@
+From 36e516290611e613aa92996cb4339561452695b4 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 7 Jul 2017 17:24:23 +0200
+Subject: net: swconfig: adds openwrt switch layer
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/net/phy/Kconfig   | 83 +++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/net/phy/Makefile  | 15 +++++++++
+ include/uapi/linux/Kbuild |  1 +
+ 3 files changed, 99 insertions(+)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -66,6 +66,80 @@ config SFP
+ 	depends on HWMON || HWMON=n
+ 	select MDIO_I2C
+ 
++comment "Switch configuration API + drivers"
++
++config SWCONFIG
++	tristate "Switch configuration API"
++	help
++	  Switch configuration API using netlink. This allows
++	  you to configure the VLAN features of certain switches.
++
++config SWCONFIG_LEDS
++	bool "Switch LED trigger support"
++	depends on (SWCONFIG && LEDS_TRIGGERS)
++
++config ADM6996_PHY
++	tristate "Driver for ADM6996 switches"
++	select SWCONFIG
++	help
++	  Currently supports the ADM6996FC and ADM6996M switches.
++	  Support for FC is very limited.
++
++config AR8216_PHY
++	tristate "Driver for Atheros AR8216 switches"
++	select SWCONFIG
++
++config AR8216_PHY_LEDS
++	bool "Atheros AR8216 switch LED support"
++	depends on (AR8216_PHY && LEDS_CLASS)
++
++source "drivers/net/phy/b53/Kconfig"
++
++config IP17XX_PHY
++	tristate "Driver for IC+ IP17xx switches"
++	select SWCONFIG
++
++config PSB6970_PHY
++	tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch"
++	select SWCONFIG
++	select ETHERNET_PACKET_MANGLE
++
++config RTL8306_PHY
++	tristate "Driver for Realtek RTL8306S switches"
++	select SWCONFIG
++
++config RTL8366_SMI
++	tristate "Driver for the RTL8366 SMI interface"
++	depends on GPIOLIB
++	help
++	  This module implements the SMI interface protocol which is used
++	  by some RTL8366 ethernet switch devices via the generic GPIO API.
++
++if RTL8366_SMI
++
++config RTL8366_SMI_DEBUG_FS
++	bool "RTL8366 SMI interface debugfs support"
++        depends on DEBUG_FS
++        default n
++
++config RTL8366S_PHY
++	tristate "Driver for the Realtek RTL8366S switch"
++	select SWCONFIG
++
++config RTL8366RB_PHY
++	tristate "Driver for the Realtek RTL8366RB switch"
++	select SWCONFIG
++
++config RTL8367_PHY
++	tristate "Driver for the Realtek RTL8367R/M switches"
++	select SWCONFIG
++
++config RTL8367B_PHY
++	tristate "Driver fot the Realtek RTL8367R-VB switch"
++	select SWCONFIG
++
++endif # RTL8366_SMI
++
+ comment "MII PHY device drivers"
+ 
+ config AMD_PHY
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -26,6 +26,19 @@ libphy-$(CONFIG_LED_TRIGGER_PHY)	+= phy_
+ obj-$(CONFIG_PHYLINK)		+= phylink.o
+ obj-$(CONFIG_PHYLIB)		+= libphy.o
+ 
++obj-$(CONFIG_SWCONFIG)		+= swconfig.o
++obj-$(CONFIG_ADM6996_PHY)	+= adm6996.o
++obj-$(CONFIG_AR8216_PHY)	+= ar8216.o ar8327.o
++obj-$(CONFIG_SWCONFIG_B53)	+= b53/
++obj-$(CONFIG_IP17XX_PHY)	+= ip17xx.o
++obj-$(CONFIG_PSB6970_PHY)	+= psb6970.o
++obj-$(CONFIG_RTL8306_PHY)	+= rtl8306.o
++obj-$(CONFIG_RTL8366_SMI)	+= rtl8366_smi.o
++obj-$(CONFIG_RTL8366S_PHY)	+= rtl8366s.o
++obj-$(CONFIG_RTL8366RB_PHY)	+= rtl8366rb.o
++obj-$(CONFIG_RTL8367_PHY)	+= rtl8367.o
++obj-$(CONFIG_RTL8367B_PHY)	+= rtl8367b.o
++
+ obj-$(CONFIG_NETWORK_PHY_TIMESTAMPING) += mii_timestamper.o
+ 
+ obj-$(CONFIG_SFP)		+= sfp.o
+--- a/include/linux/platform_data/b53.h
++++ b/include/linux/platform_data/b53.h
+@@ -29,6 +29,9 @@ struct b53_platform_data {
+ 	u32 chip_id;
+ 	u16 enabled_ports;
+ 
++	/* allow to specify an ethX alias */
++	const char *alias;
++
+ 	/* only used by MMAP'd driver */
+ 	unsigned big_endian:1;
+ 	void __iomem *regs;
diff --git a/target/linux/generic/hack-6.6/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-6.6/760-net-usb-r8152-add-LED-configuration-from-OF.patch
new file mode 100644
index 00000000000000..4b1317580a23a6
--- /dev/null
+++ b/target/linux/generic/hack-6.6/760-net-usb-r8152-add-LED-configuration-from-OF.patch
@@ -0,0 +1,74 @@
+From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 02:38:31 +0200
+Subject: [PATCH] net: usb: r8152: add LED configuration from OF
+
+This adds the ability to configure the LED configuration register using
+OF. This way, the correct value for board specific LED configuration can
+be determined.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -11,6 +11,7 @@
+ #include <linux/mii.h>
+ #include <linux/ethtool.h>
+ #include <linux/usb.h>
++#include <linux/of.h>
+ #include <linux/crc32.h>
+ #include <linux/if_vlan.h>
+ #include <linux/uaccess.h>
+@@ -7002,6 +7003,22 @@ static void rtl_tally_reset(struct r8152
+ 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
+ }
+ 
++static int r8152_led_configuration(struct r8152 *tp)
++{
++	u32 led_data;
++	int ret;
++
++	ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data",
++								&led_data);
++
++	if (ret)
++		return ret;
++	
++	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);
++
++	return 0;
++}
++
+ static void r8152b_init(struct r8152 *tp)
+ {
+ 	u32 ocp_data;
+@@ -7043,6 +7060,8 @@ static void r8152b_init(struct r8152 *tp
+ 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+ 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153_init(struct r8152 *tp)
+@@ -7183,6 +7202,8 @@ static void r8153_init(struct r8152 *tp)
+ 		tp->coalesce = COALESCE_SLOW;
+ 		break;
+ 	}
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153b_init(struct r8152 *tp)
+@@ -7265,6 +7286,8 @@ static void r8153b_init(struct r8152 *tp
+ 	rtl_tally_reset(tp);
+ 
+ 	tp->coalesce = 15000;	/* 15 us */
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153c_init(struct r8152 *tp)
diff --git a/target/linux/generic/hack-6.6/761-dt-bindings-net-add-RTL8152-binding-documentation.patch b/target/linux/generic/hack-6.6/761-dt-bindings-net-add-RTL8152-binding-documentation.patch
new file mode 100644
index 00000000000000..be262b993cd5d4
--- /dev/null
+++ b/target/linux/generic/hack-6.6/761-dt-bindings-net-add-RTL8152-binding-documentation.patch
@@ -0,0 +1,54 @@
+From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 15:30:33 +0200
+Subject: [PATCH] dt-bindings: net: add RTL8152 binding documentation
+
+Add binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet
+adapters.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ .../bindings/net/realtek,rtl8152.yaml         | 36 +++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml
+@@ -0,0 +1,36 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Realtek RTL8152/RTL8153 series USB ethernet
++
++maintainers:
++  - David Bauer <mail@david-bauer.net>
++
++properties:
++  compatible:
++    oneOf:
++      - items:
++          - enum:
++              - realtek,rtl8152
++              - realtek,rtl8153
++
++  reg:
++    description: The device number on the USB bus
++
++  realtek,led-data:
++    description: Value to be written to the LED configuration register.
++
++required:
++  - compatible
++  - reg
++
++examples:
++  - |
++    usb-eth@2 {
++      compatible = "realtek,rtl8153";
++      reg = <2>;
++      realtek,led-data = <0x87>;
++    };
+\ No newline at end of file
diff --git a/target/linux/generic/hack-6.6/773-bgmac-add-srab-switch.patch b/target/linux/generic/hack-6.6/773-bgmac-add-srab-switch.patch
new file mode 100644
index 00000000000000..85670fa0dd598b
--- /dev/null
+++ b/target/linux/generic/hack-6.6/773-bgmac-add-srab-switch.patch
@@ -0,0 +1,98 @@
+From 3cb240533ab787899dc7f17aa7d6c5b4810e2e58 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 7 Jul 2017 17:26:01 +0200
+Subject: bcm53xx: bgmac: use srab switch driver
+
+use the srab switch driver on these SoCs.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ drivers/net/ethernet/broadcom/bgmac-bcma.c |  1 +
+ drivers/net/ethernet/broadcom/bgmac.c      | 24 ++++++++++++++++++++++++
+ drivers/net/ethernet/broadcom/bgmac.h      |  4 ++++
+ 3 files changed, 29 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
++++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
+@@ -280,6 +280,7 @@ static int bgmac_probe(struct bcma_devic
+ 		bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
+ 		bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
+ 		bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
++		bgmac->feature_flags |= BGMAC_FEAT_SRAB;
+ 		break;
+ 	default:
+ 		bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
+--- a/drivers/net/ethernet/broadcom/bgmac.c
++++ b/drivers/net/ethernet/broadcom/bgmac.c
+@@ -12,6 +12,7 @@
+ #include <linux/bcma/bcma.h>
+ #include <linux/etherdevice.h>
+ #include <linux/interrupt.h>
++#include <linux/platform_data/b53.h>
+ #include <linux/bcm47xx_nvram.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
+@@ -1408,6 +1409,17 @@ static const struct ethtool_ops bgmac_et
+ 	.set_link_ksettings     = phy_ethtool_set_link_ksettings,
+ };
+ 
++static struct b53_platform_data bgmac_b53_pdata = {
++};
++
++static struct platform_device bgmac_b53_dev = {
++	.name		= "b53-srab-switch",
++	.id		= -1,
++	.dev		= {
++		.platform_data = &bgmac_b53_pdata,
++	},
++};
++
+ /**************************************************
+  * MII
+  **************************************************/
+@@ -1546,6 +1558,14 @@ int bgmac_enet_probe(struct bgmac *bgmac
+ 
+ 	bgmac->in_init = false;
+ 
++	if ((bgmac->feature_flags & BGMAC_FEAT_SRAB) && !bgmac_b53_pdata.regs) {
++		bgmac_b53_pdata.regs = ioremap_nocache(0x18007000, 0x1000);
++
++		err = platform_device_register(&bgmac_b53_dev);
++		if (!err)
++			bgmac->b53_device = &bgmac_b53_dev;
++	}
++
+ 	err = register_netdev(bgmac->net_dev);
+ 	if (err) {
+ 		dev_err(bgmac->dev, "Cannot register net device\n");
+@@ -1568,6 +1588,10 @@ EXPORT_SYMBOL_GPL(bgmac_enet_probe);
+ 
+ void bgmac_enet_remove(struct bgmac *bgmac)
+ {
++	if (bgmac->b53_device)
++		platform_device_unregister(&bgmac_b53_dev);
++	bgmac->b53_device = NULL;
++
+ 	unregister_netdev(bgmac->net_dev);
+ 	phy_disconnect(bgmac->net_dev->phydev);
+ 	netif_napi_del(&bgmac->napi);
+--- a/drivers/net/ethernet/broadcom/bgmac.h
++++ b/drivers/net/ethernet/broadcom/bgmac.h
+@@ -388,6 +388,7 @@
+ #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII	BIT(18)
+ #define BGMAC_FEAT_CC7_IF_TYPE_RGMII	BIT(19)
+ #define BGMAC_FEAT_IDM_MASK		BIT(20)
++#define BGMAC_FEAT_SRAB			BIT(21)
+ 
+ struct bgmac_slot_info {
+ 	union {
+@@ -495,6 +496,9 @@ struct bgmac {
+ 	void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,
+ 			      u32 set);
+ 	int (*phy_connect)(struct bgmac *bgmac);
++
++	/* platform device for associated switch */
++	struct platform_device *b53_device;
+ };
+ 
+ struct bgmac *bgmac_alloc(struct device *dev);
diff --git a/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
new file mode 100644
index 00000000000000..0e1d69e6192132
--- /dev/null
+++ b/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
@@ -0,0 +1,33 @@
+--- a/drivers/net/usb/qmi_wwan.c
++++ b/drivers/net/usb/qmi_wwan.c
+@@ -1089,6 +1089,7 @@ static const struct usb_device_id produc
+ 	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0620)},	/* Quectel EM160R-GL */
+ 	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0800)},	/* Quectel RM500Q-GL */
+ 	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0801)},	/* Quectel RM520N */
++	{QMI_MATCH_FF_FF_FF(0x05c6, 0xf601)},   /* MeigLink SLM750 */
+ 
+ 	/* 3. Combined interface devices matching on interface number */
+ 	{QMI_FIXED_INTF(0x0408, 0xea42, 4)},	/* Yota / Megafon M100-1 */
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -247,6 +247,8 @@ static void option_instat_callback(struc
+ #define UBLOX_PRODUCT_R410M			0x90b2
+ /* These Yuga products use Qualcomm's vendor ID */
+ #define YUGA_PRODUCT_CLM920_NC5			0x9625
++/* These MeigLink products use Qualcomm's vendor ID */
++#define MEIGLINK_PRODUCT_SLM750			0xf601
+ 
+ #define QUECTEL_VENDOR_ID			0x2c7c
+ /* These Quectel products use Quectel's vendor ID */
+@@ -1188,6 +1190,11 @@ static const struct usb_device_id option
+ 	  .driver_info = ZLP },
+ 	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
+ 	  .driver_info = RSVD(4) },
++	/* Meiglink products using Qualcomm vendor ID */
++	// Works OK. In case of some issues check macros that are used by Quectel Products
++	{ USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0xff, 0xff),
++	  .driver_info = NUMEP2 },
++	{ USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0, 0) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0xff, 0xff),
+ 	  .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0, 0) },
diff --git a/target/linux/generic/hack-6.6/800-GPIO-add-named-gpio-exports.patch b/target/linux/generic/hack-6.6/800-GPIO-add-named-gpio-exports.patch
new file mode 100644
index 00000000000000..666dcfad4d41ec
--- /dev/null
+++ b/target/linux/generic/hack-6.6/800-GPIO-add-named-gpio-exports.patch
@@ -0,0 +1,173 @@
+From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 12 Aug 2014 20:49:27 +0200
+Subject: [PATCH 30/36] GPIO: add named gpio exports
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -21,6 +21,8 @@
+ 
+ #include <linux/gpio/consumer.h>
+ #include <linux/gpio/machine.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
+ 
+ #include "gpiolib.h"
+ #include "gpiolib-of.h"
+@@ -1111,3 +1113,74 @@ void of_gpiochip_remove(struct gpio_chip
+ {
+ 	of_node_put(dev_of_node(&chip->gpiodev->dev));
+ }
++
++#ifdef CONFIG_GPIO_SYSFS
++
++static struct of_device_id gpio_export_ids[] = {
++	{ .compatible = "gpio-export" },
++	{ /* sentinel */ }
++};
++
++static int of_gpio_export_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct device_node *cnp;
++	u32 val;
++	int nb = 0;
++
++	for_each_child_of_node(np, cnp) {
++		const char *name = NULL;
++		int gpio;
++		bool dmc;
++		int max_gpio = 1;
++		int i;
++
++		of_property_read_string(cnp, "gpio-export,name", &name);
++
++		if (!name)
++			max_gpio = of_gpio_named_count(cnp, "gpios");
++
++		for (i = 0; i < max_gpio; i++) {
++			struct gpio_desc *desc;
++			unsigned flags = 0;
++			enum of_gpio_flags of_flags;
++
++			desc = of_get_named_gpiod_flags(cnp, "gpios", i, &of_flags);
++			if (IS_ERR(desc))
++				return PTR_ERR(desc);
++			gpio = desc_to_gpio(desc);
++
++			if (of_flags & OF_GPIO_ACTIVE_LOW)
++				flags |= GPIOF_ACTIVE_LOW;
++
++			if (!of_property_read_u32(cnp, "gpio-export,output", &val))
++				flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++			else
++				flags |= GPIOF_IN;
++
++			if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
++				continue;
++
++			dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
++			gpio_export_with_name(gpio_to_desc(gpio), dmc, name);
++			nb++;
++		}
++	}
++
++	dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
++
++	return 0;
++}
++
++static struct platform_driver gpio_export_driver = {
++	.driver		= {
++		.name		= "gpio-export",
++		.owner	= THIS_MODULE,
++		.of_match_table	= of_match_ptr(gpio_export_ids),
++	},
++	.probe		= of_gpio_export_probe,
++};
++
++module_platform_driver(gpio_export_driver);
++
++#endif
+--- a/include/linux/gpio/consumer.h
++++ b/include/linux/gpio/consumer.h
+@@ -644,7 +644,10 @@ static inline struct gpio_desc *acpi_get
+ 
+ #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+ 
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+ int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
++int gpio_export_with_name(struct gpio_desc *desc, bool direction_may_change,
++			  const char *name);
+ int gpiod_export_link(struct device *dev, const char *name,
+ 		      struct gpio_desc *desc);
+ void gpiod_unexport(struct gpio_desc *desc);
+@@ -653,11 +656,25 @@ void gpiod_unexport(struct gpio_desc *de
+ 
+ #include <asm/errno.h>
+ 
++static inline int __gpiod_export(struct gpio_desc *desc,
++			       bool direction_may_change,
++			       const char *name)
++{
++	return -ENOSYS;
++}
++
+ static inline int gpiod_export(struct gpio_desc *desc,
+ 			       bool direction_may_change)
+ {
+ 	return -ENOSYS;
+ }
++
++static inline int gpio_export_with_name(struct gpio_desc *desc,
++					bool direction_may_change,
++					const char *name)
++{
++	return -ENOSYS;
++}
+ 
+ static inline int gpiod_export_link(struct device *dev, const char *name,
+ 				    struct gpio_desc *desc)
+--- a/drivers/gpio/gpiolib-sysfs.c
++++ b/drivers/gpio/gpiolib-sysfs.c
+@@ -557,7 +557,7 @@ static struct class gpio_class = {
+  *
+  * Returns zero on success, else an error.
+  */
+-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
+ {
+ 	struct gpio_chip	*chip;
+ 	struct gpio_device	*gdev;
+@@ -619,6 +619,8 @@ int gpiod_export(struct gpio_desc *desc,
+ 	offset = gpio_chip_hwgpio(desc);
+ 	if (chip->names && chip->names[offset])
+ 		ioname = chip->names[offset];
++	if (name)
++		ioname = name;
+ 
+ 	dev = device_create_with_groups(&gpio_class, &gdev->dev,
+ 					MKDEV(0, 0), data, gpio_groups,
+@@ -640,8 +642,21 @@ err_unlock:
+ 	gpiod_dbg(desc, "%s: status %d\n", __func__, status);
+ 	return status;
+ }
++EXPORT_SYMBOL_GPL(__gpiod_export);
++
++int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++{
++	return __gpiod_export(desc, direction_may_change, NULL);
++}
+ EXPORT_SYMBOL_GPL(gpiod_export);
+ 
++int gpio_export_with_name(struct gpio_desc *desc, bool direction_may_change,
++			  const char *name)
++{
++	return __gpiod_export(desc, direction_may_change, name);
++}
++EXPORT_SYMBOL_GPL(gpio_export_with_name);
++
+ static int match_export(struct device *dev, const void *desc)
+ {
+ 	struct gpiod_data *data = dev_get_drvdata(dev);
diff --git a/target/linux/generic/hack-6.6/902-debloat_proc.patch b/target/linux/generic/hack-6.6/902-debloat_proc.patch
new file mode 100644
index 00000000000000..d3bf39091f04e7
--- /dev/null
+++ b/target/linux/generic/hack-6.6/902-debloat_proc.patch
@@ -0,0 +1,408 @@
+From 9e3f1d0805b2d919904dd9a4ff0d956314cc3cba Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 8 Jul 2017 08:20:09 +0200
+Subject: debloat: procfs
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ fs/locks.c               |  2 ++
+ fs/proc/Kconfig          |  5 +++++
+ fs/proc/consoles.c       |  3 +++
+ fs/proc/proc_tty.c       | 11 ++++++++++-
+ include/net/snmp.h       | 18 +++++++++++++++++-
+ ipc/msg.c                |  3 +++
+ ipc/sem.c                |  2 ++
+ ipc/shm.c                |  2 ++
+ ipc/util.c               |  3 +++
+ kernel/exec_domain.c     |  2 ++
+ kernel/irq/proc.c        |  9 +++++++++
+ kernel/time/timer_list.c |  2 ++
+ mm/vmalloc.c             |  2 ++
+ mm/vmstat.c              |  8 +++++---
+ net/8021q/vlanproc.c     |  6 ++++++
+ net/core/net-procfs.c    | 18 ++++++++++++------
+ net/core/sock.c          |  2 ++
+ net/ipv4/fib_trie.c      | 18 ++++++++++++------
+ net/ipv4/proc.c          |  3 +++
+ net/ipv4/route.c         |  3 +++
+ 20 files changed, 105 insertions(+), 17 deletions(-)
+
+--- a/fs/locks.c
++++ b/fs/locks.c
+@@ -2897,6 +2897,8 @@ static const struct seq_operations locks
+ 
+ static int __init proc_locks_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
+ 	proc_create_seq_private("locks", 0, NULL, &locks_seq_operations,
+ 			sizeof(struct locks_iterator), NULL);
+ 	return 0;
+--- a/fs/proc/Kconfig
++++ b/fs/proc/Kconfig
+@@ -101,6 +101,11 @@ config PROC_CHILDREN
+ 	  Say Y if you are running any user-space software which takes benefit from
+ 	  this interface. For example, rkt is such a piece of software.
+ 
++config PROC_STRIPPED
++	default n
++	depends on EXPERT
++	bool "Strip non-essential /proc functionality to reduce code size"
++
+ config PROC_PID_ARCH_STATUS
+ 	def_bool n
+ 	depends on PROC_FS
+--- a/fs/proc/consoles.c
++++ b/fs/proc/consoles.c
+@@ -107,6 +107,9 @@ static const struct seq_operations conso
+ 
+ static int __init proc_consoles_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
++
+ 	proc_create_seq("consoles", 0, NULL, &consoles_op);
+ 	return 0;
+ }
+--- a/fs/proc/proc_tty.c
++++ b/fs/proc/proc_tty.c
+@@ -131,7 +131,10 @@ static const struct seq_operations tty_d
+ void proc_tty_register_driver(struct tty_driver *driver)
+ {
+ 	struct proc_dir_entry *ent;
+-		
++
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
++
+ 	if (!driver->driver_name || driver->proc_entry ||
+ 	    !driver->ops->proc_show)
+ 		return;
+@@ -148,6 +151,9 @@ void proc_tty_unregister_driver(struct t
+ {
+ 	struct proc_dir_entry *ent;
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
++
+ 	ent = driver->proc_entry;
+ 	if (!ent)
+ 		return;
+@@ -162,6 +168,9 @@ void proc_tty_unregister_driver(struct t
+  */
+ void __init proc_tty_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
++
+ 	if (!proc_mkdir("tty", NULL))
+ 		return;
+ 	proc_mkdir("tty/ldisc", NULL);	/* Preserved: it's userspace visible */
+--- a/include/net/snmp.h
++++ b/include/net/snmp.h
+@@ -124,6 +124,21 @@ struct linux_tls_mib {
+ #define DECLARE_SNMP_STAT(type, name)	\
+ 	extern __typeof__(type) __percpu *name
+ 
++#ifdef CONFIG_PROC_STRIPPED
++#define __SNMP_STATS_DUMMY(mib)	\
++	do { (void) mib->mibs[0]; } while(0)
++
++#define __SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)
++#define SNMP_INC_STATS_ATOMIC_LONG(mib, field) __SNMP_STATS_DUMMY(mib)
++#define SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)
++#define SNMP_DEC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)
++#define __SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib)
++#define SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib)
++#define SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib)
++#define __SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib)
++
++#else
++
+ #define __SNMP_INC_STATS(mib, field)	\
+ 			__this_cpu_inc(mib->mibs[field])
+ 
+@@ -154,8 +169,9 @@ struct linux_tls_mib {
+ 		__this_cpu_add(ptr[basefield##OCTETS], addend);	\
+ 	} while (0)
+ 
++#endif
+ 
+-#if BITS_PER_LONG==32
++#if (BITS_PER_LONG==32) && !defined(CONFIG_PROC_STRIPPED)
+ 
+ #define __SNMP_ADD_STATS64(mib, field, addend) 				\
+ 	do {								\
+--- a/ipc/msg.c
++++ b/ipc/msg.c
+@@ -1370,6 +1370,9 @@ void __init msg_init(void)
+ {
+ 	msg_init_ns(&init_ipc_ns);
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
++
+ 	ipc_init_proc_interface("sysvipc/msg",
+ 				"       key      msqid perms      cbytes       qnum lspid lrpid   uid   gid  cuid  cgid      stime      rtime      ctime\n",
+ 				IPC_MSG_IDS, sysvipc_msg_proc_show);
+--- a/ipc/sem.c
++++ b/ipc/sem.c
+@@ -268,6 +268,8 @@ void sem_exit_ns(struct ipc_namespace *n
+ void __init sem_init(void)
+ {
+ 	sem_init_ns(&init_ipc_ns);
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
+ 	ipc_init_proc_interface("sysvipc/sem",
+ 				"       key      semid perms      nsems   uid   gid  cuid  cgid      otime      ctime\n",
+ 				IPC_SEM_IDS, sysvipc_sem_proc_show);
+--- a/ipc/shm.c
++++ b/ipc/shm.c
+@@ -154,6 +154,8 @@ pure_initcall(ipc_ns_init);
+ 
+ void __init shm_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
+ 	ipc_init_proc_interface("sysvipc/shm",
+ #if BITS_PER_LONG <= 32
+ 				"       key      shmid perms       size  cpid  lpid nattch   uid   gid  cuid  cgid      atime      dtime      ctime        rss       swap\n",
+--- a/ipc/util.c
++++ b/ipc/util.c
+@@ -141,6 +141,9 @@ void __init ipc_init_proc_interface(cons
+ 	struct proc_dir_entry *pde;
+ 	struct ipc_proc_iface *iface;
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
++
+ 	iface = kmalloc(sizeof(*iface), GFP_KERNEL);
+ 	if (!iface)
+ 		return;
+--- a/kernel/exec_domain.c
++++ b/kernel/exec_domain.c
+@@ -29,6 +29,8 @@ static int execdomains_proc_show(struct
+ 
+ static int __init proc_execdomains_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
+ 	proc_create_single("execdomains", 0, NULL, execdomains_proc_show);
+ 	return 0;
+ }
+--- a/kernel/irq/proc.c
++++ b/kernel/irq/proc.c
+@@ -341,6 +341,9 @@ void register_irq_proc(unsigned int irq,
+ 	void __maybe_unused *irqp = (void *)(unsigned long) irq;
+ 	char name [MAX_NAMELEN];
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))
++		return;
++
+ 	if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip))
+ 		return;
+ 
+@@ -394,6 +397,9 @@ void unregister_irq_proc(unsigned int ir
+ {
+ 	char name [MAX_NAMELEN];
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))
++		return;
++
+ 	if (!root_irq_dir || !desc->dir)
+ 		return;
+ #ifdef CONFIG_SMP
+@@ -432,6 +438,9 @@ void init_irq_proc(void)
+ 	unsigned int irq;
+ 	struct irq_desc *desc;
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))
++		return;
++
+ 	/* create /proc/irq */
+ 	root_irq_dir = proc_mkdir("irq", NULL);
+ 	if (!root_irq_dir)
+--- a/kernel/time/timer_list.c
++++ b/kernel/time/timer_list.c
+@@ -350,6 +350,8 @@ static int __init init_timer_list_procfs
+ {
+ 	struct proc_dir_entry *pe;
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
+ 	pe = proc_create_seq_private("timer_list", 0400, NULL, &timer_list_sops,
+ 			sizeof(struct timer_list_iter), NULL);
+ 	if (!pe)
+--- a/mm/vmalloc.c
++++ b/mm/vmalloc.c
+@@ -4439,6 +4439,8 @@ static const struct seq_operations vmall
+ 
+ static int __init proc_vmalloc_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
+ 	if (IS_ENABLED(CONFIG_NUMA))
+ 		proc_create_seq_private("vmallocinfo", 0400, NULL,
+ 				&vmalloc_op,
+--- a/mm/vmstat.c
++++ b/mm/vmstat.c
+@@ -2135,10 +2135,12 @@ void __init init_mm_internals(void)
+ 	start_shepherd_timer();
+ #endif
+ #ifdef CONFIG_PROC_FS
+-	proc_create_seq("buddyinfo", 0444, NULL, &fragmentation_op);
+-	proc_create_seq("pagetypeinfo", 0400, NULL, &pagetypeinfo_op);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {
++		proc_create_seq("buddyinfo", 0444, NULL, &fragmentation_op);
++		proc_create_seq("pagetypeinfo", 0400, NULL, &pagetypeinfo_op);
++		proc_create_seq("zoneinfo", 0444, NULL, &zoneinfo_op);
++	}
+ 	proc_create_seq("vmstat", 0444, NULL, &vmstat_op);
+-	proc_create_seq("zoneinfo", 0444, NULL, &zoneinfo_op);
+ #endif
+ }
+ 
+--- a/net/8021q/vlanproc.c
++++ b/net/8021q/vlanproc.c
+@@ -93,6 +93,9 @@ void vlan_proc_cleanup(struct net *net)
+ {
+ 	struct vlan_net *vn = net_generic(net, vlan_net_id);
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return;
++
+ 	if (vn->proc_vlan_conf)
+ 		remove_proc_entry(name_conf, vn->proc_vlan_dir);
+ 
+@@ -112,6 +115,9 @@ int __net_init vlan_proc_init(struct net
+ {
+ 	struct vlan_net *vn = net_generic(net, vlan_net_id);
+ 
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
++
+ 	vn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net);
+ 	if (!vn->proc_vlan_dir)
+ 		goto err;
+--- a/net/core/net-procfs.c
++++ b/net/core/net-procfs.c
+@@ -327,10 +327,12 @@ static int __net_init dev_proc_net_init(
+ 	if (!proc_create_net("dev", 0444, net->proc_net, &dev_seq_ops,
+ 			sizeof(struct seq_net_private)))
+ 		goto out;
+-	if (!proc_create_seq("softnet_stat", 0444, net->proc_net,
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&
++			!proc_create_seq("softnet_stat", 0444, net->proc_net,
+ 			 &softnet_seq_ops))
+ 		goto out_dev;
+-	if (!proc_create_net("ptype", 0444, net->proc_net, &ptype_seq_ops,
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&
++			!proc_create_net("ptype", 0444, net->proc_net, &ptype_seq_ops,
+ 			sizeof(struct seq_net_private)))
+ 		goto out_softnet;
+ 
+@@ -340,9 +342,11 @@ static int __net_init dev_proc_net_init(
+ out:
+ 	return rc;
+ out_ptype:
+-	remove_proc_entry("ptype", net->proc_net);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED))
++		remove_proc_entry("ptype", net->proc_net);
+ out_softnet:
+-	remove_proc_entry("softnet_stat", net->proc_net);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED))
++		remove_proc_entry("softnet_stat", net->proc_net);
+ out_dev:
+ 	remove_proc_entry("dev", net->proc_net);
+ 	goto out;
+@@ -352,8 +356,10 @@ static void __net_exit dev_proc_net_exit
+ {
+ 	wext_proc_exit(net);
+ 
+-	remove_proc_entry("ptype", net->proc_net);
+-	remove_proc_entry("softnet_stat", net->proc_net);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {
++		remove_proc_entry("ptype", net->proc_net);
++		remove_proc_entry("softnet_stat", net->proc_net);
++	}
+ 	remove_proc_entry("dev", net->proc_net);
+ }
+ 
+--- a/net/core/sock.c
++++ b/net/core/sock.c
+@@ -4124,6 +4124,8 @@ static __net_initdata struct pernet_oper
+ 
+ static int __init proto_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
+ 	return register_pernet_subsys(&proto_net_ops);
+ }
+ 
+--- a/net/ipv4/fib_trie.c
++++ b/net/ipv4/fib_trie.c
+@@ -3036,11 +3036,13 @@ static const struct seq_operations fib_r
+ 
+ int __net_init fib_proc_init(struct net *net)
+ {
+-	if (!proc_create_net("fib_trie", 0444, net->proc_net, &fib_trie_seq_ops,
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&
++			!proc_create_net("fib_trie", 0444, net->proc_net, &fib_trie_seq_ops,
+ 			sizeof(struct fib_trie_iter)))
+ 		goto out1;
+ 
+-	if (!proc_create_net_single("fib_triestat", 0444, net->proc_net,
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&
++			!proc_create_net_single("fib_triestat", 0444, net->proc_net,
+ 			fib_triestat_seq_show, NULL))
+ 		goto out2;
+ 
+@@ -3051,17 +3053,21 @@ int __net_init fib_proc_init(struct net
+ 	return 0;
+ 
+ out3:
+-	remove_proc_entry("fib_triestat", net->proc_net);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED))
++		remove_proc_entry("fib_triestat", net->proc_net);
+ out2:
+-	remove_proc_entry("fib_trie", net->proc_net);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED))
++		remove_proc_entry("fib_trie", net->proc_net);
+ out1:
+ 	return -ENOMEM;
+ }
+ 
+ void __net_exit fib_proc_exit(struct net *net)
+ {
+-	remove_proc_entry("fib_trie", net->proc_net);
+-	remove_proc_entry("fib_triestat", net->proc_net);
++	if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {
++		remove_proc_entry("fib_trie", net->proc_net);
++		remove_proc_entry("fib_triestat", net->proc_net);
++	}
+ 	remove_proc_entry("route", net->proc_net);
+ }
+ 
+--- a/net/ipv4/proc.c
++++ b/net/ipv4/proc.c
+@@ -556,5 +556,8 @@ static __net_initdata struct pernet_oper
+ 
+ int __init ip_misc_proc_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
++
+ 	return register_pernet_subsys(&ip_proc_ops);
+ }
+--- a/net/ipv4/route.c
++++ b/net/ipv4/route.c
+@@ -380,6 +380,9 @@ static struct pernet_operations ip_rt_pr
+ 
+ static int __init ip_rt_proc_init(void)
+ {
++	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
++		return 0;
++
+ 	return register_pernet_subsys(&ip_rt_proc_ops);
+ }
+ 
diff --git a/target/linux/generic/hack-6.6/904-debloat_dma_buf.patch b/target/linux/generic/hack-6.6/904-debloat_dma_buf.patch
new file mode 100644
index 00000000000000..2146edec35950b
--- /dev/null
+++ b/target/linux/generic/hack-6.6/904-debloat_dma_buf.patch
@@ -0,0 +1,93 @@
+From e3692cb2fcd5ba1244512a0f43b8118f65f1c375 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 8 Jul 2017 08:20:43 +0200
+Subject: debloat: dmabuf
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/base/Kconfig      |  2 +-
+ drivers/dma-buf/Makefile  | 10 +++++++---
+ drivers/dma-buf/dma-buf.c |  4 +++-
+ kernel/sched/core.c       |  1 +
+ 4 files changed, 12 insertions(+), 5 deletions(-)
+
+--- a/drivers/base/Kconfig
++++ b/drivers/base/Kconfig
+@@ -198,7 +198,7 @@ config SOC_BUS
+ source "drivers/base/regmap/Kconfig"
+ 
+ config DMA_SHARED_BUFFER
+-	bool
++	tristate "DMA_SHARED_BUFFER"
+ 	default n
+ 	select IRQ_WORK
+ 	help
+--- a/drivers/dma-buf/heaps/Makefile
++++ b/drivers/dma-buf/heaps/Makefile
+@@ -1,3 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
+-obj-$(CONFIG_DMABUF_HEAPS_SYSTEM)	+= system_heap.o
+-obj-$(CONFIG_DMABUF_HEAPS_CMA)		+= cma_heap.o
++dma-buf-objs-$(CONFIG_DMABUF_HEAPS_SYSTEM)	+= system_heap.o
++dma-buf-objs-$(CONFIG_DMABUF_HEAPS_CMA)		+= cma_heap.o
+--- a/drivers/dma-buf/Makefile
++++ b/drivers/dma-buf/Makefile
+@@ -1,12 +1,14 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
++obj-$(CONFIG_DMA_SHARED_BUFFER) := dma-shared-buffer.o
++
++dma-buf-objs-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
+ 	 dma-fence-unwrap.o dma-resv.o
+-obj-$(CONFIG_DMABUF_HEAPS)	+= dma-heap.o
+-obj-$(CONFIG_DMABUF_HEAPS)	+= heaps/
+-obj-$(CONFIG_SYNC_FILE)		+= sync_file.o
+-obj-$(CONFIG_SW_SYNC)		+= sw_sync.o sync_debug.o
+-obj-$(CONFIG_UDMABUF)		+= udmabuf.o
+-obj-$(CONFIG_DMABUF_SYSFS_STATS) += dma-buf-sysfs-stats.o
++dma-buf-objs-$(CONFIG_DMABUF_HEAPS)	+= dma-heap.o
++obj-$(CONFIG_DMABUF_HEAPS)		+= heaps/
++dma-buf-objs-$(CONFIG_SYNC_FILE)	+= sync_file.o
++dma-buf-objs-$(CONFIG_SW_SYNC)		+= sw_sync.o sync_debug.o
++dma-buf-objs-$(CONFIG_UDMABUF)		+= udmabuf.o
++dma-buf-objs-$(CONFIG_DMABUF_SYSFS_STATS) += dma-buf-sysfs-stats.o
+ 
+ dmabuf_selftests-y := \
+ 	selftest.o \
+@@ -15,4 +17,6 @@ dmabuf_selftests-y := \
+ 	st-dma-fence-unwrap.o \
+ 	st-dma-resv.o
+ 
+-obj-$(CONFIG_DMABUF_SELFTESTS)	+= dmabuf_selftests.o
++dma-buf-objs-$(CONFIG_DMABUF_SELFTESTS)	+= dmabuf_selftests.o
++
++dma-shared-buffer-objs :=  $(dma-buf-objs-y)
+--- a/drivers/dma-buf/dma-buf.c
++++ b/drivers/dma-buf/dma-buf.c
+@@ -1731,4 +1731,5 @@ static void __exit dma_buf_deinit(void)
+ 	kern_unmount(dma_buf_mnt);
+ 	dma_buf_uninit_sysfs_statistics();
+ }
+-__exitcall(dma_buf_deinit);
++module_exit(dma_buf_deinit);
++MODULE_LICENSE("GPL");
+--- a/kernel/sched/core.c
++++ b/kernel/sched/core.c
+@@ -4487,6 +4487,7 @@ int wake_up_state(struct task_struct *p,
+ {
+ 	return try_to_wake_up(p, state, 0);
+ }
++EXPORT_SYMBOL_GPL(wake_up_state);
+ 
+ /*
+  * Perform scheduler related setup for a newly forked process p.
+--- a/fs/d_path.c
++++ b/fs/d_path.c
+@@ -314,6 +314,7 @@ char *dynamic_dname(char *buffer, int bu
+ 	buffer += buflen - sz;
+ 	return memcpy(buffer, temp, sz);
+ }
++EXPORT_SYMBOL_GPL(dynamic_dname);
+ 
+ char *simple_dname(struct dentry *dentry, char *buffer, int buflen)
+ {
diff --git a/target/linux/generic/hack-6.6/910-kobject_uevent.patch b/target/linux/generic/hack-6.6/910-kobject_uevent.patch
new file mode 100644
index 00000000000000..c4c41ca400ae32
--- /dev/null
+++ b/target/linux/generic/hack-6.6/910-kobject_uevent.patch
@@ -0,0 +1,32 @@
+From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 16 Jul 2017 16:56:10 +0200
+Subject: lib: add uevent_next_seqnum()
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/linux/kobject.h |  5 +++++
+ lib/kobject_uevent.c    | 37 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 42 insertions(+)
+
+--- a/lib/kobject_uevent.c
++++ b/lib/kobject_uevent.c
+@@ -179,6 +179,18 @@ out:
+ 	return r;
+ }
+ 
++u64 uevent_next_seqnum(void)
++{
++	u64 seq;
++
++	mutex_lock(&uevent_sock_mutex);
++	seq = ++uevent_seqnum;
++	mutex_unlock(&uevent_sock_mutex);
++
++	return seq;
++}
++EXPORT_SYMBOL_GPL(uevent_next_seqnum);
++
+ /**
+  * kobject_synth_uevent - send synthetic uevent with arguments
+  *
diff --git a/target/linux/generic/hack-6.6/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/hack-6.6/911-kobject_add_broadcast_uevent.patch
new file mode 100644
index 00000000000000..7a21e73daee9b4
--- /dev/null
+++ b/target/linux/generic/hack-6.6/911-kobject_add_broadcast_uevent.patch
@@ -0,0 +1,76 @@
+From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 16 Jul 2017 16:56:10 +0200
+Subject: lib: add uevent_next_seqnum()
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/linux/kobject.h |  5 +++++
+ lib/kobject_uevent.c    | 37 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 42 insertions(+)
+
+--- a/include/linux/kobject.h
++++ b/include/linux/kobject.h
+@@ -32,6 +32,8 @@
+ #define UEVENT_NUM_ENVP			64	/* number of env pointers */
+ #define UEVENT_BUFFER_SIZE		2048	/* buffer for the variables */
+ 
++struct sk_buff;
++
+ #ifdef CONFIG_UEVENT_HELPER
+ /* path to the userspace helper executed on an event */
+ extern char uevent_helper[];
+@@ -219,4 +221,7 @@ int kobject_synth_uevent(struct kobject
+ __printf(2, 3)
+ int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...);
+ 
++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,
++		     gfp_t allocation);
++
+ #endif /* _KOBJECT_H_ */
+--- a/lib/kobject_uevent.c
++++ b/lib/kobject_uevent.c
+@@ -691,6 +691,43 @@ int add_uevent_var(struct kobj_uevent_en
+ EXPORT_SYMBOL_GPL(add_uevent_var);
+ 
+ #if defined(CONFIG_NET)
++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,
++		     gfp_t allocation)
++{
++	struct uevent_sock *ue_sk;
++	int err = 0;
++
++	/* send netlink message */
++	mutex_lock(&uevent_sock_mutex);
++	list_for_each_entry(ue_sk, &uevent_sock_list, list) {
++		struct sock *uevent_sock = ue_sk->sk;
++		struct sk_buff *skb2;
++
++		skb2 = skb_clone(skb, allocation);
++		if (!skb2)
++			break;
++
++		err = netlink_broadcast(uevent_sock, skb2, pid, group,
++					allocation);
++		if (err)
++			break;
++	}
++	mutex_unlock(&uevent_sock_mutex);
++
++	kfree_skb(skb);
++	return err;
++}
++#else
++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,
++		     gfp_t allocation)
++{
++	kfree_skb(skb);
++	return 0;
++}
++#endif
++EXPORT_SYMBOL_GPL(broadcast_uevent);
++
++#if defined(CONFIG_NET)
+ static int uevent_net_broadcast(struct sock *usk, struct sk_buff *skb,
+ 				struct netlink_ext_ack *extack)
+ {
diff --git a/target/linux/generic/hack-6.6/920-device_tree_cmdline.patch b/target/linux/generic/hack-6.6/920-device_tree_cmdline.patch
new file mode 100644
index 00000000000000..dcceb0a7dc5e33
--- /dev/null
+++ b/target/linux/generic/hack-6.6/920-device_tree_cmdline.patch
@@ -0,0 +1,12 @@
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1185,6 +1185,9 @@ int __init early_init_dt_scan_chosen(cha
+ 	p = of_get_flat_dt_prop(node, "bootargs", &l);
+ 	if (p != NULL && l > 0)
+ 		strscpy(cmdline, p, min(l, COMMAND_LINE_SIZE));
++	p = of_get_flat_dt_prop(node, "bootargs-append", &l);
++	if (p != NULL && l > 0)
++		strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
+ 
+ handle_cmdline:
+ 	/*
diff --git a/target/linux/generic/hack-6.6/952-add-net-conntrack-events-support-multiple-registrant.patch b/target/linux/generic/hack-6.6/952-add-net-conntrack-events-support-multiple-registrant.patch
new file mode 100644
index 00000000000000..b9fbe68776a9a1
--- /dev/null
+++ b/target/linux/generic/hack-6.6/952-add-net-conntrack-events-support-multiple-registrant.patch
@@ -0,0 +1,352 @@
+From 42824d4b753f84ccf885eca602c5037338b546c8 Mon Sep 17 00:00:00 2001
+From: Zhi Chen <zhichen@codeaurora.org>
+Date: Tue, 13 Jan 2015 14:28:18 -0800
+Subject: [PATCH 3/3] net: conntrack events, support multiple registrant
+
+Merging this patch from kernel 3.4:
+This was supported by old (.28) kernel versions but removed
+because of it's overhead.
+But we need this feature for NA connection manager. Both ipv4
+and ipv6 modules needs to register themselves to ct events.
+
+Change-Id: Iebfb254590fb594f5baf232f849d1b7ae45ef757
+Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
+---
+ include/net/netfilter/nf_conntrack_ecache.h |  15 ++-
+ include/net/netns/conntrack.h               |   3 +
+ net/netfilter/Kconfig                       |   8 ++
+ net/netfilter/nf_conntrack_core.c           |   4 +
+ net/netfilter/nf_conntrack_ecache.c         | 103 +++++++++++++++++++-
+ net/netfilter/nf_conntrack_netlink.c        |  17 ++++
+ 6 files changed, 146 insertions(+), 4 deletions(-)
+
+--- a/include/net/netfilter/nf_conntrack_ecache.h
++++ b/include/net/netfilter/nf_conntrack_ecache.h
+@@ -65,9 +65,14 @@ struct nf_ct_event_notifier {
+ 	int (*exp_event)(unsigned int events, const struct nf_exp_event *item);
+ };
+ 
+-void nf_conntrack_register_notifier(struct net *net,
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++extern int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb);
++extern int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb);
++#else
++int nf_conntrack_register_notifier(struct net *net,
+ 				   const struct nf_ct_event_notifier *nb);
+ void nf_conntrack_unregister_notifier(struct net *net);
++#endif
+ 
+ void nf_ct_deliver_cached_events(struct nf_conn *ct);
+ int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
+@@ -98,11 +103,13 @@ static inline void
+ nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
+ {
+ #ifdef CONFIG_NF_CONNTRACK_EVENTS
+-	struct net *net = nf_ct_net(ct);
+ 	struct nf_conntrack_ecache *e;
++#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	struct net *net = nf_ct_net(ct);
+ 
+ 	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
+ 		return;
++#endif
+ 
+ 	e = nf_ct_ecache_find(ct);
+ 	if (e == NULL)
+@@ -117,20 +124,34 @@ nf_conntrack_event_report(enum ip_conntr
+ 			  u32 portid, int report)
+ {
+ #ifdef CONFIG_NF_CONNTRACK_EVENTS
+-	if (nf_ct_ecache_exist(ct))
+-		return nf_conntrack_eventmask_report(1 << event, ct, portid, report);
++#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	const struct net *net = nf_ct_net(ct);
++
++	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
++		return 0;
+ #endif
++
++	return nf_conntrack_eventmask_report(1 << event, ct, portid, report);
++#else
+ 	return 0;
++#endif
+ }
+ 
+ static inline int
+ nf_conntrack_event(enum ip_conntrack_events event, struct nf_conn *ct)
+ {
+ #ifdef CONFIG_NF_CONNTRACK_EVENTS
+-	if (nf_ct_ecache_exist(ct))
+-		return nf_conntrack_eventmask_report(1 << event, ct, 0, 0);
++#ifndef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	const struct net *net = nf_ct_net(ct);
++
++	if (!rcu_access_pointer(net->ct.nf_conntrack_event_cb))
++		return 0;
+ #endif
++
++	return nf_conntrack_eventmask_report(1 << event, ct, 0, 0);
++#else
+ 	return 0;
++#endif
+ }
+ 
+ #ifdef CONFIG_NF_CONNTRACK_EVENTS
+--- a/include/net/netns/conntrack.h
++++ b/include/net/netns/conntrack.h
+@@ -105,6 +105,9 @@ struct netns_ct {
+ 	u8			sysctl_checksum;
+ 
+ 	struct ip_conntrack_stat __percpu *stat;
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	struct atomic_notifier_head nf_conntrack_chain;
++#endif
+ 	struct nf_ct_event_notifier __rcu *nf_conntrack_event_cb;
+ 	struct nf_ip_net	nf_ct_proto;
+ #if defined(CONFIG_NF_CONNTRACK_LABELS)
+--- a/net/netfilter/Kconfig
++++ b/net/netfilter/Kconfig
+@@ -164,6 +164,14 @@ config NF_CONNTRACK_EVENTS
+ 
+ 	  If unsure, say `N'.
+ 
++config NF_CONNTRACK_CHAIN_EVENTS
++	bool "Register multiple callbacks to ct events"
++	depends on NF_CONNTRACK_EVENTS
++	help
++	  Support multiple registrations.
++
++	  If unsure, say `N'.
++
+ config NF_CONNTRACK_TIMEOUT
+ 	bool  'Connection tracking timeout'
+ 	depends on NETFILTER_ADVANCED
+--- a/net/netfilter/nf_conntrack_core.c
++++ b/net/netfilter/nf_conntrack_core.c
+@@ -2800,6 +2800,10 @@ int nf_conntrack_init_net(struct net *ne
+ 	nf_conntrack_ecache_pernet_init(net);
+ 	nf_conntrack_proto_pernet_init(net);
+ 
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	ATOMIC_INIT_NOTIFIER_HEAD(&net->ct.nf_conntrack_chain);
++#endif
++
+ 	return 0;
+ 
+ err_expect:
+--- a/net/netfilter/nf_conntrack_ecache.c
++++ b/net/netfilter/nf_conntrack_ecache.c
+@@ -17,6 +17,9 @@
+ #include <linux/stddef.h>
+ #include <linux/err.h>
+ #include <linux/kernel.h>
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++#include <linux/notifier.h>
++#endif
+ #include <linux/netdevice.h>
+ #include <linux/slab.h>
+ #include <linux/export.h>
+@@ -162,6 +165,35 @@ static int __nf_conntrack_eventmask_repo
+ 	return ret;
+ }
+ 
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
++				  u32 portid, int report)
++{
++	struct nf_conntrack_ecache *e;
++	struct net *net = nf_ct_net(ct);
++
++	e = nf_ct_ecache_find(ct);
++	if (e == NULL)
++		return 0;
++
++	if (nf_ct_is_confirmed(ct)) {
++		struct nf_ct_event item = {
++			.ct = ct,
++			.portid	= e->portid ? e->portid : portid,
++			.report = report
++		};
++		/* This is a resent of a destroy event? If so, skip missed */
++		unsigned long missed = e->portid ? 0 : e->missed;
++
++		if (!((eventmask | missed) & e->ctmask))
++			return 0;
++
++		atomic_notifier_call_chain(&net->ct.nf_conntrack_chain, eventmask | missed, &item);
++	}
++
++	return 0;
++}
++#else
+ int nf_conntrack_eventmask_report(unsigned int events, struct nf_conn *ct,
+ 				  u32 portid, int report)
+ {
+@@ -197,10 +229,52 @@ int nf_conntrack_eventmask_report(unsign
+ 
+ 	return ret;
+ }
++#endif
+ EXPORT_SYMBOL_GPL(nf_conntrack_eventmask_report);
+ 
+ /* deliver cached events and clear cache entry - must be called with locally
+  * disabled softirqs */
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++void nf_ct_deliver_cached_events(struct nf_conn *ct)
++{
++	unsigned long events, missed;
++	struct nf_conntrack_ecache *e;
++	struct nf_ct_event item;
++	struct net *net = nf_ct_net(ct);
++
++	e = nf_ct_ecache_find(ct);
++	if (e == NULL)
++		return;
++
++	events = xchg(&e->cache, 0);
++
++	if (!nf_ct_is_confirmed(ct) || nf_ct_is_dying(ct) || !events)
++		return;
++
++	/* We make a copy of the missed event cache without taking
++	 * the lock, thus we may send missed events twice. However,
++	 * this does not harm and it happens very rarely. */
++	missed = e->missed;
++
++	if (!((events | missed) & e->ctmask))
++		return;
++
++	item.ct = ct;
++	item.portid = 0;
++	item.report = 0;
++
++	atomic_notifier_call_chain(&net->ct.nf_conntrack_chain,
++			events | missed,
++			&item);
++
++	if (likely(!missed))
++		return;
++
++	spin_lock_bh(&ct->lock);
++		e->missed &= ~missed;
++	spin_unlock_bh(&ct->lock);
++}
++#else
+ void nf_ct_deliver_cached_events(struct nf_conn *ct)
+ {
+ 	struct nf_conntrack_ecache *e;
+@@ -226,6 +300,7 @@ void nf_ct_deliver_cached_events(struct
+ 	 */
+ 	__nf_conntrack_eventmask_report(e, events, e->missed, &item);
+ }
++#endif
+ EXPORT_SYMBOL_GPL(nf_ct_deliver_cached_events);
+ 
+ void nf_ct_expect_event_report(enum ip_conntrack_expect_events event,
+@@ -258,20 +333,43 @@ out_unlock:
+ 	rcu_read_unlock();
+ }
+ 
+-void nf_conntrack_register_notifier(struct net *net,
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++int nf_conntrack_register_notifier(struct net *net,
++				   struct notifier_block *nb)
++{
++	return atomic_notifier_chain_register(&net->ct.nf_conntrack_chain, nb);
++}
++#else
++int nf_conntrack_register_notifier(struct net *net,
+ 				    const struct nf_ct_event_notifier *new)
+ {
++	int ret;
+ 	struct nf_ct_event_notifier *notify;
+ 
+ 	mutex_lock(&nf_ct_ecache_mutex);
+ 	notify = rcu_dereference_protected(net->ct.nf_conntrack_event_cb,
+ 					   lockdep_is_held(&nf_ct_ecache_mutex));
+ 	WARN_ON_ONCE(notify);
++	if (notify != NULL) {
++		ret = -EBUSY;
++		goto out_unlock;
++	}
++
+ 	rcu_assign_pointer(net->ct.nf_conntrack_event_cb, new);
+-	mutex_unlock(&nf_ct_ecache_mutex);
++	ret = 0;
++out_unlock:
++ 	mutex_unlock(&nf_ct_ecache_mutex);
++	return ret;
+ }
++#endif
+ EXPORT_SYMBOL_GPL(nf_conntrack_register_notifier);
+ 
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb)
++{
++	return atomic_notifier_chain_unregister(&net->ct.nf_conntrack_chain, nb);
++}
++#else
+ void nf_conntrack_unregister_notifier(struct net *net)
+ {
+ 	mutex_lock(&nf_ct_ecache_mutex);
+@@ -279,6 +377,7 @@ void nf_conntrack_unregister_notifier(st
+ 	mutex_unlock(&nf_ct_ecache_mutex);
+ 	/* synchronize_rcu() is called after netns pre_exit */
+ }
++#endif
+ EXPORT_SYMBOL_GPL(nf_conntrack_unregister_notifier);
+ 
+ void nf_conntrack_ecache_work(struct net *net, enum nf_ct_ecache_state state)
+--- a/net/netfilter/nf_conntrack_netlink.c
++++ b/net/netfilter/nf_conntrack_netlink.c
+@@ -723,12 +723,19 @@ static size_t ctnetlink_nlmsg_size(const
+ }
+ 
+ static int
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++ctnetlink_conntrack_event(struct notifier_block *this, unsigned long events, void *ptr)
++#else
+ ctnetlink_conntrack_event(unsigned int events, const struct nf_ct_event *item)
++#endif
+ {
+ 	const struct nf_conntrack_zone *zone;
+ 	struct net *net;
+ 	struct nlmsghdr *nlh;
+ 	struct nlattr *nest_parms;
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	struct nf_ct_event *item = (struct nf_ct_event *)ptr;
++#endif
+ 	struct nf_conn *ct = item->ct;
+ 	struct sk_buff *skb;
+ 	unsigned int type;
+@@ -3750,11 +3757,17 @@ static int ctnetlink_stat_exp_cpu(struct
+ }
+ 
+ #ifdef CONFIG_NF_CONNTRACK_EVENTS
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++static struct notifier_block ctnl_notifier = {
++	.notifier_call = ctnetlink_conntrack_event
++};
++#else
+ static struct nf_ct_event_notifier ctnl_notifier = {
+ 	.ct_event = ctnetlink_conntrack_event,
+ 	.exp_event = ctnetlink_expect_event,
+ };
+ #endif
++#endif
+ 
+ static const struct nfnl_callback ctnl_cb[IPCTNL_MSG_MAX] = {
+ 	[IPCTNL_MSG_CT_NEW]	= {
+@@ -3853,8 +3866,12 @@ static int __net_init ctnetlink_net_init
+ static void ctnetlink_net_pre_exit(struct net *net)
+ {
+ #ifdef CONFIG_NF_CONNTRACK_EVENTS
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	nf_conntrack_unregister_notifier(net,&ctnl_notifier);
++#else
+ 	nf_conntrack_unregister_notifier(net);
+ #endif
++#endif
+ }
+ 
+ static struct pernet_operations ctnetlink_net_ops = {
diff --git a/target/linux/generic/hack-6.6/953-net-patch-linux-kernel-to-support-shortcut-fe.patch b/target/linux/generic/hack-6.6/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
new file mode 100644
index 00000000000000..614766aad714f3
--- /dev/null
+++ b/target/linux/generic/hack-6.6/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -0,0 +1,204 @@
+--- a/include/linux/if_bridge.h
++++ b/include/linux/if_bridge.h
+@@ -71,6 +71,9 @@ void brioctl_set(int (*hook)(struct net
+ int br_ioctl_call(struct net *net, struct net_bridge *br, unsigned int cmd,
+ 		  struct ifreq *ifr, void __user *uarg);
+ 
++extern void br_dev_update_stats(struct net_device *dev,
++				struct rtnl_link_stats64 *nlstats);
++
+ #if IS_ENABLED(CONFIG_BRIDGE) && IS_ENABLED(CONFIG_BRIDGE_IGMP_SNOOPING)
+ int br_multicast_list_adjacent(struct net_device *dev,
+ 			       struct list_head *br_ip_list);
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -991,6 +991,10 @@ struct sk_buff {
+ 	__u8			csum_not_inet:1;
+ #endif
+ 
++#ifdef CONFIG_SHORTCUT_FE
++	__u8			fast_forwarded:1;
++#endif
++
+ #if defined(CONFIG_NET_SCHED) || defined(CONFIG_NET_XGRESS)
+ 	__u16			tc_index;	/* traffic control index */
+ #endif
+--- a/include/linux/timer.h
++++ b/include/linux/timer.h
+@@ -18,6 +18,10 @@ struct timer_list {
+ 	void			(*function)(struct timer_list *);
+ 	u32			flags;
+ 
++#ifdef CONFIG_SHORTCUT_FE
++	unsigned long		cust_data;
++#endif
++
+ #ifdef CONFIG_LOCKDEP
+ 	struct lockdep_map	lockdep_map;
+ #endif
+--- a/include/net/netfilter/nf_conntrack_ecache.h
++++ b/include/net/netfilter/nf_conntrack_ecache.h
+@@ -68,6 +68,8 @@ struct nf_ct_event_notifier {
+ #ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
+ extern int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb);
+ extern int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb);
++extern int nf_conntrack_register_chain_notifier(struct net *net, struct notifier_block *nb);
++extern int nf_conntrack_unregister_chain_notifier(struct net *net, struct notifier_block *nb);
+ #else
+ int nf_conntrack_register_notifier(struct net *net,
+ 				   const struct nf_ct_event_notifier *nb);
+--- a/net/Kconfig
++++ b/net/Kconfig
+@@ -495,6 +495,9 @@ config FAILOVER
+ 	  migration of VMs with direct attached VFs by failing over to the
+ 	  paravirtual datapath when the VF is unplugged.
+ 
++config SHORTCUT_FE
++	bool "Enables kernel network stack path for Shortcut  Forwarding Engine"
++
+ config ETHTOOL_NETLINK
+ 	bool "Netlink interface for ethtool"
+ 	default y
+--- a/net/bridge/br_if.c
++++ b/net/bridge/br_if.c
+@@ -764,6 +764,28 @@ void br_port_flags_change(struct net_bri
+ 		br_recalculate_neigh_suppress_enabled(br);
+ }
+ 
++void br_dev_update_stats(struct net_device *dev,
++			 struct rtnl_link_stats64 *nlstats)
++{
++	
++	struct pcpu_sw_netstats *stats;
++
++	/* Is this a bridge? */
++	if (!(dev->priv_flags & IFF_EBRIDGE))
++		return;
++
++	
++	stats = this_cpu_ptr(dev->tstats);
++
++	u64_stats_update_begin(&stats->syncp);
++	u64_stats_add(&stats->rx_packets, nlstats->rx_packets);
++	u64_stats_add(&stats->rx_bytes, nlstats->rx_bytes);
++	u64_stats_add(&stats->tx_packets, nlstats->tx_packets);
++	u64_stats_add(&stats->tx_bytes, nlstats->tx_bytes);
++	u64_stats_update_end(&stats->syncp);
++}
++EXPORT_SYMBOL_GPL(br_dev_update_stats);
++
+ bool br_port_flag_is_set(const struct net_device *dev, unsigned long flag)
+ {
+ 	struct net_bridge_port *p;
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -3567,9 +3567,17 @@ static int xmit_one(struct sk_buff *skb,
+ {
+ 	unsigned int len;
+ 	int rc;
+-
++#ifdef CONFIG_SHORTCUT_FE
++	/* If this skb has been fast forwarded then we don't want it to
++	 * go to any taps (by definition we're trying to bypass them).
++	 */
++	if (!skb->fast_forwarded) {
++#endif
+ 	if (dev_nit_active(dev))
+ 		dev_queue_xmit_nit(skb, dev);
++#ifdef CONFIG_SHORTCUT_FE
++	}
++#endif
+ 
+ 	len = skb->len;
+ 	trace_net_dev_start_xmit(skb, dev);
+@@ -5303,6 +5311,11 @@ void netdev_rx_handler_unregister(struct
+ }
+ EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
+ 
++#ifdef CONFIG_SHORTCUT_FE
++int (*athrs_fast_nat_recv)(struct sk_buff *skb) __rcu __read_mostly;
++EXPORT_SYMBOL_GPL(athrs_fast_nat_recv);
++#endif
++
+ /*
+  * Limit the use of PFMEMALLOC reserves to those protocols that implement
+  * the special handling of PFMEMALLOC skbs.
+@@ -5351,6 +5364,10 @@ static int __netif_receive_skb_core(stru
+ 	int ret = NET_RX_DROP;
+ 	__be16 type;
+ 
++#ifdef CONFIG_SHORTCUT_FE
++	int (*fast_recv)(struct sk_buff *skb);
++#endif
++
+ 	net_timestamp_check(!READ_ONCE(netdev_tstamp_prequeue), skb);
+ 
+ 	trace_netif_receive_skb(skb);
+@@ -5388,6 +5405,15 @@ another_round:
+ 			goto out;
+ 	}
+ 
++#ifdef CONFIG_SHORTCUT_FE
++	fast_recv = rcu_dereference(athrs_fast_nat_recv);
++	if (fast_recv) {
++		if (fast_recv(skb)) {
++			ret = NET_RX_SUCCESS;
++			goto out;
++		}
++	}
++#endif
+ 	if (skb_skip_tc_classify(skb))
+ 		goto skip_classify;
+ 
+--- a/net/netfilter/nf_conntrack_ecache.c
++++ b/net/netfilter/nf_conntrack_ecache.c
+@@ -143,12 +143,23 @@ static int __nf_conntrack_eventmask_repo
+ 	rcu_read_lock();
+ 
+ 	notify = rcu_dereference(net->ct.nf_conntrack_event_cb);
+-	if (!notify) {
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++	if (!notify && !rcu_dereference_raw(net->ct.nf_conntrack_chain.head))
++#else
++	if (!notify) 
++#endif
++	{
+ 		rcu_read_unlock();
+ 		return 0;
+ 	}
+-
++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
++		ret = atomic_notifier_call_chain(&net->ct.nf_conntrack_chain,
++			events | missed, &item);
++		if (notify)
++			ret = notify->ct_event(events | missed, item);
++#else
+ 	ret = notify->ct_event(events | missed, item);
++#endif
+ 	rcu_read_unlock();
+ 
+ 	if (likely(ret >= 0 && missed == 0))
+@@ -339,6 +350,11 @@ int nf_conntrack_register_notifier(struc
+ {
+ 	return atomic_notifier_chain_register(&net->ct.nf_conntrack_chain, nb);
+ }
++int nf_conntrack_register_chain_notifier(struct net *net, struct notifier_block *nb)
++{
++	return atomic_notifier_chain_register(&net->ct.nf_conntrack_chain, nb);
++}
++EXPORT_SYMBOL_GPL(nf_conntrack_register_chain_notifier);
+ #else
+ int nf_conntrack_register_notifier(struct net *net,
+ 				    const struct nf_ct_event_notifier *new)
+@@ -369,6 +385,11 @@ int nf_conntrack_unregister_notifier(str
+ {
+ 	return atomic_notifier_chain_unregister(&net->ct.nf_conntrack_chain, nb);
+ }
++int nf_conntrack_unregister_chain_notifier(struct net *net, struct notifier_block *nb)
++{
++	return atomic_notifier_chain_unregister(&net->ct.nf_conntrack_chain, nb);
++}
++EXPORT_SYMBOL_GPL(nf_conntrack_unregister_chain_notifier);
+ #else
+ void nf_conntrack_unregister_notifier(struct net *net)
+ {
diff --git a/target/linux/generic/hack-6.6/982-add-bcm-fullconenat-support.patch b/target/linux/generic/hack-6.6/982-add-bcm-fullconenat-support.patch
new file mode 100644
index 00000000000000..446f6bba5f3a1c
--- /dev/null
+++ b/target/linux/generic/hack-6.6/982-add-bcm-fullconenat-support.patch
@@ -0,0 +1,235 @@
+--- a/net/netfilter/nf_nat_masquerade.c
++++ b/net/netfilter/nf_nat_masquerade.c
+@@ -8,6 +8,9 @@
+ #include <linux/netfilter_ipv6.h>
+ 
+ #include <net/netfilter/nf_nat_masquerade.h>
++#include <net/netfilter/nf_conntrack_zones.h>
++#include <net/netfilter/nf_conntrack_helper.h>
++#include <net/netfilter/nf_conntrack_core.h>
+ 
+ struct masq_dev_work {
+ 	struct work_struct work;
+@@ -24,6 +27,129 @@ static DEFINE_MUTEX(masq_mutex);
+ static unsigned int masq_refcnt __read_mostly;
+ static atomic_t masq_worker_count __read_mostly;
+ 
++static void bcm_nat_expect(struct nf_conn *ct,
++                          struct nf_conntrack_expect *exp)
++{
++       struct nf_nat_range2 range;
++
++       /* This must be a fresh one. */
++       BUG_ON(ct->status & IPS_NAT_DONE_MASK);
++
++       /* Change src to where new ct comes from */
++       range.flags = NF_NAT_RANGE_MAP_IPS;
++       range.min_addr = range.max_addr =
++               ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3;
++       nf_nat_setup_info(ct, &range, NF_NAT_MANIP_SRC);
++
++       /* For DST manip, map port here to where it's expected. */
++       range.flags = (NF_NAT_RANGE_MAP_IPS | NF_NAT_RANGE_PROTO_SPECIFIED);
++       range.min_proto = range.max_proto = exp->saved_proto;
++       range.min_addr = range.max_addr = exp->saved_addr;
++       nf_nat_setup_info(ct, &range, NF_NAT_MANIP_DST);
++}
++
++/****************************************************************************/
++static int bcm_nat_help(struct sk_buff *skb, unsigned int protoff,
++                       struct nf_conn *ct, enum ip_conntrack_info ctinfo)
++{
++       int dir = CTINFO2DIR(ctinfo);
++       struct nf_conn_help *help = nfct_help(ct);
++       struct nf_conntrack_expect *exp;
++
++       if (dir != IP_CT_DIR_ORIGINAL ||
++           help->expecting[NF_CT_EXPECT_CLASS_DEFAULT])
++               return NF_ACCEPT;
++
++       pr_debug("bcm_nat: packet[%d bytes] ", skb->len);
++       nf_ct_dump_tuple(&ct->tuplehash[dir].tuple);
++       pr_debug("reply: ");
++       nf_ct_dump_tuple(&ct->tuplehash[!dir].tuple);
++
++       /* Create expect */
++       if ((exp = nf_ct_expect_alloc(ct)) == NULL)
++               return NF_ACCEPT;
++
++       nf_ct_expect_init(exp, NF_CT_EXPECT_CLASS_DEFAULT, AF_INET, NULL,
++                         &ct->tuplehash[!dir].tuple.dst.u3, IPPROTO_UDP,
++                         NULL, &ct->tuplehash[!dir].tuple.dst.u.udp.port);
++       exp->flags = NF_CT_EXPECT_PERMANENT;
++       exp->saved_addr = ct->tuplehash[dir].tuple.src.u3;
++       exp->saved_proto.udp.port = ct->tuplehash[dir].tuple.src.u.udp.port;
++       exp->dir = !dir;
++       exp->expectfn = bcm_nat_expect;
++
++       /* Setup expect */
++       nf_ct_expect_related(exp, 0);
++       nf_ct_expect_put(exp);
++       pr_debug("bcm_nat: expect setup\n");
++
++       return NF_ACCEPT;
++}
++
++/****************************************************************************/
++static struct nf_conntrack_expect_policy bcm_nat_exp_policy __read_mostly = {
++       .max_expected   = 1000,
++       .timeout        = 240,
++};
++
++/****************************************************************************/
++static struct nf_conntrack_helper nf_conntrack_helper_bcm_nat __read_mostly = {
++       .name = "BCM-NAT",
++       .me = THIS_MODULE,
++       .tuple.src.l3num = AF_INET,
++       .tuple.dst.protonum = IPPROTO_UDP,
++       .expect_policy = &bcm_nat_exp_policy,
++       .expect_class_max = 1,
++       .help = bcm_nat_help,
++};
++
++/****************************************************************************/
++static inline int find_exp(__be32 ip, __be16 port, struct nf_conn *ct)
++{
++       struct nf_conntrack_tuple tuple;
++       struct nf_conntrack_expect *i = NULL;
++
++
++       memset(&tuple, 0, sizeof(tuple));
++       tuple.src.l3num = AF_INET;
++       tuple.dst.protonum = IPPROTO_UDP;
++       tuple.dst.u3.ip = ip;
++       tuple.dst.u.udp.port = port;
++
++       rcu_read_lock();
++       i = __nf_ct_expect_find(nf_ct_net(ct), nf_ct_zone(ct), &tuple);
++       rcu_read_unlock();
++
++       return i != NULL;
++}
++
++/****************************************************************************/
++static inline struct nf_conntrack_expect *find_fullcone_exp(struct nf_conn *ct)
++{
++       struct nf_conntrack_tuple * tp =
++               &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
++       struct nf_conntrack_expect * exp = NULL;
++       struct nf_conntrack_expect * i;
++       unsigned int h;
++
++       rcu_read_lock();
++       for (h = 0; h < nf_ct_expect_hsize; h++) {
++               hlist_for_each_entry_rcu(i, &nf_ct_expect_hash[h], hnode) {
++                       if (nf_inet_addr_cmp(&i->saved_addr, &tp->src.u3) &&
++                           i->saved_proto.all == tp->src.u.all &&
++                           i->tuple.dst.protonum == tp->dst.protonum &&
++                           i->tuple.src.u3.ip == 0 &&
++                           i->tuple.src.u.udp.port == 0) {
++                               exp = i;
++                               break;
++                       }
++               }
++       }
++       rcu_read_unlock();
++
++       return exp;
++}
++
+ unsigned int
+ nf_nat_masquerade_ipv4(struct sk_buff *skb, unsigned int hooknum,
+ 		       const struct nf_nat_range2 *range,
+@@ -61,6 +187,72 @@ nf_nat_masquerade_ipv4(struct sk_buff *s
+ 	if (nat)
+ 		nat->masq_index = out->ifindex;
+ 
++/* RFC 4787 - 4.2.2.  Port Parity
++   i.e., an even port will be mapped to an even port, and an odd port will be mapped to an odd port.
++*/
++#define CHECK_PORT_PARITY(a, b) ((a%2)==(b%2))
++       if (range->min_addr.ip != 0 /* nat_mode == full cone */
++           && (nfct_help(ct) == NULL || nfct_help(ct)->helper == NULL)
++           && nf_ct_protonum(ct) == IPPROTO_UDP) {
++               unsigned int ret;
++               u_int16_t minport;
++               u_int16_t maxport;
++               struct nf_conntrack_expect *exp;
++
++               pr_debug("bcm_nat: need full cone NAT\n");
++
++               /* Choose port */
++               spin_lock_bh(&nf_conntrack_expect_lock);
++               /* Look for existing expectation */
++               exp = find_fullcone_exp(ct);
++               if (exp) {
++                       minport = maxport = exp->tuple.dst.u.udp.port;
++                       pr_debug("bcm_nat: existing mapped port = %hu\n",
++                                ntohs(minport));
++               } else { /* no previous expect */
++                       u_int16_t newport, tmpport, orgport;
++
++                       minport = range->min_proto.all == 0? 
++                               ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.
++                               u.udp.port : range->min_proto.all;
++                       maxport = range->max_proto.all == 0? 
++                               htons(65535) : range->max_proto.all;
++                        orgport = ntohs(minport);
++                       for (newport = ntohs(minport),tmpport = ntohs(maxport); 
++                            newport <= tmpport; newport++) {
++                               if (CHECK_PORT_PARITY(orgport, newport) && !find_exp(newsrc, htons(newport), ct)) {
++                                        pr_debug("bcm_nat: new mapped port = "
++                                                "%hu\n", newport);
++                                       minport = maxport = htons(newport);
++                                       break;
++                               }
++                       }
++               }
++               spin_unlock_bh(&nf_conntrack_expect_lock);
++
++
++       memset(&newrange.min_addr, 0, sizeof(newrange.min_addr));
++       memset(&newrange.max_addr, 0, sizeof(newrange.max_addr));
++
++               newrange.flags = range->flags | NF_NAT_RANGE_MAP_IPS |
++                       NF_NAT_RANGE_PROTO_SPECIFIED;
++               newrange.max_addr.ip = newrange.min_addr.ip = newsrc;
++               newrange.min_proto.udp.port = newrange.max_proto.udp.port = minport;
++
++               /* Set ct helper */
++               ret = nf_nat_setup_info(ct, &newrange, NF_NAT_MANIP_SRC);
++               if (ret == NF_ACCEPT) {
++                       struct nf_conn_help *help = nfct_help(ct);
++                       if (help == NULL)
++                               help = nf_ct_helper_ext_add(ct, GFP_ATOMIC);
++                       if (help != NULL) {
++                               help->helper = &nf_conntrack_helper_bcm_nat;
++                               pr_debug("bcm_nat: helper set\n");
++                       }
++               }
++               return ret;
++       }
++
+ 	/* Transfer from original range. */
+ 	memset(&newrange.min_addr, 0, sizeof(newrange.min_addr));
+ 	memset(&newrange.max_addr, 0, sizeof(newrange.max_addr));
+@@ -352,6 +544,7 @@ EXPORT_SYMBOL_GPL(nf_nat_masquerade_inet
+ 
+ void nf_nat_masquerade_inet_unregister_notifiers(void)
+ {
++       nf_conntrack_helper_unregister(&nf_conntrack_helper_bcm_nat);
+ 	mutex_lock(&masq_mutex);
+ 	/* check if the notifiers still have clients */
+ 	if (--masq_refcnt > 0)
+--- a/net/netfilter/xt_MASQUERADE.c
++++ b/net/netfilter/xt_MASQUERADE.c
+@@ -42,6 +42,9 @@ masquerade_tg(struct sk_buff *skb, const
+ 	range.min_proto = mr->range[0].min;
+ 	range.max_proto = mr->range[0].max;
+ 
++       range.min_addr.ip = mr->range[0].min_ip;
++       range.max_addr.ip = mr->range[0].max_ip;
++
+ 	return nf_nat_masquerade_ipv4(skb, xt_hooknum(par), &range,
+ 				      xt_out(par));
+ }
diff --git a/target/linux/generic/hack-6.6/992-add-ndo-do-ioctl.patch b/target/linux/generic/hack-6.6/992-add-ndo-do-ioctl.patch
new file mode 100644
index 00000000000000..5f9205183d06a8
--- /dev/null
+++ b/target/linux/generic/hack-6.6/992-add-ndo-do-ioctl.patch
@@ -0,0 +1,12 @@
+--- a/net/wireless/wext-core.c
++++ b/net/wireless/wext-core.c
+@@ -981,6 +981,9 @@ static int wireless_process_ioctl(struct
+ 		else if (private)
+ 			return private(dev, iwr, cmd, info, handler);
+ 	}
++	/* Old driver API : call driver ioctl handler */
++	if (dev->netdev_ops->ndo_do_ioctl)
++		return dev->netdev_ops->ndo_do_ioctl(dev, (struct ifreq *) iwr, cmd);
+ 	return -EOPNOTSUPP;
+ }
+ 
diff --git a/target/linux/generic/hack-6.6/998-virtio.patch b/target/linux/generic/hack-6.6/998-virtio.patch
new file mode 100644
index 00000000000000..0152f8c24d955b
--- /dev/null
+++ b/target/linux/generic/hack-6.6/998-virtio.patch
@@ -0,0 +1,31 @@
+--- a/drivers/virtio/Kconfig
++++ b/drivers/virtio/Kconfig
+@@ -3,7 +3,7 @@ config VIRTIO_ANCHOR
+ 	bool
+ 
+ config VIRTIO
+-	tristate
++	tristate "VIRTIO Support"
+ 	select VIRTIO_ANCHOR
+ 	help
+ 	  This option is selected by any driver which implements the virtio
+@@ -11,7 +11,7 @@ config VIRTIO
+ 	  or CONFIG_S390_GUEST.
+ 
+ config VIRTIO_PCI_LIB
+-	tristate
++	tristate "VIRTIO_PCI_LIB Support"
+ 	help
+ 	  Modern PCI device implementation. This module implements the
+ 	  basic probe and control for devices which are based on modern
+--- a/crypto/Kconfig
++++ b/crypto/Kconfig
+@@ -842,7 +842,7 @@ config CRYPTO_GCM
+ 	  This is required for IPSec ESP (XFRM_ESP).
+ 
+ config CRYPTO_GENIV
+-	tristate
++	tristate "IV Generation for dm-crypt"
+ 	select CRYPTO_AEAD
+ 	select CRYPTO_NULL
+ 	select CRYPTO_MANAGER
diff --git a/target/linux/generic/hack-6.6/999-revert-6.5-deprecated-API.patch b/target/linux/generic/hack-6.6/999-revert-6.5-deprecated-API.patch
new file mode 100644
index 00000000000000..25a6f742c318b5
--- /dev/null
+++ b/target/linux/generic/hack-6.6/999-revert-6.5-deprecated-API.patch
@@ -0,0 +1,153 @@
+--- a/include/linux/device/class.h
++++ b/include/linux/device/class.h
+@@ -51,6 +51,7 @@ struct fwnode_handle;
+  */
+ struct class {
+ 	const char		*name;
++	struct module		*owner;
+ 
+ 	const struct attribute_group	**class_groups;
+ 	const struct attribute_group	**dev_groups;
+--- a/include/linux/prandom.h
++++ b/include/linux/prandom.h
+@@ -24,6 +24,12 @@ void prandom_seed_full_state(struct rnd_
+ #define prandom_init_once(pcpu_state)			\
+ 	DO_ONCE(prandom_seed_full_state, (pcpu_state))
+ 
++/* Deprecated: use get_random_u32_below() instead. */
++static inline u32 prandom_u32_max(u32 ep_ro)
++{
++	return get_random_u32_below(ep_ro);
++}
++
+ /*
+  * Handle minimum values for seeds
+  */
+--- a/include/linux/u64_stats_sync.h
++++ b/include/linux/u64_stats_sync.h
+@@ -213,4 +213,16 @@ static inline bool u64_stats_fetch_retry
+ 	return __u64_stats_fetch_retry(syncp, start);
+ }
+ 
++/* Obsolete interfaces */
++static inline unsigned int u64_stats_fetch_begin_irq(const struct u64_stats_sync *syncp)
++{
++	return u64_stats_fetch_begin(syncp);
++}
++
++static inline bool u64_stats_fetch_retry_irq(const struct u64_stats_sync *syncp,
++					     unsigned int start)
++{
++	return u64_stats_fetch_retry(syncp, start);
++}
++
+ #endif /* _LINUX_U64_STATS_SYNC_H */
+--- a/drivers/thermal/thermal_core.c
++++ b/drivers/thermal/thermal_core.c
+@@ -1270,7 +1270,7 @@ thermal_zone_device_register_with_trips(
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
+-	if (num_trips > 0 && !trips)
++	if (num_trips > 0 && (!ops->get_trip_type || !ops->get_trip_temp) && !trips)
+ 		return ERR_PTR(-EINVAL);
+ 
+ 	if (!thermal_class)
+@@ -1392,6 +1392,17 @@ free_tz:
+ }
+ EXPORT_SYMBOL_GPL(thermal_zone_device_register_with_trips);
+ 
++struct thermal_zone_device *thermal_zone_device_register(const char *type, int ntrips, int mask,
++							 void *devdata, struct thermal_zone_device_ops *ops,
++							 const struct thermal_zone_params *tzp, int passive_delay,
++							 int polling_delay)
++{
++	return thermal_zone_device_register_with_trips(type, NULL, ntrips, mask,
++						       devdata, ops, tzp,
++						       passive_delay, polling_delay);
++}
++EXPORT_SYMBOL_GPL(thermal_zone_device_register);
++
+ struct thermal_zone_device *thermal_tripless_zone_device_register(
+ 					const char *type,
+ 					void *devdata,
+--- a/drivers/thermal/thermal_trip.c
++++ b/drivers/thermal/thermal_trip.c
+@@ -116,11 +116,29 @@ void __thermal_zone_set_trips(struct the
+ int __thermal_zone_get_trip(struct thermal_zone_device *tz, int trip_id,
+ 			    struct thermal_trip *trip)
+ {
+-	if (!tz || !tz->trips || trip_id < 0 || trip_id >= tz->num_trips || !trip)
++	int ret;
++
++	if (!tz || trip_id < 0 || trip_id >= tz->num_trips || !trip)
+ 		return -EINVAL;
+ 
+-	*trip = tz->trips[trip_id];
+-	return 0;
++		if (tz->trips) {
++		*trip = tz->trips[trip_id];
++		return 0;
++	}
++
++	if (tz->ops->get_trip_hyst) {
++		ret = tz->ops->get_trip_hyst(tz, trip_id, &trip->hysteresis);
++		if (ret)
++			return ret;
++	} else {
++		trip->hysteresis = 0;
++	}
++
++	ret = tz->ops->get_trip_temp(tz, trip_id, &trip->temperature);
++	if (ret)
++		return ret;
++
++	return tz->ops->get_trip_type(tz, trip_id, &trip->type);
+ }
+ EXPORT_SYMBOL_GPL(__thermal_zone_get_trip);
+ 
+--- a/include/linux/thermal.h
++++ b/include/linux/thermal.h
+@@ -76,7 +76,11 @@ struct thermal_zone_device_ops {
+ 	int (*set_trips) (struct thermal_zone_device *, int, int);
+ 	int (*change_mode) (struct thermal_zone_device *,
+ 		enum thermal_device_mode);
++	int (*get_trip_type) (struct thermal_zone_device *, int,
++		enum thermal_trip_type *);
++	int (*get_trip_temp) (struct thermal_zone_device *, int, int *);
+ 	int (*set_trip_temp) (struct thermal_zone_device *, int, int);
++	int (*get_trip_hyst) (struct thermal_zone_device *, int, int *);
+ 	int (*set_trip_hyst) (struct thermal_zone_device *, int, int);
+ 	int (*get_crit_temp) (struct thermal_zone_device *, int *);
+ 	int (*set_emul_temp) (struct thermal_zone_device *, int);
+@@ -300,6 +304,14 @@ int thermal_acpi_critical_trip_temp(stru
+ #endif
+ 
+ #ifdef CONFIG_THERMAL
++struct thermal_zone_device *thermal_zone_device_register(
++					const char *type,
++					int num_trips, int mask,
++					void *devdata,
++					struct thermal_zone_device_ops *ops,
++					const struct thermal_zone_params *tzp,
++					int passive_delay, int polling_delay);
++					
+ struct thermal_zone_device *thermal_zone_device_register_with_trips(
+ 					const char *type,
+ 					struct thermal_trip *trips,
+@@ -356,6 +368,15 @@ int thermal_zone_device_enable(struct th
+ int thermal_zone_device_disable(struct thermal_zone_device *tz);
+ void thermal_zone_device_critical(struct thermal_zone_device *tz);
+ #else
++static inline struct thermal_zone_device *thermal_zone_device_register(
++					const char *type,
++					int num_trips, int mask,
++					void *devdata,
++					struct thermal_zone_device_ops *ops,
++					const struct thermal_zone_params *tzp,
++					int passive_delay, int polling_delay)
++{ return ERR_PTR(-ENODEV); }
++
+ static inline struct thermal_zone_device *thermal_zone_device_register_with_trips(
+ 					const char *type,
+ 					struct thermal_trip *trips,
diff --git a/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch
index a10ce95222a794..ee3fc5e108c708 100644
--- a/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch
+++ b/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch
@@ -9,7 +9,7 @@ Acked-by: Rob Landley <rob@landley.net>
 ---
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1087,9 +1087,6 @@ config FW_ARC
+@@ -1086,9 +1086,6 @@ config FW_ARC
  config ARCH_MAY_HAVE_PC_FDC
  	bool
  
@@ -19,7 +19,7 @@ Acked-by: Rob Landley <rob@landley.net>
  config CEVT_BCM1480
  	bool
  
-@@ -3185,6 +3182,18 @@ choice
+@@ -3183,6 +3180,18 @@ choice
  		bool "Extend builtin kernel arguments with bootloader arguments"
  endchoice
  
diff --git a/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index 6966b9650f560e..be0b52db929556 100644
--- a/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	case RTN_THROW:
  	case RTN_UNREACHABLE:
  	default:
-@@ -4449,6 +4468,17 @@ static int ip6_pkt_prohibit_out(struct n
+@@ -4446,6 +4465,17 @@ static int ip6_pkt_prohibit_out(struct n
  	return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
  }
  
@@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  /*
   *	Allocate a dst for local (unicast / anycast) address.
   */
-@@ -4936,7 +4966,8 @@ static int rtm_to_fib6_config(struct sk_
+@@ -4933,7 +4963,8 @@ static int rtm_to_fib6_config(struct sk_
  	if (rtm->rtm_type == RTN_UNREACHABLE ||
  	    rtm->rtm_type == RTN_BLACKHOLE ||
  	    rtm->rtm_type == RTN_PROHIBIT ||
@@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		cfg->fc_flags |= RTF_REJECT;
  
  	if (rtm->rtm_type == RTN_LOCAL)
-@@ -6136,6 +6167,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6133,6 +6164,8 @@ static int ip6_route_dev_notify(struct n
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
  		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
  		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
  #endif
-@@ -6147,6 +6180,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6144,6 +6177,7 @@ static int ip6_route_dev_notify(struct n
  		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
  #endif
  	}
-@@ -6338,6 +6372,8 @@ static int __net_init ip6_route_net_init
+@@ -6335,6 +6369,8 @@ static int __net_init ip6_route_net_init
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	net->ipv6.fib6_has_custom_rules = false;
@@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
  					       sizeof(*net->ipv6.ip6_prohibit_entry),
  					       GFP_KERNEL);
-@@ -6348,11 +6384,21 @@ static int __net_init ip6_route_net_init
+@@ -6345,11 +6381,21 @@ static int __net_init ip6_route_net_init
  			 ip6_template_metrics, true);
  	INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
  
@@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
  	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
  			 ip6_template_metrics, true);
-@@ -6379,6 +6425,8 @@ out:
+@@ -6376,6 +6422,8 @@ out:
  	return ret;
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
@@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  out_ip6_prohibit_entry:
  	kfree(net->ipv6.ip6_prohibit_entry);
  out_ip6_null_entry:
-@@ -6398,6 +6446,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6395,6 +6443,7 @@ static void __net_exit ip6_route_net_exi
  	kfree(net->ipv6.ip6_null_entry);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	kfree(net->ipv6.ip6_prohibit_entry);
@@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	kfree(net->ipv6.ip6_blk_hole_entry);
  #endif
  	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6481,6 +6530,9 @@ void __init ip6_route_init_special_entri
+@@ -6478,6 +6527,9 @@ void __init ip6_route_init_special_entri
  	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
  	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
  	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
diff --git a/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 346d49269189fc..ceaf1e99f9aedc 100644
--- a/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	__u16			tc_index;	/* traffic control index */
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6073,6 +6073,9 @@ static enum gro_result dev_gro_receive(s
+@@ -6081,6 +6081,9 @@ static enum gro_result dev_gro_receive(s
  	int same_flow;
  	int grow;
  
@@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (netif_elide_gro(skb->dev))
  		goto normal;
  
-@@ -8052,6 +8055,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -8060,6 +8063,48 @@ static void __netdev_adjacent_dev_unlink
  					   &upper_dev->adj_list.lower);
  }
  
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int __netdev_upper_dev_link(struct net_device *dev,
  				   struct net_device *upper_dev, bool master,
  				   void *upper_priv, void *upper_info,
-@@ -8103,6 +8148,7 @@ static int __netdev_upper_dev_link(struc
+@@ -8111,6 +8156,7 @@ static int __netdev_upper_dev_link(struc
  	if (ret)
  		return ret;
  
@@ -99,7 +99,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  					    &changeupper_info.info);
  	ret = notifier_to_errno(ret);
-@@ -8199,6 +8245,7 @@ static void __netdev_upper_dev_unlink(st
+@@ -8207,6 +8253,7 @@ static void __netdev_upper_dev_unlink(st
  
  	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
  
@@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  				      &changeupper_info.info);
  
-@@ -8985,6 +9032,7 @@ int dev_set_mac_address(struct net_devic
+@@ -8993,6 +9040,7 @@ int dev_set_mac_address(struct net_devic
  	if (err)
  		return err;
  	dev->addr_assign_type = NET_ADDR_SET;
diff --git a/target/linux/generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch b/target/linux/generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch
new file mode 100644
index 00000000000000..1bc0e724188d6f
--- /dev/null
+++ b/target/linux/generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch
@@ -0,0 +1,32 @@
+From cb1d41b99e4afa062f904339666fae2578559718 Mon Sep 17 00:00:00 2001
+From: Namjae Jeon <linkinjeon@kernel.org>
+Date: Mon, 15 Jan 2024 10:24:54 +0900
+Subject: [PATCH] ksmbd: only v2 leases handle the directory
+
+When smb2 leases is disable, ksmbd can send oplock break notification
+and cause wait oplock break ack timeout. It may appear like hang when
+accessing a directory. This patch make only v2 leases handle the
+directory.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+---
+ fs/ksmbd/oplock.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/fs/ksmbd/oplock.c
++++ b/fs/ksmbd/oplock.c
+@@ -1191,6 +1191,12 @@ int smb_grant_oplock(struct ksmbd_work *
+ 	bool prev_op_has_lease;
+ 	__le32 prev_op_state = 0;
+ 
++	/* Only v2 leases handle the directory */
++	if (S_ISDIR(file_inode(fp->filp)->i_mode)) {
++		if (!lctx || lctx->version != 2)
++			return 0;
++	}
++
+ 	opinfo = alloc_opinfo(work, pid, tid);
+ 	if (!opinfo)
+ 		return -ENOMEM;
diff --git a/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index 7aaac9653187b9..071a2ed3e5e013 100644
--- a/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	case RTN_THROW:
  	case RTN_UNREACHABLE:
  	default:
-@@ -4560,6 +4579,17 @@ static int ip6_pkt_prohibit_out(struct n
+@@ -4557,6 +4576,17 @@ static int ip6_pkt_prohibit_out(struct n
  	return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
  }
  
@@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  /*
   *	Allocate a dst for local (unicast / anycast) address.
   */
-@@ -5047,7 +5077,8 @@ static int rtm_to_fib6_config(struct sk_
+@@ -5044,7 +5074,8 @@ static int rtm_to_fib6_config(struct sk_
  	if (rtm->rtm_type == RTN_UNREACHABLE ||
  	    rtm->rtm_type == RTN_BLACKHOLE ||
  	    rtm->rtm_type == RTN_PROHIBIT ||
@@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		cfg->fc_flags |= RTF_REJECT;
  
  	if (rtm->rtm_type == RTN_LOCAL)
-@@ -6301,6 +6332,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6298,6 +6329,8 @@ static int ip6_route_dev_notify(struct n
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
  		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
  		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
  #endif
-@@ -6312,6 +6345,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6309,6 +6342,7 @@ static int ip6_route_dev_notify(struct n
  		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
  #endif
  	}
-@@ -6503,6 +6537,8 @@ static int __net_init ip6_route_net_init
+@@ -6500,6 +6534,8 @@ static int __net_init ip6_route_net_init
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	net->ipv6.fib6_has_custom_rules = false;
@@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
  					       sizeof(*net->ipv6.ip6_prohibit_entry),
  					       GFP_KERNEL);
-@@ -6513,11 +6549,21 @@ static int __net_init ip6_route_net_init
+@@ -6510,11 +6546,21 @@ static int __net_init ip6_route_net_init
  			 ip6_template_metrics, true);
  	INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
  
@@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
  	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
  			 ip6_template_metrics, true);
-@@ -6544,6 +6590,8 @@ out:
+@@ -6541,6 +6587,8 @@ out:
  	return ret;
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
@@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  out_ip6_prohibit_entry:
  	kfree(net->ipv6.ip6_prohibit_entry);
  out_ip6_null_entry:
-@@ -6563,6 +6611,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6560,6 +6608,7 @@ static void __net_exit ip6_route_net_exi
  	kfree(net->ipv6.ip6_null_entry);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	kfree(net->ipv6.ip6_prohibit_entry);
@@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	kfree(net->ipv6.ip6_blk_hole_entry);
  #endif
  	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6646,6 +6695,9 @@ void __init ip6_route_init_special_entri
+@@ -6643,6 +6692,9 @@ void __init ip6_route_init_special_entri
  	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
  	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
  	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
diff --git a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 7df237e268d29f..0a744ad392e7f2 100644
--- a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	__u8			inner_protocol_type:1;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6089,6 +6089,9 @@ static enum gro_result dev_gro_receive(s
+@@ -6092,6 +6092,9 @@ static enum gro_result dev_gro_receive(s
  	int same_flow;
  	int grow;
  
@@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (netif_elide_gro(skb->dev))
  		goto normal;
  
-@@ -8103,6 +8106,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -8106,6 +8109,48 @@ static void __netdev_adjacent_dev_unlink
  					   &upper_dev->adj_list.lower);
  }
  
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int __netdev_upper_dev_link(struct net_device *dev,
  				   struct net_device *upper_dev, bool master,
  				   void *upper_priv, void *upper_info,
-@@ -8154,6 +8199,7 @@ static int __netdev_upper_dev_link(struc
+@@ -8157,6 +8202,7 @@ static int __netdev_upper_dev_link(struc
  	if (ret)
  		return ret;
  
@@ -99,7 +99,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  					    &changeupper_info.info);
  	ret = notifier_to_errno(ret);
-@@ -8250,6 +8296,7 @@ static void __netdev_upper_dev_unlink(st
+@@ -8253,6 +8299,7 @@ static void __netdev_upper_dev_unlink(st
  
  	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
  
@@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  				      &changeupper_info.info);
  
-@@ -9069,6 +9116,7 @@ int dev_set_mac_address(struct net_devic
+@@ -9072,6 +9119,7 @@ int dev_set_mac_address(struct net_devic
  	if (err)
  		return err;
  	dev->addr_assign_type = NET_ADDR_SET;
diff --git a/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch
index a6eaf01fd0e277..8db458b0966bab 100644
--- a/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #endif
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -4598,7 +4598,7 @@ static int rps_ipi_queued(struct softnet
+@@ -4601,7 +4601,7 @@ static int rps_ipi_queued(struct softnet
  #ifdef CONFIG_RPS
  	struct softnet_data *mysd = this_cpu_ptr(&softnet_data);
  
@@ -39,7 +39,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		sd->rps_ipi_next = mysd->rps_ipi_list;
  		mysd->rps_ipi_list = sd;
  
-@@ -5779,6 +5779,8 @@ static DEFINE_PER_CPU(struct work_struct
+@@ -5782,6 +5782,8 @@ static DEFINE_PER_CPU(struct work_struct
  /* Network device is going away, flush any packets still pending */
  static void flush_backlog(struct work_struct *work)
  {
@@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct sk_buff *skb, *tmp;
  	struct softnet_data *sd;
  
-@@ -5794,9 +5796,18 @@ static void flush_backlog(struct work_st
+@@ -5797,9 +5799,18 @@ static void flush_backlog(struct work_st
  			input_queue_head_incr(sd);
  		}
  	}
@@ -67,7 +67,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	skb_queue_walk_safe(&sd->process_queue, skb, tmp) {
  		if (skb->dev->reg_state == NETREG_UNREGISTERING) {
  			__skb_unlink(skb, &sd->process_queue);
-@@ -5804,7 +5815,18 @@ static void flush_backlog(struct work_st
+@@ -5807,7 +5818,18 @@ static void flush_backlog(struct work_st
  			input_queue_head_incr(sd);
  		}
  	}
@@ -86,7 +86,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static bool flush_required(int cpu)
-@@ -6487,6 +6509,7 @@ static int process_backlog(struct napi_s
+@@ -6490,6 +6512,7 @@ static int process_backlog(struct napi_s
  
  		local_irq_disable();
  		rps_lock(sd);
@@ -94,7 +94,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		if (skb_queue_empty(&sd->input_pkt_queue)) {
  			/*
  			 * Inline a custom version of __napi_complete().
-@@ -6496,7 +6519,8 @@ static int process_backlog(struct napi_s
+@@ -6499,7 +6522,8 @@ static int process_backlog(struct napi_s
  			 * We can use a plain write instead of clear_bit(),
  			 * and we dont need an smp_mb() memory barrier.
  			 */
@@ -104,7 +104,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			again = false;
  		} else {
  			skb_queue_splice_tail_init(&sd->input_pkt_queue,
-@@ -6913,6 +6937,57 @@ int dev_set_threaded(struct net_device *
+@@ -6916,6 +6940,57 @@ int dev_set_threaded(struct net_device *
  }
  EXPORT_SYMBOL(dev_set_threaded);
  
@@ -162,7 +162,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  void netif_napi_add(struct net_device *dev, struct napi_struct *napi,
  		    int (*poll)(struct napi_struct *, int), int weight)
  {
-@@ -11393,6 +11468,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11396,6 +11471,9 @@ static int dev_cpu_dead(unsigned int old
  	raise_softirq_irqoff(NET_TX_SOFTIRQ);
  	local_irq_enable();
  
@@ -172,7 +172,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11732,6 +11810,7 @@ static int __init net_dev_init(void)
+@@ -11735,6 +11813,7 @@ static int __init net_dev_init(void)
  		sd->cpu = i;
  #endif
  
diff --git a/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch b/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch
index c717b771fb383e..19bebb70c7a93e 100644
--- a/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch
+++ b/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch
@@ -12,7 +12,7 @@
  	{QMI_GOBI1K_DEVICE(0x05c6, 0x9212)},	/* Acer Gobi Modem Device */
 --- a/drivers/usb/serial/option.c
 +++ b/drivers/usb/serial/option.c
-@@ -2266,6 +2266,12 @@ static const struct usb_device_id option
+@@ -2271,6 +2271,12 @@ static const struct usb_device_id option
  	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a2, 0xff) },			/* Fibocom FM101-GL (laptop MBIM) */
  	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a4, 0xff),			/* Fibocom FM101-GL (laptop MBIM) */
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch b/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch
index 48d7864a46fbfa..b3148914a07f8a 100644
--- a/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch
+++ b/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch
@@ -506,7 +506,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
 +MODULE_ALIAS("nf-flow-table-hw");
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -5974,6 +5974,13 @@ static int nf_tables_flowtable_parse_hoo
+@@ -6001,6 +6001,13 @@ static int nf_tables_flowtable_parse_hoo
  	if (err < 0)
  		return err;
  
@@ -520,7 +520,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	ops = kcalloc(n, sizeof(struct nf_hook_ops), GFP_KERNEL);
  	if (!ops)
  		return -ENOMEM;
-@@ -6118,10 +6125,19 @@ static int nf_tables_newflowtable(struct
+@@ -6145,10 +6152,19 @@ static int nf_tables_newflowtable(struct
  	}
  
  	flowtable->data.type = type;
@@ -540,7 +540,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	err = nf_tables_flowtable_parse_hook(&ctx, nla[NFTA_FLOWTABLE_HOOK],
  					     flowtable);
  	if (err < 0)
-@@ -6247,7 +6263,8 @@ static int nf_tables_fill_flowtable_info
+@@ -6274,7 +6290,8 @@ static int nf_tables_fill_flowtable_info
  	    nla_put_string(skb, NFTA_FLOWTABLE_NAME, flowtable->name) ||
  	    nla_put_be32(skb, NFTA_FLOWTABLE_USE, htonl(flowtable->use)) ||
  	    nla_put_be64(skb, NFTA_FLOWTABLE_HANDLE, cpu_to_be64(flowtable->handle),
diff --git a/target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index bce15c5e20d804..052019bc99fed1 100644
--- a/target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	case RTN_THROW:
  	case RTN_UNREACHABLE:
  	default:
-@@ -4453,6 +4472,17 @@ static int ip6_pkt_prohibit_out(struct n
+@@ -4454,6 +4473,17 @@ static int ip6_pkt_prohibit_out(struct n
  	return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
  }
  
@@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  /*
   *	Allocate a dst for local (unicast / anycast) address.
   */
-@@ -4940,7 +4970,8 @@ static int rtm_to_fib6_config(struct sk_
+@@ -4941,7 +4971,8 @@ static int rtm_to_fib6_config(struct sk_
  	if (rtm->rtm_type == RTN_UNREACHABLE ||
  	    rtm->rtm_type == RTN_BLACKHOLE ||
  	    rtm->rtm_type == RTN_PROHIBIT ||
@@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		cfg->fc_flags |= RTF_REJECT;
  
  	if (rtm->rtm_type == RTN_LOCAL)
-@@ -6092,6 +6123,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6093,6 +6124,8 @@ static int ip6_route_dev_notify(struct n
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
  		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
  		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
  #endif
-@@ -6103,6 +6136,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6104,6 +6137,7 @@ static int ip6_route_dev_notify(struct n
  		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
  #endif
  	}
-@@ -6295,6 +6329,8 @@ static int __net_init ip6_route_net_init
+@@ -6296,6 +6330,8 @@ static int __net_init ip6_route_net_init
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	net->ipv6.fib6_has_custom_rules = false;
@@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
  					       sizeof(*net->ipv6.ip6_prohibit_entry),
  					       GFP_KERNEL);
-@@ -6305,11 +6341,21 @@ static int __net_init ip6_route_net_init
+@@ -6306,11 +6342,21 @@ static int __net_init ip6_route_net_init
  			 ip6_template_metrics, true);
  	INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
  
@@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
  	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
  			 ip6_template_metrics, true);
-@@ -6333,6 +6379,8 @@ out:
+@@ -6334,6 +6380,8 @@ out:
  	return ret;
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
@@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  out_ip6_prohibit_entry:
  	kfree(net->ipv6.ip6_prohibit_entry);
  out_ip6_null_entry:
-@@ -6352,6 +6400,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6353,6 +6401,7 @@ static void __net_exit ip6_route_net_exi
  	kfree(net->ipv6.ip6_null_entry);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	kfree(net->ipv6.ip6_prohibit_entry);
@@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	kfree(net->ipv6.ip6_blk_hole_entry);
  #endif
  	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6435,6 +6484,9 @@ void __init ip6_route_init_special_entri
+@@ -6436,6 +6485,9 @@ void __init ip6_route_init_special_entri
  	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
  	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
  	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
diff --git a/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 209ef2065630e7..6f7edc161a25da 100644
--- a/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		__wsum		csum;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -5508,6 +5508,9 @@ static enum gro_result dev_gro_receive(s
+@@ -5516,6 +5516,9 @@ static enum gro_result dev_gro_receive(s
  	int same_flow;
  	int grow;
  
@@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (netif_elide_gro(skb->dev))
  		goto normal;
  
-@@ -7310,6 +7313,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -7318,6 +7321,48 @@ static void __netdev_adjacent_dev_unlink
  					   &upper_dev->adj_list.lower);
  }
  
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int __netdev_upper_dev_link(struct net_device *dev,
  				   struct net_device *upper_dev, bool master,
  				   void *upper_priv, void *upper_info,
-@@ -7360,6 +7405,7 @@ static int __netdev_upper_dev_link(struc
+@@ -7368,6 +7413,7 @@ static int __netdev_upper_dev_link(struc
  	if (ret)
  		return ret;
  
@@ -99,7 +99,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  					    &changeupper_info.info);
  	ret = notifier_to_errno(ret);
-@@ -7453,6 +7499,7 @@ void netdev_upper_dev_unlink(struct net_
+@@ -7461,6 +7507,7 @@ void netdev_upper_dev_unlink(struct net_
  
  	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
  
@@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  				      &changeupper_info.info);
  
-@@ -8183,6 +8230,7 @@ int dev_set_mac_address(struct net_devic
+@@ -8191,6 +8238,7 @@ int dev_set_mac_address(struct net_devic
  	if (err)
  		return err;
  	dev->addr_assign_type = NET_ADDR_SET;
diff --git a/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch b/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch
index 2f188a3df6a2b1..bbff69238fff52 100644
--- a/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch
+++ b/target/linux/generic/pending-5.4/690-net-add-support-for-threaded-NAPI-polling.patch
@@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  static int netif_rx_internal(struct sk_buff *skb);
  static int call_netdevice_notifiers_info(unsigned long val,
-@@ -5950,6 +5951,11 @@ void __napi_schedule(struct napi_struct
+@@ -5958,6 +5959,11 @@ void __napi_schedule(struct napi_struct
  {
  	unsigned long flags;
  
@@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	local_irq_save(flags);
  	____napi_schedule(this_cpu_ptr(&softnet_data), n);
  	local_irq_restore(flags);
-@@ -6001,6 +6007,10 @@ EXPORT_SYMBOL(napi_schedule_prep);
+@@ -6009,6 +6015,10 @@ EXPORT_SYMBOL(napi_schedule_prep);
   */
  void __napi_schedule_irqoff(struct napi_struct *n)
  {
@@ -118,7 +118,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (!IS_ENABLED(CONFIG_PREEMPT_RT))
  		____napi_schedule(this_cpu_ptr(&softnet_data), n);
  	else
-@@ -6265,9 +6275,89 @@ static void init_gro_hash(struct napi_st
+@@ -6273,9 +6283,89 @@ static void init_gro_hash(struct napi_st
  	napi->gro_bitmask = 0;
  }
  
@@ -208,7 +208,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	INIT_LIST_HEAD(&napi->poll_list);
  	hrtimer_init(&napi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED);
  	napi->timer.function = napi_watchdog;
-@@ -6284,6 +6374,7 @@ void netif_napi_add(struct net_device *d
+@@ -6292,6 +6382,7 @@ void netif_napi_add(struct net_device *d
  #ifdef CONFIG_NETPOLL
  	napi->poll_owner = -1;
  #endif
@@ -216,7 +216,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	set_bit(NAPI_STATE_SCHED, &napi->state);
  	set_bit(NAPI_STATE_NPSVC, &napi->state);
  	list_add_rcu(&napi->dev_list, &dev->napi_list);
-@@ -6324,6 +6415,7 @@ static void flush_gro_hash(struct napi_s
+@@ -6332,6 +6423,7 @@ static void flush_gro_hash(struct napi_s
  void netif_napi_del(struct napi_struct *napi)
  {
  	might_sleep();
@@ -224,7 +224,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (napi_hash_del(napi))
  		synchronize_net();
  	list_del_init(&napi->dev_list);
-@@ -6336,50 +6428,18 @@ EXPORT_SYMBOL(netif_napi_del);
+@@ -6344,50 +6436,18 @@ EXPORT_SYMBOL(netif_napi_del);
  
  static int napi_poll(struct napi_struct *n, struct list_head *repoll)
  {
@@ -279,7 +279,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* Some drivers may have called napi_schedule
  	 * prior to exhausting their budget.
-@@ -10349,6 +10409,10 @@ static int __init net_dev_init(void)
+@@ -10357,6 +10417,10 @@ static int __init net_dev_init(void)
  		sd->backlog.weight = weight_p;
  	}
  
diff --git a/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch b/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch
new file mode 100644
index 00000000000000..43d7535372804a
--- /dev/null
+++ b/target/linux/generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch
@@ -0,0 +1,32 @@
+From 86b7307af26834415e1ba8597319a8b64846346f Mon Sep 17 00:00:00 2001
+From: Namjae Jeon <linkinjeon@kernel.org>
+Date: Mon, 15 Jan 2024 10:24:54 +0900
+Subject: [PATCH] ksmbd: only v2 leases handle the directory
+
+When smb2 leases is disable, ksmbd can send oplock break notification
+and cause wait oplock break ack timeout. It may appear like hang when
+accessing a directory. This patch make only v2 leases handle the
+directory.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+---
+ fs/smb/server/oplock.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/fs/smb/server/oplock.c
++++ b/fs/smb/server/oplock.c
+@@ -1197,6 +1197,12 @@ int smb_grant_oplock(struct ksmbd_work *
+ 			return 0;
+ 	}
+ 
++	/* Only v2 leases handle the directory */
++	if (S_ISDIR(file_inode(fp->filp)->i_mode)) {
++		if (!lctx || lctx->version != 2)
++			return 0;
++	}
++
+ 	opinfo = alloc_opinfo(work, pid, tid);
+ 	if (!opinfo)
+ 		return -ENOMEM;
diff --git a/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index 003a0f20ac810d..72e8de2f1d1c30 100644
--- a/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-6.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	case RTN_THROW:
  	case RTN_UNREACHABLE:
  	default:
-@@ -4543,6 +4562,17 @@ static int ip6_pkt_prohibit_out(struct n
+@@ -4540,6 +4559,17 @@ static int ip6_pkt_prohibit_out(struct n
  	return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
  }
  
@@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  /*
   *	Allocate a dst for local (unicast / anycast) address.
   */
-@@ -5036,7 +5066,8 @@ static int rtm_to_fib6_config(struct sk_
+@@ -5033,7 +5063,8 @@ static int rtm_to_fib6_config(struct sk_
  	if (rtm->rtm_type == RTN_UNREACHABLE ||
  	    rtm->rtm_type == RTN_BLACKHOLE ||
  	    rtm->rtm_type == RTN_PROHIBIT ||
@@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		cfg->fc_flags |= RTF_REJECT;
  
  	if (rtm->rtm_type == RTN_LOCAL)
-@@ -6290,6 +6321,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6287,6 +6318,8 @@ static int ip6_route_dev_notify(struct n
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
  		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
  		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
  #endif
-@@ -6301,6 +6334,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6298,6 +6331,7 @@ static int ip6_route_dev_notify(struct n
  		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
  #endif
  	}
-@@ -6492,6 +6526,8 @@ static int __net_init ip6_route_net_init
+@@ -6489,6 +6523,8 @@ static int __net_init ip6_route_net_init
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	net->ipv6.fib6_has_custom_rules = false;
@@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
  					       sizeof(*net->ipv6.ip6_prohibit_entry),
  					       GFP_KERNEL);
-@@ -6502,11 +6538,21 @@ static int __net_init ip6_route_net_init
+@@ -6499,11 +6535,21 @@ static int __net_init ip6_route_net_init
  			 ip6_template_metrics, true);
  	INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
  
@@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
  	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
  			 ip6_template_metrics, true);
-@@ -6533,6 +6579,8 @@ out:
+@@ -6530,6 +6576,8 @@ out:
  	return ret;
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
@@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  out_ip6_prohibit_entry:
  	kfree(net->ipv6.ip6_prohibit_entry);
  out_ip6_null_entry:
-@@ -6552,6 +6600,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6549,6 +6597,7 @@ static void __net_exit ip6_route_net_exi
  	kfree(net->ipv6.ip6_null_entry);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	kfree(net->ipv6.ip6_prohibit_entry);
@@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	kfree(net->ipv6.ip6_blk_hole_entry);
  #endif
  	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6635,6 +6684,9 @@ void __init ip6_route_init_special_entri
+@@ -6632,6 +6681,9 @@ void __init ip6_route_init_special_entri
  	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
  	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
  	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
diff --git a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 990cf3bd285360..870c43753f3ff6 100644
--- a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -7637,6 +7637,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -7640,6 +7640,48 @@ static void __netdev_adjacent_dev_unlink
  					   &upper_dev->adj_list.lower);
  }
  
@@ -93,7 +93,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int __netdev_upper_dev_link(struct net_device *dev,
  				   struct net_device *upper_dev, bool master,
  				   void *upper_priv, void *upper_info,
-@@ -7688,6 +7730,7 @@ static int __netdev_upper_dev_link(struc
+@@ -7691,6 +7733,7 @@ static int __netdev_upper_dev_link(struc
  	if (ret)
  		return ret;
  
@@ -101,7 +101,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  					    &changeupper_info.info);
  	ret = notifier_to_errno(ret);
-@@ -7784,6 +7827,7 @@ static void __netdev_upper_dev_unlink(st
+@@ -7787,6 +7830,7 @@ static void __netdev_upper_dev_unlink(st
  
  	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
  
@@ -109,7 +109,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  				      &changeupper_info.info);
  
-@@ -8836,6 +8880,7 @@ int dev_set_mac_address(struct net_devic
+@@ -8839,6 +8883,7 @@ int dev_set_mac_address(struct net_devic
  	if (err)
  		return err;
  	dev->addr_assign_type = NET_ADDR_SET;
diff --git a/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
index 6050db3f5b7fb8..47c742cff0689b 100644
--- a/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
+++ b/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
@@ -10,7 +10,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
 
 --- a/net/netfilter/nf_flow_table_core.c
 +++ b/net/netfilter/nf_flow_table_core.c
-@@ -659,6 +659,23 @@ static struct pernet_operations nf_flow_
+@@ -666,6 +666,23 @@ static struct pernet_operations nf_flow_
  	.exit_batch = nf_flow_table_pernet_exit,
  };
  
@@ -34,7 +34,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  static int __init nf_flow_table_module_init(void)
  {
  	int ret;
-@@ -671,8 +688,14 @@ static int __init nf_flow_table_module_i
+@@ -678,8 +695,14 @@ static int __init nf_flow_table_module_i
  	if (ret)
  		goto out_offload;
  
@@ -49,7 +49,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  out_offload:
  	unregister_pernet_subsys(&nf_flow_table_net_ops);
  	return ret;
-@@ -680,6 +703,7 @@ out_offload:
+@@ -687,6 +710,7 @@ out_offload:
  
  static void __exit nf_flow_table_module_exit(void)
  {
diff --git a/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
index 32c2ce1831db85..a18d1ad7173fe0 100644
--- a/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
+++ b/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
@@ -15,7 +15,7 @@ Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2212,6 +2212,10 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2252,6 +2252,10 @@ mt7530_setup(struct dsa_switch *ds)
  		return -ENODEV;
  	}
  
diff --git a/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch b/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch
new file mode 100644
index 00000000000000..aba067a5b9589d
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch
@@ -0,0 +1,223 @@
+From 663fa1b7e0cb2c929008482014a70c6625caad75 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 7 Mar 2023 15:55:13 +0000
+Subject: [PATCH 1/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability
+ bit
+
+Introduce MTK_NETSYS_V1 bit in the device capabilities for
+MT7621/MT7622/MT7623/MT7628/MT7629 SoCs.
+Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase.
+This is a preliminary patch to introduce support for MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++-------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++---------
+ 2 files changed, 41 insertions(+), 34 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -640,7 +640,7 @@ static void mtk_set_queue_speed(struct m
+ 	      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ 	      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
+ 	      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+-	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+ 		val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
+ 
+ 	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+@@ -1018,7 +1018,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+ 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
+ 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
+ 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+ 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
+ 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
+ 	}
+@@ -1076,7 +1076,7 @@ static int mtk_init_fq_dma(struct mtk_et
+ 
+ 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ 		txd->txd4 = 0;
+-		if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
++		if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) {
+ 			txd->txd5 = 0;
+ 			txd->txd6 = 0;
+ 			txd->txd7 = 0;
+@@ -1267,7 +1267,7 @@ static void mtk_tx_set_dma_desc(struct n
+ 	struct mtk_mac *mac = netdev_priv(dev);
+ 	struct mtk_eth *eth = mac->hw;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+ 		mtk_tx_set_dma_desc_v2(dev, txd, info);
+ 	else
+ 		mtk_tx_set_dma_desc_v1(dev, txd, info);
+@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			break;
+ 
+ 		/* find out which mac the packet come from. values start at 1 */
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+ 			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
+ 		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
+ 			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
+@@ -2046,7 +2046,7 @@ static int mtk_poll_rx(struct napi_struc
+ 		skb->dev = netdev;
+ 		bytes += skb->len;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+ 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
+ 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
+ 			if (hash != MTK_RXD5_FOE_ENTRY)
+@@ -2071,7 +2071,7 @@ static int mtk_poll_rx(struct napi_struc
+ 		/* When using VLAN untagging in combination with DSA, the
+ 		 * hardware treats the MTK special tag as a VLAN and untags it.
+ 		 */
+-		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) &&
+ 		    (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
+ 			unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
+ 
+@@ -2382,7 +2382,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 		txd->txd2 = next_ptr;
+ 		txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+ 		txd->txd4 = 0;
+-		if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
++		if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) {
+ 			txd->txd5 = 0;
+ 			txd->txd6 = 0;
+ 			txd->txd7 = 0;
+@@ -2435,7 +2435,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ 			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
+ 			      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+-			if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++			if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+ 				val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
+ 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
+ 			ofs += MTK_QTX_OFFSET;
+@@ -2571,7 +2571,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 
+ 		rxd->rxd3 = 0;
+ 		rxd->rxd4 = 0;
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+ 			rxd->rxd5 = 0;
+ 			rxd->rxd6 = 0;
+ 			rxd->rxd7 = 0;
+@@ -3122,7 +3122,7 @@ static int mtk_start_dma(struct mtk_eth
+ 		       MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
+ 		       MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+ 			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
+ 			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
+ 			       MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
+@@ -3532,7 +3532,7 @@ static void mtk_hw_reset(struct mtk_eth
+ {
+ 	u32 val;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
+ 		val = RSTCTRL_PPE0_V2;
+ 	} else {
+@@ -3544,7 +3544,7 @@ static void mtk_hw_reset(struct mtk_eth
+ 
+ 	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 			     0x3ffffff);
+ }
+@@ -3740,7 +3740,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	else
+ 		mtk_hw_reset(eth);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+ 		/* Set FE to PDMAv2 if necessary */
+ 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
+ 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
+@@ -3777,7 +3777,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	 */
+ 	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
+ 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+-	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
+ 		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
+ 		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
+ 
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -819,6 +819,7 @@ enum mkt_eth_capabilities {
+ 	MTK_SHARED_INT_BIT,
+ 	MTK_TRGMII_MT7621_CLK_BIT,
+ 	MTK_QDMA_BIT,
++	MTK_NETSYS_V1_BIT,
+ 	MTK_NETSYS_V2_BIT,
+ 	MTK_SOC_MT7628_BIT,
+ 	MTK_RSTCTRL_PPE1_BIT,
+@@ -854,6 +855,7 @@ enum mkt_eth_capabilities {
+ #define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
+ #define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
+ #define MTK_QDMA		BIT(MTK_QDMA_BIT)
++#define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
+ #define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
+ #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
+ #define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
+@@ -916,25 +918,30 @@ enum mkt_eth_capabilities {
+ 
+ #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x))
+ 
+-#define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
+-		      MTK_GMAC2_RGMII | MTK_SHARED_INT | \
+-		      MTK_TRGMII_MT7621_CLK | MTK_QDMA)
+-
+-#define MT7622_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
+-		      MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
+-		      MTK_MUX_GDM1_TO_GMAC1_ESW | \
+-		      MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
+-
+-#define MT7623_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
+-		      MTK_QDMA)
+-
+-#define MT7628_CAPS  (MTK_SHARED_INT | MTK_SOC_MT7628)
+-
+-#define MT7629_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
+-		      MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
+-		      MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
+-		      MTK_MUX_U3_GMAC2_TO_QPHY | \
+-		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
++#define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII |	\
++		      MTK_GMAC2_RGMII | MTK_SHARED_INT |	\
++		      MTK_TRGMII_MT7621_CLK | MTK_QDMA |	\
++		      MTK_NETSYS_V1)
++
++#define MT7622_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII |	\
++		      MTK_GMAC2_RGMII | MTK_GMAC2_SGMII |	\
++		      MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\
++		      MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII |	\
++		      MTK_QDMA | MTK_NETSYS_V1)
++
++#define MT7623_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII |	\
++		      MTK_GMAC2_RGMII | MTK_QDMA |		\
++		      MTK_NETSYS_V1)
++
++#define MT7628_CAPS  (MTK_SHARED_INT | MTK_SOC_MT7628 |		\
++		      MTK_NETSYS_V1)
++
++#define MT7629_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII |	\
++		      MTK_GMAC2_GEPHY | MTK_GDM1_ESW |		\
++		      MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA |	\
++		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\
++		      MTK_MUX_GDM1_TO_GMAC1_ESW |		\
++		      MTK_MUX_GMAC12_TO_GEPHY_SGMII)
+ 
+ #define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
diff --git a/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch
new file mode 100644
index 00000000000000..69d552a1f14a04
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch
@@ -0,0 +1,181 @@
+From 5af2b2dc4d6ba0ff7696e79f18e5b2bf862194eb Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 7 Mar 2023 15:55:24 +0000
+Subject: [PATCH 2/7] net: ethernet: mtk_eth_soc: move MAX_DEVS in mtk_soc_data
+
+This is a preliminary patch to add MT7988 SoC support since it runs 3
+macs instead of 2.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 34 +++++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 +++----
+ 2 files changed, 36 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4029,7 +4029,10 @@ static void mtk_sgmii_destroy(struct mtk
+ {
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAX_DEVS; i++)
++	if (!eth->sgmii_pcs)
++		return;
++
++	for (i = 0; i < eth->soc->num_devs; i++)
+ 		mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
+ }
+ 
+@@ -4482,7 +4485,12 @@ static int mtk_sgmii_init(struct mtk_eth
+ 	u32 flags;
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAX_DEVS; i++) {
++	eth->sgmii_pcs = devm_kzalloc(eth->dev,
++				      sizeof(*eth->sgmii_pcs) *
++				      eth->soc->num_devs,
++				      GFP_KERNEL);
++
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
+ 		if (!np)
+ 			break;
+@@ -4527,6 +4535,18 @@ static int mtk_probe(struct platform_dev
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ 		eth->ip_align = NET_IP_ALIGN;
+ 
++	eth->netdev = devm_kzalloc(eth->dev,
++				   sizeof(*eth->netdev) * eth->soc->num_devs,
++				   GFP_KERNEL);
++	if (!eth->netdev)
++		return -ENOMEM;
++
++	eth->mac = devm_kzalloc(eth->dev,
++				sizeof(*eth->mac) * eth->soc->num_devs,
++				GFP_KERNEL);
++	if (!eth->mac)
++		return -ENOMEM;
++
+ 	spin_lock_init(&eth->page_lock);
+ 	spin_lock_init(&eth->tx_irq_lock);
+ 	spin_lock_init(&eth->rx_irq_lock);
+@@ -4712,7 +4732,7 @@ static int mtk_probe(struct platform_dev
+ 			goto err_deinit_ppe;
+ 	}
+ 
+-	for (i = 0; i < MTK_MAX_DEVS; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->netdev[i])
+ 			continue;
+ 
+@@ -4788,6 +4808,7 @@ static const struct mtk_soc_data mt2701_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7623_CLKS_BITMAP,
+ 	.required_pctl = true,
++	.num_devs = 2,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4806,6 +4827,7 @@ static const struct mtk_soc_data mt7621_
+ 	.required_pctl = false,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
++	.num_devs = 2,
+ 	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+@@ -4827,6 +4849,7 @@ static const struct mtk_soc_data mt7622_
+ 	.offload_version = 2,
+ 	.hash_offset = 2,
+ 	.has_accounting = true,
++	.num_devs = 2,
+ 	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+@@ -4846,6 +4869,7 @@ static const struct mtk_soc_data mt7623_
+ 	.required_pctl = true,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
++	.num_devs = 2,
+ 	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+@@ -4865,6 +4889,7 @@ static const struct mtk_soc_data mt7629_
+ 	.required_clks = MT7629_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.has_accounting = true,
++	.num_devs = 2,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4886,6 +4911,7 @@ static const struct mtk_soc_data mt7981_
+ 	.hash_offset = 4,
+ 	.foe_entry_size = sizeof(struct mtk_foe_entry),
+ 	.has_accounting = true,
++	.num_devs = 2,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+@@ -4904,6 +4930,7 @@ static const struct mtk_soc_data mt7986_
+ 	.required_clks = MT7986_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.hash_offset = 4,
++	.num_devs = 2,
+ 	.foe_entry_size = sizeof(struct mtk_foe_entry),
+ 	.has_accounting = true,
+ 	.txrx = {
+@@ -4922,6 +4949,7 @@ static const struct mtk_soc_data rt5350_
+ 	.hw_features = MTK_HW_FEATURES_MT7628,
+ 	.required_clks = MT7628_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.num_devs = 2,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1021,6 +1021,7 @@ struct mtk_reg_map {
+  * @required_pctl		A bool value to show whether the SoC requires
+  *				the extra setup for those pins used by GMAC.
+  * @hash_offset			Flow table hash offset.
++ * @num_devs			SoC number of macs.
+  * @foe_entry_size		Foe table entry size.
+  * @has_accounting		Bool indicating support for accounting of
+  *				offloaded flows.
+@@ -1039,6 +1040,7 @@ struct mtk_soc_data {
+ 	bool		required_pctl;
+ 	u8		offload_version;
+ 	u8		hash_offset;
++	u8		num_devs;
+ 	u16		foe_entry_size;
+ 	netdev_features_t hw_features;
+ 	bool		has_accounting;
+@@ -1054,9 +1056,6 @@ struct mtk_soc_data {
+ 
+ #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
+ 
+-/* currently no SoC has more than 2 macs */
+-#define MTK_MAX_DEVS			2
+-
+ /* struct mtk_eth -	This is the main datasructure for holding the state
+  *			of the driver
+  * @dev:		The device pointer
+@@ -1111,14 +1110,14 @@ struct mtk_eth {
+ 	spinlock_t			tx_irq_lock;
+ 	spinlock_t			rx_irq_lock;
+ 	struct net_device		dummy_dev;
+-	struct net_device		*netdev[MTK_MAX_DEVS];
+-	struct mtk_mac			*mac[MTK_MAX_DEVS];
++	struct net_device		**netdev;
++	struct mtk_mac			**mac;
+ 	int				irq[3];
+ 	u32				msg_enable;
+ 	unsigned long			sysclk;
+ 	struct regmap			*ethsys;
+ 	struct regmap			*infra;
+-	struct phylink_pcs		*sgmii_pcs[MTK_MAX_DEVS];
++	struct phylink_pcs		**sgmii_pcs;
+ 	struct regmap			*pctl;
+ 	bool				hwlro;
+ 	refcount_t			dma_refcnt;
diff --git a/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch b/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch
new file mode 100644
index 00000000000000..accc54c93fce1e
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch
@@ -0,0 +1,153 @@
+From 4e35e80750b33727e606be9e7ce447bde2e0deb7 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 7 Mar 2023 15:55:35 +0000
+Subject: [PATCH 3/7] net: ethernet: mtk_eth_soc: rely on num_devs and remove
+ MTK_MAC_COUNT
+
+Get rid of MTK_MAC_COUNT since it is a duplicated of eth->soc->num_devs.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 ++++++++++-----------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 -
+ 2 files changed, 15 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -944,7 +944,7 @@ static void mtk_stats_update(struct mtk_
+ {
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
+ 			continue;
+ 		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
+@@ -1449,7 +1449,7 @@ static int mtk_queue_stopped(struct mtk_
+ {
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->netdev[i])
+ 			continue;
+ 		if (netif_queue_stopped(eth->netdev[i]))
+@@ -1463,7 +1463,7 @@ static void mtk_wake_queue(struct mtk_et
+ {
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->netdev[i])
+ 			continue;
+ 		netif_tx_wake_all_queues(eth->netdev[i]);
+@@ -1956,7 +1956,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
+ 			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
+ 
+-		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
++		if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
+ 			     !eth->netdev[mac]))
+ 			goto release_desc;
+ 
+@@ -2996,7 +2996,7 @@ static void mtk_dma_free(struct mtk_eth
+ 	const struct mtk_soc_data *soc = eth->soc;
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++)
++	for (i = 0; i < soc->num_devs; i++)
+ 		if (eth->netdev[i])
+ 			netdev_reset_queue(eth->netdev[i]);
+ 	if (eth->scratch_ring) {
+@@ -3150,7 +3150,7 @@ static void mtk_gdm_config(struct mtk_et
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ 		return;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+ 
+ 		/* default setup the forward port to send frame to PDMA */
+@@ -3761,7 +3761,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	 * up with the more appropriate value when mtk_mac_config call is being
+ 	 * invoked.
+ 	 */
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		struct net_device *dev = eth->netdev[i];
+ 
+ 		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
+@@ -3949,7 +3949,7 @@ static void mtk_pending_work(struct work
+ 	mtk_prepare_for_reset(eth);
+ 
+ 	/* stop all devices to make sure that dma is properly shut down */
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
+ 			continue;
+ 
+@@ -3965,7 +3965,7 @@ static void mtk_pending_work(struct work
+ 	mtk_hw_init(eth, true);
+ 
+ 	/* restart DMA and enable IRQs */
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!test_bit(i, &restart))
+ 			continue;
+ 
+@@ -3993,7 +3993,7 @@ static int mtk_free_dev(struct mtk_eth *
+ {
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->netdev[i])
+ 			continue;
+ 		free_netdev(eth->netdev[i]);
+@@ -4012,7 +4012,7 @@ static int mtk_unreg_dev(struct mtk_eth
+ {
+ 	int i;
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		struct mtk_mac *mac;
+ 		if (!eth->netdev[i])
+ 			continue;
+@@ -4316,7 +4316,7 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	}
+ 
+ 	id = be32_to_cpup(_id);
+-	if (id >= MTK_MAC_COUNT) {
++	if (id >= eth->soc->num_devs) {
+ 		dev_err(eth->dev, "%d is not a valid mac id\n", id);
+ 		return -EINVAL;
+ 	}
+@@ -4457,7 +4457,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+ 
+ 	rtnl_lock();
+ 
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		dev = eth->netdev[i];
+ 
+ 		if (!dev || !(dev->flags & IFF_UP))
+@@ -4783,7 +4783,7 @@ static int mtk_remove(struct platform_de
+ 	int i;
+ 
+ 	/* stop all devices to make sure that dma is properly shut down */
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
++	for (i = 0; i < eth->soc->num_devs; i++) {
+ 		if (!eth->netdev[i])
+ 			continue;
+ 		mtk_stop(eth->netdev[i]);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -33,7 +33,6 @@
+ #define MTK_TX_DMA_BUF_LEN_V2	0xffff
+ #define MTK_QDMA_RING_SIZE	2048
+ #define MTK_DMA_SIZE		512
+-#define MTK_MAC_COUNT		2
+ #define MTK_RX_ETH_HLEN		(VLAN_ETH_HLEN + ETH_FCS_LEN)
+ #define MTK_RX_HLEN		(NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
+ #define MTK_DMA_DUMMY_DESC	0xffffffff
diff --git a/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch b/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch
new file mode 100644
index 00000000000000..3cf8ce85de5de3
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch
@@ -0,0 +1,292 @@
+From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 7 Mar 2023 15:55:47 +0000
+Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability
+ bit
+
+Introduce MTK_NETSYS_V3 bit in the device capabilities.
+This is a preliminary patch to introduce support for MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  44 +++++++-
+ 2 files changed, 134 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -924,17 +924,32 @@ void mtk_stats_update_mac(struct mtk_mac
+ 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
+ 		hw_stats->rx_flow_control_packets +=
+ 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
+-		hw_stats->tx_skip +=
+-			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
+-		hw_stats->tx_collisions +=
+-			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
+-		hw_stats->tx_bytes +=
+-			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
+-		stats =  mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
+-		if (stats)
+-			hw_stats->tx_bytes += (stats << 32);
+-		hw_stats->tx_packets +=
+-			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++			hw_stats->tx_skip +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
++			hw_stats->tx_collisions +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
++			hw_stats->tx_bytes +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
++			stats =  mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
++			if (stats)
++				hw_stats->tx_bytes += (stats << 32);
++			hw_stats->tx_packets +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
++		} else {
++			hw_stats->tx_skip +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
++			hw_stats->tx_collisions +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
++			hw_stats->tx_bytes +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
++			stats =  mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
++			if (stats)
++				hw_stats->tx_bytes += (stats << 32);
++			hw_stats->tx_packets +=
++				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
++		}
+ 	}
+ 
+ 	u64_stats_update_end(&hw_stats->syncp);
+@@ -1238,7 +1253,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+ 		data |= TX_DMA_LS0;
+ 	WRITE_ONCE(desc->txd3, data);
+ 
+-	data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
++	if (mac->id == MTK_GMAC3_ID)
++		data = PSE_GDM3_PORT;
++	else
++		data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
+ 	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
+ 	WRITE_ONCE(desc->txd4, data);
+ 
+@@ -1249,6 +1267,9 @@ static void mtk_tx_set_dma_desc_v2(struc
+ 		/* tx checksum offload */
+ 		if (info->csum)
+ 			data |= TX_DMA_CHKSUM_V2;
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
++		    netdev_uses_dsa(dev))
++			data |= TX_DMA_SPTAG_V3;
+ 	}
+ 	WRITE_ONCE(desc->txd5, data);
+ 
+@@ -1314,8 +1335,13 @@ static int mtk_tx_map(struct sk_buff *sk
+ 	mtk_tx_set_dma_desc(dev, itxd, &txd_info);
+ 
+ 	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
+-	itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
+-			  MTK_TX_FLAGS_FPORT1;
++	if (mac->id == MTK_GMAC1_ID)
++		itx_buf->flags |= MTK_TX_FLAGS_FPORT0;
++	else if (mac->id == MTK_GMAC2_ID)
++		itx_buf->flags |= MTK_TX_FLAGS_FPORT1;
++	else
++		itx_buf->flags |= MTK_TX_FLAGS_FPORT2;
++
+ 	setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
+ 		     k++);
+ 
+@@ -1363,8 +1389,13 @@ static int mtk_tx_map(struct sk_buff *sk
+ 				memset(tx_buf, 0, sizeof(*tx_buf));
+ 			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
+ 			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
+-			tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
+-					 MTK_TX_FLAGS_FPORT1;
++
++			if (mac->id == MTK_GMAC1_ID)
++				tx_buf->flags |= MTK_TX_FLAGS_FPORT0;
++			else if (mac->id == MTK_GMAC2_ID)
++				tx_buf->flags |= MTK_TX_FLAGS_FPORT1;
++			else
++				tx_buf->flags |= MTK_TX_FLAGS_FPORT2;
+ 
+ 			setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
+ 				     txd_info.size, k++);
+@@ -1950,11 +1981,24 @@ static int mtk_poll_rx(struct napi_struc
+ 			break;
+ 
+ 		/* find out which mac the packet come from. values start at 1 */
+-		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+-			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
+-		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
+-			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
++		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
++			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
++
++			switch (val) {
++			case PSE_GDM1_PORT:
++			case PSE_GDM2_PORT:
++				mac = val - 1;
++				break;
++			case PSE_GDM3_PORT:
++				mac = MTK_GMAC3_ID;
++				break;
++			default:
++				break;
++			}
++		} else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
++			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
+ 			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
++		}
+ 
+ 		if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
+ 			     !eth->netdev[mac]))
+@@ -2185,7 +2229,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ 		tx_buf = mtk_desc_to_tx_buf(ring, desc,
+ 					    eth->soc->txrx.txd_size);
+ 		if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
+-			mac = 1;
++			mac = MTK_GMAC2_ID;
++		else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2)
++			mac = MTK_GMAC3_ID;
+ 
+ 		if (!tx_buf->data)
+ 			break;
+@@ -3799,7 +3845,26 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
+ 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++		/* PSE should not drop port1, port8 and port9 packets */
++		mtk_w32(eth, 0x00000302, PSE_DROP_CFG);
++
++		/* GDM and CDM Threshold */
++		mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES);
++		mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
++
++		/* Disable GDM1 RX CRC stripping */
++		val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0));
++		val &= ~MTK_GDMA_STRP_CRC;
++		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0));
++
++		/* PSE GDM3 MIB counter has incorrect hw default values,
++		 * so the driver ought to read clear the values beforehand
++		 * in case ethtool retrieve wrong mib values.
++		 */
++		for (i = 0; i < 0x80; i += 0x4)
++			mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
++	} else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ 		/* PSE should not drop port8 and port9 packets from WDMA Tx */
+ 		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
+ 
+@@ -4364,7 +4429,11 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	}
+ 	spin_lock_init(&mac->hw_stats->stats_lock);
+ 	u64_stats_init(&mac->hw_stats->syncp);
+-	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
++
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
++		mac->hw_stats->reg_offset = id * 0x80;
++	else
++		mac->hw_stats->reg_offset = id * 0x40;
+ 
+ 	/* phylink create */
+ 	err = of_get_phy_mode(np, &phy_mode);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -121,6 +121,7 @@
+ #define MTK_GDMA_ICS_EN		BIT(22)
+ #define MTK_GDMA_TCS_EN		BIT(21)
+ #define MTK_GDMA_UCS_EN		BIT(20)
++#define MTK_GDMA_STRP_CRC	BIT(16)
+ #define MTK_GDMA_TO_PDMA	0x0
+ #define MTK_GDMA_DROP_ALL       0x7777
+ 
+@@ -286,8 +287,6 @@
+ /* QDMA Interrupt grouping registers */
+ #define MTK_RLS_DONE_INT	BIT(0)
+ 
+-#define MTK_STAT_OFFSET		0x40
+-
+ /* QDMA TX NUM */
+ #define QID_BITS_V2(x)		(((x) & 0x3f) << 16)
+ #define MTK_QDMA_GMAC2_QID	8
+@@ -300,6 +299,8 @@
+ #define TX_DMA_CHKSUM_V2	(0x7 << 28)
+ #define TX_DMA_TSO_V2		BIT(31)
+ 
++#define TX_DMA_SPTAG_V3         BIT(27)
++
+ /* QDMA V2 descriptor txd4 */
+ #define TX_DMA_FPORT_SHIFT_V2	8
+ #define TX_DMA_FPORT_MASK_V2	0xf
+@@ -639,6 +640,7 @@ enum mtk_tx_flags {
+ 	 */
+ 	MTK_TX_FLAGS_FPORT0	= 0x04,
+ 	MTK_TX_FLAGS_FPORT1	= 0x08,
++	MTK_TX_FLAGS_FPORT2	= 0x10,
+ };
+ 
+ /* This enum allows us to identify how the clock is defined on the array of the
+@@ -724,6 +726,42 @@ enum mtk_dev_state {
+ 	MTK_RESETTING
+ };
+ 
++/* PSE Port Definition */
++enum mtk_pse_port {
++	PSE_ADMA_PORT = 0,
++	PSE_GDM1_PORT,
++	PSE_GDM2_PORT,
++	PSE_PPE0_PORT,
++	PSE_PPE1_PORT,
++	PSE_QDMA_TX_PORT,
++	PSE_QDMA_RX_PORT,
++	PSE_DROP_PORT,
++	PSE_WDMA0_PORT,
++	PSE_WDMA1_PORT,
++	PSE_TDMA_PORT,
++	PSE_NONE_PORT,
++	PSE_PPE2_PORT,
++	PSE_WDMA2_PORT,
++	PSE_EIP197_PORT,
++	PSE_GDM3_PORT,
++	PSE_PORT_MAX
++};
++
++/* GMAC Identifier */
++enum mtk_gmac_id {
++	MTK_GMAC1_ID = 0,
++	MTK_GMAC2_ID,
++	MTK_GMAC3_ID,
++	MTK_GMAC_ID_MAX
++};
++
++/* GDM Type */
++enum mtk_gdm_type {
++	MTK_GDM_TYPE = 0,
++	MTK_XGDM_TYPE,
++	MTK_GDM_TYPE_MAX
++};
++
+ enum mtk_tx_buf_type {
+ 	MTK_TYPE_SKB,
+ 	MTK_TYPE_XDP_TX,
+@@ -820,6 +858,7 @@ enum mkt_eth_capabilities {
+ 	MTK_QDMA_BIT,
+ 	MTK_NETSYS_V1_BIT,
+ 	MTK_NETSYS_V2_BIT,
++	MTK_NETSYS_V3_BIT,
+ 	MTK_SOC_MT7628_BIT,
+ 	MTK_RSTCTRL_PPE1_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
+@@ -856,6 +895,7 @@ enum mkt_eth_capabilities {
+ #define MTK_QDMA		BIT(MTK_QDMA_BIT)
+ #define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
+ #define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
++#define MTK_NETSYS_V3		BIT(MTK_NETSYS_V3_BIT)
+ #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
+ #define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
+ #define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
diff --git a/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch b/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch
new file mode 100644
index 00000000000000..068201cf7dfb24
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch
@@ -0,0 +1,197 @@
+From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 7 Mar 2023 15:56:00 +0000
+Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data
+ struct to u64
+
+This is a preliminary patch to introduce support for MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 62 ++++++++++----------
+ 2 files changed, 42 insertions(+), 42 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
+@@ -15,10 +15,10 @@
+ struct mtk_eth_muxc {
+ 	const char	*name;
+ 	int		cap_bit;
+-	int		(*set_path)(struct mtk_eth *eth, int path);
++	int		(*set_path)(struct mtk_eth *eth, u64 path);
+ };
+ 
+-static const char *mtk_eth_path_name(int path)
++static const char *mtk_eth_path_name(u64 path)
+ {
+ 	switch (path) {
+ 	case MTK_ETH_PATH_GMAC1_RGMII:
+@@ -40,7 +40,7 @@ static const char *mtk_eth_path_name(int
+ 	}
+ }
+ 
+-static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path)
++static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
+ {
+ 	bool updated = true;
+ 	u32 val, mask, set;
+@@ -71,7 +71,7 @@ static int set_mux_gdm1_to_gmac1_esw(str
+ 	return 0;
+ }
+ 
+-static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path)
++static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path)
+ {
+ 	unsigned int val = 0;
+ 	bool updated = true;
+@@ -94,7 +94,7 @@ static int set_mux_gmac2_gmac0_to_gephy(
+ 	return 0;
+ }
+ 
+-static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
++static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
+ {
+ 	unsigned int val = 0, mask = 0, reg = 0;
+ 	bool updated = true;
+@@ -125,7 +125,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
+ 	return 0;
+ }
+ 
+-static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path)
++static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
+ {
+ 	unsigned int val = 0;
+ 	bool updated = true;
+@@ -163,7 +163,7 @@ static int set_mux_gmac1_gmac2_to_sgmii_
+ 	return 0;
+ }
+ 
+-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path)
++static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
+ {
+ 	unsigned int val = 0;
+ 	bool updated = true;
+@@ -218,7 +218,7 @@ static const struct mtk_eth_muxc mtk_eth
+ 	},
+ };
+ 
+-static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)
++static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path)
+ {
+ 	int i, err = 0;
+ 
+@@ -249,7 +249,7 @@ out:
+ 
+ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
+ {
+-	int path;
++	u64 path;
+ 
+ 	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_SGMII :
+ 				MTK_ETH_PATH_GMAC2_SGMII;
+@@ -260,7 +260,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk
+ 
+ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
+ {
+-	int path = 0;
++	u64 path = 0;
+ 
+ 	if (mac_id == 1)
+ 		path = MTK_ETH_PATH_GMAC2_GEPHY;
+@@ -274,7 +274,7 @@ int mtk_gmac_gephy_path_setup(struct mtk
+ 
+ int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
+ {
+-	int path;
++	u64 path;
+ 
+ 	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_RGMII :
+ 				MTK_ETH_PATH_GMAC2_RGMII;
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -881,44 +881,44 @@ enum mkt_eth_capabilities {
+ };
+ 
+ /* Supported hardware group on SoCs */
+-#define MTK_RGMII		BIT(MTK_RGMII_BIT)
+-#define MTK_TRGMII		BIT(MTK_TRGMII_BIT)
+-#define MTK_SGMII		BIT(MTK_SGMII_BIT)
+-#define MTK_ESW			BIT(MTK_ESW_BIT)
+-#define MTK_GEPHY		BIT(MTK_GEPHY_BIT)
+-#define MTK_MUX			BIT(MTK_MUX_BIT)
+-#define MTK_INFRA		BIT(MTK_INFRA_BIT)
+-#define MTK_SHARED_SGMII	BIT(MTK_SHARED_SGMII_BIT)
+-#define MTK_HWLRO		BIT(MTK_HWLRO_BIT)
+-#define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
+-#define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
+-#define MTK_QDMA		BIT(MTK_QDMA_BIT)
+-#define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
+-#define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
+-#define MTK_NETSYS_V3		BIT(MTK_NETSYS_V3_BIT)
+-#define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
+-#define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
+-#define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
++#define MTK_RGMII		BIT_ULL(MTK_RGMII_BIT)
++#define MTK_TRGMII		BIT_ULL(MTK_TRGMII_BIT)
++#define MTK_SGMII		BIT_ULL(MTK_SGMII_BIT)
++#define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
++#define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
++#define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
++#define MTK_INFRA		BIT_ULL(MTK_INFRA_BIT)
++#define MTK_SHARED_SGMII	BIT_ULL(MTK_SHARED_SGMII_BIT)
++#define MTK_HWLRO		BIT_ULL(MTK_HWLRO_BIT)
++#define MTK_SHARED_INT		BIT_ULL(MTK_SHARED_INT_BIT)
++#define MTK_TRGMII_MT7621_CLK	BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
++#define MTK_QDMA		BIT_ULL(MTK_QDMA_BIT)
++#define MTK_NETSYS_V1		BIT_ULL(MTK_NETSYS_V1_BIT)
++#define MTK_NETSYS_V2		BIT_ULL(MTK_NETSYS_V2_BIT)
++#define MTK_NETSYS_V3		BIT_ULL(MTK_NETSYS_V3_BIT)
++#define MTK_SOC_MT7628		BIT_ULL(MTK_SOC_MT7628_BIT)
++#define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
++#define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
+ 
+ #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
+-	BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
++	BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
+ #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY	\
+-	BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
++	BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
+ #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
+-	BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
++	BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
+ #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII	\
+-	BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
++	BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
+ #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\
+-	BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
++	BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
+ 
+ /* Supported path present on SoCs */
+-#define MTK_ETH_PATH_GMAC1_RGMII	BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
+-#define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
+-#define MTK_ETH_PATH_GMAC1_SGMII	BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
+-#define MTK_ETH_PATH_GMAC2_RGMII	BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
+-#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+-#define MTK_ETH_PATH_GMAC2_GEPHY	BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
+-#define MTK_ETH_PATH_GDM1_ESW		BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
++#define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
++#define MTK_ETH_PATH_GMAC1_TRGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
++#define MTK_ETH_PATH_GMAC1_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
++#define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
++#define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
++#define MTK_ETH_PATH_GMAC2_GEPHY	BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
++#define MTK_ETH_PATH_GDM1_ESW		BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
+ 
+ #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
+ #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
+@@ -1074,7 +1074,7 @@ struct mtk_reg_map {
+ struct mtk_soc_data {
+ 	const struct mtk_reg_map *reg_map;
+ 	u32             ana_rgc3;
+-	u32		caps;
++	u64		caps;
+ 	u32		required_clks;
+ 	bool		required_pctl;
+ 	u8		offload_version;
diff --git a/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch
new file mode 100644
index 00000000000000..430808a9b41e77
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch
@@ -0,0 +1,495 @@
+From 661bacf4363ca68939c15e20056b5f72fbd034e7 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sat, 25 Feb 2023 00:08:24 +0100
+Subject: [PATCH 6/7] net: ethernet: mtk_eth_soc: add support for MT7988 SoC
+
+Introduce support for ethernet chip available in MT7988 SoC to
+mtk_eth_soc driver.
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 153 ++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 193 ++++++++++++++------
+ 2 files changed, 279 insertions(+), 67 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r
+ 	.pse_oq_sta		= 0x01a0,
+ };
+ 
++static const struct mtk_reg_map mt7988_reg_map = {
++	.tx_irq_mask		= 0x461c,
++	.tx_irq_status		= 0x4618,
++	.pdma = {
++		.rx_ptr		= 0x6900,
++		.rx_cnt_cfg	= 0x6904,
++		.pcrx_ptr	= 0x6908,
++		.glo_cfg	= 0x6a04,
++		.rst_idx	= 0x6a08,
++		.delay_irq	= 0x6a0c,
++		.irq_status	= 0x6a20,
++		.irq_mask	= 0x6a28,
++		.adma_rx_dbg0	= 0x6a38,
++		.int_grp	= 0x6a50,
++	},
++	.qdma = {
++		.qtx_cfg	= 0x4400,
++		.qtx_sch	= 0x4404,
++		.rx_ptr		= 0x4500,
++		.rx_cnt_cfg	= 0x4504,
++		.qcrx_ptr	= 0x4508,
++		.glo_cfg	= 0x4604,
++		.rst_idx	= 0x4608,
++		.delay_irq	= 0x460c,
++		.fc_th		= 0x4610,
++		.int_grp	= 0x4620,
++		.hred		= 0x4644,
++		.ctx_ptr	= 0x4700,
++		.dtx_ptr	= 0x4704,
++		.crx_ptr	= 0x4710,
++		.drx_ptr	= 0x4714,
++		.fq_head	= 0x4720,
++		.fq_tail	= 0x4724,
++		.fq_count	= 0x4728,
++		.fq_blen	= 0x472c,
++		.tx_sch_rate	= 0x4798,
++	},
++	.gdm1_cnt		= 0x1c00,
++	.gdma_to_ppe		= 0x3333,
++	.ppe_base		= 0x2200,
++	.wdma_base = {
++		[0]		= 0x4800,
++		[1]		= 0x4c00,
++	},
++	.pse_iq_sta		= 0x0180,
++	.pse_oq_sta		= 0x01a0,
++};
++
+ /* strings used by ethtool */
+ static const struct mtk_ethtool_stats {
+ 	char str[ETH_GSTRING_LEN];
+@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
+ };
+ 
+ static const char * const mtk_clks_source_name[] = {
+-	"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
+-	"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
+-	"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+-	"sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
++	"ethif",
++	"sgmiitop",
++	"esw",
++	"gp0",
++	"gp1",
++	"gp2",
++	"gp3",
++	"xgp1",
++	"xgp2",
++	"xgp3",
++	"crypto",
++	"fe",
++	"trgpll",
++	"sgmii_tx250m",
++	"sgmii_rx250m",
++	"sgmii_cdr_ref",
++	"sgmii_cdr_fb",
++	"sgmii2_tx250m",
++	"sgmii2_rx250m",
++	"sgmii2_cdr_ref",
++	"sgmii2_cdr_fb",
++	"sgmii_ck",
++	"eth2pll",
++	"wocpu0",
++	"wocpu1",
++	"netsys0",
++	"netsys1",
++	"ethwarp_wocpu2",
++	"ethwarp_wocpu1",
++	"ethwarp_wocpu0",
++	"top_usxgmii0_sel",
++	"top_usxgmii1_sel",
++	"top_sgm0_sel",
++	"top_sgm1_sel",
++	"top_xfi_phy0_xtal_sel",
++	"top_xfi_phy1_xtal_sel",
++	"top_eth_gmii_sel",
++	"top_eth_refck_50m_sel",
++	"top_eth_sys_200m_sel",
++	"top_eth_sys_sel",
++	"top_eth_xgmii_sel",
++	"top_eth_mii_sel",
++	"top_netsys_sel",
++	"top_netsys_500m_sel",
++	"top_netsys_pao_2x_sel",
++	"top_netsys_sync_250m_sel",
++	"top_netsys_ppefb_250m_sel",
++	"top_netsys_warp_sel",
+ };
+ 
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
+@@ -1253,10 +1345,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+ 		data |= TX_DMA_LS0;
+ 	WRITE_ONCE(desc->txd3, data);
+ 
+-	if (mac->id == MTK_GMAC3_ID)
+-		data = PSE_GDM3_PORT;
+-	else
+-		data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
++	 /* set forward port */
++	switch (mac->id) {
++	case MTK_GMAC1_ID:
++		data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	case MTK_GMAC2_ID:
++		data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	case MTK_GMAC3_ID:
++		data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	}
++
+ 	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
+ 	WRITE_ONCE(desc->txd4, data);
+ 
+@@ -5012,6 +5113,25 @@ static const struct mtk_soc_data mt7986_
+ 	},
+ };
+ 
++static const struct mtk_soc_data mt7988_data = {
++	.reg_map = &mt7988_reg_map,
++	.ana_rgc3 = 0x128,
++	.caps = MT7988_CAPS,
++	.hw_features = MTK_HW_FEATURES,
++	.required_clks = MT7988_CLKS_BITMAP,
++	.required_pctl = false,
++	.num_devs = 3,
++	.txrx = {
++		.txd_size = sizeof(struct mtk_tx_dma_v2),
++		.rxd_size = sizeof(struct mtk_rx_dma_v2),
++		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
++		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++		.dma_len_offset = 8,
++	},
++};
++
++
+ static const struct mtk_soc_data rt5350_data = {
+ 	.reg_map = &mt7628_reg_map,
+ 	.caps = MT7628_CAPS,
+@@ -5030,14 +5150,15 @@ static const struct mtk_soc_data rt5350_
+ };
+ 
+ const struct of_device_id of_mtk_match[] = {
+-	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
+-	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
+-	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
+-	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
+-	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
+-	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
+-	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
+-	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
++	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
++	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
++	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
++	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
++	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
++	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
++	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
++	{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
++	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, of_mtk_match);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -116,7 +116,8 @@
+ #define MTK_CDMP_EG_CTRL	0x404
+ 
+ /* GDM Exgress Control Register */
+-#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
++#define MTK_GDMA_FWD_CFG(x)	((x == MTK_GMAC3_ID) ?		\
++				 0x540 : 0x500 + (x * 0x1000))
+ #define MTK_GDMA_SPECIAL_TAG	BIT(24)
+ #define MTK_GDMA_ICS_EN		BIT(22)
+ #define MTK_GDMA_TCS_EN		BIT(21)
+@@ -653,6 +654,11 @@ enum mtk_clks_map {
+ 	MTK_CLK_GP0,
+ 	MTK_CLK_GP1,
+ 	MTK_CLK_GP2,
++	MTK_CLK_GP3,
++	MTK_CLK_XGP1,
++	MTK_CLK_XGP2,
++	MTK_CLK_XGP3,
++	MTK_CLK_CRYPTO,
+ 	MTK_CLK_FE,
+ 	MTK_CLK_TRGPLL,
+ 	MTK_CLK_SGMII_TX_250M,
+@@ -669,57 +675,108 @@ enum mtk_clks_map {
+ 	MTK_CLK_WOCPU1,
+ 	MTK_CLK_NETSYS0,
+ 	MTK_CLK_NETSYS1,
++	MTK_CLK_ETHWARP_WOCPU2,
++	MTK_CLK_ETHWARP_WOCPU1,
++	MTK_CLK_ETHWARP_WOCPU0,
++	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
++	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
++	MTK_CLK_TOP_SGM_0_SEL,
++	MTK_CLK_TOP_SGM_1_SEL,
++	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
++	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
++	MTK_CLK_TOP_ETH_GMII_SEL,
++	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
++	MTK_CLK_TOP_ETH_SYS_200M_SEL,
++	MTK_CLK_TOP_ETH_SYS_SEL,
++	MTK_CLK_TOP_ETH_XGMII_SEL,
++	MTK_CLK_TOP_ETH_MII_SEL,
++	MTK_CLK_TOP_NETSYS_SEL,
++	MTK_CLK_TOP_NETSYS_500M_SEL,
++	MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
++	MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
++	MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
++	MTK_CLK_TOP_NETSYS_WARP_SEL,
+ 	MTK_CLK_MAX
+ };
+ 
+-#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
+-				 BIT(MTK_CLK_TRGPLL))
+-#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_GP2) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK) | \
+-				 BIT(MTK_CLK_ETH2PLL))
++#define MT7623_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_TRGPLL))
++#define MT7622_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK) | \
++				 BIT_ULL(MTK_CLK_ETH2PLL))
+ #define MT7621_CLKS_BITMAP	(0)
+ #define MT7628_CLKS_BITMAP	(0)
+-#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK) | \
+-				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
+-#define MT7981_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_WOCPU0) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK))
+-#define MT7986_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB))
++#define MT7629_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK) | \
++				 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
++#define MT7981_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK))
++#define MT7986_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
++#define MT7988_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
++				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
++				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
++				 BIT_ULL(MTK_CLK_CRYPTO) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
+ 
+ enum mtk_dev_state {
+ 	MTK_HW_INIT,
+@@ -847,6 +904,7 @@ enum mkt_eth_capabilities {
+ 	MTK_RGMII_BIT = 0,
+ 	MTK_TRGMII_BIT,
+ 	MTK_SGMII_BIT,
++	MTK_USXGMII_BIT,
+ 	MTK_ESW_BIT,
+ 	MTK_GEPHY_BIT,
+ 	MTK_MUX_BIT,
+@@ -869,6 +927,8 @@ enum mkt_eth_capabilities {
+ 	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
+ 	MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
+ 	MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
++	MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
++	MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
+ 
+ 	/* PATH BITS */
+ 	MTK_ETH_PATH_GMAC1_RGMII_BIT,
+@@ -877,13 +937,18 @@ enum mkt_eth_capabilities {
+ 	MTK_ETH_PATH_GMAC2_RGMII_BIT,
+ 	MTK_ETH_PATH_GMAC2_SGMII_BIT,
+ 	MTK_ETH_PATH_GMAC2_GEPHY_BIT,
++	MTK_ETH_PATH_GMAC3_SGMII_BIT,
+ 	MTK_ETH_PATH_GDM1_ESW_BIT,
++	MTK_ETH_PATH_GMAC1_USXGMII_BIT,
++	MTK_ETH_PATH_GMAC2_USXGMII_BIT,
++	MTK_ETH_PATH_GMAC3_USXGMII_BIT,
+ };
+ 
+ /* Supported hardware group on SoCs */
+ #define MTK_RGMII		BIT_ULL(MTK_RGMII_BIT)
+ #define MTK_TRGMII		BIT_ULL(MTK_TRGMII_BIT)
+ #define MTK_SGMII		BIT_ULL(MTK_SGMII_BIT)
++#define MTK_USXGMII		BIT_ULL(MTK_USXGMII_BIT)
+ #define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
+ #define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
+ #define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
+@@ -910,6 +975,10 @@ enum mkt_eth_capabilities {
+ 	BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
+ #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\
+ 	BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
++#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII	\
++	BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
++#define MTK_ETH_MUX_GMAC123_TO_USXGMII	\
++	BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
+ 
+ /* Supported path present on SoCs */
+ #define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
+@@ -918,7 +987,11 @@ enum mkt_eth_capabilities {
+ #define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
+ #define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+ #define MTK_ETH_PATH_GMAC2_GEPHY	BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
++#define MTK_ETH_PATH_GMAC3_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
+ #define MTK_ETH_PATH_GDM1_ESW		BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
++#define MTK_ETH_PATH_GMAC1_USXGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
++#define MTK_ETH_PATH_GMAC2_USXGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
++#define MTK_ETH_PATH_GMAC3_USXGMII	BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
+ 
+ #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
+ #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
+@@ -926,7 +999,11 @@ enum mkt_eth_capabilities {
+ #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
+ #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
+ #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
++#define MTK_GMAC3_SGMII		(MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
+ #define MTK_GDM1_ESW		(MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
++#define MTK_GMAC1_USXGMII	(MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
++#define MTK_GMAC2_USXGMII	(MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
++#define MTK_GMAC3_USXGMII	(MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
+ 
+ /* MUXes present on SoCs */
+ /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
+@@ -949,6 +1026,12 @@ enum mkt_eth_capabilities {
+ #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
+ 	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
+ 
++#define MTK_MUX_GMAC123_TO_GEPHY_SGMII   \
++	(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
++
++#define MTK_MUX_GMAC123_TO_USXGMII   \
++	(MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
++
+ #ifdef CONFIG_SOC_MT7621
+ #define MTK_CAP_MASK MTK_NETSYS_V2
+ #else
+@@ -987,9 +1070,17 @@ enum mkt_eth_capabilities {
+ 		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
+ 		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
+ 
+-#define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
+-		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+-		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
++#define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII |	\
++		      MTK_MUX_GMAC12_TO_GEPHY_SGMII |		\
++		      MTK_QDMA | MTK_NETSYS_V2 |		\
++		      MTK_RSTCTRL_PPE1)
++
++#define MT7988_CAPS   (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII |	\
++		       MTK_GMAC3_SGMII | MTK_QDMA |		\
++		       MTK_MUX_GMAC123_TO_GEPHY_SGMII |		\
++		       MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 |	\
++		       MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII |	\
++		       MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+@@ -1075,7 +1166,7 @@ struct mtk_soc_data {
+ 	const struct mtk_reg_map *reg_map;
+ 	u32             ana_rgc3;
+ 	u64		caps;
+-	u32		required_clks;
++	u64		required_clks;
+ 	bool		required_pctl;
+ 	u8		offload_version;
+ 	u8		hash_offset;
diff --git a/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
new file mode 100644
index 00000000000000..f21cfcc2293a8e
--- /dev/null
+++ b/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
@@ -0,0 +1,1867 @@
+From 3d833ad2cfc1ab503d9aae2967b7f10811bb3c9c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 1 Mar 2023 11:56:04 +0000
+Subject: [PATCH 7/7] net: ethernet: mtk_eth_soc: add paths and SerDes modes 
+ for MT7988
+
+MT7988 comes with a built-in 2.5G PHY as well as
+USXGMII/10GBase-KR/5GBase-KR compatible SerDes lanes for external PHYs.
+Add support for configuring the MAC and SerDes parts for the new paths.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/Kconfig        |   7 +
+ drivers/net/ethernet/mediatek/Makefile       |   1 +
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 154 +++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 270 +++++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 194 ++++-
+ drivers/net/ethernet/mediatek/mtk_usxgmii.c  | 835 +++++++++++++++++++
+ 6 files changed, 1428 insertions(+), 33 deletions(-)
+ create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
+
+--- a/drivers/net/ethernet/mediatek/Kconfig
++++ b/drivers/net/ethernet/mediatek/Kconfig
+@@ -25,6 +25,13 @@ config NET_MEDIATEK_SOC
+ 	  This driver supports the gigabit ethernet MACs in the
+ 	  MediaTek SoC family.
+ 
++config NET_MEDIATEK_SOC_USXGMII
++	bool "Support USXGMII SerDes on MT7988"
++	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
++	def_bool NET_MEDIATEK_SOC != n
++	help
++	  Include support for 10G SerDes which can be found on MT7988.
++
+ config NET_MEDIATEK_STAR_EMAC
+ 	tristate "MediaTek STAR Ethernet MAC support"
+ 	select PHYLIB
+--- a/drivers/net/ethernet/mediatek/Makefile
++++ b/drivers/net/ethernet/mediatek/Makefile
+@@ -5,6 +5,7 @@
+ 
+ obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
+ mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
++mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
+ mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
+ ifdef CONFIG_DEBUG_FS
+ mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
+--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
+@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
+ 		return "gmac2_rgmii";
+ 	case MTK_ETH_PATH_GMAC2_SGMII:
+ 		return "gmac2_sgmii";
++	case MTK_ETH_PATH_GMAC2_2P5GPHY:
++		return "gmac2_2p5gphy";
+ 	case MTK_ETH_PATH_GMAC2_GEPHY:
+ 		return "gmac2_gephy";
++	case MTK_ETH_PATH_GMAC3_SGMII:
++		return "gmac3_sgmii";
+ 	case MTK_ETH_PATH_GDM1_ESW:
+ 		return "gdm1_esw";
++	case MTK_ETH_PATH_GMAC1_USXGMII:
++		return "gmac1_usxgmii";
++	case MTK_ETH_PATH_GMAC2_USXGMII:
++		return "gmac2_usxgmii";
++	case MTK_ETH_PATH_GMAC3_USXGMII:
++		return "gmac3_usxgmii";
+ 	default:
+ 		return "unknown path";
+ 	}
+@@ -42,8 +52,8 @@ static const char *mtk_eth_path_name(u64
+ 
+ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
+ {
++	u32 val, mask, set, reg;
+ 	bool updated = true;
+-	u32 val, mask, set;
+ 
+ 	switch (path) {
+ 	case MTK_ETH_PATH_GMAC1_SGMII:
+@@ -59,10 +69,15 @@ static int set_mux_gdm1_to_gmac1_esw(str
+ 		break;
+ 	}
+ 
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
++		reg = MTK_MAC_MISC_V3;
++	else
++		reg = MTK_MAC_MISC;
++
+ 	if (updated) {
+-		val = mtk_r32(eth, MTK_MAC_MISC);
++		val = mtk_r32(eth, reg);
+ 		val = (val & mask) | set;
+-		mtk_w32(eth, val, MTK_MAC_MISC);
++		mtk_w32(eth, val, reg);
+ 	}
+ 
+ 	dev_dbg(eth->dev, "path %s in %s updated = %d\n",
+@@ -125,6 +140,31 @@ static int set_mux_u3_gmac2_to_qphy(stru
+ 	return 0;
+ }
+ 
++static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
++{
++	unsigned int val = 0;
++	bool updated = true;
++	int mac_id = 0;
++
++	regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
++
++	switch (path) {
++	case MTK_ETH_PATH_GMAC2_2P5GPHY:
++		val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
++		mac_id = MTK_GMAC2_ID;
++		break;
++	default:
++		updated = false;
++		break;
++	};
++
++	if (updated)
++		regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
++				   SYSCFG0_SGMII_MASK, val);
++
++	return 0;
++}
++
+ static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
+ {
+ 	unsigned int val = 0;
+@@ -163,7 +203,61 @@ static int set_mux_gmac1_gmac2_to_sgmii_
+ 	return 0;
+ }
+ 
+-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
++static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
++{
++	unsigned int val = 0;
++	bool updated = true;
++	int mac_id = 0;
++
++	dev_dbg(eth->dev, "path %s in %s updated = %d\n",
++		mtk_eth_path_name(path), __func__, updated);
++
++	/* Disable SYSCFG1 SGMII */
++	regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
++
++	switch (path) {
++	case MTK_ETH_PATH_GMAC1_USXGMII:
++		val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
++		mac_id = MTK_GMAC1_ID;
++		break;
++	case MTK_ETH_PATH_GMAC2_USXGMII:
++		val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
++		mac_id = MTK_GMAC2_ID;
++		break;
++	case MTK_ETH_PATH_GMAC3_USXGMII:
++		val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
++		mac_id = MTK_GMAC3_ID;
++		break;
++	default:
++		updated = false;
++	};
++
++	if (updated) {
++		regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
++				   SYSCFG0_SGMII_MASK, val);
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
++		    mac_id == MTK_GMAC2_ID) {
++			regmap_update_bits(eth->infra,
++					   TOP_MISC_NETSYS_PCS_MUX,
++					   NETSYS_PCS_MUX_MASK,
++					   MUX_G2_USXGMII_SEL);
++		}
++	}
++
++	/* Enable XGDM Path */
++	val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac_id));
++	val |= MTK_GDMA_XGDM_SEL;
++	mtk_w32(eth, val, MTK_GDMA_EG_CTRL(mac_id));
++
++	dev_dbg(eth->dev, "path %s in %s updated = %d\n",
++		mtk_eth_path_name(path), __func__, updated);
++
++
++	return 0;
++}
++
++static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
+ {
+ 	unsigned int val = 0;
+ 	bool updated = true;
+@@ -180,6 +274,9 @@ static int set_mux_gmac12_to_gephy_sgmii
+ 	case MTK_ETH_PATH_GMAC2_SGMII:
+ 		val |= SYSCFG0_SGMII_GMAC2_V2;
+ 		break;
++	case MTK_ETH_PATH_GMAC3_SGMII:
++		val |= SYSCFG0_SGMII_GMAC3_V2;
++		break;
+ 	default:
+ 		updated = false;
+ 	}
+@@ -208,13 +305,25 @@ static const struct mtk_eth_muxc mtk_eth
+ 		.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
+ 		.set_path = set_mux_u3_gmac2_to_qphy,
+ 	}, {
++		.name = "mux_gmac2_to_2p5gphy",
++		.cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
++		.set_path = set_mux_gmac2_to_2p5gphy,
++	}, {
+ 		.name = "mux_gmac1_gmac2_to_sgmii_rgmii",
+ 		.cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
+ 		.set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
+ 	}, {
+ 		.name = "mux_gmac12_to_gephy_sgmii",
+ 		.cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
+-		.set_path = set_mux_gmac12_to_gephy_sgmii,
++		.set_path = set_mux_gmac123_to_gephy_sgmii,
++	}, {
++		.name = "mux_gmac123_to_gephy_sgmii",
++		.cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
++		.set_path = set_mux_gmac123_to_gephy_sgmii,
++	}, {
++		.name = "mux_gmac123_to_usxgmii",
++		.cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
++		.set_path = set_mux_gmac123_to_usxgmii,
+ 	},
+ };
+ 
+@@ -243,16 +352,46 @@ static int mtk_eth_mux_setup(struct mtk_
+ 		}
+ 	}
+ 
++	dev_dbg(eth->dev, "leaving mux_setup %s\n",
++		mtk_eth_path_name(path));
++
+ out:
+ 	return err;
+ }
+ 
++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
++{
++	u64 path;
++
++	path = (mac_id == MTK_GMAC1_ID) ?  MTK_ETH_PATH_GMAC1_USXGMII :
++	       (mac_id == MTK_GMAC2_ID) ?  MTK_ETH_PATH_GMAC2_USXGMII :
++					   MTK_ETH_PATH_GMAC3_USXGMII;
++
++	/* Setup proper MUXes along the path */
++	return mtk_eth_mux_setup(eth, path);
++}
++
+ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
+ {
+ 	u64 path;
+ 
+-	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_SGMII :
+-				MTK_ETH_PATH_GMAC2_SGMII;
++	path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
++	       (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
++					  MTK_ETH_PATH_GMAC3_SGMII;
++
++	/* Setup proper MUXes along the path */
++	return mtk_eth_mux_setup(eth, path);
++}
++
++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
++{
++	u64 path = 0;
++
++	if (mac_id == MTK_GMAC2_ID)
++		path = MTK_ETH_PATH_GMAC2_2P5GPHY;
++
++	if (!path)
++		return -EINVAL;
+ 
+ 	/* Setup proper MUXes along the path */
+ 	return mtk_eth_mux_setup(eth, path);
+@@ -282,4 +421,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
+ 	/* Setup proper MUXes along the path */
+ 	return mtk_eth_mux_setup(eth, path);
+ }
+-
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -480,6 +480,23 @@ static void mtk_gmac0_rgmii_adjust(struc
+ 	mtk_w32(eth, val, TRGMII_TCK_CTRL);
+ }
+ 
++static void mtk_setup_bridge_switch(struct mtk_eth *eth)
++{
++	int val;
++
++	/* Force Port1 XGMAC Link Up */
++	val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID));
++	mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
++		MTK_XGMAC_STS(MTK_GMAC1_ID));
++
++	/* Adjust GSW bridge IPG to 11*/
++	val = mtk_r32(eth, MTK_GSW_CFG);
++	val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK);
++	val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
++	       (GSW_IPG_11 << GSWRX_IPG_SHIFT);
++	mtk_w32(eth, val, MTK_GSW_CFG);
++}
++
+ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
+ 					      phy_interface_t interface)
+ {
+@@ -494,6 +511,12 @@ static struct phylink_pcs *mtk_mac_selec
+ 		       0 : mac->id;
+ 
+ 		return eth->sgmii_pcs[sid];
++	} else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
++		    interface == PHY_INTERFACE_MODE_10GKR ||
++		    interface == PHY_INTERFACE_MODE_5GBASER) &&
++		   MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
++		   mac->id != MTK_GMAC1_ID) {
++			return mtk_usxgmii_select_pcs(eth, mac->id);
+ 	}
+ 
+ 	return NULL;
+@@ -505,7 +528,7 @@ static void mtk_mac_config(struct phylin
+ 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ 					   phylink_config);
+ 	struct mtk_eth *eth = mac->hw;
+-	int val, ge_mode, err = 0;
++	int val, ge_mode, force_link, err = 0;
+ 	u32 i;
+ 
+ 	/* MT76x8 has no hardware settings between for the MAC */
+@@ -549,6 +572,23 @@ static void mtk_mac_config(struct phylin
+ 					goto init_err;
+ 			}
+ 			break;
++		case PHY_INTERFACE_MODE_USXGMII:
++		case PHY_INTERFACE_MODE_10GKR:
++		case PHY_INTERFACE_MODE_5GBASER:
++			if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
++				err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
++				if (err)
++					goto init_err;
++			}
++			break;
++		case PHY_INTERFACE_MODE_INTERNAL:
++			if (mac->id == MTK_GMAC2_ID &&
++			    MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
++				err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
++				if (err)
++					goto init_err;
++			}
++			break;
+ 		default:
+ 			goto err_phy;
+ 		}
+@@ -627,14 +667,78 @@ static void mtk_mac_config(struct phylin
+ 				   SYSCFG0_SGMII_MASK,
+ 				   ~(u32)SYSCFG0_SGMII_MASK);
+ 
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++			mtk_xfi_pll_enable(eth);
++			mtk_sgmii_reset(eth, mac->id);
++			if (phylink_autoneg_inband(mode))
++				mtk_sgmii_setup_phya_gen1(eth, mac->id);
++			else
++				mtk_sgmii_setup_phya_gen2(eth, mac->id);
++		}
+ 		/* Save the syscfg0 value for mac_finish */
+ 		mac->syscfg0 = val;
+-	} else if (phylink_autoneg_inband(mode)) {
++	} else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
++		   state->interface != PHY_INTERFACE_MODE_10GKR &&
++		   state->interface != PHY_INTERFACE_MODE_5GBASER &&
++		   phylink_autoneg_inband(mode)) {
+ 		dev_err(eth->dev,
+-			"In-band mode not supported in non SGMII mode!\n");
++			"In-band mode not supported in non-SerDes modes!\n");
+ 		return;
+ 	}
+ 
++	/* Setup gmac */
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
++	    (mtk_interface_mode_is_xgmii(state->interface) ||
++	     mac->interface == PHY_INTERFACE_MODE_INTERNAL)) {
++		mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
++		mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
++
++		switch (mac->id) {
++		case MTK_GMAC1_ID:
++			mtk_setup_bridge_switch(eth);
++			break;
++		case MTK_GMAC2_ID:
++			force_link = (mac->interface ==
++				      PHY_INTERFACE_MODE_INTERNAL) ?
++				      MTK_XGMAC_FORCE_LINK(mac->id) : 0;
++			val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
++			mtk_w32(eth, val | force_link,
++				MTK_XGMAC_STS(mac->id));
++			break;
++		case MTK_GMAC3_ID:
++			val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
++			mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(mac->id),
++				MTK_XGMAC_STS(mac->id));
++			break;
++		}
++	} else {
++		val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac->id));
++		mtk_w32(eth, val & ~MTK_GDMA_XGDM_SEL,
++			MTK_GDMA_EG_CTRL(mac->id));
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++			switch (mac->id) {
++			case MTK_GMAC2_ID:
++			case MTK_GMAC3_ID:
++				val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
++				mtk_w32(eth,
++					val & ~MTK_XGMAC_FORCE_LINK(mac->id),
++					MTK_XGMAC_STS(mac->id));
++				break;
++			}
++		}
++
++/*
++		if (mac->type != mac_type) {
++			if (atomic_read(&reset_pending) == 0) {
++				atomic_inc(&force);
++				schedule_work(&eth->pending_work);
++				atomic_inc(&reset_pending);
++			} else
++				atomic_dec(&reset_pending);
++		}
++*/
++	}
+ 	return;
+ 
+ err_phy:
+@@ -675,11 +779,40 @@ static int mtk_mac_finish(struct phylink
+ 	return 0;
+ }
+ 
+-static void mtk_mac_pcs_get_state(struct phylink_config *config,
++static void mtk_xgdm_pcs_get_state(struct mtk_mac *mac,
++				  struct phylink_link_state *state)
++{
++	u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
++
++	if (mac->id == MTK_GMAC2_ID)
++		sts = sts >> 16;
++
++	state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts);
++	if (!state->link)
++		return;
++
++	state->duplex = DUPLEX_FULL;
++	state->interface = mac->interface;
++
++	switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) {
++	case 0:
++		state->speed = SPEED_10000;
++		break;
++	case 1:
++		state->speed = SPEED_5000;
++		break;
++	case 2:
++		state->speed = SPEED_2500;
++		break;
++	case 3:
++		state->speed = SPEED_1000;
++		break;
++	}
++}
++
++static void mtk_gdm_pcs_get_state(struct mtk_mac *mac,
+ 				  struct phylink_link_state *state)
+ {
+-	struct mtk_mac *mac = container_of(config, struct mtk_mac,
+-					   phylink_config);
+ 	u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
+ 
+ 	state->link = (pmsr & MAC_MSR_LINK);
+@@ -707,15 +840,35 @@ static void mtk_mac_pcs_get_state(struct
+ 		state->pause |= MLO_PAUSE_TX;
+ }
+ 
++static void mtk_mac_pcs_get_state(struct phylink_config *config,
++				  struct phylink_link_state *state)
++{
++	struct mtk_mac *mac = container_of(config, struct mtk_mac,
++					   phylink_config);
++
++	if (mtk_interface_mode_is_xgmii(state->interface))
++		mtk_xgdm_pcs_get_state(mac, state);
++	else
++		mtk_gdm_pcs_get_state(mac, state);
++}
++
+ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
+ 			      phy_interface_t interface)
+ {
+ 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
+ 					   phylink_config);
+-	u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
++	u32 mcr;
+ 
+-	mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
+-	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
++	if (!mtk_interface_mode_is_xgmii(interface)) {
++		mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
++		mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
++		mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
++	} else if (mac->id != MTK_GMAC1_ID) {
++		mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
++		mcr &= 0xfffffff0;
++		mcr |= XMAC_MCR_TRX_DISABLE;
++		mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
++	}
+ }
+ 
+ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
+@@ -787,13 +940,11 @@ static void mtk_set_queue_speed(struct m
+ 	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
+ }
+ 
+-static void mtk_mac_link_up(struct phylink_config *config,
+-			    struct phy_device *phy,
+-			    unsigned int mode, phy_interface_t interface,
+-			    int speed, int duplex, bool tx_pause, bool rx_pause)
++static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
++				struct phy_device *phy,
++				unsigned int mode, phy_interface_t interface,
++				int speed, int duplex, bool tx_pause, bool rx_pause)
+ {
+-	struct mtk_mac *mac = container_of(config, struct mtk_mac,
+-					   phylink_config);
+ 	u32 mcr;
+ 
+ 	mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
+@@ -827,6 +978,47 @@ static void mtk_mac_link_up(struct phyli
+ 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+ }
+ 
++static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
++				 struct phy_device *phy,
++				 unsigned int mode, phy_interface_t interface,
++				 int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	u32 mcr;
++
++	if (mac->id == MTK_GMAC1_ID)
++		return;
++
++	mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
++
++	mcr &= ~(XMAC_MCR_FORCE_TX_FC |	XMAC_MCR_FORCE_RX_FC);
++	/* Configure pause modes -
++	 * phylink will avoid these for half duplex
++	 */
++	if (tx_pause)
++		mcr |= XMAC_MCR_FORCE_TX_FC;
++	if (rx_pause)
++		mcr |= XMAC_MCR_FORCE_RX_FC;
++
++	mcr &= ~(XMAC_MCR_TRX_DISABLE);
++	mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
++}
++
++static void mtk_mac_link_up(struct phylink_config *config,
++			    struct phy_device *phy,
++			    unsigned int mode, phy_interface_t interface,
++			    int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mtk_mac *mac = container_of(config, struct mtk_mac,
++					   phylink_config);
++
++	if (mtk_interface_mode_is_xgmii(interface))
++		mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
++				     tx_pause, rx_pause);
++	else
++		mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
++				    tx_pause, rx_pause);
++}
++
+ static const struct phylink_mac_ops mtk_phylink_ops = {
+ 	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mtk_mac_select_pcs,
+@@ -880,10 +1072,21 @@ static int mtk_mdio_init(struct mtk_eth
+ 	}
+ 	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
+ 
++	/* Configure MDC Turbo Mode */
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++		val = mtk_r32(eth, MTK_MAC_MISC_V3);
++		val |= MISC_MDC_TURBO;
++		mtk_w32(eth, val, MTK_MAC_MISC_V3);
++	} else {
++		val = mtk_r32(eth, MTK_PPSC);
++		val |= PPSC_MDC_TURBO;
++		mtk_w32(eth, val, MTK_PPSC);
++	}
++
+ 	/* Configure MDC Divider */
+ 	val = mtk_r32(eth, MTK_PPSC);
+ 	val &= ~PPSC_MDC_CFG;
+-	val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
++	val |= FIELD_PREP(PPSC_MDC_CFG, divider);
+ 	mtk_w32(eth, val, MTK_PPSC);
+ 
+ 	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
+@@ -4472,8 +4675,8 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	const __be32 *_id = of_get_property(np, "reg", NULL);
+ 	phy_interface_t phy_mode;
+ 	struct phylink *phylink;
+-	struct mtk_mac *mac;
+ 	int id, err;
++	struct mtk_mac *mac;
+ 	int txqs = 1;
+ 
+ 	if (!_id) {
+@@ -4575,6 +4778,32 @@ static int mtk_add_mac(struct mtk_eth *e
+ 			  mac->phylink_config.supported_interfaces);
+ 	}
+ 
++	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
++		if (id == MTK_GMAC1_ID) {
++			mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
++							       MAC_SYM_PAUSE |
++							       MAC_10000FD;
++			phy_interface_zero(
++				mac->phylink_config.supported_interfaces);
++			__set_bit(PHY_INTERFACE_MODE_INTERNAL,
++				  mac->phylink_config.supported_interfaces);
++		} else {
++			mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
++			__set_bit(PHY_INTERFACE_MODE_5GBASER,
++				  mac->phylink_config.supported_interfaces);
++			__set_bit(PHY_INTERFACE_MODE_10GKR,
++				  mac->phylink_config.supported_interfaces);
++			__set_bit(PHY_INTERFACE_MODE_USXGMII,
++				  mac->phylink_config.supported_interfaces);
++		}
++	}
++
++	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY)) {
++		if (id == MTK_GMAC2_ID)
++			__set_bit(PHY_INTERFACE_MODE_INTERNAL,
++				  mac->phylink_config.supported_interfaces);
++	}
++
+ 	phylink = phylink_create(&mac->phylink_config,
+ 				 of_fwnode_handle(mac->of_node),
+ 				 phy_mode, &mtk_phylink_ops);
+@@ -4762,6 +4991,13 @@ static int mtk_probe(struct platform_dev
+ 
+ 		if (err)
+ 			return err;
++	}
++
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
++		err = mtk_usxgmii_init(eth);
++
++		if (err)
++			return err;
+ 	}
+ 
+ 	if (eth->soc->required_pctl) {
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -126,6 +126,11 @@
+ #define MTK_GDMA_TO_PDMA	0x0
+ #define MTK_GDMA_DROP_ALL       0x7777
+ 
++/* GDM Egress Control Register */
++#define MTK_GDMA_EG_CTRL(x)	((x == MTK_GMAC3_ID) ?		\
++				 0x544 : 0x504 + (x * 0x1000))
++#define MTK_GDMA_XGDM_SEL	BIT(31)
++
+ /* Unicast Filter MAC Address Register - Low */
+ #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
+ 
+@@ -389,7 +394,26 @@
+ #define PHY_IAC_TIMEOUT		HZ
+ 
+ #define MTK_MAC_MISC		0x1000c
++#define MTK_MAC_MISC_V3		0x10010
+ #define MTK_MUX_TO_ESW		BIT(0)
++#define MISC_MDC_TURBO		BIT(4)
++
++/* XMAC status registers */
++#define MTK_XGMAC_STS(x)	((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
++#define MTK_XGMAC_FORCE_LINK(x)	((x == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
++#define MTK_USXGMII_PCS_LINK	BIT(8)
++#define MTK_XGMAC_RX_FC		BIT(5)
++#define MTK_XGMAC_TX_FC		BIT(4)
++#define MTK_USXGMII_PCS_MODE	GENMASK(3, 1)
++#define MTK_XGMAC_LINK_STS	BIT(0)
++
++/* GSW bridge registers */
++#define MTK_GSW_CFG		(0x10080)
++#define GSWTX_IPG_MASK		GENMASK(19, 16)
++#define GSWTX_IPG_SHIFT		16
++#define GSWRX_IPG_MASK		GENMASK(3, 0)
++#define GSWRX_IPG_SHIFT		0
++#define GSW_IPG_11		11
+ 
+ /* Mac control registers */
+ #define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
+@@ -414,6 +438,17 @@
+ #define MAC_MCR_FORCE_LINK	BIT(0)
+ #define MAC_MCR_FORCE_LINK_DOWN	(MAC_MCR_FORCE_MODE)
+ 
++/* Mac EEE control registers */
++#define MTK_MAC_EEE(x)		(0x10104 + (x * 0x100))
++#define MAC_EEE_WAKEUP_TIME_1000	GENMASK(31, 24)
++#define MAC_EEE_WAKEUP_TIME_100	GENMASK(23, 16)
++#define MAC_EEE_LPI_TXIDLE_THD	GENMASK(15, 8)
++#define MAC_EEE_RESV0		GENMASK(7, 4)
++#define MAC_EEE_CKG_TXILDE	BIT(3)
++#define MAC_EEE_CKG_RXLPI	BIT(2)
++#define MAC_EEE_TX_DOWN_REQ	BIT(1)
++#define MAC_EEE_LPI_MODE	BIT(0)
++
+ /* Mac status registers */
+ #define MTK_MAC_MSR(x)		(0x10108 + (x * 0x100))
+ #define MAC_MSR_EEE1G		BIT(7)
+@@ -458,6 +493,12 @@
+ #define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
+ #define INTF_MODE_RGMII_10_100  0
+ 
++/* XFI Mac control registers */
++#define MTK_XMAC_MCR(x)		(0x12000 + ((x - 1) * 0x1000))
++#define XMAC_MCR_TRX_DISABLE	0xf
++#define XMAC_MCR_FORCE_TX_FC	BIT(5)
++#define XMAC_MCR_FORCE_RX_FC	BIT(4)
++
+ /* GPIO port control registers for GMAC 2*/
+ #define GPIO_OD33_CTRL8		0x4c0
+ #define GPIO_BIAS_CTRL		0xed0
+@@ -483,6 +524,7 @@
+ #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
+ #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
+ #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
++#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
+ 
+ 
+ /* ethernet subsystem clock register */
+@@ -509,16 +551,91 @@
+ #define ETHSYS_DMA_AG_MAP_QDMA	BIT(1)
+ #define ETHSYS_DMA_AG_MAP_PPE	BIT(2)
+ 
++/* USXGMII subsystem config registers */
++/* Register to control speed */
++#define RG_PHY_TOP_SPEED_CTRL1	0x80C
++#define USXGMII_RATE_UPDATE_MODE	BIT(31)
++#define USXGMII_MAC_CK_GATED	BIT(29)
++#define USXGMII_IF_FORCE_EN	BIT(28)
++#define USXGMII_RATE_ADAPT_MODE	GENMASK(10, 8)
++#define USXGMII_RATE_ADAPT_MODE_X1	0
++#define USXGMII_RATE_ADAPT_MODE_X2	1
++#define USXGMII_RATE_ADAPT_MODE_X4	2
++#define USXGMII_RATE_ADAPT_MODE_X10	3
++#define USXGMII_RATE_ADAPT_MODE_X100	4
++#define USXGMII_RATE_ADAPT_MODE_X5	5
++#define USXGMII_RATE_ADAPT_MODE_X50	6
++#define USXGMII_XFI_RX_MODE	GENMASK(6, 4)
++#define USXGMII_XFI_RX_MODE_10G	0
++#define USXGMII_XFI_RX_MODE_5G	1
++#define USXGMII_XFI_TX_MODE	GENMASK(2, 0)
++#define USXGMII_XFI_TX_MODE_10G	0
++#define USXGMII_XFI_TX_MODE_5G	1
++
++/* Register to control PCS AN */
++#define RG_PCS_AN_CTRL0		0x810
++#define USXGMII_AN_RESTART	BIT(31)
++#define USXGMII_AN_SYNC_CNT	GENMASK(30, 11)
++#define USXGMII_AN_ENABLE	BIT(0)
++
++#define RG_PCS_AN_CTRL2		0x818
++#define USXGMII_LINK_TIMER_IDLE_DETECT	GENMASK(29, 20)
++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
++#define USXGMII_LINK_TIMER_AN_RESTART	GENMASK(9, 0)
++
++/* Register to read PCS AN status */
++#define RG_PCS_AN_STS0		0x81c
++#define USXGMII_LPA_SPEED_MASK	GENMASK(11, 9)
++#define USXGMII_LPA_SPEED_10	0
++#define USXGMII_LPA_SPEED_100	1
++#define USXGMII_LPA_SPEED_1000	2
++#define USXGMII_LPA_SPEED_10000	3
++#define USXGMII_LPA_SPEED_2500	4
++#define USXGMII_LPA_SPEED_5000	5
++#define USXGMII_LPA_DUPLEX	BIT(12)
++#define USXGMII_LPA_LINK	BIT(15)
++#define USXGMII_LPA_LATCH	BIT(31)
++
++/* Register to control USXGMII XFI PLL digital */
++#define XFI_PLL_DIG_GLB8	0x08
++#define RG_XFI_PLL_EN		BIT(31)
++
++/* Register to control USXGMII XFI PLL analog */
++#define XFI_PLL_ANA_GLB8	0x108
++#define RG_XFI_PLL_ANA_SWWA	0x02283248
++
+ /* Infrasys subsystem config registers */
+ #define INFRA_MISC2            0x70c
+ #define CO_QPHY_SEL            BIT(0)
+ #define GEPHY_MAC_SEL          BIT(1)
+ 
++/* Toprgu subsystem config registers */
++#define TOPRGU_SWSYSRST		0x18
++#define SWSYSRST_UNLOCK_KEY	GENMASK(31, 24)
++#define SWSYSRST_XFI_PLL_GRST	BIT(16)
++#define SWSYSRST_XFI_PEXPT1_GRST	BIT(15)
++#define SWSYSRST_XFI_PEXPT0_GRST	BIT(14)
++#define SWSYSRST_XFI1_GRST	BIT(13)
++#define SWSYSRST_XFI0_GRST	BIT(12)
++#define SWSYSRST_SGMII1_GRST	BIT(2)
++#define SWSYSRST_SGMII0_GRST	BIT(1)
++#define TOPRGU_SWSYSRST_EN		0xFC
++
+ /* Top misc registers */
++#define TOP_MISC_NETSYS_PCS_MUX	0x84
++#define NETSYS_PCS_MUX_MASK	GENMASK(1, 0)
++#define	MUX_G2_USXGMII_SEL	BIT(1)
++#define MUX_HSGMII1_G1_SEL	BIT(0)
++
+ #define USB_PHY_SWITCH_REG	0x218
+ #define QPHY_SEL_MASK		GENMASK(1, 0)
+ #define SGMII_QPHY_SEL		0x2
+ 
++/* MDIO control */
++#define MII_MMD_ACC_CTL_REG	0x0d
++#define MII_MMD_ADDR_DATA_REG	0x0e
++#define MMD_OP_MODE_DATA	BIT(14)
++
+ /* MT7628/88 specific stuff */
+ #define MT7628_PDMA_OFFSET	0x0800
+ #define MT7628_SDM_OFFSET	0x0c00
+@@ -812,13 +929,6 @@ enum mtk_gmac_id {
+ 	MTK_GMAC_ID_MAX
+ };
+ 
+-/* GDM Type */
+-enum mtk_gdm_type {
+-	MTK_GDM_TYPE = 0,
+-	MTK_XGDM_TYPE,
+-	MTK_GDM_TYPE_MAX
+-};
+-
+ enum mtk_tx_buf_type {
+ 	MTK_TYPE_SKB,
+ 	MTK_TYPE_XDP_TX,
+@@ -905,6 +1015,7 @@ enum mkt_eth_capabilities {
+ 	MTK_TRGMII_BIT,
+ 	MTK_SGMII_BIT,
+ 	MTK_USXGMII_BIT,
++	MTK_2P5GPHY_BIT,
+ 	MTK_ESW_BIT,
+ 	MTK_GEPHY_BIT,
+ 	MTK_MUX_BIT,
+@@ -925,6 +1036,7 @@ enum mkt_eth_capabilities {
+ 	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
+ 	MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
+ 	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
++	MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
+ 	MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
+ 	MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
+ 	MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
+@@ -936,6 +1048,7 @@ enum mkt_eth_capabilities {
+ 	MTK_ETH_PATH_GMAC1_SGMII_BIT,
+ 	MTK_ETH_PATH_GMAC2_RGMII_BIT,
+ 	MTK_ETH_PATH_GMAC2_SGMII_BIT,
++	MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
+ 	MTK_ETH_PATH_GMAC2_GEPHY_BIT,
+ 	MTK_ETH_PATH_GMAC3_SGMII_BIT,
+ 	MTK_ETH_PATH_GDM1_ESW_BIT,
+@@ -949,6 +1062,7 @@ enum mkt_eth_capabilities {
+ #define MTK_TRGMII		BIT_ULL(MTK_TRGMII_BIT)
+ #define MTK_SGMII		BIT_ULL(MTK_SGMII_BIT)
+ #define MTK_USXGMII		BIT_ULL(MTK_USXGMII_BIT)
++#define MTK_2P5GPHY		BIT_ULL(MTK_2P5GPHY_BIT)
+ #define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
+ #define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
+ #define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
+@@ -971,6 +1085,8 @@ enum mkt_eth_capabilities {
+ 	BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
+ #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
+ 	BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
++#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY		\
++	BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
+ #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII	\
+ 	BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
+ #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\
+@@ -986,6 +1102,7 @@ enum mkt_eth_capabilities {
+ #define MTK_ETH_PATH_GMAC1_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
+ #define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
+ #define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
++#define MTK_ETH_PATH_GMAC2_2P5GPHY	BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
+ #define MTK_ETH_PATH_GMAC2_GEPHY	BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
+ #define MTK_ETH_PATH_GMAC3_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
+ #define MTK_ETH_PATH_GDM1_ESW		BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
+@@ -999,6 +1116,7 @@ enum mkt_eth_capabilities {
+ #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
+ #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
+ #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
++#define MTK_GMAC2_2P5GPHY	(MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
+ #define MTK_GMAC3_SGMII		(MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
+ #define MTK_GDM1_ESW		(MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
+ #define MTK_GMAC1_USXGMII	(MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
+@@ -1022,6 +1140,10 @@ enum mkt_eth_capabilities {
+ 	(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
+ 	MTK_SHARED_SGMII)
+ 
++/* 2: GMAC2 -> XGMII */
++#define MTK_MUX_GMAC2_TO_2P5GPHY      \
++	(MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
++
+ /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
+ #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
+ 	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
+@@ -1080,7 +1202,8 @@ enum mkt_eth_capabilities {
+ 		       MTK_MUX_GMAC123_TO_GEPHY_SGMII |		\
+ 		       MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 |	\
+ 		       MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII |	\
+-		       MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII)
++		       MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \
++		       MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+@@ -1186,6 +1309,22 @@ struct mtk_soc_data {
+ 
+ #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
+ 
++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
++ *			associated data
++ * @regmap:		The register map pointing at the range used to setup
++ *			USXGMII modes
++ * @interface:		Currently selected interface mode
++ * @id:			The element is used to record the index of PCS
++ * @pcs:		Phylink PCS structure
++ */
++struct mtk_usxgmii_pcs {
++	struct mtk_eth		*eth;
++	struct regmap		*regmap;
++	phy_interface_t		interface;
++	u8			id;
++	struct phylink_pcs	pcs;
++};
++
+ /* struct mtk_eth -	This is the main datasructure for holding the state
+  *			of the driver
+  * @dev:		The device pointer
+@@ -1206,6 +1345,11 @@ struct mtk_soc_data {
+  * @infra:              The register map pointing at the range used to setup
+  *                      SGMII and GePHY path
+  * @sgmii_pcs:		Pointers to mtk-pcs-lynxi phylink_pcs instances
++ * @usxgmii_pll:	The register map pointing at the range used to control
++ *			the USXGMII SerDes PLL
++ * @regmap_pextp:	The register map pointing at the range used to setup
++ *			PHYA
++ * @usxgmii_pcs:	Pointer to array of pointers to struct for USXGMII PCS
+  * @pctl:		The register map pointing at the range used to setup
+  *			GMAC port drive/slew values
+  * @dma_refcnt:		track how many netdevs are using the DMA engine
+@@ -1247,7 +1391,11 @@ struct mtk_eth {
+ 	unsigned long			sysclk;
+ 	struct regmap			*ethsys;
+ 	struct regmap			*infra;
++	struct regmap			*toprgu;
+ 	struct phylink_pcs		**sgmii_pcs;
++	struct regmap			*usxgmii_pll;
++	struct regmap			**regmap_pextp;
++	struct mtk_usxgmii_pcs		**usxgmii_pcs;
+ 	struct regmap			*pctl;
+ 	bool				hwlro;
+ 	refcount_t			dma_refcnt;
+@@ -1403,6 +1551,19 @@ static inline u32 mtk_get_ib2_multicast_
+ 	return MTK_FOE_IB2_MULTICAST;
+ }
+ 
++static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_USXGMII:
++	case PHY_INTERFACE_MODE_10GKR:
++	case PHY_INTERFACE_MODE_5GBASER:
++		return true;
++		break;
++	default:
++		return false;
++	}
++}
++
+ /* read the hardware status register */
+ void mtk_stats_update_mac(struct mtk_mac *mac);
+ 
+@@ -1410,8 +1571,10 @@ void mtk_w32(struct mtk_eth *eth, u32 va
+ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
+ 
+ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
+ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
+ int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
+ 
+ int mtk_eth_offload_init(struct mtk_eth *eth);
+ int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
+@@ -1421,5 +1584,20 @@ int mtk_flow_offload_cmd(struct mtk_eth
+ void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
+ void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
+ 
++#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
++int mtk_usxgmii_init(struct mtk_eth *eth);
++int mtk_xfi_pll_enable(struct mtk_eth *eth);
++void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id);
++void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id);
++void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id);
++#else
++static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) { return NULL; }
++static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
++static inline int mtk_xfi_pll_enable(struct mtk_eth *eth) { return 0; }
++static inline void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) { }
++static inline void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) { }
++static inline void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) { }
++#endif /* NET_MEDIATEK_SOC_USXGMII */
+ 
+ #endif /* MTK_ETH_H */
+--- /dev/null
++++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
+@@ -0,0 +1,835 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ *         Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/mfd/syscon.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++#include "mtk_eth_soc.h"
++
++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
++}
++
++static int mtk_xfi_pextp_init(struct mtk_eth *eth)
++{
++	struct device *dev = eth->dev;
++	struct device_node *r = dev->of_node;
++	struct device_node *np;
++	int i;
++
++	eth->regmap_pextp = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->regmap_pextp), GFP_KERNEL);
++	if (!eth->regmap_pextp)
++		return -ENOMEM;
++
++	for (i = 0; i < eth->soc->num_devs; i++) {
++		np = of_parse_phandle(r, "mediatek,xfi_pextp", i);
++		if (!np)
++			break;
++
++		eth->regmap_pextp[i] = syscon_node_to_regmap(np);
++		if (IS_ERR(eth->regmap_pextp[i]))
++			return PTR_ERR(eth->regmap_pextp[i]);
++	}
++
++	return 0;
++}
++
++static int mtk_xfi_pll_init(struct mtk_eth *eth)
++{
++	struct device_node *r = eth->dev->of_node;
++	struct device_node *np;
++
++	np = of_parse_phandle(r, "mediatek,xfi_pll", 0);
++	if (!np)
++		return -1;
++
++	eth->usxgmii_pll = syscon_node_to_regmap(np);
++	if (IS_ERR(eth->usxgmii_pll))
++		return PTR_ERR(eth->usxgmii_pll);
++
++	return 0;
++}
++
++static int mtk_toprgu_init(struct mtk_eth *eth)
++{
++	struct device_node *r = eth->dev->of_node;
++	struct device_node *np;
++
++	np = of_parse_phandle(r, "mediatek,toprgu", 0);
++	if (!np)
++		return -1;
++
++	eth->toprgu = syscon_node_to_regmap(np);
++	if (IS_ERR(eth->toprgu))
++		return PTR_ERR(eth->toprgu);
++
++	return 0;
++}
++
++int mtk_xfi_pll_enable(struct mtk_eth *eth)
++{
++	u32 val = 0;
++
++	if (!eth->usxgmii_pll)
++		return -EINVAL;
++
++	/* Add software workaround for USXGMII PLL TCL issue */
++	regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
++
++	regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
++	val |= RG_XFI_PLL_EN;
++	regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
++
++	return 0;
++}
++
++static int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
++{
++	int xgmii_id = mac_id;
++
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++		switch (mac_id) {
++		case MTK_GMAC1_ID:
++		case MTK_GMAC2_ID:
++			xgmii_id = 1;
++			break;
++		case MTK_GMAC3_ID:
++			xgmii_id = 0;
++			break;
++		default:
++			xgmii_id = -1;
++		}
++	}
++
++	return xgmii_id;
++}
++
++static int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
++{
++	int mac_id = xgmii_id;
++
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++		switch (xgmii_id) {
++		case 0:
++			mac_id = 2;
++			break;
++		case 1:
++			mac_id = 1;
++			break;
++		default:
++			mac_id = -1;
++		}
++	}
++
++	return mac_id;
++}
++
++
++static void mtk_usxgmii_setup_phya_usxgmii(struct mtk_usxgmii_pcs *mpcs)
++{
++	struct regmap *pextp;
++
++	if (!mpcs->eth)
++		return;
++
++	pextp = mpcs->eth->regmap_pextp[mpcs->id];
++	if (!pextp)
++		return;
++
++	/* Setup operation mode */
++	regmap_write(pextp, 0x9024, 0x00C9071C);
++	regmap_write(pextp, 0x2020, 0xAA8585AA);
++	regmap_write(pextp, 0x2030, 0x0C020707);
++	regmap_write(pextp, 0x2034, 0x0E050F0F);
++	regmap_write(pextp, 0x2040, 0x00140032);
++	regmap_write(pextp, 0x50F0, 0x00C014AA);
++	regmap_write(pextp, 0x50E0, 0x3777C12B);
++	regmap_write(pextp, 0x506C, 0x005F9CFF);
++	regmap_write(pextp, 0x5070, 0x9D9DFAFA);
++	regmap_write(pextp, 0x5074, 0x27273F3F);
++	regmap_write(pextp, 0x5078, 0xA7883C68);
++	regmap_write(pextp, 0x507C, 0x11661166);
++	regmap_write(pextp, 0x5080, 0x0E000AAF);
++	regmap_write(pextp, 0x5084, 0x08080D0D);
++	regmap_write(pextp, 0x5088, 0x02030909);
++	regmap_write(pextp, 0x50E4, 0x0C0C0000);
++	regmap_write(pextp, 0x50E8, 0x04040000);
++	regmap_write(pextp, 0x50EC, 0x0F0F0C06);
++	regmap_write(pextp, 0x50A8, 0x506E8C8C);
++	regmap_write(pextp, 0x6004, 0x18190000);
++	regmap_write(pextp, 0x00F8, 0x01423342);
++	/* Force SGDT_OUT off and select PCS */
++	regmap_write(pextp, 0x00F4, 0x80201F20);
++	/* Force GLB_CKDET_OUT */
++	regmap_write(pextp, 0x0030, 0x00050C00);
++	/* Force AEQ on */
++	regmap_write(pextp, 0x0070, 0x02002800);
++	ndelay(1020);
++	/* Setup DA default value */
++	regmap_write(pextp, 0x30B0, 0x00000020);
++	regmap_write(pextp, 0x3028, 0x00008A01);
++	regmap_write(pextp, 0x302C, 0x0000A884);
++	regmap_write(pextp, 0x3024, 0x00083002);
++	regmap_write(pextp, 0x3010, 0x00022220);
++	regmap_write(pextp, 0x5064, 0x0F020A01);
++	regmap_write(pextp, 0x50B4, 0x06100600);
++	regmap_write(pextp, 0x3048, 0x40704000);
++	regmap_write(pextp, 0x3050, 0xA8000000);
++	regmap_write(pextp, 0x3054, 0x000000AA);
++	regmap_write(pextp, 0x306C, 0x00000F00);
++	regmap_write(pextp, 0xA060, 0x00040000);
++	regmap_write(pextp, 0x90D0, 0x00000001);
++	/* Release reset */
++	regmap_write(pextp, 0x0070, 0x0200E800);
++	udelay(150);
++	/* Switch to P0 */
++	regmap_write(pextp, 0x0070, 0x0200C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0200C101);
++	udelay(15);
++	/* Switch to Gen3 */
++	regmap_write(pextp, 0x0070, 0x0202C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0202C101);
++	udelay(100);
++	regmap_write(pextp, 0x30B0, 0x00000030);
++	regmap_write(pextp, 0x00F4, 0x80201F00);
++	regmap_write(pextp, 0x3040, 0x30000000);
++	udelay(400);
++}
++
++static void mtk_usxgmii_setup_phya_5gbaser(struct mtk_usxgmii_pcs *mpcs)
++{
++	struct regmap *pextp;
++
++	if (!mpcs->eth)
++		return;
++
++	pextp = mpcs->eth->regmap_pextp[mpcs->id];
++	if (!pextp)
++		return;
++
++	/* Setup operation mode */
++	regmap_write(pextp, 0x9024, 0x00D9071C);
++	regmap_write(pextp, 0x2020, 0xAAA5A5AA);
++	regmap_write(pextp, 0x2030, 0x0C020707);
++	regmap_write(pextp, 0x2034, 0x0E050F0F);
++	regmap_write(pextp, 0x2040, 0x00140032);
++	regmap_write(pextp, 0x50F0, 0x00C018AA);
++	regmap_write(pextp, 0x50E0, 0x3777812B);
++	regmap_write(pextp, 0x506C, 0x005C9CFF);
++	regmap_write(pextp, 0x5070, 0x9DFAFAFA);
++	regmap_write(pextp, 0x5074, 0x273F3F3F);
++	regmap_write(pextp, 0x5078, 0xA8883868);
++	regmap_write(pextp, 0x507C, 0x14661466);
++	regmap_write(pextp, 0x5080, 0x0E001ABF);
++	regmap_write(pextp, 0x5084, 0x080B0D0D);
++	regmap_write(pextp, 0x5088, 0x02050909);
++	regmap_write(pextp, 0x50E4, 0x0C000000);
++	regmap_write(pextp, 0x50E8, 0x04000000);
++	regmap_write(pextp, 0x50EC, 0x0F0F0C06);
++	regmap_write(pextp, 0x50A8, 0x50808C8C);
++	regmap_write(pextp, 0x6004, 0x18000000);
++	regmap_write(pextp, 0x00F8, 0x00A132A1);
++	/* Force SGDT_OUT off and select PCS */
++	regmap_write(pextp, 0x00F4, 0x80201F20);
++	/* Force GLB_CKDET_OUT */
++	regmap_write(pextp, 0x0030, 0x00050C00);
++	/* Force AEQ on */
++	regmap_write(pextp, 0x0070, 0x02002800);
++	ndelay(1020);
++	/* Setup DA default value */
++	regmap_write(pextp, 0x30B0, 0x00000020);
++	regmap_write(pextp, 0x3028, 0x00008A01);
++	regmap_write(pextp, 0x302C, 0x0000A884);
++	regmap_write(pextp, 0x3024, 0x00083002);
++	regmap_write(pextp, 0x3010, 0x00022220);
++	regmap_write(pextp, 0x5064, 0x0F020A01);
++	regmap_write(pextp, 0x50B4, 0x06100600);
++	regmap_write(pextp, 0x3048, 0x40704000);
++	regmap_write(pextp, 0x3050, 0xA8000000);
++	regmap_write(pextp, 0x3054, 0x000000AA);
++	regmap_write(pextp, 0x306C, 0x00000F00);
++	regmap_write(pextp, 0xA060, 0x00040000);
++	regmap_write(pextp, 0x90D0, 0x00000003);
++	/* Release reset */
++	regmap_write(pextp, 0x0070, 0x0200E800);
++	udelay(150);
++	/* Switch to P0 */
++	regmap_write(pextp, 0x0070, 0x0200C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0200C101);
++	udelay(15);
++	/* Switch to Gen3 */
++	regmap_write(pextp, 0x0070, 0x0202C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0202C101);
++	udelay(100);
++	regmap_write(pextp, 0x30B0, 0x00000030);
++	regmap_write(pextp, 0x00F4, 0x80201F00);
++	regmap_write(pextp, 0x3040, 0x30000000);
++	udelay(400);
++}
++
++static void mtk_usxgmii_setup_phya_10gbaser(struct mtk_usxgmii_pcs *mpcs)
++{
++	struct regmap *pextp;
++
++	if (!mpcs->eth)
++		return;
++
++	pextp = mpcs->eth->regmap_pextp[mpcs->id];
++	if (!pextp)
++		return;
++
++	/* Setup operation mode */
++	regmap_write(pextp, 0x9024, 0x00C9071C);
++	regmap_write(pextp, 0x2020, 0xAA8585AA);
++	regmap_write(pextp, 0x2030, 0x0C020707);
++	regmap_write(pextp, 0x2034, 0x0E050F0F);
++	regmap_write(pextp, 0x2040, 0x00140032);
++	regmap_write(pextp, 0x50F0, 0x00C014AA);
++	regmap_write(pextp, 0x50E0, 0x3777C12B);
++	regmap_write(pextp, 0x506C, 0x005F9CFF);
++	regmap_write(pextp, 0x5070, 0x9D9DFAFA);
++	regmap_write(pextp, 0x5074, 0x27273F3F);
++	regmap_write(pextp, 0x5078, 0xA7883C68);
++	regmap_write(pextp, 0x507C, 0x11661166);
++	regmap_write(pextp, 0x5080, 0x0E000AAF);
++	regmap_write(pextp, 0x5084, 0x08080D0D);
++	regmap_write(pextp, 0x5088, 0x02030909);
++	regmap_write(pextp, 0x50E4, 0x0C0C0000);
++	regmap_write(pextp, 0x50E8, 0x04040000);
++	regmap_write(pextp, 0x50EC, 0x0F0F0C06);
++	regmap_write(pextp, 0x50A8, 0x506E8C8C);
++	regmap_write(pextp, 0x6004, 0x18190000);
++	regmap_write(pextp, 0x00F8, 0x01423342);
++	/* Force SGDT_OUT off and select PCS */
++	regmap_write(pextp, 0x00F4, 0x80201F20);
++	/* Force GLB_CKDET_OUT */
++	regmap_write(pextp, 0x0030, 0x00050C00);
++	/* Force AEQ on */
++	regmap_write(pextp, 0x0070, 0x02002800);
++	ndelay(1020);
++	/* Setup DA default value */
++	regmap_write(pextp, 0x30B0, 0x00000020);
++	regmap_write(pextp, 0x3028, 0x00008A01);
++	regmap_write(pextp, 0x302C, 0x0000A884);
++	regmap_write(pextp, 0x3024, 0x00083002);
++	regmap_write(pextp, 0x3010, 0x00022220);
++	regmap_write(pextp, 0x5064, 0x0F020A01);
++	regmap_write(pextp, 0x50B4, 0x06100600);
++	regmap_write(pextp, 0x3048, 0x47684100);
++	regmap_write(pextp, 0x3050, 0x00000000);
++	regmap_write(pextp, 0x3054, 0x00000000);
++	regmap_write(pextp, 0x306C, 0x00000F00);
++	if (mpcs->id == 0)
++		regmap_write(pextp, 0xA008, 0x0007B400);
++
++	regmap_write(pextp, 0xA060, 0x00040000);
++	regmap_write(pextp, 0x90D0, 0x00000001);
++	/* Release reset */
++	regmap_write(pextp, 0x0070, 0x0200E800);
++	udelay(150);
++	/* Switch to P0 */
++	regmap_write(pextp, 0x0070, 0x0200C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0200C101);
++	udelay(15);
++	/* Switch to Gen3 */
++	regmap_write(pextp, 0x0070, 0x0202C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0202C101);
++	udelay(100);
++	regmap_write(pextp, 0x30B0, 0x00000030);
++	regmap_write(pextp, 0x00F4, 0x80201F00);
++	regmap_write(pextp, 0x3040, 0x30000000);
++	udelay(400);
++}
++
++void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id)
++{
++	u32 id = mtk_mac2xgmii_id(eth, mac_id);
++	struct regmap *pextp;
++
++	if (id >= eth->soc->num_devs)
++		return;
++
++	pextp = eth->regmap_pextp[id];
++	if (!pextp)
++		return;
++
++	/* Setup operation mode */
++	regmap_write(pextp, 0x9024, 0x00D9071C);
++	regmap_write(pextp, 0x2020, 0xAA8585AA);
++	regmap_write(pextp, 0x2030, 0x0C020207);
++	regmap_write(pextp, 0x2034, 0x0E05050F);
++	regmap_write(pextp, 0x2040, 0x00200032);
++	regmap_write(pextp, 0x50F0, 0x00C014BA);
++	regmap_write(pextp, 0x50E0, 0x3777C12B);
++	regmap_write(pextp, 0x506C, 0x005F9CFF);
++	regmap_write(pextp, 0x5070, 0x9D9DFAFA);
++	regmap_write(pextp, 0x5074, 0x27273F3F);
++	regmap_write(pextp, 0x5078, 0xA7883C68);
++	regmap_write(pextp, 0x507C, 0x11661166);
++	regmap_write(pextp, 0x5080, 0x0E000EAF);
++	regmap_write(pextp, 0x5084, 0x08080E0D);
++	regmap_write(pextp, 0x5088, 0x02030B09);
++	regmap_write(pextp, 0x50E4, 0x0C0C0000);
++	regmap_write(pextp, 0x50E8, 0x04040000);
++	regmap_write(pextp, 0x50EC, 0x0F0F0606);
++	regmap_write(pextp, 0x50A8, 0x506E8C8C);
++	regmap_write(pextp, 0x6004, 0x18190000);
++	regmap_write(pextp, 0x00F8, 0x00FA32FA);
++	/* Force SGDT_OUT off and select PCS */
++	regmap_write(pextp, 0x00F4, 0x80201F21);
++	/* Force GLB_CKDET_OUT */
++	regmap_write(pextp, 0x0030, 0x00050C00);
++	/* Force AEQ on */
++	regmap_write(pextp, 0x0070, 0x02002800);
++	ndelay(1020);
++	/* Setup DA default value */
++	regmap_write(pextp, 0x30B0, 0x00000020);
++	regmap_write(pextp, 0x3028, 0x00008A01);
++	regmap_write(pextp, 0x302C, 0x0000A884);
++	regmap_write(pextp, 0x3024, 0x00083002);
++	regmap_write(pextp, 0x3010, 0x00011110);
++	regmap_write(pextp, 0x3048, 0x40704000);
++	regmap_write(pextp, 0x3064, 0x0000C000);
++	regmap_write(pextp, 0x3050, 0xA8000000);
++	regmap_write(pextp, 0x3054, 0x000000AA);
++	regmap_write(pextp, 0x306C, 0x20200F00);
++	regmap_write(pextp, 0xA060, 0x00050000);
++	regmap_write(pextp, 0x90D0, 0x00000007);
++	/* Release reset */
++	regmap_write(pextp, 0x0070, 0x0200E800);
++	udelay(150);
++	/* Switch to P0 */
++	regmap_write(pextp, 0x0070, 0x0200C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0200C101);
++	udelay(15);
++	/* Switch to Gen2 */
++	regmap_write(pextp, 0x0070, 0x0201C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0201C101);
++	udelay(100);
++	regmap_write(pextp, 0x30B0, 0x00000030);
++	regmap_write(pextp, 0x00F4, 0x80201F01);
++	regmap_write(pextp, 0x3040, 0x30000000);
++	udelay(400);
++}
++
++void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id)
++{
++	u32 id = mtk_mac2xgmii_id(eth, mac_id);
++	struct regmap *pextp;
++
++	if (id >= eth->soc->num_devs)
++		return;
++
++	pextp = eth->regmap_pextp[id];
++	if (!pextp)
++		return;
++
++	/* Setup operation mode */
++	regmap_write(pextp, 0x9024, 0x00D9071C);
++	regmap_write(pextp, 0x2020, 0xAA8585AA);
++	regmap_write(pextp, 0x2030, 0x0C020707);
++	regmap_write(pextp, 0x2034, 0x0E050F0F);
++	regmap_write(pextp, 0x2040, 0x00140032);
++	regmap_write(pextp, 0x50F0, 0x00C014AA);
++	regmap_write(pextp, 0x50E0, 0x3777C12B);
++	regmap_write(pextp, 0x506C, 0x005F9CFF);
++	regmap_write(pextp, 0x5070, 0x9D9DFAFA);
++	regmap_write(pextp, 0x5074, 0x27273F3F);
++	regmap_write(pextp, 0x5078, 0xA7883C68);
++	regmap_write(pextp, 0x507C, 0x11661166);
++	regmap_write(pextp, 0x5080, 0x0E000AAF);
++	regmap_write(pextp, 0x5084, 0x08080D0D);
++	regmap_write(pextp, 0x5088, 0x02030909);
++	regmap_write(pextp, 0x50E4, 0x0C0C0000);
++	regmap_write(pextp, 0x50E8, 0x04040000);
++	regmap_write(pextp, 0x50EC, 0x0F0F0C06);
++	regmap_write(pextp, 0x50A8, 0x506E8C8C);
++	regmap_write(pextp, 0x6004, 0x18190000);
++	regmap_write(pextp, 0x00F8, 0x009C329C);
++	/* Force SGDT_OUT off and select PCS */
++	regmap_write(pextp, 0x00F4, 0x80201F21);
++	/* Force GLB_CKDET_OUT */
++	regmap_write(pextp, 0x0030, 0x00050C00);
++	/* Force AEQ on */
++	regmap_write(pextp, 0x0070, 0x02002800);
++	ndelay(1020);
++	/* Setup DA default value */
++	regmap_write(pextp, 0x30B0, 0x00000020);
++	regmap_write(pextp, 0x3028, 0x00008A01);
++	regmap_write(pextp, 0x302C, 0x0000A884);
++	regmap_write(pextp, 0x3024, 0x00083002);
++	regmap_write(pextp, 0x3010, 0x00011110);
++	regmap_write(pextp, 0x3048, 0x40704000);
++	regmap_write(pextp, 0x3050, 0xA8000000);
++	regmap_write(pextp, 0x3054, 0x000000AA);
++	regmap_write(pextp, 0x306C, 0x22000F00);
++	regmap_write(pextp, 0xA060, 0x00050000);
++	regmap_write(pextp, 0x90D0, 0x00000005);
++	/* Release reset */
++	regmap_write(pextp, 0x0070, 0x0200E800);
++	udelay(150);
++	/* Switch to P0 */
++	regmap_write(pextp, 0x0070, 0x0200C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0200C101);
++	udelay(15);
++	/* Switch to Gen2 */
++	regmap_write(pextp, 0x0070, 0x0201C111);
++	ndelay(1020);
++	regmap_write(pextp, 0x0070, 0x0201C101);
++	udelay(100);
++	regmap_write(pextp, 0x30B0, 0x00000030);
++	regmap_write(pextp, 0x00F4, 0x80201F01);
++	regmap_write(pextp, 0x3040, 0x30000000);
++	udelay(400);
++}
++
++static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
++{
++	u32 val = 0;
++
++	if (id >= eth->soc->num_devs || !eth->toprgu)
++		return;
++
++	switch (id) {
++	case 0:
++		/* Enable software reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
++		val |= SWSYSRST_XFI_PEXPT0_GRST |
++		       SWSYSRST_XFI0_GRST;
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
++
++		/* Assert USXGMII reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
++		val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
++		       SWSYSRST_XFI_PEXPT0_GRST |
++		       SWSYSRST_XFI0_GRST;
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
++
++		udelay(100);
++
++		/* De-assert USXGMII reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
++		val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
++		val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
++			 SWSYSRST_XFI0_GRST);
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
++
++		/* Disable software reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
++		val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
++			 SWSYSRST_XFI0_GRST);
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
++		break;
++	case 1:
++		/* Enable software reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
++		val |= SWSYSRST_XFI_PEXPT1_GRST |
++		       SWSYSRST_XFI1_GRST;
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
++
++		/* Assert USXGMII reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
++		val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
++		       SWSYSRST_XFI_PEXPT1_GRST |
++		       SWSYSRST_XFI1_GRST;
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
++
++		udelay(100);
++
++		/* De-assert USXGMII reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
++		val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
++		val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
++			 SWSYSRST_XFI1_GRST);
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
++
++		/* Disable software reset */
++		regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
++		val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
++			 SWSYSRST_XFI1_GRST);
++		regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
++		break;
++	}
++
++	mdelay(10);
++}
++
++void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id)
++{
++	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
++
++	mtk_usxgmii_reset(eth, xgmii_id);
++}
++
++
++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++				  phy_interface_t interface,
++				  const unsigned long *advertising,
++				  bool permit_pause_to_mac)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++	struct mtk_eth *eth = mpcs->eth;
++	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
++	bool mode_changed = false;
++
++	if (interface == PHY_INTERFACE_MODE_USXGMII) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) |
++			  USXGMII_AN_ENABLE;
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
++	} else if (interface == PHY_INTERFACE_MODE_10GKR) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else
++		return -EINVAL;
++
++	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
++
++	if (mpcs->interface != interface) {
++		mpcs->interface = interface;
++		mode_changed = true;
++	}
++
++	mtk_xfi_pll_enable(eth);
++	mtk_usxgmii_reset(eth, mpcs->id);
++
++	/* Setup USXGMII AN ctrl */
++	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
++			   USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
++			   an_ctrl);
++
++	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
++			   USXGMII_LINK_TIMER_IDLE_DETECT |
++			   USXGMII_LINK_TIMER_COMP_ACK_DETECT |
++			   USXGMII_LINK_TIMER_AN_RESTART,
++			   link_timer);
++
++	/* Gated MAC CK */
++	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
++			   USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
++
++	/* Enable interface force mode */
++	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
++			   USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
++
++	/* Setup USXGMII adapt mode */
++	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
++			   USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
++			   adapt_mode);
++
++	/* Setup USXGMII speed */
++	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
++			   USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
++			   xfi_mode);
++
++	udelay(1);
++
++	/* Un-gated MAC CK */
++	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
++			   USXGMII_MAC_CK_GATED, 0);
++
++	udelay(1);
++
++	/* Disable interface force mode for the AN mode */
++	if (an_ctrl & USXGMII_AN_ENABLE)
++		regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
++				   USXGMII_IF_FORCE_EN, 0);
++
++	/* Setup USXGMIISYS with the determined property */
++	if (interface == PHY_INTERFACE_MODE_USXGMII)
++		mtk_usxgmii_setup_phya_usxgmii(mpcs);
++	else if (interface == PHY_INTERFACE_MODE_10GKR)
++		mtk_usxgmii_setup_phya_10gbaser(mpcs);
++	else if (interface == PHY_INTERFACE_MODE_5GBASER)
++		mtk_usxgmii_setup_phya_5gbaser(mpcs);
++
++	return mode_changed;
++}
++
++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
++				    struct phylink_link_state *state)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++	struct mtk_eth *eth = mpcs->eth;
++	struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
++	u32 val = 0;
++
++	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
++	if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
++		/* Refresh LPA by inverting LPA_LATCH */
++		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
++		regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
++				   USXGMII_LPA_LATCH,
++				   !(val & USXGMII_LPA_LATCH));
++
++		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
++
++		state->interface = mpcs->interface;
++		state->link = FIELD_GET(USXGMII_LPA_LINK, val);
++		state->duplex = FIELD_GET(USXGMII_LPA_DUPLEX, val);
++
++		switch (FIELD_GET(USXGMII_LPA_SPEED_MASK, val)) {
++		case USXGMII_LPA_SPEED_10:
++			state->speed = SPEED_10;
++			break;
++		case USXGMII_LPA_SPEED_100:
++			state->speed = SPEED_100;
++			break;
++		case USXGMII_LPA_SPEED_1000:
++			state->speed = SPEED_1000;
++			break;
++		case USXGMII_LPA_SPEED_2500:
++			state->speed = SPEED_2500;
++			break;
++		case USXGMII_LPA_SPEED_5000:
++			state->speed = SPEED_5000;
++			break;
++		case USXGMII_LPA_SPEED_10000:
++			state->speed = SPEED_10000;
++			break;
++		}
++	} else {
++		val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
++
++		if (mac->id == MTK_GMAC2_ID)
++			val = val >> 16;
++
++		switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
++		case 0:
++			state->speed = SPEED_10000;
++			break;
++		case 1:
++			state->speed = SPEED_5000;
++			break;
++		case 2:
++			state->speed = SPEED_2500;
++			break;
++		case 3:
++			state->speed = SPEED_1000;
++			break;
++		}
++
++		state->interface = mpcs->interface;
++		state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
++		state->duplex = DUPLEX_FULL;
++	}
++
++	if (state->link == 0)
++		mtk_usxgmii_pcs_config(pcs, MLO_AN_INBAND,
++				       state->interface, NULL, false);
++}
++
++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++	unsigned int val = 0;
++
++	if (!mpcs->regmap)
++		return;
++
++	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
++	val |= USXGMII_AN_RESTART;
++	regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
++}
++
++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++				    phy_interface_t interface,
++				    int speed, int duplex)
++{
++	/* Reconfiguring USXGMII to ensure the quality of the RX signal
++	 * after the line side link up.
++	 */
++	mtk_usxgmii_pcs_config(pcs, mode,
++			       interface, NULL, false);
++}
++
++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
++	.pcs_config = mtk_usxgmii_pcs_config,
++	.pcs_get_state = mtk_usxgmii_pcs_get_state,
++	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
++	.pcs_link_up = mtk_usxgmii_pcs_link_up,
++};
++
++int mtk_usxgmii_init(struct mtk_eth *eth)
++{
++	struct device_node *r = eth->dev->of_node;
++	struct device *dev = eth->dev;
++	struct device_node *np;
++	int i, ret;
++
++	eth->usxgmii_pcs = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->usxgmii_pcs), GFP_KERNEL);
++	if (!eth->usxgmii_pcs)
++		return -ENOMEM;
++
++	for (i = 0; i < eth->soc->num_devs; i++) {
++		np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
++		if (!np)
++			break;
++
++		eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs), GFP_KERNEL);
++		if (!eth->usxgmii_pcs[i])
++			return -ENOMEM;
++
++		eth->usxgmii_pcs[i]->id = i;
++		eth->usxgmii_pcs[i]->eth = eth;
++		eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
++		if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
++			return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
++
++		eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
++		eth->usxgmii_pcs[i]->pcs.poll = true;
++		eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
++
++		of_node_put(np);
++	}
++
++	ret = mtk_xfi_pextp_init(eth);
++	if (ret)
++		return ret;
++
++	ret = mtk_xfi_pll_init(eth);
++	if (ret)
++		return ret;
++
++	return mtk_toprgu_init(eth);
++}
++
++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
++{
++	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
++
++	if (!eth->usxgmii_pcs[xgmii_id]->regmap)
++		return NULL;
++
++	return &eth->usxgmii_pcs[xgmii_id]->pcs;
++}
diff --git a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
index 5f4da76b0e048a..14abe9b55abb89 100644
--- a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #endif
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -4637,7 +4637,7 @@ static int napi_schedule_rps(struct soft
+@@ -4640,7 +4640,7 @@ static int napi_schedule_rps(struct soft
  	struct softnet_data *mysd = this_cpu_ptr(&softnet_data);
  
  #ifdef CONFIG_RPS
@@ -39,7 +39,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		sd->rps_ipi_next = mysd->rps_ipi_list;
  		mysd->rps_ipi_list = sd;
  
-@@ -5818,6 +5818,8 @@ static DEFINE_PER_CPU(struct work_struct
+@@ -5821,6 +5821,8 @@ static DEFINE_PER_CPU(struct work_struct
  /* Network device is going away, flush any packets still pending */
  static void flush_backlog(struct work_struct *work)
  {
@@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct sk_buff *skb, *tmp;
  	struct softnet_data *sd;
  
-@@ -5832,8 +5834,17 @@ static void flush_backlog(struct work_st
+@@ -5835,8 +5837,17 @@ static void flush_backlog(struct work_st
  			input_queue_head_incr(sd);
  		}
  	}
@@ -66,7 +66,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	skb_queue_walk_safe(&sd->process_queue, skb, tmp) {
  		if (skb->dev->reg_state == NETREG_UNREGISTERING) {
  			__skb_unlink(skb, &sd->process_queue);
-@@ -5841,7 +5852,16 @@ static void flush_backlog(struct work_st
+@@ -5844,7 +5855,16 @@ static void flush_backlog(struct work_st
  			input_queue_head_incr(sd);
  		}
  	}
@@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static bool flush_required(int cpu)
-@@ -5973,6 +5993,7 @@ static int process_backlog(struct napi_s
+@@ -5976,6 +5996,7 @@ static int process_backlog(struct napi_s
  		}
  
  		rps_lock_irq_disable(sd);
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		if (skb_queue_empty(&sd->input_pkt_queue)) {
  			/*
  			 * Inline a custom version of __napi_complete().
-@@ -5982,7 +6003,8 @@ static int process_backlog(struct napi_s
+@@ -5985,7 +6006,8 @@ static int process_backlog(struct napi_s
  			 * We can use a plain write instead of clear_bit(),
  			 * and we dont need an smp_mb() memory barrier.
  			 */
@@ -101,7 +101,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			again = false;
  		} else {
  			skb_queue_splice_tail_init(&sd->input_pkt_queue,
-@@ -6398,6 +6420,55 @@ int dev_set_threaded(struct net_device *
+@@ -6401,6 +6423,55 @@ int dev_set_threaded(struct net_device *
  }
  EXPORT_SYMBOL(dev_set_threaded);
  
@@ -157,7 +157,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
  			   int (*poll)(struct napi_struct *, int), int weight)
  {
-@@ -11180,6 +11251,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11183,6 +11254,9 @@ static int dev_cpu_dead(unsigned int old
  	raise_softirq_irqoff(NET_TX_SOFTIRQ);
  	local_irq_enable();
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11483,6 +11557,7 @@ static int __init net_dev_init(void)
+@@ -11486,6 +11560,7 @@ static int __init net_dev_init(void)
  		INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
  		spin_lock_init(&sd->defer_lock);
  
diff --git a/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
index 201beb8d539839..d333f3f4890da9 100644
--- a/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
+++ b/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
@@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2102,10 +2102,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2142,10 +2142,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
  {
  	struct dsa_switch *ds = priv->ds;
  	struct device *dev = priv->dev;
@@ -30,7 +30,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	bus = devm_mdiobus_alloc(dev);
  	if (!bus)
  		return -ENOMEM;
-@@ -2122,7 +2125,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2162,7 +2165,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
  	if (priv->irq)
  		mt7530_setup_mdio_irq(priv);
  
diff --git a/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch b/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch
index 6c8cbd6d6996ef..4ced7e5ef6ad99 100644
--- a/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch
+++ b/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch
@@ -12,7 +12,7 @@
  	{QMI_GOBI1K_DEVICE(0x05c6, 0x9212)},	/* Acer Gobi Modem Device */
 --- a/drivers/usb/serial/option.c
 +++ b/drivers/usb/serial/option.c
-@@ -2266,6 +2266,12 @@ static const struct usb_device_id option
+@@ -2271,6 +2271,12 @@ static const struct usb_device_id option
  	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a2, 0xff) },			/* Fibocom FM101-GL (laptop MBIM) */
  	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a4, 0xff),			/* Fibocom FM101-GL (laptop MBIM) */
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch b/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch
index 8c52719649de4a..aec74d0047dbfe 100644
--- a/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch
+++ b/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch
@@ -6,11 +6,11 @@
  #define QUECTEL_PRODUCT_RM520N			0x0801
 +#define QUECTEL_PRODUCT_RM500U			0x0900
  #define QUECTEL_PRODUCT_EC200U			0x0901
+ #define QUECTEL_PRODUCT_EG912Y			0x6001
  #define QUECTEL_PRODUCT_EC200S_CN		0x6002
- #define QUECTEL_PRODUCT_EC200A			0x6005
-@@ -1245,6 +1246,7 @@ static const struct usb_device_id option
- 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) },
+@@ -1248,6 +1249,7 @@ static const struct usb_device_id option
  	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) },
+ 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EG912Y, 0xff, 0, 0) },
  	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500K, 0xff, 0x00, 0x00) },
 +	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500U, 0xff, 0x00, 0x00) },
  
diff --git a/target/linux/generic/pending-6.6/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch b/target/linux/generic/pending-6.6/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch
new file mode 100644
index 00000000000000..0844fcd6dbd657
--- /dev/null
+++ b/target/linux/generic/pending-6.6/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch
@@ -0,0 +1,29 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Thu, 22 Oct 2020 22:00:03 +0200
+Subject: [PATCH] compiler.h: only include asm/rwonce.h for kernel code
+
+This header file is not in uapi, which makes any user space code that includes
+linux/compiler.h to fail with the error 'asm/rwonce.h: No such file or directory'
+
+Fixes: e506ea451254 ("compiler.h: Split {READ,WRITE}_ONCE definitions out into rwonce.h")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/compiler.h
++++ b/include/linux/compiler.h
+@@ -202,6 +202,8 @@ void ftrace_likely_update(struct ftrace_
+ 	__v;								\
+ })
+ 
++#include <asm/rwonce.h>
++
+ #endif /* __KERNEL__ */
+ 
+ /*
+@@ -243,6 +245,4 @@ static inline void *offset_to_ptr(const
+  */
+ #define prevent_tail_call_optimization()	mb()
+ 
+-#include <asm/rwonce.h>
+-
+ #endif /* __LINUX_COMPILER_H */
diff --git a/target/linux/generic/pending-6.6/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch b/target/linux/generic/pending-6.6/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch
new file mode 100644
index 00000000000000..d79d03defb3ad4
--- /dev/null
+++ b/target/linux/generic/pending-6.6/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch
@@ -0,0 +1,57 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 18 Apr 2018 10:50:05 +0200
+Subject: [PATCH] MIPS: only process negative stack offsets on stack traces
+
+Fixes endless back traces in cases where the compiler emits a stack
+pointer increase in a branch delay slot (probably for some form of
+function return).
+
+[    3.475442] BUG: MAX_STACK_TRACE_ENTRIES too low!
+[    3.480070] turning off the locking correctness validator.
+[    3.485521] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.34 #0
+[    3.491475] Stack : 00000000 00000000 00000000 00000000 80e0fce2 00000034 00000000 00000000
+[    3.499764]         87c3838c 80696377 8061047c 00000000 00000001 00000001 87c2d850 6534689f
+[    3.508059]         00000000 00000000 80e10000 00000000 00000000 000000cf 0000000f 00000000
+[    3.516353]         00000000 806a0000 00076891 00000000 00000000 00000000 ffffffff 00000000
+[    3.524648]         806c0000 00000004 80e10000 806a0000 00000003 80690000 00000000 80700000
+[    3.532942]         ...
+[    3.535362] Call Trace:
+[    3.537818] [<80010a48>] show_stack+0x58/0x100
+[    3.542207] [<804c2f78>] dump_stack+0xe8/0x170
+[    3.546613] [<80079f90>] save_trace+0xf0/0x110
+[    3.551010] [<8007b1ec>] mark_lock+0x33c/0x78c
+[    3.555413] [<8007bf48>] __lock_acquire+0x2ac/0x1a08
+[    3.560337] [<8007de60>] lock_acquire+0x64/0x8c
+[    3.564846] [<804e1570>] _raw_spin_lock_irqsave+0x54/0x78
+[    3.570186] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.574770] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.579257] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.583839] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.588329] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.592911] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.597401] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.601983] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.606473] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.611055] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.615545] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.620125] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.624619] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.629197] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.633691] [<801b618c>] kernfs_notify+0x94/0xac
+[    3.638269] [<801b7b10>] sysfs_notify+0x74/0xa0
+[    3.642763] [<801b618c>] kernfs_notify+0x94/0xac
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/mips/kernel/process.c
++++ b/arch/mips/kernel/process.c
+@@ -395,6 +395,8 @@ static inline int is_sp_move_ins(union m
+ 
+ 	if (ip->i_format.opcode == addiu_op ||
+ 	    ip->i_format.opcode == daddiu_op) {
++		if (ip->i_format.simmediate > 0)
++			return 0;
+ 		*frame_size = -ip->i_format.simmediate;
+ 		return 1;
+ 	}
diff --git a/target/linux/generic/pending-6.6/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/pending-6.6/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch
new file mode 100644
index 00000000000000..132d5c48ee0c7c
--- /dev/null
+++ b/target/linux/generic/pending-6.6/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch
@@ -0,0 +1,81 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: jffs2: use .rename2 and add RENAME_WHITEOUT support
+
+It is required for renames on overlayfs
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/fs/jffs2/dir.c
++++ b/fs/jffs2/dir.c
+@@ -617,8 +617,8 @@ static int jffs2_rmdir (struct inode *di
+ 	return ret;
+ }
+ 
+-static int jffs2_mknod (struct mnt_idmap *idmap, struct inode *dir_i,
+-		        struct dentry *dentry, umode_t mode, dev_t rdev)
++static int __jffs2_mknod (struct mnt_idmap *idmap, struct inode *dir_i,
++		        struct dentry *dentry, umode_t mode, dev_t rdev, bool whiteout)
+ {
+ 	struct jffs2_inode_info *f, *dir_f;
+ 	struct jffs2_sb_info *c;
+@@ -758,7 +758,11 @@ static int jffs2_mknod (struct mnt_idmap
+ 	mutex_unlock(&dir_f->sem);
+ 	jffs2_complete_reservation(c);
+ 
+-	d_instantiate_new(dentry, inode);
++	if (!whiteout)
++		d_instantiate_new(dentry, inode);
++	else
++		unlock_new_inode(inode);
++
+ 	return 0;
+ 
+  fail:
+@@ -766,6 +770,19 @@ static int jffs2_mknod (struct mnt_idmap
+ 	return ret;
+ }
+ 
++static int jffs2_mknod (struct mnt_idmap *idmap, struct inode *dir_i,
++			  struct dentry *dentry, umode_t mode, dev_t rdev)
++{
++	return __jffs2_mknod(idmap, dir_i, dentry, mode, rdev, false);
++}
++
++static int jffs2_whiteout (struct mnt_idmap *idmap, struct inode *old_dir,
++			    struct dentry *old_dentry)
++{
++	return __jffs2_mknod(idmap, old_dir, old_dentry, S_IFCHR | WHITEOUT_MODE,
++			     WHITEOUT_DEV, true);
++}
++
+ static int jffs2_rename (struct mnt_idmap *idmap,
+ 			 struct inode *old_dir_i, struct dentry *old_dentry,
+ 			 struct inode *new_dir_i, struct dentry *new_dentry,
+@@ -777,7 +794,7 @@ static int jffs2_rename (struct mnt_idma
+ 	uint8_t type;
+ 	uint32_t now;
+ 
+-	if (flags & ~RENAME_NOREPLACE)
++	if (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT))
+ 		return -EINVAL;
+ 
+ 	/* The VFS will check for us and prevent trying to rename a
+@@ -843,9 +860,14 @@ static int jffs2_rename (struct mnt_idma
+ 	if (d_is_dir(old_dentry) && !victim_f)
+ 		inc_nlink(new_dir_i);
+ 
+-	/* Unlink the original */
+-	ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),
+-			      old_dentry->d_name.name, old_dentry->d_name.len, NULL, now);
++	if (flags & RENAME_WHITEOUT)
++		/* Replace with whiteout */
++		ret = jffs2_whiteout(idmap, old_dir_i, old_dentry);
++	else
++		/* Unlink the original */
++		ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),
++				      old_dentry->d_name.name,
++				      old_dentry->d_name.len, NULL, now);
+ 
+ 	/* We don't touch inode->i_nlink */
+ 
diff --git a/target/linux/generic/pending-6.6/141-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/pending-6.6/141-jffs2-add-RENAME_EXCHANGE-support.patch
new file mode 100644
index 00000000000000..c3a528ec9026aa
--- /dev/null
+++ b/target/linux/generic/pending-6.6/141-jffs2-add-RENAME_EXCHANGE-support.patch
@@ -0,0 +1,73 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: jffs2: add RENAME_EXCHANGE support
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/fs/jffs2/dir.c
++++ b/fs/jffs2/dir.c
+@@ -791,18 +791,31 @@ static int jffs2_rename (struct mnt_idma
+ 	int ret;
+ 	struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb);
+ 	struct jffs2_inode_info *victim_f = NULL;
++	struct inode *fst_inode = d_inode(old_dentry);
++	struct inode *snd_inode = d_inode(new_dentry);
+ 	uint8_t type;
+ 	uint32_t now;
+ 
+-	if (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT))
++	if (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT|RENAME_EXCHANGE))
+ 		return -EINVAL;
+ 
++	if ((flags & RENAME_EXCHANGE) && (old_dir_i != new_dir_i)) {
++		if (S_ISDIR(fst_inode->i_mode) && !S_ISDIR(snd_inode->i_mode)) {
++			inc_nlink(new_dir_i);
++			drop_nlink(old_dir_i);
++		}
++		else if (!S_ISDIR(fst_inode->i_mode) && S_ISDIR(snd_inode->i_mode)) {
++			drop_nlink(new_dir_i);
++			inc_nlink(old_dir_i);
++		}
++	}
++
+ 	/* The VFS will check for us and prevent trying to rename a
+ 	 * file over a directory and vice versa, but if it's a directory,
+ 	 * the VFS can't check whether the victim is empty. The filesystem
+ 	 * needs to do that for itself.
+ 	 */
+-	if (d_really_is_positive(new_dentry)) {
++	if (d_really_is_positive(new_dentry) && !(flags & RENAME_EXCHANGE)) {
+ 		victim_f = JFFS2_INODE_INFO(d_inode(new_dentry));
+ 		if (d_is_dir(new_dentry)) {
+ 			struct jffs2_full_dirent *fd;
+@@ -837,7 +850,7 @@ static int jffs2_rename (struct mnt_idma
+ 	if (ret)
+ 		return ret;
+ 
+-	if (victim_f) {
++	if (victim_f && !(flags & RENAME_EXCHANGE)) {
+ 		/* There was a victim. Kill it off nicely */
+ 		if (d_is_dir(new_dentry))
+ 			clear_nlink(d_inode(new_dentry));
+@@ -863,6 +876,12 @@ static int jffs2_rename (struct mnt_idma
+ 	if (flags & RENAME_WHITEOUT)
+ 		/* Replace with whiteout */
+ 		ret = jffs2_whiteout(idmap, old_dir_i, old_dentry);
++	else if (flags & RENAME_EXCHANGE)
++		/* Replace the original */
++		ret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i),
++				    d_inode(new_dentry)->i_ino, type,
++				    old_dentry->d_name.name, old_dentry->d_name.len,
++				    now);
+ 	else
+ 		/* Unlink the original */
+ 		ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),
+@@ -895,7 +914,7 @@ static int jffs2_rename (struct mnt_idma
+ 		return ret;
+ 	}
+ 
+-	if (d_is_dir(old_dentry))
++	if (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE))
+ 		drop_nlink(old_dir_i);
+ 
+ 	old_dir_i->i_mtime = inode_set_ctime_to_ts(old_dir_i, ITIME(now));
diff --git a/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch
new file mode 100644
index 00000000000000..b23cae1f5e051d
--- /dev/null
+++ b/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch
@@ -0,0 +1,45 @@
+From: Stephen Hemminger <stephen@networkplumber.org>
+Subject: bridge: allow receiption on disabled port
+
+When an ethernet device is enslaved to a bridge, and the bridge STP
+detects loss of carrier (or operational state down), then normally
+packet receiption is blocked.
+
+This breaks control applications like WPA which maybe expecting to
+receive packets to negotiate to bring link up. The bridge needs to
+block forwarding packets from these disabled ports, but there is no
+hard requirement to not allow local packet delivery.
+
+Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/net/bridge/br_input.c
++++ b/net/bridge/br_input.c
+@@ -239,6 +239,9 @@ static void __br_handle_local_finish(str
+ /* note: already called with rcu_read_lock */
+ static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
+ {
++	struct net_bridge_port *p = br_port_get_rcu(skb->dev);
++
++	if (p->state != BR_STATE_DISABLED)
+ 	__br_handle_local_finish(skb);
+ 
+ 	/* return 1 to signal the okfn() was called so it's ok to use the skb */
+@@ -408,6 +411,17 @@ forward:
+ 		goto defer_stp_filtering;
+ 
+ 	switch (p->state) {
++	case BR_STATE_DISABLED:
++		if (ether_addr_equal(p->br->dev->dev_addr, dest))
++			skb->pkt_type = PACKET_HOST;
++
++		if (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING,
++			dev_net(skb->dev), NULL, skb, skb->dev, NULL,
++			br_handle_local_finish) == 1) {
++			return RX_HANDLER_PASS;
++		}
++		break;
++
+ 	case BR_STATE_FORWARDING:
+ 	case BR_STATE_LEARNING:
+ defer_stp_filtering:
diff --git a/target/linux/generic/pending-6.6/190-rtc-rs5c372-support_alarms_up_to_1_week.patch b/target/linux/generic/pending-6.6/190-rtc-rs5c372-support_alarms_up_to_1_week.patch
new file mode 100644
index 00000000000000..2f5c2228c7a4e2
--- /dev/null
+++ b/target/linux/generic/pending-6.6/190-rtc-rs5c372-support_alarms_up_to_1_week.patch
@@ -0,0 +1,94 @@
+From: Daniel González Cabanelas <dgcbueu@gmail.com>
+Subject: [PATCH 1/2] rtc: rs5c372: support alarms up to 1 week
+
+The Ricoh R2221x, R2223x, RS5C372, RV5C387A chips can handle 1 week
+alarms.
+
+Read the "wday" alarm register and convert it to a date to support up 1
+week in our driver.
+
+Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
+---
+ drivers/rtc/rtc-rs5c372.c | 48 ++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 42 insertions(+), 6 deletions(-)
+
+--- a/drivers/rtc/rtc-rs5c372.c
++++ b/drivers/rtc/rtc-rs5c372.c
+@@ -399,7 +399,9 @@ static int rs5c_read_alarm(struct device
+ {
+ 	struct i2c_client	*client = to_i2c_client(dev);
+ 	struct rs5c372		*rs5c = i2c_get_clientdata(client);
+-	int			status;
++	int			status, wday_offs;
++	struct rtc_time 	rtc;
++	unsigned long 		alarm_secs;
+ 
+ 	status = rs5c_get_regs(rs5c);
+ 	if (status < 0)
+@@ -409,6 +411,30 @@ static int rs5c_read_alarm(struct device
+ 	t->time.tm_sec = 0;
+ 	t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f);
+ 	t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]);
++	t->time.tm_wday = ffs(rs5c->regs[RS5C_REG_ALARM_A_WDAY] & 0x7f) - 1;
++
++	/* determine the day, month and year based on alarm wday, taking as a
++	 * reference the current time from the rtc
++	 */
++	status = rs5c372_rtc_read_time(dev, &rtc);
++	if (status < 0)
++		return status;
++
++	wday_offs = t->time.tm_wday - rtc.tm_wday;
++	alarm_secs = mktime64(rtc.tm_year + 1900,
++			      rtc.tm_mon + 1,
++			      rtc.tm_mday + wday_offs,
++			      t->time.tm_hour,
++			      t->time.tm_min,
++			      t->time.tm_sec);
++
++	if (wday_offs < 0 || (wday_offs == 0 &&
++			      (t->time.tm_hour < rtc.tm_hour ||
++			       (t->time.tm_hour == rtc.tm_hour &&
++				t->time.tm_min <= rtc.tm_min))))
++		alarm_secs += 7 * 86400;
++
++	rtc_time64_to_tm(alarm_secs, &t->time);
+ 
+ 	/* ... and status */
+ 	t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE);
+@@ -423,12 +449,20 @@ static int rs5c_set_alarm(struct device
+ 	struct rs5c372		*rs5c = i2c_get_clientdata(client);
+ 	int			status, addr, i;
+ 	unsigned char		buf[3];
++	struct rtc_time 	rtc_tm;
++	unsigned long 		rtc_secs, alarm_secs;
+ 
+-	/* only handle up to 24 hours in the future, like RTC_ALM_SET */
+-	if (t->time.tm_mday != -1
+-			|| t->time.tm_mon != -1
+-			|| t->time.tm_year != -1)
++	/* chip only can handle alarms up to one week in the future*/
++	status = rs5c372_rtc_read_time(dev, &rtc_tm);
++	if (status)
++		return status;
++	rtc_secs = rtc_tm_to_time64(&rtc_tm);
++	alarm_secs = rtc_tm_to_time64(&t->time);
++	if (alarm_secs >= rtc_secs + 7 * 86400) {
++		dev_err(dev, "%s: alarm maximum is one week in the future (%d)\n",
++			__func__, status);
+ 		return -EINVAL;
++	}
+ 
+ 	/* REVISIT: round up tm_sec */
+ 
+@@ -449,7 +483,9 @@ static int rs5c_set_alarm(struct device
+ 	/* set alarm */
+ 	buf[0] = bin2bcd(t->time.tm_min);
+ 	buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour);
+-	buf[2] = 0x7f;	/* any/all days */
++	/* each bit is the day of the week, 0x7f means all days */
++	buf[2] = (t->time.tm_wday >= 0 && t->time.tm_wday < 7) ?
++		  BIT(t->time.tm_wday) : 0x7f;
+ 
+ 	for (i = 0; i < sizeof(buf); i++) {
+ 		addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i);
diff --git a/target/linux/generic/pending-6.6/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch b/target/linux/generic/pending-6.6/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch
new file mode 100644
index 00000000000000..9eea41299a1587
--- /dev/null
+++ b/target/linux/generic/pending-6.6/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch
@@ -0,0 +1,70 @@
+From: Daniel González Cabanelas <dgcbueu@gmail.com>
+Subject: [PATCH 2/2] rtc: rs5c372: let the alarm to be used as wakeup source
+
+Currently there is no use for the interrupts on the rs5c372 RTC and the
+wakealarm isn't enabled. There are some devices like NASes which use this
+RTC to wake up from the power off state when the INTR pin is activated by
+the alarm clock.
+
+Enable the alarm and let to be used as a wakeup source.
+
+Tested on a Buffalo LS421DE NAS.
+
+Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
+---
+ drivers/rtc/rtc-rs5c372.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/rtc/rtc-rs5c372.c
++++ b/drivers/rtc/rtc-rs5c372.c
+@@ -832,6 +832,7 @@ static int rs5c372_probe(struct i2c_clie
+ 	int err = 0;
+ 	int smbus_mode = 0;
+ 	struct rs5c372 *rs5c372;
++	bool rs5c372_can_wakeup_device = false;
+ 
+ 	dev_dbg(&client->dev, "%s\n", __func__);
+ 
+@@ -868,6 +869,12 @@ static int rs5c372_probe(struct i2c_clie
+ 		rs5c372->type = id->driver_data;
+ 	}
+ 
++#ifdef CONFIG_OF
++	if(of_property_read_bool(client->dev.of_node,
++					      "wakeup-source"))
++		rs5c372_can_wakeup_device = true;
++#endif
++
+ 	/* we read registers 0x0f then 0x00-0x0f; skip the first one */
+ 	rs5c372->regs = &rs5c372->buf[1];
+ 	rs5c372->smbus = smbus_mode;
+@@ -901,6 +908,8 @@ static int rs5c372_probe(struct i2c_clie
+ 		goto exit;
+ 	}
+ 
++	rs5c372->has_irq = 1;
++
+ 	/* if the oscillator lost power and no other software (like
+ 	 * the bootloader) set it up, do it here.
+ 	 *
+@@ -927,6 +936,10 @@ static int rs5c372_probe(struct i2c_clie
+ 			);
+ 
+ 	/* REVISIT use client->irq to register alarm irq ... */
++	if (rs5c372_can_wakeup_device) {
++		device_init_wakeup(&client->dev, true);
++	}
++
+ 	rs5c372->rtc = devm_rtc_device_register(&client->dev,
+ 					rs5c372_driver.driver.name,
+ 					&rs5c372_rtc_ops, THIS_MODULE);
+@@ -940,6 +953,9 @@ static int rs5c372_probe(struct i2c_clie
+ 	if (err)
+ 		goto exit;
+ 
++	/* the rs5c372 alarm only supports a minute accuracy */
++
++
+ 	return 0;
+ 
+ exit:
diff --git a/target/linux/generic/pending-6.6/203-kallsyms_uncompressed.patch b/target/linux/generic/pending-6.6/203-kallsyms_uncompressed.patch
new file mode 100644
index 00000000000000..d7afc5c82d331b
--- /dev/null
+++ b/target/linux/generic/pending-6.6/203-kallsyms_uncompressed.patch
@@ -0,0 +1,110 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: add a config option for keeping the kallsyms table uncompressed, saving ~9kb kernel size after lzma on ar71xx
+
+[john@phrozen.org: added to my upstream queue 30.12.2016]
+lede-commit: e0e3509b5ce2ccf93d4d67ea907613f5f7ec2eed
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ init/Kconfig            | 11 +++++++++++
+ kernel/kallsyms.c       |  8 ++++++++
+ scripts/kallsyms.c      | 12 ++++++++++++
+ scripts/link-vmlinux.sh |  4 ++++
+ 4 files changed, 35 insertions(+)
+
+--- a/init/Kconfig
++++ b/init/Kconfig
+@@ -1432,6 +1432,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW
+ 	  the unaligned access emulation.
+ 	  see arch/parisc/kernel/unaligned.c for reference
+ 
++config KALLSYMS_UNCOMPRESSED
++	bool "Keep kallsyms uncompressed"
++	depends on KALLSYMS
++	help
++		Normally kallsyms contains compressed symbols (using a token table),
++		reducing the uncompressed kernel image size. Keeping the symbol table
++		uncompressed significantly improves the size of this part in compressed
++		kernel images.
++
++		Say N unless you need compressed kernel images to be small.
++
+ config HAVE_PCSPKR_PLATFORM
+ 	bool
+ 
+--- a/kernel/kallsyms.c
++++ b/kernel/kallsyms.c
+@@ -69,6 +69,11 @@ static unsigned int kallsyms_expand_symb
+ 	 * For every byte on the compressed symbol data, copy the table
+ 	 * entry for that byte.
+ 	 */
++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED
++	memcpy(result, data + 1, len - 1);
++	result += len - 1;
++	len = 0;
++#endif
+ 	while (len) {
+ 		tptr = &kallsyms_token_table[kallsyms_token_index[*data]];
+ 		data++;
+@@ -101,6 +106,9 @@ tail:
+  */
+ static char kallsyms_get_symbol_type(unsigned int off)
+ {
++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED
++	return kallsyms_names[off + 1];
++#endif
+ 	/*
+ 	 * Get just the first code, look it up in the token table,
+ 	 * and return the first char from this token.
+--- a/scripts/kallsyms.c
++++ b/scripts/kallsyms.c
+@@ -62,6 +62,7 @@ static struct addr_range percpu_range =
+ static struct sym_entry **table;
+ static unsigned int table_size, table_cnt;
+ static int all_symbols;
++static int uncompressed;
+ static int absolute_percpu;
+ static int base_relative;
+ static int lto_clang;
+@@ -469,6 +470,9 @@ static void write_src(void)
+ 
+ 	free(markers);
+ 
++	if (uncompressed)
++		return;
++
+ 	output_label("kallsyms_token_table");
+ 	off = 0;
+ 	for (i = 0; i < 256; i++) {
+@@ -582,6 +586,9 @@ static unsigned char *find_token(unsigne
+ {
+ 	int i;
+ 
++	if (uncompressed)
++		return NULL;
++
+ 	for (i = 0; i < len - 1; i++) {
+ 		if (str[i] == token[0] && str[i+1] == token[1])
+ 			return &str[i];
+@@ -654,6 +661,9 @@ static void optimize_result(void)
+ {
+ 	int i, best;
+ 
++	if (uncompressed)
++		return;
++
+ 	/* using the '\0' symbol last allows compress_symbols to use standard
+ 	 * fast string functions */
+ 	for (i = 255; i >= 0; i--) {
+--- a/scripts/link-vmlinux.sh
++++ b/scripts/link-vmlinux.sh
+@@ -160,6 +160,10 @@ kallsyms()
+ 		kallsymopt="${kallsymopt} --lto-clang"
+ 	fi
+ 
++	if [ -n "${CONFIG_KALLSYMS_UNCOMPRESSED}" ]; then
++		kallsymopt="${kallsymopt} --uncompressed"
++	fi
++
+ 	info KSYMS ${2}
+ 	scripts/kallsyms ${kallsymopt} ${1} > ${2}
+ }
diff --git a/target/linux/generic/pending-6.6/205-backtrace_module_info.patch b/target/linux/generic/pending-6.6/205-backtrace_module_info.patch
new file mode 100644
index 00000000000000..e4d7a4508d9b5d
--- /dev/null
+++ b/target/linux/generic/pending-6.6/205-backtrace_module_info.patch
@@ -0,0 +1,41 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: when KALLSYMS is disabled, print module address + size for matching backtrace entries
+
+[john@phrozen.org: felix will add this to his upstream queue]
+
+lede-commit 53827cdc824556cda910b23ce5030c363b8f1461
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ lib/vsprintf.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+--- a/lib/vsprintf.c
++++ b/lib/vsprintf.c
+@@ -982,8 +982,10 @@ char *symbol_string(char *buf, char *end
+ 		    struct printf_spec spec, const char *fmt)
+ {
+ 	unsigned long value;
+-#ifdef CONFIG_KALLSYMS
+ 	char sym[KSYM_SYMBOL_LEN];
++#ifndef CONFIG_KALLSYMS
++	struct module *mod;
++	int len;
+ #endif
+ 
+ 	if (fmt[1] == 'R')
+@@ -1004,8 +1006,14 @@ char *symbol_string(char *buf, char *end
+ 
+ 	return string_nocheck(buf, end, sym, spec);
+ #else
+-	return special_hex_number(buf, end, value, sizeof(void *));
++	len = snprintf(sym, sizeof(sym), "0x%lx", value);
++	mod = __module_address(value);
++	if (mod)
++		snprintf(sym + len, sizeof(sym) - len, " [%s@%p+0x%x]",
++			 mod->name, mod->core_layout.base,
++			 mod->core_layout.size);
+ #endif
++	return string(buf, end, sym, spec);
+ }
+ 
+ static const struct printf_spec default_str_spec = {
diff --git a/target/linux/generic/pending-6.6/240-remove-unsane-filenames-from-deps_initramfs-list.patch b/target/linux/generic/pending-6.6/240-remove-unsane-filenames-from-deps_initramfs-list.patch
new file mode 100644
index 00000000000000..9e78284ecf707b
--- /dev/null
+++ b/target/linux/generic/pending-6.6/240-remove-unsane-filenames-from-deps_initramfs-list.patch
@@ -0,0 +1,30 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: usr: sanitize deps_initramfs list
+
+If any filename in the intramfs dependency
+list contains a colon, that causes a kernel
+build error like this:
+
+/devel/openwrt/build_dir/linux-ar71xx_generic/linux-3.6.6/usr/Makefile:58: *** multiple target patterns.  Stop.
+make[5]: *** [usr] Error 2
+
+Fix it by removing such filenames from the
+deps_initramfs list.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ usr/Makefile | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/usr/Makefile
++++ b/usr/Makefile
+@@ -56,6 +56,8 @@ hostprogs := gen_init_cpio
+ # The dependency list is generated by gen_initramfs.sh -l
+ -include $(obj)/.initramfs_data.cpio.d
+ 
++deps_initramfs := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v)))
++
+ # do not try to update files included in initramfs
+ $(deps_initramfs): ;
+ 
diff --git a/target/linux/generic/pending-6.6/270-platform-mikrotik-build-bits.patch b/target/linux/generic/pending-6.6/270-platform-mikrotik-build-bits.patch
new file mode 100644
index 00000000000000..41510fb7edac93
--- /dev/null
+++ b/target/linux/generic/pending-6.6/270-platform-mikrotik-build-bits.patch
@@ -0,0 +1,35 @@
+From c2deb5ef01a0ef09088832744cbace9e239a6ee0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks@slashdirt.org>
+Date: Sat, 28 Mar 2020 12:11:50 +0100
+Subject: [PATCH] generic: platform/mikrotik build bits (5.4)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch adds platform/mikrotik kernel build bits
+
+Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
+---
+ drivers/platform/Kconfig  | 2 ++
+ drivers/platform/Makefile | 1 +
+ 2 files changed, 3 insertions(+)
+
+--- a/drivers/platform/Kconfig
++++ b/drivers/platform/Kconfig
+@@ -9,6 +9,8 @@ source "drivers/platform/chrome/Kconfig"
+ 
+ source "drivers/platform/mellanox/Kconfig"
+ 
++source "drivers/platform/mikrotik/Kconfig"
++
+ source "drivers/platform/olpc/Kconfig"
+ 
+ source "drivers/platform/surface/Kconfig"
+--- a/drivers/platform/Makefile
++++ b/drivers/platform/Makefile
+@@ -10,4 +10,5 @@ obj-$(CONFIG_MIPS)		+= mips/
+ obj-$(CONFIG_OLPC_EC)		+= olpc/
+ obj-$(CONFIG_GOLDFISH)		+= goldfish/
+ obj-$(CONFIG_CHROME_PLATFORMS)	+= chrome/
++obj-$(CONFIG_MIKROTIK)		+= mikrotik/
+ obj-$(CONFIG_SURFACE_PLATFORMS)	+= surface/
diff --git a/target/linux/generic/pending-6.6/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-6.6/300-mips_expose_boot_raw.patch
new file mode 100644
index 00000000000000..ebeeb7bae703a7
--- /dev/null
+++ b/target/linux/generic/pending-6.6/300-mips_expose_boot_raw.patch
@@ -0,0 +1,40 @@
+From: Mark Miller <mark@mirell.org>
+Subject: mips: expose CONFIG_BOOT_RAW
+
+This exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on
+certain Broadcom chipsets running CFE in order to load the kernel.
+
+Signed-off-by: Mark Miller <mark@mirell.org>
+Acked-by: Rob Landley <rob@landley.net>
+---
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1013,9 +1013,6 @@ config FW_ARC
+ config ARCH_MAY_HAVE_PC_FDC
+ 	bool
+ 
+-config BOOT_RAW
+-	bool
+-
+ config CEVT_BCM1480
+ 	bool
+ 
+@@ -2996,6 +2993,18 @@ choice
+ 		bool "Extend builtin kernel arguments with bootloader arguments"
+ endchoice
+ 
++config BOOT_RAW
++	bool "Enable the kernel to be executed from the load address"
++	default n
++	help
++	 Allow the kernel to be executed from the load address for
++	 bootloaders which cannot read the ELF format. This places
++	 a jump to start_kernel at the load address.
++
++	 If unsure, say N.
++
++
++
+ endmenu
+ 
+ config LOCKDEP_SUPPORT
diff --git a/target/linux/generic/pending-6.6/302-mips_no_branch_likely.patch b/target/linux/generic/pending-6.6/302-mips_no_branch_likely.patch
new file mode 100644
index 00000000000000..669aa8143ac3a2
--- /dev/null
+++ b/target/linux/generic/pending-6.6/302-mips_no_branch_likely.patch
@@ -0,0 +1,22 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: mips: use -mno-branch-likely for kernel and userspace
+
+saves ~11k kernel size after lzma and ~12k squashfs size in the
+
+lede-commit: 41a039f46450ffae9483d6216422098669da2900
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ arch/mips/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -94,7 +94,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin
+ # machines may also.  Since BFD is incredibly buggy with respect to
+ # crossformat linking we rely on the elf2ecoff tool for format conversion.
+ #
+-cflags-y			+= -G 0 -mno-abicalls -fno-pic -pipe
++cflags-y			+= -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely
+ cflags-y			+= -msoft-float -Wa,-msoft-float
+ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
+ KBUILD_AFLAGS_MODULE		+= -mlong-calls
diff --git a/target/linux/generic/pending-6.6/305-mips_module_reloc.patch b/target/linux/generic/pending-6.6/305-mips_module_reloc.patch
new file mode 100644
index 00000000000000..0e29f9dd682fa9
--- /dev/null
+++ b/target/linux/generic/pending-6.6/305-mips_module_reloc.patch
@@ -0,0 +1,370 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: mips: replace -mlong-calls with -mno-long-calls to make function calls faster in kernel modules to achieve this, try to
+
+lede-commit: 3b3d64743ba2a874df9d70cd19e242205b0a788c
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ arch/mips/Makefile             |   5 +
+ arch/mips/include/asm/module.h |   5 +
+ arch/mips/kernel/module.c      | 279 ++++++++++++++++++++++++++++++++++++++++-
+ 3 files changed, 284 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -97,8 +97,18 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin
+ cflags-y			+= -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely
+ cflags-y			+= -msoft-float -Wa,-msoft-float
+ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
++ifdef CONFIG_64BIT
+ KBUILD_AFLAGS_MODULE		+= -mlong-calls
+ KBUILD_CFLAGS_MODULE		+= -mlong-calls
++else
++  ifdef CONFIG_DYNAMIC_FTRACE
++    KBUILD_AFLAGS_MODULE	+= -mlong-calls
++    KBUILD_CFLAGS_MODULE	+= -mlong-calls
++  else
++    KBUILD_AFLAGS_MODULE	+= -mno-long-calls
++    KBUILD_CFLAGS_MODULE	+= -mno-long-calls
++  endif
++endif
+ 
+ ifeq ($(CONFIG_RELOCATABLE),y)
+ LDFLAGS_vmlinux			+= --emit-relocs
+--- a/arch/mips/include/asm/module.h
++++ b/arch/mips/include/asm/module.h
+@@ -12,6 +12,11 @@ struct mod_arch_specific {
+ 	const struct exception_table_entry *dbe_start;
+ 	const struct exception_table_entry *dbe_end;
+ 	struct mips_hi16 *r_mips_hi16_list;
++
++	void *phys_plt_tbl;
++	void *virt_plt_tbl;
++	unsigned int phys_plt_offset;
++	unsigned int virt_plt_offset;
+ };
+ 
+ typedef uint8_t Elf64_Byte;		/* Type for a 8-bit quantity.  */
+--- a/arch/mips/kernel/module.c
++++ b/arch/mips/kernel/module.c
+@@ -32,23 +32,261 @@ struct mips_hi16 {
+ static LIST_HEAD(dbe_list);
+ static DEFINE_SPINLOCK(dbe_lock);
+ 
+-#ifdef MODULE_START
++/*
++ * Get the potential max trampolines size required of the init and
++ * non-init sections. Only used if we cannot find enough contiguous
++ * physically mapped memory to put the module into.
++ */
++static unsigned int
++get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
++             const char *secstrings, unsigned int symindex, bool is_init)
++{
++	unsigned long ret = 0;
++	unsigned int i, j;
++	Elf_Sym *syms;
++
++	/* Everything marked ALLOC (this includes the exported symbols) */
++	for (i = 1; i < hdr->e_shnum; ++i) {
++		unsigned int info = sechdrs[i].sh_info;
++
++		if (sechdrs[i].sh_type != SHT_REL
++		    && sechdrs[i].sh_type != SHT_RELA)
++			continue;
++
++		/* Not a valid relocation section? */
++		if (info >= hdr->e_shnum)
++			continue;
++
++		/* Don't bother with non-allocated sections */
++		if (!(sechdrs[info].sh_flags & SHF_ALLOC))
++			continue;
++
++		/* If it's called *.init*, and we're not init, we're
++                   not interested */
++		if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0)
++		    != is_init)
++			continue;
++
++		syms = (Elf_Sym *) sechdrs[symindex].sh_addr;
++		if (sechdrs[i].sh_type == SHT_REL) {
++			Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr;
++			unsigned int size = sechdrs[i].sh_size / sizeof(*rel);
++
++			for (j = 0; j < size; ++j) {
++				Elf_Sym *sym;
++
++				if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26)
++					continue;
++
++				sym = syms + ELF_MIPS_R_SYM(rel[j]);
++				if (!is_init && sym->st_shndx != SHN_UNDEF)
++					continue;
++
++				ret += 4 * sizeof(int);
++			}
++		} else {
++			Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr;
++			unsigned int size = sechdrs[i].sh_size / sizeof(*rela);
++
++			for (j = 0; j < size; ++j) {
++				Elf_Sym *sym;
++
++				if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26)
++					continue;
++
++				sym = syms + ELF_MIPS_R_SYM(rela[j]);
++				if (!is_init && sym->st_shndx != SHN_UNDEF)
++					continue;
++
++				ret += 4 * sizeof(int);
++			}
++		}
++	}
++
++	return ret;
++}
++
++#ifndef MODULE_START
++static void *alloc_phys(unsigned long size)
++{
++	unsigned order;
++	struct page *page;
++	struct page *p;
++
++	size = PAGE_ALIGN(size);
++	order = get_order(size);
++
++	page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN |
++			__GFP_THISNODE, order);
++	if (!page)
++		return NULL;
++
++	split_page(page, order);
++
++	/* mark all pages except for the last one */
++	for (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p)
++		set_bit(PG_owner_priv_1, &p->flags);
++
++	for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p)
++		__free_page(p);
++
++	return page_address(page);
++}
++#endif
++
++static void free_phys(void *ptr)
++{
++	struct page *page;
++	bool free;
++
++	page = virt_to_page(ptr);
++	do {
++		free = test_and_clear_bit(PG_owner_priv_1, &page->flags);
++		__free_page(page);
++		page++;
++	} while (free);
++}
++
+ void *module_alloc(unsigned long size)
+ {
++#ifdef MODULE_START
+ 	return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
+ 				GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,
+ 				__builtin_return_address(0));
++#else
++	void *ptr;
++
++	if (size == 0)
++		return NULL;
++
++	ptr = alloc_phys(size);
++
++	/* If we failed to allocate physically contiguous memory,
++	 * fall back to regular vmalloc. The module loader code will
++	 * create jump tables to handle long jumps */
++	if (!ptr)
++		return vmalloc(size);
++
++	return ptr;
++#endif
+ }
++
++static inline bool is_phys_addr(void *ptr)
++{
++#ifdef CONFIG_64BIT
++	return (KSEGX((unsigned long)ptr) == CKSEG0);
++#else
++	return (KSEGX(ptr) == KSEG0);
+ #endif
++}
++
++/* Free memory returned from module_alloc */
++void module_memfree(void *module_region)
++{
++	if (is_phys_addr(module_region))
++		free_phys(module_region);
++	else
++		vfree(module_region);
++}
++
++static void *__module_alloc(int size, bool phys)
++{
++	void *ptr;
++
++	if (phys)
++		ptr = kmalloc(size, GFP_KERNEL);
++	else
++		ptr = vmalloc(size);
++	return ptr;
++}
++
++static void __module_free(void *ptr)
++{
++	if (is_phys_addr(ptr))
++		kfree(ptr);
++	else
++		vfree(ptr);
++}
++
++int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
++			      char *secstrings, struct module *mod)
++{
++	unsigned int symindex = 0;
++	unsigned int core_size, init_size;
++	int i;
++
++	mod->arch.phys_plt_offset = 0;
++	mod->arch.virt_plt_offset = 0;
++	mod->arch.phys_plt_tbl = NULL;
++	mod->arch.virt_plt_tbl = NULL;
++
++	if (IS_ENABLED(CONFIG_64BIT))
++		return 0;
++
++	for (i = 1; i < hdr->e_shnum; i++)
++		if (sechdrs[i].sh_type == SHT_SYMTAB)
++			symindex = i;
++
++	core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false);
++	init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true);
++
++	if ((core_size + init_size) == 0)
++		return 0;
++
++	mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1);
++	if (!mod->arch.phys_plt_tbl)
++		return -ENOMEM;
++
++	mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0);
++	if (!mod->arch.virt_plt_tbl) {
++		__module_free(mod->arch.phys_plt_tbl);
++		mod->arch.phys_plt_tbl = NULL;
++		return -ENOMEM;
++	}
++
++	return 0;
++}
+ 
+ static void apply_r_mips_32(u32 *location, u32 base, Elf_Addr v)
+ {
+ 	*location = base + v;
+ }
+ 
++static Elf_Addr add_plt_entry_to(unsigned *plt_offset,
++				 void *start, Elf_Addr v)
++{
++	unsigned *tramp = start + *plt_offset;
++	*plt_offset += 4 * sizeof(int);
++
++	/* adjust carry for addiu */
++	if (v & 0x00008000)
++		v += 0x10000;
++
++	tramp[0] = 0x3c190000 | (v >> 16);      /* lui t9, hi16 */
++	tramp[1] = 0x27390000 | (v & 0xffff);   /* addiu t9, t9, lo16 */
++	tramp[2] = 0x03200008;                  /* jr t9 */
++	tramp[3] = 0x00000000;                  /* nop */
++
++	return (Elf_Addr) tramp;
++}
++
++static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v)
++{
++	if (is_phys_addr(location))
++		return add_plt_entry_to(&me->arch.phys_plt_offset,
++				me->arch.phys_plt_tbl, v);
++	else
++		return add_plt_entry_to(&me->arch.virt_plt_offset,
++				me->arch.virt_plt_tbl, v);
++
++}
++
++
+ static int apply_r_mips_26(struct module *me, u32 *location, u32 base,
+ 			   Elf_Addr v)
+ {
++	u32 ofs = base & 0x03ffffff;
++
+ 	if (v % 4) {
+ 		pr_err("module %s: dangerous R_MIPS_26 relocation\n",
+ 		       me->name);
+@@ -56,13 +294,17 @@ static int apply_r_mips_26(struct module
+ 	}
+ 
+ 	if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
+-		pr_err("module %s: relocation overflow\n",
+-		       me->name);
+-		return -ENOEXEC;
++		v = add_plt_entry(me, location, v + (ofs << 2));
++		if (!v) {
++			pr_err("module %s: relocation overflow\n",
++			       me->name);
++			return -ENOEXEC;
++		}
++		ofs = 0;
+ 	}
+ 
+ 	*location = (*location & ~0x03ffffff) |
+-		    ((base + (v >> 2)) & 0x03ffffff);
++		    ((ofs + (v >> 2)) & 0x03ffffff);
+ 
+ 	return 0;
+ }
+@@ -442,9 +684,36 @@ int module_finalize(const Elf_Ehdr *hdr,
+ 		list_add(&me->arch.dbe_list, &dbe_list);
+ 		spin_unlock_irq(&dbe_lock);
+ 	}
++
++	/* Get rid of the fixup trampoline if we're running the module
++	 * from physically mapped address space */
++	if (me->arch.phys_plt_offset == 0) {
++		__module_free(me->arch.phys_plt_tbl);
++		me->arch.phys_plt_tbl = NULL;
++	}
++	if (me->arch.virt_plt_offset == 0) {
++		__module_free(me->arch.virt_plt_tbl);
++		me->arch.virt_plt_tbl = NULL;
++	}
++
+ 	return 0;
+ }
+ 
++void module_arch_freeing_init(struct module *mod)
++{
++	if (mod->state == MODULE_STATE_LIVE)
++		return;
++
++	if (mod->arch.phys_plt_tbl) {
++		__module_free(mod->arch.phys_plt_tbl);
++		mod->arch.phys_plt_tbl = NULL;
++	}
++	if (mod->arch.virt_plt_tbl) {
++		__module_free(mod->arch.virt_plt_tbl);
++		mod->arch.virt_plt_tbl = NULL;
++	}
++}
++
+ void module_arch_cleanup(struct module *mod)
+ {
+ 	spin_lock_irq(&dbe_lock);
diff --git a/target/linux/generic/pending-6.6/307-mips_highmem_offset.patch b/target/linux/generic/pending-6.6/307-mips_highmem_offset.patch
new file mode 100644
index 00000000000000..0529b0c5c8aa88
--- /dev/null
+++ b/target/linux/generic/pending-6.6/307-mips_highmem_offset.patch
@@ -0,0 +1,19 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: adjust mips highmem offset to avoid the need for -mlong-calls on systems with >256M RAM
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ arch/mips/include/asm/mach-generic/spaces.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/mach-generic/spaces.h
++++ b/arch/mips/include/asm/mach-generic/spaces.h
+@@ -46,7 +46,7 @@
+  * Memory above this physical address will be considered highmem.
+  */
+ #ifndef HIGHMEM_START
+-#define HIGHMEM_START		_AC(0x20000000, UL)
++#define HIGHMEM_START		_AC(0x10000000, UL)
+ #endif
+ 
+ #endif /* CONFIG_32BIT */
diff --git a/target/linux/generic/pending-6.6/308-mips32r2_tune.patch b/target/linux/generic/pending-6.6/308-mips32r2_tune.patch
new file mode 100644
index 00000000000000..b12058053b1d63
--- /dev/null
+++ b/target/linux/generic/pending-6.6/308-mips32r2_tune.patch
@@ -0,0 +1,22 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: add -mtune=34kc to MIPS CFLAGS when building for mips32r2
+
+This provides a good tradeoff across at least 24Kc-74Kc, while also
+producing smaller code.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ arch/mips/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -163,7 +163,7 @@ cflags-$(CONFIG_CPU_R4300)	+= -march=r43
+ cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap
+ cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap
+ cflags-$(CONFIG_CPU_MIPS32_R1)	+= -march=mips32 -Wa,--trap
+-cflags-$(CONFIG_CPU_MIPS32_R2)	+= -march=mips32r2 -Wa,--trap
++cflags-$(CONFIG_CPU_MIPS32_R2)	+= -march=mips32r2 -mtune=34kc -Wa,--trap
+ cflags-$(CONFIG_CPU_MIPS32_R5)	+= -march=mips32r5 -Wa,--trap -modd-spreg
+ cflags-$(CONFIG_CPU_MIPS32_R6)	+= -march=mips32r6 -Wa,--trap -modd-spreg
+ cflags-$(CONFIG_CPU_MIPS64_R1)	+= -march=mips64 -Wa,--trap
diff --git a/target/linux/generic/pending-6.6/310-arm_module_unresolved_weak_sym.patch b/target/linux/generic/pending-6.6/310-arm_module_unresolved_weak_sym.patch
new file mode 100644
index 00000000000000..54cc9ba64767d8
--- /dev/null
+++ b/target/linux/generic/pending-6.6/310-arm_module_unresolved_weak_sym.patch
@@ -0,0 +1,22 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: fix errors in unresolved weak symbols on arm
+
+lede-commit: 570699d4838a907c3ef9f2819bf19eb72997b32f
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ arch/arm/kernel/module.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm/kernel/module.c
++++ b/arch/arm/kernel/module.c
+@@ -146,6 +146,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons
+ 			return -ENOEXEC;
+ 		}
+ 
++		if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) &&
++		    ELF_ST_BIND(sym->st_info) == STB_WEAK)
++			continue;
++
+ 		loc = dstsec->sh_addr + rel->r_offset;
+ 
+ 		switch (ELF32_R_TYPE(rel->r_info)) {
diff --git a/target/linux/generic/pending-6.6/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch b/target/linux/generic/pending-6.6/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch
new file mode 100644
index 00000000000000..3f553b28b34be7
--- /dev/null
+++ b/target/linux/generic/pending-6.6/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch
@@ -0,0 +1,282 @@
+From: Yousong Zhou <yszhou4tech@gmail.com>
+Subject: MIPS: kexec: Accept command line parameters from userspace.
+
+Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
+---
+ arch/mips/kernel/machine_kexec.c   |  153 +++++++++++++++++++++++++++++++-----
+ arch/mips/kernel/machine_kexec.h   |   20 +++++
+ arch/mips/kernel/relocate_kernel.S |   21 +++--
+ 3 files changed, 167 insertions(+), 27 deletions(-)
+ create mode 100644 arch/mips/kernel/machine_kexec.h
+
+--- a/arch/mips/kernel/machine_kexec.c
++++ b/arch/mips/kernel/machine_kexec.c
+@@ -9,14 +9,11 @@
+ #include <linux/delay.h>
+ #include <linux/libfdt.h>
+ 
++#include <asm/bootinfo.h>
+ #include <asm/cacheflush.h>
+ #include <asm/page.h>
+-
+-extern const unsigned char relocate_new_kernel[];
+-extern const size_t relocate_new_kernel_size;
+-
+-extern unsigned long kexec_start_address;
+-extern unsigned long kexec_indirection_page;
++#include <linux/uaccess.h>
++#include "machine_kexec.h"
+ 
+ static unsigned long reboot_code_buffer;
+ 
+@@ -30,6 +27,101 @@ void (*_crash_smp_send_stop)(void) = NUL
+ void (*_machine_kexec_shutdown)(void) = NULL;
+ void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL;
+ 
++static void machine_kexec_print_args(void)
++{
++	unsigned long argc = (int)kexec_args[0];
++	int i;
++
++	pr_info("kexec_args[0] (argc): %lu\n", argc);
++	pr_info("kexec_args[1] (argv): %p\n", (void *)kexec_args[1]);
++	pr_info("kexec_args[2] (env ): %p\n", (void *)kexec_args[2]);
++	pr_info("kexec_args[3] (desc): %p\n", (void *)kexec_args[3]);
++
++	for (i = 0; i < argc; i++) {
++		pr_info("kexec_argv[%d] = %p, %s\n",
++				i, kexec_argv[i], kexec_argv[i]);
++	}
++}
++
++static void machine_kexec_init_argv(struct kimage *image)
++{
++	void __user *buf = NULL;
++	size_t bufsz;
++	size_t size;
++	int i;
++
++	bufsz = 0;
++	for (i = 0; i < image->nr_segments; i++) {
++		struct kexec_segment *seg;
++
++		seg = &image->segment[i];
++		if (seg->bufsz < 6)
++			continue;
++
++		if (strncmp((char *) seg->buf, "kexec ", 6))
++			continue;
++
++		buf = seg->buf;
++		bufsz = seg->bufsz;
++		break;
++	}
++
++	if (!buf)
++		return;
++
++	size = KEXEC_COMMAND_LINE_SIZE;
++	size = min(size, bufsz);
++	if (size < bufsz)
++		pr_warn("kexec command line truncated to %zd bytes\n", size);
++
++	/* Copy to kernel space */
++	if (copy_from_user(kexec_argv_buf, buf, size))
++		pr_warn("kexec command line copy to kernel space failed\n");
++
++	kexec_argv_buf[size - 1] = 0;
++}
++
++static void machine_kexec_parse_argv(struct kimage *image)
++{
++	char *reboot_code_buffer;
++	int reloc_delta;
++	char *ptr;
++	int argc;
++	int i;
++
++	ptr = kexec_argv_buf;
++	argc = 0;
++
++	/*
++	 * convert command line string to array of parameters
++	 * (as bootloader does).
++	 */
++	while (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) {
++		if (*ptr == ' ') {
++			*ptr++ = '\0';
++			continue;
++		}
++
++		kexec_argv[argc++] = ptr;
++		ptr = strchr(ptr, ' ');
++	}
++
++	if (!argc)
++		return;
++
++	kexec_args[0] = argc;
++	kexec_args[1] = (unsigned long)kexec_argv;
++	kexec_args[2] = 0;
++	kexec_args[3] = 0;
++
++	reboot_code_buffer = page_address(image->control_code_page);
++	reloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel;
++
++	kexec_args[1] += reloc_delta;
++	for (i = 0; i < argc; i++)
++		kexec_argv[i] += reloc_delta;
++}
++
+ static void kexec_image_info(const struct kimage *kimage)
+ {
+ 	unsigned long i;
+@@ -99,6 +191,18 @@ machine_kexec_prepare(struct kimage *kim
+ #endif
+ 
+ 	kexec_image_info(kimage);
++	/*
++	 * Whenever arguments passed from kexec-tools, Init the arguments as
++	 * the original ones to try avoiding booting failure.
++	 */
++
++	kexec_args[0] = fw_arg0;
++	kexec_args[1] = fw_arg1;
++	kexec_args[2] = fw_arg2;
++	kexec_args[3] = fw_arg3;
++
++	machine_kexec_init_argv(kimage);
++	machine_kexec_parse_argv(kimage);
+ 
+ 	if (_machine_kexec_prepare)
+ 		return _machine_kexec_prepare(kimage);
+@@ -161,7 +265,7 @@ machine_crash_shutdown(struct pt_regs *r
+ void kexec_nonboot_cpu_jump(void)
+ {
+ 	local_flush_icache_range((unsigned long)relocated_kexec_smp_wait,
+-				 reboot_code_buffer + relocate_new_kernel_size);
++				 reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE);
+ 
+ 	relocated_kexec_smp_wait(NULL);
+ }
+@@ -199,7 +303,7 @@ void kexec_reboot(void)
+ 	 * machine_kexec() CPU.
+ 	 */
+ 	local_flush_icache_range(reboot_code_buffer,
+-				 reboot_code_buffer + relocate_new_kernel_size);
++				 reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE);
+ 
+ 	do_kexec = (void *)reboot_code_buffer;
+ 	do_kexec();
+@@ -212,10 +316,12 @@ machine_kexec(struct kimage *image)
+ 	unsigned long *ptr;
+ 
+ 	reboot_code_buffer =
+-	  (unsigned long)page_address(image->control_code_page);
++		(unsigned long)page_address(image->control_code_page);
++	pr_info("reboot_code_buffer = %p\n", (void *)reboot_code_buffer);
+ 
+ 	kexec_start_address =
+ 		(unsigned long) phys_to_virt(image->start);
++	pr_info("kexec_start_address = %p\n", (void *)kexec_start_address);
+ 
+ 	if (image->type == KEXEC_TYPE_DEFAULT) {
+ 		kexec_indirection_page =
+@@ -223,9 +329,19 @@ machine_kexec(struct kimage *image)
+ 	} else {
+ 		kexec_indirection_page = (unsigned long)&image->head;
+ 	}
++	pr_info("kexec_indirection_page = %p\n", (void *)kexec_indirection_page);
+ 
+-	memcpy((void*)reboot_code_buffer, relocate_new_kernel,
+-	       relocate_new_kernel_size);
++	pr_info("Where is memcpy: %p\n", memcpy);
++	pr_info("kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\n",
++		(void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end);
++	pr_info("Copy %lu bytes from %p to %p\n", KEXEC_RELOCATE_NEW_KERNEL_SIZE,
++		(void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer);
++	memcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel,
++	       KEXEC_RELOCATE_NEW_KERNEL_SIZE);
++
++	pr_info("Before _print_args().\n");
++	machine_kexec_print_args();
++	pr_info("Before eval loop.\n");
+ 
+ 	/*
+ 	 * The generic kexec code builds a page list with physical
+@@ -256,7 +372,7 @@ machine_kexec(struct kimage *image)
+ #ifdef CONFIG_SMP
+ 	/* All secondary cpus now may jump to kexec_wait cycle */
+ 	relocated_kexec_smp_wait = reboot_code_buffer +
+-		(void *)(kexec_smp_wait - relocate_new_kernel);
++		(void *)(kexec_smp_wait - kexec_relocate_new_kernel);
+ 	smp_wmb();
+ 	atomic_set(&kexec_ready_to_reboot, 1);
+ #endif
+--- /dev/null
++++ b/arch/mips/kernel/machine_kexec.h
+@@ -0,0 +1,20 @@
++#ifndef _MACHINE_KEXEC_H
++#define _MACHINE_KEXEC_H
++
++#ifndef __ASSEMBLY__
++extern const unsigned char kexec_relocate_new_kernel[];
++extern unsigned long kexec_relocate_new_kernel_end;
++extern unsigned long kexec_start_address;
++extern unsigned long kexec_indirection_page;
++
++extern char kexec_argv_buf[];
++extern char *kexec_argv[];
++
++#define KEXEC_RELOCATE_NEW_KERNEL_SIZE	((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel)
++#endif /* !__ASSEMBLY__ */
++
++#define KEXEC_COMMAND_LINE_SIZE		256
++#define KEXEC_ARGV_SIZE			(KEXEC_COMMAND_LINE_SIZE / 16)
++#define KEXEC_MAX_ARGC			(KEXEC_ARGV_SIZE / sizeof(long))
++
++#endif
+--- a/arch/mips/kernel/relocate_kernel.S
++++ b/arch/mips/kernel/relocate_kernel.S
+@@ -10,10 +10,11 @@
+ #include <asm/mipsregs.h>
+ #include <asm/stackframe.h>
+ #include <asm/addrspace.h>
++#include "machine_kexec.h"
+ 
+ #include <kernel-entry-init.h>
+ 
+-LEAF(relocate_new_kernel)
++LEAF(kexec_relocate_new_kernel)
+ 	PTR_L a0,	arg0
+ 	PTR_L a1,	arg1
+ 	PTR_L a2,	arg2
+@@ -98,7 +99,7 @@ done:
+ #endif
+ 	/* jump to kexec_start_address */
+ 	j		s1
+-	END(relocate_new_kernel)
++	END(kexec_relocate_new_kernel)
+ 
+ #ifdef CONFIG_SMP
+ /*
+@@ -177,8 +178,15 @@ EXPORT(kexec_indirection_page)
+ 	PTR_WD		0
+ 	.size		kexec_indirection_page, PTRSIZE
+ 
+-relocate_new_kernel_end:
++kexec_argv_buf:
++	EXPORT(kexec_argv_buf)
++	.skip		KEXEC_COMMAND_LINE_SIZE
++	.size		kexec_argv_buf, KEXEC_COMMAND_LINE_SIZE
++
++kexec_argv:
++	EXPORT(kexec_argv)
++	.skip		KEXEC_ARGV_SIZE
++	.size		kexec_argv, KEXEC_ARGV_SIZE
+ 
+-EXPORT(relocate_new_kernel_size)
+-	PTR_WD		relocate_new_kernel_end - relocate_new_kernel
+-	.size		relocate_new_kernel_size, PTRSIZE
++kexec_relocate_new_kernel_end:
++	EXPORT(kexec_relocate_new_kernel_end)
diff --git a/target/linux/generic/pending-6.6/332-arc-add-OWRTDTB-section.patch b/target/linux/generic/pending-6.6/332-arc-add-OWRTDTB-section.patch
new file mode 100644
index 00000000000000..490e26ab169523
--- /dev/null
+++ b/target/linux/generic/pending-6.6/332-arc-add-OWRTDTB-section.patch
@@ -0,0 +1,84 @@
+From bb0c3b0175240bf152fd7c644821a0cf9f77c37c Mon Sep 17 00:00:00 2001
+From: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
+Date: Fri, 15 Mar 2019 18:53:38 +0300
+Subject: [PATCH] arc add OWRTDTB section
+
+This change allows OpenWRT to patch resulting kernel binary with
+external .dtb.
+
+That allows us to re-use exactky the same vmlinux on different boards
+given its ARC core configurations match (at least cache line sizes etc).
+
+""patch-dtb" searches for ASCII "OWRTDTB:" strign and copies external
+.dtb right after it, keeping the string in place.
+
+Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
+Signed-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
+---
+ arch/arc/kernel/head.S        | 10 ++++++++++
+ arch/arc/kernel/setup.c       |  4 +++-
+ arch/arc/kernel/vmlinux.lds.S | 13 +++++++++++++
+ 3 files changed, 26 insertions(+), 1 deletion(-)
+
+--- a/arch/arc/kernel/head.S
++++ b/arch/arc/kernel/head.S
+@@ -88,6 +88,16 @@
+ 	DSP_EARLY_INIT
+ .endm
+ 
++	; Here "patch-dtb" will embed external .dtb
++	; Note "patch-dtb" searches for ASCII "OWRTDTB:" string
++	; and pastes .dtb right after it, hense the string precedes
++	; __image_dtb symbol.
++	.section .owrt, "aw",@progbits
++	.ascii  "OWRTDTB:"
++ENTRY(__image_dtb)
++	.fill   0x4000
++END(__image_dtb)
++
+ 	.section .init.text, "ax",@progbits
+ 
+ ;----------------------------------------------------------------
+--- a/arch/arc/kernel/setup.c
++++ b/arch/arc/kernel/setup.c
+@@ -450,6 +450,8 @@ static inline bool uboot_arg_invalid(uns
+ /* We always pass 0 as magic from U-boot */
+ #define UBOOT_MAGIC_VALUE	0
+ 
++extern struct boot_param_header __image_dtb;
++
+ void __init handle_uboot_args(void)
+ {
+ 	bool use_embedded_dtb = true;
+@@ -488,7 +490,7 @@ void __init handle_uboot_args(void)
+ ignore_uboot_args:
+ 
+ 	if (use_embedded_dtb) {
+-		machine_desc = setup_machine_fdt(__dtb_start);
++		machine_desc = setup_machine_fdt(&__image_dtb);
+ 		if (!machine_desc)
+ 			panic("Embedded DT invalid\n");
+ 	}
+--- a/arch/arc/kernel/vmlinux.lds.S
++++ b/arch/arc/kernel/vmlinux.lds.S
+@@ -27,6 +27,19 @@ SECTIONS
+ 
+ 	. = CONFIG_LINUX_LINK_BASE;
+ 
++	/*
++	* In OpenWRT we want to patch built binary embedding .dtb of choice.
++	* This is implemented with "patch-dtb" utility which searches for
++	* "OWRTDTB:" string in first 16k of image and if it is found
++	* copies .dtb right after mentioned string.
++	*
++	* Note: "OWRTDTB:" won't be overwritten with .dtb, .dtb will follow it.
++	*/
++ 	.owrt : {
++		*(.owrt)
++	. = ALIGN(PAGE_SIZE);
++	}
++
+ 	_int_vec_base_lds = .;
+ 	.vector : {
+ 		*(.vector)
diff --git a/target/linux/generic/pending-6.6/333-arc-enable-unaligned-access-in-kernel-mode.patch b/target/linux/generic/pending-6.6/333-arc-enable-unaligned-access-in-kernel-mode.patch
new file mode 100644
index 00000000000000..1848a84cc4970f
--- /dev/null
+++ b/target/linux/generic/pending-6.6/333-arc-enable-unaligned-access-in-kernel-mode.patch
@@ -0,0 +1,24 @@
+From: Alexey Brodkin <abrodkin@synopsys.com>
+Subject: arc: enable unaligned access in kernel mode
+
+This enables misaligned access handling even in kernel mode.
+Some wireless drivers (ath9k-htc and mt7601u) use misaligned accesses
+here and there and to cope with that without fixing stuff in the drivers
+we're just gracefully handling it on ARC.
+
+Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
+---
+ arch/arc/kernel/unaligned.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arc/kernel/unaligned.c
++++ b/arch/arc/kernel/unaligned.c
+@@ -202,7 +202,7 @@ int misaligned_fixup(unsigned long addre
+ 	char buf[TASK_COMM_LEN];
+ 
+ 	/* handle user mode only and only if enabled by sysadmin */
+-	if (!user_mode(regs) || !unaligned_enabled)
++	if (!unaligned_enabled)
+ 		return 1;
+ 
+ 	if (no_unaligned_warning) {
diff --git a/target/linux/generic/pending-6.6/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch b/target/linux/generic/pending-6.6/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch
new file mode 100644
index 00000000000000..71173b081c104c
--- /dev/null
+++ b/target/linux/generic/pending-6.6/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch
@@ -0,0 +1,25 @@
+From 66770a004afe10df11d3902e16eaa0c2c39436bb Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Fri, 24 May 2019 17:56:19 +0200
+Subject: [PATCH] powerpc: Enable kernel XZ compression option on PPC_85xx
+
+Enable kernel XZ compression option on PPC_85xx. Tested with
+simpleImage on TP-Link TL-WDR4900 (Freescale P1014 processor).
+
+Suggested-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -251,7 +251,7 @@ config PPC
+ 	select HAVE_KERNEL_GZIP
+ 	select HAVE_KERNEL_LZMA			if DEFAULT_UIMAGE
+ 	select HAVE_KERNEL_LZO			if DEFAULT_UIMAGE
+-	select HAVE_KERNEL_XZ			if PPC_BOOK3S || 44x
++	select HAVE_KERNEL_XZ			if PPC_BOOK3S || 44x || PPC_85xx
+ 	select HAVE_KPROBES
+ 	select HAVE_KPROBES_ON_FTRACE
+ 	select HAVE_KRETPROBES
diff --git a/target/linux/generic/pending-6.6/400-mtd-mtdsplit-support.patch b/target/linux/generic/pending-6.6/400-mtd-mtdsplit-support.patch
new file mode 100644
index 00000000000000..4ccf51fd9d56cd
--- /dev/null
+++ b/target/linux/generic/pending-6.6/400-mtd-mtdsplit-support.patch
@@ -0,0 +1,314 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -12,6 +12,25 @@ menuconfig MTD
+ 
+ if MTD
+ 
++menu "OpenWrt specific MTD options"
++
++config MTD_ROOTFS_ROOT_DEV
++	bool "Automatically set 'rootfs' partition to be root filesystem"
++	default y
++
++config MTD_SPLIT_FIRMWARE
++	bool "Automatically split firmware partition for kernel+rootfs"
++	default y
++
++config MTD_SPLIT_FIRMWARE_NAME
++	string "Firmware partition name"
++	depends on MTD_SPLIT_FIRMWARE
++	default "firmware"
++
++source "drivers/mtd/mtdsplit/Kconfig"
++
++endmenu
++
+ config MTD_TESTS
+ 	tristate "MTD tests support (DANGEROUS)"
+ 	depends on m
+--- a/drivers/mtd/mtdpart.c
++++ b/drivers/mtd/mtdpart.c
+@@ -15,11 +15,13 @@
+ #include <linux/kmod.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
++#include <linux/magic.h>
+ #include <linux/err.h>
+ #include <linux/of.h>
+ #include <linux/of_platform.h>
+ 
+ #include "mtdcore.h"
++#include "mtdsplit/mtdsplit.h"
+ 
+ /*
+  * MTD methods which simply translate the effective address and pass through
+@@ -242,6 +244,146 @@ static int mtd_add_partition_attrs(struc
+ 	return ret;
+ }
+ 
++static DEFINE_SPINLOCK(part_parser_lock);
++static LIST_HEAD(part_parsers);
++
++static struct mtd_part_parser *mtd_part_parser_get(const char *name)
++{
++	struct mtd_part_parser *p, *ret = NULL;
++
++	spin_lock(&part_parser_lock);
++
++	list_for_each_entry(p, &part_parsers, list)
++		if (!strcmp(p->name, name) && try_module_get(p->owner)) {
++			ret = p;
++			break;
++		}
++
++	spin_unlock(&part_parser_lock);
++
++	return ret;
++}
++
++static inline void mtd_part_parser_put(const struct mtd_part_parser *p)
++{
++	module_put(p->owner);
++}
++
++static struct mtd_part_parser *
++get_partition_parser_by_type(enum mtd_parser_type type,
++			     struct mtd_part_parser *start)
++{
++	struct mtd_part_parser *p, *ret = NULL;
++
++	spin_lock(&part_parser_lock);
++
++	p = list_prepare_entry(start, &part_parsers, list);
++	if (start)
++		mtd_part_parser_put(start);
++
++	list_for_each_entry_continue(p, &part_parsers, list) {
++		if (p->type == type && try_module_get(p->owner)) {
++			ret = p;
++			break;
++		}
++	}
++
++	spin_unlock(&part_parser_lock);
++
++	return ret;
++}
++
++static int parse_mtd_partitions_by_type(struct mtd_info *master,
++					enum mtd_parser_type type,
++					const struct mtd_partition **pparts,
++					struct mtd_part_parser_data *data)
++{
++	struct mtd_part_parser *prev = NULL;
++	int ret = 0;
++
++	while (1) {
++		struct mtd_part_parser *parser;
++
++		parser = get_partition_parser_by_type(type, prev);
++		if (!parser)
++			break;
++
++		ret = (*parser->parse_fn)(master, pparts, data);
++
++		if (ret > 0) {
++			mtd_part_parser_put(parser);
++			printk(KERN_NOTICE
++			       "%d %s partitions found on MTD device %s\n",
++			       ret, parser->name, master->name);
++			break;
++		}
++
++		prev = parser;
++	}
++
++	return ret;
++}
++
++static int
++run_parsers_by_type(struct mtd_info *child, enum mtd_parser_type type)
++{
++	struct mtd_partition *parts;
++	int nr_parts;
++	int i;
++
++	nr_parts = parse_mtd_partitions_by_type(child, type, (const struct mtd_partition **)&parts,
++						NULL);
++	if (nr_parts <= 0)
++		return nr_parts;
++
++	if (WARN_ON(!parts))
++		return 0;
++
++	for (i = 0; i < nr_parts; i++) {
++		/* adjust partition offsets */
++		parts[i].offset += child->part.offset;
++
++		mtd_add_partition(child->parent,
++				  parts[i].name,
++				  parts[i].offset,
++				  parts[i].size);
++	}
++
++	kfree(parts);
++
++	return nr_parts;
++}
++
++#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME
++#define SPLIT_FIRMWARE_NAME	CONFIG_MTD_SPLIT_FIRMWARE_NAME
++#else
++#define SPLIT_FIRMWARE_NAME	"unused"
++#endif
++
++static void split_firmware(struct mtd_info *master, struct mtd_info *part)
++{
++	run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE);
++}
++
++static void mtd_partition_split(struct mtd_info *master, struct mtd_info *part)
++{
++	static int rootfs_found = 0;
++
++	if (rootfs_found)
++		return;
++
++	if (!strcmp(part->name, "rootfs")) {
++		run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS);
++
++		rootfs_found = 1;
++	}
++
++	if (IS_ENABLED(CONFIG_MTD_SPLIT_FIRMWARE) &&
++	    !strcmp(part->name, SPLIT_FIRMWARE_NAME) &&
++	    !of_find_property(mtd_get_of_node(part), "compatible", NULL))
++		split_firmware(master, part);
++}
++
+ int mtd_add_partition(struct mtd_info *parent, const char *name,
+ 		      long long offset, long long length)
+ {
+@@ -280,6 +422,7 @@ int mtd_add_partition(struct mtd_info *p
+ 	if (ret)
+ 		goto err_remove_part;
+ 
++	mtd_partition_split(parent, child);
+ 	mtd_add_partition_attrs(child);
+ 
+ 	return 0;
+@@ -423,6 +566,7 @@ int add_mtd_partitions(struct mtd_info *
+ 			goto err_del_partitions;
+ 		}
+ 
++		mtd_partition_split(master, child);
+ 		mtd_add_partition_attrs(child);
+ 
+ 		/* Look for subpartitions */
+@@ -439,31 +583,6 @@ err_del_partitions:
+ 	return ret;
+ }
+ 
+-static DEFINE_SPINLOCK(part_parser_lock);
+-static LIST_HEAD(part_parsers);
+-
+-static struct mtd_part_parser *mtd_part_parser_get(const char *name)
+-{
+-	struct mtd_part_parser *p, *ret = NULL;
+-
+-	spin_lock(&part_parser_lock);
+-
+-	list_for_each_entry(p, &part_parsers, list)
+-		if (!strcmp(p->name, name) && try_module_get(p->owner)) {
+-			ret = p;
+-			break;
+-		}
+-
+-	spin_unlock(&part_parser_lock);
+-
+-	return ret;
+-}
+-
+-static inline void mtd_part_parser_put(const struct mtd_part_parser *p)
+-{
+-	module_put(p->owner);
+-}
+-
+ /*
+  * Many partition parsers just expected the core to kfree() all their data in
+  * one chunk. Do that by default.
+--- a/include/linux/mtd/partitions.h
++++ b/include/linux/mtd/partitions.h
+@@ -75,6 +75,12 @@ struct mtd_part_parser_data {
+  * Functions dealing with the various ways of partitioning the space
+  */
+ 
++enum mtd_parser_type {
++	MTD_PARSER_TYPE_DEVICE = 0,
++	MTD_PARSER_TYPE_ROOTFS,
++	MTD_PARSER_TYPE_FIRMWARE,
++};
++
+ struct mtd_part_parser {
+ 	struct list_head list;
+ 	struct module *owner;
+@@ -83,6 +89,7 @@ struct mtd_part_parser {
+ 	int (*parse_fn)(struct mtd_info *, const struct mtd_partition **,
+ 			struct mtd_part_parser_data *);
+ 	void (*cleanup)(const struct mtd_partition *pparts, int nr_parts);
++	enum mtd_parser_type type;
+ };
+ 
+ /* Container for passing around a set of parsed partitions */
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -9,6 +9,8 @@ mtd-y				:= mtdcore.o mtdsuper.o mtdconc
+ 
+ obj-y				+= parsers/
+ 
++obj-$(CONFIG_MTD_SPLIT)		+= mtdsplit/
++
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_BLKDEVS)	+= mtd_blkdevs.o
+ obj-$(CONFIG_MTD_BLOCK)		+= mtdblock.o
+--- a/include/linux/mtd/mtd.h
++++ b/include/linux/mtd/mtd.h
+@@ -615,6 +615,24 @@ static inline void mtd_align_erase_req(s
+ 		req->len += mtd->erasesize - mod;
+ }
+ 
++static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd)
++{
++	if (mtd_mod_by_eb(sz, mtd) == 0)
++		return sz;
++
++	/* Round up to next erase block */
++	return (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize;
++}
++
++static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd)
++{
++	if (mtd_mod_by_eb(sz, mtd) == 0)
++		return sz;
++
++	/* Round down to the start of the current erase block */
++	return (mtd_div_by_eb(sz, mtd)) * mtd->erasesize;
++}
++
+ static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd)
+ {
+ 	if (mtd->writesize_shift)
+@@ -688,6 +706,13 @@ extern struct mtd_info *of_get_mtd_devic
+ extern struct mtd_info *get_mtd_device_nm(const char *name);
+ extern void put_mtd_device(struct mtd_info *mtd);
+ 
++static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd)
++{
++	if (!mtd_is_partition(mtd))
++		return 0;
++
++	return mtd->part.offset;
++}
+ 
+ struct mtd_notifier {
+ 	void (*add)(struct mtd_info *mtd);
diff --git a/target/linux/generic/pending-6.6/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch b/target/linux/generic/pending-6.6/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch
new file mode 100644
index 00000000000000..cbe9003f95b42b
--- /dev/null
+++ b/target/linux/generic/pending-6.6/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch
@@ -0,0 +1,389 @@
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+From: John Thomson <git@johnthomson.fastmail.com.au>
+To: Miquel Raynal <miquel.raynal@bootlin.com>,
+ Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,
+ Tudor Ambarus <tudor.ambarus@microchip.com>,
+ Michael Walle <michael@walle.cc>, Pratyush Yadav <p.yadav@ti.com>,
+ linux-mtd@lists.infradead.org
+Cc: linux-kernel@vger.kernel.org,
+ John Thomson <git@johnthomson.fastmail.com.au>,
+ kernel test robot <lkp@intel.com>, Dan Carpenter <dan.carpenter@oracle.com>
+Subject: [PATCH] mtd: spi-nor: write support for minor aligned partitions
+Date: Tue,  8 Jun 2021 14:07:19 +1000
+Message-Id: <20210608040719.14431-1-git@johnthomson.fastmail.com.au>
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+ Content preview:  Do not prevent writing to mtd partitions where a partition
+ boundary sits on a minor erasesize boundary. This addresses a FIXME that
+ has been present since the start of the linux git history: /* Doesn' [...]
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+
+Do not prevent writing to mtd partitions where a partition boundary sits
+on a minor erasesize boundary.
+This addresses a FIXME that has been present since the start of the
+linux git history:
+/* Doesn't start on a boundary of major erase size */
+/* FIXME: Let it be writable if it is on a boundary of
+ * _minor_ erase size though */
+
+Allow a uniform erase region spi-nor device to be configured
+to use the non-uniform erase regions code path for an erase with:
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+
+On supporting hardware (SECT_4K: majority of current SPI-NOR device)
+provide the facility for an erase to use the least number
+of SPI-NOR operations, as well as access to 4K erase without
+requiring CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
+
+Introduce erasesize_minor to the mtd struct,
+the smallest erasesize supported by the device
+
+On existing devices, this is useful where write support is wanted
+for data on a 4K partition, such as some u-boot-env partitions,
+or RouterBoot soft_config, while still netting the performance
+benefits of using 64K sectors
+
+Performance:
+time mtd erase firmware
+OpenWrt 5.10 ramips MT7621 w25q128jv 0xfc0000 partition length
+
+Without this patch
+MTD_SPI_NOR_USE_4K_SECTORS=y	|n
+real    2m 11.66s		|0m 50.86s
+user    0m 0.00s		|0m 0.00s
+sys     1m 56.20s		|0m 50.80s
+
+With this patch
+MTD_SPI_NOR_USE_VARIABLE_ERASE=n|y		|4K_SECTORS=y
+real    0m 51.68s		|0m 50.85s	|2m 12.89s
+user    0m 0.00s		|0m 0.00s	|0m 0.01s
+sys     0m 46.94s		|0m 50.38s	|2m 12.46s
+
+Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
+---
+Have not tested on variable erase regions device.
+
+checkpatch does not like the printk(KERN_WARNING
+these should be changed separately beforehand?
+
+Changes RFC -> v1:
+Fix uninitialized variable smatch warning
+Reported-by: kernel test robot <lkp@intel.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+---
+ drivers/mtd/mtdpart.c       | 52 ++++++++++++++++++++++++++++---------
+ drivers/mtd/spi-nor/Kconfig | 10 +++++++
+ drivers/mtd/spi-nor/core.c  | 10 +++++--
+ include/linux/mtd/mtd.h     |  2 ++
+ 4 files changed, 60 insertions(+), 14 deletions(-)
+
+--- a/drivers/mtd/mtdpart.c
++++ b/drivers/mtd/mtdpart.c
+@@ -47,10 +47,11 @@ static struct mtd_info *allocate_partiti
+ 	struct mtd_info *master = mtd_get_master(parent);
+ 	int wr_alignment = (parent->flags & MTD_NO_ERASE) ?
+ 			   master->writesize : master->erasesize;
++	int wr_alignment_minor = 0;
+ 	u64 parent_size = mtd_is_partition(parent) ?
+ 			  parent->part.size : parent->size;
+ 	struct mtd_info *child;
+-	u32 remainder;
++	u32 remainder, remainder_minor;
+ 	char *name;
+ 	u64 tmp;
+ 
+@@ -152,6 +153,7 @@ static struct mtd_info *allocate_partiti
+ 		int i, max = parent->numeraseregions;
+ 		u64 end = child->part.offset + child->part.size;
+ 		struct mtd_erase_region_info *regions = parent->eraseregions;
++		uint32_t erasesize_minor = child->erasesize;
+ 
+ 		/* Find the first erase regions which is part of this
+ 		 * partition. */
+@@ -162,15 +164,24 @@ static struct mtd_info *allocate_partiti
+ 		if (i > 0)
+ 			i--;
+ 
+-		/* Pick biggest erasesize */
+ 		for (; i < max && regions[i].offset < end; i++) {
++			/* Pick biggest erasesize */
+ 			if (child->erasesize < regions[i].erasesize)
+ 				child->erasesize = regions[i].erasesize;
++			/* Pick smallest non-zero erasesize */
++			if ((erasesize_minor > regions[i].erasesize) && (regions[i].erasesize > 0))
++				erasesize_minor = regions[i].erasesize;
+ 		}
++
++		if (erasesize_minor < child->erasesize)
++			child->erasesize_minor = erasesize_minor;
++
+ 		BUG_ON(child->erasesize == 0);
+ 	} else {
+ 		/* Single erase size */
+ 		child->erasesize = master->erasesize;
++		if (master->erasesize_minor)
++			child->erasesize_minor = master->erasesize_minor;
+ 	}
+ 
+ 	/*
+@@ -178,26 +189,43 @@ static struct mtd_info *allocate_partiti
+ 	 * exposes several regions with different erasesize. Adjust
+ 	 * wr_alignment accordingly.
+ 	 */
+-	if (!(child->flags & MTD_NO_ERASE))
++	if (!(child->flags & MTD_NO_ERASE)) {
+ 		wr_alignment = child->erasesize;
++		if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE) && child->erasesize_minor)
++			wr_alignment_minor = child->erasesize_minor;
++	}
+ 
+ 	tmp = mtd_get_master_ofs(child, 0);
+ 	remainder = do_div(tmp, wr_alignment);
+ 	if ((child->flags & MTD_WRITEABLE) && remainder) {
+-		/* Doesn't start on a boundary of major erase size */
+-		/* FIXME: Let it be writable if it is on a boundary of
+-		 * _minor_ erase size though */
+-		child->flags &= ~MTD_WRITEABLE;
+-		printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase/write block boundary -- force read-only\n",
+-			part->name);
++		if (wr_alignment_minor) {
++			tmp = mtd_get_master_ofs(child, 0);
++			remainder_minor = do_div(tmp, wr_alignment_minor);
++			if (remainder_minor == 0)
++				child->erasesize = child->erasesize_minor;
++		}
++
++		if ((!wr_alignment_minor) || (wr_alignment_minor && remainder_minor != 0)) {
++			child->flags &= ~MTD_WRITEABLE;
++			printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase/write block boundary -- force read-only\n",
++				part->name);
++		}
+ 	}
+ 
+ 	tmp = mtd_get_master_ofs(child, 0) + child->part.size;
+ 	remainder = do_div(tmp, wr_alignment);
+ 	if ((child->flags & MTD_WRITEABLE) && remainder) {
+-		child->flags &= ~MTD_WRITEABLE;
+-		printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase/write block -- force read-only\n",
+-			part->name);
++		if (wr_alignment_minor) {
++			tmp = mtd_get_master_ofs(child, 0) + child->part.size;
++			remainder_minor = do_div(tmp, wr_alignment_minor);
++			if (remainder_minor == 0)
++				child->erasesize = child->erasesize_minor;
++		}
++		if ((!wr_alignment_minor) || (wr_alignment_minor && remainder_minor != 0)) {
++			child->flags &= ~MTD_WRITEABLE;
++			printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase/write block -- force read-only\n",
++				part->name);
++		}
+ 	}
+ 
+ 	child->size = child->part.size;
+--- a/drivers/mtd/spi-nor/Kconfig
++++ b/drivers/mtd/spi-nor/Kconfig
+@@ -10,6 +10,16 @@ menuconfig MTD_SPI_NOR
+ 
+ if MTD_SPI_NOR
+ 
++config MTD_SPI_NOR_USE_VARIABLE_ERASE
++	bool "Disable uniform_erase to allow use of all hardware supported erasesizes"
++	depends on !MTD_SPI_NOR_USE_4K_SECTORS
++	default n
++	help
++	  Allow mixed use of all hardware supported erasesizes,
++	  by forcing spi_nor to use the multiple eraseregions code path.
++	  For example: A 68K erase will use one 64K erase, and one 4K erase
++	  on supporting hardware.
++
+ config MTD_SPI_NOR_USE_4K_SECTORS
+ 	bool "Use small 4096 B erase sectors"
+ 	default y
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1150,6 +1150,8 @@ static u8 spi_nor_convert_3to4_erase(u8
+ 
+ static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
+ {
++	if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE))
++		return false;
+ 	return !!nor->params->erase_map.uniform_erase_type;
+ }
+ 
+@@ -2582,6 +2584,7 @@ static int spi_nor_select_erase(struct s
+ {
+ 	struct spi_nor_erase_map *map = &nor->params->erase_map;
+ 	const struct spi_nor_erase_type *erase = NULL;
++	const struct spi_nor_erase_type *erase_minor = NULL;
+ 	struct mtd_info *mtd = &nor->mtd;
+ 	u32 wanted_size = nor->info->sector_size;
+ 	int i;
+@@ -2614,8 +2617,9 @@ static int spi_nor_select_erase(struct s
+ 	 */
+ 	for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
+ 		if (map->erase_type[i].size) {
+-			erase = &map->erase_type[i];
+-			break;
++			if (!erase)
++				erase = &map->erase_type[i];
++			erase_minor = &map->erase_type[i];
+ 		}
+ 	}
+ 
+@@ -2623,6 +2627,8 @@ static int spi_nor_select_erase(struct s
+ 		return -EINVAL;
+ 
+ 	mtd->erasesize = erase->size;
++	if (erase_minor && erase_minor->size < erase->size)
++		mtd->erasesize_minor = erase_minor->size;
+ 	return 0;
+ }
+ 
+--- a/include/linux/mtd/mtd.h
++++ b/include/linux/mtd/mtd.h
+@@ -245,6 +245,8 @@ struct mtd_info {
+ 	 * information below if they desire
+ 	 */
+ 	uint32_t erasesize;
++	/* "Minor" (smallest) erase size supported by the whole device */
++	uint32_t erasesize_minor;
+ 	/* Minimal writable flash unit size. In case of NOR flash it is 1 (even
+ 	 * though individual bits can be cleared), in case of NAND flash it is
+ 	 * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
diff --git a/target/linux/generic/pending-6.6/419-mtd-redboot-add-of_match_table-with-DT-binding.patch b/target/linux/generic/pending-6.6/419-mtd-redboot-add-of_match_table-with-DT-binding.patch
new file mode 100644
index 00000000000000..ade36033ddd656
--- /dev/null
+++ b/target/linux/generic/pending-6.6/419-mtd-redboot-add-of_match_table-with-DT-binding.patch
@@ -0,0 +1,22 @@
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH] mtd: redboot: add of_match_table with DT binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This allows parsing RedBoot compatible partitions for properly described
+flash device in DT.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/mtd/parsers/redboot.c
++++ b/drivers/mtd/parsers/redboot.c
+@@ -305,6 +305,7 @@ nogood:
+ 
+ static const struct of_device_id mtd_parser_redboot_of_match_table[] = {
+ 	{ .compatible = "redboot-fis" },
++	{ .compatible = "ecoscentric,redboot-fis-partitions" },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, mtd_parser_redboot_of_match_table);
diff --git a/target/linux/generic/pending-6.6/420-mtd-redboot_space.patch b/target/linux/generic/pending-6.6/420-mtd-redboot_space.patch
new file mode 100644
index 00000000000000..5518ea71dd51f9
--- /dev/null
+++ b/target/linux/generic/pending-6.6/420-mtd-redboot_space.patch
@@ -0,0 +1,41 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: add patch for including unpartitioned space in the rootfs partition for redboot devices (if applicable)
+
+[john@phrozen.org: used by ixp and others]
+
+lede-commit: 394918851f84e4d00fa16eb900e7700e95091f00
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/mtd/redboot.c | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/parsers/redboot.c
++++ b/drivers/mtd/parsers/redboot.c
+@@ -278,14 +278,21 @@ nogood:
+ #endif
+ 		names += strlen(names) + 1;
+ 
+-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
+ 		if (fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) {
+-			i++;
+-			parts[i].offset = parts[i - 1].size + parts[i - 1].offset;
+-			parts[i].size = fl->next->img->flash_base - parts[i].offset;
+-			parts[i].name = nullname;
+-		}
++			if (!strcmp(parts[i].name, "rootfs")) {
++				parts[i].size = fl->next->img->flash_base;
++				parts[i].size &= ~(master->erasesize - 1);
++				parts[i].size -= parts[i].offset;
++#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
++				nrparts--;
++			} else {
++				i++;
++				parts[i].offset = parts[i-1].size + parts[i-1].offset;
++				parts[i].size = fl->next->img->flash_base - parts[i].offset;
++				parts[i].name = nullname;
+ #endif
++			}
++		}
+ 		tmp_fl = fl;
+ 		fl = fl->next;
+ 		kfree(tmp_fl);
diff --git a/target/linux/generic/pending-6.6/430-mtd-add-myloader-partition-parser.patch b/target/linux/generic/pending-6.6/430-mtd-add-myloader-partition-parser.patch
new file mode 100644
index 00000000000000..c0b8c9b6011f24
--- /dev/null
+++ b/target/linux/generic/pending-6.6/430-mtd-add-myloader-partition-parser.patch
@@ -0,0 +1,229 @@
+From: Florian Fainelli <f.fainelli@gmail.com>
+Subject: Add myloader partition table parser
+
+[john@phozen.org: shoud be upstreamable]
+
+lede-commit: d8bf22859b51faa09d22c056fe221a45d2f7a3b8
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+[adjust for kernel 5.4, add myloader.c to patch]
+Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
+
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -67,6 +67,22 @@ config MTD_CMDLINE_PARTS
+ 
+ 	  If unsure, say 'N'.
+ 
++config MTD_MYLOADER_PARTS
++	tristate "MyLoader partition parsing"
++	depends on ADM5120 || ATH25 || ATH79
++	help
++	  MyLoader is a bootloader which allows the user to define partitions
++	  in flash devices, by putting a table in the second erase block
++	  on the device, similar to a partition table. This table gives the 
++	  offsets and lengths of the user defined partitions.
++
++	  If you need code which can detect and parse these tables, and
++	  register MTD 'partitions' corresponding to each image detected,
++	  enable this option.
++
++	  You will still need the parsing functions to be called by the driver
++	  for your particular device. It won't happen automatically.
++
+ config MTD_OF_PARTS
+ 	tristate "OpenFirmware (device tree) partitioning parser"
+ 	default y
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_MTD_BCM47XX_PARTS)		+= bcm4
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)		+= bcm63xxpart.o
+ obj-$(CONFIG_MTD_BRCM_U_BOOT)		+= brcm_u-boot.o
+ obj-$(CONFIG_MTD_CMDLINE_PARTS)		+= cmdlinepart.o
++obj-$(CONFIG_MTD_MYLOADER_PARTS)		+= myloader.o
+ obj-$(CONFIG_MTD_OF_PARTS)		+= ofpart.o
+ ofpart-y				+= ofpart_core.o
+ ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)	+= ofpart_bcm4908.o
+--- /dev/null
++++ b/drivers/mtd/parsers/myloader.c
+@@ -0,0 +1,181 @@
++/*
++ *  Parse MyLoader-style flash partition tables and produce a Linux partition
++ *  array to match.
++ *
++ *  Copyright (C) 2007-2009 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This file was based on drivers/mtd/redboot.c
++ *  Author: Red Hat, Inc. - David Woodhouse <dwmw2@cambridge.redhat.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/vmalloc.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/byteorder/generic.h>
++#include <linux/myloader.h>
++
++#define BLOCK_LEN_MIN		0x10000
++#define PART_NAME_LEN		32
++
++struct part_data {
++	struct mylo_partition_table	tab;
++	char names[MYLO_MAX_PARTITIONS][PART_NAME_LEN];
++};
++
++static int myloader_parse_partitions(struct mtd_info *master,
++				     const struct mtd_partition **pparts,
++				     struct mtd_part_parser_data *data)
++{
++	struct part_data *buf;
++	struct mylo_partition_table *tab;
++	struct mylo_partition *part;
++	struct mtd_partition *mtd_parts;
++	struct mtd_partition *mtd_part;
++	int num_parts;
++	int ret, i;
++	size_t retlen;
++	char *names;
++	unsigned long offset;
++	unsigned long blocklen;
++
++	buf = vmalloc(sizeof(*buf));
++	if (!buf) {
++		return -ENOMEM;
++		goto out;
++	}
++	tab = &buf->tab;
++
++	blocklen = master->erasesize;
++	if (blocklen < BLOCK_LEN_MIN)
++		blocklen = BLOCK_LEN_MIN;
++
++	offset = blocklen;
++
++	/* Find the partition table */
++	for (i = 0; i < 4; i++, offset += blocklen) {
++		printk(KERN_DEBUG "%s: searching for MyLoader partition table"
++				" at offset 0x%lx\n", master->name, offset);
++
++		ret = mtd_read(master, offset, sizeof(*buf), &retlen,
++			       (void *)buf);
++		if (ret)
++			goto out_free_buf;
++
++		if (retlen != sizeof(*buf)) {
++			ret = -EIO;
++			goto out_free_buf;
++		}
++
++		/* Check for Partition Table magic number */
++		if (tab->magic == le32_to_cpu(MYLO_MAGIC_PARTITIONS))
++			break;
++
++	}
++
++	if (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) {
++		printk(KERN_DEBUG "%s: no MyLoader partition table found\n",
++			master->name);
++		ret = 0;
++		goto out_free_buf;
++	}
++
++	/* The MyLoader and the Partition Table is always present */
++	num_parts = 2;
++
++	/* Detect number of used partitions */
++	for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
++		part = &tab->partitions[i];
++
++		if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
++			continue;
++
++		num_parts++;
++	}
++
++	mtd_parts = kzalloc((num_parts * sizeof(*mtd_part) +
++				num_parts * PART_NAME_LEN), GFP_KERNEL);
++
++	if (!mtd_parts) {
++		ret = -ENOMEM;
++		goto out_free_buf;
++	}
++
++	mtd_part = mtd_parts;
++	names = (char *)&mtd_parts[num_parts];
++
++	strncpy(names, "myloader", PART_NAME_LEN);
++	mtd_part->name = names;
++	mtd_part->offset = 0;
++	mtd_part->size = offset;
++	mtd_part->mask_flags = MTD_WRITEABLE;
++	mtd_part++;
++	names += PART_NAME_LEN;
++
++	strncpy(names, "partition_table", PART_NAME_LEN);
++	mtd_part->name = names;
++	mtd_part->offset = offset;
++	mtd_part->size = blocklen;
++	mtd_part->mask_flags = MTD_WRITEABLE;
++	mtd_part++;
++	names += PART_NAME_LEN;
++
++	for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
++		part = &tab->partitions[i];
++
++		if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
++			continue;
++
++		if ((buf->names[i][0]) && (buf->names[i][0] != '\xff'))
++			strncpy(names, buf->names[i], PART_NAME_LEN);
++		else
++			snprintf(names, PART_NAME_LEN, "partition%d", i);
++
++		mtd_part->offset = le32_to_cpu(part->addr);
++		mtd_part->size = le32_to_cpu(part->size);
++		mtd_part->name = names;
++		mtd_part++;
++		names += PART_NAME_LEN;
++	}
++
++	*pparts = mtd_parts;
++	ret = num_parts;
++
++ out_free_buf:
++	vfree(buf);
++ out:
++	return ret;
++}
++
++static struct mtd_part_parser myloader_mtd_parser = {
++	.owner		= THIS_MODULE,
++	.parse_fn	= myloader_parse_partitions,
++	.name		= "MyLoader",
++};
++
++static int __init myloader_mtd_parser_init(void)
++{
++	register_mtd_parser(&myloader_mtd_parser);
++
++	return 0;
++}
++
++static void __exit myloader_mtd_parser_exit(void)
++{
++	deregister_mtd_parser(&myloader_mtd_parser);
++}
++
++module_init(myloader_mtd_parser_init);
++module_exit(myloader_mtd_parser_exit);
++
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_DESCRIPTION("Parsing code for MyLoader partition tables");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/generic/pending-6.6/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch b/target/linux/generic/pending-6.6/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch
new file mode 100644
index 00000000000000..bcea45d009bb11
--- /dev/null
+++ b/target/linux/generic/pending-6.6/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch
@@ -0,0 +1,68 @@
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Subject: [PATCH] mtd: bcm47xxpart: check for bad blocks when calculating offsets
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+
+--- a/drivers/mtd/parsers/parser_trx.c
++++ b/drivers/mtd/parsers/parser_trx.c
+@@ -25,6 +25,33 @@ struct trx_header {
+ 	uint32_t offset[3];
+ } __packed;
+ 
++/*
++ * Calculate real end offset (address) for a given amount of data. It checks
++ * all blocks skipping bad ones.
++ */
++static size_t parser_trx_real_offset(struct mtd_info *mtd, size_t bytes)
++{
++	size_t real_offset = 0;
++
++	if (mtd_block_isbad(mtd, real_offset))
++		pr_warn("Base offset shouldn't be at bad block");
++
++	while (bytes >= mtd->erasesize) {
++		bytes -= mtd->erasesize;
++		real_offset += mtd->erasesize;
++		while (mtd_block_isbad(mtd, real_offset)) {
++			real_offset += mtd->erasesize;
++
++			if (real_offset >= mtd->size)
++				return real_offset - mtd->erasesize;
++		}
++	}
++
++	real_offset += bytes;
++
++	return real_offset;
++}
++
+ static const char *parser_trx_data_part_name(struct mtd_info *master,
+ 					     size_t offset)
+ {
+@@ -86,21 +113,21 @@ static int parser_trx_parse(struct mtd_i
+ 	if (trx.offset[2]) {
+ 		part = &parts[curr_part++];
+ 		part->name = "loader";
+-		part->offset = trx.offset[i];
++		part->offset = parser_trx_real_offset(mtd, trx.offset[i]);
+ 		i++;
+ 	}
+ 
+ 	if (trx.offset[i]) {
+ 		part = &parts[curr_part++];
+ 		part->name = "linux";
+-		part->offset = trx.offset[i];
++		part->offset = parser_trx_real_offset(mtd, trx.offset[i]);
+ 		i++;
+ 	}
+ 
+ 	if (trx.offset[i]) {
+ 		part = &parts[curr_part++];
+-		part->name = parser_trx_data_part_name(mtd, trx.offset[i]);
+-		part->offset = trx.offset[i];
++		part->offset = parser_trx_real_offset(mtd, trx.offset[i]);
++		part->name = parser_trx_data_part_name(mtd, part->offset);
+ 		i++;
+ 	}
+ 
diff --git a/target/linux/generic/pending-6.6/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch b/target/linux/generic/pending-6.6/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch
new file mode 100644
index 00000000000000..852654d924a8ce
--- /dev/null
+++ b/target/linux/generic/pending-6.6/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch
@@ -0,0 +1,37 @@
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Subject: mtd: bcm47xxpart: detect T_Meter partition
+
+It can be found on many Netgear devices. It consists of many 0x30 blocks
+starting with 4D 54.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/mtd/bcm47xxpart.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/mtd/parsers/bcm47xxpart.c
++++ b/drivers/mtd/parsers/bcm47xxpart.c
+@@ -35,6 +35,7 @@
+ #define NVRAM_HEADER			0x48534C46	/* FLSH */
+ #define POT_MAGIC1			0x54544f50	/* POTT */
+ #define POT_MAGIC2			0x504f		/* OP */
++#define T_METER_MAGIC			0x4D540000	/* MT */
+ #define ML_MAGIC1			0x39685a42
+ #define ML_MAGIC2			0x26594131
+ #define TRX_MAGIC			0x30524448
+@@ -178,6 +179,15 @@ static int bcm47xxpart_parse(struct mtd_
+ 					     MTD_WRITEABLE);
+ 			continue;
+ 		}
++
++		/* T_Meter */
++		if ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC &&
++		    (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC &&
++		    (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) {
++			bcm47xxpart_add_part(&parts[curr_part++], "T_Meter", offset,
++					     MTD_WRITEABLE);
++			continue;
++		}
+ 
+ 		/* TRX */
+ 		if (buf[0x000 / 4] == TRX_MAGIC) {
diff --git a/target/linux/generic/pending-6.6/435-mtd-add-routerbootpart-parser-config.patch b/target/linux/generic/pending-6.6/435-mtd-add-routerbootpart-parser-config.patch
new file mode 100644
index 00000000000000..a42dcc868f7baf
--- /dev/null
+++ b/target/linux/generic/pending-6.6/435-mtd-add-routerbootpart-parser-config.patch
@@ -0,0 +1,38 @@
+From 4437e01fb6bca63fccdba5d6c44888b0935885c2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks@slashdirt.org>
+Date: Tue, 24 Mar 2020 11:45:07 +0100
+Subject: [PATCH] generic: routerboot partition build bits (5.4)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch adds routerbootpart kernel build bits
+
+Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
+---
+ drivers/mtd/parsers/Kconfig  | 9 +++++++++
+ drivers/mtd/parsers/Makefile | 1 +
+ 2 files changed, 10 insertions(+)
+
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -236,3 +236,12 @@ config MTD_SERCOMM_PARTS
+ 	  partition map. This partition table contains real partition
+ 	  offsets, which may differ from device to device depending on the
+ 	  number and location of bad blocks on NAND.
++
++config MTD_ROUTERBOOT_PARTS
++	tristate "RouterBoot flash partition parser"
++	depends on MTD && OF
++	help
++	 MikroTik RouterBoot is implemented as a multi segment system on the
++	 flash, some of which are fixed and some of which are located at
++	 variable offsets. This parser handles both cases via properly
++	 formatted DTS.
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -17,3 +17,4 @@ obj-$(CONFIG_MTD_SERCOMM_PARTS)		+= scpa
+ obj-$(CONFIG_MTD_SHARPSL_PARTS)		+= sharpslpart.o
+ obj-$(CONFIG_MTD_REDBOOT_PARTS)		+= redboot.o
+ obj-$(CONFIG_MTD_QCOMSMEM_PARTS)	+= qcomsmempart.o
++obj-$(CONFIG_MTD_ROUTERBOOT_PARTS)		+= routerbootpart.o
diff --git a/target/linux/generic/pending-6.6/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch b/target/linux/generic/pending-6.6/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch
new file mode 100644
index 00000000000000..2435133fa0b0e9
--- /dev/null
+++ b/target/linux/generic/pending-6.6/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch
@@ -0,0 +1,25 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: disable cfi cmdset 0002 erase suspend
+
+on some platforms, erase suspend leads to data corruption and lockups when write
+ops collide with erase ops. this has been observed on the buffalo wzr-hp-g300nh.
+rather than play whack-a-mole with a hard to reproduce issue on a variety of devices,
+simply disable erase suspend, as it will usually not produce any useful gain on
+the small filesystems used on embedded hardware.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -906,7 +906,7 @@ static int get_chip(struct map_info *map
+ 		return 0;
+ 
+ 	case FL_ERASING:
+-		if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
++		if (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
+ 		    !(mode == FL_READY || mode == FL_POINT ||
+ 		    (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
+ 			goto sleep;
diff --git a/target/linux/generic/pending-6.6/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch b/target/linux/generic/pending-6.6/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch
new file mode 100644
index 00000000000000..059d9673dcb80e
--- /dev/null
+++ b/target/linux/generic/pending-6.6/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch
@@ -0,0 +1,17 @@
+From: George Kashperko <george@znau.edu.ua>
+Subject: Issue map read after Write Buffer Load command to ensure chip is ready to receive data.
+
+Signed-off-by: George Kashperko <george@znau.edu.ua>
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c |    1 +
+ 1 file changed, 1 insertion(+)
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -2050,6 +2050,7 @@ static int __xipram do_write_buffer(stru
+ 
+ 	/* Write Buffer Load */
+ 	map_write(map, CMD(0x25), cmd_adr);
++	(void) map_read(map, cmd_adr);
+ 
+ 	chip->state = FL_WRITING_TO_BUFFER;
+ 
diff --git a/target/linux/generic/pending-6.6/465-m25p80-mx-disable-software-protection.patch b/target/linux/generic/pending-6.6/465-m25p80-mx-disable-software-protection.patch
new file mode 100644
index 00000000000000..f2de209c26fbbf
--- /dev/null
+++ b/target/linux/generic/pending-6.6/465-m25p80-mx-disable-software-protection.patch
@@ -0,0 +1,18 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: Disable software protection bits for Macronix flashes.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/spi-nor/macronix.c
++++ b/drivers/mtd/spi-nor/macronix.c
+@@ -114,6 +114,7 @@ static int macronix_nor_late_init(struct
+ {
+ 	if (!nor->params->set_4byte_addr_mode)
+ 		nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
++		nor->flags |= SNOR_F_HAS_LOCK;
+ 
+ 	return 0;
+ }
diff --git a/target/linux/generic/pending-6.6/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/pending-6.6/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
new file mode 100644
index 00000000000000..4a091f9cabfae4
--- /dev/null
+++ b/target/linux/generic/pending-6.6/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
@@ -0,0 +1,97 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Subject: ubi: auto-attach mtd device named "ubi" or "data" on boot
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -1214,6 +1214,73 @@ static struct mtd_info * __init open_mtd
+ 	return mtd;
+ }
+ 
++/*
++ * This function tries attaching mtd partitions named either "ubi" or "data"
++ * during boot.
++ */
++static void __init ubi_auto_attach(void)
++{
++	int err;
++	struct mtd_info *mtd;
++	loff_t offset = 0;
++	size_t len;
++	char magic[4];
++
++	/* try attaching mtd device named "ubi" or "data" */
++	mtd = open_mtd_device("ubi");
++	if (IS_ERR(mtd))
++		mtd = open_mtd_device("data");
++
++	if (IS_ERR(mtd))
++		return;
++
++	/* get the first not bad block */
++	if (mtd_can_have_bb(mtd))
++		while (mtd_block_isbad(mtd, offset)) {
++			offset += mtd->erasesize;
++
++			if (offset > mtd->size) {
++				pr_err("UBI error: Failed to find a non-bad "
++				       "block on mtd%d\n", mtd->index);
++				goto cleanup;
++			}
++		}
++
++	/* check if the read from flash was successful */
++	err = mtd_read(mtd, offset, 4, &len, (void *) magic);
++	if ((err && !mtd_is_bitflip(err)) || len != 4) {
++		pr_err("UBI error: unable to read from mtd%d\n", mtd->index);
++		goto cleanup;
++	}
++
++	/* check for a valid ubi magic */
++	if (strncmp(magic, "UBI#", 4)) {
++		pr_err("UBI error: no valid UBI magic found inside mtd%d\n", mtd->index);
++		goto cleanup;
++	}
++
++	/* don't auto-add media types where UBI doesn't makes sense */
++	if (mtd->type != MTD_NANDFLASH &&
++	    mtd->type != MTD_NORFLASH &&
++	    mtd->type != MTD_DATAFLASH &&
++	    mtd->type != MTD_MLCNANDFLASH)
++		goto cleanup;
++
++	mutex_lock(&ubi_devices_mutex);
++	pr_notice("UBI: auto-attach mtd%d\n", mtd->index);
++	err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0);
++	mutex_unlock(&ubi_devices_mutex);
++	if (err < 0) {
++		pr_err("UBI error: cannot attach mtd%d\n", mtd->index);
++		goto cleanup;
++	}
++
++	return;
++
++cleanup:
++	put_mtd_device(mtd);
++}
++
+ static int __init ubi_init(void)
+ {
+ 	int err, i, k;
+@@ -1298,6 +1365,12 @@ static int __init ubi_init(void)
+ 		}
+ 	}
+ 
++	/* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd
++	 * parameter was given */
++	if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&
++	    !ubi_is_module() && !mtd_devs)
++		ubi_auto_attach();
++
+ 	err = ubiblock_init();
+ 	if (err) {
+ 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
diff --git a/target/linux/generic/pending-6.6/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/pending-6.6/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
new file mode 100644
index 00000000000000..9ea2570beffc25
--- /dev/null
+++ b/target/linux/generic/pending-6.6/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
@@ -0,0 +1,69 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Subject: ubi: auto-create ubiblock device for rootfs
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -618,6 +618,47 @@ static void __init ubiblock_create_from_
+ 	}
+ }
+ 
++#define UBIFS_NODE_MAGIC  0x06101831
++static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc)
++{
++	int ret;
++	uint32_t magic_of, magic;
++	ret = ubi_read(desc, 0, (char *)&magic_of, 0, 4);
++	if (ret)
++		return 0;
++	magic = le32_to_cpu(magic_of);
++	return magic == UBIFS_NODE_MAGIC;
++}
++
++static void __init ubiblock_create_auto_rootfs(void)
++{
++	int ubi_num, ret, is_ubifs;
++	struct ubi_volume_desc *desc;
++	struct ubi_volume_info vi;
++
++	for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) {
++		desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY);
++		if (IS_ERR(desc))
++			desc = ubi_open_volume_nm(ubi_num, "fit", UBI_READONLY);;
++
++		if (IS_ERR(desc))
++			continue;
++
++		ubi_get_volume_info(desc, &vi);
++		is_ubifs = ubi_vol_is_ubifs(desc);
++		ubi_close_volume(desc);
++		if (is_ubifs)
++			break;
++
++		ret = ubiblock_create(&vi);
++		if (ret)
++			pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
++				vi.name, ret);
++		/* always break if we get here */
++		break;
++	}
++}
++
+ static void ubiblock_remove_all(void)
+ {
+ 	struct ubiblock *next;
+@@ -650,6 +691,10 @@ int __init ubiblock_init(void)
+ 	 */
+ 	ubiblock_create_from_param();
+ 
++	/* auto-attach "rootfs" volume if existing and non-ubifs */
++	if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
++		ubiblock_create_auto_rootfs();
++
+ 	/*
+ 	 * Block devices are only created upon user requests, so we ignore
+ 	 * existing volumes.
diff --git a/target/linux/generic/pending-6.6/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/pending-6.6/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
new file mode 100644
index 00000000000000..367bf6598e2a99
--- /dev/null
+++ b/target/linux/generic/pending-6.6/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
@@ -0,0 +1,34 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Subject: ubi: set ROOT_DEV to ubiblock "rootfs" if unset
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -41,6 +41,7 @@
+ #include <linux/scatterlist.h>
+ #include <linux/idr.h>
+ #include <asm/div64.h>
++#include <linux/root_dev.h>
+ 
+ #include "ubi-media.h"
+ #include "ubi.h"
+@@ -428,6 +429,15 @@ int ubiblock_create(struct ubi_volume_in
+ 	dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)",
+ 		 dev->ubi_num, dev->vol_id, vi->name);
+ 	mutex_unlock(&devices_mutex);
++
++	if (!strcmp(vi->name, "rootfs") &&
++	    IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&
++	    ROOT_DEV == 0) {
++		pr_notice("ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\n",
++			  dev->ubi_num, dev->vol_id, vi->name);
++		ROOT_DEV = MKDEV(gd->major, gd->first_minor);
++	}
++
+ 	return 0;
+ 
+ out_remove_minor:
diff --git a/target/linux/generic/pending-6.6/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/pending-6.6/494-mtd-ubi-add-EOF-marker-support.patch
new file mode 100644
index 00000000000000..413431755f1d2c
--- /dev/null
+++ b/target/linux/generic/pending-6.6/494-mtd-ubi-add-EOF-marker-support.patch
@@ -0,0 +1,60 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: mtd: add EOF marker support to the UBI layer
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/mtd/ubi/attach.c | 25 ++++++++++++++++++++++---
+ drivers/mtd/ubi/ubi.h    |  1 +
+ 2 files changed, 23 insertions(+), 3 deletions(-)
+
+--- a/drivers/mtd/ubi/attach.c
++++ b/drivers/mtd/ubi/attach.c
+@@ -926,6 +926,13 @@ static bool vol_ignored(int vol_id)
+ #endif
+ }
+ 
++static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech)
++{
++	return ech->padding1[0] == 'E' &&
++	       ech->padding1[1] == 'O' &&
++	       ech->padding1[2] == 'F';
++}
++
+ /**
+  * scan_peb - scan and process UBI headers of a PEB.
+  * @ubi: UBI device description object
+@@ -958,9 +965,21 @@ static int scan_peb(struct ubi_device *u
+ 		return 0;
+ 	}
+ 
+-	err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+-	if (err < 0)
+-		return err;
++	if (!ai->eof_found) {
++		err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
++		if (err < 0)
++			return err;
++
++		if (ec_hdr_has_eof(ech)) {
++			pr_notice("UBI: EOF marker found, PEBs from %d will be erased\n",
++				pnum);
++			ai->eof_found = true;
++		}
++	}
++
++	if (ai->eof_found)
++		err = UBI_IO_FF_BITFLIPS;
++
+ 	switch (err) {
+ 	case 0:
+ 		break;
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -778,6 +778,7 @@ struct ubi_attach_info {
+ 	int mean_ec;
+ 	uint64_t ec_sum;
+ 	int ec_count;
++	bool eof_found;
+ 	struct kmem_cache *aeb_slab_cache;
+ 	struct ubi_ec_hdr *ech;
+ 	struct ubi_vid_io_buf *vidb;
diff --git a/target/linux/generic/pending-6.6/495-mtd-core-add-get_mtd_device_by_node.patch b/target/linux/generic/pending-6.6/495-mtd-core-add-get_mtd_device_by_node.patch
new file mode 100644
index 00000000000000..a5dab88e82fd9c
--- /dev/null
+++ b/target/linux/generic/pending-6.6/495-mtd-core-add-get_mtd_device_by_node.patch
@@ -0,0 +1,75 @@
+From 1bd1b740f208d1cf4071932cc51860d37266c402 Mon Sep 17 00:00:00 2001
+From: Bernhard Frauendienst <kernel@nospam.obeliks.de>
+Date: Sat, 1 Sep 2018 00:30:11 +0200
+Subject: [PATCH 495/497] mtd: core: add get_mtd_device_by_node
+
+Add function to retrieve a mtd device by its OF node. Since drivers can
+assign arbitrary names to mtd devices in the absence of a label
+property, there is no other reliable way to retrieve a mtd device for a
+given OF node.
+
+Signed-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+---
+ drivers/mtd/mtdcore.c   | 38 ++++++++++++++++++++++++++++++++++++++
+ include/linux/mtd/mtd.h |  2 ++
+ 2 files changed, 40 insertions(+)
+
+--- a/drivers/mtd/mtdcore.c
++++ b/drivers/mtd/mtdcore.c
+@@ -1326,6 +1326,44 @@ out_unlock:
+ }
+ EXPORT_SYMBOL_GPL(get_mtd_device_nm);
+ 
++/**
++ *	get_mtd_device_by_node - obtain a validated handle for an MTD device
++ *	by of_node
++ *	@of_node: OF node of MTD device to open
++ *
++ *	This function returns MTD device description structure in case of
++ *	success and an error code in case of failure.
++ */
++struct mtd_info *get_mtd_device_by_node(const struct device_node *of_node)
++{
++	int err = -ENODEV;
++	struct mtd_info *mtd = NULL, *other;
++
++	mutex_lock(&mtd_table_mutex);
++
++	mtd_for_each_device(other) {
++		if (of_node == other->dev.of_node) {
++			mtd = other;
++			break;
++		}
++	}
++
++	if (!mtd)
++		goto out_unlock;
++
++	err = __get_mtd_device(mtd);
++	if (err)
++		goto out_unlock;
++
++	mutex_unlock(&mtd_table_mutex);
++	return mtd;
++
++out_unlock:
++	mutex_unlock(&mtd_table_mutex);
++	return ERR_PTR(err);
++}
++EXPORT_SYMBOL_GPL(get_mtd_device_by_node);
++
+ void put_mtd_device(struct mtd_info *mtd)
+ {
+ 	mutex_lock(&mtd_table_mutex);
+--- a/include/linux/mtd/mtd.h
++++ b/include/linux/mtd/mtd.h
+@@ -706,6 +706,8 @@ extern int __get_mtd_device(struct mtd_i
+ extern void __put_mtd_device(struct mtd_info *mtd);
+ extern struct mtd_info *of_get_mtd_device_by_node(struct device_node *np);
+ extern struct mtd_info *get_mtd_device_nm(const char *name);
++extern struct mtd_info *get_mtd_device_by_node(
++		const struct device_node *of_node);
+ extern void put_mtd_device(struct mtd_info *mtd);
+ 
+ static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd)
diff --git a/target/linux/generic/pending-6.6/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch b/target/linux/generic/pending-6.6/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch
new file mode 100644
index 00000000000000..01f3b9ec2da0ce
--- /dev/null
+++ b/target/linux/generic/pending-6.6/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch
@@ -0,0 +1,52 @@
+From 5734c6669fba7ddb5ef491ccff7159d15dba0b59 Mon Sep 17 00:00:00 2001
+From: Bernhard Frauendienst <kernel@nospam.obeliks.de>
+Date: Wed, 5 Sep 2018 01:32:51 +0200
+Subject: [PATCH 496/497] dt-bindings: add bindings for mtd-concat devices
+
+Document virtual mtd-concat device bindings.
+
+Signed-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>
+---
+ .../devicetree/bindings/mtd/mtd-concat.txt    | 36 +++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/mtd-concat.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/mtd-concat.txt
+@@ -0,0 +1,36 @@
++Virtual MTD concat device
++
++Requires properties:
++- devices: list of phandles to mtd nodes that should be concatenated
++
++Example:
++
++&spi {
++	flash0: flash@0 {
++		...
++	};
++	flash1: flash@1 {
++		...
++	};
++};
++
++flash {
++	compatible = "mtd-concat";
++
++	devices = <&flash0 &flash1>;
++
++	partitions {
++		compatible = "fixed-partitions";
++
++		partition@0 {
++			label = "boot";
++			reg = <0x0000000 0x0040000>;
++			read-only;
++		};
++
++		partition@40000 {
++			label = "firmware";
++			reg = <0x0040000 0x1fc0000>;
++		};
++	}
++}
diff --git a/target/linux/generic/pending-6.6/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch b/target/linux/generic/pending-6.6/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch
new file mode 100644
index 00000000000000..321680154d5716
--- /dev/null
+++ b/target/linux/generic/pending-6.6/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch
@@ -0,0 +1,216 @@
+From e53f712d8eac71f54399b61038ccf87d2cee99d7 Mon Sep 17 00:00:00 2001
+From: Bernhard Frauendienst <kernel@nospam.obeliks.de>
+Date: Sat, 25 Aug 2018 12:35:22 +0200
+Subject: [PATCH 497/497] mtd: mtdconcat: add dt driver for concat devices
+
+Some mtd drivers like physmap variants have support for concatenating
+multiple mtd devices, but there is no generic way to define such a
+concat device from within the device tree.
+
+This is useful for some SoC boards that use multiple flash chips as
+memory banks of a single mtd device, with partitions spanning chip
+borders.
+
+This commit adds a driver for creating virtual mtd-concat devices. They
+must have a compatible = "mtd-concat" line, and define a list of devices
+to concat in the 'devices' property, for example:
+
+flash {
+  compatible = "mtd-concat";
+
+  devices = <&flash0 &flash1>;
+
+  partitions {
+    ...
+  };
+};
+
+The driver is added to the very end of the mtd Makefile to increase the
+likelyhood of all child devices already being loaded at the time of
+probing, preventing unnecessary deferred probes.
+
+Signed-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>
+---
+ drivers/mtd/Kconfig                 |   2 +
+ drivers/mtd/Makefile                |   3 +
+ drivers/mtd/composite/Kconfig       |  12 +++
+ drivers/mtd/composite/Makefile      |   6 ++
+ drivers/mtd/composite/virt_concat.c | 128 ++++++++++++++++++++++++++++
+ 5 files changed, 151 insertions(+)
+ create mode 100644 drivers/mtd/composite/Kconfig
+ create mode 100644 drivers/mtd/composite/Makefile
+ create mode 100644 drivers/mtd/composite/virt_concat.c
+
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -241,4 +241,6 @@ source "drivers/mtd/ubi/Kconfig"
+ 
+ source "drivers/mtd/hyperbus/Kconfig"
+ 
++source "drivers/mtd/composite/Kconfig"
++
+ endif # MTD
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -33,3 +33,6 @@ obj-y		+= chips/ lpddr/ maps/ devices/ n
+ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor/
+ obj-$(CONFIG_MTD_UBI)		+= ubi/
+ obj-$(CONFIG_MTD_HYPERBUS)	+= hyperbus/
++
++# Composite drivers must be loaded last
++obj-y				+= composite/
+--- /dev/null
++++ b/drivers/mtd/composite/Kconfig
+@@ -0,0 +1,12 @@
++menu "Composite MTD device drivers"
++	depends on MTD!=n
++
++config MTD_VIRT_CONCAT
++	tristate "Virtual concat MTD device"
++	help
++	  This driver allows creation of a virtual MTD concat device, which
++	  concatenates multiple underlying MTD devices to a single device.
++	  This is required by some SoC boards where multiple memory banks are
++	  used as one device with partitions spanning across device boundaries.
++
++endmenu
+--- /dev/null
++++ b/drivers/mtd/composite/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# linux/drivers/mtd/composite/Makefile
++#
++
++obj-$(CONFIG_MTD_VIRT_CONCAT)   += virt_concat.o
+--- /dev/null
++++ b/drivers/mtd/composite/virt_concat.c
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Virtual concat MTD device driver
++ *
++ * Copyright (C) 2018 Bernhard Frauendienst
++ * Author: Bernhard Frauendienst, kernel@nospam.obeliks.de
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/mtd/concat.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/slab.h>
++
++/*
++ * struct of_virt_concat - platform device driver data.
++ * @cmtd the final mtd_concat device
++ * @num_devices the number of devices in @devices
++ * @devices points to an array of devices already loaded
++ */
++struct of_virt_concat {
++	struct mtd_info	*cmtd;
++	int num_devices;
++	struct mtd_info	**devices;
++};
++
++static int virt_concat_remove(struct platform_device *pdev)
++{
++	struct of_virt_concat *info;
++	int i;
++
++	info = platform_get_drvdata(pdev);
++	if (!info)
++		return 0;
++
++	// unset data for when this is called after a probe error
++	platform_set_drvdata(pdev, NULL);
++
++	if (info->cmtd) {
++		mtd_device_unregister(info->cmtd);
++		mtd_concat_destroy(info->cmtd);
++	}
++
++	if (info->devices) {
++		for (i = 0; i < info->num_devices; i++)
++			put_mtd_device(info->devices[i]);
++	}
++
++	return 0;
++}
++
++static int virt_concat_probe(struct platform_device *pdev)
++{
++	struct device_node *node = pdev->dev.of_node;
++	struct of_phandle_iterator it;
++	struct of_virt_concat *info;
++	struct mtd_info *mtd;
++	int err = 0, count;
++
++	count = of_count_phandle_with_args(node, "devices", NULL);
++	if (count <= 0)
++		return -EINVAL;
++
++	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
++	if (!info)
++		return -ENOMEM;
++	info->devices = devm_kcalloc(&pdev->dev, count,
++				     sizeof(*(info->devices)), GFP_KERNEL);
++	if (!info->devices) {
++		err = -ENOMEM;
++		goto err_remove;
++	}
++
++	platform_set_drvdata(pdev, info);
++
++	of_for_each_phandle(&it, err, node, "devices", NULL, 0) {
++		mtd = get_mtd_device_by_node(it.node);
++		if (IS_ERR(mtd)) {
++			of_node_put(it.node);
++			err = -EPROBE_DEFER;
++			goto err_remove;
++		}
++
++		info->devices[info->num_devices++] = mtd;
++	}
++
++	info->cmtd = mtd_concat_create(info->devices, info->num_devices,
++				       dev_name(&pdev->dev));
++	if (!info->cmtd) {
++		err = -ENXIO;
++		goto err_remove;
++	}
++
++	info->cmtd->dev.parent = &pdev->dev;
++	mtd_set_of_node(info->cmtd, node);
++	mtd_device_register(info->cmtd, NULL, 0);
++
++	return 0;
++
++err_remove:
++	virt_concat_remove(pdev);
++
++	return err;
++}
++
++static const struct of_device_id virt_concat_of_match[] = {
++	{ .compatible = "mtd-concat", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, virt_concat_of_match);
++
++static struct platform_driver virt_concat_driver = {
++	.probe = virt_concat_probe,
++	.remove = virt_concat_remove,
++	.driver	 = {
++		.name   = "virt-mtdconcat",
++		.of_match_table = virt_concat_of_match,
++	},
++};
++
++module_platform_driver(virt_concat_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Bernhard Frauendienst <kernel@nospam.obeliks.de>");
++MODULE_DESCRIPTION("Virtual concat MTD device driver");
diff --git a/target/linux/generic/pending-6.6/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch b/target/linux/generic/pending-6.6/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch
new file mode 100644
index 00000000000000..dd35a74a85e098
--- /dev/null
+++ b/target/linux/generic/pending-6.6/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch
@@ -0,0 +1,30 @@
+From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001
+From: Nick Hainke <vincent@systemli.org>
+Date: Mon, 27 Dec 2021 09:33:13 +0100
+Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
+
+Macronix flash chips seem to consist of only one status register.
+These chips will not work with the "16-bit Write Status (01h) Command".
+Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
+
+Tested with MX25L6405D.
+
+Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
+lock()/unlock()")
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Nick Hainke <vincent@systemli.org>
+---
+ drivers/mtd/spi-nor/macronix.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/spi-nor/macronix.c
++++ b/drivers/mtd/spi-nor/macronix.c
+@@ -114,6 +114,7 @@ static int macronix_nor_late_init(struct
+ {
+ 	if (!nor->params->set_4byte_addr_mode)
+ 		nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
++		nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+ 		nor->flags |= SNOR_F_HAS_LOCK;
+ 
+ 	return 0;
diff --git a/target/linux/generic/pending-6.6/500-fs_cdrom_dependencies.patch b/target/linux/generic/pending-6.6/500-fs_cdrom_dependencies.patch
new file mode 100644
index 00000000000000..7c143584a4fb7a
--- /dev/null
+++ b/target/linux/generic/pending-6.6/500-fs_cdrom_dependencies.patch
@@ -0,0 +1,52 @@
+From af7b91bcecce0eae24e90acd35d96ecee73e1407 Mon Sep 17 00:00:00 2001
+From: OpenWrt community <openwrt-devel@lists.openwrt.org>
+Date: Wed, 13 Jul 2022 12:21:15 +0200
+Subject: [PATCH] fs: add cdrom dependency
+
+---
+ fs/hfs/Kconfig     | 1 +
+ fs/hfsplus/Kconfig | 1 +
+ fs/isofs/Kconfig   | 1 +
+ fs/udf/Kconfig     | 1 +
+ 4 files changed, 4 insertions(+)
+
+--- a/fs/hfs/Kconfig
++++ b/fs/hfs/Kconfig
+@@ -2,6 +2,7 @@
+ config HFS_FS
+ 	tristate "Apple Macintosh file system support"
+ 	depends on BLOCK
++	select CDROM
+ 	select BUFFER_HEAD
+ 	select NLS
+ 	select LEGACY_DIRECT_IO
+--- a/fs/hfsplus/Kconfig
++++ b/fs/hfsplus/Kconfig
+@@ -2,6 +2,7 @@
+ config HFSPLUS_FS
+ 	tristate "Apple Extended HFS file system support"
+ 	depends on BLOCK
++	select CDROM
+ 	select BUFFER_HEAD
+ 	select NLS
+ 	select NLS_UTF8
+--- a/fs/isofs/Kconfig
++++ b/fs/isofs/Kconfig
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ config ISO9660_FS
+ 	tristate "ISO 9660 CDROM file system support"
++	select CDROM
+ 	select BUFFER_HEAD
+ 	help
+ 	  This is the standard file system used on CD-ROMs.  It was previously
+--- a/fs/udf/Kconfig
++++ b/fs/udf/Kconfig
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ config UDF_FS
+ 	tristate "UDF file system support"
++	select CDROM
+ 	select BUFFER_HEAD
+ 	select CRC_ITU_T
+ 	select NLS
diff --git a/target/linux/generic/pending-6.6/530-jffs2_make_lzma_available.patch b/target/linux/generic/pending-6.6/530-jffs2_make_lzma_available.patch
new file mode 100644
index 00000000000000..12052de759b14f
--- /dev/null
+++ b/target/linux/generic/pending-6.6/530-jffs2_make_lzma_available.patch
@@ -0,0 +1,5180 @@
+From: Alexandros C. Couloumbis <alex@ozo.com>
+Subject: fs: add jffs2/lzma support (not activated by default yet)
+
+lede-commit: c2c88d315fa0e881f8b19da07b62859b915b11b2
+Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
+---
+ fs/jffs2/Kconfig             |    9 +
+ fs/jffs2/Makefile            |    3 +
+ fs/jffs2/compr.c             |    6 +
+ fs/jffs2/compr.h             |   10 +-
+ fs/jffs2/compr_lzma.c        |  128 +++
+ fs/jffs2/super.c             |   33 +-
+ include/linux/lzma.h         |   62 ++
+ include/linux/lzma/LzFind.h  |  115 +++
+ include/linux/lzma/LzHash.h  |   54 +
+ include/linux/lzma/LzmaDec.h |  231 +++++
+ include/linux/lzma/LzmaEnc.h |   80 ++
+ include/linux/lzma/Types.h   |  226 +++++
+ include/uapi/linux/jffs2.h   |    1 +
+ lib/Kconfig                  |    6 +
+ lib/Makefile                 |   12 +
+ lib/lzma/LzFind.c            |  761 ++++++++++++++
+ lib/lzma/LzmaDec.c           |  999 +++++++++++++++++++
+ lib/lzma/LzmaEnc.c           | 2271 ++++++++++++++++++++++++++++++++++++++++++
+ lib/lzma/Makefile            |    7 +
+ 19 files changed, 5008 insertions(+), 6 deletions(-)
+ create mode 100644 fs/jffs2/compr_lzma.c
+ create mode 100644 include/linux/lzma.h
+ create mode 100644 include/linux/lzma/LzFind.h
+ create mode 100644 include/linux/lzma/LzHash.h
+ create mode 100644 include/linux/lzma/LzmaDec.h
+ create mode 100644 include/linux/lzma/LzmaEnc.h
+ create mode 100644 include/linux/lzma/Types.h
+ create mode 100644 lib/lzma/LzFind.c
+ create mode 100644 lib/lzma/LzmaDec.c
+ create mode 100644 lib/lzma/LzmaEnc.c
+ create mode 100644 lib/lzma/Makefile
+
+--- a/fs/jffs2/Kconfig
++++ b/fs/jffs2/Kconfig
+@@ -136,6 +136,15 @@ config JFFS2_LZO
+ 	  This feature was added in July, 2007. Say 'N' if you need
+ 	  compatibility with older bootloaders or kernels.
+ 
++config JFFS2_LZMA
++	bool "JFFS2 LZMA compression support" if JFFS2_COMPRESSION_OPTIONS
++	select LZMA_COMPRESS
++	select LZMA_DECOMPRESS
++	depends on JFFS2_FS
++	default n
++	help
++	  JFFS2 wrapper to the LZMA C SDK
++
+ config JFFS2_RTIME
+ 	bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS
+ 	depends on JFFS2_FS
+--- a/fs/jffs2/Makefile
++++ b/fs/jffs2/Makefile
+@@ -19,4 +19,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN)	+= compr_rub
+ jffs2-$(CONFIG_JFFS2_RTIME)	+= compr_rtime.o
+ jffs2-$(CONFIG_JFFS2_ZLIB)	+= compr_zlib.o
+ jffs2-$(CONFIG_JFFS2_LZO)	+= compr_lzo.o
++jffs2-$(CONFIG_JFFS2_LZMA)	+= compr_lzma.o
+ jffs2-$(CONFIG_JFFS2_SUMMARY)   += summary.o
++
++CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma
+--- a/fs/jffs2/compr.c
++++ b/fs/jffs2/compr.c
+@@ -382,6 +382,9 @@ int __init jffs2_compressors_init(void)
+ 	if (ret)
+ 		goto exit_dynrubin;
+ 
++#ifdef CONFIG_JFFS2_LZMA
++	jffs2_lzma_init();
++#endif
+ 
+ /* Setting default compression mode */
+ #ifdef CONFIG_JFFS2_CMODE_NONE
+@@ -417,6 +420,9 @@ exit:
+ int jffs2_compressors_exit(void)
+ {
+ /* Unregistering compressors */
++#ifdef CONFIG_JFFS2_LZMA
++	jffs2_lzma_exit();
++#endif
+ 	jffs2_lzo_exit();
+ 	jffs2_dynrubin_exit();
+ 	jffs2_rubinmips_exit();
+--- a/fs/jffs2/compr.h
++++ b/fs/jffs2/compr.h
+@@ -29,9 +29,9 @@
+ #define JFFS2_DYNRUBIN_PRIORITY  20
+ #define JFFS2_LZARI_PRIORITY     30
+ #define JFFS2_RTIME_PRIORITY     50
+-#define JFFS2_ZLIB_PRIORITY      60
+-#define JFFS2_LZO_PRIORITY       80
+-
++#define JFFS2_LZMA_PRIORITY      70
++#define JFFS2_ZLIB_PRIORITY      80
++#define JFFS2_LZO_PRIORITY       90
+ 
+ #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */
+ #define JFFS2_DYNRUBIN_DISABLED  /*	   for decompression */
+@@ -116,4 +116,9 @@ static inline int jffs2_lzo_init(void) {
+ static inline void jffs2_lzo_exit(void) {}
+ #endif
+ 
++#ifdef CONFIG_JFFS2_LZMA
++int jffs2_lzma_init(void);
++void jffs2_lzma_exit(void);
++#endif
++
+ #endif /* __JFFS2_COMPR_H__ */
+--- /dev/null
++++ b/fs/jffs2/compr_lzma.c
+@@ -0,0 +1,128 @@
++/*
++ * JFFS2 -- Journalling Flash File System, Version 2.
++ *
++ * For licensing information, see the file 'LICENCE' in this directory.
++ *
++ * JFFS2 wrapper to the LZMA C SDK
++ *
++ */
++
++#include <linux/lzma.h>
++#include "compr.h"
++
++#ifdef __KERNEL__
++	static DEFINE_MUTEX(deflate_mutex);
++#endif
++
++CLzmaEncHandle *p;
++Byte propsEncoded[LZMA_PROPS_SIZE];
++SizeT propsSize = sizeof(propsEncoded);
++
++STATIC void lzma_free_workspace(void)
++{
++	LzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc);
++}
++
++STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props)
++{
++	if ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL)
++	{
++		PRINT_ERROR("Failed to allocate lzma deflate workspace\n");
++		return -ENOMEM;
++	}
++
++	if (LzmaEnc_SetProps(p, props) != SZ_OK)
++	{
++		lzma_free_workspace();
++		return -1;
++	}
++
++	if (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK)
++	{
++		lzma_free_workspace();
++		return -1;
++	}
++
++	return 0;
++}
++
++STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out,
++			      uint32_t *sourcelen, uint32_t *dstlen)
++{
++	SizeT compress_size = (SizeT)(*dstlen);
++	int ret;
++
++	#ifdef __KERNEL__
++		mutex_lock(&deflate_mutex);
++	#endif
++
++	ret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen,
++		0, NULL, &lzma_alloc, &lzma_alloc);
++
++	#ifdef __KERNEL__
++		mutex_unlock(&deflate_mutex);
++	#endif
++
++	if (ret != SZ_OK)
++		return -1;
++
++	*dstlen = (uint32_t)compress_size;
++
++	return 0;
++}
++
++STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out,
++				 uint32_t srclen, uint32_t destlen)
++{
++	int ret;
++	SizeT dl = (SizeT)destlen;
++	SizeT sl = (SizeT)srclen;
++	ELzmaStatus status;
++
++	ret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded,
++		propsSize, LZMA_FINISH_ANY, &status, &lzma_alloc);
++
++	if (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen)
++		return -1;
++
++	return 0;
++}
++
++static struct jffs2_compressor jffs2_lzma_comp = {
++	.priority = JFFS2_LZMA_PRIORITY,
++	.name = "lzma",
++	.compr = JFFS2_COMPR_LZMA,
++	.compress = &jffs2_lzma_compress,
++	.decompress = &jffs2_lzma_decompress,
++	.disabled = 0,
++};
++
++int INIT jffs2_lzma_init(void)
++{
++	int ret;
++	CLzmaEncProps props;
++	LzmaEncProps_Init(&props);
++
++	props.dictSize = LZMA_BEST_DICT(0x2000);
++	props.level = LZMA_BEST_LEVEL;
++	props.lc = LZMA_BEST_LC;
++	props.lp = LZMA_BEST_LP;
++	props.pb = LZMA_BEST_PB;
++	props.fb = LZMA_BEST_FB;
++
++	ret = lzma_alloc_workspace(&props);
++	if (ret < 0)
++		return ret;
++
++	ret = jffs2_register_compressor(&jffs2_lzma_comp);
++	if (ret)
++		lzma_free_workspace();
++
++	return ret;
++}
++
++void jffs2_lzma_exit(void)
++{
++	jffs2_unregister_compressor(&jffs2_lzma_comp);
++	lzma_free_workspace();
++}
+--- a/fs/jffs2/super.c
++++ b/fs/jffs2/super.c
+@@ -374,14 +374,41 @@ static int __init init_jffs2_fs(void)
+ 	BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68);
+ 	BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32);
+ 
+-	pr_info("version 2.2."
++	pr_info("version 2.2"
+ #ifdef CONFIG_JFFS2_FS_WRITEBUFFER
+ 	       " (NAND)"
+ #endif
+ #ifdef CONFIG_JFFS2_SUMMARY
+-	       " (SUMMARY) "
++	       " (SUMMARY)"
+ #endif
+-	       " © 2001-2006 Red Hat, Inc.\n");
++#ifdef CONFIG_JFFS2_ZLIB
++	       " (ZLIB)"
++#endif
++#ifdef CONFIG_JFFS2_LZO
++	       " (LZO)"
++#endif
++#ifdef CONFIG_JFFS2_LZMA
++	       " (LZMA)"
++#endif
++#ifdef CONFIG_JFFS2_RTIME
++	       " (RTIME)"
++#endif
++#ifdef CONFIG_JFFS2_RUBIN
++	       " (RUBIN)"
++#endif
++#ifdef  CONFIG_JFFS2_CMODE_NONE
++	       " (CMODE_NONE)"
++#endif
++#ifdef CONFIG_JFFS2_CMODE_PRIORITY
++	       " (CMODE_PRIORITY)"
++#endif
++#ifdef CONFIG_JFFS2_CMODE_SIZE
++	       " (CMODE_SIZE)"
++#endif
++#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO
++	       " (CMODE_FAVOURLZO)"
++#endif
++	       " (c) 2001-2006 Red Hat, Inc.\n");
+ 
+ 	jffs2_inode_cachep = kmem_cache_create("jffs2_i",
+ 					     sizeof(struct jffs2_inode_info),
+--- /dev/null
++++ b/include/linux/lzma.h
+@@ -0,0 +1,62 @@
++#ifndef __LZMA_H__
++#define __LZMA_H__
++
++#ifdef __KERNEL__
++	#include <linux/kernel.h>
++	#include <linux/sched.h>
++	#include <linux/slab.h>
++	#include <linux/vmalloc.h>
++	#include <linux/init.h>
++	#define LZMA_MALLOC vmalloc
++	#define LZMA_FREE vfree
++	#define PRINT_ERROR(msg) printk(KERN_WARNING #msg)
++	#define INIT __init
++	#define STATIC static
++#else
++	#include <stdint.h>
++	#include <stdlib.h>
++	#include <stdio.h>
++	#include <unistd.h>
++	#include <string.h>
++	#include <asm/types.h>
++	#include <errno.h>
++	#include <linux/jffs2.h>
++	#ifndef PAGE_SIZE
++		extern int page_size;
++		#define PAGE_SIZE page_size
++	#endif
++	#define LZMA_MALLOC malloc
++	#define LZMA_FREE free
++	#define PRINT_ERROR(msg) fprintf(stderr, msg)
++	#define INIT
++	#define STATIC
++#endif
++
++#include "lzma/LzmaDec.h"
++#include "lzma/LzmaEnc.h"
++
++#define LZMA_BEST_LEVEL (9)
++#define LZMA_BEST_LC    (0)
++#define LZMA_BEST_LP    (0)
++#define LZMA_BEST_PB    (0)
++#define LZMA_BEST_FB  (273)
++
++#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2)
++
++static void *p_lzma_malloc(void *p, size_t size)
++{
++	if (size == 0)
++		return NULL;
++
++	return LZMA_MALLOC(size);
++}
++
++static void p_lzma_free(void *p, void *address)
++{
++	if (address != NULL)
++		LZMA_FREE(address);
++}
++
++static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free};
++
++#endif
+--- /dev/null
++++ b/include/linux/lzma/LzFind.h
+@@ -0,0 +1,115 @@
++/* LzFind.h -- Match finder for LZ algorithms
++2009-04-22 : Igor Pavlov : Public domain */
++
++#ifndef __LZ_FIND_H
++#define __LZ_FIND_H
++
++#include "Types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++typedef UInt32 CLzRef;
++
++typedef struct _CMatchFinder
++{
++  Byte *buffer;
++  UInt32 pos;
++  UInt32 posLimit;
++  UInt32 streamPos;
++  UInt32 lenLimit;
++
++  UInt32 cyclicBufferPos;
++  UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */
++
++  UInt32 matchMaxLen;
++  CLzRef *hash;
++  CLzRef *son;
++  UInt32 hashMask;
++  UInt32 cutValue;
++
++  Byte *bufferBase;
++  ISeqInStream *stream;
++  int streamEndWasReached;
++
++  UInt32 blockSize;
++  UInt32 keepSizeBefore;
++  UInt32 keepSizeAfter;
++
++  UInt32 numHashBytes;
++  int directInput;
++  size_t directInputRem;
++  int btMode;
++  int bigHash;
++  UInt32 historySize;
++  UInt32 fixedHashSize;
++  UInt32 hashSizeSum;
++  UInt32 numSons;
++  SRes result;
++  UInt32 crc[256];
++} CMatchFinder;
++
++#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer)
++#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)])
++
++#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)
++
++int MatchFinder_NeedMove(CMatchFinder *p);
++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);
++void MatchFinder_MoveBlock(CMatchFinder *p);
++void MatchFinder_ReadIfRequired(CMatchFinder *p);
++
++void MatchFinder_Construct(CMatchFinder *p);
++
++/* Conditions:
++     historySize <= 3 GB
++     keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB
++*/
++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize,
++    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,
++    ISzAlloc *alloc);
++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);
++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);
++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);
++
++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son,
++    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue,
++    UInt32 *distances, UInt32 maxLen);
++
++/*
++Conditions:
++  Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func.
++  Mf_GetPointerToCurrentPos_Func's result must be used only before any other function
++*/
++
++typedef void (*Mf_Init_Func)(void *object);
++typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index);
++typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object);
++typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object);
++typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances);
++typedef void (*Mf_Skip_Func)(void *object, UInt32);
++
++typedef struct _IMatchFinder
++{
++  Mf_Init_Func Init;
++  Mf_GetIndexByte_Func GetIndexByte;
++  Mf_GetNumAvailableBytes_Func GetNumAvailableBytes;
++  Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos;
++  Mf_GetMatches_Func GetMatches;
++  Mf_Skip_Func Skip;
++} IMatchFinder;
++
++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);
++
++void MatchFinder_Init(CMatchFinder *p);
++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);
++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);
++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);
++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif
+--- /dev/null
++++ b/include/linux/lzma/LzHash.h
+@@ -0,0 +1,54 @@
++/* LzHash.h -- HASH functions for LZ algorithms
++2009-02-07 : Igor Pavlov : Public domain */
++
++#ifndef __LZ_HASH_H
++#define __LZ_HASH_H
++
++#define kHash2Size (1 << 10)
++#define kHash3Size (1 << 16)
++#define kHash4Size (1 << 20)
++
++#define kFix3HashSize (kHash2Size)
++#define kFix4HashSize (kHash2Size + kHash3Size)
++#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size)
++
++#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8);
++
++#define HASH3_CALC { \
++  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \
++  hash2Value = temp & (kHash2Size - 1); \
++  hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; }
++
++#define HASH4_CALC { \
++  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \
++  hash2Value = temp & (kHash2Size - 1); \
++  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \
++  hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; }
++
++#define HASH5_CALC { \
++  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \
++  hash2Value = temp & (kHash2Size - 1); \
++  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \
++  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \
++  hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \
++  hash4Value &= (kHash4Size - 1); }
++
++/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */
++#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF;
++
++
++#define MT_HASH2_CALC \
++  hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1);
++
++#define MT_HASH3_CALC { \
++  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \
++  hash2Value = temp & (kHash2Size - 1); \
++  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); }
++
++#define MT_HASH4_CALC { \
++  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \
++  hash2Value = temp & (kHash2Size - 1); \
++  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \
++  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); }
++
++#endif
+--- /dev/null
++++ b/include/linux/lzma/LzmaDec.h
+@@ -0,0 +1,231 @@
++/* LzmaDec.h -- LZMA Decoder
++2009-02-07 : Igor Pavlov : Public domain */
++
++#ifndef __LZMA_DEC_H
++#define __LZMA_DEC_H
++
++#include "Types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* #define _LZMA_PROB32 */
++/* _LZMA_PROB32 can increase the speed on some CPUs,
++   but memory usage for CLzmaDec::probs will be doubled in that case */
++
++#ifdef _LZMA_PROB32
++#define CLzmaProb UInt32
++#else
++#define CLzmaProb UInt16
++#endif
++
++
++/* ---------- LZMA Properties ---------- */
++
++#define LZMA_PROPS_SIZE 5
++
++typedef struct _CLzmaProps
++{
++  unsigned lc, lp, pb;
++  UInt32 dicSize;
++} CLzmaProps;
++
++/* LzmaProps_Decode - decodes properties
++Returns:
++  SZ_OK
++  SZ_ERROR_UNSUPPORTED - Unsupported properties
++*/
++
++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);
++
++
++/* ---------- LZMA Decoder state ---------- */
++
++/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case.
++   Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */
++
++#define LZMA_REQUIRED_INPUT_MAX 20
++
++typedef struct
++{
++  CLzmaProps prop;
++  CLzmaProb *probs;
++  Byte *dic;
++  const Byte *buf;
++  UInt32 range, code;
++  SizeT dicPos;
++  SizeT dicBufSize;
++  UInt32 processedPos;
++  UInt32 checkDicSize;
++  unsigned state;
++  UInt32 reps[4];
++  unsigned remainLen;
++  int needFlush;
++  int needInitState;
++  UInt32 numProbs;
++  unsigned tempBufSize;
++  Byte tempBuf[LZMA_REQUIRED_INPUT_MAX];
++} CLzmaDec;
++
++#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }
++
++void LzmaDec_Init(CLzmaDec *p);
++
++/* There are two types of LZMA streams:
++     0) Stream with end mark. That end mark adds about 6 bytes to compressed size.
++     1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */
++
++typedef enum
++{
++  LZMA_FINISH_ANY,   /* finish at any point */
++  LZMA_FINISH_END    /* block must be finished at the end */
++} ELzmaFinishMode;
++
++/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!!
++
++   You must use LZMA_FINISH_END, when you know that current output buffer
++   covers last bytes of block. In other cases you must use LZMA_FINISH_ANY.
++
++   If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK,
++   and output value of destLen will be less than output buffer size limit.
++   You can check status result also.
++
++   You can use multiple checks to test data integrity after full decompression:
++     1) Check Result and "status" variable.
++     2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.
++     3) Check that output(srcLen) = compressedSize, if you know real compressedSize.
++        You must use correct finish mode in that case. */
++
++typedef enum
++{
++  LZMA_STATUS_NOT_SPECIFIED,               /* use main error code instead */
++  LZMA_STATUS_FINISHED_WITH_MARK,          /* stream was finished with end mark. */
++  LZMA_STATUS_NOT_FINISHED,                /* stream was not finished */
++  LZMA_STATUS_NEEDS_MORE_INPUT,            /* you must provide more input bytes */
++  LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK  /* there is probability that stream was finished without end mark */
++} ELzmaStatus;
++
++/* ELzmaStatus is used only as output value for function call */
++
++
++/* ---------- Interfaces ---------- */
++
++/* There are 3 levels of interfaces:
++     1) Dictionary Interface
++     2) Buffer Interface
++     3) One Call Interface
++   You can select any of these interfaces, but don't mix functions from different
++   groups for same object. */
++
++
++/* There are two variants to allocate state for Dictionary Interface:
++     1) LzmaDec_Allocate / LzmaDec_Free
++     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs
++   You can use variant 2, if you set dictionary buffer manually.
++   For Buffer Interface you must always use variant 1.
++
++LzmaDec_Allocate* can return:
++  SZ_OK
++  SZ_ERROR_MEM         - Memory allocation error
++  SZ_ERROR_UNSUPPORTED - Unsupported properties
++*/
++
++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);
++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);
++
++SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);
++void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);
++
++/* ---------- Dictionary Interface ---------- */
++
++/* You can use it, if you want to eliminate the overhead for data copying from
++   dictionary to some other external buffer.
++   You must work with CLzmaDec variables directly in this interface.
++
++   STEPS:
++     LzmaDec_Constr()
++     LzmaDec_Allocate()
++     for (each new stream)
++     {
++       LzmaDec_Init()
++       while (it needs more decompression)
++       {
++         LzmaDec_DecodeToDic()
++         use data from CLzmaDec::dic and update CLzmaDec::dicPos
++       }
++     }
++     LzmaDec_Free()
++*/
++
++/* LzmaDec_DecodeToDic
++
++   The decoding to internal dictionary buffer (CLzmaDec::dic).
++   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!
++
++finishMode:
++  It has meaning only if the decoding reaches output limit (dicLimit).
++  LZMA_FINISH_ANY - Decode just dicLimit bytes.
++  LZMA_FINISH_END - Stream must be finished after dicLimit.
++
++Returns:
++  SZ_OK
++    status:
++      LZMA_STATUS_FINISHED_WITH_MARK
++      LZMA_STATUS_NOT_FINISHED
++      LZMA_STATUS_NEEDS_MORE_INPUT
++      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK
++  SZ_ERROR_DATA - Data error
++*/
++
++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,
++    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);
++
++
++/* ---------- Buffer Interface ---------- */
++
++/* It's zlib-like interface.
++   See LzmaDec_DecodeToDic description for information about STEPS and return results,
++   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need
++   to work with CLzmaDec variables manually.
++
++finishMode:
++  It has meaning only if the decoding reaches output limit (*destLen).
++  LZMA_FINISH_ANY - Decode just destLen bytes.
++  LZMA_FINISH_END - Stream must be finished after (*destLen).
++*/
++
++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,
++    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);
++
++
++/* ---------- One Call Interface ---------- */
++
++/* LzmaDecode
++
++finishMode:
++  It has meaning only if the decoding reaches output limit (*destLen).
++  LZMA_FINISH_ANY - Decode just destLen bytes.
++  LZMA_FINISH_END - Stream must be finished after (*destLen).
++
++Returns:
++  SZ_OK
++    status:
++      LZMA_STATUS_FINISHED_WITH_MARK
++      LZMA_STATUS_NOT_FINISHED
++      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK
++  SZ_ERROR_DATA - Data error
++  SZ_ERROR_MEM  - Memory allocation error
++  SZ_ERROR_UNSUPPORTED - Unsupported properties
++  SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).
++*/
++
++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,
++    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,
++    ELzmaStatus *status, ISzAlloc *alloc);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif
+--- /dev/null
++++ b/include/linux/lzma/LzmaEnc.h
+@@ -0,0 +1,80 @@
++/*  LzmaEnc.h -- LZMA Encoder
++2009-02-07 : Igor Pavlov : Public domain */
++
++#ifndef __LZMA_ENC_H
++#define __LZMA_ENC_H
++
++#include "Types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define LZMA_PROPS_SIZE 5
++
++typedef struct _CLzmaEncProps
++{
++  int level;       /*  0 <= level <= 9 */
++  UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version
++                      (1 << 12) <= dictSize <= (1 << 30) for 64-bit version
++                       default = (1 << 24) */
++  int lc;          /* 0 <= lc <= 8, default = 3 */
++  int lp;          /* 0 <= lp <= 4, default = 0 */
++  int pb;          /* 0 <= pb <= 4, default = 2 */
++  int algo;        /* 0 - fast, 1 - normal, default = 1 */
++  int fb;          /* 5 <= fb <= 273, default = 32 */
++  int btMode;      /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */
++  int numHashBytes; /* 2, 3 or 4, default = 4 */
++  UInt32 mc;        /* 1 <= mc <= (1 << 30), default = 32 */
++  unsigned writeEndMark;  /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */
++  int numThreads;  /* 1 or 2, default = 2 */
++} CLzmaEncProps;
++
++void LzmaEncProps_Init(CLzmaEncProps *p);
++void LzmaEncProps_Normalize(CLzmaEncProps *p);
++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);
++
++
++/* ---------- CLzmaEncHandle Interface ---------- */
++
++/* LzmaEnc_* functions can return the following exit codes:
++Returns:
++  SZ_OK           - OK
++  SZ_ERROR_MEM    - Memory allocation error
++  SZ_ERROR_PARAM  - Incorrect paramater in props
++  SZ_ERROR_WRITE  - Write callback error.
++  SZ_ERROR_PROGRESS - some break from progress callback
++  SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version)
++*/
++
++typedef void * CLzmaEncHandle;
++
++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc);
++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);
++SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);
++SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);
++SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream,
++    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
++SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
++    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
++
++/* ---------- One Call Interface ---------- */
++
++/* LzmaEncode
++Return code:
++  SZ_OK               - OK
++  SZ_ERROR_MEM        - Memory allocation error
++  SZ_ERROR_PARAM      - Incorrect paramater
++  SZ_ERROR_OUTPUT_EOF - output buffer overflow
++  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)
++*/
++
++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
++    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,
++    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif
+--- /dev/null
++++ b/include/linux/lzma/Types.h
+@@ -0,0 +1,226 @@
++/* Types.h -- Basic types
++2009-11-23 : Igor Pavlov : Public domain */
++
++#ifndef __7Z_TYPES_H
++#define __7Z_TYPES_H
++
++#include <stddef.h>
++
++#ifdef _WIN32
++#include <windows.h>
++#endif
++
++#ifndef EXTERN_C_BEGIN
++#ifdef __cplusplus
++#define EXTERN_C_BEGIN extern "C" {
++#define EXTERN_C_END }
++#else
++#define EXTERN_C_BEGIN
++#define EXTERN_C_END
++#endif
++#endif
++
++EXTERN_C_BEGIN
++
++#define SZ_OK 0
++
++#define SZ_ERROR_DATA 1
++#define SZ_ERROR_MEM 2
++#define SZ_ERROR_CRC 3
++#define SZ_ERROR_UNSUPPORTED 4
++#define SZ_ERROR_PARAM 5
++#define SZ_ERROR_INPUT_EOF 6
++#define SZ_ERROR_OUTPUT_EOF 7
++#define SZ_ERROR_READ 8
++#define SZ_ERROR_WRITE 9
++#define SZ_ERROR_PROGRESS 10
++#define SZ_ERROR_FAIL 11
++#define SZ_ERROR_THREAD 12
++
++#define SZ_ERROR_ARCHIVE 16
++#define SZ_ERROR_NO_ARCHIVE 17
++
++typedef int SRes;
++
++#ifdef _WIN32
++typedef DWORD WRes;
++#else
++typedef int WRes;
++#endif
++
++#ifndef RINOK
++#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; }
++#endif
++
++typedef unsigned char Byte;
++typedef short Int16;
++typedef unsigned short UInt16;
++
++#ifdef _LZMA_UINT32_IS_ULONG
++typedef long Int32;
++typedef unsigned long UInt32;
++#else
++typedef int Int32;
++typedef unsigned int UInt32;
++#endif
++
++#ifdef _SZ_NO_INT_64
++
++/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers.
++   NOTES: Some code will work incorrectly in that case! */
++
++typedef long Int64;
++typedef unsigned long UInt64;
++
++#else
++
++#if defined(_MSC_VER) || defined(__BORLANDC__)
++typedef __int64 Int64;
++typedef unsigned __int64 UInt64;
++#else
++typedef long long int Int64;
++typedef unsigned long long int UInt64;
++#endif
++
++#endif
++
++#ifdef _LZMA_NO_SYSTEM_SIZE_T
++typedef UInt32 SizeT;
++#else
++typedef size_t SizeT;
++#endif
++
++typedef int Bool;
++#define True 1
++#define False 0
++
++
++#ifdef _WIN32
++#define MY_STD_CALL __stdcall
++#else
++#define MY_STD_CALL
++#endif
++
++#ifdef _MSC_VER
++
++#if _MSC_VER >= 1300
++#define MY_NO_INLINE __declspec(noinline)
++#else
++#define MY_NO_INLINE
++#endif
++
++#define MY_CDECL __cdecl
++#define MY_FAST_CALL __fastcall
++
++#else
++
++#define MY_CDECL
++#define MY_FAST_CALL
++
++#endif
++
++
++/* The following interfaces use first parameter as pointer to structure */
++
++typedef struct
++{
++  SRes (*Read)(void *p, void *buf, size_t *size);
++    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.
++       (output(*size) < input(*size)) is allowed */
++} ISeqInStream;
++
++/* it can return SZ_ERROR_INPUT_EOF */
++SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size);
++SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType);
++SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf);
++
++typedef struct
++{
++  size_t (*Write)(void *p, const void *buf, size_t size);
++    /* Returns: result - the number of actually written bytes.
++       (result < size) means error */
++} ISeqOutStream;
++
++typedef enum
++{
++  SZ_SEEK_SET = 0,
++  SZ_SEEK_CUR = 1,
++  SZ_SEEK_END = 2
++} ESzSeek;
++
++typedef struct
++{
++  SRes (*Read)(void *p, void *buf, size_t *size);  /* same as ISeqInStream::Read */
++  SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);
++} ISeekInStream;
++
++typedef struct
++{
++  SRes (*Look)(void *p, void **buf, size_t *size);
++    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.
++       (output(*size) > input(*size)) is not allowed
++       (output(*size) < input(*size)) is allowed */
++  SRes (*Skip)(void *p, size_t offset);
++    /* offset must be <= output(*size) of Look */
++
++  SRes (*Read)(void *p, void *buf, size_t *size);
++    /* reads directly (without buffer). It's same as ISeqInStream::Read */
++  SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);
++} ILookInStream;
++
++SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size);
++SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset);
++
++/* reads via ILookInStream::Read */
++SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType);
++SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size);
++
++#define LookToRead_BUF_SIZE (1 << 14)
++
++typedef struct
++{
++  ILookInStream s;
++  ISeekInStream *realStream;
++  size_t pos;
++  size_t size;
++  Byte buf[LookToRead_BUF_SIZE];
++} CLookToRead;
++
++void LookToRead_CreateVTable(CLookToRead *p, int lookahead);
++void LookToRead_Init(CLookToRead *p);
++
++typedef struct
++{
++  ISeqInStream s;
++  ILookInStream *realStream;
++} CSecToLook;
++
++void SecToLook_CreateVTable(CSecToLook *p);
++
++typedef struct
++{
++  ISeqInStream s;
++  ILookInStream *realStream;
++} CSecToRead;
++
++void SecToRead_CreateVTable(CSecToRead *p);
++
++typedef struct
++{
++  SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize);
++    /* Returns: result. (result != SZ_OK) means break.
++       Value (UInt64)(Int64)-1 for size means unknown value. */
++} ICompressProgress;
++
++typedef struct
++{
++  void *(*Alloc)(void *p, size_t size);
++  void (*Free)(void *p, void *address); /* address can be 0 */
++} ISzAlloc;
++
++#define IAlloc_Alloc(p, size) (p)->Alloc((p), size)
++#define IAlloc_Free(p, a) (p)->Free((p), a)
++
++EXTERN_C_END
++
++#endif
+--- a/include/uapi/linux/jffs2.h
++++ b/include/uapi/linux/jffs2.h
+@@ -46,6 +46,7 @@
+ #define JFFS2_COMPR_DYNRUBIN	0x05
+ #define JFFS2_COMPR_ZLIB	0x06
+ #define JFFS2_COMPR_LZO		0x07
++#define JFFS2_COMPR_LZMA	0x08
+ /* Compatibility flags. */
+ #define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */
+ #define JFFS2_NODE_ACCURATE 0x2000
+--- a/lib/Kconfig
++++ b/lib/Kconfig
+@@ -356,6 +356,12 @@ config ZSTD_DECOMPRESS
+ 
+ source "lib/xz/Kconfig"
+ 
++config LZMA_COMPRESS
++    tristate
++
++config LZMA_DECOMPRESS
++    tristate
++
+ #
+ # These all provide a common interface (hence the apparent duplication with
+ # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -145,6 +145,16 @@ CFLAGS_kobject.o += -DDEBUG
+ CFLAGS_kobject_uevent.o += -DDEBUG
+ endif
+ 
++ifdef CONFIG_JFFS2_ZLIB
++  CONFIG_ZLIB_INFLATE:=y
++  CONFIG_ZLIB_DEFLATE:=y
++endif
++
++ifdef CONFIG_JFFS2_LZMA
++  CONFIG_LZMA_DECOMPRESS:=y
++  CONFIG_LZMA_COMPRESS:=y
++endif
++
+ obj-$(CONFIG_DEBUG_INFO_REDUCED) += debug_info.o
+ CFLAGS_debug_info.o += $(call cc-option, -femit-struct-debug-detailed=any)
+ 
+@@ -205,6 +215,8 @@ obj-$(CONFIG_ZSTD_COMPRESS) += zstd/
+ obj-$(CONFIG_ZSTD_DECOMPRESS) += zstd/
+ obj-$(CONFIG_XZ_DEC) += xz/
+ obj-$(CONFIG_RAID6_PQ) += raid6/
++obj-$(CONFIG_LZMA_COMPRESS) += lzma/
++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/
+ 
+ lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o
+ lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
+--- /dev/null
++++ b/lib/lzma/LzFind.c
+@@ -0,0 +1,761 @@
++/* LzFind.c -- Match finder for LZ algorithms
++2009-04-22 : Igor Pavlov : Public domain */
++
++#include <string.h>
++
++#include "LzFind.h"
++#include "LzHash.h"
++
++#define kEmptyHashValue 0
++#define kMaxValForNormalize ((UInt32)0xFFFFFFFF)
++#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */
++#define kNormalizeMask (~(kNormalizeStepMin - 1))
++#define kMaxHistorySize ((UInt32)3 << 30)
++
++#define kStartMaxLen 3
++
++static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)
++{
++  if (!p->directInput)
++  {
++    alloc->Free(alloc, p->bufferBase);
++    p->bufferBase = 0;
++  }
++}
++
++/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */
++
++static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)
++{
++  UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;
++  if (p->directInput)
++  {
++    p->blockSize = blockSize;
++    return 1;
++  }
++  if (p->bufferBase == 0 || p->blockSize != blockSize)
++  {
++    LzInWindow_Free(p, alloc);
++    p->blockSize = blockSize;
++    p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize);
++  }
++  return (p->bufferBase != 0);
++}
++
++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }
++Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }
++
++UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }
++
++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)
++{
++  p->posLimit -= subValue;
++  p->pos -= subValue;
++  p->streamPos -= subValue;
++}
++
++static void MatchFinder_ReadBlock(CMatchFinder *p)
++{
++  if (p->streamEndWasReached || p->result != SZ_OK)
++    return;
++  if (p->directInput)
++  {
++    UInt32 curSize = 0xFFFFFFFF - p->streamPos;
++    if (curSize > p->directInputRem)
++      curSize = (UInt32)p->directInputRem;
++    p->directInputRem -= curSize;
++    p->streamPos += curSize;
++    if (p->directInputRem == 0)
++      p->streamEndWasReached = 1;
++    return;
++  }
++  for (;;)
++  {
++    Byte *dest = p->buffer + (p->streamPos - p->pos);
++    size_t size = (p->bufferBase + p->blockSize - dest);
++    if (size == 0)
++      return;
++    p->result = p->stream->Read(p->stream, dest, &size);
++    if (p->result != SZ_OK)
++      return;
++    if (size == 0)
++    {
++      p->streamEndWasReached = 1;
++      return;
++    }
++    p->streamPos += (UInt32)size;
++    if (p->streamPos - p->pos > p->keepSizeAfter)
++      return;
++  }
++}
++
++void MatchFinder_MoveBlock(CMatchFinder *p)
++{
++  memmove(p->bufferBase,
++    p->buffer - p->keepSizeBefore,
++    (size_t)(p->streamPos - p->pos + p->keepSizeBefore));
++  p->buffer = p->bufferBase + p->keepSizeBefore;
++}
++
++int MatchFinder_NeedMove(CMatchFinder *p)
++{
++  if (p->directInput)
++    return 0;
++  /* if (p->streamEndWasReached) return 0; */
++  return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);
++}
++
++void MatchFinder_ReadIfRequired(CMatchFinder *p)
++{
++  if (p->streamEndWasReached)
++    return;
++  if (p->keepSizeAfter >= p->streamPos - p->pos)
++    MatchFinder_ReadBlock(p);
++}
++
++static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)
++{
++  if (MatchFinder_NeedMove(p))
++    MatchFinder_MoveBlock(p);
++  MatchFinder_ReadBlock(p);
++}
++
++static void MatchFinder_SetDefaultSettings(CMatchFinder *p)
++{
++  p->cutValue = 32;
++  p->btMode = 1;
++  p->numHashBytes = 4;
++  p->bigHash = 0;
++}
++
++#define kCrcPoly 0xEDB88320
++
++void MatchFinder_Construct(CMatchFinder *p)
++{
++  UInt32 i;
++  p->bufferBase = 0;
++  p->directInput = 0;
++  p->hash = 0;
++  MatchFinder_SetDefaultSettings(p);
++
++  for (i = 0; i < 256; i++)
++  {
++    UInt32 r = i;
++    int j;
++    for (j = 0; j < 8; j++)
++      r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1));
++    p->crc[i] = r;
++  }
++}
++
++static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc)
++{
++  alloc->Free(alloc, p->hash);
++  p->hash = 0;
++}
++
++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc)
++{
++  MatchFinder_FreeThisClassMemory(p, alloc);
++  LzInWindow_Free(p, alloc);
++}
++
++static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc)
++{
++  size_t sizeInBytes = (size_t)num * sizeof(CLzRef);
++  if (sizeInBytes / sizeof(CLzRef) != num)
++    return 0;
++  return (CLzRef *)alloc->Alloc(alloc, sizeInBytes);
++}
++
++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize,
++    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,
++    ISzAlloc *alloc)
++{
++  UInt32 sizeReserv;
++  if (historySize > kMaxHistorySize)
++  {
++    MatchFinder_Free(p, alloc);
++    return 0;
++  }
++  sizeReserv = historySize >> 1;
++  if (historySize > ((UInt32)2 << 30))
++    sizeReserv = historySize >> 2;
++  sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19);
++
++  p->keepSizeBefore = historySize + keepAddBufferBefore + 1;
++  p->keepSizeAfter = matchMaxLen + keepAddBufferAfter;
++  /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */
++  if (LzInWindow_Create(p, sizeReserv, alloc))
++  {
++    UInt32 newCyclicBufferSize = historySize + 1;
++    UInt32 hs;
++    p->matchMaxLen = matchMaxLen;
++    {
++      p->fixedHashSize = 0;
++      if (p->numHashBytes == 2)
++        hs = (1 << 16) - 1;
++      else
++      {
++        hs = historySize - 1;
++        hs |= (hs >> 1);
++        hs |= (hs >> 2);
++        hs |= (hs >> 4);
++        hs |= (hs >> 8);
++        hs >>= 1;
++        hs |= 0xFFFF; /* don't change it! It's required for Deflate */
++        if (hs > (1 << 24))
++        {
++          if (p->numHashBytes == 3)
++            hs = (1 << 24) - 1;
++          else
++            hs >>= 1;
++        }
++      }
++      p->hashMask = hs;
++      hs++;
++      if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size;
++      if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size;
++      if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size;
++      hs += p->fixedHashSize;
++    }
++
++    {
++      UInt32 prevSize = p->hashSizeSum + p->numSons;
++      UInt32 newSize;
++      p->historySize = historySize;
++      p->hashSizeSum = hs;
++      p->cyclicBufferSize = newCyclicBufferSize;
++      p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize);
++      newSize = p->hashSizeSum + p->numSons;
++      if (p->hash != 0 && prevSize == newSize)
++        return 1;
++      MatchFinder_FreeThisClassMemory(p, alloc);
++      p->hash = AllocRefs(newSize, alloc);
++      if (p->hash != 0)
++      {
++        p->son = p->hash + p->hashSizeSum;
++        return 1;
++      }
++    }
++  }
++  MatchFinder_Free(p, alloc);
++  return 0;
++}
++
++static void MatchFinder_SetLimits(CMatchFinder *p)
++{
++  UInt32 limit = kMaxValForNormalize - p->pos;
++  UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos;
++  if (limit2 < limit)
++    limit = limit2;
++  limit2 = p->streamPos - p->pos;
++  if (limit2 <= p->keepSizeAfter)
++  {
++    if (limit2 > 0)
++      limit2 = 1;
++  }
++  else
++    limit2 -= p->keepSizeAfter;
++  if (limit2 < limit)
++    limit = limit2;
++  {
++    UInt32 lenLimit = p->streamPos - p->pos;
++    if (lenLimit > p->matchMaxLen)
++      lenLimit = p->matchMaxLen;
++    p->lenLimit = lenLimit;
++  }
++  p->posLimit = p->pos + limit;
++}
++
++void MatchFinder_Init(CMatchFinder *p)
++{
++  UInt32 i;
++  for (i = 0; i < p->hashSizeSum; i++)
++    p->hash[i] = kEmptyHashValue;
++  p->cyclicBufferPos = 0;
++  p->buffer = p->bufferBase;
++  p->pos = p->streamPos = p->cyclicBufferSize;
++  p->result = SZ_OK;
++  p->streamEndWasReached = 0;
++  MatchFinder_ReadBlock(p);
++  MatchFinder_SetLimits(p);
++}
++
++static UInt32 MatchFinder_GetSubValue(CMatchFinder *p)
++{
++  return (p->pos - p->historySize - 1) & kNormalizeMask;
++}
++
++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)
++{
++  UInt32 i;
++  for (i = 0; i < numItems; i++)
++  {
++    UInt32 value = items[i];
++    if (value <= subValue)
++      value = kEmptyHashValue;
++    else
++      value -= subValue;
++    items[i] = value;
++  }
++}
++
++static void MatchFinder_Normalize(CMatchFinder *p)
++{
++  UInt32 subValue = MatchFinder_GetSubValue(p);
++  MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons);
++  MatchFinder_ReduceOffsets(p, subValue);
++}
++
++static void MatchFinder_CheckLimits(CMatchFinder *p)
++{
++  if (p->pos == kMaxValForNormalize)
++    MatchFinder_Normalize(p);
++  if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos)
++    MatchFinder_CheckAndMoveAndRead(p);
++  if (p->cyclicBufferPos == p->cyclicBufferSize)
++    p->cyclicBufferPos = 0;
++  MatchFinder_SetLimits(p);
++}
++
++static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,
++    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,
++    UInt32 *distances, UInt32 maxLen)
++{
++  son[_cyclicBufferPos] = curMatch;
++  for (;;)
++  {
++    UInt32 delta = pos - curMatch;
++    if (cutValue-- == 0 || delta >= _cyclicBufferSize)
++      return distances;
++    {
++      const Byte *pb = cur - delta;
++      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];
++      if (pb[maxLen] == cur[maxLen] && *pb == *cur)
++      {
++        UInt32 len = 0;
++        while (++len != lenLimit)
++          if (pb[len] != cur[len])
++            break;
++        if (maxLen < len)
++        {
++          *distances++ = maxLen = len;
++          *distances++ = delta - 1;
++          if (len == lenLimit)
++            return distances;
++        }
++      }
++    }
++  }
++}
++
++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,
++    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,
++    UInt32 *distances, UInt32 maxLen)
++{
++  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;
++  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);
++  UInt32 len0 = 0, len1 = 0;
++  for (;;)
++  {
++    UInt32 delta = pos - curMatch;
++    if (cutValue-- == 0 || delta >= _cyclicBufferSize)
++    {
++      *ptr0 = *ptr1 = kEmptyHashValue;
++      return distances;
++    }
++    {
++      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);
++      const Byte *pb = cur - delta;
++      UInt32 len = (len0 < len1 ? len0 : len1);
++      if (pb[len] == cur[len])
++      {
++        if (++len != lenLimit && pb[len] == cur[len])
++          while (++len != lenLimit)
++            if (pb[len] != cur[len])
++              break;
++        if (maxLen < len)
++        {
++          *distances++ = maxLen = len;
++          *distances++ = delta - 1;
++          if (len == lenLimit)
++          {
++            *ptr1 = pair[0];
++            *ptr0 = pair[1];
++            return distances;
++          }
++        }
++      }
++      if (pb[len] < cur[len])
++      {
++        *ptr1 = curMatch;
++        ptr1 = pair + 1;
++        curMatch = *ptr1;
++        len1 = len;
++      }
++      else
++      {
++        *ptr0 = curMatch;
++        ptr0 = pair;
++        curMatch = *ptr0;
++        len0 = len;
++      }
++    }
++  }
++}
++
++static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,
++    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue)
++{
++  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;
++  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);
++  UInt32 len0 = 0, len1 = 0;
++  for (;;)
++  {
++    UInt32 delta = pos - curMatch;
++    if (cutValue-- == 0 || delta >= _cyclicBufferSize)
++    {
++      *ptr0 = *ptr1 = kEmptyHashValue;
++      return;
++    }
++    {
++      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);
++      const Byte *pb = cur - delta;
++      UInt32 len = (len0 < len1 ? len0 : len1);
++      if (pb[len] == cur[len])
++      {
++        while (++len != lenLimit)
++          if (pb[len] != cur[len])
++            break;
++        {
++          if (len == lenLimit)
++          {
++            *ptr1 = pair[0];
++            *ptr0 = pair[1];
++            return;
++          }
++        }
++      }
++      if (pb[len] < cur[len])
++      {
++        *ptr1 = curMatch;
++        ptr1 = pair + 1;
++        curMatch = *ptr1;
++        len1 = len;
++      }
++      else
++      {
++        *ptr0 = curMatch;
++        ptr0 = pair;
++        curMatch = *ptr0;
++        len0 = len;
++      }
++    }
++  }
++}
++
++#define MOVE_POS \
++  ++p->cyclicBufferPos; \
++  p->buffer++; \
++  if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);
++
++#define MOVE_POS_RET MOVE_POS return offset;
++
++static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }
++
++#define GET_MATCHES_HEADER2(minLen, ret_op) \
++  UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \
++  lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \
++  cur = p->buffer;
++
++#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0)
++#define SKIP_HEADER(minLen)        GET_MATCHES_HEADER2(minLen, continue)
++
++#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue
++
++#define GET_MATCHES_FOOTER(offset, maxLen) \
++  offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \
++  distances + offset, maxLen) - distances); MOVE_POS_RET;
++
++#define SKIP_FOOTER \
++  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;
++
++static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
++{
++  UInt32 offset;
++  GET_MATCHES_HEADER(2)
++  HASH2_CALC;
++  curMatch = p->hash[hashValue];
++  p->hash[hashValue] = p->pos;
++  offset = 0;
++  GET_MATCHES_FOOTER(offset, 1)
++}
++
++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
++{
++  UInt32 offset;
++  GET_MATCHES_HEADER(3)
++  HASH_ZIP_CALC;
++  curMatch = p->hash[hashValue];
++  p->hash[hashValue] = p->pos;
++  offset = 0;
++  GET_MATCHES_FOOTER(offset, 2)
++}
++
++static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
++{
++  UInt32 hash2Value, delta2, maxLen, offset;
++  GET_MATCHES_HEADER(3)
++
++  HASH3_CALC;
++
++  delta2 = p->pos - p->hash[hash2Value];
++  curMatch = p->hash[kFix3HashSize + hashValue];
++
++  p->hash[hash2Value] =
++  p->hash[kFix3HashSize + hashValue] = p->pos;
++
++
++  maxLen = 2;
++  offset = 0;
++  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)
++  {
++    for (; maxLen != lenLimit; maxLen++)
++      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])
++        break;
++    distances[0] = maxLen;
++    distances[1] = delta2 - 1;
++    offset = 2;
++    if (maxLen == lenLimit)
++    {
++      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));
++      MOVE_POS_RET;
++    }
++  }
++  GET_MATCHES_FOOTER(offset, maxLen)
++}
++
++static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
++{
++  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;
++  GET_MATCHES_HEADER(4)
++
++  HASH4_CALC;
++
++  delta2 = p->pos - p->hash[                hash2Value];
++  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];
++  curMatch = p->hash[kFix4HashSize + hashValue];
++
++  p->hash[                hash2Value] =
++  p->hash[kFix3HashSize + hash3Value] =
++  p->hash[kFix4HashSize + hashValue] = p->pos;
++
++  maxLen = 1;
++  offset = 0;
++  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)
++  {
++    distances[0] = maxLen = 2;
++    distances[1] = delta2 - 1;
++    offset = 2;
++  }
++  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)
++  {
++    maxLen = 3;
++    distances[offset + 1] = delta3 - 1;
++    offset += 2;
++    delta2 = delta3;
++  }
++  if (offset != 0)
++  {
++    for (; maxLen != lenLimit; maxLen++)
++      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])
++        break;
++    distances[offset - 2] = maxLen;
++    if (maxLen == lenLimit)
++    {
++      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));
++      MOVE_POS_RET;
++    }
++  }
++  if (maxLen < 3)
++    maxLen = 3;
++  GET_MATCHES_FOOTER(offset, maxLen)
++}
++
++static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
++{
++  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;
++  GET_MATCHES_HEADER(4)
++
++  HASH4_CALC;
++
++  delta2 = p->pos - p->hash[                hash2Value];
++  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];
++  curMatch = p->hash[kFix4HashSize + hashValue];
++
++  p->hash[                hash2Value] =
++  p->hash[kFix3HashSize + hash3Value] =
++  p->hash[kFix4HashSize + hashValue] = p->pos;
++
++  maxLen = 1;
++  offset = 0;
++  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)
++  {
++    distances[0] = maxLen = 2;
++    distances[1] = delta2 - 1;
++    offset = 2;
++  }
++  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)
++  {
++    maxLen = 3;
++    distances[offset + 1] = delta3 - 1;
++    offset += 2;
++    delta2 = delta3;
++  }
++  if (offset != 0)
++  {
++    for (; maxLen != lenLimit; maxLen++)
++      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])
++        break;
++    distances[offset - 2] = maxLen;
++    if (maxLen == lenLimit)
++    {
++      p->son[p->cyclicBufferPos] = curMatch;
++      MOVE_POS_RET;
++    }
++  }
++  if (maxLen < 3)
++    maxLen = 3;
++  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),
++    distances + offset, maxLen) - (distances));
++  MOVE_POS_RET
++}
++
++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)
++{
++  UInt32 offset;
++  GET_MATCHES_HEADER(3)
++  HASH_ZIP_CALC;
++  curMatch = p->hash[hashValue];
++  p->hash[hashValue] = p->pos;
++  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),
++    distances, 2) - (distances));
++  MOVE_POS_RET
++}
++
++static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
++{
++  do
++  {
++    SKIP_HEADER(2)
++    HASH2_CALC;
++    curMatch = p->hash[hashValue];
++    p->hash[hashValue] = p->pos;
++    SKIP_FOOTER
++  }
++  while (--num != 0);
++}
++
++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
++{
++  do
++  {
++    SKIP_HEADER(3)
++    HASH_ZIP_CALC;
++    curMatch = p->hash[hashValue];
++    p->hash[hashValue] = p->pos;
++    SKIP_FOOTER
++  }
++  while (--num != 0);
++}
++
++static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
++{
++  do
++  {
++    UInt32 hash2Value;
++    SKIP_HEADER(3)
++    HASH3_CALC;
++    curMatch = p->hash[kFix3HashSize + hashValue];
++    p->hash[hash2Value] =
++    p->hash[kFix3HashSize + hashValue] = p->pos;
++    SKIP_FOOTER
++  }
++  while (--num != 0);
++}
++
++static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
++{
++  do
++  {
++    UInt32 hash2Value, hash3Value;
++    SKIP_HEADER(4)
++    HASH4_CALC;
++    curMatch = p->hash[kFix4HashSize + hashValue];
++    p->hash[                hash2Value] =
++    p->hash[kFix3HashSize + hash3Value] = p->pos;
++    p->hash[kFix4HashSize + hashValue] = p->pos;
++    SKIP_FOOTER
++  }
++  while (--num != 0);
++}
++
++static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
++{
++  do
++  {
++    UInt32 hash2Value, hash3Value;
++    SKIP_HEADER(4)
++    HASH4_CALC;
++    curMatch = p->hash[kFix4HashSize + hashValue];
++    p->hash[                hash2Value] =
++    p->hash[kFix3HashSize + hash3Value] =
++    p->hash[kFix4HashSize + hashValue] = p->pos;
++    p->son[p->cyclicBufferPos] = curMatch;
++    MOVE_POS
++  }
++  while (--num != 0);
++}
++
++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)
++{
++  do
++  {
++    SKIP_HEADER(3)
++    HASH_ZIP_CALC;
++    curMatch = p->hash[hashValue];
++    p->hash[hashValue] = p->pos;
++    p->son[p->cyclicBufferPos] = curMatch;
++    MOVE_POS
++  }
++  while (--num != 0);
++}
++
++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)
++{
++  vTable->Init = (Mf_Init_Func)MatchFinder_Init;
++  vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;
++  vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;
++  vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;
++  if (!p->btMode)
++  {
++    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;
++    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;
++  }
++  else if (p->numHashBytes == 2)
++  {
++    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;
++    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;
++  }
++  else if (p->numHashBytes == 3)
++  {
++    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;
++    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;
++  }
++  else
++  {
++    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;
++    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;
++  }
++}
+--- /dev/null
++++ b/lib/lzma/LzmaDec.c
+@@ -0,0 +1,999 @@
++/* LzmaDec.c -- LZMA Decoder
++2009-09-20 : Igor Pavlov : Public domain */
++
++#include "LzmaDec.h"
++
++#include <string.h>
++
++#define kNumTopBits 24
++#define kTopValue ((UInt32)1 << kNumTopBits)
++
++#define kNumBitModelTotalBits 11
++#define kBitModelTotal (1 << kNumBitModelTotalBits)
++#define kNumMoveBits 5
++
++#define RC_INIT_SIZE 5
++
++#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); }
++
++#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)
++#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits));
++#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits));
++#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \
++  { UPDATE_0(p); i = (i + i); A0; } else \
++  { UPDATE_1(p); i = (i + i) + 1; A1; }
++#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;)
++
++#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); }
++#define TREE_DECODE(probs, limit, i) \
++  { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; }
++
++/* #define _LZMA_SIZE_OPT */
++
++#ifdef _LZMA_SIZE_OPT
++#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i)
++#else
++#define TREE_6_DECODE(probs, i) \
++  { i = 1; \
++  TREE_GET_BIT(probs, i); \
++  TREE_GET_BIT(probs, i); \
++  TREE_GET_BIT(probs, i); \
++  TREE_GET_BIT(probs, i); \
++  TREE_GET_BIT(probs, i); \
++  TREE_GET_BIT(probs, i); \
++  i -= 0x40; }
++#endif
++
++#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); }
++
++#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)
++#define UPDATE_0_CHECK range = bound;
++#define UPDATE_1_CHECK range -= bound; code -= bound;
++#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \
++  { UPDATE_0_CHECK; i = (i + i); A0; } else \
++  { UPDATE_1_CHECK; i = (i + i) + 1; A1; }
++#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;)
++#define TREE_DECODE_CHECK(probs, limit, i) \
++  { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; }
++
++
++#define kNumPosBitsMax 4
++#define kNumPosStatesMax (1 << kNumPosBitsMax)
++
++#define kLenNumLowBits 3
++#define kLenNumLowSymbols (1 << kLenNumLowBits)
++#define kLenNumMidBits 3
++#define kLenNumMidSymbols (1 << kLenNumMidBits)
++#define kLenNumHighBits 8
++#define kLenNumHighSymbols (1 << kLenNumHighBits)
++
++#define LenChoice 0
++#define LenChoice2 (LenChoice + 1)
++#define LenLow (LenChoice2 + 1)
++#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
++#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
++#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
++
++
++#define kNumStates 12
++#define kNumLitStates 7
++
++#define kStartPosModelIndex 4
++#define kEndPosModelIndex 14
++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
++
++#define kNumPosSlotBits 6
++#define kNumLenToPosStates 4
++
++#define kNumAlignBits 4
++#define kAlignTableSize (1 << kNumAlignBits)
++
++#define kMatchMinLen 2
++#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)
++
++#define IsMatch 0
++#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
++#define IsRepG0 (IsRep + kNumStates)
++#define IsRepG1 (IsRepG0 + kNumStates)
++#define IsRepG2 (IsRepG1 + kNumStates)
++#define IsRep0Long (IsRepG2 + kNumStates)
++#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
++#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
++#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
++#define LenCoder (Align + kAlignTableSize)
++#define RepLenCoder (LenCoder + kNumLenProbs)
++#define Literal (RepLenCoder + kNumLenProbs)
++
++#define LZMA_BASE_SIZE 1846
++#define LZMA_LIT_SIZE 768
++
++#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp)))
++
++#if Literal != LZMA_BASE_SIZE
++StopCompilingDueBUG
++#endif
++
++#define LZMA_DIC_MIN (1 << 12)
++
++/* First LZMA-symbol is always decoded.
++And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization
++Out:
++  Result:
++    SZ_OK - OK
++    SZ_ERROR_DATA - Error
++  p->remainLen:
++    < kMatchSpecLenStart : normal remain
++    = kMatchSpecLenStart : finished
++    = kMatchSpecLenStart + 1 : Flush marker
++    = kMatchSpecLenStart + 2 : State Init Marker
++*/
++
++static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit)
++{
++  CLzmaProb *probs = p->probs;
++
++  unsigned state = p->state;
++  UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3];
++  unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1;
++  unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1;
++  unsigned lc = p->prop.lc;
++
++  Byte *dic = p->dic;
++  SizeT dicBufSize = p->dicBufSize;
++  SizeT dicPos = p->dicPos;
++
++  UInt32 processedPos = p->processedPos;
++  UInt32 checkDicSize = p->checkDicSize;
++  unsigned len = 0;
++
++  const Byte *buf = p->buf;
++  UInt32 range = p->range;
++  UInt32 code = p->code;
++
++  do
++  {
++    CLzmaProb *prob;
++    UInt32 bound;
++    unsigned ttt;
++    unsigned posState = processedPos & pbMask;
++
++    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;
++    IF_BIT_0(prob)
++    {
++      unsigned symbol;
++      UPDATE_0(prob);
++      prob = probs + Literal;
++      if (checkDicSize != 0 || processedPos != 0)
++        prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) +
++        (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc))));
++
++      if (state < kNumLitStates)
++      {
++        state -= (state < 4) ? state : 3;
++        symbol = 1;
++        do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);
++      }
++      else
++      {
++        unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];
++        unsigned offs = 0x100;
++        state -= (state < 10) ? 3 : 6;
++        symbol = 1;
++        do
++        {
++          unsigned bit;
++          CLzmaProb *probLit;
++          matchByte <<= 1;
++          bit = (matchByte & offs);
++          probLit = prob + offs + bit + symbol;
++          GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit)
++        }
++        while (symbol < 0x100);
++      }
++      dic[dicPos++] = (Byte)symbol;
++      processedPos++;
++      continue;
++    }
++    else
++    {
++      UPDATE_1(prob);
++      prob = probs + IsRep + state;
++      IF_BIT_0(prob)
++      {
++        UPDATE_0(prob);
++        state += kNumStates;
++        prob = probs + LenCoder;
++      }
++      else
++      {
++        UPDATE_1(prob);
++        if (checkDicSize == 0 && processedPos == 0)
++          return SZ_ERROR_DATA;
++        prob = probs + IsRepG0 + state;
++        IF_BIT_0(prob)
++        {
++          UPDATE_0(prob);
++          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;
++          IF_BIT_0(prob)
++          {
++            UPDATE_0(prob);
++            dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];
++            dicPos++;
++            processedPos++;
++            state = state < kNumLitStates ? 9 : 11;
++            continue;
++          }
++          UPDATE_1(prob);
++        }
++        else
++        {
++          UInt32 distance;
++          UPDATE_1(prob);
++          prob = probs + IsRepG1 + state;
++          IF_BIT_0(prob)
++          {
++            UPDATE_0(prob);
++            distance = rep1;
++          }
++          else
++          {
++            UPDATE_1(prob);
++            prob = probs + IsRepG2 + state;
++            IF_BIT_0(prob)
++            {
++              UPDATE_0(prob);
++              distance = rep2;
++            }
++            else
++            {
++              UPDATE_1(prob);
++              distance = rep3;
++              rep3 = rep2;
++            }
++            rep2 = rep1;
++          }
++          rep1 = rep0;
++          rep0 = distance;
++        }
++        state = state < kNumLitStates ? 8 : 11;
++        prob = probs + RepLenCoder;
++      }
++      {
++        unsigned limit, offset;
++        CLzmaProb *probLen = prob + LenChoice;
++        IF_BIT_0(probLen)
++        {
++          UPDATE_0(probLen);
++          probLen = prob + LenLow + (posState << kLenNumLowBits);
++          offset = 0;
++          limit = (1 << kLenNumLowBits);
++        }
++        else
++        {
++          UPDATE_1(probLen);
++          probLen = prob + LenChoice2;
++          IF_BIT_0(probLen)
++          {
++            UPDATE_0(probLen);
++            probLen = prob + LenMid + (posState << kLenNumMidBits);
++            offset = kLenNumLowSymbols;
++            limit = (1 << kLenNumMidBits);
++          }
++          else
++          {
++            UPDATE_1(probLen);
++            probLen = prob + LenHigh;
++            offset = kLenNumLowSymbols + kLenNumMidSymbols;
++            limit = (1 << kLenNumHighBits);
++          }
++        }
++        TREE_DECODE(probLen, limit, len);
++        len += offset;
++      }
++
++      if (state >= kNumStates)
++      {
++        UInt32 distance;
++        prob = probs + PosSlot +
++            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits);
++        TREE_6_DECODE(prob, distance);
++        if (distance >= kStartPosModelIndex)
++        {
++          unsigned posSlot = (unsigned)distance;
++          int numDirectBits = (int)(((distance >> 1) - 1));
++          distance = (2 | (distance & 1));
++          if (posSlot < kEndPosModelIndex)
++          {
++            distance <<= numDirectBits;
++            prob = probs + SpecPos + distance - posSlot - 1;
++            {
++              UInt32 mask = 1;
++              unsigned i = 1;
++              do
++              {
++                GET_BIT2(prob + i, i, ; , distance |= mask);
++                mask <<= 1;
++              }
++              while (--numDirectBits != 0);
++            }
++          }
++          else
++          {
++            numDirectBits -= kNumAlignBits;
++            do
++            {
++              NORMALIZE
++              range >>= 1;
++
++              {
++                UInt32 t;
++                code -= range;
++                t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */
++                distance = (distance << 1) + (t + 1);
++                code += range & t;
++              }
++              /*
++              distance <<= 1;
++              if (code >= range)
++              {
++                code -= range;
++                distance |= 1;
++              }
++              */
++            }
++            while (--numDirectBits != 0);
++            prob = probs + Align;
++            distance <<= kNumAlignBits;
++            {
++              unsigned i = 1;
++              GET_BIT2(prob + i, i, ; , distance |= 1);
++              GET_BIT2(prob + i, i, ; , distance |= 2);
++              GET_BIT2(prob + i, i, ; , distance |= 4);
++              GET_BIT2(prob + i, i, ; , distance |= 8);
++            }
++            if (distance == (UInt32)0xFFFFFFFF)
++            {
++              len += kMatchSpecLenStart;
++              state -= kNumStates;
++              break;
++            }
++          }
++        }
++        rep3 = rep2;
++        rep2 = rep1;
++        rep1 = rep0;
++        rep0 = distance + 1;
++        if (checkDicSize == 0)
++        {
++          if (distance >= processedPos)
++            return SZ_ERROR_DATA;
++        }
++        else if (distance >= checkDicSize)
++          return SZ_ERROR_DATA;
++        state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3;
++      }
++
++      len += kMatchMinLen;
++
++      if (limit == dicPos)
++        return SZ_ERROR_DATA;
++      {
++        SizeT rem = limit - dicPos;
++        unsigned curLen = ((rem < len) ? (unsigned)rem : len);
++        SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0);
++
++        processedPos += curLen;
++
++        len -= curLen;
++        if (pos + curLen <= dicBufSize)
++        {
++          Byte *dest = dic + dicPos;
++          ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos;
++          const Byte *lim = dest + curLen;
++          dicPos += curLen;
++          do
++            *(dest) = (Byte)*(dest + src);
++          while (++dest != lim);
++        }
++        else
++        {
++          do
++          {
++            dic[dicPos++] = dic[pos];
++            if (++pos == dicBufSize)
++              pos = 0;
++          }
++          while (--curLen != 0);
++        }
++      }
++    }
++  }
++  while (dicPos < limit && buf < bufLimit);
++  NORMALIZE;
++  p->buf = buf;
++  p->range = range;
++  p->code = code;
++  p->remainLen = len;
++  p->dicPos = dicPos;
++  p->processedPos = processedPos;
++  p->reps[0] = rep0;
++  p->reps[1] = rep1;
++  p->reps[2] = rep2;
++  p->reps[3] = rep3;
++  p->state = state;
++
++  return SZ_OK;
++}
++
++static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit)
++{
++  if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart)
++  {
++    Byte *dic = p->dic;
++    SizeT dicPos = p->dicPos;
++    SizeT dicBufSize = p->dicBufSize;
++    unsigned len = p->remainLen;
++    UInt32 rep0 = p->reps[0];
++    if (limit - dicPos < len)
++      len = (unsigned)(limit - dicPos);
++
++    if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len)
++      p->checkDicSize = p->prop.dicSize;
++
++    p->processedPos += len;
++    p->remainLen -= len;
++    while (len-- != 0)
++    {
++      dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];
++      dicPos++;
++    }
++    p->dicPos = dicPos;
++  }
++}
++
++static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit)
++{
++  do
++  {
++    SizeT limit2 = limit;
++    if (p->checkDicSize == 0)
++    {
++      UInt32 rem = p->prop.dicSize - p->processedPos;
++      if (limit - p->dicPos > rem)
++        limit2 = p->dicPos + rem;
++    }
++    RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit));
++    if (p->processedPos >= p->prop.dicSize)
++      p->checkDicSize = p->prop.dicSize;
++    LzmaDec_WriteRem(p, limit);
++  }
++  while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart);
++
++  if (p->remainLen > kMatchSpecLenStart)
++  {
++    p->remainLen = kMatchSpecLenStart;
++  }
++  return 0;
++}
++
++typedef enum
++{
++  DUMMY_ERROR, /* unexpected end of input stream */
++  DUMMY_LIT,
++  DUMMY_MATCH,
++  DUMMY_REP
++} ELzmaDummy;
++
++static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize)
++{
++  UInt32 range = p->range;
++  UInt32 code = p->code;
++  const Byte *bufLimit = buf + inSize;
++  CLzmaProb *probs = p->probs;
++  unsigned state = p->state;
++  ELzmaDummy res;
++
++  {
++    CLzmaProb *prob;
++    UInt32 bound;
++    unsigned ttt;
++    unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1);
++
++    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;
++    IF_BIT_0_CHECK(prob)
++    {
++      UPDATE_0_CHECK
++
++      /* if (bufLimit - buf >= 7) return DUMMY_LIT; */
++
++      prob = probs + Literal;
++      if (p->checkDicSize != 0 || p->processedPos != 0)
++        prob += (LZMA_LIT_SIZE *
++          ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) +
++          (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc))));
++
++      if (state < kNumLitStates)
++      {
++        unsigned symbol = 1;
++        do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100);
++      }
++      else
++      {
++        unsigned matchByte = p->dic[p->dicPos - p->reps[0] +
++            ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)];
++        unsigned offs = 0x100;
++        unsigned symbol = 1;
++        do
++        {
++          unsigned bit;
++          CLzmaProb *probLit;
++          matchByte <<= 1;
++          bit = (matchByte & offs);
++          probLit = prob + offs + bit + symbol;
++          GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit)
++        }
++        while (symbol < 0x100);
++      }
++      res = DUMMY_LIT;
++    }
++    else
++    {
++      unsigned len;
++      UPDATE_1_CHECK;
++
++      prob = probs + IsRep + state;
++      IF_BIT_0_CHECK(prob)
++      {
++        UPDATE_0_CHECK;
++        state = 0;
++        prob = probs + LenCoder;
++        res = DUMMY_MATCH;
++      }
++      else
++      {
++        UPDATE_1_CHECK;
++        res = DUMMY_REP;
++        prob = probs + IsRepG0 + state;
++        IF_BIT_0_CHECK(prob)
++        {
++          UPDATE_0_CHECK;
++          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;
++          IF_BIT_0_CHECK(prob)
++          {
++            UPDATE_0_CHECK;
++            NORMALIZE_CHECK;
++            return DUMMY_REP;
++          }
++          else
++          {
++            UPDATE_1_CHECK;
++          }
++        }
++        else
++        {
++          UPDATE_1_CHECK;
++          prob = probs + IsRepG1 + state;
++          IF_BIT_0_CHECK(prob)
++          {
++            UPDATE_0_CHECK;
++          }
++          else
++          {
++            UPDATE_1_CHECK;
++            prob = probs + IsRepG2 + state;
++            IF_BIT_0_CHECK(prob)
++            {
++              UPDATE_0_CHECK;
++            }
++            else
++            {
++              UPDATE_1_CHECK;
++            }
++          }
++        }
++        state = kNumStates;
++        prob = probs + RepLenCoder;
++      }
++      {
++        unsigned limit, offset;
++        CLzmaProb *probLen = prob + LenChoice;
++        IF_BIT_0_CHECK(probLen)
++        {
++          UPDATE_0_CHECK;
++          probLen = prob + LenLow + (posState << kLenNumLowBits);
++          offset = 0;
++          limit = 1 << kLenNumLowBits;
++        }
++        else
++        {
++          UPDATE_1_CHECK;
++          probLen = prob + LenChoice2;
++          IF_BIT_0_CHECK(probLen)
++          {
++            UPDATE_0_CHECK;
++            probLen = prob + LenMid + (posState << kLenNumMidBits);
++            offset = kLenNumLowSymbols;
++            limit = 1 << kLenNumMidBits;
++          }
++          else
++          {
++            UPDATE_1_CHECK;
++            probLen = prob + LenHigh;
++            offset = kLenNumLowSymbols + kLenNumMidSymbols;
++            limit = 1 << kLenNumHighBits;
++          }
++        }
++        TREE_DECODE_CHECK(probLen, limit, len);
++        len += offset;
++      }
++
++      if (state < 4)
++      {
++        unsigned posSlot;
++        prob = probs + PosSlot +
++            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
++            kNumPosSlotBits);
++        TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot);
++        if (posSlot >= kStartPosModelIndex)
++        {
++          int numDirectBits = ((posSlot >> 1) - 1);
++
++          /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */
++
++          if (posSlot < kEndPosModelIndex)
++          {
++            prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1;
++          }
++          else
++          {
++            numDirectBits -= kNumAlignBits;
++            do
++            {
++              NORMALIZE_CHECK
++              range >>= 1;
++              code -= range & (((code - range) >> 31) - 1);
++              /* if (code >= range) code -= range; */
++            }
++            while (--numDirectBits != 0);
++            prob = probs + Align;
++            numDirectBits = kNumAlignBits;
++          }
++          {
++            unsigned i = 1;
++            do
++            {
++              GET_BIT_CHECK(prob + i, i);
++            }
++            while (--numDirectBits != 0);
++          }
++        }
++      }
++    }
++  }
++  NORMALIZE_CHECK;
++  return res;
++}
++
++
++static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)
++{
++  p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);
++  p->range = 0xFFFFFFFF;
++  p->needFlush = 0;
++}
++
++void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)
++{
++  p->needFlush = 1;
++  p->remainLen = 0;
++  p->tempBufSize = 0;
++
++  if (initDic)
++  {
++    p->processedPos = 0;
++    p->checkDicSize = 0;
++    p->needInitState = 1;
++  }
++  if (initState)
++    p->needInitState = 1;
++}
++
++void LzmaDec_Init(CLzmaDec *p)
++{
++  p->dicPos = 0;
++  LzmaDec_InitDicAndState(p, True, True);
++}
++
++static void LzmaDec_InitStateReal(CLzmaDec *p)
++{
++  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp));
++  UInt32 i;
++  CLzmaProb *probs = p->probs;
++  for (i = 0; i < numProbs; i++)
++    probs[i] = kBitModelTotal >> 1;
++  p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1;
++  p->state = 0;
++  p->needInitState = 0;
++}
++
++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,
++    ELzmaFinishMode finishMode, ELzmaStatus *status)
++{
++  SizeT inSize = *srcLen;
++  (*srcLen) = 0;
++  LzmaDec_WriteRem(p, dicLimit);
++
++  *status = LZMA_STATUS_NOT_SPECIFIED;
++
++  while (p->remainLen != kMatchSpecLenStart)
++  {
++      int checkEndMarkNow;
++
++      if (p->needFlush != 0)
++      {
++        for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--)
++          p->tempBuf[p->tempBufSize++] = *src++;
++        if (p->tempBufSize < RC_INIT_SIZE)
++        {
++          *status = LZMA_STATUS_NEEDS_MORE_INPUT;
++          return SZ_OK;
++        }
++        if (p->tempBuf[0] != 0)
++          return SZ_ERROR_DATA;
++
++        LzmaDec_InitRc(p, p->tempBuf);
++        p->tempBufSize = 0;
++      }
++
++      checkEndMarkNow = 0;
++      if (p->dicPos >= dicLimit)
++      {
++        if (p->remainLen == 0 && p->code == 0)
++        {
++          *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK;
++          return SZ_OK;
++        }
++        if (finishMode == LZMA_FINISH_ANY)
++        {
++          *status = LZMA_STATUS_NOT_FINISHED;
++          return SZ_OK;
++        }
++        if (p->remainLen != 0)
++        {
++          *status = LZMA_STATUS_NOT_FINISHED;
++          return SZ_ERROR_DATA;
++        }
++        checkEndMarkNow = 1;
++      }
++
++      if (p->needInitState)
++        LzmaDec_InitStateReal(p);
++
++      if (p->tempBufSize == 0)
++      {
++        SizeT processed;
++        const Byte *bufLimit;
++        if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)
++        {
++          int dummyRes = LzmaDec_TryDummy(p, src, inSize);
++          if (dummyRes == DUMMY_ERROR)
++          {
++            memcpy(p->tempBuf, src, inSize);
++            p->tempBufSize = (unsigned)inSize;
++            (*srcLen) += inSize;
++            *status = LZMA_STATUS_NEEDS_MORE_INPUT;
++            return SZ_OK;
++          }
++          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)
++          {
++            *status = LZMA_STATUS_NOT_FINISHED;
++            return SZ_ERROR_DATA;
++          }
++          bufLimit = src;
++        }
++        else
++          bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX;
++        p->buf = src;
++        if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0)
++          return SZ_ERROR_DATA;
++        processed = (SizeT)(p->buf - src);
++        (*srcLen) += processed;
++        src += processed;
++        inSize -= processed;
++      }
++      else
++      {
++        unsigned rem = p->tempBufSize, lookAhead = 0;
++        while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize)
++          p->tempBuf[rem++] = src[lookAhead++];
++        p->tempBufSize = rem;
++        if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)
++        {
++          int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem);
++          if (dummyRes == DUMMY_ERROR)
++          {
++            (*srcLen) += lookAhead;
++            *status = LZMA_STATUS_NEEDS_MORE_INPUT;
++            return SZ_OK;
++          }
++          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)
++          {
++            *status = LZMA_STATUS_NOT_FINISHED;
++            return SZ_ERROR_DATA;
++          }
++        }
++        p->buf = p->tempBuf;
++        if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0)
++          return SZ_ERROR_DATA;
++        lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf));
++        (*srcLen) += lookAhead;
++        src += lookAhead;
++        inSize -= lookAhead;
++        p->tempBufSize = 0;
++      }
++  }
++  if (p->code == 0)
++    *status = LZMA_STATUS_FINISHED_WITH_MARK;
++  return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;
++}
++
++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)
++{
++  SizeT outSize = *destLen;
++  SizeT inSize = *srcLen;
++  *srcLen = *destLen = 0;
++  for (;;)
++  {
++    SizeT inSizeCur = inSize, outSizeCur, dicPos;
++    ELzmaFinishMode curFinishMode;
++    SRes res;
++    if (p->dicPos == p->dicBufSize)
++      p->dicPos = 0;
++    dicPos = p->dicPos;
++    if (outSize > p->dicBufSize - dicPos)
++    {
++      outSizeCur = p->dicBufSize;
++      curFinishMode = LZMA_FINISH_ANY;
++    }
++    else
++    {
++      outSizeCur = dicPos + outSize;
++      curFinishMode = finishMode;
++    }
++
++    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);
++    src += inSizeCur;
++    inSize -= inSizeCur;
++    *srcLen += inSizeCur;
++    outSizeCur = p->dicPos - dicPos;
++    memcpy(dest, p->dic + dicPos, outSizeCur);
++    dest += outSizeCur;
++    outSize -= outSizeCur;
++    *destLen += outSizeCur;
++    if (res != 0)
++      return res;
++    if (outSizeCur == 0 || outSize == 0)
++      return SZ_OK;
++  }
++}
++
++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)
++{
++  alloc->Free(alloc, p->probs);
++  p->probs = 0;
++}
++
++static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)
++{
++  alloc->Free(alloc, p->dic);
++  p->dic = 0;
++}
++
++void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)
++{
++  LzmaDec_FreeProbs(p, alloc);
++  LzmaDec_FreeDict(p, alloc);
++}
++
++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)
++{
++  UInt32 dicSize;
++  Byte d;
++
++  if (size < LZMA_PROPS_SIZE)
++    return SZ_ERROR_UNSUPPORTED;
++  else
++    dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);
++
++  if (dicSize < LZMA_DIC_MIN)
++    dicSize = LZMA_DIC_MIN;
++  p->dicSize = dicSize;
++
++  d = data[0];
++  if (d >= (9 * 5 * 5))
++    return SZ_ERROR_UNSUPPORTED;
++
++  p->lc = d % 9;
++  d /= 9;
++  p->pb = d / 5;
++  p->lp = d % 5;
++
++  return SZ_OK;
++}
++
++static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc)
++{
++  UInt32 numProbs = LzmaProps_GetNumProbs(propNew);
++  if (p->probs == 0 || numProbs != p->numProbs)
++  {
++    LzmaDec_FreeProbs(p, alloc);
++    p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb));
++    p->numProbs = numProbs;
++    if (p->probs == 0)
++      return SZ_ERROR_MEM;
++  }
++  return SZ_OK;
++}
++
++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
++{
++  CLzmaProps propNew;
++  RINOK(LzmaProps_Decode(&propNew, props, propsSize));
++  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));
++  p->prop = propNew;
++  return SZ_OK;
++}
++
++SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)
++{
++  CLzmaProps propNew;
++  SizeT dicBufSize;
++  RINOK(LzmaProps_Decode(&propNew, props, propsSize));
++  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));
++  dicBufSize = propNew.dicSize;
++  if (p->dic == 0 || dicBufSize != p->dicBufSize)
++  {
++    LzmaDec_FreeDict(p, alloc);
++    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);
++    if (p->dic == 0)
++    {
++      LzmaDec_FreeProbs(p, alloc);
++      return SZ_ERROR_MEM;
++    }
++  }
++  p->dicBufSize = dicBufSize;
++  p->prop = propNew;
++  return SZ_OK;
++}
++
++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,
++    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,
++    ELzmaStatus *status, ISzAlloc *alloc)
++{
++  CLzmaDec p;
++  SRes res;
++  SizeT inSize = *srcLen;
++  SizeT outSize = *destLen;
++  *srcLen = *destLen = 0;
++  if (inSize < RC_INIT_SIZE)
++    return SZ_ERROR_INPUT_EOF;
++
++  LzmaDec_Construct(&p);
++  res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc);
++  if (res != 0)
++    return res;
++  p.dic = dest;
++  p.dicBufSize = outSize;
++
++  LzmaDec_Init(&p);
++
++  *srcLen = inSize;
++  res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);
++
++  if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT)
++    res = SZ_ERROR_INPUT_EOF;
++
++  (*destLen) = p.dicPos;
++  LzmaDec_FreeProbs(&p, alloc);
++  return res;
++}
+--- /dev/null
++++ b/lib/lzma/LzmaEnc.c
+@@ -0,0 +1,2271 @@
++/* LzmaEnc.c -- LZMA Encoder
++2009-11-24 : Igor Pavlov : Public domain */
++
++#include <string.h>
++
++/* #define SHOW_STAT */
++/* #define SHOW_STAT2 */
++
++#if defined(SHOW_STAT) || defined(SHOW_STAT2)
++#include <stdio.h>
++#endif
++
++#include "LzmaEnc.h"
++
++/* disable MT */
++#define _7ZIP_ST
++
++#include "LzFind.h"
++#ifndef _7ZIP_ST
++#include "LzFindMt.h"
++#endif
++
++#ifdef SHOW_STAT
++static int ttt = 0;
++#endif
++
++#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1)
++
++#define kBlockSize (9 << 10)
++#define kUnpackBlockSize (1 << 18)
++#define kMatchArraySize (1 << 21)
++#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX)
++
++#define kNumMaxDirectBits (31)
++
++#define kNumTopBits 24
++#define kTopValue ((UInt32)1 << kNumTopBits)
++
++#define kNumBitModelTotalBits 11
++#define kBitModelTotal (1 << kNumBitModelTotalBits)
++#define kNumMoveBits 5
++#define kProbInitValue (kBitModelTotal >> 1)
++
++#define kNumMoveReducingBits 4
++#define kNumBitPriceShiftBits 4
++#define kBitPrice (1 << kNumBitPriceShiftBits)
++
++void LzmaEncProps_Init(CLzmaEncProps *p)
++{
++  p->level = 5;
++  p->dictSize = p->mc = 0;
++  p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1;
++  p->writeEndMark = 0;
++}
++
++void LzmaEncProps_Normalize(CLzmaEncProps *p)
++{
++  int level = p->level;
++  if (level < 0) level = 5;
++  p->level = level;
++  if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26)));
++  if (p->lc < 0) p->lc = 3;
++  if (p->lp < 0) p->lp = 0;
++  if (p->pb < 0) p->pb = 2;
++  if (p->algo < 0) p->algo = (level < 5 ? 0 : 1);
++  if (p->fb < 0) p->fb = (level < 7 ? 32 : 64);
++  if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1);
++  if (p->numHashBytes < 0) p->numHashBytes = 4;
++  if (p->mc == 0)  p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1);
++  if (p->numThreads < 0)
++    p->numThreads =
++      #ifndef _7ZIP_ST
++      ((p->btMode && p->algo) ? 2 : 1);
++      #else
++      1;
++      #endif
++}
++
++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)
++{
++  CLzmaEncProps props = *props2;
++  LzmaEncProps_Normalize(&props);
++  return props.dictSize;
++}
++
++/* #define LZMA_LOG_BSR */
++/* Define it for Intel's CPU */
++
++
++#ifdef LZMA_LOG_BSR
++
++#define kDicLogSizeMaxCompress 30
++
++#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }
++
++UInt32 GetPosSlot1(UInt32 pos)
++{
++  UInt32 res;
++  BSR2_RET(pos, res);
++  return res;
++}
++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }
++#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); }
++
++#else
++
++#define kNumLogBits (9 + (int)sizeof(size_t) / 2)
++#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)
++
++void LzmaEnc_FastPosInit(Byte *g_FastPos)
++{
++  int c = 2, slotFast;
++  g_FastPos[0] = 0;
++  g_FastPos[1] = 1;
++
++  for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++)
++  {
++    UInt32 k = (1 << ((slotFast >> 1) - 1));
++    UInt32 j;
++    for (j = 0; j < k; j++, c++)
++      g_FastPos[c] = (Byte)slotFast;
++  }
++}
++
++#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \
++  (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \
++  res = p->g_FastPos[pos >> i] + (i * 2); }
++/*
++#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \
++  p->g_FastPos[pos >> 6] + 12 : \
++  p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; }
++*/
++
++#define GetPosSlot1(pos) p->g_FastPos[pos]
++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }
++#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); }
++
++#endif
++
++
++#define LZMA_NUM_REPS 4
++
++typedef unsigned CState;
++
++typedef struct
++{
++  UInt32 price;
++
++  CState state;
++  int prev1IsChar;
++  int prev2;
++
++  UInt32 posPrev2;
++  UInt32 backPrev2;
++
++  UInt32 posPrev;
++  UInt32 backPrev;
++  UInt32 backs[LZMA_NUM_REPS];
++} COptimal;
++
++#define kNumOpts (1 << 12)
++
++#define kNumLenToPosStates 4
++#define kNumPosSlotBits 6
++#define kDicLogSizeMin 0
++#define kDicLogSizeMax 32
++#define kDistTableSizeMax (kDicLogSizeMax * 2)
++
++
++#define kNumAlignBits 4
++#define kAlignTableSize (1 << kNumAlignBits)
++#define kAlignMask (kAlignTableSize - 1)
++
++#define kStartPosModelIndex 4
++#define kEndPosModelIndex 14
++#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex)
++
++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
++
++#ifdef _LZMA_PROB32
++#define CLzmaProb UInt32
++#else
++#define CLzmaProb UInt16
++#endif
++
++#define LZMA_PB_MAX 4
++#define LZMA_LC_MAX 8
++#define LZMA_LP_MAX 4
++
++#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX)
++
++
++#define kLenNumLowBits 3
++#define kLenNumLowSymbols (1 << kLenNumLowBits)
++#define kLenNumMidBits 3
++#define kLenNumMidSymbols (1 << kLenNumMidBits)
++#define kLenNumHighBits 8
++#define kLenNumHighSymbols (1 << kLenNumHighBits)
++
++#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)
++
++#define LZMA_MATCH_LEN_MIN 2
++#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1)
++
++#define kNumStates 12
++
++typedef struct
++{
++  CLzmaProb choice;
++  CLzmaProb choice2;
++  CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits];
++  CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits];
++  CLzmaProb high[kLenNumHighSymbols];
++} CLenEnc;
++
++typedef struct
++{
++  CLenEnc p;
++  UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal];
++  UInt32 tableSize;
++  UInt32 counters[LZMA_NUM_PB_STATES_MAX];
++} CLenPriceEnc;
++
++typedef struct
++{
++  UInt32 range;
++  Byte cache;
++  UInt64 low;
++  UInt64 cacheSize;
++  Byte *buf;
++  Byte *bufLim;
++  Byte *bufBase;
++  ISeqOutStream *outStream;
++  UInt64 processed;
++  SRes res;
++} CRangeEnc;
++
++typedef struct
++{
++  CLzmaProb *litProbs;
++
++  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];
++  CLzmaProb isRep[kNumStates];
++  CLzmaProb isRepG0[kNumStates];
++  CLzmaProb isRepG1[kNumStates];
++  CLzmaProb isRepG2[kNumStates];
++  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];
++
++  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];
++  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];
++  CLzmaProb posAlignEncoder[1 << kNumAlignBits];
++
++  CLenPriceEnc lenEnc;
++  CLenPriceEnc repLenEnc;
++
++  UInt32 reps[LZMA_NUM_REPS];
++  UInt32 state;
++} CSaveState;
++
++typedef struct
++{
++  IMatchFinder matchFinder;
++  void *matchFinderObj;
++
++  #ifndef _7ZIP_ST
++  Bool mtMode;
++  CMatchFinderMt matchFinderMt;
++  #endif
++
++  CMatchFinder matchFinderBase;
++
++  #ifndef _7ZIP_ST
++  Byte pad[128];
++  #endif
++
++  UInt32 optimumEndIndex;
++  UInt32 optimumCurrentIndex;
++
++  UInt32 longestMatchLength;
++  UInt32 numPairs;
++  UInt32 numAvail;
++  COptimal opt[kNumOpts];
++
++  #ifndef LZMA_LOG_BSR
++  Byte g_FastPos[1 << kNumLogBits];
++  #endif
++
++  UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
++  UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1];
++  UInt32 numFastBytes;
++  UInt32 additionalOffset;
++  UInt32 reps[LZMA_NUM_REPS];
++  UInt32 state;
++
++  UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];
++  UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances];
++  UInt32 alignPrices[kAlignTableSize];
++  UInt32 alignPriceCount;
++
++  UInt32 distTableSize;
++
++  unsigned lc, lp, pb;
++  unsigned lpMask, pbMask;
++
++  CLzmaProb *litProbs;
++
++  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];
++  CLzmaProb isRep[kNumStates];
++  CLzmaProb isRepG0[kNumStates];
++  CLzmaProb isRepG1[kNumStates];
++  CLzmaProb isRepG2[kNumStates];
++  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];
++
++  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];
++  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];
++  CLzmaProb posAlignEncoder[1 << kNumAlignBits];
++
++  CLenPriceEnc lenEnc;
++  CLenPriceEnc repLenEnc;
++
++  unsigned lclp;
++
++  Bool fastMode;
++
++  CRangeEnc rc;
++
++  Bool writeEndMark;
++  UInt64 nowPos64;
++  UInt32 matchPriceCount;
++  Bool finished;
++  Bool multiThread;
++
++  SRes result;
++  UInt32 dictSize;
++  UInt32 matchFinderCycles;
++
++  int needInit;
++
++  CSaveState saveState;
++} CLzmaEnc;
++
++void LzmaEnc_SaveState(CLzmaEncHandle pp)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  CSaveState *dest = &p->saveState;
++  int i;
++  dest->lenEnc = p->lenEnc;
++  dest->repLenEnc = p->repLenEnc;
++  dest->state = p->state;
++
++  for (i = 0; i < kNumStates; i++)
++  {
++    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));
++    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));
++  }
++  for (i = 0; i < kNumLenToPosStates; i++)
++    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));
++  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));
++  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));
++  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));
++  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));
++  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));
++  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));
++  memcpy(dest->reps, p->reps, sizeof(p->reps));
++  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));
++}
++
++void LzmaEnc_RestoreState(CLzmaEncHandle pp)
++{
++  CLzmaEnc *dest = (CLzmaEnc *)pp;
++  const CSaveState *p = &dest->saveState;
++  int i;
++  dest->lenEnc = p->lenEnc;
++  dest->repLenEnc = p->repLenEnc;
++  dest->state = p->state;
++
++  for (i = 0; i < kNumStates; i++)
++  {
++    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));
++    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));
++  }
++  for (i = 0; i < kNumLenToPosStates; i++)
++    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));
++  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));
++  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));
++  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));
++  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));
++  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));
++  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));
++  memcpy(dest->reps, p->reps, sizeof(p->reps));
++  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));
++}
++
++SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  CLzmaEncProps props = *props2;
++  LzmaEncProps_Normalize(&props);
++
++  if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX ||
++      props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30))
++    return SZ_ERROR_PARAM;
++  p->dictSize = props.dictSize;
++  p->matchFinderCycles = props.mc;
++  {
++    unsigned fb = props.fb;
++    if (fb < 5)
++      fb = 5;
++    if (fb > LZMA_MATCH_LEN_MAX)
++      fb = LZMA_MATCH_LEN_MAX;
++    p->numFastBytes = fb;
++  }
++  p->lc = props.lc;
++  p->lp = props.lp;
++  p->pb = props.pb;
++  p->fastMode = (props.algo == 0);
++  p->matchFinderBase.btMode = props.btMode;
++  {
++    UInt32 numHashBytes = 4;
++    if (props.btMode)
++    {
++      if (props.numHashBytes < 2)
++        numHashBytes = 2;
++      else if (props.numHashBytes < 4)
++        numHashBytes = props.numHashBytes;
++    }
++    p->matchFinderBase.numHashBytes = numHashBytes;
++  }
++
++  p->matchFinderBase.cutValue = props.mc;
++
++  p->writeEndMark = props.writeEndMark;
++
++  #ifndef _7ZIP_ST
++  /*
++  if (newMultiThread != _multiThread)
++  {
++    ReleaseMatchFinder();
++    _multiThread = newMultiThread;
++  }
++  */
++  p->multiThread = (props.numThreads > 1);
++  #endif
++
++  return SZ_OK;
++}
++
++static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};
++static const int kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};
++static const int kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};
++static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};
++
++#define IsCharState(s) ((s) < 7)
++
++#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1)
++
++#define kInfinityPrice (1 << 30)
++
++static void RangeEnc_Construct(CRangeEnc *p)
++{
++  p->outStream = 0;
++  p->bufBase = 0;
++}
++
++#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize)
++
++#define RC_BUF_SIZE (1 << 16)
++static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc)
++{
++  if (p->bufBase == 0)
++  {
++    p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE);
++    if (p->bufBase == 0)
++      return 0;
++    p->bufLim = p->bufBase + RC_BUF_SIZE;
++  }
++  return 1;
++}
++
++static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc)
++{
++  alloc->Free(alloc, p->bufBase);
++  p->bufBase = 0;
++}
++
++static void RangeEnc_Init(CRangeEnc *p)
++{
++  /* Stream.Init(); */
++  p->low = 0;
++  p->range = 0xFFFFFFFF;
++  p->cacheSize = 1;
++  p->cache = 0;
++
++  p->buf = p->bufBase;
++
++  p->processed = 0;
++  p->res = SZ_OK;
++}
++
++static void RangeEnc_FlushStream(CRangeEnc *p)
++{
++  size_t num;
++  if (p->res != SZ_OK)
++    return;
++  num = p->buf - p->bufBase;
++  if (num != p->outStream->Write(p->outStream, p->bufBase, num))
++    p->res = SZ_ERROR_WRITE;
++  p->processed += num;
++  p->buf = p->bufBase;
++}
++
++static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p)
++{
++  if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0)
++  {
++    Byte temp = p->cache;
++    do
++    {
++      Byte *buf = p->buf;
++      *buf++ = (Byte)(temp + (Byte)(p->low >> 32));
++      p->buf = buf;
++      if (buf == p->bufLim)
++        RangeEnc_FlushStream(p);
++      temp = 0xFF;
++    }
++    while (--p->cacheSize != 0);
++    p->cache = (Byte)((UInt32)p->low >> 24);
++  }
++  p->cacheSize++;
++  p->low = (UInt32)p->low << 8;
++}
++
++static void RangeEnc_FlushData(CRangeEnc *p)
++{
++  int i;
++  for (i = 0; i < 5; i++)
++    RangeEnc_ShiftLow(p);
++}
++
++static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits)
++{
++  do
++  {
++    p->range >>= 1;
++    p->low += p->range & (0 - ((value >> --numBits) & 1));
++    if (p->range < kTopValue)
++    {
++      p->range <<= 8;
++      RangeEnc_ShiftLow(p);
++    }
++  }
++  while (numBits != 0);
++}
++
++static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol)
++{
++  UInt32 ttt = *prob;
++  UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt;
++  if (symbol == 0)
++  {
++    p->range = newBound;
++    ttt += (kBitModelTotal - ttt) >> kNumMoveBits;
++  }
++  else
++  {
++    p->low += newBound;
++    p->range -= newBound;
++    ttt -= ttt >> kNumMoveBits;
++  }
++  *prob = (CLzmaProb)ttt;
++  if (p->range < kTopValue)
++  {
++    p->range <<= 8;
++    RangeEnc_ShiftLow(p);
++  }
++}
++
++static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol)
++{
++  symbol |= 0x100;
++  do
++  {
++    RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1);
++    symbol <<= 1;
++  }
++  while (symbol < 0x10000);
++}
++
++static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte)
++{
++  UInt32 offs = 0x100;
++  symbol |= 0x100;
++  do
++  {
++    matchByte <<= 1;
++    RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1);
++    symbol <<= 1;
++    offs &= ~(matchByte ^ symbol);
++  }
++  while (symbol < 0x10000);
++}
++
++void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)
++{
++  UInt32 i;
++  for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))
++  {
++    const int kCyclesBits = kNumBitPriceShiftBits;
++    UInt32 w = i;
++    UInt32 bitCount = 0;
++    int j;
++    for (j = 0; j < kCyclesBits; j++)
++    {
++      w = w * w;
++      bitCount <<= 1;
++      while (w >= ((UInt32)1 << 16))
++      {
++        w >>= 1;
++        bitCount++;
++      }
++    }
++    ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount);
++  }
++}
++
++
++#define GET_PRICE(prob, symbol) \
++  p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];
++
++#define GET_PRICEa(prob, symbol) \
++  ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];
++
++#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits]
++#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]
++
++#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits]
++#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]
++
++static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices)
++{
++  UInt32 price = 0;
++  symbol |= 0x100;
++  do
++  {
++    price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1);
++    symbol <<= 1;
++  }
++  while (symbol < 0x10000);
++  return price;
++}
++
++static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices)
++{
++  UInt32 price = 0;
++  UInt32 offs = 0x100;
++  symbol |= 0x100;
++  do
++  {
++    matchByte <<= 1;
++    price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1);
++    symbol <<= 1;
++    offs &= ~(matchByte ^ symbol);
++  }
++  while (symbol < 0x10000);
++  return price;
++}
++
++
++static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)
++{
++  UInt32 m = 1;
++  int i;
++  for (i = numBitLevels; i != 0;)
++  {
++    UInt32 bit;
++    i--;
++    bit = (symbol >> i) & 1;
++    RangeEnc_EncodeBit(rc, probs + m, bit);
++    m = (m << 1) | bit;
++  }
++}
++
++static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)
++{
++  UInt32 m = 1;
++  int i;
++  for (i = 0; i < numBitLevels; i++)
++  {
++    UInt32 bit = symbol & 1;
++    RangeEnc_EncodeBit(rc, probs + m, bit);
++    m = (m << 1) | bit;
++    symbol >>= 1;
++  }
++}
++
++static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)
++{
++  UInt32 price = 0;
++  symbol |= (1 << numBitLevels);
++  while (symbol != 1)
++  {
++    price += GET_PRICEa(probs[symbol >> 1], symbol & 1);
++    symbol >>= 1;
++  }
++  return price;
++}
++
++static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)
++{
++  UInt32 price = 0;
++  UInt32 m = 1;
++  int i;
++  for (i = numBitLevels; i != 0; i--)
++  {
++    UInt32 bit = symbol & 1;
++    symbol >>= 1;
++    price += GET_PRICEa(probs[m], bit);
++    m = (m << 1) | bit;
++  }
++  return price;
++}
++
++
++static void LenEnc_Init(CLenEnc *p)
++{
++  unsigned i;
++  p->choice = p->choice2 = kProbInitValue;
++  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++)
++    p->low[i] = kProbInitValue;
++  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++)
++    p->mid[i] = kProbInitValue;
++  for (i = 0; i < kLenNumHighSymbols; i++)
++    p->high[i] = kProbInitValue;
++}
++
++static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState)
++{
++  if (symbol < kLenNumLowSymbols)
++  {
++    RangeEnc_EncodeBit(rc, &p->choice, 0);
++    RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol);
++  }
++  else
++  {
++    RangeEnc_EncodeBit(rc, &p->choice, 1);
++    if (symbol < kLenNumLowSymbols + kLenNumMidSymbols)
++    {
++      RangeEnc_EncodeBit(rc, &p->choice2, 0);
++      RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols);
++    }
++    else
++    {
++      RangeEnc_EncodeBit(rc, &p->choice2, 1);
++      RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols);
++    }
++  }
++}
++
++static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices)
++{
++  UInt32 a0 = GET_PRICE_0a(p->choice);
++  UInt32 a1 = GET_PRICE_1a(p->choice);
++  UInt32 b0 = a1 + GET_PRICE_0a(p->choice2);
++  UInt32 b1 = a1 + GET_PRICE_1a(p->choice2);
++  UInt32 i = 0;
++  for (i = 0; i < kLenNumLowSymbols; i++)
++  {
++    if (i >= numSymbols)
++      return;
++    prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices);
++  }
++  for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++)
++  {
++    if (i >= numSymbols)
++      return;
++    prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices);
++  }
++  for (; i < numSymbols; i++)
++    prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices);
++}
++
++static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices)
++{
++  LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices);
++  p->counters[posState] = p->tableSize;
++}
++
++static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices)
++{
++  UInt32 posState;
++  for (posState = 0; posState < numPosStates; posState++)
++    LenPriceEnc_UpdateTable(p, posState, ProbPrices);
++}
++
++static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices)
++{
++  LenEnc_Encode(&p->p, rc, symbol, posState);
++  if (updatePrice)
++    if (--p->counters[posState] == 0)
++      LenPriceEnc_UpdateTable(p, posState, ProbPrices);
++}
++
++
++
++
++static void MovePos(CLzmaEnc *p, UInt32 num)
++{
++  #ifdef SHOW_STAT
++  ttt += num;
++  printf("\n MovePos %d", num);
++  #endif
++  if (num != 0)
++  {
++    p->additionalOffset += num;
++    p->matchFinder.Skip(p->matchFinderObj, num);
++  }
++}
++
++static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes)
++{
++  UInt32 lenRes = 0, numPairs;
++  p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);
++  numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches);
++  #ifdef SHOW_STAT
++  printf("\n i = %d numPairs = %d    ", ttt, numPairs / 2);
++  ttt++;
++  {
++    UInt32 i;
++    for (i = 0; i < numPairs; i += 2)
++      printf("%2d %6d   | ", p->matches[i], p->matches[i + 1]);
++  }
++  #endif
++  if (numPairs > 0)
++  {
++    lenRes = p->matches[numPairs - 2];
++    if (lenRes == p->numFastBytes)
++    {
++      const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;
++      UInt32 distance = p->matches[numPairs - 1] + 1;
++      UInt32 numAvail = p->numAvail;
++      if (numAvail > LZMA_MATCH_LEN_MAX)
++        numAvail = LZMA_MATCH_LEN_MAX;
++      {
++        const Byte *pby2 = pby - distance;
++        for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++);
++      }
++    }
++  }
++  p->additionalOffset++;
++  *numDistancePairsRes = numPairs;
++  return lenRes;
++}
++
++
++#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False;
++#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False;
++#define IsShortRep(p) ((p)->backPrev == 0)
++
++static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState)
++{
++  return
++    GET_PRICE_0(p->isRepG0[state]) +
++    GET_PRICE_0(p->isRep0Long[state][posState]);
++}
++
++static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState)
++{
++  UInt32 price;
++  if (repIndex == 0)
++  {
++    price = GET_PRICE_0(p->isRepG0[state]);
++    price += GET_PRICE_1(p->isRep0Long[state][posState]);
++  }
++  else
++  {
++    price = GET_PRICE_1(p->isRepG0[state]);
++    if (repIndex == 1)
++      price += GET_PRICE_0(p->isRepG1[state]);
++    else
++    {
++      price += GET_PRICE_1(p->isRepG1[state]);
++      price += GET_PRICE(p->isRepG2[state], repIndex - 2);
++    }
++  }
++  return price;
++}
++
++static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState)
++{
++  return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] +
++    GetPureRepPrice(p, repIndex, state, posState);
++}
++
++static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur)
++{
++  UInt32 posMem = p->opt[cur].posPrev;
++  UInt32 backMem = p->opt[cur].backPrev;
++  p->optimumEndIndex = cur;
++  do
++  {
++    if (p->opt[cur].prev1IsChar)
++    {
++      MakeAsChar(&p->opt[posMem])
++      p->opt[posMem].posPrev = posMem - 1;
++      if (p->opt[cur].prev2)
++      {
++        p->opt[posMem - 1].prev1IsChar = False;
++        p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2;
++        p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2;
++      }
++    }
++    {
++      UInt32 posPrev = posMem;
++      UInt32 backCur = backMem;
++
++      backMem = p->opt[posPrev].backPrev;
++      posMem = p->opt[posPrev].posPrev;
++
++      p->opt[posPrev].backPrev = backCur;
++      p->opt[posPrev].posPrev = cur;
++      cur = posPrev;
++    }
++  }
++  while (cur != 0);
++  *backRes = p->opt[0].backPrev;
++  p->optimumCurrentIndex  = p->opt[0].posPrev;
++  return p->optimumCurrentIndex;
++}
++
++#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300)
++
++static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes)
++{
++  UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur;
++  UInt32 matchPrice, repMatchPrice, normalMatchPrice;
++  UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS];
++  UInt32 *matches;
++  const Byte *data;
++  Byte curByte, matchByte;
++  if (p->optimumEndIndex != p->optimumCurrentIndex)
++  {
++    const COptimal *opt = &p->opt[p->optimumCurrentIndex];
++    UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex;
++    *backRes = opt->backPrev;
++    p->optimumCurrentIndex = opt->posPrev;
++    return lenRes;
++  }
++  p->optimumCurrentIndex = p->optimumEndIndex = 0;
++
++  if (p->additionalOffset == 0)
++    mainLen = ReadMatchDistances(p, &numPairs);
++  else
++  {
++    mainLen = p->longestMatchLength;
++    numPairs = p->numPairs;
++  }
++
++  numAvail = p->numAvail;
++  if (numAvail < 2)
++  {
++    *backRes = (UInt32)(-1);
++    return 1;
++  }
++  if (numAvail > LZMA_MATCH_LEN_MAX)
++    numAvail = LZMA_MATCH_LEN_MAX;
++
++  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;
++  repMaxIndex = 0;
++  for (i = 0; i < LZMA_NUM_REPS; i++)
++  {
++    UInt32 lenTest;
++    const Byte *data2;
++    reps[i] = p->reps[i];
++    data2 = data - (reps[i] + 1);
++    if (data[0] != data2[0] || data[1] != data2[1])
++    {
++      repLens[i] = 0;
++      continue;
++    }
++    for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++);
++    repLens[i] = lenTest;
++    if (lenTest > repLens[repMaxIndex])
++      repMaxIndex = i;
++  }
++  if (repLens[repMaxIndex] >= p->numFastBytes)
++  {
++    UInt32 lenRes;
++    *backRes = repMaxIndex;
++    lenRes = repLens[repMaxIndex];
++    MovePos(p, lenRes - 1);
++    return lenRes;
++  }
++
++  matches = p->matches;
++  if (mainLen >= p->numFastBytes)
++  {
++    *backRes = matches[numPairs - 1] + LZMA_NUM_REPS;
++    MovePos(p, mainLen - 1);
++    return mainLen;
++  }
++  curByte = *data;
++  matchByte = *(data - (reps[0] + 1));
++
++  if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2)
++  {
++    *backRes = (UInt32)-1;
++    return 1;
++  }
++
++  p->opt[0].state = (CState)p->state;
++
++  posState = (position & p->pbMask);
++
++  {
++    const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));
++    p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) +
++        (!IsCharState(p->state) ?
++          LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) :
++          LitEnc_GetPrice(probs, curByte, p->ProbPrices));
++  }
++
++  MakeAsChar(&p->opt[1]);
++
++  matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]);
++  repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]);
++
++  if (matchByte == curByte)
++  {
++    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState);
++    if (shortRepPrice < p->opt[1].price)
++    {
++      p->opt[1].price = shortRepPrice;
++      MakeAsShortRep(&p->opt[1]);
++    }
++  }
++  lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]);
++
++  if (lenEnd < 2)
++  {
++    *backRes = p->opt[1].backPrev;
++    return 1;
++  }
++
++  p->opt[1].posPrev = 0;
++  for (i = 0; i < LZMA_NUM_REPS; i++)
++    p->opt[0].backs[i] = reps[i];
++
++  len = lenEnd;
++  do
++    p->opt[len--].price = kInfinityPrice;
++  while (len >= 2);
++
++  for (i = 0; i < LZMA_NUM_REPS; i++)
++  {
++    UInt32 repLen = repLens[i];
++    UInt32 price;
++    if (repLen < 2)
++      continue;
++    price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState);
++    do
++    {
++      UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2];
++      COptimal *opt = &p->opt[repLen];
++      if (curAndLenPrice < opt->price)
++      {
++        opt->price = curAndLenPrice;
++        opt->posPrev = 0;
++        opt->backPrev = i;
++        opt->prev1IsChar = False;
++      }
++    }
++    while (--repLen >= 2);
++  }
++
++  normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]);
++
++  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);
++  if (len <= mainLen)
++  {
++    UInt32 offs = 0;
++    while (len > matches[offs])
++      offs += 2;
++    for (; ; len++)
++    {
++      COptimal *opt;
++      UInt32 distance = matches[offs + 1];
++
++      UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN];
++      UInt32 lenToPosState = GetLenToPosState(len);
++      if (distance < kNumFullDistances)
++        curAndLenPrice += p->distancesPrices[lenToPosState][distance];
++      else
++      {
++        UInt32 slot;
++        GetPosSlot2(distance, slot);
++        curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot];
++      }
++      opt = &p->opt[len];
++      if (curAndLenPrice < opt->price)
++      {
++        opt->price = curAndLenPrice;
++        opt->posPrev = 0;
++        opt->backPrev = distance + LZMA_NUM_REPS;
++        opt->prev1IsChar = False;
++      }
++      if (len == matches[offs])
++      {
++        offs += 2;
++        if (offs == numPairs)
++          break;
++      }
++    }
++  }
++
++  cur = 0;
++
++    #ifdef SHOW_STAT2
++    if (position >= 0)
++    {
++      unsigned i;
++      printf("\n pos = %4X", position);
++      for (i = cur; i <= lenEnd; i++)
++      printf("\nprice[%4X] = %d", position - cur + i, p->opt[i].price);
++    }
++    #endif
++
++  for (;;)
++  {
++    UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen;
++    UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice;
++    Bool nextIsChar;
++    Byte curByte, matchByte;
++    const Byte *data;
++    COptimal *curOpt;
++    COptimal *nextOpt;
++
++    cur++;
++    if (cur == lenEnd)
++      return Backward(p, backRes, cur);
++
++    newLen = ReadMatchDistances(p, &numPairs);
++    if (newLen >= p->numFastBytes)
++    {
++      p->numPairs = numPairs;
++      p->longestMatchLength = newLen;
++      return Backward(p, backRes, cur);
++    }
++    position++;
++    curOpt = &p->opt[cur];
++    posPrev = curOpt->posPrev;
++    if (curOpt->prev1IsChar)
++    {
++      posPrev--;
++      if (curOpt->prev2)
++      {
++        state = p->opt[curOpt->posPrev2].state;
++        if (curOpt->backPrev2 < LZMA_NUM_REPS)
++          state = kRepNextStates[state];
++        else
++          state = kMatchNextStates[state];
++      }
++      else
++        state = p->opt[posPrev].state;
++      state = kLiteralNextStates[state];
++    }
++    else
++      state = p->opt[posPrev].state;
++    if (posPrev == cur - 1)
++    {
++      if (IsShortRep(curOpt))
++        state = kShortRepNextStates[state];
++      else
++        state = kLiteralNextStates[state];
++    }
++    else
++    {
++      UInt32 pos;
++      const COptimal *prevOpt;
++      if (curOpt->prev1IsChar && curOpt->prev2)
++      {
++        posPrev = curOpt->posPrev2;
++        pos = curOpt->backPrev2;
++        state = kRepNextStates[state];
++      }
++      else
++      {
++        pos = curOpt->backPrev;
++        if (pos < LZMA_NUM_REPS)
++          state = kRepNextStates[state];
++        else
++          state = kMatchNextStates[state];
++      }
++      prevOpt = &p->opt[posPrev];
++      if (pos < LZMA_NUM_REPS)
++      {
++        UInt32 i;
++        reps[0] = prevOpt->backs[pos];
++        for (i = 1; i <= pos; i++)
++          reps[i] = prevOpt->backs[i - 1];
++        for (; i < LZMA_NUM_REPS; i++)
++          reps[i] = prevOpt->backs[i];
++      }
++      else
++      {
++        UInt32 i;
++        reps[0] = (pos - LZMA_NUM_REPS);
++        for (i = 1; i < LZMA_NUM_REPS; i++)
++          reps[i] = prevOpt->backs[i - 1];
++      }
++    }
++    curOpt->state = (CState)state;
++
++    curOpt->backs[0] = reps[0];
++    curOpt->backs[1] = reps[1];
++    curOpt->backs[2] = reps[2];
++    curOpt->backs[3] = reps[3];
++
++    curPrice = curOpt->price;
++    nextIsChar = False;
++    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;
++    curByte = *data;
++    matchByte = *(data - (reps[0] + 1));
++
++    posState = (position & p->pbMask);
++
++    curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]);
++    {
++      const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));
++      curAnd1Price +=
++        (!IsCharState(state) ?
++          LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) :
++          LitEnc_GetPrice(probs, curByte, p->ProbPrices));
++    }
++
++    nextOpt = &p->opt[cur + 1];
++
++    if (curAnd1Price < nextOpt->price)
++    {
++      nextOpt->price = curAnd1Price;
++      nextOpt->posPrev = cur;
++      MakeAsChar(nextOpt);
++      nextIsChar = True;
++    }
++
++    matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]);
++    repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]);
++
++    if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0))
++    {
++      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState);
++      if (shortRepPrice <= nextOpt->price)
++      {
++        nextOpt->price = shortRepPrice;
++        nextOpt->posPrev = cur;
++        MakeAsShortRep(nextOpt);
++        nextIsChar = True;
++      }
++    }
++    numAvailFull = p->numAvail;
++    {
++      UInt32 temp = kNumOpts - 1 - cur;
++      if (temp < numAvailFull)
++        numAvailFull = temp;
++    }
++
++    if (numAvailFull < 2)
++      continue;
++    numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes);
++
++    if (!nextIsChar && matchByte != curByte) /* speed optimization */
++    {
++      /* try Literal + rep0 */
++      UInt32 temp;
++      UInt32 lenTest2;
++      const Byte *data2 = data - (reps[0] + 1);
++      UInt32 limit = p->numFastBytes + 1;
++      if (limit > numAvailFull)
++        limit = numAvailFull;
++
++      for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++);
++      lenTest2 = temp - 1;
++      if (lenTest2 >= 2)
++      {
++        UInt32 state2 = kLiteralNextStates[state];
++        UInt32 posStateNext = (position + 1) & p->pbMask;
++        UInt32 nextRepMatchPrice = curAnd1Price +
++            GET_PRICE_1(p->isMatch[state2][posStateNext]) +
++            GET_PRICE_1(p->isRep[state2]);
++        /* for (; lenTest2 >= 2; lenTest2--) */
++        {
++          UInt32 curAndLenPrice;
++          COptimal *opt;
++          UInt32 offset = cur + 1 + lenTest2;
++          while (lenEnd < offset)
++            p->opt[++lenEnd].price = kInfinityPrice;
++          curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);
++          opt = &p->opt[offset];
++          if (curAndLenPrice < opt->price)
++          {
++            opt->price = curAndLenPrice;
++            opt->posPrev = cur + 1;
++            opt->backPrev = 0;
++            opt->prev1IsChar = True;
++            opt->prev2 = False;
++          }
++        }
++      }
++    }
++
++    startLen = 2; /* speed optimization */
++    {
++    UInt32 repIndex;
++    for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++)
++    {
++      UInt32 lenTest;
++      UInt32 lenTestTemp;
++      UInt32 price;
++      const Byte *data2 = data - (reps[repIndex] + 1);
++      if (data[0] != data2[0] || data[1] != data2[1])
++        continue;
++      for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++);
++      while (lenEnd < cur + lenTest)
++        p->opt[++lenEnd].price = kInfinityPrice;
++      lenTestTemp = lenTest;
++      price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState);
++      do
++      {
++        UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2];
++        COptimal *opt = &p->opt[cur + lenTest];
++        if (curAndLenPrice < opt->price)
++        {
++          opt->price = curAndLenPrice;
++          opt->posPrev = cur;
++          opt->backPrev = repIndex;
++          opt->prev1IsChar = False;
++        }
++      }
++      while (--lenTest >= 2);
++      lenTest = lenTestTemp;
++
++      if (repIndex == 0)
++        startLen = lenTest + 1;
++
++      /* if (_maxMode) */
++        {
++          UInt32 lenTest2 = lenTest + 1;
++          UInt32 limit = lenTest2 + p->numFastBytes;
++          UInt32 nextRepMatchPrice;
++          if (limit > numAvailFull)
++            limit = numAvailFull;
++          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);
++          lenTest2 -= lenTest + 1;
++          if (lenTest2 >= 2)
++          {
++            UInt32 state2 = kRepNextStates[state];
++            UInt32 posStateNext = (position + lenTest) & p->pbMask;
++            UInt32 curAndLenCharPrice =
++                price + p->repLenEnc.prices[posState][lenTest - 2] +
++                GET_PRICE_0(p->isMatch[state2][posStateNext]) +
++                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),
++                    data[lenTest], data2[lenTest], p->ProbPrices);
++            state2 = kLiteralNextStates[state2];
++            posStateNext = (position + lenTest + 1) & p->pbMask;
++            nextRepMatchPrice = curAndLenCharPrice +
++                GET_PRICE_1(p->isMatch[state2][posStateNext]) +
++                GET_PRICE_1(p->isRep[state2]);
++
++            /* for (; lenTest2 >= 2; lenTest2--) */
++            {
++              UInt32 curAndLenPrice;
++              COptimal *opt;
++              UInt32 offset = cur + lenTest + 1 + lenTest2;
++              while (lenEnd < offset)
++                p->opt[++lenEnd].price = kInfinityPrice;
++              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);
++              opt = &p->opt[offset];
++              if (curAndLenPrice < opt->price)
++              {
++                opt->price = curAndLenPrice;
++                opt->posPrev = cur + lenTest + 1;
++                opt->backPrev = 0;
++                opt->prev1IsChar = True;
++                opt->prev2 = True;
++                opt->posPrev2 = cur;
++                opt->backPrev2 = repIndex;
++              }
++            }
++          }
++        }
++    }
++    }
++    /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */
++    if (newLen > numAvail)
++    {
++      newLen = numAvail;
++      for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2);
++      matches[numPairs] = newLen;
++      numPairs += 2;
++    }
++    if (newLen >= startLen)
++    {
++      UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]);
++      UInt32 offs, curBack, posSlot;
++      UInt32 lenTest;
++      while (lenEnd < cur + newLen)
++        p->opt[++lenEnd].price = kInfinityPrice;
++
++      offs = 0;
++      while (startLen > matches[offs])
++        offs += 2;
++      curBack = matches[offs + 1];
++      GetPosSlot2(curBack, posSlot);
++      for (lenTest = /*2*/ startLen; ; lenTest++)
++      {
++        UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN];
++        UInt32 lenToPosState = GetLenToPosState(lenTest);
++        COptimal *opt;
++        if (curBack < kNumFullDistances)
++          curAndLenPrice += p->distancesPrices[lenToPosState][curBack];
++        else
++          curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask];
++
++        opt = &p->opt[cur + lenTest];
++        if (curAndLenPrice < opt->price)
++        {
++          opt->price = curAndLenPrice;
++          opt->posPrev = cur;
++          opt->backPrev = curBack + LZMA_NUM_REPS;
++          opt->prev1IsChar = False;
++        }
++
++        if (/*_maxMode && */lenTest == matches[offs])
++        {
++          /* Try Match + Literal + Rep0 */
++          const Byte *data2 = data - (curBack + 1);
++          UInt32 lenTest2 = lenTest + 1;
++          UInt32 limit = lenTest2 + p->numFastBytes;
++          UInt32 nextRepMatchPrice;
++          if (limit > numAvailFull)
++            limit = numAvailFull;
++          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);
++          lenTest2 -= lenTest + 1;
++          if (lenTest2 >= 2)
++          {
++            UInt32 state2 = kMatchNextStates[state];
++            UInt32 posStateNext = (position + lenTest) & p->pbMask;
++            UInt32 curAndLenCharPrice = curAndLenPrice +
++                GET_PRICE_0(p->isMatch[state2][posStateNext]) +
++                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),
++                    data[lenTest], data2[lenTest], p->ProbPrices);
++            state2 = kLiteralNextStates[state2];
++            posStateNext = (posStateNext + 1) & p->pbMask;
++            nextRepMatchPrice = curAndLenCharPrice +
++                GET_PRICE_1(p->isMatch[state2][posStateNext]) +
++                GET_PRICE_1(p->isRep[state2]);
++
++            /* for (; lenTest2 >= 2; lenTest2--) */
++            {
++              UInt32 offset = cur + lenTest + 1 + lenTest2;
++              UInt32 curAndLenPrice;
++              COptimal *opt;
++              while (lenEnd < offset)
++                p->opt[++lenEnd].price = kInfinityPrice;
++              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);
++              opt = &p->opt[offset];
++              if (curAndLenPrice < opt->price)
++              {
++                opt->price = curAndLenPrice;
++                opt->posPrev = cur + lenTest + 1;
++                opt->backPrev = 0;
++                opt->prev1IsChar = True;
++                opt->prev2 = True;
++                opt->posPrev2 = cur;
++                opt->backPrev2 = curBack + LZMA_NUM_REPS;
++              }
++            }
++          }
++          offs += 2;
++          if (offs == numPairs)
++            break;
++          curBack = matches[offs + 1];
++          if (curBack >= kNumFullDistances)
++            GetPosSlot2(curBack, posSlot);
++        }
++      }
++    }
++  }
++}
++
++#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist))
++
++static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes)
++{
++  UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i;
++  const Byte *data;
++  const UInt32 *matches;
++
++  if (p->additionalOffset == 0)
++    mainLen = ReadMatchDistances(p, &numPairs);
++  else
++  {
++    mainLen = p->longestMatchLength;
++    numPairs = p->numPairs;
++  }
++
++  numAvail = p->numAvail;
++  *backRes = (UInt32)-1;
++  if (numAvail < 2)
++    return 1;
++  if (numAvail > LZMA_MATCH_LEN_MAX)
++    numAvail = LZMA_MATCH_LEN_MAX;
++  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;
++
++  repLen = repIndex = 0;
++  for (i = 0; i < LZMA_NUM_REPS; i++)
++  {
++    UInt32 len;
++    const Byte *data2 = data - (p->reps[i] + 1);
++    if (data[0] != data2[0] || data[1] != data2[1])
++      continue;
++    for (len = 2; len < numAvail && data[len] == data2[len]; len++);
++    if (len >= p->numFastBytes)
++    {
++      *backRes = i;
++      MovePos(p, len - 1);
++      return len;
++    }
++    if (len > repLen)
++    {
++      repIndex = i;
++      repLen = len;
++    }
++  }
++
++  matches = p->matches;
++  if (mainLen >= p->numFastBytes)
++  {
++    *backRes = matches[numPairs - 1] + LZMA_NUM_REPS;
++    MovePos(p, mainLen - 1);
++    return mainLen;
++  }
++
++  mainDist = 0; /* for GCC */
++  if (mainLen >= 2)
++  {
++    mainDist = matches[numPairs - 1];
++    while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1)
++    {
++      if (!ChangePair(matches[numPairs - 3], mainDist))
++        break;
++      numPairs -= 2;
++      mainLen = matches[numPairs - 2];
++      mainDist = matches[numPairs - 1];
++    }
++    if (mainLen == 2 && mainDist >= 0x80)
++      mainLen = 1;
++  }
++
++  if (repLen >= 2 && (
++        (repLen + 1 >= mainLen) ||
++        (repLen + 2 >= mainLen && mainDist >= (1 << 9)) ||
++        (repLen + 3 >= mainLen && mainDist >= (1 << 15))))
++  {
++    *backRes = repIndex;
++    MovePos(p, repLen - 1);
++    return repLen;
++  }
++
++  if (mainLen < 2 || numAvail <= 2)
++    return 1;
++
++  p->longestMatchLength = ReadMatchDistances(p, &p->numPairs);
++  if (p->longestMatchLength >= 2)
++  {
++    UInt32 newDistance = matches[p->numPairs - 1];
++    if ((p->longestMatchLength >= mainLen && newDistance < mainDist) ||
++        (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) ||
++        (p->longestMatchLength > mainLen + 1) ||
++        (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist)))
++      return 1;
++  }
++
++  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;
++  for (i = 0; i < LZMA_NUM_REPS; i++)
++  {
++    UInt32 len, limit;
++    const Byte *data2 = data - (p->reps[i] + 1);
++    if (data[0] != data2[0] || data[1] != data2[1])
++      continue;
++    limit = mainLen - 1;
++    for (len = 2; len < limit && data[len] == data2[len]; len++);
++    if (len >= limit)
++      return 1;
++  }
++  *backRes = mainDist + LZMA_NUM_REPS;
++  MovePos(p, mainLen - 2);
++  return mainLen;
++}
++
++static void WriteEndMarker(CLzmaEnc *p, UInt32 posState)
++{
++  UInt32 len;
++  RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);
++  RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);
++  p->state = kMatchNextStates[p->state];
++  len = LZMA_MATCH_LEN_MIN;
++  LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);
++  RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1);
++  RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits);
++  RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask);
++}
++
++static SRes CheckErrors(CLzmaEnc *p)
++{
++  if (p->result != SZ_OK)
++    return p->result;
++  if (p->rc.res != SZ_OK)
++    p->result = SZ_ERROR_WRITE;
++  if (p->matchFinderBase.result != SZ_OK)
++    p->result = SZ_ERROR_READ;
++  if (p->result != SZ_OK)
++    p->finished = True;
++  return p->result;
++}
++
++static SRes Flush(CLzmaEnc *p, UInt32 nowPos)
++{
++  /* ReleaseMFStream(); */
++  p->finished = True;
++  if (p->writeEndMark)
++    WriteEndMarker(p, nowPos & p->pbMask);
++  RangeEnc_FlushData(&p->rc);
++  RangeEnc_FlushStream(&p->rc);
++  return CheckErrors(p);
++}
++
++static void FillAlignPrices(CLzmaEnc *p)
++{
++  UInt32 i;
++  for (i = 0; i < kAlignTableSize; i++)
++    p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices);
++  p->alignPriceCount = 0;
++}
++
++static void FillDistancesPrices(CLzmaEnc *p)
++{
++  UInt32 tempPrices[kNumFullDistances];
++  UInt32 i, lenToPosState;
++  for (i = kStartPosModelIndex; i < kNumFullDistances; i++)
++  {
++    UInt32 posSlot = GetPosSlot1(i);
++    UInt32 footerBits = ((posSlot >> 1) - 1);
++    UInt32 base = ((2 | (posSlot & 1)) << footerBits);
++    tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices);
++  }
++
++  for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)
++  {
++    UInt32 posSlot;
++    const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState];
++    UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState];
++    for (posSlot = 0; posSlot < p->distTableSize; posSlot++)
++      posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices);
++    for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++)
++      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits);
++
++    {
++      UInt32 *distancesPrices = p->distancesPrices[lenToPosState];
++      UInt32 i;
++      for (i = 0; i < kStartPosModelIndex; i++)
++        distancesPrices[i] = posSlotPrices[i];
++      for (; i < kNumFullDistances; i++)
++        distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i];
++    }
++  }
++  p->matchPriceCount = 0;
++}
++
++void LzmaEnc_Construct(CLzmaEnc *p)
++{
++  RangeEnc_Construct(&p->rc);
++  MatchFinder_Construct(&p->matchFinderBase);
++  #ifndef _7ZIP_ST
++  MatchFinderMt_Construct(&p->matchFinderMt);
++  p->matchFinderMt.MatchFinder = &p->matchFinderBase;
++  #endif
++
++  {
++    CLzmaEncProps props;
++    LzmaEncProps_Init(&props);
++    LzmaEnc_SetProps(p, &props);
++  }
++
++  #ifndef LZMA_LOG_BSR
++  LzmaEnc_FastPosInit(p->g_FastPos);
++  #endif
++
++  LzmaEnc_InitPriceTables(p->ProbPrices);
++  p->litProbs = 0;
++  p->saveState.litProbs = 0;
++}
++
++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc)
++{
++  void *p;
++  p = alloc->Alloc(alloc, sizeof(CLzmaEnc));
++  if (p != 0)
++    LzmaEnc_Construct((CLzmaEnc *)p);
++  return p;
++}
++
++void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)
++{
++  alloc->Free(alloc, p->litProbs);
++  alloc->Free(alloc, p->saveState.litProbs);
++  p->litProbs = 0;
++  p->saveState.litProbs = 0;
++}
++
++void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  #ifndef _7ZIP_ST
++  MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);
++  #endif
++  MatchFinder_Free(&p->matchFinderBase, allocBig);
++  LzmaEnc_FreeLits(p, alloc);
++  RangeEnc_Free(&p->rc, alloc);
++}
++
++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig);
++  alloc->Free(alloc, p);
++}
++
++static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize)
++{
++  UInt32 nowPos32, startPos32;
++  if (p->needInit)
++  {
++    p->matchFinder.Init(p->matchFinderObj);
++    p->needInit = 0;
++  }
++
++  if (p->finished)
++    return p->result;
++  RINOK(CheckErrors(p));
++
++  nowPos32 = (UInt32)p->nowPos64;
++  startPos32 = nowPos32;
++
++  if (p->nowPos64 == 0)
++  {
++    UInt32 numPairs;
++    Byte curByte;
++    if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)
++      return Flush(p, nowPos32);
++    ReadMatchDistances(p, &numPairs);
++    RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0);
++    p->state = kLiteralNextStates[p->state];
++    curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset);
++    LitEnc_Encode(&p->rc, p->litProbs, curByte);
++    p->additionalOffset--;
++    nowPos32++;
++  }
++
++  if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0)
++  for (;;)
++  {
++    UInt32 pos, len, posState;
++
++    if (p->fastMode)
++      len = GetOptimumFast(p, &pos);
++    else
++      len = GetOptimum(p, nowPos32, &pos);
++
++    #ifdef SHOW_STAT2
++    printf("\n pos = %4X,   len = %d   pos = %d", nowPos32, len, pos);
++    #endif
++
++    posState = nowPos32 & p->pbMask;
++    if (len == 1 && pos == (UInt32)-1)
++    {
++      Byte curByte;
++      CLzmaProb *probs;
++      const Byte *data;
++
++      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0);
++      data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;
++      curByte = *data;
++      probs = LIT_PROBS(nowPos32, *(data - 1));
++      if (IsCharState(p->state))
++        LitEnc_Encode(&p->rc, probs, curByte);
++      else
++        LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1));
++      p->state = kLiteralNextStates[p->state];
++    }
++    else
++    {
++      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);
++      if (pos < LZMA_NUM_REPS)
++      {
++        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1);
++        if (pos == 0)
++        {
++          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0);
++          RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1));
++        }
++        else
++        {
++          UInt32 distance = p->reps[pos];
++          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1);
++          if (pos == 1)
++            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0);
++          else
++          {
++            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1);
++            RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2);
++            if (pos == 3)
++              p->reps[3] = p->reps[2];
++            p->reps[2] = p->reps[1];
++          }
++          p->reps[1] = p->reps[0];
++          p->reps[0] = distance;
++        }
++        if (len == 1)
++          p->state = kShortRepNextStates[p->state];
++        else
++        {
++          LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);
++          p->state = kRepNextStates[p->state];
++        }
++      }
++      else
++      {
++        UInt32 posSlot;
++        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);
++        p->state = kMatchNextStates[p->state];
++        LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);
++        pos -= LZMA_NUM_REPS;
++        GetPosSlot(pos, posSlot);
++        RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot);
++
++        if (posSlot >= kStartPosModelIndex)
++        {
++          UInt32 footerBits = ((posSlot >> 1) - 1);
++          UInt32 base = ((2 | (posSlot & 1)) << footerBits);
++          UInt32 posReduced = pos - base;
++
++          if (posSlot < kEndPosModelIndex)
++            RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced);
++          else
++          {
++            RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits);
++            RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask);
++            p->alignPriceCount++;
++          }
++        }
++        p->reps[3] = p->reps[2];
++        p->reps[2] = p->reps[1];
++        p->reps[1] = p->reps[0];
++        p->reps[0] = pos;
++        p->matchPriceCount++;
++      }
++    }
++    p->additionalOffset -= len;
++    nowPos32 += len;
++    if (p->additionalOffset == 0)
++    {
++      UInt32 processed;
++      if (!p->fastMode)
++      {
++        if (p->matchPriceCount >= (1 << 7))
++          FillDistancesPrices(p);
++        if (p->alignPriceCount >= kAlignTableSize)
++          FillAlignPrices(p);
++      }
++      if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)
++        break;
++      processed = nowPos32 - startPos32;
++      if (useLimits)
++      {
++        if (processed + kNumOpts + 300 >= maxUnpackSize ||
++            RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize)
++          break;
++      }
++      else if (processed >= (1 << 15))
++      {
++        p->nowPos64 += nowPos32 - startPos32;
++        return CheckErrors(p);
++      }
++    }
++  }
++  p->nowPos64 += nowPos32 - startPos32;
++  return Flush(p, nowPos32);
++}
++
++#define kBigHashDicLimit ((UInt32)1 << 24)
++
++static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  UInt32 beforeSize = kNumOpts;
++  Bool btMode;
++  if (!RangeEnc_Alloc(&p->rc, alloc))
++    return SZ_ERROR_MEM;
++  btMode = (p->matchFinderBase.btMode != 0);
++  #ifndef _7ZIP_ST
++  p->mtMode = (p->multiThread && !p->fastMode && btMode);
++  #endif
++
++  {
++    unsigned lclp = p->lc + p->lp;
++    if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp)
++    {
++      LzmaEnc_FreeLits(p, alloc);
++      p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));
++      p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));
++      if (p->litProbs == 0 || p->saveState.litProbs == 0)
++      {
++        LzmaEnc_FreeLits(p, alloc);
++        return SZ_ERROR_MEM;
++      }
++      p->lclp = lclp;
++    }
++  }
++
++  p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit);
++
++  if (beforeSize + p->dictSize < keepWindowSize)
++    beforeSize = keepWindowSize - p->dictSize;
++
++  #ifndef _7ZIP_ST
++  if (p->mtMode)
++  {
++    RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig));
++    p->matchFinderObj = &p->matchFinderMt;
++    MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder);
++  }
++  else
++  #endif
++  {
++    if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig))
++      return SZ_ERROR_MEM;
++    p->matchFinderObj = &p->matchFinderBase;
++    MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder);
++  }
++  return SZ_OK;
++}
++
++void LzmaEnc_Init(CLzmaEnc *p)
++{
++  UInt32 i;
++  p->state = 0;
++  for (i = 0 ; i < LZMA_NUM_REPS; i++)
++    p->reps[i] = 0;
++
++  RangeEnc_Init(&p->rc);
++
++
++  for (i = 0; i < kNumStates; i++)
++  {
++    UInt32 j;
++    for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++)
++    {
++      p->isMatch[i][j] = kProbInitValue;
++      p->isRep0Long[i][j] = kProbInitValue;
++    }
++    p->isRep[i] = kProbInitValue;
++    p->isRepG0[i] = kProbInitValue;
++    p->isRepG1[i] = kProbInitValue;
++    p->isRepG2[i] = kProbInitValue;
++  }
++
++  {
++    UInt32 num = 0x300 << (p->lp + p->lc);
++    for (i = 0; i < num; i++)
++      p->litProbs[i] = kProbInitValue;
++  }
++
++  {
++    for (i = 0; i < kNumLenToPosStates; i++)
++    {
++      CLzmaProb *probs = p->posSlotEncoder[i];
++      UInt32 j;
++      for (j = 0; j < (1 << kNumPosSlotBits); j++)
++        probs[j] = kProbInitValue;
++    }
++  }
++  {
++    for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)
++      p->posEncoders[i] = kProbInitValue;
++  }
++
++  LenEnc_Init(&p->lenEnc.p);
++  LenEnc_Init(&p->repLenEnc.p);
++
++  for (i = 0; i < (1 << kNumAlignBits); i++)
++    p->posAlignEncoder[i] = kProbInitValue;
++
++  p->optimumEndIndex = 0;
++  p->optimumCurrentIndex = 0;
++  p->additionalOffset = 0;
++
++  p->pbMask = (1 << p->pb) - 1;
++  p->lpMask = (1 << p->lp) - 1;
++}
++
++void LzmaEnc_InitPrices(CLzmaEnc *p)
++{
++  if (!p->fastMode)
++  {
++    FillDistancesPrices(p);
++    FillAlignPrices(p);
++  }
++
++  p->lenEnc.tableSize =
++  p->repLenEnc.tableSize =
++      p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN;
++  LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices);
++  LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices);
++}
++
++static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  UInt32 i;
++  for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++)
++    if (p->dictSize <= ((UInt32)1 << i))
++      break;
++  p->distTableSize = i * 2;
++
++  p->finished = False;
++  p->result = SZ_OK;
++  RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig));
++  LzmaEnc_Init(p);
++  LzmaEnc_InitPrices(p);
++  p->nowPos64 = 0;
++  return SZ_OK;
++}
++
++static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream,
++    ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  p->matchFinderBase.stream = inStream;
++  p->needInit = 1;
++  p->rc.outStream = outStream;
++  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);
++}
++
++SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp,
++    ISeqInStream *inStream, UInt32 keepWindowSize,
++    ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  p->matchFinderBase.stream = inStream;
++  p->needInit = 1;
++  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);
++}
++
++static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)
++{
++  p->matchFinderBase.directInput = 1;
++  p->matchFinderBase.bufferBase = (Byte *)src;
++  p->matchFinderBase.directInputRem = srcLen;
++}
++
++SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,
++    UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  LzmaEnc_SetInputBuf(p, src, srcLen);
++  p->needInit = 1;
++
++  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);
++}
++
++void LzmaEnc_Finish(CLzmaEncHandle pp)
++{
++  #ifndef _7ZIP_ST
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  if (p->mtMode)
++    MatchFinderMt_ReleaseStream(&p->matchFinderMt);
++  #else
++  pp = pp;
++  #endif
++}
++
++typedef struct
++{
++  ISeqOutStream funcTable;
++  Byte *data;
++  SizeT rem;
++  Bool overflow;
++} CSeqOutStreamBuf;
++
++static size_t MyWrite(void *pp, const void *data, size_t size)
++{
++  CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp;
++  if (p->rem < size)
++  {
++    size = p->rem;
++    p->overflow = True;
++  }
++  memcpy(p->data, data, size);
++  p->rem -= size;
++  p->data += size;
++  return size;
++}
++
++
++UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)
++{
++  const CLzmaEnc *p = (CLzmaEnc *)pp;
++  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);
++}
++
++const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)
++{
++  const CLzmaEnc *p = (CLzmaEnc *)pp;
++  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;
++}
++
++SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit,
++    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  UInt64 nowPos64;
++  SRes res;
++  CSeqOutStreamBuf outStream;
++
++  outStream.funcTable.Write = MyWrite;
++  outStream.data = dest;
++  outStream.rem = *destLen;
++  outStream.overflow = False;
++
++  p->writeEndMark = False;
++  p->finished = False;
++  p->result = SZ_OK;
++
++  if (reInit)
++    LzmaEnc_Init(p);
++  LzmaEnc_InitPrices(p);
++  nowPos64 = p->nowPos64;
++  RangeEnc_Init(&p->rc);
++  p->rc.outStream = &outStream.funcTable;
++
++  res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);
++
++  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);
++  *destLen -= outStream.rem;
++  if (outStream.overflow)
++    return SZ_ERROR_OUTPUT_EOF;
++
++  return res;
++}
++
++static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress)
++{
++  SRes res = SZ_OK;
++
++  #ifndef _7ZIP_ST
++  Byte allocaDummy[0x300];
++  int i = 0;
++  for (i = 0; i < 16; i++)
++    allocaDummy[i] = (Byte)i;
++  #endif
++
++  for (;;)
++  {
++    res = LzmaEnc_CodeOneBlock(p, False, 0, 0);
++    if (res != SZ_OK || p->finished != 0)
++      break;
++    if (progress != 0)
++    {
++      res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc));
++      if (res != SZ_OK)
++      {
++        res = SZ_ERROR_PROGRESS;
++        break;
++      }
++    }
++  }
++  LzmaEnc_Finish(p);
++  return res;
++}
++
++SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,
++    ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig));
++  return LzmaEnc_Encode2((CLzmaEnc *)pp, progress);
++}
++
++SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)
++{
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++  int i;
++  UInt32 dictSize = p->dictSize;
++  if (*size < LZMA_PROPS_SIZE)
++    return SZ_ERROR_PARAM;
++  *size = LZMA_PROPS_SIZE;
++  props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc);
++
++  for (i = 11; i <= 30; i++)
++  {
++    if (dictSize <= ((UInt32)2 << i))
++    {
++      dictSize = (2 << i);
++      break;
++    }
++    if (dictSize <= ((UInt32)3 << i))
++    {
++      dictSize = (3 << i);
++      break;
++    }
++  }
++
++  for (i = 0; i < 4; i++)
++    props[1 + i] = (Byte)(dictSize >> (8 * i));
++  return SZ_OK;
++}
++
++SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
++    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  SRes res;
++  CLzmaEnc *p = (CLzmaEnc *)pp;
++
++  CSeqOutStreamBuf outStream;
++
++  LzmaEnc_SetInputBuf(p, src, srcLen);
++
++  outStream.funcTable.Write = MyWrite;
++  outStream.data = dest;
++  outStream.rem = *destLen;
++  outStream.overflow = False;
++
++  p->writeEndMark = writeEndMark;
++
++  p->rc.outStream = &outStream.funcTable;
++  res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig);
++  if (res == SZ_OK)
++    res = LzmaEnc_Encode2(p, progress);
++
++  *destLen -= outStream.rem;
++  if (outStream.overflow)
++    return SZ_ERROR_OUTPUT_EOF;
++  return res;
++}
++
++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,
++    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,
++    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)
++{
++  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);
++  SRes res;
++  if (p == 0)
++    return SZ_ERROR_MEM;
++
++  res = LzmaEnc_SetProps(p, props);
++  if (res == SZ_OK)
++  {
++    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);
++    if (res == SZ_OK)
++      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,
++          writeEndMark, progress, alloc, allocBig);
++  }
++
++  LzmaEnc_Destroy(p, alloc, allocBig);
++  return res;
++}
+--- /dev/null
++++ b/lib/lzma/Makefile
+@@ -0,0 +1,7 @@
++lzma_compress-objs := LzFind.o LzmaEnc.o
++lzma_decompress-objs := LzmaDec.o
++
++obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o
++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o
++
++EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h
diff --git a/target/linux/generic/pending-6.6/532-jffs2_eofdetect.patch b/target/linux/generic/pending-6.6/532-jffs2_eofdetect.patch
new file mode 100644
index 00000000000000..744fbd0e21790b
--- /dev/null
+++ b/target/linux/generic/pending-6.6/532-jffs2_eofdetect.patch
@@ -0,0 +1,65 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: fs: jffs2: EOF marker
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ fs/jffs2/build.c | 10 ++++++++++
+ fs/jffs2/scan.c  | 21 +++++++++++++++++++--
+ 2 files changed, 29 insertions(+), 2 deletions(-)
+
+--- a/fs/jffs2/build.c
++++ b/fs/jffs2/build.c
+@@ -117,6 +117,16 @@ static int jffs2_build_filesystem(struct
+ 	dbg_fsbuild("scanned flash completely\n");
+ 	jffs2_dbg_dump_block_lists_nolock(c);
+ 
++	if (c->flags & (1 << 7)) {
++		printk("%s(): unlocking the mtd device... ", __func__);
++		mtd_unlock(c->mtd, 0, c->mtd->size);
++		printk("done.\n");
++
++		printk("%s(): erasing all blocks after the end marker... ", __func__);
++		jffs2_erase_pending_blocks(c, -1);
++		printk("done.\n");
++	}
++
+ 	dbg_fsbuild("pass 1 starting\n");
+ 	c->flags |= JFFS2_SB_FLAG_BUILDING;
+ 	/* Now scan the directory tree, increasing nlink according to every dirent found. */
+--- a/fs/jffs2/scan.c
++++ b/fs/jffs2/scan.c
+@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in
+ 		/* reset summary info for next eraseblock scan */
+ 		jffs2_sum_reset_collected(s);
+ 
+-		ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset),
+-						buf_size, s);
++		if (c->flags & (1 << 7)) {
++			if (mtd_block_isbad(c->mtd, jeb->offset))
++				ret = BLK_STATE_BADBLOCK;
++			else
++				ret = BLK_STATE_ALLFF;
++		} else
++			ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset),
++							buf_size, s);
+ 
+ 		if (ret < 0)
+ 			goto out;
+@@ -567,6 +573,17 @@ full_scan:
+ 			return err;
+ 	}
+ 
++	if ((buf[0] == 0xde) &&
++		(buf[1] == 0xad) &&
++		(buf[2] == 0xc0) &&
++		(buf[3] == 0xde)) {
++		/* end of filesystem. erase everything after this point */
++		printk("%s(): End of filesystem marker found at 0x%x\n", __func__, jeb->offset);
++		c->flags |= (1 << 7);
++
++		return BLK_STATE_ALLFF;
++	}
++
+ 	/* We temporarily use 'ofs' as a pointer into the buffer/jeb */
+ 	ofs = 0;
+ 	max_ofs = EMPTY_SCAN_SIZE(c->sector_size);
diff --git a/target/linux/generic/pending-6.6/600-netfilter_conntrack_flush.patch b/target/linux/generic/pending-6.6/600-netfilter_conntrack_flush.patch
new file mode 100644
index 00000000000000..3743f7704349f6
--- /dev/null
+++ b/target/linux/generic/pending-6.6/600-netfilter_conntrack_flush.patch
@@ -0,0 +1,88 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: netfilter: add support for flushing conntrack via /proc
+
+lede-commit 8193bbe59a74d34d6a26d4a8cb857b1952905314
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ net/netfilter/nf_conntrack_standalone.c | 59 ++++++++++++++++++++++++++++++++-
+ 1 file changed, 58 insertions(+), 1 deletion(-)
+
+--- a/net/netfilter/nf_conntrack_standalone.c
++++ b/net/netfilter/nf_conntrack_standalone.c
+@@ -9,6 +9,7 @@
+ #include <linux/percpu.h>
+ #include <linux/netdevice.h>
+ #include <linux/security.h>
++#include <linux/inet.h>
+ #include <net/net_namespace.h>
+ #ifdef CONFIG_SYSCTL
+ #include <linux/sysctl.h>
+@@ -461,6 +462,56 @@ static int ct_cpu_seq_show(struct seq_fi
+ 	return 0;
+ }
+ 
++struct kill_request {
++	u16 family;
++	union nf_inet_addr addr;
++};
++
++static int kill_matching(struct nf_conn *i, void *data)
++{
++	struct kill_request *kr = data;
++	struct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
++	struct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple;
++
++	if (!kr->family)
++		return 1;
++
++	if (t1->src.l3num != kr->family)
++		return 0;
++
++	return (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) ||
++	        nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) ||
++	        nf_inet_addr_cmp(&kr->addr, &t2->src.u3) ||
++	        nf_inet_addr_cmp(&kr->addr, &t2->dst.u3));
++}
++
++static int ct_file_write(struct file *file, char *buf, size_t count)
++{
++	struct seq_file *seq = file->private_data;
++	struct net *net = seq_file_net(seq);
++	struct kill_request kr = { };
++
++	if (count == 0)
++		return 0;
++
++	if (count >= INET6_ADDRSTRLEN)
++		count = INET6_ADDRSTRLEN - 1;
++
++	if (strnchr(buf, count, ':')) {
++		kr.family = AF_INET6;
++		if (!in6_pton(buf, count, (void *)&kr.addr, '\n', NULL))
++			return -EINVAL;
++	} else if (strnchr(buf, count, '.')) {
++		kr.family = AF_INET;
++		if (!in4_pton(buf, count, (void *)&kr.addr, '\n', NULL))
++			return -EINVAL;
++	}
++
++
++
++	return 0;
++}
++
+ static const struct seq_operations ct_cpu_seq_ops = {
+ 	.start	= ct_cpu_seq_start,
+ 	.next	= ct_cpu_seq_next,
+@@ -474,8 +525,9 @@ static int nf_conntrack_standalone_init_
+ 	kuid_t root_uid;
+ 	kgid_t root_gid;
+ 
+-	pde = proc_create_net("nf_conntrack", 0440, net->proc_net, &ct_seq_ops,
+-			sizeof(struct ct_iter_state));
++	pde = proc_create_net_data_write("nf_conntrack", 0440, net->proc_net,
++					 &ct_seq_ops, &ct_file_write,
++					 sizeof(struct ct_iter_state), NULL);
+ 	if (!pde)
+ 		goto out_nf_conntrack;
+ 
diff --git a/target/linux/generic/pending-6.6/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/pending-6.6/610-netfilter_match_bypass_default_checks.patch
new file mode 100644
index 00000000000000..67dcf25a0d809d
--- /dev/null
+++ b/target/linux/generic/pending-6.6/610-netfilter_match_bypass_default_checks.patch
@@ -0,0 +1,110 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: add a new version of my netfilter speedup patches for linux 2.6.39 and 3.0
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/uapi/linux/netfilter_ipv4/ip_tables.h |  1 +
+ net/ipv4/netfilter/ip_tables.c                | 37 +++++++++++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h
++++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h
+@@ -89,6 +89,7 @@ struct ipt_ip {
+ #define IPT_F_FRAG		0x01	/* Set if rule is a fragment rule */
+ #define IPT_F_GOTO		0x02	/* Set if jump is a goto */
+ #define IPT_F_MASK		0x03	/* All possible flag bits mask. */
++#define IPT_F_NO_DEF_MATCH	0x80	/* Internal: no default match rules present */
+ 
+ /* Values for "inv" field in struct ipt_ip. */
+ #define IPT_INV_VIA_IN		0x01	/* Invert the sense of IN IFACE. */
+--- a/net/ipv4/netfilter/ip_tables.c
++++ b/net/ipv4/netfilter/ip_tables.c
+@@ -48,6 +48,9 @@ ip_packet_match(const struct iphdr *ip,
+ {
+ 	unsigned long ret;
+ 
++	if (ipinfo->flags & IPT_F_NO_DEF_MATCH)
++		return true;
++
+ 	if (NF_INVF(ipinfo, IPT_INV_SRCIP,
+ 		    (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) ||
+ 	    NF_INVF(ipinfo, IPT_INV_DSTIP,
+@@ -78,6 +81,29 @@ ip_packet_match(const struct iphdr *ip,
+ 	return true;
+ }
+ 
++static void
++ip_checkdefault(struct ipt_ip *ip)
++{
++	static const char iface_mask[IFNAMSIZ] = {};
++
++	if (ip->invflags || ip->flags & IPT_F_FRAG)
++		return;
++
++	if (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0)
++		return;
++
++	if (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0)
++		return;
++
++	if (ip->smsk.s_addr || ip->dmsk.s_addr)
++		return;
++
++	if (ip->proto)
++		return;
++
++	ip->flags |= IPT_F_NO_DEF_MATCH;
++}
++
+ static bool
+ ip_checkentry(const struct ipt_ip *ip)
+ {
+@@ -523,6 +549,8 @@ find_check_entry(struct ipt_entry *e, st
+ 	struct xt_mtchk_param mtpar;
+ 	struct xt_entry_match *ematch;
+ 
++	ip_checkdefault(&e->ip);
++
+ 	if (!xt_percpu_counter_alloc(alloc_state, &e->counters))
+ 		return -ENOMEM;
+ 
+@@ -817,6 +845,7 @@ copy_entries_to_user(unsigned int total_
+ 	const struct xt_table_info *private = table->private;
+ 	int ret = 0;
+ 	const void *loc_cpu_entry;
++	u8 flags;
+ 
+ 	counters = alloc_counters(table);
+ 	if (IS_ERR(counters))
+@@ -844,6 +873,14 @@ copy_entries_to_user(unsigned int total_
+ 			goto free_counters;
+ 		}
+ 
++		flags = e->ip.flags & IPT_F_MASK;
++		if (copy_to_user(userptr + off
++				 + offsetof(struct ipt_entry, ip.flags),
++				 &flags, sizeof(flags)) != 0) {
++			ret = -EFAULT;
++			goto free_counters;
++		}
++
+ 		for (i = sizeof(struct ipt_entry);
+ 		     i < e->target_offset;
+ 		     i += m->u.match_size) {
+@@ -1221,12 +1258,15 @@ compat_copy_entry_to_user(struct ipt_ent
+ 	compat_uint_t origsize;
+ 	const struct xt_entry_match *ematch;
+ 	int ret = 0;
++	u8 flags = e->ip.flags & IPT_F_MASK;
+ 
+ 	origsize = *size;
+ 	ce = *dstptr;
+ 	if (copy_to_user(ce, e, sizeof(struct ipt_entry)) != 0 ||
+ 	    copy_to_user(&ce->counters, &counters[i],
+-	    sizeof(counters[i])) != 0)
++	    sizeof(counters[i])) != 0 ||
++	    copy_to_user(&ce->ip.flags, &flags,
++	    sizeof(flags)) != 0)
+ 		return -EFAULT;
+ 
+ 	*dstptr += sizeof(struct compat_ipt_entry);
diff --git a/target/linux/generic/pending-6.6/611-netfilter_match_bypass_default_table.patch b/target/linux/generic/pending-6.6/611-netfilter_match_bypass_default_table.patch
new file mode 100644
index 00000000000000..9f0efe4ec417cc
--- /dev/null
+++ b/target/linux/generic/pending-6.6/611-netfilter_match_bypass_default_table.patch
@@ -0,0 +1,106 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: netfilter: match bypass default table
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ net/ipv4/netfilter/ip_tables.c | 79 +++++++++++++++++++++++++++++++-----------
+ 1 file changed, 58 insertions(+), 21 deletions(-)
+
+--- a/net/ipv4/netfilter/ip_tables.c
++++ b/net/ipv4/netfilter/ip_tables.c
+@@ -244,6 +244,33 @@ struct ipt_entry *ipt_next_entry(const s
+ 	return (void *)entry + entry->next_offset;
+ }
+ 
++static bool
++ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict)
++{
++	struct xt_entry_target *t;
++	struct xt_standard_target *st;
++
++	if (e->target_offset != sizeof(struct ipt_entry))
++		return false;
++
++	if (!(e->ip.flags & IPT_F_NO_DEF_MATCH))
++		return false;
++
++	t = ipt_get_target(e);
++	if (t->u.kernel.target->target)
++		return false;
++
++	st = (struct xt_standard_target *) t;
++	if (st->verdict == XT_RETURN)
++		return false;
++
++	if (st->verdict >= 0)
++		return false;
++
++	*verdict = (unsigned)(-st->verdict) - 1;
++	return true;
++}
++
+ /* Returns one of the generic firewall policies, like NF_ACCEPT. */
+ unsigned int
+ ipt_do_table(void *priv,
+@@ -265,27 +292,28 @@ ipt_do_table(void *priv,
+ 	unsigned int addend;
+ 
+ 	/* Initialization */
++	WARN_ON(!(table->valid_hooks & (1 << hook)));
++	local_bh_disable();
++	private = READ_ONCE(table->private); /* Address dependency. */
++	cpu        = smp_processor_id();
++	table_base = private->entries;
++
++	e = get_entry(table_base, private->hook_entry[hook]);
++	if (ipt_handle_default_rule(e, &verdict)) {
++		struct xt_counters *counter;
++
++		counter = xt_get_this_cpu_counter(&e->counters);
++		ADD_COUNTER(*counter, skb->len, 1);
++		local_bh_enable();
++		return verdict;
++	}
++
+ 	stackidx = 0;
+ 	ip = ip_hdr(skb);
+ 	indev = state->in ? state->in->name : nulldevname;
+ 	outdev = state->out ? state->out->name : nulldevname;
+-	/* We handle fragments by dealing with the first fragment as
+-	 * if it was a normal packet.  All other fragments are treated
+-	 * normally, except that they will NEVER match rules that ask
+-	 * things we don't know, ie. tcp syn flag or ports).  If the
+-	 * rule is also a fragment-specific rule, non-fragments won't
+-	 * match it. */
+-	acpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET;
+-	acpar.thoff   = ip_hdrlen(skb);
+-	acpar.hotdrop = false;
+-	acpar.state   = state;
+ 
+-	WARN_ON(!(table->valid_hooks & (1 << hook)));
+-	local_bh_disable();
+ 	addend = xt_write_recseq_begin();
+-	private = READ_ONCE(table->private); /* Address dependency. */
+-	cpu        = smp_processor_id();
+-	table_base = private->entries;
+ 	jumpstack  = (struct ipt_entry **)private->jumpstack[cpu];
+ 
+ 	/* Switch to alternate jumpstack if we're being invoked via TEE.
+@@ -298,7 +326,16 @@ ipt_do_table(void *priv,
+ 	if (static_key_false(&xt_tee_enabled))
+ 		jumpstack += private->stacksize * __this_cpu_read(nf_skb_duplicated);
+ 
+-	e = get_entry(table_base, private->hook_entry[hook]);
++	/* We handle fragments by dealing with the first fragment as
++	 * if it was a normal packet.  All other fragments are treated
++	 * normally, except that they will NEVER match rules that ask
++	 * things we don't know, ie. tcp syn flag or ports).  If the
++	 * rule is also a fragment-specific rule, non-fragments won't
++	 * match it. */
++	acpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET;
++	acpar.thoff   = ip_hdrlen(skb);
++	acpar.hotdrop = false;
++	acpar.state   = state;
+ 
+ 	do {
+ 		const struct xt_entry_target *t;
diff --git a/target/linux/generic/pending-6.6/612-netfilter_match_reduce_memory_access.patch b/target/linux/generic/pending-6.6/612-netfilter_match_reduce_memory_access.patch
new file mode 100644
index 00000000000000..7f291fc0083bc8
--- /dev/null
+++ b/target/linux/generic/pending-6.6/612-netfilter_match_reduce_memory_access.patch
@@ -0,0 +1,22 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: netfilter: reduce match memory access
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ net/ipv4/netfilter/ip_tables.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/net/ipv4/netfilter/ip_tables.c
++++ b/net/ipv4/netfilter/ip_tables.c
+@@ -51,9 +51,9 @@ ip_packet_match(const struct iphdr *ip,
+ 	if (ipinfo->flags & IPT_F_NO_DEF_MATCH)
+ 		return true;
+ 
+-	if (NF_INVF(ipinfo, IPT_INV_SRCIP,
++	if (NF_INVF(ipinfo, IPT_INV_SRCIP, ipinfo->smsk.s_addr &&
+ 		    (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) ||
+-	    NF_INVF(ipinfo, IPT_INV_DSTIP,
++	    NF_INVF(ipinfo, IPT_INV_DSTIP, ipinfo->dmsk.s_addr &&
+ 		    (ip->daddr & ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr))
+ 		return false;
+ 
diff --git a/target/linux/generic/pending-6.6/613-netfilter_optional_tcp_window_check.patch b/target/linux/generic/pending-6.6/613-netfilter_optional_tcp_window_check.patch
new file mode 100644
index 00000000000000..e6c3b2a02ada01
--- /dev/null
+++ b/target/linux/generic/pending-6.6/613-netfilter_optional_tcp_window_check.patch
@@ -0,0 +1,89 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: netfilter: optional tcp window check
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
+---
+ net/netfilter/nf_conntrack_proto_tcp.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/net/netfilter/nf_conntrack_proto_tcp.c
++++ b/net/netfilter/nf_conntrack_proto_tcp.c
+@@ -513,11 +513,15 @@ tcp_in_window(struct nf_conn *ct, enum i
+ 	struct ip_ct_tcp *state = &ct->proto.tcp;
+ 	struct ip_ct_tcp_state *sender = &state->seen[dir];
+ 	struct ip_ct_tcp_state *receiver = &state->seen[!dir];
++	const struct nf_tcp_net *tn = nf_tcp_pernet(nf_ct_net(ct));
+ 	__u32 seq, ack, sack, end, win, swin;
+ 	bool in_recv_win, seq_ok;
+ 	s32 receiver_offset;
+ 	u16 win_raw;
+ 
++	if (tn->tcp_no_window_check)
++		return NFCT_TCP_ACCEPT;
++
+ 	/*
+ 	 * Get the required data from the packet.
+ 	 */
+@@ -1283,7 +1287,7 @@ int nf_conntrack_tcp_packet(struct nf_co
+ 		 IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED &&
+ 		 timeouts[new_state] > timeouts[TCP_CONNTRACK_UNACK])
+ 		timeout = timeouts[TCP_CONNTRACK_UNACK];
+-	else if (ct->proto.tcp.last_win == 0 &&
++	else if (!tn->tcp_no_window_check && ct->proto.tcp.last_win == 0 &&
+ 		 timeouts[new_state] > timeouts[TCP_CONNTRACK_RETRANS])
+ 		timeout = timeouts[TCP_CONNTRACK_RETRANS];
+ 	else
+@@ -1599,6 +1603,9 @@ void nf_conntrack_tcp_init_net(struct ne
+ 	 */
+ 	tn->tcp_be_liberal = 0;
+ 
++	/* Skip Windows Check */
++	tn->tcp_no_window_check = 0;
++
+ 	/* If it's non-zero, we turn off RST sequence number check */
+ 	tn->tcp_ignore_invalid_rst = 0;
+ 
+--- a/net/netfilter/nf_conntrack_standalone.c
++++ b/net/netfilter/nf_conntrack_standalone.c
+@@ -631,6 +631,7 @@ enum nf_ct_sysctl_index {
+ #endif
+ 	NF_SYSCTL_CT_PROTO_TCP_LOOSE,
+ 	NF_SYSCTL_CT_PROTO_TCP_LIBERAL,
++	NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK,
+ 	NF_SYSCTL_CT_PROTO_TCP_IGNORE_INVALID_RST,
+ 	NF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS,
+ 	NF_SYSCTL_CT_PROTO_TIMEOUT_UDP,
+@@ -838,6 +839,14 @@ static struct ctl_table nf_ct_sysctl_tab
+ 		.extra1 	= SYSCTL_ZERO,
+ 		.extra2 	= SYSCTL_ONE,
+ 	},
++	[NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK] = {
++		.procname       = "nf_conntrack_tcp_no_window_check",
++		.maxlen         = sizeof(u8),
++		.mode           = 0644,
++		.proc_handler	= proc_dou8vec_minmax,
++		.extra1 	= SYSCTL_ZERO,
++		.extra2 	= SYSCTL_ONE,
++	},
+ 	[NF_SYSCTL_CT_PROTO_TCP_IGNORE_INVALID_RST] = {
+ 		.procname	= "nf_conntrack_tcp_ignore_invalid_rst",
+ 		.maxlen		= sizeof(u8),
+@@ -1048,6 +1057,7 @@ static void nf_conntrack_standalone_init
+ 
+ 	XASSIGN(LOOSE, &tn->tcp_loose);
+ 	XASSIGN(LIBERAL, &tn->tcp_be_liberal);
++	XASSIGN(NO_WINDOW_CHECK, &tn->tcp_no_window_check);
+ 	XASSIGN(MAX_RETRANS, &tn->tcp_max_retrans);
+ 	XASSIGN(IGNORE_INVALID_RST, &tn->tcp_ignore_invalid_rst);
+ #undef XASSIGN
+--- a/include/net/netns/conntrack.h
++++ b/include/net/netns/conntrack.h
+@@ -26,6 +26,7 @@ struct nf_tcp_net {
+ 	unsigned int timeouts[TCP_CONNTRACK_TIMEOUT_MAX];
+ 	u8 tcp_loose;
+ 	u8 tcp_be_liberal;
++	u8 tcp_no_window_check;
+ 	u8 tcp_max_retrans;
+ 	u8 tcp_ignore_invalid_rst;
+ #if IS_ENABLED(CONFIG_NF_FLOW_TABLE)
diff --git a/target/linux/generic/pending-6.6/620-net_sched-codel-do-not-defer-queue-length-update.patch b/target/linux/generic/pending-6.6/620-net_sched-codel-do-not-defer-queue-length-update.patch
new file mode 100644
index 00000000000000..4b4825ae3b9a4a
--- /dev/null
+++ b/target/linux/generic/pending-6.6/620-net_sched-codel-do-not-defer-queue-length-update.patch
@@ -0,0 +1,86 @@
+From: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>
+Date: Mon, 21 Aug 2017 11:14:14 +0300
+Subject: [PATCH] net_sched/codel: do not defer queue length update
+
+When codel wants to drop last packet in ->dequeue() it cannot call
+qdisc_tree_reduce_backlog() right away - it will notify parent qdisc
+about zero qlen and HTB/HFSC will deactivate class. The same class will
+be deactivated second time by caller of ->dequeue(). Currently codel and
+fq_codel defer update. This triggers warning in HFSC when it's qlen != 0
+but there is no active classes.
+
+This patch update parent queue length immediately: just temporary increase
+qlen around qdisc_tree_reduce_backlog() to prevent first class deactivation
+if we have skb to return.
+
+This might open another problem in HFSC - now operation peek could fail and
+deactivate parent class.
+
+Signed-off-by: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=109581
+---
+
+--- a/net/sched/sch_codel.c
++++ b/net/sched/sch_codel.c
+@@ -95,11 +95,17 @@ static struct sk_buff *codel_qdisc_deque
+ 			    &q->stats, qdisc_pkt_len, codel_get_enqueue_time,
+ 			    drop_func, dequeue_func);
+ 
+-	/* We cant call qdisc_tree_reduce_backlog() if our qlen is 0,
+-	 * or HTB crashes. Defer it for next round.
++	/* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate
++	 * parent class, dequeue in parent qdisc will do the same if we
++	 * return skb. Temporary increment qlen if we have skb.
+ 	 */
+-	if (q->stats.drop_count && sch->q.qlen) {
+-		qdisc_tree_reduce_backlog(sch, q->stats.drop_count, q->stats.drop_len);
++	if (q->stats.drop_count) {
++		if (skb)
++			sch->q.qlen++;
++		qdisc_tree_reduce_backlog(sch, q->stats.drop_count,
++					  q->stats.drop_len);
++		if (skb)
++			sch->q.qlen--;
+ 		q->stats.drop_count = 0;
+ 		q->stats.drop_len = 0;
+ 	}
+--- a/net/sched/sch_fq_codel.c
++++ b/net/sched/sch_fq_codel.c
+@@ -304,6 +304,21 @@ begin:
+ 			    &flow->cvars, &q->cstats, qdisc_pkt_len,
+ 			    codel_get_enqueue_time, drop_func, dequeue_func);
+ 
++	/* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate
++	 * parent class, dequeue in parent qdisc will do the same if we
++	 * return skb. Temporary increment qlen if we have skb.
++	 */
++	if (q->cstats.drop_count) {
++		if (skb)
++			sch->q.qlen++;
++		qdisc_tree_reduce_backlog(sch, q->cstats.drop_count,
++					  q->cstats.drop_len);
++		if (skb)
++			sch->q.qlen--;
++		q->cstats.drop_count = 0;
++		q->cstats.drop_len = 0;
++	}
++
+ 	if (!skb) {
+ 		/* force a pass through old_flows to prevent starvation */
+ 		if ((head == &q->new_flows) && !list_empty(&q->old_flows))
+@@ -314,15 +329,6 @@ begin:
+ 	}
+ 	qdisc_bstats_update(sch, skb);
+ 	flow->deficit -= qdisc_pkt_len(skb);
+-	/* We cant call qdisc_tree_reduce_backlog() if our qlen is 0,
+-	 * or HTB crashes. Defer it for next round.
+-	 */
+-	if (q->cstats.drop_count && sch->q.qlen) {
+-		qdisc_tree_reduce_backlog(sch, q->cstats.drop_count,
+-					  q->cstats.drop_len);
+-		q->cstats.drop_count = 0;
+-		q->cstats.drop_len = 0;
+-	}
+ 	return skb;
+ }
+ 
diff --git a/target/linux/generic/pending-6.6/655-increase_skb_pad.patch b/target/linux/generic/pending-6.6/655-increase_skb_pad.patch
new file mode 100644
index 00000000000000..3e13511e8b405d
--- /dev/null
+++ b/target/linux/generic/pending-6.6/655-increase_skb_pad.patch
@@ -0,0 +1,20 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: kernel: add a few patches for avoiding unnecessary skb reallocations - significantly improves ethernet<->wireless performance
+
+lede-commit: 6f89cffc9add6939d44a6b54cf9a5e77849aa7fd
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/linux/skbuff.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -3041,7 +3041,7 @@ static inline int pskb_network_may_pull(
+  * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)
+  */
+ #ifndef NET_SKB_PAD
+-#define NET_SKB_PAD	max(32, L1_CACHE_BYTES)
++#define NET_SKB_PAD	max(64, L1_CACHE_BYTES)
+ #endif
+ 
+ int ___pskb_trim(struct sk_buff *skb, unsigned int len);
diff --git a/target/linux/generic/pending-6.6/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-6.6/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
new file mode 100644
index 00000000000000..1501bfba0d96c2
--- /dev/null
+++ b/target/linux/generic/pending-6.6/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
@@ -0,0 +1,511 @@
+From: Steven Barth <steven@midlink.org>
+Subject: Add support for MAP-E FMRs (mesh mode)
+
+MAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication
+between MAP CEs (mesh mode) without the need to forward such data to a
+border relay. This is similar to how 6rd works but for IPv4 over IPv6.
+
+Signed-off-by: Steven Barth <cyrus@openwrt.org>
+---
+ include/net/ip6_tunnel.h       |  13 ++
+ include/uapi/linux/if_tunnel.h |  13 ++
+ net/ipv6/ip6_tunnel.c          | 276 +++++++++++++++++++++++++++++++++++++++--
+ 3 files changed, 291 insertions(+), 11 deletions(-)
+
+--- a/include/net/ip6_tunnel.h
++++ b/include/net/ip6_tunnel.h
+@@ -18,6 +18,18 @@
+ /* determine capability on a per-packet basis */
+ #define IP6_TNL_F_CAP_PER_PACKET 0x40000
+ 
++/* IPv6 tunnel FMR */
++struct __ip6_tnl_fmr {
++	struct __ip6_tnl_fmr *next; /* next fmr in list */
++	struct in6_addr ip6_prefix;
++	struct in_addr ip4_prefix;
++
++	__u8 ip6_prefix_len;
++	__u8 ip4_prefix_len;
++	__u8 ea_len;
++	__u8 offset;
++};
++
+ struct __ip6_tnl_parm {
+ 	char name[IFNAMSIZ];	/* name of tunnel device */
+ 	int link;		/* ifindex of underlying L2 interface */
+@@ -29,6 +41,7 @@ struct __ip6_tnl_parm {
+ 	__u32 flags;		/* tunnel flags */
+ 	struct in6_addr laddr;	/* local tunnel end-point address */
+ 	struct in6_addr raddr;	/* remote tunnel end-point address */
++	struct __ip6_tnl_fmr *fmrs;	/* FMRs */
+ 
+ 	__be16			i_flags;
+ 	__be16			o_flags;
+--- a/include/uapi/linux/if_tunnel.h
++++ b/include/uapi/linux/if_tunnel.h
+@@ -77,10 +77,23 @@ enum {
+ 	IFLA_IPTUN_ENCAP_DPORT,
+ 	IFLA_IPTUN_COLLECT_METADATA,
+ 	IFLA_IPTUN_FWMARK,
++	IFLA_IPTUN_FMRS,
+ 	__IFLA_IPTUN_MAX,
+ };
+ #define IFLA_IPTUN_MAX	(__IFLA_IPTUN_MAX - 1)
+ 
++enum {
++	IFLA_IPTUN_FMR_UNSPEC,
++	IFLA_IPTUN_FMR_IP6_PREFIX,
++	IFLA_IPTUN_FMR_IP4_PREFIX,
++	IFLA_IPTUN_FMR_IP6_PREFIX_LEN,
++	IFLA_IPTUN_FMR_IP4_PREFIX_LEN,
++	IFLA_IPTUN_FMR_EA_LEN,
++	IFLA_IPTUN_FMR_OFFSET,
++	__IFLA_IPTUN_FMR_MAX,
++};
++#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1)
++
+ enum tunnel_encap_types {
+ 	TUNNEL_ENCAP_NONE,
+ 	TUNNEL_ENCAP_FOU,
+--- a/net/ipv6/ip6_tunnel.c
++++ b/net/ipv6/ip6_tunnel.c
+@@ -11,6 +11,9 @@
+  *      linux/net/ipv6/sit.c and linux/net/ipv4/ipip.c
+  *
+  *      RFC 2473
++ *
++ *      Changes:
++ *      Steven Barth <cyrus@openwrt.org>:           MAP-E FMR support
+  */
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+@@ -67,9 +70,9 @@ static bool log_ecn_error = true;
+ module_param(log_ecn_error, bool, 0644);
+ MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN");
+ 
+-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2)
++static u32 HASH(const struct in6_addr *addr)
+ {
+-	u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2);
++	u32 hash = ipv6_addr_hash(addr);
+ 
+ 	return hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT);
+ }
+@@ -114,17 +117,33 @@ static struct ip6_tnl *
+ ip6_tnl_lookup(struct net *net, int link,
+ 	       const struct in6_addr *remote, const struct in6_addr *local)
+ {
+-	unsigned int hash = HASH(remote, local);
++	unsigned int hash = HASH(local);
+ 	struct ip6_tnl *t, *cand = NULL;
+ 	struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id);
+ 	struct in6_addr any;
+ 
+ 	for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {
+ 		if (!ipv6_addr_equal(local, &t->parms.laddr) ||
+-		    !ipv6_addr_equal(remote, &t->parms.raddr) ||
+ 		    !(t->dev->flags & IFF_UP))
+ 			continue;
+ 
++		if (!ipv6_addr_equal(remote, &t->parms.raddr)) {
++			struct __ip6_tnl_fmr *fmr;
++			bool found = false;
++
++			for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) {
++				if (!ipv6_prefix_equal(remote, &fmr->ip6_prefix,
++						       fmr->ip6_prefix_len))
++					continue;
++
++				found = true;
++				break;
++			}
++
++			if (!found)
++				continue;
++		}
++
+ 		if (link == t->parms.link)
+ 			return t;
+ 		else
+@@ -132,7 +151,7 @@ ip6_tnl_lookup(struct net *net, int link
+ 	}
+ 
+ 	memset(&any, 0, sizeof(any));
+-	hash = HASH(&any, local);
++	hash = HASH(local);
+ 	for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {
+ 		if (!ipv6_addr_equal(local, &t->parms.laddr) ||
+ 		    !ipv6_addr_any(&t->parms.raddr) ||
+@@ -145,7 +164,7 @@ ip6_tnl_lookup(struct net *net, int link
+ 			cand = t;
+ 	}
+ 
+-	hash = HASH(remote, &any);
++	hash = HASH(&any);
+ 	for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {
+ 		if (!ipv6_addr_equal(remote, &t->parms.raddr) ||
+ 		    !ipv6_addr_any(&t->parms.laddr) ||
+@@ -194,7 +213,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n,
+ 
+ 	if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) {
+ 		prio = 1;
+-		h = HASH(remote, local);
++		h = HASH(local);
+ 	}
+ 	return &ip6n->tnls[prio][h];
+ }
+@@ -376,6 +395,12 @@ ip6_tnl_dev_uninit(struct net_device *de
+ 	struct net *net = t->net;
+ 	struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id);
+ 
++	while (t->parms.fmrs) {
++		struct __ip6_tnl_fmr *next = t->parms.fmrs->next;
++		kfree(t->parms.fmrs);
++		t->parms.fmrs = next;
++	}
++
+ 	if (dev == ip6n->fb_tnl_dev)
+ 		RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL);
+ 	else
+@@ -788,6 +813,107 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t,
+ }
+ EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl);
+ 
++/**
++ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR
++ *   @dest: destination IPv6 address buffer
++ *   @skb: received socket buffer
++ *   @fmr: MAP FMR
++ *   @xmit: Calculate for xmit or rcv
++ **/
++static void ip4ip6_fmr_calc(struct in6_addr *dest,
++		const struct iphdr *iph, const uint8_t *end,
++		const struct __ip6_tnl_fmr *fmr, bool xmit)
++{
++	int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len);
++	u8 *portp = NULL;
++	bool use_dest_addr;
++	const struct iphdr *dsth = iph;
++
++	if ((u8*)dsth >= end)
++		return;
++
++	/* find significant IP header */
++	if (iph->protocol == IPPROTO_ICMP) {
++		struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4);
++		if (ih && ((u8*)&ih[1]) <= end && (
++			ih->type == ICMP_DEST_UNREACH ||
++			ih->type == ICMP_SOURCE_QUENCH ||
++			ih->type == ICMP_TIME_EXCEEDED ||
++			ih->type == ICMP_PARAMETERPROB ||
++			ih->type == ICMP_REDIRECT))
++				dsth = (const struct iphdr*)&ih[1];
++	}
++
++	/* in xmit-path use dest port by default and source port only if
++		this is an ICMP reply to something else; vice versa in rcv-path */
++	use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph);
++
++	/* get dst port */
++	if (((u8*)&dsth[1]) <= end && (
++		dsth->protocol == IPPROTO_UDP ||
++		dsth->protocol == IPPROTO_TCP ||
++		dsth->protocol == IPPROTO_SCTP ||
++		dsth->protocol == IPPROTO_DCCP)) {
++			/* for UDP, TCP, SCTP and DCCP source and dest port
++			follow IPv4 header directly */
++			portp = ((u8*)dsth) + dsth->ihl * 4;
++
++			if (use_dest_addr)
++				portp += sizeof(u16);
++	} else if (iph->protocol == IPPROTO_ICMP) {
++		struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4);
++
++		/* use icmp identifier as port */
++		if (((u8*)&ih) <= end && (
++		    (use_dest_addr && (
++		    ih->type == ICMP_ECHOREPLY ||
++			ih->type == ICMP_TIMESTAMPREPLY ||
++			ih->type == ICMP_INFO_REPLY ||
++			ih->type == ICMP_ADDRESSREPLY)) ||
++			(!use_dest_addr && (
++			ih->type == ICMP_ECHO ||
++			ih->type == ICMP_TIMESTAMP ||
++			ih->type == ICMP_INFO_REQUEST ||
++			ih->type == ICMP_ADDRESS)
++			)))
++				portp = (u8*)&ih->un.echo.id;
++	}
++
++	if ((portp && &portp[2] <= end) || psidlen == 0) {
++		int frombyte = fmr->ip6_prefix_len / 8;
++		int fromrem = fmr->ip6_prefix_len % 8;
++		int bytes = sizeof(struct in6_addr) - frombyte;
++		const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr;
++		u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len);
++		u64 t = 0;
++
++		/* extract PSID from port and add it to eabits */
++		u16 psidbits = 0;
++		if (psidlen > 0) {
++			psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]);
++			psidbits >>= 16 - psidlen - fmr->offset;
++			psidbits = (u16)(psidbits << (16 - psidlen));
++			eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen));
++		}
++
++		/* rewrite destination address */
++		*dest = fmr->ip6_prefix;
++		memcpy(&dest->s6_addr[10], addr, sizeof(*addr));
++		dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen));
++
++		if (bytes > sizeof(u64))
++			bytes = sizeof(u64);
++
++		/* insert eabits */
++		memcpy(&t, &dest->s6_addr[frombyte], bytes);
++		t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1)
++			<< (64 - fmr->ea_len - fromrem));
++		t = cpu_to_be64(t | (eabits >> fromrem));
++		memcpy(&dest->s6_addr[frombyte], &t, bytes);
++	}
++}
++
++
+ static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb,
+ 			 const struct tnl_ptk_info *tpi,
+ 			 struct metadata_dst *tun_dst,
+@@ -840,6 +966,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
+ 	skb_reset_network_header(skb);
+ 	memset(skb->cb, 0, sizeof(struct inet6_skb_parm));
+ 
++	if (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs &&
++		!ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) {
++			/* Packet didn't come from BR, so lookup FMR */
++			struct __ip6_tnl_fmr *fmr;
++			struct in6_addr expected = tunnel->parms.raddr;
++			for (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next)
++				if (ipv6_prefix_equal(&ipv6h->saddr,
++					&fmr->ip6_prefix, fmr->ip6_prefix_len))
++						break;
++
++			/* Check that IPv6 matches IPv4 source to prevent spoofing */
++			if (fmr)
++				ip4ip6_fmr_calc(&expected, ip_hdr(skb),
++						skb_tail_pointer(skb), fmr, false);
++
++			if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) {
++				rcu_read_unlock();
++				goto drop;
++			}
++	}
++
+ 	__skb_tunnel_rx(skb, tunnel->dev, tunnel->net);
+ 
+ 	err = dscp_ecn_decapsulate(tunnel, ipv6h, skb);
+@@ -987,6 +1134,7 @@ static void init_tel_txopt(struct ipv6_t
+ 	opt->ops.opt_nflen = 8;
+ }
+ 
++
+ /**
+  * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own
+  *   @t: the outgoing tunnel device
+@@ -1277,6 +1425,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
+ 		u8 protocol)
+ {
+ 	struct ip6_tnl *t = netdev_priv(dev);
++	struct __ip6_tnl_fmr *fmr;
+ 	struct ipv6hdr *ipv6h;
+ 	const struct iphdr  *iph;
+ 	int encap_limit = -1;
+@@ -1376,6 +1525,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
+ 	fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL);
+ 	dsfield = INET_ECN_encapsulate(dsfield, orig_dsfield);
+ 
++	/* try to find matching FMR */
++	for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) {
++		unsigned mshift = 32 - fmr->ip4_prefix_len;
++		if (ntohl(fmr->ip4_prefix.s_addr) >> mshift ==
++				ntohl(ip_hdr(skb)->daddr) >> mshift)
++			break;
++	}
++
++	/* change dstaddr according to FMR */
++	if (fmr)
++		ip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true);
++
+ 	if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))
+ 		return -1;
+ 
+@@ -1528,6 +1689,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
+ 	t->parms.link = p->link;
+ 	t->parms.proto = p->proto;
+ 	t->parms.fwmark = p->fwmark;
++
++	while (t->parms.fmrs) {
++		struct __ip6_tnl_fmr *next = t->parms.fmrs->next;
++		kfree(t->parms.fmrs);
++		t->parms.fmrs = next;
++	}
++	t->parms.fmrs = p->fmrs;
++
+ 	dst_cache_reset(&t->dst_cache);
+ 	ip6_tnl_link_config(t);
+ }
+@@ -1562,6 +1731,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
+ 	p->flowinfo = u->flowinfo;
+ 	p->link = u->link;
+ 	p->proto = u->proto;
++	p->fmrs = NULL;
+ 	memcpy(p->name, u->name, sizeof(u->name));
+ }
+ 
+@@ -1948,6 +2118,15 @@ static int ip6_tnl_validate(struct nlatt
+ 	return 0;
+ }
+ 
++static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = {
++	[IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) },
++	[IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) },
++	[IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 },
++	[IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 },
++	[IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 },
++	[IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 }
++};
++
+ static void ip6_tnl_netlink_parms(struct nlattr *data[],
+ 				  struct __ip6_tnl_parm *parms)
+ {
+@@ -1985,6 +2164,46 @@ static void ip6_tnl_netlink_parms(struct
+ 
+ 	if (data[IFLA_IPTUN_FWMARK])
+ 		parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);
++
++	if (data[IFLA_IPTUN_FMRS]) {
++		unsigned rem;
++		struct nlattr *fmr;
++		nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) {
++			struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c;
++			struct __ip6_tnl_fmr *nfmr;
++
++			nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX,
++				fmr, ip6_tnl_fmr_policy, NULL);
++
++			if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL)))
++				continue;
++
++			nfmr->offset = 6;
++
++			if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX]))
++				nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX],
++					sizeof(nfmr->ip6_prefix));
++
++			if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX]))
++				nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX],
++					sizeof(nfmr->ip4_prefix));
++
++			if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN]))
++				nfmr->ip6_prefix_len = nla_get_u8(c);
++
++			if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN]))
++				nfmr->ip4_prefix_len = nla_get_u8(c);
++
++			if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN]))
++				nfmr->ea_len = nla_get_u8(c);
++
++			if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET]))
++				nfmr->offset = nla_get_u8(c);
++
++			nfmr->next = parms->fmrs;
++			parms->fmrs = nfmr;
++		}
++	}
+ }
+ 
+ static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev,
+@@ -2068,6 +2287,12 @@ static void ip6_tnl_dellink(struct net_d
+ 
+ static size_t ip6_tnl_get_size(const struct net_device *dev)
+ {
++	const struct ip6_tnl *t = netdev_priv(dev);
++	struct __ip6_tnl_fmr *c;
++	int fmrs = 0;
++	for (c = t->parms.fmrs; c; c = c->next)
++		++fmrs;
++
+ 	return
+ 		/* IFLA_IPTUN_LINK */
+ 		nla_total_size(4) +
+@@ -2097,6 +2322,24 @@ static size_t ip6_tnl_get_size(const str
+ 		nla_total_size(0) +
+ 		/* IFLA_IPTUN_FWMARK */
+ 		nla_total_size(4) +
++		/* IFLA_IPTUN_FMRS */
++		nla_total_size(0) +
++		(
++			/* nest */
++			nla_total_size(0) +
++			/* IFLA_IPTUN_FMR_IP6_PREFIX */
++			nla_total_size(sizeof(struct in6_addr)) +
++			/* IFLA_IPTUN_FMR_IP4_PREFIX */
++			nla_total_size(sizeof(struct in_addr)) +
++			/* IFLA_IPTUN_FMR_EA_LEN */
++			nla_total_size(1) +
++			/* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */
++			nla_total_size(1) +
++			/* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */
++			nla_total_size(1) +
++			/* IFLA_IPTUN_FMR_OFFSET */
++			nla_total_size(1)
++		) * fmrs +
+ 		0;
+ }
+ 
+@@ -2104,6 +2347,9 @@ static int ip6_tnl_fill_info(struct sk_b
+ {
+ 	struct ip6_tnl *tunnel = netdev_priv(dev);
+ 	struct __ip6_tnl_parm *parm = &tunnel->parms;
++	struct __ip6_tnl_fmr *c;
++	int fmrcnt = 0;
++	struct nlattr *fmrs;
+ 
+ 	if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||
+ 	    nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||
+@@ -2113,9 +2359,27 @@ static int ip6_tnl_fill_info(struct sk_b
+ 	    nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||
+ 	    nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||
+ 	    nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||
+-	    nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark))
++	    nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) ||
++	    !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS)))
+ 		goto nla_put_failure;
+ 
++	for (c = parm->fmrs; c; c = c->next) {
++		struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt);
++		if (!fmr ||
++			nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX,
++				sizeof(c->ip6_prefix), &c->ip6_prefix) ||
++			nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX,
++				sizeof(c->ip4_prefix), &c->ip4_prefix) ||
++			nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) ||
++			nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) ||
++			nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) ||
++			nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset))
++				goto nla_put_failure;
++
++		nla_nest_end(skb, fmr);
++	}
++	nla_nest_end(skb, fmrs);
++
+ 	if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||
+ 	    nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||
+ 	    nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||
+@@ -2155,6 +2419,7 @@ static const struct nla_policy ip6_tnl_p
+ 	[IFLA_IPTUN_ENCAP_DPORT]	= { .type = NLA_U16 },
+ 	[IFLA_IPTUN_COLLECT_METADATA]	= { .type = NLA_FLAG },
+ 	[IFLA_IPTUN_FWMARK]		= { .type = NLA_U32 },
++	[IFLA_IPTUN_FMRS]		= { .type = NLA_NESTED },
+ };
+ 
+ static struct rtnl_link_ops ip6_link_ops __read_mostly = {
diff --git a/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
new file mode 100644
index 00000000000000..e09decca568f88
--- /dev/null
+++ b/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -0,0 +1,263 @@
+From: Jonas Gorski <jogo@openwrt.org>
+Subject: ipv6: allow rejecting with "source address failed policy"
+
+RFC6204 L-14 requires rejecting traffic from invalid addresses with
+ICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/
+egress policy) on the LAN side, so add an appropriate rule for that.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ include/net/netns/ipv6.h       |  1 +
+ include/uapi/linux/fib_rules.h |  4 +++
+ include/uapi/linux/rtnetlink.h |  1 +
+ net/ipv4/fib_semantics.c       |  4 +++
+ net/ipv4/fib_trie.c            |  1 +
+ net/ipv4/ipmr.c                |  1 +
+ net/ipv6/fib6_rules.c          |  4 +++
+ net/ipv6/ip6mr.c               |  2 ++
+ net/ipv6/route.c               | 58 +++++++++++++++++++++++++++++++++++++++++-
+ 9 files changed, 75 insertions(+), 1 deletion(-)
+
+--- a/include/net/netns/ipv6.h
++++ b/include/net/netns/ipv6.h
+@@ -86,6 +86,7 @@ struct netns_ipv6 {
+ 	unsigned int		fib6_routes_require_src;
+ #endif
+ 	struct rt6_info         *ip6_prohibit_entry;
++	struct rt6_info		*ip6_policy_failed_entry;
+ 	struct rt6_info         *ip6_blk_hole_entry;
+ 	struct fib6_table       *fib6_local_tbl;
+ 	struct fib_rules_ops    *fib6_rules_ops;
+--- a/include/uapi/linux/fib_rules.h
++++ b/include/uapi/linux/fib_rules.h
+@@ -82,6 +82,10 @@ enum {
+ 	FR_ACT_BLACKHOLE,	/* Drop without notification */
+ 	FR_ACT_UNREACHABLE,	/* Drop with ENETUNREACH */
+ 	FR_ACT_PROHIBIT,	/* Drop with EACCES */
++	FR_ACT_RES9,
++	FR_ACT_RES10,
++	FR_ACT_RES11,
++	FR_ACT_POLICY_FAILED,	/* Drop with EACCES */
+ 	__FR_ACT_MAX,
+ };
+ 
+--- a/include/uapi/linux/rtnetlink.h
++++ b/include/uapi/linux/rtnetlink.h
+@@ -265,6 +265,7 @@ enum {
+ 	RTN_THROW,		/* Not in this table		*/
+ 	RTN_NAT,		/* Translate this address	*/
+ 	RTN_XRESOLVE,		/* Use external resolver	*/
++	RTN_POLICY_FAILED,	/* Failed ingress/egress policy */
+ 	__RTN_MAX
+ };
+ 
+--- a/net/ipv4/fib_semantics.c
++++ b/net/ipv4/fib_semantics.c
+@@ -145,6 +145,10 @@ const struct fib_prop fib_props[RTN_MAX
+ 		.error	= -EINVAL,
+ 		.scope	= RT_SCOPE_NOWHERE,
+ 	},
++	[RTN_POLICY_FAILED] = {
++		.error	= -EACCES,
++		.scope	= RT_SCOPE_UNIVERSE,
++	},
+ };
+ 
+ static void rt_fibinfo_free(struct rtable __rcu **rtp)
+--- a/net/ipv4/fib_trie.c
++++ b/net/ipv4/fib_trie.c
+@@ -2783,6 +2783,7 @@ static const char *const rtn_type_names[
+ 	[RTN_THROW] = "THROW",
+ 	[RTN_NAT] = "NAT",
+ 	[RTN_XRESOLVE] = "XRESOLVE",
++	[RTN_POLICY_FAILED] = "POLICY_FAILED",
+ };
+ 
+ static inline const char *rtn_type(char *buf, size_t len, unsigned int t)
+--- a/net/ipv4/ipmr.c
++++ b/net/ipv4/ipmr.c
+@@ -180,6 +180,7 @@ static int ipmr_rule_action(struct fib_r
+ 	case FR_ACT_UNREACHABLE:
+ 		return -ENETUNREACH;
+ 	case FR_ACT_PROHIBIT:
++	case FR_ACT_POLICY_FAILED:
+ 		return -EACCES;
+ 	case FR_ACT_BLACKHOLE:
+ 	default:
+--- a/net/ipv6/fib6_rules.c
++++ b/net/ipv6/fib6_rules.c
+@@ -221,6 +221,10 @@ static int __fib6_rule_action(struct fib
+ 		err = -EACCES;
+ 		rt = net->ipv6.ip6_prohibit_entry;
+ 		goto discard_pkt;
++	case FR_ACT_POLICY_FAILED:
++		err = -EACCES;
++		rt = net->ipv6.ip6_policy_failed_entry;
++		goto discard_pkt;
+ 	}
+ 
+ 	tb_id = fib_rule_get_table(rule, arg);
+--- a/net/ipv6/ip6mr.c
++++ b/net/ipv6/ip6mr.c
+@@ -170,6 +170,8 @@ static int ip6mr_rule_action(struct fib_
+ 		return -ENETUNREACH;
+ 	case FR_ACT_PROHIBIT:
+ 		return -EACCES;
++	case FR_ACT_POLICY_FAILED:
++		return -EACCES;
+ 	case FR_ACT_BLACKHOLE:
+ 	default:
+ 		return -EINVAL;
+--- a/net/ipv6/route.c
++++ b/net/ipv6/route.c
+@@ -97,6 +97,8 @@ static int		ip6_pkt_discard(struct sk_bu
+ static int		ip6_pkt_discard_out(struct net *net, struct sock *sk, struct sk_buff *skb);
+ static int		ip6_pkt_prohibit(struct sk_buff *skb);
+ static int		ip6_pkt_prohibit_out(struct net *net, struct sock *sk, struct sk_buff *skb);
++static int		ip6_pkt_policy_failed(struct sk_buff *skb);
++static int		ip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb);
+ static void		ip6_link_failure(struct sk_buff *skb);
+ static void		ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk,
+ 					   struct sk_buff *skb, u32 mtu,
+@@ -317,6 +319,18 @@ static const struct rt6_info ip6_prohibi
+ 	.rt6i_flags	= (RTF_REJECT | RTF_NONEXTHOP),
+ };
+ 
++static const struct rt6_info ip6_policy_failed_entry_template = {
++	.dst = {
++		.__rcuref	= RCUREF_INIT(1),
++		.__use		= 1,
++		.obsolete	= DST_OBSOLETE_FORCE_CHK,
++		.error		= -EACCES,
++		.input		= ip6_pkt_policy_failed,
++		.output		= ip6_pkt_policy_failed_out,
++	},
++	.rt6i_flags	= (RTF_REJECT | RTF_NONEXTHOP),
++};
++
+ static const struct rt6_info ip6_blk_hole_entry_template = {
+ 	.dst = {
+ 		.__rcuref	= RCUREF_INIT(1),
+@@ -1037,6 +1051,7 @@ static const int fib6_prop[RTN_MAX + 1]
+ 	[RTN_BLACKHOLE]	= -EINVAL,
+ 	[RTN_UNREACHABLE] = -EHOSTUNREACH,
+ 	[RTN_PROHIBIT]	= -EACCES,
++	[RTN_POLICY_FAILED] = -EACCES,
+ 	[RTN_THROW]	= -EAGAIN,
+ 	[RTN_NAT]	= -EINVAL,
+ 	[RTN_XRESOLVE]	= -EINVAL,
+@@ -1072,6 +1087,10 @@ static void ip6_rt_init_dst_reject(struc
+ 		rt->dst.output = ip6_pkt_prohibit_out;
+ 		rt->dst.input = ip6_pkt_prohibit;
+ 		break;
++	case RTN_POLICY_FAILED:
++		rt->dst.output = ip6_pkt_policy_failed_out;
++		rt->dst.input = ip6_pkt_policy_failed;
++		break;
+ 	case RTN_THROW:
+ 	case RTN_UNREACHABLE:
+ 	default:
+@@ -4539,6 +4558,17 @@ static int ip6_pkt_prohibit_out(struct n
+ 	return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
+ }
+ 
++static int ip6_pkt_policy_failed(struct sk_buff *skb)
++{
++	return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES);
++}
++
++static int ip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb)
++{
++	skb->dev = skb_dst(skb)->dev;
++	return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES);
++}
++
+ /*
+  *	Allocate a dst for local (unicast / anycast) address.
+  */
+@@ -5030,7 +5060,8 @@ static int rtm_to_fib6_config(struct sk_
+ 	if (rtm->rtm_type == RTN_UNREACHABLE ||
+ 	    rtm->rtm_type == RTN_BLACKHOLE ||
+ 	    rtm->rtm_type == RTN_PROHIBIT ||
+-	    rtm->rtm_type == RTN_THROW)
++	    rtm->rtm_type == RTN_THROW ||
++	    rtm->rtm_type == RTN_POLICY_FAILED)
+ 		cfg->fc_flags |= RTF_REJECT;
+ 
+ 	if (rtm->rtm_type == RTN_LOCAL)
+@@ -6284,6 +6315,8 @@ static int ip6_route_dev_notify(struct n
+ #ifdef CONFIG_IPV6_MULTIPLE_TABLES
+ 		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
+ 		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
++		net->ipv6.ip6_policy_failed_entry->dst.dev = dev;
++		net->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev);
+ 		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
+ 		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
+ #endif
+@@ -6295,6 +6328,7 @@ static int ip6_route_dev_notify(struct n
+ 		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
+ #ifdef CONFIG_IPV6_MULTIPLE_TABLES
+ 		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
++		in6_dev_put_clear(&net->ipv6.ip6_policy_failed_entry->rt6i_idev);
+ 		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
+ #endif
+ 	}
+@@ -6495,6 +6529,8 @@ static int __net_init ip6_route_net_init
+ 
+ #ifdef CONFIG_IPV6_MULTIPLE_TABLES
+ 	net->ipv6.fib6_has_custom_rules = false;
++
++
+ 	net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
+ 					       sizeof(*net->ipv6.ip6_prohibit_entry),
+ 					       GFP_KERNEL);
+@@ -6505,11 +6541,21 @@ static int __net_init ip6_route_net_init
+ 			 ip6_template_metrics, true);
+ 	INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->dst.rt_uncached);
+ 
++	net->ipv6.ip6_policy_failed_entry =
++				kmemdup(&ip6_policy_failed_entry_template,
++				sizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL);
++	if (!net->ipv6.ip6_policy_failed_entry)
++		goto out_ip6_prohibit_entry;
++	net->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops;
++	dst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst,
++			 ip6_template_metrics, true);
++	INIT_LIST_HEAD(&net->ipv6.ip6_policy_failed_entry->dst.rt_uncached);
++
+ 	net->ipv6.ip6_blk_hole_entry = kmemdup(&ip6_blk_hole_entry_template,
+ 					       sizeof(*net->ipv6.ip6_blk_hole_entry),
+ 					       GFP_KERNEL);
+ 	if (!net->ipv6.ip6_blk_hole_entry)
+-		goto out_ip6_prohibit_entry;
++		goto out_ip6_policy_failed_entry;
+ 	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
+ 	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
+ 			 ip6_template_metrics, true);
+@@ -6536,6 +6582,8 @@ out:
+ 	return ret;
+ 
+ #ifdef CONFIG_IPV6_MULTIPLE_TABLES
++out_ip6_policy_failed_entry:
++	kfree(net->ipv6.ip6_policy_failed_entry);
+ out_ip6_prohibit_entry:
+ 	kfree(net->ipv6.ip6_prohibit_entry);
+ out_ip6_null_entry:
+@@ -6555,6 +6603,7 @@ static void __net_exit ip6_route_net_exi
+ 	kfree(net->ipv6.ip6_null_entry);
+ #ifdef CONFIG_IPV6_MULTIPLE_TABLES
+ 	kfree(net->ipv6.ip6_prohibit_entry);
++	kfree(net->ipv6.ip6_policy_failed_entry);
+ 	kfree(net->ipv6.ip6_blk_hole_entry);
+ #endif
+ 	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
+@@ -6638,6 +6687,9 @@ void __init ip6_route_init_special_entri
+ 	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
+ 	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
+ 	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
++	init_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev;
++	init_net.ipv6.ip6_policy_failed_entry->rt6i_idev =
++		in6_dev_get(init_net.loopback_dev);
+   #endif
+ }
+ 
diff --git a/target/linux/generic/pending-6.6/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch b/target/linux/generic/pending-6.6/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch
new file mode 100644
index 00000000000000..94416a5d70e536
--- /dev/null
+++ b/target/linux/generic/pending-6.6/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch
@@ -0,0 +1,50 @@
+From: Jonas Gorski <jogo@openwrt.org>
+Subject: net: provide defines for _POLICY_FAILED until all code is updated
+
+Upstream introduced ICMPV6_POLICY_FAIL for code 5 of destination
+unreachable, conflicting with our name.
+
+Add appropriate defines to allow our code to build with the new
+name until we have updated our local patches for older kernels
+and userspace packages.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ include/uapi/linux/fib_rules.h | 2 ++
+ include/uapi/linux/icmpv6.h    | 2 ++
+ include/uapi/linux/rtnetlink.h | 2 ++
+ 3 files changed, 6 insertions(+)
+
+--- a/include/uapi/linux/fib_rules.h
++++ b/include/uapi/linux/fib_rules.h
+@@ -89,6 +89,8 @@ enum {
+ 	__FR_ACT_MAX,
+ };
+ 
++#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED
++
+ #define FR_ACT_MAX (__FR_ACT_MAX - 1)
+ 
+ #endif
+--- a/include/uapi/linux/icmpv6.h
++++ b/include/uapi/linux/icmpv6.h
+@@ -126,6 +126,8 @@ struct icmp6hdr {
+ #define ICMPV6_POLICY_FAIL		5
+ #define ICMPV6_REJECT_ROUTE		6
+ 
++#define ICMPV6_FAILED_POLICY		ICMPV6_POLICY_FAIL
++
+ /*
+  *	Codes for Time Exceeded
+  */
+--- a/include/uapi/linux/rtnetlink.h
++++ b/include/uapi/linux/rtnetlink.h
+@@ -269,6 +269,8 @@ enum {
+ 	__RTN_MAX
+ };
+ 
++#define RTN_FAILED_POLICY RTN_POLICY_FAILED
++
+ #define RTN_MAX (__RTN_MAX - 1)
+ 
+ 
diff --git a/target/linux/generic/pending-6.6/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-6.6/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
new file mode 100644
index 00000000000000..20081a30e30e83
--- /dev/null
+++ b/target/linux/generic/pending-6.6/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -0,0 +1,139 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ include/linux/netdevice.h |  2 ++
+ include/linux/skbuff.h    |  3 ++-
+ net/core/dev.c            | 48 +++++++++++++++++++++++++++++++++++++++++++++++
+ net/ethernet/eth.c        | 18 +++++++++++++++++-
+ 4 files changed, 69 insertions(+), 2 deletions(-)
+
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -2187,6 +2187,8 @@ struct net_device {
+ 	struct netdev_hw_addr_list	mc;
+ 	struct netdev_hw_addr_list	dev_addrs;
+ 
++	unsigned char		local_addr_mask[MAX_ADDR_LEN];
++
+ #ifdef CONFIG_SYSFS
+ 	struct kset		*queues_kset;
+ #endif
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -964,6 +964,7 @@ struct sk_buff {
+ #ifdef CONFIG_IPV6_NDISC_NODETYPE
+ 	__u8			ndisc_nodetype:2;
+ #endif
++	__u8			gro_skip:1;
+ 
+ #if IS_ENABLED(CONFIG_IP_VS)
+ 	__u8			ipvs_property:1;
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -7686,6 +7686,48 @@ static void __netdev_adjacent_dev_unlink
+ 					   &upper_dev->adj_list.lower);
+ }
+ 
++static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
++			       struct net_device *dev)
++{
++	int i;
++
++	for (i = 0; i < dev->addr_len; i++)
++		mask[i] |= addr[i] ^ dev->dev_addr[i];
++}
++
++static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
++				struct net_device *lower)
++{
++	struct net_device *cur;
++	struct list_head *iter;
++
++	netdev_for_each_upper_dev_rcu(dev, cur, iter) {
++		__netdev_addr_mask(mask, cur->dev_addr, lower);
++		__netdev_upper_mask(mask, cur, lower);
++	}
++}
++
++static void __netdev_update_addr_mask(struct net_device *dev)
++{
++	unsigned char mask[MAX_ADDR_LEN];
++	struct net_device *cur;
++	struct list_head *iter;
++
++	memset(mask, 0, sizeof(mask));
++	__netdev_upper_mask(mask, dev, dev);
++	memcpy(dev->local_addr_mask, mask, dev->addr_len);
++
++	netdev_for_each_lower_dev(dev, cur, iter)
++		__netdev_update_addr_mask(cur);
++}
++
++static void netdev_update_addr_mask(struct net_device *dev)
++{
++	rcu_read_lock();
++	__netdev_update_addr_mask(dev);
++	rcu_read_unlock();
++}
++
+ static int __netdev_upper_dev_link(struct net_device *dev,
+ 				   struct net_device *upper_dev, bool master,
+ 				   void *upper_priv, void *upper_info,
+@@ -7737,6 +7779,7 @@ static int __netdev_upper_dev_link(struc
+ 	if (ret)
+ 		return ret;
+ 
++	netdev_update_addr_mask(dev);
+ 	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
+ 					    &changeupper_info.info);
+ 	ret = notifier_to_errno(ret);
+@@ -7828,6 +7871,7 @@ static void __netdev_upper_dev_unlink(st
+ 
+ 	changeupper_info.master = netdev_master_upper_dev_get(dev) == upper_dev;
+ 
++	netdev_update_addr_mask(dev);
+ 	call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER,
+ 				      &changeupper_info.info);
+ 
+@@ -8889,6 +8933,7 @@ int dev_set_mac_address(struct net_devic
+ 			return err;
+ 	}
+ 	dev->addr_assign_type = NET_ADDR_SET;
++	netdev_update_addr_mask(dev);
+ 	call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
+ 	add_device_randomness(dev->dev_addr, dev->addr_len);
+ 	return 0;
+--- a/net/ethernet/eth.c
++++ b/net/ethernet/eth.c
+@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
+ }
+ EXPORT_SYMBOL(eth_get_headlen);
+ 
++static inline bool
++eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
++{
++	const u16 *a1 = addr1;
++	const u16 *a2 = addr2;
++	const u16 *m = mask;
++
++	return (((a1[0] ^ a2[0]) & ~m[0]) |
++		((a1[1] ^ a2[1]) & ~m[1]) |
++		((a1[2] ^ a2[2]) & ~m[2]));
++}
++
+ /**
+  * eth_type_trans - determine the packet's protocol ID.
+  * @skb: received socket data
+@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
+ 		} else {
+ 			skb->pkt_type = PACKET_OTHERHOST;
+ 		}
++
++		if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
++					 dev->local_addr_mask))
++			skb->gro_skip = 1;
+ 	}
+ 
+ 	/*
diff --git a/target/linux/generic/pending-6.6/682-of_net-add-mac-address-increment-support.patch b/target/linux/generic/pending-6.6/682-of_net-add-mac-address-increment-support.patch
new file mode 100644
index 00000000000000..24c04a19bf703c
--- /dev/null
+++ b/target/linux/generic/pending-6.6/682-of_net-add-mac-address-increment-support.patch
@@ -0,0 +1,90 @@
+From 844c273286f328acf0dab5fbd5d864366b4904dc Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 30 Mar 2021 18:21:14 +0200
+Subject: [PATCH] of_net: add mac-address-increment support
+
+Lots of embedded devices use the mac-address of other interface
+extracted from nvmem cells and increments it by one or two. Add two
+bindings to integrate this and directly use the right mac-address for
+the interface. Some example are some routers that use the gmac
+mac-address stored in the art partition and increments it by one for the
+wifi. mac-address-increment-byte bindings is used to tell what byte of
+the mac-address has to be increased (if not defined the last byte is
+increased) and mac-address-increment tells how much the byte decided
+early has to be increased.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ net/core/of_net.c | 43 +++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 39 insertions(+), 4 deletions(-)
+
+--- a/net/core/of_net.c
++++ b/net/core/of_net.c
+@@ -121,28 +121,63 @@ EXPORT_SYMBOL(of_get_mac_address_nvmem);
+  * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
+  * but is all zeros.
+  *
++ * DT can tell the system to increment the mac-address after is extracted by
++ * using:
++ * - mac-address-increment-byte to decide what byte to increase
++ *   (if not defined is increased the last byte)
++ * - mac-address-increment to decide how much to increase. The value WILL
++ *   overflow to other bytes if the increment is over 255 or the total
++ *   increment will exceed 255 of the current byte.
++ *   (example 00:01:02:03:04:ff + 1 == 00:01:02:03:05:00)
++ *   (example 00:01:02:03:04:fe + 5 == 00:01:02:03:05:03)
++ *
+  * Return: 0 on success and errno in case of error.
+ */
+ int of_get_mac_address(struct device_node *np, u8 *addr)
+ {
++	u32 inc_idx, mac_inc, mac_val;
+ 	int ret;
+ 
++	/* Check first if the increment byte is present and valid.
++	 * If not set assume to increment the last byte if found.
++	 */
++	if (of_property_read_u32(np, "mac-address-increment-byte", &inc_idx))
++		inc_idx = 5;
++	if (inc_idx < 3 || inc_idx > 5)
++		return -EINVAL;
++
+ 	if (!np)
+ 		return -ENODEV;
+ 
+ 	ret = of_get_mac_addr(np, "mac-address", addr);
+ 	if (!ret)
+-		return 0;
++		goto found;
+ 
+ 	ret = of_get_mac_addr(np, "local-mac-address", addr);
+ 	if (!ret)
+-		return 0;
++		goto found;
+ 
+ 	ret = of_get_mac_addr(np, "address", addr);
+ 	if (!ret)
+-		return 0;
++		goto found;
++
++	ret = of_get_mac_address_nvmem(np, addr);
++	if (ret)
++		return ret;
++
++found:
++	if (!of_property_read_u32(np, "mac-address-increment", &mac_inc)) {
++		/* Convert to a contiguous value */
++		mac_val = (addr[3] << 16) + (addr[4] << 8) + addr[5];
++		mac_val += mac_inc << 8 * (5-inc_idx);
++
++		/* Apply the incremented value handling overflow case */
++		addr[3] = (mac_val >> 16) & 0xff;
++		addr[4] = (mac_val >> 8) & 0xff;
++		addr[5] = (mac_val >> 0) & 0xff;
++	}
+ 
+-	return of_get_mac_address_nvmem(np, addr);
++	return ret;
+ }
+ EXPORT_SYMBOL(of_get_mac_address);
+ 
diff --git a/target/linux/generic/pending-6.6/683-of_net-add-mac-address-to-of-tree.patch b/target/linux/generic/pending-6.6/683-of_net-add-mac-address-to-of-tree.patch
new file mode 100644
index 00000000000000..f5f1981f786292
--- /dev/null
+++ b/target/linux/generic/pending-6.6/683-of_net-add-mac-address-to-of-tree.patch
@@ -0,0 +1,38 @@
+--- a/net/core/of_net.c
++++ b/net/core/of_net.c
+@@ -97,6 +97,27 @@ int of_get_mac_address_nvmem(struct devi
+ }
+ EXPORT_SYMBOL(of_get_mac_address_nvmem);
+ 
++static int of_add_mac_address(struct device_node *np, u8* addr)
++{
++	struct property *prop;
++
++	prop = kzalloc(sizeof(*prop), GFP_KERNEL);
++	if (!prop)
++		return -ENOMEM;
++
++	prop->name = "mac-address";
++	prop->length = ETH_ALEN;
++	prop->value = kmemdup(addr, ETH_ALEN, GFP_KERNEL);
++	if (!prop->value || of_update_property(np, prop))
++		goto free;
++
++	return 0;
++free:
++	kfree(prop->value);
++	kfree(prop);
++	return -ENOMEM;
++}
++
+ /**
+  * of_get_mac_address()
+  * @np:		Caller's Device Node
+@@ -177,6 +198,7 @@ found:
+ 		addr[5] = (mac_val >> 0) & 0xff;
+ 	}
+ 
++	of_add_mac_address(np, addr);
+ 	return ret;
+ }
+ EXPORT_SYMBOL(of_get_mac_address);
diff --git a/target/linux/generic/pending-6.6/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch b/target/linux/generic/pending-6.6/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch
new file mode 100644
index 00000000000000..dcea67a206239d
--- /dev/null
+++ b/target/linux/generic/pending-6.6/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch
@@ -0,0 +1,26 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Thu, 8 Jul 2021 07:08:29 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: avoid creating duplicate offload
+ entries
+
+Sometimes multiple CLS_REPLACE calls are issued for the same connection.
+rhashtable_insert_fast does not check for these duplicates, so multiple
+hardware flow entries can be created.
+Fix this by checking for an existing entry early
+
+Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -256,6 +256,9 @@ mtk_flow_offload_replace(struct mtk_eth
+ 	if (rhashtable_lookup(&eth->flow_table, &f->cookie, mtk_flow_ht_params))
+ 		return -EEXIST;
+ 
++	if (rhashtable_lookup(&eth->flow_table, &f->cookie, mtk_flow_ht_params))
++		return -EEXIST;
++
+ 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) {
+ 		struct flow_match_meta match;
+ 
diff --git a/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
new file mode 100644
index 00000000000000..1cfc4b7cae99c6
--- /dev/null
+++ b/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -0,0 +1,29 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Thu, 31 Aug 2023 21:48:38 +0200
+Subject: [PATCH] netfilter: nf_tables: ignore -EOPNOTSUPP on flowtable device
+ offload setup
+
+On many embedded devices, it is common to configure flowtable offloading for
+a mix of different devices, some of which have hardware offload support and
+some of which don't.
+The current code limits the ability of user space to properly set up such a
+configuration by only allowing adding devices with hardware offload support to
+a offload-enabled flowtable.
+Given that offload-enabled flowtables also imply fallback to pure software
+offloading, this limitation makes little sense.
+Fix it by not bailing out when the offload setup returns -EOPNOTSUPP
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/netfilter/nf_tables_api.c
++++ b/net/netfilter/nf_tables_api.c
+@@ -8202,7 +8202,7 @@ static int nft_register_flowtable_net_ho
+ 		err = flowtable->data.type->setup(&flowtable->data,
+ 						  hook->ops.dev,
+ 						  FLOW_BLOCK_BIND);
+-		if (err < 0)
++		if (err < 0 && err != -EOPNOTSUPP)
+ 			goto err_unregister_net_hooks;
+ 
+ 		err = nf_register_net_hook(net, &hook->ops);
diff --git a/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
new file mode 100644
index 00000000000000..11f0143e1909dd
--- /dev/null
+++ b/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -0,0 +1,21 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Mon, 21 Mar 2022 20:39:59 +0100
+Subject: [PATCH] net: ethernet: mtk_eth_soc: enable threaded NAPI
+
+This can improve performance under load by ensuring that NAPI processing is
+not pinned on CPU 0.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4978,6 +4978,8 @@ static int mtk_probe(struct platform_dev
+ 	 * for NAPI to work
+ 	 */
+ 	init_dummy_netdev(&eth->dummy_dev);
++	eth->dummy_dev.threaded = 1;
++	strcpy(eth->dummy_dev.name, "mtk_eth");
+ 	netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx);
+ 	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx);
+ 
diff --git a/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch
new file mode 100644
index 00000000000000..bf455fbd4def6e
--- /dev/null
+++ b/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch
@@ -0,0 +1,38 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: generic: add detach callback to struct phy_driver
+
+lede-commit: fe61fc2d7d0b3fb348b502f68f98243b3ddf5867
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/net/phy/phy_device.c | 3 +++
+ include/linux/phy.h          | 6 ++++++
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1801,6 +1801,9 @@ void phy_detach(struct phy_device *phyde
+ 	if (phydev->devlink)
+ 		device_link_del(phydev->devlink);
+ 
++	if (phydev->drv && phydev->drv->detach)
++		phydev->drv->detach(phydev);
++
+ 	if (phydev->sysfs_links) {
+ 		if (dev)
+ 			sysfs_remove_link(&dev->dev.kobj, "phydev");
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -963,6 +963,12 @@ struct phy_driver {
+ 	/** @handle_interrupt: Override default interrupt handling */
+ 	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
+ 
++	/*
++	 * Called before an ethernet device is detached
++	 * from the PHY.
++	 */
++	void (*detach)(struct phy_device *phydev);
++
+ 	/** @remove: Clears up any memory if needed */
+ 	void (*remove)(struct phy_device *phydev);
+ 
diff --git a/target/linux/generic/pending-6.6/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch b/target/linux/generic/pending-6.6/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch
new file mode 100644
index 00000000000000..f7e4e777732a81
--- /dev/null
+++ b/target/linux/generic/pending-6.6/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch
@@ -0,0 +1,28 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 6 May 2022 21:38:42 +0200
+Subject: [PATCH] net: dsa: tag_mtk: add padding for tx packets
+
+Padding for transmitted packets needs to account for the special tag.
+With not enough padding, garbage bytes are inserted by the switch at the
+end of small packets.
+
+Fixes: 5cd8985a1909 ("net-next: dsa: add Mediatek tag RX/TX handler")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/dsa/tag_mtk.c
++++ b/net/dsa/tag_mtk.c
+@@ -29,6 +29,13 @@ static struct sk_buff *mtk_tag_xmit(stru
+ 
+ 	skb_set_queue_mapping(skb, dp->index);
+ 
++	/* The Ethernet switch we are interfaced with needs packets to be at
++	 * least 64 bytes (including FCS) otherwise their padding might be
++	 * corrupted. With tags enabled, we need to make sure that packets are
++	 * at least 68 bytes (including FCS and tag).
++	 */
++	eth_skb_pad(skb);
++
+ 	/* Build the special tag after the MAC Source Address. If VLAN header
+ 	 * is present, it's required that VLAN header and special tag is
+ 	 * being combined. Only in this way we can allow the switch can parse
diff --git a/target/linux/generic/pending-6.6/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch b/target/linux/generic/pending-6.6/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch
new file mode 100644
index 00000000000000..72b22e474db473
--- /dev/null
+++ b/target/linux/generic/pending-6.6/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch
@@ -0,0 +1,101 @@
+From ace6abaa0f9203083fe4c0a6a74da2d96410b625 Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <lynxis@fe80.eu>
+Date: Sat, 13 Aug 2022 12:49:33 +0200
+Subject: [PATCH 01/10] net: phy: realtek: rtl8221: allow to configure SERDES
+ mode
+
+The rtl8221 supports multiple SERDES modes:
+- SGMII
+- 2500base-x
+- HiSGMII
+
+Further it supports rate adaption on SERDES links to allow
+slow ethernet speeds (10/100/1000mbit) to work on 2500base-x/HiSGMII
+links without reducing the SERDES speed.
+
+When operating without rate adapters the SERDES link will follow the
+ethernet speed.
+
+Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
+---
+ drivers/net/phy/realtek.c | 48 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -54,6 +54,15 @@
+ 						 RTL8201F_ISR_LINK)
+ #define RTL8201F_IER				0x13
+ 
++#define RTL8221B_MMD_SERDES_CTRL		MDIO_MMD_VEND1
++#define RTL8221B_MMD_PHY_CTRL			MDIO_MMD_VEND2
++#define RTL8221B_SERDES_OPTION			0x697a
++#define RTL8221B_SERDES_OPTION_MODE_MASK	GENMASK(5, 0)
++#define RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII	0
++#define RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII	1
++#define RTL8221B_SERDES_OPTION_MODE_2500BASEX		2
++#define RTL8221B_SERDES_OPTION_MODE_HISGMII		3
++
+ #define RTL8366RB_POWER_SAVE			0x15
+ #define RTL8366RB_POWER_SAVE_ON			BIT(12)
+ 
+@@ -877,6 +886,43 @@ static irqreturn_t rtl9000a_handle_inter
+ 	return IRQ_HANDLED;
+ }
+ 
++static int rtl8221b_config_init(struct phy_device *phydev)
++{
++	u16 option_mode;
++
++	switch (phydev->interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII;
++		break;
++	default:
++		return 0;
++	}
++
++	phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL,
++                      0x75f3, 0);
++
++	phy_modify_mmd_changed(phydev, RTL8221B_MMD_SERDES_CTRL,
++			       RTL8221B_SERDES_OPTION,
++			       RTL8221B_SERDES_OPTION_MODE_MASK, option_mode);
++	switch (option_mode) {
++        case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII:
++        case RTL8221B_SERDES_OPTION_MODE_2500BASEX:
++                phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
++                phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455);
++                phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
++                break;
++        case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII:
++        case RTL8221B_SERDES_OPTION_MODE_HISGMII:
++                phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
++                phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433);
++                phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
++                break;
++	}
++
++	return 0;
++}
++
+ static struct phy_driver realtek_drvs[] = {
+ 	{
+ 		PHY_ID_MATCH_EXACT(0x00008201),
+@@ -1031,6 +1077,7 @@ static struct phy_driver realtek_drvs[]
+ 		PHY_ID_MATCH_EXACT(0x001cc849),
+ 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
+ 		.get_features   = rtl822x_get_features,
++		.config_init	= rtl8221b_config_init,
+ 		.config_aneg    = rtl822x_config_aneg,
+ 		.read_status    = rtl822x_read_status,
+ 		.suspend        = genphy_suspend,
+@@ -1042,6 +1089,7 @@ static struct phy_driver realtek_drvs[]
+ 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
+ 		.get_features   = rtl822x_get_features,
+ 		.config_aneg    = rtl822x_config_aneg,
++		.config_init	= rtl8221b_config_init,
+ 		.read_status    = rtl822x_read_status,
+ 		.suspend        = genphy_suspend,
+ 		.resume         = rtlgen_resume,
diff --git a/target/linux/generic/pending-6.6/722-net-phy-realtek-support-switching-between-SGMII-and-.patch b/target/linux/generic/pending-6.6/722-net-phy-realtek-support-switching-between-SGMII-and-.patch
new file mode 100644
index 00000000000000..035f0581251c7b
--- /dev/null
+++ b/target/linux/generic/pending-6.6/722-net-phy-realtek-support-switching-between-SGMII-and-.patch
@@ -0,0 +1,61 @@
+From 312753d0aadba0f58841ae513b80fdbabc887523 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Wed, 8 Feb 2023 16:32:18 +0800
+Subject: [PATCH] net: phy: realtek: support switching between SGMII and
+ 2500BASE-X for RTL822x series
+
+After commit ace6aba ("net: phy: realtek: rtl8221: allow to configure
+SERDES mode"), the rtl8221 phy can work in SGMII and 2500base-x modes
+respectively. So add interface automatic switching for rtl8221 phy to
+match various wire speeds.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ drivers/net/phy/realtek.c | 26 ++++++++++++++++++++++++--
+ 1 file changed, 24 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -712,6 +712,25 @@ static int rtl822x_config_aneg(struct ph
+ 	return __genphy_config_aneg(phydev, ret);
+ }
+ 
++static void rtl822x_update_interface(struct phy_device *phydev)
++{
++	/* Automatically switch SERDES interface between
++	 * SGMII and 2500-BaseX according to speed.
++	 */
++	switch (phydev->speed) {
++	case SPEED_2500:
++		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++		break;
++	case SPEED_1000:
++	case SPEED_100:
++	case SPEED_10:
++		phydev->interface = PHY_INTERFACE_MODE_SGMII;
++		break;
++	default:
++		break;
++	}
++}
++
+ static int rtl822x_read_status(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -730,11 +749,14 @@ static int rtl822x_read_status(struct ph
+ 			phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
+ 	}
+ 
+-	ret = genphy_read_status(phydev);
++	ret = rtlgen_read_status(phydev);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	return rtlgen_get_speed(phydev);
++	if (phydev->link)
++		rtl822x_update_interface(phydev);
++
++	return 0;
+ }
+ 
+ static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
diff --git a/target/linux/generic/pending-6.6/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-6.6/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
new file mode 100644
index 00000000000000..4ab8e24f994250
--- /dev/null
+++ b/target/linux/generic/pending-6.6/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
@@ -0,0 +1,28 @@
+From 3fb8841513c4ec3a2e5d366df86230c45f239a57 Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <lynxis@fe80.eu>
+Date: Sat, 13 Aug 2022 13:08:22 +0200
+Subject: [PATCH 03/10] net: mt7531: ensure all MACs are powered down before
+ reset
+
+The datasheet [1] explicit describes it as requirement for a reset.
+
+[1] MT7531 Reference Manual for Development Board rev 1.0, page 735
+
+Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
+---
+ drivers/net/dsa/mt7530.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2268,6 +2268,10 @@ mt7530_setup(struct dsa_switch *ds)
+ 		return -ENODEV;
+ 	}
+ 
++	/* all MACs must be forced link-down before sw reset */
++	for (i = 0; i < MT7530_NUM_PORTS; i++)
++		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++
+ 	/* Reset the switch through internal reset */
+ 	mt7530_write(priv, MT7530_SYS_CTRL,
+ 		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
diff --git a/target/linux/generic/pending-6.6/724-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch b/target/linux/generic/pending-6.6/724-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch
new file mode 100644
index 00000000000000..70dab32724a847
--- /dev/null
+++ b/target/linux/generic/pending-6.6/724-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch
@@ -0,0 +1,65 @@
+From 85cd45580f5e3b26068cccb7d6173f200e754dc0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 2 Apr 2023 23:56:16 +0100
+Subject: [PATCH 1/2] net: phy: realtek: use genphy_soft_reset for 2.5G PHYs
+
+Some vendor bootloaders do weird things with those PHYs which result in
+link modes being reported wrongly. Start from a clean sheet by resetting
+the PHY.
+
+Reported-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/realtek.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -1063,6 +1063,7 @@ static struct phy_driver realtek_drvs[]
+ 		.write_page	= rtl821x_write_page,
+ 		.read_mmd	= rtl822x_read_mmd,
+ 		.write_mmd	= rtl822x_write_mmd,
++		.soft_reset     = genphy_soft_reset,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc840),
+ 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
+@@ -1075,6 +1076,7 @@ static struct phy_driver realtek_drvs[]
+ 		.write_page	= rtl821x_write_page,
+ 		.read_mmd	= rtl822x_read_mmd,
+ 		.write_mmd	= rtl822x_write_mmd,
++		.soft_reset     = genphy_soft_reset,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc838),
+ 		.name           = "RTL8226-CG 2.5Gbps PHY",
+@@ -1085,6 +1087,7 @@ static struct phy_driver realtek_drvs[]
+ 		.resume         = rtlgen_resume,
+ 		.read_page      = rtl821x_read_page,
+ 		.write_page     = rtl821x_write_page,
++		.soft_reset     = genphy_soft_reset,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc848),
+ 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
+@@ -1095,6 +1098,7 @@ static struct phy_driver realtek_drvs[]
+ 		.resume         = rtlgen_resume,
+ 		.read_page      = rtl821x_read_page,
+ 		.write_page     = rtl821x_write_page,
++		.soft_reset     = genphy_soft_reset,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc849),
+ 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
+@@ -1106,6 +1110,7 @@ static struct phy_driver realtek_drvs[]
+ 		.resume         = rtlgen_resume,
+ 		.read_page      = rtl821x_read_page,
+ 		.write_page     = rtl821x_write_page,
++		.soft_reset     = genphy_soft_reset,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc84a),
+ 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
+@@ -1117,6 +1122,7 @@ static struct phy_driver realtek_drvs[]
+ 		.resume         = rtlgen_resume,
+ 		.read_page      = rtl821x_read_page,
+ 		.write_page     = rtl821x_write_page,
++		.soft_reset     = genphy_soft_reset,
+ 	}, {
+ 		PHY_ID_MATCH_EXACT(0x001cc961),
+ 		.name		= "RTL8366RB Gigabit Ethernet",
diff --git a/target/linux/generic/pending-6.6/725-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch b/target/linux/generic/pending-6.6/725-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch
new file mode 100644
index 00000000000000..725babb2aa0610
--- /dev/null
+++ b/target/linux/generic/pending-6.6/725-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch
@@ -0,0 +1,43 @@
+From 2b1b8c4c215af7988136401c902338d091d408a1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 01:21:57 +0300
+Subject: [PATCH 2/2] net: phy: realtek: disable SGMII in-band AN for 2.5G PHYs
+
+MAC drivers don't use SGMII in-band autonegotiation unless told to do so
+in device tree using 'managed = "in-band-status"'. When using MDIO to
+access a PHY, in-band-status is unneeded as we have link-status via
+MDIO. Switch off SGMII in-band autonegotiation using magic values.
+
+Reported-by: Chen Minqiang <ptpt52@gmail.com>
+Reported-by: Chukun Pan <amadeus@jmu.edu.cn>
+Reported-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
+Tested-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/realtek.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -911,6 +911,7 @@ static irqreturn_t rtl9000a_handle_inter
+ static int rtl8221b_config_init(struct phy_device *phydev)
+ {
+ 	u16 option_mode;
++	int val;
+ 
+ 	switch (phydev->interface) {
+ 	case PHY_INTERFACE_MODE_SGMII:
+@@ -942,6 +943,13 @@ static int rtl8221b_config_init(struct p
+                 break;
+ 	}
+ 
++	/* Disable SGMII AN */
++	phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7588, 0x2);
++	phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7589, 0x71d0);
++	phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587, 0x3);
++	phy_read_mmd_poll_timeout(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587, val,
++				  !(val & BIT(0)), 500, 100000, false);
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
new file mode 100644
index 00000000000000..332d7e721a70e0
--- /dev/null
+++ b/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
@@ -0,0 +1,27 @@
+From:   Tobias Waldekranz <tobias@waldekranz.com>
+Subject: [RFC net-next 7/7] net: dsa: mv88e6xxx: Request assisted learning on CPU port
+Date:   Sat, 16 Jan 2021 02:25:15 +0100
+Archived-At: <https://lore.kernel.org/netdev/20210116012515.3152-8-tobias@waldekranz.com/>
+
+While the hardware is capable of performing learning on the CPU port,
+it requires alot of additions to the bridge's forwarding path in order
+to handle multi-destination traffic correctly.
+
+Until that is in place, opt for the next best thing and let DSA sync
+the relevant addresses down to the hardware FDB.
+
+Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -6883,6 +6883,7 @@ static int mv88e6xxx_register_switch(str
+ 	ds->ops = &mv88e6xxx_switch_ops;
+ 	ds->ageing_time_min = chip->info->age_time_coeff;
+ 	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
++	ds->assisted_learning_on_cpu_port = true;
+ 
+ 	/* Some chips support up to 32, but that requires enabling the
+ 	 * 5-bit port mode, which we do not support. 640k^W16 ought to
diff --git a/target/linux/generic/pending-6.6/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch b/target/linux/generic/pending-6.6/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch
new file mode 100644
index 00000000000000..39ba71606ec235
--- /dev/null
+++ b/target/linux/generic/pending-6.6/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch
@@ -0,0 +1,61 @@
+From patchwork Thu Aug  5 22:23:30 2021
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 12422209
+Date: Thu, 5 Aug 2021 23:23:30 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,
+ linux-kernel@vger.kernel.org
+Cc: "David S. Miller" <davem@davemloft.net>, Andrew Lunn <andrew@lunn.ch>,
+ Michael Walle <michael@walle.cc>
+Subject: [PATCH] ARM: kirkwood: add missing <linux/if_ether.h> for ETH_ALEN
+Message-ID: <YQxk4jrbm31NM1US@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+X-BeenThere: linux-arm-kernel@lists.infradead.org
+X-Mailman-Version: 2.1.34
+Precedence: list
+List-Id: <linux-arm-kernel.lists.infradead.org>
+List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
+Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
+
+After commit 83216e3988cd1 ("of: net: pass the dst buffer to
+of_get_mac_address()") build fails for kirkwood as ETH_ALEN is not
+defined.
+
+arch/arm/mach-mvebu/kirkwood.c: In function 'kirkwood_dt_eth_fixup':
+arch/arm/mach-mvebu/kirkwood.c:87:13: error: 'ETH_ALEN' undeclared (first use in this function); did you mean 'ESTALE'?
+   u8 tmpmac[ETH_ALEN];
+             ^~~~~~~~
+             ESTALE
+arch/arm/mach-mvebu/kirkwood.c:87:13: note: each undeclared identifier is reported only once for each function it appears in
+arch/arm/mach-mvebu/kirkwood.c:87:6: warning: unused variable 'tmpmac' [-Wunused-variable]
+   u8 tmpmac[ETH_ALEN];
+      ^~~~~~
+make[5]: *** [scripts/Makefile.build:262: arch/arm/mach-mvebu/kirkwood.o] Error 1
+make[5]: *** Waiting for unfinished jobs....
+
+Add missing #include <linux/if_ether.h> to fix this.
+
+Cc: David S. Miller <davem@davemloft.net>
+Cc: Andrew Lunn <andrew@lunn.ch>
+Cc: Michael Walle <michael@walle.cc>
+Reported-by: https://buildbot.openwrt.org/master/images/#/builders/56/builds/220/steps/44/logs/stdio
+Fixes: 83216e3988cd1 ("of: net: pass the dst buffer to of_get_mac_address()")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ arch/arm/mach-mvebu/kirkwood.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-mvebu/kirkwood.c
++++ b/arch/arm/mach-mvebu/kirkwood.c
+@@ -11,6 +11,7 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/mbus.h>
++#include <linux/if_ether.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_net.h>
diff --git a/target/linux/generic/pending-6.6/790-bus-mhi-core-add-SBL-state-callback.patch b/target/linux/generic/pending-6.6/790-bus-mhi-core-add-SBL-state-callback.patch
new file mode 100644
index 00000000000000..874df43e7ce6fc
--- /dev/null
+++ b/target/linux/generic/pending-6.6/790-bus-mhi-core-add-SBL-state-callback.patch
@@ -0,0 +1,48 @@
+From 5f7c5e1c0d7a79be144e5efc1f24728ddd7fc25c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 5 Nov 2022 20:02:56 +0100
+Subject: [PATCH 1/2] bus: mhi: core: add SBL state callback
+
+Add support for SBL state callback in MHI core.
+
+It is required for ath11k MHI devices in order to be able to set QRTR
+instance ID in the SBL state so that QRTR instance ID-s dont conflict in
+case of multiple PCI/MHI cards or AHB + PCI/MHI card.
+Setting QRTR instance ID is only possible in SBL state and there is
+currently no way to ensure that we are in that state, so provide a
+callback that the controller can trigger off.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/bus/mhi/host/main.c | 1 +
+ include/linux/mhi.h         | 2 ++
+ 2 files changed, 3 insertions(+)
+
+--- a/drivers/bus/mhi/host/main.c
++++ b/drivers/bus/mhi/host/main.c
+@@ -900,6 +900,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
+ 			switch (event) {
+ 			case MHI_EE_SBL:
+ 				st = DEV_ST_TRANSITION_SBL;
++				mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_SBL_MODE);
+ 				break;
+ 			case MHI_EE_WFW:
+ 			case MHI_EE_AMSS:
+--- a/include/linux/mhi.h
++++ b/include/linux/mhi.h
+@@ -34,6 +34,7 @@ struct mhi_buf_info;
+  * @MHI_CB_SYS_ERROR: MHI device entered error state (may recover)
+  * @MHI_CB_FATAL_ERROR: MHI device entered fatal error state
+  * @MHI_CB_BW_REQ: Received a bandwidth switch request from device
++ * @MHI_CB_EE_SBL_MODE: MHI device entered SBL mode
+  */
+ enum mhi_callback {
+ 	MHI_CB_IDLE,
+@@ -45,6 +46,7 @@ enum mhi_callback {
+ 	MHI_CB_SYS_ERROR,
+ 	MHI_CB_FATAL_ERROR,
+ 	MHI_CB_BW_REQ,
++	MHI_CB_EE_SBL_MODE,
+ };
+ 
+ /**
diff --git a/target/linux/generic/pending-6.6/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-6.6/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
new file mode 100644
index 00000000000000..4b5eb767fd5f96
--- /dev/null
+++ b/target/linux/generic/pending-6.6/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
@@ -0,0 +1,43 @@
+From 1d81e51d6d79d9098013b2e8cdd677bae998c5d8 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 28 Apr 2023 02:22:59 +0200
+Subject: [PATCH 1/2] mt7530: register OF node for internal MDIO bus
+
+The MT753x switches provide a switch-internal MDIO bus for the embedded
+PHYs.
+
+Register a OF sub-node on the switch OF-node for this internal MDIO bus.
+This allows to configure the embedded PHYs using device-tree.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/dsa/mt7530.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2156,10 +2156,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+ {
+ 	struct dsa_switch *ds = priv->ds;
+ 	struct device *dev = priv->dev;
++	struct device_node *np, *mnp;
+ 	struct mii_bus *bus;
+ 	static int idx;
+ 	int ret;
+ 
++	np = priv->dev->of_node;
++
+ 	bus = devm_mdiobus_alloc(dev);
+ 	if (!bus)
+ 		return -ENOMEM;
+@@ -2178,7 +2181,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+ 	if (priv->irq)
+ 		mt7530_setup_mdio_irq(priv);
+ 
+-	ret = devm_mdiobus_register(dev, bus);
++	mnp = of_get_child_by_name(np, "mdio");
++	ret = devm_of_mdiobus_register(dev, bus, mnp);
++	of_node_put(mnp);
+ 	if (ret) {
+ 		dev_err(dev, "failed to register MDIO bus: %d\n", ret);
+ 		if (priv->irq)
diff --git a/target/linux/generic/pending-6.6/796-dt-bindings-net-dsa-mediatek-mt7530-document-MDIO-bu.patch b/target/linux/generic/pending-6.6/796-dt-bindings-net-dsa-mediatek-mt7530-document-MDIO-bu.patch
new file mode 100644
index 00000000000000..ed4a29e0c42f33
--- /dev/null
+++ b/target/linux/generic/pending-6.6/796-dt-bindings-net-dsa-mediatek-mt7530-document-MDIO-bu.patch
@@ -0,0 +1,28 @@
+From 76cf5b6b03f2e5185f1f59e1afb39c0c9c51d8ce Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 30 Apr 2023 13:28:33 +0200
+Subject: [PATCH] dt-bindings: net: dsa: mediatek,mt7530: document MDIO-bus
+
+Document the ability to add nodes for the MDIO bus connecting the
+switch-internal PHYs.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml        | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
++++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+@@ -128,6 +128,12 @@ properties:
+       See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
+       details for the regulator setup on these boards.
+ 
++  mdio:
++    $ref: /schemas/net/mdio.yaml#
++    unevaluatedProperties: false
++    description:
++      Node for the internal MDIO bus connected to the embedded ethernet-PHYs.
++
+   mediatek,mcm:
+     type: boolean
+     description:
diff --git a/target/linux/generic/pending-6.6/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch b/target/linux/generic/pending-6.6/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch
new file mode 100644
index 00000000000000..4a9c188d179686
--- /dev/null
+++ b/target/linux/generic/pending-6.6/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch
@@ -0,0 +1,73 @@
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH] bcma: get SoC device struct & copy its DMA params to the
+ subdevices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For bus devices to be fully usable it's required to set their DMA
+parameters.
+
+For years it has been missing and remained unnoticed because of
+mips_dma_alloc_coherent() silently handling the empty coherent_dma_mask.
+Kernel 4.19 came with a lot of DMA changes and caused a regression on
+the bcm47xx. Starting with the commit f8c55dc6e828 ("MIPS: use generic
+dma noncoherent ops for simple noncoherent platforms") DMA coherent
+allocations just fail. Example:
+[    1.114914] bgmac_bcma bcma0:2: Allocation of TX ring 0x200 failed
+[    1.121215] bgmac_bcma bcma0:2: Unable to alloc memory for DMA
+[    1.127626] bgmac_bcma: probe of bcma0:2 failed with error -12
+[    1.133838] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
+
+This change fixes above regression in addition to the MIPS bcm47xx
+commit 321c46b91550 ("MIPS: BCM47XX: Setup struct device for the SoC").
+
+It also fixes another *old* GPIO regression caused by a parent pointing
+to the NULL:
+[    0.157054] missing gpiochip .dev parent pointer
+[    0.157287] bcma: bus0: Error registering GPIO driver: -22
+introduced by the commit 74f4e0cc6108 ("bcma: switch GPIO portions to
+use GPIOLIB_IRQCHIP").
+
+Fixes: f8c55dc6e828 ("MIPS: use generic dma noncoherent ops for simple noncoherent platforms")
+Fixes: 74f4e0cc6108 ("bcma: switch GPIO portions to use GPIOLIB_IRQCHIP")
+Cc: linux-mips@linux-mips.org
+Cc: Christoph Hellwig <hch@lst.de>
+Cc: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/bcma/host_soc.c
++++ b/drivers/bcma/host_soc.c
+@@ -191,6 +191,8 @@ int __init bcma_host_soc_init(struct bcm
+ 	struct bcma_bus *bus = &soc->bus;
+ 	int err;
+ 
++	bus->dev = soc->dev;
++
+ 	/* Scan bus and initialize it */
+ 	err = bcma_bus_early_register(bus);
+ 	if (err)
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -237,13 +237,17 @@ EXPORT_SYMBOL(bcma_core_irq);
+ 
+ void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core)
+ {
+-	device_initialize(&core->dev);
++	struct device *dev = &core->dev;
++
++	device_initialize(dev);
+ 	core->dev.release = bcma_release_core_dev;
+ 	core->dev.bus = &bcma_bus_type;
+-	dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
++	dev_set_name(dev, "bcma%d:%d", bus->num, core->core_index);
+ 	core->dev.parent = bus->dev;
+-	if (bus->dev)
++	if (bus->dev) {
+ 		bcma_of_fill_device(bus->dev, core);
++		dma_coerce_mask_and_coherent(dev, bus->dev->coherent_dma_mask);
++	}
+ 
+ 	switch (bus->hosttype) {
+ 	case BCMA_HOSTTYPE_PCI:
diff --git a/target/linux/generic/pending-6.6/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch b/target/linux/generic/pending-6.6/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch
new file mode 100644
index 00000000000000..ca4101f14888d4
--- /dev/null
+++ b/target/linux/generic/pending-6.6/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch
@@ -0,0 +1,222 @@
+From fc23ea48ba52c24f201fe5ca0132ee1a3de5a70a Mon Sep 17 00:00:00 2001
+From: Mauri Sandberg <maukka@ext.kapsi.fi>
+Date: Thu, 25 Mar 2021 11:48:05 +0200
+Subject: [PATCH 2/2] gpio: gpio-cascade: add generic GPIO cascade
+
+Adds support for building cascades of GPIO lines. That is, it allows
+setups when there is one upstream line and multiple cascaded lines, out
+of which one can be chosen at a time. The status of the upstream line
+can be conveyed to the selected cascaded line or, vice versa, the status
+of the cascaded line can be conveyed to the upstream line.
+
+A multiplexer is being used to select, which cascaded GPIO line is being
+used at any given time.
+
+At the moment only input direction is supported. In future it should be
+possible to add support for output direction, too.
+
+Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+---
+v7 -> v8:
+ - rearrange members in struct gpio_cascade
+ - cosmetic changes in file header and in one function declaration
+ - added Reviewed-by tags by Linus and Andy
+v6 -> v7:
+ - In Kconfig add info about module name
+ - adhere to new convention that allows lines longer than 80 chars
+ - use dev_probe_err with upstream gpio line too
+ - refactor for cleaner exit of probe function.
+v5 -> v6:
+ - In Kconfig, remove dependency to OF_GPIO and select only MULTIPLEXER
+ - refactor code preferring one-liners
+ - clean up prints, removing them from success-path.
+ - don't explicitly set gpio_chip.of_node as it's done in the GPIO library
+ - use devm_gpiochip_add_data instead of gpiochip_add
+v4 -> v5:
+ - renamed gpio-mux-input -> gpio-cascade. refactored code accordingly
+   here and there and changed to use new bindings and compatible string
+   - ambigious and vague 'pin' was rename to 'upstream_line'
+ - dropped Tested-by and Reviewed-by due to changes in bindings
+ - dropped Reported-by suggested by an automatic bot as it was not really
+   appropriate to begin with
+ - functionally it's the same as v4
+v3 -> v4:
+ - Changed author email
+ - Included Tested-by and Reviewed-by from Drew
+v2 -> v3:
+ - use managed device resources
+ - update Kconfig description
+v1 -> v2:
+ - removed .owner from platform_driver as per test bot's instruction
+ - added MODULE_AUTHOR, MODULE_DESCRIPTION, MODULE_LICENSE
+ - added gpio_mux_input_get_direction as it's recommended for all chips
+ - removed because this is input only chip: gpio_mux_input_set_value
+ - removed because they are not needed for input/output only chips:
+     gpio_mux_input_direction_input
+     gpio_mux_input_direction_output
+ - fixed typo in an error message
+ - added info message about successful registration
+ - removed can_sleep flag as this does not sleep while getting GPIO value
+   like I2C or SPI do
+ - Updated description in Kconfig
+---
+ drivers/gpio/Kconfig        |  15 +++++
+ drivers/gpio/Makefile       |   1 +
+ drivers/gpio/gpio-cascade.c | 117 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 133 insertions(+)
+ create mode 100644 drivers/gpio/gpio-cascade.c
+
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -1819,4 +1819,19 @@ config GPIO_SIM
+ 
+ endmenu
+ 
++comment "Other GPIO expanders"
++
++config GPIO_CASCADE
++	tristate "General GPIO cascade"
++	select MULTIPLEXER
++	help
++	  Say yes here to enable support for generic GPIO cascade.
++
++	  This allows building one-to-many cascades of GPIO lines using
++	  different types of multiplexers readily available. At the
++	  moment only input lines are supported.
++
++	  To build the driver as a module choose 'm' and the resulting module
++	  will be called 'gpio-cascade'.
++
+ endif
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_GPIO_BD9571MWV)		+= gpio-bd
+ obj-$(CONFIG_GPIO_BRCMSTB)		+= gpio-brcmstb.o
+ obj-$(CONFIG_GPIO_BT8XX)		+= gpio-bt8xx.o
+ obj-$(CONFIG_GPIO_CADENCE)		+= gpio-cadence.o
++obj-$(CONFIG_GPIO_CASCADE)		+= gpio-cascade.o
+ obj-$(CONFIG_GPIO_CLPS711X)		+= gpio-clps711x.o
+ obj-$(CONFIG_GPIO_SNPS_CREG)		+= gpio-creg-snps.o
+ obj-$(CONFIG_GPIO_CRYSTAL_COVE)		+= gpio-crystalcove.o
+--- /dev/null
++++ b/drivers/gpio/gpio-cascade.c
+@@ -0,0 +1,117 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ *  A generic GPIO cascade driver
++ *
++ *  Copyright (C) 2021 Mauri Sandberg <maukka@ext.kapsi.fi>
++ *
++ * This allows building cascades of GPIO lines in a manner illustrated
++ * below:
++ *
++ *                 /|---- Cascaded GPIO line 0
++ *  Upstream      | |---- Cascaded GPIO line 1
++ *  GPIO line ----+ | .
++ *                | | .
++ *                 \|---- Cascaded GPIO line n
++ *
++ * A multiplexer is being used to select, which cascaded line is being
++ * addressed at any given time.
++ *
++ * At the moment only input mode is supported due to lack of means for
++ * testing output functionality. At least theoretically output should be
++ * possible with open drain constructions.
++ */
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++#include <linux/mux/consumer.h>
++
++#include <linux/gpio/consumer.h>
++#include <linux/gpio/driver.h>
++
++struct gpio_cascade {
++	struct gpio_chip	gpio_chip;
++	struct device		*parent;
++	struct mux_control	*mux_control;
++	struct gpio_desc	*upstream_line;
++};
++
++static struct gpio_cascade *chip_to_cascade(struct gpio_chip *gc)
++{
++	return container_of(gc, struct gpio_cascade, gpio_chip);
++}
++
++static int gpio_cascade_get_direction(struct gpio_chip *gc, unsigned int offset)
++{
++	return GPIO_LINE_DIRECTION_IN;
++}
++
++static int gpio_cascade_get_value(struct gpio_chip *gc, unsigned int offset)
++{
++	struct gpio_cascade *cas = chip_to_cascade(gc);
++	int ret;
++
++	ret = mux_control_select(cas->mux_control, offset);
++	if (ret)
++		return ret;
++
++	ret = gpiod_get_value(cas->upstream_line);
++	mux_control_deselect(cas->mux_control);
++	return ret;
++}
++
++static int gpio_cascade_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct gpio_cascade *cas;
++	struct mux_control *mc;
++	struct gpio_desc *upstream;
++	struct gpio_chip *gc;
++
++	cas = devm_kzalloc(dev, sizeof(*cas), GFP_KERNEL);
++	if (!cas)
++		return -ENOMEM;
++
++	mc = devm_mux_control_get(dev, NULL);
++	if (IS_ERR(mc))
++		return dev_err_probe(dev, PTR_ERR(mc), "unable to get mux-control\n");
++
++	cas->mux_control = mc;
++	upstream = devm_gpiod_get(dev, "upstream",  GPIOD_IN);
++	if (IS_ERR(upstream))
++		return dev_err_probe(dev, PTR_ERR(upstream), "unable to claim upstream GPIO line\n");
++
++	cas->upstream_line = upstream;
++	cas->parent = dev;
++
++	gc = &cas->gpio_chip;
++	gc->get = gpio_cascade_get_value;
++	gc->get_direction = gpio_cascade_get_direction;
++	gc->base = -1;
++	gc->ngpio = mux_control_states(mc);
++	gc->label = dev_name(cas->parent);
++	gc->parent = cas->parent;
++	gc->owner = THIS_MODULE;
++
++	platform_set_drvdata(pdev, cas);
++	return devm_gpiochip_add_data(dev, &cas->gpio_chip, NULL);
++}
++
++static const struct of_device_id gpio_cascade_id[] = {
++	{ .compatible = "gpio-cascade" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, gpio_cascade_id);
++
++static struct platform_driver gpio_cascade_driver = {
++	.driver	= {
++		.name		= "gpio-cascade",
++		.of_match_table = gpio_cascade_id,
++	},
++	.probe	= gpio_cascade_probe,
++};
++module_platform_driver(gpio_cascade_driver);
++
++MODULE_AUTHOR("Mauri Sandberg <maukka@ext.kapsi.fi>");
++MODULE_DESCRIPTION("Generic GPIO cascade");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.6/810-pci_disable_common_quirks.patch b/target/linux/generic/pending-6.6/810-pci_disable_common_quirks.patch
new file mode 100644
index 00000000000000..513824d9e8a565
--- /dev/null
+++ b/target/linux/generic/pending-6.6/810-pci_disable_common_quirks.patch
@@ -0,0 +1,62 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: debloat: add kernel config option to disabling common PCI quirks
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/pci/Kconfig  | 6 ++++++
+ drivers/pci/quirks.c | 6 ++++++
+ 2 files changed, 12 insertions(+)
+
+--- a/drivers/pci/Kconfig
++++ b/drivers/pci/Kconfig
+@@ -113,6 +113,13 @@ config XEN_PCIDEV_FRONTEND
+ 	  The PCI device frontend driver allows the kernel to import arbitrary
+ 	  PCI devices from a PCI backend to support PCI driver domains.
+ 
++config PCI_DISABLE_COMMON_QUIRKS
++	bool "PCI disable common quirks"
++	depends on PCI
++	help
++	  If you don't know what to do here, say N.
++
++
+ config PCI_ATS
+ 	bool
+ 
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -300,6 +300,7 @@ static void quirk_mmio_always_on(struct
+ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
+ 				PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
+ 
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
+ /*
+  * The Mellanox Tavor device gives false positive parity errors.  Disable
+  * parity error reporting.
+@@ -3485,6 +3486,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
+ 
++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
++
+ /*
+  * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
+  * To work around this, query the size it should be configured to by the
+@@ -3510,6 +3513,8 @@ static void quirk_intel_ntb(struct pci_d
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
+ 
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
++
+ /*
+  * Some BIOS implementations leave the Intel GPU interrupts enabled, even
+  * though no one is handling them (e.g., if the i915 driver is never
+@@ -3548,6 +3553,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
+ 
++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
++
+ /*
+  * PCI devices which are on Intel chips can skip the 10ms delay
+  * before entering D3 mode.
diff --git a/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch
new file mode 100644
index 00000000000000..4c271a7bd807fb
--- /dev/null
+++ b/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch
@@ -0,0 +1,115 @@
+From: Felix Fietkau <nbd@nbd.name>
+Subject: debloat: disable common USB quirks
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+ drivers/usb/host/pci-quirks.c | 16 ++++++++++++++++
+ drivers/usb/host/pci-quirks.h | 18 +++++++++++++++++-
+ include/linux/usb/hcd.h       |  7 +++++++
+ 3 files changed, 40 insertions(+), 1 deletion(-)
+
+--- a/drivers/usb/host/pci-quirks.c
++++ b/drivers/usb/host/pci-quirks.c
+@@ -128,6 +128,8 @@ struct amd_chipset_type {
+ 	u8 rev;
+ };
+ 
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
++
+ static struct amd_chipset_info {
+ 	struct pci_dev	*nb_dev;
+ 	struct pci_dev	*smbus_dev;
+@@ -631,6 +633,10 @@ bool usb_amd_pt_check_port(struct device
+ }
+ EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
+ 
++#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */
++
++#if IS_ENABLED(CONFIG_USB_UHCI_HCD)
++
+ /*
+  * Make sure the controller is completely inactive, unable to
+  * generate interrupts or do DMA.
+@@ -710,8 +716,17 @@ reset_needed:
+ 	uhci_reset_hc(pdev, base);
+ 	return 1;
+ }
++#else
++int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
++{
++	return 0;
++}
++
++#endif
+ EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
+ 
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
++
+ static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
+ {
+ 	u16 cmd;
+@@ -1283,3 +1298,4 @@ static void quirk_usb_early_handoff(stru
+ }
+ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+ 			PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
++#endif
+--- a/drivers/usb/host/pci-quirks.h
++++ b/drivers/usb/host/pci-quirks.h
+@@ -5,6 +5,9 @@
+ #ifdef CONFIG_USB_PCI
+ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
+ int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
++#endif  /* CONFIG_USB_PCI */
++
++#if defined(CONFIG_USB_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS)
+ int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev);
+ bool usb_amd_hang_symptom_quirk(void);
+ bool usb_amd_prefetch_quirk(void);
+@@ -19,6 +22,18 @@ void sb800_prefetch(struct device *dev,
+ bool usb_amd_pt_check_port(struct device *device, int port);
+ #else
+ struct pci_dev;
++static inline int usb_amd_quirk_pll_check(void)
++{
++	return 0;
++}
++static inline bool usb_amd_hang_symptom_quirk(void)
++{
++	return false;
++}
++static inline bool usb_amd_prefetch_quirk(void)
++{
++	return false;
++}
+ static inline void usb_amd_quirk_pll_disable(void) {}
+ static inline void usb_amd_quirk_pll_enable(void) {}
+ static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {}
+@@ -29,6 +44,11 @@ static inline bool usb_amd_pt_check_port
+ {
+ 	return false;
+ }
++static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {}
++static inline bool usb_xhci_needs_pci_reset(struct pci_dev *pdev)
++{
++	return false;
++}
+ #endif  /* CONFIG_USB_PCI */
+ 
+ #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
+--- a/include/linux/usb/hcd.h
++++ b/include/linux/usb/hcd.h
+@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
+ extern void usb_hcd_pci_remove(struct pci_dev *dev);
+ extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
+ 
++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
+ extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev);
++#else
++static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev)
++{
++	return 0;
++}
++#endif
+ 
+ extern const struct dev_pm_ops usb_hcd_pci_pm_ops;
+ #endif /* CONFIG_USB_PCI */
diff --git a/target/linux/generic/pending-6.6/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch b/target/linux/generic/pending-6.6/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch
new file mode 100644
index 00000000000000..33eb34c913ea4a
--- /dev/null
+++ b/target/linux/generic/pending-6.6/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch
@@ -0,0 +1,26 @@
+From d9c8bc8c1408f3e8529db6e4e04017b4c579c342 Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Sun, 18 Feb 2018 17:08:04 +0100
+Subject: [PATCH] w1: gpio: fix problem with platfom data in w1-gpio
+
+In devices, where fdt is used, is impossible to apply platform data
+without proper fdt node.
+
+This patch allow to use platform data in devices with fdt.
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ drivers/w1/masters/w1-gpio.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- a/drivers/w1/masters/w1-gpio.c
++++ b/drivers/w1/masters/w1-gpio.c
+@@ -76,7 +76,7 @@ static int w1_gpio_probe(struct platform
+ 	enum gpiod_flags gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
+ 	int err;
+ 
+-	if (of_have_populated_dt()) {
++	if (of_have_populated_dt() && !dev_get_platdata(&pdev->dev)) {
+ 		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ 		if (!pdata)
+ 			return -ENOMEM;
diff --git a/target/linux/generic/pending-6.6/834-ledtrig-libata.patch b/target/linux/generic/pending-6.6/834-ledtrig-libata.patch
new file mode 100644
index 00000000000000..b256f166e9c0d5
--- /dev/null
+++ b/target/linux/generic/pending-6.6/834-ledtrig-libata.patch
@@ -0,0 +1,149 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Subject: libata: add ledtrig support
+
+This adds a LED trigger for each ATA port indicating disk activity.
+
+As this is needed only on specific platforms (NAS SoCs and such),
+these platforms should define ARCH_WANTS_LIBATA_LEDS if there
+are boards with LED(s) intended to indicate ATA disk activity and
+need the OS to take care of that.
+In that way, if not selected, LED trigger support not will be
+included in libata-core and both, codepaths and structures remain
+untouched.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/ata/Kconfig       | 16 ++++++++++++++++
+ drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++
+ include/linux/libata.h    |  9 +++++++++
+ 3 files changed, 66 insertions(+)
+
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -67,6 +67,22 @@ config ATA_FORCE
+ 
+ 	  If unsure, say Y.
+ 
++config ARCH_WANT_LIBATA_LEDS
++	bool
++
++config ATA_LEDS
++	bool "support ATA port LED triggers"
++	depends on ARCH_WANT_LIBATA_LEDS
++	select NEW_LEDS
++	select LEDS_CLASS
++	select LEDS_TRIGGERS
++	default y
++	help
++	  This option adds a LED trigger for each registered ATA port.
++	  It is used to drive disk activity leds connected via GPIO.
++
++	  If unsure, say N.
++
+ config ATA_ACPI
+ 	bool "ATA ACPI Support"
+ 	depends on ACPI
+--- a/drivers/ata/libata-core.c
++++ b/drivers/ata/libata-core.c
+@@ -685,6 +685,19 @@ static inline void ata_set_tf_cdl(struct
+ 	qc->flags |= ATA_QCFLAG_HAS_CDL | ATA_QCFLAG_RESULT_TF;
+ }
+ 
++#ifdef CONFIG_ATA_LEDS
++#define LIBATA_BLINK_DELAY 20 /* ms */
++static inline void ata_led_act(struct ata_port *ap)
++{
++	unsigned long led_delay = LIBATA_BLINK_DELAY;
++
++	if (unlikely(!ap->ledtrig))
++		return;
++
++	led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0);
++}
++#endif
++
+ /**
+  *	ata_build_rw_tf - Build ATA taskfile for given read/write request
+  *	@qc: Metadata associated with the taskfile to build
+@@ -4767,6 +4780,9 @@ void __ata_qc_complete(struct ata_queued
+ 		link->active_tag = ATA_TAG_POISON;
+ 		ap->nr_active_links--;
+ 	}
++#ifdef CONFIG_ATA_LEDS
++	ata_led_act(ap);
++#endif
+ 
+ 	/* clear exclusive status */
+ 	if (unlikely(qc->flags & ATA_QCFLAG_CLEAR_EXCL &&
+@@ -5490,6 +5506,9 @@ struct ata_port *ata_port_alloc(struct a
+ 	ap->stats.unhandled_irq = 1;
+ 	ap->stats.idle_irq = 1;
+ #endif
++#ifdef CONFIG_ATA_LEDS
++	ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
++#endif
+ 	ata_sff_port_init(ap);
+ 
+ 	return ap;
+@@ -5526,6 +5545,12 @@ static void ata_host_release(struct kref
+ 		kfree(ap->pmp_link);
+ 		kfree(ap->slave_link);
+ 		kfree(ap->ncq_sense_buf);
++#ifdef CONFIG_ATA_LEDS
++		if (ap->ledtrig) {
++			led_trigger_unregister(ap->ledtrig);
++			kfree(ap->ledtrig);
++		};
++#endif
+ 		kfree(ap);
+ 		host->ports[i] = NULL;
+ 	}
+@@ -5916,7 +5941,23 @@ int ata_host_register(struct ata_host *h
+ 		host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
+ 		host->ports[i]->local_port_no = i + 1;
+ 	}
++#ifdef CONFIG_ATA_LEDS
++	for (i = 0; i < host->n_ports; i++) {
++		if (unlikely(!host->ports[i]->ledtrig))
++			continue;
+ 
++		snprintf(host->ports[i]->ledtrig_name,
++			sizeof(host->ports[i]->ledtrig_name), "ata%u",
++			host->ports[i]->print_id);
++
++		host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;
++
++		if (led_trigger_register(host->ports[i]->ledtrig)) {
++			kfree(host->ports[i]->ledtrig);
++			host->ports[i]->ledtrig = NULL;
++		}
++	}
++#endif
+ 	/* Create associated sysfs transport objects  */
+ 	for (i = 0; i < host->n_ports; i++) {
+ 		rc = ata_tport_add(host->dev,host->ports[i]);
+--- a/include/linux/libata.h
++++ b/include/linux/libata.h
+@@ -23,6 +23,9 @@
+ #include <linux/cdrom.h>
+ #include <linux/sched.h>
+ #include <linux/async.h>
++#ifdef CONFIG_ATA_LEDS
++#include <linux/leds.h>
++#endif
+ 
+ /*
+  * Define if arch has non-standard setup.  This is a _PCI_ standard
+@@ -874,6 +877,12 @@ struct ata_port {
+ #ifdef CONFIG_ATA_ACPI
+ 	struct ata_acpi_gtm	__acpi_init_gtm; /* use ata_acpi_init_gtm() */
+ #endif
++
++#ifdef CONFIG_ATA_LEDS
++	struct led_trigger	*ledtrig;
++	char			ledtrig_name[8];
++#endif
++
+ 	/* owned by EH */
+ 	u8			*ncq_sense_buf;
+ 	u8			sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
diff --git a/target/linux/generic/pending-6.6/840-hwrng-bcm2835-set-quality-to-1000.patch b/target/linux/generic/pending-6.6/840-hwrng-bcm2835-set-quality-to-1000.patch
new file mode 100644
index 00000000000000..3172ad5a167b0e
--- /dev/null
+++ b/target/linux/generic/pending-6.6/840-hwrng-bcm2835-set-quality-to-1000.patch
@@ -0,0 +1,26 @@
+From d6988cf1d16faac56899918bb2b1be8d85155e3f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Sat, 20 Feb 2021 18:36:38 +0100
+Subject: [PATCH] hwrng: bcm2835: set quality to 1000
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This allows devices without a high precission timer to reduce boot from >100s
+to <30s.
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+---
+ drivers/char/hw_random/bcm2835-rng.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/char/hw_random/bcm2835-rng.c
++++ b/drivers/char/hw_random/bcm2835-rng.c
+@@ -169,6 +169,7 @@ static int bcm2835_rng_probe(struct plat
+ 	priv->rng.init = bcm2835_rng_init;
+ 	priv->rng.read = bcm2835_rng_read;
+ 	priv->rng.cleanup = bcm2835_rng_cleanup;
++	priv->rng.quality = 1000;
+ 
+ 	if (dev_of_node(dev)) {
+ 		rng_id = of_match_node(bcm2835_rng_of_match, dev->of_node);
diff --git a/target/linux/generic/pending-6.6/920-mangle_bootargs.patch b/target/linux/generic/pending-6.6/920-mangle_bootargs.patch
new file mode 100644
index 00000000000000..998fc500d1f515
--- /dev/null
+++ b/target/linux/generic/pending-6.6/920-mangle_bootargs.patch
@@ -0,0 +1,71 @@
+From: Imre Kaloz <kaloz@openwrt.org>
+Subject: init: add CONFIG_MANGLE_BOOTARGS and disable it by default
+
+Enabling this option renames the bootloader supplied root=
+and rootfstype= variables, which might have to be know but
+would break the automatisms OpenWrt uses.
+
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+---
+ init/Kconfig |  9 +++++++++
+ init/main.c  | 24 ++++++++++++++++++++++++
+ 2 files changed, 33 insertions(+)
+
+--- a/init/Kconfig
++++ b/init/Kconfig
+@@ -1792,6 +1792,15 @@ config DEBUG_RSEQ
+ 
+ 	  If unsure, say N.
+ 
++config MANGLE_BOOTARGS
++	bool "Rename offending bootargs"
++	depends on EXPERT
++	help
++	  Sometimes the bootloader passed bogus root= and rootfstype=
++	  parameters to the kernel, and while you want to ignore them,
++	  you need to know the values f.e. to support dual firmware
++	  layouts on the flash.
++
+ config HAVE_PERF_EVENTS
+ 	bool
+ 	help
+--- a/init/main.c
++++ b/init/main.c
+@@ -608,6 +608,29 @@ static inline void setup_nr_cpu_ids(void
+ static inline void smp_prepare_cpus(unsigned int maxcpus) { }
+ #endif
+ 
++#ifdef CONFIG_MANGLE_BOOTARGS
++static void __init mangle_bootargs(char *command_line)
++{
++	char *rootdev;
++	char *rootfs;
++
++	rootdev = strstr(command_line, "root=/dev/mtdblock");
++
++	if (rootdev)
++		strncpy(rootdev, "mangled_rootblock=", 18);
++
++	rootfs = strstr(command_line, "rootfstype");
++
++	if (rootfs)
++		strncpy(rootfs, "mangled_fs", 10);
++
++}
++#else
++static void __init mangle_bootargs(char *command_line)
++{
++}
++#endif
++
+ /*
+  * We need to store the untouched command line for future reference.
+  * We also need to store the touched command line since the parameter
+@@ -895,6 +918,7 @@ void start_kernel(void)
+ 	pr_notice("%s", linux_banner);
+ 	early_security_init();
+ 	setup_arch(&command_line);
++	mangle_bootargs(command_line);
+ 	setup_boot_config();
+ 	setup_command_line(command_line);
+ 	setup_nr_cpu_ids();
diff --git a/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch b/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch
index 05846cf53ab293..a6be2c15fc9243 100644
--- a/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch
+++ b/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch
@@ -430,7 +430,7 @@
  #endif
 --- a/net/core/neighbour.c
 +++ b/net/core/neighbour.c
-@@ -1204,7 +1204,21 @@ static void neigh_update_hhs(struct neig
+@@ -1211,7 +1211,21 @@ static void neigh_update_hhs(struct neig
  	}
  }
  
@@ -452,7 +452,7 @@
  
  /* Generic update routine.
     -- lladdr is new lladdr or NULL, if it is not supplied.
-@@ -1235,6 +1249,7 @@ static int __neigh_update(struct neighbo
+@@ -1242,6 +1256,7 @@ static int __neigh_update(struct neighbo
  	int notify = 0;
  	struct net_device *dev;
  	int update_isrouter = 0;
@@ -460,7 +460,7 @@
  
  	trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid);
  
-@@ -1249,6 +1264,8 @@ static int __neigh_update(struct neighbo
+@@ -1256,6 +1271,8 @@ static int __neigh_update(struct neighbo
  		new = old;
  		goto out;
  	}
@@ -469,7 +469,7 @@
  	if (!(flags & NEIGH_UPDATE_F_ADMIN) &&
  	    (old & (NUD_NOARP | NUD_PERMANENT)))
  		goto out;
-@@ -1286,6 +1303,11 @@ static int __neigh_update(struct neighbo
+@@ -1293,6 +1310,11 @@ static int __neigh_update(struct neighbo
  		   - compare new & old
  		   - if they are different, check override flag
  		 */
@@ -481,7 +481,7 @@
  		if ((old & NUD_VALID) &&
  		    !memcmp(lladdr, neigh->ha, dev->addr_len))
  			lladdr = neigh->ha;
-@@ -1408,8 +1430,11 @@ out:
+@@ -1415,8 +1437,11 @@ out:
  	if (((new ^ old) & NUD_PERMANENT) || ext_learn_change)
  		neigh_update_gc_list(neigh);
  
@@ -561,7 +561,7 @@
  #endif
 --- a/net/ipv6/route.c
 +++ b/net/ipv6/route.c
-@@ -3878,6 +3878,9 @@ out_free:
+@@ -3875,6 +3875,9 @@ out_free:
  	return ERR_PTR(err);
  }
  
@@ -571,7 +571,7 @@
  int ip6_route_add(struct fib6_config *cfg, gfp_t gfp_flags,
  		  struct netlink_ext_ack *extack)
  {
-@@ -3889,6 +3892,10 @@ int ip6_route_add(struct fib6_config *cf
+@@ -3886,6 +3889,10 @@ int ip6_route_add(struct fib6_config *cf
  		return PTR_ERR(rt);
  
  	err = __ip6_ins_rt(rt, &cfg->fc_nlinfo, extack);
@@ -582,7 +582,7 @@
  	fib6_info_release(rt);
  
  	return err;
-@@ -3910,6 +3917,9 @@ static int __ip6_del_rt(struct fib6_info
+@@ -3907,6 +3914,9 @@ static int __ip6_del_rt(struct fib6_info
  	err = fib6_del(rt, info);
  	spin_unlock_bh(&table->tb6_lock);
  
@@ -592,7 +592,7 @@
  out:
  	fib6_info_release(rt);
  	return err;
-@@ -6353,6 +6363,20 @@ static int ip6_route_dev_notify(struct n
+@@ -6350,6 +6360,20 @@ static int ip6_route_dev_notify(struct n
  	return NOTIFY_OK;
  }
  
diff --git a/target/linux/ipq806x/Makefile b/target/linux/ipq806x/Makefile
index 9487746acfd624..5a93a2955fe2a2 100644
--- a/target/linux/ipq806x/Makefile
+++ b/target/linux/ipq806x/Makefile
@@ -10,8 +10,7 @@ CPU_TYPE:=cortex-a15
 CPU_SUBTYPE:=neon-vfpv4
 SUBTARGETS:=generic
 
-KERNEL_PATCHVER:=5.4
-KERNEL_TESTING_PATCHVER:=5.4
+KERNEL_PATCHVER:=5.10
 
 KERNELNAME:=zImage Image dtbs
 
@@ -22,7 +21,6 @@ DEFAULT_PACKAGES += \
 	kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \
 	kmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \
 	kmod-ath10k-ct wpad-openssl uboot-envtools \
-	kmod-shortcut-fe kmod-qca-nss-drv kmod-qca-nss-ecm-standard kmod-qca-nss-gmac kmod-qca-nss-drv-pppoe kmod-qca-mcs \
-	autocore-arm htop automount autosamba luci-app-adbyby-plus luci-app-ipsec-vpnd luci-app-unblockmusic luci-app-zerotier
-	
+	autocore-arm automount autosamba htop
+
 $(eval $(call BuildTarget))
diff --git a/target/linux/ipq806x/base-files/etc/board.d/01_leds b/target/linux/ipq806x/base-files/etc/board.d/01_leds
index ab946fc47d646a..8e4983c60fa634 100644
--- a/target/linux/ipq806x/base-files/etc/board.d/01_leds
+++ b/target/linux/ipq806x/base-files/etc/board.d/01_leds
@@ -21,9 +21,10 @@ edgecore,ecw5410)
 	ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy1tpt"
 	ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy0tpt"
 	;;
-linksys,e8350-v1)
-        ucidef_set_led_wlan "wlan" "WLAN" "${boardname}:green:wifi" "phy0tpt"
-        ;;
+meraki,mr52)
+	ucidef_set_led_netdev "eth0" "eth0" "green:lan1" "eth0"
+	ucidef_set_led_netdev "eth1" "eth1" "green:lan2" "eth1"
+	;;
 nec,wg2600hp)
 	ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy1tpt"
 	ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy0tpt"
diff --git a/target/linux/ipq806x/base-files/etc/board.d/02_network b/target/linux/ipq806x/base-files/etc/board.d/02_network
index 2ac883183c5230..565a46a8e59268 100644
--- a/target/linux/ipq806x/base-files/etc/board.d/02_network
+++ b/target/linux/ipq806x/base-files/etc/board.d/02_network
@@ -11,13 +11,12 @@ board_config_update
 board=$(board_name)
 
 case "$board" in
-arris,rac2v1a)
+arris,tr4400-v2)
 	ucidef_set_interfaces_lan_wan "eth1" "eth2"
 	ucidef_add_switch "switch0" \
 		"1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "0u@eth0"
 	;;
 askey,rt4230w-rev6 |\
-askey,rt4230w-rev9.3 |\
 asrock,g10 |\
 nec,wg2600hp)
 	ucidef_add_switch "switch0" \
@@ -25,7 +24,6 @@ nec,wg2600hp)
 	;;
 buffalo,wxr-2533dhp |\
 compex,wpq864 |\
-linksys,e8350-v1 |\
 netgear,d7800 |\
 netgear,r7500 |\
 netgear,r7500v2 |\
@@ -36,14 +34,6 @@ surf,g-nat200)
 	;;
 edgecore,ecw5410)
 	ucidef_set_interfaces_lan_wan "eth1" "eth0"
-	if [ -b "$(find_mtd_part 0:art)" ]; then
-		ucidef_set_interface_macaddr "lan" "$(mtd_get_mac_binary "0:art" 0x6)"
-		ucidef_set_interface_macaddr "wan" "$(mtd_get_mac_binary "0:art" 0x0)"
-	else
-		# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-		ucidef_set_interface_macaddr "lan" "$(mtd_get_mac_binary "0:ART" 0x6)"
-		ucidef_set_interface_macaddr "wan" "$(mtd_get_mac_binary "0:ART" 0x0)"
-	fi
 	;;
 linksys,ea7500-v1)
 	hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
@@ -59,6 +49,12 @@ linksys,ea8500)
 	ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
 	ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
 	;;
+meraki,mr42)
+	ucidef_set_interface_lan "eth0"
+	;;
+meraki,mr52)
+	ucidef_set_interfaces_lan_wan "eth0" "eth1"
+	;;
 nec,wg2600hp3)
 	ucidef_add_switch "switch0" \
 		"2:lan" "3:lan" "4:lan" "5:lan" "0@eth1" "1:wan" "6@eth0"
@@ -70,13 +66,6 @@ tplink,vr2600v)
 	ucidef_add_switch "switch0" \
 		"1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0"
 	;;
-norton,core-518)
-	hw_mac_addr=$(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr)
-	ucidef_add_switch "switch0" \
-		"2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0"
-	ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
-	ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 1)"
-	;;
 qcom,ipq8064-ap161)
 	ucidef_set_interface_lan "eth1 eth2"
 	ucidef_add_switch "switch0" \
@@ -103,9 +92,6 @@ ubnt,unifi-ac-hd)
 	;;
 zyxel,nbg6817)
 	hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr)
-	# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-	[ -n "$hw_mac_addr" ] || \
-		hw_mac_addr=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
 	ucidef_add_switch "switch0" \
 		"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
 	ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)"
diff --git a/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
index 1d2b818afda7ae..2571e2e01414b5 100644
--- a/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ b/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
@@ -9,6 +9,10 @@ board=$(board_name)
 case "$FIRMWARE" in
 "ath10k/cal-pci-0000:01:00.0.bin")
 	case "$board" in
+	meraki,mr52)
+		CI_UBIPART=art
+		caldata_extract_ubi "ART" 0x1000 0x844
+		;;
 	ruijie,rg-mtfi-m520)
 		caldata_extract "ART" 0x1000 0x844
 		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii PRODUCTINFO ethaddr) 2)
@@ -25,149 +29,70 @@ case "$FIRMWARE" in
 	;;
 "ath10k/pre-cal-pci-0000:01:00.0.bin")
 	case $board in
-	arris,rac2v1a)
-		caldata_extract "0:ART" 0x1000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary fw_env 0x12)
-		;;
-	askey,rt4230w-rev6 |\
-	askey,rt4230w-rev9.3)
+	askey,rt4230w-rev6)
 		caldata_extract "0:ART" 0x1000 0x2f20
 		;;
 	asrock,g10)
-		if [ -b "$(find_mtd_part 0:art)" ]; then
-			caldata_extract "0:art" 0x1000 0x2f20
-		else
-			# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-			caldata_extract "0:ART" 0x1000 0x2f20
-		fi
-		;;
-	buffalo,wxr-2533dhp)
-		caldata_extract "ART" 0x1000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary ART 0x1e)
-		;;
-	edgecore,ecw5410)
-		if [ -b "$(find_mtd_part 0:art)" ]; then
-			caldata_extract "0:art" 0x1000 0x2f20
-		else
-			# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-			caldata_extract "0:ART" 0x1000 0x2f20
-		fi
+		caldata_extract "0:art" 0x1000 0x2f20
 		;;
 	linksys,ea7500-v1 |\
 	linksys,ea8500)
 		caldata_extract "art" 0x1000 0x2f20
 		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 1)
 		;;
-	nec,wg2600hp |\
-	nec,wg2600hp3)
-		caldata_extract "ART" 0x1000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary PRODUCTDATA 0x12)
-		;;
-	netgear,d7800 |\
-	netgear,r7500v2 |\
-	netgear,r7800 |\
-	netgear,xr500)
-		caldata_extract "art" 0x1000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x6) 1)
-		;;
-	norton,core-518)
-		caldata_extract_mmc "0:ART" 0x1000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 2)
-		;;
-	tplink,ad7200 |\
-	tplink,c2600)
-		caldata_extract "radio" 0x1000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 0x8) -1)
-		;;
-	tplink,vr2600v)
-		caldata_extract "ART" 0x1000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 0x0) -1)
+	meraki,mr42)
+		CI_UBIPART=art
+		caldata_extract_ubi "ART" 0x1000 0x2f20
 		;;
 	zyxel,nbg6817)
-		if [ -b "$(find_mtd_part 0:art)" ]; then
-			caldata_extract "0:art" 0x1000 0x2f20
-			ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:appsblenv ethaddr) 1)
-		else
-			# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-			caldata_extract "0:ART" 0x1000 0x2f20
-			ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV ethaddr) 1)
-		fi
+		caldata_extract "0:art" 0x1000 0x2f20
+		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:appsblenv ethaddr) 1)
 		;;
 	esac
 	;;
 "ath10k/pre-cal-pci-0001:01:00.0.bin")
 	case $board in
-	arris,rac2v1a)
-		caldata_extract "0:ART" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary fw_env 0xc)
-		;;
-	askey,rt4230w-rev6 |\
-	askey,rt4230w-rev9.3)
+	askey,rt4230w-rev6)
 		caldata_extract "0:ART" 0x5000 0x2f20
 		;;
 	asrock,g10)
-		if [ -b "$(find_mtd_part 0:art)" ]; then
-			caldata_extract "0:art" 0x5000 0x2f20
-		else
-			# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-			caldata_extract "0:ART" 0x5000 0x2f20
-		fi
+		caldata_extract "0:art" 0x5000 0x2f20
 		;;
-	buffalo,wxr-2533dhp)
-		caldata_extract "ART" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary ART 0x18)
+	edgecore,ecw5410)
+		caldata_extract "0:art" 0x1000 0x2f20
 		;;
 	linksys,ea7500-v1 |\
 	linksys,ea8500)
 		caldata_extract "art" 0x5000 0x2f20
 		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 2)
 		;;
-	nec,wg2600hp |\
-	nec,wg2600hp3)
-		caldata_extract "ART" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary PRODUCTDATA 0xc)
-		;;
-	netgear,d7800 |\
-	netgear,r7500v2 |\
-	netgear,r7800 |\
-	netgear,xr500)
-		caldata_extract "art" 0x5000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x6) 2)
-		;;
-	norton,core-518)
-		caldata_extract_mmc "0:ART" 0x5000 0x2f20
-		ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 3)
-		;;
-	tplink,ad7200 |\
-	tplink,c2600)
-		caldata_extract "radio" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary default-mac 0x8)
-		;;
-	tplink,vr2600v)
-		caldata_extract "ART" 0x5000 0x2f20
-		ath10k_patch_mac $(mtd_get_mac_binary default-mac 0x0)
+	meraki,mr42 |\
+	meraki,mr52)
+		CI_UBIPART=art
+		caldata_extract_ubi "ART" 0x5000 0x2f20
 		;;
 	zyxel,nbg6817)
-		if [ -b "$(find_mtd_part 0:art)" ]; then
-			caldata_extract "0:art" 0x5000 0x2f20
-			ath10k_patch_mac $(mtd_get_mac_ascii 0:appsblenv ethaddr)
-		else
-			# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-			caldata_extract "0:ART" 0x5000 0x2f20
-			ath10k_patch_mac $(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
-		fi
+		caldata_extract "0:art" 0x5000 0x2f20
+		ath10k_patch_mac $(mtd_get_mac_ascii 0:appsblenv ethaddr)
+		;;
+	esac
+	;;
+"ath10k/cal-pci-0002:01:00.0.bin")
+	case "$board" in
+	meraki,mr42)
+		CI_UBIPART=art
+		caldata_extract_ubi "ART" 0x9000 0x844
 		;;
 	esac
 	;;
 "ath10k/pre-cal-pci-0002:01:00.0.bin")
 	case $board in
 	edgecore,ecw5410)
-		if [ -b "$(find_mtd_part 0:art)" ]; then
-			caldata_extract "0:art" 0x5000 0x2f20
-		else
-			# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-			caldata_extract "0:ART" 0x5000 0x2f20
-		fi
+		caldata_extract "0:art" 0x5000 0x2f20
+		;;
+	meraki,mr52)
+		CI_UBIPART=art
+		caldata_extract_ubi "ART" 0x9000 0x2f20
 		;;
 	esac
 	;;
diff --git a/target/linux/ipq806x/base-files/etc/init.d/bootcount b/target/linux/ipq806x/base-files/etc/init.d/bootcount
index fcf896a00027dc..cb32a4ed3568d8 100755
--- a/target/linux/ipq806x/base-files/etc/init.d/bootcount
+++ b/target/linux/ipq806x/base-files/etc/init.d/bootcount
@@ -16,30 +16,5 @@ boot() {
 	linksys,ea8500)
 		mtd resetbc s_env || true
 		;;
-	norton,core-518)
-        . /lib/functions/caldata.sh
-        FIRMWARE='ath10k/pre-cal-pci-0000:01:00.0.bin'
-		[ -e /lib/firmware/$FIRMWARE ] || {
-            caldata_extract_mmc "0:ART" 0x1000 0x2f20
-		    ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 2)
-        }
-
-        FIRMWARE='ath10k/pre-cal-pci-0001:01:00.0.bin'
-        [ -e /lib/firmware/$FIRMWARE ] || {
-            caldata_extract_mmc "0:ART" 0x5000 0x2f20
-		    ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 3)
-        }
-
-		[ -e /etc/config/wireless ] || {
-			/sbin/wifi config
-			/sbin/wifi up
-		}
-
-		[ -s /etc/config/wireless ] || {
-			rm /etc/config/wireless
-			/sbin/wifi config
-			/sbin/wifi up
-		}
-		;;
 	esac
 }
diff --git a/target/linux/ipq806x/base-files/etc/init.d/cpu_freq b/target/linux/ipq806x/base-files/etc/init.d/cpu_freq
index ecd253cc0091bf..19278902ed82b7 100755
--- a/target/linux/ipq806x/base-files/etc/init.d/cpu_freq
+++ b/target/linux/ipq806x/base-files/etc/init.d/cpu_freq
@@ -9,13 +9,9 @@ boot() {
 
   if [ "$governor" = "ondemand" ]; then
     # Effective only with ondemand
+    echo 600000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq
+    echo 600000 > /sys/devices/system/cpu/cpufreq/policy1/scaling_min_freq
     echo 10 > /sys/devices/system/cpu/cpufreq/ondemand/sampling_down_factor
     echo 50 > /sys/devices/system/cpu/cpufreq/ondemand/up_threshold
   fi
-
-	echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
-	echo 1000000 > /sys/devices/system/cpu/cpu1/cpufreq/scaling_min_freq
-	
-	sysctl -w vm.min_free_kbytes=65536
-	sysctl -w net.netfilter.nf_conntrack_max=65535
 }
diff --git a/target/linux/ipq806x/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/ipq806x/base-files/etc/uci-defaults/05_fix-compat-version
new file mode 100644
index 00000000000000..3b9dd4e0280178
--- /dev/null
+++ b/target/linux/ipq806x/base-files/etc/uci-defaults/05_fix-compat-version
@@ -0,0 +1,11 @@
+. /lib/functions.sh
+
+case "$(board_name)" in
+	linksys,ea7500-v1|\
+	linksys,ea8500)
+		uci set system.@system[0].compat_version="2.0"
+		uci commit system
+	;;
+esac
+
+exit 0
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh b/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh
index 8be737d2dad915..9645b646710718 100644
--- a/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh
@@ -2,8 +2,6 @@
 
 asrock_bootconfig_mangle() {
 	local mtdnum="$(find_mtd_index 0:bootconfig)"
-	# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-	[ -n "$mtdnum" ] || mtdnum="$(find_mtd_index 0:BOOTCONFIG)"
 
 	if [ -z "$mtdnum" ]; then
 		echo "cannot find bootconfig mtd partition"
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh b/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh
index 22771278ce1a13..1feffc7aa2420b 100644
--- a/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh
@@ -9,7 +9,7 @@ linksys_get_target_firmware() {
 	cur_boot_part=$(/usr/sbin/fw_printenv -n boot_part)
 	if [ -z "${cur_boot_part}" ] ; then
 		mtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)
-		case $(egrep ^mtd${mtd_ubi0}: /proc/mtd | cut -d '"' -f 2) in
+		case $(grep -E ^mtd${mtd_ubi0}: /proc/mtd | cut -d '"' -f 2) in
 		kernel1|rootfs1)
 			cur_boot_part=1
 			;;
@@ -44,10 +44,6 @@ linksys_get_target_firmware() {
 	esac
 }
 
-linksys_get_root_magic() {
-	(get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null
-}
-
 platform_do_upgrade_linksys() {
 	local magic_long="$(get_magic_long "$1")"
 
@@ -101,18 +97,6 @@ platform_do_upgrade_linksys() {
 		nand_upgrade_tar "$1"
 	}
 	[ "$magic_long" = "27051956" ] && {
-		# check firmwares' rootfs types
-		local oldroot="$(linksys_get_root_magic $target_mtd)"
-		local newroot="$(linksys_get_root_magic "$1")"
-
-		if [ "$newroot" = "55424923" -a "$oldroot" = "55424923" ]
-		# we're upgrading from a firmware with UBI to one with UBI
-		then
-			# erase everything to be safe
-			mtd erase $part_label
-			get_image "$1" | mtd -n write - $part_label
-		else
-			get_image "$1" | mtd write - $part_label
-		fi
+		get_image "$1" | mtd write - $part_label
 	}
 }
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/norton.sh b/target/linux/ipq806x/base-files/lib/upgrade/norton.sh
deleted file mode 100644
index d89d766cb6147d..00000000000000
--- a/target/linux/ipq806x/base-files/lib/upgrade/norton.sh
+++ /dev/null
@@ -1,110 +0,0 @@
-#
-# Copyright (C) 2016 lede-project.org
-#
-
-norton_get_rootfs() {
-	local rootfsdev
-
-	if read cmdline < /proc/cmdline; then
-		case "$cmdline" in
-			*root=*)
-				rootfsdev="${cmdline##*root=}"
-				rootfsdev="${rootfsdev%% *}"
-			;;
-		esac
-
-		echo "${rootfsdev}"
-	fi
-}
-
-norton_do_flash() {
-	local tar_file=$1
-	local kernel=$2
-	local rootfs=$3
-
-	# keep sure its unbound
-	losetup --detach-all || {
-		echo Failed to detach all loop devices. Skip this try.
-		reboot -f
-	}
-
-	# use the first found directory in the tar archive
-	local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
-	board_dir=${board_dir%/}
-
-	echo "flashing kernel to $kernel"
-	mkdir /tmp/upgrade
-	dd if=/dev/zero bs=40 count=1 > /tmp/upgrade/pad40
-	tar xf $tar_file ${board_dir}/kernel -C /tmp/upgrade/
-	cat /tmp/upgrade/pad40 /tmp/upgrade/${board_dir}/kernel > $kernel
-
-	echo "flashing rootfs to ${rootfs}"
-	tar xf $tar_file ${board_dir}/root -O > $rootfs
-
-	# a padded rootfs is needed for overlay fs creation
-	local offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
-	[ $offset -lt 65536 ] && {
-		echo Wrong size for rootfs: $offset
-		sleep 10
-		reboot -f
-	}
-
-	[ -e /tmp/sysupgrade.tgz ] || {
-		echo "formating rootfs_data /dev/mmcblk0p25"
-		mkfs.ext4 -F -L rootfs_data /dev/mmcblk0p25
-	}
-
-	# flashing successful
-	case "$rootfs" in
-		"/dev/mmcblk0p10")
-			;;
-		"/dev/mmcblk0p21")
-			;;
-	esac
-
-	# Cleanup
-	losetup -d $loopdev >/dev/null 2>&1
-	sync
-	umount -a
-	reboot -f
-}
-
-norton_do_upgrade() {
-	local tar_file="$1"
-	local board=$(board_name)
-	local rootfs="$(norton_get_rootfs)"
-	local kernel=
-
-	[ -b "${rootfs}" ] || return 1
-	case "$board" in
-	norton,core-518)
-
-		case "$rootfs" in
-			"/dev/mmcblk0p10")
-				# booted from the primary partition set
-				# write to the alternative set
-				kernel="/dev/mmcblk0p9"
-				rootfs="/dev/mmcblk0p10"
-			;;
-			"/dev/mmcblk0p21")
-				# booted from the alternative partition set
-				# write to the primary set
-				kernel="/dev/mmcblk0p20"
-				rootfs="/dev/mmcblk0p21"
-			;;
-			*)
-				return 1
-			;;
-		esac
-		;;
-	*)
-		return 1
-		;;
-	esac
-
-	norton_do_flash $tar_file $kernel $rootfs
-
-	nand_do_upgrade "$1"
-
-	return 0
-}
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
index 0745b24b5120b4..84565fde88b947 100644
--- a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
@@ -1,7 +1,7 @@
 PART_NAME=firmware
 REQUIRE_IMAGE_METADATA=1
 
-RAMFS_COPY_BIN='fw_printenv fw_setenv fwtool'
+RAMFS_COPY_BIN='fw_printenv fw_setenv'
 RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
 
 platform_check_image() {
@@ -10,9 +10,8 @@ platform_check_image() {
 
 platform_do_upgrade() {
 	case "$(board_name)" in
-	arris,rac2v1a |\
+	arris,tr4400-v2 |\
 	askey,rt4230w-rev6 |\
-	askey,rt4230w-rev9.3 |\
 	compex,wpq864 |\
 	netgear,d7800 |\
 	netgear,r7500 |\
@@ -23,10 +22,6 @@ platform_do_upgrade() {
 	qcom,ipq8064-ap161)
 		nand_do_upgrade "$1"
 		;;
-	linksys,e8350-v1)
-		fwtool -q -t -i /dev/null "$1"
-		nand_do_upgrade "$1"
-		;;
 	asrock,g10)
 		asrock_upgrade_prepare
 		nand_do_upgrade "$1"
@@ -51,6 +46,14 @@ platform_do_upgrade() {
 	linksys,ea8500)
 		platform_do_upgrade_linksys "$1"
 		;;
+	meraki,mr42 |\
+	meraki,mr52)
+		CI_KERNPART="bootkernel2"
+		nand_do_upgrade "$1"
+		;;
+	ruijie,rg-mtfi-m520)
+		ruijie_do_upgrade "$1"
+		;;
 	tplink,ad7200 |\
 	tplink,c2600)
 		PART_NAME="os-image:rootfs"
@@ -58,16 +61,9 @@ platform_do_upgrade() {
 		default_do_upgrade "$1"
 		;;
 	tplink,vr2600v)
-		PART_NAME="kernel:rootfs"
 		MTD_CONFIG_ARGS="-s 0x200000"
 		default_do_upgrade "$1"
 		;;
-	norton,core-518)
-		norton_do_upgrade "$1"
-		;;
-	ruijie,rg-mtfi-m520)
-		ruijie_do_upgrade "$1"
-		;;
 	zyxel,nbg6817)
 		zyxel_do_upgrade "$1"
 		;;
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh b/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh
index 50f8a3ceaf3687..f5501822f3476b 100644
--- a/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh
@@ -91,9 +91,6 @@ zyxel_do_upgrade() {
 	case "$board" in
 	zyxel,nbg6817)
 		local dualflagmtd="$(find_mtd_part 0:dual_flag)"
-		# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
-		[ -b $dualflagmtd ] || \
-			dualflagmtd="$(find_mtd_part 0:DUAL_FLAG)"
 		[ -b $dualflagmtd ] || return 1
 
 		case "$rootfs" in
diff --git a/target/linux/ipq806x/config-5.4 b/target/linux/ipq806x/config-5.10
similarity index 84%
rename from target/linux/ipq806x/config-5.4
rename to target/linux/ipq806x/config-5.10
index 5059ff8e614852..51008c4da1bc11 100644
--- a/target/linux/ipq806x/config-5.4
+++ b/target/linux/ipq806x/config-5.10
@@ -3,8 +3,8 @@ CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_APQ_MMCC_8084 is not set
 CONFIG_AR8216_PHY=y
 CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_IPQ40XX is not set
 CONFIG_ARCH_KEEP_MEMBLOCK=y
 # CONFIG_ARCH_MDM9615 is not set
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
@@ -18,6 +18,8 @@ CONFIG_ARCH_NR_GPIO=0
 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARM=y
 CONFIG_ARM_AMBA=y
@@ -41,7 +43,7 @@ CONFIG_ARM_PATCH_PHYS_VIRT=y
 # CONFIG_ARM_QCOM_CPUFREQ_HW is not set
 CONFIG_ARM_QCOM_CPUFREQ_KRAIT=y
 CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_ARM_QCOM_CPUIDLE=y
+CONFIG_ARM_QCOM_SPM_CPUIDLE=y
 # CONFIG_ARM_SMMU is not set
 CONFIG_ARM_THUMB=y
 CONFIG_ARM_UNWIND=y
@@ -70,8 +72,8 @@ CONFIG_CPU_COPY_V6=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
 CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
 CONFIG_CPU_FREQ_GOV_ATTR_SET=y
 CONFIG_CPU_FREQ_GOV_COMMON=y
 # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
@@ -97,25 +99,19 @@ CONFIG_CPU_V7=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLAKE2S=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_DEV_QCOM_RNG=y
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_DRBG_HMAC=y
 CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_SHA256=y
@@ -123,9 +119,16 @@ CONFIG_CRYPTO_ZSTD=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
 CONFIG_DMADEVICES=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
 CONFIG_DMA_REMAP=y
 CONFIG_DMA_VIRTUAL_CHANNELS=y
 CONFIG_DTC=y
@@ -146,6 +149,7 @@ CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
@@ -163,10 +167,9 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GRO_CELLS=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDEN_BRANCH_PREDICTOR=y
@@ -176,7 +179,7 @@ CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HAVE_SMP=y
 CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
+CONFIG_HIGHPTE=y
 CONFIG_HWMON=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
@@ -186,26 +189,29 @@ CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_QCOM_CCI is not set
 CONFIG_I2C_QUP=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_IOMMU_DEBUGFS is not set
 # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
 # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
 CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IPQ_APSS_PLL is not set
 # CONFIG_IPQ_GCC_4019 is not set
+# CONFIG_IPQ_GCC_6018 is not set
 CONFIG_IPQ_GCC_806X=y
 # CONFIG_IPQ_GCC_8074 is not set
 # CONFIG_IPQ_LCC_806X is not set
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
 CONFIG_KPSS_XCC=y
 CONFIG_KRAITCC=y
 CONFIG_KRAIT_CLOCKS=y
 CONFIG_KRAIT_L2_ACCESSORS=y
-CONFIG_LEDS_TRIGGER_DISK=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
@@ -214,11 +220,13 @@ CONFIG_LZO_DECOMPRESS=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
 CONFIG_MDIO_GPIO=y
 CONFIG_MDIO_IPQ8064=y
 # CONFIG_MDM_GCC_9615 is not set
 # CONFIG_MDM_LCC_9615 is not set
 CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_HI6421_SPMI is not set
 CONFIG_MFD_QCOM_RPM=y
 # CONFIG_MFD_SPMI_PMIC is not set
 CONFIG_MFD_SYSCON=y
@@ -228,6 +236,7 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_CQHCI=y
 CONFIG_MMC_QCOM_DML=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_IO_ACCESSORS=y
@@ -237,18 +246,22 @@ CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MSM_GCC_8660=y
 # CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8939 is not set
 # CONFIG_MSM_GCC_8960 is not set
 # CONFIG_MSM_GCC_8974 is not set
 # CONFIG_MSM_GCC_8994 is not set
 # CONFIG_MSM_GCC_8996 is not set
 # CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_GPUCC_8998 is not set
 # CONFIG_MSM_IOMMU is not set
 # CONFIG_MSM_LCC_8960 is not set
 # CONFIG_MSM_MMCC_8960 is not set
 # CONFIG_MSM_MMCC_8974 is not set
 # CONFIG_MSM_MMCC_8996 is not set
+# CONFIG_MSM_MMCC_8998 is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND_ECC_SW_HAMMING=y
 CONFIG_MTD_NAND_QCOM=y
 CONFIG_MTD_QCOMSMEM_PARTS=y
@@ -277,7 +290,7 @@ CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
-# CONFIG_NVME_TCP is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@@ -304,28 +317,35 @@ CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCS_XPCS=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
 CONFIG_PHYLINK=y
 # CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_IPQ4019_USB is not set
 CONFIG_PHY_QCOM_IPQ806X_SATA=y
 # CONFIG_PHY_QCOM_IPQ806X_USB is not set
 # CONFIG_PHY_QCOM_PCIE2 is not set
 # CONFIG_PHY_QCOM_QMP is not set
 # CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_UFS is not set
+# CONFIG_PHY_QCOM_USB_HS_28NM is not set
+# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
+# CONFIG_PHY_QCOM_USB_SS is not set
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_APQ8064 is not set
 # CONFIG_PINCTRL_APQ8084 is not set
 # CONFIG_PINCTRL_IPQ4019 is not set
+# CONFIG_PINCTRL_IPQ6018 is not set
 CONFIG_PINCTRL_IPQ8064=y
 # CONFIG_PINCTRL_IPQ8074 is not set
 # CONFIG_PINCTRL_MDM9615 is not set
 CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8226 is not set
 # CONFIG_PINCTRL_MSM8660 is not set
 # CONFIG_PINCTRL_MSM8916 is not set
 # CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_MSM8976 is not set
 # CONFIG_PINCTRL_MSM8994 is not set
 # CONFIG_PINCTRL_MSM8996 is not set
 # CONFIG_PINCTRL_MSM8998 is not set
@@ -336,6 +356,9 @@ CONFIG_PINCTRL_MSM=y
 # CONFIG_PINCTRL_SDM660 is not set
 # CONFIG_PINCTRL_SDM845 is not set
 # CONFIG_PINCTRL_SM8150 is not set
+# CONFIG_PINCTRL_SM8250 is not set
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
 CONFIG_PM_OPP=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_MSM=y
@@ -348,19 +371,20 @@ CONFIG_QCOM_ADM=y
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_QCOM_CLK_RPM=y
 # CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_CPR is not set
 # CONFIG_QCOM_EBI2 is not set
 # CONFIG_QCOM_GENI_SE is not set
 CONFIG_QCOM_GSBI=y
 CONFIG_QCOM_HFPLL=y
 # CONFIG_QCOM_IOMMU is not set
 # CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_OCMEM is not set
 # CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_PM=y
 CONFIG_QCOM_QFPROM=y
 # CONFIG_QCOM_RMTFS_MEM is not set
 CONFIG_QCOM_RPMCC=y
+# CONFIG_QCOM_RPMH is not set
 CONFIG_QCOM_SCM=y
-CONFIG_QCOM_SCM_32=y
 # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
 CONFIG_QCOM_SMEM=y
 # CONFIG_QCOM_SMSM is not set
@@ -369,22 +393,19 @@ CONFIG_QCOM_TCSR=y
 CONFIG_QCOM_TSENS=y
 CONFIG_QCOM_WDT=y
 # CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_Q6SSTOP_404 is not set
 # CONFIG_QCS_TURING_404 is not set
-# CONFIG_QRTR is not set
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REFCOUNT_FULL=y
 CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_NSS_VOLT=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
 CONFIG_REGULATOR_QCOM_RPM=y
 # CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
 CONFIG_RESET_CONTROLLER=y
 # CONFIG_RESET_QCOM_AOSS is not set
 # CONFIG_RESET_QCOM_PDC is not set
@@ -394,6 +415,12 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_I2C_AND_SPI=y
 CONFIG_RTC_MC146818_LIB=y
 CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SC_DISPCC_7180 is not set
+# CONFIG_SC_GCC_7180 is not set
+# CONFIG_SC_GPUCC_7180 is not set
+# CONFIG_SC_LPASS_CORECC_7180 is not set
+# CONFIG_SC_MSS_7180 is not set
+# CONFIG_SC_VIDEOCC_7180 is not set
 # CONFIG_SDM_CAMCC_845 is not set
 # CONFIG_SDM_DISPCC_845 is not set
 # CONFIG_SDM_GCC_660 is not set
@@ -409,12 +436,18 @@ CONFIG_SGL_ALLOC=y
 CONFIG_SMP=y
 CONFIG_SMP_ON_UP=y
 # CONFIG_SM_GCC_8150 is not set
+# CONFIG_SM_GCC_8250 is not set
+# CONFIG_SM_GPUCC_8150 is not set
+# CONFIG_SM_GPUCC_8250 is not set
+# CONFIG_SM_VIDEOCC_8150 is not set
+# CONFIG_SM_VIDEOCC_8250 is not set
 CONFIG_SPARSE_IRQ=y
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
 CONFIG_SPI_QUP=y
 CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
 CONFIG_SPMI_MSM_PMIC_ARB=y
 # CONFIG_SPMI_PMIC_CLKDIV is not set
 CONFIG_SRCU=y
@@ -438,6 +471,7 @@ CONFIG_TIMER_PROBE=y
 CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 # CONFIG_UCLAMP_TASK is not set
 CONFIG_UEVENT_HELPER_PATH=""
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
index 3e04618d5782cb..c1c21856ca5fb0 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
@@ -317,6 +317,17 @@
 					label = "ART";
 					reg = <0x02e0000 0x0040000>;
 					read-only;
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_ART_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_ART_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 
 				partition@320000 {
@@ -359,6 +370,9 @@
 			reg = <0x00010000 0 0 0 0>;
 
 			qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
+
+			nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
 		};
 	};
 };
@@ -379,6 +393,9 @@
 
 			ieee80211-freq-limit = <2400000 2483000>;
 			qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
+
+			nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
 		};
 	};
 };
@@ -416,7 +433,8 @@
 	phy-mode = "rgmii";
 	qcom,id = <1>;
 	mdiobus = <&mdio0>;
-	mtd-mac-address = <&factory 0x0>;
+	nvmem-cells = <&macaddr_factory_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -429,10 +447,33 @@
 	phy-mode = "sgmii";
 	qcom,id = <2>;
 	mdiobus = <&mdio0>;
-	mtd-mac-address = <&factory 0x6>;
+	nvmem-cells = <&macaddr_factory_6>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
 		full-duplex;
 	};
 };
+
+&factory {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_factory_0: macaddr@0 {
+		reg = <0x0 0x6>;
+	};
+
+	macaddr_factory_6: macaddr@6 {
+		reg = <0x6 0x6>;
+	};
+
+	macaddr_PRODUCTDATA_c: macaddr@c {
+		reg = <0xc 0x6>;
+	};
+
+	macaddr_PRODUCTDATA_12: macaddr@12 {
+		reg = <0x12 0x6>;
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi
index 6243337468012a..29226ca27514d8 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi
@@ -45,32 +45,35 @@
 	/delete-node/opp-1200000000;
 	/delete-node/opp-1400000000;
 
+	/*
+	 * Voltage thresholds are <target min max>
+	 */
 	opp-384000000 {
-		opp-microvolt-speed0-pvs0-v0 = <902500 950000 997500>;
-		opp-microvolt-speed0-pvs1-v0 = <855000 900000 945000>;
-		opp-microvolt-speed0-pvs2-v0 = <807500 850000 892500>;
-		opp-microvolt-speed0-pvs3-v0 = <760000 800000 840000>;
+		opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs1-v0 = < 925000 878750  971250>;
+		opp-microvolt-speed0-pvs2-v0 = < 875000 831250  918750>;
+		opp-microvolt-speed0-pvs3-v0 = < 800000 760000  840000>;
 	};
 
 	opp-600000000 {
-		opp-microvolt-speed0-pvs0-v0 = <950000 1000000 1050000>;
-		opp-microvolt-speed0-pvs1-v0 = <945000  950000  955000>;
-		opp-microvolt-speed0-pvs2-v0 = <895000  900000  905000>;
-		opp-microvolt-speed0-pvs3-v0 = <845000  850000  855000>;
+		opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+		opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
+		opp-microvolt-speed0-pvs2-v0 = < 925000 878750  971250>;
+		opp-microvolt-speed0-pvs3-v0 = < 850000 807500  892500>;
 	};
 
 	opp-800000000 {
-		opp-microvolt-speed0-pvs0-v0 = <997500 1050000 1102500>;
-		opp-microvolt-speed0-pvs1-v0 = < 995000 1000000 1005000>;
-		opp-microvolt-speed0-pvs2-v0 = < 945000  950000  955000>;
-		opp-microvolt-speed0-pvs3-v0 = < 895000  900000  905000>;
+		opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs1-v0 = <1025000  973750 1076250>;
+		opp-microvolt-speed0-pvs2-v0 = < 995000  945250 1044750>;
+		opp-microvolt-speed0-pvs3-v0 = < 900000  855000  945000>;
 	};
 
 	opp-1000000000 {
-		opp-microvolt-speed0-pvs0-v0 = <1045000 1100000 1155000>;
-		opp-microvolt-speed0-pvs1-v0 = <997500 1050000 1102500>;
-		opp-microvolt-speed0-pvs2-v0 = < 995000 1000000 1005000>;
-		opp-microvolt-speed0-pvs3-v0 = < 945000  950000  955000>;
+		opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+		opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+		opp-microvolt-speed0-pvs2-v0 = <1025000  973750 1076250>;
+		opp-microvolt-speed0-pvs3-v0 = < 950000  902500  997500>;
 	};
 };
 
@@ -93,15 +96,3 @@
 &smb208_s2b {
 	regulator-max-microvolt = <1150000>;
 };
-
-&nss0 {
-	qcom,low-frequency = <550000000>; /* orig value 110000000 */
-	qcom,mid-frequency = <550000000>; /* orig value 275000000 */
-	qcom,max-frequency = <550000000>;
-};
-
-&nss1 {
-	qcom,low-frequency = <550000000>; /* orig value 110000000 */
-	qcom,mid-frequency = <550000000>; /* orig value 275000000 */
-	qcom,max-frequency = <550000000>;
-};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
index 2c2505bd2de4ad..115c6d43d24377 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
@@ -82,152 +82,169 @@
 			spi-max-frequency = <50000000>;
 			reg = <0>;
 
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x20000>;
-				read-only;
-			};
-
-			partition@20000 {
-				label = "MIBIB";
-				reg = <0x20000 0x20000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "SBL2";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "SBL3";
-				reg = <0x60000 0x30000>;
-				read-only;
-			};
-
-			partition@90000 {
-				label = "DDRCONFIG";
-				reg = <0x90000 0x10000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "SSD";
-				reg = <0xa0000 0x10000>;
-				read-only;
-			};
-
-			partition@b0000 {
-				label = "TZ";
-				reg = <0xb0000 0x30000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "RPM";
-				reg = <0xe0000 0x20000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "fs-uboot";
-				reg = <0x100000 0x70000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "uboot-env";
-				reg = <0x170000 0x40000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "radio";
-				reg = <0x1b0000 0x40000>;
-				read-only;
-			};
-
-			partition@1f0000 {
-				label = "os-image";
-				reg = <0x1f0000 0x400000>;
-			};
-
-			partition@5f0000 {
-				label = "rootfs";
-				reg = <0x5f0000 0x1900000>;
-			};
-
-			defaultmac: partition@1ef0000 {
-				label = "default-mac";
-				reg = <0x1ef0000 0x00200>;
-				read-only;
-			};
-
-			partition@1ef0200 {
-				label = "pin";
-				reg = <0x1ef0200 0x00200>;
-				read-only;
-			};
-
-			partition@1ef0400 {
-				label = "product-info";
-				reg = <0x1ef0400 0x0fc00>;
-				read-only;
-			};
-
-			partition@1f00000 {
-				label = "partition-table";
-				reg = <0x1f00000 0x10000>;
-				read-only;
-			};
-
-			partition@1f10000 {
-				label = "soft-version";
-				reg = <0x1f10000 0x10000>;
-				read-only;
-			};
-
-			partition@1f20000 {
-				label = "support-list";
-				reg = <0x1f20000 0x10000>;
-				read-only;
-			};
-
-			partition@1f30000 {
-				label = "profile";
-				reg = <0x1f30000 0x10000>;
-				read-only;
-			};
-
-			partition@1f40000 {
-				label = "default-config";
-				reg = <0x1f40000 0x10000>;
-				read-only;
-			};
-
-			partition@1f50000 {
-				label = "user-config";
-				reg = <0x1f50000 0x40000>;
-				read-only;
-			};
-
-			partition@1f90000 {
-				label = "qos-db";
-				reg = <0x1f90000 0x40000>;
-				read-only;
-			};
-
-			partition@1fd0000 {
-				label = "usb-config";
-				reg = <0x1fd0000 0x10000>;
-				read-only;
-			};
-
-			partition@1fe0000 {
-				label = "log";
-				reg = <0x1fe0000 0x20000>;
-				read-only;
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					label = "SBL1";
+					reg = <0x0 0x20000>;
+					read-only;
+				};
+
+				partition@20000 {
+					label = "MIBIB";
+					reg = <0x20000 0x20000>;
+					read-only;
+				};
+
+				partition@40000 {
+					label = "SBL2";
+					reg = <0x40000 0x20000>;
+					read-only;
+				};
+
+				partition@60000 {
+					label = "SBL3";
+					reg = <0x60000 0x30000>;
+					read-only;
+				};
+
+				partition@90000 {
+					label = "DDRCONFIG";
+					reg = <0x90000 0x10000>;
+					read-only;
+				};
+
+				partition@a0000 {
+					label = "SSD";
+					reg = <0xa0000 0x10000>;
+					read-only;
+				};
+
+				partition@b0000 {
+					label = "TZ";
+					reg = <0xb0000 0x30000>;
+					read-only;
+				};
+
+				partition@e0000 {
+					label = "RPM";
+					reg = <0xe0000 0x20000>;
+					read-only;
+				};
+
+				partition@100000 {
+					label = "fs-uboot";
+					reg = <0x100000 0x70000>;
+					read-only;
+				};
+
+				partition@170000 {
+					label = "uboot-env";
+					reg = <0x170000 0x40000>;
+					read-only;
+				};
+
+				partition@1b0000 {
+					label = "radio";
+					reg = <0x1b0000 0x40000>;
+					read-only;
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_radio_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_radio_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
+
+				partition@1f0000 {
+					label = "os-image";
+					reg = <0x1f0000 0x400000>;
+				};
+
+				partition@5f0000 {
+					label = "rootfs";
+					reg = <0x5f0000 0x1900000>;
+				};
+
+				defaultmac: partition@1ef0000 {
+					label = "default-mac";
+					reg = <0x1ef0000 0x00200>;
+					read-only;
+				};
+
+				partition@1ef0200 {
+					label = "pin";
+					reg = <0x1ef0200 0x00200>;
+					read-only;
+				};
+
+				partition@1ef0400 {
+					label = "product-info";
+					reg = <0x1ef0400 0x0fc00>;
+					read-only;
+				};
+
+				partition@1f00000 {
+					label = "partition-table";
+					reg = <0x1f00000 0x10000>;
+					read-only;
+				};
+
+				partition@1f10000 {
+					label = "soft-version";
+					reg = <0x1f10000 0x10000>;
+					read-only;
+				};
+
+				partition@1f20000 {
+					label = "support-list";
+					reg = <0x1f20000 0x10000>;
+					read-only;
+				};
+
+				partition@1f30000 {
+					label = "profile";
+					reg = <0x1f30000 0x10000>;
+					read-only;
+				};
+
+				partition@1f40000 {
+					label = "default-config";
+					reg = <0x1f40000 0x10000>;
+					read-only;
+				};
+
+				partition@1f50000 {
+					label = "user-config";
+					reg = <0x1f50000 0x40000>;
+					read-only;
+				};
+
+				partition@1f90000 {
+					label = "qos-db";
+					reg = <0x1f90000 0x40000>;
+					read-only;
+				};
+
+				partition@1fd0000 {
+					label = "usb-config";
+					reg = <0x1fd0000 0x10000>;
+					read-only;
+				};
+
+				partition@1fe0000 {
+					label = "log";
+					reg = <0x1fe0000 0x20000>;
+					read-only;
+				};
 			};
 		};
 	};
@@ -249,11 +266,42 @@
 
 &pcie0 {
 	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+			mac-address-increment = <(-1)>;
+		};
+	};
 };
 
 &pcie1 {
 	status = "okay";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+		};
+	};
 };
 
 &mdio0 {
@@ -282,29 +330,16 @@
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&defaultmac 0x8>;
-	mtd-mac-address-increment = <1>;
-	
+	nvmem-cells = <&macaddr_defaultmac_8>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <1>;
+
 	fixed-link {
 		speed = <1000>;
 		full-duplex;
@@ -313,24 +348,11 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>; /* none */
-	qcom,poll-required = <0>; /* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-	
-	mtd-mac-address = <&defaultmac 0x8>;
+
+	nvmem-cells = <&macaddr_defaultmac_8>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -341,3 +363,13 @@
 &adm_dma {
 	status = "okay";
 };
+
+&defaultmac {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_defaultmac_8: macaddr@8 {
+		reg = <0x8 0x6>;
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
index b1c8e7c880f801..2f259150fa4db4 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
@@ -11,6 +11,13 @@
 		device_type = "memory";
 	};
 
+	reserved-memory {
+		rsvd@5fe00000 {
+			reg = <0x5fe00000 0x200000>;
+			reusable;
+		};
+	};
+
 	aliases {
 		mdio-gpio0 = &mdio0;
 
@@ -175,6 +182,22 @@
 	reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 	pinctrl-0 = <&pcie0_pins>;
 	pinctrl-names = "default";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+			mac-address-increment = <(1)>;
+		};
+	};
 };
 
 &pcie1 {
@@ -183,6 +206,29 @@
 	pinctrl-0 = <&pcie1_pins>;
 	pinctrl-names = "default";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+			mac-address-increment = <(2)>;
+		};
+	};
+};
+
+&pcie2 {
+	status = "okay";
+	reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&pcie2_pins>;
+	pinctrl-names = "default";
 };
 
 &nand_controller {
@@ -228,10 +274,29 @@
 				read-only;
 			};
 
-			art: art@1200000 {
+			art@1200000 {
 				label = "art";
 				reg = <0x1200000 0x0140000>;
 				read-only;
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_art_0: macaddr@0 {
+					reg = <0x0 0x6>;
+				};
+
+				macaddr_art_6: macaddr@6 {
+					reg = <0x6 0x6>;
+				};
+
+				precal_art_1000: precal@1000 {
+					reg = <0x1000 0x2f20>;
+				};
+
+				precal_art_5000: precal@5000 {
+					reg = <0x5000 0x2f20>;
+				};
 			};
 
 			artbak: art@1340000 {
@@ -285,27 +350,14 @@
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&art 6>;
+	nvmem-cells = <&macaddr_art_6>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -315,24 +367,11 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	mtd-mac-address = <&art 0>;
+
+	nvmem-cells = <&macaddr_art_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-e8350-v1.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-e8350-v1.dts
deleted file mode 100644
index 053c40ee86fd16..00000000000000
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-e8350-v1.dts
+++ /dev/null
@@ -1,279 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "qcom-ipq8064-v2.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Linksys E8350 V1 WiFi Router";
-	compatible = "linksys,e8350-v1", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		serial0 = &gsbi4_serial;
-
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-		};
-	};
-
-	nand-controller@1ac00000 {
-		compatible = "qcom,ipq806x-nand";
-		reg = <0x1ac00000 0x800>;
-		clocks = <&gcc EBI2_CLK>,
-			<&gcc EBI2_AON_CLK>;
-		clock-names = "core", "aon";
-		dmas = <&adm_dma 3>;
-		dma-names = "rxtx";
-		qcom,cmd-crci = <15>;
-		qcom,data-crci = <3>;
-
-		nand@0 {
-			reg = <0>;
-
-			nand-ecc-strength = <4>;
-			nand-bus-width = <8>;
-
-			partitions {
-				compatible = "fixed-partitions";
-
-				partition@0 {
-					label = "ubi";
-					reg = <0 0x4000000>;
-				};
-	
-				partition@4000000 {
-					label = "extra";
-					reg = <0x4000000 0x4000000>;
-				};
-		
-			};
-		};
-	};
-
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power: power {
-			label = "e8350-v1:green:power";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		wps {
-			label = "e8350-v1:green:wps";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-                };
-
-		wifi {
-			label = "e8350-v1:green:wifi";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio68","gpio65", "gpio67";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio26","gpio53", "gpio54";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-};
-
-&gsbi4 {
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-	status = "okay";
-	serial@16340000 {
-		status = "okay";
-	};
-	/*
-	* The i2c device on gsbi4 should not be enabled.
-	* On ipq806x designs gsbi4 i2c is meant for exclusive
-	* RPM usage. Turning this on in kernel manifests as
-	* i2c failure for the RPM.
-	*/
-};
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi5: spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		m25p80@0 {
-			compatible = "jedec,spi-nor";
-			spi-max-frequency = <51200000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "qcom,smem";
-			};
-		};
-	};
-};
-
-&sata_phy {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&usb3_0 {
-	clocks = <&gcc USB30_1_MASTER_CLK>;
-	status = "okay";
-};
-
-&usb3_1 {
-	clocks = <&gcc USB30_0_MASTER_CLK>;
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "okay";
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		qca,ar8327-initvals = <
-			0x00004 0x7600000   /* PAD0_MODE */
-			0x00008 0x1000000   /* PAD5_MODE */
-			0x0000c 0x80        /* PAD6_MODE */
-			0x00010 0x2613a0    /* PWS_REG */
-			0x000e4 0x6a545     /* MAC_POWER_SEL */
-			0x000e0 0xc74164de  /* SGMII_CTRL */
-			0x0007c 0x4e        /* PORT0_STATUS */
-			0x00094 0x4e        /* PORT6_STATUS */
-			>;
-	};
-	
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <0>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&tcsr {
-	qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-	compatible = "qcom,tcsr";
-};
-
-&adm_dma {
-	status = "okay";
-};
\ No newline at end of file
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
index 512d214673eb28..955ad97e3a85d9 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
@@ -133,12 +133,12 @@
 
 			partition@f80000 {
 				label = "kernel1";
-				reg = <0x0f80000 0x2800000>;  /* 3 MB spill to rootfs */
+				reg = <0x0f80000 0x2800000>;  /* 4 MB, spill to rootfs */
 			};
 
-			partition@1280000 {
+			partition@1380000 {
 				label = "rootfs1";
-				reg = <0x1280000 0x2500000>;
+				reg = <0x1380000 0x2400000>;
 			};
 
 			partition@3780000 {
@@ -146,9 +146,9 @@
 				reg = <0x3780000 0x2800000>;
 			};
 
-			partition@3a80000 {
+			partition@3b80000 {
 				label = "rootfs2";
-				reg = <0x3a80000 0x2500000>;
+				reg = <0x3b80000 0x2400000>;
 			};
 		};
 	};
@@ -173,30 +173,13 @@
 			0x00094 0x4e        /* PORT6_STATUS */
 			>;
 	};
-	
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
 };
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <0>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
@@ -209,22 +192,9 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
 
 	fixed-link {
 		speed = <1000>;
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g-nat200.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g-nat200.dts
index 3908c7faa0ef12..bf258e9acebd7f 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g-nat200.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g-nat200.dts
@@ -236,30 +236,13 @@
 			0x00094 0x4e        /* PORT6_STATUS */
 			>;
 	};
-
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
 };
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
@@ -274,22 +257,9 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
 
 	mtd-mac-address = <&ART 0xc>;
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
index d1a3853bc4925f..71dc177b1fb384 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
@@ -122,26 +122,13 @@
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
+	phy-mode = "rgmii";
+	qcom,id = <1>;
+
 	fixed-link {
 		speed = <1000>;
 		full-duplex;
@@ -150,22 +137,9 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
 
 	fixed-link {
 		speed = <1000>;
@@ -196,10 +170,6 @@
 			0x00094 0x4e        /* PORT6_STATUS */
 			>;
 	};
-	
-	ethernet-phy@4 {
-		reg = <4>;
-	};
 };
 
 &nand_controller {
@@ -216,6 +186,9 @@
 		nand-bus-width = <8>;
 		nand-ecc-step-size = <512>;
 
+		nand-is-boot-medium;
+		qcom,boot_pages_size = <0x1200000>;
+
 		partitions {
 			compatible = "qcom,smem-part";
 		};
@@ -224,10 +197,36 @@
 
 &pcie0 {
 	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi5g: wifi@1,0 {
+			reg = <0x00010000 0 0 0 0>;
+			compatible = "qcom,ath10k";
+			qcom,ath10k-calibration-variant = "ASRock-G10";
+		};
+	};
 };
 
 &pcie1 {
 	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi2g: wifi@1,0 {
+			reg = <0x00010000 0 0 0 0>;
+			compatible = "qcom,ath10k";
+			qcom,ath10k-calibration-variant = "ASRock-G10";
+		};
+	};
 };
 
 &qcom_pinmux {
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
index e3b90d7159b11b..f4d452d0610c9c 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
@@ -1,4 +1,4 @@
-#include "qcom-ipq8064-v2.0.dtsi"
+#include "qcom-ipq8064-v1.0.dtsi"
 
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/soc/qcom,tcsr.h>
@@ -148,12 +148,10 @@
 };
 
 &usb3_0 {
-	clocks = <&gcc USB30_1_MASTER_CLK>;
 	status = "okay";
 };
 
 &usb3_1 {
-	clocks = <&gcc USB30_0_MASTER_CLK>;
 	status = "okay";
 };
 
@@ -219,9 +217,20 @@
 
 			ubi@1740000 {
 				label = "ubi";
-				reg = <0x1740000 0x68C0000>;
+				reg = <0x1740000 0x1600000>;
+			};
+
+			netgear@2d40000 {
+				label = "netgear";
+				reg = <0x2d40000 0x0c00000>;
+				read-only;
+			};
+
+			reserve@3940000 {
+				label = "reserve";
+				reg = <0x3940000 0x46c0000>;
+				read-only;
 			};
-			
 		};
 	};
 };
@@ -252,27 +261,14 @@
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&art 6>;
+	nvmem-cells = <&macaddr_art_6>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -282,24 +278,11 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	mtd-mac-address = <&art 0>;
+
+	nvmem-cells = <&macaddr_art_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -315,3 +298,17 @@
 &adm_dma {
 	status = "okay";
 };
+
+&art {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_art_0: macaddr@0 {
+		reg = <0x0 0x6>;
+	};
+
+	macaddr_art_6: macaddr@6 {
+		reg = <0x6 0x6>;
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
index 5f41b4001d48aa..b3181d8857d9e3 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
@@ -186,6 +186,22 @@
 	reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 	pinctrl-0 = <&pcie0_pins>;
 	pinctrl-names = "default";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+			mac-address-increment = <(1)>;
+		};
+	};
 };
 
 &pcie1 {
@@ -194,6 +210,22 @@
 	pinctrl-0 = <&pcie1_pins>;
 	pinctrl-names = "default";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+			mac-address-increment = <(2)>;
+		};
+	};
 };
 
 &nand_controller {
@@ -236,10 +268,29 @@
 				read-only;
 			};
 
-			art: art@1200000 {
+			art@1200000 {
 				label = "art";
 				reg = <0x1200000 0x0140000>;
 				read-only;
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_art_0: macaddr@0 {
+					reg = <0x0 0x6>;
+				};
+
+				macaddr_art_6: macaddr@6 {
+					reg = <0x6 0x6>;
+				};
+
+				precal_art_1000: precal@1000 {
+					reg = <0x1000 0x2f20>;
+				};
+
+				precal_art_5000: precal@5000 {
+					reg = <0x5000 0x2f20>;
+				};
 			};
 
 			artbak: art@1340000 {
@@ -293,27 +344,14 @@
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&art 6>;
+	nvmem-cells = <&macaddr_art_6>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -323,24 +361,11 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	mtd-mac-address = <&art 0>;
+
+	nvmem-cells = <&macaddr_art_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-rg-mtfi-m520.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-rg-mtfi-m520.dts
index db992d7ae83ed7..d3cf1d5d14d882 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-rg-mtfi-m520.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-rg-mtfi-m520.dts
@@ -264,6 +264,7 @@
 	status = "okay";
 	pinctrl-0 = <&mdio0_pins>;
 	pinctrl-names = "default";
+
 	phy0: ethernet-phy@0 {
 		reg = <0>;
 		qca,ar8327-initvals = <
@@ -276,29 +277,13 @@
 			0x00094 0x4e        /* PORT6_STATUS */
 			>;
 	};
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
 };
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <0>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
@@ -311,22 +296,9 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
 
 	fixed-link {
 		speed = <1000>;
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
index d6ac1fef1de164..a50204fee14674 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
@@ -250,7 +250,8 @@
 	phy-mode = "sgmii";
 	qcom,id = <1>;
 
-	mtd-mac-address = <&eeprom 0x6>;
+	nvmem-cells = <&macaddr_eeprom_6>;
+	nvmem-cell-names = "mac-address";
 };
 
 &gmac2 {
@@ -261,7 +262,8 @@
 	phy-mode = "sgmii";
 	qcom,id = <2>;
 
-	mtd-mac-address = <&eeprom 0x0>;
+	nvmem-cells = <&macaddr_eeprom_0>;
+	nvmem-cell-names = "mac-address";
 };
 
 &pcie0 {
@@ -299,3 +301,17 @@
 &usb3_1 {
 	status = "okay";
 };
+
+&eeprom {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_eeprom_0: macaddr@0 {
+		reg = <0x0 0x6>;
+	};
+
+	macaddr_eeprom_6: macaddr@6 {
+		reg = <0x6 0x6>;
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
index 893addf240909b..27d9fc84b35ffa 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
@@ -176,99 +176,124 @@
 
 		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 
-		W25Q128@0 {
+		flash@0 {
 			compatible = "jedec,spi-nor";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			spi-max-frequency = <50000000>;
 			reg = <0>;
 
-			SBL1@0 {
-				label = "SBL1";
-				reg = <0x0 0x20000>;
-				read-only;
-			};
-
-			MIBIB@20000 {
-				label = "MIBIB";
-				reg = <0x20000 0x20000>;
-				read-only;
-			};
-
-			SBL2@40000 {
-				label = "SBL2";
-				reg = <0x40000 0x40000>;
-				read-only;
-			};
-
-			SBL3@80000 {
-				label = "SBL3";
-				reg = <0x80000 0x80000>;
-				read-only;
-			};
-
-			DDRCONFIG@100000 {
-				label = "DDRCONFIG";
-				reg = <0x100000 0x10000>;
-				read-only;
-			};
-
-			SSD@110000 {
-				label = "SSD";
-				reg = <0x110000 0x10000>;
-				read-only;
-			};
-
-			TZ@120000 {
-				label = "TZ";
-				reg = <0x120000 0x80000>;
-				read-only;
-			};
-
-			RPM@1a0000 {
-				label = "RPM";
-				reg = <0x1a0000 0x80000>;
-				read-only;
-			};
-
-			APPSBL@220000 {
-				label = "APPSBL";
-				reg = <0x220000 0x80000>;
-				read-only;
-			};
-
-			APPSBLENV@2a0000 {
-				label = "APPSBLENV";
-				reg = <0x2a0000 0x40000>;
-				read-only;
-			};
-
-			OLDART@2e0000 {
-				label = "OLDART";
-				reg = <0x2e0000 0x40000>;
-				read-only;
-			};
-
-			kernel@320000 {
-				label = "kernel";
-				reg = <0x320000 0x300000>;
-			};
-
-			rootfs@620000 {
-				label = "rootfs";
-				reg = <0x620000 0x960000>;
-			};
-
-			defaultmac: default-mac@0xfaf100 {
-				label = "default-mac";
-				reg = <0xfaf100 0x00200>;
-				read-only;
-			};
-
-			ART@fc0000 {
-				label = "ART";
-				reg = <0xfc0000 0x40000>;
-				read-only;
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					label = "SBL1";
+					reg = <0x0 0x20000>;
+					read-only;
+				};
+
+				partition@20000 {
+					label = "MIBIB";
+					reg = <0x20000 0x20000>;
+					read-only;
+				};
+
+				partition@40000 {
+					label = "SBL2";
+					reg = <0x40000 0x40000>;
+					read-only;
+				};
+
+				partition@80000 {
+					label = "SBL3";
+					reg = <0x80000 0x80000>;
+					read-only;
+				};
+
+				partition@100000 {
+					label = "DDRCONFIG";
+					reg = <0x100000 0x10000>;
+					read-only;
+				};
+
+				partition@110000 {
+					label = "SSD";
+					reg = <0x110000 0x10000>;
+					read-only;
+				};
+
+				partition@120000 {
+					label = "TZ";
+					reg = <0x120000 0x80000>;
+					read-only;
+				};
+
+				partition@1a0000 {
+					label = "RPM";
+					reg = <0x1a0000 0x80000>;
+					read-only;
+				};
+
+				partition@220000 {
+					label = "APPSBL";
+					reg = <0x220000 0x80000>;
+					read-only;
+				};
+
+				partition@2a0000 {
+					label = "APPSBLENV";
+					reg = <0x2a0000 0x40000>;
+					read-only;
+				};
+
+				partition@2e0000 {
+					label = "OLDART";
+					reg = <0x2e0000 0x40000>;
+					read-only;
+				};
+
+				partition@320000 {
+					label = "firmware";
+					reg = <0x320000 0xc60000>;
+					compatible = "openwrt,uimage";
+					openwrt,offset = <512>; /* account for pad-extra 512 */
+				};
+
+				/* hole 0xf80000 - 0xfaf100 */
+
+				partition@faf100 {
+					label = "default-mac";
+					reg = <0xfaf100 0x00200>;
+					read-only;
+
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_defaultmac_0: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+				};
+
+				partition@fc0000 {
+					label = "ART";
+					reg = <0xfc0000 0x40000>;
+					read-only;
+
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_ART_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_ART_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
 			};
 		};
 	};
@@ -284,11 +309,42 @@
 
 &pcie0 {
 	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+			mac-address-increment = <(-1)>;
+		};
+	};
 };
 
 &pcie1 {
 	status = "okay";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+		};
+	};
 };
 
 &mdio0 {
@@ -323,8 +379,9 @@
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&defaultmac 0>;
-	mtd-mac-address-increment = <1>;
+	nvmem-cells = <&macaddr_defaultmac_0>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <1>;
 
 	fixed-link {
 		speed = <1000>;
@@ -337,7 +394,8 @@
 	phy-mode = "sgmii";
 	qcom,id = <2>;
 
-	mtd-mac-address = <&defaultmac 0>;
+	nvmem-cells = <&macaddr_defaultmac_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
index 635e9fc8f94425..998dad55c5e591 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
@@ -167,7 +167,8 @@
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&PRODUCTDATA 6>;
+	nvmem-cells = <&macaddr_PRODUCTDATA_6>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -181,7 +182,8 @@
 	phy-mode = "sgmii";
 	qcom,id = <2>;
 
-	mtd-mac-address = <&PRODUCTDATA 0>;
+	nvmem-cells = <&macaddr_PRODUCTDATA_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -281,6 +283,17 @@
 					label = "ART";
 					reg = <0x2e0000 0x40000>;
 					read-only;
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_ART_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_ART_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 
 				TP@320000 {
@@ -318,11 +331,41 @@
 
 &pcie0 {
 	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+		};
+	};
 };
 
 &pcie1 {
 	status = "okay";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+		};
+	};
 };
 
 &qcom_pinmux {
@@ -380,3 +423,25 @@
 		};
 	};
 };
+
+&PRODUCTDATA {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_PRODUCTDATA_0: macaddr@0 {
+		reg = <0x0 0x6>;
+	};
+
+	macaddr_PRODUCTDATA_6: macaddr@6 {
+		reg = <0x6 0x6>;
+	};
+
+	macaddr_PRODUCTDATA_c: macaddr@c {
+		reg = <0xc 0x6>;
+	};
+
+	macaddr_PRODUCTDATA_12: macaddr@12 {
+		reg = <0x12 0x6>;
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
index 8c4e3b71e36e6e..e7ae1a25b2cd5e 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
@@ -229,7 +229,8 @@
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&ART 6>;
+	nvmem-cells = <&macaddr_ART_6>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -243,7 +244,8 @@
 	phy-mode = "sgmii";
 	qcom,id = <2>;
 
-	mtd-mac-address = <&ART 0>;
+	nvmem-cells = <&macaddr_ART_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -338,10 +340,38 @@
 					read-only;
 				};
 
-				ART: ART@180000 {
+				ART@180000 {
 					label = "ART";
 					reg = <0x180000 0x40000>;
 					read-only;
+
+					compatible = "nvmem-cells";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_ART_0: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+
+					macaddr_ART_6: macaddr@6 {
+						reg = <0x6 0x6>;
+					};
+
+					macaddr_ART_18: macaddr@18 {
+						reg = <0x18 0x6>;
+					};
+
+					macaddr_ART_1e: macaddr@1e {
+						reg = <0x1e 0x6>;
+					};
+
+					precal_ART_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_ART_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
 				};
 
 				BOOTCONFIG@1c0000 {
@@ -393,11 +423,41 @@
 
 &pcie0 {
 	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+		};
+	};
 };
 
 &pcie1 {
 	status = "okay";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
+			nvmem-cell-names = "mac-address", "pre-calibration";
+		};
+	};
 };
 
 &qcom_pinmux {
@@ -463,4 +523,4 @@
 			output-high;
 		};
 	};
-};
\ No newline at end of file
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-core-518.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-core-518.dts
deleted file mode 100755
index 3263c2d6d8871c..00000000000000
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-core-518.dts
+++ /dev/null
@@ -1,462 +0,0 @@
-#include "qcom-ipq8065.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Norton Core 518";
-	compatible = "norton,core-518", "qcom,ipq8065", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x3e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		rsvd@41200000 {
-			reg = <0x41200000 0x300000>;
-			no-map;
-		};
-	};
-
-	aliases {
-		serial0 = &gsbi4_serial;
-		mdio-gpio0 = &mdio0;
-		sdcc1 = &sdcc1;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd";
-		stdout-path = "serial0:115200n8";
-		append-rootblock = "root=/dev/mmcblk0p";
-	};
-
-	soc {
-		pinmux@800000 {
-			button_pins: button_pins {
-				mux {
-					pins = "gpio68";
-					function = "gpio";
-					drive-strength = <2>;
-					bias-pull-up;
-				};
-			};
-
-			hs_uart_pins: hs_uart_pins {
-				mux {
-					pins = "gpio6", "gpio7", "gpio8", "gpio9";
-					function = "gsbi7";
-					drive-strength = <0xc>;
-					bias-disable;
-				};
-			};
-
-			serial_pins: serial_pins {
-				mux {
-					pins = "gpio55", "gpio56";
-					function = "gsbi6";
-					drive-strength = <0xc>;
-					bias-disable;
-				};
-			};
-
-			i2c_pins: i2c_pins {
-				mux {
-					pins = "gpio57", "gpio58";
-					function = "gsbi6";
-					drive-strength = <0xc>;
-					bias-disable;
-				};
-			};
-
-			sdcc1_pins: sdcc1_pinmux {
-				mux {
-					pins = "gpio38", "gpio39", "gpio40",
-					"gpio41", "gpio42", "gpio43",
-					"gpio44", "gpio45", "gpio46",
-					"gpio47";
-					function = "sdc1";
-				};
-				cmd {
-					pins = "gpio45";
-					drive-strength = <10>;
-					bias-pull-up;
-				};
-				data {
-					pins = "gpio38", "gpio39", "gpio40",
-					"gpio41", "gpio43", "gpio44",
-					"gpio46", "gpio47";
-					drive-strength = <10>;
-					bias-pull-up;
-				};
-				clk {
-					pins = "gpio42";
-					drive-strength = <16>;
-					bias-disable;
-				};
-			};
-
-			mdio0_pins: mdio0_pins {
-				mux {
-					pins = "gpio0", "gpio1";
-					function = "gpio";
-					drive-strength = <8>;
-					bias-disable;
-				};
-
-				clk {
-					pins = "gpio1";
-					input-disable;
-				};
-			};
-
-			rgmii2_pins: rgmii2_pins {
-				mux {
-					pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
-					       "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
-					function = "rgmii2";
-					drive-strength = <8>;
-					bias-disable;
-				};
-
-				tx {
-					pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
-					input-disable;
-				};
-			};
-
-			spi_pins: spi_pins {
-				mux {
-					pins = "gpio18", "gpio19", "gpio21";
-					function = "gsbi5";
-					drive-strength = <10>;
-					bias-none;
-				};
-
-				cs {
-					pins = "gpio20";
-					drive-strength = <12>;
-				};
-			};
-
-			usb0_pwr_en_pins: usb0_pwr_en_pins {
-				mux {
-					pins = "gpio22", "gpio24";
-					function = "gpio";
-					drive-strength = <12>;
-				};
-
-				pwr {
-					pins = "gpio22";
-					bias-pull-down;
-					output-high;
-				};
-
-				ovc {
-					pins = "gpio24";
-					bias-pull-up;
-				};
-			};
-
-			usb1_pwr_en_pins: usb1_pwr_en_pins {
-				mux {
-					pins = "gpio23", "gpio25";
-					function = "gpio";
-					drive-strength = <12>;
-				};
-
-				pwr {
-					pins = "gpio23";
-					bias-pull-down;
-					output-high;
-				};
-
-				ovc {
-					pins = "gpio25";
-					bias-pull-up;
-				};
-			};
-		};
-
-		gsbi@16300000 {
-			qcom,mode = <GSBI_PROT_I2C_UART>;
-			status = "okay";
-			serial@16340000 {
-				status = "okay";
-			};
-			/*
-			 * The i2c device on gsbi4 should not be enabled.
-			 * On ipq806x designs gsbi4 i2c is meant for exclusive
-			 * RPM usage. Turning this on in kernel manifests as
-			 * i2c failure for the RPM.
-			 */
-		};
-
-		gsbi5: gsbi@1a200000 {
-			qcom,mode = <GSBI_PROT_SPI>;
-			status = "okay";
-
-			spi4: spi@1a280000 {
-				status = "okay";
-
-				pinctrl-0 = <&spi_pins>;
-				pinctrl-names = "default";
-
-				cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-				flash: m25p80@0 {
-					compatible = "jedec,spi-nor";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					spi-max-frequency = <51200000>;
-					reg = <0>;
-
-					partitions {
-						compatible = "qcom,smem";
-					};
-				};
-			};
-		};
-
-		// gsbi@16500000 {
-		// 	status = "okay";
-		// 	qcom,mode = < 0x06 >;
-
-		// 	i2c@16580000 {
-		// 		status = "okay";
-
-		// 		ncp5623@38 {
-		// 			compatible = "ncp5623";
-		// 			reg = < 0x38 >;
-
-		// 			white {
-		// 				label = "white";
-		// 				led_group = < 0x05 >;
-		// 				linux,default-trigger = "timer";
-		// 			};
-
-		// 			amber {
-		// 				label = "amber";
-		// 				led_group = < 0x02 >;
-		// 				init_state = "full_on";
-		// 				linux,default-trigger = "none";
-		// 			};
-		// 		};
-		// 	};
-		// };
-
-		phy@100f8800 {		/* USB3 port 1 HS phy */
-			status = "okay";
-		};
-
-		phy@100f8830 {		/* USB3 port 1 SS phy */
-			status = "okay";
-		};
-
-		phy@110f8800 {		/* USB3 port 0 HS phy */
-			status = "okay";
-		};
-
-		phy@110f8830 {		/* USB3 port 0 SS phy */
-			status = "okay";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		qca,ar8327-initvals = <
-			0x00004 0x7600000   /* PAD0_MODE */
-			0x00008 0x1000000   /* PAD5_MODE */
-			0x0000c 0x80        /* PAD6_MODE */
-			0x000e4 0xaa545     /* MAC_POWER_SEL */
-			0x000e0 0xc74164de  /* SGMII_CTRL */
-			0x0007c 0x4e        /* PORT0_STATUS */
-			0x00094 0x4e        /* PORT6_STATUS */
-			0x00970 0x1e864443  /* QM_PORT0_CTRL0 */
-			0x00974 0x000001c6  /* QM_PORT0_CTRL1 */
-			0x00978 0x19008643  /* QM_PORT1_CTRL0 */
-			0x0097c 0x000001c6  /* QM_PORT1_CTRL1 */
-			0x00980 0x19008643  /* QM_PORT2_CTRL0 */
-			0x00984 0x000001c6  /* QM_PORT2_CTRL1 */
-			0x00988 0x19008643  /* QM_PORT3_CTRL0 */
-			0x0098c 0x000001c6  /* QM_PORT3_CTRL1 */
-			0x00990 0x19008643  /* QM_PORT4_CTRL0 */
-			0x00994 0x000001c6  /* QM_PORT4_CTRL1 */
-			0x00998 0x1e864443  /* QM_PORT5_CTRL0 */
-			0x0099c 0x000001c6  /* QM_PORT5_CTRL1 */
-			0x009a0 0x1e864443  /* QM_PORT6_CTRL0 */
-			0x009a4 0x000001c6  /* QM_PORT6_CTRL1 */
-			>;
-	};
-
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-		qca,ar8327-initvals = <
-			0x000e4 0x6a545     /* MAC_POWER_SEL */
-			0x0000c 0x80        /* PAD6_MODE */
-			>;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-// &gmac1 {
-// 	status = "okay";
-// 	phy-mode = "rgmii";
-// 	qcom,id = <1>;
-// 	qcom,phy_mdio_addr = <4>;
-// 	qcom,poll_required = <0>;
-// 	qcom,rgmii_delay = <1>;
-// 	qcom,phy_mii_type = <0>;
-// 	qcom,emulation = <0>;
-// 	qcom,irq = <255>;
-// 	mdiobus = <&mdio0>;
-
-// 	pinctrl-0 = <&rgmii2_pins>;
-// 	pinctrl-names = "default";
-
-// 	fixed-link {
-// 		speed = <1000>;
-// 		full-duplex;
-// 	};
-// };
-
-// &gmac2 {
-// 	status = "okay";
-// 	phy-mode = "sgmii";
-// 	qcom,id = <2>;
-// 	qcom,phy_mdio_addr = <0>;	/* none */
-// 	qcom,poll_required = <0>;	/* no polling */
-// 	qcom,rgmii_delay = <0>;
-// 	qcom,phy_mii_type = <1>;
-// 	qcom,emulation = <0>;
-// 	qcom,irq = <258>;
-// 	mdiobus = <&mdio0>;
-
-// 	fixed-link {
-// 		speed = <1000>;
-// 		full-duplex;
-// 	};
-// };
-
-&pcie0 {
-	status = "okay";
-	reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-};
-
-&amba {
-	sdcc1: sdcc@12400000 {
-		status = "okay";
-		pinctrl-0 = <&sdcc1_pins>;
-		pinctrl-names = "default";
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
index 3eae01aa7a2523..969ca724e3ae50 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
@@ -268,20 +268,13 @@
 
 &gmac1 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "rgmii";
 	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
+	qcom,phy_mdio_addr = <4>;
+	qcom,poll_required = <0>;
+	qcom,rgmii_delay = <1>;
 	qcom,phy_mii_type = <0>;
 	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
 	qcom,irq = <255>;
 	mdiobus = <&mdio0>;
 
@@ -296,20 +289,13 @@
 
 &gmac2 {
 	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 	phy-mode = "sgmii";
 	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
+	qcom,phy_mdio_addr = <0>;	/* none */
+	qcom,poll_required = <0>;	/* no polling */
+	qcom,rgmii_delay = <0>;
 	qcom,phy_mii_type = <1>;
 	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
 	qcom,irq = <258>;
 	mdiobus = <&mdio0>;
 
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
new file mode 100644
index 00000000000000..cca887bb3bc898
--- /dev/null
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
@@ -0,0 +1,453 @@
+#include "qcom-ipq8065.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+	memory@0 {
+		reg = <0x42000000 0x1e000000>;
+		device_type = "memory";
+	};
+
+	reserved-memory {
+		rsvd@5fe00000 {
+			reg = <0x5fe00000 0x200000>;
+			reusable;
+		};
+
+		ramoops@42100000 {
+			compatible = "ramoops";
+			reg = <0x42100000 0x40000>;
+			record-size = <0x4000>;
+			console-size = <0x4000>;
+			ftrace-size = <0x4000>;
+			pmsg-size = <0x4000>;
+		};
+	};
+
+	aliases {
+		label-mac-device = &gmac2;
+
+		led-boot = &power_white;
+		led-failsafe = &power_amber;
+		led-running = &power_white;
+		led-upgrade = &power_amber;
+
+		mdio-gpio0 = &mdio0;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		wifi {
+			label = "wifi";
+			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		power_white: power_white {
+			label = "white:power";
+			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+
+		power_amber: power_amber {
+			label = "amber:power";
+			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		wan_white {
+			label = "white:wan";
+			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		wan_amber {
+			label = "amber:wan";
+			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
+		};
+
+		wifi {
+			label = "white:wifi";
+			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
+		};
+
+		wps {
+			label = "white:wps";
+			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&qcom_pinmux {
+	button_pins: button_pins {
+		mux {
+			pins = "gpio6", "gpio54", "gpio65";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	led_pins: led_pins {
+		mux {
+			pins = "gpio7", "gpio8", "gpio9",
+				"gpio22", "gpio23", "gpio24",
+				"gpio26", "gpio53", "gpio64";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	mdio0_pins: mdio0_pins {
+		clk {
+			pins = "gpio1";
+			input-disable;
+		};
+	};
+
+	rgmii2_pins: rgmii2_pins {
+		tx {
+			pins = "gpio27", "gpio28", "gpio29",
+				"gpio30", "gpio31", "gpio32";
+			input-disable;
+		};
+	};
+
+	spi_pins: spi_pins {
+		mux {
+			pins = "gpio18", "gpio19", "gpio21";
+			function = "gsbi5";
+			bias-pull-down;
+		};
+
+		data {
+			pins = "gpio18", "gpio19";
+			drive-strength = <10>;
+		};
+
+		cs {
+			pins = "gpio20";
+			drive-strength = <10>;
+			bias-pull-up;
+		};
+
+		clk {
+			pins = "gpio21";
+			drive-strength = <12>;
+		};
+	};
+
+	spi6_pins: spi6_pins {
+		mux {
+			pins = "gpio55", "gpio56", "gpio58";
+			function = "gsbi6";
+			bias-pull-down;
+		};
+
+		mosi {
+			pins = "gpio55";
+			drive-strength = <12>;
+		};
+
+		miso {
+			pins = "gpio56";
+			drive-strength = <14>;
+		};
+
+		cs {
+			pins = "gpio57";
+			drive-strength = <12>;
+			bias-pull-up;
+		};
+
+		clk {
+			pins = "gpio58";
+			drive-strength = <12>;
+		};
+
+		reset {
+			pins = "gpio33";
+			drive-strength = <10>;
+			bias-pull-down;
+			output-high;
+		};
+	};
+
+	usb0_pwr_en_pins: usb0_pwr_en_pins {
+		mux {
+			pins = "gpio15";
+			function = "gpio";
+			drive-strength = <12>;
+			bias-pull-down;
+			output-high;
+		};
+	};
+
+	usb1_pwr_en_pins: usb1_pwr_en_pins {
+		mux {
+			pins = "gpio16", "gpio68";
+			function = "gpio";
+			drive-strength = <12>;
+			bias-pull-down;
+			output-high;
+		};
+	};
+};
+
+&nand_controller {
+	status = "okay";
+
+	pinctrl-0 = <&nand_pins>;
+	pinctrl-names = "default";
+
+	nand@0 {
+		reg = <0>;
+		compatible = "qcom,nandcs";
+
+		nand-ecc-strength = <4>;
+		nand-bus-width = <8>;
+		nand-ecc-step-size = <512>;
+
+		nand-is-boot-medium;
+		qcom,boot_pages_size = <0x1180000>;
+
+		partitions: partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "qcadata";
+				reg = <0x0000000 0x0c80000>;
+				read-only;
+			};
+
+			partition@c80000 {
+				label = "APPSBL";
+				reg = <0x0c80000 0x0500000>;
+				read-only;
+			};
+
+			partition@1180000 {
+				label = "APPSBLENV";
+				reg = <0x1180000 0x0080000>;
+				read-only;
+			};
+
+			art: partition@1200000 {
+				label = "art";
+				reg = <0x1200000 0x0140000>;
+				read-only;
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_art_0: macaddr@0 {
+					reg = <0x0 0x6>;
+				};
+
+				macaddr_art_6: macaddr@6 {
+					reg = <0x6 0x6>;
+				};
+
+				precal_art_1000: precal@1000 {
+					reg = <0x1000 0x2f20>;
+				};
+
+				precal_art_5000: precal@5000 {
+					reg = <0x5000 0x2f20>;
+				};
+			};
+
+			partition@1340000 {
+				label = "artbak";
+				reg = <0x1340000 0x0140000>;
+				read-only;
+			};
+
+			partition@1480000 {
+				label = "kernel";
+				reg = <0x1480000 0x0400000>;
+			};
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio0_pins>;
+	pinctrl-names = "default";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		qca,ar8327-initvals = <
+			0x00004 0x7600000   /* PAD0_MODE */
+			0x00008 0x1000000   /* PAD5_MODE */
+			0x0000c 0x80        /* PAD6_MODE */
+			0x000e4 0xaa545     /* MAC_POWER_SEL */
+			0x000e0 0xc74164de  /* SGMII_CTRL */
+			0x0007c 0x4e        /* PORT0_STATUS */
+			0x00094 0x4e        /* PORT6_STATUS */
+			0x00970 0x1e864443  /* QM_PORT0_CTRL0 */
+			0x00974 0x000001c6  /* QM_PORT0_CTRL1 */
+			0x00978 0x19008643  /* QM_PORT1_CTRL0 */
+			0x0097c 0x000001c6  /* QM_PORT1_CTRL1 */
+			0x00980 0x19008643  /* QM_PORT2_CTRL0 */
+			0x00984 0x000001c6  /* QM_PORT2_CTRL1 */
+			0x00988 0x19008643  /* QM_PORT3_CTRL0 */
+			0x0098c 0x000001c6  /* QM_PORT3_CTRL1 */
+			0x00990 0x19008643  /* QM_PORT4_CTRL0 */
+			0x00994 0x000001c6  /* QM_PORT4_CTRL1 */
+			0x00998 0x1e864443  /* QM_PORT5_CTRL0 */
+			0x0099c 0x000001c6  /* QM_PORT5_CTRL1 */
+			0x009a0 0x1e864443  /* QM_PORT6_CTRL0 */
+			0x009a4 0x000001c6  /* QM_PORT6_CTRL1 */
+			>;
+		qca,ar8327-vlans = <
+			0x1	0x5e	    /* VLAN1 Ports 1/2/3/4/6 */
+			0x2	0x21	    /* VLAN2 Ports 0/5 */
+		>;
+	};
+
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+		qca,ar8327-initvals = <
+			0x000e4 0x6a545     /* MAC_POWER_SEL */
+			0x0000c 0x80        /* PAD6_MODE */
+			>;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	qcom,id = <1>;
+	qcom,phy_mdio_addr = <4>;
+	qcom,poll_required = <0>;
+	qcom,rgmii_delay = <1>;
+	qcom,phy_mii_type = <0>;
+	qcom,emulation = <0>;
+	qcom,irq = <255>;
+	mdiobus = <&mdio0>;
+
+	pinctrl-0 = <&rgmii2_pins>;
+	pinctrl-names = "default";
+
+	nvmem-cells = <&macaddr_art_6>;
+	nvmem-cell-names = "mac-address";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&gmac2 {
+	status = "okay";
+
+	phy-mode = "sgmii";
+	qcom,id = <2>;
+	qcom,phy_mdio_addr = <0>;	/* none */
+	qcom,poll_required = <0>;	/* no polling */
+	qcom,rgmii_delay = <0>;
+	qcom,phy_mii_type = <1>;
+	qcom,emulation = <0>;
+	qcom,irq = <258>;
+	mdiobus = <&mdio0>;
+
+	nvmem-cells = <&macaddr_art_0>;
+	nvmem-cell-names = "mac-address";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&adm_dma {
+	status = "okay";
+};
+
+&sata_phy {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+
+	pinctrl-0 = <&usb0_pwr_en_pins>;
+	pinctrl-names = "default";
+};
+
+&usb3_1 {
+	status = "okay";
+
+	pinctrl-0 = <&usb1_pwr_en_pins>;
+	pinctrl-names = "default";
+};
+
+&pcie0 {
+	status = "okay";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi0: wifi@1,0 {
+			compatible = "pci168c,0046";
+			reg = <0x00010000 0 0 0 0>;
+		};
+	};
+};
+
+&pcie1 {
+	status = "okay";
+
+	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi1: wifi@1,0 {
+			compatible = "pci168c,0046";
+			reg = <0x00010000 0 0 0 0>;
+		};
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
index 5d5c44fcc7029e..bf7c963944b72d 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
@@ -1,466 +1,48 @@
-#include "qcom-ipq8065.dtsi"
-
-#include <dt-bindings/input/input.h>
+#include "qcom-ipq8065-nighthawk.dtsi"
 
 / {
 	model = "Netgear Nighthawk X4S R7800";
 	compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		rsvd@5fe00000 {
-			reg = <0x5fe00000 0x200000>;
-			reusable;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &power_white;
-		led-failsafe = &power_amber;
-		led-running = &power_white;
-		led-upgrade = &power_amber;
-		label-mac-device = &gmac2;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		power_white: power_white {
-			label = "white:power";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		power_amber: power_amber {
-			label = "amber:power";
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_white {
-			label = "white:wan";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_amber {
-			label = "amber:wan";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb1 {
-			label = "white:usb1";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb2 {
-			label = "white:usb2";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		esata {
-			label = "white:esata";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		wifi {
-			label = "white:wifi";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			label = "white:wps";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-	};
 };
 
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
-				"gpio24","gpio26", "gpio53", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	mdio0_pins: mdio0_pins {
-		clk {
-			pins = "gpio1";
-			input-disable;
-		};
-	};
-
-	rgmii2_pins: rgmii2_pins {
-		tx {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
+&leds {
+	usb1 {
+		label = "white:usb1";
+		gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
 	};
 
-	spi6_pins: spi6_pins {
-		mux {
-			pins = "gpio55", "gpio56", "gpio58";
-			function = "gsbi6";
-			bias-pull-down;
-		};
-
-		mosi {
-			pins = "gpio55";
-			drive-strength = <12>;
-		};
-
-		miso {
-			pins = "gpio56";
-			drive-strength = <14>;
-		};
-
-		cs {
-			pins = "gpio57";
-			drive-strength = <12>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio58";
-			drive-strength = <12>;
-		};
-
-		reset {
-			pins = "gpio33";
-			drive-strength = <10>;
-			bias-pull-down;
-			output-high;
-		};
+	usb2 {
+		label = "white:usb2";
+		gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
 	};
 
-	usb0_pwr_en_pins: usb0_pwr_en_pins {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb1_pwr_en_pins: usb1_pwr_en_pins {
-		mux {
-			pins = "gpio16", "gpio68";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
+	esata {
+		label = "white:esata";
+		gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
 	};
 };
 
-&nand_controller {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot_pages_size = <0x1180000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			qcadata@0 {
-				label = "qcadata";
-				reg = <0x0000000 0x0c80000>;
-				read-only;
-			};
-
-			APPSBL@c80000 {
-				label = "APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			APPSBLENV@1180000 {
-				label = "APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-				read-only;
-			};
-
-			art: art@1200000 {
-				label = "art";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-			};
-
-			artbak: art@1340000 {
-				label = "artbak";
-				reg = <0x1340000 0x0140000>;
-				read-only;
-			};
-
-			kernel@1480000 {
-				label = "kernel";
-				reg = <0x1480000 0x0400000>;
-			};
-
-			ubi@1880000 {
-				label = "ubi";
-				reg = <0x1880000 0x6080000>;
-			};
-
-			reserve@7900000 {
-				label = "reserve";
-				reg = <0x7900000 0x0700000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		qca,ar8327-initvals = <
-			0x00004 0x7600000   /* PAD0_MODE */
-			0x00008 0x1000000   /* PAD5_MODE */
-			0x0000c 0x80        /* PAD6_MODE */
-			0x000e4 0xaa545     /* MAC_POWER_SEL */
-			0x000e0 0xc74164de  /* SGMII_CTRL */
-			0x0007c 0x4e        /* PORT0_STATUS */
-			0x00094 0x4e        /* PORT6_STATUS */
-			0x00970 0x1e864443  /* QM_PORT0_CTRL0 */
-			0x00974 0x000001c6  /* QM_PORT0_CTRL1 */
-			0x00978 0x19008643  /* QM_PORT1_CTRL0 */
-			0x0097c 0x000001c6  /* QM_PORT1_CTRL1 */
-			0x00980 0x19008643  /* QM_PORT2_CTRL0 */
-			0x00984 0x000001c6  /* QM_PORT2_CTRL1 */
-			0x00988 0x19008643  /* QM_PORT3_CTRL0 */
-			0x0098c 0x000001c6  /* QM_PORT3_CTRL1 */
-			0x00990 0x19008643  /* QM_PORT4_CTRL0 */
-			0x00994 0x000001c6  /* QM_PORT4_CTRL1 */
-			0x00998 0x1e864443  /* QM_PORT5_CTRL0 */
-			0x0099c 0x000001c6  /* QM_PORT5_CTRL1 */
-			0x009a0 0x1e864443  /* QM_PORT6_CTRL0 */
-			0x009a4 0x000001c6  /* QM_PORT6_CTRL1 */
-			>;
-		qca,ar8327-vlans = <
-			0x1	0x5e	    /* VLAN1 Ports 1/2/3/4/6 */
-			0x2	0x21	    /* VLAN2 Ports 0/5 */
-		>;
-	};
-
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-		qca,ar8327-initvals = <
-			0x000e4 0x6a545     /* MAC_POWER_SEL */
-			0x0000c 0x80        /* PAD6_MODE */
-			>;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	mtd-mac-address = <&art 6>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
+&partitions {
+	partition@1880000 {
+		label = "ubi";
+		reg = <0x1880000 0x6080000>;
 	};
-};
-
-&gmac2 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
 
-	mtd-mac-address = <&art 0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
+	partition@7900000 {
+		label = "reserve";
+		reg = <0x7900000 0x0700000>;
+		read-only;
 	};
 };
 
-&adm_dma {
-	status = "okay";
-};
-
-&sata_phy {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-	
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&usb3_1 {
-	status = "okay";
-	
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
+&wifi0 {
+	nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
+	nvmem-cell-names = "mac-address", "pre-calibration";
+	mac-address-increment = <(1)>;
 };
 
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			mtd-mac-address = <&art 6>;
-			mtd-mac-address-increment = <(1)>;
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			mtd-mac-address = <&art 6>;
-			mtd-mac-address-increment = <(2)>;
-		};
-	};
+&wifi1 {
+	nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
+	nvmem-cell-names = "mac-address", "pre-calibration";
+	mac-address-increment = <(2)>;
 };
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
index c30e3c2c7e51be..d58324d70dd621 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
@@ -1,13 +1,319 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
-#include "qcom-ipq8065-rt4230w.dtsi"
+#include "qcom-ipq8065.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
 	model = "Askey RT4230W REV6";
 	compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
+
+	memory@0 {
+		reg = <0x42000000 0x3e000000>;
+		device_type = "memory";
+	};
+
+	aliases {
+		led-boot = &ledctrl3;
+		led-failsafe = &ledctrl1;
+		led-running = &ledctrl2;
+		led-upgrade = &ledctrl3;
+	};
+
+	chosen {
+		bootargs = "rootfstype=squashfs noinitrd";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		ledctrl1: ledctrl1 {
+			label = "ledctrl1";
+			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
+		};
+
+		ledctrl2: ledctrl2 {
+			label = "ledctrl2";
+			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
+		};
+
+		ledctrl3: ledctrl3 {
+			label = "ledctrl3";
+			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&qcom_pinmux {
+	button_pins: button_pins {
+		mux {
+			pins = "gpio54", "gpio68";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	led_pins: led_pins {
+		mux {
+			pins = "gpio22", "gpio23", "gpio24";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	rgmii2_pins: rgmii2_pins {
+		mux {
+			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
+				"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
+			function = "rgmii2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		tx {
+			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
+			input-disable;
+		};
+	};
+};
+
+&nand_controller {
+	status = "okay";
+
+	pinctrl-0 = <&nand_pins>;
+	pinctrl-names = "default";
+
+	nand@0 {
+		reg = <0>;
+		compatible = "qcom,nandcs";
+
+		nand-ecc-strength = <4>;
+		nand-bus-width = <8>;
+		nand-ecc-step-size = <512>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x0000000 0x0040000>;
+				read-only;
+			};
+			partition@40000 {
+				label = "0:MIBIB";
+				reg = <0x0040000 0x0140000>;
+				read-only;
+			};
+			partition@180000 {
+				label = "0:SBL2";
+				reg = <0x0180000 0x0140000>;
+				read-only;
+			};
+			partition@2c0000 {
+				label = "0:SBL3";
+				reg = <0x02c0000 0x0280000>;
+				read-only;
+			};
+			partition@540000 {
+				label = "0:DDRCONFIG";
+				reg = <0x0540000 0x0120000>;
+				read-only;
+			};
+			partition@660000 {
+				label = "0:SSD";
+				reg = <0x0660000 0x0120000>;
+				read-only;
+			};
+			partition@780000 {
+				label = "0:TZ";
+				reg = <0x0780000 0x0280000>;
+				read-only;
+			};
+			partition@a00000 {
+				label = "0:RPM";
+				reg = <0x0a00000 0x0280000>;
+				read-only;
+			};
+			partition@c80000 {
+				label = "0:APPSBL";
+				reg = <0x0c80000 0x0500000>;
+				read-only;
+			};
+			partition@1180000 {
+				label = "0:APPSBLENV";
+				reg = <0x1180000 0x0080000>;
+			};
+			ART: partition@1200000 {
+				label = "0:ART";
+				reg = <0x1200000 0x0140000>;
+				read-only;
+			};
+			partition@1340000 {
+				label = "0:BOOTCONFIG";
+				reg = <0x1340000 0x0060000>;
+				read-only;
+			};
+			partition@13a0000 {
+				label = "0:SBL2_1";
+				reg = <0x13a0000 0x0140000>;
+				read-only;
+			};
+			partition@14e0000 {
+				label = "0:SBL3_1";
+				reg = <0x14e0000 0x0280000>;
+				read-only;
+			};
+			partition@1760000 {
+				label = "0:DDRCONFIG_1";
+				reg = <0x1760000 0x0120000>;
+				read-only;
+			};
+			partition@1880000 {
+				label = "0:SSD_1";
+				reg = <0x1880000 0x0120000>;
+				read-only;
+			};
+			partition@19a0000 {
+				label = "0:TZ_1";
+				reg = <0x19a0000 0x0280000>;
+				read-only;
+			};
+			partition@1c20000 {
+				label = "0:RPM_1";
+				reg = <0x1c20000 0x0280000>;
+				read-only;
+			};
+			partition@1ea0000 {
+				label = "0:BOOTCONFIG1";
+				reg = <0x1ea0000 0x0060000>;
+				read-only;
+			};
+			partition@1f00000 {
+				label = "0:APPSBL_1";
+				reg = <0x1f00000 0x0500000>;
+				read-only;
+			};
+			partition@2400000 {
+				label = "ubi";
+				reg = <0x2400000 0x1a000000>;
+			};
+		};
+	};
 };
 
-&ubi {
-	reg = <0x2400000 0x1a000000>;
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio0_pins>;
+	pinctrl-names = "default";
+
+	phy0: ethernet-phy@0 {
+		reg = <0x0>;
+		qca,ar8327-initvals = <
+			0x00004 0x7600000   /* PAD0_MODE */
+			0x00008 0x1000000   /* PAD5_MODE */
+			0x0000c 0x80        /* PAD6_MODE */
+			0x000e4 0xaa545     /* MAC_POWER_SEL */
+			0x000e0 0xc74164de  /* SGMII_CTRL */
+			0x0007c 0x4e        /* PORT0_STATUS */
+			0x00094 0x4e        /* PORT6_STATUS */
+			0x00050 0xcf02cf02  /* LED_CTRL_0 */
+			0x00054 0xc832c832  /* LED_CTRL_1 */
+			>;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	qcom,id = <0>;
+
+	nvmem-cells = <&macaddr_ART_0>;
+	nvmem-cell-names = "mac-address";
+
+	pinctrl-0 = <&rgmii2_pins>;
+	pinctrl-names = "default";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "sgmii";
+	qcom,id = <1>;
+
+	nvmem-cells = <&macaddr_ART_6>;
+	nvmem-cell-names = "mac-address";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&adm_dma {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+	reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&pcie0_pins>;
+	pinctrl-names = "default";
+};
+
+&pcie1 {
+	status = "okay";
+	reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&pcie1_pins>;
+	pinctrl-names = "default";
+	max-link-speed = <1>;
+};
+
+&ART {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_ART_0: macaddr@0 {
+		reg = <0x0 0x6>;
+	};
+
+	macaddr_ART_6: macaddr@6 {
+		reg = <0x6 0x6>;
+	};
 };
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev9.3.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev9.3.dts
deleted file mode 100644
index 2dd8c2291d879f..00000000000000
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev9.3.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-rt4230w.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Askey RT4230W REV9.3";
-	compatible = "askey,rt4230w-rev9.3", "qcom,ipq8065", "qcom,ipq8064";
-};
-
-&ubi {
-	reg = <0x2400000 0xdc00000>;
-};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w.dtsi
deleted file mode 100644
index 85890dec556ee7..00000000000000
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w.dtsi
+++ /dev/null
@@ -1,364 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
-	memory@0 {
-		reg = <0x42000000 0x3e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		led-boot = &ledctrl3;
-		led-failsafe = &ledctrl1;
-		led-running = &ledctrl2;
-		led-upgrade = &ledctrl3;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs noinitrd";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		ledctrl1: ledctrl1 {
-			label = "ledctrl1";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		ledctrl2: ledctrl2 {
-			label = "ledctrl2";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		ledctrl3: ledctrl3 {
-			label = "ledctrl3";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio54", "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio22", "gpio23", "gpio24";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	rgmii2_pins: rgmii2_pins {
-		mux {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
-				"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
-			function = "rgmii2";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		tx {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		cs {
-			pins = "gpio20";
-			drive-strength = <12>;
-		};
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi4: spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		m25p80@0 {
-			compatible = "everspin,mr25h256";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <40000000>;
-			reg = <0>;
-		};
-	};
-};
-
-&nand_controller {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot_pages_size = <0x1180000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0000000 0x0040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x0040000 0x0140000>;
-				read-only;
-			};
-			partition@180000 {
-				label = "0:SBL2";
-				reg = <0x0180000 0x0140000>;
-				read-only;
-			};
-			partition@2c0000 {
-				label = "0:SBL3";
-				reg = <0x02c0000 0x0280000>;
-				read-only;
-			};
-			partition@540000 {
-				label = "0:DDRCONFIG";
-				reg = <0x0540000 0x0120000>;
-				read-only;
-			};
-			partition@660000 {
-				label = "0:SSD";
-				reg = <0x0660000 0x0120000>;
-				read-only;
-			};
-			partition@780000 {
-				label = "0:TZ";
-				reg = <0x0780000 0x0280000>;
-				read-only;
-			};
-			partition@a00000 {
-				label = "0:RPM";
-				reg = <0x0a00000 0x0280000>;
-				read-only;
-			};
-			partition@c80000 {
-				label = "0:APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-			partition@1180000 {
-				label = "0:APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-			};
-			ART: partition@1200000 {
-				label = "0:ART";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-			};
-			partition@1340000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x1340000 0x0060000>;
-				read-only;
-			};
-			partition@13a0000 {
-				label = "0:SBL2_1";
-				reg = <0x13a0000 0x0140000>;
-				read-only;
-			};
-			partition@14e0000 {
-				label = "0:SBL3_1";
-				reg = <0x14e0000 0x0280000>;
-				read-only;
-			};
-			partition@1760000 {
-				label = "0:DDRCONFIG_1";
-				reg = <0x1760000 0x0120000>;
-				read-only;
-			};
-			partition@1880000 {
-				label = "0:SSD_1";
-				reg = <0x1880000 0x0120000>;
-				read-only;
-			};
-			partition@19a0000 {
-				label = "0:TZ_1";
-				reg = <0x19a0000 0x0280000>;
-				read-only;
-			};
-			partition@1c20000 {
-				label = "0:RPM_1";
-				reg = <0x1c20000 0x0280000>;
-				read-only;
-			};
-			partition@1ea0000 {
-				label = "0:BOOTCONFIG1";
-				reg = <0x1ea0000 0x0060000>;
-				read-only;
-			};
-			partition@1f00000 {
-				label = "0:APPSBL_1";
-				reg = <0x1f00000 0x0500000>;
-				read-only;
-			};
-			ubi: partition@2400000 {
-				label = "ubi";
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy0: ethernet-phy@0 {
-		reg = <0x0>;
-		qca,ar8327-initvals = <
-			0x00004 0x7600000   /* PAD0_MODE */
-			0x00008 0x1000000   /* PAD5_MODE */
-			0x0000c 0x80        /* PAD6_MODE */
-			0x000e4 0xaa545     /* MAC_POWER_SEL */
-			0x000e0 0xc74164de  /* SGMII_CTRL */
-			0x0007c 0x4e        /* PORT0_STATUS */
-			0x00094 0x4e        /* PORT6_STATUS */
-			0x00050 0xcf02cf02  /* LED_CTRL_0 */
-			0x00054 0xc832c832  /* LED_CTRL_1 */
-			>;
-	};
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37000000 0x200000>;
-	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <0>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	mtd-mac-address = <&ART 0x0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "sgmii";
-	qcom,id = <1>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	mtd-mac-address = <&ART 0x6>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-	clocks = <&gcc USB30_1_MASTER_CLK>;
-};
-
-&usb3_1 {
-	status = "okay";
-	clocks = <&gcc USB30_0_MASTER_CLK>;
-};
-
-&pcie0 {
-	status = "okay";
-	reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rac2v1a.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
similarity index 79%
rename from target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rac2v1a.dts
rename to target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
index 7895765357afeb..7567b1dec57f7c 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rac2v1a.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
@@ -4,8 +4,8 @@
 #include <dt-bindings/input/input.h>
 
 / {
-	model = "Arris RAC2V1A";
-	compatible = "arris,rac2v1a", "qcom,ipq8065", "qcom,ipq8064";
+	model = "Arris TR4400 v2";
+	compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
 
 	memory@0 {
 		reg = <0x42000000 0x1e000000>;
@@ -110,8 +110,6 @@
 
 		flash@0 {
 			compatible = "everspin,mr25h256";
-			#address-cells = <1>;
-			#size-cells = <1>;
 			spi-max-frequency = <40000000>;
 			reg = <0>;
 		};
@@ -190,6 +188,17 @@
 				label = "0:ART";
 				reg = <0x1200000 0x0140000>;
 				read-only;
+
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				precal_ART_1000: precal@1000 {
+					reg = <0x1000 0x2f20>;
+				};
+				precal_ART_5000: precal@5000 {
+					reg = <0x5000 0x2f20>;
+				};
 			};
 			partition@1340000 {
 				label = "rootfs_1";
@@ -248,6 +257,26 @@
 				label = "fw_env";
 				reg = <0xa400000 0x0100000>;
 				read-only;
+
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				macaddr_fw_env_0: macaddr@0 {
+					reg = <0x00 0x6>;
+				};
+				macaddr_fw_env_6: macaddr@6 {
+					reg = <0x06 0x6>;
+				};
+				macaddr_fw_env_c: macaddr@c {
+					reg = <0x0c 0x6>;
+				};
+				macaddr_fw_env_12: macaddr@12 {
+					reg = <0x12 0x6>;
+				};
+				macaddr_fw_env_18: macaddr@18 {
+					reg = <0x18 0x6>;
+				};
 			};
 			partition@a500000 {
 				label = "config";
@@ -274,7 +303,7 @@
 	pinctrl-0 = <&mdio0_pins>;
 	pinctrl-names = "default";
 
-	phy0: ethernet-phy@0 {
+	ethernet-phy@0 {
 		reg = <0x0>;
 		qca,ar8327-initvals = <
 			0x00004 0x7600000   /* PAD0_MODE */
@@ -287,10 +316,6 @@
 			>;
 	};
 
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-
 	phy7: ethernet-phy@7 {
 		reg = <7>;
 	};
@@ -300,13 +325,13 @@
 	status = "okay";
 	phy-mode = "rgmii";
 	qcom,id = <0>;
-	phy-handle = <&phy4>;
+
+	nvmem-cells = <&macaddr_fw_env_18>;
+	nvmem-cell-names = "mac-address";
 
 	pinctrl-0 = <&rgmii2_pins>;
 	pinctrl-names = "default";
 
-	mtd-mac-address = <&fw_env 0x18>;
-
 	fixed-link {
 		speed = <1000>;
 		full-duplex;
@@ -318,7 +343,8 @@
 	phy-mode = "sgmii";
 	qcom,id = <1>;
 
-	mtd-mac-address = <&fw_env 0x0>;
+	nvmem-cells = <&macaddr_fw_env_0>;
+	nvmem-cell-names = "mac-address";
 
 	fixed-link {
 		speed = <1000>;
@@ -332,21 +358,16 @@
 	qcom,id = <3>;
 	phy-handle = <&phy7>;
 
-	mtd-mac-address = <&fw_env 0x6>;
+	nvmem-cells = <&macaddr_fw_env_6>;
+	nvmem-cell-names = "mac-address";
 };
 
 &adm_dma {
 	status = "okay";
 };
 
-&usb3_0 {
-	status = "okay";
-	clocks = <&gcc USB30_1_MASTER_CLK>;
-};
-
 &usb3_1 {
 	status = "okay";
-	clocks = <&gcc USB30_0_MASTER_CLK>;
 };
 
 &pcie0 {
@@ -354,6 +375,21 @@
 	reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 	pinctrl-0 = <&pcie0_pins>;
 	pinctrl-names = "default";
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi0: wifi@1,0 {
+			compatible = "pci168c,0046";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
+			nvmem-cell-names = "pre-calibration", "mac-address";
+		};
+	};
 };
 
 &pcie1 {
@@ -362,4 +398,19 @@
 	pinctrl-0 = <&pcie1_pins>;
 	pinctrl-names = "default";
 	max-link-speed = <1>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi1: wifi@1,0 {
+			compatible = "pci168c,0040";
+			reg = <0x00010000 0 0 0 0>;
+
+			nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
+			nvmem-cell-names = "pre-calibration", "mac-address";
+		};
+	};
 };
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts
index 05c4c5fd4b5a14..f584735e155e9f 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts
@@ -1,461 +1,50 @@
-#include "qcom-ipq8065.dtsi"
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include <dt-bindings/input/input.h>
+#include "qcom-ipq8065-nighthawk.dtsi"
 
 / {
-	model = "Netgear Nighthawk Pro Gaming XR500";
+	model = "Netgear Nighthawk XR500";
 	compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064";
 
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		rsvd@5fe00000 {
-			reg = <0x5fe00000 0x200000>;
-			reusable;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &led_power_white;
-		led-failsafe = &led_power_amber;
-		led-running = &led_power_white;
-		led-upgrade = &led_power_amber;
-		label-mac-device = &gmac2;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power_white: power_white {
-			label = "white:power";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		led_power_amber: power_amber {
-			label = "amber:power";
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_white {
-			label = "white:wan";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_amber {
-			label = "amber:wan";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb1 {
-			label = "white:usb1";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb2 {
-			label = "white:usb2";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		wifi {
-			label = "white:wifi";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			label = "white:wps";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-	};
 };
 
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
+&leds {
+	usb1 {
+		label = "white:usb1";
+		gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
 	};
 
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
-				"gpio24","gpio26", "gpio53", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	mdio0_pins: mdio0_pins {
-		clk {
-			pins = "gpio1";
-			input-disable;
-		};
-	};
-
-	rgmii2_pins: rgmii2_pins {
-		tx {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	spi6_pins: spi6_pins {
-		mux {
-			pins = "gpio55", "gpio56", "gpio58";
-			function = "gsbi6";
-			bias-pull-down;
-		};
-
-		mosi {
-			pins = "gpio55";
-			drive-strength = <12>;
-		};
-
-		miso {
-			pins = "gpio56";
-			drive-strength = <14>;
-		};
-
-		cs {
-			pins = "gpio57";
-			drive-strength = <12>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio58";
-			drive-strength = <12>;
-		};
-
-		reset {
-			pins = "gpio33";
-			drive-strength = <10>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb0_pwr_en_pins: usb0_pwr_en_pins {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb1_pwr_en_pins: usb1_pwr_en_pins {
-		mux {
-			pins = "gpio16", "gpio68";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
+	usb2 {
+		label = "white:usb2";
+		gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
 	};
 };
 
-&nand_controller {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot_pages_size = <0x1180000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			qcadata@0 {
-				label = "qcadata";
-				reg = <0x0000000 0x0c80000>;
-				read-only;
-			};
-
-			APPSBL@c80000 {
-				label = "APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			APPSBLENV@1180000 {
-				label = "APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-				read-only;
-			};
-
-			art: art@1200000 {
-				label = "art";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-			};
-
-			artbak: art@1340000 {
-				label = "artbak";
-				reg = <0x1340000 0x0140000>;
-				read-only;
-			};
-
-			kernel@1480000 {
-				label = "kernel";
-				reg = <0x1480000 0x0400000>;
-			};
-
-			ubi@1880000 {
-				label = "ubi";
-				reg = <0x1880000 0xce00000>;
-			};
-
-			reserve@e680000 {
-				label = "reserve";
-				reg = <0xe680000 0x0780000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		qca,ar8327-initvals = <
-			0x00004 0x7600000   /* PAD0_MODE */
-			0x00008 0x1000000   /* PAD5_MODE */
-			0x0000c 0x80        /* PAD6_MODE */
-			0x000e4 0xaa545     /* MAC_POWER_SEL */
-			0x000e0 0xc74164de  /* SGMII_CTRL */
-			0x0007c 0x4e        /* PORT0_STATUS */
-			0x00094 0x4e        /* PORT6_STATUS */
-			0x00970 0x1e864443  /* QM_PORT0_CTRL0 */
-			0x00974 0x000001c6  /* QM_PORT0_CTRL1 */
-			0x00978 0x19008643  /* QM_PORT1_CTRL0 */
-			0x0097c 0x000001c6  /* QM_PORT1_CTRL1 */
-			0x00980 0x19008643  /* QM_PORT2_CTRL0 */
-			0x00984 0x000001c6  /* QM_PORT2_CTRL1 */
-			0x00988 0x19008643  /* QM_PORT3_CTRL0 */
-			0x0098c 0x000001c6  /* QM_PORT3_CTRL1 */
-			0x00990 0x19008643  /* QM_PORT4_CTRL0 */
-			0x00994 0x000001c6  /* QM_PORT4_CTRL1 */
-			0x00998 0x1e864443  /* QM_PORT5_CTRL0 */
-			0x0099c 0x000001c6  /* QM_PORT5_CTRL1 */
-			0x009a0 0x1e864443  /* QM_PORT6_CTRL0 */
-			0x009a4 0x000001c6  /* QM_PORT6_CTRL1 */
-			>;
-		qca,ar8327-vlans = <
-			0x1	0x5e	    /* VLAN1 Ports 1/2/3/4/6 */
-			0x2	0x21	    /* VLAN2 Ports 0/5 */
-		>;
-	};
-
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-		qca,ar8327-initvals = <
-			0x000e4 0x6a545     /* MAC_POWER_SEL */
-			0x0000c 0x80        /* PAD6_MODE */
-			>;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37200000 0x200000>;
-	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,pcs-chanid = <0>;
-	qcom,phy-mdio-addr = <4>;
-	qcom,poll-required = <0>;
-	qcom,rgmii-delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	mtd-mac-address = <&art 6>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
+&partitions {
+	partition@1880000 {
+		label = "ubi";
+		reg = <0x1880000 0xce00000>;
 	};
-};
-
-&gmac2 {
-	status = "okay";
-	compatible = "qcom,nss-gmac";
-	reg = <0x37400000 0x200000>;
-	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	qcom,pcs-chanid = <1>;
-	qcom,phy-mdio-addr = <0>;	/* none */
-	qcom,poll-required = <0>;	/* no polling */
-	qcom,rgmii-delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,forced-speed = <1000>;
-	qcom,forced-duplex = <1>;
-	qcom,socver = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	mtd-mac-address = <&art 0>;
 
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
+	partition@e680000 {
+		label = "reserve";
+		reg = <0xe680000 0x0780000>;
+		read-only;
 	};
 };
 
-&adm_dma {
-	status = "okay";
+&wifi0 {
+	nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
+	nvmem-cell-names = "mac-address", "pre-calibration";
 };
 
-&sata_phy {
-	status = "okay";
+&wifi1 {
+	nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
+	nvmem-cell-names = "mac-address", "pre-calibration";
 };
 
-&sata {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-	
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&usb3_1 {
-	status = "okay";
-	
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			mtd-mac-address = <&art 6>;
-			mtd-mac-address-increment = <(1)>;
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			mtd-mac-address = <&art 6>;
-			mtd-mac-address-increment = <(2)>;
-		};
+&art {
+	macaddr_art_c: macaddr@c {
+		reg = <0xc 0x6>;
 	};
 };
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
index bc9ec11e203a0e..c70a5cbaed5ff5 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -97,80 +97,71 @@
 
 	/delete-node/opp-1200000000;
 
+	/*
+	 * Voltage thresholds are <target min max>
+	 */
 	opp-384000000 {
-		opp-microvolt-speed0-pvs0-v0 = <926250 975000 1023750>;
-		opp-microvolt-speed0-pvs1-v0 = <902500 950000 997500>;
-		opp-microvolt-speed0-pvs2-v0 = <878750 925000 971250>;
-		opp-microvolt-speed0-pvs3-v0 = <855000 900000 945000>;
-		opp-microvolt-speed0-pvs4-v0 = <831250 875000 918750>;
-		opp-microvolt-speed0-pvs5-v0 = <783750 825000 866250>;
-		opp-microvolt-speed0-pvs6-v0 = <736250 775000 813750>;
+		opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
+		opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+		opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+		opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
+		opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
+		opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
 	};
 
 	opp-600000000 {
-		opp-microvolt-speed0-pvs0-v0 = <950000 1000000 1050000>;
-		opp-microvolt-speed0-pvs1-v0 = <926250 975000 1023750>;
-		opp-microvolt-speed0-pvs2-v0 = <902500 950000 997500>;
-		opp-microvolt-speed0-pvs3-v0 = <878750 925000 971250>;
-		opp-microvolt-speed0-pvs4-v0 = <855000 900000 945000>;
-		opp-microvolt-speed0-pvs5-v0 = <807500 850000 892500>;
-		opp-microvolt-speed0-pvs6-v0 = <760000 800000 840000>;
+		opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+		opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
+		opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
+		opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
+		opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
 	};
 
 	opp-800000000 {
-		opp-microvolt-speed0-pvs0-v0 = <997500 1050000 1102500>;
-		opp-microvolt-speed0-pvs1-v0 = <973750 1025000 1076250>;
-		opp-microvolt-speed0-pvs2-v0 = <950000 1000000 1050000>;
-		opp-microvolt-speed0-pvs3-v0 = <926250 975000 1023750>;
-		opp-microvolt-speed0-pvs4-v0 = <902500 950000 997500>;
-		opp-microvolt-speed0-pvs5-v0 = <855000 900000 945000>;
-		opp-microvolt-speed0-pvs6-v0 = <807500 850000 892500>;
+		opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+		opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+		opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
+		opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
+		opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
 	};
 
 	opp-1000000000 {
-		opp-microvolt-speed0-pvs0-v0 = <1045000 1100000 1155000>;
-		opp-microvolt-speed0-pvs1-v0 = <1021250 1075000 1128750>;
-		opp-microvolt-speed0-pvs2-v0 = <997500 1050000 1102500>;
-		opp-microvolt-speed0-pvs3-v0 = <973750 1025000 1076250>;
-		opp-microvolt-speed0-pvs4-v0 = <950000 1000000 1050000>;
-		opp-microvolt-speed0-pvs5-v0 = <902500 950000 997500>;
-		opp-microvolt-speed0-pvs6-v0 = <855000 900000 945000>;
+		opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+		opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
+		opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
+		opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
 	};
 
 	opp-1400000000 {
-		opp-microvolt-speed0-pvs0-v0 = <1116250 1175000 1233750>;
-		opp-microvolt-speed0-pvs1-v0 = <1092500 1150000 1207500>;
-		opp-microvolt-speed0-pvs2-v0 = <1068750 1125000 1181250>;
-		opp-microvolt-speed0-pvs3-v0 = <1045000 1100000 1155000>;
-		opp-microvolt-speed0-pvs4-v0 = <1021250 1075000 1128750>;
-		opp-microvolt-speed0-pvs5-v0 = <973750 1025000 1076250>;
-		opp-microvolt-speed0-pvs6-v0 = <926250 975000 1023750>;
+		opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
+		opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
+		opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+		opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
+		opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
+		opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
 		opp-level = <1>;
 	};
 
 	opp-1725000000 {
 		opp-hz = /bits/ 64 <1725000000>;
-		opp-microvolt-speed0-pvs0-v0 = <1199375 1262500 1325625>;
-		opp-microvolt-speed0-pvs1-v0 = <1163750 1225000 1286250>;
-		opp-microvolt-speed0-pvs2-v0 = <1140000 1200000 1260000>;
-		opp-microvolt-speed0-pvs3-v0 = <1116250 1175000 1233750>;
-		opp-microvolt-speed0-pvs4-v0 = <1092500 1150000 1207500>;
-		opp-microvolt-speed0-pvs5-v0 = <1045000 1100000 1155000>;
-		opp-microvolt-speed0-pvs6-v0 = <997500 1050000 1102500>;
+		opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
+		opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
+		opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
+		opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
+		opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
+		opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
 		opp-supported-hw = <0x1>;
 		clock-latency-ns = <100000>;
 		opp-level = <2>;
 	};
 };
-
-&nss0 {
-	qcom,low-frequency = <800000000>;
-	qcom,mid-frequency = <800000000>;
-	qcom,max-frequency = <800000000>;
-};
-
-&nss1 {
-	qcom,low-frequency = <800000000>;
-	qcom,mid-frequency = <800000000>;
-	qcom,max-frequency = <800000000>;
-};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi
new file mode 100644
index 00000000000000..10ab4821e8c6e6
--- /dev/null
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+
+#include "qcom-ipq8064-v2.0.dtsi"
+
+/ {
+	memory {
+		device_type = "memory";
+		linux,usable-memory = <0x41500000 0x1ea00000>;
+		reg = <0x40000000 0x20000000>;
+	};
+
+	cpus {
+		idle-states {
+			CPU_SPC: spc {
+				status = "disabled";
+			};
+		};
+	};
+
+	chosen {
+		bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art";
+	};
+};
+
+&qcom_pinmux {
+	mdio0_pins_active: mdio0_pins_active {
+		mux {
+			pins = "gpio0", "gpio1";
+			function = "mdio";
+			drive-strength = <2>;
+			bias-pull-down;
+			output-low;
+		};
+
+		clk {
+			pins = "gpio1";
+			input-disable;
+		};
+	};
+
+	phy_active: phy_active {
+		phy {
+			pins = "gpio6", "gpio7";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+			output-high;
+		};
+	};
+
+	uart1_pins: uart1_pins {
+		mux {
+			pins = "gpio51", "gpio52";
+			function = "gsbi1";
+			drive-strength = <4>;
+			bias-disable;
+		};
+	};
+};
+
+&gsbi1 {
+	status = "okay";
+	qcom,mode = <GSBI_PROT_UART_W_FC>;
+
+	serial@12450000 {
+		status = "okay";
+
+		pinctrl-0 = <&uart1_pins>;
+		pinctrl-names = "default";
+	};
+};
+
+&pcie0 {
+	status = "okay";
+
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	/delete-property/ perst-gpios;
+
+	bridge@0,0 {
+		reg = <0x0 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi0: wifi@1,0 {
+			compatible = "qcom,ath10k";
+			status = "okay";
+			reg = <0x10000 0 0 0 0>;
+		};
+	};
+};
+
+&pcie1 {
+	status = "okay";
+
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	/delete-property/ perst-gpios;
+
+	bridge@0,0 {
+		reg = <0x0 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi1: wifi@1,0 {
+			compatible = "qcom,ath10k";
+			status = "okay";
+			reg = <0x10000 0 0 0 0>;
+		};
+	};
+};
+
+&pcie2 {
+	status = "okay";
+
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	/delete-property/ perst-gpios;
+
+	bridge@0,0 {
+		reg = <0x0 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi2: wifi@1,0 {
+			compatible = "qcom,ath10k";
+			status = "okay";
+			reg = <0x10000 0 0 0 0>;
+		};
+	};
+};
+
+&adm_dma {
+	status = "okay";
+};
+
+&nand_controller {
+	status = "okay";
+
+	pinctrl-0 = <&nand_pins>;
+	pinctrl-names = "default";
+
+	nand@0 {
+		compatible = "qcom,nandcs";
+
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-bus-width = <8>;
+		nand-ecc-step-size = <512>;
+
+		nand-is-boot-medium;
+		qcom,boot_pages_size = <0x2140000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "sbl1";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "mibib";
+				reg = <0x40000 0x140000>;
+				read-only;
+			};
+
+			partition@180000 {
+				label = "sbl2";
+				reg = <0x180000 0x140000>;
+				read-only;
+			};
+
+			partition@2c0000 {
+				label = "sbl3";
+				reg = <0x2c0000 0x280000>;
+				read-only;
+			};
+
+			partition@540000 {
+				label = "ddrconfig";
+				reg = <0x540000 0x120000>;
+				read-only;
+			};
+
+			partition@660000 {
+				label = "ssd";
+				reg = <0x660000 0x120000>;
+				read-only;
+			};
+
+			partition@780000 {
+				label = "tz";
+				reg = <0x780000 0x280000>;
+				read-only;
+			};
+
+			partition@a00000 {
+				label = "rpm";
+				reg = <0xa00000 0x280000>;
+				read-only;
+			};
+
+			partition@1fc0000 {
+				label = "u-boot";
+				reg = <0x1fc0000 0x180000>;
+				read-only;
+			};
+
+			partition@21c0000 {
+				label = "bootkernel1";
+				reg = <0x21c0000 0xa80000>;
+			};
+
+			partition@2c40000 {
+				label = "bootkernel2";
+				reg = <0x2c40000 0xa80000>;
+			};
+
+			partition@36c0000 {
+				label = "ubi";
+				reg = <0x36c0000 0x46c0000>;
+			};
+
+			partition@7d80000 {
+				label = "art";
+				reg = <0x7d80000 0x200000>;
+				read-only;
+			};
+		};
+	};
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
index 43bed451cbfb08..377bb09616c885 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
@@ -34,9 +34,8 @@
 
 	aliases {
 		serial1 = &gsbi1_serial;
-		mdio-gpio0 = &mdio0;
-		ethernet0 = &gmac3;
-		ethernet1 = &gmac2;
+		ethernet0 = &gmac2;
+		ethernet1 = &gmac3;
 
 		led-boot = &led_power_green;
 		led-failsafe = &led_power_red;
@@ -293,26 +292,18 @@
 	};
 };
 
-&soc {
-	mdio1: mdio {
-		compatible = "virtual,mdio-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		status = "okay";
-
-		pinctrl-0 = <&mdio0_pins>;
-		pinctrl-names = "default";
+&mdio0 {
+	status = "okay";
 
-		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&mdio0_pins>;
+	pinctrl-names = "default";
 
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-		};
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
 
-		phy1: ethernet-phy@1 {
-			reg = <1>;
-		};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
 	};
 };
 
@@ -330,7 +321,7 @@
 	status = "okay";
 
 	qcom,id = <3>;
-	mdiobus = <&mdio1>;
+	mdiobus = <&mdio0>;
 
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
new file mode 100644
index 00000000000000..ccf2554ca319fa
--- /dev/null
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+
+#include "qcom-ipq8068-cryptid-common.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Meraki MR42";
+	compatible = "meraki,mr42", "qcom,ipq8064";
+
+	aliases {
+		serial1 = &gsbi1_serial;
+		ethernet0 = &gmac3;
+
+		led-boot = &led_active;
+		led-failsafe = &led_power;
+		led-running = &led_active;
+		led-upgrade = &led_active;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		led_power: power {
+			label = "orange:power";
+			gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_active: active {
+			label = "white:active";
+			gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&gmac3 {
+	status = "okay";
+
+	qcom,id = <3>;
+	mdiobus = <&mdio0>;
+
+	phy-mode = "sgmii";
+	phy-handle = <&phy2>;
+
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gsbi2 {
+	status = "okay";
+	qcom,mode = <GSBI_PROT_I2C>;
+};
+
+&gsbi2_i2c {
+	status = "okay";
+
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+
+	ina2xx@40 {
+		compatible = "ina219";
+		shunt-resistor = <40000>;
+		reg = <0x40>;
+	};
+
+	eeprom@56 {
+		compatible = "atmel,24c64";
+		pagesize = <32>;
+		reg = <0x56>;
+		read-only;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mac_address: mac-address@66 {
+			reg = <0x66 0x6>;
+		};
+	};
+};
+
+&gsbi6 {
+	qcom,mode = <GSBI_PROT_I2C>;
+	status = "okay";
+};
+
+&gsbi6_i2c {
+	status = "okay";
+
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+
+	tlc591xx@40 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "ti,tlc59108";
+		reg = <0x40>;
+
+		red@0 {
+			label = "red:user";
+			reg = <0x0>;
+		};
+
+		green@1 {
+			label = "green:user";
+			reg = <0x1>;
+		};
+
+		blue@2 {
+			label = "blue:user";
+			reg = <0x2>;
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
+	pinctrl-names = "default";
+
+	phy2: ethernet-phy2 {
+		reg = <2>;
+
+		reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <24000>;
+
+		eee-broken-100tx;
+		eee-broken-1000t;
+	};
+};
+
+&qcom_pinmux {
+	i2c0_pins: i2c0_pins {
+		mux {
+			pins = "gpio24", "gpio25";
+			function = "gsbi2";
+			drive-strength = <2>;
+			bias-pull-up;
+			input;
+		};
+	};
+
+	button_pins: button_pins {
+		mux {
+			pins = "gpio26";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	i2c1_pins: i2c1_pins {
+		mux {
+			pins = "gpio29", "gpio30";
+			function = "gsbi6";
+			drive-strength = <2>;
+			bias-pull-up;
+			input;
+		};
+	};
+
+	led_pins: led_pins {
+		mux {
+			pins = "gpio31", "gpio32";
+			function = "gpio";
+			drive-strength = <12>;
+			bias-pull-down;
+			output-low;
+		};
+	};
+};
+
+&wifi0 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <1>;
+};
+
+&wifi1 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <2>;
+};
+
+&wifi2 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <3>;
+};
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
new file mode 100644
index 00000000000000..e1c233254d25dd
--- /dev/null
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+
+#include "qcom-ipq8068-cryptid-common.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Meraki MR52";
+	compatible = "meraki,mr52", "qcom,ipq8064";
+
+	aliases {
+		serial1 = &gsbi1_serial;
+		mdio-gpio0 = &mdio_gpio0;
+		ethernet0 = &gmac2;
+		ethernet1 = &gmac3;
+
+		led-boot = &led_active;
+		led-failsafe = &led_power;
+		led-running = &led_active;
+		led-upgrade = &led_active;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		led_power: power {
+			label = "orange:power";
+			gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		lan2_green {
+			label = "green:lan2";
+			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
+		};
+
+		lan1_green {
+			label = "green:lan1";
+			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_active: active {
+			label = "white:active";
+			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
+		};
+
+		lan2_orange {
+			label = "orange:lan2";
+			gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
+		};
+
+		lan1_orange {
+			label = "orange:lan1";
+			gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&gmac2 {
+	status = "okay";
+
+	qcom,id = <2>;
+	mdiobus = <&mdio0>;
+
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gmac3 {
+	status = "okay";
+
+	qcom,id = <3>;
+	mdiobus = <&mdio_gpio0>;
+
+	phy-mode = "sgmii";
+	phy-handle = <&phy4>;
+
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <1>;
+};
+
+&gsbi7 {
+	status = "okay";
+	qcom,mode = <GSBI_PROT_I2C>;
+};
+
+&gsbi7_i2c {
+	status = "okay";
+
+	pinctrl-0 = <&i2c_pins>;
+	pinctrl-names = "default";
+
+	ina2xx@45 {
+		compatible = "ina219";
+		shunt-resistor = <80000>;
+		reg = <0x45>;
+	};
+
+	tlc591xx@49 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "ti,tlc59108";
+		reg = <0x49>;
+
+		red@0 {
+			label = "red:user";
+			reg = <0x0>;
+		};
+
+		green@1 {
+			label = "green:user";
+			reg = <0x1>;
+		};
+
+		blue@2 {
+			label = "blue:user";
+			reg = <0x2>;
+		};
+	};
+
+	eeprom@52 {
+		compatible = "atmel,24c64";
+		pagesize = <32>;
+		reg = <0x52>;
+		read-only;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mac_address: mac-address@66 {
+			reg = <0x66 0x6>;
+		};
+	};
+};
+
+&qcom_pinmux {
+	i2c_pins: i2c_pins {
+		mux {
+			pins = "gpio8", "gpio9";
+			function = "gsbi7";
+			drive-strength = <2>;
+			bias-pull-up;
+			input;
+		};
+	};
+
+	led_pins: led_pins {
+		mux {
+			pins = "gpio19", "gpio26";
+			function = "gpio";
+			drive-strength = <12>;
+			bias-pull-down;
+			output-low;
+		};
+	};
+
+	button_pins: button_pins {
+		mux {
+			pins = "gpio25";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+			input;
+		};
+	};
+};
+
+&soc {
+	mdio_gpio0: mdio {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "okay";
+
+		pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
+		pinctrl-names = "default";
+
+		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH
+			 &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
+
+		phy0: ethernet-phy0 {
+			reg = <0>;
+			reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <24000>;
+		};
+
+		phy4: ethernet-phy4 {
+			reg = <4>;
+			reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <24000>;
+		};
+	};
+};
+
+&wifi0 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <4>;
+};
+
+&wifi1 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <3>;
+};
+
+&wifi2 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+	mac-address-increment = <2>;
+};
diff --git a/target/linux/ipq806x/files/include/linux/regulator/nss-volt-ipq806x.h b/target/linux/ipq806x/files/include/linux/regulator/nss-volt-ipq806x.h
deleted file mode 100644
index 648160f06c6acc..00000000000000
--- a/target/linux/ipq806x/files/include/linux/regulator/nss-volt-ipq806x.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef __QCOM_NSS_VOL_SCALING_H
-#define __QCOM_NSS_VOL_SCALING_H
-
-#include <linux/regulator/consumer.h>
-
-int nss_ramp_voltage(unsigned long rate, bool ramp_up);
-
-#endif
diff --git a/target/linux/ipq806x/files/include/net/netfilter/nf_conntrack_dscpremark_ext.h b/target/linux/ipq806x/files/include/net/netfilter/nf_conntrack_dscpremark_ext.h
deleted file mode 100644
index f37e1ac84c1c35..00000000000000
--- a/target/linux/ipq806x/files/include/net/netfilter/nf_conntrack_dscpremark_ext.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- **************************************************************************
- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all copies.
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- **************************************************************************
- */
-
-/* DSCP remark conntrack extension APIs. */
-
-#ifndef _NF_CONNTRACK_DSCPREMARK_H
-#define _NF_CONNTRACK_DSCPREMARK_H
-#include <net/netfilter/nf_conntrack.h>
-#include <net/netfilter/nf_conntrack_extend.h>
-
-/* Rule flags */
-#define NF_CT_DSCPREMARK_EXT_DSCP_RULE_VALID 0x1
-
-/* Rule validity */
-#define NF_CT_DSCPREMARK_EXT_RULE_VALID 0x1
-#define NF_CT_DSCPREMARK_EXT_RULE_NOT_VALID 0x0
-
-/*
- * DSCP remark conntrack extension structure.
- */
-struct nf_ct_dscpremark_ext {
-	__u32 flow_priority;	/* Original direction packet priority */
-	__u32 reply_priority;	/* Reply direction packet priority */
-	__u16 igs_flow_qos_tag;	/* Original direction ingress packet priority */
-	__u16 igs_reply_qos_tag;	/* Reply direction ingress packet priority */
-	__u8 flow_dscp;		/* IP DSCP value for original direction */
-	__u8 reply_dscp;	/* IP DSCP value for reply direction */
-	__u16 rule_flags;	/* Rule Validity flags */
-};
-
-/*
- * nf_ct_dscpremark_ext_find()
- *	Finds the extension data of the conntrack entry if it exists.
- */
-static inline struct nf_ct_dscpremark_ext *
-nf_ct_dscpremark_ext_find(const struct nf_conn *ct)
-{
-#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
-	return nf_ct_ext_find(ct, NF_CT_EXT_DSCPREMARK);
-#else
-	return NULL;
-#endif
-}
-
-/*
- * nf_ct_dscpremark_ext_add()
- *	Adds the extension data to the conntrack entry.
- */
-static inline
-struct nf_ct_dscpremark_ext *nf_ct_dscpremark_ext_add(struct nf_conn *ct,
-						      gfp_t gfp)
-{
-#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
-	struct nf_ct_dscpremark_ext *ncde;
-
-	ncde = nf_ct_ext_add(ct, NF_CT_EXT_DSCPREMARK, gfp);
-	if (!ncde)
-		return NULL;
-
-	return ncde;
-#else
-	return NULL;
-#endif
-};
-
-#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
-extern int nf_conntrack_dscpremark_ext_init(void);
-extern void nf_conntrack_dscpremark_ext_fini(void);
-extern int nf_conntrack_dscpremark_ext_set_dscp_rule_valid(struct nf_conn *ct);
-extern int
-nf_conntrack_dscpremark_ext_get_dscp_rule_validity(struct nf_conn *ct);
-#else
-/*
- * nf_conntrack_dscpremark_ext_init()
- */
-static inline int nf_conntrack_dscpremark_ext_init(void)
-{
-	return 0;
-}
-
-/*
- * nf_conntrack_dscpremark_ext_fini()
- */
-static inline void nf_conntrack_dscpremark_ext_fini(void)
-{
-}
-#endif /* CONFIG_NF_CONNTRACK_DSCPREMARK_EXT */
-#endif /* _NF_CONNTRACK_DSCPREMARK_H */
diff --git a/target/linux/ipq806x/files/include/uapi/linux/tc_act/tc_nss_mirred.h b/target/linux/ipq806x/files/include/uapi/linux/tc_act/tc_nss_mirred.h
deleted file mode 100644
index 3a368fcc8c17ee..00000000000000
--- a/target/linux/ipq806x/files/include/uapi/linux/tc_act/tc_nss_mirred.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef __LINUX_TC_NSS_MIRRED_H
-#define __LINUX_TC_NSS_MIRRED_H
-
-#include <linux/pkt_cls.h>
-
-/*
- * Type of nss mirred action.
- */
-#define TCA_ACT_MIRRED_NSS 17
-
-/*
- * Types of parameters for nss mirred action.
- */
-enum {
-	TC_NSS_MIRRED_UNSPEC,
-	TC_NSS_MIRRED_TM,
-	TC_NSS_MIRRED_PARMS,
-	__TC_NSS_MIRRED_MAX
-};
-#define TC_NSS_MIRRED_MAX (__TC_NSS_MIRRED_MAX - 1)
-
-/*
- * tc_nss_mirred
- *	tc command structure for nss mirred action.
- */
-struct tc_nss_mirred {
-	tc_gen;			/* General tc structure. */
-	__u32 from_ifindex;	/* ifindex of the port from which traffic
-				 * will be redirected.
-				 */
-	__u32 to_ifindex;	/* ifindex of the port to which traffic
-				 * will be redirected.
-				 */
-};
-
-#endif	/* __LINUX_TC_NSS_MIRRED_H */
diff --git a/target/linux/ipq806x/files/net/netfilter/nf_conntrack_dscpremark_ext.c b/target/linux/ipq806x/files/net/netfilter/nf_conntrack_dscpremark_ext.c
deleted file mode 100644
index ded6d0290eea27..00000000000000
--- a/target/linux/ipq806x/files/net/netfilter/nf_conntrack_dscpremark_ext.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- **************************************************************************
- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all copies.
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
- * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- **************************************************************************
- */
-
-/* DSCP remark handling conntrack extension registration. */
-
-#include <linux/netfilter.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/moduleparam.h>
-#include <linux/export.h>
-
-#include <net/netfilter/nf_conntrack.h>
-#include <net/netfilter/nf_conntrack_extend.h>
-#include <net/netfilter/nf_conntrack_dscpremark_ext.h>
-
-/* DSCP remark conntrack extension type declaration */
-static struct nf_ct_ext_type dscpremark_extend __read_mostly = {
-	.len = sizeof(struct nf_ct_dscpremark_ext),
-	.align = __alignof__(struct nf_ct_dscpremark_ext),
-	.id = NF_CT_EXT_DSCPREMARK,
-};
-
-/* nf_conntrack_dscpremark_ext_init()
- *	Initializes the DSCP remark conntrack extension.
- */
-int nf_conntrack_dscpremark_ext_init(void)
-{
-	int ret;
-
-	ret = nf_ct_extend_register(&dscpremark_extend);
-	if (ret < 0) {
-		pr_warn("nf_conntrack_dscpremark: Unable to register extension\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-/* nf_conntrack_dscpremark_ext_set_dscp_rule_valid()
- *	Set DSCP rule validity flag in the extension
- */
-int nf_conntrack_dscpremark_ext_set_dscp_rule_valid(struct nf_conn *ct)
-{
-	struct nf_ct_dscpremark_ext *ncde;
-
-	ncde = nf_ct_dscpremark_ext_find(ct);
-	if (!ncde)
-		return -1;
-
-	ncde->rule_flags = NF_CT_DSCPREMARK_EXT_DSCP_RULE_VALID;
-	return 0;
-}
-EXPORT_SYMBOL(nf_conntrack_dscpremark_ext_set_dscp_rule_valid);
-
-/* nf_conntrack_dscpremark_ext_get_dscp_rule_validity()
- *	Check if the DSCP rule flag is valid from the extension
- */
-int nf_conntrack_dscpremark_ext_get_dscp_rule_validity(struct nf_conn *ct)
-{
-	struct nf_ct_dscpremark_ext *ncde;
-
-	ncde = nf_ct_dscpremark_ext_find(ct);
-	if (!ncde)
-		return NF_CT_DSCPREMARK_EXT_RULE_NOT_VALID;
-
-	if (ncde->rule_flags & NF_CT_DSCPREMARK_EXT_DSCP_RULE_VALID)
-		return NF_CT_DSCPREMARK_EXT_RULE_VALID;
-
-	return NF_CT_DSCPREMARK_EXT_RULE_NOT_VALID;
-}
-EXPORT_SYMBOL(nf_conntrack_dscpremark_ext_get_dscp_rule_validity);
-
-/* nf_conntrack_dscpremark_ext_fini()
- *	De-initializes the DSCP remark conntrack extension.
- */
-void nf_conntrack_dscpremark_ext_fini(void)
-{
-	nf_ct_extend_unregister(&dscpremark_extend);
-}
diff --git a/target/linux/ipq806x/image/Makefile b/target/linux/ipq806x/image/Makefile
index 12f49a3d56891c..f4f829b35c65fd 100644
--- a/target/linux/ipq806x/image/Makefile
+++ b/target/linux/ipq806x/image/Makefile
@@ -3,37 +3,6 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/image.mk
 
-DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
-DEVICE_VARS += TPLINK_BOARD_ID
-
-define Build/buffalo-rootfs-cksum
-	( \
-		echo -ne "\x$$(od -A n -t u1 $@ | tr -s ' ' '\n' | \
-			$(STAGING_DIR_HOST)/bin/awk '{s+=$$0}END{printf "%x", 255-s%256}')"; \
-	) >> $@
-endef
-
-define Build/edimax-header
-	$(eval edimax_model=$(word 1,$(1)))
-
-	$(STAGING_DIR_HOST)/bin/mkedimaximg \
-	-b -s CSYS -m $(edimax_model) \
-	-f 0x70000 -S 0x1200000 \
-	-i $@ -o $@.new
-	@mv $@.new $@
-endef
-
-# tune addpattern for Linksys E8350-V1 fw pattern generation
-define Build/linksys-bin
-        $(STAGING_DIR_HOST)/bin/addpattern -p $(FW_DEVICE_ID) -v $(FW_VERSION) $(if $(SERIAL),-s $(SERIAL)) -i $@ -o $@.new
-        mv $@.new $@
-endef
-# Use Linksys fw header generator to upgrade openwrt factory image over the native Linksys WEB interface
-define Build/linksys-addfwhdr
-        -$(STAGING_DIR_HOST)/bin/addfwhdr -i $@ -o $@.new \
-       	;mv "$@.new" "$@"
-endef
-
 define Device/Default
 	PROFILES := Default
 	KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
@@ -70,470 +39,6 @@ define Device/UbiFit
 	IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 
-define Device/DniImage
-	KERNEL_SUFFIX := -uImage
-	KERNEL = kernel-bin | append-dtb | uImage none
-	KERNEL_NAME := zImage
-	NETGEAR_BOARD_ID :=
-	NETGEAR_HW_ID :=
-	UBINIZE_OPTS := -E 5
-	IMAGES += factory.img
-	IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-ubi | netgear-dni
-	IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | append-metadata
-endef
-
-define Device/TpSafeImage
-	KERNEL_SUFFIX := -uImage
-	KERNEL = kernel-bin | append-dtb | uImage none
-	KERNEL_NAME := zImage
-	TPLINK_BOARD_ID :=
-	IMAGES += factory.bin
-	IMAGE/factory.bin := append-rootfs | tplink-safeloader factory
-	IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | append-metadata
-endef
-
-define Device/ZyXELImage
-	KERNEL_SUFFIX := -uImage
-	KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE)
-	KERNEL_NAME := zImage
-	IMAGES += factory.bin
-	IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to $$$$(BLOCKSIZE) | zyxel-ras-image separate-kernel
-	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata
-endef
-
-define Device/arris_rac2v1a
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := Arris
-	DEVICE_MODEL := RAC2V1A
-	DEVICE_ALT0_VENDOR := Arris
-	DEVICE_ALT0_MODEL := TR4400-AC
-	SOC := qcom-ipq8065
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	KERNEL_IN_UBI := 1
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += arris_rac2v1a
-
-define Device/askey_rt4230w
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := Askey
-	DEVICE_MODEL := RT4230W
-	SOC := qcom-ipq8065
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	KERNEL_IN_UBI := 1
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
-endef
-
-define Device/askey_rt4230w-rev6
-	$(call Device/askey_rt4230w)
-	DEVICE_VARIANT := REV6
-endef
-TARGET_DEVICES += askey_rt4230w-rev6
-
-define Device/askey_rt4230w-rev9.3
-	$(call Device/askey_rt4230w)
-	DEVICE_VARIANT := REV9.3
-endef
-TARGET_DEVICES += askey_rt4230w-rev9.3
-
-define Device/asrock_g10
-	$(call Device/FitImage)
-	$(call Device/UbiFit)
-	SOC := qcom-ipq8064
-	DEVICE_VENDOR := ASRock
-	DEVICE_MODEL := G10
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	KERNEL_SIZE := 5332k
-	DEVICE_PACKAGES := kmod-i2c-gpio ath10k-firmware-qca99x0-ct
-	IMAGE/nand-factory.bin := append-ubi | edimax-header RN67
-endef
-TARGET_DEVICES += asrock_g10
-
-define Device/buffalo_wxr-2533dhp
-	$(call Device/LegacyImage)
-	SOC := qcom-ipq8064
-	DEVICE_VENDOR := Buffalo
-	DEVICE_MODEL := WXR-2533DHP
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	IMAGE_SIZE := 65536k
-	KERNEL_IN_UBI := 1
-	IMAGE/sysupgrade.bin := append-rootfs | buffalo-rootfs-cksum | \
-		sysupgrade-tar rootfs=$$$$@ | append-metadata
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += buffalo_wxr-2533dhp
-
-define Device/compex_wpq864
-	$(call Device/FitImage)
-	$(call Device/UbiFit)
-	DEVICE_VENDOR := Compex
-	DEVICE_MODEL := WPQ864
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	SOC := qcom-ipq8064
-	DEVICE_PACKAGES := kmod-gpio-beeper
-endef
-TARGET_DEVICES += compex_wpq864
-
-define Device/edgecore_ecw5410
-	$(call Device/FitImage)
-	$(call Device/UbiFit)
-	DEVICE_VENDOR := Edgecore
-	DEVICE_MODEL := ECW5410
-	SOC := qcom-ipq8068
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	DEVICE_DTS_CONFIG := config@v2.0-ap160
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ipq-wifi-edgecore_ecw5410
-endef
-TARGET_DEVICES += edgecore_ecw5410
-
-define Device/linksys_ea7500-v1
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := Linksys
-	DEVICE_MODEL := EA7500
-	DEVICE_VARIANT := v1
-	SOC := qcom-ipq8064
-	PAGESIZE := 2048
-	BLOCKSIZE := 128k
-	KERNEL_SIZE := 3072k
-	KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem
-	UBINIZE_OPTS := -E 5
-	IMAGES := factory.bin sysupgrade.bin
-	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | pad-to $$$$(PAGESIZE)
-	DEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers ath10k-firmware-qca99x0-ct luci-app-advanced-reboot
-endef
-TARGET_DEVICES += linksys_ea7500-v1
-
-define Device/linksys_e8350-v1
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := Linksys
-	DEVICE_MODEL := E8350
-	DEVICE_VARIANT := v1
-	SOC := qcom-ipq8064
-	FW_VERSION := v1.0.03.003
-	FW_DEVICE_ID := 8350
-	PAGESIZE := 2048
-	BLOCKSIZE := 128k
-	KERNEL_IN_UBI := 1
-	IMAGES = factory.bin sysupgrade.ubi
-	IMAGE/sysupgrade.ubi := append-ubi | check-size 0x08000000 | append-metadata
-	IMAGE/factory.bin := append-ubi | check-size 0x08000000 | linksys-addfwhdr | linksys-bin
-	DEVICE_PACKAGES := ath10k-firmware-qca988x-ct qtn-utils qtn-firmware qtn-proto kmod-qtn-pcie2
-endef
-TARGET_DEVICES += linksys_e8350-v1
-
-define Device/linksys_ea8500
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := Linksys
-	DEVICE_MODEL := EA8500
-	SOC := qcom-ipq8064
-	PAGESIZE := 2048
-	BLOCKSIZE := 128k
-	KERNEL_SIZE := 3072k
-	KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem
-	BOARD_NAME := ea8500
-	SUPPORTED_DEVICES += ea8500
-	UBINIZE_OPTS := -E 5
-	IMAGES += factory.bin
-	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct luci-app-advanced-reboot
-endef
-TARGET_DEVICES += linksys_ea8500
-
-define Device/nec_wg2600hp
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := NEC
-	DEVICE_MODEL := Aterm WG2600HP
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 64k
-	BOARD_NAME := wg2600hp
-	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += nec_wg2600hp
-
-define Device/nec_wg2600hp3
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := NEC Platforms
-	DEVICE_MODEL := Aterm WG2600HP3
-	SOC := qcom-ipq8062
-	BLOCKSIZE := 64k
-	IMAGES := sysupgrade.bin
-	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
-	DEVICE_PACKAGES := -kmod-ata-ahci -kmod-ata-ahci-platform -kmod-usb-ohci -kmod-usb2 \
-		-kmod-usb-ledtrig-usbport -kmod-usb-phy-qcom-dwc3 -kmod-usb3 -kmod-usb-dwc3-qcom \
-		ath10k-firmware-qca9984-ct ipq-wifi-nec_wg2600hp3
-endef
-TARGET_DEVICES += nec_wg2600hp3
-
-define Device/netgear_d7800
-	$(call Device/DniImage)
-	DEVICE_VENDOR := NETGEAR
-	DEVICE_MODEL := Nighthawk X4 D7800
-	SOC := qcom-ipq8064
-	KERNEL_SIZE := 4096k
-	NETGEAR_BOARD_ID := D7800
-	NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := d7800
-	SUPPORTED_DEVICES += d7800
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += netgear_d7800
-
-define Device/netgear_r7500
-	$(call Device/DniImage)
-	DEVICE_VENDOR := NETGEAR
-	DEVICE_MODEL := Nighthawk X4 R7500
-	DEVICE_VARIANT := v1
-	SOC := qcom-ipq8064
-	KERNEL_SIZE := 4096k
-	NETGEAR_BOARD_ID := R7500
-	NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := r7500
-	SUPPORTED_DEVICES += r7500
-	DEVICE_PACKAGES := ath10k-firmware-qca988x-ct qtn-utils qtn-firmware qtn-proto kmod-qtn-pcie2
-endef
-TARGET_DEVICES += netgear_r7500
-
-define Device/netgear_r7500v2
-	$(call Device/DniImage)
-	DEVICE_VENDOR := NETGEAR
-	DEVICE_MODEL := Nighthawk X4 R7500
-	DEVICE_VARIANT := v2
-	SOC := qcom-ipq8064
-	KERNEL_SIZE := 4096k
-	NETGEAR_BOARD_ID := R7500v2
-	NETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := r7500v2
-	SUPPORTED_DEVICES += r7500v2
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct ath10k-firmware-qca988x-ct
-endef
-TARGET_DEVICES += netgear_r7500v2
-
-define Device/netgear_r7800
-	$(call Device/DniImage)
-	DEVICE_VENDOR := NETGEAR
-	DEVICE_MODEL := Nighthawk X4S R7800
-	SOC := qcom-ipq8065
-	KERNEL_SIZE := 4096k
-	NETGEAR_BOARD_ID := R7800
-	NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := r7800
-	SUPPORTED_DEVICES += r7800
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
-endef
-TARGET_DEVICES += netgear_r7800
-
-define Device/netgear_xr500
-	$(call Device/DniImage)
-	DEVICE_VENDOR := NETGEAR
-	DEVICE_MODEL := Nighthawk Pro Gaming XR500
-	SOC := qcom-ipq8065
-	KERNEL_SIZE := 4096k
-	NETGEAR_BOARD_ID := XR500
-	NETGEAR_HW_ID := 29764958+0+256+512+4x4+4x4+cascade
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
-endef
-TARGET_DEVICES += netgear_xr500
-
-define Device/qcom_ipq8064-ap148
-	$(call Device/FitImage)
-	$(call Device/UbiFit)
-	DEVICE_VENDOR := Qualcomm
-	DEVICE_MODEL := AP148
-	DEVICE_VARIANT := standard
-	SOC := qcom-ipq8064
-	DEVICE_DTS := qcom-ipq8064-ap148
-	KERNEL_INSTALL := 1
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := ap148
-	SUPPORTED_DEVICES += ap148
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += qcom_ipq8064-ap148
-
-define Device/qcom_ipq8064-ap148-legacy
-	$(call Device/LegacyImage)
-	$(call Device/UbiFit)
-	DEVICE_VENDOR := Qualcomm
-	DEVICE_MODEL := AP148
-	DEVICE_VARIANT := legacy
-	SOC := qcom-ipq8064
-	DEVICE_DTS := qcom-ipq8064-ap148
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := ap148
-	SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += qcom_ipq8064-ap148-legacy
-
-define Device/qcom_ipq8064-ap161
-	$(call Device/FitImage)
-	$(call Device/UbiFit)
-	DEVICE_VENDOR := Qualcomm
-	DEVICE_MODEL := AP161
-	SOC := qcom-ipq8064
-	DEVICE_DTS := qcom-ipq8064-ap161
-	KERNEL_INSTALL := 1
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := ap161
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += qcom_ipq8064-ap161
-
-define Device/qcom_ipq8064-db149
-	$(call Device/FitImage)
-	DEVICE_VENDOR := Qualcomm
-	DEVICE_MODEL := DB149
-	SOC := qcom-ipq8064
-	DEVICE_DTS := qcom-ipq8064-db149
-	KERNEL_INSTALL := 1
-	BOARD_NAME := db149
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += qcom_ipq8064-db149
-
-define Device/ruijie_rg-mtfi-m520
-	DEVICE_VENDOR := Ruijie
-	DEVICE_MODEL := RG-MTFi-M520
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 64k
-	KERNEL_SIZE := 4096k
-	KERNEL_SUFFIX := -uImage
-	KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE)
-	KERNEL_NAME := zImage
-	IMAGES += factory.bin
-	IMAGE/factory.bin := qsdk-ipq-factory-mmc
-	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata
-	DEVICE_PACKAGES := ath10k-firmware-qca988x-ct e2fsprogs kmod-hwmon-lm75 \
-	kmod-fs-ext4 kmod-fs-f2fs kmod-rtc-pcf8563 losetup mkf2fs
-endef
-TARGET_DEVICES += ruijie_rg-mtfi-m520
-
-define Device/norton_core-518
-	DEVICE_TITLE := Norton Core 518
-	BOARD_NAME := core-518
-	SOC := qcom-ipq8065
-	DEVICE_DTS := qcom-ipq8065-core-518
-	BLOCKSIZE := 64k
-	KERNEL_SIZE := 4096k
-	KERNEL_SUFFIX := -uImage
-	KERNEL = kernel-bin | append-dtb | uImage none | pad-to $${KERNEL_SIZE}
-	KERNEL_NAME := zImage
-	SUPPORTED_DEVICES += core-518
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup f2fs-tools
-	IMAGES := mmcblk0p10-rootfs.bin mmcblk0p9-kernel.bin sysupgrade.bin
-	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$${BLOCKSIZE} | sysupgrade-tar rootfs=$$$$@ | append-metadata
-	IMAGE/mmcblk0p9-kernel.bin := pad-extra 40 | append-kernel | pad-to $$$${KERNEL_SIZE}
-	IMAGE/mmcblk0p10-rootfs.bin := append-rootfs | pad-rootfs
-endef
-TARGET_DEVICES += norton_core-518
-
-define Device/surf_g-nat200
-	$(call Device/LegacyImage)
-	DEVICE_VENDOR := SURF
-	DEVICE_MODEL := G-NAT200
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	IMAGE_SIZE := 26624k
-	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
-endef
-TARGET_DEVICES += surf_g-nat200
-
-define Device/tplink_ad7200
-	$(call Device/TpSafeImage)
-	DEVICE_VENDOR := TP-Link
-	DEVICE_MODEL := AD7200
-	DEVICE_VARIANT := v1/v2
-	DEVICE_ALT0_VENDOR := TP-Link
-	DEVICE_ALT0_MODEL := Talon AD7200
-	DEVICE_ALT0_VARIANT := v1/v2
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	TPLINK_BOARD_ID := AD7200
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-wil6210
-endef
-TARGET_DEVICES += tplink_ad7200
-
-define Device/tplink_c2600
-	$(call Device/TpSafeImage)
-	DEVICE_VENDOR := TP-Link
-	DEVICE_MODEL := Archer C2600
-	DEVICE_VARIANT := v1
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := c2600
-	SUPPORTED_DEVICES += c2600
-	TPLINK_BOARD_ID := C2600
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-endef
-TARGET_DEVICES += tplink_c2600
-
-define Device/tplink_vr2600v
-	DEVICE_VENDOR := TP-Link
-	DEVICE_MODEL := Archer VR2600v
-	DEVICE_VARIANT := v1
-	KERNEL_SUFFIX := -uImage
-	KERNEL = kernel-bin | append-dtb | uImage none
-	KERNEL_NAME := zImage
-	KERNEL_SIZE := 3072k
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := vr2600v
-	SUPPORTED_DEVICES += vr2600v
-	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
-	IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata
-endef
-TARGET_DEVICES += tplink_vr2600v
-
-define Device/ubnt_unifi-ac-hd
-	$(call Device/FitImageLzma)
-	DEVICE_VENDOR := Ubiquiti
-	DEVICE_MODEL := UniFi AC HD
-	SOC := qcom-ipq8064
-	BLOCKSIZE := 64k
-	IMAGE_SIZE := 14784k
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
-	IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | append-metadata | check-size
-endef
-TARGET_DEVICES += ubnt_unifi-ac-hd
-
-define Device/zyxel_nbg6817
-	DEVICE_VENDOR := ZyXEL
-	DEVICE_MODEL := NBG6817
-	SOC := qcom-ipq8065
-	KERNEL_SIZE := 4096k
-	BLOCKSIZE := 64k
-	BOARD_NAME := nbg6817
-	RAS_BOARD := NBG6817
-	RAS_ROOTFS_SIZE := 20934k
-	RAS_VERSION := "V1.99(OWRT.9999)C0"
-	SUPPORTED_DEVICES += nbg6817
-	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup
-	$(call Device/ZyXELImage)
-endef
-TARGET_DEVICES += zyxel_nbg6817
+include $(SUBTARGET).mk
 
 $(eval $(call BuildImage))
diff --git a/target/linux/ipq806x/image/generic.mk b/target/linux/ipq806x/image/generic.mk
new file mode 100644
index 00000000000000..bd8e2e26f4398f
--- /dev/null
+++ b/target/linux/ipq806x/image/generic.mk
@@ -0,0 +1,508 @@
+DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
+DEVICE_VARS += TPLINK_BOARD_ID
+
+define Device/kernel-size-migration
+  DEVICE_COMPAT_VERSION := 2.0
+  DEVICE_COMPAT_MESSAGE := *** Kernel partition size has changed from earlier \
+	versions. You need to sysupgrade with the OpenWrt factory image and \
+	use the force flag when image check fails. Settings will be lost. ***
+endef
+
+define Build/buffalo-rootfs-cksum
+	( \
+		echo -ne "\x$$(od -A n -t u1 $@ | tr -s ' ' '\n' | \
+			$(STAGING_DIR_HOST)/bin/awk '{s+=$$0}END{printf "%x", 255-s%256}')"; \
+	) >> $@
+endef
+
+define Build/edimax-header
+	$(eval edimax_model=$(word 1,$(1)))
+
+	$(STAGING_DIR_HOST)/bin/mkedimaximg \
+	-b -s CSYS -m $(edimax_model) \
+	-f 0x70000 -S 0x1200000 \
+	-i $@ -o $@.new
+	@mv $@.new $@
+endef
+
+define Device/DniImage
+	KERNEL_SUFFIX := -uImage
+	KERNEL = kernel-bin | append-dtb | uImage none
+	KERNEL_NAME := zImage
+	NETGEAR_BOARD_ID :=
+	NETGEAR_HW_ID :=
+	UBINIZE_OPTS := -E 5
+	IMAGES += factory.img
+	IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \
+		append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | \
+		append-ubi | netgear-dni
+	IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \
+		append-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | \
+		append-metadata
+endef
+
+define Device/TpSafeImage
+	KERNEL_SUFFIX := -uImage
+	KERNEL = kernel-bin | append-dtb | uImage none
+	KERNEL_NAME := zImage
+	TPLINK_BOARD_ID :=
+	IMAGES += factory.bin
+	IMAGE/factory.bin := append-rootfs | tplink-safeloader factory
+	IMAGE/sysupgrade.bin := append-rootfs | \
+		tplink-safeloader sysupgrade | append-metadata
+endef
+
+define Device/ZyXELImage
+	KERNEL_SUFFIX := -uImage
+	KERNEL = kernel-bin | append-dtb | uImage none | \
+		pad-to $$(KERNEL_SIZE)
+	KERNEL_NAME := zImage
+	IMAGES += factory.bin
+	IMAGE/factory.bin := append-rootfs | pad-rootfs | \
+		pad-to $$$$(BLOCKSIZE) | zyxel-ras-image separate-kernel
+	IMAGE/sysupgrade.bin/squashfs := append-rootfs | \
+		pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | \
+		append-metadata
+endef
+
+define Device/arris_tr4400-v2
+	$(call Device/LegacyImage)
+	DEVICE_VENDOR := Arris
+	DEVICE_MODEL := TR4400
+	DEVICE_VARIANT := v2
+	SOC := qcom-ipq8065
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	KERNEL_IN_UBI := 1
+	SUPPORTED_DEVICES += arris,rac2v1a
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += arris_tr4400-v2
+
+define Device/askey_rt4230w-rev6
+	$(call Device/LegacyImage)
+	DEVICE_VENDOR := Askey
+	DEVICE_MODEL := RT4230W
+	DEVICE_VARIANT := REV6
+	SOC := qcom-ipq8065
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
+	KERNEL_IN_UBI := 1
+endef
+TARGET_DEVICES += askey_rt4230w-rev6
+
+define Device/asrock_g10
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	SOC := qcom-ipq8064
+	DEVICE_VENDOR := ASRock
+	DEVICE_MODEL := G10
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	KERNEL_SIZE := 5332k
+	DEVICE_PACKAGES := kmod-i2c-gpio ath10k-firmware-qca99x0-ct
+	IMAGE/nand-factory.bin := append-ubi | edimax-header RN67
+endef
+TARGET_DEVICES += asrock_g10
+
+define Device/buffalo_wxr-2533dhp
+	$(call Device/LegacyImage)
+	SOC := qcom-ipq8064
+	DEVICE_VENDOR := Buffalo
+	DEVICE_MODEL := WXR-2533DHP
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	IMAGE_SIZE := 65536k
+	KERNEL_IN_UBI := 1
+	IMAGE/sysupgrade.bin := append-rootfs | buffalo-rootfs-cksum | \
+		sysupgrade-tar rootfs=$$$$@ | append-metadata
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += buffalo_wxr-2533dhp
+
+define Device/compex_wpq864
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := Compex
+	DEVICE_MODEL := WPQ864
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	SOC := qcom-ipq8064
+	DEVICE_PACKAGES := kmod-gpio-beeper
+endef
+TARGET_DEVICES += compex_wpq864
+
+define Device/edgecore_ecw5410
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := Edgecore
+	DEVICE_MODEL := ECW5410
+	SOC := qcom-ipq8068
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_DTS_CONFIG := config@v2.0-ap160
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
+endef
+TARGET_DEVICES += edgecore_ecw5410
+
+define Device/linksys_ea7500-v1
+	$(call Device/LegacyImage)
+	$(Device/kernel-size-migration)
+	DEVICE_VENDOR := Linksys
+	DEVICE_MODEL := EA7500
+	DEVICE_VARIANT := v1
+	SOC := qcom-ipq8064
+	PAGESIZE := 2048
+	BLOCKSIZE := 128k
+	KERNEL_SIZE := 4096k
+	KERNEL = kernel-bin | append-dtb | uImage none | \
+		append-uImage-fakehdr filesystem
+	UBINIZE_OPTS := -E 5
+	IMAGES := factory.bin sysupgrade.bin
+	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
+		append-ubi | pad-to $$$$(PAGESIZE)
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += linksys_ea7500-v1
+
+define Device/linksys_ea8500
+	$(call Device/LegacyImage)
+	$(Device/kernel-size-migration)
+	DEVICE_VENDOR := Linksys
+	DEVICE_MODEL := EA8500
+	SOC := qcom-ipq8064
+	PAGESIZE := 2048
+	BLOCKSIZE := 128k
+	KERNEL_SIZE := 4096k
+	KERNEL = kernel-bin | append-dtb | uImage none | \
+		append-uImage-fakehdr filesystem
+	BOARD_NAME := ea8500
+	SUPPORTED_DEVICES += ea8500
+	UBINIZE_OPTS := -E 5
+	IMAGES += factory.bin
+	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
+		append-ubi
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += linksys_ea8500
+
+define Device/meraki_mr42
+	$(call Device/FitImage)
+	DEVICE_VENDOR := Cisco Meraki
+	DEVICE_MODEL := MR42
+	SOC := qcom-ipq8068
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	KERNEL_LOADADDR = 0x44208000
+	DEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \
+		-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \
+		-kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \
+		-uboot-envtools ath10k-firmware-qca9887-ct \
+		ath10k-firmware-qca99x0-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \
+		kmod-leds-tlc591xx
+endef
+TARGET_DEVICES += meraki_mr42
+
+define Device/meraki_mr52
+	$(call Device/FitImage)
+	DEVICE_VENDOR := Cisco Meraki
+	DEVICE_MODEL := MR52
+	SOC := qcom-ipq8068
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	KERNEL_LOADADDR = 0x44208000
+	DEVICE_DTS_CONFIG := config@2
+	DEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \
+		-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \
+		-kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \
+		-uboot-envtools ath10k-firmware-qca9887-ct \
+		ath10k-firmware-qca9984-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \
+		kmod-leds-tlc591xx
+endef
+TARGET_DEVICES += meraki_mr52
+
+define Device/nec_wg2600hp
+	$(call Device/LegacyImage)
+	DEVICE_VENDOR := NEC
+	DEVICE_MODEL := Aterm WG2600HP
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 64k
+	BOARD_NAME := wg2600hp
+	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
+		pad-rootfs | append-metadata
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += nec_wg2600hp
+
+define Device/nec_wg2600hp3
+	$(call Device/LegacyImage)
+	DEVICE_VENDOR := NEC Platforms
+	DEVICE_MODEL := Aterm WG2600HP3
+	SOC := qcom-ipq8062
+	BLOCKSIZE := 64k
+	IMAGES := sysupgrade.bin
+	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
+		pad-rootfs | append-metadata
+	DEVICE_PACKAGES := -kmod-ata-ahci -kmod-ata-ahci-platform \
+		-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \
+		-kmod-usb-phy-qcom-dwc3 -kmod-usb3 -kmod-usb-dwc3-qcom \
+		ath10k-firmware-qca9984-ct
+endef
+TARGET_DEVICES += nec_wg2600hp3
+
+define Device/netgear_d7800
+	$(call Device/DniImage)
+	DEVICE_VENDOR := NETGEAR
+	DEVICE_MODEL := Nighthawk X4 D7800
+	SOC := qcom-ipq8064
+	KERNEL_SIZE := 4096k
+	NETGEAR_BOARD_ID := D7800
+	NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := d7800
+	SUPPORTED_DEVICES += d7800
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+	DEVICE_COMPAT_VERSION := 2.0
+	DEVICE_COMPAT_MESSAGE := Sysupgrade does not work due to rootfs ubi partition size change. \
+		Use factory image with the TFTP recovery flash routine.
+endef
+TARGET_DEVICES += netgear_d7800
+
+define Device/netgear_r7500
+	$(call Device/DniImage)
+	DEVICE_VENDOR := NETGEAR
+	DEVICE_MODEL := Nighthawk X4 R7500
+	DEVICE_VARIANT := v1
+	SOC := qcom-ipq8064
+	KERNEL_SIZE := 4096k
+	NETGEAR_BOARD_ID := R7500
+	NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := r7500
+	SUPPORTED_DEVICES += r7500
+	DEVICE_PACKAGES := ath10k-firmware-qca988x-ct
+endef
+TARGET_DEVICES += netgear_r7500
+
+define Device/netgear_r7500v2
+	$(call Device/DniImage)
+	DEVICE_VENDOR := NETGEAR
+	DEVICE_MODEL := Nighthawk X4 R7500
+	DEVICE_VARIANT := v2
+	SOC := qcom-ipq8064
+	KERNEL_SIZE := 4096k
+	NETGEAR_BOARD_ID := R7500v2
+	NETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := r7500v2
+	SUPPORTED_DEVICES += r7500v2
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct \
+		ath10k-firmware-qca988x-ct
+endef
+TARGET_DEVICES += netgear_r7500v2
+
+define Device/netgear_r7800
+	$(call Device/DniImage)
+	DEVICE_VENDOR := NETGEAR
+	DEVICE_MODEL := Nighthawk X4S R7800
+	SOC := qcom-ipq8065
+	KERNEL_SIZE := 4096k
+	NETGEAR_BOARD_ID := R7800
+	NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := r7800
+	SUPPORTED_DEVICES += r7800
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-ramoops
+endef
+TARGET_DEVICES += netgear_r7800
+
+define Device/netgear_xr500
+	$(call Device/DniImage)
+	DEVICE_VENDOR := NETGEAR
+	DEVICE_MODEL := Nighthawk XR500
+	SOC := qcom-ipq8065
+	KERNEL_SIZE := 4096k
+	NETGEAR_BOARD_ID := XR500
+	NETGEAR_HW_ID := 29764958+0+256+512+4x4+4x4+cascade
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-ramoops
+endef
+TARGET_DEVICES += netgear_xr500
+
+define Device/qcom_ipq8064-ap148
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := Qualcomm
+	DEVICE_MODEL := AP148
+	DEVICE_VARIANT := standard
+	SOC := qcom-ipq8064
+	DEVICE_DTS := qcom-ipq8064-ap148
+	KERNEL_INSTALL := 1
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := ap148
+	SUPPORTED_DEVICES += ap148
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += qcom_ipq8064-ap148
+
+define Device/qcom_ipq8064-ap148-legacy
+	$(call Device/LegacyImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := Qualcomm
+	DEVICE_MODEL := AP148
+	DEVICE_VARIANT := legacy
+	SOC := qcom-ipq8064
+	DEVICE_DTS := qcom-ipq8064-ap148
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := ap148
+	SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += qcom_ipq8064-ap148-legacy
+
+define Device/qcom_ipq8064-ap161
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_VENDOR := Qualcomm
+	DEVICE_MODEL := AP161
+	SOC := qcom-ipq8064
+	DEVICE_DTS := qcom-ipq8064-ap161
+	KERNEL_INSTALL := 1
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := ap161
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += qcom_ipq8064-ap161
+
+define Device/qcom_ipq8064-db149
+	$(call Device/FitImage)
+	DEVICE_VENDOR := Qualcomm
+	DEVICE_MODEL := DB149
+	SOC := qcom-ipq8064
+	DEVICE_DTS := qcom-ipq8064-db149
+	KERNEL_INSTALL := 1
+	BOARD_NAME := db149
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += qcom_ipq8064-db149
+
+define Device/ruijie_rg-mtfi-m520
+	DEVICE_VENDOR := Ruijie
+	DEVICE_MODEL := RG-MTFi-M520
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 64k
+	KERNEL_SIZE := 4096k
+	KERNEL_SUFFIX := -uImage
+	KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE)
+	KERNEL_NAME := zImage
+	IMAGES += factory.bin
+	IMAGE/factory.bin := qsdk-ipq-factory-mmc
+	IMAGE/sysupgrade.bin/squashfs := append-rootfs | \
+		pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | \
+		append-metadata
+	DEVICE_PACKAGES := ath10k-firmware-qca988x-ct e2fsprogs kmod-hwmon-lm75 \
+		kmod-fs-ext4 kmod-fs-f2fs kmod-rtc-pcf8563 losetup mkf2fs
+endef
+TARGET_DEVICES += ruijie_rg-mtfi-m520
+
+define Device/surf_g-nat200
+	$(call Device/LegacyImage)
+	DEVICE_VENDOR := SURF
+	DEVICE_MODEL := G-NAT200
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	IMAGE_SIZE := 26624k
+	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
+		pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += surf_g-nat200
+
+define Device/tplink_ad7200
+	$(call Device/TpSafeImage)
+	DEVICE_VENDOR := TP-Link
+	DEVICE_MODEL := AD7200
+	DEVICE_VARIANT := v1/v2
+	DEVICE_ALT0_VENDOR := TP-Link
+	DEVICE_ALT0_MODEL := Talon AD7200
+	DEVICE_ALT0_VARIANT := v1/v2
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	TPLINK_BOARD_ID := AD7200
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-wil6210
+endef
+TARGET_DEVICES += tplink_ad7200
+
+define Device/tplink_c2600
+	$(call Device/TpSafeImage)
+	DEVICE_VENDOR := TP-Link
+	DEVICE_MODEL := Archer C2600
+	DEVICE_VARIANT := v1
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := c2600
+	SUPPORTED_DEVICES += c2600
+	TPLINK_BOARD_ID := C2600
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+endef
+TARGET_DEVICES += tplink_c2600
+
+define Device/tplink_vr2600v
+	DEVICE_VENDOR := TP-Link
+	DEVICE_MODEL := Archer VR2600v
+	DEVICE_VARIANT := v1
+	KERNEL_SUFFIX := -uImage
+	KERNEL = kernel-bin | append-dtb | uImage none
+	KERNEL_NAME := zImage
+	IMAGE_SIZE := 12672k
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	BOARD_NAME := vr2600v
+	SUPPORTED_DEVICES += vr2600v
+	DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
+	IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | \
+		append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += tplink_vr2600v
+
+define Device/ubnt_unifi-ac-hd
+	$(call Device/FitImageLzma)
+	DEVICE_VENDOR := Ubiquiti
+	DEVICE_MODEL := UniFi AC HD
+	SOC := qcom-ipq8064
+	BLOCKSIZE := 64k
+	IMAGE_SIZE := 14784k
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
+	IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
+		append-rootfs | pad-rootfs | check-size | append-metadata
+endef
+TARGET_DEVICES += ubnt_unifi-ac-hd
+
+define Device/zyxel_nbg6817
+	DEVICE_VENDOR := ZyXEL
+	DEVICE_MODEL := NBG6817
+	SOC := qcom-ipq8065
+	KERNEL_SIZE := 4096k
+	BLOCKSIZE := 64k
+	BOARD_NAME := nbg6817
+	RAS_BOARD := NBG6817
+	RAS_ROOTFS_SIZE := 20934k
+	RAS_VERSION := "V1.99(OWRT.9999)C0"
+	SUPPORTED_DEVICES += nbg6817
+	DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs \
+		kmod-fs-ext4 losetup
+	$(call Device/ZyXELImage)
+endef
+TARGET_DEVICES += zyxel_nbg6817
diff --git a/target/linux/ipq806x/patches-5.4/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch b/target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch
rename to target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch
diff --git a/target/linux/ipq806x/patches-5.4/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch
rename to target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch
diff --git a/target/linux/ipq806x/patches-5.4/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
similarity index 93%
rename from target/linux/ipq806x/patches-5.4/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
rename to target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
index 6d3e7d9ee04ce8..5065c12d8d663a 100644
--- a/target/linux/ipq806x/patches-5.4/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
+++ b/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
@@ -33,8 +33,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
-@@ -319,7 +319,7 @@ config ARCH_MULTIPLATFORM
- 	depends on MMU
+@@ -323,7 +323,7 @@ config ARCH_MULTIPLATFORM
+ 	select ARCH_SELECT_MEMORY_MODEL
  	select ARM_HAS_SG_CHAIN
  	select ARM_PATCH_PHYS_VIRT
 -	select AUTO_ZRELADDR
@@ -44,7 +44,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  	select GENERIC_CLOCKEVENTS
 --- a/arch/arm/Makefile
 +++ b/arch/arm/Makefile
-@@ -258,9 +258,11 @@ MACHINE  := arch/arm/mach-$(word 1,$(mac
+@@ -251,9 +251,11 @@ MACHINE  := arch/arm/mach-$(word 1,$(mac
  else
  MACHINE  :=
  endif
diff --git a/target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch b/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch
similarity index 93%
rename from target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch
rename to target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch
index 23c858163608b2..a1a0371fbc48de 100644
--- a/target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch
+++ b/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch
@@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/arch/arm/Makefile
 +++ b/arch/arm/Makefile
-@@ -67,7 +67,7 @@ KBUILD_CFLAGS	+= $(call cc-option,-fno-i
+@@ -61,7 +61,7 @@ KBUILD_CFLAGS	+= $(call cc-option,-fno-i
  # macro, but instead defines a whole series of macros which makes
  # testing for a specific architecture or later rather impossible.
  arch-$(CONFIG_CPU_32v7M)	=-D__LINUX_ARM_ARCH__=7 -march=armv7-m
diff --git a/target/linux/ipq806x/patches-5.4/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
similarity index 91%
rename from target/linux/ipq806x/patches-5.4/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
rename to target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
index e67d498f160859..5bfc3eddefe5c2 100644
--- a/target/linux/ipq806x/patches-5.4/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
+++ b/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
@@ -22,7 +22,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
 
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
-@@ -1824,6 +1824,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+@@ -1778,6 +1778,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
  	  The command-line arguments provided by the boot loader will be
  	  appended to the the device tree bootargs property.
  
@@ -42,7 +42,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  config CMDLINE
 --- a/arch/arm/boot/compressed/atags_to_fdt.c
 +++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -4,6 +4,8 @@
+@@ -5,6 +5,8 @@
  
  #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
  #define do_extend_cmdline 1
@@ -51,7 +51,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  #else
  #define do_extend_cmdline 0
  #endif
-@@ -67,6 +69,80 @@ static uint32_t get_cell_size(const void
+@@ -69,6 +71,80 @@ static uint32_t get_cell_size(const void
  	return cell_size;
  }
  
@@ -132,7 +132,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
  {
  	char cmdline[COMMAND_LINE_SIZE];
-@@ -86,12 +162,21 @@ static void merge_fdt_bootargs(void *fdt
+@@ -88,12 +164,21 @@ static void merge_fdt_bootargs(void *fdt
  
  	/* and append the ATAG_CMDLINE */
  	if (fdt_cmdline) {
@@ -154,7 +154,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  	}
  	*ptr = '\0';
  
-@@ -166,7 +251,9 @@ int atags_to_fdt(void *atag_list, void *
+@@ -168,7 +253,9 @@ int atags_to_fdt(void *atag_list, void *
  			else
  				setprop_string(fdt, "/chosen", "bootargs",
  					       atag->u.cmdline.cmdline);
@@ -165,7 +165,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  			if (memcount >= sizeof(mem_reg_property)/4)
  				continue;
  			if (!atag->u.mem.size)
-@@ -210,6 +297,10 @@ int atags_to_fdt(void *atag_list, void *
+@@ -212,6 +299,10 @@ int atags_to_fdt(void *atag_list, void *
  		setprop(fdt, "/memory", "reg", mem_reg_property,
  			4 * memcount * memsize);
  	}
@@ -178,9 +178,9 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  }
 --- a/init/main.c
 +++ b/init/main.c
-@@ -102,6 +102,10 @@
- #define CREATE_TRACE_POINTS
- #include <trace/events/initcall.h>
+@@ -108,6 +108,10 @@
+ 
+ #include <kunit/test.h>
  
 +#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
 +#include <linux/of.h>
@@ -189,8 +189,8 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
  static int kernel_init(void *);
  
  extern void init_IRQ(void);
-@@ -630,6 +634,18 @@ asmlinkage __visible void __init start_k
- 	pr_notice("Kernel command line: %s\n", boot_command_line);
+@@ -903,6 +907,18 @@ asmlinkage __visible void __init __no_sa
+ 	pr_notice("Kernel command line: %s\n", saved_command_line);
  	/* parameters may set static keys */
  	jump_label_init();
 +
diff --git a/target/linux/ipq806x/patches-5.4/0069-arm-boot-add-dts-files.patch b/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
similarity index 87%
rename from target/linux/ipq806x/patches-5.4/0069-arm-boot-add-dts-files.patch
rename to target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
index d698b0c299308e..14787df90e15ad 100644
--- a/target/linux/ipq806x/patches-5.4/0069-arm-boot-add-dts-files.patch
+++ b/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
@@ -10,18 +10,18 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
-@@ -842,7 +842,32 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+@@ -909,8 +909,32 @@ dtb-$(CONFIG_ARCH_QCOM) += \
  	qcom-ipq4019-ap.dk04.1-c3.dtb \
  	qcom-ipq4019-ap.dk07.1-c1.dtb \
  	qcom-ipq4019-ap.dk07.1-c2.dtb \
 +	qcom-ipq8062-wg2600hp3.dtb \
  	qcom-ipq8064-ap148.dtb \
+ 	qcom-ipq8064-rb3011.dtb \
 +	qcom-ipq8064-c2600.dtb \
 +	qcom-ipq8064-d7800.dtb \
 +	qcom-ipq8064-db149.dtb \
 +	qcom-ipq8064-ap161.dtb \
 +	qcom-ipq8064-ea7500-v1.dtb \
-+	qcom-ipq8064-e8350-v1.dtb \
 +	qcom-ipq8064-ea8500.dtb \
 +	qcom-ipq8064-g10.dtb \
 +	qcom-ipq8064-g-nat200.dtb \
@@ -33,13 +33,13 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +	qcom-ipq8064-wpq864.dtb \
 +	qcom-ipq8064-wxr-2533dhp.dtb \
 +	qcom-ipq8065-nbg6817.dtb \
-+	qcom-ipq8065-core-518.dtb \
 +	qcom-ipq8065-r7800.dtb \
-+	qcom-ipq8065-xr500.dtb \
-+	qcom-ipq8065-rac2v1a.dtb \
 +	qcom-ipq8065-rt4230w-rev6.dtb \
-+	qcom-ipq8065-rt4230w-rev9.3.dtb \
++	qcom-ipq8065-tr4400-v2.dtb \
++	qcom-ipq8065-xr500.dtb \
 +	qcom-ipq8068-ecw5410.dtb \
++	qcom-ipq8068-mr42.dtb \
++	qcom-ipq8068-mr52.dtb \
  	qcom-msm8660-surf.dtb \
  	qcom-msm8960-cdp.dtb \
  	qcom-msm8974-fairphone-fp2.dtb \
diff --git a/target/linux/ipq806x/patches-5.4/0072-add-ipq806x-with-no-clocks.patch b/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch
similarity index 86%
rename from target/linux/ipq806x/patches-5.4/0072-add-ipq806x-with-no-clocks.patch
rename to target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch
index 50848c27a7b963..62bba1d72a001f 100644
--- a/target/linux/ipq806x/patches-5.4/0072-add-ipq806x-with-no-clocks.patch
+++ b/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch
@@ -1,6 +1,6 @@
 --- a/drivers/firmware/qcom_scm.c
 +++ b/drivers/firmware/qcom_scm.c
-@@ -597,6 +597,7 @@ static const struct of_device_id qcom_sc
+@@ -1275,6 +1275,7 @@ static const struct of_device_id qcom_sc
  							     SCM_HAS_BUS_CLK)
  	},
  	{ .compatible = "qcom,scm-ipq4019" },
diff --git a/target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch b/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch
similarity index 51%
rename from target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch
rename to target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch
index 568ca5bb883e2f..d6a459374939c8 100644
--- a/target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch
+++ b/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch
@@ -27,7 +27,15 @@
  			reg = <0x41000000 0x200000>;
  			no-map;
  		};
-@@ -155,6 +155,7 @@
+@@ -128,6 +128,7 @@
+ 			gpio-ranges = <&qcom_pinmux 0 0 69>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
++			#address-cells = <0>;
+ 			#interrupt-cells = <2>;
+ 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ 
+@@ -155,6 +156,7 @@
  					function = "pcie3_rst";
  					drive-strength = <12>;
  					bias-disable;
@@ -35,7 +43,15 @@
  				};
  			};
  
-@@ -219,21 +220,23 @@
+@@ -190,6 +192,7 @@
+ 		intc: interrupt-controller@2000000 {
+ 			compatible = "qcom,msm-qgic2";
+ 			interrupt-controller;
++			#address-cells = <0>;
+ 			#interrupt-cells = <3>;
+ 			reg = <0x02000000 0x1000>,
+ 			      <0x02002000 0x1000>;
+@@ -219,21 +222,23 @@
  		acc0: clock-controller@2088000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -61,7 +77,7 @@
  			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  			regulator;
  		};
-@@ -251,7 +254,7 @@
+@@ -251,7 +256,7 @@
  
  			syscon-tcsr = <&tcsr>;
  
@@ -70,7 +86,16 @@
  				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  				reg = <0x12490000 0x1000>,
  				      <0x12480000 0x1000>;
-@@ -326,7 +329,7 @@
+@@ -261,7 +266,7 @@
+ 				status = "disabled";
+ 			};
+ 
+-			i2c@124a0000 {
++			gsbi2_i2c: i2c@124a0000 {
+ 				compatible = "qcom,i2c-qup-v1.1.1";
+ 				reg = <0x124a0000 0x1000>;
+ 				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+@@ -326,7 +331,7 @@
  
  			syscon-tcsr = <&tcsr>;
  
@@ -79,7 +104,7 @@
  				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  				reg = <0x1a240000 0x1000>,
  				      <0x1a200000 0x1000>;
-@@ -397,7 +400,7 @@
+@@ -397,7 +402,7 @@
  			status = "disabled";
  		};
  
@@ -88,15 +113,80 @@
  			compatible = "qcom,ipq806x-ahci", "generic-ahci";
  			reg = <0x29000000 0x180>;
  
-@@ -430,6 +433,7 @@
+@@ -430,13 +435,35 @@
+ 			reg = <0x00700000 0x1000>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
++
++			tsens_calib: calib@400 {
++				reg = <0x400 0xb>;
++			};
++			tsens_backup: backup@410 {
++				reg = <0x410 0xb>;
++			};
++			speedbin_efuse: speedbin@0c0 {
++				reg = <0x0c0 0x4>;
++			};
+ 		};
+ 
+ 		gcc: clock-controller@900000 {
+-			compatible = "qcom,gcc-ipq8064";
++			compatible = "qcom,gcc-ipq8064", "syscon";
  			reg = <0x00900000 0x4000>;
  			#clock-cells = <1>;
  			#reset-cells = <1>;
 +			#power-domain-cells = <1>;
++
++			tsens: thermal-sensor@900000 {
++				compatible = "qcom,ipq8064-tsens";
++
++				nvmem-cells = <&tsens_calib>, <&tsens_backup>;
++				nvmem-cell-names = "calib", "calib_backup";
++				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++				interrupt-names = "uplow";
++				#thermal-sensor-cells = <1>;
++				#qcom,sensors = <11>;
++			};
  		};
  
  		tcsr: syscon@1a400000 {
-@@ -625,13 +629,13 @@
+@@ -622,7 +649,7 @@
+ 
+ 		gmac0: ethernet@37000000 {
+ 			device_type = "network";
+-			compatible = "qcom,ipq806x-gmac";
++			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ 			reg = <0x37000000 0x200000>;
+ 			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "macirq";
+@@ -645,7 +672,7 @@
+ 
+ 		gmac1: ethernet@37200000 {
+ 			device_type = "network";
+-			compatible = "qcom,ipq806x-gmac";
++			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ 			reg = <0x37200000 0x200000>;
+ 			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "macirq";
+@@ -668,7 +695,7 @@
+ 
+ 		gmac2: ethernet@37400000 {
+ 			device_type = "network";
+-			compatible = "qcom,ipq806x-gmac";
++			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ 			reg = <0x37400000 0x200000>;
+ 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "macirq";
+@@ -691,7 +718,7 @@
+ 
+ 		gmac3: ethernet@37600000 {
+ 			device_type = "network";
+-			compatible = "qcom,ipq806x-gmac";
++			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ 			reg = <0x37600000 0x200000>;
+ 			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ 			interrupt-names = "macirq";
+@@ -740,13 +767,13 @@
  			qcom,ee = <0>;
  		};
  
@@ -113,7 +203,7 @@
  				status          = "disabled";
  				compatible      = "arm,pl18x", "arm,primecell";
  				arm,primecell-periphid = <0x00051180>;
-@@ -645,13 +649,12 @@
+@@ -760,13 +787,12 @@
  				non-removable;
  				cap-sd-highspeed;
  				cap-mmc-highspeed;
diff --git a/target/linux/ipq806x/patches-5.4/083-ipq8064-dtsi-additions.patch b/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
similarity index 62%
rename from target/linux/ipq806x/patches-5.4/083-ipq8064-dtsi-additions.patch
rename to target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
index ccfae25494f09c..b37ad50f148b7f 100644
--- a/target/linux/ipq806x/patches-5.4/083-ipq8064-dtsi-additions.patch
+++ b/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
@@ -26,7 +26,7 @@
  		};
  
  		cpu1: cpu@1 {
-@@ -38,11 +50,476 @@
+@@ -38,14 +50,350 @@
  			next-level-cache = <&L2>;
  			qcom,acc = <&acc1>;
  			qcom,saw = <&saw1>;
@@ -40,22 +40,22 @@
 +			cooling-max-state = <10>;
 +			#cooling-cells = <2>;
 +			cpu-idle-states = <&CPU_SPC>;
- 		};
- 
--		L2: l2-cache {
--			compatible = "cache";
--			cache-level = <2>;
++ 		};
++
 +		idle-states {
 +			CPU_SPC: spc {
-+				compatible = "qcom,idle-state-spc", "arm,idle-state";
++				compatible = "qcom,idle-state-spc";
 +				status = "disabled";
 +				entry-latency-us = <400>;
 +				exit-latency-us = <900>;
 +				min-residency-us = <3000>;
 +			};
-+		};
+ 		};
 +	};
-+
+ 
+-		L2: l2-cache {
+-			compatible = "cache";
+-			cache-level = <2>;
 +	opp_table_l2: opp_table_l2 {
 +		compatible = "operating-points-v2";
 +
@@ -78,19 +78,22 @@
 +			opp-microvolt = <1150000>;
 +			clock-latency-ns = <100000>;
 +			opp-level = <2>;
-+ 		};
-+ 	};
-+ 
++		};
++	};
++
 +	opp_table0: opp_table0 {
 +		compatible = "operating-points-v2-kryo-cpu";
 +		nvmem-cells = <&speedbin_efuse>;
 +
++		/*
++		 * Voltage thresholds are <target min max>
++		 */
 +		opp-384000000 {
 +			opp-hz = /bits/ 64 <384000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1000000>;
-+			opp-microvolt-speed0-pvs1-v0 = <925000>;
-+			opp-microvolt-speed0-pvs2-v0 = <875000>;
-+			opp-microvolt-speed0-pvs3-v0 = <800000>;
++			opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
++			opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
++			opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
++			opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
 +			opp-supported-hw = <0x1>;
 +			clock-latency-ns = <100000>;
 +			opp-level = <0>;
@@ -98,10 +101,10 @@
 +
 +		opp-600000000 {
 +			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1050000>;
-+			opp-microvolt-speed0-pvs1-v0 = <975000>;
-+			opp-microvolt-speed0-pvs2-v0 = <925000>;
-+			opp-microvolt-speed0-pvs3-v0 = <850000>;
++			opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
++			opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
++			opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
++			opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
 +			opp-supported-hw = <0x1>;
 +			clock-latency-ns = <100000>;
 +			opp-level = <1>;
@@ -109,10 +112,10 @@
 +
 +		opp-800000000 {
 +			opp-hz = /bits/ 64 <800000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1100000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1025000>;
-+			opp-microvolt-speed0-pvs2-v0 = <995000>;
-+			opp-microvolt-speed0-pvs3-v0 = <900000>;
++			opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
++			opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
++			opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
++			opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
 +			opp-supported-hw = <0x1>;
 +			clock-latency-ns = <100000>;
 +			opp-level = <1>;
@@ -120,10 +123,10 @@
 +
 +		opp-1000000000 {
 +			opp-hz = /bits/ 64 <1000000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1150000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1075000>;
-+			opp-microvolt-speed0-pvs2-v0 = <1025000>;
-+			opp-microvolt-speed0-pvs3-v0 = <950000>;
++			opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
++			opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
++			opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
++			opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
 +			opp-supported-hw = <0x1>;
 +			clock-latency-ns = <100000>;
 +			opp-level = <1>;
@@ -131,27 +134,27 @@
 +
 +		opp-1200000000 {
 +			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1200000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1125000>;
-+			opp-microvolt-speed0-pvs2-v0 = <1075000>;
-+			opp-microvolt-speed0-pvs3-v0 = <1000000>;
++			opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
++			opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
++			opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
++			opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
 +			opp-supported-hw = <0x1>;
 +			clock-latency-ns = <100000>;
-+			opp-level = <1>;
++			opp-level = <2>;
 +		};
 +
 +		opp-1400000000 {
 +			opp-hz = /bits/ 64 <1400000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1250000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1175000>;
-+			opp-microvolt-speed0-pvs2-v0 = <1125000>;
-+			opp-microvolt-speed0-pvs3-v0 = <1050000>;
++			opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
++			opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
++			opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
++			opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
 +			opp-supported-hw = <0x1>;
 +			clock-latency-ns = <100000>;
 +			opp-level = <2>;
-+		};
-+	};
-+
+ 		};
+ 	};
+ 
 +	thermal-zones {
 +		tsens_tz_sensor0 {
 +			polling-delay-passive = <0>;
@@ -159,28 +162,16 @@
 +			thermal-sensors = <&tsens 0>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -191,28 +182,16 @@
 +			thermal-sensors = <&tsens 1>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -223,28 +202,16 @@
 +			thermal-sensors = <&tsens 2>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -255,28 +222,16 @@
 +			thermal-sensors = <&tsens 3>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -287,28 +242,16 @@
 +			thermal-sensors = <&tsens 4>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -319,28 +262,16 @@
 +			thermal-sensors = <&tsens 5>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -351,28 +282,16 @@
 +			thermal-sensors = <&tsens 6>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -383,28 +302,16 @@
 +			thermal-sensors = <&tsens 7>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -415,28 +322,16 @@
 +			thermal-sensors = <&tsens 8>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -447,28 +342,16 @@
 +			thermal-sensors = <&tsens 9>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
 +		};
@@ -479,34 +362,25 @@
 +			thermal-sensors = <&tsens 10>;
 +
 +			trips {
-+				cpu-critical-hi {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical_high";
-+				};
-+
-+				cpu-config-hi {
++				cpu-critical {
 +					temperature = <105000>;
 +					hysteresis = <2000>;
-+					type = "configurable_hi";
++					type = "critical";
 +				};
 +
-+				cpu-config-lo {
++				cpu-hot {
 +					temperature = <95000>;
 +					hysteresis = <2000>;
-+					type = "configurable_lo";
-+				};
-+
-+				cpu-critical-low {
-+					temperature = <0>;
-+					hysteresis = <2000>;
-+					type = "critical_low";
++					type = "hot";
 +				};
 +			};
- 		};
- 	};
- 
-@@ -93,6 +570,15 @@
++ 		};
++ 	};
++
+ 	memory {
+ 		device_type = "memory";
+ 		reg = <0x0 0x0>;
+@@ -93,6 +441,15 @@
  		};
  	};
  
@@ -522,7 +396,7 @@
  	firmware {
  		scm {
  			compatible = "qcom,scm-ipq806x", "qcom,scm";
-@@ -120,6 +606,95 @@
+@@ -120,6 +477,78 @@
  			reg-names = "lpass-lpaif";
  		};
  
@@ -537,23 +411,6 @@
 +			operating-points-v2 = <&opp_table_l2>;
 +		};
 +
-+		qfprom: qfprom@700000 {
-+			compatible = "qcom,qfprom", "syscon";
-+			reg = <0x700000 0x1000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			status = "okay";
-+			tsens_calib: calib@400 {
-+				reg = <0x400 0xb>;
-+			};
-+			tsens_backup: backup@410 {
-+				reg = <0x410 0xb>;
-+			};
-+			speedbin_efuse: speedbin@0c0 {
-+				reg = <0x0c0 0x4>;
-+			};
-+		};
-+
 +		rpm: rpm@108000 {
 +			compatible = "qcom,rpm-ipq8064";
 +			reg = <0x108000 0x1000>;
@@ -618,7 +475,7 @@
  		qcom_pinmux: pinmux@800000 {
  			compatible = "qcom,ipq8064-pinctrl";
  			reg = <0x800000 0x4000>;
-@@ -159,6 +734,15 @@
+@@ -160,6 +589,15 @@
  				};
  			};
  
@@ -634,7 +491,7 @@
  			spi_pins: spi_pins {
  				mux {
  					pins = "gpio18", "gpio19", "gpio21";
-@@ -168,6 +752,53 @@
+@@ -169,6 +607,53 @@
  				};
  			};
  
@@ -688,7 +545,7 @@
  			leds_pins: leds_pins {
  				mux {
  					pins = "gpio7", "gpio8", "gpio9",
-@@ -229,6 +860,17 @@
+@@ -231,6 +716,17 @@
  			clock-output-names = "acpu1_aux";
  		};
  
@@ -706,7 +563,7 @@
  		saw0: regulator@2089000 {
  			compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-@@ -241,6 +883,17 @@
+@@ -243,6 +739,52 @@
  			regulator;
  		};
  
@@ -720,27 +577,100 @@
 +			compatible = "syscon";
 +			reg = <0x12100000 0x10000>;
 +		};
++
++		gsbi1: gsbi@12440000 {
++			compatible = "qcom,gsbi-v1.0.0";
++			cell-index = <1>;
++			reg = <0x12440000 0x100>;
++			clocks = <&gcc GSBI1_H_CLK>;
++			clock-names = "iface";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges;
++			status = "disabled";
++
++			syscon-tcsr = <&tcsr>;
++
++			gsbi1_serial: serial@12450000 {
++				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++				reg = <0x12450000 0x100>,
++				      <0x12400000 0x03>;
++				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
++				clock-names = "core", "iface";
++				status = "disabled";
++			};
++
++			gsbi1_i2c: i2c@12460000 {
++				compatible = "qcom,i2c-qup-v1.1.1";
++				reg = <0x12460000 0x1000>;
++				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
++				clock-names = "core", "iface";
++				#address-cells = <1>;
++				#size-cells = <0>;
++				status = "disabled";
++			};
++		};
 +
  		gsbi2: gsbi@12480000 {
  			compatible = "qcom,gsbi-v1.0.0";
  			cell-index = <2>;
-@@ -436,6 +1089,15 @@
- 			#power-domain-cells = <1>;
+@@ -368,6 +910,33 @@
+ 			};
  		};
  
-+		tsens: thermal-sensor@900000 {
-+			compatible = "qcom,ipq8064-tsens";
-+			reg = <0x900000 0x3680>;
-+			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
-+			nvmem-cell-names = "calib", "calib_backup";
-+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
-+			#thermal-sensor-cells = <1>;
++		gsbi6: gsbi@16500000 {
++			status = "disabled";
++			compatible = "qcom,gsbi-v1.0.0";
++			cell-index = <6>;
++			reg = <0x16500000 0x100>;
++			clocks = <&gcc GSBI6_H_CLK>;
++			clock-names = "iface";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges;
++
++			syscon-tcsr = <&tcsr>;
++
++			gsbi6_i2c: i2c@16580000 {
++				compatible = "qcom,i2c-qup-v1.1.1";
++				reg = <0x16580000 0x1000>;
++				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++
++				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
++				clock-names = "core", "iface";
++				status = "disabled";
++
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
 +		};
 +
- 		tcsr: syscon@1a400000 {
- 			compatible = "qcom,tcsr-ipq8064", "syscon";
- 			reg = <0x1a400000 0x100>;
-@@ -448,6 +1110,95 @@
+ 		gsbi7: gsbi@16600000 {
+ 			status = "disabled";
+ 			compatible = "qcom,gsbi-v1.0.0";
+@@ -389,6 +958,19 @@
+ 				clock-names = "core", "iface";
+ 				status = "disabled";
+ 			};
++
++			gsbi7_i2c: i2c@16680000 {
++ 				compatible = "qcom,i2c-qup-v1.1.1";
++ 				reg = <0x16680000 0x1000>;
++				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++
++ 				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
++ 				clock-names = "core", "iface";
++				status = "disabled";
++
++ 				#address-cells = <1>;
++				#size-cells = <0>;
++			};
+ 		};
+ 
+ 		sata_phy: sata-phy@1b400000 {
+@@ -478,6 +1060,95 @@
  			#reset-cells = <1>;
  		};
  
@@ -751,7 +681,7 @@
 +
 +		hs_phy_0: hs_phy_0 {
 +			compatible = "qcom,ipq806x-usb-phy-hs";
-+			reg = <0x110f8800 0x30>;
++			reg = <0x100f8800 0x30>;
 +			clocks = <&gcc USB30_0_UTMI_CLK>;
 +			clock-names = "ref";
 +			#phy-cells = <0>;
@@ -759,17 +689,17 @@
 +
 +		ss_phy_0: ss_phy_0 {
 +			compatible = "qcom,ipq806x-usb-phy-ss";
-+			reg = <0x110f8830 0x30>;
++			reg = <0x100f8830 0x30>;
 +			clocks = <&gcc USB30_0_MASTER_CLK>;
 +			clock-names = "ref";
 +			#phy-cells = <0>;
 +		};
 +
-+		usb3_0: usb3@110f8800 {
++		usb3_0: usb3@100f8800 {
 +			compatible = "qcom,dwc3", "syscon";
 +			#address-cells = <1>;
 +			#size-cells = <1>;
-+			reg = <0x110f8800 0x8000>;
++			reg = <0x100f8800 0x8000>;
 +			clocks = <&gcc USB30_0_MASTER_CLK>;
 +			clock-names = "core";
 +
@@ -780,10 +710,10 @@
 +
 +			status = "disabled";
 +
-+			dwc3_0: dwc3@11000000 {
++			dwc3_0: dwc3@10000000 {
 +				compatible = "snps,dwc3";
-+				reg = <0x11000000 0xcd00>;
-+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++				reg = <0x10000000 0xcd00>;
++				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 +				phys = <&hs_phy_0>, <&ss_phy_0>;
 +				phy-names = "usb2-phy", "usb3-phy";
 +				dr_mode = "host";
@@ -793,7 +723,7 @@
 +
 +		hs_phy_1: hs_phy_1 {
 +			compatible = "qcom,ipq806x-usb-phy-hs";
-+			reg = <0x100f8800 0x30>;
++			reg = <0x110f8800 0x30>;
 +			clocks = <&gcc USB30_1_UTMI_CLK>;
 +			clock-names = "ref";
 +			#phy-cells = <0>;
@@ -801,17 +731,17 @@
 +
 +		ss_phy_1: ss_phy_1 {
 +			compatible = "qcom,ipq806x-usb-phy-ss";
-+			reg = <0x100f8830 0x30>;
++			reg = <0x110f8830 0x30>;
 +			clocks = <&gcc USB30_1_MASTER_CLK>;
 +			clock-names = "ref";
 +			#phy-cells = <0>;
 +		};
 +
-+		usb3_1: usb3@100f8800 {
++		usb3_1: usb3@110f8800 {
 +			compatible = "qcom,dwc3", "syscon";
 +			#address-cells = <1>;
 +			#size-cells = <1>;
-+			reg = <0x100f8800 0x8000>;
++			reg = <0x110f8800 0x8000>;
 +			clocks = <&gcc USB30_1_MASTER_CLK>;
 +			clock-names = "core";
 +
@@ -822,10 +752,10 @@
 +
 +			status = "disabled";
 +
-+			dwc3_1: dwc3@10000000 {
++			dwc3_1: dwc3@11000000 {
 +				compatible = "snps,dwc3";
-+				reg = <0x10000000 0xcd00>;
-+				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++				reg = <0x11000000 0xcd00>;
++				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 +				phys = <&hs_phy_1>, <&ss_phy_1>;
 +				phy-names = "usb2-phy", "usb3-phy";
 +				dr_mode = "host";
@@ -836,8 +766,8 @@
  		pcie0: pci@1b500000 {
  			compatible = "qcom,pcie-ipq8064";
  			reg = <0x1b500000 0x1000
-@@ -601,6 +1352,167 @@
- 			perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+@@ -739,6 +1410,59 @@
+ 			status = "disabled";
  		};
  
 +		adm_dma: dma@18300000 {
@@ -879,22 +809,6 @@
 +			#size-cells = <0>;
 +		};
 +
-+		nss_common: syscon@03000000 {
-+			compatible = "syscon";
-+			reg = <0x03000000 0x0000FFFF>;
-+		};
-+
-+		qsgmii_csr: syscon@1bb00000 {
-+			compatible = "syscon";
-+			reg = <0x1bb00000 0x000001FF>;
-+		};
-+
-+		stmmac_axi_setup: stmmac-axi-config {
-+			snps,wr_osr_lmt = <7>;
-+			snps,rd_osr_lmt = <7>;
-+			snps,blen = <16 0 0 0 0 0 0>;
-+		};
-+
 +		mdio0: mdio@37000000 {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
@@ -908,103 +822,11 @@
 +
 +			status = "disabled";
 +		};
-+
-+		gmac0: ethernet@37000000 {
-+			device_type = "network";
-+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
-+			reg = <0x37000000 0x200000>;
-+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "macirq";
-+
-+			snps,axi-config = <&stmmac_axi_setup>;
-+			snps,pbl = <32>;
-+			snps,aal = <1>;
-+
-+			qcom,nss-common = <&nss_common>;
-+			qcom,qsgmii-csr = <&qsgmii_csr>;
-+
-+			clocks = <&gcc GMAC_CORE1_CLK>;
-+			clock-names = "stmmaceth";
-+
-+			resets = <&gcc GMAC_CORE1_RESET>;
-+			reset-names = "stmmaceth";
-+
-+			status = "disabled";
-+		};
-+
-+		gmac1: ethernet@37200000 {
-+			device_type = "network";
-+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
-+			reg = <0x37200000 0x200000>;
-+			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "macirq";
-+
-+			snps,axi-config = <&stmmac_axi_setup>;
-+			snps,pbl = <32>;
-+			snps,aal = <1>;
-+
-+			qcom,nss-common = <&nss_common>;
-+			qcom,qsgmii-csr = <&qsgmii_csr>;
-+
-+			clocks = <&gcc GMAC_CORE2_CLK>;
-+			clock-names = "stmmaceth";
-+
-+			resets = <&gcc GMAC_CORE2_RESET>;
-+			reset-names = "stmmaceth";
-+
-+			status = "disabled";
-+		};
-+
-+		gmac2: ethernet@37400000 {
-+			device_type = "network";
-+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
-+			reg = <0x37400000 0x200000>;
-+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "macirq";
-+
-+			snps,axi-config = <&stmmac_axi_setup>;
-+			snps,pbl = <32>;
-+			snps,aal = <1>;
-+
-+			qcom,nss-common = <&nss_common>;
-+			qcom,qsgmii-csr = <&qsgmii_csr>;
-+
-+			clocks = <&gcc GMAC_CORE3_CLK>;
-+			clock-names = "stmmaceth";
-+
-+			resets = <&gcc GMAC_CORE3_RESET>;
-+			reset-names = "stmmaceth";
-+
-+			status = "disabled";
-+		};
-+
-+		gmac3: ethernet@37600000 {
-+			device_type = "network";
-+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
-+			reg = <0x37600000 0x200000>;
-+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "macirq";
-+
-+			snps,axi-config = <&stmmac_axi_setup>;
-+			snps,pbl = <32>;
-+			snps,aal = <1>;
-+
-+			qcom,nss-common = <&nss_common>;
-+			qcom,qsgmii-csr = <&qsgmii_csr>;
-+
-+			clocks = <&gcc GMAC_CORE4_CLK>;
-+			clock-names = "stmmaceth";
-+
-+			resets = <&gcc GMAC_CORE4_RESET>;
-+			reset-names = "stmmaceth";
-+
-+			status = "disabled";
-+		};
 +
  		vsdcc_fixed: vsdcc-regulator {
  			compatible = "regulator-fixed";
  			regulator-name = "SDCC Power";
-@@ -676,4 +1588,17 @@
+@@ -814,4 +1538,17 @@
  			};
  		};
  	};
diff --git a/target/linux/ipq806x/patches-5.4/084-ipq8064-v1.0-dtsi-cleanup.patch b/target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/084-ipq8064-v1.0-dtsi-cleanup.patch
rename to target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch
diff --git a/target/linux/ipq806x/patches-5.4/085-ipq8064-v1.0-dtsi-additions.patch b/target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/085-ipq8064-v1.0-dtsi-additions.patch
rename to target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch
diff --git a/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch b/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch
new file mode 100644
index 00000000000000..747fa8c0197fc0
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch
@@ -0,0 +1,145 @@
+--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
++++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+@@ -24,73 +24,6 @@
+ 		device_type = "memory";
+ 	};
+ 
+-	mdio0: mdio-0 {
+-		status = "okay";
+-		compatible = "virtual,mdio-gpio";
+-		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
+-			<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+-		pinctrl-0 = <&mdio0_pins>;
+-		pinctrl-names = "default";
+-
+-		switch0: switch@10 {
+-			compatible = "qca,qca8337";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			dsa,member = <0 0>;
+-
+-			pinctrl-0 = <&sw0_reset_pin>;
+-			pinctrl-names = "default";
+-
+-			reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
+-			reg = <0x10>;
+-
+-			ports {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				switch0cpu: port@0 {
+-					reg = <0>;
+-					label = "cpu";
+-					ethernet = <&gmac0>;
+-					phy-mode = "rgmii-id";
+-					fixed-link {
+-						speed = <1000>;
+-						full-duplex;
+-					};
+-				};
+-
+-				port@1 {
+-					reg = <1>;
+-					label = "sw1";
+-				};
+-
+-				port@2 {
+-					reg = <2>;
+-					label = "sw2";
+-				};
+-
+-				port@3 {
+-					reg = <3>;
+-					label = "sw3";
+-				};
+-
+-				port@4 {
+-					reg = <4>;
+-					label = "sw4";
+-				};
+-
+-				port@5 {
+-					reg = <5>;
+-					label = "sw5";
+-				};
+-			};
+-		};
+-	};
+-
+ 	mdio1: mdio-1 {
+ 		status = "okay";
+ 		compatible = "virtual,mdio-gpio";
+@@ -216,6 +149,68 @@
+ 	};
+ };
+ 
++&mdio0 {
++	status = "okay";
++
++	pinctrl-0 = <&mdio0_pins>;
++	pinctrl-names = "default";
++
++	switch0: switch@10 {
++		compatible = "qca,qca8337";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		dsa,member = <0 0>;
++
++		pinctrl-0 = <&sw0_reset_pin>;
++		pinctrl-names = "default";
++
++		reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
++		reg = <0x10>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			switch0cpu: port@0 {
++				reg = <0>;
++				label = "cpu";
++				ethernet = <&gmac0>;
++				phy-mode = "rgmii-id";
++				fixed-link {
++					speed = <1000>;
++					full-duplex;
++				};
++			};
++
++			port@1 {
++				reg = <1>;
++				label = "sw1";
++			};
++
++			port@2 {
++				reg = <2>;
++				label = "sw2";
++			};
++
++			port@3 {
++				reg = <3>;
++				label = "sw3";
++			};
++
++			port@4 {
++				reg = <4>;
++				label = "sw4";
++			};
++
++			port@5 {
++				reg = <5>;
++				label = "sw5";
++			};
++		};
++	};
++};
++
+ &gmac0 {
+ 	status = "okay";
+ 
diff --git a/target/linux/ipq806x/patches-5.4/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch b/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
similarity index 92%
rename from target/linux/ipq806x/patches-5.4/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
rename to target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
index 19c3d096c416f9..8a25b17a192ab2 100644
--- a/target/linux/ipq806x/patches-5.4/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
+++ b/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
@@ -21,7 +21,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  };
  
  struct qcom_cpufreq_drv {
-@@ -250,6 +251,7 @@ static const struct qcom_cpufreq_match_d
+@@ -253,6 +254,7 @@ static const struct qcom_cpufreq_match_d
  
  static const struct qcom_cpufreq_match_data match_data_krait = {
  	.get_version = qcom_cpufreq_krait_name_version,
@@ -29,7 +29,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  };
  
  static const char *qcs404_genpd_names[] = { "cpr", NULL };
-@@ -385,6 +387,19 @@ static int qcom_cpufreq_probe(struct pla
+@@ -389,6 +391,19 @@ static int qcom_cpufreq_probe(struct pla
  		}
  	}
  
diff --git a/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch b/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch
new file mode 100644
index 00000000000000..3b4900fafba45b
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch
@@ -0,0 +1,99 @@
+From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 16:52:56 +0100
+Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag
+
+Some flag are missing from the original code.
+These clk can't be set using the protected-clock proprities as they
+cause the malfunction of the serial interface.
+These clks are needed for the rpm interface to work proprely or the
+cpu regulators starts to fail as soon as they are disabled by the
+kernel.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -65,6 +65,7 @@ static struct clk_pll pll3 = {
+ 		.parent_names = (const char *[]){ "pxo" },
+ 		.num_parents = 1,
+ 		.ops = &clk_pll_ops,
++		.flags = CLK_IS_CRITICAL,
+ 	},
+ };
+ 
+@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {
+ 			.parent_names = gcc_pxo_pll8,
+ 			.num_parents = 2,
+ 			.ops = &clk_rcg_ops,
+-			.flags = CLK_SET_PARENT_GATE,
++			.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
+@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =
+ 			.parent_names = (const char *[]){ "gsbi4_qup_src" },
+ 			.num_parents = 1,
+ 			.ops = &clk_branch_ops,
+-			.flags = CLK_SET_RATE_PARENT,
++			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
+@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {
+ 			.parent_names = gcc_pxo_pll8,
+ 			.num_parents = 2,
+ 			.ops = &clk_rcg_ops,
+-			.flags = CLK_SET_PARENT_GATE,
++			.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
+@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =
+ 			.parent_names = (const char *[]){ "gsbi7_qup_src" },
+ 			.num_parents = 1,
+ 			.ops = &clk_branch_ops,
+-			.flags = CLK_SET_RATE_PARENT,
++			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
+@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {
+ 		.hw.init = &(struct clk_init_data){
+ 			.name = "gsbi4_h_clk",
+ 			.ops = &clk_branch_ops,
++			.flags = CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
+@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = {
+ 			.parent_names = gcc_pxo_pll8,
+ 			.num_parents = 2,
+ 			.ops = &clk_rcg_ops,
++			.flags = CLK_SET_RATE_GATE,
+ 		},
+ 	}
+ };
+@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr
+ 			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ 			.num_parents = 5,
+ 			.ops = &clk_dyn_rcg_ops,
+-			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
++			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
++				 CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
+@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr
+ 			.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ 			.num_parents = 5,
+ 			.ops = &clk_dyn_rcg_ops,
+-			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
++			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
++				 CLK_IGNORE_UNUSED,
+ 		},
+ 	},
+ };
diff --git a/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch b/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch
new file mode 100644
index 00000000000000..cd2cb333564420
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch
@@ -0,0 +1,59 @@
+From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:00:07 +0100
+Subject: [PATCH 2/4] ipq806x: lcc: add missing reset
+
+Add missing reset for ipq806x lcc clk
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/lcc-ipq806x.c               | 8 ++++++++
+ include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 +
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/clk/qcom/lcc-ipq806x.c
++++ b/drivers/clk/qcom/lcc-ipq806x.c
+@@ -12,6 +12,7 @@
+ #include <linux/of_device.h>
+ #include <linux/clk-provider.h>
+ #include <linux/regmap.h>
++#include <linux/reset-controller.h>
+ 
+ #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
+ 
+@@ -22,6 +23,7 @@
+ #include "clk-branch.h"
+ #include "clk-regmap-divider.h"
+ #include "clk-regmap-mux.h"
++#include "reset.h"
+ 
+ static struct clk_pll pll4 = {
+ 	.l_reg = 0x4,
+@@ -39,6 +41,10 @@ static struct clk_pll pll4 = {
+ 	},
+ };
+ 
++static const struct qcom_reset_map lcc_ipq806x_resets[] = {
++	[LCC_PCM_RESET] = { 0x54, 13 },
++};
++
+ static const struct pll_config pll4_config = {
+ 	.l = 0xf,
+ 	.m = 0x91,
+@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq
+ 	.config = &lcc_ipq806x_regmap_config,
+ 	.clks = lcc_ipq806x_clks,
+ 	.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
++	.resets = lcc_ipq806x_resets,
++	.num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
+ };
+ 
+ static const struct of_device_id lcc_ipq806x_match_table[] = {
+--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h
++++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
+@@ -19,4 +19,5 @@
+ #define SPDIF_CLK			10
+ #define AHBIX_CLK			11
+ 
++#define LCC_PCM_RESET			0
+ #endif
diff --git a/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch b/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch
new file mode 100644
index 00000000000000..78068f359c43eb
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch
@@ -0,0 +1,57 @@
+From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:08:16 +0100
+Subject: [PATCH 3/4] clk: qcom: krait: add missing enable disable
+
+Add missing enable disable mux function. Add extra check to
+div2_round_rate.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/clk-krait.c
++++ b/drivers/clk/qcom/clk-krait.c
+@@ -73,7 +73,25 @@ static u8 krait_mux_get_parent(struct cl
+ 	return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
+ }
+ 
++static int krait_mux_enable(struct clk_hw *hw)
++{
++	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
++
++	__krait_mux_set_sel(mux, mux->en_mask);
++
++	return 0;
++}
++
++static void krait_mux_disable(struct clk_hw *hw)
++{
++	struct krait_mux_clk *mux = to_krait_mux_clk(hw);
++
++	__krait_mux_set_sel(mux, mux->safe_sel);
++}
++
+ const struct clk_ops krait_mux_clk_ops = {
++	.enable = krait_mux_enable,
++	.disable = krait_mux_disable,
+ 	.set_parent = krait_mux_set_parent,
+ 	.get_parent = krait_mux_get_parent,
+ 	.determine_rate = __clk_mux_determine_rate_closest,
+@@ -84,8 +102,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+ static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+ 				  unsigned long *parent_rate)
+ {
+-	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+-	return DIV_ROUND_UP(*parent_rate, 2);
++	struct clk_hw *hw_parent = clk_hw_get_parent(hw);
++
++	if (hw_parent) {
++		*parent_rate = clk_hw_round_rate(hw_parent, rate * 2);
++		return DIV_ROUND_UP(*parent_rate, 2);
++	} else
++		return -1;
+ }
+ 
+ static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
diff --git a/target/linux/ipq806x/patches-5.4/999-02-nss-core-and-crypto-clocks.patch b/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
similarity index 57%
rename from target/linux/ipq806x/patches-5.4/999-02-nss-core-and-crypto-clocks.patch
rename to target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
index 3706c1369cc60b..d1e047cabf02bb 100644
--- a/target/linux/ipq806x/patches-5.4/999-02-nss-core-and-crypto-clocks.patch
+++ b/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
@@ -1,51 +1,21 @@
---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
-@@ -240,7 +240,7 @@
- #define PLL14					232
- #define PLL14_VOTE				233
- #define PLL18					234
--#define CE5_SRC					235
-+#define CE5_A_CLK				235
- #define CE5_H_CLK				236
- #define CE5_CORE_CLK				237
- #define CE3_SLEEP_CLK				238
-@@ -283,5 +283,9 @@
- #define EBI2_AON_CLK				281
- #define NSSTCM_CLK_SRC				282
- #define NSSTCM_CLK				283
-+#define NSS_CORE_CLK				284 /* Virtual */
-+#define CE5_A_CLK_SRC				285
-+#define CE5_H_CLK_SRC				286
-+#define CE5_CORE_CLK_SRC			287
- 
- #endif
---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
-+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
-@@ -163,5 +163,10 @@
- #define NSS_CAL_PRBS_RST_N_RESET			154
- #define NSS_LCKDT_RST_N_RESET				155
- #define NSS_SRDS_N_RESET				156
-+#define CRYPTO_ENG1_RESET				157
-+#define CRYPTO_ENG2_RESET				158
-+#define CRYPTO_ENG3_RESET				159
-+#define CRYPTO_ENG4_RESET				160
-+#define CRYPTO_AHB_RESET				161
- 
- #endif
+From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:23:38 +0100
+Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
+
+Add missing clk and reset needed for nss additional core and crypto
+engine.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c               | 250 +++++++++++++++++++
+ include/dt-bindings/clock/qcom,gcc-ipq806x.h |   5 +-
+ include/dt-bindings/reset/qcom,gcc-ipq806x.h |   5 +
+ 3 files changed, 259 insertions(+), 1 deletion(-)
+
 --- a/drivers/clk/qcom/gcc-ipq806x.c
 +++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -24,6 +24,10 @@
- #include "clk-branch.h"
- #include "clk-hfpll.h"
- #include "reset.h"
-+#include <linux/regulator/nss-volt-ipq806x.h>
-+
-+/* NSS safe parent index which will be used during NSS PLL rate change */
-+static int gcc_ipq806x_nss_safe_parent;
- 
- static struct clk_pll pll0 = {
- 	.l_reg = 0x30c4,
-@@ -222,7 +226,9 @@ static struct clk_regmap pll14_vote = {
+@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
  
  static struct pll_freq_tbl pll18_freq_tbl[] = {
  	NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
@@ -55,7 +25,7 @@
  };
  
  static struct clk_pll pll18 = {
-@@ -244,6 +250,22 @@ static struct clk_pll pll18 = {
+@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
  	},
  };
  
@@ -78,7 +48,7 @@
  enum {
  	P_PXO,
  	P_PLL8,
-@@ -252,6 +274,7 @@ enum {
+@@ -253,6 +271,7 @@ enum {
  	P_CXO,
  	P_PLL14,
  	P_PLL18,
@@ -86,7 +56,7 @@
  };
  
  static const struct parent_map gcc_pxo_pll8_map[] = {
-@@ -319,6 +342,42 @@ static const char * const gcc_pxo_pll8_p
+@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p
  	"pll18",
  };
  
@@ -129,7 +99,15 @@
  static struct freq_tbl clk_tbl_gsbi_uart[] = {
  	{  1843200, P_PLL8, 2,  6, 625 },
  	{  3686400, P_PLL8, 2, 12, 625 },
-@@ -2643,7 +2702,9 @@ static const struct freq_tbl clk_tbl_nss
+@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc
+ 	{  20210000, P_PLL8,  1, 1,  19 },
+ 	{  24000000, P_PLL8,  4, 1,   4 },
+ 	{  48000000, P_PLL8,  4, 1,   2 },
++	{  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
+ 	{  64000000, P_PLL8,  3, 1,   2 },
+ 	{  96000000, P_PLL8,  4, 0,   0 },
+ 	{ 192000000, P_PLL8,  2, 0,   0 },
+@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss
  	{ 110000000, P_PLL18, 1, 1, 5 },
  	{ 275000000, P_PLL18, 2, 0, 0 },
  	{ 550000000, P_PLL18, 1, 0, 0 },
@@ -139,7 +117,7 @@
  	{ }
  };
  
-@@ -2753,6 +2814,319 @@ static struct clk_dyn_rcg ubi32_core2_sr
+@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
  	},
  };
  
@@ -322,144 +300,11 @@
 +		},
 +	},
 +};
-+
-+static int nss_core_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-+				 unsigned long parent_rate)
-+{
-+	int ret;
-+
-+	/*
-+	 * When ramping up voltage, it needs to be done first. This ensures that
-+	 * the volt required will be available when you step up the frequency.
-+	 */
-+	ret = nss_ramp_voltage(rate, true);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_dyn_rcg_ops.set_rate(&ubi32_core1_src_clk.clkr.hw, rate,
-+				    parent_rate);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_dyn_rcg_ops.set_rate(&ubi32_core2_src_clk.clkr.hw, rate,
-+				    parent_rate);
-+
-+	if (ret)
-+		return ret;
-+
-+	/*
-+	 * When ramping down voltage, it needs to be set first. This ensures
-+	 * that the volt required will be available until you step down the
-+	 * frequency.
-+	 */
-+	ret = nss_ramp_voltage(rate, false);
-+
-+	return ret;
-+}
-+
-+static int
-+nss_core_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
-+				 unsigned long parent_rate, u8 index)
-+{
-+	int ret;
-+
-+	/*
-+	 * When ramping up voltage needs to be done first. This ensures that
-+	 * the voltage required will be available when you step up the
-+	 * frequency.
-+	 */
-+	ret = nss_ramp_voltage(rate, true);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_dyn_rcg_ops.set_rate_and_parent(
-+			&ubi32_core1_src_clk.clkr.hw, rate, parent_rate, index);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_dyn_rcg_ops.set_rate_and_parent(
-+			&ubi32_core2_src_clk.clkr.hw, rate, parent_rate, index);
-+
-+	if (ret)
-+		return ret;
-+
-+	/*
-+	 * When ramping down voltage needs to be done last. This ensures that
-+	 * the voltage required will be available when you step down the
-+	 * frequency.
-+	 */
-+	ret = nss_ramp_voltage(rate, false);
-+
-+	return ret;
-+}
-+
-+static int nss_core_clk_determine_rate(struct clk_hw *hw,
-+					struct clk_rate_request *req)
-+{
-+	return clk_dyn_rcg_ops.determine_rate(&ubi32_core1_src_clk.clkr.hw,
-+						req);
-+}
-+
-+static unsigned long
-+nss_core_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+	return clk_dyn_rcg_ops.recalc_rate(&ubi32_core1_src_clk.clkr.hw,
-+						 parent_rate);
-+}
-+
-+static u8 nss_core_clk_get_parent(struct clk_hw *hw)
-+{
-+	return clk_dyn_rcg_ops.get_parent(&ubi32_core1_src_clk.clkr.hw);
-+}
-+
-+static int nss_core_clk_set_parent(struct clk_hw *hw, u8 i)
-+{
-+	int ret;
-+	struct clk_dyn_rcg *rcg;
-+	struct freq_tbl f = {  200000000, P_PLL0, 2,  1, 2 };
-+
-+	/* P_PLL0 is 800 Mhz which needs to be divided for 200 Mhz */
-+	if (i == gcc_ipq806x_nss_safe_parent) {
-+		rcg = to_clk_dyn_rcg(&ubi32_core1_src_clk.clkr.hw);
-+		clk_dyn_configure_bank(rcg, &f);
-+
-+		rcg = to_clk_dyn_rcg(&ubi32_core2_src_clk.clkr.hw);
-+		clk_dyn_configure_bank(rcg, &f);
-+
-+		return 0;
-+	}
-+
-+	ret = clk_dyn_rcg_ops.set_parent(&ubi32_core1_src_clk.clkr.hw, i);
-+	if (ret)
-+		return ret;
-+
-+	return clk_dyn_rcg_ops.set_parent(&ubi32_core2_src_clk.clkr.hw, i);
-+}
-+
-+static const struct clk_ops clk_ops_nss_core = {
-+	.set_rate = nss_core_clk_set_rate,
-+	.set_rate_and_parent = nss_core_clk_set_rate_and_parent,
-+	.determine_rate = nss_core_clk_determine_rate,
-+	.recalc_rate = nss_core_clk_recalc_rate,
-+	.get_parent = nss_core_clk_get_parent,
-+	.set_parent = nss_core_clk_set_parent,
-+};
-+
-+/* Virtual clock for nss core clocks */
-+static struct clk_regmap nss_core_clk = {
-+	.hw.init = &(struct clk_init_data){
-+		.name = "nss_core_clk",
-+		.ops = &clk_ops_nss_core,
-+		.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+		.num_parents = 5,
-+		.flags = CLK_SET_RATE_PARENT,
-+	},
-+};
 +
  static struct clk_regmap *gcc_ipq806x_clks[] = {
  	[PLL0] = &pll0.clkr,
  	[PLL0_VOTE] = &pll0_vote,
-@@ -2760,6 +3134,7 @@ static struct clk_regmap *gcc_ipq806x_cl
+@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl
  	[PLL4_VOTE] = &pll4_vote,
  	[PLL8] = &pll8.clkr,
  	[PLL8_VOTE] = &pll8_vote,
@@ -467,11 +312,7 @@
  	[PLL14] = &pll14.clkr,
  	[PLL14_VOTE] = &pll14_vote,
  	[PLL18] = &pll18.clkr,
-@@ -2871,9 +3246,16 @@ static struct clk_regmap *gcc_ipq806x_cl
- 	[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
- 	[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
- 	[NSSTCM_CLK] = &nss_tcm_clk.clkr,
-+	[NSS_CORE_CLK] = &nss_core_clk,
+@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl
  	[PLL9] = &hfpll0.clkr,
  	[PLL10] = &hfpll1.clkr,
  	[PLL12] = &hfpll_l2.clkr,
@@ -484,7 +325,7 @@
  };
  
  static const struct qcom_reset_map gcc_ipq806x_resets[] = {
-@@ -3005,6 +3387,11 @@ static const struct qcom_reset_map gcc_i
+@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i
  	[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
  	[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
  	[GMAC_AHB_RESET] = { 0x3e24, 0 },
@@ -496,40 +337,36 @@
  	[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
  	[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
  	[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
-@@ -3080,6 +3467,12 @@ static int gcc_ipq806x_probe(struct plat
- 	if (!regmap)
- 		return -ENODEV;
+--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+@@ -240,7 +240,7 @@
+ #define PLL14					232
+ #define PLL14_VOTE				233
+ #define PLL18					234
+-#define CE5_SRC					235
++#define CE5_A_CLK				235
+ #define CE5_H_CLK				236
+ #define CE5_CORE_CLK				237
+ #define CE3_SLEEP_CLK				238
+@@ -283,5 +283,8 @@
+ #define EBI2_AON_CLK				281
+ #define NSSTCM_CLK_SRC				282
+ #define NSSTCM_CLK				283
++#define CE5_A_CLK_SRC				285
++#define CE5_H_CLK_SRC				286
++#define CE5_CORE_CLK_SRC			287
  
-+	gcc_ipq806x_nss_safe_parent = qcom_find_src_index(&nss_core_clk.hw,
-+					gcc_pxo_pll8_pll14_pll18_pll0_map,
-+					P_PLL0);
-+	if (gcc_ipq806x_nss_safe_parent < 0)
-+		return gcc_ipq806x_nss_safe_parent;
-+
- 	/* Setup PLL18 static bits */
- 	regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
- 	regmap_write(regmap, 0x31b0, 0x3080);
---- a/drivers/clk/qcom/clk-rcg.c
-+++ b/drivers/clk/qcom/clk-rcg.c
-@@ -805,6 +805,11 @@ static int clk_dyn_rcg_set_rate_and_pare
- 	return __clk_dyn_rcg_set_rate(hw, rate);
- }
+ #endif
+--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+@@ -163,5 +163,10 @@
+ #define NSS_CAL_PRBS_RST_N_RESET			154
+ #define NSS_LCKDT_RST_N_RESET				155
+ #define NSS_SRDS_N_RESET				156
++#define CRYPTO_ENG1_RESET				157
++#define CRYPTO_ENG2_RESET				158
++#define CRYPTO_ENG3_RESET				159
++#define CRYPTO_ENG4_RESET				160
++#define CRYPTO_AHB_RESET				161
  
-+void clk_dyn_configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
-+{
-+	configure_bank(rcg, f);
-+}
-+
- const struct clk_ops clk_rcg_ops = {
- 	.enable = clk_enable_regmap,
- 	.disable = clk_disable_regmap,
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -173,4 +173,7 @@ struct clk_rcg_dfs_data {
- extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
- 				    const struct clk_rcg_dfs_data *rcgs,
- 				    size_t len);
-+ 
-+extern void clk_dyn_configure_bank(struct clk_dyn_rcg *rcg,
-+					const struct freq_tbl *f);
  #endif
diff --git a/target/linux/ipq806x/patches-5.4/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch b/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
similarity index 98%
rename from target/linux/ipq806x/patches-5.4/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
rename to target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
index 597598e8a91a8f..d3677253f6d609 100644
--- a/target/linux/ipq806x/patches-5.4/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
+++ b/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
@@ -29,7 +29,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
 
 --- a/drivers/cpufreq/Kconfig.arm
 +++ b/drivers/cpufreq/Kconfig.arm
-@@ -155,6 +155,18 @@ config ARM_QCOM_CPUFREQ_HW
+@@ -150,6 +150,18 @@ config ARM_QCOM_CPUFREQ_HW
  	  The driver implements the cpufreq interface for this HW engine.
  	  Say Y if you want to support CPUFreq HW.
  
@@ -48,7 +48,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  config ARM_RASPBERRYPI_CPUFREQ
  	tristate "Raspberry Pi cpufreq support"
  	depends on CLK_RASPBERRYPI || COMPILE_TEST
-@@ -338,4 +350,4 @@ config ARM_PXA2xx_CPUFREQ
+@@ -339,4 +351,4 @@ config ARM_PXA2xx_CPUFREQ
  	help
  	  This add the CPUFreq driver support for Intel PXA2xx SOCs.
  
@@ -57,7 +57,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
 \ No newline at end of file
 --- a/drivers/cpufreq/Makefile
 +++ b/drivers/cpufreq/Makefile
-@@ -65,6 +65,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2
+@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2
  obj-$(CONFIG_PXA3xx)			+= pxa3xx-cpufreq.o
  obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW)	+= qcom-cpufreq-hw.o
  obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)	+= qcom-cpufreq-nvmem.o
@@ -65,8 +65,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) 	+= raspberrypi-cpufreq.o
  obj-$(CONFIG_ARM_S3C2410_CPUFREQ)	+= s3c2410-cpufreq.o
  obj-$(CONFIG_ARM_S3C2412_CPUFREQ)	+= s3c2412-cpufreq.o
-@@ -87,6 +88,7 @@ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ)	+= te
- obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)	+= tegra186-cpufreq.o
+@@ -86,6 +87,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)	+= te
+ obj-$(CONFIG_ARM_TEGRA194_CPUFREQ)	+= tegra194-cpufreq.o
  obj-$(CONFIG_ARM_TI_CPUFREQ)		+= ti-cpufreq.o
  obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ)	+= vexpress-spc-cpufreq.o
 +obj-$(CONFIG_ARM_KRAIT_CPUFREQ)		+= krait-cpufreq.o
@@ -387,7 +387,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
 +	policy->cpuinfo.transition_latency = transition_latency;
 +	policy->dvfs_possible_from_any_cpu = true;
 +
-+	dev_pm_opp_of_register_em(policy->cpus);
++	dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
 +
 +	return 0;
 +
diff --git a/target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch b/target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
rename to target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
diff --git a/target/linux/ipq806x/patches-5.4/098-3-add-fab-scaling-support-with-cpufreq.patch b/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/098-3-add-fab-scaling-support-with-cpufreq.patch
rename to target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch
diff --git a/target/linux/ipq806x/patches-5.4/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch b/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch
similarity index 97%
rename from target/linux/ipq806x/patches-5.4/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch
rename to target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch
index 60b430afc1f78d..37501bc64b335d 100644
--- a/target/linux/ipq806x/patches-5.4/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch
+++ b/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch
@@ -203,7 +203,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  	host->use_ecc = true;
  	clear_bam_transaction(nandc);
  
-@@ -2781,6 +2840,7 @@ static int qcom_nand_host_init_and_regis
+@@ -2805,6 +2864,7 @@ static int qcom_nand_host_init_and_regis
  	struct nand_chip *chip = &host->chip;
  	struct mtd_info *mtd = nand_to_mtd(chip);
  	struct device *dev = nandc->dev;
@@ -211,7 +211,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  	int ret;
  
  	ret = of_property_read_u32(dn, "reg", &host->cs);
-@@ -2841,6 +2901,17 @@ static int qcom_nand_host_init_and_regis
+@@ -2865,6 +2925,17 @@ static int qcom_nand_host_init_and_regis
  	if (ret)
  		nand_cleanup(chip);
  
@@ -229,7 +229,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  	return ret;
  }
  
-@@ -3001,6 +3072,7 @@ static int qcom_nandc_remove(struct plat
+@@ -3030,6 +3101,7 @@ static int qcom_nandc_remove(struct plat
  static const struct qcom_nandc_props ipq806x_nandc_props = {
  	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
  	.is_bam = false,
diff --git a/target/linux/ipq806x/patches-5.4/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch b/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch
rename to target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch
diff --git a/target/linux/ipq806x/patches-5.4/100-v5.11-dmaengine-qcom-add_ADM_driver.patch b/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/100-v5.11-dmaengine-qcom-add_ADM_driver.patch
rename to target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch
diff --git a/target/linux/ipq806x/patches-5.4/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch b/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch
rename to target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch
diff --git a/target/linux/ipq806x/patches-5.4/100-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch b/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch
similarity index 92%
rename from target/linux/ipq806x/patches-5.4/100-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch
rename to target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch
index be026bfac8df46..2210f4e2492283 100644
--- a/target/linux/ipq806x/patches-5.4/100-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch
+++ b/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch
@@ -18,7 +18,7 @@
  #define QSGMII_PCS_CAL_LCKDT_CTL		0x120
  #define QSGMII_PCS_CAL_LCKDT_CTL_RST		BIT(19)
  
-@@ -241,6 +252,36 @@ static void ipq806x_gmac_fix_mac_speed(v
+@@ -242,6 +253,36 @@ static void ipq806x_gmac_fix_mac_speed(v
  	ipq806x_gmac_set_speed(gmac, speed);
  }
  
@@ -55,7 +55,7 @@
  static int ipq806x_gmac_probe(struct platform_device *pdev)
  {
  	struct plat_stmmacenet_data *plat_dat;
-@@ -249,6 +290,7 @@ static int ipq806x_gmac_probe(struct pla
+@@ -250,6 +291,7 @@ static int ipq806x_gmac_probe(struct pla
  	struct ipq806x_gmac *gmac;
  	int val;
  	int err;
@@ -63,7 +63,7 @@
  
  	val = stmmac_get_platform_resources(pdev, &stmmac_res);
  	if (val)
-@@ -338,6 +380,17 @@ static int ipq806x_gmac_probe(struct pla
+@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla
  			     0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
  			     0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
  			     0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
diff --git a/target/linux/ipq806x/patches-5.4/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
similarity index 100%
rename from target/linux/ipq806x/patches-5.4/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
rename to target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
diff --git a/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch b/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch
new file mode 100644
index 00000000000000..5f422c1dde7e88
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch
@@ -0,0 +1,285 @@
+From 5c7d1181056feef0b58fb2f556f55e170ba5b479 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sat, 25 Jul 2020 19:14:59 +0200
+Subject: [PATCH 01/10] drivers: thermal: tsens: Add VER_0 tsens version
+
+VER_0 is used to describe device based on tsens version before v0.1.
+These device are devices based on msm8960 for example apq8064 or
+ipq806x.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
+Reported-by: kernel test robot <lkp@intel.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+---
+ drivers/thermal/qcom/tsens.c | 150 ++++++++++++++++++++++++++++-------
+ drivers/thermal/qcom/tsens.h |   4 +-
+ 2 files changed, 124 insertions(+), 30 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -12,6 +12,7 @@
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm.h>
+ #include <linux/regmap.h>
+@@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int
+ 			dev_dbg(priv->dev, "[%u] %s: no violation:  %d\n",
+ 				hw_id, __func__, temp);
+ 		}
++
++		if (tsens_version(priv) < VER_0_1) {
++			/* Constraint: There is only 1 interrupt control register for all
++			 * 11 temperature sensor. So monitoring more than 1 sensor based
++			 * on interrupts will yield inconsistent result. To overcome this
++			 * issue we will monitor only sensor 0 which is the master sensor.
++			 */
++			break;
++		}
+ 	}
+ 
+ 	return IRQ_HANDLED;
+@@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor
+ 	int high_val, low_val, cl_high, cl_low;
+ 	u32 hw_id = s->hw_id;
+ 
++	if (tsens_version(priv) < VER_0_1) {
++		/* Pre v0.1 IP had a single register for each type of interrupt
++		 * and thresholds
++		 */
++		hw_id = 0;
++	}
++
+ 	dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
+ 		hw_id, __func__, low, high);
+ 
+@@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct ts
+ 	u32 valid;
+ 	int ret;
+ 
+-	ret = regmap_field_read(priv->rf[valid_idx], &valid);
+-	if (ret)
+-		return ret;
+-	while (!valid) {
+-		/* Valid bit is 0 for 6 AHB clock cycles.
+-		 * At 19.2MHz, 1 AHB clock is ~60ns.
+-		 * We should enter this loop very, very rarely.
+-		 */
+-		ndelay(400);
++	/* VER_0 doesn't have VALID bit */
++	if (tsens_version(priv) >= VER_0_1) {
+ 		ret = regmap_field_read(priv->rf[valid_idx], &valid);
+ 		if (ret)
+ 			return ret;
++		while (!valid) {
++			/* Valid bit is 0 for 6 AHB clock cycles.
++			 * At 19.2MHz, 1 AHB clock is ~60ns.
++			 * We should enter this loop very, very rarely.
++			 */
++			ndelay(400);
++			ret = regmap_field_read(priv->rf[valid_idx], &valid);
++			if (ret)
++				return ret;
++		}
+ 	}
+ 
+ 	/* Valid bit is set, OK to read the temperature */
+@@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_s
+ {
+ 	struct tsens_priv *priv = s->priv;
+ 	int hw_id = s->hw_id;
+-	int last_temp = 0, ret;
++	int last_temp = 0, ret, trdy;
++	unsigned long timeout;
+ 
+-	ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
+-	if (ret)
+-		return ret;
++	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
++	do {
++		if (tsens_version(priv) == VER_0) {
++			ret = regmap_field_read(priv->rf[TRDY], &trdy);
++			if (ret)
++				return ret;
++			if (!trdy)
++				continue;
++		}
+ 
+-	*temp = code_to_degc(last_temp, s) * 1000;
++		ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
++		if (ret)
++			return ret;
+ 
+-	return 0;
++		*temp = code_to_degc(last_temp, s) * 1000;
++
++		return 0;
++	} while (time_before(jiffies, timeout));
++
++	return -ETIMEDOUT;
+ }
+ 
+ #ifdef CONFIG_DEBUG_FS
+@@ -738,19 +772,34 @@ int __init init_common(struct tsens_priv
+ 		priv->tm_offset = 0x1000;
+ 	}
+ 
+-	res = platform_get_resource(op, IORESOURCE_MEM, 0);
+-	tm_base = devm_ioremap_resource(dev, res);
+-	if (IS_ERR(tm_base)) {
+-		ret = PTR_ERR(tm_base);
+-		goto err_put_device;
++	if (tsens_version(priv) >= VER_0_1) {
++		res = platform_get_resource(op, IORESOURCE_MEM, 0);
++		tm_base = devm_ioremap_resource(dev, res);
++		if (IS_ERR(tm_base)) {
++			ret = PTR_ERR(tm_base);
++			goto err_put_device;
++		}
++
++		priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
++	} else { /* VER_0 share the same gcc regs using a syscon */
++		struct device *parent = priv->dev->parent;
++
++		if (parent)
++			priv->tm_map = syscon_node_to_regmap(parent->of_node);
+ 	}
+ 
+-	priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
+-	if (IS_ERR(priv->tm_map)) {
+-		ret = PTR_ERR(priv->tm_map);
++	if (IS_ERR_OR_NULL(priv->tm_map)) {
++		if (!priv->tm_map)
++			ret = -ENODEV;
++		else
++			ret = PTR_ERR(priv->tm_map);
+ 		goto err_put_device;
+ 	}
+ 
++	/* VER_0 have only tm_map */
++	if (!priv->srot_map)
++		priv->srot_map = priv->tm_map;
++
+ 	if (tsens_version(priv) > VER_0_1) {
+ 		for (i = VER_MAJOR; i <= VER_STEP; i++) {
+ 			priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
+@@ -771,6 +820,10 @@ int __init init_common(struct tsens_priv
+ 		ret = PTR_ERR(priv->rf[TSENS_EN]);
+ 		goto err_put_device;
+ 	}
++	/* in VER_0 TSENS need to be explicitly enabled */
++	if (tsens_version(priv) == VER_0)
++		regmap_field_write(priv->rf[TSENS_EN], 1);
++
+ 	ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
+ 	if (ret)
+ 		goto err_put_device;
+@@ -793,6 +846,19 @@ int __init init_common(struct tsens_priv
+ 		goto err_put_device;
+ 	}
+ 
++	priv->rf[TSENS_SW_RST] =
++		devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]);
++	if (IS_ERR(priv->rf[TSENS_SW_RST])) {
++		ret = PTR_ERR(priv->rf[TSENS_SW_RST]);
++		goto err_put_device;
++	}
++
++	priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]);
++	if (IS_ERR(priv->rf[TRDY])) {
++		ret = PTR_ERR(priv->rf[TRDY]);
++		goto err_put_device;
++	}
++
+ 	/* This loop might need changes if enum regfield_ids is reordered */
+ 	for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
+ 		for (i = 0; i < priv->feat->max_sensors; i++) {
+@@ -808,7 +874,7 @@ int __init init_common(struct tsens_priv
+ 		}
+ 	}
+ 
+-	if (priv->feat->crit_int) {
++	if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) {
+ 		/* Loop might need changes if enum regfield_ids is reordered */
+ 		for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {
+ 			for (i = 0; i < priv->feat->max_sensors; i++) {
+@@ -846,7 +912,11 @@ int __init init_common(struct tsens_priv
+ 	}
+ 
+ 	spin_lock_init(&priv->ul_lock);
+-	tsens_enable_irq(priv);
++
++	/* VER_0 interrupt doesn't need to be enabled */
++	if (tsens_version(priv) >= VER_0_1)
++		tsens_enable_irq(priv);
++
+ 	tsens_debug_init(op);
+ 
+ err_put_device:
+@@ -951,10 +1021,19 @@ static int tsens_register_irq(struct tse
+ 		if (irq == -ENXIO)
+ 			ret = 0;
+ 	} else {
+-		ret = devm_request_threaded_irq(&pdev->dev, irq,
+-						NULL, thread_fn,
+-						IRQF_ONESHOT,
+-						dev_name(&pdev->dev), priv);
++		/* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */
++		if (tsens_version(priv) == VER_0)
++			ret = devm_request_threaded_irq(&pdev->dev, irq,
++							thread_fn, NULL,
++							IRQF_TRIGGER_RISING,
++							dev_name(&pdev->dev),
++							priv);
++		else
++			ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
++							thread_fn, IRQF_ONESHOT,
++							dev_name(&pdev->dev),
++							priv);
++
+ 		if (ret)
+ 			dev_err(&pdev->dev, "%s: failed to get irq\n",
+ 				__func__);
+@@ -983,6 +1062,19 @@ static int tsens_register(struct tsens_p
+ 			priv->ops->enable(priv, i);
+ 	}
+ 
++	/* VER_0 require to set MIN and MAX THRESH
++	 * These 2 regs are set using the:
++	 * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C
++	 * - CRIT_THRESH_1 for MIN THRESH hardcoded to   0°C
++	 */
++	if (tsens_version(priv) < VER_0_1) {
++		regmap_field_write(priv->rf[CRIT_THRESH_0],
++				   tsens_mC_to_hw(priv->sensor, 120000));
++
++		regmap_field_write(priv->rf[CRIT_THRESH_1],
++				   tsens_mC_to_hw(priv->sensor, 0));
++	}
++
+ 	ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
+ 	if (ret < 0)
+ 		return ret;
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -13,6 +13,7 @@
+ #define CAL_DEGC_PT2		120
+ #define SLOPE_FACTOR		1000
+ #define SLOPE_DEFAULT		3200
++#define TIMEOUT_US		100
+ #define THRESHOLD_MAX_ADC_CODE	0x3ff
+ #define THRESHOLD_MIN_ADC_CODE	0x0
+ 
+@@ -25,7 +26,8 @@ struct tsens_priv;
+ 
+ /* IP version numbers in ascending order */
+ enum tsens_ver {
+-	VER_0_1 = 0,
++	VER_0 = 0,
++	VER_0_1,
+ 	VER_1_X,
+ 	VER_2_X,
+ };
diff --git a/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch b/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch
new file mode 100644
index 00000000000000..109f524bbd05a4
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch
@@ -0,0 +1,28 @@
+From efa0d50a6c5ec7619371dfe4d3e6ca54b73787d5 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 25 Nov 2020 16:47:21 +0100
+Subject: [PATCH 02/10] drivers: thermal: tsens: Don't hardcode sensor slope
+
+Function compute_intercept_slope hardcode the sensor slope to
+SLOPE_DEFAULT. Change this and use the default value only if a slope is
+not defined. This is needed for tsens VER_0 that has a hardcoded slope
+table.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsen
+ 			"%s: sensor%d - data_point1:%#x data_point2:%#x\n",
+ 			__func__, i, p1[i], p2[i]);
+ 
+-		priv->sensor[i].slope = SLOPE_DEFAULT;
++		if (!priv->sensor[i].slope)
++			priv->sensor[i].slope = SLOPE_DEFAULT;
+ 		if (mode == TWO_PT_CALIB) {
+ 			/*
+ 			 * slope (m) = adc_code2 - adc_code1 (y2 - y1)/
diff --git a/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch b/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch
new file mode 100644
index 00000000000000..bf378107c60251
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch
@@ -0,0 +1,119 @@
+From 6bac2e2fa36c2d7c304768a689d8b73155b90aa2 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 25 Nov 2020 17:15:51 +0100
+Subject: [PATCH 03/10] drivers: thermal: tsens: Convert msm8960 to reg_field
+
+Convert msm9860 driver to reg_field to use the init_common
+function.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 80 ++++++++++++++++++++++++++++++-
+ 1 file changed, 79 insertions(+), 1 deletion(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -51,11 +51,22 @@
+ #define MIN_LIMIT_TH		0x0
+ #define MAX_LIMIT_TH		0xff
+ 
+-#define S0_STATUS_ADDR		0x3628
+ #define INT_STATUS_ADDR		0x363c
+ #define TRDY_MASK		BIT(7)
+ #define TIMEOUT_US		100
+ 
++#define S0_STATUS_OFF		0x3628
++#define S1_STATUS_OFF		0x362c
++#define S2_STATUS_OFF		0x3630
++#define S3_STATUS_OFF		0x3634
++#define S4_STATUS_OFF		0x3638
++#define S5_STATUS_OFF		0x3664  /* Sensors 5-10 found on apq8064/msm8960 */
++#define S6_STATUS_OFF		0x3668
++#define S7_STATUS_OFF		0x366c
++#define S8_STATUS_OFF		0x3670
++#define S9_STATUS_OFF		0x3674
++#define S10_STATUS_OFF		0x3678
++
+ static int suspend_8960(struct tsens_priv *priv)
+ {
+ 	int ret;
+@@ -269,6 +280,71 @@ static int get_temp_8960(const struct ts
+ 	return -ETIMEDOUT;
+ }
+ 
++static struct tsens_features tsens_8960_feat = {
++	.ver_major	= VER_0,
++	.crit_int	= 0,
++	.adc		= 1,
++	.srot_split	= 0,
++	.max_sensors	= 11,
++};
++
++static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {
++	/* ----- SROT ------ */
++	/* No VERSION information */
++
++	/* CNTL */
++	[TSENS_EN]     = REG_FIELD(CNTL_ADDR,  0, 0),
++	[TSENS_SW_RST] = REG_FIELD(CNTL_ADDR,  1, 1),
++	/* 8960 has 5 sensors, 8660 has 11, we only handle 5 */
++	[SENSOR_EN]    = REG_FIELD(CNTL_ADDR,  3, 7),
++
++	/* ----- TM ------ */
++	/* INTERRUPT ENABLE */
++	/* NO INTERRUPT ENABLE */
++
++	/* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */
++	[LOW_THRESH_0]   = REG_FIELD(THRESHOLD_ADDR,  0,  7),
++	[UP_THRESH_0]    = REG_FIELD(THRESHOLD_ADDR,  8, 15),
++	/* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield
++	 * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp
++	 * MIN_THRESH_0 -> CRIT_THRESH_1
++	 * MAX_THRESH_0 -> CRIT_THRESH_0
++	 */
++	[CRIT_THRESH_1]   = REG_FIELD(THRESHOLD_ADDR, 16, 23),
++	[CRIT_THRESH_0]   = REG_FIELD(THRESHOLD_ADDR, 24, 31),
++
++	/* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */
++	/* 1 == clear, 0 == normal operation */
++	[LOW_INT_CLEAR_0]   = REG_FIELD(CNTL_ADDR,  9,  9),
++	[UP_INT_CLEAR_0]    = REG_FIELD(CNTL_ADDR, 10, 10),
++
++	/* NO CRITICAL INTERRUPT SUPPORT on 8960 */
++
++	/* Sn_STATUS */
++	[LAST_TEMP_0]  = REG_FIELD(S0_STATUS_OFF,  0,  7),
++	[LAST_TEMP_1]  = REG_FIELD(S1_STATUS_OFF,  0,  7),
++	[LAST_TEMP_2]  = REG_FIELD(S2_STATUS_OFF,  0,  7),
++	[LAST_TEMP_3]  = REG_FIELD(S3_STATUS_OFF,  0,  7),
++	[LAST_TEMP_4]  = REG_FIELD(S4_STATUS_OFF,  0,  7),
++	[LAST_TEMP_5]  = REG_FIELD(S5_STATUS_OFF,  0,  7),
++	[LAST_TEMP_6]  = REG_FIELD(S6_STATUS_OFF,  0,  7),
++	[LAST_TEMP_7]  = REG_FIELD(S7_STATUS_OFF,  0,  7),
++	[LAST_TEMP_8]  = REG_FIELD(S8_STATUS_OFF,  0,  7),
++	[LAST_TEMP_9]  = REG_FIELD(S9_STATUS_OFF,  0,  7),
++	[LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0,  7),
++
++	/* No VALID field on 8960 */
++	/* TSENS_INT_STATUS bits: 1 == threshold violated */
++	[MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0),
++	[LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1),
++	[UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2),
++	/* No CRITICAL field on 8960 */
++	[MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3),
++
++	/* TRDY: 1=ready, 0=in progress */
++	[TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7),
++};
++
+ static const struct tsens_ops ops_8960 = {
+ 	.init		= init_8960,
+ 	.calibrate	= calibrate_8960,
+@@ -282,4 +358,6 @@ static const struct tsens_ops ops_8960 =
+ struct tsens_plat_data data_8960 = {
+ 	.num_sensors	= 11,
+ 	.ops		= &ops_8960,
++	.feat		= &tsens_8960_feat,
++	.fields		= tsens_8960_regfields,
+ };
diff --git a/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch b/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch
new file mode 100644
index 00000000000000..ae8a52c100c398
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch
@@ -0,0 +1,81 @@
+From c04f98a496929f75d75c65115d5717423c3d0634 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 25 Nov 2020 17:16:36 +0100
+Subject: [PATCH 04/10] drivers: thermal: tsens: Use init_common for msm8960
+
+Use init_common and drop custom init for msm8960.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------
+ 1 file changed, 1 insertion(+), 51 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -173,56 +173,6 @@ static void disable_8960(struct tsens_pr
+ 	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ }
+ 
+-static int init_8960(struct tsens_priv *priv)
+-{
+-	int ret, i;
+-	u32 reg_cntl;
+-
+-	priv->tm_map = dev_get_regmap(priv->dev, NULL);
+-	if (!priv->tm_map)
+-		return -ENODEV;
+-
+-	/*
+-	 * The status registers for each sensor are discontiguous
+-	 * because some SoCs have 5 sensors while others have more
+-	 * but the control registers stay in the same place, i.e
+-	 * directly after the first 5 status registers.
+-	 */
+-	for (i = 0; i < priv->num_sensors; i++) {
+-		if (i >= 5)
+-			priv->sensor[i].status = S0_STATUS_ADDR + 40;
+-		priv->sensor[i].status += i * 4;
+-	}
+-
+-	reg_cntl = SW_RST;
+-	ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
+-	if (ret)
+-		return ret;
+-
+-	if (priv->num_sensors > 1) {
+-		reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
+-		reg_cntl &= ~SW_RST;
+-		ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
+-					 CONFIG_MASK, CONFIG);
+-	} else {
+-		reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
+-		reg_cntl &= ~CONFIG_MASK_8660;
+-		reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
+-	}
+-
+-	reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
+-	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+-	if (ret)
+-		return ret;
+-
+-	reg_cntl |= EN;
+-	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+-	if (ret)
+-		return ret;
+-
+-	return 0;
+-}
+-
+ static int calibrate_8960(struct tsens_priv *priv)
+ {
+ 	int i;
+@@ -346,7 +296,7 @@ static const struct reg_field tsens_8960
+ };
+ 
+ static const struct tsens_ops ops_8960 = {
+-	.init		= init_8960,
++	.init		= init_common,
+ 	.calibrate	= calibrate_8960,
+ 	.get_temp	= get_temp_8960,
+ 	.enable		= enable_8960,
diff --git a/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch b/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch
new file mode 100644
index 00000000000000..7b01a67d900438
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch
@@ -0,0 +1,66 @@
+From b3e8bd33b84a6b6c863bd1733bd15b5f1483b8ab Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 25 Nov 2020 17:06:55 +0100
+Subject: [PATCH 05/10] drivers: thermal: tsens: Fix bug in sensor enable for
+ msm8960
+
+Device based on tsens VER_0 contains a hardware bug that results in some
+problem with sensor enablement. Sensor id 6-11 can't be enabled
+selectively and all of them must be enabled in one step.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 23 ++++++++++++++++++++---
+ 1 file changed, 20 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -27,9 +27,9 @@
+ #define EN			BIT(0)
+ #define SW_RST			BIT(1)
+ #define SENSOR0_EN		BIT(3)
++#define MEASURE_PERIOD		BIT(18)
+ #define SLP_CLK_ENA		BIT(26)
+ #define SLP_CLK_ENA_8660	BIT(24)
+-#define MEASURE_PERIOD		1
+ #define SENSOR0_SHIFT		3
+ 
+ /* INT_STATUS_ADDR bitmasks */
+@@ -126,17 +126,34 @@ static int resume_8960(struct tsens_priv
+ static int enable_8960(struct tsens_priv *priv, int id)
+ {
+ 	int ret;
+-	u32 reg, mask;
++	u32 reg, mask = BIT(id);
+ 
+ 	ret = regmap_read(priv->tm_map, CNTL_ADDR, &reg);
+ 	if (ret)
+ 		return ret;
+ 
+-	mask = BIT(id + SENSOR0_SHIFT);
++	/* HARDWARE BUG:
++	 * On platforms with more than 6 sensors, all remaining sensors
++	 * must be enabled together, otherwise undefined results are expected.
++	 * (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver,
++	 * all the sensors are enabled in one step hence this bug is not
++	 * triggered.
++	 */
++	if (id > 5)
++		mask = GENMASK(10, 6);
++
++	mask <<= SENSOR0_SHIFT;
++
++	/* Sensors already enabled. Skip. */
++	if ((reg & mask) == mask)
++		return 0;
++
+ 	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);
+ 	if (ret)
+ 		return ret;
+ 
++	reg |= MEASURE_PERIOD;
++
+ 	if (priv->num_sensors > 1)
+ 		reg |= mask | SLP_CLK_ENA | EN;
+ 	else
diff --git a/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch b/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch
new file mode 100644
index 00000000000000..a82f5969542b2c
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch
@@ -0,0 +1,109 @@
+From 1ff9f982051759e0387e8c7e793b49c48eae291d Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Wed, 25 Nov 2020 17:11:05 +0100
+Subject: [PATCH 06/10] drivers: thermal: tsens: Replace custom 8960 apis with
+ generic apis
+
+Rework calibrate function to use common function. Derive the offset from
+a missing hardcoded slope table and the data from the nvmem calib
+efuses.
+Drop custom get_temp function and use generic api.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 56 +++++++++----------------------
+ 1 file changed, 15 insertions(+), 41 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -67,6 +67,13 @@
+ #define S9_STATUS_OFF		0x3674
+ #define S10_STATUS_OFF		0x3678
+ 
++/* Original slope - 200 to compensate mC to C inaccuracy */
++static u32 tsens_msm8960_slope[] = {
++			976, 976, 954, 976,
++			911, 932, 932, 999,
++			932, 999, 932
++			};
++
+ static int suspend_8960(struct tsens_priv *priv)
+ {
+ 	int ret;
+@@ -194,9 +201,7 @@ static int calibrate_8960(struct tsens_p
+ {
+ 	int i;
+ 	char *data;
+-
+-	ssize_t num_read = priv->num_sensors;
+-	struct tsens_sensor *s = priv->sensor;
++	u32 p1[11];
+ 
+ 	data = qfprom_read(priv->dev, "calib");
+ 	if (IS_ERR(data))
+@@ -204,49 +209,18 @@ static int calibrate_8960(struct tsens_p
+ 	if (IS_ERR(data))
+ 		return PTR_ERR(data);
+ 
+-	for (i = 0; i < num_read; i++, s++)
+-		s->offset = data[i];
++	for (i = 0; i < priv->num_sensors; i++) {
++		p1[i] = data[i];
++		priv->sensor[i].slope = tsens_msm8960_slope[i];
++	}
++
++	compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB);
+ 
+ 	kfree(data);
+ 
+ 	return 0;
+ }
+ 
+-/* Temperature on y axis and ADC-code on x-axis */
+-static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)
+-{
+-	int slope, offset;
+-
+-	slope = thermal_zone_get_slope(s->tzd);
+-	offset = CAL_MDEGC - slope * s->offset;
+-
+-	return adc_code * slope + offset;
+-}
+-
+-static int get_temp_8960(const struct tsens_sensor *s, int *temp)
+-{
+-	int ret;
+-	u32 code, trdy;
+-	struct tsens_priv *priv = s->priv;
+-	unsigned long timeout;
+-
+-	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+-	do {
+-		ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
+-		if (ret)
+-			return ret;
+-		if (!(trdy & TRDY_MASK))
+-			continue;
+-		ret = regmap_read(priv->tm_map, s->status, &code);
+-		if (ret)
+-			return ret;
+-		*temp = code_to_mdegC(code, s);
+-		return 0;
+-	} while (time_before(jiffies, timeout));
+-
+-	return -ETIMEDOUT;
+-}
+-
+ static struct tsens_features tsens_8960_feat = {
+ 	.ver_major	= VER_0,
+ 	.crit_int	= 0,
+@@ -315,7 +289,7 @@ static const struct reg_field tsens_8960
+ static const struct tsens_ops ops_8960 = {
+ 	.init		= init_common,
+ 	.calibrate	= calibrate_8960,
+-	.get_temp	= get_temp_8960,
++	.get_temp	= get_temp_common,
+ 	.enable		= enable_8960,
+ 	.disable	= disable_8960,
+ 	.suspend	= suspend_8960,
diff --git a/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch b/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch
new file mode 100644
index 00000000000000..77ca3cfe4578d8
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch
@@ -0,0 +1,65 @@
+From 5716a61239c6ac9ceb137e825e93c3aea06c4634 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Fri, 19 Mar 2021 00:48:23 +0100
+Subject: [PATCH 07/10] drivers: thermal: tsens: Drop unused define for msm8960
+
+Drop unused define for msm8960 replaced by generic api and reg_field.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 24 +-----------------------
+ 1 file changed, 1 insertion(+), 23 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -10,8 +10,6 @@
+ #include <linux/thermal.h>
+ #include "tsens.h"
+ 
+-#define CAL_MDEGC		30000
+-
+ #define CONFIG_ADDR		0x3640
+ #define CONFIG_ADDR_8660	0x3620
+ /* CONFIG_ADDR bitmasks */
+@@ -21,39 +19,19 @@
+ #define CONFIG_SHIFT_8660	28
+ #define CONFIG_MASK_8660	(3 << CONFIG_SHIFT_8660)
+ 
+-#define STATUS_CNTL_ADDR_8064	0x3660
+ #define CNTL_ADDR		0x3620
+ /* CNTL_ADDR bitmasks */
+ #define EN			BIT(0)
+ #define SW_RST			BIT(1)
+-#define SENSOR0_EN		BIT(3)
++
+ #define MEASURE_PERIOD		BIT(18)
+ #define SLP_CLK_ENA		BIT(26)
+ #define SLP_CLK_ENA_8660	BIT(24)
+ #define SENSOR0_SHIFT		3
+ 
+-/* INT_STATUS_ADDR bitmasks */
+-#define MIN_STATUS_MASK		BIT(0)
+-#define LOWER_STATUS_CLR	BIT(1)
+-#define UPPER_STATUS_CLR	BIT(2)
+-#define MAX_STATUS_MASK		BIT(3)
+-
+ #define THRESHOLD_ADDR		0x3624
+-/* THRESHOLD_ADDR bitmasks */
+-#define THRESHOLD_MAX_LIMIT_SHIFT	24
+-#define THRESHOLD_MIN_LIMIT_SHIFT	16
+-#define THRESHOLD_UPPER_LIMIT_SHIFT	8
+-#define THRESHOLD_LOWER_LIMIT_SHIFT	0
+-
+-/* Initial temperature threshold values */
+-#define LOWER_LIMIT_TH		0x50
+-#define UPPER_LIMIT_TH		0xdf
+-#define MIN_LIMIT_TH		0x0
+-#define MAX_LIMIT_TH		0xff
+ 
+ #define INT_STATUS_ADDR		0x363c
+-#define TRDY_MASK		BIT(7)
+-#define TIMEOUT_US		100
+ 
+ #define S0_STATUS_OFF		0x3628
+ #define S1_STATUS_OFF		0x362c
diff --git a/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch b/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch
new file mode 100644
index 00000000000000..127abaefc3002a
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch
@@ -0,0 +1,26 @@
+From 0d0c22a59bf2672b57e23da9a9ea743e91b71f54 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sat, 25 Jul 2020 19:55:57 +0200
+Subject: [PATCH 08/10] drivers: thermal: tsens: Add support for ipq8064-tsens
+
+Add support for tsens present in ipq806x SoCs based on generic msm8960
+tsens driver.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -968,6 +968,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t
+ 
+ static const struct of_device_id tsens_table[] = {
+ 	{
++		.compatible = "qcom,ipq8064-tsens",
++		.data = &data_8960,
++	}, {
+ 		.compatible = "qcom,msm8916-tsens",
+ 		.data = &data_8916,
+ 	}, {
diff --git a/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch b/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch
new file mode 100644
index 00000000000000..382106863f90ac
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch
@@ -0,0 +1,112 @@
+From ac369071920d427dd484cf74cddba2774bba45f5 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Thu, 9 Jul 2020 22:35:54 +0200
+Subject: [PATCH 09/10] dt-bindings: thermal: tsens: Document ipq8064 bindings
+
+Document the use of bindings used for msm8960 tsens based devices.
+msm8960 use the same gcc regs and is set as a child of the qcom gcc.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+---
+ .../bindings/thermal/qcom-tsens.yaml          | 56 ++++++++++++++++---
+ 1 file changed, 48 insertions(+), 8 deletions(-)
+
+--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
++++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+@@ -19,6 +19,11 @@ description: |
+ properties:
+   compatible:
+     oneOf:
++      - description: msm9860 TSENS based
++        items:
++          - enum:
++              - qcom,ipq8064-tsens
++
+       - description: v0.1 of TSENS
+         items:
+           - enum:
+@@ -73,7 +78,9 @@ properties:
+     maxItems: 2
+     items:
+       - const: calib
+-      - const: calib_sel
++      - enum:
++          - calib_backup
++          - calib_sel
+ 
+   "#qcom,sensors":
+     description:
+@@ -88,12 +95,20 @@ properties:
+       Number of cells required to uniquely identify the thermal sensors. Since
+       we have multiple sensors this is set to 1
+ 
++required:
++  - compatible
++  - interrupts
++  - interrupt-names
++  - "#thermal-sensor-cells"
++  - "#qcom,sensors"
++
+ allOf:
+   - if:
+       properties:
+         compatible:
+           contains:
+             enum:
++              - qcom,ipq8064-tsens
+               - qcom,msm8916-tsens
+               - qcom,msm8974-tsens
+               - qcom,msm8976-tsens
+@@ -114,19 +129,44 @@ allOf:
+         interrupt-names:
+           minItems: 2
+ 
+-required:
+-  - compatible
+-  - reg
+-  - "#qcom,sensors"
+-  - interrupts
+-  - interrupt-names
+-  - "#thermal-sensor-cells"
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - qcom,tsens-v0_1
++              - qcom,tsens-v1
++              - qcom,tsens-v2
++
++    then:
++      required:
++        - reg
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+     #include <dt-bindings/interrupt-controller/arm-gic.h>
++    // Example msm9860 based SoC (ipq8064):
++    gcc: clock-controller {
++
++           /* ... */
++
++           tsens: thermal-sensor {
++                compatible = "qcom,ipq8064-tsens";
++
++                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
++                 nvmem-cell-names = "calib", "calib_backup";
++                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++                 interrupt-names = "uplow";
++
++                 #qcom,sensors = <11>;
++                 #thermal-sensor-cells = <1>;
++          };
++    };
++
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
+     // Example 1 (legacy: for pre v1 IP):
+     tsens1: thermal-sensor@900000 {
+            compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
diff --git a/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch b/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch
new file mode 100644
index 00000000000000..6cdc0b263fb8d0
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch
@@ -0,0 +1,32 @@
+From 68e720ed73c8f038c8c500e4c49c1e65a993a448 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 6 Apr 2021 04:45:31 +0200
+Subject: [PATCH 10/10] drivers: thermal: tsens: Fix wrong slope on msm-8960
+
+Some user using some stats with the old legacy implementation and the
+new implementation using the compute_intercept_slope reported an offset
+of 3C. Fix the slope table to reflect the original temp.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/thermal/qcom/tsens-8960.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -45,11 +45,11 @@
+ #define S9_STATUS_OFF		0x3674
+ #define S10_STATUS_OFF		0x3678
+ 
+-/* Original slope - 200 to compensate mC to C inaccuracy */
++/* Original slope - 350 to compensate mC to C inaccuracy */
+ static u32 tsens_msm8960_slope[] = {
+-			976, 976, 954, 976,
+-			911, 932, 932, 999,
+-			932, 999, 932
++			826, 826, 804, 826,
++			761, 782, 782, 849,
++			782, 849, 782
+ 			};
+ 
+ static int suspend_8960(struct tsens_priv *priv)
diff --git a/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch b/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch
new file mode 100644
index 00000000000000..5c9ba71c794dda
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch
@@ -0,0 +1,41 @@
+From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 19 Apr 2021 03:01:53 +0200
+Subject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with
+ successful probe
+
+calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
+double or a wrong init of the debugfs information. Init debugfs only
+with successful probe fixing warning about directory already present.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
+ 	if (tsens_version(priv) >= VER_0_1)
+ 		tsens_enable_irq(priv);
+ 
+-	tsens_debug_init(op);
+-
+ err_put_device:
+ 	put_device(&op->dev);
+ 	return ret;
+@@ -1161,7 +1159,12 @@ static int tsens_probe(struct platform_d
+ 		}
+ 	}
+ 
+-	return tsens_register(priv);
++	ret = tsens_register(priv);
++
++	if (!ret)
++		tsens_debug_init(pdev);
++
++	return ret;
+ }
+ 
+ static int tsens_remove(struct platform_device *pdev)
diff --git a/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch b/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch
new file mode 100644
index 00000000000000..0fbc4bd8cad85f
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch
@@ -0,0 +1,54 @@
+From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 19 Apr 2021 03:08:37 +0200
+Subject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init
+ function
+
+Simplify debugfs init function.
+- Add check for existing dev directory.
+- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was
+  incorrectly reported)
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
+---
+ drivers/thermal/qcom/tsens.c | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
+ 			return ret;
+ 		seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
+ 	} else {
+-		seq_puts(s, "0.1.0\n");
++		seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
+ 	}
+ 
+ 	return 0;
+@@ -704,21 +704,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
+ static void tsens_debug_init(struct platform_device *pdev)
+ {
+ 	struct tsens_priv *priv = platform_get_drvdata(pdev);
+-	struct dentry *root, *file;
+ 
+-	root = debugfs_lookup("tsens", NULL);
+-	if (!root)
++	priv->debug_root = debugfs_lookup("tsens", NULL);
++	if (!priv->debug_root)
+ 		priv->debug_root = debugfs_create_dir("tsens", NULL);
+-	else
+-		priv->debug_root = root;
+ 
+-	file = debugfs_lookup("version", priv->debug_root);
+-	if (!file)
++	if (!debugfs_lookup("version", priv->debug_root))
+ 		debugfs_create_file("version", 0444, priv->debug_root,
+ 				    pdev, &dbg_version_fops);
+ 
+ 	/* A directory for each instance of the TSENS IP */
+-	priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
++	priv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root);
+ 	debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
+ }
+ #else
diff --git a/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch b/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch
new file mode 100644
index 00000000000000..5bf15f4b09cec5
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch
@@ -0,0 +1,75 @@
+From e67f325e9cd67562b761e884680c0fec03a6f404 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Tue, 8 Jun 2021 19:59:06 +0100
+Subject: net: stmmac: explicitly deassert GMAC_AHB_RESET
+
+We are currently assuming that GMAC_AHB_RESET will already be deasserted
+by the bootloader. However if this has not been done, probing of the GMAC
+will fail. To remedy this we must ensure GMAC_AHB_RESET has been deasserted
+prior to probing.
+
+v2 changes:
+ - remove NULL condition check for stmmac_ahb_rst in stmmac_main.c
+ - unwrap dev_err() message in stmmac_main.c
+ - add PTR_ERR() around plat->stmmac_ahb_rst in stmmac_platform.c
+
+v3 changes:
+ - add error pointer to dev_err() output
+ - add reset_control_assert(stmmac_ahb_rst) in stmmac_dvr_remove
+ - revert PTR_ERR() around plat->stmmac_ahb_rst since this is performed
+   on the returned value of ret by the calling function
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c     | 5 +++++
+ drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++++
+ include/linux/stmmac.h                                | 1 +
+ 3 files changed, 12 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -5049,6 +5049,10 @@ int stmmac_dvr_probe(struct device *devi
+ 			reset_control_reset(priv->plat->stmmac_rst);
+ 	}
+ 
++	ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
++	if (ret == -ENOTSUPP)
++		dev_err(priv->device, "unable to bring out of ahb reset\n");
++
+ 	/* Init MAC and get the capabilities */
+ 	ret = stmmac_hw_init(priv);
+ 	if (ret)
+@@ -5257,6 +5261,7 @@ int stmmac_dvr_remove(struct device *dev
+ 	phylink_destroy(priv->phylink);
+ 	if (priv->plat->stmmac_rst)
+ 		reset_control_assert(priv->plat->stmmac_rst);
++	reset_control_assert(priv->plat->stmmac_ahb_rst);
+ 	pm_runtime_put(dev);
+ 	pm_runtime_disable(dev);
+ 	if (priv->hw->pcs != STMMAC_PCS_TBI &&
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+@@ -616,6 +616,12 @@ stmmac_probe_config_dt(struct platform_d
+ 		plat->stmmac_rst = NULL;
+ 	}
+ 
++	plat->stmmac_ahb_rst = devm_reset_control_get_optional_shared(
++							&pdev->dev, "ahb");
++	if (IS_ERR(plat->stmmac_ahb_rst))
++		if (PTR_ERR(plat->stmmac_ahb_rst) == -EPROBE_DEFER)
++			goto error_hw_init;
++
+ 	return plat;
+ 
+ error_hw_init:
+--- a/include/linux/stmmac.h
++++ b/include/linux/stmmac.h
+@@ -192,6 +192,7 @@ struct plat_stmmacenet_data {
+ 	unsigned int clk_ref_rate;
+ 	s32 ptp_max_adj;
+ 	struct reset_control *stmmac_rst;
++	struct reset_control *stmmac_ahb_rst;
+ 	struct stmmac_axi *axi;
+ 	int has_gmac4;
+ 	bool has_sun8i;
diff --git a/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch b/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch
new file mode 100644
index 00000000000000..4a047ed6eb332e
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch
@@ -0,0 +1,64 @@
+From f95c4c56d65225a537a2d88735fde7ec4d37641d Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sat, 5 Jun 2021 18:35:38 +0100
+Subject: ARM: dts: qcom: add ahb reset to ipq806x-gmac
+
+Add GMAC_AHB_RESET to the resets property of each gmac node.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Link: https://lore.kernel.org/r/20210605173546.4102455-2-mnhagan88@gmail.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 ++++++++++++--------
+ 1 file changed, 12 insertions(+), 8 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -1335,8 +1335,9 @@
+ 			clocks = <&gcc GMAC_CORE1_CLK>;
+ 			clock-names = "stmmaceth";
+ 
+-			resets = <&gcc GMAC_CORE1_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&gcc GMAC_CORE1_RESET>,
++				 <&gcc GMAC_AHB_RESET>;
++			reset-names = "stmmaceth", "ahb";
+ 
+ 			status = "disabled";
+ 		};
+@@ -1358,8 +1359,9 @@
+ 			clocks = <&gcc GMAC_CORE2_CLK>;
+ 			clock-names = "stmmaceth";
+ 
+-			resets = <&gcc GMAC_CORE2_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&gcc GMAC_CORE2_RESET>,
++				 <&gcc GMAC_AHB_RESET>;
++			reset-names = "stmmaceth", "ahb";
+ 
+ 			status = "disabled";
+ 		};
+@@ -1381,8 +1383,9 @@
+ 			clocks = <&gcc GMAC_CORE3_CLK>;
+ 			clock-names = "stmmaceth";
+ 
+-			resets = <&gcc GMAC_CORE3_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&gcc GMAC_CORE3_RESET>,
++				 <&gcc GMAC_AHB_RESET>;
++			reset-names = "stmmaceth", "ahb";
+ 
+ 			status = "disabled";
+ 		};
+@@ -1404,8 +1407,9 @@
+ 			clocks = <&gcc GMAC_CORE4_CLK>;
+ 			clock-names = "stmmaceth";
+ 
+-			resets = <&gcc GMAC_CORE4_RESET>;
+-			reset-names = "stmmaceth";
++			resets = <&gcc GMAC_CORE4_RESET>,
++				 <&gcc GMAC_AHB_RESET>;
++			reset-names = "stmmaceth", "ahb";
+ 
+ 			status = "disabled";
+ 		};
diff --git a/target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch
similarity index 97%
rename from target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch
rename to target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch
index dfc383684af1d4..d433cb49b85fac 100644
--- a/target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch
+++ b/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch
@@ -2,7 +2,7 @@ From: Christian Lamparter <chunkeey@googlemail.com>
 Subject: SoC: add qualcomm syscon
 --- a/drivers/soc/qcom/Makefile
 +++ b/drivers/soc/qcom/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SMP2P)	+= smp2p.o
+@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P)	+= smp2p.o
  obj-$(CONFIG_QCOM_SMSM)	+= smsm.o
  obj-$(CONFIG_QCOM_SOCINFO)	+= socinfo.o
  obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
@@ -12,7 +12,7 @@ Subject: SoC: add qualcomm syscon
  obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 --- a/drivers/soc/qcom/Kconfig
 +++ b/drivers/soc/qcom/Kconfig
-@@ -176,6 +176,13 @@ config QCOM_SOCINFO
+@@ -191,6 +191,13 @@ config QCOM_SOCINFO
  	 Say yes here to support the Qualcomm socinfo driver, providing
  	 information about the SoC to user space.
  
diff --git a/target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch
similarity index 84%
rename from target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch
rename to target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch
index ecd55ce2f01304..9d9501b872dedf 100644
--- a/target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch
+++ b/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
-@@ -1837,6 +1837,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
+@@ -1791,6 +1791,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
  
  endchoice
  
@@ -17,9 +17,9 @@
  	default ""
 --- a/drivers/of/fdt.c
 +++ b/drivers/of/fdt.c
-@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns
+@@ -1058,6 +1058,17 @@ int __init early_init_dt_scan_chosen(uns
  	if (p != NULL && l > 0)
- 		strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
+ 		strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
  
 +    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
 +     * device tree option of chosen/bootargs-override. This is
diff --git a/target/linux/ipq806x/patches-5.4/0030-clk-Disable-i2c-device-on-gsbi4.patch b/target/linux/ipq806x/patches-5.4/0030-clk-Disable-i2c-device-on-gsbi4.patch
deleted file mode 100644
index a5fb714e6c46e9..00000000000000
--- a/target/linux/ipq806x/patches-5.4/0030-clk-Disable-i2c-device-on-gsbi4.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 0c974b87829e007dc4fae94e20d488204e20e662 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 08:16:10 +0100
-Subject: [PATCH 30/69] clk: Disable i2c device on gsbi4
-
-This patch was not annotated and comes from the v4.4 tree.
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/clk/qcom/gcc-ipq806x.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -365,7 +365,7 @@ static struct clk_rcg gsbi1_uart_src = {
- 			.parent_names = gcc_pxo_pll8,
- 			.num_parents = 2,
- 			.ops = &clk_rcg_ops,
--			.flags = CLK_SET_PARENT_GATE,
-+			.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
- 		},
- 	},
- };
-@@ -383,7 +383,7 @@ static struct clk_branch gsbi1_uart_clk
- 			},
- 			.num_parents = 1,
- 			.ops = &clk_branch_ops,
--			.flags = CLK_SET_RATE_PARENT,
-+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
- 		},
- 	},
- };
-@@ -961,6 +961,7 @@ static struct clk_branch gsbi1_h_clk = {
- 		.hw.init = &(struct clk_init_data){
- 			.name = "gsbi1_h_clk",
- 			.ops = &clk_branch_ops,
-+			.flags = CLK_IGNORE_UNUSED,
- 		},
- 	},
- };
diff --git a/target/linux/ipq806x/patches-5.4/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch b/target/linux/ipq806x/patches-5.4/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch
deleted file mode 100644
index 7d6e3f16055443..00000000000000
--- a/target/linux/ipq806x/patches-5.4/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001
-From: Lina Iyer <lina.iyer@linaro.org>
-Date: Wed, 25 Mar 2015 14:25:29 -0600
-Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus
-
-Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
-
-Cc: Stephen Boyd <sboyd@codeaurora.org>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Kevin Hilman <khilman@linaro.org>
-Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
----
- drivers/cpuidle/Kconfig.arm | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/cpuidle/Kconfig.arm
-+++ b/drivers/cpuidle/Kconfig.arm
-@@ -86,3 +86,10 @@ config ARM_MVEBU_V7_CPUIDLE
- 	depends on ARCH_MVEBU && !ARM64
- 	help
- 	  Select this to enable cpuidle on Armada 370, 38x and XP processors.
-+
-+config ARM_QCOM_CPUIDLE
-+	bool "CPU Idle Driver for QCOM processors"
-+	depends on ARCH_QCOM
-+	select ARM_CPUIDLE
-+	help
-+	  Select this to enable cpuidle on QCOM processors.
diff --git a/target/linux/ipq806x/patches-5.4/0063-1-ipq806x-tsens-driver.patch b/target/linux/ipq806x/patches-5.4/0063-1-ipq806x-tsens-driver.patch
deleted file mode 100644
index 80954c17fd55de..00000000000000
--- a/target/linux/ipq806x/patches-5.4/0063-1-ipq806x-tsens-driver.patch
+++ /dev/null
@@ -1,616 +0,0 @@
-From 3302e1e1a3cfa4e67fda2a61d6f0c42205d40932 Mon Sep 17 00:00:00 2001
-From: Rajith Cherian <rajith@codeaurora.org>
-Date: Tue, 14 Feb 2017 18:30:43 +0530
-Subject: [PATCH] ipq8064: tsens: Base tsens driver for IPQ8064
-
-Add TSENS driver template to support IPQ8064.
-This is a base file copied from tsens-8960.c
-
-Change-Id: I47c573fdfa2d898243c6a6ba952d1632f91391f7
-Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
-
-ipq8064: tsens: TSENS driver support for IPQ8064
-
-Support for IPQ8064 tsens driver. The driver works
-with the thermal framework. The driver overrides the
-following fucntionalities:
-
-1. Get current temperature.
-2. Get/Set trip temperatures.
-3. Enabled/Disable trip points.
-4. ISR for threshold generated interrupt.
-5. Notify userspace when trip points are hit.
-
-Change-Id: I8bc7204fd627d10875ab13fc1de8cb6c2ed7a918
-Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
----
-
---- a/drivers/thermal/qcom/Makefile
-+++ b/drivers/thermal/qcom/Makefile
-@@ -2,5 +2,5 @@
- obj-$(CONFIG_QCOM_TSENS)	+= qcom_tsens.o
- 
- qcom_tsens-y			+= tsens.o tsens-common.o tsens-v0_1.o \
--				   tsens-8960.o tsens-v2.o tsens-v1.o
-+				   tsens-8960.o tsens-v2.o tsens-v1.o tsens-ipq8064.o
- obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM)	+= qcom-spmi-temp-alarm.o
---- /dev/null
-+++ b/drivers/thermal/qcom/tsens-ipq8064.c
-@@ -0,0 +1,551 @@
-+/*
-+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/delay.h>
-+#include <linux/bitops.h>
-+#include <linux/regmap.h>
-+#include <linux/thermal.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include "tsens.h"
-+
-+#define CAL_MDEGC		30000
-+
-+#define CONFIG_ADDR		0x3640
-+/* CONFIG_ADDR bitmasks */
-+#define CONFIG			0x9b
-+#define CONFIG_MASK		0xf
-+#define CONFIG_SHIFT		0
-+
-+#define STATUS_CNTL_8064	0x3660
-+#define CNTL_ADDR		0x3620
-+/* CNTL_ADDR bitmasks */
-+#define EN			BIT(0)
-+#define SW_RST			BIT(1)
-+#define SENSOR0_EN		BIT(3)
-+#define SLP_CLK_ENA		BIT(26)
-+#define MEASURE_PERIOD		1
-+#define SENSOR0_SHIFT		3
-+
-+/* INT_STATUS_ADDR bitmasks */
-+#define MIN_STATUS_MASK		BIT(0)
-+#define LOWER_STATUS_CLR	BIT(1)
-+#define UPPER_STATUS_CLR	BIT(2)
-+#define MAX_STATUS_MASK		BIT(3)
-+
-+#define THRESHOLD_ADDR		0x3624
-+/* THRESHOLD_ADDR bitmasks */
-+#define THRESHOLD_MAX_CODE		0x20000
-+#define THRESHOLD_MIN_CODE		0
-+#define THRESHOLD_MAX_LIMIT_SHIFT	24
-+#define THRESHOLD_MIN_LIMIT_SHIFT	16
-+#define THRESHOLD_UPPER_LIMIT_SHIFT	8
-+#define THRESHOLD_LOWER_LIMIT_SHIFT	0
-+#define THRESHOLD_MAX_LIMIT_MASK	(THRESHOLD_MAX_CODE << \
-+						THRESHOLD_MAX_LIMIT_SHIFT)
-+#define THRESHOLD_MIN_LIMIT_MASK	(THRESHOLD_MAX_CODE << \
-+						THRESHOLD_MIN_LIMIT_SHIFT)
-+#define THRESHOLD_UPPER_LIMIT_MASK	(THRESHOLD_MAX_CODE << \
-+						THRESHOLD_UPPER_LIMIT_SHIFT)
-+#define THRESHOLD_LOWER_LIMIT_MASK	(THRESHOLD_MAX_CODE << \
-+						THRESHOLD_LOWER_LIMIT_SHIFT)
-+
-+/* Initial temperature threshold values */
-+#define LOWER_LIMIT_TH		0x9d /* 95C */
-+#define UPPER_LIMIT_TH		0xa6 /* 105C */
-+#define MIN_LIMIT_TH		0x0
-+#define MAX_LIMIT_TH		0xff
-+
-+#define S0_STATUS_ADDR		0x3628
-+#define STATUS_ADDR_OFFSET	2
-+#define SENSOR_STATUS_SIZE	4
-+#define INT_STATUS_ADDR		0x363c
-+#define TRDY_MASK		BIT(7)
-+#define TIMEOUT_US		100
-+
-+#define TSENS_EN		BIT(0)
-+#define TSENS_SW_RST		BIT(1)
-+#define TSENS_ADC_CLK_SEL	BIT(2)
-+#define SENSOR0_EN		BIT(3)
-+#define SENSOR1_EN		BIT(4)
-+#define SENSOR2_EN		BIT(5)
-+#define SENSOR3_EN		BIT(6)
-+#define SENSOR4_EN		BIT(7)
-+#define SENSORS_EN		(SENSOR0_EN | SENSOR1_EN | \
-+				SENSOR2_EN | SENSOR3_EN | SENSOR4_EN)
-+#define TSENS_8064_SENSOR5_EN				BIT(8)
-+#define TSENS_8064_SENSOR6_EN				BIT(9)
-+#define TSENS_8064_SENSOR7_EN				BIT(10)
-+#define TSENS_8064_SENSOR8_EN				BIT(11)
-+#define TSENS_8064_SENSOR9_EN				BIT(12)
-+#define TSENS_8064_SENSOR10_EN				BIT(13)
-+#define TSENS_8064_SENSORS_EN				(SENSORS_EN | \
-+						TSENS_8064_SENSOR5_EN | \
-+						TSENS_8064_SENSOR6_EN | \
-+						TSENS_8064_SENSOR7_EN | \
-+						TSENS_8064_SENSOR8_EN | \
-+						TSENS_8064_SENSOR9_EN | \
-+						TSENS_8064_SENSOR10_EN)
-+
-+#define TSENS_8064_SEQ_SENSORS	5
-+#define TSENS_8064_S4_S5_OFFSET	40
-+#define TSENS_FACTOR		1
-+
-+/* Trips: from very hot to very cold */
-+enum tsens_trip_type {
-+	TSENS_TRIP_STAGE3 = 0,
-+	TSENS_TRIP_STAGE2,
-+	TSENS_TRIP_STAGE1,
-+	TSENS_TRIP_STAGE0,
-+	TSENS_TRIP_NUM,
-+};
-+
-+u32 tsens_8064_slope[] = {
-+			1176, 1176, 1154, 1176,
-+			1111, 1132, 1132, 1199,
-+			1132, 1199, 1132
-+			};
-+
-+/* Temperature on y axis and ADC-code on x-axis */
-+static inline int code_to_degC(u32 adc_code, const struct tsens_sensor *s)
-+{
-+	int degcbeforefactor, degc;
-+
-+	degcbeforefactor = (adc_code * s->slope) + s->offset;
-+
-+	if (degcbeforefactor == 0)
-+		degc = degcbeforefactor;
-+	else if (degcbeforefactor > 0)
-+		degc = (degcbeforefactor + TSENS_FACTOR/2)
-+			/ TSENS_FACTOR;
-+	else
-+		degc = (degcbeforefactor - TSENS_FACTOR/2)
-+			/ TSENS_FACTOR;
-+
-+	return degc;
-+}
-+
-+static int degC_to_code(int degC, const struct tsens_sensor *s)
-+{
-+	int code = ((degC * TSENS_FACTOR - s->offset) + (s->slope/2))
-+			/ s->slope;
-+
-+	if (code > THRESHOLD_MAX_CODE)
-+		code = THRESHOLD_MAX_CODE;
-+	else if (code < THRESHOLD_MIN_CODE)
-+		code = THRESHOLD_MIN_CODE;
-+	return code;
-+}
-+
-+static int suspend_ipq8064(struct tsens_priv *priv)
-+{
-+	int ret;
-+	unsigned int mask;
-+	struct regmap *map = priv->tm_map;
-+
-+	ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
-+	if (ret)
-+		return ret;
-+
-+	ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
-+	if (ret)
-+		return ret;
-+
-+	mask = SLP_CLK_ENA | EN;
-+
-+	ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int resume_ipq8064(struct tsens_priv *priv)
-+{
-+	int ret;
-+	struct regmap *map = priv->tm_map;
-+
-+	ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
-+	if (ret)
-+		return ret;
-+
-+	ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
-+	if (ret)
-+		return ret;
-+
-+	ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
-+	if (ret)
-+		return ret;
-+
-+	ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static void notify_uspace_tsens_fn(struct work_struct *work)
-+{
-+	struct tsens_sensor *s = container_of(work, struct tsens_sensor,
-+								notify_work);
-+
-+	sysfs_notify(&s->tzd->device.kobj, NULL, "type");
-+}
-+
-+static void tsens_scheduler_fn(struct work_struct *work)
-+{
-+	struct tsens_priv *priv = container_of(work, struct tsens_priv,
-+					tsens_work);
-+	unsigned int threshold, threshold_low, code, reg, sensor, mask;
-+	unsigned int sensor_addr;
-+	bool upper_th_x, lower_th_x;
-+	int adc_code, ret;
-+
-+	ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
-+	if (ret)
-+		return;
-+	reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR;
-+	ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, reg);
-+	if (ret)
-+		return;
-+
-+	mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR);
-+	ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold);
-+	if (ret)
-+		return;
-+	threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK)
-+				>> THRESHOLD_LOWER_LIMIT_SHIFT;
-+	threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK)
-+				>> THRESHOLD_UPPER_LIMIT_SHIFT;
-+
-+	ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
-+	if (ret)
-+		return;
-+
-+	ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor);
-+	if (ret)
-+		return;
-+	sensor &= (uint32_t) TSENS_8064_SENSORS_EN;
-+	sensor >>= SENSOR0_SHIFT;
-+
-+	/* Constraint: There is only 1 interrupt control register for all
-+	 * 11 temperature sensor. So monitoring more than 1 sensor based
-+	 * on interrupts will yield inconsistent result. To overcome this
-+	 * issue we will monitor only sensor 0 which is the master sensor.
-+	 */
-+
-+	/* Skip if the sensor is disabled */
-+	if (sensor & 1) {
-+		ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code);
-+		if (ret)
-+			return;
-+		upper_th_x = code >= threshold;
-+		lower_th_x = code <= threshold_low;
-+		if (upper_th_x)
-+			mask |= UPPER_STATUS_CLR;
-+		if (lower_th_x)
-+			mask |= LOWER_STATUS_CLR;
-+		if (upper_th_x || lower_th_x) {
-+			/* Notify user space */
-+			schedule_work(&priv->sensor[0].notify_work);
-+			regmap_read(priv->tm_map, sensor_addr, &adc_code);
-+			pr_debug("Trigger (%d degrees) for sensor %d\n",
-+				code_to_degC(adc_code, &priv->sensor[0]), 0);
-+		}
-+	}
-+	regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
-+
-+	/* force memory to sync */
-+	mb();
-+}
-+
-+static irqreturn_t tsens_isr(int irq, void *data)
-+{
-+	struct tsens_priv *priv = data;
-+
-+	schedule_work(&priv->tsens_work);
-+	return IRQ_HANDLED;
-+}
-+
-+static void hw_init(struct tsens_priv *priv)
-+{
-+	int ret;
-+	unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0;
-+	unsigned int reg_status_cntl = 0;
-+
-+	regmap_read(priv->tm_map, CNTL_ADDR, &reg_cntl);
-+	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST);
-+
-+	reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18)
-+		| (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT);
-+	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
-+	regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_status_cntl);
-+	reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR
-+			| MIN_STATUS_MASK | MAX_STATUS_MASK;
-+	regmap_write(priv->tm_map, STATUS_CNTL_8064, reg_status_cntl);
-+	reg_cntl |= TSENS_EN;
-+	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
-+
-+	regmap_read(priv->tm_map, CONFIG_ADDR, &reg_cfg);
-+	reg_cfg = (reg_cfg & ~CONFIG_MASK) | (CONFIG << CONFIG_SHIFT);
-+	regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg);
-+
-+	reg_thr |= (LOWER_LIMIT_TH << THRESHOLD_LOWER_LIMIT_SHIFT)
-+		| (UPPER_LIMIT_TH << THRESHOLD_UPPER_LIMIT_SHIFT)
-+		| (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT)
-+		| (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT);
-+
-+	regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr);
-+
-+	ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr,
-+			IRQF_TRIGGER_RISING, "tsens_interrupt", priv);
-+	if (ret < 0) {
-+		pr_err("%s: request_irq FAIL: %d\n", __func__, ret);
-+		return;
-+	}
-+
-+	INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
-+}
-+
-+static int init_ipq8064(struct tsens_priv *priv)
-+{
-+	int ret, i;
-+	u32 reg_cntl, offset = 0;
-+
-+	init_common(priv);
-+	if (!priv->tm_map)
-+		return -ENODEV;
-+
-+	/*
-+	 * The status registers for each sensor are discontiguous
-+	 * because some SoCs have 5 sensors while others have more
-+	 * but the control registers stay in the same place, i.e
-+	 * directly after the first 5 status registers.
-+	 */
-+	for (i = 0; i < priv->num_sensors; i++) {
-+		if (i >= TSENS_8064_SEQ_SENSORS)
-+			offset = TSENS_8064_S4_S5_OFFSET;
-+
-+		priv->sensor[i].status = S0_STATUS_ADDR + offset
-+					+ (i << STATUS_ADDR_OFFSET);
-+		priv->sensor[i].slope = tsens_8064_slope[i];
-+		INIT_WORK(&priv->sensor[i].notify_work,
-+						notify_uspace_tsens_fn);
-+	}
-+
-+	reg_cntl = SW_RST;
-+	ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
-+	if (ret)
-+		return ret;
-+
-+	reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
-+	reg_cntl &= ~SW_RST;
-+	ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
-+					 CONFIG_MASK, CONFIG);
-+
-+	reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
-+	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
-+	if (ret)
-+		return ret;
-+
-+	reg_cntl |= EN;
-+	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int calibrate_ipq8064(struct tsens_priv *priv)
-+{
-+	int i;
-+	char *data, *data_backup;
-+
-+	ssize_t num_read = priv->num_sensors;
-+	struct tsens_sensor *s = priv->sensor;
-+
-+	data = qfprom_read(priv->dev, "calib");
-+	if (IS_ERR(data)) {
-+		pr_err("Calibration not found.\n");
-+		return PTR_ERR(data);
-+	}
-+
-+	data_backup = qfprom_read(priv->dev, "calib_backup");
-+	if (IS_ERR(data_backup)) {
-+		pr_err("Backup calibration not found.\n");
-+		return PTR_ERR(data_backup);
-+	}
-+
-+	for (i = 0; i < num_read; i++) {
-+		s[i].calib_data = readb_relaxed(data + i);
-+		s[i].calib_data_backup = readb_relaxed(data_backup + i);
-+
-+		if (s[i].calib_data_backup)
-+			s[i].calib_data = s[i].calib_data_backup;
-+		if (!s[i].calib_data) {
-+			pr_err("QFPROM TSENS calibration data not present\n");
-+			return -ENODEV;
-+		}
-+		s[i].slope = tsens_8064_slope[i];
-+		s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
-+	}
-+
-+	hw_init(priv);
-+
-+	return 0;
-+}
-+
-+static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
-+{
-+	int ret;
-+	u32 code, trdy;
-+	const struct tsens_sensor *s = &priv->sensor[id];
-+	unsigned long timeout;
-+
-+	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
-+	do {
-+		ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
-+		if (ret)
-+			return ret;
-+		if (!(trdy & TRDY_MASK))
-+			continue;
-+		ret = regmap_read(priv->tm_map, s->status, &code);
-+		if (ret)
-+			return ret;
-+		*temp = code_to_degC(code, s);
-+		return 0;
-+	} while (time_before(jiffies, timeout));
-+
-+	return -ETIMEDOUT;
-+}
-+
-+static int set_trip_temp_ipq8064(void *data, int trip, int temp)
-+{
-+	unsigned int reg_th, reg_cntl;
-+	int ret, code, code_chk, hi_code, lo_code;
-+	const struct tsens_sensor *s = data;
-+	struct tsens_priv *priv = s->priv;
-+
-+	code_chk = code = degC_to_code(temp, s);
-+
-+	if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE)
-+		return -EINVAL;
-+
-+	ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_cntl);
-+	if (ret)
-+		return ret;
-+
-+	ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &reg_th);
-+	if (ret)
-+		return ret;
-+
-+	hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK)
-+			>> THRESHOLD_UPPER_LIMIT_SHIFT;
-+	lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK)
-+			>> THRESHOLD_LOWER_LIMIT_SHIFT;
-+
-+	switch (trip) {
-+	case TSENS_TRIP_STAGE3:
-+		code <<= THRESHOLD_MAX_LIMIT_SHIFT;
-+		reg_th &= ~THRESHOLD_MAX_LIMIT_MASK;
-+		break;
-+	case TSENS_TRIP_STAGE2:
-+		if (code_chk <= lo_code)
-+			return -EINVAL;
-+		code <<= THRESHOLD_UPPER_LIMIT_SHIFT;
-+		reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK;
-+		break;
-+	case TSENS_TRIP_STAGE1:
-+		if (code_chk >= hi_code)
-+			return -EINVAL;
-+		code <<= THRESHOLD_LOWER_LIMIT_SHIFT;
-+		reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK;
-+		break;
-+	case TSENS_TRIP_STAGE0:
-+		code <<= THRESHOLD_MIN_LIMIT_SHIFT;
-+		reg_th &= ~THRESHOLD_MIN_LIMIT_MASK;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int set_trip_activate_ipq8064(void *data, int trip,
-+					enum thermal_trip_activation_mode mode)
-+{
-+	unsigned int reg_cntl, mask, val;
-+	const struct tsens_sensor *s = data;
-+	struct tsens_priv *priv = s->priv;
-+	int ret;
-+
-+	if (!priv || trip < 0)
-+		return -EINVAL;
-+
-+	ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_cntl);
-+	if (ret)
-+		return ret;
-+
-+	switch (trip) {
-+	case TSENS_TRIP_STAGE3:
-+		mask = MAX_STATUS_MASK;
-+		break;
-+	case TSENS_TRIP_STAGE2:
-+		mask = UPPER_STATUS_CLR;
-+		break;
-+	case TSENS_TRIP_STAGE1:
-+		mask = LOWER_STATUS_CLR;
-+		break;
-+	case TSENS_TRIP_STAGE0:
-+		mask = MIN_STATUS_MASK;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (mode == THERMAL_TRIP_ACTIVATION_DISABLED)
-+		val = reg_cntl | mask;
-+	else
-+		val = reg_cntl & ~mask;
-+
-+	ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, val);
-+	if (ret)
-+		return ret;
-+
-+	/* force memory to sync */
-+	mb();
-+	return 0;
-+}
-+
-+const struct tsens_ops ops_ipq8064 = {
-+	.init		= init_ipq8064,
-+	.calibrate	= calibrate_ipq8064,
-+	.get_temp	= get_temp_ipq8064,
-+	.suspend	= suspend_ipq8064,
-+	.resume		= resume_ipq8064,
-+	.set_trip_temp	= set_trip_temp_ipq8064,
-+	.set_trip_activate = set_trip_activate_ipq8064,
-+};
-+
-+const struct tsens_plat_data data_ipq8064 = {
-+	.num_sensors	= 11,
-+	.ops		= &ops_ipq8064,
-+};
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -69,8 +69,11 @@ static const struct of_device_id tsens_t
- 	}, {
- 		.compatible = "qcom,tsens-v2",
- 		.data = &data_tsens_v2,
-+	}, {
-+		.compatible = "qcom,ipq8064-tsens",
-+		.data = &data_ipq8064,
- 	},
--	{}
-+ 	{}
- };
- MODULE_DEVICE_TABLE(of, tsens_table);
- 
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -324,7 +324,7 @@ extern const struct tsens_plat_data data
- extern const struct tsens_plat_data data_8916, data_8974;
- 
- /* TSENS v1 targets */
--extern const struct tsens_plat_data data_tsens_v1;
-+extern const struct tsens_plat_data data_tsens_v1, data_ipq8064;
- 
- /* TSENS v2 targets */
- extern const struct tsens_plat_data data_8996, data_tsens_v2;
diff --git a/target/linux/ipq806x/patches-5.4/0063-2-tsens-support-configurable-interrupts.patch b/target/linux/ipq806x/patches-5.4/0063-2-tsens-support-configurable-interrupts.patch
deleted file mode 100644
index cdb54b905307b3..00000000000000
--- a/target/linux/ipq806x/patches-5.4/0063-2-tsens-support-configurable-interrupts.patch
+++ /dev/null
@@ -1,437 +0,0 @@
-From 4e87400732c77765afae2ea89ed43837457aa604 Mon Sep 17 00:00:00 2001
-From: Rajith Cherian <rajith@codeaurora.org>
-Date: Wed, 1 Feb 2017 19:00:26 +0530
-Subject: [PATCH] ipq8064: tsens: Support for configurable interrupts
-
-Provide support for adding configurable high and
-configurable low trip temperatures. An interrupts is
-also triggerred when these trip points are hit. The
-interrupts can be activated or deactivated from sysfs.
-This functionality is made available only if
-CONFIG_THERMAL_WRITABLE_TRIPS is defined.
-
-Change-Id: Ib73f3f9459de4fffce7bb985a0312a88291f4934
-Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
----
- .../devicetree/bindings/thermal/qcom-tsens.txt     |  4 ++
- drivers/thermal/of-thermal.c                       | 63 ++++++++++++++++++----
- drivers/thermal/qcom/tsens.c                       | 43 ++++++++++++---
- drivers/thermal/qcom/tsens.h                       | 11 ++++
- drivers/thermal/thermal_core.c                     | 44 ++++++++++++++-
- include/linux/thermal.h                            | 14 +++++
- 6 files changed, 162 insertions(+), 17 deletions(-)
-
---- a/drivers/thermal/of-thermal.c
-+++ b/drivers/thermal/of-thermal.c
-@@ -91,7 +91,7 @@ static int of_thermal_get_temp(struct th
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (!data->ops || !data->ops->get_temp)
-+	if (!data->ops || !data->ops->get_temp || (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EINVAL;
- 
- 	return data->ops->get_temp(data->sensor_data, temp);
-@@ -102,7 +102,8 @@ static int of_thermal_set_trips(struct t
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (!data->ops || !data->ops->set_trips)
-+	if (!data->ops || !data->ops->set_trips
-+			|| (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EINVAL;
- 
- 	return data->ops->set_trips(data->sensor_data, low, high);
-@@ -191,6 +192,9 @@ static int of_thermal_set_emul_temp(stru
- 	if (!data->ops || !data->ops->set_emul_temp)
- 		return -EINVAL;
- 
-+	if (data->mode == THERMAL_DEVICE_DISABLED)
-+		return -EINVAL;
-+
- 	return data->ops->set_emul_temp(data->sensor_data, temp);
- }
- 
-@@ -199,7 +203,7 @@ static int of_thermal_get_trend(struct t
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (!data->ops || !data->ops->get_trend)
-+	if (!data->ops || !data->ops->get_trend || (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EINVAL;
- 
- 	return data->ops->get_trend(data->sensor_data, trip, trend);
-@@ -300,7 +304,9 @@ static int of_thermal_set_mode(struct th
- 	mutex_unlock(&tz->lock);
- 
- 	data->mode = mode;
--	thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
-+
-+	if (mode == THERMAL_DEVICE_ENABLED)
-+		thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
- 
- 	return 0;
- }
-@@ -310,7 +316,8 @@ static int of_thermal_get_trip_type(stru
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (trip >= data->ntrips || trip < 0)
-+	if (trip >= data->ntrips || trip < 0
-+				|| (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EDOM;
- 
- 	*type = data->trips[trip].type;
-@@ -318,12 +325,39 @@ static int of_thermal_get_trip_type(stru
- 	return 0;
- }
- 
-+static int of_thermal_activate_trip_type(struct thermal_zone_device *tz,
-+			int trip, enum thermal_trip_activation_mode mode)
-+{
-+	struct __thermal_zone *data = tz->devdata;
-+
-+	if (trip >= data->ntrips || trip < 0
-+				|| (data->mode == THERMAL_DEVICE_DISABLED))
-+		return -EDOM;
-+
-+	/*
-+	 * The configurable_hi and configurable_lo trip points can be
-+	 * activated and deactivated.
-+	 */
-+
-+	if (data->ops->set_trip_activate) {
-+		int ret;
-+
-+		ret = data->ops->set_trip_activate(data->sensor_data,
-+								trip, mode);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
- static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip,
- 				    int *temp)
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (trip >= data->ntrips || trip < 0)
-+	if (trip >= data->ntrips || trip < 0
-+				|| (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EDOM;
- 
- 	*temp = data->trips[trip].temperature;
-@@ -336,7 +370,8 @@ static int of_thermal_set_trip_temp(stru
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (trip >= data->ntrips || trip < 0)
-+	if (trip >= data->ntrips || trip < 0
-+				|| (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EDOM;
- 
- 	if (data->ops && data->ops->set_trip_temp) {
-@@ -358,7 +393,8 @@ static int of_thermal_get_trip_hyst(stru
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (trip >= data->ntrips || trip < 0)
-+	if (trip >= data->ntrips || trip < 0
-+				|| (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EDOM;
- 
- 	*hyst = data->trips[trip].hysteresis;
-@@ -371,7 +407,8 @@ static int of_thermal_set_trip_hyst(stru
- {
- 	struct __thermal_zone *data = tz->devdata;
- 
--	if (trip >= data->ntrips || trip < 0)
-+	if (trip >= data->ntrips || trip < 0
-+				|| (data->mode == THERMAL_DEVICE_DISABLED))
- 		return -EDOM;
- 
- 	/* thermal framework should take care of data->mask & (1 << trip) */
-@@ -446,6 +483,9 @@ thermal_zone_of_add_sensor(struct device
- 	if (ops->set_emul_temp)
- 		tzd->ops->set_emul_temp = of_thermal_set_emul_temp;
- 
-+	if (ops->set_trip_activate)
-+		tzd->ops->set_trip_activate = of_thermal_activate_trip_type;
-+
- 	mutex_unlock(&tzd->lock);
- 
- 	return tzd;
-@@ -768,7 +808,10 @@ static const char * const trip_types[] =
- 	[THERMAL_TRIP_ACTIVE]	= "active",
- 	[THERMAL_TRIP_PASSIVE]	= "passive",
- 	[THERMAL_TRIP_HOT]	= "hot",
--	[THERMAL_TRIP_CRITICAL]	= "critical",
-+	[THERMAL_TRIP_CRITICAL]	= "critical_high",
-+	[THERMAL_TRIP_CONFIGURABLE_HI] = "configurable_hi",
-+	[THERMAL_TRIP_CONFIGURABLE_LOW] = "configurable_lo",
-+	[THERMAL_TRIP_CRITICAL_LOW] = "critical_low",
- };
- 
- /**
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -22,7 +22,7 @@ static int tsens_get_temp(void *data, in
- 
- static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend)
- {
--	const struct tsens_sensor *s = data;
-+	struct tsens_sensor *s = data;
- 	struct tsens_priv *priv = s->priv;
- 
- 	if (priv->ops->get_trend)
-@@ -31,9 +31,10 @@ static int tsens_get_trend(void *data, i
- 	return -ENOTSUPP;
- }
- 
--static int  __maybe_unused tsens_suspend(struct device *dev)
-+static int  __maybe_unused tsens_suspend(void *data)
- {
--	struct tsens_priv *priv = dev_get_drvdata(dev);
-+	struct tsens_sensor *s = data;
-+	struct tsens_priv *priv = s->priv;
- 
- 	if (priv->ops && priv->ops->suspend)
- 		return priv->ops->suspend(priv);
-@@ -41,9 +42,10 @@ static int  __maybe_unused tsens_suspend
- 	return 0;
- }
- 
--static int __maybe_unused tsens_resume(struct device *dev)
-+static int __maybe_unused tsens_resume(void *data)
- {
--	struct tsens_priv *priv = dev_get_drvdata(dev);
-+	struct tsens_sensor *s = data;
-+	struct tsens_priv *priv = s->priv;
- 
- 	if (priv->ops && priv->ops->resume)
- 		return priv->ops->resume(priv);
-@@ -51,6 +53,30 @@ static int __maybe_unused tsens_resume(s
- 	return 0;
- }
- 
-+static int  __maybe_unused tsens_set_trip_temp(void *data, int trip, int temp)
-+{
-+	struct tsens_sensor *s = data;
-+	struct tsens_priv *priv = s->priv;
-+
-+	if (priv->ops && priv->ops->set_trip_temp)
-+		return priv->ops->set_trip_temp(s, trip, temp);
-+
-+	return 0;
-+}
-+
-+static int __maybe_unused tsens_activate_trip_type(void *data, int trip,
-+					enum thermal_trip_activation_mode mode)
-+{
-+	struct tsens_sensor *s = data;
-+	struct tsens_priv *priv = s->priv;
-+
-+	if (priv->ops && priv->ops->set_trip_activate)
-+		return priv->ops->set_trip_activate(s, trip, mode);
-+
-+	return 0;
-+}
-+
-+
- static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
- 
- static const struct of_device_id tsens_table[] = {
-@@ -80,6 +106,8 @@ MODULE_DEVICE_TABLE(of, tsens_table);
- static const struct thermal_zone_of_device_ops tsens_of_ops = {
- 	.get_temp = tsens_get_temp,
- 	.get_trend = tsens_get_trend,
-+	.set_trip_temp = tsens_set_trip_temp,
-+	.set_trip_activate = tsens_activate_trip_type,
- };
- 
- static int tsens_register(struct tsens_priv *priv)
-@@ -123,7 +151,7 @@ static int tsens_probe(struct platform_d
- 	if (id)
- 		data = id->data;
- 	else
--		data = &data_8960;
-+		return -EINVAL;
- 
- 	num_sensors = data->num_sensors;
- 
-@@ -144,6 +172,9 @@ static int tsens_probe(struct platform_d
- 	priv->dev = dev;
- 	priv->num_sensors = num_sensors;
- 	priv->ops = data->ops;
-+
-+	priv->tsens_irq = platform_get_irq(pdev, 0);
-+
- 	for (i = 0;  i < priv->num_sensors; i++) {
- 		if (data->hw_ids)
- 			priv->sensor[i].hw_id = data->hw_ids[i];
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -40,9 +40,12 @@ enum tsens_ver {
- struct tsens_sensor {
- 	struct tsens_priv		*priv;
- 	struct thermal_zone_device	*tzd;
-+	struct work_struct		notify_work;
- 	int				offset;
- 	unsigned int			id;
- 	unsigned int			hw_id;
-+	int				calib_data;
-+	int				calib_data_backup;
- 	int				slope;
- 	u32				status;
- };
-@@ -57,6 +60,9 @@ struct tsens_sensor {
-  * @suspend: Function to suspend the tsens device
-  * @resume: Function to resume the tsens device
-  * @get_trend: Function to get the thermal/temp trend
-+ * @set_trip_temp: Function to set trip temp
-+ * @get_trip_temp: Function to get trip temp
-+ * @set_trip_activate: Function to activate trip points
-  */
- struct tsens_ops {
- 	/* mandatory callbacks */
-@@ -69,6 +75,9 @@ struct tsens_ops {
- 	int (*suspend)(struct tsens_priv *priv);
- 	int (*resume)(struct tsens_priv *priv);
- 	int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend);
-+	int (*set_trip_temp)(void *data, int trip, int temp);
-+	int (*set_trip_activate)(void *data, int trip,
-+					enum thermal_trip_activation_mode mode);
- };
- 
- #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
-@@ -300,6 +309,7 @@ struct tsens_context {
- struct tsens_priv {
- 	struct device			*dev;
- 	u32				num_sensors;
-+	u32				tsens_irq;
- 	struct regmap			*tm_map;
- 	struct regmap			*srot_map;
- 	u32				tm_offset;
-@@ -308,6 +318,7 @@ struct tsens_priv {
- 	const struct tsens_features	*feat;
- 	const struct reg_field		*fields;
- 	const struct tsens_ops		*ops;
-+	struct work_struct		tsens_work;
- 	struct tsens_sensor		sensor[0];
- };
- 
---- a/drivers/thermal/thermal_sysfs.c
-+++ b/drivers/thermal/thermal_sysfs.c
-@@ -113,12 +113,48 @@ trip_point_type_show(struct device *dev,
- 		return sprintf(buf, "passive\n");
- 	case THERMAL_TRIP_ACTIVE:
- 		return sprintf(buf, "active\n");
-+	case THERMAL_TRIP_CONFIGURABLE_HI:
-+		return sprintf(buf, "configurable_hi\n");
-+	case THERMAL_TRIP_CONFIGURABLE_LOW:
-+		return sprintf(buf, "configurable_low\n");
-+	case THERMAL_TRIP_CRITICAL_LOW:
-+		return sprintf(buf, "critical_low\n");
- 	default:
- 		return sprintf(buf, "unknown\n");
- 	}
- }
- 
- static ssize_t
-+trip_point_type_activate(struct device *dev, struct device_attribute *attr,
-+						const char *buf, size_t count)
-+{
-+	struct thermal_zone_device *tz = to_thermal_zone(dev);
-+	int trip, ret;
-+	char *enabled = "enabled";
-+	char *disabled = "disabled";
-+
-+	if (!tz->ops->set_trip_activate)
-+		return -EPERM;
-+
-+	if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip))
-+		return -EINVAL;
-+
-+	if (!strncmp(buf, enabled, strlen(enabled)))
-+		ret = tz->ops->set_trip_activate(tz, trip,
-+				THERMAL_TRIP_ACTIVATION_ENABLED);
-+	else if (!strncmp(buf, disabled, strlen(disabled)))
-+		ret = tz->ops->set_trip_activate(tz, trip,
-+				THERMAL_TRIP_ACTIVATION_DISABLED);
-+	else
-+		ret = -EINVAL;
-+
-+	if (ret)
-+		return ret;
-+
-+	return count;
-+}
-+
-+static ssize_t
- trip_point_temp_store(struct device *dev, struct device_attribute *attr,
- 		      const char *buf, size_t count)
- {
-@@ -559,6 +595,12 @@ static int create_trip_attrs(struct ther
- 		tz->trip_type_attrs[indx].attr.show = trip_point_type_show;
- 		attrs[indx] = &tz->trip_type_attrs[indx].attr.attr;
- 
-+		if (IS_ENABLED(CONFIG_THERMAL_WRITABLE_TRIPS)) {
-+			tz->trip_type_attrs[indx].attr.store
-+						= trip_point_type_activate;
-+			tz->trip_type_attrs[indx].attr.attr.mode |= S_IWUSR;
-+		}
-+
- 		/* create trip temp attribute */
- 		snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH,
- 			 "trip_point_%d_temp", indx);
---- a/include/linux/thermal.h
-+++ b/include/linux/thermal.h
-@@ -63,11 +63,19 @@ enum thermal_device_mode {
- 	THERMAL_DEVICE_ENABLED,
- };
- 
-+enum thermal_trip_activation_mode {
-+	THERMAL_TRIP_ACTIVATION_DISABLED = 0,
-+	THERMAL_TRIP_ACTIVATION_ENABLED,
-+};
-+
- enum thermal_trip_type {
- 	THERMAL_TRIP_ACTIVE = 0,
- 	THERMAL_TRIP_PASSIVE,
- 	THERMAL_TRIP_HOT,
- 	THERMAL_TRIP_CRITICAL,
-+	THERMAL_TRIP_CONFIGURABLE_HI,
-+	THERMAL_TRIP_CONFIGURABLE_LOW,
-+	THERMAL_TRIP_CRITICAL_LOW,
- };
- 
- enum thermal_trend {
-@@ -105,6 +113,8 @@ struct thermal_zone_device_ops {
- 		enum thermal_trip_type *);
- 	int (*get_trip_temp) (struct thermal_zone_device *, int, int *);
- 	int (*set_trip_temp) (struct thermal_zone_device *, int, int);
-+	int (*set_trip_activate) (struct thermal_zone_device *, int,
-+					enum thermal_trip_activation_mode);
- 	int (*get_trip_hyst) (struct thermal_zone_device *, int, int *);
- 	int (*set_trip_hyst) (struct thermal_zone_device *, int, int);
- 	int (*get_crit_temp) (struct thermal_zone_device *, int *);
-@@ -349,6 +359,8 @@ struct thermal_genl_event {
-  *		   temperature.
-  * @set_trip_temp: a pointer to a function that sets the trip temperature on
-  *		   hardware.
-+ * @activate_trip_type: a pointer to a function to enable/disable trip
-+ *		temperature interrupts
-  */
- struct thermal_zone_of_device_ops {
- 	int (*get_temp)(void *, int *);
-@@ -356,6 +368,8 @@ struct thermal_zone_of_device_ops {
- 	int (*set_trips)(void *, int, int);
- 	int (*set_emul_temp)(void *, int);
- 	int (*set_trip_temp)(void *, int, int);
-+	int (*set_trip_activate)(void *, int,
-+				enum thermal_trip_activation_mode);
- };
- 
- /**
diff --git a/target/linux/ipq806x/patches-5.4/0063-3-tsens-fix-kernel-5_4.patch b/target/linux/ipq806x/patches-5.4/0063-3-tsens-fix-kernel-5_4.patch
deleted file mode 100644
index 6c056db3b75e65..00000000000000
--- a/target/linux/ipq806x/patches-5.4/0063-3-tsens-fix-kernel-5_4.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/drivers/thermal/qcom/tsens-ipq8064.c
-+++ b/drivers/thermal/qcom/tsens-ipq8064.c
-@@ -18,6 +18,7 @@
- #include <linux/regmap.h>
- #include <linux/thermal.h>
- #include <linux/nvmem-consumer.h>
-+#include <linux/of_platform.h>
- #include <linux/io.h>
- #include <linux/interrupt.h>
- #include "tsens.h"
-@@ -320,15 +321,42 @@ static void hw_init(struct tsens_priv *p
- 	INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
- }
- 
-+static const struct regmap_config tsens_config = {
-+	.name		= "tm",
-+	.reg_bits	= 32,
-+	.val_bits	= 32,
-+	.reg_stride	= 4,
-+};
-+
- static int init_ipq8064(struct tsens_priv *priv)
- {
--	int ret, i;
-+	struct device *dev = priv->dev;
- 	u32 reg_cntl, offset = 0;
-+	struct resource *res;
-+	resource_size_t size;
-+	void __iomem *base;
-+	int ret, i;
-+	struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
-+
-+	if (!op)
-+		return -EINVAL;
- 
--	init_common(priv);
--	if (!priv->tm_map)
--		return -ENODEV;
-+	/* old DTs where SROT and TM were in a contiguous 2K block */
-+	priv->tm_offset = 0x1000;
- 
-+	res = platform_get_resource(op, IORESOURCE_MEM, 0);
-+	size = resource_size(res);
-+	base = devm_ioremap(&op->dev, res->start, size);
-+	if (IS_ERR(base)) {
-+		ret = PTR_ERR(base);
-+		goto err_put_device;
-+	}
-+
-+	priv->tm_map = devm_regmap_init_mmio(dev, base, &tsens_config);
-+	if (IS_ERR(priv->tm_map)) {
-+		ret = PTR_ERR(priv->tm_map);
-+		goto err_put_device;
-+	}
- 	/*
- 	 * The status registers for each sensor are discontiguous
- 	 * because some SoCs have 5 sensors while others have more
-@@ -367,6 +395,10 @@ static int init_ipq8064(struct tsens_pri
- 		return ret;
- 
- 	return 0;
-+
-+err_put_device:
-+	put_device(&op->dev);
-+	return ret;
- }
- 
- static int calibrate_ipq8064(struct tsens_priv *priv)
diff --git a/target/linux/ipq806x/patches-5.4/0063-4-ip806x-tsense-rework-driver.patch b/target/linux/ipq806x/patches-5.4/0063-4-ip806x-tsense-rework-driver.patch
deleted file mode 100644
index 67fc8db7a37644..00000000000000
--- a/target/linux/ipq806x/patches-5.4/0063-4-ip806x-tsense-rework-driver.patch
+++ /dev/null
@@ -1,107 +0,0 @@
---- a/drivers/thermal/qcom/tsens-ipq8064.c
-+++ b/drivers/thermal/qcom/tsens-ipq8064.c
-@@ -13,10 +13,12 @@
-  */
- 
- #include <linux/platform_device.h>
-+#include <linux/err.h>
- #include <linux/delay.h>
- #include <linux/bitops.h>
- #include <linux/regmap.h>
- #include <linux/thermal.h>
-+#include <linux/slab.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_platform.h>
- #include <linux/io.h>
-@@ -211,9 +213,8 @@ static void tsens_scheduler_fn(struct wo
- 	struct tsens_priv *priv = container_of(work, struct tsens_priv,
- 					tsens_work);
- 	unsigned int threshold, threshold_low, code, reg, sensor, mask;
--	unsigned int sensor_addr;
- 	bool upper_th_x, lower_th_x;
--	int adc_code, ret;
-+	int ret;
- 
- 	ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
- 	if (ret)
-@@ -262,9 +263,8 @@ static void tsens_scheduler_fn(struct wo
- 		if (upper_th_x || lower_th_x) {
- 			/* Notify user space */
- 			schedule_work(&priv->sensor[0].notify_work);
--			regmap_read(priv->tm_map, sensor_addr, &adc_code);
- 			pr_debug("Trigger (%d degrees) for sensor %d\n",
--				code_to_degC(adc_code, &priv->sensor[0]), 0);
-+				code_to_degC(code, &priv->sensor[0]), 0);
- 		}
- 	}
- 	regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
-@@ -404,40 +404,55 @@ err_put_device:
- static int calibrate_ipq8064(struct tsens_priv *priv)
- {
- 	int i;
--	char *data, *data_backup;
--
-+	int ret = 0;
-+	u8 *data, *data_backup;
-+	struct device *dev = priv->dev;
- 	ssize_t num_read = priv->num_sensors;
- 	struct tsens_sensor *s = priv->sensor;
- 
--	data = qfprom_read(priv->dev, "calib");
-+	data = qfprom_read(dev, "calib");
- 	if (IS_ERR(data)) {
--		pr_err("Calibration not found.\n");
--		return PTR_ERR(data);
-+		ret = PTR_ERR(data);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(dev, "Calibration not found.");
-+		goto exit;
- 	}
- 
--	data_backup = qfprom_read(priv->dev, "calib_backup");
-+	data_backup = qfprom_read(dev, "calib_backup");
- 	if (IS_ERR(data_backup)) {
--		pr_err("Backup calibration not found.\n");
--		return PTR_ERR(data_backup);
-+		ret = PTR_ERR(data_backup);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(dev, "Backup Calibration not found.");
-+		goto free_data;
- 	}
- 
- 	for (i = 0; i < num_read; i++) {
- 		s[i].calib_data = readb_relaxed(data + i);
--		s[i].calib_data_backup = readb_relaxed(data_backup + i);
-+		
-+		if (!s[i].calib_data) {
-+			s[i].calib_data_backup = readb_relaxed(data_backup + i);
-+
-+			if (!s[i].calib_data_backup) {
-+				dev_err(dev, "QFPROM TSENS calibration data not present");
-+				ret = -ENODEV;
-+				goto free_backup;
-+			}
- 
--		if (s[i].calib_data_backup)
- 			s[i].calib_data = s[i].calib_data_backup;
--		if (!s[i].calib_data) {
--			pr_err("QFPROM TSENS calibration data not present\n");
--			return -ENODEV;
- 		}
-+
- 		s[i].slope = tsens_8064_slope[i];
- 		s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
- 	}
- 
- 	hw_init(priv);
- 
--	return 0;
-+free_backup:
-+	kfree(data_backup);
-+free_data:
-+	kfree(data);
-+exit:
-+	return ret;
- }
- 
- static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
diff --git a/target/linux/ipq806x/patches-5.4/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq806x/patches-5.4/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch
deleted file mode 100644
index 0dc9debbfd6d91..00000000000000
--- a/target/linux/ipq806x/patches-5.4/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From patchwork Mon May 21 20:57:38 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
-X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
-X-Patchwork-Id: 917856
-Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
-To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
- linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
-Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
- Linus Walleij <linus.walleij@linaro.org>,
- Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
- Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
- Andy Gross <andy.gross@linaro.org>,
- Sven Eckelmann <sven.eckelmann@openmesh.com>
-Date: Mon, 21 May 2018 22:57:38 +0200
-From: Christian Lamparter <chunkeey@gmail.com>
-List-Id: <linux-gpio.vger.kernel.org>
-
-This patch adds the gpio-ranges property to almost all of
-the Qualcomm ARM platforms that utilize the pinctrl-msm
-framework.
-
-The gpio-ranges property is part of the gpiolib subsystem.
-As a result, the binding text is available in section
-"2.1 gpio- and pin-controller interaction" of
-Documentation/devicetree/bindings/gpio/gpio.txt
-
-For more information please see the patch titled:
-"pinctrl: msm: fix gpio-hog related boot issues" from
-this series.
-
-Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
-Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
----
-To help with git bisect, the DT update patch has been intentionally
-placed after the "pinctrl: msm: fix gpio-hog related boot issues".
-Otherwise - if the order was reveresed - and bisect decides to split
-between these two patches, the gpiochip_add_pin_ranges() function
-will be executed twice with the same parameters for the same pinctrl.
----
- arch/arm/boot/dts/qcom-apq8064.dtsi   | 1 +
- arch/arm/boot/dts/qcom-apq8084.dtsi   | 1 +
- arch/arm/boot/dts/qcom-ipq4019.dtsi   | 1 +
- arch/arm/boot/dts/qcom-ipq8064.dtsi   | 1 +
- arch/arm/boot/dts/qcom-mdm9615.dtsi   | 1 +
- arch/arm/boot/dts/qcom-msm8660.dtsi   | 1 +
- arch/arm/boot/dts/qcom-msm8960.dtsi   | 1 +
- arch/arm/boot/dts/qcom-msm8974.dtsi   | 1 +
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
- arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
- arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
- 13 files changed, 14 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -119,6 +119,7 @@
- 			reg = <0x800000 0x4000>;
- 
- 			gpio-controller;
-+			gpio-ranges = <&qcom_pinmux 0 0 69>;
- 			#gpio-cells = <2>;
- 			interrupt-controller;
- 			#interrupt-cells = <2>;
diff --git a/target/linux/ipq806x/patches-5.4/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch b/target/linux/ipq806x/patches-5.4/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch
deleted file mode 100644
index f5483ac7347385..00000000000000
--- a/target/linux/ipq806x/patches-5.4/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Thu, 19 Mar 2020 23:44:24 +0100
-Subject: ARM: dts: qcom: add scm definition to ipq806x
-
-Add missing scm definition for ipq806x soc
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -93,6 +93,12 @@
- 		};
- 	};
- 
-+	firmware {
-+		scm {
-+			compatible = "qcom,scm-ipq806x", "qcom,scm";
-+		};
-+	};
-+
- 	soc: soc {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
diff --git a/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
deleted file mode 100644
index 2b5171fc54096f..00000000000000
--- a/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
-From: Ajay Kishore <akisho@codeaurora.org>
-Date: Fri, 27 Mar 2020 23:32:08 +0100
-Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
-
-For IPQ806x targets, TZ protects the registers that are used to
-configure the routing of interrupts to a target processor.
-To resolve this, this patch uses scm call to route GPIO interrupts
-to application processor. Also the scm call interface is changed.
-
-Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
- 1 file changed, 37 insertions(+), 6 deletions(-)
-
-(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
-
---- a/drivers/pinctrl/qcom/pinctrl-msm.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
-@@ -22,6 +22,8 @@
- #include <linux/reboot.h>
- #include <linux/pm.h>
- #include <linux/log2.h>
-+#include <linux/qcom_scm.h>
-+#include <linux/io.h>
- 
- #include "../core.h"
- #include "../pinconf.h"
-@@ -57,6 +59,8 @@ struct msm_pinctrl {
- 	struct irq_chip irq_chip;
- 	int irq;
- 
-+	bool intr_target_use_scm;
-+
- 	raw_spinlock_t lock;
- 
- 	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
-@@ -64,6 +68,7 @@ struct msm_pinctrl {
- 
- 	const struct msm_pinctrl_soc_data *soc;
- 	void __iomem *regs[MAX_NR_TILES];
-+	u32 phys_base[MAX_NR_TILES];
- };
- 
- #define MSM_ACCESSOR(name) \
-@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
- 	else
- 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
- 
--	/* Route interrupts to application cpu */
--	val = msm_readl_intr_target(pctrl, g);
--	val &= ~(7 << g->intr_target_bit);
--	val |= g->intr_target_kpss_val << g->intr_target_bit;
--	msm_writel_intr_target(val, pctrl, g);
-+	/* Route interrupts to application cpu.
-+	 * With intr_target_use_scm interrupts are routed to
-+	 * application cpu using scm calls.
-+	 */
-+	if (pctrl->intr_target_use_scm) {
-+		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
-+		int ret;
-+
-+		qcom_scm_io_readl(addr, &val);
-+
-+		val &= ~(7 << g->intr_target_bit);
-+		val |= g->intr_target_kpss_val << g->intr_target_bit;
-+
-+		ret = qcom_scm_io_writel(addr, val);
-+		if (ret)
-+			dev_err(pctrl->dev,
-+				"Failed routing %lu interrupt to Apps proc",
-+				d->hwirq);
-+	} else {
-+		val = msm_readl_intr_target(pctrl, g);
-+		val &= ~(7 << g->intr_target_bit);
-+		val |= g->intr_target_kpss_val << g->intr_target_bit;
-+		msm_writel_intr_target(val, pctrl, g);
-+	}
- 
- 	/* Update configuration for gpio.
- 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
-@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
- 	pctrl->dev = &pdev->dev;
- 	pctrl->soc = soc_data;
- 	pctrl->chip = msm_gpio_template;
-+	pctrl->intr_target_use_scm = of_device_is_compatible(
-+					pctrl->dev->of_node,
-+					"qcom,ipq8064-pinctrl");
- 
- 	raw_spin_lock_init(&pctrl->lock);
- 
-@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
- 		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
- 		if (IS_ERR(pctrl->regs[0]))
- 			return PTR_ERR(pctrl->regs[0]);
-+
-+		pctrl->phys_base[0] = res->start;
- 	}
- 
- 	msm_pinctrl_setup_pm_reset(pctrl);
diff --git a/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
deleted file mode 100644
index 612c33cd0e42f6..00000000000000
--- a/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Wed, 19 Feb 2020 18:59:39 +0100
-Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
-
-Add missing gpio definition for mdio and rgmii2.
-
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
-+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
-@@ -299,7 +299,7 @@ static const char * const gpio_groups[]
- };
- 
- static const char * const mdio_groups[] = {
--	"gpio0", "gpio1", "gpio10", "gpio11",
-+	"gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
- };
- 
- static const char * const mi2s_groups[] = {
-@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou
- };
- 
- static const char * const rgmii2_groups[] = {
--	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
--	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
-+	"gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
-+	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
- };
- 
- static const char * const sata_groups[] = {
-@@ -539,7 +539,7 @@ static const struct msm_function ipq8064
- static const struct msm_pingroup ipq8064_groups[] = {
- 	PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
-@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064
- 	PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
diff --git a/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch b/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch
deleted file mode 100644
index 1bd44fd5a0b251..00000000000000
--- a/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 4 Feb 2020 20:56:48 +0100
-Subject: watchdog: qcom-wdt: disable pretimeout on timer platform
-
-Some platform like ipq806x doesn't support pretimeout and define
-some interrupts used by qcom,msm-timer. Change the driver to check
-and use pretimeout only on qcom,kpss-wdt as it's the only platform
-that actually supports it.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com
-[groeck: Conflict resolution]
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++--------
- 1 file changed, 23 insertions(+), 8 deletions(-)
-
---- a/drivers/watchdog/qcom-wdt.c
-+++ b/drivers/watchdog/qcom-wdt.c
-@@ -39,6 +39,11 @@ static const u32 reg_offset_data_kpss[]
- 	[WDT_BITE_TIME] = 0x14,
- };
- 
-+struct qcom_wdt_match_data {
-+	const u32 *offset;
-+	bool pretimeout;
-+};
-+
- struct qcom_wdt {
- 	struct watchdog_device	wdd;
- 	unsigned long		rate;
-@@ -168,19 +173,29 @@ static void qcom_clk_disable_unprepare(v
- 	clk_disable_unprepare(data);
- }
- 
-+static const struct qcom_wdt_match_data match_data_apcs_tmr = {
-+	.offset = reg_offset_data_apcs_tmr,
-+	.pretimeout = false,
-+};
-+
-+static const struct qcom_wdt_match_data match_data_kpss = {
-+	.offset = reg_offset_data_kpss,
-+	.pretimeout = true,
-+};
-+
- static int qcom_wdt_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
- 	struct qcom_wdt *wdt;
- 	struct resource *res;
- 	struct device_node *np = dev->of_node;
--	const u32 *regs;
-+	const struct qcom_wdt_match_data *data;
- 	u32 percpu_offset;
- 	int irq, ret;
- 	struct clk *clk;
- 
--	regs = of_device_get_match_data(dev);
--	if (!regs) {
-+	data = of_device_get_match_data(dev);
-+	if (!data) {
- 		dev_err(dev, "Unsupported QCOM WDT module\n");
- 		return -ENODEV;
- 	}
-@@ -236,7 +251,7 @@ static int qcom_wdt_probe(struct platfor
- 
- 	/* check if there is pretimeout support */
- 	irq = platform_get_irq_optional(pdev, 0);
--	if (irq > 0) {
-+	if (data->pretimeout && irq > 0) {
- 		ret = devm_request_irq(dev, irq, qcom_wdt_isr,
- 				       IRQF_TRIGGER_RISING,
- 				       "wdt_bark", &wdt->wdd);
-@@ -256,7 +271,7 @@ static int qcom_wdt_probe(struct platfor
- 	wdt->wdd.min_timeout = 1;
- 	wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
- 	wdt->wdd.parent = dev;
--	wdt->layout = regs;
-+	wdt->layout = data->offset;
- 
- 	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
- 		wdt->wdd.bootstatus = WDIOF_CARDRESET;
-@@ -300,9 +315,9 @@ static int __maybe_unused qcom_wdt_resum
- static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
- 
- static const struct of_device_id qcom_wdt_of_table[] = {
--	{ .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
--	{ .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
--	{ .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
-+	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
-+	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
-+	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
- 	{ },
- };
- MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
diff --git a/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch b/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch
deleted file mode 100644
index 015a917e20995d..00000000000000
--- a/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
-From: Abhishek Sahu <absahu@codeaurora.org>
-Date: Wed, 18 Mar 2020 14:16:56 +0100
-Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
-
-Kernel got hanged while reading from /dev/hwrng at the
-time of PRNG clock enable
-
-Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
-Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/qcom/gcc-ipq806x.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -1225,6 +1225,8 @@ static struct clk_rcg prng_src = {
- 		.parent_map = gcc_pxo_pll8_map,
- 	},
- 	.clkr = {
-+		.enable_reg = 0x2e80,
-+		.enable_mask = BIT(11),
- 		.hw.init = &(struct clk_init_data){
- 			.name = "prng_src",
- 			.parent_names = gcc_pxo_pll8,
diff --git a/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch b/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch
deleted file mode 100644
index a28570974e2783..00000000000000
--- a/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 10 Mar 2020 15:37:56 +0100
-Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x
-
-Add missing definition of rpm clk for ipq806x soc
-
-Signed-off-by: John Crispin <john@phrozen.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Acked-by: John Crispin <john@phrozen.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../devicetree/bindings/clock/qcom,rpmcc.txt       |  1 +
- drivers/clk/qcom/clk-rpm.c                         | 35 ++++++++++++++++++++++
- include/dt-bindings/clock/qcom,rpmcc.h             |  4 +++
- 3 files changed, 40 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
-+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
-@@ -15,6 +15,7 @@ Required properties :
- 			"qcom,rpmcc-msm8916", "qcom,rpmcc"
- 			"qcom,rpmcc-msm8974", "qcom,rpmcc"
- 			"qcom,rpmcc-apq8064", "qcom,rpmcc"
-+			"qcom,rpmcc-ipq806x", "qcom,rpmcc"
- 			"qcom,rpmcc-msm8996", "qcom,rpmcc"
- 			"qcom,rpmcc-msm8998", "qcom,rpmcc"
- 			"qcom,rpmcc-qcs404", "qcom,rpmcc"
---- a/drivers/clk/qcom/clk-rpm.c
-+++ b/drivers/clk/qcom/clk-rpm.c
-@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk
- 	.num_clks = ARRAY_SIZE(apq8064_clks),
- };
- 
-+/* ipq806x */
-+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
-+DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
-+DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
-+DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
-+DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
-+DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
-+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
-+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
-+
-+static struct clk_rpm *ipq806x_clks[] = {
-+	[RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
-+	[RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
-+	[RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
-+	[RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
-+	[RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
-+	[RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
-+	[RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
-+	[RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
-+	[RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
-+	[RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
-+	[RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
-+	[RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
-+	[RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
-+	[RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
-+	[RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
-+	[RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
-+};
-+
-+static const struct rpm_clk_desc rpm_clk_ipq806x = {
-+	.clks = ipq806x_clks,
-+	.num_clks = ARRAY_SIZE(ipq806x_clks),
-+};
-+
- static const struct of_device_id rpm_clk_match_table[] = {
- 	{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
- 	{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
- 	{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
-+	{ .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
---- a/include/dt-bindings/clock/qcom,rpmcc.h
-+++ b/include/dt-bindings/clock/qcom,rpmcc.h
-@@ -37,6 +37,10 @@
- #define RPM_XO_A0				27
- #define RPM_XO_A1				28
- #define RPM_XO_A2				29
-+#define RPM_NSS_FABRIC_0_CLK			30
-+#define RPM_NSS_FABRIC_0_A_CLK			31
-+#define RPM_NSS_FABRIC_1_CLK			32
-+#define RPM_NSS_FABRIC_1_A_CLK			33
- 
- /* SMD RPM clocks */
- #define RPM_SMD_XO_CLK_SRC				0
diff --git a/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch b/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch
deleted file mode 100644
index 42a02865a3217e..00000000000000
--- a/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Wed, 19 Feb 2020 17:37:11 +0100
-Subject: regulator: add smb208 support
-
-Smb208 regulators are used on some ipq806x soc.
-Add support for it to make it avaiable on some routers
-that use it.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-Acked-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
- drivers/regulator/qcom_rpm-regulator.c             | 9 +++++++++
- 2 files changed, 13 insertions(+)
-
---- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
-+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt
-@@ -61,6 +61,7 @@ Regulator nodes are identified by their
- 		    "qcom,rpm-pm8901-regulators"
- 		    "qcom,rpm-pm8921-regulators"
- 		    "qcom,rpm-pm8018-regulators"
-+		    "qcom,rpm-smb208-regulators"
- 
- - vdd_l0_l1_lvs-supply:
- - vdd_l2_l11_l12-supply:
-@@ -171,6 +172,9 @@ pm8018:
- 	s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
- 	l12, l14, lvs1
- 
-+smb208:
-+	s1a, s1b, s2a, s2b
-+
- The content of each sub-node is defined by the standard binding for regulators -
- see regulator.txt - with additional custom properties described below:
- 
---- a/drivers/regulator/qcom_rpm-regulator.c
-+++ b/drivers/regulator/qcom_rpm-regulator.c
-@@ -925,12 +925,21 @@ static const struct rpm_regulator_data r
- 	{ }
- };
- 
-+static const struct rpm_regulator_data rpm_smb208_regulators[] = {
-+	{ "s1a",  QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" },
-+	{ "s1b",  QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" },
-+	{ "s2a",  QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" },
-+	{ "s2b",  QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" },
-+	{ }
-+};
-+
- static const struct of_device_id rpm_of_match[] = {
- 	{ .compatible = "qcom,rpm-pm8018-regulators",
- 		.data = &rpm_pm8018_regulators },
- 	{ .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators },
- 	{ .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators },
- 	{ .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators },
-+	{ .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, rpm_of_match);
diff --git a/target/linux/ipq806x/patches-5.4/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch b/target/linux/ipq806x/patches-5.4/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch
deleted file mode 100644
index 06b18b385211ac..00000000000000
--- a/target/linux/ipq806x/patches-5.4/092-1-v5.7-qcom-cpufreq-nvmem-Add-support-for-krait-based-socs.patch
+++ /dev/null
@@ -1,361 +0,0 @@
-From a8811ec764f95a04ba82f6f457e28c5e9e36e36b Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Fri, 13 Mar 2020 18:52:13 +0100
-Subject: cpufreq: qcom: Add support for krait based socs
-
-In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
-that has KRAIT processors the voltage/current value of each OPP
-varies based on the silicon variant in use.
-
-The required OPP related data is determined based on
-the efuse value. This is similar to the existing code for
-kryo cores. So adding support for krait cores here.
-
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- .../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt |   3 +-
- drivers/cpufreq/Kconfig.arm                        |   2 +-
- drivers/cpufreq/cpufreq-dt-platdev.c               |   5 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c               | 191 +++++++++++++++++++--
- 4 files changed, 183 insertions(+), 18 deletions(-)
-
---- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
-+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
-@@ -19,7 +19,8 @@ In 'cpu' nodes:
- 
- In 'operating-points-v2' table:
- - compatible: Should be
--	- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
-+	- 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
-+					     apq8064, ipq8064, msm8960 and ipq8074.
- 
- Optional properties:
- --------------------
---- a/drivers/cpufreq/Kconfig.arm
-+++ b/drivers/cpufreq/Kconfig.arm
-@@ -135,7 +135,7 @@ config ARM_OMAP2PLUS_CPUFREQ
- 
- config ARM_QCOM_CPUFREQ_NVMEM
- 	tristate "Qualcomm nvmem based CPUFreq"
--	depends on ARM64
-+	depends on ARCH_QCOM
- 	depends on QCOM_QFPROM
- 	depends on QCOM_SMEM
- 	select PM_OPP
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -141,6 +141,11 @@ static const struct of_device_id blackli
- 	{ .compatible = "ti,am43", },
- 	{ .compatible = "ti,dra7", },
- 
-+	{ .compatible = "qcom,ipq8064", },
-+	{ .compatible = "qcom,apq8064", },
-+	{ .compatible = "qcom,msm8974", },
-+	{ .compatible = "qcom,msm8960", },
-+
- 	{ }
- };
- 
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -49,12 +49,14 @@ struct qcom_cpufreq_drv;
- struct qcom_cpufreq_match_data {
- 	int (*get_version)(struct device *cpu_dev,
- 			   struct nvmem_cell *speedbin_nvmem,
-+			   char **pvs_name,
- 			   struct qcom_cpufreq_drv *drv);
- 	const char **genpd_names;
- };
- 
- struct qcom_cpufreq_drv {
--	struct opp_table **opp_tables;
-+	struct opp_table **names_opp_tables;
-+	struct opp_table **hw_opp_tables;
- 	struct opp_table **genpd_opp_tables;
- 	u32 versions;
- 	const struct qcom_cpufreq_match_data *data;
-@@ -62,6 +64,84 @@ struct qcom_cpufreq_drv {
- 
- static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
- 
-+static void get_krait_bin_format_a(struct device *cpu_dev,
-+					  int *speed, int *pvs, int *pvs_ver,
-+					  struct nvmem_cell *pvs_nvmem, u8 *buf)
-+{
-+	u32 pte_efuse;
-+
-+	pte_efuse = *((u32 *)buf);
-+
-+	*speed = pte_efuse & 0xf;
-+	if (*speed == 0xf)
-+		*speed = (pte_efuse >> 4) & 0xf;
-+
-+	if (*speed == 0xf) {
-+		*speed = 0;
-+		dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
-+	} else {
-+		dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
-+	}
-+
-+	*pvs = (pte_efuse >> 10) & 0x7;
-+	if (*pvs == 0x7)
-+		*pvs = (pte_efuse >> 13) & 0x7;
-+
-+	if (*pvs == 0x7) {
-+		*pvs = 0;
-+		dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
-+	} else {
-+		dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
-+	}
-+}
-+
-+static void get_krait_bin_format_b(struct device *cpu_dev,
-+					  int *speed, int *pvs, int *pvs_ver,
-+					  struct nvmem_cell *pvs_nvmem, u8 *buf)
-+{
-+	u32 pte_efuse, redundant_sel;
-+
-+	pte_efuse = *((u32 *)buf);
-+	redundant_sel = (pte_efuse >> 24) & 0x7;
-+
-+	*pvs_ver = (pte_efuse >> 4) & 0x3;
-+
-+	switch (redundant_sel) {
-+	case 1:
-+		*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
-+		*speed = (pte_efuse >> 27) & 0xf;
-+		break;
-+	case 2:
-+		*pvs = (pte_efuse >> 27) & 0xf;
-+		*speed = pte_efuse & 0x7;
-+		break;
-+	default:
-+		/* 4 bits of PVS are in efuse register bits 31, 8-6. */
-+		*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
-+		*speed = pte_efuse & 0x7;
-+	}
-+
-+	/* Check SPEED_BIN_BLOW_STATUS */
-+	if (pte_efuse & BIT(3)) {
-+		dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
-+	} else {
-+		dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
-+		*speed = 0;
-+	}
-+
-+	/* Check PVS_BLOW_STATUS */
-+	pte_efuse = *(((u32 *)buf) + 4);
-+	pte_efuse &= BIT(21);
-+	if (pte_efuse) {
-+		dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
-+	} else {
-+		dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
-+		*pvs = 0;
-+	}
-+
-+	dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
-+}
-+
- static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
- {
- 	size_t len;
-@@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufre
- 
- static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
- 					  struct nvmem_cell *speedbin_nvmem,
-+					  char **pvs_name,
- 					  struct qcom_cpufreq_drv *drv)
- {
- 	size_t len;
- 	u8 *speedbin;
- 	enum _msm8996_version msm8996_version;
-+	*pvs_name = NULL;
- 
- 	msm8996_version = qcom_cpufreq_get_msm_id();
- 	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
-@@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_versio
- 	return 0;
- }
- 
-+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
-+					   struct nvmem_cell *speedbin_nvmem,
-+					   char **pvs_name,
-+					   struct qcom_cpufreq_drv *drv)
-+{
-+	int speed = 0, pvs = 0, pvs_ver = 0;
-+	u8 *speedbin;
-+	size_t len;
-+
-+	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
-+
-+	if (IS_ERR(speedbin))
-+		return PTR_ERR(speedbin);
-+
-+	switch (len) {
-+	case 4:
-+		get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
-+				       speedbin_nvmem, speedbin);
-+		break;
-+	case 8:
-+		get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
-+				       speedbin_nvmem, speedbin);
-+		break;
-+	default:
-+		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
-+		return -ENODEV;
-+	}
-+
-+	snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
-+		 speed, pvs, pvs_ver);
-+
-+	drv->versions = (1 << speed);
-+
-+	kfree(speedbin);
-+	return 0;
-+}
-+
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- 	.get_version = qcom_cpufreq_kryo_name_version,
- };
- 
-+static const struct qcom_cpufreq_match_data match_data_krait = {
-+	.get_version = qcom_cpufreq_krait_name_version,
-+};
-+
- static const char *qcs404_genpd_names[] = { "cpr", NULL };
- 
- static const struct qcom_cpufreq_match_data match_data_qcs404 = {
-@@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct pla
- 	struct nvmem_cell *speedbin_nvmem;
- 	struct device_node *np;
- 	struct device *cpu_dev;
-+	char *pvs_name = "speedXX-pvsXX-vXX";
- 	unsigned cpu;
- 	const struct of_device_id *match;
- 	int ret;
-@@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
- 	if (!np)
- 		return -ENOENT;
- 
--	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
-+	ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
- 	if (!ret) {
- 		of_node_put(np);
- 		return -ENOENT;
-@@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct pla
- 			goto free_drv;
- 		}
- 
--		ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
-+		ret = drv->data->get_version(cpu_dev,
-+							speedbin_nvmem, &pvs_name, drv);
- 		if (ret) {
- 			nvmem_cell_put(speedbin_nvmem);
- 			goto free_drv;
-@@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct pla
- 	}
- 	of_node_put(np);
- 
--	drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
-+	drv->names_opp_tables = kcalloc(num_possible_cpus(),
-+				  sizeof(*drv->names_opp_tables),
- 				  GFP_KERNEL);
--	if (!drv->opp_tables) {
-+	if (!drv->names_opp_tables) {
- 		ret = -ENOMEM;
- 		goto free_drv;
- 	}
-+	drv->hw_opp_tables = kcalloc(num_possible_cpus(),
-+				  sizeof(*drv->hw_opp_tables),
-+				  GFP_KERNEL);
-+	if (!drv->hw_opp_tables) {
-+		ret = -ENOMEM;
-+		goto free_opp_names;
-+	}
- 
- 	drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
- 					sizeof(*drv->genpd_opp_tables),
-@@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct pla
- 		}
- 
- 		if (drv->data->get_version) {
--			drv->opp_tables[cpu] =
--				dev_pm_opp_set_supported_hw(cpu_dev,
--							    &drv->versions, 1);
--			if (IS_ERR(drv->opp_tables[cpu])) {
--				ret = PTR_ERR(drv->opp_tables[cpu]);
-+
-+			if (pvs_name) {
-+				drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
-+								     cpu_dev,
-+								     pvs_name);
-+				if (IS_ERR(drv->names_opp_tables[cpu])) {
-+					ret = PTR_ERR(drv->names_opp_tables[cpu]);
-+					dev_err(cpu_dev, "Failed to add OPP name %s\n",
-+						pvs_name);
-+					goto free_opp;
-+				}
-+			}
-+
-+			drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
-+									 cpu_dev, &drv->versions, 1);
-+			if (IS_ERR(drv->hw_opp_tables[cpu])) {
-+				ret = PTR_ERR(drv->hw_opp_tables[cpu]);
- 				dev_err(cpu_dev,
- 					"Failed to set supported hardware\n");
- 				goto free_genpd_opp;
-@@ -259,11 +404,18 @@ free_genpd_opp:
- 	kfree(drv->genpd_opp_tables);
- free_opp:
- 	for_each_possible_cpu(cpu) {
--		if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
-+		if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
-+			break;
-+		dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
-+	}
-+	for_each_possible_cpu(cpu) {
-+		if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
- 			break;
--		dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
-+		dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
- 	}
--	kfree(drv->opp_tables);
-+	kfree(drv->hw_opp_tables);
-+free_opp_names:
-+	kfree(drv->names_opp_tables);
- free_drv:
- 	kfree(drv);
- 
-@@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct pl
- 	platform_device_unregister(cpufreq_dt_pdev);
- 
- 	for_each_possible_cpu(cpu) {
--		if (drv->opp_tables[cpu])
--			dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
-+		if (drv->names_opp_tables[cpu])
-+			dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
-+		if (drv->hw_opp_tables[cpu])
-+			dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
- 		if (drv->genpd_opp_tables[cpu])
- 			dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
- 	}
- 
--	kfree(drv->opp_tables);
-+	kfree(drv->names_opp_tables);
-+	kfree(drv->hw_opp_tables);
- 	kfree(drv->genpd_opp_tables);
- 	kfree(drv);
- 
-@@ -303,6 +458,10 @@ static const struct of_device_id qcom_cp
- 	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
- 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
- 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
-+	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
-+	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
-+	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
-+	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
diff --git a/target/linux/ipq806x/patches-5.4/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch b/target/linux/ipq806x/patches-5.4/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch
deleted file mode 100644
index 764a917c1f0809..00000000000000
--- a/target/linux/ipq806x/patches-5.4/092-2-v5.7-cpufreq-qcom-fix-wrong-compatible-binding.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 2dea651680cea1f3a29925de51002f33d1f55711 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Fri, 1 May 2020 00:22:25 +0200
-Subject: cpufreq: qcom: fix wrong compatible binding
-
-Binding in Documentation is still "operating-points-v2-kryo-cpu".
-Restore the old binding to fix the compatibility problem.
-
-Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -277,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
- 	if (!np)
- 		return -ENOENT;
- 
--	ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
-+	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
- 	if (!ret) {
- 		of_node_put(np);
- 		return -ENOENT;
diff --git a/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch b/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
deleted file mode 100644
index ecfcd746930a0f..00000000000000
--- a/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
+++ /dev/null
@@ -1,228 +0,0 @@
-From 6a114526af4689938863bf34976c83bfd279f517 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 15 Jun 2020 23:06:02 +0200
-Subject: PCI: qcom: Use bulk clk api and assert on error
-
-Rework 2.1.0 revision to use bulk clk api and fix missing assert on
-reset_control_deassert error.
-
-Link: https://lore.kernel.org/r/20200615210608.21469-7-ansuelsmth@gmail.com
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 131 ++++++++++++---------------------
- 1 file changed, 46 insertions(+), 85 deletions(-)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -99,12 +99,9 @@
- #define SLV_ADDR_SPACE_SZ			0x10000000
- 
- #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
-+#define QCOM_PCIE_2_1_0_MAX_CLOCKS	5
- struct qcom_pcie_resources_2_1_0 {
--	struct clk *iface_clk;
--	struct clk *core_clk;
--	struct clk *phy_clk;
--	struct clk *aux_clk;
--	struct clk *ref_clk;
-+	struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
- 	struct reset_control *pci_reset;
- 	struct reset_control *axi_reset;
- 	struct reset_control *ahb_reset;
-@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0
- 	if (ret)
- 		return ret;
- 
--	res->iface_clk = devm_clk_get(dev, "iface");
--	if (IS_ERR(res->iface_clk))
--		return PTR_ERR(res->iface_clk);
--
--	res->core_clk = devm_clk_get(dev, "core");
--	if (IS_ERR(res->core_clk))
--		return PTR_ERR(res->core_clk);
--
--	res->phy_clk = devm_clk_get(dev, "phy");
--	if (IS_ERR(res->phy_clk))
--		return PTR_ERR(res->phy_clk);
--
--	res->aux_clk = devm_clk_get_optional(dev, "aux");
--	if (IS_ERR(res->aux_clk))
--		return PTR_ERR(res->aux_clk);
--
--	res->ref_clk = devm_clk_get_optional(dev, "ref");
--	if (IS_ERR(res->ref_clk))
--		return PTR_ERR(res->ref_clk);
-+	res->clks[0].id = "iface";
-+	res->clks[1].id = "core";
-+	res->clks[2].id = "phy";
-+	res->clks[3].id = "aux";
-+	res->clks[4].id = "ref";
-+
-+	/* iface, core, phy are required */
-+	ret = devm_clk_bulk_get(dev, 3, res->clks);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* aux, ref are optional */
-+	ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
-+	if (ret < 0)
-+		return ret;
- 
- 	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
- 	if (IS_ERR(res->pci_reset))
-@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc
- {
- 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- 
--	clk_disable_unprepare(res->phy_clk);
-+	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
- 	reset_control_assert(res->pci_reset);
- 	reset_control_assert(res->axi_reset);
- 	reset_control_assert(res->ahb_reset);
- 	reset_control_assert(res->por_reset);
- 	reset_control_assert(res->ext_reset);
- 	reset_control_assert(res->phy_reset);
--	clk_disable_unprepare(res->iface_clk);
--	clk_disable_unprepare(res->core_clk);
--	clk_disable_unprepare(res->aux_clk);
--	clk_disable_unprepare(res->ref_clk);
- 
- 	writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
- 
-@@ -334,47 +323,45 @@ static int qcom_pcie_init_2_1_0(struct q
- 		return ret;
- 	}
- 
--	ret = reset_control_assert(res->ahb_reset);
-+	ret = reset_control_deassert(res->ahb_reset);
- 	if (ret) {
--		dev_err(dev, "cannot assert ahb reset\n");
--		goto err_assert_ahb;
-+		dev_err(dev, "cannot deassert ahb reset\n");
-+		goto err_deassert_ahb;
- 	}
- 
--	ret = clk_prepare_enable(res->iface_clk);
-+	ret = reset_control_deassert(res->ext_reset);
- 	if (ret) {
--		dev_err(dev, "cannot prepare/enable iface clock\n");
--		goto err_assert_ahb;
-+		dev_err(dev, "cannot deassert ext reset\n");
-+		goto err_deassert_ext;
- 	}
- 
--	ret = clk_prepare_enable(res->core_clk);
-+	ret = reset_control_deassert(res->phy_reset);
- 	if (ret) {
--		dev_err(dev, "cannot prepare/enable core clock\n");
--		goto err_clk_core;
-+		dev_err(dev, "cannot deassert phy reset\n");
-+		goto err_deassert_phy;
- 	}
- 
--	ret = clk_prepare_enable(res->aux_clk);
-+	ret = reset_control_deassert(res->pci_reset);
- 	if (ret) {
--		dev_err(dev, "cannot prepare/enable aux clock\n");
--		goto err_clk_aux;
-+		dev_err(dev, "cannot deassert pci reset\n");
-+		goto err_deassert_pci;
- 	}
- 
--	ret = clk_prepare_enable(res->ref_clk);
-+	ret = reset_control_deassert(res->por_reset);
- 	if (ret) {
--		dev_err(dev, "cannot prepare/enable ref clock\n");
--		goto err_clk_ref;
-+		dev_err(dev, "cannot deassert por reset\n");
-+		goto err_deassert_por;
- 	}
- 
--	ret = reset_control_deassert(res->ahb_reset);
-+	ret = reset_control_deassert(res->axi_reset);
- 	if (ret) {
--		dev_err(dev, "cannot deassert ahb reset\n");
--		goto err_deassert_ahb;
-+		dev_err(dev, "cannot deassert axi reset\n");
-+		goto err_deassert_axi;
- 	}
- 
--	ret = reset_control_deassert(res->ext_reset);
--	if (ret) {
--		dev_err(dev, "cannot deassert ext reset\n");
--		goto err_deassert_ahb;
--	}
-+	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+	if (ret)
-+		goto err_clks;
- 
- 	/* enable PCIe clocks and resets */
- 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-@@ -408,36 +395,6 @@ static int qcom_pcie_init_2_1_0(struct q
- 	val |= PHY_REFCLK_SSP_EN;
- 	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
- 
--	ret = reset_control_deassert(res->phy_reset);
--	if (ret) {
--		dev_err(dev, "cannot deassert phy reset\n");
--		return ret;
--	}
--
--	ret = reset_control_deassert(res->pci_reset);
--	if (ret) {
--		dev_err(dev, "cannot deassert pci reset\n");
--		return ret;
--	}
--
--	ret = reset_control_deassert(res->por_reset);
--	if (ret) {
--		dev_err(dev, "cannot deassert por reset\n");
--		return ret;
--	}
--
--	ret = reset_control_deassert(res->axi_reset);
--	if (ret) {
--		dev_err(dev, "cannot deassert axi reset\n");
--		return ret;
--	}
--
--	ret = clk_prepare_enable(res->phy_clk);
--	if (ret) {
--		dev_err(dev, "cannot prepare/enable phy clock\n");
--		goto err_deassert_ahb;
--	}
--
- 	/* wait for clock acquisition */
- 	usleep_range(1000, 1500);
- 
-@@ -450,15 +407,19 @@ static int qcom_pcie_init_2_1_0(struct q
- 
- 	return 0;
- 
-+err_clks:
-+	reset_control_assert(res->axi_reset);
-+err_deassert_axi:
-+	reset_control_assert(res->por_reset);
-+err_deassert_por:
-+	reset_control_assert(res->pci_reset);
-+err_deassert_pci:
-+	reset_control_assert(res->phy_reset);
-+err_deassert_phy:
-+	reset_control_assert(res->ext_reset);
-+err_deassert_ext:
-+	reset_control_assert(res->ahb_reset);
- err_deassert_ahb:
--	clk_disable_unprepare(res->ref_clk);
--err_clk_ref:
--	clk_disable_unprepare(res->aux_clk);
--err_clk_aux:
--	clk_disable_unprepare(res->core_clk);
--err_clk_core:
--	clk_disable_unprepare(res->iface_clk);
--err_assert_ahb:
- 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
- 
- 	return ret;
diff --git a/target/linux/ipq806x/patches-5.4/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch b/target/linux/ipq806x/patches-5.4/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch
deleted file mode 100644
index 5530662a52359f..00000000000000
--- a/target/linux/ipq806x/patches-5.4/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 15 Jun 2020 23:06:05 +0200
-Subject: PCI: qcom: Add ipq8064 rev2 variant
-
-Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
-different offset based on the revision.
-
-Link: https://lore.kernel.org/r/20200615210608.21469-10-ansuelsmth@gmail.com
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q
- 	val &= ~BIT(0);
- 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
- 
--	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
-+	if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
-+	    of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
- 		writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
- 			       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
- 			       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
-@@ -1329,6 +1330,7 @@ err_pm_runtime_put:
- static const struct of_device_id qcom_pcie_match[] = {
- 	{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
- 	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
-+	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
- 	{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
- 	{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
- 	{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
diff --git a/target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch b/target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch
deleted file mode 100644
index 5440b2f7f82a11..00000000000000
--- a/target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001
-From: Sham Muthayyan <smuthayy@codeaurora.org>
-Date: Mon, 15 Jun 2020 23:06:07 +0200
-Subject: PCI: qcom: Support pci speed set for ipq806x
-
-Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to
-some hardware limitations. Add support for speed setting defined by the
-max-link-speed binding. If not defined the max speed is set to GEN2 by
-default.
-
-Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com
-Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
----
-
-Backported with light changes:
-* One include is missing in kernel 5.4
-
- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -27,6 +27,7 @@
- #include <linux/slab.h>
- #include <linux/types.h>
- 
-+#include "../../pci.h"
- #include "pcie-designware.h"
- 
- #define PCIE20_PARF_SYS_CTRL			0x00
-@@ -98,6 +99,8 @@
- #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
- #define SLV_ADDR_SPACE_SZ			0x10000000
- 
-+#define PCIE20_LNK_CONTROL2_LINK_STATUS2	0xa0
-+
- #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
- #define QCOM_PCIE_2_1_0_MAX_CLOCKS	5
- struct qcom_pcie_resources_2_1_0 {
-@@ -184,6 +187,7 @@ struct qcom_pcie {
- 	struct phy *phy;
- 	struct gpio_desc *reset;
- 	const struct qcom_pcie_ops *ops;
-+	int gen;
- };
- 
- #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
-@@ -399,6 +403,11 @@ static int qcom_pcie_init_2_1_0(struct q
- 	/* wait for clock acquisition */
- 	usleep_range(1000, 1500);
- 
-+	if (pcie->gen == 1) {
-+		val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
-+		val |= PCI_EXP_LNKSTA_CLS_2_5GB;
-+		writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
-+	}
- 
- 	/* Set the Max TLP size to 2K, instead of using default of 4K */
- 	writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
-@@ -1263,6 +1272,10 @@ static int qcom_pcie_probe(struct platfo
- 		goto err_pm_runtime_put;
- 	}
- 
-+	pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
-+	if (pcie->gen < 0)
-+		pcie->gen = 2;
-+
- 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
- 	pcie->parf = devm_ioremap_resource(dev, res);
- 	if (IS_ERR(pcie->parf)) {
diff --git a/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch b/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch
deleted file mode 100644
index cf86c43973814b..00000000000000
--- a/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Wed, 4 Mar 2020 22:38:32 +0100
-Subject: net: mdio: add ipq8064 mdio driver
-
-Currently ipq806x soc use generic bitbang driver to
-comunicate with the gmac ethernet interface.
-Add a dedicated driver created by chunkeey to fix this.
-
-Co-developed-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/Kconfig        |   8 ++
- drivers/net/phy/Makefile       |   1 +
- drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 175 insertions(+)
- create mode 100644 drivers/net/phy/mdio-ipq8064.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -156,6 +156,14 @@ config MDIO_I2C
- 
- 	  This is library mode.
- 
-+config MDIO_IPQ8064
-+	tristate "Qualcomm IPQ8064 MDIO interface support"
-+	depends on HAS_IOMEM && OF_MDIO
-+	depends on MFD_SYSCON
-+	help
-+	  This driver supports the MDIO interface found in the network
-+	  interface units of the IPQ8064 SoC
-+
- config MDIO_MOXART
- 	tristate "MOXA ART MDIO interface support"
- 	depends on ARCH_MOXART || COMPILE_TEST
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -52,6 +52,7 @@ obj-$(CONFIG_MDIO_CAVIUM)	+= mdio-cavium
- obj-$(CONFIG_MDIO_GPIO)		+= mdio-gpio.o
- obj-$(CONFIG_MDIO_HISI_FEMAC)	+= mdio-hisi-femac.o
- obj-$(CONFIG_MDIO_I2C)		+= mdio-i2c.o
-+obj-$(CONFIG_MDIO_IPQ8064)	+= mdio-ipq8064.o
- obj-$(CONFIG_MDIO_MOXART)	+= mdio-moxart.o
- obj-$(CONFIG_MDIO_MSCC_MIIM)	+= mdio-mscc-miim.o
- obj-$(CONFIG_MDIO_OCTEON)	+= mdio-octeon.o
---- /dev/null
-+++ b/drivers/net/phy/mdio-ipq8064.c
-@@ -0,0 +1,166 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/* Qualcomm IPQ8064 MDIO interface driver
-+ *
-+ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/regmap.h>
-+#include <linux/of_mdio.h>
-+#include <linux/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/mfd/syscon.h>
-+
-+/* MII address register definitions */
-+#define MII_ADDR_REG_ADDR                       0x10
-+#define MII_BUSY                                BIT(0)
-+#define MII_WRITE                               BIT(1)
-+#define MII_CLKRANGE_60_100M                    (0 << 2)
-+#define MII_CLKRANGE_100_150M                   (1 << 2)
-+#define MII_CLKRANGE_20_35M                     (2 << 2)
-+#define MII_CLKRANGE_35_60M                     (3 << 2)
-+#define MII_CLKRANGE_150_250M                   (4 << 2)
-+#define MII_CLKRANGE_250_300M                   (5 << 2)
-+#define MII_CLKRANGE_MASK			GENMASK(4, 2)
-+#define MII_REG_SHIFT				6
-+#define MII_REG_MASK				GENMASK(10, 6)
-+#define MII_ADDR_SHIFT				11
-+#define MII_ADDR_MASK				GENMASK(15, 11)
-+
-+#define MII_DATA_REG_ADDR                       0x14
-+
-+#define MII_MDIO_DELAY_USEC                     (1000)
-+#define MII_MDIO_RETRY_MSEC                     (10)
-+
-+struct ipq8064_mdio {
-+	struct regmap *base; /* NSS_GMAC0_BASE */
-+};
-+
-+static int
-+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
-+{
-+	u32 busy;
-+
-+	return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
-+					!(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
-+					MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
-+}
-+
-+static int
-+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
-+{
-+	u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
-+	struct ipq8064_mdio *priv = bus->priv;
-+	u32 ret_val;
-+	int err;
-+
-+	/* Reject clause 45 */
-+	if (reg_offset & MII_ADDR_C45)
-+		return -EOPNOTSUPP;
-+
-+	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
-+		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
-+
-+	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
-+	usleep_range(8, 10);
-+
-+	err = ipq8064_mdio_wait_busy(priv);
-+	if (err)
-+		return err;
-+
-+	regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
-+	return (int)ret_val;
-+}
-+
-+static int
-+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
-+{
-+	u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
-+	struct ipq8064_mdio *priv = bus->priv;
-+
-+	/* Reject clause 45 */
-+	if (reg_offset & MII_ADDR_C45)
-+		return -EOPNOTSUPP;
-+
-+	regmap_write(priv->base, MII_DATA_REG_ADDR, data);
-+
-+	miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
-+		   ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
-+
-+	regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
-+	usleep_range(8, 10);
-+
-+	return ipq8064_mdio_wait_busy(priv);
-+}
-+
-+static int
-+ipq8064_mdio_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct ipq8064_mdio *priv;
-+	struct mii_bus *bus;
-+	int ret;
-+
-+	bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
-+	if (!bus)
-+		return -ENOMEM;
-+
-+	bus->name = "ipq8064_mdio_bus";
-+	bus->read = ipq8064_mdio_read;
-+	bus->write = ipq8064_mdio_write;
-+	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
-+	bus->parent = &pdev->dev;
-+
-+	priv = bus->priv;
-+	priv->base = device_node_to_regmap(np);
-+	if (IS_ERR(priv->base)) {
-+		if (priv->base == ERR_PTR(-EPROBE_DEFER))
-+			return -EPROBE_DEFER;
-+
-+		dev_err(&pdev->dev, "error getting device regmap, error=%pe\n",
-+			priv->base);
-+		return PTR_ERR(priv->base);
-+	}
-+
-+	ret = of_mdiobus_register(bus, np);
-+	if (ret)
-+		return ret;
-+
-+	platform_set_drvdata(pdev, bus);
-+	return 0;
-+}
-+
-+static int
-+ipq8064_mdio_remove(struct platform_device *pdev)
-+{
-+	struct mii_bus *bus = platform_get_drvdata(pdev);
-+
-+	mdiobus_unregister(bus);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id ipq8064_mdio_dt_ids[] = {
-+	{ .compatible = "qcom,ipq8064-mdio" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
-+
-+static struct platform_driver ipq8064_mdio_driver = {
-+	.probe = ipq8064_mdio_probe,
-+	.remove = ipq8064_mdio_remove,
-+	.driver = {
-+		.name = "ipq8064-mdio",
-+		.of_match_table = ipq8064_mdio_dt_ids,
-+	},
-+};
-+
-+module_platform_driver(ipq8064_mdio_driver);
-+
-+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
-+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
-+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/ipq806x/patches-5.4/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch b/target/linux/ipq806x/patches-5.4/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch
deleted file mode 100644
index 47dc4557153782..00000000000000
--- a/target/linux/ipq806x/patches-5.4/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch
+++ /dev/null
@@ -1,621 +0,0 @@
-From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Fri, 17 Jul 2020 15:16:31 +0200
-Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver
-
-This has lost in the original push for the dwc3 qcom driver.
-This is needed for ipq806x SoC as without this the usb ports
-doesn't work at all.
-
-Signed-off-by: Andy Gross <agross@codeaurora.org>
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
-
-Light modification to Kconfig as some config are missing in kernel 5.4
-
- drivers/phy/qualcomm/Kconfig                |  10 +
- drivers/phy/qualcomm/Makefile               |   1 +
- drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++
- 3 files changed, 582 insertions(+)
- create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
-
---- a/drivers/phy/qualcomm/Kconfig
-+++ b/drivers/phy/qualcomm/Kconfig
-@@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC
- 	select GENERIC_PHY
- 	help
- 	  Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
-+
-+config PHY_QCOM_IPQ806X_USB
-+	tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
-+	depends on HAS_IOMEM
-+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
-+	select GENERIC_PHY
-+	help
-+	  This option enables support for the Synopsis PHYs present inside the
-+	  Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
-+	  both HS and SS PHY controllers.
---- a/drivers/phy/qualcomm/Makefile
-+++ b/drivers/phy/qualcomm/Makefile
-@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM)		+= phy-
- obj-$(CONFIG_PHY_QCOM_UFS_20NM)		+= phy-qcom-ufs-qmp-20nm.o
- obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
- obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
-+obj-$(CONFIG_PHY_QCOM_IPQ806X_USB)		+= phy-qcom-ipq806x-usb.o
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
-@@ -0,0 +1,571 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/delay.h>
-+#include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+
-+/* USB QSCRATCH Hardware registers */
-+#define QSCRATCH_GENERAL_CFG		(0x08)
-+#define HSUSB_PHY_CTRL_REG		(0x10)
-+
-+/* PHY_CTRL_REG */
-+#define HSUSB_CTRL_DMSEHV_CLAMP		BIT(24)
-+#define HSUSB_CTRL_USB2_SUSPEND		BIT(23)
-+#define HSUSB_CTRL_UTMI_CLK_EN		BIT(21)
-+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID	BIT(20)
-+#define HSUSB_CTRL_USE_CLKCORE		BIT(18)
-+#define HSUSB_CTRL_DPSEHV_CLAMP		BIT(17)
-+#define HSUSB_CTRL_COMMONONN		BIT(11)
-+#define HSUSB_CTRL_ID_HV_CLAMP		BIT(9)
-+#define HSUSB_CTRL_OTGSESSVLD_CLAMP	BIT(8)
-+#define HSUSB_CTRL_CLAMP_EN		BIT(7)
-+#define HSUSB_CTRL_RETENABLEN		BIT(1)
-+#define HSUSB_CTRL_POR			BIT(0)
-+
-+/* QSCRATCH_GENERAL_CFG */
-+#define HSUSB_GCFG_XHCI_REV		BIT(2)
-+
-+/* USB QSCRATCH Hardware registers */
-+#define SSUSB_PHY_CTRL_REG		(0x00)
-+#define SSUSB_PHY_PARAM_CTRL_1		(0x04)
-+#define SSUSB_PHY_PARAM_CTRL_2		(0x08)
-+#define CR_PROTOCOL_DATA_IN_REG		(0x0c)
-+#define CR_PROTOCOL_DATA_OUT_REG	(0x10)
-+#define CR_PROTOCOL_CAP_ADDR_REG	(0x14)
-+#define CR_PROTOCOL_CAP_DATA_REG	(0x18)
-+#define CR_PROTOCOL_READ_REG		(0x1c)
-+#define CR_PROTOCOL_WRITE_REG		(0x20)
-+
-+/* PHY_CTRL_REG */
-+#define SSUSB_CTRL_REF_USE_PAD		BIT(28)
-+#define SSUSB_CTRL_TEST_POWERDOWN	BIT(27)
-+#define SSUSB_CTRL_LANE0_PWR_PRESENT	BIT(24)
-+#define SSUSB_CTRL_SS_PHY_EN		BIT(8)
-+#define SSUSB_CTRL_SS_PHY_RESET		BIT(7)
-+
-+/* SSPHY control registers - Does this need 0x30? */
-+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane)	(0x1006 + 0x100 * (lane))
-+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)	(0x1002 + 0x100 * (lane))
-+
-+/* SSPHY SoC version specific values */
-+#define SSPHY_RX_EQ_VALUE		4 /* Override value for rx_eq */
-+/* Override value for transmit preemphasis */
-+#define SSPHY_TX_DEEMPH_3_5DB		23
-+/* Override value for mpll */
-+#define SSPHY_MPLL_VALUE		0
-+
-+/* QSCRATCH PHY_PARAM_CTRL1 fields */
-+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK	GENMASK(26, 19)
-+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK	GENMASK(19, 13)
-+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK	GENMASK(13, 7)
-+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK		GENMASK(7, 2)
-+
-+#define PHY_PARAM_CTRL1_MASK				\
-+		(PHY_PARAM_CTRL1_TX_FULL_SWING_MASK |	\
-+		 PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK |	\
-+		 PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK |	\
-+		 PHY_PARAM_CTRL1_LOS_BIAS_MASK)
-+
-+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x)	\
-+		(((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
-+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x)	\
-+		(((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
-+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x)	\
-+		(((x) <<  8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
-+#define PHY_PARAM_CTRL1_LOS_BIAS(x)	\
-+		(((x) <<  3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
-+
-+/* RX OVRD IN HI bits */
-+#define RX_OVRD_IN_HI_RX_RESET_OVRD		BIT(13)
-+#define RX_OVRD_IN_HI_RX_RX_RESET		BIT(12)
-+#define RX_OVRD_IN_HI_RX_EQ_OVRD		BIT(11)
-+#define RX_OVRD_IN_HI_RX_EQ_MASK		GENMASK(10, 7)
-+#define RX_OVRD_IN_HI_RX_EQ(x)			((x) << 8)
-+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD		BIT(7)
-+#define RX_OVRD_IN_HI_RX_EQ_EN			BIT(6)
-+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD	BIT(5)
-+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK	GENMASK(4, 2)
-+#define RX_OVRD_IN_HI_RX_RATE_OVRD		BIT(2)
-+#define RX_OVRD_IN_HI_RX_RATE_MASK		GENMASK(2, 0)
-+
-+/* TX OVRD DRV LO register bits */
-+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK		GENMASK(6, 0)
-+#define TX_OVRD_DRV_LO_PREEMPH_MASK		GENMASK(13, 6)
-+#define TX_OVRD_DRV_LO_PREEMPH(x)		((x) << 7)
-+#define TX_OVRD_DRV_LO_EN			BIT(14)
-+
-+/* MPLL bits */
-+#define SSPHY_MPLL_MASK				GENMASK(8, 5)
-+#define SSPHY_MPLL(x)				((x) << 5)
-+
-+/* SS CAP register bits */
-+#define SS_CR_CAP_ADDR_REG			BIT(0)
-+#define SS_CR_CAP_DATA_REG			BIT(0)
-+#define SS_CR_READ_REG				BIT(0)
-+#define SS_CR_WRITE_REG				BIT(0)
-+
-+struct usb_phy {
-+	void __iomem		*base;
-+	struct device		*dev;
-+	struct clk		*xo_clk;
-+	struct clk		*ref_clk;
-+	u32			rx_eq;
-+	u32			tx_deamp_3_5db;
-+	u32			mpll;
-+};
-+
-+struct phy_drvdata {
-+	struct phy_ops	ops;
-+	u32		clk_rate;
-+};
-+
-+/**
-+ * Write register and read back masked value to confirm it is written
-+ *
-+ * @base - QCOM DWC3 PHY base virtual address.
-+ * @offset - register offset.
-+ * @mask - register bitmask specifying what should be updated
-+ * @val - value to write.
-+ */
-+static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
-+					  u32 offset,
-+					  const u32 mask, u32 val)
-+{
-+	u32 write_val, tmp = readl(phy_dwc3->base + offset);
-+
-+	tmp &= ~mask;		/* retain other bits */
-+	write_val = tmp | val;
-+
-+	writel(write_val, phy_dwc3->base + offset);
-+
-+	/* Read back to see if val was written */
-+	tmp = readl(phy_dwc3->base + offset);
-+	tmp &= mask;		/* clear other bits */
-+
-+	if (tmp != val)
-+		dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
-+}
-+
-+static int wait_for_latch(void __iomem *addr)
-+{
-+	u32 retry = 10;
-+
-+	while (true) {
-+		if (!readl(addr))
-+			break;
-+
-+		if (--retry == 0)
-+			return -ETIMEDOUT;
-+
-+		usleep_range(10, 20);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Write SSPHY register
-+ *
-+ * @base - QCOM DWC3 PHY base virtual address.
-+ * @addr - SSPHY address to write.
-+ * @val - value to write.
-+ */
-+static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
-+				u32 addr, u32 val)
-+{
-+	int ret;
-+
-+	writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
-+	writel(SS_CR_CAP_ADDR_REG,
-+	       phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
-+
-+	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
-+	if (ret)
-+		goto err_wait;
-+
-+	writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
-+	writel(SS_CR_CAP_DATA_REG,
-+	       phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
-+
-+	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
-+	if (ret)
-+		goto err_wait;
-+
-+	writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
-+
-+	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
-+
-+err_wait:
-+	if (ret)
-+		dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
-+	return ret;
-+}
-+
-+/**
-+ * Read SSPHY register.
-+ *
-+ * @base - QCOM DWC3 PHY base virtual address.
-+ * @addr - SSPHY address to read.
-+ */
-+static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
-+			       u32 addr, u32 *val)
-+{
-+	int ret;
-+
-+	writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
-+	writel(SS_CR_CAP_ADDR_REG,
-+	       phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
-+
-+	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
-+	if (ret)
-+		goto err_wait;
-+
-+	/*
-+	 * Due to hardware bug, first read of SSPHY register might be
-+	 * incorrect. Hence as workaround, SW should perform SSPHY register
-+	 * read twice, but use only second read and ignore first read.
-+	 */
-+	writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
-+
-+	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
-+	if (ret)
-+		goto err_wait;
-+
-+	/* throwaway read */
-+	readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
-+
-+	writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
-+
-+	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
-+	if (ret)
-+		goto err_wait;
-+
-+	*val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
-+
-+err_wait:
-+	return ret;
-+}
-+
-+static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
-+{
-+	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
-+	int ret;
-+	u32 val;
-+
-+	ret = clk_prepare_enable(phy_dwc3->xo_clk);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(phy_dwc3->ref_clk);
-+	if (ret) {
-+		clk_disable_unprepare(phy_dwc3->xo_clk);
-+		return ret;
-+	}
-+
-+	/*
-+	 * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
-+	 * enable clamping, and disable RETENTION (power-on default is ENABLED)
-+	 */
-+	val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
-+		HSUSB_CTRL_RETENABLEN  | HSUSB_CTRL_COMMONONN |
-+		HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
-+		HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
-+		HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
-+
-+	/* use core clock if external reference is not present */
-+	if (!phy_dwc3->xo_clk)
-+		val |= HSUSB_CTRL_USE_CLKCORE;
-+
-+	writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
-+	usleep_range(2000, 2200);
-+
-+	/* Disable (bypass) VBUS and ID filters */
-+	writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
-+
-+	return 0;
-+}
-+
-+static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
-+{
-+	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
-+
-+	clk_disable_unprepare(phy_dwc3->ref_clk);
-+	clk_disable_unprepare(phy_dwc3->xo_clk);
-+
-+	return 0;
-+}
-+
-+static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
-+{
-+	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
-+	int ret;
-+	u32 data;
-+
-+	ret = clk_prepare_enable(phy_dwc3->xo_clk);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(phy_dwc3->ref_clk);
-+	if (ret) {
-+		clk_disable_unprepare(phy_dwc3->xo_clk);
-+		return ret;
-+	}
-+
-+	/* reset phy */
-+	data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
-+	writel(data | SSUSB_CTRL_SS_PHY_RESET,
-+	       phy_dwc3->base + SSUSB_PHY_CTRL_REG);
-+	usleep_range(2000, 2200);
-+	writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
-+
-+	/* clear REF_PAD if we don't have XO clk */
-+	if (!phy_dwc3->xo_clk)
-+		data &= ~SSUSB_CTRL_REF_USE_PAD;
-+	else
-+		data |= SSUSB_CTRL_REF_USE_PAD;
-+
-+	writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
-+
-+	/* wait for ref clk to become stable, this can take up to 30ms */
-+	msleep(30);
-+
-+	data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
-+	writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
-+
-+	/*
-+	 * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
-+	 * in HS mode instead of SS mode. Workaround it by asserting
-+	 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
-+	 */
-+	ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	data |= (1 << 7);
-+	ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	data &= ~0xff0;
-+	data |= 0x20;
-+	ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	/*
-+	 * Fix RX Equalization setting as follows
-+	 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
-+	 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
-+	 * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
-+	 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
-+	 */
-+	ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
-+	data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
-+	data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
-+	data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
-+	data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
-+	ret = usb_ss_write_phycreg(phy_dwc3,
-+				   SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	/*
-+	 * Set EQ and TX launch amplitudes as follows
-+	 * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
-+	 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
-+	 * LANE0.TX_OVRD_DRV_LO.EN set to 1.
-+	 */
-+	ret = usb_ss_read_phycreg(phy_dwc3,
-+				  SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
-+	data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
-+	data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
-+	data |= 0x6E;
-+	data |= TX_OVRD_DRV_LO_EN;
-+	ret = usb_ss_write_phycreg(phy_dwc3,
-+				   SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
-+	if (ret)
-+		goto err_phy_trans;
-+
-+	data = 0;
-+	data &= ~SSPHY_MPLL_MASK;
-+	data |= SSPHY_MPLL(phy_dwc3->mpll);
-+	usb_ss_write_phycreg(phy_dwc3, 0x30, data);
-+
-+	/*
-+	 * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
-+	 * TX_FULL_SWING [26:20] amplitude to 110
-+	 * TX_DEEMPH_6DB [19:14] to 32
-+	 * TX_DEEMPH_3_5DB [13:8] set based on SoC version
-+	 * LOS_BIAS [7:3] to 9
-+	 */
-+	data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
-+
-+	data &= ~PHY_PARAM_CTRL1_MASK;
-+
-+	data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
-+		PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
-+		PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
-+		PHY_PARAM_CTRL1_LOS_BIAS(0x9);
-+
-+	usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
-+			       PHY_PARAM_CTRL1_MASK, data);
-+
-+err_phy_trans:
-+	return ret;
-+}
-+
-+static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
-+{
-+	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
-+
-+	/* Sequence to put SSPHY in low power state:
-+	 * 1. Clear REF_PHY_EN in PHY_CTRL_REG
-+	 * 2. Clear REF_USE_PAD in PHY_CTRL_REG
-+	 * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
-+	 */
-+	usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
-+			       SSUSB_CTRL_SS_PHY_EN, 0x0);
-+	usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
-+			       SSUSB_CTRL_REF_USE_PAD, 0x0);
-+	usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
-+			       SSUSB_CTRL_TEST_POWERDOWN, 0x0);
-+
-+	clk_disable_unprepare(phy_dwc3->ref_clk);
-+	clk_disable_unprepare(phy_dwc3->xo_clk);
-+
-+	return 0;
-+}
-+
-+static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
-+	.ops = {
-+		.init		= qcom_ipq806x_usb_hs_phy_init,
-+		.exit		= qcom_ipq806x_usb_hs_phy_exit,
-+		.owner		= THIS_MODULE,
-+	},
-+	.clk_rate = 60000000,
-+};
-+
-+static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
-+	.ops = {
-+		.init		= qcom_ipq806x_usb_ss_phy_init,
-+		.exit		= qcom_ipq806x_usb_ss_phy_exit,
-+		.owner		= THIS_MODULE,
-+	},
-+	.clk_rate = 125000000,
-+};
-+
-+static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
-+	{ .compatible = "qcom,ipq806x-usb-phy-hs",
-+	  .data = &qcom_ipq806x_usb_hs_drvdata },
-+	{ .compatible = "qcom,ipq806x-usb-phy-ss",
-+	  .data = &qcom_ipq806x_usb_ss_drvdata },
-+	{ /* Sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
-+
-+static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	resource_size_t size;
-+	struct phy *generic_phy;
-+	struct usb_phy *phy_dwc3;
-+	const struct phy_drvdata *data;
-+	struct phy_provider *phy_provider;
-+
-+	phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
-+	if (!phy_dwc3)
-+		return -ENOMEM;
-+
-+	data = of_device_get_match_data(&pdev->dev);
-+
-+	phy_dwc3->dev = &pdev->dev;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res)
-+		return -EINVAL;
-+	size = resource_size(res);
-+	phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
-+
-+	if (IS_ERR(phy_dwc3->base)) {
-+		dev_err(phy_dwc3->dev, "failed to map reg\n");
-+		return PTR_ERR(phy_dwc3->base);
-+	}
-+
-+	phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
-+	if (IS_ERR(phy_dwc3->ref_clk)) {
-+		dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
-+		return PTR_ERR(phy_dwc3->ref_clk);
-+	}
-+
-+	clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
-+
-+	phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
-+	if (IS_ERR(phy_dwc3->xo_clk)) {
-+		dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
-+		phy_dwc3->xo_clk = NULL;
-+	}
-+
-+	/* Parse device node to probe HSIO settings */
-+	if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
-+				     &phy_dwc3->rx_eq))
-+		phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
-+
-+	if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
-+				     &phy_dwc3->tx_deamp_3_5db))
-+		phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
-+
-+	if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
-+		phy_dwc3->mpll = SSPHY_MPLL_VALUE;
-+
-+	generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
-+
-+	if (IS_ERR(generic_phy))
-+		return PTR_ERR(generic_phy);
-+
-+	phy_set_drvdata(generic_phy, phy_dwc3);
-+	platform_set_drvdata(pdev, phy_dwc3);
-+
-+	phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
-+						     of_phy_simple_xlate);
-+
-+	if (IS_ERR(phy_provider))
-+		return PTR_ERR(phy_provider);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver qcom_ipq806x_usb_phy_driver = {
-+	.probe		= qcom_ipq806x_usb_phy_probe,
-+	.driver		= {
-+		.name	= "qcom-ipq806x-usb-phy",
-+		.owner	= THIS_MODULE,
-+		.of_match_table = qcom_ipq806x_usb_phy_table,
-+	},
-+};
-+
-+module_platform_driver(qcom_ipq806x_usb_phy_driver);
-+
-+MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
-+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
diff --git a/target/linux/ipq806x/patches-5.4/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch b/target/linux/ipq806x/patches-5.4/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch
deleted file mode 100644
index dedbb510498a10..00000000000000
--- a/target/linux/ipq806x/patches-5.4/095-2-v5.9-phy-qualcomm-fix-setting-of-tx_deamp_3_5db-when-device-property-read-fails.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 3d7b0ca5300bd01b176f2b4c10e173db802560d8 Mon Sep 17 00:00:00 2001
-From: Colin Ian King <colin.king@canonical.com>
-Date: Tue, 21 Jul 2020 16:06:13 +0100
-Subject: phy: qualcomm: fix setting of tx_deamp_3_5db when device property
- read fails
-
-Currently when reading of the device property for "qcom,tx-deamp_3_5db"
-fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This
-looks like a copy-n-paste error and in fact should be assigning the
-default instead to phy_dwc3->tx_deamp_3_5db
-
-Addresses-Coverity: ("Copy-paste error")
-Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver")
-Signed-off-by: Colin Ian King <colin.king@canonical.com>
-Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
-@@ -531,7 +531,7 @@ static int qcom_ipq806x_usb_phy_probe(st
- 
- 	if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
- 				     &phy_dwc3->tx_deamp_3_5db))
--		phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
-+		phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
- 
- 	if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
- 		phy_dwc3->mpll = SSPHY_MPLL_VALUE;
diff --git a/target/linux/ipq806x/patches-5.4/851-add-gsbi1-dts.patch b/target/linux/ipq806x/patches-5.4/851-add-gsbi1-dts.patch
deleted file mode 100644
index a1231898044861..00000000000000
--- a/target/linux/ipq806x/patches-5.4/851-add-gsbi1-dts.patch
+++ /dev/null
@@ -1,44 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -894,6 +894,41 @@
- 			reg = <0x12100000 0x10000>;
- 		};
- 
-+		gsbi1: gsbi@12440000 {
-+			compatible = "qcom,gsbi-v1.0.0";
-+			cell-index = <1>;
-+			reg = <0x12440000 0x100>;
-+			clocks = <&gcc GSBI1_H_CLK>;
-+			clock-names = "iface";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			ranges;
-+			status = "disabled";
-+
-+			syscon-tcsr = <&tcsr>;
-+
-+			gsbi1_serial: serial@12450000 {
-+				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-+				reg = <0x12450000 0x100>,
-+				      <0x12400000 0x03>;
-+				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-+				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
-+				clock-names = "core", "iface";
-+				status = "disabled";
-+			};
-+
-+			gsbi1_i2c: i2c@12460000 {
-+				compatible = "qcom,i2c-qup-v1.1.1";
-+				reg = <0x12460000 0x1000>;
-+				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-+				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
-+				clock-names = "core", "iface";
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				status = "disabled";
-+			};
-+		};
-+
- 		gsbi2: gsbi@12480000 {
- 			compatible = "qcom,gsbi-v1.0.0";
- 			cell-index = <2>;
diff --git a/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch b/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch
deleted file mode 100644
index 9ff4d9ec36a088..00000000000000
--- a/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch
+++ /dev/null
@@ -1,170 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -1456,6 +1456,12 @@
- 			status = "disabled";
- 		};
- 
-+		nss-gmac-common {
-+			compatible = "qcom,nss-gmac-common";
-+			reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>;
-+			reg-names = "nss_reg_base", "qsgmii_reg_base", "clk_ctl_base";
-+		};
-+
- 		gmac0: ethernet@37000000 {
- 			device_type = "network";
- 			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
-@@ -1556,7 +1562,132 @@
- 			regulator-always-on;
- 		};
- 
--		sdcc1bam:dma@12402000 {
-+		nss0: nss@40000000 {
-+			compatible = "qcom,nss";
-+			qcom,low-frequency = <733000000>; /* orig value 110000000 */
-+			qcom,mid-frequency = <733000000>; /* orig value 550000000 */
-+			qcom,max-frequency = <733000000>;
-+
-+			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
-+			reg = <0x36000000 0x1000 0x39000000 0x10000>;
-+			reg-names = "nphys", "vphys";
-+			clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK_SRC>,
-+				 <&gcc NSSTCM_CLK>, <&rpmcc RPM_NSS_FABRIC_0_CLK>,
-+				 <&rpmcc RPM_NSS_FABRIC_1_CLK>;
-+			clock-names = "nss-core-clk", "nss-tcm-src",
-+				      "nss-tcm-clk", "nss-fab0-clk",
-+				      "nss-fab1-clk";
-+			resets = <&gcc UBI32_CORE1_CLKRST_CLAMP_RESET>,
-+				 <&gcc UBI32_CORE1_CLAMP_RESET>,
-+				 <&gcc UBI32_CORE1_AHB_RESET>,
-+				 <&gcc UBI32_CORE1_AXI_RESET>;
-+			reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
-+
-+			qcom,id = <0>;
-+			qcom,num-irq = <2>;
-+			qcom,num-queue = <2>;
-+			qcom,load-addr = <0x40000000>;
-+			qcom,turbo-frequency;
-+
-+			qcom,bridge-enabled;
-+			qcom,gre-enabled;
-+			qcom,gre-redir-enabled;
-+			qcom,gre_tunnel_enabled;
-+			qcom,ipv4-enabled;
-+			qcom,ipv4-reasm-enabled;
-+			qcom,ipv6-enabled;
-+			qcom,ipv6-reasm-enabled;
-+			qcom,l2tpv2-enabled;
-+			qcom,map-t-enabled;
-+			qcom,pppoe-enabled;
-+			qcom,pptp-enabled;
-+			qcom,portid-enabled;
-+			qcom,shaping-enabled;
-+			qcom,tun6rd-enabled;
-+			qcom,tunipip6-enabled;
-+			qcom,vlan-enabled;
-+			qcom,wlan-dataplane-offload-enabled;
-+			qcom,wlanredirect-enabled;
-+			qcom,pxvlan-enabled;
-+			qcom,vxlan-enabled;
-+			qcom,match-enabled;
-+			qcom,mirror-enabled;
-+			qcom,rmnet-enabled;
-+			qcom,clmap-enabled;
-+		};
-+
-+		nss1: nss@40800000 {
-+			compatible = "qcom,nss";
-+			qcom,low-frequency = <733000000>; /* orig value 110000000 */
-+			qcom,mid-frequency = <733000000>; /* orig value 550000000 */
-+			qcom,max-frequency = <733000000>;
-+
-+			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
-+			reg = <0x36400000 0x1000 0x39010000 0x10000>;
-+			reg-names = "nphys", "vphys";
-+			resets = <&gcc UBI32_CORE2_CLKRST_CLAMP_RESET>,
-+				 <&gcc UBI32_CORE2_CLAMP_RESET>,
-+				 <&gcc UBI32_CORE2_AHB_RESET>,
-+				 <&gcc UBI32_CORE2_AXI_RESET>;
-+			reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
-+
-+			qcom,id = <1>;
-+			qcom,num-irq = <2>;
-+			qcom,load-addr = <0x40800000>;
-+			qcom,num-queue = <2>;
-+			qcom,turbo-frequency;
-+
-+			qcom,capwap-enabled;
-+			qcom,crypto-enabled;
-+			qcom,dtls-enabled;
-+			qcom,ipsec-enabled;
-+		};
-+
-+		crypto1: crypto@38000000 {
-+			compatible = "qcom,nss-crypto";
-+			reg = <0x38000000 0x20000>, <0x38004000 0x22000>;
-+			reg-names = "crypto_pbase", "bam_base";
-+			clocks = <&gcc CE5_CORE_CLK>, <&gcc CE5_A_CLK>, <&gcc CE5_H_CLK>;
-+			clock-names = "ce5_core", "ce5_aclk", "ce5_hclk";
-+			resets = <&gcc CRYPTO_ENG1_RESET>, <&gcc CRYPTO_AHB_RESET>;
-+			reset-names = "rst_eng", "rst_ahb";
-+			qcom,id = <0>;
-+			qcom,ee = <0>;
-+		};
-+
-+		crypto2: crypto@38400000 {
-+			compatible = "qcom,nss-crypto";
-+			reg = <0x38400000 0x20000>, <0x38404000 0x22000>;
-+			reg-names = "crypto_pbase", "bam_base";
-+			resets = <&gcc CRYPTO_ENG2_RESET>;
-+			reset-names = "rst_eng";
-+			qcom,id = <1>;
-+			qcom,ee = <0>;
-+		};
-+
-+		crypto3: crypto@38800000 {
-+			compatible = "qcom,nss-crypto";
-+			reg = <0x38800000 0x20000>, <0x38804000 0x22000>;
-+			reg-names = "crypto_pbase", "bam_base";
-+			resets = <&gcc CRYPTO_ENG3_RESET>;
-+			reset-names = "rst_eng";
-+			qcom,id = <2>;
-+			qcom,ee = <0>;
-+		};
-+
-+		crypto4: crypto@38c00000 {
-+			compatible = "qcom,nss-crypto";
-+			reg = <0x38c00000 0x20000>, <0x38c04000 0x22000>;
-+			reg-names = "crypto_pbase", "bam_base";
-+			resets = <&gcc CRYPTO_ENG4_RESET>;
-+			reset-names = "rst_eng";
-+			qcom,id = <3>;
-+			qcom,ee = <0>;
-+		};
-+
-+		sdcc1bam: dma@12402000 {
- 			compatible = "qcom,bam-v1.3.0";
- 			reg = <0x12402000 0x8000>;
- 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-@@ -1622,6 +1753,20 @@
- 				dma-names = "tx", "rx";
- 			};
- 		};
-+
-+		nss-common {
-+			compatible = "qcom,nss-common";
-+			reg = <0x03000000 0x00001000>;
-+			reg-names = "nss_fpb_base";
-+			clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK>,
-+				<&rpmcc RPM_NSS_FABRIC_0_CLK>, <&rpmcc RPM_NSS_FABRIC_1_CLK>;
-+			clock-names = "nss_core_clk", "nss_tcm_clk",
-+				"nss-fab0-clk", "nss-fab1-clk";
-+			nss_core-supply = <&smb208_s1b>;
-+			nss_core_vdd_nominal = <1100000>;
-+			nss_core_vdd_high = <1150000>;
-+			nss_core_threshold_freq = <733000000>;
-+		};
- 	};
- 
- 	sfpb_mutex: sfpb-mutex {
diff --git a/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch b/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch
deleted file mode 100644
index 047a098949a88f..00000000000000
--- a/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1058,6 +1058,9 @@ int __init early_init_dt_scan_chosen(uns
- 	p = of_get_flat_dt_prop(node, "bootargs", &l);
- 	if (p != NULL && l > 0)
- 		strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
-+	p = of_get_flat_dt_prop(node, "bootargs-append", &l);
-+	if (p != NULL && l > 0)
-+		strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
- 
-     /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-      * device tree option of chosen/bootargs-override. This is
diff --git a/target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch b/target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch
deleted file mode 100644
index c4456f3d70a2bf..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch
+++ /dev/null
@@ -1,215 +0,0 @@
-From c70758d96b22e4421a6afd824cb59e350c6a8040 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Tue, 2 Jun 2020 22:09:15 +0200
-Subject: [PATCH] Regulator: Add NSS VOLT
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/regulator/Kconfig  | 7 +++++++
- drivers/regulator/Makefile | 1 +
- 2 files changed, 8 insertions(+)
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1105,5 +1105,12 @@ config REGULATOR_WM8994
- 	  This driver provides support for the voltage regulators on the
- 	  WM8994 CODEC.
- 
-+config REGULATOR_NSS_VOLT
-+	bool "Qualcomm IPQ806X NSS Voltage regulator"
-+	depends on ARCH_QCOM || COMPILE_TEST
-+	help
-+	  This driver provides support for the Qualcomm IPQ806X NSS Voltage
-+	  regulator.
-+
- endif
- 
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -138,5 +138,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x
- obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
- obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
- obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
-+obj-$(CONFIG_REGULATOR_NSS_VOLT) += nss-volt-ipq806x.o
- 
- ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
---- /dev/null
-+++ b/drivers/regulator/nss-volt-ipq806x.c
-@@ -0,0 +1,146 @@
-+/*
-+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/regulator/nss-volt-ipq806x.h>
-+
-+struct nss_data {
-+	struct regulator *nss_reg;
-+	u32 nss_core_vdd_nominal;
-+	u32 nss_core_vdd_high;
-+	u32 nss_core_threshold_freq;
-+};
-+
-+static struct nss_data *data;
-+
-+int nss_ramp_voltage(unsigned long rate, bool ramp_up)
-+{
-+	int ret;
-+	int curr_uV, uV;
-+	struct regulator *reg;
-+
-+	if (!data) {
-+		pr_err("NSS core regulator not init.\n");
-+		return -ENODEV;
-+	}
-+
-+	reg = data->nss_reg;
-+
-+	if (!reg) {
-+		pr_err("NSS core regulator not found.\n");
-+		return -EINVAL;
-+	}
-+
-+	uV = data->nss_core_vdd_nominal;
-+	if (rate >= data->nss_core_threshold_freq)
-+		return data->nss_core_vdd_high;
-+
-+	curr_uV = regulator_get_voltage(reg);
-+
-+	if (ramp_up) {
-+		if (uV <= curr_uV)
-+			return 0;
-+	} else {
-+		if (uV >= curr_uV)
-+			return 0;
-+	}
-+
-+	ret = regulator_set_voltage(reg, uV, data->nss_core_vdd_high);
-+	if (ret)
-+		pr_err("NSS volt scaling failed (%d)\n", uV);
-+
-+	return ret;
-+}
-+
-+static const struct of_device_id nss_ipq806x_match_table[] = {
-+	{ .compatible = "qcom,nss-common" },
-+	{}
-+};
-+
-+static int nss_volt_ipq806x_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	int ret;
-+
-+	if (!np)
-+		return -ENODEV;
-+
-+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
-+	if (!data)
-+		return -ENOMEM;
-+
-+	data->nss_reg = devm_regulator_get(&pdev->dev, "nss_core");
-+	ret = PTR_ERR_OR_ZERO(data->nss_reg);
-+	if (ret) {
-+		if (ret == -EPROBE_DEFER)
-+			dev_dbg(&pdev->dev,
-+				"nss_core regulator not ready, retry\n");
-+		else
-+			dev_err(&pdev->dev, "no regulator for nss_core: %d\n",
-+				ret);
-+
-+		return ret;
-+	}
-+
-+	if (of_property_read_u32(np, "nss_core_vdd_nominal",
-+				 &data->nss_core_vdd_nominal)) {
-+		pr_warn("NSS core vdd nominal not found. Using defaults...\n");
-+		data->nss_core_vdd_nominal = 1100000;
-+	}
-+
-+	if (of_property_read_u32(np, "nss_core_vdd_high",
-+				 &data->nss_core_vdd_high)) {
-+		pr_warn("NSS core vdd high not found. Using defaults...\n");
-+		data->nss_core_vdd_high = 1150000;
-+	}
-+
-+	if (of_property_read_u32(np, "nss_core_threshold_freq",
-+				 &data->nss_core_threshold_freq)) {
-+		pr_warn("NSS core thres freq not found. Using defaults...\n");
-+		data->nss_core_threshold_freq = 733000000;
-+	}
-+
-+	platform_set_drvdata(pdev, data);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver nss_ipq806x_driver = {
-+	.probe          = nss_volt_ipq806x_probe,
-+	.driver         = {
-+		.name   = "nss-volt-ipq806x",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = nss_ipq806x_match_table,
-+	},
-+};
-+
-+static int __init nss_ipq806x_init(void)
-+{
-+	return platform_driver_register(&nss_ipq806x_driver);
-+}
-+late_initcall(nss_ipq806x_init);
-+
-+static void __exit nss_ipq806x_exit(void)
-+{
-+	platform_driver_unregister(&nss_ipq806x_driver);
-+}
-+module_exit(nss_ipq806x_exit);
-+
---- a/include/linux/regulator/nss-volt-ipq806x.h
-+++ b/include/linux/regulator/nss-volt-ipq806x.h
-@@ -22,3 +22,28 @@
- int nss_ramp_voltage(unsigned long rate, bool ramp_up);
- 
- #endif
-+
-+/*
-+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#ifndef __QCOM_NSS_VOL_SCALING_H
-+#define __QCOM_NSS_VOL_SCALING_H
-+
-+#include <linux/regulator/consumer.h>
-+
-+int nss_ramp_voltage(unsigned long rate, bool ramp_up);
-+
-+#endif
diff --git a/target/linux/ipq806x/patches-5.4/999-01-Revert-ARM-dma-mapping-remove-dmac_clean_range-and-d.patch b/target/linux/ipq806x/patches-5.4/999-01-Revert-ARM-dma-mapping-remove-dmac_clean_range-and-d.patch
deleted file mode 100644
index 03d97fadf90353..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-01-Revert-ARM-dma-mapping-remove-dmac_clean_range-and-d.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From 733a75729c1fbb478caaed875dd9c09a878a553d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 5 Jun 2020 11:44:27 +0200
-Subject: [PATCH] Revert "ARM: dma-mapping: remove dmac_clean_range and
- dmac_inv_range"
-
-This partially reverts 'commit 702b94bff3c505 ("ARM: dma-mapping:
-remove dmac_clean_range and dmac_inv_range")'
-
-Some MSM drivers still use the dmac_clean and dmac_inv_range APIs.
-Bring back the defines and exports for v7 CPUs.
-
-Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
-Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
-[sramana: resolved minor merge conflicts]
-Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
-(cherry picked from commit d6118c0a9f7ab2b131ca36dd3dbd5634603d14fe)
-
-Change-Id: Ib2ddb4452711c5c2013bf29f0b5d8a3572b10357
-Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/include/asm/cacheflush.h | 21 +++++++++++++++++++++
- arch/arm/include/asm/glue-cache.h |  2 ++
- arch/arm/mm/cache-v7.S            |  6 ++++--
- arch/arm/mm/proc-macros.S         |  2 ++
- arch/arm/mm/proc-syms.c           |  3 +++
- 5 files changed, 32 insertions(+), 2 deletions(-)
-
---- a/arch/arm/include/asm/cacheflush.h
-+++ b/arch/arm/include/asm/cacheflush.h
-@@ -91,6 +91,21 @@
-  *	DMA Cache Coherency
-  *	===================
-  *
-+ *	dma_inv_range(start, end)
-+ *
-+ *		Invalidate (discard) the specified virtual address range.
-+ *		May not write back any entries.  If 'start' or 'end'
-+ *		are not cache line aligned, those lines must be written
-+ *		back.
-+ *		- start  - virtual start address
-+ *		- end    - virtual end address
-+ *
-+ *	dma_clean_range(start, end)
-+ *
-+ *		Clean (write back) the specified virtual address range.
-+ *		- start  - virtual start address
-+ *		- end    - virtual end address
-+ *
-  *	dma_flush_range(start, end)
-  *
-  *		Clean and invalidate the specified virtual address range.
-@@ -112,6 +127,8 @@ struct cpu_cache_fns {
- 	void (*dma_map_area)(const void *, size_t, int);
- 	void (*dma_unmap_area)(const void *, size_t, int);
- 
-+	void (*dma_inv_range)(const void *, const void *);
-+	void (*dma_clean_range)(const void *, const void *);
- 	void (*dma_flush_range)(const void *, const void *);
- } __no_randomize_layout;
- 
-@@ -137,6 +154,8 @@ extern struct cpu_cache_fns cpu_cache;
-  * is visible to DMA, or data written by DMA to system memory is
-  * visible to the CPU.
-  */
-+#define dmac_inv_range			cpu_cache.dma_inv_range
-+#define dmac_clean_range		cpu_cache.dma_clean_range
- #define dmac_flush_range		cpu_cache.dma_flush_range
- 
- #else
-@@ -156,6 +175,8 @@ extern void __cpuc_flush_dcache_area(voi
-  * is visible to DMA, or data written by DMA to system memory is
-  * visible to the CPU.
-  */
-+extern void dmac_inv_range(const void *, const void *);
-+extern void dmac_clean_range(const void *, const void *);
- extern void dmac_flush_range(const void *, const void *);
- 
- #endif
---- a/arch/arm/include/asm/glue-cache.h
-+++ b/arch/arm/include/asm/glue-cache.h
-@@ -156,6 +156,8 @@ static inline void nop_dma_unmap_area(co
- #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
- 
- #define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
-+#define dmac_inv_range			__glue(_CACHE, _dma_inv_range)
-+#define dmac_clean_range		__glue(_CACHE, _dma_clean_range)
- #endif
- 
- #endif
---- a/arch/arm/mm/cache-v7.S
-+++ b/arch/arm/mm/cache-v7.S
-@@ -363,7 +363,7 @@ ENDPROC(v7_flush_kern_dcache_area)
-  *	- start   - virtual start address of region
-  *	- end     - virtual end address of region
-  */
--v7_dma_inv_range:
-+ENTRY(v7_dma_inv_range)
- 	dcache_line_size r2, r3
- 	sub	r3, r2, #1
- 	tst	r0, r3
-@@ -393,7 +393,7 @@ ENDPROC(v7_dma_inv_range)
-  *	- start   - virtual start address of region
-  *	- end     - virtual end address of region
-  */
--v7_dma_clean_range:
-+ENTRY(v7_dma_clean_range)
- 	dcache_line_size r2, r3
- 	sub	r3, r2, #1
- 	bic	r0, r0, r3
-@@ -479,6 +479,8 @@ ENDPROC(v7_dma_unmap_area)
- 
- 	globl_equ	b15_dma_map_area,		v7_dma_map_area
- 	globl_equ	b15_dma_unmap_area,		v7_dma_unmap_area
-+	globl_equ	b15_dma_inv_range,		v7_dma_inv_range
-+	globl_equ	b15_dma_clean_range,		v7_dma_clean_range
- 	globl_equ	b15_dma_flush_range,		v7_dma_flush_range
- 
- 	define_cache_functions b15
---- a/arch/arm/mm/proc-macros.S
-+++ b/arch/arm/mm/proc-macros.S
-@@ -336,6 +336,8 @@ ENTRY(\name\()_cache_fns)
- 	.long	\name\()_flush_kern_dcache_area
- 	.long	\name\()_dma_map_area
- 	.long	\name\()_dma_unmap_area
-+	.long   \name\()_dma_inv_range
-+	.long   \name\()_dma_clean_range
- 	.long	\name\()_dma_flush_range
- 	.size	\name\()_cache_fns, . - \name\()_cache_fns
- .endm
---- a/arch/arm/mm/proc-syms.c
-+++ b/arch/arm/mm/proc-syms.c
-@@ -27,6 +27,9 @@ EXPORT_SYMBOL(__cpuc_flush_user_all);
- EXPORT_SYMBOL(__cpuc_flush_user_range);
- EXPORT_SYMBOL(__cpuc_coherent_kern_range);
- EXPORT_SYMBOL(__cpuc_flush_dcache_area);
-+EXPORT_SYMBOL(dmac_inv_range);
-+EXPORT_SYMBOL(dmac_clean_range);
-+EXPORT_SYMBOL(dmac_flush_range);
- #else
- EXPORT_SYMBOL(cpu_cache);
- #endif
diff --git a/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch b/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch
deleted file mode 100644
index 63a578c0d01708..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch
+++ /dev/null
@@ -1,1584 +0,0 @@
---- a/include/linux/if_bridge.h
-+++ b/include/linux/if_bridge.h
-@@ -149,4 +149,39 @@ br_port_flag_is_set(const struct net_dev
- }
- #endif
- 
-+/* QCA NSS ECM support - Start */
-+extern struct net_device *br_port_dev_get(struct net_device *dev,
-+					  unsigned char *addr,
-+					  struct sk_buff *skb,
-+					  unsigned int cookie);
-+extern void br_refresh_fdb_entry(struct net_device *dev, const char *addr);
-+extern struct net_bridge_fdb_entry *br_fdb_has_entry(struct net_device *dev,
-+						     const char *addr,
-+						     __u16 vid);
-+extern void br_fdb_update_register_notify(struct notifier_block *nb);
-+extern void br_fdb_update_unregister_notify(struct notifier_block *nb);
-+
-+typedef struct net_bridge_port *br_port_dev_get_hook_t(struct net_device *dev,
-+						       struct sk_buff *skb,
-+						       unsigned char *addr,
-+						       unsigned int cookie);
-+extern br_port_dev_get_hook_t __rcu *br_port_dev_get_hook;
-+
-+#define BR_FDB_EVENT_ADD     0x01
-+#define BR_FDB_EVENT_DEL     0x02
-+
-+struct br_fdb_event {
-+	struct net_device *dev;
-+	unsigned char      addr[6];
-+	unsigned char      is_local;
-+};
-+extern void br_fdb_register_notify(struct notifier_block *nb);
-+extern void br_fdb_unregister_notify(struct notifier_block *nb);
-+
-+typedef struct net_bridge_port *br_get_dst_hook_t(
-+		const struct net_bridge_port *src,
-+		struct sk_buff **skb);
-+extern br_get_dst_hook_t __rcu *br_get_dst_hook;
-+/* QCA NSS ECM support - End */
-+
- #endif
---- a/include/linux/if_pppol2tp.h
-+++ b/include/linux/if_pppol2tp.h
-@@ -14,4 +14,30 @@
- #include <linux/in6.h>
- #include <uapi/linux/if_pppol2tp.h>
- 
-+/* QCA NSS ECM support - Start */
-+/*
-+ * Holds L2TP channel info
-+ */
-+struct  pppol2tp_common_addr {
-+	int tunnel_version;				/* v2 or v3 */
-+	__u32 local_tunnel_id, remote_tunnel_id;	/* tunnel id */
-+	__u32 local_session_id, remote_session_id;	/* session id */
-+	struct sockaddr_in local_addr, remote_addr; /* ip address and port */
-+};
-+
-+/*
-+ * L2TP channel operations
-+ */
-+struct pppol2tp_channel_ops {
-+	struct ppp_channel_ops ops; /* ppp channel ops */
-+};
-+
-+/*
-+ * exported function which calls pppol2tp channel's get addressing
-+ * function
-+ */
-+extern int pppol2tp_channel_addressing_get(struct ppp_channel *,
-+					   struct pppol2tp_common_addr *);
-+/* QCA NSS ECM support - End */
-+
- #endif
---- a/include/linux/if_vlan.h
-+++ b/include/linux/if_vlan.h
-@@ -222,7 +222,28 @@ extern void vlan_vids_del_by_dev(struct
- 
- extern bool vlan_uses_dev(const struct net_device *dev);
- 
-+/* QCA NSS ECM support - Start */
-+extern void __vlan_dev_update_accel_stats(struct net_device *dev,
-+                                    struct rtnl_link_stats64 *stats);
-+extern u16 vlan_dev_get_egress_prio(struct net_device *dev, u32 skb_prio);
-+extern struct net_device *vlan_dev_next_dev(const struct net_device *dev);
-+/* QCA NSS ECM support - End */
-+
- #else
-+/* QCA NSS ECM support - Start */
-+static inline void __vlan_dev_update_accel_stats(struct net_device *dev,
-+					   struct rtnl_link_stats64 *stats)
-+{
-+
-+}
-+
-+static inline u16 vlan_dev_get_egress_prio(struct net_device *dev,
-+						u32 skb_prio)
-+{
-+	return 0;
-+}
-+/* QCA NSS ECM support - End */
-+
- static inline struct net_device *
- __vlan_find_dev_deep_rcu(struct net_device *real_dev,
- 		     __be16 vlan_proto, u16 vlan_id)
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -1659,6 +1659,20 @@ enum netdev_ml_priv_type {
- 	ML_PRIV_CAN,
- };
- 
-+/* QCA NSS ECM support - Start */
-+enum netdev_priv_qca_ecm_flags {
-+	IFF_QCA_ECM_TUN_TAP		= 1<<0,
-+	IFF_QCA_ECM_PPP_L2TPV2		= 1<<1,
-+	IFF_QCA_ECM_PPP_L2TPV3		= 1<<2,
-+	IFF_QCA_ECM_PPP_PPTP		= 1<<3,
-+};
-+
-+#define IFF_QCA_ECM_TUN_TAP		IFF_QCA_ECM_TUN_TAP
-+#define IFF_QCA_ECM_PPP_L2TPV2		IFF_QCA_ECM_PPP_L2TPV2
-+#define IFF_QCA_ECM_PPP_L2TPV3		IFF_QCA_ECM_PPP_L2TPV3
-+#define IFF_QCA_ECM_PPP_PPTP		IFF_QCA_ECM_PPP_PPTP
-+/* QCA NSS ECM support - End */
-+
- /**
-  *	struct net_device - The DEVICE structure.
-  *
-@@ -1968,6 +1982,7 @@ struct net_device {
- 
- 	unsigned int		flags;
- 	unsigned int		priv_flags;
-+	unsigned int		priv_flags_qca_ecm;	/* QCA NSS ECM support */
- 
- 	unsigned short		gflags;
- 	unsigned short		padded;
-@@ -2648,6 +2663,10 @@ enum netdev_cmd {
- 	NETDEV_CVLAN_FILTER_DROP_INFO,
- 	NETDEV_SVLAN_FILTER_PUSH_INFO,
- 	NETDEV_SVLAN_FILTER_DROP_INFO,
-+	/* QCA NSS ECM Support - Start */
-+	NETDEV_BR_JOIN,
-+	NETDEV_BR_LEAVE,
-+	/* QCA NSS ECM Support - End */
- };
- const char *netdev_cmd_to_name(enum netdev_cmd cmd);
- 
---- a/include/net/bond_3ad.h
-+++ b/include/net/bond_3ad.h
-@@ -307,5 +307,13 @@ void bond_3ad_update_lacp_rate(struct bo
- void bond_3ad_update_ad_actor_settings(struct bonding *bond);
- int bond_3ad_stats_fill(struct sk_buff *skb, struct bond_3ad_stats *stats);
- size_t bond_3ad_stats_size(void);
-+
-+/* QCA NSS ECM support - Start */
-+struct net_device *bond_3ad_get_tx_dev(struct sk_buff *skb, uint8_t *src_mac,
-+				       uint8_t *dst_mac, void *src,
-+				       void *dst, uint16_t protocol,
-+				       struct net_device *bond_dev,
-+				       __be16 *layer4hdr);
-+/* QCA NSS ECM support - End */
- #endif /* _NET_BOND_3AD_H */
- 
---- a/include/net/bonding.h
-+++ b/include/net/bonding.h
-@@ -244,6 +244,7 @@ struct bonding {
- #endif /* CONFIG_DEBUG_FS */
- 	struct rtnl_link_stats64 bond_stats;
- 	struct lock_class_key stats_lock_key;
-+	u32      id; /* QCA NSS ECM support */
- };
- 
- #define bond_slave_get_rcu(dev) \
-@@ -735,4 +736,12 @@ static inline void bond_tx_drop(struct n
- 	dev_kfree_skb_any(skb);
- }
- 
-+/* QCA NSS ECM support - Start */
-+extern struct bond_cb __rcu *bond_cb;
-+
-+uint32_t bond_xmit_hash_without_skb(uint8_t *src_mac, uint8_t *dst_mac,
-+				    void *psrc, void *pdst, uint16_t protocol,
-+				    struct net_device *bond_dev,
-+				    __be16 *layer4hdr);
-+/* QCA NSS ECM support - End */
- #endif /* _NET_BONDING_H */
---- a/include/net/ip6_route.h
-+++ b/include/net/ip6_route.h
-@@ -209,6 +209,11 @@ void rt6_multipath_rebalance(struct fib6
- void rt6_uncached_list_add(struct rt6_info *rt);
- void rt6_uncached_list_del(struct rt6_info *rt);
- 
-+/* QCA NSS ECM support - Start */
-+int rt6_register_notifier(struct notifier_block *nb);
-+int rt6_unregister_notifier(struct notifier_block *nb);
-+/* QCA NSS ECM support - End */
-+
- static inline const struct rt6_info *skb_rt6_info(const struct sk_buff *skb)
- {
- 	const struct dst_entry *dst = skb_dst(skb);
---- a/include/net/neighbour.h
-+++ b/include/net/neighbour.h
-@@ -568,4 +568,15 @@ static inline void neigh_update_is_route
- 		*notify = 1;
- 	}
- }
-+
-+/* QCA NSS ECM support - Start */
-+struct neigh_mac_update {
-+	unsigned char old_mac[ALIGN(MAX_ADDR_LEN, sizeof(unsigned long))];
-+	unsigned char update_mac[ALIGN(MAX_ADDR_LEN, sizeof(unsigned long))];
-+};
-+
-+extern void neigh_mac_update_register_notify(struct notifier_block *nb);
-+extern void neigh_mac_update_unregister_notify(struct notifier_block *nb);
-+/* QCA NSS ECM support - End */
-+
- #endif
---- a/include/net/netfilter/nf_conntrack_extend.h
-+++ b/include/net/netfilter/nf_conntrack_extend.h
-@@ -28,6 +28,10 @@ enum nf_ct_ext_id {
- #if IS_ENABLED(CONFIG_NETFILTER_SYNPROXY)
- 	NF_CT_EXT_SYNPROXY,
- #endif
-+#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
-+	NF_CT_EXT_DSCPREMARK,   /* QCA NSS ECM support */
-+#endif
-+
- 	NF_CT_EXT_NUM,
- };
- 
-@@ -40,6 +44,9 @@ enum nf_ct_ext_id {
- #define NF_CT_EXT_TIMEOUT_TYPE struct nf_conn_timeout
- #define NF_CT_EXT_LABELS_TYPE struct nf_conn_labels
- #define NF_CT_EXT_SYNPROXY_TYPE struct nf_conn_synproxy
-+/* QCA NSS ECM support - Start */
-+#define NF_CT_EXT_DSCPREMARK_TYPE struct nf_ct_dscpremark_ext
-+/* QCA NSS ECM support - End */
- 
- /* Extensions: optional stuff which isn't permanently in struct. */
- struct nf_ct_ext {
---- a/include/net/route.h
-+++ b/include/net/route.h
-@@ -224,6 +224,11 @@ struct rtable *rt_dst_alloc(struct net_d
- 			     bool nopolicy, bool noxfrm, bool will_cache);
- struct rtable *rt_dst_clone(struct net_device *dev, struct rtable *rt);
- 
-+/* QCA NSS ECM support - Start */
-+int ip_rt_register_notifier(struct notifier_block *nb);
-+int ip_rt_unregister_notifier(struct notifier_block *nb);
-+/* QCA NSS ECM support - End */
-+
- struct in_ifaddr;
- void fib_add_ifaddr(struct in_ifaddr *);
- void fib_del_ifaddr(struct in_ifaddr *, struct in_ifaddr *);
---- a/include/uapi/linux/if_bonding.h
-+++ b/include/uapi/linux/if_bonding.h
-@@ -141,6 +141,23 @@ enum {
- };
- #define BOND_3AD_STAT_MAX (__BOND_3AD_STAT_MAX - 1)
- 
-+/* QCA NSS ECM support - Start */
-+#ifdef __KERNEL__
-+struct bond_cb {
-+	void (*bond_cb_link_up)(struct net_device *slave);
-+	void (*bond_cb_link_down)(struct net_device *slave);
-+	void (*bond_cb_enslave)(struct net_device *slave);
-+	void (*bond_cb_release)(struct net_device *slave);
-+	void (*bond_cb_delete_by_slave)(struct net_device *slave);
-+	void (*bond_cb_delete_by_mac)(uint8_t *mac_addr);
-+};
-+
-+extern int bond_register_cb(struct bond_cb *cb);
-+extern void bond_unregister_cb(void);
-+extern int bond_get_id(struct net_device *bond_dev);
-+#endif /* __KERNEL__ */
-+/* QCA NSS ECM support - End */
-+
- #endif /* _LINUX_IF_BONDING_H */
- 
- /*
---- a/drivers/net/bonding/bond_3ad.c
-+++ b/drivers/net/bonding/bond_3ad.c
-@@ -121,6 +121,39 @@ static void ad_marker_response_received(
- 					struct port *port);
- static void ad_update_actor_keys(struct port *port, bool reset);
- 
-+/* QCA NSS ECM support - Start */
-+struct bond_cb __rcu *bond_cb;
-+
-+int bond_register_cb(struct bond_cb *cb)
-+{
-+	struct bond_cb *lag_cb;
-+
-+	rcu_read_lock();
-+	lag_cb = kzalloc(sizeof(*lag_cb), GFP_ATOMIC | __GFP_NOWARN);
-+	if (!lag_cb) {
-+		rcu_read_unlock();
-+		return -1;
-+	}
-+
-+	memcpy((void *)lag_cb, (void *)cb, sizeof(*cb));
-+	rcu_assign_pointer(bond_cb, lag_cb);
-+	rcu_read_unlock();
-+	return 0;
-+}
-+EXPORT_SYMBOL(bond_register_cb);
-+
-+void bond_unregister_cb(void)
-+{
-+	struct bond_cb *lag_cb_main;
-+
-+	rcu_read_lock();
-+	lag_cb_main = rcu_dereference(bond_cb);
-+	kfree(lag_cb_main);
-+	rcu_assign_pointer(bond_cb, NULL);
-+	rcu_read_unlock();
-+}
-+EXPORT_SYMBOL(bond_unregister_cb);
-+/* QCA NSS ECM support - Start */
- 
- /* ================= api to bonding and kernel code ================== */
- 
-@@ -998,6 +1031,29 @@ static void ad_mux_machine(struct port *
- 				port->actor_oper_port_state |=
- 				    AD_STATE_SYNCHRONIZATION;
- 			}
-+
-+			/* QCA NSS ECM support - Start */
-+			/* Send a notificaton about change in state of this
-+			 * port. We only want to handle case where port moves
-+			 * from AD_MUX_COLLECTING_DISTRIBUTING ->
-+			 * AD_MUX_ATTACHED.
-+			 */
-+			if (bond_slave_is_up(port->slave) &&
-+			    (last_state == AD_MUX_COLLECTING_DISTRIBUTING)) {
-+				struct bond_cb *lag_cb_main;
-+
-+				rcu_read_lock();
-+				lag_cb_main = rcu_dereference(bond_cb);
-+				if (lag_cb_main &&
-+				    lag_cb_main->bond_cb_link_down) {
-+					struct net_device *dev;
-+
-+					dev = port->slave->dev;
-+					lag_cb_main->bond_cb_link_down(dev);
-+				}
-+				rcu_read_unlock();
-+			}
-+			/* QCA NSS ECM support - End */
- 			break;
- 		case AD_MUX_COLLECTING_DISTRIBUTING:
- 			if (!(port->sm_vars & AD_PORT_SELECTED) ||
-@@ -1897,6 +1953,8 @@ static void ad_enable_collecting_distrib
- 					      bool *update_slave_arr)
- {
- 	if (port->aggregator->is_active) {
-+		struct bond_cb *lag_cb_main; /* QCA NSS ECM support */
-+
- 		slave_dbg(port->slave->bond->dev, port->slave->dev,
- 			  "Enabling port %d (LAG %d)\n",
- 			  port->actor_port_number,
-@@ -1904,6 +1962,16 @@ static void ad_enable_collecting_distrib
- 		__enable_port(port);
- 		/* Slave array needs update */
- 		*update_slave_arr = true;
-+
-+		/* QCA NSS ECM support - Start */
-+		rcu_read_lock();
-+		lag_cb_main = rcu_dereference(bond_cb);
-+
-+		if (lag_cb_main && lag_cb_main->bond_cb_link_up)
-+			lag_cb_main->bond_cb_link_up(port->slave->dev);
-+
-+		rcu_read_unlock();
-+		/* QCA NSS ECM support - End */
- 	}
- }
- 
-@@ -2776,3 +2844,101 @@ int bond_3ad_stats_fill(struct sk_buff *
- 
- 	return 0;
- }
-+
-+/* QCA NSS ECM support - Start */
-+/* bond_3ad_get_tx_dev - Calculate egress interface for a given packet,
-+ * for a LAG that is configured in 802.3AD mode
-+ * @skb: pointer to skb to be egressed
-+ * @src_mac: pointer to source L2 address
-+ * @dst_mac: pointer to destination L2 address
-+ * @src: pointer to source L3 address
-+ * @dst: pointer to destination L3 address
-+ * @protocol: L3 protocol id from L2 header
-+ * @bond_dev: pointer to bond master device
-+ *
-+ * If @skb is NULL, bond_xmit_hash is used to calculate hash using L2/L3
-+ * addresses.
-+ *
-+ * Returns: Either valid slave device, or NULL otherwise
-+ */
-+struct net_device *bond_3ad_get_tx_dev(struct sk_buff *skb, u8 *src_mac,
-+				       u8 *dst_mac, void *src,
-+				       void *dst, u16 protocol,
-+				       struct net_device *bond_dev,
-+				       __be16 *layer4hdr)
-+{
-+	struct bonding *bond = netdev_priv(bond_dev);
-+	struct aggregator *agg;
-+	struct ad_info ad_info;
-+	struct list_head *iter;
-+	struct slave *slave;
-+	struct slave *first_ok_slave = NULL;
-+	u32 hash = 0;
-+	int slaves_in_agg;
-+	int slave_agg_no = 0;
-+	int agg_id;
-+
-+	if (__bond_3ad_get_active_agg_info(bond, &ad_info)) {
-+		pr_debug("%s: Error: __bond_3ad_get_active_agg_info failed\n",
-+			 bond_dev->name);
-+		return NULL;
-+	}
-+
-+	slaves_in_agg = ad_info.ports;
-+	agg_id = ad_info.aggregator_id;
-+
-+	if (slaves_in_agg == 0) {
-+		pr_debug("%s: Error: active aggregator is empty\n",
-+			 bond_dev->name);
-+		return NULL;
-+	}
-+
-+	if (skb) {
-+		hash = bond_xmit_hash(bond, skb);
-+		slave_agg_no = hash % slaves_in_agg;
-+	} else {
-+		if (bond->params.xmit_policy != BOND_XMIT_POLICY_LAYER23 &&
-+		    bond->params.xmit_policy != BOND_XMIT_POLICY_LAYER2 &&
-+		    bond->params.xmit_policy != BOND_XMIT_POLICY_LAYER34) {
-+			pr_debug("%s: Error: Unsupported hash policy for 802.3AD fast path\n",
-+				 bond_dev->name);
-+			return NULL;
-+		}
-+
-+		hash = bond_xmit_hash_without_skb(src_mac, dst_mac,
-+						  src, dst, protocol,
-+						  bond_dev, layer4hdr);
-+		slave_agg_no = hash % slaves_in_agg;
-+	}
-+
-+	bond_for_each_slave_rcu(bond, slave, iter) {
-+		agg = SLAVE_AD_INFO(slave)->port.aggregator;
-+		if (!agg || agg->aggregator_identifier != agg_id)
-+			continue;
-+
-+		if (slave_agg_no >= 0) {
-+			if (!first_ok_slave && bond_slave_can_tx(slave))
-+				first_ok_slave = slave;
-+			slave_agg_no--;
-+			continue;
-+		}
-+
-+		if (bond_slave_can_tx(slave))
-+			return slave->dev;
-+	}
-+
-+	if (slave_agg_no >= 0) {
-+		pr_err("%s: Error: Couldn't find a slave to tx on for aggregator ID %d\n",
-+		       bond_dev->name, agg_id);
-+		return NULL;
-+	}
-+
-+	/* we couldn't find any suitable slave after the agg_no, so use the
-+	 * first suitable found, if found.
-+	 */
-+	if (first_ok_slave)
-+		return first_ok_slave->dev;
-+
-+	return NULL;
-+}
-+/* QCA NSS ECM support - End */
---- a/drivers/net/bonding/bond_main.c
-+++ b/drivers/net/bonding/bond_main.c
-@@ -199,6 +199,7 @@ atomic_t netpoll_block_tx = ATOMIC_INIT(
- #endif
- 
- unsigned int bond_net_id __read_mostly;
-+static unsigned long bond_id_mask = 0xFFFFFFF0; /* QCA NSS ECM Support */
- 
- /*-------------------------- Forward declarations ---------------------------*/
- 
-@@ -847,6 +848,23 @@ void bond_change_active_slave(struct bon
- 			if (BOND_MODE(bond) == BOND_MODE_8023AD)
- 				bond_3ad_handle_link_change(new_active, BOND_LINK_UP);
- 
-+			/* QCA NSS ECM support - Start */
-+			if (bond->params.mode == BOND_MODE_XOR) {
-+				struct bond_cb *lag_cb_main;
-+
-+				rcu_read_lock();
-+				lag_cb_main = rcu_dereference(bond_cb);
-+				if (lag_cb_main &&
-+				    lag_cb_main->bond_cb_link_up) {
-+					struct net_device *dev;
-+
-+					dev = new_active->dev;
-+					lag_cb_main->bond_cb_link_up(dev);
-+				}
-+				rcu_read_unlock();
-+			}
-+			/* QCA NSS ECM support - End */
-+
- 			if (bond_is_lb(bond))
- 				bond_alb_handle_link_change(bond, new_active, BOND_LINK_UP);
- 		} else {
-@@ -1418,6 +1436,7 @@ int bond_enslave(struct net_device *bond
- 	const struct net_device_ops *slave_ops = slave_dev->netdev_ops;
- 	struct slave *new_slave = NULL, *prev_slave;
- 	struct sockaddr_storage ss;
-+	struct bond_cb *lag_cb_main; /* QCA NSS ECM support */
- 	int link_reporting;
- 	int res = 0, i;
- 
-@@ -1817,6 +1836,13 @@ int bond_enslave(struct net_device *bond
- 	if (bond_mode_can_use_xmit_hash(bond))
- 		bond_update_slave_arr(bond, NULL);
- 
-+	/* QCA NSS ECM support - Start */
-+	rcu_read_lock();
-+	lag_cb_main = rcu_dereference(bond_cb);
-+	if (lag_cb_main && lag_cb_main->bond_cb_enslave)
-+		lag_cb_main->bond_cb_enslave(slave_dev);
-+	rcu_read_unlock();
-+	/* QCA NSS ECM support - End */
- 
- 	slave_info(bond_dev, slave_dev, "Enslaving as %s interface with %s link\n",
- 		   bond_is_active_slave(new_slave) ? "an active" : "a backup",
-@@ -1889,6 +1915,14 @@ err_undo_flags:
- 		}
- 	}
- 
-+	/* QCA NSS ECM support - Start */
-+	rcu_read_lock();
-+	lag_cb_main = rcu_dereference(bond_cb);
-+	if (lag_cb_main && lag_cb_main->bond_cb_enslave)
-+		lag_cb_main->bond_cb_enslave(slave_dev);
-+	rcu_read_unlock();
-+	/* QCA NSS ECM support - End */
-+
- 	return res;
- }
- 
-@@ -1910,6 +1944,7 @@ static int __bond_release_one(struct net
- 	struct bonding *bond = netdev_priv(bond_dev);
- 	struct slave *slave, *oldcurrent;
- 	struct sockaddr_storage ss;
-+	struct bond_cb *lag_cb_main; /* QCA NSS ECM support */
- 	int old_flags = bond_dev->flags;
- 	netdev_features_t old_features = bond_dev->features;
- 
-@@ -1932,6 +1967,14 @@ static int __bond_release_one(struct net
- 
- 	bond_set_slave_inactive_flags(slave, BOND_SLAVE_NOTIFY_NOW);
- 
-+	/* QCA NSS ECM support - Start */
-+	rcu_read_lock();
-+	lag_cb_main = rcu_dereference(bond_cb);
-+	if (lag_cb_main && lag_cb_main->bond_cb_release)
-+		lag_cb_main->bond_cb_release(slave_dev);
-+	rcu_read_unlock();
-+	/* QCA NSS ECM support - End */
-+
- 	bond_sysfs_slave_del(slave);
- 
- 	/* recompute stats just before removing the slave */
-@@ -2237,6 +2280,10 @@ static void bond_miimon_commit(struct bo
- {
- 	struct list_head *iter;
- 	struct slave *slave, *primary;
-+	/* QCA NSS ECM support - Start */
-+	struct net_device *slave_dev = NULL;
-+	struct bond_cb *lag_cb_main;
-+	/* QCA NSS ECM support - End */
- 
- 	bond_for_each_slave(bond, slave, iter) {
- 		switch (slave->link_new_state) {
-@@ -2280,6 +2327,12 @@ static void bond_miimon_commit(struct bo
- 
- 			bond_miimon_link_change(bond, slave, BOND_LINK_UP);
- 
-+			/* QCA NSS ECM support - Start */
-+			if ((bond->params.mode == BOND_MODE_XOR) &&
-+			    (!slave_dev))
-+				slave_dev = slave->dev;
-+			/* QCA NSS ECM support - End */
-+
- 			if (!bond->curr_active_slave || slave == primary)
- 				goto do_failover;
- 
-@@ -2321,6 +2374,15 @@ do_failover:
- 	}
- 
- 	bond_set_carrier(bond);
-+
-+	/* QCA NSS ECM support - Start */
-+	rcu_read_lock();
-+	lag_cb_main = rcu_dereference(bond_cb);
-+
-+	if (slave_dev && lag_cb_main && lag_cb_main->bond_cb_link_up)
-+		lag_cb_main->bond_cb_link_up(slave_dev);
-+	rcu_read_unlock();
-+	/* QCA NSS ECM support - End */
- }
- 
- /* bond_mii_monitor
-@@ -4414,6 +4476,11 @@ static void bond_destructor(struct net_d
- 	struct bonding *bond = netdev_priv(bond_dev);
- 	if (bond->wq)
- 		destroy_workqueue(bond->wq);
-+
-+	/* QCA NSS ECM Support - Start */
-+	if (bond->id != (~0U))
-+		clear_bit(bond->id, &bond_id_mask);
-+	/* QCA NSS ECM Support - End */
- }
- 
- void bond_setup(struct net_device *bond_dev)
-@@ -4967,6 +5034,16 @@ int bond_create(struct net *net, const c
- 	bond_work_init_all(bond);
- 
- 	rtnl_unlock();
-+
-+	/* QCA NSS ECM Support - Start */
-+	bond = netdev_priv(bond_dev);
-+	bond->id = ~0U;
-+	if (bond_id_mask != (~0UL)) {
-+		bond->id = (u32)ffz(bond_id_mask);
-+		set_bit(bond->id, &bond_id_mask);
-+	}
-+	/* QCA NSS ECM Support - End */
-+
- 	return 0;
- }
- 
-@@ -5062,6 +5139,203 @@ static void __exit bonding_exit(void)
- #endif
- }
- 
-+/* QCA NSS ECM support - Start */
-+static bool bond_flow_dissect_without_skb(struct bonding *bond,
-+					  u8 *src_mac, u8 *dst_mac,
-+					  void *psrc, void *pdst,
-+					  u16 protocol, __be16 *layer4hdr,
-+					  struct flow_keys *fk)
-+{
-+	u32 *src = NULL;
-+	u32 *dst = NULL;
-+
-+	fk->ports.ports = 0;
-+	src = (uint32_t *)psrc;
-+	dst = (uint32_t *)pdst;
-+
-+	if (protocol == htons(ETH_P_IP)) {
-+		/* V4 addresses and address type*/
-+		fk->addrs.v4addrs.src = src[0];
-+		fk->addrs.v4addrs.dst = dst[0];
-+		fk->control.addr_type = FLOW_DISSECTOR_KEY_IPV4_ADDRS;
-+	} else if (protocol == htons(ETH_P_IPV6)) {
-+		/* V6 addresses and address type*/
-+		memcpy(&fk->addrs.v6addrs.src, src, sizeof(struct in6_addr));
-+		memcpy(&fk->addrs.v6addrs.dst, dst, sizeof(struct in6_addr));
-+		fk->control.addr_type = FLOW_DISSECTOR_KEY_IPV6_ADDRS;
-+	} else {
-+		return false;
-+	}
-+	if ((bond->params.xmit_policy == BOND_XMIT_POLICY_LAYER34) &&
-+	    (layer4hdr))
-+		fk->ports.ports = *layer4hdr;
-+
-+	return true;
-+}
-+
-+/* Extract the appropriate headers based on bond's xmit policy */
-+
-+/* bond_xmit_hash_without_skb - Applies load balancing algorithm for a packet,
-+ * to calculate hash for a given set of L2/L3 addresses. Does not
-+ * calculate egress interface.
-+ */
-+uint32_t bond_xmit_hash_without_skb(u8 *src_mac, u8 *dst_mac,
-+				    void *psrc, void *pdst, u16 protocol,
-+				    struct net_device *bond_dev,
-+				    __be16 *layer4hdr)
-+{
-+	struct bonding *bond = netdev_priv(bond_dev);
-+	struct flow_keys flow;
-+	u32 hash = 0;
-+
-+	if (bond->params.xmit_policy == BOND_XMIT_POLICY_LAYER2 ||
-+	    !bond_flow_dissect_without_skb(bond, src_mac, dst_mac, psrc,
-+					   pdst, protocol, layer4hdr, &flow))
-+		return (dst_mac[5] ^ src_mac[5]);
-+
-+	if (bond->params.xmit_policy == BOND_XMIT_POLICY_LAYER23)
-+		hash = dst_mac[5] ^ src_mac[5];
-+	else if (layer4hdr)
-+		hash = (__force u32)flow.ports.ports;
-+
-+	hash ^= (__force u32)flow_get_u32_dst(&flow) ^
-+		(__force u32)flow_get_u32_src(&flow);
-+	hash ^= (hash >> 16);
-+	hash ^= (hash >> 8);
-+
-+	return hash;
-+}
-+
-+/* bond_xor_get_tx_dev - Calculate egress interface for a given packet for a LAG
-+ * that is configured in balance-xor mode
-+ * @skb: pointer to skb to be egressed
-+ * @src_mac: pointer to source L2 address
-+ * @dst_mac: pointer to destination L2 address
-+ * @src: pointer to source L3 address in network order
-+ * @dst: pointer to destination L3 address in network order
-+ * @protocol: L3 protocol
-+ * @bond_dev: pointer to bond master device
-+ *
-+ * If @skb is NULL, bond_xmit_hash_without_skb is used to calculate hash using
-+ * L2/L3 addresses.
-+ *
-+ * Returns: Either valid slave device, or NULL otherwise
-+ */
-+static struct net_device *bond_xor_get_tx_dev(struct sk_buff *skb,
-+					      u8 *src_mac, u8 *dst_mac,
-+					      void *src, void *dst,
-+					      u16 protocol,
-+					      struct net_device *bond_dev,
-+					      __be16 *layer4hdr)
-+{
-+	struct bonding *bond = netdev_priv(bond_dev);
-+	int slave_cnt = READ_ONCE(bond->slave_cnt);
-+	int slave_id = 0, i = 0;
-+	u32 hash;
-+	struct list_head *iter;
-+	struct slave *slave;
-+
-+	if (slave_cnt == 0) {
-+		pr_debug("%s: Error: No slave is attached to the interface\n",
-+			 bond_dev->name);
-+		return NULL;
-+	}
-+
-+	if (skb) {
-+		hash = bond_xmit_hash(bond, skb);
-+		slave_id = hash % slave_cnt;
-+	} else {
-+		if (bond->params.xmit_policy != BOND_XMIT_POLICY_LAYER23 &&
-+		    bond->params.xmit_policy != BOND_XMIT_POLICY_LAYER2	&&
-+		    bond->params.xmit_policy != BOND_XMIT_POLICY_LAYER34) {
-+			pr_debug("%s: Error: Unsupported hash policy for balance-XOR fast path\n",
-+				 bond_dev->name);
-+			return NULL;
-+		}
-+
-+		hash = bond_xmit_hash_without_skb(src_mac, dst_mac, src,
-+						  dst, protocol, bond_dev,
-+						  layer4hdr);
-+		slave_id = hash % slave_cnt;
-+	}
-+
-+	i = slave_id;
-+
-+	/* Here we start from the slave with slave_id */
-+	bond_for_each_slave_rcu(bond, slave, iter) {
-+		if (--i < 0) {
-+			if (bond_slave_can_tx(slave))
-+				return slave->dev;
-+		}
-+	}
-+
-+	/* Here we start from the first slave up to slave_id */
-+	i = slave_id;
-+	bond_for_each_slave_rcu(bond, slave, iter) {
-+		if (--i < 0)
-+			break;
-+		if (bond_slave_can_tx(slave))
-+			return slave->dev;
-+	}
-+
-+	return NULL;
-+}
-+
-+/* bond_get_tx_dev - Calculate egress interface for a given packet.
-+ *
-+ * Supports 802.3AD and balance-xor modes
-+ *
-+ * @skb: pointer to skb to be egressed, if valid
-+ * @src_mac: pointer to source L2 address
-+ * @dst_mac: pointer to destination L2 address
-+ * @src: pointer to source L3 address in network order
-+ * @dst: pointer to destination L3 address in network order
-+ * @protocol: L3 protocol id from L2 header
-+ * @bond_dev: pointer to bond master device
-+ *
-+ * Returns: Either valid slave device, or NULL for un-supported LAG modes
-+ */
-+struct net_device *bond_get_tx_dev(struct sk_buff *skb, uint8_t *src_mac,
-+				   u8 *dst_mac, void *src,
-+				   void *dst, u16 protocol,
-+				   struct net_device *bond_dev,
-+				   __be16 *layer4hdr)
-+{
-+	struct bonding *bond = netdev_priv(bond_dev);
-+
-+	if (!bond)
-+		return NULL;
-+
-+	switch (bond->params.mode) {
-+	case BOND_MODE_XOR:
-+		return bond_xor_get_tx_dev(skb, src_mac, dst_mac,
-+					   src, dst, protocol,
-+					   bond_dev, layer4hdr);
-+	case BOND_MODE_8023AD:
-+		return bond_3ad_get_tx_dev(skb, src_mac, dst_mac,
-+					   src, dst, protocol,
-+					   bond_dev, layer4hdr);
-+	default:
-+		return NULL;
-+	}
-+}
-+EXPORT_SYMBOL(bond_get_tx_dev);
-+
-+int bond_get_id(struct net_device *bond_dev)
-+{
-+	struct bonding *bond;
-+
-+	if (!((bond_dev->priv_flags & IFF_BONDING) &&
-+	      (bond_dev->flags & IFF_MASTER)))
-+		return -EINVAL;
-+
-+	bond = netdev_priv(bond_dev);
-+
-+	return bond->id;
-+}
-+EXPORT_SYMBOL(bond_get_id);
-+/* QCA NSS ECM support - End */
-+
- module_init(bonding_init);
- module_exit(bonding_exit);
- MODULE_LICENSE("GPL");
---- a/net/8021q/vlan_core.c
-+++ b/net/8021q/vlan_core.c
-@@ -551,4 +551,52 @@ static int __init vlan_offload_init(void
- 	return 0;
- }
- 
-+/* QCA NSS ECM support - Start */
-+/* Update the VLAN device with statistics from network offload engines */
-+void __vlan_dev_update_accel_stats(struct net_device *dev,
-+				   struct rtnl_link_stats64 *nlstats)
-+{
-+	struct vlan_pcpu_stats *stats;
-+
-+	if (!is_vlan_dev(dev))
-+		return;
-+
-+	stats = per_cpu_ptr(vlan_dev_priv(dev)->vlan_pcpu_stats, 0);
-+
-+	u64_stats_update_begin(&stats->syncp);
-+	stats->rx_packets += nlstats->rx_packets;
-+	stats->rx_bytes += nlstats->rx_bytes;
-+	stats->tx_packets += nlstats->tx_packets;
-+	stats->tx_bytes += nlstats->tx_bytes;
-+	u64_stats_update_end(&stats->syncp);
-+}
-+EXPORT_SYMBOL(__vlan_dev_update_accel_stats);
-+
-+/* Lookup the 802.1p egress_map table and return the 802.1p value */
-+u16 vlan_dev_get_egress_prio(struct net_device *dev, u32 skb_prio)
-+{
-+	struct vlan_priority_tci_mapping *mp;
-+
-+	mp = vlan_dev_priv(dev)->egress_priority_map[(skb_prio & 0xf)];
-+	while (mp) {
-+		if (mp->priority == skb_prio) {
-+			/* This should already be shifted
-+			 * to mask correctly with the
-+			 * VLAN's TCI
-+			 */
-+			return mp->vlan_qos;
-+		}
-+		mp = mp->next;
-+	}
-+	return 0;
-+}
-+EXPORT_SYMBOL(vlan_dev_get_egress_prio);
-+
-+struct net_device *vlan_dev_next_dev(const struct net_device *dev)
-+{
-+	return vlan_dev_priv(dev)->real_dev;
-+}
-+EXPORT_SYMBOL(vlan_dev_next_dev);
-+/* QCA NSS ECM support - End */
-+
- fs_initcall(vlan_offload_init);
---- a/net/bridge/br_fdb.c
-+++ b/net/bridge/br_fdb.c
-@@ -37,6 +37,35 @@ static int fdb_insert(struct net_bridge
- static void fdb_notify(struct net_bridge *br,
- 		       const struct net_bridge_fdb_entry *, int, bool);
- 
-+/* QCA NSS ECM support - Start */
-+ATOMIC_NOTIFIER_HEAD(br_fdb_notifier_list);
-+ATOMIC_NOTIFIER_HEAD(br_fdb_update_notifier_list);
-+
-+void br_fdb_register_notify(struct notifier_block *nb)
-+{
-+	atomic_notifier_chain_register(&br_fdb_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(br_fdb_register_notify);
-+
-+void br_fdb_unregister_notify(struct notifier_block *nb)
-+{
-+	atomic_notifier_chain_unregister(&br_fdb_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(br_fdb_unregister_notify);
-+
-+void br_fdb_update_register_notify(struct notifier_block *nb)
-+{
-+	atomic_notifier_chain_register(&br_fdb_update_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(br_fdb_update_register_notify);
-+
-+void br_fdb_update_unregister_notify(struct notifier_block *nb)
-+{
-+	atomic_notifier_chain_unregister(&br_fdb_update_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(br_fdb_update_unregister_notify);
-+/* QCA NSS ECM support - End */
-+
- int __init br_fdb_init(void)
- {
- 	br_fdb_cache = kmem_cache_create("bridge_fdb_cache",
-@@ -337,6 +366,7 @@ void br_fdb_cleanup(struct work_struct *
- 	unsigned long delay = hold_time(br);
- 	unsigned long work_delay = delay;
- 	unsigned long now = jiffies;
-+	u8 mac_addr[6]; /* QCA NSS ECM support */
- 
- 	/* this part is tricky, in order to avoid blocking learning and
- 	 * consequently forwarding, we rely on rcu to delete objects with
-@@ -353,8 +383,15 @@ void br_fdb_cleanup(struct work_struct *
- 			work_delay = min(work_delay, this_timer - now);
- 		} else {
- 			spin_lock_bh(&br->hash_lock);
--			if (!hlist_unhashed(&f->fdb_node))
-+			if (!hlist_unhashed(&f->fdb_node)) {
-+				ether_addr_copy(mac_addr, f->key.addr.addr);
- 				fdb_delete(br, f, true);
-+				/* QCA NSS ECM support - Start */
-+				atomic_notifier_call_chain(
-+					&br_fdb_update_notifier_list, 0,
-+					(void *)mac_addr);
-+				/* QCA NSS ECM support - End */
-+			}
- 			spin_unlock_bh(&br->hash_lock);
- 		}
- 	}
-@@ -587,6 +624,12 @@ void br_fdb_update(struct net_bridge *br
- 				/* Take over HW learned entry */
- 				if (unlikely(fdb->added_by_external_learn))
- 					fdb->added_by_external_learn = 0;
-+
-+				/* QCA NSS ECM support - Start */
-+				atomic_notifier_call_chain(
-+					&br_fdb_update_notifier_list,
-+					0, (void *)addr);
-+				/* QCA NSS ECM support - End */
- 			}
- 			if (now != fdb->updated)
- 				fdb->updated = now;
-@@ -696,6 +739,25 @@ static void fdb_notify(struct net_bridge
- 	struct sk_buff *skb;
- 	int err = -ENOBUFS;
- 
-+	/* QCA NSS ECM support - Start */
-+	if (fdb->dst) {
-+		int event;
-+		struct br_fdb_event fdb_event;
-+
-+		if (type == RTM_NEWNEIGH)
-+			event = BR_FDB_EVENT_ADD;
-+		else
-+			event = BR_FDB_EVENT_DEL;
-+
-+		fdb_event.dev = fdb->dst->dev;
-+		ether_addr_copy(fdb_event.addr, fdb->key.addr.addr);
-+		fdb_event.is_local = fdb->is_local;
-+		atomic_notifier_call_chain(&br_fdb_notifier_list,
-+					   event,
-+					   (void *)&fdb_event);
-+	}
-+	/* QCA NSS ECM support - End */
-+
- 	if (swdev_notify)
- 		br_switchdev_fdb_notify(br, fdb, type);
- 
-@@ -1212,3 +1274,44 @@ void br_fdb_clear_offload(const struct n
- 	spin_unlock_bh(&p->br->hash_lock);
- }
- EXPORT_SYMBOL_GPL(br_fdb_clear_offload);
-+
-+/* QCA NSS ECM support - Start */
-+/* Refresh FDB entries for bridge packets being forwarded by offload engines */
-+void br_refresh_fdb_entry(struct net_device *dev, const char *addr)
-+{
-+	struct net_bridge_port *p = br_port_get_rcu(dev);
-+
-+	if (!p || p->state == BR_STATE_DISABLED)
-+		return;
-+
-+	if (!is_valid_ether_addr(addr)) {
-+		pr_info("bridge: Attempt to refresh with invalid ether address %pM\n",
-+			addr);
-+		return;
-+	}
-+
-+	rcu_read_lock();
-+	br_fdb_update(p->br, p, addr, 0, true);
-+	rcu_read_unlock();
-+}
-+EXPORT_SYMBOL_GPL(br_refresh_fdb_entry);
-+
-+/* Look up the MAC address in the device's bridge fdb table */
-+struct net_bridge_fdb_entry *br_fdb_has_entry(struct net_device *dev,
-+					      const char *addr, __u16 vid)
-+{
-+	struct net_bridge_port *p = br_port_get_rcu(dev);
-+	struct net_bridge_fdb_entry *fdb;
-+
-+	if (!p || p->state == BR_STATE_DISABLED)
-+		return NULL;
-+
-+	rcu_read_lock();
-+	fdb = fdb_find_rcu(&p->br->fdb_hash_tbl, addr, vid);
-+	rcu_read_unlock();
-+
-+	return fdb;
-+}
-+EXPORT_SYMBOL_GPL(br_fdb_has_entry);
-+/* QCA NSS ECM support - End */
-+
---- a/net/bridge/br_if.c
-+++ b/net/bridge/br_if.c
-@@ -26,6 +26,12 @@
- 
- #include "br_private.h"
- 
-+/* QCA NSS ECM support - Start */
-+/* Hook for external forwarding logic */
-+br_port_dev_get_hook_t __rcu *br_port_dev_get_hook __read_mostly;
-+EXPORT_SYMBOL_GPL(br_port_dev_get_hook);
-+/* QCA NSS ECM support - End */
-+
- /*
-  * Determine initial path cost based on speed.
-  * using recommendations from 802.1d standard
-@@ -696,6 +702,8 @@ int br_add_if(struct net_bridge *br, str
- 
- 	kobject_uevent(&p->kobj, KOBJ_ADD);
- 
-+	call_netdevice_notifiers(NETDEV_BR_JOIN, dev); /* QCA NSS ECM support */
-+
- 	return 0;
- 
- err7:
-@@ -731,6 +739,8 @@ int br_del_if(struct net_bridge *br, str
- 	p = br_port_get_rtnl(dev);
- 	if (!p || p->br != br)
- 		return -EINVAL;
-+		
-+	call_netdevice_notifiers(NETDEV_BR_LEAVE, dev); /* QCA NSS ECM support */
- 
- 	/* Since more than one interface can be attached to a bridge,
- 	 * there still maybe an alternate path for netconsole to use;
-@@ -786,6 +796,67 @@ void br_dev_update_stats(struct net_devi
- }
- EXPORT_SYMBOL_GPL(br_dev_update_stats);
- 
-+/* QCA NSS ECM support - Start */
-+/* br_port_dev_get()
-+ *      If a skb is provided, and the br_port_dev_get_hook_t hook exists,
-+ *      use that to try and determine the egress port for that skb.
-+ *      If not, or no egress port could be determined, use the given addr
-+ *      to identify the port to which it is reachable,
-+ *	returing a reference to the net device associated with that port.
-+ *
-+ * NOTE: Return NULL if given dev is not a bridge or the mac has no
-+ * associated port.
-+ */
-+struct net_device *br_port_dev_get(struct net_device *dev, unsigned char *addr,
-+				   struct sk_buff *skb,
-+				   unsigned int cookie)
-+{
-+	struct net_bridge_fdb_entry *fdbe;
-+	struct net_bridge *br;
-+	struct net_device *netdev = NULL;
-+
-+	/* Is this a bridge? */
-+	if (!(dev->priv_flags & IFF_EBRIDGE))
-+		return NULL;
-+
-+	rcu_read_lock();
-+
-+	/* If the hook exists and the skb isn't NULL, try and get the port */
-+	if (skb) {
-+		br_port_dev_get_hook_t *port_dev_get_hook;
-+
-+		port_dev_get_hook = rcu_dereference(br_port_dev_get_hook);
-+		if (port_dev_get_hook) {
-+			struct net_bridge_port *pdst =
-+				__br_get(port_dev_get_hook, NULL, dev, skb,
-+					 addr, cookie);
-+			if (pdst) {
-+				dev_hold(pdst->dev);
-+				netdev = pdst->dev;
-+				goto out;
-+			}
-+		}
-+	}
-+
-+	/* Either there is no hook, or can't
-+	 * determine the port to use - fall back to using FDB
-+	 */
-+
-+	br = netdev_priv(dev);
-+
-+	/* Lookup the fdb entry and get reference to the port dev */
-+	fdbe = br_fdb_find_rcu(br, addr, 0);
-+	if (fdbe && fdbe->dst) {
-+		netdev = fdbe->dst->dev; /* port device */
-+		dev_hold(netdev);
-+	}
-+out:
-+	rcu_read_unlock();
-+	return netdev;
-+}
-+EXPORT_SYMBOL_GPL(br_port_dev_get);
-+/* QCA NSS ECM support - End */
-+
- bool br_port_flag_is_set(const struct net_device *dev, unsigned long flag)
- {
- 	struct net_bridge_port *p;
---- a/net/bridge/br_private.h
-+++ b/net/bridge/br_private.h
-@@ -1269,4 +1269,9 @@ void br_do_proxy_suppress_arp(struct sk_
- void br_do_suppress_nd(struct sk_buff *skb, struct net_bridge *br,
- 		       u16 vid, struct net_bridge_port *p, struct nd_msg *msg);
- struct nd_msg *br_is_nd_neigh_msg(struct sk_buff *skb, struct nd_msg *m);
-+
-+/* QCA NSS ECM support - Start */
-+#define __br_get(__hook, __default, __args ...) \
-+		(__hook ? (__hook(__args)) : (__default))
-+/* QCA NSS ECM support - End */
- #endif
---- a/net/core/neighbour.c
-+++ b/net/core/neighbour.c
-@@ -1208,7 +1208,21 @@ static void neigh_update_hhs(struct neig
- 	}
- }
- 
-+/* QCA NSS ECM support - start */
-+ATOMIC_NOTIFIER_HEAD(neigh_mac_update_notifier_list);
-+ 
-+void neigh_mac_update_register_notify(struct notifier_block *nb)
-+{
-+	atomic_notifier_chain_register(&neigh_mac_update_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(neigh_mac_update_register_notify);
- 
-+void neigh_mac_update_unregister_notify(struct notifier_block *nb)
-+{
-+	atomic_notifier_chain_unregister(&neigh_mac_update_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(neigh_mac_update_unregister_notify);
-+/* QCA NSS ECM support - End */
- 
- /* Generic update routine.
-    -- lladdr is new lladdr or NULL, if it is not supplied.
-@@ -1239,6 +1253,7 @@ static int __neigh_update(struct neighbo
- 	int notify = 0;
- 	struct net_device *dev;
- 	int update_isrouter = 0;
-+	struct neigh_mac_update nmu; /* QCA NSS ECM support */
- 
- 	trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid);
- 
-@@ -1248,6 +1263,8 @@ static int __neigh_update(struct neighbo
- 	old    = neigh->nud_state;
- 	err    = -EPERM;
- 
-+	memset(&nmu, 0, sizeof(struct neigh_mac_update)); /* QCA NSS ECM support */
-+
- 	if (neigh->dead) {
- 		NL_SET_ERR_MSG(extack, "Neighbor entry is now dead");
- 		new = old;
-@@ -1290,6 +1307,11 @@ static int __neigh_update(struct neighbo
- 		   - compare new & old
- 		   - if they are different, check override flag
- 		 */
-+		/* QCA NSS ECM update - Start */
-+		memcpy(nmu.old_mac, neigh->ha, dev->addr_len);
-+		memcpy(nmu.update_mac, lladdr, dev->addr_len);
-+		/* QCA NSS ECM update - End */
-+
- 		if ((old & NUD_VALID) &&
- 		    !memcmp(lladdr, neigh->ha, dev->addr_len))
- 			lladdr = neigh->ha;
-@@ -1412,8 +1434,11 @@ out:
- 	if (((new ^ old) & NUD_PERMANENT) || ext_learn_change)
- 		neigh_update_gc_list(neigh);
- 
--	if (notify)
-+	if (notify) {
- 		neigh_update_notify(neigh, nlmsg_pid);
-+		atomic_notifier_call_chain(&neigh_mac_update_notifier_list, 0,
-+					   (struct neigh_mac_update *)&nmu); /* QCA NSS ECM support */
-+	}
- 
- 	trace_neigh_update_done(neigh, err);
- 
---- a/net/ipv4/fib_trie.c
-+++ b/net/ipv4/fib_trie.c
-@@ -1116,6 +1116,9 @@ static bool fib_valid_key_len(u32 key, u
- 	return true;
- }
- 
-+/* Define route change notification chain. */
-+static BLOCKING_NOTIFIER_HEAD(iproute_chain);	/* QCA NSS ECM support */
-+
- /* Caller must hold RTNL. */
- int fib_table_insert(struct net *net, struct fib_table *tb,
- 		     struct fib_config *cfg, struct netlink_ext_ack *extack)
-@@ -1283,6 +1286,9 @@ int fib_table_insert(struct net *net, st
- 	rtmsg_fib(RTM_NEWROUTE, htonl(key), new_fa, plen, new_fa->tb_id,
- 		  &cfg->fc_nlinfo, nlflags);
- succeeded:
-+	blocking_notifier_call_chain(&iproute_chain,
-+				     RTM_NEWROUTE, fi);
-+
- 	return 0;
- 
- out_fib_notif:
-@@ -1610,6 +1616,9 @@ int fib_table_delete(struct net *net, st
- 	if (fa_to_delete->fa_state & FA_S_ACCESSED)
- 		rt_cache_flush(cfg->fc_nlinfo.nl_net);
- 
-+	blocking_notifier_call_chain(&iproute_chain,
-+				     RTM_DELROUTE, fa_to_delete->fa_info);
-+
- 	fib_release_info(fa_to_delete->fa_info);
- 	alias_free_mem_rcu(fa_to_delete);
- 	return 0;
-@@ -2221,6 +2230,20 @@ void __init fib_trie_init(void)
- 					   0, SLAB_PANIC, NULL);
- }
- 
-+/* QCA NSS ECM support - Start */
-+int ip_rt_register_notifier(struct notifier_block *nb)
-+{
-+	return blocking_notifier_chain_register(&iproute_chain, nb);
-+}
-+EXPORT_SYMBOL(ip_rt_register_notifier);
-+
-+int ip_rt_unregister_notifier(struct notifier_block *nb)
-+{
-+	return blocking_notifier_chain_unregister(&iproute_chain, nb);
-+}
-+EXPORT_SYMBOL(ip_rt_unregister_notifier);
-+/* QCA NSS ECM support - End */
-+
- struct fib_table *fib_trie_table(u32 id, struct fib_table *alias)
- {
- 	struct fib_table *tb;
---- a/net/ipv6/addrconf.c
-+++ b/net/ipv6/addrconf.c
-@@ -7203,3 +7203,35 @@ void addrconf_cleanup(void)
- 
- 	destroy_workqueue(addrconf_wq);
- }
-+
-+/* QCA NSS ECM support - Start */
-+/* ipv6_dev_find()
-+ *	Find (and hold) net device that has the given address.
-+ *	Or NULL on failure.
-+ */
-+struct net_device *ipv6_dev_find(struct net *net, struct in6_addr *addr,
-+				 int strict)
-+{
-+	struct inet6_ifaddr *ifp;
-+	struct net_device *dev;
-+
-+	ifp = ipv6_get_ifaddr(net, addr, NULL, strict);
-+	if (!ifp)
-+		return NULL;
-+
-+	if (!ifp->idev) {
-+		in6_ifa_put(ifp);
-+		return NULL;
-+	}
-+
-+	dev = ifp->idev->dev;
-+	if (dev)
-+		dev_hold(dev);
-+
-+	in6_ifa_put(ifp);
-+
-+	return dev;
-+}
-+EXPORT_SYMBOL(ipv6_dev_find);
-+/* QCA NSS ECM support - End */
-+
---- a/net/ipv6/ndisc.c
-+++ b/net/ipv6/ndisc.c
-@@ -649,6 +649,7 @@ void ndisc_send_ns(struct net_device *de
- 
- 	ndisc_send_skb(skb, daddr, saddr);
- }
-+EXPORT_SYMBOL(ndisc_send_ns);
- 
- void ndisc_send_rs(struct net_device *dev, const struct in6_addr *saddr,
- 		   const struct in6_addr *daddr)
---- a/net/ipv6/route.c
-+++ b/net/ipv6/route.c
-@@ -3784,6 +3784,9 @@ out_free:
- 	return ERR_PTR(err);
- }
- 
-+/* Define route change notification chain. */
-+ATOMIC_NOTIFIER_HEAD(ip6route_chain);	/* QCA NSS ECM support */
-+
- int ip6_route_add(struct fib6_config *cfg, gfp_t gfp_flags,
- 		  struct netlink_ext_ack *extack)
- {
-@@ -3795,6 +3798,10 @@ int ip6_route_add(struct fib6_config *cf
- 		return PTR_ERR(rt);
- 
- 	err = __ip6_ins_rt(rt, &cfg->fc_nlinfo, extack);
-+	if (!err)
-+		atomic_notifier_call_chain(&ip6route_chain,
-+					   RTM_NEWROUTE, rt);
-+
- 	fib6_info_release(rt);
- 
- 	return err;
-@@ -3816,6 +3823,9 @@ static int __ip6_del_rt(struct fib6_info
- 	err = fib6_del(rt, info);
- 	spin_unlock_bh(&table->tb6_lock);
- 
-+	if (!err)
-+		atomic_notifier_call_chain(&ip6route_chain,
-+					   RTM_DELROUTE, rt);
- out:
- 	fib6_info_release(rt);
- 	return err;
-@@ -6144,6 +6154,20 @@ static int ip6_route_dev_notify(struct n
- 	return NOTIFY_OK;
- }
- 
-+/* QCA NSS ECM support - Start */
-+int rt6_register_notifier(struct notifier_block *nb)
-+{
-+	return atomic_notifier_chain_register(&ip6route_chain, nb);
-+}
-+EXPORT_SYMBOL(rt6_register_notifier);
-+
-+int rt6_unregister_notifier(struct notifier_block *nb)
-+{
-+	return atomic_notifier_chain_unregister(&ip6route_chain, nb);
-+}
-+EXPORT_SYMBOL(rt6_unregister_notifier);
-+/* QCA NSS ECM support - End */
-+
- /*
-  *	/proc
-  */
---- a/net/l2tp/l2tp_ppp.c
-+++ b/net/l2tp/l2tp_ppp.c
-@@ -92,6 +92,7 @@
- #include <net/ip.h>
- #include <net/udp.h>
- #include <net/inet_common.h>
-+#include <linux/if_pppox.h>
- 
- #include <asm/byteorder.h>
- #include <linux/atomic.h>
-@@ -125,9 +126,19 @@ struct pppol2tp_session {
- 
- static int pppol2tp_xmit(struct ppp_channel *chan, struct sk_buff *skb);
- 
--static const struct ppp_channel_ops pppol2tp_chan_ops = {
--	.start_xmit =  pppol2tp_xmit,
-+/* QCA NSS ECM support - Start */
-+static int pppol2tp_get_channel_protocol(struct ppp_channel *);
-+static int pppol2tp_get_channel_protocol_ver(struct ppp_channel *);
-+static void pppol2tp_hold_chan(struct ppp_channel *);
-+static void pppol2tp_release_chan(struct ppp_channel *);
-+static const struct pppol2tp_channel_ops pppol2tp_chan_ops = {
-+	.ops.start_xmit =  pppol2tp_xmit,
-+	.ops.get_channel_protocol = pppol2tp_get_channel_protocol,
-+	.ops.get_channel_protocol_ver = pppol2tp_get_channel_protocol_ver,
-+	.ops.hold = pppol2tp_hold_chan,
-+	.ops.release = pppol2tp_release_chan,
- };
-+/* QCA NSS ECM support - End */
- 
- static const struct proto_ops pppol2tp_ops;
- 
-@@ -240,6 +251,7 @@ static void pppol2tp_recv(struct l2tp_se
- 			 session->name, data_len);
- 
- 		po = pppox_sk(sk);
-+		skb->skb_iif = ppp_dev_index(&po->chan); /* QCA NSS ECM support */
- 		ppp_input(&po->chan, skb);
- 	} else {
- 		l2tp_dbg(session, L2TP_MSG_DATA,
-@@ -380,6 +392,13 @@ static int pppol2tp_xmit(struct ppp_chan
- 	skb->data[0] = PPP_ALLSTATIONS;
- 	skb->data[1] = PPP_UI;
- 
-+	/* QCA NSS ECM support - start */
-+	/* set incoming interface as the ppp interface */
-+	if ((skb->protocol == htons(ETH_P_IP)) ||
-+	    (skb->protocol == htons(ETH_P_IPV6)))
-+		skb->skb_iif = ppp_dev_index(chan);
-+	/* QCA NSS ECM support - End */
-+
- 	local_bh_disable();
- 	l2tp_xmit_skb(session, skb, session->hdr_len);
- 	local_bh_enable();
-@@ -816,7 +835,7 @@ static int pppol2tp_connect(struct socke
- 	po->chan.hdrlen = PPPOL2TP_L2TP_HDR_SIZE_NOSEQ;
- 
- 	po->chan.private = sk;
--	po->chan.ops	 = &pppol2tp_chan_ops;
-+	po->chan.ops	 = &pppol2tp_chan_ops.ops; /* QCA NSS ECM support */
- 	po->chan.mtu	 = pppol2tp_tunnel_mtu(tunnel);
- 
- 	error = ppp_register_net_channel(sock_net(sk), &po->chan);
-@@ -1749,6 +1768,109 @@ static void __exit pppol2tp_exit(void)
- 	unregister_pernet_device(&pppol2tp_net_ops);
- }
- 
-+/* QCA NSS ECM support - Start */
-+/* pppol2tp_hold_chan() */
-+static void pppol2tp_hold_chan(struct ppp_channel *chan)
-+{
-+	struct sock *sk = (struct sock *)chan->private;
-+
-+	sock_hold(sk);
-+}
-+
-+/* pppol2tp_release_chan() */
-+static void pppol2tp_release_chan(struct ppp_channel *chan)
-+{
-+	struct sock *sk = (struct sock *)chan->private;
-+
-+	sock_put(sk);
-+}
-+
-+/* pppol2tp_get_channel_protocol()
-+ * Return the protocol type of the L2TP over PPP protocol
-+ */
-+static int pppol2tp_get_channel_protocol(struct ppp_channel *chan)
-+{
-+	return PX_PROTO_OL2TP;
-+}
-+
-+/* pppol2tp_get_channel_protocol_ver()
-+ * Return the protocol version of the L2TP over PPP protocol
-+ */
-+static int pppol2tp_get_channel_protocol_ver(struct ppp_channel *chan)
-+{
-+	struct sock *sk;
-+	struct l2tp_session *session;
-+	struct l2tp_tunnel *tunnel;
-+	int version = 0;
-+
-+	if (chan && chan->private)
-+		sk = (struct sock *)chan->private;
-+	else
-+		return -1;
-+
-+	/* Get session and tunnel contexts from the socket */
-+	session = pppol2tp_sock_to_session(sk);
-+	if (!session)
-+		return -1;
-+
-+	tunnel = session->tunnel;
-+	if (!tunnel) {
-+		sock_put(sk);
-+		return -1;
-+	}
-+
-+	version = tunnel->version;
-+
-+	sock_put(sk);
-+
-+	return version;
-+}
-+
-+/* pppol2tp_get_addressing() */
-+static int pppol2tp_get_addressing(struct ppp_channel *chan,
-+				   struct pppol2tp_common_addr *addr)
-+{
-+	struct sock *sk = (struct sock *)chan->private;
-+	struct l2tp_session *session;
-+	struct l2tp_tunnel *tunnel;
-+	struct inet_sock *isk = NULL;
-+	int err = -ENXIO;
-+
-+	/* Get session and tunnel contexts from the socket */
-+	session = pppol2tp_sock_to_session(sk);
-+	if (!session)
-+		return err;
-+
-+	tunnel = session->tunnel;
-+	if (!tunnel) {
-+		sock_put(sk);
-+		return err;
-+	}
-+	isk = inet_sk(tunnel->sock);
-+
-+	addr->local_tunnel_id = tunnel->tunnel_id;
-+	addr->remote_tunnel_id = tunnel->peer_tunnel_id;
-+	addr->local_session_id = session->session_id;
-+	addr->remote_session_id = session->peer_session_id;
-+
-+	addr->local_addr.sin_port = isk->inet_sport;
-+	addr->remote_addr.sin_port = isk->inet_dport;
-+	addr->local_addr.sin_addr.s_addr = isk->inet_saddr;
-+	addr->remote_addr.sin_addr.s_addr = isk->inet_daddr;
-+
-+	sock_put(sk);
-+	return 0;
-+}
-+
-+/* pppol2tp_channel_addressing_get() */
-+int pppol2tp_channel_addressing_get(struct ppp_channel *chan,
-+				    struct pppol2tp_common_addr *addr)
-+{
-+	return pppol2tp_get_addressing(chan, addr);
-+}
-+EXPORT_SYMBOL(pppol2tp_channel_addressing_get);
-+/* QCA NSS ECM support - End */
-+
- module_init(pppol2tp_init);
- module_exit(pppol2tp_exit);
- 
---- a/net/netfilter/Kconfig
-+++ b/net/netfilter/Kconfig
-@@ -135,6 +135,13 @@ config NF_CONNTRACK_EVENTS
- 
- 	  If unsure, say `N'.
- 
-+config NF_CONNTRACK_DSCPREMARK_EXT
-+	bool  'Connection tracking extension for dscp remark target'
-+	depends on NETFILTER_ADVANCED
-+	help
-+	  This option enables support for connection tracking extension
-+	  for dscp remark.
-+
- config NF_CONNTRACK_CHAIN_EVENTS
- 	bool "Register multiple callbacks to ct events"
- 	depends on NF_CONNTRACK_EVENTS
---- a/net/netfilter/Makefile
-+++ b/net/netfilter/Makefile
-@@ -14,6 +14,7 @@ nf_conntrack-$(CONFIG_NF_CONNTRACK_LABEL
- nf_conntrack-$(CONFIG_NF_CT_PROTO_DCCP) += nf_conntrack_proto_dccp.o
- nf_conntrack-$(CONFIG_NF_CT_PROTO_SCTP) += nf_conntrack_proto_sctp.o
- nf_conntrack-$(CONFIG_NF_CT_PROTO_GRE) += nf_conntrack_proto_gre.o
-+nf_conntrack-$(CONFIG_NF_CONNTRACK_DSCPREMARK_EXT) += nf_conntrack_dscpremark_ext.o
- 
- obj-$(CONFIG_NETFILTER) = netfilter.o
- 
diff --git a/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch b/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch
deleted file mode 100644
index 91c308187b279c..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch
+++ /dev/null
@@ -1,141 +0,0 @@
---- a/include/linux/if_bridge.h
-+++ b/include/linux/if_bridge.h
-@@ -54,6 +54,7 @@ extern void brioctl_set(int (*ioctl_hook
- 
- extern void br_dev_update_stats(struct net_device *dev,
- 				struct rtnl_link_stats64 *nlstats);
-+extern bool br_is_hairpin_enabled(struct net_device *dev);
- 
- #if IS_ENABLED(CONFIG_BRIDGE) && IS_ENABLED(CONFIG_BRIDGE_IGMP_SNOOPING)
- int br_multicast_list_adjacent(struct net_device *dev,
-@@ -174,6 +175,8 @@ struct br_fdb_event {
- 	struct net_device *dev;
- 	unsigned char      addr[6];
- 	unsigned char      is_local;
-+	struct net_bridge *br;
-+	struct net_device *orig_dev;
- };
- extern void br_fdb_register_notify(struct notifier_block *nb);
- extern void br_fdb_unregister_notify(struct notifier_block *nb);
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -1665,12 +1665,18 @@ enum netdev_priv_qca_ecm_flags {
- 	IFF_QCA_ECM_PPP_L2TPV2		= 1<<1,
- 	IFF_QCA_ECM_PPP_L2TPV3		= 1<<2,
- 	IFF_QCA_ECM_PPP_PPTP		= 1<<3,
-+	IFF_QCA_ECM_GRE_V4_TAP		= 1<<4,
-+	IFF_QCA_ECM_GRE_V6_TAP		= 1<<5,
-+	IFF_QCA_ECM_IFB			= 1<<6,
- };
- 
- #define IFF_QCA_ECM_TUN_TAP		IFF_QCA_ECM_TUN_TAP
- #define IFF_QCA_ECM_PPP_L2TPV2		IFF_QCA_ECM_PPP_L2TPV2
- #define IFF_QCA_ECM_PPP_L2TPV3		IFF_QCA_ECM_PPP_L2TPV3
- #define IFF_QCA_ECM_PPP_PPTP		IFF_QCA_ECM_PPP_PPTP
-+#define IFF_QCA_ECM_GRE_V4_TAP		IFF_QCA_ECM_GRE_V4_TAP
-+#define	IFF_QCA_ECM_GRE_V6_TAP		IFF_QCA_ECM_GRE_V6_TAP
-+#define	IFF_QCA_ECM_IFB			IFF_QCA_ECM_IFB
- /* QCA NSS ECM support - End */
- 
- /**
---- a/include/linux/netfilter/nf_conntrack_proto_gre.h
-+++ b/include/linux/netfilter/nf_conntrack_proto_gre.h
-@@ -31,4 +31,35 @@ void nf_ct_gre_keymap_destroy(struct nf_
- 
- bool gre_pkt_to_tuple(const struct sk_buff *skb, unsigned int dataoff,
- 		      struct net *net, struct nf_conntrack_tuple *tuple);
-+
-+/* QCA NSS ECM Support - Start */
-+/* GRE is a mess: Four different standards */
-+struct gre_hdr {
-+#if defined(__LITTLE_ENDIAN_BITFIELD)
-+	__u16	rec:3,
-+		srr:1,
-+		seq:1,
-+		key:1,
-+		routing:1,
-+		csum:1,
-+		version:3,
-+		reserved:4,
-+		ack:1;
-+#elif defined(__BIG_ENDIAN_BITFIELD)
-+	__u16	csum:1,
-+		routing:1,
-+		key:1,
-+		seq:1,
-+		srr:1,
-+		rec:3,
-+		ack:1,
-+		reserved:4,
-+		version:3;
-+#else
-+#error "Adjust your <asm/byteorder.h> defines"
-+#endif
-+	__be16	protocol;
-+};
-+/* QCA NSS ECM Support - End */
-+
- #endif /* _CONNTRACK_PROTO_GRE_H */
---- a/include/net/addrconf.h
-+++ b/include/net/addrconf.h
-@@ -508,4 +508,9 @@ int if6_proc_init(void);
- void if6_proc_exit(void);
- #endif
- 
-+/* QCA NSS ECM support - Start */
-+struct net_device *ipv6_dev_find(struct net *net, struct in6_addr *addr,
-+				 int strict);
-+/* QCA NSS ECM support - End */
-+
- #endif
---- a/drivers/net/tun.c
-+++ b/drivers/net/tun.c
-@@ -2853,6 +2853,8 @@ static int tun_set_iff(struct net *net,
- 			return 0;
- 		}
- 
-+		dev->priv_flags_qca_ecm |= IFF_QCA_ECM_TUN_TAP; /* QCA NSS ECM Support */
-+
- 		tun->flags = (tun->flags & ~TUN_FEATURES) |
- 			      (ifr->ifr_flags & TUN_FEATURES);
- 
---- a/net/ipv4/ip_gre.c
-+++ b/net/ipv4/ip_gre.c
-@@ -1305,6 +1305,7 @@ static void ipgre_tap_setup(struct net_d
- 	dev->netdev_ops	= &gre_tap_netdev_ops;
- 	dev->priv_flags &= ~IFF_TX_SKB_SHARING;
- 	dev->priv_flags	|= IFF_LIVE_ADDR_CHANGE;
-+	dev->priv_flags_qca_ecm |= IFF_QCA_ECM_GRE_V4_TAP; /* QCA NSS ECM Support */
- 	ip_tunnel_setup(dev, gre_tap_net_id);
- }
- 
---- a/net/ipv6/ip6_gre.c
-+++ b/net/ipv6/ip6_gre.c
-@@ -1926,6 +1926,7 @@ static void ip6gre_tap_setup(struct net_
- 
- 	dev->priv_flags &= ~IFF_TX_SKB_SHARING;
- 	dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
-+	dev->priv_flags_qca_ecm |= IFF_QCA_ECM_GRE_V6_TAP; /* QCA NSS ECM Support */
- 	netif_keep_dst(dev);
- }
- 
---- a/net/bridge/br_if.c
-+++ b/net/bridge/br_if.c
-@@ -797,6 +797,17 @@ void br_dev_update_stats(struct net_devi
- EXPORT_SYMBOL_GPL(br_dev_update_stats);
- 
- /* QCA NSS ECM support - Start */
-+/* API to know if hairpin feature is enabled/disabled on this bridge port */
-+bool br_is_hairpin_enabled(struct net_device *dev)
-+{
-+	struct net_bridge_port *port = br_port_get_check_rcu(dev);
-+
-+	if (likely(port))
-+		return port->flags & BR_HAIRPIN_MODE;
-+	return false;
-+}
-+EXPORT_SYMBOL_GPL(br_is_hairpin_enabled);
-+
- /* br_port_dev_get()
-  *      If a skb is provided, and the br_port_dev_get_hook_t hook exists,
-  *      use that to try and determine the egress port for that skb.
diff --git a/target/linux/ipq806x/patches-5.4/999-03c-qca-nss-pppoe-offload-support.patch b/target/linux/ipq806x/patches-5.4/999-03c-qca-nss-pppoe-offload-support.patch
deleted file mode 100644
index 0d6a070a7f3f3a..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-03c-qca-nss-pppoe-offload-support.patch
+++ /dev/null
@@ -1,437 +0,0 @@
-From 5f3ab2b6d1a6cadc1b7c231cefdf91b14972e436 Mon Sep 17 00:00:00 2001
-From: Murat Sezgin <msezgin@codeaurora.org>
-Date: Fri, 16 Jan 2015 15:28:47 -0800
-Subject: ppp: PPPoE acceleration support.
-
-Added some new APIs to the PPP/PPPoE kernel modules
-for using from the hardware acceleration connection managers.
-
-Change-Id: I2c16c6d6ccba8ffa14aec077c8dad1681535ae0b
-Signed-off-by: Murat Sezgin <msezgin@codeaurora.org>
----
- drivers/net/ppp/ppp_generic.c | 190 ++++++++++++++++++++++++++++++++++++++++++
- drivers/net/ppp/pppoe.c       |  79 ++++++++++++++++--
- include/linux/if_pppox.h      |  16 +++-
- include/linux/ppp_channel.h   |  38 +++++++++
- 4 files changed, 317 insertions(+), 6 deletions(-)
-
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -1,5 +1,21 @@
- // SPDX-License-Identifier: GPL-2.0-or-later
- /*
-+ **************************************************************************
-+ * Copyright (c) 2016, The Linux Foundation.  All rights reserved.
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ **************************************************************************
-+ */
-+
-+/*
-  * Generic PPP layer for Linux.
-  *
-  * Copyright 1999-2002 Paul Mackerras.
-@@ -3359,6 +3375,178 @@ static void *unit_find(struct idr *p, in
- 	return idr_find(p, n);
- }
- 
-+/* Updates the PPP interface statistics. */
-+void ppp_update_stats(struct net_device *dev, unsigned long rx_packets,
-+		      unsigned long rx_bytes, unsigned long tx_packets,
-+		      unsigned long tx_bytes)
-+{
-+	struct ppp *ppp;
-+
-+	if (!dev)
-+		return;
-+
-+	if (dev->type != ARPHRD_PPP)
-+		return;
-+
-+	ppp = netdev_priv(dev);
-+
-+	ppp_xmit_lock(ppp);
-+	ppp->stats64.tx_packets += tx_packets;
-+	ppp->stats64.tx_bytes += tx_bytes;
-+	ppp_xmit_unlock(ppp);
-+
-+	ppp_recv_lock(ppp);
-+	ppp->stats64.rx_packets += rx_packets;
-+	ppp->stats64.rx_bytes += rx_bytes;
-+	ppp_recv_unlock(ppp);
-+}
-+
-+/* Returns >0 if the device is a multilink PPP netdevice, 0 if not or < 0 if
-+ * the device is not PPP.
-+ */
-+int ppp_is_multilink(struct net_device *dev)
-+{
-+	struct ppp *ppp;
-+	unsigned int flags;
-+
-+	if (!dev)
-+		return -1;
-+
-+	if (dev->type != ARPHRD_PPP)
-+		return -1;
-+
-+	ppp = netdev_priv(dev);
-+	ppp_lock(ppp);
-+	flags = ppp->flags;
-+	ppp_unlock(ppp);
-+
-+	if (flags & SC_MULTILINK)
-+		return 1;
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ppp_is_multilink);
-+
-+/* ppp_channel_get_protocol()
-+ *	Call this to obtain the underlying protocol of the PPP channel,
-+ *	e.g. PX_PROTO_OE
-+ *
-+ * NOTE: Some channels do not use PX sockets so the protocol value may be very
-+ * different for them.
-+ * NOTE: -1 indicates failure.
-+ * NOTE: Once you know the channel protocol you may then either cast 'chan' to
-+ * its sub-class or use the channel protocol specific API's as provided by that
-+ * channel sub type.
-+ */
-+int ppp_channel_get_protocol(struct ppp_channel *chan)
-+{
-+	if (!chan->ops->get_channel_protocol)
-+		return -1;
-+
-+	return chan->ops->get_channel_protocol(chan);
-+}
-+EXPORT_SYMBOL(ppp_channel_get_protocol);
-+
-+/* ppp_channel_hold()
-+ *	Call this to hold a channel.
-+ *
-+ * Returns true on success or false if the hold could not happen.
-+ *
-+ * NOTE: chan must be protected against destruction during this call -
-+ * either by correct locking etc. or because you already have an implicit
-+ * or explicit hold to the channel already and this is an additional hold.
-+ */
-+bool ppp_channel_hold(struct ppp_channel *chan)
-+{
-+	if (!chan->ops->hold)
-+		return false;
-+
-+	chan->ops->hold(chan);
-+	return true;
-+}
-+EXPORT_SYMBOL(ppp_channel_hold);
-+
-+/* ppp_channel_release()
-+ *	Call this to release a hold you have upon a channel
-+ */
-+void ppp_channel_release(struct ppp_channel *chan)
-+{
-+	chan->ops->release(chan);
-+}
-+EXPORT_SYMBOL(ppp_channel_release);
-+
-+/* ppp_hold_channels()
-+ *	Returns the PPP channels of the PPP device, storing each one into
-+ *	channels[].
-+ *
-+ * channels[] has chan_sz elements.
-+ * This function returns the number of channels stored, up to chan_sz.
-+ * It will return < 0 if the device is not PPP.
-+ *
-+ * You MUST release the channels using ppp_release_channels().
-+ */
-+int ppp_hold_channels(struct net_device *dev, struct ppp_channel *channels[],
-+		      unsigned int chan_sz)
-+{
-+	struct ppp *ppp;
-+	int c;
-+	struct channel *pch;
-+
-+	if (!dev)
-+		return -1;
-+
-+	if (dev->type != ARPHRD_PPP)
-+		return -1;
-+
-+	ppp = netdev_priv(dev);
-+
-+	c = 0;
-+	ppp_lock(ppp);
-+	list_for_each_entry(pch, &ppp->channels, clist) {
-+		struct ppp_channel *chan;
-+
-+		if (!pch->chan) {
-+			/* Channel is going / gone away */
-+			continue;
-+		}
-+
-+		if (c == chan_sz) {
-+			/* No space to record channel */
-+			ppp_unlock(ppp);
-+			return c;
-+		}
-+
-+		/* Hold the channel, if supported */
-+		chan = pch->chan;
-+		if (!chan->ops->hold)
-+			continue;
-+
-+		chan->ops->hold(chan);
-+
-+		 /* Record the channel */
-+		channels[c++] = chan;
-+	}
-+	ppp_unlock(ppp);
-+	return c;
-+}
-+EXPORT_SYMBOL(ppp_hold_channels);
-+
-+/* ppp_release_channels()
-+ *	Releases channels
-+ */
-+void ppp_release_channels(struct ppp_channel *channels[], unsigned int chan_sz)
-+{
-+	unsigned int c;
-+
-+	for (c = 0; c < chan_sz; ++c) {
-+		struct ppp_channel *chan;
-+
-+		chan = channels[c];
-+		chan->ops->release(chan);
-+	}
-+}
-+EXPORT_SYMBOL(ppp_release_channels);
-+
- /* Module/initialization stuff */
- 
- module_init(ppp_init);
-@@ -3375,6 +3563,8 @@ EXPORT_SYMBOL(ppp_input_error);
- EXPORT_SYMBOL(ppp_output_wakeup);
- EXPORT_SYMBOL(ppp_register_compressor);
- EXPORT_SYMBOL(ppp_unregister_compressor);
-+EXPORT_SYMBOL(ppp_update_stats);
-+
- MODULE_LICENSE("GPL");
- MODULE_ALIAS_CHARDEV(PPP_MAJOR, 0);
- MODULE_ALIAS_RTNL_LINK("ppp");
---- a/drivers/net/ppp/pppoe.c
-+++ b/drivers/net/ppp/pppoe.c
-@@ -62,6 +62,7 @@
- #include <linux/inetdevice.h>
- #include <linux/etherdevice.h>
- #include <linux/skbuff.h>
-+#include <linux/if_arp.h>
- #include <linux/init.h>
- #include <linux/if_ether.h>
- #include <linux/if_pppox.h>
-@@ -92,7 +93,7 @@
- static int __pppoe_xmit(struct sock *sk, struct sk_buff *skb);
- 
- static const struct proto_ops pppoe_ops;
--static const struct ppp_channel_ops pppoe_chan_ops;
-+static const struct pppoe_channel_ops pppoe_chan_ops;
- 
- /* per-net private data for this module */
- static unsigned int pppoe_net_id __read_mostly;
-@@ -652,6 +653,7 @@ static int pppoe_connect(struct socket *
- 	if (stage_session(po->pppoe_pa.sid)) {
- 		pppox_unbind_sock(sk);
- 		pn = pppoe_pernet(sock_net(sk));
-+
- 		delete_item(pn, po->pppoe_pa.sid,
- 			    po->pppoe_pa.remote, po->pppoe_ifindex);
- 		if (po->pppoe_dev) {
-@@ -699,7 +701,7 @@ static int pppoe_connect(struct socket *
- 
- 		po->chan.mtu = dev->mtu - sizeof(struct pppoe_hdr) - 2;
- 		po->chan.private = sk;
--		po->chan.ops = &pppoe_chan_ops;
-+		po->chan.ops = (struct ppp_channel_ops *)&pppoe_chan_ops;
- 
- 		error = ppp_register_net_channel(dev_net(dev), &po->chan);
- 		if (error) {
-@@ -1004,11 +1006,78 @@ static int pppoe_flow_offload_check(stru
- }
- #endif /* CONFIG_NF_FLOW_TABLE */
- 
--static const struct ppp_channel_ops pppoe_chan_ops = {
--	.start_xmit = pppoe_xmit,
-+/************************************************************************
-+ *
-+ * function called by generic PPP driver to hold channel
-+ *
-+ ***********************************************************************/
-+static void pppoe_hold_chan(struct ppp_channel *chan)
-+{
-+	struct sock *sk = (struct sock *)chan->private;
-+
-+	sock_hold(sk);
-+}
-+
-+/************************************************************************
-+ *
-+ * function called by generic PPP driver to release channel
-+ *
-+ ***********************************************************************/
-+static void pppoe_release_chan(struct ppp_channel *chan)
-+{
-+	struct sock *sk = (struct sock *)chan->private;
-+
-+	sock_put(sk);
-+}
-+
-+/************************************************************************
-+ *
-+ * function called to get the channel protocol type
-+ *
-+ ***********************************************************************/
-+static int pppoe_get_channel_protocol(struct ppp_channel *chan)
-+{
-+	return PX_PROTO_OE;
-+}
-+
-+/************************************************************************
-+ *
-+ * function called to get the PPPoE channel addressing
-+ * NOTE: This function returns a HOLD to the netdevice
-+ *
-+ ***********************************************************************/
-+static void pppoe_get_addressing(struct ppp_channel *chan,
-+				 struct pppoe_opt *addressing)
-+{
-+	struct sock *sk = (struct sock *)chan->private;
-+	struct pppox_sock *po = pppox_sk(sk);
-+
-+	*addressing = po->proto.pppoe;
-+	if (addressing->dev)
-+		dev_hold(addressing->dev);
-+}
-+
-+/* pppoe_channel_addressing_get()
-+ *	Return PPPoE channel specific addressing information.
-+ */
-+void pppoe_channel_addressing_get(struct ppp_channel *chan,
-+				  struct pppoe_opt *addressing)
-+{
-+	pppoe_get_addressing(chan, addressing);
-+}
-+EXPORT_SYMBOL(pppoe_channel_addressing_get);
-+
-+static const struct pppoe_channel_ops pppoe_chan_ops = {
-+	/* PPPoE specific channel ops */
-+	.get_addressing = pppoe_get_addressing,
-+	/* General ppp channel ops */
-+	.ops.start_xmit = pppoe_xmit,
- #if IS_ENABLED(CONFIG_NF_FLOW_TABLE)
--	.flow_offload_check = pppoe_flow_offload_check,
-+	.ops.flow_offload_check = pppoe_flow_offload_check,
- #endif
-+	.ops.get_channel_protocol = pppoe_get_channel_protocol,
-+	.ops.hold = pppoe_hold_chan,
-+	.ops.release = pppoe_release_chan,
- };
- 
- static int pppoe_recvmsg(struct socket *sock, struct msghdr *m,
---- a/include/linux/if_pppox.h
-+++ b/include/linux/if_pppox.h
-@@ -1,13 +1,14 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- /***************************************************************************
-  * Linux PPP over X - Generic PPP transport layer sockets
-- * Linux PPP over Ethernet (PPPoE) Socket Implementation (RFC 2516) 
-+ * Linux PPP over Ethernet (PPPoE) Socket Implementation (RFC 2516)
-  *
-  * This file supplies definitions required by the PPP over Ethernet driver
-  * (pppox.c).  All version information wrt this file is located in pppox.c
-  *
-  * License:
-  */
-+
- #ifndef __LINUX_IF_PPPOX_H
- #define __LINUX_IF_PPPOX_H
- 
-@@ -93,4 +94,17 @@ enum {
-     PPPOX_DEAD		= 16  /* dead, useless, please clean me up!*/
- };
- 
-+/*
-+ * PPPoE Channel specific operations
-+ */
-+struct pppoe_channel_ops {
-+	/* Must be first - general to all PPP channels */
-+	struct ppp_channel_ops ops;
-+	void (*get_addressing)(struct ppp_channel *, struct pppoe_opt *);
-+};
-+
-+/* Return PPPoE channel specific addressing information */
-+extern void pppoe_channel_addressing_get(struct ppp_channel *chan,
-+					 struct pppoe_opt *addressing);
-+
- #endif /* !(__LINUX_IF_PPPOX_H) */
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -32,6 +32,14 @@ struct ppp_channel_ops {
- #if IS_ENABLED(CONFIG_NF_FLOW_TABLE)
- 	int	(*flow_offload_check)(struct ppp_channel *, struct flow_offload_hw_path *);
- #endif
-+	/* Get channel protocol type, one of PX_PROTO_XYZ or specific to
-+	 * the channel subtype
-+	 */
-+	int (*get_channel_protocol)(struct ppp_channel *);
-+	/* Hold the channel from being destroyed */
-+	void (*hold)(struct ppp_channel *);
-+	/* Release hold on the channel */
-+	void (*release)(struct ppp_channel *);
- };
- 
- struct ppp_channel {
-@@ -46,6 +54,36 @@ struct ppp_channel {
- };
- 
- #ifdef __KERNEL__
-+/* Call this to obtain the underlying protocol of the PPP channel,
-+ * e.g. PX_PROTO_OE
-+ */
-+extern int ppp_channel_get_protocol(struct ppp_channel *);
-+
-+/* Call this to hold a channel */
-+extern bool ppp_channel_hold(struct ppp_channel *);
-+
-+/* Call this to release a hold you have upon a channel */
-+extern void ppp_channel_release(struct ppp_channel *);
-+
-+/* Release hold on PPP channels */
-+extern void ppp_release_channels(struct ppp_channel *channels[],
-+				 unsigned int chan_sz);
-+
-+/* Hold PPP channels for the PPP device */
-+extern int ppp_hold_channels(struct net_device *dev,
-+			     struct ppp_channel *channels[],
-+			     unsigned int chan_sz);
-+
-+/* Test if the ppp device is a multi-link ppp device */
-+extern int ppp_is_multilink(struct net_device *dev);
-+
-+/* Update statistics of the PPP net_device by incrementing related
-+ * statistics field value with corresponding parameter
-+ */
-+extern void ppp_update_stats(struct net_device *dev, unsigned long rx_packets,
-+			     unsigned long rx_bytes, unsigned long tx_packets,
-+			     unsigned long tx_bytes);
-+
- /* Called by the channel when it can send some more data. */
- extern void ppp_output_wakeup(struct ppp_channel *);
- 
diff --git a/target/linux/ipq806x/patches-5.4/999-03d-qca-nss-pppoe-offload-support.patch b/target/linux/ipq806x/patches-5.4/999-03d-qca-nss-pppoe-offload-support.patch
deleted file mode 100644
index e540fe9ee778c8..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-03d-qca-nss-pppoe-offload-support.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 4df2e1c28e8e3baadd50bdafa40fb35ea99cc52f Mon Sep 17 00:00:00 2001
-From: Murat Sezgin <msezgin@codeaurora.org>
-Date: Fri, 26 Feb 2016 14:59:20 -0800
-Subject: net: ppp: rx/tx error and dropped pkt stats support
-
-ppp_update_stats functions accepts rx/tx errors and dropped
-pkt stats args.
-
-Change-Id: Iba2f6ea2114d8a4678254332fec0ef7bc35bed2c
-Signed-off-by: ratheesh kannoth <rkannoth@codeaurora.org>
-Signed-off-by: Murat Sezgin <msezgin@codeaurora.org>
----
- drivers/net/ppp/ppp_generic.c |  8 +++++++-
- include/linux/ppp_channel.h   |  4 +++-
- net/l2tp/l2tp_core.c          | 24 ++++++++++++++++++++++++
- net/l2tp/l2tp_core.h          |  2 ++
- 4 files changed, 36 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -3378,7 +3378,9 @@ static void *unit_find(struct idr *p, in
- /* Updates the PPP interface statistics. */
- void ppp_update_stats(struct net_device *dev, unsigned long rx_packets,
- 		      unsigned long rx_bytes, unsigned long tx_packets,
--		      unsigned long tx_bytes)
-+		      unsigned long tx_bytes, unsigned long rx_errors,
-+		      unsigned long tx_errors, unsigned long rx_dropped,
-+		      unsigned long tx_dropped)
- {
- 	struct ppp *ppp;
- 
-@@ -3393,11 +3395,15 @@ void ppp_update_stats(struct net_device
- 	ppp_xmit_lock(ppp);
- 	ppp->stats64.tx_packets += tx_packets;
- 	ppp->stats64.tx_bytes += tx_bytes;
-+	ppp->dev->stats.tx_errors += tx_errors;
-+	ppp->dev->stats.tx_dropped += tx_dropped;
- 	ppp_xmit_unlock(ppp);
- 
- 	ppp_recv_lock(ppp);
- 	ppp->stats64.rx_packets += rx_packets;
- 	ppp->stats64.rx_bytes += rx_bytes;
-+	ppp->dev->stats.rx_errors += rx_errors;
-+	ppp->dev->stats.rx_dropped += rx_dropped;
- 	ppp_recv_unlock(ppp);
- }
- 
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -82,7 +82,9 @@ extern int ppp_is_multilink(struct net_d
-  */
- extern void ppp_update_stats(struct net_device *dev, unsigned long rx_packets,
- 			     unsigned long rx_bytes, unsigned long tx_packets,
--			     unsigned long tx_bytes);
-+			     unsigned long tx_bytes, unsigned long rx_errors,
-+			     unsigned long tx_errors, unsigned long rx_dropped,
-+			     unsigned long tx_dropped);
- 
- /* Called by the channel when it can send some more data. */
- extern void ppp_output_wakeup(struct ppp_channel *);
---- a/net/l2tp/l2tp_core.c
-+++ b/net/l2tp/l2tp_core.c
-@@ -355,6 +355,30 @@ err_tlock:
- }
- EXPORT_SYMBOL_GPL(l2tp_session_register);
- 
-+void l2tp_stats_update(struct l2tp_tunnel *tunnel,
-+		       struct l2tp_session *session,
-+		       struct l2tp_stats *stats)
-+{
-+	atomic_long_add(atomic_long_read(&stats->rx_packets),
-+			&tunnel->stats.rx_packets);
-+	atomic_long_add(atomic_long_read(&stats->rx_bytes),
-+			&tunnel->stats.rx_bytes);
-+	atomic_long_add(atomic_long_read(&stats->tx_packets),
-+			&tunnel->stats.tx_packets);
-+	atomic_long_add(atomic_long_read(&stats->tx_bytes),
-+			&tunnel->stats.tx_bytes);
-+
-+	atomic_long_add(atomic_long_read(&stats->rx_packets),
-+			&session->stats.rx_packets);
-+	atomic_long_add(atomic_long_read(&stats->rx_bytes),
-+			&session->stats.rx_bytes);
-+	atomic_long_add(atomic_long_read(&stats->tx_packets),
-+			&session->stats.tx_packets);
-+	atomic_long_add(atomic_long_read(&stats->tx_bytes),
-+			&session->stats.tx_bytes);
-+}
-+EXPORT_SYMBOL_GPL(l2tp_stats_update);
-+
- /*****************************************************************************
-  * Receive data handling
-  *****************************************************************************/
---- a/net/l2tp/l2tp_core.h
-+++ b/net/l2tp/l2tp_core.h
-@@ -200,6 +200,8 @@ struct l2tp_session *l2tp_session_get(co
- struct l2tp_session *l2tp_session_get_nth(struct l2tp_tunnel *tunnel, int nth);
- struct l2tp_session *l2tp_session_get_by_ifname(const struct net *net,
- 						const char *ifname);
-+void l2tp_stats_update(struct l2tp_tunnel *tunnel, struct l2tp_session *session,
-+		       struct l2tp_stats *stats);
- 
- int l2tp_tunnel_create(struct net *net, int fd, int version, u32 tunnel_id,
- 		       u32 peer_tunnel_id, struct l2tp_tunnel_cfg *cfg,
diff --git a/target/linux/ipq806x/patches-5.4/999-03e-qca-nss-pppoe-offload-support.patch b/target/linux/ipq806x/patches-5.4/999-03e-qca-nss-pppoe-offload-support.patch
deleted file mode 100644
index 0ed05d6028dde8..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-03e-qca-nss-pppoe-offload-support.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 0ebfa720350a5fde3efb45872f867ac30074a43c Mon Sep 17 00:00:00 2001
-From: Murat Sezgin <msezgin@codeaurora.org>
-Date: Tue, 13 Oct 2015 22:40:25 -0700
-Subject: ppp: Update the last_recv and last_xmit times.
-
-These need to be updated for accelerated connections, so that
-on demand mode will recognize the active traffic.
-
-Change-Id: I3c0ee4e8f4c3bc4c7ce221e6109bfd82046d11b4
-Signed-off-by: Murat Sezgin <msezgin@codeaurora.org>
----
- drivers/net/ppp/ppp_generic.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -3397,6 +3397,8 @@ void ppp_update_stats(struct net_device
- 	ppp->stats64.tx_bytes += tx_bytes;
- 	ppp->dev->stats.tx_errors += tx_errors;
- 	ppp->dev->stats.tx_dropped += tx_dropped;
-+	if (tx_packets)
-+		ppp->last_xmit = jiffies;
- 	ppp_xmit_unlock(ppp);
- 
- 	ppp_recv_lock(ppp);
-@@ -3404,6 +3406,8 @@ void ppp_update_stats(struct net_device
- 	ppp->stats64.rx_bytes += rx_bytes;
- 	ppp->dev->stats.rx_errors += rx_errors;
- 	ppp->dev->stats.rx_dropped += rx_dropped;
-+	if (rx_packets)
-+		ppp->last_recv = jiffies;
- 	ppp_recv_unlock(ppp);
- }
- 
diff --git a/target/linux/ipq806x/patches-5.4/999-04-qca-nss-cfi-support.patch b/target/linux/ipq806x/patches-5.4/999-04-qca-nss-cfi-support.patch
deleted file mode 100644
index afacf892091d6a..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-04-qca-nss-cfi-support.patch
+++ /dev/null
@@ -1,111 +0,0 @@
---- a/crypto/authenc.c
-+++ b/crypto/authenc.c
-@@ -449,6 +449,8 @@ static int crypto_authenc_create(struct
- 
- 	inst->alg.base.cra_flags = (auth_base->cra_flags |
- 				    enc->base.cra_flags) & CRYPTO_ALG_ASYNC;
-+	inst->alg.base.cra_flags |= (auth_base->cra_flags |
-+				    enc->base.cra_flags) & CRYPTO_ALG_NOSUPP_SG;
- 	inst->alg.base.cra_priority = enc->base.cra_priority * 10 +
- 				      auth_base->cra_priority;
- 	inst->alg.base.cra_blocksize = enc->base.cra_blocksize;
---- a/include/linux/crypto.h
-+++ b/include/linux/crypto.h
-@@ -105,6 +105,11 @@
- #define CRYPTO_NOLOAD			0x00008000
- 
- /*
-+ * Set this flag if algorithm does not support SG list transforms
-+ */
-+#define CRYPTO_ALG_NOSUPP_SG		0x0000c000
-+
-+/*
-  * Transform masks and values (for crt_flags).
-  */
- #define CRYPTO_TFM_NEED_KEY		0x00000001
---- a/net/ipv4/esp4.c
-+++ b/net/ipv4/esp4.c
-@@ -487,6 +487,7 @@ static int esp_output(struct xfrm_state
- 	struct ip_esp_hdr *esph;
- 	struct crypto_aead *aead;
- 	struct esp_info esp;
-+	bool nosupp_sg;
- 
- 	esp.inplace = true;
- 
-@@ -498,6 +499,11 @@ static int esp_output(struct xfrm_state
- 	aead = x->data;
- 	alen = crypto_aead_authsize(aead);
- 
-+	nosupp_sg = crypto_tfm_alg_type(&aead->base) & CRYPTO_ALG_NOSUPP_SG;
-+	if (nosupp_sg && skb_linearize(skb)) {
-+		return -ENOMEM;
-+	}
-+
- 	esp.tfclen = 0;
- 	if (x->tfcpad) {
- 		struct xfrm_dst *dst = (struct xfrm_dst *)skb_dst(skb);
-@@ -709,6 +715,7 @@ static int esp_input(struct xfrm_state *
- 	u8 *iv;
- 	struct scatterlist *sg;
- 	int err = -EINVAL;
-+	bool nosupp_sg;
- 
- 	if (!pskb_may_pull(skb, sizeof(struct ip_esp_hdr) + ivlen))
- 		goto out;
-@@ -716,6 +723,12 @@ static int esp_input(struct xfrm_state *
- 	if (elen <= 0)
- 		goto out;
- 
-+	nosupp_sg = crypto_tfm_alg_type(&aead->base) & CRYPTO_ALG_NOSUPP_SG;
-+	if (nosupp_sg && skb_linearize(skb)) {
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
- 	assoclen = sizeof(struct ip_esp_hdr);
- 	seqhilen = 0;
- 
---- a/net/ipv6/esp6.c
-+++ b/net/ipv6/esp6.c
-@@ -428,6 +428,7 @@ static int esp6_output(struct xfrm_state
- 	struct ip_esp_hdr *esph;
- 	struct crypto_aead *aead;
- 	struct esp_info esp;
-+	bool nosupp_sg;
- 
- 	esp.inplace = true;
- 
-@@ -439,6 +440,11 @@ static int esp6_output(struct xfrm_state
- 	aead = x->data;
- 	alen = crypto_aead_authsize(aead);
- 
-+	nosupp_sg = crypto_tfm_alg_type(&aead->base) & CRYPTO_ALG_NOSUPP_SG;
-+	if (nosupp_sg && skb_linearize(skb)) {
-+		return -ENOMEM;
-+	}
-+
- 	esp.tfclen = 0;
- 	if (x->tfcpad) {
- 		struct xfrm_dst *dst = (struct xfrm_dst *)skb_dst(skb);
-@@ -604,6 +610,7 @@ static int esp6_input(struct xfrm_state
- 	__be32 *seqhi;
- 	u8 *iv;
- 	struct scatterlist *sg;
-+	bool nosupp_sg;
- 
- 	if (!pskb_may_pull(skb, sizeof(struct ip_esp_hdr) + ivlen)) {
- 		ret = -EINVAL;
-@@ -615,6 +622,12 @@ static int esp6_input(struct xfrm_state
- 		goto out;
- 	}
- 
-+	nosupp_sg = crypto_tfm_alg_type(&aead->base) & CRYPTO_ALG_NOSUPP_SG;
-+	if (nosupp_sg && skb_linearize(skb)) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
- 	assoclen = sizeof(struct ip_esp_hdr);
- 	seqhilen = 0;
- 
diff --git a/target/linux/ipq806x/patches-5.4/999-07a-qca-nss-drv-qdisc-support.patch b/target/linux/ipq806x/patches-5.4/999-07a-qca-nss-drv-qdisc-support.patch
deleted file mode 100644
index 7f9896f8737ee5..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-07a-qca-nss-drv-qdisc-support.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -818,6 +818,8 @@ struct sk_buff {
- #ifdef CONFIG_NET_CLS_ACT
- 	__u8			tc_skip_classify:1;
- 	__u8			tc_at_ingress:1;
-+
-+	__u16			tc_verd_qca_nss; /* QCA NSS Qdisc Support */
- #endif
- #ifdef CONFIG_NET_REDIRECT
- 	__u8			redirected:1;
---- a/include/uapi/linux/pkt_cls.h
-+++ b/include/uapi/linux/pkt_cls.h
-@@ -687,4 +687,14 @@ enum {
- 	TCF_EM_OPND_LT
- };
- 
-+/* QCA NSS Qdisc Support - Start */
-+#define _TC_MAKE32(x)		((x))
-+#define _TC_MAKEMASK1(n)	(_TC_MAKE32(1) << _TC_MAKE32(n))
-+
-+#define TC_NCLS                 _TC_MAKEMASK1(8)
-+#define TC_NCLS_NSS		_TC_MAKEMASK1(12)
-+#define SET_TC_NCLS_NSS(v)	( TC_NCLS_NSS | ((v) & ~TC_NCLS_NSS))
-+#define CLR_TC_NCLS_NSS(v)	( (v) & ~TC_NCLS_NSS)
-+/* QCA NSS Qdisc Support - End */
-+
- #endif
diff --git a/target/linux/ipq806x/patches-5.4/999-07b-qca-nss-clients-qdisc-support.patch b/target/linux/ipq806x/patches-5.4/999-07b-qca-nss-clients-qdisc-support.patch
deleted file mode 100644
index bb8beed3d8e89a..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-07b-qca-nss-clients-qdisc-support.patch
+++ /dev/null
@@ -1,319 +0,0 @@
---- a/include/net/sch_generic.h
-+++ b/include/net/sch_generic.h
-@@ -80,6 +80,7 @@ struct Qdisc {
- #define TCQ_F_INVISIBLE		0x80 /* invisible by default in dump */
- #define TCQ_F_NOLOCK		0x100 /* qdisc does not require locking */
- #define TCQ_F_OFFLOADED		0x200 /* qdisc is offloaded to HW */
-+#define TCQ_F_NSS		0x1000 /* NSS qdisc flag. */
- 	u32			limit;
- 	const struct Qdisc_ops	*ops;
- 	struct qdisc_size_table	__rcu *stab;
-@@ -1342,4 +1343,9 @@ static inline void qdisc_synchronize(con
- 		msleep(1);
- }
- 
-+/* QCA NSS Qdisc Support - Start */
-+void qdisc_destroy(struct Qdisc *qdisc);
-+void tcf_destroy_chain(struct tcf_proto __rcu **fl);
-+/* QCA NSS Qdisc Support - End */
-+
- #endif
---- a/include/uapi/linux/pkt_sched.h
-+++ b/include/uapi/linux/pkt_sched.h
-@@ -1183,4 +1183,248 @@ enum {
- 
- #define TCA_TAPRIO_ATTR_MAX (__TCA_TAPRIO_ATTR_MAX - 1)
- 
-+/* QCA NSS Clients Support - Start */
-+enum {
-+	TCA_NSS_ACCEL_MODE_NSS_FW,
-+	TCA_NSS_ACCEL_MODE_PPE,
-+	TCA_NSS_ACCEL_MODE_MAX
-+};
-+
-+/* NSSFIFO section */
-+
-+enum {
-+	TCA_NSSFIFO_UNSPEC,
-+	TCA_NSSFIFO_PARMS,
-+	__TCA_NSSFIFO_MAX
-+};
-+
-+#define TCA_NSSFIFO_MAX	(__TCA_NSSFIFO_MAX - 1)
-+
-+struct tc_nssfifo_qopt {
-+	__u32	limit;		/* Queue length: bytes for bfifo, packets for pfifo */
-+	__u8	set_default;	/* Sets qdisc to be the default qdisc for enqueue */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSWRED section */
-+
-+enum {
-+	TCA_NSSWRED_UNSPEC,
-+	TCA_NSSWRED_PARMS,
-+	__TCA_NSSWRED_MAX
-+};
-+
-+#define TCA_NSSWRED_MAX (__TCA_NSSWRED_MAX - 1)
-+#define NSSWRED_CLASS_MAX 6
-+struct tc_red_alg_parameter {
-+	__u32	min;	/* qlen_avg < min: pkts are all enqueued */
-+	__u32	max;	/* qlen_avg > max: pkts are all dropped */
-+	__u32	probability;/* Drop probability at qlen_avg = max */
-+	__u32	exp_weight_factor;/* exp_weight_factor for calculate qlen_avg */
-+};
-+
-+struct tc_nsswred_traffic_class {
-+	__u32 limit;			/* Queue length */
-+	__u32 weight_mode_value;	/* Weight mode value */
-+	struct tc_red_alg_parameter rap;/* Parameters for RED alg */
-+};
-+
-+/*
-+ * Weight modes for WRED
-+ */
-+enum tc_nsswred_weight_modes {
-+	TC_NSSWRED_WEIGHT_MODE_DSCP = 0,/* Weight mode is DSCP */
-+	TC_NSSWRED_WEIGHT_MODES,	/* Must be last */
-+};
-+
-+struct tc_nsswred_qopt {
-+	__u32	limit;			/* Queue length */
-+	enum tc_nsswred_weight_modes weight_mode;
-+					/* Weight mode */
-+	__u32	traffic_classes;	/* How many traffic classes: DPs */
-+	__u32	def_traffic_class;	/* Default traffic if no match: def_DP */
-+	__u32	traffic_id;		/* The traffic id to be configured: DP */
-+	__u32	weight_mode_value;	/* Weight mode value */
-+	struct tc_red_alg_parameter rap;/* RED algorithm parameters */
-+	struct tc_nsswred_traffic_class tntc[NSSWRED_CLASS_MAX];
-+					/* Traffic settings for dumpping */
-+	__u8	ecn;			/* Setting ECN bit or dropping */
-+	__u8	set_default;		/* Sets qdisc to be the default for enqueue */
-+	__u8	accel_mode;		/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSCODEL section */
-+
-+enum {
-+	TCA_NSSCODEL_UNSPEC,
-+	TCA_NSSCODEL_PARMS,
-+	__TCA_NSSCODEL_MAX
-+};
-+
-+#define TCA_NSSCODEL_MAX	(__TCA_NSSCODEL_MAX - 1)
-+
-+struct tc_nsscodel_qopt {
-+	__u32	target;		/* Acceptable queueing delay */
-+	__u32	limit;		/* Max number of packets that can be held in the queue */
-+	__u32	interval;	/* Monitoring interval */
-+	__u32	flows;		/* Number of flow buckets */
-+	__u32	quantum;	/* Weight (in bytes) used for DRR of flow buckets */
-+	__u8	ecn;		/* 0 - disable ECN, 1 - enable ECN */
-+	__u8	set_default;	/* Sets qdisc to be the default qdisc for enqueue */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+struct tc_nsscodel_xstats {
-+	__u32 peak_queue_delay;	/* Peak delay experienced by a dequeued packet */
-+	__u32 peak_drop_delay;	/* Peak delay experienced by a dropped packet */
-+};
-+
-+/* NSSFQ_CODEL section */
-+
-+struct tc_nssfq_codel_xstats {
-+	__u32 new_flow_count;	/* Total number of new flows seen */
-+	__u32 new_flows_len;	/* Current number of new flows */
-+	__u32 old_flows_len;	/* Current number of old flows */
-+	__u32 ecn_mark;		/* Number of packets marked with ECN */
-+	__u32 drop_overlimit;	/* Number of packets dropped due to overlimit */
-+	__u32 maxpacket;	/* The largest packet seen so far in the queue */
-+};
-+
-+/* NSSTBL section */
-+
-+enum {
-+	TCA_NSSTBL_UNSPEC,
-+	TCA_NSSTBL_PARMS,
-+	__TCA_NSSTBL_MAX
-+};
-+
-+#define TCA_NSSTBL_MAX	(__TCA_NSSTBL_MAX - 1)
-+
-+struct tc_nsstbl_qopt {
-+	__u32	burst;		/* Maximum burst size */
-+	__u32	rate;		/* Limiting rate of TBF */
-+	__u32	peakrate;	/* Maximum rate at which TBF is allowed to send */
-+	__u32	mtu;		/* Max size of packet, or minumim burst size */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSPRIO section */
-+
-+#define TCA_NSSPRIO_MAX_BANDS 256
-+
-+enum {
-+	TCA_NSSPRIO_UNSPEC,
-+	TCA_NSSPRIO_PARMS,
-+	__TCA_NSSPRIO_MAX
-+};
-+
-+#define TCA_NSSPRIO_MAX	(__TCA_NSSPRIO_MAX - 1)
-+
-+struct tc_nssprio_qopt {
-+	__u32	bands;		/* Number of bands */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSBF section */
-+
-+enum {
-+	TCA_NSSBF_UNSPEC,
-+	TCA_NSSBF_CLASS_PARMS,
-+	TCA_NSSBF_QDISC_PARMS,
-+	__TCA_NSSBF_MAX
-+};
-+
-+#define TCA_NSSBF_MAX	(__TCA_NSSBF_MAX - 1)
-+
-+struct tc_nssbf_class_qopt {
-+	__u32	burst;		/* Maximum burst size */
-+	__u32	rate;		/* Allowed bandwidth for this class */
-+	__u32	mtu;		/* MTU of the associated interface */
-+	__u32	quantum;	/* Quantum allocation for DRR */
-+};
-+
-+struct tc_nssbf_qopt {
-+	__u16	defcls;		/* Default class value */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSWRR section */
-+
-+enum {
-+	TCA_NSSWRR_UNSPEC,
-+	TCA_NSSWRR_CLASS_PARMS,
-+	TCA_NSSWRR_QDISC_PARMS,
-+	__TCA_NSSWRR_MAX
-+};
-+
-+#define TCA_NSSWRR_MAX	(__TCA_NSSWRR_MAX - 1)
-+
-+struct tc_nsswrr_class_qopt {
-+	__u32	quantum;	/* Weight associated to this class */
-+};
-+
-+struct tc_nsswrr_qopt {
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSWFQ section */
-+
-+enum {
-+	TCA_NSSWFQ_UNSPEC,
-+	TCA_NSSWFQ_CLASS_PARMS,
-+	TCA_NSSWFQ_QDISC_PARMS,
-+	__TCA_NSSWFQ_MAX
-+};
-+
-+#define TCA_NSSWFQ_MAX	(__TCA_NSSWFQ_MAX - 1)
-+
-+struct tc_nsswfq_class_qopt {
-+	__u32	quantum;	/* Weight associated to this class */
-+};
-+
-+struct tc_nsswfq_qopt {
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSHTB section */
-+
-+enum {
-+	TCA_NSSHTB_UNSPEC,
-+	TCA_NSSHTB_CLASS_PARMS,
-+	TCA_NSSHTB_QDISC_PARMS,
-+	__TCA_NSSHTB_MAX
-+};
-+
-+#define TCA_NSSHTB_MAX	(__TCA_NSSHTB_MAX - 1)
-+
-+struct tc_nsshtb_class_qopt {
-+	__u32	burst;		/* Allowed burst size */
-+	__u32	rate;		/* Allowed bandwidth for this class */
-+	__u32	cburst;		/* Maximum burst size */
-+	__u32	crate;		/* Maximum bandwidth for this class */
-+	__u32	quantum;	/* Quantum allocation for DRR */
-+	__u32	priority;	/* Priority value associated with this class */
-+	__u32	overhead;	/* Overhead in bytes per packet */
-+};
-+
-+struct tc_nsshtb_qopt {
-+	__u32	r2q;		/* Rate to quantum ratio */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+
-+/* NSSBLACKHOLE section */
-+
-+enum {
-+	TCA_NSSBLACKHOLE_UNSPEC,
-+	TCA_NSSBLACKHOLE_PARMS,
-+	__TCA_NSSBLACKHOLE_MAX
-+};
-+
-+#define TCA_NSSBLACKHOLE_MAX	(__TCA_NSSBLACKHOLE_MAX - 1)
-+
-+struct tc_nssblackhole_qopt {
-+	__u8	set_default;	/* Sets qdisc to be the default qdisc for enqueue */
-+	__u8	accel_mode;	/* Dictates which data plane offloads the qdisc */
-+};
-+/* QCA NSS Clients Support - End */
- #endif
---- a/net/sched/sch_api.c
-+++ b/net/sched/sch_api.c
-@@ -2346,4 +2346,26 @@ static int __init pktsched_init(void)
- 	return 0;
- }
- 
-+/* QCA NSS Qdisc Support - Start */
-+bool tcf_destroy(struct tcf_proto *tp, bool force)
-+{
-+	tp->ops->destroy(tp, force, NULL);
-+	module_put(tp->ops->owner);
-+	kfree_rcu(tp, rcu);
-+
-+	return true;
-+}
-+
-+void tcf_destroy_chain(struct tcf_proto __rcu **fl)
-+{
-+	struct tcf_proto *tp;
-+
-+	while ((tp = rtnl_dereference(*fl)) != NULL) {
-+		RCU_INIT_POINTER(*fl, tp->next);
-+		tcf_destroy(tp, true);
-+	}
-+}
-+EXPORT_SYMBOL(tcf_destroy_chain);
-+/* QCA NSS Qdisc Support - End */
-+
- subsys_initcall(pktsched_init);
---- a/net/sched/sch_generic.c
-+++ b/net/sched/sch_generic.c
-@@ -767,7 +767,7 @@ static void qdisc_free_cb(struct rcu_hea
- 	qdisc_free(q);
- }
- 
--static void qdisc_destroy(struct Qdisc *qdisc)
-+void qdisc_destroy(struct Qdisc *qdisc)
- {
- 	const struct Qdisc_ops  *ops = qdisc->ops;
- 	struct sk_buff *skb, *tmp;
-@@ -798,6 +798,7 @@ static void qdisc_destroy(struct Qdisc *
- 
- 	call_rcu(&qdisc->rcu, qdisc_free_cb);
- }
-+EXPORT_SYMBOL(qdisc_destroy);
- 
- void qdisc_put(struct Qdisc *qdisc)
- {
diff --git a/target/linux/ipq806x/patches-5.4/999-07c-qca-nss-clients-ppp-support.patch b/target/linux/ipq806x/patches-5.4/999-07c-qca-nss-clients-ppp-support.patch
deleted file mode 100644
index aa7d61bef4e302..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-07c-qca-nss-clients-ppp-support.patch
+++ /dev/null
@@ -1,132 +0,0 @@
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -64,6 +64,7 @@
- #include <net/slhc_vj.h>
- #include <linux/atomic.h>
- #include <linux/refcount.h>
-+#include <linux/if_pppox.h>
- 
- #include <linux/nsproxy.h>
- #include <net/net_namespace.h>
-@@ -3241,6 +3242,10 @@ ppp_connect_channel(struct channel *pch,
- 	struct ppp_net *pn;
- 	int ret = -ENXIO;
- 	int hdrlen;
-+	/* QCA NSS ECM Support - Start */
-+	int ppp_proto;
-+	int version;
-+	/* QCA NSS ECM Support - End */
- 
- 	pn = ppp_pernet(pch->chan_net);
- 
-@@ -3272,6 +3277,26 @@ ppp_connect_channel(struct channel *pch,
- 	++ppp->n_channels;
- 	pch->ppp = ppp;
- 	refcount_inc(&ppp->file.refcnt);
-+
-+	/* QCA NSS ECM support - Start */
-+	/* Set the netdev priv flag if the prototype
-+	 * is L2TP or PPTP. Return success in all cases
-+	 */
-+	if (!pch->chan)
-+		goto out2;
-+
-+	ppp_proto = ppp_channel_get_protocol(pch->chan);
-+	if (ppp_proto == PX_PROTO_PPTP) {
-+		ppp->dev->priv_flags_qca_ecm |= IFF_QCA_ECM_PPP_PPTP;
-+	} else if (ppp_proto == PX_PROTO_OL2TP) {
-+		version = ppp_channel_get_proto_version(pch->chan);
-+		if (version == 2)
-+			ppp->dev->priv_flags_qca_ecm |= IFF_QCA_ECM_PPP_L2TPV2;
-+		else if (version == 3)
-+			ppp->dev->priv_flags_qca_ecm |= IFF_QCA_ECM_PPP_L2TPV3;
-+	}
-+	/* QCA NSS ECM support - End */
-+ out2:
- 	ppp_unlock(ppp);
- 	ret = 0;
- 
-@@ -3557,6 +3582,56 @@ void ppp_release_channels(struct ppp_cha
- }
- EXPORT_SYMBOL(ppp_release_channels);
- 
-+/* Return the PPP net device index */
-+int ppp_dev_index(struct ppp_channel *chan)
-+{
-+	struct channel *pch = chan->ppp;
-+	int ifindex = 0;
-+
-+	if (pch) {
-+		read_lock_bh(&pch->upl);
-+		if (pch->ppp && pch->ppp->dev)
-+			ifindex = pch->ppp->dev->ifindex;
-+		read_unlock_bh(&pch->upl);
-+	}
-+	return ifindex;
-+}
-+EXPORT_SYMBOL(ppp_dev_index);
-+
-+/* ppp_channel_get_proto_version()
-+ *	Call this to get channel protocol version
-+ */
-+int ppp_channel_get_proto_version(struct ppp_channel *chan)
-+{
-+	if (!chan->ops->get_channel_protocol_ver)
-+		return -1;
-+
-+	return chan->ops->get_channel_protocol_ver(chan);
-+}
-+EXPORT_SYMBOL(ppp_channel_get_proto_version);
-+
-+/* Check if ppp xmit lock is on hold */
-+bool ppp_is_xmit_locked(struct net_device *dev)
-+{
-+	struct ppp *ppp;
-+
-+	if (!dev)
-+		return false;
-+
-+	if (dev->type != ARPHRD_PPP)
-+		return false;
-+
-+	ppp = netdev_priv(dev);
-+	if (!ppp)
-+		return false;
-+
-+	if (spin_is_locked(&(ppp)->wlock))
-+		return true;
-+
-+	return false;
-+}
-+EXPORT_SYMBOL(ppp_is_xmit_locked);
-+
- /* Module/initialization stuff */
- 
- module_init(ppp_init);
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -36,6 +36,8 @@ struct ppp_channel_ops {
- 	 * the channel subtype
- 	 */
- 	int (*get_channel_protocol)(struct ppp_channel *);
-+	/* Get channel protocol version */
-+	int (*get_channel_protocol_ver)(struct ppp_channel *);
- 	/* Hold the channel from being destroyed */
- 	void (*hold)(struct ppp_channel *);
- 	/* Release hold on the channel */
-@@ -69,6 +71,15 @@ extern void ppp_channel_release(struct p
- extern void ppp_release_channels(struct ppp_channel *channels[],
- 				 unsigned int chan_sz);
- 
-+/* Test if ppp xmit lock is locked */
-+extern bool ppp_is_xmit_locked(struct net_device *dev);
-+
-+/* Call this get protocol version */
-+extern int ppp_channel_get_proto_version(struct ppp_channel *);
-+
-+/* Get the device index  associated with a channel, or 0, if none */
-+extern int ppp_dev_index(struct ppp_channel *);
-+
- /* Hold PPP channels for the PPP device */
- extern int ppp_hold_channels(struct net_device *dev,
- 			     struct ppp_channel *channels[],
diff --git a/target/linux/ipq806x/patches-5.4/999-07d-qca-nss-clients-ppp-support.patch b/target/linux/ipq806x/patches-5.4/999-07d-qca-nss-clients-ppp-support.patch
deleted file mode 100644
index 8f9309171a399d..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-07d-qca-nss-clients-ppp-support.patch
+++ /dev/null
@@ -1,99 +0,0 @@
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -135,5 +135,17 @@ extern char *ppp_dev_name(struct ppp_cha
-  * that ppp_unregister_channel returns.
-  */
- 
-+/* QCA NSS Clients Support - Start */
-+/* PPP channel connection event types */
-+#define PPP_CHANNEL_DISCONNECT	0
-+#define PPP_CHANNEL_CONNECT	1
-+
-+/* Register the PPP channel connect notifier */
-+extern void ppp_channel_connection_register_notify(struct notifier_block *nb);
-+
-+/* Unregister the PPP channel connect notifier */
-+extern void ppp_channel_connection_unregister_notify(struct notifier_block *nb);
-+/* QCA NSS Clients Support - End */
-+
- #endif /* __KERNEL__ */
- #endif
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -274,6 +274,26 @@ struct ppp_net {
- #define seq_before(a, b)	((s32)((a) - (b)) < 0)
- #define seq_after(a, b)		((s32)((a) - (b)) > 0)
- 
-+/* QCA NSS Client Support - Start */
-+/*
-+ * Registration/Unregistration methods
-+ * for PPP channel connect and disconnect event notifications.
-+ */
-+RAW_NOTIFIER_HEAD(ppp_channel_connection_notifier_list);
-+
-+void ppp_channel_connection_register_notify(struct notifier_block *nb)
-+{
-+	raw_notifier_chain_register(&ppp_channel_connection_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(ppp_channel_connection_register_notify);
-+
-+void ppp_channel_connection_unregister_notify(struct notifier_block *nb)
-+{
-+	raw_notifier_chain_unregister(&ppp_channel_connection_notifier_list, nb);
-+}
-+EXPORT_SYMBOL_GPL(ppp_channel_connection_unregister_notify);
-+/* QCA NSS Client Support - End */
-+
- /* Prototypes. */
- static int ppp_unattached_ioctl(struct net *net, struct ppp_file *pf,
- 			struct file *file, unsigned int cmd, unsigned long arg);
-@@ -3246,6 +3266,7 @@ ppp_connect_channel(struct channel *pch,
- 	int ppp_proto;
- 	int version;
- 	/* QCA NSS ECM Support - End */
-+	int notify = 0; /* QCA NSS Client Support */
- 
- 	pn = ppp_pernet(pch->chan_net);
- 
-@@ -3296,6 +3317,8 @@ ppp_connect_channel(struct channel *pch,
- 			ppp->dev->priv_flags_qca_ecm |= IFF_QCA_ECM_PPP_L2TPV3;
- 	}
- 	/* QCA NSS ECM support - End */
-+
-+	notify = 1; /* QCA NSS Clients Support */
-  out2:
- 	ppp_unlock(ppp);
- 	ret = 0;
-@@ -3304,6 +3327,16 @@ ppp_connect_channel(struct channel *pch,
- 	write_unlock_bh(&pch->upl);
-  out:
- 	mutex_unlock(&pn->all_ppp_mutex);
-+
-+	/* QCA NSS Clients Support - Start */
-+	if (notify && ppp && ppp->dev) {
-+		dev_hold(ppp->dev);
-+		raw_notifier_call_chain(&ppp_channel_connection_notifier_list,
-+					   PPP_CHANNEL_CONNECT, ppp->dev);
-+		dev_put(ppp->dev);
-+	}
-+	/* QCA NSS Clients Support - End */
-+
- 	return ret;
- }
- 
-@@ -3321,6 +3354,15 @@ ppp_disconnect_channel(struct channel *p
- 	pch->ppp = NULL;
- 	write_unlock_bh(&pch->upl);
- 	if (ppp) {
-+		/* QCA NSS Clients Support - Start */
-+		if (ppp->dev) {
-+			dev_hold(ppp->dev);
-+			raw_notifier_call_chain(&ppp_channel_connection_notifier_list,
-+					   PPP_CHANNEL_DISCONNECT, ppp->dev);
-+			dev_put(ppp->dev);
-+		}
-+		/* QCA NSS Clients Support - Start */
-+
- 		/* remove it from the ppp unit's list */
- 		ppp_lock(ppp);
- 		list_del(&pch->clist);
diff --git a/target/linux/ipq806x/patches-5.4/999-07e-qca-nss-clients-iptunnel-support.patch b/target/linux/ipq806x/patches-5.4/999-07e-qca-nss-clients-iptunnel-support.patch
deleted file mode 100644
index 1d2b425bb6d882..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-07e-qca-nss-clients-iptunnel-support.patch
+++ /dev/null
@@ -1,77 +0,0 @@
---- a/include/net/ip6_tunnel.h
-+++ b/include/net/ip6_tunnel.h
-@@ -36,6 +36,7 @@ struct __ip6_tnl_parm {
- 	__u8 proto;		/* tunnel protocol */
- 	__u8 encap_limit;	/* encapsulation limit for tunnel */
- 	__u8 hop_limit;		/* hop limit for tunnel */
-+	__u8 draft03;		/* FMR using draft03 of map-e - QCA NSS Clients Support */
- 	bool collect_md;
- 	__be32 flowinfo;	/* traffic class and flowlabel for tunnel */
- 	__u32 flags;		/* tunnel flags */
---- a/include/net/ip_tunnels.h
-+++ b/include/net/ip_tunnels.h
-@@ -532,4 +532,9 @@ static inline void ip_tunnel_info_opts_s
- 
- #endif /* CONFIG_INET */
- 
-+/* QCA NSS Clients Support - Start */
-+void ipip6_update_offload_stats(struct net_device *dev, void *ptr);
-+void ip6_update_offload_stats(struct net_device *dev, void *ptr);
-+/* QCA NSS Clients Support - End */
-+
- #endif /* __NET_IP_TUNNELS_H */
---- a/net/ipv6/ip6_tunnel.c
-+++ b/net/ipv6/ip6_tunnel.c
-@@ -2401,6 +2401,26 @@ nla_put_failure:
- 	return -EMSGSIZE;
- }
- 
-+/* QCA NSS Client Support - Start */
-+/*
-+ * Update offload stats
-+ */
-+void ip6_update_offload_stats(struct net_device *dev, void *ptr)
-+{
-+	struct pcpu_sw_netstats *tstats = per_cpu_ptr(dev->tstats, 0);
-+	const struct pcpu_sw_netstats *offload_stats =
-+					(struct pcpu_sw_netstats *)ptr;
-+
-+	u64_stats_update_begin(&tstats->syncp);
-+	tstats->tx_packets += offload_stats->tx_packets;
-+	tstats->tx_bytes   += offload_stats->tx_bytes;
-+	tstats->rx_packets += offload_stats->rx_packets;
-+	tstats->rx_bytes   += offload_stats->rx_bytes;
-+	u64_stats_update_end(&tstats->syncp);
-+}
-+EXPORT_SYMBOL(ip6_update_offload_stats);
-+/* QCA NSS Client Support - End */
-+
- struct net *ip6_tnl_get_link_net(const struct net_device *dev)
- {
- 	struct ip6_tnl *tunnel = netdev_priv(dev);
---- a/net/ipv6/sit.c
-+++ b/net/ipv6/sit.c
-@@ -1741,6 +1741,23 @@ nla_put_failure:
- 	return -EMSGSIZE;
- }
- 
-+/* QCA NSS Clients Support - Start */
-+void ipip6_update_offload_stats(struct net_device *dev, void *ptr)
-+{
-+	struct pcpu_sw_netstats *tstats = per_cpu_ptr(dev->tstats, 0);
-+	const struct pcpu_sw_netstats *offload_stats =
-+					(struct pcpu_sw_netstats *)ptr;
-+
-+	u64_stats_update_begin(&tstats->syncp);
-+	tstats->tx_packets += offload_stats->tx_packets;
-+	tstats->tx_bytes   += offload_stats->tx_bytes;
-+	tstats->rx_packets += offload_stats->rx_packets;
-+	tstats->rx_bytes   += offload_stats->rx_bytes;
-+	u64_stats_update_end(&tstats->syncp);
-+}
-+EXPORT_SYMBOL(ipip6_update_offload_stats);
-+/* QCA NSS Clients Support - End */
-+
- static const struct nla_policy ipip6_policy[IFLA_IPTUN_MAX + 1] = {
- 	[IFLA_IPTUN_LINK]		= { .type = NLA_U32 },
- 	[IFLA_IPTUN_LOCAL]		= { .type = NLA_U32 },
diff --git a/target/linux/ipq806x/patches-5.4/999-08-qca-mcs-support.patch b/target/linux/ipq806x/patches-5.4/999-08-qca-mcs-support.patch
deleted file mode 100644
index e87ded79bfdfdd..00000000000000
--- a/target/linux/ipq806x/patches-5.4/999-08-qca-mcs-support.patch
+++ /dev/null
@@ -1,931 +0,0 @@
---- a/include/linux/if_bridge.h
-+++ b/include/linux/if_bridge.h
-@@ -187,4 +187,17 @@ typedef struct net_bridge_port *br_get_d
- extern br_get_dst_hook_t __rcu *br_get_dst_hook;
- /* QCA NSS ECM support - End */
- 
-+/* QCA qca-mcs support - Start */
-+typedef struct net_bridge_port *br_get_dst_hook_t(const struct net_bridge_port *src,
-+		struct sk_buff **skb);
-+extern br_get_dst_hook_t __rcu *br_get_dst_hook;
-+
-+typedef int (br_multicast_handle_hook_t)(const struct net_bridge_port *src,
-+		struct sk_buff *skb);
-+extern br_multicast_handle_hook_t __rcu *br_multicast_handle_hook;
-+
-+typedef void (br_notify_hook_t)(int group, int event, const void *ptr);
-+extern br_notify_hook_t __rcu *br_notify_hook;
-+/* QCA qca-mcs support - End */
-+
- #endif
---- a/net/bridge/br_fdb.c
-+++ b/net/bridge/br_fdb.c
-@@ -175,6 +175,7 @@ struct net_bridge_fdb_entry *br_fdb_find
- {
- 	return fdb_find_rcu(&br->fdb_hash_tbl, addr, vid);
- }
-+EXPORT_SYMBOL_GPL(br_fdb_find_rcu); /* QCA qca-mcs support */
- 
- /* When a static FDB entry is added, the mac address from the entry is
-  * added to the bridge private HW address list and all required ports
-@@ -772,6 +773,7 @@ static void fdb_notify(struct net_bridge
- 		kfree_skb(skb);
- 		goto errout;
- 	}
-+	__br_notify(RTNLGRP_NEIGH, type, fdb); /* QCA qca-mcs support */
- 	rtnl_notify(skb, net, 0, RTNLGRP_NEIGH, NULL, GFP_ATOMIC);
- 	return;
- errout:
---- a/net/bridge/br_private.h
-+++ b/net/bridge/br_private.h
-@@ -627,6 +627,7 @@ void br_manage_promisc(struct net_bridge
- int nbp_backup_change(struct net_bridge_port *p, struct net_device *backup_dev);
- 
- /* br_input.c */
-+int br_pass_frame_up(struct sk_buff *skb); /* QCA qca-mcs support */
- int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb);
- rx_handler_result_t br_handle_frame(struct sk_buff **pskb);
- 
-@@ -1274,4 +1275,14 @@ struct nd_msg *br_is_nd_neigh_msg(struct
- #define __br_get(__hook, __default, __args ...) \
- 		(__hook ? (__hook(__args)) : (__default))
- /* QCA NSS ECM support - End */
-+
-+/* QCA qca-mcs support - Start */
-+static inline void __br_notify(int group, int type, const void *data)
-+{
-+	br_notify_hook_t *notify_hook = rcu_dereference(br_notify_hook);
-+
-+	if (notify_hook)
-+		notify_hook(group, type, data);
-+}
-+/* QCA qca-mcs support - End */
- #endif
---- a/net/bridge/br_netlink.c
-+++ b/net/bridge/br_netlink.c
-@@ -499,6 +499,7 @@ void br_ifinfo_notify(int event, const s
- 		kfree_skb(skb);
- 		goto errout;
- 	}
-+	__br_notify(RTNLGRP_LINK, event, port); /* QCA qca-mcs support */
- 	rtnl_notify(skb, net, 0, RTNLGRP_LINK, NULL, GFP_ATOMIC);
- 	return;
- errout:
---- a/net/bridge/br.c
-+++ b/net/bridge/br.c
-@@ -394,6 +394,12 @@ static void __exit br_deinit(void)
- 	br_fdb_fini();
- }
- 
-+/* QCA qca-mcs support - Start */
-+/* Hook for bridge event notifications */
-+br_notify_hook_t __rcu *br_notify_hook __read_mostly;
-+EXPORT_SYMBOL_GPL(br_notify_hook);
-+/* QCA qca-mcs support - End */
-+
- module_init(br_init)
- module_exit(br_deinit)
- MODULE_LICENSE("GPL");
---- a/net/bridge/br_device.c
-+++ b/net/bridge/br_device.c
-@@ -85,6 +85,12 @@ netdev_tx_t br_dev_xmit(struct sk_buff *
- 	if (is_broadcast_ether_addr(dest)) {
- 		br_flood(br, skb, BR_PKT_BROADCAST, false, true);
- 	} else if (is_multicast_ether_addr(dest)) {
-+		/* QCA qca-mcs support - Start */
-+		br_multicast_handle_hook_t *multicast_handle_hook = rcu_dereference(br_multicast_handle_hook);
-+		if (!__br_get(multicast_handle_hook, true, NULL, skb))
-+			goto out;
-+		/* QCA qca-mcs support - End */
-+
- 		if (unlikely(netpoll_tx_running(dev))) {
- 			br_flood(br, skb, BR_PKT_MULTICAST, false, true);
- 			goto out;
---- a/net/bridge/br_input.c
-+++ b/net/bridge/br_input.c
-@@ -22,6 +22,16 @@
- #include "br_private.h"
- #include "br_private_tunnel.h"
- 
-+/* QCA qca-mcs support - Start */
-+/* Hook for external Multicast handler */
-+br_multicast_handle_hook_t __rcu *br_multicast_handle_hook __read_mostly;
-+EXPORT_SYMBOL_GPL(br_multicast_handle_hook);
-+
-+/* Hook for external forwarding logic */
-+br_get_dst_hook_t __rcu *br_get_dst_hook __read_mostly;
-+EXPORT_SYMBOL_GPL(br_get_dst_hook);
-+/* QCA qca-mcs support - End */
-+
- static int
- br_netif_receive_skb(struct net *net, struct sock *sk, struct sk_buff *skb)
- {
-@@ -29,7 +39,7 @@ br_netif_receive_skb(struct net *net, st
- 	return netif_receive_skb(skb);
- }
- 
--static int br_pass_frame_up(struct sk_buff *skb)
-+int br_pass_frame_up(struct sk_buff *skb)
- {
- 	struct net_device *indev, *brdev = BR_INPUT_SKB_CB(skb)->brdev;
- 	struct net_bridge *br = netdev_priv(brdev);
-@@ -72,6 +82,7 @@ static int br_pass_frame_up(struct sk_bu
- 		       dev_net(indev), NULL, skb, indev, NULL,
- 		       br_netif_receive_skb);
- }
-+EXPORT_SYMBOL_GPL(br_pass_frame_up); /* QCA qca-mcs support */
- 
- /* note: already called with rcu_read_lock */
- int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
-@@ -83,6 +94,11 @@ int br_handle_frame_finish(struct net *n
- 	bool local_rcv, mcast_hit = false;
- 	struct net_bridge *br;
- 	u16 vid = 0;
-+	/* QCA qca-mcs support - Start */
-+	br_multicast_handle_hook_t *multicast_handle_hook;
-+	struct net_bridge_port *pdst = NULL;
-+	br_get_dst_hook_t *get_dst_hook = rcu_dereference(br_get_dst_hook);
-+	/* QCA qca-mcs support - End */
- 
- 	if (!p || p->state == BR_STATE_DISABLED)
- 		goto drop;
-@@ -139,6 +155,12 @@ int br_handle_frame_finish(struct net *n
- 
- 	switch (pkt_type) {
- 	case BR_PKT_MULTICAST:
-+		/* QCA qca-mcs support - Start */
-+		multicast_handle_hook = rcu_dereference(br_multicast_handle_hook);
-+		if (!__br_get(multicast_handle_hook, true, p, skb))
-+			goto out;
-+		/* QCA qca-mcs support - End */
-+
- 		mdst = br_mdb_get(br, skb, vid);
- 		if ((mdst || BR_INPUT_SKB_CB_MROUTERS_ONLY(skb)) &&
- 		    br_multicast_querier_exists(br, eth_hdr(skb))) {
-@@ -154,7 +176,15 @@ int br_handle_frame_finish(struct net *n
- 		}
- 		break;
- 	case BR_PKT_UNICAST:
--		dst = br_fdb_find_rcu(br, eth_hdr(skb)->h_dest, vid);
-+		/* QCA qca-mcs support - Start */
-+		pdst = __br_get(get_dst_hook, NULL, p, &skb);
-+		if (pdst) {
-+			if (!skb)
-+				goto out;
-+		} else {
-+		/* QCA qca-mcs support - End */
-+			dst = br_fdb_find_rcu(br, eth_hdr(skb)->h_dest, vid);
-+		}
- 	default:
- 		break;
- 	}
-@@ -169,12 +199,20 @@ int br_handle_frame_finish(struct net *n
- 			dst->used = now;
- 		br_forward(dst->dst, skb, local_rcv, false);
- 	} else {
-+		/* QCA qca-mcs support - Start */
-+		if (pdst) {
-+			br_forward(pdst, skb, local_rcv, false);
-+			goto out1;
-+		}
-+		/* QCA qca-mcs support - End */
-+
- 		if (!mcast_hit)
- 			br_flood(br, skb, pkt_type, local_rcv, false);
- 		else
- 			br_multicast_flood(mdst, skb, local_rcv, false);
- 	}
- 
-+out1: /* QCA qca-mcs support */
- 	if (local_rcv)
- 		return br_pass_frame_up(skb);
- 
---- a/include/linux/mroute.h
-+++ b/include/linux/mroute.h
-@@ -84,4 +84,44 @@ struct rtmsg;
- int ipmr_get_route(struct net *net, struct sk_buff *skb,
- 		   __be32 saddr, __be32 daddr,
- 		   struct rtmsg *rtm, u32 portid);
-+
-+/* QCA ECM qca-mcs support - Start */
-+#define IPMR_MFC_EVENT_UPDATE   1
-+#define IPMR_MFC_EVENT_DELETE   2
-+
-+/*
-+ * Callback to registered modules in the event of updates to a multicast group
-+ */
-+typedef void (*ipmr_mfc_event_offload_callback_t)(__be32 origin, __be32 group,
-+						  u32 max_dest_dev,
-+						  u32 dest_dev_idx[],
-+						  u8 op);
-+
-+/*
-+ * Register the callback used to inform offload modules when updates occur to
-+ * MFC. The callback is registered by offload modules
-+ */
-+extern bool ipmr_register_mfc_event_offload_callback(
-+			ipmr_mfc_event_offload_callback_t mfc_offload_cb);
-+
-+/*
-+ * De-Register the callback used to inform offload modules when updates occur
-+ * to MFC
-+ */
-+extern void ipmr_unregister_mfc_event_offload_callback(void);
-+
-+/*
-+ * Find the destination interface list, given a multicast group and source
-+ */
-+extern int ipmr_find_mfc_entry(struct net *net, __be32 origin, __be32 group,
-+				 u32 max_dst_cnt, u32 dest_dev[]);
-+
-+/*
-+ * Out-of-band multicast statistics update for flows that are offloaded from
-+ * Linux
-+ */
-+extern int ipmr_mfc_stats_update(struct net *net, __be32 origin, __be32 group,
-+				 u64 pkts_in, u64 bytes_in,
-+				 u64 pkts_out, u64 bytes_out);
-+/* QCA ECM qca-mcs support - End */
- #endif
---- a/include/linux/mroute6.h
-+++ b/include/linux/mroute6.h
-@@ -110,4 +110,47 @@ static inline int ip6mr_sk_done(struct s
- 	return 0;
- }
- #endif
-+
-+/* QCA qca-mcs support - Start */
-+#define IP6MR_MFC_EVENT_UPDATE   1
-+#define IP6MR_MFC_EVENT_DELETE   2
-+
-+/*
-+ * Callback to registered modules in the event of updates to a multicast group
-+ */
-+typedef void (*ip6mr_mfc_event_offload_callback_t)(struct in6_addr *origin,
-+						   struct in6_addr *group,
-+						   u32 max_dest_dev,
-+						   u32 dest_dev_idx[],
-+						   uint8_t op);
-+
-+/*
-+ * Register the callback used to inform offload modules when updates occur
-+ * to MFC. The callback is registered by offload modules
-+ */
-+extern bool ip6mr_register_mfc_event_offload_callback(
-+			ip6mr_mfc_event_offload_callback_t mfc_offload_cb);
-+
-+/*
-+ * De-Register the callback used to inform offload modules when updates occur
-+ * to MFC
-+ */
-+extern void ip6mr_unregister_mfc_event_offload_callback(void);
-+
-+/*
-+ * Find the destination interface list given a multicast group and source
-+ */
-+extern int ip6mr_find_mfc_entry(struct net *net, struct in6_addr *origin,
-+				struct in6_addr *group, u32 max_dst_cnt,
-+				u32 dest_dev[]);
-+
-+/*
-+ * Out-of-band multicast statistics update for flows that are offloaded from
-+ * Linux
-+ */
-+extern int ip6mr_mfc_stats_update(struct net *net, struct in6_addr *origin,
-+				  struct in6_addr *group, uint64_t pkts_in,
-+				  uint64_t bytes_in, uint64_t pkts_out,
-+				  uint64_t bytes_out);
-+/* QCA qca-mcs support - End */
- #endif
---- a/net/ipv4/ipmr.c
-+++ b/net/ipv4/ipmr.c
-@@ -108,6 +108,15 @@ static void igmpmsg_netlink_event(struct
- static void mroute_clean_tables(struct mr_table *mrt, int flags);
- static void ipmr_expire_process(struct timer_list *t);
- 
-+/* QCA ECM qca-mcs support - Start */
-+/* spinlock for offload */
-+static DEFINE_SPINLOCK(lock);
-+
-+static struct mfc_cache *ipmr_cache_find(struct mr_table *mrt, __be32 origin,
-+					 __be32 mcastgrp);
-+static ipmr_mfc_event_offload_callback_t __rcu ipmr_mfc_event_offload_callback;
-+/* QCA ECM qca-mcs support - End */
-+
- #ifdef CONFIG_IP_MROUTE_MULTIPLE_TABLES
- #define ipmr_for_each_table(mrt, net) \
- 	list_for_each_entry_rcu(mrt, &net->ipv4.mr_tables, list)
-@@ -220,6 +229,228 @@ static int ipmr_rule_fill(struct fib_rul
- 	return 0;
- }
- 
-+/* QCA ECM qca-mcs support - Start */
-+/* ipmr_sync_entry_update()
-+ * Call the registered offload callback to report an update to a multicast
-+ * route entry. The callback receives the list of destination interfaces and
-+ * the interface count
-+ */
-+static void ipmr_sync_entry_update(struct mr_table *mrt,
-+				   struct mfc_cache *cache)
-+{
-+	int vifi, dest_if_count = 0;
-+	u32 dest_dev[MAXVIFS];
-+	__be32  origin;
-+	__be32  group;
-+	ipmr_mfc_event_offload_callback_t offload_update_cb_f;
-+
-+	memset(dest_dev, 0, sizeof(dest_dev));
-+
-+	origin = cache->mfc_origin;
-+	group = cache->mfc_mcastgrp;
-+
-+	read_lock(&mrt_lock);
-+	for (vifi = 0; vifi < cache->_c.mfc_un.res.maxvif; vifi++) {
-+		if (!((cache->_c.mfc_un.res.ttls[vifi] > 0) &&
-+		      (cache->_c.mfc_un.res.ttls[vifi] < 255))) {
-+			continue;
-+		}
-+		if (dest_if_count == MAXVIFS) {
-+			read_unlock(&mrt_lock);
-+			return;
-+		}
-+
-+		if (!VIF_EXISTS(mrt, vifi)) {
-+			read_unlock(&mrt_lock);
-+			return;
-+		}
-+		dest_dev[dest_if_count] = mrt->vif_table[vifi].dev->ifindex;
-+		dest_if_count++;
-+	}
-+	read_unlock(&mrt_lock);
-+
-+	rcu_read_lock();
-+	offload_update_cb_f = rcu_dereference(ipmr_mfc_event_offload_callback);
-+
-+	if (!offload_update_cb_f) {
-+		rcu_read_unlock();
-+		return;
-+	}
-+
-+	offload_update_cb_f(group, origin, dest_if_count, dest_dev,
-+			    IPMR_MFC_EVENT_UPDATE);
-+	rcu_read_unlock();
-+}
-+
-+/* ipmr_sync_entry_delete()
-+ * Call the registered offload callback to inform of a multicast route entry
-+ * delete event
-+ */
-+static void ipmr_sync_entry_delete(u32 origin, u32 group)
-+{
-+	ipmr_mfc_event_offload_callback_t offload_update_cb_f;
-+
-+	rcu_read_lock();
-+	offload_update_cb_f = rcu_dereference(ipmr_mfc_event_offload_callback);
-+
-+	if (!offload_update_cb_f) {
-+		rcu_read_unlock();
-+		return;
-+	}
-+
-+	offload_update_cb_f(group, origin, 0, NULL, IPMR_MFC_EVENT_DELETE);
-+	rcu_read_unlock();
-+}
-+
-+/* ipmr_register_mfc_event_offload_callback()
-+ * Register the IPv4 Multicast update offload callback with IPMR
-+ */
-+bool ipmr_register_mfc_event_offload_callback(
-+		ipmr_mfc_event_offload_callback_t mfc_offload_cb)
-+{
-+	ipmr_mfc_event_offload_callback_t offload_update_cb_f;
-+
-+	rcu_read_lock();
-+	offload_update_cb_f = rcu_dereference(ipmr_mfc_event_offload_callback);
-+
-+	if (offload_update_cb_f) {
-+		rcu_read_unlock();
-+		return false;
-+	}
-+	rcu_read_unlock();
-+
-+	spin_lock(&lock);
-+	rcu_assign_pointer(ipmr_mfc_event_offload_callback, mfc_offload_cb);
-+	spin_unlock(&lock);
-+	synchronize_rcu();
-+	return true;
-+}
-+EXPORT_SYMBOL(ipmr_register_mfc_event_offload_callback);
-+
-+/* ipmr_unregister_mfc_event_offload_callback()
-+ * De-register the IPv4 Multicast update offload callback with IPMR
-+ */
-+void ipmr_unregister_mfc_event_offload_callback(void)
-+{
-+	spin_lock(&lock);
-+	rcu_assign_pointer(ipmr_mfc_event_offload_callback, NULL);
-+	spin_unlock(&lock);
-+	synchronize_rcu();
-+}
-+EXPORT_SYMBOL(ipmr_unregister_mfc_event_offload_callback);
-+
-+/* ipmr_find_mfc_entry()
-+ * Returns destination interface list for a particular multicast flow, and
-+ * the number of interfaces in the list
-+ */
-+int ipmr_find_mfc_entry(struct net *net, __be32 origin, __be32 group,
-+			u32 max_dest_cnt, u32 dest_dev[])
-+{
-+	int vifi, dest_if_count = 0;
-+	struct mr_table *mrt;
-+	struct mfc_cache *cache;
-+
-+	mrt = ipmr_get_table(net, RT_TABLE_DEFAULT);
-+	if (!mrt)
-+		return -ENOENT;
-+
-+	rcu_read_lock();
-+	cache = ipmr_cache_find(mrt, origin, group);
-+	if (!cache) {
-+		rcu_read_unlock();
-+		return -ENOENT;
-+	}
-+
-+	read_lock(&mrt_lock);
-+	for (vifi = 0; vifi < cache->_c.mfc_un.res.maxvif; vifi++) {
-+		if (!((cache->_c.mfc_un.res.ttls[vifi] > 0) &&
-+		      (cache->_c.mfc_un.res.ttls[vifi] < 255))) {
-+			continue;
-+		}
-+
-+		/* We have another valid destination interface entry. Check if
-+		 * the number of the destination interfaces for the route is
-+		 * exceeding the size of the array given to us
-+		 */
-+		if (dest_if_count == max_dest_cnt) {
-+			read_unlock(&mrt_lock);
-+			rcu_read_unlock();
-+			return -EINVAL;
-+		}
-+
-+		if (!VIF_EXISTS(mrt, vifi)) {
-+			read_unlock(&mrt_lock);
-+			rcu_read_unlock();
-+			return -EINVAL;
-+		}
-+
-+		dest_dev[dest_if_count] = mrt->vif_table[vifi].dev->ifindex;
-+		dest_if_count++;
-+	}
-+	read_unlock(&mrt_lock);
-+	rcu_read_unlock();
-+
-+	return dest_if_count;
-+}
-+EXPORT_SYMBOL(ipmr_find_mfc_entry);
-+
-+/* ipmr_mfc_stats_update()
-+ * Update the MFC/VIF statistics for offloaded flows
-+ */
-+int ipmr_mfc_stats_update(struct net *net, __be32 origin, __be32 group,
-+			  u64 pkts_in, u64 bytes_in,
-+			  u64 pkts_out, u64 bytes_out)
-+{
-+	int vif, vifi;
-+	struct mr_table *mrt;
-+	struct mfc_cache *cache;
-+
-+	mrt = ipmr_get_table(net, RT_TABLE_DEFAULT);
-+	if (!mrt)
-+		return -ENOENT;
-+
-+	rcu_read_lock();
-+	cache = ipmr_cache_find(mrt, origin, group);
-+	if (!cache) {
-+		rcu_read_unlock();
-+		return -ENOENT;
-+	}
-+
-+	vif = cache->_c.mfc_parent;
-+
-+	read_lock(&mrt_lock);
-+	if (!VIF_EXISTS(mrt, vif)) {
-+		read_unlock(&mrt_lock);
-+		rcu_read_unlock();
-+		return -EINVAL;
-+	}
-+
-+	mrt->vif_table[vif].pkt_in += pkts_in;
-+	mrt->vif_table[vif].bytes_in += bytes_in;
-+	cache->_c.mfc_un.res.pkt  += pkts_out;
-+	cache->_c.mfc_un.res.bytes += bytes_out;
-+
-+	for (vifi = cache->_c.mfc_un.res.minvif;
-+			vifi < cache->_c.mfc_un.res.maxvif; vifi++) {
-+		if ((cache->_c.mfc_un.res.ttls[vifi] > 0) &&
-+		    (cache->_c.mfc_un.res.ttls[vifi] < 255)) {
-+			if (!VIF_EXISTS(mrt, vifi)) {
-+				read_unlock(&mrt_lock);
-+				rcu_read_unlock();
-+				return -EINVAL;
-+			}
-+			mrt->vif_table[vifi].pkt_out += pkts_out;
-+			mrt->vif_table[vifi].bytes_out += bytes_out;
-+		}
-+	}
-+	read_unlock(&mrt_lock);
-+	rcu_read_unlock();
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ipmr_mfc_stats_update);
-+/* QCA ECM qca-mcs support - End */
-+
- static const struct fib_rules_ops __net_initconst ipmr_rules_ops_template = {
- 	.family		= RTNL_FAMILY_IPMR,
- 	.rule_size	= sizeof(struct ipmr_rule),
-@@ -1210,6 +1441,11 @@ static int ipmr_mfc_delete(struct mr_tab
- 	mroute_netlink_event(mrt, c, RTM_DELROUTE);
- 	mr_cache_put(&c->_c);
- 
-+	/* QCA ECM qca-mcs support - Start */
-+	/* Inform offload modules of the delete event */
-+	ipmr_sync_entry_delete(c->mfc_origin, c->mfc_mcastgrp);
-+	/* QCA ECM qca-mcs support - End */
-+
- 	return 0;
- }
- 
-@@ -1239,6 +1475,12 @@ static int ipmr_mfc_add(struct net *net,
- 		call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_REPLACE, c,
- 					      mrt->id);
- 		mroute_netlink_event(mrt, c, RTM_NEWROUTE);
-+
-+		/* QCA ECM qca-mcs support - Start */
-+		/* Inform offload modules of the update event */
-+		ipmr_sync_entry_update(mrt, c);
-+		/* QCA ECM qca-mcs support - End */
-+
- 		return 0;
- 	}
- 
-@@ -1299,6 +1541,7 @@ static void mroute_clean_tables(struct m
- 	struct net *net = read_pnet(&mrt->net);
- 	struct mr_mfc *c, *tmp;
- 	struct mfc_cache *cache;
-+	u32 origin, group; /* QCA ECM qca-mcs support */
- 	LIST_HEAD(list);
- 	int i;
- 
-@@ -1323,10 +1566,19 @@ static void mroute_clean_tables(struct m
- 			rhltable_remove(&mrt->mfc_hash, &c->mnode, ipmr_rht_params);
- 			list_del_rcu(&c->list);
- 			cache = (struct mfc_cache *)c;
-+			/* QCA ECM qca-mcs support - Start */
-+			origin = cache->mfc_origin;
-+			group = cache->mfc_mcastgrp;
-+			/* QCA ECM qca-mcs support - End */
- 			call_ipmr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_DEL, cache,
- 						      mrt->id);
- 			mroute_netlink_event(mrt, cache, RTM_DELROUTE);
- 			mr_cache_put(c);
-+
-+			/* QCA ECM qca-mcs support - Start */
-+			/* Inform offload modules of the delete event */
-+			ipmr_sync_entry_delete(origin, group);
-+			/* QCA ECM qca-mcs support - End */
- 		}
- 	}
- 
---- a/net/ipv6/ip6mr.c
-+++ b/net/ipv6/ip6mr.c
-@@ -95,6 +95,17 @@ static int ip6mr_rtm_dumproute(struct sk
- static void mroute_clean_tables(struct mr_table *mrt, int flags);
- static void ipmr_expire_process(struct timer_list *t);
- 
-+/* QCA qca-mcs support - Start */
-+/* Spinlock for offload */
-+static DEFINE_SPINLOCK(lock);
-+
-+static struct mfc6_cache *ip6mr_cache_find(struct mr_table *mrt,
-+					   const struct in6_addr *origin,
-+					   const struct in6_addr *mcastgrp);
-+static ip6mr_mfc_event_offload_callback_t __rcu
-+				ip6mr_mfc_event_offload_callback;
-+/* QCA qca-mcs support - End */
-+
- #ifdef CONFIG_IPV6_MROUTE_MULTIPLE_TABLES
- #define ip6mr_for_each_table(mrt, net) \
- 	list_for_each_entry_rcu(mrt, &net->ipv6.mr6_tables, list)
-@@ -376,6 +387,227 @@ static struct mr_table_ops ip6mr_mr_tabl
- 	.cmparg_any = &ip6mr_mr_table_ops_cmparg_any,
- };
- 
-+/* QCA qca-mcs support - Start */
-+/* ip6mr_sync_entry_update()
-+ * Call the registered offload callback to report an update to a multicast
-+ * route entry. The callback receives the list of destination interfaces and
-+ * the interface count
-+ */
-+static void ip6mr_sync_entry_update(struct mr_table *mrt,
-+				    struct mfc6_cache *cache)
-+{
-+	int vifi, dest_if_count = 0;
-+	u32 dest_dev[MAXMIFS];
-+	struct in6_addr mc_origin, mc_group;
-+	ip6mr_mfc_event_offload_callback_t offload_update_cb_f;
-+
-+	memset(dest_dev, 0, sizeof(dest_dev));
-+
-+	read_lock(&mrt_lock);
-+
-+	for (vifi = 0; vifi < cache->_c.mfc_un.res.maxvif; vifi++) {
-+		if (!((cache->_c.mfc_un.res.ttls[vifi] > 0) &&
-+		      (cache->_c.mfc_un.res.ttls[vifi] < 255))) {
-+			continue;
-+		}
-+
-+		if (dest_if_count == MAXMIFS) {
-+			read_unlock(&mrt_lock);
-+			return;
-+		}
-+
-+		if (!VIF_EXISTS(mrt, vifi)) {
-+			read_unlock(&mrt_lock);
-+			return;
-+		}
-+
-+		dest_dev[dest_if_count] = mrt->vif_table[vifi].dev->ifindex;
-+		dest_if_count++;
-+	}
-+
-+	memcpy(&mc_origin, &cache->mf6c_origin, sizeof(struct in6_addr));
-+	memcpy(&mc_group, &cache->mf6c_mcastgrp, sizeof(struct in6_addr));
-+	read_unlock(&mrt_lock);
-+
-+	rcu_read_lock();
-+	offload_update_cb_f = rcu_dereference(ip6mr_mfc_event_offload_callback);
-+
-+	if (!offload_update_cb_f) {
-+		rcu_read_unlock();
-+		return;
-+	}
-+
-+	offload_update_cb_f(&mc_group, &mc_origin, dest_if_count, dest_dev,
-+			    IP6MR_MFC_EVENT_UPDATE);
-+	rcu_read_unlock();
-+}
-+
-+/* ip6mr_sync_entry_delete()
-+ * Call the registered offload callback to inform of a multicast route entry
-+ * delete event
-+ */
-+static void ip6mr_sync_entry_delete(struct in6_addr *mc_origin,
-+				    struct in6_addr *mc_group)
-+{
-+	ip6mr_mfc_event_offload_callback_t offload_update_cb_f;
-+
-+	rcu_read_lock();
-+	offload_update_cb_f = rcu_dereference(ip6mr_mfc_event_offload_callback);
-+
-+	if (!offload_update_cb_f) {
-+		rcu_read_unlock();
-+		return;
-+	}
-+
-+	offload_update_cb_f(mc_group, mc_origin, 0, NULL,
-+			    IP6MR_MFC_EVENT_DELETE);
-+	rcu_read_unlock();
-+}
-+
-+/* ip6mr_register_mfc_event_offload_callback()
-+ * Register the IPv6 multicast update callback for offload modules
-+ */
-+bool ip6mr_register_mfc_event_offload_callback(
-+		ip6mr_mfc_event_offload_callback_t mfc_offload_cb)
-+{
-+	ip6mr_mfc_event_offload_callback_t offload_update_cb_f;
-+
-+	rcu_read_lock();
-+	offload_update_cb_f = rcu_dereference(ip6mr_mfc_event_offload_callback);
-+
-+	if (offload_update_cb_f) {
-+		rcu_read_unlock();
-+		return false;
-+	}
-+	rcu_read_unlock();
-+
-+	spin_lock(&lock);
-+	rcu_assign_pointer(ip6mr_mfc_event_offload_callback, mfc_offload_cb);
-+	spin_unlock(&lock);
-+	synchronize_rcu();
-+	return true;
-+}
-+EXPORT_SYMBOL(ip6mr_register_mfc_event_offload_callback);
-+
-+/* ip6mr_unregister_mfc_event_offload_callback()
-+ * De-register the IPv6 multicast update callback for offload modules
-+ */
-+void ip6mr_unregister_mfc_event_offload_callback(void)
-+{
-+	spin_lock(&lock);
-+	rcu_assign_pointer(ip6mr_mfc_event_offload_callback, NULL);
-+	spin_unlock(&lock);
-+	synchronize_rcu();
-+}
-+EXPORT_SYMBOL(ip6mr_unregister_mfc_event_offload_callback);
-+
-+/* ip6mr_find_mfc_entry()
-+ * Return the destination interface list for a particular multicast flow, and
-+ * the number of interfaces in the list
-+ */
-+int ip6mr_find_mfc_entry(struct net *net, struct in6_addr *origin,
-+			 struct in6_addr *group, u32 max_dest_cnt,
-+			 u32 dest_dev[])
-+{
-+	int vifi, dest_if_count = 0;
-+	struct mr_table *mrt;
-+	struct mfc6_cache *cache;
-+
-+	mrt = ip6mr_get_table(net, RT6_TABLE_DFLT);
-+	if (!mrt)
-+		return -ENOENT;
-+
-+	read_lock(&mrt_lock);
-+	cache = ip6mr_cache_find(mrt, origin, group);
-+	if (!cache) {
-+		read_unlock(&mrt_lock);
-+		return -ENOENT;
-+	}
-+
-+	for (vifi = 0; vifi < cache->_c.mfc_un.res.maxvif; vifi++) {
-+		if (!((cache->_c.mfc_un.res.ttls[vifi] > 0) &&
-+		      (cache->_c.mfc_un.res.ttls[vifi] < 255))) {
-+			continue;
-+		}
-+
-+		/* We have another valid destination interface entry. Check if
-+		 * the number of the destination interfaces for the route is
-+		 * exceeding the size of the array given to us
-+		 */
-+		if (dest_if_count == max_dest_cnt) {
-+			read_unlock(&mrt_lock);
-+			return -EINVAL;
-+		}
-+
-+		if (!VIF_EXISTS(mrt, vifi)) {
-+			read_unlock(&mrt_lock);
-+			return -EINVAL;
-+		}
-+
-+		dest_dev[dest_if_count] = mrt->vif_table[vifi].dev->ifindex;
-+		dest_if_count++;
-+	}
-+	read_unlock(&mrt_lock);
-+
-+	return dest_if_count;
-+}
-+EXPORT_SYMBOL(ip6mr_find_mfc_entry);
-+
-+/* ip6mr_mfc_stats_update()
-+ * Update the MFC/VIF statistics for offloaded flows
-+ */
-+int ip6mr_mfc_stats_update(struct net *net, struct in6_addr *origin,
-+			   struct in6_addr *group, u64 pkts_in,
-+			   u64 bytes_in, uint64_t pkts_out,
-+			   u64 bytes_out)
-+{
-+	int vif, vifi;
-+	struct mr_table *mrt;
-+	struct mfc6_cache *cache;
-+
-+	mrt = ip6mr_get_table(net, RT6_TABLE_DFLT);
-+
-+	if (!mrt)
-+		return -ENOENT;
-+
-+	read_lock(&mrt_lock);
-+	cache = ip6mr_cache_find(mrt, origin, group);
-+	if (!cache) {
-+		read_unlock(&mrt_lock);
-+		return -ENOENT;
-+	}
-+
-+	vif = cache->_c.mfc_parent;
-+
-+	if (!VIF_EXISTS(mrt, vif)) {
-+		read_unlock(&mrt_lock);
-+		return -EINVAL;
-+	}
-+
-+	mrt->vif_table[vif].pkt_in += pkts_in;
-+	mrt->vif_table[vif].bytes_in += bytes_in;
-+	cache->_c.mfc_un.res.pkt += pkts_out;
-+	cache->_c.mfc_un.res.bytes += bytes_out;
-+
-+	for (vifi = cache->_c.mfc_un.res.minvif;
-+			vifi < cache->_c.mfc_un.res.maxvif; vifi++) {
-+		if ((cache->_c.mfc_un.res.ttls[vifi] > 0) &&
-+		    (cache->_c.mfc_un.res.ttls[vifi] < 255)) {
-+			if (!VIF_EXISTS(mrt, vifi)) {
-+				read_unlock(&mrt_lock);
-+				return -EINVAL;
-+			}
-+			mrt->vif_table[vifi].pkt_out += pkts_out;
-+			mrt->vif_table[vifi].bytes_out += bytes_out;
-+		}
-+	}
-+
-+	read_unlock(&mrt_lock);
-+	return 0;
-+}
-+EXPORT_SYMBOL(ip6mr_mfc_stats_update);
-+/* QCA qca-mcs support - End */
-+
- static struct mr_table *ip6mr_new_table(struct net *net, u32 id)
- {
- 	struct mr_table *mrt;
-@@ -1212,6 +1444,7 @@ static int ip6mr_mfc_delete(struct mr_ta
- 			    int parent)
- {
- 	struct mfc6_cache *c;
-+	struct in6_addr mc_origin, mc_group; /* QCA qca-mcs support */
- 
- 	/* The entries are added/deleted only under RTNL */
- 	rcu_read_lock();
-@@ -1220,6 +1453,12 @@ static int ip6mr_mfc_delete(struct mr_ta
- 	rcu_read_unlock();
- 	if (!c)
- 		return -ENOENT;
-+
-+	/* QCA qca-mcs support - Start */
-+	memcpy(&mc_origin, &c->mf6c_origin, sizeof(struct in6_addr));
-+	memcpy(&mc_group, &c->mf6c_mcastgrp, sizeof(struct in6_addr));
-+	/* QCA qca-mcs support - End */
-+
- 	rhltable_remove(&mrt->mfc_hash, &c->_c.mnode, ip6mr_rht_params);
- 	list_del_rcu(&c->_c.list);
- 
-@@ -1227,6 +1466,12 @@ static int ip6mr_mfc_delete(struct mr_ta
- 				       FIB_EVENT_ENTRY_DEL, c, mrt->id);
- 	mr6_netlink_event(mrt, c, RTM_DELROUTE);
- 	mr_cache_put(&c->_c);
-+
-+	/* QCA qca-mcs support - Start */
-+	/* Inform offload modules of the delete event */
-+	ip6mr_sync_entry_delete(&mc_origin, &mc_group);
-+	/* QCA qca-mcs support - End */
-+
- 	return 0;
- }
- 
-@@ -1435,6 +1680,12 @@ static int ip6mr_mfc_add(struct net *net
- 		call_ip6mr_mfc_entry_notifiers(net, FIB_EVENT_ENTRY_REPLACE,
- 					       c, mrt->id);
- 		mr6_netlink_event(mrt, c, RTM_NEWROUTE);
-+
-+		/* QCA qca-mcs support - Start */
-+		/* Inform offload modules of the update event */
-+		ip6mr_sync_entry_update(mrt, c);
-+		/* QCA qca-mcs support - End */
-+
- 		return 0;
- 	}
- 
-@@ -1497,6 +1748,10 @@ static int ip6mr_mfc_add(struct net *net
- 
- static void mroute_clean_tables(struct mr_table *mrt, int flags)
- {
-+	/* QCA qca-mcs support - Start */
-+	struct mfc6_cache *cache;
-+	struct in6_addr mc_origin, mc_group;
-+	/* QCA qca-mcs support - End */
- 	struct mr_mfc *c, *tmp;
- 	LIST_HEAD(list);
- 	int i;
-@@ -1519,13 +1774,23 @@ static void mroute_clean_tables(struct m
- 			if (((c->mfc_flags & MFC_STATIC) && !(flags & MRT6_FLUSH_MFC_STATIC)) ||
- 			    (!(c->mfc_flags & MFC_STATIC) && !(flags & MRT6_FLUSH_MFC)))
- 				continue;
-+			/* QCA qca-mcs support - Start */
-+			cache = (struct mfc6_cache *)c;
-+			memcpy(&mc_origin, &cache->mf6c_origin, sizeof(struct in6_addr));
-+			memcpy(&mc_group, &cache->mf6c_mcastgrp, sizeof(struct in6_addr));
-+			/* QCA qca-mcs support - End */
- 			rhltable_remove(&mrt->mfc_hash, &c->mnode, ip6mr_rht_params);
- 			list_del_rcu(&c->list);
- 			call_ip6mr_mfc_entry_notifiers(read_pnet(&mrt->net),
- 						       FIB_EVENT_ENTRY_DEL,
--						       (struct mfc6_cache *)c, mrt->id);
--			mr6_netlink_event(mrt, (struct mfc6_cache *)c, RTM_DELROUTE);
-+						       cache, mrt->id);
-+			mr6_netlink_event(mrt, cache, RTM_DELROUTE);
- 			mr_cache_put(c);
-+
-+			/* QCA qca-mcs support - Start */
-+			/* Inform offload modules of the delete event */
-+			ip6mr_sync_entry_delete(&mc_origin, &mc_group);
-+			/* QCA qca-mcs support - End */
- 		}
- 	}
- 
diff --git a/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch b/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch
index 31ead21f111f88..c0e7f973d97739 100644
--- a/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch
+++ b/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch
@@ -168,7 +168,7 @@
  void fib_del_ifaddr(struct in_ifaddr *, struct in_ifaddr *);
 --- a/net/8021q/vlan_core.c
 +++ b/net/8021q/vlan_core.c
-@@ -550,4 +550,52 @@ static int __init vlan_offload_init(void
+@@ -557,4 +557,52 @@ static int __init vlan_offload_init(void
  	return 0;
  }
  
@@ -508,7 +508,7 @@
  #endif
 --- a/net/core/neighbour.c
 +++ b/net/core/neighbour.c
-@@ -1209,7 +1209,21 @@ static void neigh_update_hhs(struct neig
+@@ -1216,7 +1216,21 @@ static void neigh_update_hhs(struct neig
  	}
  }
  
@@ -530,7 +530,7 @@
  
  /* Generic update routine.
     -- lladdr is new lladdr or NULL, if it is not supplied.
-@@ -1240,6 +1254,7 @@ static int __neigh_update(struct neighbo
+@@ -1247,6 +1261,7 @@ static int __neigh_update(struct neighbo
  	int notify = 0;
  	struct net_device *dev;
  	int update_isrouter = 0;
@@ -538,7 +538,7 @@
  
  	trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid);
  
-@@ -1254,6 +1269,8 @@ static int __neigh_update(struct neighbo
+@@ -1261,6 +1276,8 @@ static int __neigh_update(struct neighbo
  		new = old;
  		goto out;
  	}
@@ -547,7 +547,7 @@
  	if (!(flags & NEIGH_UPDATE_F_ADMIN) &&
  	    (old & (NUD_NOARP | NUD_PERMANENT)))
  		goto out;
-@@ -1291,6 +1308,11 @@ static int __neigh_update(struct neighbo
+@@ -1298,6 +1315,11 @@ static int __neigh_update(struct neighbo
  		   - compare new & old
  		   - if they are different, check override flag
  		 */
@@ -559,7 +559,7 @@
  		if ((old & NUD_VALID) &&
  		    !memcmp(lladdr, neigh->ha, dev->addr_len))
  			lladdr = neigh->ha;
-@@ -1413,8 +1435,11 @@ out:
+@@ -1420,8 +1442,11 @@ out:
  	if (((new ^ old) & NUD_PERMANENT) || ext_learn_change)
  		neigh_update_gc_list(neigh);
  
@@ -687,7 +687,7 @@
  		   const struct in6_addr *daddr)
 --- a/net/ipv6/route.c
 +++ b/net/ipv6/route.c
-@@ -3768,6 +3768,9 @@ out_free:
+@@ -3765,6 +3765,9 @@ out_free:
  	return ERR_PTR(err);
  }
  
@@ -697,7 +697,7 @@
  int ip6_route_add(struct fib6_config *cfg, gfp_t gfp_flags,
  		  struct netlink_ext_ack *extack)
  {
-@@ -3779,6 +3782,10 @@ int ip6_route_add(struct fib6_config *cf
+@@ -3776,6 +3779,10 @@ int ip6_route_add(struct fib6_config *cf
  		return PTR_ERR(rt);
  
  	err = __ip6_ins_rt(rt, &cfg->fc_nlinfo, extack);
@@ -708,7 +708,7 @@
  	fib6_info_release(rt);
  
  	return err;
-@@ -3800,6 +3807,9 @@ static int __ip6_del_rt(struct fib6_info
+@@ -3797,6 +3804,9 @@ static int __ip6_del_rt(struct fib6_info
  	err = fib6_del(rt, info);
  	spin_unlock_bh(&table->tb6_lock);
  
@@ -718,7 +718,7 @@
  out:
  	fib6_info_release(rt);
  	return err;
-@@ -6188,6 +6198,20 @@ static int ip6_route_dev_notify(struct n
+@@ -6185,6 +6195,20 @@ static int ip6_route_dev_notify(struct n
  	return NOTIFY_OK;
  }
  
diff --git a/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch b/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch
index 05846cf53ab293..a6be2c15fc9243 100644
--- a/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch
+++ b/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch
@@ -430,7 +430,7 @@
  #endif
 --- a/net/core/neighbour.c
 +++ b/net/core/neighbour.c
-@@ -1204,7 +1204,21 @@ static void neigh_update_hhs(struct neig
+@@ -1211,7 +1211,21 @@ static void neigh_update_hhs(struct neig
  	}
  }
  
@@ -452,7 +452,7 @@
  
  /* Generic update routine.
     -- lladdr is new lladdr or NULL, if it is not supplied.
-@@ -1235,6 +1249,7 @@ static int __neigh_update(struct neighbo
+@@ -1242,6 +1256,7 @@ static int __neigh_update(struct neighbo
  	int notify = 0;
  	struct net_device *dev;
  	int update_isrouter = 0;
@@ -460,7 +460,7 @@
  
  	trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid);
  
-@@ -1249,6 +1264,8 @@ static int __neigh_update(struct neighbo
+@@ -1256,6 +1271,8 @@ static int __neigh_update(struct neighbo
  		new = old;
  		goto out;
  	}
@@ -469,7 +469,7 @@
  	if (!(flags & NEIGH_UPDATE_F_ADMIN) &&
  	    (old & (NUD_NOARP | NUD_PERMANENT)))
  		goto out;
-@@ -1286,6 +1303,11 @@ static int __neigh_update(struct neighbo
+@@ -1293,6 +1310,11 @@ static int __neigh_update(struct neighbo
  		   - compare new & old
  		   - if they are different, check override flag
  		 */
@@ -481,7 +481,7 @@
  		if ((old & NUD_VALID) &&
  		    !memcmp(lladdr, neigh->ha, dev->addr_len))
  			lladdr = neigh->ha;
-@@ -1408,8 +1430,11 @@ out:
+@@ -1415,8 +1437,11 @@ out:
  	if (((new ^ old) & NUD_PERMANENT) || ext_learn_change)
  		neigh_update_gc_list(neigh);
  
@@ -561,7 +561,7 @@
  #endif
 --- a/net/ipv6/route.c
 +++ b/net/ipv6/route.c
-@@ -3878,6 +3878,9 @@ out_free:
+@@ -3875,6 +3875,9 @@ out_free:
  	return ERR_PTR(err);
  }
  
@@ -571,7 +571,7 @@
  int ip6_route_add(struct fib6_config *cfg, gfp_t gfp_flags,
  		  struct netlink_ext_ack *extack)
  {
-@@ -3889,6 +3892,10 @@ int ip6_route_add(struct fib6_config *cf
+@@ -3886,6 +3889,10 @@ int ip6_route_add(struct fib6_config *cf
  		return PTR_ERR(rt);
  
  	err = __ip6_ins_rt(rt, &cfg->fc_nlinfo, extack);
@@ -582,7 +582,7 @@
  	fib6_info_release(rt);
  
  	return err;
-@@ -3910,6 +3917,9 @@ static int __ip6_del_rt(struct fib6_info
+@@ -3907,6 +3914,9 @@ static int __ip6_del_rt(struct fib6_info
  	err = fib6_del(rt, info);
  	spin_unlock_bh(&table->tb6_lock);
  
@@ -592,7 +592,7 @@
  out:
  	fib6_info_release(rt);
  	return err;
-@@ -6353,6 +6363,20 @@ static int ip6_route_dev_notify(struct n
+@@ -6350,6 +6360,20 @@ static int ip6_route_dev_notify(struct n
  	return NOTIFY_OK;
  }
  
diff --git a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch
index 7d09e2df1a12b4..15ea1a5b777833 100644
--- a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch
+++ b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -2441,6 +2441,12 @@ config MIPS_VPE_LOADER
+@@ -2439,6 +2439,12 @@ config MIPS_VPE_LOADER
  	  Includes a loader for loading an elf relocatable object
  	  onto another VPE and running it.
  
diff --git a/target/linux/loongarch64/Makefile b/target/linux/loongarch64/Makefile
new file mode 100644
index 00000000000000..c87042053c72d1
--- /dev/null
+++ b/target/linux/loongarch64/Makefile
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Weijie Gao <hackpascal@gmail.com>
+
+include $(TOPDIR)/rules.mk
+
+ARCH:=loongarch64
+BOARD:=loongarch64
+BOARDNAME:=Loongson LoongArch
+FEATURES:=audio display squashfs ext4 pcie boot-part rootfs-part rtc usb targz
+
+KERNEL_PATCHVER:=6.6
+
+KERNELNAME:=vmlinuz.efi
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += \
+	partx-utils blkid e2fsprogs grub2-efi-loongarch64 htop wpad-openssl
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/loongarch64/base-files.mk b/target/linux/loongarch64/base-files.mk
new file mode 100644
index 00000000000000..88ba97d38a3d9f
--- /dev/null
+++ b/target/linux/loongarch64/base-files.mk
@@ -0,0 +1,8 @@
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_GRUB_SERIAL))
+ifeq ($(GRUB_SERIAL),)
+$(error This platform requires CONFIG_GRUB_SERIAL be set!)
+endif
+
+define Package/base-files/install-target
+	$(SED) "s#@GRUB_SERIAL@#$(GRUB_SERIAL)#" $(1)/etc/inittab
+endef
diff --git a/target/linux/loongarch64/base-files/etc/inittab b/target/linux/loongarch64/base-files/etc/inittab
new file mode 100644
index 00000000000000..584a4114d48056
--- /dev/null
+++ b/target/linux/loongarch64/base-files/etc/inittab
@@ -0,0 +1,4 @@
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+@GRUB_SERIAL@::askfirst:/usr/libexec/login.sh
+tty0::askfirst:/usr/libexec/login.sh
diff --git a/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi b/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi
new file mode 100644
index 00000000000000..4d9e92e544a203
--- /dev/null
+++ b/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+sanitize_name_loongarch64() {
+	sed -e '
+		y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/;
+		s/[^a-z0-9_-]\+/-/g;
+		s/^-//;
+		s/-$//;
+	' "$@"
+}
+
+do_sysinfo_loongarch64() {
+	local vendor product file
+
+	for file in sys_vendor board_vendor; do
+		vendor="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+		case "$vendor" in
+		empty | \
+		System\ manufacturer | \
+		To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+			continue
+			;;
+		esac
+		[ -n "$vendor" ] && break
+	done
+
+	for file in product_name board_name; do
+		product="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+		case "$vendor:$product" in
+		?*:empty | \
+		?*:System\ Product\ Name | \
+		?*:To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+			continue
+			;;
+		?*:?*)
+			break
+			;;
+		esac
+	done
+
+	[ -d "/sys/firmware/devicetree/base" ] && return
+
+	[ -n "$vendor" -a -n "$product" ] || return
+
+	mkdir -p /tmp/sysinfo
+
+	echo "$vendor $product" > /tmp/sysinfo/model
+
+	sanitize_name_loongarch64 /tmp/sysinfo/model > /tmp/sysinfo/board_name
+}
+
+boot_hook_add preinit_main do_sysinfo_loongarch64
diff --git a/target/linux/loongarch64/base-files/lib/preinit/79_move_config b/target/linux/loongarch64/base-files/lib/preinit/79_move_config
new file mode 100644
index 00000000000000..864d4dfa644fc7
--- /dev/null
+++ b/target/linux/loongarch64/base-files/lib/preinit/79_move_config
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+move_config() {
+	local partdev parttype=ext4
+
+	. /lib/upgrade/common.sh
+
+	if export_bootdevice && export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		if mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt; then
+			if [ -f "/mnt/$BACKUP_FILE" ]; then
+				mv -f "/mnt/$BACKUP_FILE" /
+			fi
+			umount /mnt
+		fi
+	fi
+}
+
+boot_hook_add preinit_mount_root move_config
diff --git a/target/linux/loongarch64/base-files/lib/upgrade/platform.sh b/target/linux/loongarch64/base-files/lib/upgrade/platform.sh
new file mode 100644
index 00000000000000..a0d4c2dcec7eb3
--- /dev/null
+++ b/target/linux/loongarch64/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+RAMFS_COPY_BIN="/usr/sbin/blkid"
+
+platform_check_image() {
+	local board=$(board_name)
+	local diskdev partdev diff
+	[ "$#" -gt 1 ] && return 1
+
+	v "Board is ${board}"
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "platform_check_image: Unable to determine upgrade device"
+		return 1
+	}
+
+	get_partitions "/dev/$diskdev" bootdisk
+
+	v "Extract boot sector from the image"
+	get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+	get_partitions /tmp/image.bs image
+
+	#compare tables
+	diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+
+	rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
+
+	if [ -n "$diff" ]; then
+		v "Partition layout has changed. Full image will be written."
+		ask_bool 0 "Abort" && exit 1
+		return 0
+	fi
+}
+
+platform_copy_config() {
+	local partdev parttype=ext4
+
+	if export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+		cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
+		umount /mnt
+	else
+		v "ERROR: Unable to find partition to copy config data to"
+	fi
+
+	sleep 5
+}
+
+# To avoid writing over any firmware
+# files (e.g ubootefi.var or firmware/X/ aka EBBR)
+# Copy efi/openwrt and efi/boot from the new image
+# to the existing ESP
+platform_do_upgrade_efi_system_partition() {
+	local image_file=$1
+	local target_partdev=$2
+	local image_efisp_start=$3
+	local image_efisp_size=$4
+
+	v "Updating ESP on ${target_partdev}"
+	NEW_ESP_DIR="/mnt/new_esp_loop"
+	CUR_ESP_DIR="/mnt/cur_esp"
+	mkdir "${NEW_ESP_DIR}"
+	mkdir "${CUR_ESP_DIR}"
+
+	get_image_dd "$image_file" of="/tmp/new_efi_sys_part.img" \
+		skip="$image_efisp_start" count="$image_efisp_size"
+
+	mount -t vfat -o loop -o ro /tmp/new_efi_sys_part.img "${NEW_ESP_DIR}"
+	if [ ! -d "${NEW_ESP_DIR}/efi/boot" ]; then
+		v "ERROR: Image does not contain EFI boot files (/efi/boot)"
+		return 1
+	fi
+
+	mount -t vfat "/dev/$partdev" "${CUR_ESP_DIR}"
+
+	for d in $(find "${NEW_ESP_DIR}/efi/" -mindepth 1 -maxdepth 1 -type d); do
+		v "Copying ${d}"
+		newdir_bname=$(basename "${d}")
+		rm -rf "${CUR_ESP_DIR}/efi/${newdir_bname}"
+		cp -r "${d}" "${CUR_ESP_DIR}/efi"
+		v "rm -rf \"${CUR_ESP_DIR}/efi/${newdir_bname}\""
+		v "cp -r \"${d}\" \"${CUR_ESP_DIR}/efi\""
+	done
+
+	umount "${NEW_ESP_DIR}"
+	umount "${CUR_ESP_DIR}"
+}
+
+platform_do_upgrade() {
+	local board=$(board_name)
+	local diskdev partdev diff
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "platform_do_upgrade: Unable to determine upgrade device"
+		return 1
+	}
+
+	sync
+
+	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
+		get_partitions "/dev/$diskdev" bootdisk
+
+		v "Extract boot sector from the image"
+		get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+		get_partitions /tmp/image.bs image
+
+		#compare tables
+		diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+	else
+		diff=1
+	fi
+
+	# Only change the partition table if sysupgrade -p is set,
+	# otherwise doing so could interfere with embedded "single storage"
+	# (e.g SoC boot from SD card) setups, as well as other user
+	# created storage (like uvol)
+	if [ -n "$diff" ] && [ "${UPGRADE_OPT_SAVE_PARTITIONS}" = "0" ]; then
+		# Need to remove partitions before dd, otherwise the partitions
+		# that are added after will have minor numbers offset
+		partx -d - "/dev/$diskdev"
+
+		get_image_dd "$1" of="/dev/$diskdev" bs=4096 conv=fsync
+
+		# Separate removal and addtion is necessary; otherwise, partition 1
+		# will be missing if it overlaps with the old partition 2
+		partx -a - "/dev/$diskdev"
+
+		return 0
+	fi
+
+	#iterate over each partition from the image and write it to the boot disk
+	while read part start size; do
+		if export_partdevice partdev $part; then
+			v "Writing image to /dev/$partdev..."
+			if [ "$part" = "1" ]; then
+				platform_do_upgrade_efi_system_partition \
+					$1 $partdev $start $size || return 1
+			else
+				v "Normal partition, doing DD"
+				get_image_dd "$1" of="/dev/$partdev" ibs=512 obs=1M skip="$start" \
+					count="$size" conv=fsync
+			fi
+		else
+			v "Unable to find partition $part device, skipped."
+		fi
+	done < /tmp/partmap.image
+
+	local parttype=ext4
+
+	if (blkid > /dev/null) && export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+		if export_partdevice partdev 2; then
+			THIS_PART_BLKID=$(blkid -o value -s PARTUUID "/dev/${partdev}")
+			v "Setting rootfs PARTUUID=${THIS_PART_BLKID}"
+			sed -i "s/\(PARTUUID=\)[a-f0-9-]\+/\1${THIS_PART_BLKID}/ig" \
+				/mnt/efi/openwrt/grub.cfg
+		fi
+		umount /mnt
+	fi
+	# Provide time for the storage medium to flush before system reset
+	# (despite the sync/umount it appears NVMe etc. do it in the background)
+	sleep 5
+}
diff --git a/target/linux/loongarch64/config-6.6 b/target/linux/loongarch64/config-6.6
new file mode 100644
index 00000000000000..596301f0f4ab12
--- /dev/null
+++ b/target/linux/loongarch64/config-6.6
@@ -0,0 +1,806 @@
+# CONFIG_16KB_2LEVEL is not set
+CONFIG_16KB_3LEVEL=y
+# CONFIG_4KB_3LEVEL is not set
+# CONFIG_4KB_4LEVEL is not set
+CONFIG_64BIT=y
+# CONFIG_64KB_2LEVEL is not set
+# CONFIG_64KB_3LEVEL is not set
+CONFIG_AC97_BUS=y
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_FFH is not set
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_MCFG=y
+# CONFIG_ACPI_PCI_SLOT is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_SLEEP=y
+# CONFIG_ACPI_SPCR_TABLE is not set
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+CONFIG_APERTURE_HELPERS=y
+CONFIG_ARCH_DISABLE_KASAN_INLINE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_IOREMAP is not set
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=12
+CONFIG_ARCH_MMAP_RND_BITS_MAX=18
+CONFIG_ARCH_MMAP_RND_BITS_MIN=12
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_STRICT_ALIGN=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+# CONFIG_ARCH_WRITECOMBINE is not set
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_FORCE=y
+# CONFIG_ATA_SFF is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTZ8866 is not set
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEBUG_FS_ZONED=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLK_RQ_ALLOC_TIME=y
+CONFIG_BLK_SED_OPAL=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CDROM=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_BPF is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_HUGETLB is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_LOONGSON2 is not set
+# CONFIG_COMMON_CLK_SI521XX is not set
+# CONFIG_COMMON_CLK_VC3 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_HAS_FPU=y
+CONFIG_CPU_HAS_LASX=y
+CONFIG_CPU_HAS_LBT=y
+CONFIG_CPU_HAS_LSX=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32_LOONGARCH is not set
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_DCB=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
+# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
+# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+# CONFIG_DMAPOOL_TEST is not set
+CONFIG_DMA_CMA=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DRM=y
+# CONFIG_DRM_ACCEL is not set
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_LOONGSON=y
+CONFIG_DRM_PANEL=y
+# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
+# CONFIG_DRM_SAMSUNG_DSIM is not set
+CONFIG_DRM_TTM=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+CONFIG_EFI_ZBOOT=y
+CONFIG_ELF_CORE=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_FAILOVER=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FANOTIFY=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_EFI=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_10x18 is not set
+# CONFIG_FONT_6x10 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_SUN8x16 is not set
+CONFIG_FONT_SUPPORT=y
+CONFIG_FONT_TER16x32=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_CACHE=y
+# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+# CONFIG_GPIO_DS4520 is not set
+# CONFIG_GPIO_FXL6408 is not set
+# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_LOONGSON_64BIT is not set
+CONFIG_HAMRADIO=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_LS2X is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INIT_STACK_ALL_ZERO=y
+# CONFIG_INIT_STACK_NONE is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_LOONGARCH_CPU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_SELFTEST is not set
+CONFIG_KCMP=y
+CONFIG_KEYS=y
+CONFIG_KSM=y
+CONFIG_L1_CACHE_SHIFT=6
+# CONFIG_LEDS_AW200XX is not set
+# CONFIG_LEDS_BD2606MVV is not set
+# CONFIG_LEDS_GROUP_MULTICOLOR is not set
+# CONFIG_LEDS_LM3697 is not set
+# CONFIG_LEDS_PCA995X is not set
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LIBFDT=y
+CONFIG_LIST_HARDENED=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOONGARCH=y
+CONFIG_LOONGARCH_PLATFORM_DEVICES=y
+# CONFIG_LOONGSON2_GUTS is not set
+# CONFIG_LOONGSON2_PM is not set
+# CONFIG_LOONGSON2_THERMAL is not set
+CONFIG_LOONGSON_EIOINTC=y
+CONFIG_LOONGSON_HTVEC=y
+CONFIG_LOONGSON_LAPTOP=y
+CONFIG_LOONGSON_LIOINTC=y
+CONFIG_LOONGSON_PCH_LPC=y
+CONFIG_LOONGSON_PCH_MSI=y
+CONFIG_LOONGSON_PCH_PIC=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo,bpf"
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_LOONGSON64=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+# CONFIG_MAX31827 is not set
+CONFIG_MAX_SKB_FRAGS=17
+# CONFIG_MEMCG is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_CS42L43_I2C is not set
+# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
+# CONFIG_MFD_MAX5970 is not set
+# CONFIG_MFD_MAX77541 is not set
+# CONFIG_MFD_RK8XX_I2C is not set
+# CONFIG_MFD_RK8XX_SPI is not set
+# CONFIG_MFD_SMPRO is not set
+# CONFIG_MFD_TPS65219 is not set
+# CONFIG_MFD_TPS6594_I2C is not set
+# CONFIG_MFD_TPS6594_SPI is not set
+CONFIG_MIGRATION=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MODULE_DEBUG is not set
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=64
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_VERBOSE_ERRORS=y
+# CONFIG_N_HDLC is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OID_REGISTRY=y
+# CONFIG_OVERLAY_FS_DEBUG is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_EXTENSION=y
+CONFIG_PAGE_POISONING=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DPC=y
+# CONFIG_PCIE_EDR is not set
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+# CONFIG_PCI_DYNAMIC_OF_NODES is not set
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOONGSON=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCPU_DEV_REFCNT=y
+# CONFIG_PDS_CORE is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_3LEVEL=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_DEBUG=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_STD_PARTITION=""
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_PTP_1588_CLOCK_MOCK is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+# CONFIG_RANDOM_KMALLOC_CACHES is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_RCU_CPU_STALL_CPUTIME is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_LOONGSON=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_HOST=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SENSORS_HS3001 is not set
+# CONFIG_SENSORS_MC34VR500 is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI1XXXX is not set
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+# CONFIG_SLAB_DEPRECATED is not set
+# CONFIG_SLUB_TINY is not set
+CONFIG_SMP=y
+CONFIG_SND=y
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_CTL_LED=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_HDA=y
+# CONFIG_SND_HDA_CODEC_ANALOG is not set
+# CONFIG_SND_HDA_CODEC_CA0110 is not set
+# CONFIG_SND_HDA_CODEC_CA0132 is not set
+# CONFIG_SND_HDA_CODEC_CIRRUS is not set
+# CONFIG_SND_HDA_CODEC_CMEDIA is not set
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+# CONFIG_SND_HDA_CODEC_REALTEK is not set
+# CONFIG_SND_HDA_CODEC_SI3054 is not set
+# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
+# CONFIG_SND_HDA_CODEC_VIA is not set
+CONFIG_SND_HDA_CORE=y
+# CONFIG_SND_HDA_CTL_DEV_ID is not set
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_HWDEP=y
+# CONFIG_SND_HDA_INPUT_BEEP is not set
+CONFIG_SND_HDA_INTEL=y
+# CONFIG_SND_HDA_PATCH_LOADER is not set
+# CONFIG_SND_HDA_RECONFIG is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
+# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
+CONFIG_SND_HWDEP=y
+CONFIG_SND_INTEL_DSP_CONFIG=y
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQ_DEVICE=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_SEQ_MIDI=y
+CONFIG_SND_SEQ_MIDI_EVENT=y
+CONFIG_SND_SEQ_VIRMIDI=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_LOONGSON_CARD=y
+CONFIG_SND_SOC_LOONGSON_I2S_PCI=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_VIRMIDI=y
+CONFIG_SND_VMASTER=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_LOONGSON_CORE=y
+CONFIG_SPI_LOONGSON_PCI=y
+CONFIG_SPI_LOONGSON_PLATFORM=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_PCI1XXXX is not set
+# CONFIG_SPI_SN_F_OSPI is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+# CONFIG_SWIOTLB_DYNAMIC is not set
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y
+CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+# CONFIG_TEST_DHRY is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_QUOTA is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UCS2_STRING=y
+# CONFIG_UEVENT_HELPER is not set
+# CONFIG_UNWINDER_GUESS is not set
+CONFIG_UNWINDER_PROLOGUE=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UAS=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USERFAULTFD=y
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+# CONFIG_VCAP is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGA_CONSOLE=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIRTIO_VSOCKETS_COMMON=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VSOCKETS=y
+CONFIG_VSOCKETS_LOOPBACK=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WPCM450_SOC is not set
+# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+# CONFIG_ZONEFS_FS is not set
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/loongarch64/image/Makefile b/target/linux/loongarch64/image/Makefile
new file mode 100644
index 00000000000000..c9e5d60c5d3fb8
--- /dev/null
+++ b/target/linux/loongarch64/image/Makefile
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Weijie Gao <hackpascal@gmail.com>
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+GRUB2_VARIANT =
+GRUB_TERMINALS =
+GRUB_SERIAL_CONFIG =
+GRUB_TERMINAL_CONFIG =
+GRUB_CONSOLE_CMDLINE =
+
+ifneq ($(CONFIG_GRUB_CONSOLE),)
+  GRUB_CONSOLE_CMDLINE += console=tty0
+  GRUB_TERMINALS += console
+endif
+
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_GRUB_SERIAL))
+
+GRUB_CONSOLE_CMDLINE += console=$(GRUB_SERIAL),$(CONFIG_GRUB_BAUDRATE)n8$(if $(CONFIG_GRUB_FLOWCONTROL),r,)
+GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1 --rtscts=$(if $(CONFIG_GRUB_FLOWCONTROL),on,off)
+GRUB_TERMINALS += serial
+
+GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS)
+
+ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+ROOTPART:=$(if $(ROOTPART),$(ROOTPART),PARTUUID=$(IMG_PART_SIGNATURE)-02)
+GPT_ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+GPT_ROOTPART:=$(if $(GPT_ROOTPART),$(GPT_ROOTPART),PARTUUID=$(shell echo $(IMG_PART_DISKGUID) | sed 's/00$$/02/'))
+
+GRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT))
+GRUB_TITLE:=$(call qstrip,$(CONFIG_GRUB_TITLE))
+
+BOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS))
+
+define Build/combined
+	$(INSTALL_DIR) $@.boot/
+	$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/efi/openwrt/
+	$(INSTALL_DIR) $@.boot/efi/boot
+	$(CP) $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi $@.boot/efi/boot/
+	KERNELPARTTYPE=ef FAT_TYPE="32" PADDING="1" SIGNATURE="$(IMG_PART_SIGNATURE)" \
+		GUID="$(IMG_PART_DISKGUID)" $(SCRIPT_DIR)/gen_image_generic.sh \
+		$@ \
+		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+		256
+endef
+
+define Build/grub-config
+	rm -fR $@.boot
+	$(INSTALL_DIR) $@.boot/efi/openwrt/
+	sed \
+		-e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \
+		-e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \
+		-e 's#@ROOTPART@#root=$(ROOTPART) rootwait#g' \
+		-e 's#@GPT_ROOTPART@#root=$(GPT_ROOTPART) rootwait#g' \
+		-e 's#@CMDLINE@#$(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE)#g' \
+		-e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \
+		-e 's#@TITLE@#$(GRUB_TITLE)#g' \
+		-e 's#@KERNEL_NAME@#$(KERNEL_NAME)#g' \
+		./grub-$(1).cfg > $@.boot/efi/openwrt/grub.cfg
+endef
+
+define Device/Default
+  IMAGE/rootfs.img := append-rootfs | pad-to $(ROOTFS_PARTSIZE)
+  IMAGE/rootfs.img.gz := append-rootfs | pad-to $(ROOTFS_PARTSIZE) | gzip
+  IMAGE/combined-efi.img := grub-config efi | combined | append-metadata
+  IMAGE/combined-efi.img.gz := grub-config efi | combined | gzip | append-metadata
+  ifeq ($(CONFIG_TARGET_IMAGES_GZIP),y)
+    IMAGES-y := rootfs.img.gz
+    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img.gz
+  else
+    IMAGES-y := rootfs.img
+    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img
+  endif
+  KERNEL := kernel-bin
+  KERNEL_INSTALL := 1
+  KERNEL_NAME := vmlinuz.efi
+  IMAGES := $$(IMAGES-y)
+  ARTIFACTS := $$(ARTIFACTS-y)
+  SUPPORTED_DEVICES :=
+endef
+
+define Device/generic
+  DEVICE_VENDOR := Generic
+  DEVICE_MODEL := LoongArch64
+  DEVICE_PACKAGES += kmod-r8169 kmod-drm-amdgpu
+endef
+TARGET_DEVICES += generic
+
+$(eval $(call BuildImage))
diff --git a/target/linux/loongarch64/image/grub-efi.cfg b/target/linux/loongarch64/image/grub-efi.cfg
new file mode 100644
index 00000000000000..fd329e41e0ff2d
--- /dev/null
+++ b/target/linux/loongarch64/image/grub-efi.cfg
@@ -0,0 +1,14 @@
+@SERIAL_CONFIG@
+@TERMINAL_CONFIG@
+
+set default="0"
+set timeout="@TIMEOUT@"
+
+menuentry "@TITLE@" {
+	search --set=root --label kernel
+	linux /efi/openwrt/@KERNEL_NAME@ @GPT_ROOTPART@ @CMDLINE@ noinitrd
+}
+menuentry "@TITLE@ (failsafe)" {
+	search --set=root --label kernel
+	linux /efi/openwrt/@KERNEL_NAME@ failsafe=true @GPT_ROOTPART@ @CMDLINE@ noinitrd
+}
diff --git a/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts b/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts
new file mode 100644
index 00000000000000..5371e2ae0235d5
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "mt7981.dtsi"
+
+/ {
+	model = "IMOU LC-HX3001";
+	compatible = "imou,lc-hx3001", "mediatek,mt7981";
+
+	aliases {
+		serial0 = &uart0;
+
+		led-boot = &led_power;
+		led-failsafe = &led_power;
+		led-running = &led_power;
+		led-upgrade = &led_power;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power: power {
+			label = "green:power";
+			gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		wifi {
+			label = "green:wifi";
+			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		wan_red {
+			label = "red:wan";
+			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+		};
+
+		wan_green {
+			label = "green:wan";
+			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		lan {
+			label = "green:lan";
+			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+	};
+};
+
+&mdio_bus {
+	switch: switch@0 {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand@0 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		mediatek,nmbm;
+		mediatek,bmt-max-ratio = <1>;
+		mediatek,bmt-max-reserved-blocks = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x0000000 0x0100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+			};
+
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x0180000 0x0200000>;
+				read-only;
+			};
+
+			partition@380000 {
+				label = "FIP";
+				reg = <0x0380000 0x0200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x0580000 0x7280000>;
+			};
+		};
+	};
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+		};
+
+		port@6 {
+			reg = <6>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>; /* bias-disable */
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>; /* bias-disable */
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	status = "okay";
+
+	mediatek,mtd-eeprom = <&factory 0x0>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts
new file mode 100644
index 00000000000000..dedd33a940dc51
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+	model = "Ruijie RG-X60 Pro";
+	compatible = "ruijie,rg-x60-pro", "mediatek,mt7986a";
+
+	aliases {
+		serial0 = &uart0;
+		led-boot = &led_system;
+		led-failsafe = &led_alarm;
+		led-running = &led_system;
+		led-upgrade = &led_alarm;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x11002000";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x20000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		mesh {
+			label = "mesh";
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_MISC>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_alarm: status_purple {
+			label = "purple:status";
+			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led_system: status_white {
+			label = "white:status";
+			gpios = <&pio 22 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-handle = <&phy7>;
+		phy-mode = "2500base-x";
+	};
+
+	mdio: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&mdio {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	phy7: phy@7 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <7>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+		realtek,aldps-enable;
+	};
+};
+
+&pio {
+	spi_flash_pins: spi-flash-pins-33-to-38 {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>; /* bias-disable */
+		};
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <8>;
+			mediatek,pull-down-adv = <0>; /* bias-disable */
+		};
+	};
+
+	wf_2g_5g_pins: wf_2g_5g-pins {
+		mux {
+			function = "wifi";
+			groups = "wf_2g", "wf_5g";
+		};
+		conf {
+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+			drive-strength = <4>;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+
+		spi-max-frequency = <20000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		mediatek,nmbm;
+		mediatek,bmt-max-ratio = <1>;
+		mediatek,bmt-max-reserved-blocks = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x000000 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x100000 0x80000>;
+				read-only;
+			};
+
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x200000>;
+				read-only;
+			};
+
+			partition@380000 {
+				label = "FIP";
+				reg = <0x380000 0x200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "product_info";
+				reg = <0x580000 0x80000>;
+				read-only;
+			};
+
+			partition@600000 {
+				label = "kdump";
+				reg = <0x600000 0x80000>;
+				read-only;
+			};
+
+			partition@680000 {
+				label = "ubi";
+				reg = <0x680000 0x3f00000>;
+			};
+		};
+	};
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+		};
+
+		port@6 {
+			reg = <6>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&wmac {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&wf_2g_5g_pins>;
+
+	mediatek,mtd-eeprom = <&factory 0x0>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
new file mode 100644
index 00000000000000..98dbf8d6913ff1
--- /dev/null
+++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a-rfb-spim-nand.dtsi"
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+/ {
+	model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
+	compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
+		     "mediatek,mt7988a-rfb-snand",
+		     "mediatek,mt7988";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x40000000>;
+	};
+};
+
+&eth {
+	pinctrl-0 = <&mdio0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "internal";
+
+		fixed-link {
+			speed = <10000>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "internal";
+		phy-connection-type = "internal";
+		phy = <&phy15>;
+	};
+
+	gmac2: mac@2 {
+		compatible = "mediatek,eth-mac";
+		reg = <2>;
+		phy-mode = "10gbase-kr";
+		phy-connection-type = "10gbase-kr";
+		phy = <&phy8>;
+	};
+
+	mdio0: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* external Aquantia AQR113C */
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reset-gpios = <&pio 72 1>;
+			reset-assert-us = <100000>;
+			reset-deassert-us = <221000>;
+		};
+
+		/* external Aquantia AQR113C */
+		phy8: ethernet-phy@8 {
+			reg = <8>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reset-gpios = <&pio 71 1>;
+			reset-assert-us = <100000>;
+			reset-deassert-us = <221000>;
+		};
+
+		/* external Maxlinear GPY211C */
+		phy5: ethernet-phy@5 {
+			reg = <5>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			phy-mode = "2500base-x";
+		};
+
+		/* external Maxlinear GPY211C */
+		phy13: ethernet-phy@13 {
+			reg = <13>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			phy-mode = "2500base-x";
+		};
+
+		/* internal 2.5G PHY */
+		phy15: ethernet-phy@15 {
+			reg = <15>;
+			pinctrl-names = "i2p5gbe-led";
+			pinctrl-0 = <&i2p5gbe_led0_pins>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			phy-mode = "internal";
+		};
+	};
+};
+
+&switch {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan0";
+			phy-mode = "internal";
+			phy-handle = <&gsw_phy0>;
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan1";
+			phy-mode = "internal";
+			phy-handle = <&gsw_phy1>;
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+			phy-mode = "internal";
+			phy-handle = <&gsw_phy2>;
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan3";
+			phy-mode = "internal";
+			phy-handle = <&gsw_phy3>;
+		};
+
+		port@6 {
+			reg = <6>;
+			ethernet = <&gmac0>;
+			phy-mode = "internal";
+
+			fixed-link {
+				speed = <10000>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gsw_phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-id03a2.9481";
+			reg = <0>;
+			phy-mode = "internal";
+			pinctrl-names = "gbe-led";
+			pinctrl-0 = <&gbe0_led0_pins>;
+			nvmem-cells = <&phy_calibration_p0>;
+			nvmem-cell-names = "phy-cal-data";
+		};
+
+		gsw_phy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-id03a2.9481";
+			reg = <1>;
+			phy-mode = "internal";
+			pinctrl-names = "gbe-led";
+			pinctrl-0 = <&gbe1_led0_pins>;
+			nvmem-cells = <&phy_calibration_p1>;
+			nvmem-cell-names = "phy-cal-data";
+		};
+
+		gsw_phy2: ethernet-phy@2 {
+			compatible = "ethernet-phy-id03a2.9481";
+			reg = <2>;
+			phy-mode = "internal";
+			pinctrl-names = "gbe-led";
+			pinctrl-0 = <&gbe2_led0_pins>;
+			nvmem-cells = <&phy_calibration_p2>;
+			nvmem-cell-names = "phy-cal-data";
+		};
+
+		gsw_phy3: ethernet-phy@3 {
+			compatible = "ethernet-phy-id03a2.9481";
+			reg = <3>;
+			phy-mode = "internal";
+			pinctrl-names = "gbe-led";
+			pinctrl-0 = <&gbe3_led0_pins>;
+			nvmem-cells = <&phy_calibration_p3>;
+			nvmem-cell-names = "phy-cal-data";
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi
new file mode 100644
index 00000000000000..e4c05712509ee4
--- /dev/null
+++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a-rfb.dtsi"
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+	};
+
+};
+
+&spi_nand {
+	mediatek,nmbm;
+	mediatek,bmt-max-ratio = <1>;
+	mediatek,bmt-max-reserved-blocks = <64>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "BL2";
+			reg = <0x00000 0x0100000>;
+			read-only;
+		};
+
+		partition@100000 {
+			label = "u-boot-env";
+			reg = <0x0100000 0x0080000>;
+		};
+
+		factory: partition@180000 {
+			label = "Factory";
+			reg = <0x180000 0x0400000>;
+		};
+
+		partition@580000 {
+			label = "FIP";
+			reg = <0x580000 0x0200000>;
+		};
+
+		partition@780000 {
+			label = "ubi";
+			reg = <0x780000 0x7080000>;
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi
new file mode 100644
index 00000000000000..423b3860c6c64e
--- /dev/null
+++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&eth {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+&pcie2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_pins>;
+	status = "disabled";
+};
+
+&pcie3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_pins>;
+	status = "okay";
+};
+
+&ssusb0 {
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&tphy {
+	status = "okay";
+};
+
+&pio {
+	pcie0_pins: pcie0-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+				 "pcie_wake_n0_0";
+		};
+	};
+
+	pcie1_pins: pcie1-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+				 "pcie_wake_n1_0";
+		};
+	};
+
+	pcie2_pins: pcie2-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+				 "pcie_wake_n2_0";
+		};
+	};
+
+	pcie3_pins: pcie3-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+				 "pcie_wake_n3_0";
+		};
+	};
+};
+
+&spi0 {
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&xphy {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
new file mode 100644
index 00000000000000..13ad39500d1b93
--- /dev/null
+++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "mediatek,mt7988";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clk40m: oscillator@0 {
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+		#clock-cells = <0>;
+		clock-output-names = "clkxtal";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			enable-method = "psci";
+			reg = <0x0>;
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			enable-method = "psci";
+			reg = <0x1>;
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			enable-method = "psci";
+			reg = <0x2>;
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			enable-method = "psci";
+			reg = <0x3>;
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
+			mediatek,cci = <&cci>;
+		};
+
+		cluster0_opp: opp_table0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+			opp00 {
+				opp-hz = /bits/ 64 <800000000>;
+				opp-microvolt = <850000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <1100000000>;
+				opp-microvolt = <850000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <1500000000>;
+				opp-microvolt = <850000>;
+			};
+			opp03 {
+				opp-hz = /bits/ 64 <1800000000>;
+				opp-microvolt = <900000>;
+			};
+		};
+	};
+
+	cci: cci {
+		compatible = "mediatek,mt7988-cci",
+			     "mediatek,mt8183-cci";
+		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+			 <&topckgen CLK_TOP_XTAL>;
+		clock-names = "cci", "intermediate";
+		operating-points-v2 = <&cci_opp>;
+	};
+
+	cci_opp: opp_table_cci {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp00 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <850000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <660000000>;
+			opp-microvolt = <850000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <850000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <900000>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a73-pmu";
+		interrupt-parent = <&gic>;
+		interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible  = "arm,psci-0.2";
+		method      = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon@43000000 {
+			reg = <0 0x43000000 0 0x30000>;
+			no-map;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		gic: interrupt-controller@c000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+			      <0 0x0c080000 0 0x200000>, /* GICR */
+			      <0 0x0c400000 0 0x2000>,   /* GICC */
+			      <0 0x0c410000 0 0x1000>,   /* GICH */
+			      <0 0x0c420000 0 0x2000>;   /* GICV */
+
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		phyfw: phy-firmware@f000000 {
+			compatible = "mediatek,2p5gphy-fw";
+			reg = <0 0x0f000000 0 0x8000>,
+			      <0 0x0f100000 0 0x20000>,
+			      <0 0x0f0f0000 0 0x200>;
+		};
+
+		infracfg: infracfg@10001000 {
+			compatible = "mediatek,mt7988-infracfg", "syscon";
+			reg = <0 0x10001000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		topckgen: topckgen@1001b000 {
+			compatible = "mediatek,mt7988-topckgen", "syscon";
+			reg = <0 0x1001b000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		watchdog: watchdog@1001c000 {
+			compatible = "mediatek,mt7988-wdt",
+				     "mediatek,mt6589-wdt",
+				     "syscon";
+			reg = <0 0x1001c000 0 0x1000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			#reset-cells = <1>;
+		};
+
+		apmixedsys: apmixedsys@1001e000 {
+			compatible = "mediatek,mt7988-apmixedsys";
+			reg = <0 0x1001e000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		pio: pinctrl@1001f000 {
+			compatible = "mediatek,mt7988-pinctrl";
+			reg = <0 0x1001f000 0 0x1000>,
+			<0 0x11c10000 0 0x1000>,
+			<0 0x11d00000 0 0x1000>,
+			<0 0x11d20000 0 0x1000>,
+			<0 0x11e00000 0 0x1000>,
+			<0 0x11f00000 0 0x1000>,
+			<0 0x1000b000 0 0x1000>;
+			reg-names = "gpio_base", "iocfg_tr_base",
+				    "iocfg_br_base", "iocfg_rb_base",
+				    "iocfg_lb_base", "iocfg_tl_base", "eint";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 83>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+
+			mdio0_pins: mdio0-pins {
+				mux {
+					function = "eth";
+					groups = "mdc_mdio0";
+				};
+
+				conf {
+					groups = "mdc_mdio0";
+					drive-strength = <MTK_DRIVE_8mA>;
+				};
+			};
+
+			i2c0_pins: i2c0-pins-g0 {
+				mux {
+					function = "i2c";
+					groups = "i2c0_1";
+				};
+			};
+
+			i2c1_pins: i2c1-pins-g0 {
+				mux {
+					function = "i2c";
+					groups = "i2c1_0";
+				};
+			};
+
+			i2c2_pins: i2c2-pins-g0 {
+				mux {
+					function = "i2c";
+					groups = "i2c2_1";
+				};
+			};
+
+			gbe0_led0_pins: gbe0-pins {
+				mux {
+					function = "led";
+					groups = "gbe0_led0";
+				};
+			};
+
+			gbe1_led0_pins: gbe1-pins {
+				mux {
+					function = "led";
+					groups = "gbe1_led0";
+				};
+			};
+
+			gbe2_led0_pins: gbe2-pins {
+				mux {
+					function = "led";
+					groups = "gbe2_led0";
+				};
+			};
+
+			gbe3_led0_pins: gbe3-pins {
+				mux {
+					function = "led";
+					groups = "gbe3_led0";
+				};
+			};
+
+			i2p5gbe_led0_pins: 2p5gbe-pins {
+				mux {
+					function = "led";
+					groups = "2p5gbe_led0";
+				};
+			};
+		};
+
+		boottrap: boottrap@1001f6f0 {
+			compatible = "mediatek,boottrap";
+			reg = <0 0x1001f6f0 0 0x4>;
+		};
+
+		sgmiisys0: syscon@10060000 {
+			compatible = "mediatek,mt7988-sgmiisys",
+				     "mediatek,mt7988-sgmiisys_0",
+				     "syscon";
+			reg = <0 0x10060000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		sgmiisys1: syscon@10070000 {
+			compatible = "mediatek,mt7988-sgmiisys",
+				     "mediatek,mt7988-sgmiisys_1",
+				     "syscon";
+			reg = <0 0x10070000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		usxgmiisys0: usxgmiisys@10080000 {
+			compatible = "mediatek,mt7988-usxgmiisys",
+				     "mediatek,mt7988-usxgmiisys_0",
+				     "syscon";
+			reg = <0 0x10080000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		usxgmiisys1: usxgmiisys@10081000 {
+			compatible = "mediatek,mt7988-usxgmiisys",
+				     "mediatek,mt7988-usxgmiisys_1",
+				     "syscon";
+			reg = <0 0x10081000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		xfi_pextp0: xfi_pextp@11f20000 {
+			compatible = "mediatek,mt7988-xfi_pextp",
+				     "mediatek,mt7988-xfi_pextp_0",
+				     "syscon";
+			reg = <0 0x11f20000 0 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		xfi_pextp1: xfi_pextp@11f30000 {
+			compatible = "mediatek,mt7988-xfi_pextp",
+				     "mediatek,mt7988-xfi_pextp_1",
+				     "syscon";
+			reg = <0 0x11f30000 0 0x10000>;
+			#clock-cells = <1>;
+		};
+
+		xfi_pll: xfi_pll@11f40000 {
+			compatible = "mediatek,mt7988-xfi_pll", "syscon";
+			reg = <0 0x11f40000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		mcusys: mcusys@100e0000 {
+			compatible = "mediatek,mt7988-mcusys", "syscon";
+			reg = <0 0x100e0000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		uart0: serial@11000000 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000000 0 0x100>;
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			 * 8250-mtk driver don't control "baud" clock since commit
+			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+			 * still need to be passed to the driver to prevent probe fail
+			 */
+			clocks = <&topckgen CLK_TOP_UART_SEL>,
+				 <&infracfg CLK_INFRA_52M_UART0_CK>;
+			clock-names = "baud", "bus";
+			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+						 <&topckgen CLK_TOP_UART_SEL>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@11003000 {
+			compatible = "mediatek,mt7988-i2c",
+				     "mediatek,mt7981-i2c";
+			reg = <0 0x11003000 0 0x1000>,
+			      <0 0x10217080 0 0x80>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
+			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@11004000 {
+			compatible = "mediatek,mt7988-i2c",
+				     "mediatek,mt7981-i2c";
+			reg = <0 0x11004000 0 0x1000>,
+			      <0 0x10217100 0 0x80>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
+			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@11005000 {
+			compatible = "mediatek,mt7988-i2c",
+				"mediatek,mt7981-i2c";
+			reg = <0 0x11005000 0 0x1000>,
+			      <0 0x10217180 0 0x80>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
+			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi0: spi@11007000 {
+			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
+			reg = <0 0x11007000 0 0x100>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg CLK_INFRA_104M_SPI0>,
+				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk",
+				      "spi-hclk";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		pcie2: pcie@11280000 {
+			compatible = "mediatek,mt7988-pcie",
+				     "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11280000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <3>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x20000000 0x00
+				  0x20000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x20200000 0x00
+				  0x20200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			status = "disabled";
+
+			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+			phy-names = "pcie-phy";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+					<0 0 0 2 &pcie_intc2 1>,
+					<0 0 0 3 &pcie_intc2 2>,
+					<0 0 0 4 &pcie_intc2 3>;
+			pcie_intc2: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie3: pcie@11290000 {
+			compatible = "mediatek,mt7988-pcie",
+				     "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11290000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <2>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x28000000 0x00
+				  0x28000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x28200000 0x00
+				  0x28200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+					<0 0 0 2 &pcie_intc3 1>,
+					<0 0 0 3 &pcie_intc3 2>,
+					<0 0 0 4 &pcie_intc3 3>;
+			pcie_intc3: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie0: pcie@11300000 {
+			compatible = "mediatek,mt7988-pcie",
+				     "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11300000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <0>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x30000000 0x00
+				  0x30000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x30200000 0x00
+				  0x30200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			pcie_intc0: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie1: pcie@11310000 {
+			compatible = "mediatek,mt7988-pcie",
+				     "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11310000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <1>;
+			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x38000000 0x00
+				  0x38000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x38200000 0x00
+				  0x38200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		ssusb0: usb@11190000 {
+			compatible = "mediatek,mt7988-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11190000 0 0x2e00>,
+			      <0 0x11193e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&xphyu2port0 PHY_TYPE_USB2>,
+			       <&xphyu3port0 PHY_TYPE_USB3>;
+			clocks = <&infracfg CLK_INFRA_USB_SYS>,
+				 <&infracfg CLK_INFRA_USB_XHCI>,
+				 <&infracfg CLK_INFRA_USB_REF>,
+				 <&infracfg CLK_INFRA_66M_USB_HCK>,
+				 <&infracfg CLK_INFRA_133M_USB_HCK>;
+			clock-names = "sys_ck",
+				      "xhci_ck",
+				      "ref_ck",
+				      "mcu_ck",
+				      "dma_ck";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			mediatek,p0_speed_fixup;
+			status = "disabled";
+		};
+
+		ssusb1: usb@11200000 {
+			compatible = "mediatek,mt7988-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x2e00>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&tphyu2port0 PHY_TYPE_USB2>,
+			       <&tphyu3port0 PHY_TYPE_USB3>;
+			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
+				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
+				 <&infracfg CLK_INFRA_USB_CK_P1>,
+				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
+				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
+			clock-names = "sys_ck",
+				      "xhci_ck",
+				      "ref_ck",
+				      "mcu_ck",
+				      "dma_ck";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+		};
+
+		tphy: tphy@11c50000 {
+			compatible = "mediatek,mt7988",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+			tphyu2port0: usb-phy@11c50000 {
+				reg = <0 0x11c50000 0 0x700>;
+				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+			tphyu3port0: usb-phy@11c50700 {
+				reg = <0 0x11c50700 0 0x900>;
+				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				mediatek,usb3-pll-ssc-delta;
+				mediatek,usb3-pll-ssc-delta1;
+			};
+		};
+
+		topmisc: topmisc@11d10000 {
+			compatible = "mediatek,mt7988-topmisc", "syscon",
+				     "mediatek,mt7988-power-controller";
+			reg = <0 0x11d10000 0 0x10000>;
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		xphy: xphy@11e10000 {
+			compatible = "mediatek,mt7988",
+				     "mediatek,xsphy";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			xphyu2port0: usb-phy@11e10000 {
+				reg = <0 0x11e10000 0 0x400>;
+				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			xphyu3port0: usb-phy@11e13000 {
+				reg = <0 0x11e13400 0 0x500>;
+				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				mediatek,syscon-type = <&topmisc 0x218 0>;
+			};
+		};
+
+		efuse: efuse@11f50000 {
+			compatible = "mediatek,efuse";
+			reg = <0 0x11f50000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			lvts_calibration: calib@918 {
+				reg = <0x918 0x28>;
+			};
+			phy_calibration_p0: calib@940 {
+				reg = <0x940 0x10>;
+			};
+			phy_calibration_p1: calib@954 {
+				reg = <0x954 0x10>;
+			};
+			phy_calibration_p2: calib@968 {
+				reg = <0x968 0x10>;
+			};
+			phy_calibration_p3: calib@97c {
+				reg = <0x97c 0x10>;
+			};
+			cpufreq_calibration: calib@278 {
+				reg = <0x278 0x1>;
+			};
+		};
+
+		ethsys: syscon@15000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "mediatek,mt7988-ethsys", "syscon";
+			reg = <0 0x15000000 0 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		switch: switch@15020000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "mediatek,mt7988-switch";
+			reg = <0 0x15020000 0 0x8000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ethrst 0>;
+		};
+
+		ethwarp: syscon@15031000 {
+			compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
+			reg = <0 0x15031000 0 0x1000>;
+			#clock-cells = <1>;
+
+			ethrst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+				ti,reset-bits = <
+					0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
+				>;
+			};
+		};
+
+		eth: ethernet@15100000 {
+			compatible = "mediatek,mt7988-eth";
+			reg = <0 0x15100000 0 0x80000>,
+			      <0 0x15400000 0 0x380000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
+				 <&ethsys CLK_ETHDMA_XGP2_EN>,
+				 <&ethsys CLK_ETHDMA_XGP3_EN>,
+				 <&ethsys CLK_ETHDMA_FE_EN>,
+				 <&ethsys CLK_ETHDMA_GP2_EN>,
+				 <&ethsys CLK_ETHDMA_GP1_EN>,
+				 <&ethsys CLK_ETHDMA_GP3_EN>,
+				 <&ethsys CLK_ETHDMA_ESW_EN>,
+				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
+				 <&sgmiisys0 CLK_SGM0_TX_EN>,
+				 <&sgmiisys0 CLK_SGM0_RX_EN>,
+				 <&sgmiisys1 CLK_SGM1_TX_EN>,
+				 <&sgmiisys1 CLK_SGM1_RX_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
+				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
+				 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+				 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+				 <&topckgen CLK_TOP_SGM_0_SEL>,
+				 <&topckgen CLK_TOP_SGM_1_SEL>,
+				 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
+				 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
+				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
+				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
+				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+				 <&topckgen CLK_TOP_ETH_MII_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
+			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
+				      "gp3", "esw", "crypto", "sgmii_tx250m",
+				      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+				      "ethwarp_wocpu2", "ethwarp_wocpu1",
+				      "ethwarp_wocpu0", "top_usxgmii0_sel",
+				      "top_usxgmii1_sel", "top_sgm0_sel",
+				      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
+				      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+				      "top_eth_sys_sel", "top_eth_xgmii_sel",
+				      "top_eth_mii_sel", "top_netsys_sel",
+				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+				      "top_netsys_sync_250m_sel",
+				      "top_netsys_ppefb_250m_sel",
+				      "top_netsys_warp_sel";
+			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+					  <&topckgen CLK_TOP_SGM_0_SEL>,
+					  <&topckgen CLK_TOP_SGM_1_SEL>;
+			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+						 <&topckgen CLK_TOP_NET1PLL_D4>,
+						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+						 <&apmixedsys CLK_APMIXED_SGMPLL>,
+						 <&apmixedsys CLK_APMIXED_SGMPLL>;
+			mediatek,ethsys = <&ethsys>;
+			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+			mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
+			mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
+			mediatek,xfi_pll = <&xfi_pll>;
+			mediatek,infracfg = <&topmisc>;
+			mediatek,toprgu = <&watchdog>;
+			#reset-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
index 3bfaacb18ae5d4..5444f4586a2a87 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
@@ -6,6 +6,10 @@ board=$(board_name)
 board_config_update
 
 case $board in
+imou,lc-hx3001)
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "br-lan"
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1"
+	;;
 xiaomi,mi-router-wr30u)
 	ucidef_set_led_netdev "wan" "wan" "blue:internet" "wan"
 	;;
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
index 552663d5dca94c..7e58f32c841730 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
@@ -10,7 +10,8 @@ mediatek_setup_interfaces()
 	case $board in
 	asus,tuf-ax4200|\
 	jdcloud,re-cs-05|\
-	netcore,n60)
+	netcore,n60|\
+	ruijie,rg-x60-pro)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
 		;;
 	bananapi,bpi-r3)
@@ -26,13 +27,17 @@ mediatek_setup_interfaces()
 	glinet,gl-mt3000)
 		ucidef_set_interfaces_lan_wan eth1 eth0
 		;;
-	h3c,magic-nx30-pro)
+	h3c,magic-nx30-pro|\
+	imou,lc-hx3001)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1
 		;;
 	mediatek,mt7986a-rfb|\
 	mediatek,mt7986b-rfb)
 		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1
 		;;
+	mediatek,mt7988a-dsa-10g-spim-snand)
+		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth1 eth2"
+		;;
 	glinet,gl-mt6000|\
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6088|\
@@ -85,6 +90,11 @@ mediatek_setup_macs()
 		lan_mac=$(macaddr_add "$wan_mac" 1)
 		label_mac=$wan_mac
 		;;
+	imou,lc-hx3001)
+		lan_mac=$(mtd_get_mac_ascii u-boot-env mac)
+		wan_mac=$(macaddr_add "$lan_mac" 2)
+		label_mac=$lan_mac
+		;;
 	jdcloud,re-cs-05)
 		wan_mac=$(mmc_get_mac_binary factory 0x24)
 		lan_mac=$(mmc_get_mac_binary factory 0x2a)
@@ -95,6 +105,11 @@ mediatek_setup_macs()
 		wan_mac=$(macaddr_add "$lan_mac" 1)
 		label_mac=$wan_mac
 		;;
+	ruijie,rg-x60-pro)
+		label_mac=$(mtd_get_mac_ascii product_info ethaddr)
+		wan_mac=$label_mac
+		lan_mac=$(macaddr_add "$label_mac" 1)
+		;;
 	xiaomi,mi-router-wr30u|\
 	xiaomi,mi-router-ax3000t|\
 	xiaomi,redmi-router-ax6000)
diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
index 1d3d162d12f303..bb5dd48feee6d3 100644
--- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
+++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
@@ -20,9 +20,9 @@ case "$board" in
 		[ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress
 		;;
 	bananapi,bpi-r3)
-		addr=$(macaddr_add $(cat /sys/class/net/eth0/address) 2)
-		[ "$PHYNBR" = "0" ] && macaddr_unsetbit $addr 6 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "1" ] && macaddr_setbit $addr 6 > /sys${DEVPATH}/macaddress
+		addr=$(cat /sys/class/net/eth0/address)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		;;
 	cetron,ct3003*)
 		addr=$(mtd_get_mac_binary "art" 0)
@@ -39,6 +39,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		;;
+	imou,lc-hx3001)
+		addr=$(mtd_get_mac_ascii u-boot-env mac)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+		;;
 	jcg,q30-pro|\
 	netcore,n60)
 		# Originally, phy1 is phy0 mac with LA bit set. However, this would conflict
@@ -50,6 +55,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		;;
+	ruijie,rg-x60-pro)
+		addr=$(mtd_get_mac_ascii product_info ethaddr)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+		;;
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6086|\
 	tplink,tl-xdr6088)
diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15
index 545a09df6ea643..31b2741cabfd5e 100644
--- a/target/linux/mediatek/filogic/config-5.15
+++ b/target/linux/mediatek/filogic/config-5.15
@@ -363,6 +363,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MT6380=y
 CONFIG_REGULATOR_RT5190A=y
 CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_TI_SYSCON=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 CONFIG_RPS=y
diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk
index 294d7f8f2552ff..1a5efa06231895 100644
--- a/target/linux/mediatek/image/filogic.mk
+++ b/target/linux/mediatek/image/filogic.mk
@@ -215,6 +215,20 @@ define Device/h3c_magic-nx30-pro
 endef
 TARGET_DEVICES += h3c_magic-nx30-pro
 
+define Device/imou_lc-hx3001
+  DEVICE_VENDOR := IMOU
+  DEVICE_MODEL := LC-HX3001
+  DEVICE_DTS := mt7981b-imou-lc-hx3001
+  DEVICE_DTS_DIR := ../dts
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  KERNEL_IN_UBI := 1
+  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += imou_lc-hx3001
+
 define Device/jcg_q30-pro
   DEVICE_VENDOR := JCG
   DEVICE_MODEL := Q30 PRO
@@ -280,6 +294,24 @@ define Device/mediatek_mt7986b-rfb
 endef
 TARGET_DEVICES += mediatek_mt7986b-rfb
 
+define Device/mediatek_mt7988a-rfb-nand
+  DEVICE_VENDOR := MediaTek
+  DEVICE_MODEL := MT7988a nand rfb
+  DEVICE_DTS := mt7988a-dsa-10g-spim-nand
+  DEVICE_DTS_DIR := $(DTS_DIR)/
+  KERNEL_LOADADDR := 0x48000000
+  SUPPORTED_DEVICES := mediatek,mt7988a-rfb
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE_SIZE := 65536k
+  KERNEL_IN_UBI := 1
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += mediatek_mt7988a-rfb-nand
+
 define Device/netcore_n60
   DEVICE_VENDOR := Netcore
   DEVICE_MODEL := N60
@@ -308,6 +340,16 @@ define Device/qihoo_360t7
 endef
 TARGET_DEVICES += qihoo_360t7
 
+define Device/ruijie_rg-x60-pro
+  DEVICE_VENDOR := Ruijie
+  DEVICE_MODEL := RG-X60 Pro
+  DEVICE_DTS := mt7986a-ruijie-rg-x60-pro
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += ruijie_rg-x60-pro
+
 define Device/tplink_tl-common
   DEVICE_VENDOR := TP-Link
   DEVICE_DTS_DIR := ../dts
diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch
new file mode 100644
index 00000000000000..6ab05b897c3e39
--- /dev/null
+++ b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch
@@ -0,0 +1,53 @@
+From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 26 May 2023 10:31:40 +0100
+Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623
+
+The MT6380 regulator typically used together with MT7622 does not
+support the current maximum processor and SRAM voltage in the cpufreq
+driver (1360000uV).
+For MT7622 limit processor and SRAM supply voltages to 1350000uV to
+avoid having the tracking algorithm request unsupported voltages from
+the regulator.
+
+On MT7623 there is no separate SRAM supply and the maximum voltage used
+is 1300000uV. Create dedicated platform data for MT7623 to cover that
+case as well.
+
+Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623")
+Suggested-by: Jia-wei Chang <Jia-wei.Chang@mediatek.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+--- a/drivers/cpufreq/mediatek-cpufreq.c
++++ b/drivers/cpufreq/mediatek-cpufreq.c
+@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform
+ static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
+ 	.min_volt_shift = 100000,
+ 	.max_volt_shift = 200000,
+-	.proc_max_volt = 1360000,
++	.proc_max_volt = 1350000,
+ 	.sram_min_volt = 0,
+-	.sram_max_volt = 1360000,
++	.sram_max_volt = 1350000,
++	.ccifreq_supported = false,
++};
++
++static const struct mtk_cpufreq_platform_data mt7623_platform_data = {
++	.min_volt_shift = 100000,
++	.max_volt_shift = 200000,
++	.proc_max_volt = 1300000,
+ 	.ccifreq_supported = false,
+ };
+ 
+@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu
+ 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
+ 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+ 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
+-	{ .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
++	{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
+ 	{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
+ 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
+ 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch
deleted file mode 100644
index a7a4bd8ea2bba9..00000000000000
--- a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 20aad28ba5d62f1618408c264384d0b2ad7417db Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 22 May 2023 23:25:48 +0100
-Subject: [PATCH] cpufreq: mediatek: don't request unsupported voltage
-
-PMICs on MT7622 and MT7623 boards only support up to 1350000uV despite
-the SoC's processor and SRAM voltage can be up to 1360000uV. As a
-work-around specify max. processor and SRAM voltage as 1350000uV to
-avoid requesting an unsupported voltage from the regulator.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -696,9 +696,9 @@ static const struct mtk_cpufreq_platform
- static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
--	.proc_max_volt = 1360000,
-+	.proc_max_volt = 1350000,
- 	.sram_min_volt = 0,
--	.sram_max_volt = 1360000,
-+	.sram_max_volt = 1350000,
- 	.ccifreq_supported = false,
- };
- 
diff --git a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
index 4c980e9438d1ee..e795eda3b2b77f 100644
--- a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
+++ b/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch
@@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -1234,6 +1234,70 @@ static int spi_transfer_wait(struct spi_
+@@ -1246,6 +1246,70 @@ static int spi_transfer_wait(struct spi_
  	return 0;
  }
  
@@ -82,7 +82,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  static void _spi_transfer_delay_ns(u32 ns)
  {
  	if (!ns)
-@@ -2021,6 +2085,75 @@ void spi_flush_queue(struct spi_controll
+@@ -2033,6 +2097,75 @@ void spi_flush_queue(struct spi_controll
  /*-------------------------------------------------------------------------*/
  
  #if defined(CONFIG_OF)
@@ -158,7 +158,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
  			   struct device_node *nc)
  {
-@@ -2139,6 +2272,10 @@ of_register_spi_device(struct spi_contro
+@@ -2151,6 +2284,10 @@ of_register_spi_device(struct spi_contro
  	if (rc)
  		goto err_out;
  
diff --git a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
index ff482272108307..b7311e042d8e78 100644
--- a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
+++ b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
@@ -18,7 +18,7 @@ Acked-by: Pali Rohár <pali@kernel.org>
 
 --- a/drivers/pci/controller/pcie-mediatek.c
 +++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
+@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
  	 */
  	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
  
diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
index de64eda8277d5c..76ee2fc89abdad 100644
--- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
+++ b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  struct mtk_pcie_port;
  
  /**
-@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci
+@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
  	struct mtk_pcie_port *port, *tmp;
  	int err, slot;
  
diff --git a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
index 69f2d2a545dcf4..46e92a92f31354 100644
--- a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
+++ b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
@@ -72,7 +72,7 @@ Signed-off-by: Wolfram Sang <wsa@kernel.org>
  	idev->adapter.dev.parent = &pdev->dev;
 --- a/drivers/i2c/busses/i2c-aspeed.c
 +++ b/drivers/i2c/busses/i2c-aspeed.c
-@@ -1028,7 +1028,7 @@ static int aspeed_i2c_probe_bus(struct p
+@@ -1044,7 +1044,7 @@ static int aspeed_i2c_probe_bus(struct p
  	bus->adap.algo = &aspeed_i2c_algo;
  	bus->adap.dev.parent = &pdev->dev;
  	bus->adap.dev.of_node = pdev->dev.of_node;
@@ -458,7 +458,7 @@ Signed-off-by: Wolfram Sang <wsa@kernel.org>
  	adap->dev.parent = &pdev->dev;
 --- a/drivers/i2c/busses/i2c-rk3x.c
 +++ b/drivers/i2c/busses/i2c-rk3x.c
-@@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platfor
+@@ -1247,7 +1247,7 @@ static int rk3x_i2c_probe(struct platfor
  	/* use common interface to get I2C timing properties */
  	i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
  
@@ -469,7 +469,7 @@ Signed-off-by: Wolfram Sang <wsa@kernel.org>
  	i2c->adap.retries = 3;
 --- a/drivers/i2c/busses/i2c-s3c2410.c
 +++ b/drivers/i2c/busses/i2c-s3c2410.c
-@@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct plat
+@@ -1078,7 +1078,7 @@ static int s3c24xx_i2c_probe(struct plat
  	else
  		s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
  
diff --git a/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch b/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch
index 578124f94d4b2d..cb88a548780343 100644
--- a/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch
+++ b/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch
@@ -44,7 +44,7 @@ Signed-off-by: Marek Behún <kabel@kernel.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -182,6 +182,7 @@ config LEDS_TURRIS_OMNIA
+@@ -183,6 +183,7 @@ config LEDS_TURRIS_OMNIA
  	depends on I2C
  	depends on MACH_ARMADA_38X || COMPILE_TEST
  	depends on OF
diff --git a/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
index 3ac2427b801a0f..84cef8da110a92 100644
--- a/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
+++ b/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
@@ -30,7 +30,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -334,6 +334,14 @@ config LEDS_IPAQ_MICRO
+@@ -335,6 +335,14 @@ config LEDS_IPAQ_MICRO
  	  Choose this option if you want to use the notification LED on
  	  Compaq/HP iPAQ h3100 and h3600.
  
diff --git a/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch b/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch
index 34e3ce9a13925c..ffec312ced75b6 100644
--- a/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch
+++ b/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch
@@ -44,7 +44,7 @@ Signed-off-by: Marek Behún <kabel@kernel.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA
+@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA
  	depends on I2C
  	depends on MACH_ARMADA_38X || COMPILE_TEST
  	depends on OF
diff --git a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
index a3fc731c471967..8192d1998bfbc3 100644
--- a/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
+++ b/target/linux/mvebu/patches-5.15/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
@@ -30,7 +30,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -306,6 +306,14 @@ config LEDS_IPAQ_MICRO
+@@ -307,6 +307,14 @@ config LEDS_IPAQ_MICRO
  	  Choose this option if you want to use the notification LED on
  	  Compaq/HP iPAQ h3100 and h3600.
  
diff --git a/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch b/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
index ef3beb56d1b044..afcb18d16829e2 100644
--- a/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
+++ b/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
@@ -22,7 +22,7 @@ Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  #include <linux/platform_data/x86/apple.h>
  #include <linux/pm_runtime.h>
  #include <linux/suspend.h>
-@@ -5823,3 +5824,34 @@ static void nvidia_ion_ahci_fixup(struct
+@@ -5847,3 +5848,34 @@ static void nvidia_ion_ahci_fixup(struct
  	pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
  }
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
diff --git a/target/linux/phytium/Makefile b/target/linux/phytium/Makefile
new file mode 100644
index 00000000000000..8c2d3d9cabc2b9
--- /dev/null
+++ b/target/linux/phytium/Makefile
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Phytium Technology Co., Ltd.
+# Copyright (C) 2023-2024 Ailick <277498654@qq.com>
+
+include $(TOPDIR)/rules.mk
+
+BOARD:=phytium
+BOARDNAME:=Phytium
+FEATURES:=fpu pci pcie rtc usb boot-part rootfs-part
+FEATURES+=cpiogz ext4 ramdisk squashfs targz vmdk usb gpio fpu pci pcie jffs2
+SUBTARGETS:=armv8 e2000 phytiumpi
+
+KERNEL_PATCHVER:=5.10
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += mkf2fs e2fsprogs
+# blkid used for resolving PARTUUID
+# in sysupgrade. vfat required for
+# mounting ESP partition
+DEFAULT_PACKAGES += blkid kmod-fs-vfat kmod-usb2 kmod-usb3 kmod-hwmon-phytium
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/phytium/README b/target/linux/phytium/README
new file mode 100644
index 00000000000000..052badd2b9f4cb
--- /dev/null
+++ b/target/linux/phytium/README
@@ -0,0 +1,5 @@
+This target generates images that can be used on ARM machines with EFI
+support (e.g EDKII/TianoCore or U-Boot with bootefi).
+
+Tested:
+THTF ChaoXiang TF830-V050
diff --git a/target/linux/phytium/armv8/config-5.10 b/target/linux/phytium/armv8/config-5.10
new file mode 100644
index 00000000000000..dbaf5789cc839d
--- /dev/null
+++ b/target/linux/phytium/armv8/config-5.10
@@ -0,0 +1,827 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_USELIB=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_RCU_EXPERT=y
+CONFIG_RCU_NOCB_CPU=y
+CONFIG_RCU_FANOUT=64
+CONFIG_RCU_FANOUT_LEAF=16
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TASKS_TRACE_RCU_READ_MB is not set
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_ZONE_DMA32=y
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=8
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_DMI=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_HIBERNATION_SNAPSHOT_DEV is not set
+CONFIG_PM_STD_PARTITION=""
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_ACPI_CPPC_CPUFREQ is not set
+# CONFIG_ARM_SCMI_CPUFREQ is not set
+# CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING is not set
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_DMIID=y
+# CONFIG_DMI_SYSFS is not set
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
+CONFIG_ACPI_DEBUGGER=y
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+# CONFIG_ACPI_TINY_POWER_BUTTON is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_IPMI is not set
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_CUSTOM_DSDT_FILE=""
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_HMAT is not set
+# CONFIG_ACPI_APEI_ERST_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER_USER is not set
+CONFIG_KVM_ARM_PMU=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_BLK_WBT_MQ=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_BFQ_CGROUP_DEBUG is not set
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_BALLOON_COMPACTION=y
+# CONFIG_HWPOISON_INJECT is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
+CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
+# CONFIG_ZSWAP_DEFAULT_ON is not set
+# CONFIG_Z3FOLD is not set
+# CONFIG_BPFILTER_UMH is not set
+# CONFIG_NCSI_OEM_CMD_GET_MAC is not set
+# CONFIG_NET_9P_XEN is not set
+# CONFIG_NET_9P_DEBUG is not set
+# CONFIG_NFC_DIGITAL is not set
+# CONFIG_NFC_NCI_SPI is not set
+# CONFIG_NFC_NCI_UART is not set
+# CONFIG_NFC_HCI is not set
+# CONFIG_NFC_FDP is not set
+# CONFIG_NFC_PN533_USB is not set
+# CONFIG_NFC_PN533_I2C is not set
+# CONFIG_NFC_PN532_UART is not set
+# CONFIG_NFC_MRVL_USB is not set
+# CONFIG_NFC_ST_NCI_I2C is not set
+# CONFIG_NFC_ST_NCI_SPI is not set
+# CONFIG_NFC_NXP_NCI is not set
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+CONFIG_PCI_XGENE_MSI=y
+# CONFIG_PCIE_HISI_ERR is not set
+# CONFIG_PCIE_CADENCE_PLAT_EP is not set
+# CONFIG_PCI_J721E_EP is not set
+CONFIG_FW_CACHE=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_NAND_PHYTIUM_PCI is not set
+# CONFIG_SPI_HISI_SFC is not set
+CONFIG_XEN_BLKDEV_FRONTEND=y
+# CONFIG_XEN_BLKDEV_BACKEND is not set
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_MEGARAID_MM is not set
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+# CONFIG_SCSI_UFSHCD_PCI is not set
+# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
+# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
+# CONFIG_SCSI_UFS_BSG is not set
+# CONFIG_XEN_SCSI_FRONTEND is not set
+# CONFIG_SCSI_DH_RDAC is not set
+# CONFIG_SCSI_DH_HP_SW is not set
+# CONFIG_SCSI_DH_EMC is not set
+# CONFIG_SCSI_DH_ALUA is not set
+# CONFIG_DM_INIT is not set
+# CONFIG_DM_ZONED is not set
+CONFIG_FUSION_MAX_SGE=128
+# CONFIG_MACB_PCI is not set
+# CONFIG_HNS3_HCLGEVF is not set
+# CONFIG_STMMAC_SELFTESTS is not set
+# CONFIG_ROADRUNNER is not set
+# CONFIG_MOTORCOMM_PHY is not set
+# CONFIG_DLCI is not set
+CONFIG_XEN_NETDEV_FRONTEND=y
+# CONFIG_XEN_NETDEV_BACKEND is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYSTICK is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_USERFAULTFD=y
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_SLUB_MEMCG_SYSFS_ON=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB_MERGE_DEFAULT is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_HISI=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_PHYTIUM=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_XEN=y
+CONFIG_COMPAT=y
+CONFIG_ARMV8_DEPRECATED=y
+CONFIG_SWP_EMULATION=y
+CONFIG_CP15_BARRIER_EMULATION=y
+CONFIG_SETEND_EMULATION=y
+CONFIG_ARM64_PMEM=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
+CONFIG_CMDLINE="pcie_aspm=off"
+CONFIG_HIBERNATION=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SDE_INTERFACE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_ACPI=y
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_PMIC_OPREGION=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_VMAP_STACK is not set
+CONFIG_MODVERSIONS=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_DEV_THROTTLING_LOW=y
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_CGROUP_IOLATENCY=y
+# CONFIG_BLK_DEBUG_FS is not set
+CONFIG_BLK_SED_OPAL=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_OSF_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_SGI_PARTITION=y
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_MEMORY_FAILURE=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_FRONTSWAP=y
+CONFIG_ZSWAP=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XDP_SOCKETS=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_NET_FOU=y
+CONFIG_NET_FOU_IP_TUNNELS=y
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_MD5SIG=y
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_IPV6_SEG6_LWTUNNEL=y
+CONFIG_IPV6_SEG6_HMAC=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_NF_REJECT_IPV4=y
+CONFIG_BPFILTER=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_DEFAULT=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_DCB=y
+CONFIG_NET_NCSI=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_STUB=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+CONFIG_PCIE_DW_PLAT_EP=y
+CONFIG_PCI_HISI=y
+CONFIG_PCIE_KIRIN=y
+CONFIG_PCIE_HISI_STB=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_DEVTMPFS=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD_PARTITIONED_MASTER=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_8=y
+CONFIG_MTD_MAP_BANK_WIDTH_16=y
+CONFIG_MTD_MAP_BANK_WIDTH_32=y
+CONFIG_MTD_CFI_I4=y
+CONFIG_MTD_CFI_I8=y
+CONFIG_MTD_OTP=y
+CONFIG_MTD_PHYSMAP_COMPAT=y
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_SPI_PHYTIUM_QUADSPI=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=8
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_SRAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_SCSI_DH=y
+CONFIG_ATA=y
+# CONFIG_ATA_ACPI is not set
+CONFIG_SATA_AHCI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_UEVENT=y
+CONFIG_FUSION=y
+CONFIG_FUSION_LOGGING=y
+CONFIG_NET_FC=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_AMD_XGBE_DCB=y
+CONFIG_NET_TULIP=y
+CONFIG_HNS3_DCB=y
+CONFIG_IXGBE_DCB=y
+CONFIG_I40E_DCB=y
+# CONFIG_MLX4_DEBUG is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PCI=y
+CONFIG_HIPPI=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_HISI_FEMAC=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_WIRELESS_WDS=y
+CONFIG_WAN=y
+CONFIG_ISDN=y
+# CONFIG_INPUT_LEDS is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_TABLET=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_HISI_POWERKEY=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_RUNTIME_UARTS=32
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL010=y
+CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C_SLAVE=y
+CONFIG_SPI=y
+CONFIG_SPI_PHYTIUM_PLAT=y
+CONFIG_SPI_PHYTIUM_PCI=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_XGENE=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_HISI=y
+CONFIG_POWER_RESET_LTC2952=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_PMIC_DA903X=y
+CONFIG_MFD_DA9052_SPI=y
+CONFIG_MFD_DA9052_I2C=y
+CONFIG_MFD_DA9055=y
+CONFIG_MFD_DA9063=y
+CONFIG_HTC_I2CPLD=y
+CONFIG_MFD_88PM860X=y
+CONFIG_MFD_MAX14577=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX77693=y
+CONFIG_MFD_MAX77843=y
+CONFIG_MFD_MAX8925=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_EZX_PCAP=y
+CONFIG_MFD_PHYTIUM_I2S_LSD=y
+CONFIG_MFD_PHYTIUM_I2S_MMD=y
+CONFIG_MFD_RC5T583=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_ABX500_CORE=y
+CONFIG_AB3100_CORE=y
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_LP8788=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TPS65912_I2C=y
+CONFIG_MFD_TPS65912_SPI=y
+CONFIG_MFD_TPS80031=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL6040_CORE=y
+CONFIG_MFD_TC3589X=y
+CONFIG_MFD_WM8400=y
+CONFIG_MFD_WM831X_I2C=y
+CONFIG_MFD_WM831X_SPI=y
+CONFIG_MFD_WM8350_I2C=y
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_CADENCE=y
+CONFIG_DVB_PLATFORM_DRIVERS=y
+CONFIG_DRM=y
+CONFIG_DRM_DP_AUX_CHARDEV=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_DP_CEC=y
+CONFIG_DRM_RADEON_USERPTR=y
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_XEN=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_EFI=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
+CONFIG_SND=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_PHYTIUM=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_HDA_CODEC_CIRRUS=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_CA0110=y
+CONFIG_SND_HDA_CODEC_CA0132=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_PREALLOC_SIZE=1024
+CONFIG_SND_SOC_IMG=y
+CONFIG_SND_SOC_PHYTIUM_I2S=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_HID_PID=y
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DBGCAP=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_USB_DWC3_ULPI=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_ULPI=y
+CONFIG_MMC_PHYTIUM_SDCI=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307_CENTURY=y
+CONFIG_RTC_DRV_RV8803=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_ZYNQMP=y
+CONFIG_RTC_DRV_PL030=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_SW_SYNC=y
+CONFIG_AUXDISPLAY=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GNTDEV_DMABUF=y
+CONFIG_XEN_GRANT_DMA_ALLOC=y
+CONFIG_XEN_PVCALLS_BACKEND=y
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CLK_QORIQ=y
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_TI=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_MEMORY=y
+CONFIG_NTB=y
+CONFIG_PWM=y
+CONFIG_PHYTIUM_IXIC=y
+CONFIG_POWERCAP=y
+CONFIG_HISI_PMU=y
+CONFIG_STM=y
+CONFIG_STM_SOURCE_CONSOLE=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_CHECK_FS=y
+CONFIG_FS_DAX=y
+CONFIG_FANOTIFY=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FSCACHE=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_DECOMP_MULTI=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_PSTORE_842_COMPRESS=y
+CONFIG_PSTORE_ZSTD_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_NFS_V4_1_MIGRATION=y
+CONFIG_NFS_USE_LEGACY_DNS=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_SECURITY=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_INDIRECT_PIO=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_RCU_TRACE is not set
+# CONFIG_STRICT_DEVMEM is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_EFI=y
+CONFIG_MTD_NAND_PHYTIUM_PLAT=y
+CONFIG_SERIAL_PHYTIUM_PCI=y
+CONFIG_HW_RANDOM_PHYTIUM=y
+CONFIG_I2C_PHYTIUM_PCI=y
+CONFIG_I2C_PHYTIUM_PLATFORM=y
+CONFIG_SPI_PHYTIUM_QSPI=y
+CONFIG_W1_MASTER_PHYTIUM=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_PHYTIUM=y
+# CONFIG_MMC_PHYTIUM_MCI_PCI is not set
+CONFIG_EDAC_PHYTIUM=y
+CONFIG_PHYTIUM_DDMA=y
+CONFIG_HWSPINLOCK_PHYTIUM=y
+CONFIG_PHYTIUM_ADC=y
+CONFIG_PWM_PHYTIUM=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_2457168=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_16K_PAGES is not set
+# CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PA_BITS=48
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NR_CPUS=256
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_KUSER_HELPERS=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_PAN=y
+CONFIG_AS_HAS_LSE_ATOMICS=y
+CONFIG_ARM64_LSE_ATOMICS=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
+CONFIG_AS_HAS_PAC=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+CONFIG_ARM64_AMU_EXTN=y
+CONFIG_AS_HAS_ARMV8_4=y
+CONFIG_ARM64_TLB_RANGE=y
+CONFIG_ARM64_BTI=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
+CONFIG_ARM64_E0PD=y
+CONFIG_ARCH_RANDOM=y
+CONFIG_ARM64_AS_HAS_MTE=y
+CONFIG_ARM64_MTE=y
+CONFIG_ARM64_MODULE_PLTS=y
+# CONFIG_ARM64_PSEUDO_NMI is not set
+CONFIG_RELOCATABLE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_BRIDGE=y
+CONFIG_QRTR=y
+CONFIG_QRTR_TUN=y
+CONFIG_CAN=y
+CONFIG_NFC=y
+CONFIG_NFC_NCI=y
+CONFIG_NFC_S3FWRN5_I2C=y
+CONFIG_PCI_EPF_TEST=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_PCI_ENDPOINT_TEST=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_UACCE=y
+CONFIG_SCSI_MPT3SAS=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
+CONFIG_VETH=y
+CONFIG_ATL1C=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_DEVICE_INTERFACE=y
+CONFIG_IPMI_SI=y
+CONFIG_PHYTIUM_KCS_IPMI_BMC=y
+CONFIG_PHYTIUM_BT_IPMI_BMC=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI_BITBANG=y
+CONFIG_GPIO_ALTERA=y
+CONFIG_GPIO_BD9571MWV=y
+CONFIG_W1=y
+CONFIG_W1_SLAVE_THERM=y
+CONFIG_BATTERY_SBS=y
+CONFIG_RC_CORE=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_DRM_I2C_CH7006=y
+CONFIG_DRM_I2C_SIL164=y
+CONFIG_DRM_I2C_NXP_TDA998X=y
+CONFIG_DRM_MALI_DISPLAY=y
+CONFIG_DRM_RCAR_DW_HDMI=y
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_LONTIUM_LT9611=y
+CONFIG_DRM_NWL_MIPI_DSI=y
+CONFIG_DRM_SII902X=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
+CONFIG_DRM_THINE_THC63LVD1024=y
+CONFIG_DRM_TI_SN65DSI86=y
+CONFIG_DRM_I2C_ADV7511=y
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
+CONFIG_DRM_DW_HDMI_CEC=y
+CONFIG_SND_SOC_FSL_SAI=y
+CONFIG_SND_SOC_AK4613=y
+CONFIG_SND_SOC_CROS_EC_CODEC=y
+CONFIG_SND_SOC_DMIC=y
+CONFIG_SND_SOC_ES7134=y
+CONFIG_SND_SOC_ES7241=y
+CONFIG_SND_SOC_MAX98357A=y
+CONFIG_SND_SOC_MAX98927=y
+CONFIG_SND_SOC_PCM3168A_I2C=y
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SND_SOC_TAS571X=y
+CONFIG_SND_SOC_WM8904=y
+CONFIG_SND_SOC_WSA881X=y
+CONFIG_I2C_HID=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_DRV_PCF85363=y
+CONFIG_RTC_DRV_RX8581=y
+CONFIG_RTC_DRV_SD3068=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_CROS_EC_CHARDEV=y
+CONFIG_COMMON_CLK_BD718XX=y
+CONFIG_SOUNDWIRE=y
+CONFIG_SOUNDWIRE_QCOM=y
+CONFIG_MAX9611=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_IIO_CROS_EC_SENSORS_CORE=y
+CONFIG_IIO_CROS_EC_SENSORS=y
+CONFIG_IIO_CROS_EC_LIGHT_PROX=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_IIO_CROS_EC_BARO=y
+CONFIG_MPL3115=y
+CONFIG_PWM_CROS_EC=y
+CONFIG_PHY_MIXEL_MIPI_DPHY=y
+CONFIG_FPGA_BRIDGE=y
+CONFIG_ALTERA_FREEZE_BRIDGE=y
+CONFIG_FPGA_REGION=y
+CONFIG_OF_FPGA_REGION=y
+CONFIG_OVERLAY_FS=y
diff --git a/target/linux/phytium/armv8/target.mk b/target/linux/phytium/armv8/target.mk
new file mode 100644
index 00000000000000..c5b20913f951e8
--- /dev/null
+++ b/target/linux/phytium/armv8/target.mk
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2023-2024 Ailick <277498654@qq.com>
+
+ARCH:=aarch64
+SUBTARGET:=armv8
+BOARDNAME:=64-bit (armv8) SystemReady (EFI) compliant
+
+define Target/Description
+  Build multi-platform images for the Phytium ARMv8 instruction set architecture
+endef
diff --git a/target/linux/phytium/base-files.mk b/target/linux/phytium/base-files.mk
new file mode 100644
index 00000000000000..88ba97d38a3d9f
--- /dev/null
+++ b/target/linux/phytium/base-files.mk
@@ -0,0 +1,8 @@
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_GRUB_SERIAL))
+ifeq ($(GRUB_SERIAL),)
+$(error This platform requires CONFIG_GRUB_SERIAL be set!)
+endif
+
+define Package/base-files/install-target
+	$(SED) "s#@GRUB_SERIAL@#$(GRUB_SERIAL)#" $(1)/etc/inittab
+endef
diff --git a/target/linux/phytium/base-files/etc/board.d/01_led b/target/linux/phytium/base-files/etc/board.d/01_led
new file mode 100644
index 00000000000000..0250a9672f5e5c
--- /dev/null
+++ b/target/linux/phytium/base-files/etc/board.d/01_led
@@ -0,0 +1,19 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+
+case "$board" in
+traverse,ten64)
+	ucidef_set_led_netdev "sfp1" "SFP 1" "ten64:green:sfp1:down" "eth8" "link tx rx"
+	ucidef_set_led_netdev "sfp2" "SFP 2" "ten64:green:sfp2:up" "eth9" "link tx rx"
+	;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/phytium/base-files/etc/board.d/02_network b/target/linux/phytium/base-files/etc/board.d/02_network
new file mode 100644
index 00000000000000..f58de1c27d3986
--- /dev/null
+++ b/target/linux/phytium/base-files/etc/board.d/02_network
@@ -0,0 +1,18 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/system.sh
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+case "$(board_name)" in
+	traverse,ten64)
+		ucidef_set_interface_lan "eth0 eth1 eth2 eth3"
+		ucidef_set_interface_wan "eth6"
+		;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/phytium/base-files/etc/board.d/03_gpio_switches b/target/linux/phytium/base-files/etc/board.d/03_gpio_switches
new file mode 100644
index 00000000000000..cf07bc0f54fbc0
--- /dev/null
+++ b/target/linux/phytium/base-files/etc/board.d/03_gpio_switches
@@ -0,0 +1,23 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+
+case "$board" in
+traverse,ten64)
+	ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "376"
+	ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "377"
+	ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "378"
+	ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "379"
+	ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "369"
+	ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "373"
+	;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/phytium/base-files/etc/inittab b/target/linux/phytium/base-files/etc/inittab
new file mode 100644
index 00000000000000..87d5460d323313
--- /dev/null
+++ b/target/linux/phytium/base-files/etc/inittab
@@ -0,0 +1,9 @@
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+ttyAMA0::askfirst:/usr/libexec/login.sh
+@GRUB_SERIAL@::askfirst:/usr/libexec/login.sh
+tty0::askfirst:/usr/libexec/login.sh
+hvc0::askfirst:/usr/libexec/login.sh
+ttymxc0::askfirst:/usr/libexec/login.sh
+ttymxc1::askfirst:/usr/libexec/login.sh
+ttymxc2::askfirst:/usr/libexec/login.sh
diff --git a/target/linux/phytium/base-files/lib/preinit/01_sysinfo_acpi b/target/linux/phytium/base-files/lib/preinit/01_sysinfo_acpi
new file mode 100644
index 00000000000000..1069d74cf3e3cb
--- /dev/null
+++ b/target/linux/phytium/base-files/lib/preinit/01_sysinfo_acpi
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+sanitize_name_arm64() {
+	sed -e '
+		y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/;
+		s/[^a-z0-9_-]\+/-/g;
+		s/^-//;
+		s/-$//;
+	' "$@"
+}
+
+do_sysinfo_arm64() {
+	local vendor product file
+
+	for file in sys_vendor board_vendor; do
+		vendor="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+		case "$vendor" in
+		empty | \
+		System\ manufacturer | \
+		To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+			continue
+			;;
+		esac
+		[ -n "$vendor" ] && break
+	done
+
+	for file in product_name board_name; do
+		product="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+		case "$vendor:$product" in
+		?*:empty | \
+		?*:System\ Product\ Name | \
+		?*:To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+			continue
+			;;
+		?*:?*)
+			break
+			;;
+		esac
+	done
+
+	[ -d "/sys/firmware/devicetree/base" ] && return
+
+	[ -n "$vendor" -a -n "$product" ] || return
+
+	mkdir -p /tmp/sysinfo
+
+	echo "$vendor $product" > /tmp/sysinfo/model
+
+	sanitize_name_arm64 /tmp/sysinfo/model > /tmp/sysinfo/board_name
+}
+
+boot_hook_add preinit_main do_sysinfo_arm64
diff --git a/target/linux/phytium/base-files/lib/preinit/79_move_config b/target/linux/phytium/base-files/lib/preinit/79_move_config
new file mode 100644
index 00000000000000..864d4dfa644fc7
--- /dev/null
+++ b/target/linux/phytium/base-files/lib/preinit/79_move_config
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+move_config() {
+	local partdev parttype=ext4
+
+	. /lib/upgrade/common.sh
+
+	if export_bootdevice && export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		if mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt; then
+			if [ -f "/mnt/$BACKUP_FILE" ]; then
+				mv -f "/mnt/$BACKUP_FILE" /
+			fi
+			umount /mnt
+		fi
+	fi
+}
+
+boot_hook_add preinit_mount_root move_config
diff --git a/target/linux/phytium/base-files/lib/upgrade/platform.sh b/target/linux/phytium/base-files/lib/upgrade/platform.sh
new file mode 100644
index 00000000000000..e72c6955e5814a
--- /dev/null
+++ b/target/linux/phytium/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+RAMFS_COPY_BIN="/usr/sbin/blkid"
+
+platform_check_image() {
+	local board=$(board_name)
+	local diskdev partdev diff
+	[ "$#" -gt 1 ] && return 1
+
+	v "Board is ${board}"
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "platform_check_image: Unable to determine upgrade device"
+		return 1
+	}
+
+	get_partitions "/dev/$diskdev" bootdisk
+
+	v "Extract boot sector from the image"
+	get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+	get_partitions /tmp/image.bs image
+
+	#compare tables
+	diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+
+	rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
+
+	if [ -n "$diff" ]; then
+		v "Partition layout has changed. Full image will be written."
+		ask_bool 0 "Abort" && exit 1
+		return 0
+	fi
+}
+
+platform_copy_config() {
+	local partdev parttype=ext4
+
+	if export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+		cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
+		umount /mnt
+	else
+		v "ERROR: Unable to find partition to copy config data to"
+	fi
+
+	sleep 5
+}
+
+# To avoid writing over any firmware
+# files (e.g ubootefi.var or firmware/X/ aka EBBR)
+# Copy efi/openwrt and efi/boot from the new image
+# to the existing ESP
+platform_do_upgrade_efi_system_partition() {
+	local image_file=$1
+	local target_partdev=$2
+	local image_efisp_start=$3
+	local image_efisp_size=$4
+
+	v "Updating ESP on ${target_partdev}"
+	NEW_ESP_DIR="/mnt/new_esp_loop"
+	CUR_ESP_DIR="/mnt/cur_esp"
+	mkdir "${NEW_ESP_DIR}"
+	mkdir "${CUR_ESP_DIR}"
+
+	get_image_dd "$image_file" of="/tmp/new_efi_sys_part.img" \
+		skip="$image_efisp_start" count="$image_efisp_size"
+
+	mount -t vfat -o loop -o ro /tmp/new_efi_sys_part.img "${NEW_ESP_DIR}"
+	if [ ! -d "${NEW_ESP_DIR}/efi/boot" ]; then
+		v "ERROR: Image does not contain EFI boot files (/efi/boot)"
+		return 1
+	fi
+
+	mount -t vfat "/dev/$partdev" "${CUR_ESP_DIR}"
+
+	for d in $(find "${NEW_ESP_DIR}/efi/" -mindepth 1 -maxdepth 1 -type d); do
+		v "Copying ${d}"
+		newdir_bname=$(basename "${d}")
+		rm -rf "${CUR_ESP_DIR}/efi/${newdir_bname}"
+		cp -r "${d}" "${CUR_ESP_DIR}/efi"
+	done
+
+	umount "${NEW_ESP_DIR}"
+	umount "${CUR_ESP_DIR}"
+}
+
+platform_do_upgrade() {
+	local board=$(board_name)
+	local diskdev partdev diff
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "platform_do_upgrade: Unable to determine upgrade device"
+		return 1
+	}
+
+	sync
+
+	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
+		get_partitions "/dev/$diskdev" bootdisk
+
+		v "Extract boot sector from the image"
+		get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+		get_partitions /tmp/image.bs image
+
+		#compare tables
+		diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+	else
+		diff=1
+	fi
+
+	# Only change the partition table if sysupgrade -p is set,
+	# otherwise doing so could interfere with embedded "single storage"
+	# (e.g SoC boot from SD card) setups, as well as other user
+	# created storage (like uvol)
+	if [ -n "$diff" ] && [ "${UPGRADE_OPT_SAVE_PARTITIONS}" = "0" ]; then
+		# Need to remove partitions before dd, otherwise the partitions
+		# that are added after will have minor numbers offset
+		partx -d - "/dev/$diskdev"
+
+		get_image_dd "$1" of="/dev/$diskdev" bs=4096 conv=fsync
+
+		# Separate removal and addtion is necessary; otherwise, partition 1
+		# will be missing if it overlaps with the old partition 2
+		partx -a - "/dev/$diskdev"
+
+		return 0
+	fi
+
+	#iterate over each partition from the image and write it to the boot disk
+	while read part start size; do
+		if export_partdevice partdev $part; then
+			v "Writing image to /dev/$partdev..."
+			if [ "$part" = "1" ]; then
+				platform_do_upgrade_efi_system_partition \
+					$1 $partdev $start $size || return 1
+			else
+				v "Normal partition, doing DD"
+				get_image_dd "$1" of="/dev/$partdev" ibs=512 obs=1M skip="$start" \
+					count="$size" conv=fsync
+			fi
+		else
+			v "Unable to find partition $part device, skipped."
+		fi
+	done < /tmp/partmap.image
+
+	local parttype=ext4
+
+	if (blkid > /dev/null) && export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+		if export_partdevice partdev 2; then
+			THIS_PART_BLKID=$(blkid -o value -s PARTUUID "/dev/${partdev}")
+			v "Setting rootfs PARTUUID=${THIS_PART_BLKID}"
+			sed -i "s/\(PARTUUID=\)[a-f0-9-]\+/\1${THIS_PART_BLKID}/ig" \
+				/mnt/efi/openwrt/grub.cfg
+		fi
+		umount /mnt
+	fi
+	# Provide time for the storage medium to flush before system reset
+	# (despite the sync/umount it appears NVMe etc. do it in the background)
+	sleep 5
+}
diff --git a/target/linux/phytium/config-5.10 b/target/linux/phytium/config-5.10
new file mode 100644
index 00000000000000..73a54d5efee6c5
--- /dev/null
+++ b/target/linux/phytium/config-5.10
@@ -0,0 +1,743 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+# CONFIG_ARCH_ACTIONS is not set
+# CONFIG_ARCH_AGILEX is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_ALPINE is not set
+# CONFIG_ARCH_BCM2835 is not set
+# CONFIG_ARCH_BCM_IPROC is not set
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_ARCH_BRCMSTB is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_K3 is not set
+# CONFIG_ARCH_LAYERSCAPE is not set
+# CONFIG_ARCH_LG1K is not set
+# CONFIG_ARCH_HISI is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_QCOM is not set
+# CONFIG_ARCH_RENESAS is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_ARCH_S32 is not set
+# CONFIG_ARCH_SEATTLE is not set
+# CONFIG_ARCH_STRATIX10 is not set
+# CONFIG_ARCH_SYNQUACER is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_THUNDER2 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VISCONTI is not set
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZX is not set
+# CONFIG_ARCH_ZYNQMP is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_NUMA=y
+CONFIG_SECCOMP=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_XEN=y
+CONFIG_COMPAT=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_HIBERNATION=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
+CONFIG_ARM_QCOM_CPUFREQ_HW=y
+CONFIG_ARM_TEGRA186_CPUFREQ=y
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_INTEL_STRATIX10_SERVICE=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_IMX_SCU=y
+CONFIG_IMX_SCU_PD=y
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ACPI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_KSM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_BPF_JIT=y
+# CONFIG_BT_HS is not set
+# CONFIG_BT_LE is not set
+CONFIG_BT_LEDS=y
+# CONFIG_BT_DEBUGFS is not set
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_PCI_AARDVARK=y
+CONFIG_PCI_TEGRA=y
+CONFIG_PCIE_RCAR_HOST=y
+CONFIG_PCIE_RCAR_EP=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCIE_ALTERA=y
+CONFIG_PCIE_ALTERA_MSI=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCI_HISI=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCIE_ARMADA_8K=y
+CONFIG_PCIE_KIRIN=y
+CONFIG_PCIE_HISI_STB=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_HISILICON_LPC=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_FSL_MC_BUS=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_MARVELL=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_SRAM=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_HISI_SAS=y
+CONFIG_SCSI_HISI_SAS_PCI=y
+CONFIG_MEGARAID_SAS=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_HISI=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_SATA_SIL24=y
+CONFIG_SATA_RCAR=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_MD=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VIRTIO_NET=y
+CONFIG_AMD_XGBE=y
+CONFIG_NET_XGENE=y
+CONFIG_MACB=y
+CONFIG_THUNDER_NIC_PF=y
+CONFIG_FEC=y
+CONFIG_FSL_FMAN=y
+CONFIG_FSL_DPAA_ETH=y
+CONFIG_FSL_DPAA2_ETH=y
+CONFIG_FSL_ENETC=y
+CONFIG_FSL_ENETC_VF=y
+CONFIG_FSL_ENETC_QOS=y
+CONFIG_HIX5HD2_GMAC=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
+CONFIG_HNS3=y
+CONFIG_HNS3_HCLGE=y
+CONFIG_HNS3_ENET=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
+CONFIG_IGBVF=y
+CONFIG_MVNETA=y
+CONFIG_MVPP2=y
+CONFIG_SKY2=y
+CONFIG_MLX5_CORE_EN=y
+CONFIG_SH_ETH=y
+CONFIG_RAVB=y
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+CONFIG_SNI_AVE=y
+CONFIG_SNI_NETSEC=y
+CONFIG_TI_K3_AM65_CPSW_NUSS=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_CROS_EC=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PM8941_PWRKEY=y
+CONFIG_INPUT_HISI_POWERKEY=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_OMAP=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MESON=y
+CONFIG_SERIAL_MESON_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIAL_TEGRA_TCU=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_QCOM_GENI=y
+CONFIG_SERIAL_QCOM_GENI_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
+CONFIG_SERIAL_OWL=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_I2C_MESON=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_OWL=y
+CONFIG_I2C_PXA=y
+CONFIG_I2C_QUP=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_TEGRA=y
+CONFIG_I2C_UNIPHIER_F=y
+CONFIG_I2C_RCAR=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SPI=y
+CONFIG_SPI_ARMADA_3700=y
+CONFIG_SPI_FSL_LPSPI=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_SPI_NXP_FLEXSPI=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_SPI_ORION=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_S3C64XX=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_MAX77620=y
+CONFIG_PINCTRL_OWL=y
+CONFIG_PINCTRL_S700=y
+CONFIG_PINCTRL_S900=y
+CONFIG_PINCTRL_IMX8MM=y
+CONFIG_PINCTRL_IMX8MN=y
+CONFIG_PINCTRL_IMX8MP=y
+CONFIG_PINCTRL_IMX8MQ=y
+CONFIG_PINCTRL_IMX8QXP=y
+CONFIG_PINCTRL_IMX8DXL=y
+CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_IPQ6018=y
+CONFIG_PINCTRL_MSM8916=y
+CONFIG_PINCTRL_MSM8994=y
+CONFIG_PINCTRL_MSM8996=y
+CONFIG_PINCTRL_MSM8998=y
+CONFIG_PINCTRL_QCS404=y
+CONFIG_PINCTRL_QDF2XXX=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_PINCTRL_SC7180=y
+CONFIG_PINCTRL_SDM845=y
+CONFIG_PINCTRL_SM8150=y
+CONFIG_PINCTRL_SM8250=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_MB86S7X=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_RCAR=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_XGENE_SB=y
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_MAX77620=y
+CONFIG_POWER_AVS=y
+CONFIG_QCOM_CPR=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_ARMADA_THERMAL=y
+CONFIG_EXYNOS_THERMAL=y
+CONFIG_QCOM_TSENS=y
+CONFIG_UNIPHIER_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ARM_SBSA_WATCHDOG=y
+CONFIG_ARM_SMC_WATCHDOG=y
+CONFIG_S3C2410_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_RENESAS_WDT=y
+CONFIG_UNIPHIER_WATCHDOG=y
+CONFIG_BCM2835_WDT=y
+CONFIG_MFD_ALTERA_SYSMGR=y
+CONFIG_MFD_BD9571MWV=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_HI6421_PMIC=y
+CONFIG_MFD_HI655X_PMIC=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_SL28CPLD=y
+CONFIG_MFD_ROHM_BD718XX=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BD718XX=y
+CONFIG_REGULATOR_BD9571MWV=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_HI6421V530=y
+CONFIG_REGULATOR_HI655X=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_MAX8973=y
+CONFIG_REGULATOR_PCA9450=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_RPMH=y
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+# CONFIG_DVB_NET is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DSI=y
+# CONFIG_DRM_EXYNOS_DP is not set
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_MIC=y
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_EFI=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_SAMSUNG=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_EXYNOS=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_EXYNOS=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_HI3798CV200=y
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MMC_OWL=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_EDAC=y
+CONFIG_EDAC_GHES=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_CROS_EC=y
+CONFIG_RTC_DRV_S3C=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_DRV_ARMADA38X=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BCM2835=y
+CONFIG_FSL_EDMA=y
+CONFIG_K3_DMA=y
+CONFIG_MV_XOR=y
+CONFIG_MV_XOR_V2=y
+CONFIG_OWL_DMA=y
+CONFIG_PL330_DMA=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_RCAR_DMAC=y
+CONFIG_TI_K3_UDMA=y
+CONFIG_TI_K3_UDMA_GLUE_LAYER=y
+CONFIG_VFIO=y
+CONFIG_VFIO_PCI=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_MFD_CROS_EC_DEV=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_FSL_SAI=y
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_VC5=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MQ=y
+CONFIG_CLK_IMX8QXP=y
+CONFIG_TI_SCI_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_QCOM_A53PLL=y
+CONFIG_QCOM_CLK_APCS_MSM8916=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_QCOM_CLK_RPMH=y
+CONFIG_IPQ_GCC_8074=y
+CONFIG_IPQ_GCC_6018=y
+CONFIG_MSM_GCC_8916=y
+CONFIG_MSM_GCC_8994=y
+CONFIG_MSM_MMCC_8996=y
+CONFIG_MSM_GCC_8998=y
+CONFIG_QCS_GCC_404=y
+CONFIG_SC_GCC_7180=y
+CONFIG_SDM_GCC_845=y
+CONFIG_SDM_GPUCC_845=y
+CONFIG_SDM_VIDEOCC_845=y
+CONFIG_SDM_DISPCC_845=y
+CONFIG_SM_GCC_8150=y
+CONFIG_SM_GCC_8250=y
+CONFIG_SM_GPUCC_8150=y
+CONFIG_SM_GPUCC_8250=y
+CONFIG_QCOM_HFPLL=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_ARM_MHU=y
+CONFIG_IMX_MBOX=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_BCM2835_MBOX=y
+CONFIG_QCOM_APCS_IPC=y
+CONFIG_QCOM_IPCC=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_QCOM_IOMMU=y
+CONFIG_REMOTEPROC=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_OWL_PM_DOMAINS=y
+CONFIG_RASPBERRYPI_POWER=y
+CONFIG_FSL_DPAA=y
+CONFIG_FSL_MC_DPIO=y
+# CONFIG_QCOM_AOSS_QMP is not set
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_RPMH is not set
+# CONFIG_QCOM_RPMHPD is not set
+# CONFIG_QCOM_RPMPD is not set
+# CONFIG_QCOM_SMEM is not set
+# CONFIG_QCOM_SMD_RPM is not set
+# CONFIG_QCOM_SMP2P is not set
+# CONFIG_QCOM_SMSM is not set
+# CONFIG_ARCH_R8A774A1 is not set
+# CONFIG_ARCH_R8A774B1 is not set
+# CONFIG_ARCH_R8A774C0 is not set
+# CONFIG_ARCH_R8A774E1 is not set
+# CONFIG_ARCH_R8A77950 is not set
+# CONFIG_ARCH_R8A77951 is not set
+# CONFIG_ARCH_R8A77960 is not set
+# CONFIG_ARCH_R8A77961 is not set
+# CONFIG_ARCH_R8A77965 is not set
+# CONFIG_ARCH_R8A77970 is not set
+# CONFIG_ARCH_R8A77980 is not set
+# CONFIG_ARCH_R8A77990 is not set
+# CONFIG_ARCH_R8A77995 is not set
+# CONFIG_ROCKCHIP_PM_DOMAINS is not set
+# CONFIG_ARCH_TEGRA_132_SOC is not set
+# CONFIG_ARCH_TEGRA_210_SOC is not set
+# CONFIG_ARCH_TEGRA_186_SOC is not set
+# CONFIG_ARCH_TEGRA_194_SOC is not set
+# CONFIG_ARCH_K3_AM6_SOC is not set
+# CONFIG_ARCH_K3_J721E_SOC is not set
+CONFIG_TI_SCI_PM_DOMAINS=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON_USBC_CROS_EC=y
+CONFIG_IIO=y
+CONFIG_EXYNOS_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SAMSUNG=y
+CONFIG_SL28CPLD_INTC=y
+CONFIG_QCOM_PDC=y
+CONFIG_RESET_IMX7=y
+CONFIG_RESET_QCOM_AOSS=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_PHY_XGENE=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_HI6220_USB=y
+CONFIG_PHY_HISTB_COMBPHY=y
+CONFIG_PHY_HISI_INNO_USB2=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
+CONFIG_PHY_RCAR_GEN3_PCIE=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_UNIPHIER_USB2=y
+CONFIG_PHY_UNIPHIER_USB3=y
+CONFIG_PHY_TEGRA_XUSB=y
+CONFIG_HISI_PMU=y
+CONFIG_QCOM_L2_PMU=y
+CONFIG_QCOM_L3_PMU=y
+CONFIG_NVMEM_IMX_OCOTP=y
+CONFIG_NVMEM_IMX_OCOTP_SCU=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_UNIPHIER_EFUSE=y
+CONFIG_FPGA=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_MUX_MMIO=y
+CONFIG_INTERCONNECT=y
+CONFIG_INTERCONNECT_QCOM=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_HUGETLBFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
+# CONFIG_SHORTCUT_FE is not set
+# CONFIG_RTL8821CS is not set
diff --git a/target/linux/phytium/e2000/base-files/lib/upgrade/platform.sh b/target/linux/phytium/e2000/base-files/lib/upgrade/platform.sh
new file mode 100755
index 00000000000000..cc16bda81c4488
--- /dev/null
+++ b/target/linux/phytium/e2000/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,35 @@
+PART_NAME=dtb:kernel:rootfs
+REQUIRE_IMAGE_METADATA=1
+
+platform_do_upgrade() {
+	local board=$(board_name)
+
+	case "$board" in
+	e2000q-demo-board |\
+	e2000d-demo-board |\
+	e2000q-miniitx-board |\
+	e2000d-miniitx-board)
+		default_do_upgrade "$1"
+		;;
+	esac
+}
+
+platform_check_image() {
+	local board=$(board_name)
+	local magic="$(get_magic_long "$1")"
+
+	case "$board" in
+	e2000q-demo-board|\
+	e2000d-demo-board|\
+	e2000q-miniitx-board|\
+	e2000d-miniitx-board)
+		[ "$magic" != "d00dfeed" ] && {
+			echo "Invalid image type."
+			return 1
+		}
+		return 0
+		;;
+	esac
+
+	return 0
+}
diff --git a/target/linux/phytium/e2000/config-5.10 b/target/linux/phytium/e2000/config-5.10
new file mode 100644
index 00000000000000..b4a812628976f9
--- /dev/null
+++ b/target/linux/phytium/e2000/config-5.10
@@ -0,0 +1,604 @@
+CONFIG_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PHYTIUM=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_MODULE_PLTS=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SVE=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_UAO=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_VHE=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=5
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_SCMI is not set
+CONFIG_COMPAT=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTIG_ALLOC=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_BLAKE2S=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_PHYTIUM_CORE=y
+# CONFIG_GPIO_PHYTIUM_PCI is not set
+CONFIG_GPIO_PHYTIUM_PLAT=y
+# CONFIG_GPIO_PHYTIUM_SGPIO is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+# CONFIG_HARDENED_USERCOPY is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HOLES_IN_ZONE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KSM=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_PHYTIUM_MCI_PLTFM is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_XPCS=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHYTIUM_MBOX=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RTL8821CS is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_HOST=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SG_POOL=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_PHYTIUM=y
+# CONFIG_SPI_PHYTIUM_PCI is not set
+CONFIG_SPI_PHYTIUM_PLAT=y
+CONFIG_SPI_PHYTIUM_QSPI=y
+CONFIG_SPI_PHYTIUM_QUADSPI=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_DP_ALTMODE is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_UACCE is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_PHYTIUM=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WATCHDOG is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/phytium/e2000/target.mk b/target/linux/phytium/e2000/target.mk
new file mode 100644
index 00000000000000..3f1d89d92c3819
--- /dev/null
+++ b/target/linux/phytium/e2000/target.mk
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Phytium Technology Co., Ltd.
+
+ARCH:=aarch64
+SUBTARGET:=e2000
+BOARDNAME:=E2000
+
+define Target/Description
+	Build firmware image for Phytium E2000 devices.
+endef
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/dma/phytium-ddma.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/dma/phytium-ddma.yaml
new file mode 100644
index 00000000000000..7dbe7c44ff5477
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/dma/phytium-ddma.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+title: Phytium DDMA Controller bindings
+
+description:
+  The Phytium DDMA is a general-purpose direct memory access controller capable of
+  supporting 8 independent DMA channels. Each channel can have up to 32 requests.
+  DMA clients connected to the Phytium DDMA controller must use the format
+  described in the dma.txt file, using a two-cell specifier for each
+  channel: a phandle to the DMA controller plus the following two integer cells:
+    1. The channel id
+    2. The request line number
+
+maintainers:
+  - Huang Jie <huangjie1663@phytium.com.cn>
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  "#dma-cells":
+    const: 2
+
+  compatible:
+    const: phytium,ddma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  dma-channels:
+    minItems: 1
+    maxItems: 8
+    description: it indicates that the number of channels are used
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - dma-channels
+
+unevaluatedProperties: false
+
+examples:
+    ddma0: ddma@28003000 {
+        compatible = "phytium,ddma";
+        reg = <0x0 0x28003000 0x0 0x1000>;
+        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+        #dma-cells = <2>;
+        dma-channels = <8>;
+    };
+...
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/edac/phytium-pe220x-edac.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/edac/phytium-pe220x-edac.txt
new file mode 100644
index 00000000000000..ddbf14b018968b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/edac/phytium-pe220x-edac.txt
@@ -0,0 +1,23 @@
+* Phytium Pe220x SoC EDAC node
+
+EDAC node is defined to describe on-chip error detection and correction.
+The follow error types are supported:
+
+  SoC			- SoC IP's such as Ethernet, SATA, and etc
+
+The following section describes the EDAC DT node binding.
+
+Required properties:
+- compatible: Shall be "phytium,pe220x-edac".
+- reg: Shall be the Pe220x RAS resource.
+- interrupts: Interrupt-specifier for RAS error IRQ(s).
+
+Example:
+	edac: edac@32b28000 {
+		compatible = "phytium,pe220x-edac";
+		reg = <0x0 0x32b28000 0x0 0x1000>,
+			<0x0 0x31400000 0x0 0x1000>,
+			<0x0 0x31401000 0x0 0x1000>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+	};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/gpio/gpio-phytium-sgpio.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/gpio/gpio-phytium-sgpio.txt
new file mode 100644
index 00000000000000..65c5c1b9bf42aa
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/gpio/gpio-phytium-sgpio.txt
@@ -0,0 +1,32 @@
+* Phytium SGPIO controller
+
+This SGPIO controller is for Phytium Pe220x SoC, which supports up to
+96 (32x3) Serial GPIOs.
+
+Required properties:
+- compatible : Should contain "phytium,gpio"
+- reg : Address and length of the register set for the device.
+- interrupts: Interrupt mapping for GPIO IRQ.
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be 2. The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+      0 = active high
+      1 = active low
+- ngpios: number of GPIO lines, see gpio.txt
+          (should be multiple of 32, up to 96 pins)
+- bus-frequency: SGPIO CLK frequency
+- clocks: A phandle to the APB clock for SGPIO clock division
+
+Example:
+
+	sgpio: sgpio@2807d000 {
+		compatible = "phytium,sgpio";
+		reg = <0x0 0x2807d000 0x0 0x1000>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_48mhz>;
+		ngpios = <96>;
+		bus-frequency = <48000>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/gpio/phytium,gpio.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/gpio/phytium,gpio.yaml
new file mode 100755
index 00000000000000..0a6dfd4085b476
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/gpio/phytium,gpio.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/phytium,gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium GPIO controller
+
+description: |
+  Phytium GPIO controllers have one or two configurable ports, each of which
+  are intended to be represented as child nodes with the generic GPIO-controller
+  properties as desribed in this bindings file.
+
+maintainers:
+  - Chen Baozi <chenbaozi@phytium.com.cn>
+
+properties:
+  $nodename:
+    pattern: "^gpio@[0-9a-f]+$"
+
+  compatible:
+    const: phytium,gpio
+
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+  '#gpio-cells':
+    const: 2
+
+  interrupts:
+    description: |
+      The interrupts to the parent controller raised when GPIOs generate
+      the interrupts. If the controller provides one combined interrupt
+      for all GPIOs, specify a single interrupt. If the controller provides
+      one interrupt for each GPIO, provide a list of interrupts that
+      correspond to each of the GPIO pins.
+    minItems: 1
+    maxItems: 32
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+patternProperties:
+  "^gpio-(port|controller)@[0-9a-f]+$":
+    type: object
+    properties:
+      compatible:
+        const: phytium,gpio-port
+
+      reg:
+        maxItems: 1
+
+     nr-gpios:
+        description: The number of GPIO pins exported by the port.
+        default: 32
+        minimum: 1
+        maximum: 32
+
+    required:
+      - compatible
+      - reg
+      - gpio-controller
+      - '#gpio-cells'
+
+    dependencies:
+      interrupt-controller: [ interrupts ]
+
+    additionalProperties: false
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+
+examples:
+  - |
+    gpio: gpio@28004000 {
+      compatible = "phytium,gpio";
+      reg = <0x0 0x28004000 0x0 0x1000>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+      interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+
+      porta: gpio-port@0 {
+        compatible = "phytium,gpio-port";
+        reg = <0>;
+        nr-gpios = <8>;
+      };
+
+      portb: gpio-port@1 {
+        compatible = "phytium,gpio-port";
+        reg = <1>;
+        nr-gpios = <8>;
+      };
+};
+...
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/hwlock/phytium-hwspinlock.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/hwlock/phytium-hwspinlock.txt
new file mode 100644
index 00000000000000..f39c86492bc9d4
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/hwlock/phytium-hwspinlock.txt
@@ -0,0 +1,21 @@
+Phytium HwSpinlock Driver
+========================
+
+Required properties:
+- compatible:		Should be "phytium,hwspinlock"
+- reg:			Contains the hwspinlock module register address space
+			(base address and length)
+- #hwlock-cells:	Should be 1.
+- nr-locks:		The number of locks in the device.
+
+Please look at the generic hwlock binding for usage information for consumers,
+"Documentation/devicetree/bindings/hwlock/hwlock.txt"
+
+Example:
+
+hwspinlock: spinlock@40000000 {
+	compatible = "phytium,hwspinlock";
+	reg = <0x40000000 0x1000>;
+	#hwlock-cells = <1>;
+	nr-locks = <32>;
+};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/hwmon/tacho-phytium.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/hwmon/tacho-phytium.txt
new file mode 100755
index 00000000000000..0d02b0684c13f1
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/hwmon/tacho-phytium.txt
@@ -0,0 +1,48 @@
+Phytium Fan Tacho and capture counter controller device driver
+
+The controller can support one input signal. The function of controller is to
+measure the speed of fan and the edge number of input signal. The function
+can be selected by devicetree setting. The edging mode and anti-jitter level
+can also setted in devicetree.
+
+Required properties for tacho node:
+- #address-cells : should be 1.
+
+- #size-cells : should be 1.
+
+- reg : address and length of the register set for the device.
+
+- compatible : should be "phytium,tacho"
+
+- clocks : phandle to clock provider with the clock number in the second cell
+
+Optional properties for tacho node:
+
+- tacho : set the controller work as fan tachometer, which is a default option.
+
+- capture : set the controller work as capture counter.
+
+-------------------------------------------------------------------------------
+
+- up : set the input edging mode as ascending, which is a default option.
+
+- down : set the input edging mode as descending.
+
+- double : set the input edging mode as doule-edging.
+
+-------------------------------------------------------------------------------
+
+- debounce-level : set the debounce-levle, which can be 0, 1, 2 and 3.
+
+Examples:
+
+tacho: tacho@28054000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg = <0x0 0x28054000 0x0 0x1000>;
+	compatible = "phytium,tacho";
+	clocks = <&sysclk>;
+	tacho;
+	up;
+	debounce-level = <2>;
+};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/i2c/phytium,i2c.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/i2c/phytium,i2c.yaml
new file mode 100755
index 00000000000000..62f496d0c175da
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/i2c/phytium,i2c.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium I2C/SMBus Controller
+
+maintainers:
+  - Chen Baozi <chenbaozi@phytium.com.cn>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    const: phytium,i2c
+
+  reg:
+    minItems: 1
+    items:
+      - description: Offset and length of the memory mapped registers
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: I2C controller reference clock source
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    i2c0: i2c@28011000 {
+      compatible = "phytium,i2c";
+      reg = <0x0 0x28011000 0x0 0x1000>;
+      interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+      interrupt-names = "smbus_alert";
+      clocks = <&sysclk_48mhz>;
+    };
+...
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/iio/adc/phytium-adc.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/iio/adc/phytium-adc.txt
new file mode 100755
index 00000000000000..edf0823d76c9b5
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/iio/adc/phytium-adc.txt
@@ -0,0 +1,57 @@
+Phytium ADC
+
+This device is a 10-bit converter for 8 voltage channels. All inputs are
+single ended.
+
+Required properties:
+- compatible: Should be "phytium,adc"
+- reg: memory window mapping address and length
+- interrupts: Interrupt for the ADC control interface.
+- clocks: Input clock used to derive the sample clock.
+- #address-cells: Should be <1> (settings for the subnodes).
+- #size-cells: Should be <0> (settings for the subnodes).
+
+Required subnodes:
+
+The ADC channels are configured as subnodes of the ADC.
+
+Required channel node properties:
+
+- reg: should contain the hardware channel number.
+
+Examples:
+
+	adc0: adc@2807b000 {
+		compatible = "phytium,adc";
+		reg = <0x0 0x2807b000 0x0 0x1000>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_48mhz>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@0 {
+			reg = <0>;
+		};
+		channel@1 {
+			reg = <1>;
+		};
+		channel@2 {
+			reg = <2>;
+		};
+		channel@3 {
+			reg = <3>;
+		};
+		channel@4 {
+			reg = <4>;
+		};
+		channel@5 {
+			reg = <5>;
+		};
+		channel@6 {
+			reg = <6>;
+		};
+		channel@7 {
+			reg = <7>;
+		};
+	};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/input/phytium-keypad.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/input/phytium-keypad.txt
new file mode 100755
index 00000000000000..b34e6a1b367821
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/input/phytium-keypad.txt
@@ -0,0 +1,41 @@
+* Phytium Keypad Port device tree bindings
+
+The keypad port is designed to interface with a keypad matrix, which
+simplify the software task of scanning a keypad matrix. It is capable
+of detecting, debouncing, and decoding one or multiple keys pressed
+simultaneously on a keypad.
+
+Required SoC Specific Properties:
+- compatible: Should be "phytium,keypad".
+- reg: Physical base address and length of memory mapped region.
+- interrupts: Interrupt number to the CPU(s).
+
+Required Board Specific Properties:
+- linux,keymap: The definition can be found at
+bindings/input/matrix-keymap.txt.
+
+Example:
+
+keypad: keypad@2807a000 {
+	compatible = "phytium,keypad";
+	reg = <0x 0x2807a000 0x0 0x1000>;
+	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+	keypad,num-rows = <4>;
+	keypad,num-columns = <4>;
+	linux,keymap = <0x00000067	/* KEY_UP */
+			0x0001006c	/* KEY_DOWN */
+			0x00020072	/* KEY_VOLUMEDOWN */
+			0x00030066	/* KEY_HOME */
+			0x0100006a	/* KEY_RIGHT */
+			0x01010069	/* KEY_LEFT */
+			0x0102001c	/* KEY_ENTER */
+			0x01030073	/* KEY_VOLUMEUP */
+			0x02000040	/* KEY_F6 */
+			0x02010042	/* KEY_F8 */
+			0x02020043	/* KEY_F9 */
+			0x02030044	/* KEY_F10 */
+			0x0300003b	/* KEY_F1 */
+			0x0301003c	/* KEY_F2 */
+			0x0302003d	/* KEY_F3 */
+			0x03030074>;	/* KEY_POWER */
+};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/interrupt-controller/phytium,ixic.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/interrupt-controller/phytium,ixic.txt
new file mode 100644
index 00000000000000..82180b38bb6b62
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/interrupt-controller/phytium,ixic.txt
@@ -0,0 +1,28 @@
+Phytium INTx interrupt controller (IXIC)
+
+This is a pseudo interrupt controller to handle PCI legacy interrupt on
+some Phytium SoCs, which sits between the PCI INTx devices and the GIC
+and forwards the 4 INTx input signals to 4 adjacent GICv3 SPIs.
+
+Required properties:
+
+- compatible		: "phytium,ixic"
+- reg			: Specifies two regions of the register set, which
+			  are called 'ctr' and 'hpb'.
+- interrupt-controller	: Identifies the node as an interrupt controller.
+- #interrupt-cells	: Specifies the number of cells needed to encode an
+			  interrupt source. The value must be 3.
+- intx-spi-base		: The SPI number of the first SPI of the 4 adjacent
+			  ones the IXIC forwards its interrupts to.
+
+Example:
+	ixic: interrupt-controller@29000000 {
+		compatible = "phytium,ixic";
+		reg-names = "ctr", "hpb";
+		reg = <0x0 0x29000000 0x0 0x00060000>,
+		      <0x0 0x29100000 0x0 0x00002000>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <3>;
+		intx-spi-base = <28>;
+	};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/interrupt-controller/phytium,ixic.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/interrupt-controller/phytium,ixic.yaml
new file mode 100755
index 00000000000000..67b17652e9e6ee
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/interrupt-controller/phytium,ixic.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/phytium,ixic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium INTx interrupt controller (IXIC)
+
+description: |
+This is a psuedo interrupt controller to handle PCI legacy interrupt on
+Phytium D2000 and FT-2000/4C SoC, which sits between the PCI INTx devices
+and the GIC and forwards the 4 INTx input signals to 4 adjacent GICv3 SPIs.
+
+maintainers:
+  - Chen Baozi <chenbaozi@phytium.com.cn>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - phytium,d2000-ixic
+      - phytium,ft2004c-ixic
+
+  reg:
+    description: |
+      Specifies two regions of the register set, which are called
+      'ctr' and 'hpb'
+    minItems: 2
+    maxItems: 2
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    description: |
+      Specifies the number of cells needed to encode an interrupt source.
+    const: 3
+
+  intx-spi-base:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      The SPI number of the first SPI of the 4 adjacent ones the IXIC
+      forwards its interrupts to.
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+  - intx-spi-base
+
+additionalProperties: false
+
+examples:
+  - |
+    ixic: interrupt-controller@29000000 {
+      compatible = "phytium,d2000-ixic";
+      reg-names = "ctr", "hpb";
+      reg = <0x0 0x29000000 0x0 0x00060000>,
+            <0x0 0x29100000 0x0 0x00002000>;
+      interrupt-controller;
+      interrupt-parent = <&gic>;
+      #interrupt-cells = <3>;
+      intx-spi-base = <28>;
+    };
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mailbox/phytium,mbox.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mailbox/phytium,mbox.yaml
new file mode 100755
index 00000000000000..1061d26f2cf880
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mailbox/phytium,mbox.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium Mailbox Controller
+
+maintainers:
+  - Chen Baozi <chenbaozi@phytium.com.cn>
+
+description: |
+  The Phytium mailbox controller that has a channel/link to communicate
+  with the remote end. A link raises interrupt for any received data. However,
+  there is no specified way of knowing if the sent data has been read by the
+  remote. This driver assumes the sender polls STAT register and the remote
+  clears it after having read the data.
+
+properties:
+  compatible:
+    - enum: phytium,mbox
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: |
+      Contains the interrupt information corresponding to the link
+    maxItems: 1
+
+  '#mbox-cells':
+    description: |
+      It should be 1, which is the index of the channel needed.
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - '#mbox-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    mbox: mailbox@2a000000 {
+    	compatible = "phytium,mbox";
+    	reg = <0x0 0x2a000000 0x0 0x1000>;
+    	#mbox-cells = <1>;
+    	interrupts = <0 48 4>;
+    };
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/media/phytium-jpeg.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/media/phytium-jpeg.txt
new file mode 100755
index 00000000000000..c79e47f30b9a04
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/media/phytium-jpeg.txt
@@ -0,0 +1,21 @@
+* Device tree bindings for Phytium JPEG Engine
+
+The JPEG Engine embedded in the Phytium SOCs can capture
+and compress video data from digital or analog sources.
+
+Required properties:
+ - compatible:		"phytium,jpeg"
+ - reg:			 contains the offset and length of the
+			 JPEG Engine memory region
+ - interrupts:		 the interrupt associated with the VE on this platform
+ - phytium,ocm-buf-addr  the physical address used to storage the inputing video data
+
+Example:
+
+jpeg: jpeg@32b32000 {
+		compatible = "phytium,jpeg";
+		reg = <0x0 0x32b32000 0 0x1000>;
+		interrupts = <0 41 4>;
+		phytium,ocm-buf-addr = <0x30c40000 0x30c60000>;
+		status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mmc/phytium,sdci.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mmc/phytium,sdci.yaml
new file mode 100755
index 00000000000000..1364583c90e867
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mmc/phytium,sdci.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/phytium,sdci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium SDCI Controller Binding
+
+maintainers:
+  - Chen Baozi <chenbaozi@phytium.com.cn>
+
+allOf:
+  - $ref: mmc-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - phytium,sdci
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 3
+    maxItems: 3
+
+  clocks:
+    minItems: 1
+    items:
+      - description: core clock
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: phytium_sdc_clk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    sdci: sdci@28207c00 {
+      compatible = "phytium,sdci";
+      reg = <0x0 0x28207c00 0x0 0x100>;
+      interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&sysclk_600mhz>;
+      clock-names = "phytium_sdc_clk";
+    };
+
+...
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mmc/phytium-mci.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mmc/phytium-mci.txt
new file mode 100755
index 00000000000000..129efb1fb2f694
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/mmc/phytium-mci.txt
@@ -0,0 +1,36 @@
+* Phytium Multimedia Card Interface controller
+
+The highspeed MMC host controller on Phytium SoCs provides an interface
+for MMC, SD and SDIO types of memory cards.
+
+Required properties:
+- compatible : should be "phytium,mci".
+- reg: mmc controller base registers.
+- clocks : phandles to input clocks.
+- clock-names : should be "phytium_mci_clk".
+- interrupts : mmc controller interrupt.
+
+Examples:
+	- Within .dtsi:
+	mmc0: mmc@28000000 {
+		compatible = "phytium,mci";
+		reg = <0x0 0x28000000 0x0 0x1000>;
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_1200mhz>;
+		clock-names = "phytium_mci_clk";
+		status = "disabled";
+	};
+
+	- Within dts:
+	&mmc0 {
+		bus-width = <4>;
+		max-frequency = <50000000>;
+		cap-sdio-irq;
+		cap-sd-highspeed;
+		sd-uhs-sdr12;
+		sd-uhs-sdr25;
+		sd-uhs-sdr50;
+		no-mmc;
+		status = "ok";
+	};
+
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/net/can/phytium-can.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/net/can/phytium-can.txt
new file mode 100755
index 00000000000000..ab109e54052c8f
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/net/can/phytium-can.txt
@@ -0,0 +1,29 @@
+Phytium CAN controller
+------------------------
+
+Required properties:
+- compatible: Should be:
+              - "phytium,can" for Phytium CAN controllers
+              - "phytium,canfd" for Phytium CAN controllers with CANFD support
+- reg: Should contain CANFD controller registers location and length
+- interrupts: Should contain IRQ line for the CANFD controller
+- clocks: CLocks used by the controller
+- clock-names: Input clock names, should be "can_clk"
+- tx-fifo-depth: Indicates the length of TX FIFO
+- rx-fifo-depth: Indicates the length of TX FIFO
+
+Optional property:
+- extend_brp: Indicates to apply the extend BRP parameter of bit timming for
+              early version of CAN controller
+
+Example:
+
+	can0: can@2800a000{
+		compatible = "phytium,canfd";
+		reg = <0x0 0x2800a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_600mhz>;
+		clock-names = "can_clk";
+		tx-fifo-depth = <64>;
+		rx-fifo-depth = <64>;
+	};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/net/phytium,gmac.yaml b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/net/phytium,gmac.yaml
new file mode 100755
index 00000000000000..486f10a80c278e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/net/phytium,gmac.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/phytium,gmac.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Phytium 10/100/1000 Ethernet driver (GMAC)
+
+maintainers:
+  - Chen Baozi <chenbaozi@phytium.com.cn>
+
+# We need a select here so we don't match all nodes with 'snps,dwmac'
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - phytium,gmac
+  required:
+    - compatible
+
+allOf:
+  - $ref: "snps,dwmac.yaml#"
+
+properties:
+  compatible:
+      - items:
+          - enum:
+              - phytium,gmac
+
+  clock-frequency: true
+
+required:
+  - compatible
+  - clock-frequency
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    gmac0: eth@2820c000 {
+        compatible = "phytium,gmac";
+        reg = <0x0 0x2820c000 0x0 0x2000>;
+        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+        clock-frequency = <250000000>;
+
+        snps,pbl = <16>;
+        snps,fixed-burst;
+        snps,multicast-filter-bins = <64>;
+        snps,perfect-filter-entries = <128>;
+        tx-fifo-depth = <4096>;
+        rx-fifo-depth = <4096>;
+        max-frame-size = <9000>;
+    };
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/pwm/pwm-phytium.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/pwm/pwm-phytium.txt
new file mode 100755
index 00000000000000..0285e95a373090
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/pwm/pwm-phytium.txt
@@ -0,0 +1,23 @@
+Phytium PWM controller
+
+Required properties:
+- compatible: should be "phytium,pwm"
+- reg: physical base address and length of the controller's registers
+- interrupts:  interrupt for the pwm controller
+- clocks : clock specifiers for both ipg and per clocks.
+- phytium,db: One or two <cntmod dutymod div updbcly dbpolarity> to describe dead-band configurations.
+              "cntmod" indicates the counter mode (0 for modulo, 1 for up-and-down).
+              "dutymod" indicdates which duty to compare with (0 for PMW_CCR, 1 for FIFO).
+              "div" selects the clock divider value, from 0 to 1023.
+              "updbcly" selects the rising edge delay cycles.
+              "dbpolarity" selects the polarity for dead-band.
+
+Example:
+
+pwm0: pwm@2804a000 {
+	compatible = "phytium,pwm";
+	reg= <0x0 0x2804a000 0x0 0x1000>;
+	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&sysclk_48mhz>;
+	phytium,db = <0 0 0 1000 0>;
+};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/remoteproc/homo-rproc.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/remoteproc/homo-rproc.txt
new file mode 100644
index 00000000000000..00f4c4402ece3c
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/remoteproc/homo-rproc.txt
@@ -0,0 +1,39 @@
+homogeneous remoteproc driver
+==========================================
+
+This driver implements communication between remote processors under a homogeneous CPU architecture(SMP).
+
+Homogeneous RemoteProc Device Node:
+=================================
+A homo_remoteproc device node is used to represent the remote core instance within SoC.
+
+Required properties:
+--------------------
+ - compatible : should be "homo,rproc"
+ - remote-processor: remote processor's linux cpu logical number
+ - inter-processor-interrupt: IPI/SGI interrupt number, default is 9
+ - memory-region: reserved memory which will be used by remote processor
+ - firmware-name: the name of openamp image, default is "openamp_core0.elf"
+
+Example:
+--------
+
+    reserved-memory {
+        #address-cells = <0x2>;
+        #size-cells = <0x2>;
+        ranges;
+
+        rproc: rproc@b0100000 {
+            no-map;
+            reg = <0x0 0xb0100000 0x0 0x19900000>;
+        };
+    };
+
+    homo_rproc: homo_rproc@0 {
+        compatible = "homo,rproc";
+        remote-processor = <3>;
+        inter-processor-interrupt = <9>;
+        memory-region = <&rproc>;
+        firmware-name = "openamp_core0.elf";
+        status = "disabled";
+    };
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/rng/phytium-rng.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/rng/phytium-rng.txt
new file mode 100755
index 00000000000000..ee893f65c94ce4
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/rng/phytium-rng.txt
@@ -0,0 +1,13 @@
+Phytium Random Number Generator
+
+Required properties:
+- compatible : Should be "phytium,rng"
+- reg : Offset and length of the register set of this block
+
+Example:
+
+	rng@0x31a06000 {
+		compatible = "phytium,rng";
+		reg = <0x0 0x31a06000 0x0 0x1000>;
+	};
+
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/spi/spi-phytium.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/spi/spi-phytium.txt
new file mode 100755
index 00000000000000..a674d192132c0c
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/spi/spi-phytium.txt
@@ -0,0 +1,24 @@
+Phytium SPI controller
+
+Required properties:
+- compatible: should be "phytium,spi"
+- #address-cells: see spi-bus.txt
+- #size-cells: see spi-bus.txt
+- reg: address and length of the spi master registers
+- interrupts: should contain one interrupt
+- clocks: spi clock phandle
+- num-cs: see spi-bus.txt
+
+Optional properties:
+- cs-gpios: see spi-bus.txt
+
+Example:
+
+
+spi0: spi@2800c000 {
+	compatible = "phytium,spi";
+	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+	reg = <0x0 0x2800c000 0x0 0x1000>;
+	clocks = <&sysclk_48mhz>;
+	num-cs = <4>;
+};
diff --git a/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/w1/phytium-w1.txt b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/w1/phytium-w1.txt
new file mode 100755
index 00000000000000..43784c3aa6de16
--- /dev/null
+++ b/target/linux/phytium/files-5.10/Documentation/devicetree/bindings/w1/phytium-w1.txt
@@ -0,0 +1,14 @@
+* Phytium 1-wire bus master controller
+
+Required properties:
+- compatible : should be "phytium,w1"
+- reg : Address and length of the register set for the device
+- interrupts : interrupt line.
+
+Example:
+
+  onewire0: onewire@2803f000 {
+	compatible = "phytium,w1";
+	reg = <0x0 0x2803f000 0x0 0x1000>;
+	interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+  };
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/Makefile b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/Makefile
new file mode 100644
index 00000000000000..037b33ba929c23
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+
+## pe220x general demo development board series.
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-demo-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-demo-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000s-demo-board.dtb
+
+## pe220x specific industry development board series.
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-miniitx-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-miniitx-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-vpx-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-edu-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-come-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-power-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000q-hanwei-board.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += phytiumpi_firefly.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += e2000d-chillipi-edu-board.dtb
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts
new file mode 100644
index 00000000000000..28a1f0d47b743b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-chillipi-edu-board.dts
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2202 chillipi education board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2202.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+
+
+/{
+	model = "Pe2202 CHILLIPI EDUCATION BOARD";
+	compatible = "phytium,pe2202";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,pin-switches = "mic-in";
+		simple-audio-card,widgets = "Microphone","mic-in";
+		simple-audio-card,routing = "MIC2","mic-in";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec{
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio6: i2c@28020000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28020000 0x0 0x1000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		oled@3c {
+			compatible = "SinoWealth,sh1106";
+			reg = <0x3c>;
+		};
+
+		pcf8591@48 {
+			compatible = "philips,pcf8591";
+			reg = <0x48>;
+		};
+	};
+	
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		/* localized chillipi education board use this rtc device */
+		rtc@32 {
+			compatible = "wave,sd3068";
+			reg = <0x32>;
+			status = "disabled";
+		};
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+			status = "disabled";
+		};
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 5  GPIO_ACTIVE_LOW>;
+			sel-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+			#sound-dai-cells = <0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+			status = "disabled";
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&watchdog1 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "host";
+	status = "disabled";
+};
+
+&usb2_2 {
+	dr_mode = "host";
+	status = "disabled";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+/*
+ * In chillipi education board, M.2 interface may insert two types of disks: PCIE (nvme protocol) or SATA (ahci protocol),
+ * so here enable 'sata0' node by default to correspond to the sata drive case. Pin multiplexing exists
+ * in PCIE2 and SATA0, when used as a boot disk, the BIOS can automatically recognize these two conditions.
+ */
+&sata0 {
+	status = "disabled";
+};
+
+&sata1 {
+	status = "disabled";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "okay";
+
+	ILI9488@0 {
+		compatible = "ilitek,ili9488";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+
+		rotate = <0>;
+		fps = <30>;
+		buswidth = <8>;
+		regwidth = <8>;
+		bgr;
+		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+		dc-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+		//cs-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+
+		//backlight = <&backlight>;
+		debug = <0>;
+	};
+
+	ADS7843@1 {
+		compatible = "ti,ads7843";
+		spi-max-frequency = <1000000>;
+		reg = <1>;
+		//cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <12 0>;
+		pendown-gpio = <&gpio4 12 0>;
+
+		ti,x-min = /bits/ 16 <0>;
+		//ti,x-max = /bits/ 16 <8000>;
+		ti,x-max = /bits/ 16 <3200>;
+		ti,y-min = /bits/ 16 <0>;
+		//ti,y-max = /bits/ 16 <4800>;
+		ti,y-max = /bits/ 16 <4800>;
+		ti,x-plate-ohms = /bits/ 16 <40>;
+		ti,pressure-max = /bits/ 16 <255>;
+
+		wakeup-source;
+	};
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "okay";
+
+	mpu6500@0 {
+		compatible = "InvenSense,mpu6500";
+		spi-max-frequency = <500000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <0x00000008>;
+	max-frequency = <100000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <0x00000004>;
+	max-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&dc0 {
+	pipe_mask = /bits/ 8 <0x2>;
+	edp_mask = /bits/ 8 <0x0>;
+	status = "okay";
+};
+
+&i2s_dp1 {
+	status = "okay";
+};
+
+&pmdk_dp {
+	num-dp = <1>;
+	dp-mask = /bits/ 8 <0x2>;
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
+
+&pwm0 {
+	phytium,db = <0 0 0 1000 1000 0>;
+	status = "okay";
+};
+
+&pwm1 {
+	phytium,db = <0 0 0 1000 1000 0>;
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts
new file mode 100644
index 00000000000000..bdfe8f2fc29d90
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-demo-board.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2202 demo board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2202.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+
+
+/{
+	model = "Pe2202 DEMO DDR4";
+	compatible = "phytium,pe2202";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,pin-switches = "mic-in";
+		simple-audio-card,widgets = "Microphone","mic-in";
+		simple-audio-card,routing = "MIC2","mic-in";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec{
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		/* localized demo board use this rtc device */
+		rtc@32 {
+			compatible = "wave,sd3068";
+			reg = <0x32>;
+		};
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 5  GPIO_ACTIVE_LOW>;
+			sel-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+			#sound-dai-cells = <0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&watchdog1 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_2 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+/*
+ * In demo board, M.2 interface may insert two types of disks: PCIE (nvme protocol) or SATA (ahci protocol),
+ * so here enable 'sata0' node by default to correspond to the sata drive case. Pin multiplexing exists
+ * in PCIE2 and SATA0, when used as a boot disk, the BIOS can automatically recognize these two conditions.
+ */
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <0x00000008>;
+	max-frequency = <100000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <0x00000004>;
+	max-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&dc0 {
+	pipe_mask = /bits/ 8 <0x2>;
+	edp_mask = /bits/ 8 <0x0>;
+	status = "okay";
+};
+
+&i2s_dp1 {
+	status = "okay";
+};
+
+&pmdk_dp {
+	num-dp = <1>;
+	dp-mask = /bits/ 8 <0x2>;
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts
new file mode 100644
index 00000000000000..631c967c1c02e3
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-miniitx-board.dts
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2202 miniitx board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Hongmin Qi <qihongmin@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2202.dtsi"
+
+/{
+	model = "Pe2202 MINIITX Board";
+	compatible = "phytium,pe2202";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x1 0x00000000>;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio0: uart@28014000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28014000 0x0 0x1000>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "disabled";
+	};
+
+	mio1: uart@28016000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28016000 0x0 0x1000>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "disabled";
+	};
+
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio6: uart@28020000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28020000 0x0 0x1000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio7: uart@28022000  {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28022000 0x0 0x1000>;
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 5 0>;
+			sel-gpios = <&gpio2 6 0>;
+			#sound-dai-cells = <0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+			mic-src = [20];
+		};
+	};
+
+	mio15: uart@28032000  {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "host";
+	status = "disabled";
+};
+
+&usb2_2 {
+	dr_mode = "host";
+	status = "disabled";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb1 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "disabled";
+};
+
+&macb2 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb3 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "disabled";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "disabled";
+
+	flash: w25q128@0 {
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		spi-max-frequency = <12000000>;
+		reg = <0x00>;
+		status = "disabled";
+	};
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&spi3 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&mmc0 {
+	status = "okay";
+	bus-width = <0x4>;
+	max-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-mmc;
+};
+
+&mmc1 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&dc0 {
+	status = "okay";
+	pipe_mask = [02];
+	edp_mask = [00];
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	dai-name = "phytium-i2s-lsd";
+	status = "okay";
+};
+
+&pwm1 {
+	phytium,db = <0 0 0 1000 1000 0>;
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-power-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-power-board.dts
new file mode 100755
index 00000000000000..8d481b8c1b4872
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000d-power-board.dts
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2202 power board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Hongmin Qi <qihongmin@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2202.dtsi"
+
+/{
+	model = "Pe2202S power Board";
+	compatible = "phytium,pe2202";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x1 0x00000000>;
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <0x0 0x65 0x4>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		status = "okay";
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio6: i2c@28020000 {
+		status = "okay";
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28020000 0x0 0x1000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		eeprom@50 {
+			compatible = "atmel,24c02";
+			reg = <0x50>;
+			pagesize = <1>;
+		};
+	};
+
+	mio10: uart@28028000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28028000 0x0 0x1000>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio11: uart@2802a000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x2802a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio13: uart@2802e000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x2802e000 0x0 0x1000>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio14: uart@28030000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb1 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb2 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb3 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "disabled";
+};
+
+&dc0 {
+	pipe_mask = [02];
+	edp_mask = [00];
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&mmc0 {
+	bus-width = <8>;
+	max-frequency = <50000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&mmc1 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-come-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-come-board.dts
new file mode 100755
index 00000000000000..f98655dd49e473
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-come-board.dts
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2204 come board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Hongmin Qi <qihongmin@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2204.dtsi"
+
+/{
+	model = "Pe2204 come Board";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+};
+
+&soc {
+	mio3: i2c@2801a000 {
+		status = "okay";
+		compatible = "phytium,i2c";
+		reg = <0x0 0x2801a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eeprom@50 {
+			compatible = "atmel,24c02";
+			reg = <0x50>;
+			pagesize = <1>;
+		};
+	};
+
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		rtc@32 {
+			compatible = "wave,sd3068";
+			reg = <0x32>;
+		};
+	};
+
+	mio6: uart@28020000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28020000 0x0 0x1000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio10: uart@28028000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28028000 0x0 0x1000>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio14: uart@28030000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb1 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "disabled";
+};
+
+&macb2 {
+	phy-mode = "rgmii";
+	use-mii;
+	status = "disabled";
+};
+
+&macb3 {
+	phy-mode = "rgmii";
+	use-mii;
+	status = "disabled";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "okay";
+
+	flash: w25q128@0 {
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		spi-max-frequency = <12000000>;
+		reg = <0x00>;
+	};
+};
+
+&mmc0 {
+	bus-width = <4>;
+	max-frequency = <25000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&mmc1 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&hda0 {
+	status = "okay";
+};
+
+&dc0 {
+	status = "okay";
+	pipe_mask = [03];
+	edp_mask = [00];
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&pwm1 {
+	phytium,db = <0 0 0 1000 1000 0>;
+	status = "okay";
+};
+
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts
new file mode 100644
index 00000000000000..33c6b98279a820
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-demo-board.dts
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2204 demo board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2204.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+
+/{
+	model = "Pe2204 DEMO DDR4";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,pin-switches = "mic-in";
+		simple-audio-card,widgets = "Microphone","mic-in";
+		simple-audio-card,routing = "MIC2","mic-in";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec{
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		/* localized demo board use this rtc device */
+		rtc@32 {
+			compatible = "wave,sd3068";
+			reg = <0x32>;
+		};
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 5  GPIO_ACTIVE_LOW>;
+			sel-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+			#sound-dai-cells = <0x0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&watchdog1 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_2 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+/*
+ * In demo board, M.2 interface may insert two types of disks: PCIE (nvme protocol) or SATA (ahci protocol),
+ * so here enable 'sata0' node by default to correspond to the sata drive case. Pin multiplexing exists
+ * in PCIE2 and SATA0, when used as a boot disk, the BIOS can automatically recognize these two conditions.
+ */
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <0x00000008>;
+	max-frequency = <100000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <0x00000004>;
+	max-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	dai-name = "phytium-i2s-lsd";
+	status = "okay";
+};
+
+&dc0 {
+	pipe_mask = /bits/ 8 <0x3>;
+	edp_mask = /bits/ 8 <0x0>;
+	status = "okay";
+};
+
+&i2s_dp0 {
+	status = "okay";
+};
+
+&i2s_dp1 {
+	status = "okay";
+};
+
+&pmdk_dp {
+	num-dp = <2>;
+	dp-mask = /bits/ 8 <0x3>;
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts
new file mode 100755
index 00000000000000..02a97b686d20d7
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-edu-board.dts
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2204 edu board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Hongmin Qi <qihongmin@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2204.dtsi"
+
+/{
+	model = "Pe2204 edu Board";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		status = "okay";
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio8: i2c@28024000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28024000 0x0 0x1000>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		status = "okay";
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		status = "okay";
+
+		codec0:es8336@10 {
+			det-gpios = <&gpio2 5 0>;
+			sel-gpios = <&gpio2 6 0>;
+			#sound-dai-cells = <0x0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+			mic-src = [30];
+	   };
+	};
+
+	mio0: uart@28014000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28014000 0x0 0x1000>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio1: uart@28016000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28016000 0x0 0x1000>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio11: uart@2802A000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x2802a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	//status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "host";
+	//status = "okay";
+};
+
+&usb2_2 {
+	dr_mode = "host";
+	//status = "okay";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	//status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	//status = "okay";
+};
+
+&macb1 {
+	phy-mode = "sgmii";
+	use-mii;
+	//status = "okay";
+};
+
+&macb2 {
+	phy-mode = "sgmii";
+	use-mii;
+	//status = "okay";
+};
+
+&macb3 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "okay";
+
+	flash: w25q128@0 {
+		compatible = "jedec,spi-nor";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		spi-max-frequency = <12000000>;
+		reg = <0x00>;
+		status = "okay";
+	};
+};
+
+&mmc0 {
+	bus-width = <0x8>;
+	max-frequency = <50000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <0x4>;
+	max-frequency = <25000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&sata0 {
+	//status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&dc0 {
+	status = "okay";
+	pipe_mask = [01];
+	edp_mask = [00];
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	dai-name = "phytium-i2s-lsd";
+	status = "okay";
+};
+
+&i2s_dp0 {
+	status = "okay";
+};
+
+&pmdk_dp {
+	num-dp = <1>;
+	dp-mask = /bits/ 8 <0x1>;
+	status = "okay";
+};
+
+&pwm0 {
+	phytium,db = <0 0 0 0 0 0>;
+	status = "okay";
+};
+
+&pwm1 {
+	phytium,db = <0 0 0 0 0 0>;
+	status = "okay";
+};
+
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&keypad {
+	keypad,num-rows = <4>;
+	keypad,num-columns = <4>;
+	linux,keymap = <0x00000011
+					0x00010012
+					0x00020013
+					0x00030014
+					0x01000021 /*KEY_21*/
+					0x01010022 /*KEY_22*/
+					0x01020023 /*KEY_23*/
+					0x01030024 /*KEY_24*/
+					0x02000031 /*KEY_31*/
+					0x02010032 /*KEY_32*/
+					0x02020033 /*KEY_33*/
+					0x02030034 /*KEY_34*/
+					0x03000041 /*KEY_41*/
+					0x03010042 /*KEY_42*/
+					0x03020043 /*KEY_43*/
+					0x03030044 /*KEY_44*/>;
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts
new file mode 100755
index 00000000000000..0c58438e385e34
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-hanwei-board.dts
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2204 hanwei board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Hongmin Qi <qihongmin@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2204.dtsi"
+
+/{
+	model = "Pe2204 hanwei Board";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+};
+
+&soc {
+	mio3: uart@2801a000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x2801a000 0x0 0x1000>;
+		interrupts = <0x0 0x5f 0x4>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio8: uart@28024000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28024000 0x0 0x1000>;
+		interrupts = <0x0 0x64 0x4>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio10: uart@28028000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28028000 0x0 0x1000>;
+		interrupts = <0x0 0x66 0x4>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio14: uart@28030000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <0x0 0x6a 0x4>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <0x0 0x6b 0x4>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb1 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb2 {
+	phy-mode = "rgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb3 {
+	phy-mode = "rgmii";
+	use-mii;
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&mmc0 {
+	bus-width = <8>;
+	max-frequency = <25000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "disabled";
+};
+
+&mmc1 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts
new file mode 100644
index 00000000000000..81218adbeddb2d
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-miniitx-board.dts
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium miniITX-Pe2204 development board.
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Shaojun Yang <yangshaojun@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+/memreserve/ 0xf4000000 0x4000000;
+
+#include "pe2204.dtsi"
+
+/{
+	model = "miniITX-Pe2204 Board";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+	aliases {
+		serial4 = &mio0;
+		serial5 = &mio1;
+		serial6 = &mio8;
+		serial7 = &mio11;
+		serial8 = &mio15;
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec{
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 5 0>;
+			sel-gpios = <&gpio2 6 0>;
+			#sound-dai-cells = <0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+			mic-src = [20];
+		};
+	};
+
+
+	mio0: uart@28014000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28014000 0x0 0x1000>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio1: uart@28016000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28016000 0x0 0x1000>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio8: uart@28024000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28024000 0x0 0x1000>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio11: uart@2802A000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x2802A000 0x0 0x1000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&watchdog1 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "peripheral";
+	status = "disabled";
+};
+
+&usb2_2 {
+	dr_mode = "peripheral";
+	status = "disabled";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb2 {
+	phy-mode = "rgmii";
+	use-mii;
+	status = "okay";
+};
+
+&dc0 {
+		reg = <0x0 0x32000000 0x0 0x8000>,
+			  <0x0 0xf4000000 0x0 0x4000000>; // (optional)
+	pipe_mask = [03];
+	edp_mask = [00];
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	dai-name = "phytium-i2s-lsd";
+	status = "okay";
+};
+
+&i2s_dp0 {
+	dai-name = "phytium-i2s-dp0";
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "disabled";
+
+	flash: w25q128@0 {
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		spi-max-frequency = <12000000>;
+		reg = <0x00>;
+		status = "disabled";
+	};
+};
+
+&spi1 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&mmc0 {
+	bus-width = <0x00000004>;
+	max-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-mmc;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <0x00000008>;
+	max-frequency = <50000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "disabled";
+};
+
+&pwm0 {
+	phytium,db = <0 0 0 1000 1000 0>;
+	status = "okay";
+};
+
+&pwm1 {
+	phytium,db = <0 0 0 1000 1000 0>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
+
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts
new file mode 100755
index 00000000000000..3924c5bcee70e5
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000q-vpx-board.dts
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2204 vpx board.
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * Tianyu Liu <liutianyu1250@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2204.dtsi"
+
+/{
+	model = "Pe2204 vpx board";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+	aliases {
+		serial4 = &mio3;
+		serial5 = &mio8;
+		serial6 = &mio10;
+		serial7 = &mio11;
+		serial8 = &mio15;
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec{
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 5 0>;
+			sel-gpios = <&gpio2 6 0>;
+			#sound-dai-cells = <0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+			mic-src = [30];
+		};
+	};
+
+	mio3: uart@2801A000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x2801A000 0x0 0x1000>;
+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio8: uart@28024000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28024000 0x0 0x1000>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio10: uart@28028000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28028000 0x0 0x1000>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio11: uart@2802A000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x2802A000 0x0 0x1000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio13: uart@2802E000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x2802E000 0x0 0x1000>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "host";
+	status = "disabled";
+};
+
+&usb2_2 {
+	dr_mode = "host";
+	status = "disabled";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb2 {
+	phy-mode = "rgmii";
+	use-mii;
+	force-phy-mode;
+	status = "okay";
+};
+
+&macb3 {
+	phy-mode = "rgmii";
+	use-mii;
+	status = "okay";
+};
+
+&dc0 {
+	pipe_mask = [03];
+	edp_mask = [00];
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	dai-name = "phytium-i2s-lsd";
+	status = "okay";
+};
+
+&i2s_dp0 {
+	status = "okay";
+};
+
+&i2s_dp1 {
+	status = "okay";
+};
+
+&pmdk_dp {
+	num-dp = <2>;
+	dp-mask = /bits/ 8 <0x3>;
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "disabled";
+
+	flash: w25q128@0 {
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		spi-max-frequency = <12000000>;
+		reg = <0x00>;
+		status = "disabled";
+	};
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "disabled";
+};
+
+&mmc0 {
+	bus-width = <0x00000008>;
+	max-frequency = <25000000>;
+	cap-mmc-hw-reset;
+	cap-mmc-highspeed;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
+
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts
new file mode 100644
index 00000000000000..047d1c5d5bacc2
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/e2000s-demo-board.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2201 demo board
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2201.dtsi"
+
+/{
+	model = "Pe2201 DEMO DDR4";
+	compatible = "phytium,pe2201";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_2 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi2 {
+	global-cs = <1>;
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&mmc0 {
+	status = "okay";
+};
+
+&mmc1 {
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2201.dtsi b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2201.dtsi
new file mode 100644
index 00000000000000..b7576e684c2800
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2201.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Phytium Pe2201 SoC
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ */
+
+#include "pe220x.dtsi"
+
+/ {
+	compatible = "phytium,pe2201";
+
+	aliases {
+		ethernet0 = &macb0;
+		ethernet1 = &macb1;
+	};
+};
+
+&cpu {
+	cpu0: cpu@0 {
+		device_type = "cpu";
+		compatible = "phytium,ftc310", "arm,armv8";
+		reg = <0x0 0x200>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 2>;
+	};
+};
+
+&soc {
+	i2c0: i2c@28011000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28011000 0x0 0x1000>;
+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "smbus_alert";
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@28012000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28012000 0x0 0x1000>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "smbus_alert";
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@28013000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28013000 0x0 0x1000>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	onewire0: onewire@2803f000 {
+		compatible = "phytium,w1";
+		reg = <0x0 0x2803f000 0x0 0x1000>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	pwm2: pwm@2804c000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x2804c000 0x0 0x1000>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm3: pwm@2804d000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x2804d000 0x0 0x1000>;
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm4: pwm@2804e000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x2804e000 0x0 0x1000>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm5: pwm@2804f000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x2804f000 0x0 0x1000>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm6: pwm@28050000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x28050000 0x0 0x1000>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm7: pwm@28051000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x28051000 0x0 0x1000>;
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	adc0: adc@2807b000 {
+		compatible = "phytium,adc";
+		reg = <0x0 0x2807b000 0x0 0x1000>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@0 {
+			reg = <0>;
+		};
+		channel@1 {
+			reg = <1>;
+		};
+		channel@2 {
+			reg = <2>;
+		};
+		channel@3 {
+			reg = <3>;
+		};
+		channel@4 {
+			reg = <4>;
+		};
+		channel@5 {
+			reg = <5>;
+		};
+		channel@6 {
+			reg = <6>;
+		};
+		channel@7 {
+			reg = <7>;
+		};
+	};
+
+	adc1: adc@2807c000 {
+		compatible = "phytium,adc";
+		reg = <0x0 0x2807c000 0x0 0x1000>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@0 {
+			reg = <0>;
+		};
+		channel@1 {
+			reg = <1>;
+		};
+		channel@2 {
+			reg = <2>;
+		};
+		channel@3 {
+			reg = <3>;
+		};
+		channel@4 {
+			reg = <4>;
+		};
+		channel@5 {
+			reg = <5>;
+		};
+		channel@6 {
+			reg = <6>;
+		};
+		channel@7 {
+			reg = <7>;
+		};
+	};
+
+	sgpio: sgpio@2807d000 {
+		compatible = "phytium,sgpio";
+		reg = <0x0 0x2807d000 0x0 0x1000>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		ngpios = <96>;
+		bus-frequency = <48000>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	macb0: ethernet@32010000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x32010000 0x0 0x2000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	macb1: ethernet@32012000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x32012000 0x0 0x2000>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	jpeg0: jpeg@32b32000 {
+		compatible = "phytium,jpeg";
+		reg = <0x0 0x32b32000 0 0x1000>,
+			  <0x0 0x28072000 0 0x30>,
+			  <0x0 0x28073000 0 0x30>;
+		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		phytium,ocm-buf-addr = <0x30c40000 0x30c60000>;
+		status = "disabled";
+	};
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2202.dtsi b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2202.dtsi
new file mode 100644
index 00000000000000..9f19b71be3c290
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2202.dtsi
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Phytium Pe2202 SoC
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ */
+
+#include "pe220x.dtsi"
+
+/ {
+	compatible = "phytium,pe2202";
+
+	aliases {
+		ethernet0 = &macb0;
+		ethernet1 = &macb1;
+		ethernet2 = &macb2;
+		ethernet3 = &macb3;
+	};
+};
+
+&cpu {
+	cpu-map {
+		cluster0 {
+			core0 {
+				cpu = <&cpu_l0>;
+			};
+
+			core1 {
+				cpu = <&cpu_l1>;
+			};
+		};
+	};
+
+	cpu_l0: cpu@0 {
+		device_type = "cpu";
+		compatible = "phytium,ftc310", "arm,armv8";
+		reg = <0x0 0x200>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 2>;
+	};
+
+	cpu_l1: cpu@1 {
+		device_type = "cpu";
+		compatible = "phytium,ftc310", "arm,armv8";
+		reg = <0x0 0x201>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 2>;
+	};
+};
+
+&soc {
+	hda0: hda@28006000 {
+		compatible = "phytium,hda";
+		reg = <0x0 0x28006000 0x0 0x1000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	i2s0: i2s@28009000 {
+		compatible = "phytium,i2s";
+		reg = <0x0 0x28009000 0x0 0x1000>,
+			  <0x0 0x28005000 0x0 0x1000>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_600mhz>;
+		clock-names = "i2s_clk";
+		status = "disabled";
+	};
+
+	can0: can@2800a000 {
+		compatible = "phytium,canfd";
+		reg = <0x0 0x2800a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_200mhz>;
+		clock-names = "can_clk";
+		tx-fifo-depth = <64>;
+		rx-fifo-depth = <64>;
+		status = "disabled";
+	};
+
+	can1: can@2800b000 {
+		compatible = "phytium,canfd";
+		reg = <0x0 0x2800b000 0x0 0x1000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_200mhz>;
+		clock-names = "can_clk";
+		tx-fifo-depth = <64>;
+		rx-fifo-depth = <64>;
+		status = "disabled";
+	};
+
+	keypad: keypad@2807a000 {
+		compatible = "phytium,keypad";
+		reg = <0x0 0x2807a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	usb3_0: usb3@31a08000 {
+		compatible = "phytium,pe220x-xhci";
+		reg = <0x0 0x31a08000 0x0 0x18000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	usb3_1: usb3@31a28000 {
+		compatible = "phytium,pe220x-xhci";
+		reg = <0x0 0x31a28000 0x0 0x18000>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	sata0: sata@31a40000 {
+		compatible = "generic-ahci";
+		reg = <0x0 0x31a40000 0x0 0x1000>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	sata1: sata@32014000 {
+		compatible = "generic-ahci";
+		reg = <0x0 0x32014000 0x0 0x1000>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	macb0: ethernet@3200c000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x3200c000 0x0 0x2000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	macb1: ethernet@3200e000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x3200e000 0x0 0x2000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	macb2: ethernet@32010000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x32010000 0x0 0x2000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		use-mii;
+		status = "disabled";
+	};
+
+	macb3: ethernet@32012000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x32012000 0x0 0x2000>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		use-mii;
+		status = "disabled";
+	};
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2204.dtsi b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2204.dtsi
new file mode 100644
index 00000000000000..59dc498cd58b2e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe2204.dtsi
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Phytium Pe2204 SoC
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ */
+
+#include "pe220x.dtsi"
+
+/ {
+	compatible = "phytium,pe2204";
+
+	aliases {
+		ethernet0 = &macb0;
+		ethernet1 = &macb1;
+		ethernet2 = &macb2;
+		ethernet3 = &macb3;
+	};
+};
+
+&cpu {
+	cpu-map {
+		cluster0 {
+			core0 {
+				cpu = <&cpu_b0>;
+			};
+		};
+
+		cluster1 {
+			core0 {
+				cpu = <&cpu_b1>;
+			};
+		};
+
+		cluster2 {
+			core0 {
+				cpu = <&cpu_l0>;
+			};
+
+			core1 {
+				cpu = <&cpu_l1>;
+			};
+		};
+	};
+
+	cpu_l0: cpu@0 {
+		device_type = "cpu";
+		compatible = "phytium,ftc310", "arm,armv8";
+		reg = <0x0 0x200>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 2>;
+		capacity-dmips-mhz = <2850>;
+	};
+
+	cpu_l1: cpu@1 {
+		device_type = "cpu";
+		compatible = "phytium,ftc310", "arm,armv8";
+		reg = <0x0 0x201>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 2>;
+		capacity-dmips-mhz = <2850>;
+	};
+
+	cpu_b0: cpu@100 {
+		device_type = "cpu";
+		compatible = "phytium,ftc664", "arm,armv8";
+		reg = <0x0 0x0>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 0>;
+		capacity-dmips-mhz = <5660>;
+	};
+
+	cpu_b1: cpu@101 {
+		device_type = "cpu";
+		compatible = "phytium,ftc664", "arm,armv8";
+		reg = <0x0 0x100>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 1>;
+		capacity-dmips-mhz = <5660>;
+	};
+};
+
+&soc {
+	hda0: hda@28006000 {
+		compatible = "phytium,hda";
+		reg = <0x0 0x28006000 0x0 0x1000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	i2s0: i2s@28009000 {
+		compatible = "phytium,i2s";
+		reg = <0x0 0x28009000 0x0 0x1000>,
+			  <0x0 0x28005000 0x0 0x1000>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_600mhz>;
+		clock-names = "i2s_clk";
+		status = "disabled";
+	};
+
+	can0: can@2800a000 {
+		compatible = "phytium,canfd";
+		reg = <0x0 0x2800a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_200mhz>;
+		clock-names = "can_clk";
+		tx-fifo-depth = <64>;
+		rx-fifo-depth = <64>;
+		status = "disabled";
+	};
+
+	can1: can@2800b000 {
+		compatible = "phytium,canfd";
+		reg = <0x0 0x2800b000 0x0 0x1000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_200mhz>;
+		clock-names = "can_clk";
+		tx-fifo-depth = <64>;
+		rx-fifo-depth = <64>;
+		status = "disabled";
+	};
+
+	keypad: keypad@2807a000 {
+		compatible = "phytium,keypad";
+		reg = <0x0 0x2807a000 0x0 0x1000>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	usb3_0: usb3@31a08000 {
+		compatible = "phytium,pe220x-xhci";
+		reg = <0x0 0x31a08000 0x0 0x18000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	usb3_1: usb3@31a28000 {
+		compatible = "phytium,pe220x-xhci";
+		reg = <0x0 0x31a28000 0x0 0x18000>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	sata0: sata@31a40000 {
+		compatible = "generic-ahci";
+		reg = <0x0 0x31a40000 0x0 0x1000>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	sata1: sata@32014000 {
+		compatible = "generic-ahci";
+		reg = <0x0 0x32014000 0x0 0x1000>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	macb0: ethernet@3200c000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x3200c000 0x0 0x2000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		support-tsn;
+		status = "disabled";
+	};
+
+	macb1: ethernet@3200e000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x3200e000 0x0 0x2000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	macb2: ethernet@32010000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x32010000 0x0 0x2000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	macb3: ethernet@32012000 {
+		compatible = "cdns,phytium-gem-1.0";
+		reg = <0x0 0x32012000 0x0 0x2000>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe220x.dtsi b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe220x.dtsi
new file mode 100644
index 00000000000000..a03fe32361e705
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/pe220x.dtsi
@@ -0,0 +1,1001 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Phytium Pe220x SoC
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "phytium,pe220x";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	psci {
+		compatible   = "arm,psci-1.0";
+		method       = "smc";
+		cpu_suspend  = <0xc4000001>;
+		cpu_off      = <0x84000002>;
+		cpu_on       = <0xc4000003>;
+		sys_poweroff = <0x84000008>;
+		sys_reset    = <0x84000009>;
+	};
+
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi";
+			mboxes = <&mbox 0>;
+			mbox-names = "tx";
+			shmem = <&cpu_scp_hpri>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_dvfs: protocol@13 {
+				reg = <0x13>;
+				#clock-cells = <1>;
+			};
+
+			scmi_sensors0: protocol@15 {
+				reg = <0x15>;
+				#thermal-sensor-cells = <1>;
+			};
+		};
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	thermal-zones {
+		sensor0 {
+			polling-delay-passive = <100>;
+			polling-delay = <1000>;
+			thermal-sensors = <&scmi_sensors0 0>;
+		};
+
+		sensor1 {
+			polling-delay-passive = <100>;
+			polling-delay = <1000>;
+			thermal-sensors = <&scmi_sensors0 1>;
+		};
+	};
+
+	cpu: cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+	};
+
+	gic: interrupt-controller@30800000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+		reg = <0x0 0x30800000 0 0x20000>,	/* GICD */
+			  <0x0 0x30880000 0 0x80000>,	/* GICR */
+			  <0x0 0x30840000 0 0x10000>,	/* GICC */
+			  <0x0 0x30850000 0 0x10000>,	/* GICH */
+			  <0x0 0x30860000 0 0x10000>;	/* GICV */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+		its: gic-its@30820000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x30820000 0x0 0x20000>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+		clock-frequency = <50000000>;
+	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sysclk_48mhz: clk48mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+		};
+
+		sysclk_50mhz: clk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+
+		sysclk_100mhz: clk100mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+		};
+
+		sysclk_200mhz: clk200mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+
+		sysclk_250mhz: clk250mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <250000000>;
+		};
+
+		sysclk_300mhz: clk300mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <300000000>;
+		};
+
+		sysclk_600mhz: clk600mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <600000000>;
+		};
+
+		sysclk_1200mhz: clk1200mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1200000000>;
+		};
+	};
+
+	smmu: iommu@30000000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x0 0x30000000 0x0 0x800000>;
+		interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+				 <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+				 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+				 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+		dma-coherent;
+		#iommu-cells = <1>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-coherent;
+		ranges;
+
+		mmc0: mmc@28000000 {
+			compatible = "phytium,mci";
+			reg = <0x0 0x28000000 0x0 0x1000>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_1200mhz>;
+			clock-names = "phytium_mci_clk";
+			status = "disabled";
+		};
+
+		mmc1: mmc@28001000 {
+			compatible = "phytium,mci";
+			reg = <0x0 0x28001000 0x0 0x1000>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_1200mhz>;
+			clock-names = "phytium_mci_clk";
+			status = "disabled";
+		};
+
+		nand0: nand@28002000 {
+			compatible = "phytium,nfc";
+			reg = <0x0 0x28002000 0x0 0x1000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		ddma0: ddma@28003000 {
+			compatible = "phytium,ddma";
+			reg = <0x0 0x28003000 0x0 0x1000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <2>;
+			dma-channels = <8>;
+		};
+
+		ddma1: ddma@28004000 {
+			compatible = "phytium,ddma";
+			reg = <0x0 0x28004000 0x0 0x1000>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <2>;
+			dma-channels = <8>;
+		};
+
+		qspi0: spi@28008000 {
+			compatible = "phytium,qspi-nor";
+			reg = <0x0 0x28008000 0x0	  0x1000>,
+				  <0x0		  0x0 0x0 0x0fffffff>;
+			reg-names = "qspi", "qspi_mm";
+			clocks = <&sysclk_300mhz>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0x00>;
+				spi-rx-bus-width = <1>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		uart0: uart@2800c000 {
+			compatible = "arm,pl011","arm,primecell";
+			reg = <0x0 0x2800c000 0x0 0x1000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_100mhz &sysclk_100mhz>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: uart@2800d000 {
+			compatible = "arm,pl011","arm,primecell";
+			reg = <0x0 0x2800d000 0x0 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_100mhz &sysclk_100mhz>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: uart@2800e000 {
+			compatible = "arm,pl011","arm,primecell";
+			reg = <0x0 0x2800e000 0x0 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_100mhz &sysclk_100mhz>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: uart@2800f000 {
+			compatible = "arm,pl011","arm,primecell";
+			reg = <0x0 0x2800f000 0x0 0x1000>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_100mhz &sysclk_100mhz>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		lpc: lpc@28010000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x0 0x28010000 0x0 0x1000>;
+			reg-io-width = <4>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x28010000 0x1000>;
+
+			kcs0: kcs@24 {
+				compatible = "phytium,kcs-bmc";
+				reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			kcs1: kcs@28 {
+				compatible = "phytium,kcs-bmc";
+				reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			kcs2: kcs@2c {
+				compatible = "phytium,kcs-bmc";
+				reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			kcs3: kcs@8c {
+				compatible = "phytium,kcs-bmc";
+				reg = <0x8c 0x1>, <0x90 0x1>, <0x94 0x1>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			bt: bt@48 {
+				compatible = "phytium,bt-bmc";
+				reg = <0x48 0x20>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		/* MIO */
+
+		gpio0: gpio@28034000 {
+			compatible = "phytium,gpio";
+			reg = <0x0 0x28034000 0x0 0x1000>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			porta {
+				compatible = "phytium,gpio-port";
+				reg = <0>;
+				ngpios = <16>;
+			};
+		};
+
+		gpio1: gpio@28035000 {
+			compatible = "phytium,gpio";
+			reg = <0x0 0x28035000 0x0 0x1000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			porta {
+				compatible = "phytium,gpio-port";
+				reg = <0>;
+				ngpios = <16>;
+			};
+		};
+
+		gpio2: gpio@28036000 {
+			compatible = "phytium,gpio";
+			reg = <0x0 0x28036000 0x0 0x1000>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			porta {
+				compatible = "phytium,gpio-port";
+				reg = <0>;
+				ngpios = <16>;
+			};
+		};
+
+		gpio3: gpio@28037000 {
+			compatible = "phytium,gpio";
+			reg = <0x0 0x28037000 0x0 0x1000>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			porta {
+				compatible = "phytium,gpio-port";
+				reg = <0>;
+				ngpios = <16>;
+			};
+		};
+
+		gpio4: gpio@28038000 {
+			compatible = "phytium,gpio";
+			reg = <0x0 0x28038000 0x0 0x1000>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			porta {
+				compatible = "phytium,gpio-port";
+				reg = <0>;
+				ngpios = <16>;
+			};
+		};
+
+		gpio5: gpio@28039000 {
+			compatible = "phytium,gpio";
+			reg = <0x0 0x28039000 0x0 0x1000>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			porta {
+				compatible = "phytium,gpio-port";
+				reg = <0>;
+				ngpios = <16>;
+			};
+		};
+
+		spi0: spi@2803a000 {
+			compatible = "phytium,spi";
+			reg = <0x0 0x2803a000 0x0 0x1000>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz>;
+			num-cs = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@2803b000 {
+			compatible = "phytium,spi";
+			reg = <0x0 0x2803b000 0x0 0x1000>;
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz>;
+			num-cs = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@2803c000 {
+			compatible = "phytium,spi";
+			reg = <0x0 0x2803c000 0x0 0x1000>;
+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz>;
+			num-cs = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi3: spi@2803d000 {
+			compatible = "phytium,spi";
+			reg = <0x0 0x2803d000 0x0 0x1000>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz>;
+			num-cs = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		watchdog0: watchdog@28040000 {
+			compatible = "arm,sbsa-gwdt";
+			reg = <0x0 0x28041000 0x0 0x1000>,
+				  <0x0 0x28040000 0x0 0x1000>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			timeout-sec = <30>;
+			status = "disabled";
+		};
+
+		watchdog1: watchdog@28042000 {
+			compatible = "arm,sbsa-gwdt";
+			reg = <0x0 0x28043000 0x0 0x1000>,
+				  <0x0 0x28042000 0x0 0x1000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			timeout-sec = <30>;
+			status = "disabled";
+		};
+
+		pwm0: pwm@2804a000 {
+			compatible = "phytium,pwm";
+			reg = <0x0 0x2804a000 0x0 0x1000>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz>;
+			status = "disabled";
+		};
+
+		pwm1: pwm@2804b000 {
+			compatible = "phytium,pwm";
+			reg = <0x0 0x2804b000 0x0 0x1000>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz>;
+			status = "disabled";
+		};
+
+		tacho0: tacho@28054000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28054000 0x0 0x1000>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho1: tacho@28055000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28055000 0x0 0x1000>;
+			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho2: tacho@28056000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28056000 0x0 0x1000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho3: tacho@28057000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28057000 0x0 0x1000>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho4: tacho@28058000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28058000 0x0 0x1000>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho5: tacho@28059000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28059000 0x0 0x1000>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho6: tacho@2805a000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2805a000 0x0 0x1000>;
+			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho7: tacho@2805b000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2805b000 0x0 0x1000>;
+			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho8: tacho@2805c000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2805c000 0x0 0x1000>;
+			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho9: tacho@2805d000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2805d000 0x0 0x1000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho10: tacho@2805e000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2805e000 0x0 0x1000>;
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho11: tacho@2805f000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2805f000 0x0 0x1000>;
+			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho12: tacho@28060000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28060000 0x0 0x1000>;
+			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho13: tacho@28061000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28061000 0x0 0x1000>;
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho14: tacho@28062000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28062000 0x0 0x1000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho15: tacho@28063000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28063000 0x0 0x1000>;
+			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho16: tacho@28064000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28064000 0x0 0x1000>;
+			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho17: tacho@28065000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28065000 0x0 0x1000>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho18: tacho@28066000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28066000 0x0 0x1000>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho19: tacho@28067000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28067000 0x0 0x1000>;
+			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho20: tacho@28068000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28068000 0x0 0x1000>;
+			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho21: tacho@28069000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28069000 0x0 0x1000>;
+			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho22: tacho@2806a000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2806a000 0x0 0x1000>;
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho23: tacho@2806b000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2806b000 0x0 0x1000>;
+			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho24: tacho@2806c000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2806c000 0x0 0x1000>;
+			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho25: tacho@2806d000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2806d000 0x0 0x1000>;
+			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho26: tacho@2806e000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2806e000 0x0 0x1000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho27: tacho@2806f000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x2806f000 0x0 0x1000>;
+			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho28: tacho@28070000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28070000 0x0 0x1000>;
+			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho29: tacho@28071000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28071000 0x0 0x1000>;
+			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho30: tacho@28072000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28072000 0x0 0x1000>;
+			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho31: tacho@28073000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28073000 0x0 0x1000>;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho32: tacho@28074000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28074000 0x0 0x1000>;
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho33: tacho@28075000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28075000 0x0 0x1000>;
+			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho34: tacho@28076000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28076000 0x0 0x1000>;
+			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho35: tacho@28077000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28077000 0x0 0x1000>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho36: tacho@28078000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28078000 0x0 0x1000>;
+			interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		tacho37: tacho@28079000 {
+			compatible = "phytium,tacho";
+			reg = <0x0 0x28079000 0x0 0x1000>;
+			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_50mhz >;
+			status = "disabled";
+		};
+
+		usb2_0: usb2@31800000 { /* usb_vhub0 USB2_P2 only otg mode */
+			compatible = "phytium,usb2";
+			reg = <0x0 0x31800000 0x0 0x80000>,
+				  <0x0 0x31990000 0x0 0x10000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		usb2_1: usb2@31880000 { /* usb_vhub1 USB2_P2 */
+			compatible = "phytium,usb2";
+			reg = <0x0 0x31880000 0x0 0x80000>,
+				  <0x0 0x319a0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		usb2_2: usb2@31900000 { /* usb_vhub2 USB2_P2 */
+			compatible = "phytium,usb2";
+			reg = <0x0 0x31900000 0x0 0x80000>,
+				  <0x0 0x319b0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		usb2_3: usb2@32800000 { /* USB2_0 controller registers USB2_P3 */
+			compatible = "phytium,usb2";
+			reg = <0x0 0x32800000 0x0 0x40000>,
+				  <0x0 0x32880000 0x0 0x40000>; /* USB2_0 UIB registers */
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		usb2_4: usb2@32840000 { /* USB2_1 controller registers USB2_P4 */
+			compatible = "phytium,usb2";
+			reg = <0x0 0x32840000 0x0 0x40000>,
+				  <0x0 0x328c0000 0x0 0x40000>; /* USB2_1 UIB registers */
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		dc0: dc@32000000 {
+			compatible = "phytium,dc";
+			reg = <0x0 0x32000000 0x0 0x8000>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2s_dp0: i2s_dp0@32009000 {
+			compatible = "phytium,i2s";
+			reg = <0x0 0x32009000 0x0 0x1000>,
+				  <0x0 0x32008000 0x0 0x1000>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_600mhz>;
+			clock-names = "i2s_clk";
+			dai-name = "phytium-i2s-dp0";
+			status = "disabled";
+		};
+
+		i2s_dp1: i2s_dp1@3200B000 {
+			compatible = "phytium,i2s";
+			reg = <0x0 0x3200B000 0x0 0x1000>,
+				  <0x0 0x3200A000 0x0 0x1000>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk_600mhz>;
+			clock-names = "i2s_clk";
+			dai-name = "phytium-i2s-dp1";
+			status = "disabled";
+		};
+
+		pmdk_dp: pmdk_dp {
+			compatible = "phytium,pmdk-dp";
+			status = "disabled";
+		};
+
+		mbox: mailbox@32a00000 {
+			compatible = "phytium,mbox";
+			reg = <0x0 0x32a00000 0x0 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <1>;
+		};
+
+		rng0: rng@32a36000 {
+			compatible = "phytium,rng";
+			reg = <0x0 0x32a36000 0x0 0x1000>;
+			status = "disabled";
+		};
+
+		sram: sram@32a10000 {
+			compatible = "phytium,pe220x-sram-ns", "mmio-sram";
+			reg = <0x0 0x32a10000 0x0 0x2000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x32a10000 0x2000>;
+
+			cpu_scp_lpri: scp-shmem@0 {
+				compatible = "arm,scmi-shmem";
+				reg = <0x1000 0x400>;
+			};
+
+			cpu_scp_hpri: scp-shmem@1 {
+				compatible = "arm,scmi-shmem";
+				reg = <0x1400 0x400>;
+			};
+		};
+
+		hwspinlock: spinlock@32b36000 {
+			compatible = "phytium,hwspinlock";
+			reg = <0x0 0x32b36000 0x0 0x1000>;
+			#hwlock-cells = <1>;
+			nr-locks = <32>;
+			status = "disabled";
+		};
+
+		pcie: pcie@40000000 {
+			compatible = "pci-host-ecam-generic";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			reg = <0x0 0x40000000 0x0 0x10000000>;
+			msi-parent = <&its>;
+			bus-range = <0x0 0xff>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			ranges = <0x01000000 0x00 0x00000000 0x0  0x50000000  0x0  0x00f00000>,
+				 <0x02000000 0x00 0x58000000 0x0  0x58000000  0x0  0x28000000>,
+				 <0x03000000 0x10 0x00000000 0x10 0x00000000 0x10  0x00000000>;
+			iommu-map = <0x0 &smmu 0x0 0x10000>;
+			status = "disabled";
+		};
+
+		edac: edac@32b28000 {
+			compatible = "phytium,pe220x-edac";
+			reg = <0x0 0x32b28000 0x0 0x1000>,
+				<0x0 0x31400000 0x0 0x1000>,
+				<0x0 0x31401000 0x0 0x1000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts
new file mode 100644
index 00000000000000..d935c7d9d2f702
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/boot/dts/phytium/phytiumpi_firefly.dts
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pi development board.
+ *
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ *
+ * Shaojun Yang <yangshaojun@phytium.com.cn>
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2204.dtsi"
+
+/{
+	model = "Phytium Pi Board";
+	compatible = "phytium,pe2204";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+	aliases {
+		serial4 = &mio0;
+		serial5 = &mio11;
+		serial6 = &mio15;
+	};
+
+	memory@00{
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		sysled {
+			label = "sysled";
+			gpios = <&gpio1 5 0>;
+			linux,default-trigger = "none";
+		};
+	};
+
+	sound_card: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "phytium,pe220x-i2s-audio";
+		simple-audio-card,pin-switches = "mic-in";
+		simple-audio-card,widgets = "Microphone","mic-in";
+		simple-audio-card,routing = "MIC2","mic-in";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec{
+			sound-dai = <&codec0>;
+		};
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+
+	mio14: i2c@28030000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28030000 0x0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		codec0: es8336@10 {
+			det-gpios = <&gpio2 11 0>;
+			sel-gpios = <&gpio2 7 0>;
+			#sound-dai-cells = <0>;
+			compatible = "everest,es8336";
+			reg = <0x10>;
+		};
+	};
+
+
+	mio0: uart@28014000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28014000 0x0 0x1000>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio1: i2c@28016000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28016000 0x0 0x1000>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+
+	mio8: i2c@28024000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28024000 0x0 0x1000>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+
+	mio11: uart@2802A000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x2802A000 0x0 0x1000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+
+	mio15: uart@28032000 {
+		compatible = "arm,pl011","arm,primecell";
+		reg = <0x0 0x28032000 0x0 0x1000>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz &sysclk_50mhz>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "okay";
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&watchdog1 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "peripheral";
+	status = "disabled";
+};
+
+&usb2_2 {
+	dr_mode = "peripheral";
+	status = "disabled";
+};
+
+&usb2_3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2_4 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&macb1 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&dc0 {
+	pipe_mask = /bits/ 8 <0x1>;
+	edp_mask = /bits/ 8 <0x0>;
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <0>;
+	dai-name = "phytium-i2s-lsd";
+	status = "okay";
+};
+
+&i2s_dp0 {
+	dai-name = "phytium-i2s-dp0";
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+	};
+};
+
+&spi0 {
+	global-cs = <1>;
+	status = "okay";
+
+	spidev0: spidev@0 {
+		compatible = "spidev";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		status = "disabled";
+	};
+};
+
+&mmc0 {
+	bus-width = <0x00000004>;
+	max-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-mmc;
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <0x00000004>;
+	max-frequency = <25000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	no-mmc;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&pwm0 {
+	phytium,db = <0 0 100 1000 1000 0>;
+	status = "okay";
+};
+
+&pwm1 {
+	phytium,db = <0 0 100 1000 1000 0>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&pmdk_dp {
+	num-dp = <1>;
+	dp-mask = /bits/ 8 <0x1>;
+	status = "okay";
+};
+
+&rng0 {
+	status = "okay";
+};
diff --git a/target/linux/phytium/files-5.10/arch/arm64/configs/phytium_defconfig b/target/linux/phytium/files-5.10/arch/arm64/configs/phytium_defconfig
new file mode 100644
index 00000000000000..d1d1c81d63f4bc
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/configs/phytium_defconfig
@@ -0,0 +1,770 @@
+CONFIG_LOCALVERSION="-phytium-embeded-v2.0"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_USER_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_PHYTIUM=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_XEN=y
+CONFIG_COMPAT=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_HIBERNATION=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPUFREQ_DT=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_ACPI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_AES_ARM64_BS=m
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_KSM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_CMA=y
+CONFIG_CMA_AREAS=19
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IPV6=m
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_NET_DSA=m
+CONFIG_NET_DSA_TAG_OCELOT=m
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_TAPRIO=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_GACT=m
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_GATE=m
+CONFIG_QRTR=m
+CONFIG_QRTR_SMD=m
+CONFIG_QRTR_TUN=m
+CONFIG_BPF_JIT=y
+CONFIG_CAN=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_PHYTIUM=m
+CONFIG_CAN_PHYTIUM_PLATFORM=m
+CONFIG_CAN_PHYTIUM_PCI=m
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+# CONFIG_BT_LE is not set
+CONFIG_BT_LEDS=y
+# CONFIG_BT_DEBUGFS is not set
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NFC=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCIE_ALTERA=y
+CONFIG_PCIE_ALTERA_MSI=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_PHYTIUM_PLAT=m
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_PHYTIUM_QUADSPI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_FC=y
+CONFIG_NVME_TCP=y
+CONFIG_NVME_TARGET=y
+CONFIG_NVME_TARGET_PASSTHRU=y
+CONFIG_NVME_TARGET_LOOP=y
+CONFIG_NVME_TARGET_FC=y
+CONFIG_NVME_TARGET_FCLOOP=y
+CONFIG_NVME_TARGET_TCP=y
+CONFIG_SRAM=y
+CONFIG_PCI_ENDPOINT_TEST=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_UACCE=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_MEGARAID_SAS=y
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_SATA_SIL24=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_TUN=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_AMD_XGBE=y
+CONFIG_ATL1C=m
+CONFIG_BCMGENET=m
+CONFIG_BNX2X=m
+CONFIG_MACB=y
+CONFIG_MACB_PCI=y
+CONFIG_THUNDER_NIC_PF=y
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGBVF=m
+CONFIG_IXGB=m
+CONFIG_IXGBE=m
+CONFIG_IXGBEVF=m
+CONFIG_I40E=m
+CONFIG_I40EVF=m
+CONFIG_MVMDIO=y
+CONFIG_SKY2=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_CORE_EN=y
+CONFIG_QCOM_EMAC=m
+CONFIG_RMNET=m
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+CONFIG_STMMAC_ETH=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_BROADCOM_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MICREL_PHY=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_REALTEK_PHY=m
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_PPP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_QMI_WWAN=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_BRCMFMAC=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_RTL_CARDS=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_RTL8821CS=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_CROS_EC=y
+CONFIG_KEYBOARD_PHYTIUM=m
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_PHYTIUM_PCI=m
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_HISI_V2 is not set
+CONFIG_HW_RANDOM_PHYTIUM=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_PHYTIUM_PCI=y
+CONFIG_I2C_PHYTIUM_PLATFORM=y
+CONFIG_I3C=y
+CONFIG_CDNS_I3C_MASTER=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_PHYTIUM_PLAT=y
+CONFIG_SPI_PHYTIUM_PCI=y
+CONFIG_SPI_PHYTIUM_QSPI=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_MAX77620=y
+CONFIG_GPIO_ALTERA=m
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_MB86S7X=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_WCD934X=m
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_BD9571MWV=m
+CONFIG_GPIO_MAX77620=y
+CONFIG_W1=m
+CONFIG_W1_MASTER_PHYTIUM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_INA3221=m
+CONFIG_SENSORS_PHYTIUM=m
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ARM_SBSA_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_ARM_SMC_WATCHDOG=y
+CONFIG_MFD_BD9571MWV=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_HI6421_PMIC=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_PHYTIUM_I2S_LSD=y
+CONFIG_MFD_PHYTIUM_I2S_MMD=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_ROHM_BD718XX=y
+CONFIG_MFD_WCD934X=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BD718XX=y
+CONFIG_REGULATOR_BD9571MWV=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_HI6421V530=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_MAX8973=y
+CONFIG_REGULATOR_PCA9450=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+# CONFIG_DVB_NET is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_IMX219=m
+CONFIG_VIDEO_OV5645=m
+CONFIG_DRM=y
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_MALI_DISPLAY=m
+CONFIG_DRM_RCAR_DW_HDMI=m
+CONFIG_DRM_RCAR_LVDS=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_NWL_MIPI_DSI=m
+CONFIG_DRM_SII902X=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_THINE_THC63LVD1024=m
+CONFIG_DRM_TI_SN65DSI86=m
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_PHYTIUM=y
+CONFIG_DRM_LEGACY=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_HDA_PHYTIUM=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_PHYTIUM_I2S=y
+CONFIG_SND_PMDK_ES8388=y
+CONFIG_SND_PMDK_ES8336=y
+CONFIG_SND_PMDK_DP=y
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_TAS571X=m
+CONFIG_SND_SOC_WCD934X=m
+CONFIG_SND_SOC_WM8904=m
+CONFIG_SND_SOC_WSA881X=m
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_I2C_HID=m
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_PHYTIUM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CH341=y
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_SNP_UDC_PLAT=y
+CONFIG_USB_BDC_UDC=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_TYPEC=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_HD3SS3220=m
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_HI3798CV200=y
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MMC_SDHCI_AM654=y
+# CONFIG_MMC_PHYTIUM_MCI_PCI is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_EDAC=y
+CONFIG_EDAC_GHES=y
+CONFIG_EDAC_PHYTIUM=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_RK808=m
+CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_RV8803=m
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_DRV_SD3068=m
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_CROS_EC=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_BCM_SBA_RAID=m
+CONFIG_FSL_EDMA=y
+CONFIG_MV_XOR_V2=y
+CONFIG_PL330_DMA=y
+CONFIG_PHYTIUM_DDMA=y
+CONFIG_UIO=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_AEC=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_MF624=m
+CONFIG_VFIO=y
+CONFIG_VFIO_PCI=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_STAGING=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_CHARDEV=m
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_CLK_QORIQ=y
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_VC5=y
+CONFIG_COMMON_CLK_BD718XX=m
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_PHYTIUM=y
+CONFIG_ARM_MHU=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PHYTIUM_MBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_REMOTEPROC=y
+CONFIG_REMOTEPROC_CDEV=y
+CONFIG_HOMO_REMOTEPROC=y
+CONFIG_RPMSG_CHAR=m
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_SOUNDWIRE=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_TI=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON_USBC_CROS_EC=y
+CONFIG_MEMORY=y
+CONFIG_IIO=y
+CONFIG_MAX9611=m
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_PHYTIUM_ADC=m
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_SENSORS_ISL29018=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_MPL3115=m
+CONFIG_PWM=y
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_PHYTIUM=m
+CONFIG_PHYTIUM_IXIC=y
+CONFIG_PHY_XGENE=y
+CONFIG_PHY_FSL_IMX8MQ_USB=y
+CONFIG_PHY_MIXEL_MIPI_DPHY=m
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_SAMSUNG_USB2=y
+CONFIG_ARM_SMMU_V3_PMU=m
+CONFIG_FPGA=y
+CONFIG_FPGA_BRIDGE=m
+CONFIG_ALTERA_FREEZE_BRIDGE=m
+CONFIG_FPGA_REGION=m
+CONFIG_OF_FPGA_REGION=m
+CONFIG_MUX_MMIO=y
+CONFIG_SLIM_QCOM_CTRL=m
+CONFIG_INTERCONNECT=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_OVERLAY_FS=m
+CONFIG_ISO9660_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_EFIVAR_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_SCSILAYOUT=y
+CONFIG_NFSD_FLEXFILELAYOUT=y
+CONFIG_NFSD_V4_2_INTER_SSC=y
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=y
+CONFIG_CRYPTO_DEV_CCREE=m
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
+CONFIG_CRYPTO_DEV_HISI_ZIP=m
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+CONFIG_INDIRECT_PIO=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
diff --git a/target/linux/phytium/files-5.10/arch/arm64/configs/phytium_optee.config b/target/linux/phytium/files-5.10/arch/arm64/configs/phytium_optee.config
new file mode 100644
index 00000000000000..07554cf843d34e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/configs/phytium_optee.config
@@ -0,0 +1,2 @@
+CONFIG_TEE=y
+CONFIG_OPTEE=y
diff --git a/target/linux/phytium/files-5.10/arch/arm64/configs/phytiumpi_firefly_defconfig b/target/linux/phytium/files-5.10/arch/arm64/configs/phytiumpi_firefly_defconfig
new file mode 100644
index 00000000000000..243a07f01ff7cc
--- /dev/null
+++ b/target/linux/phytium/files-5.10/arch/arm64/configs/phytiumpi_firefly_defconfig
@@ -0,0 +1,738 @@
+CONFIG_LOCALVERSION="-phytium-embeded-2023-v1.0-GA"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_USER_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_PHYTIUM=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_XEN=y
+CONFIG_COMPAT=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_HIBERNATION=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPUFREQ_DT=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_ACPI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_AES_ARM64_BS=m
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_KSM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_CMA=y
+CONFIG_CMA_AREAS=19
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IPV6=m
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_NET_DSA=m
+CONFIG_NET_DSA_TAG_OCELOT=m
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_TAPRIO=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_GACT=m
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_GATE=m
+CONFIG_QRTR=m
+CONFIG_QRTR_SMD=m
+CONFIG_QRTR_TUN=m
+CONFIG_BPF_JIT=y
+CONFIG_CAN=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_PHYTIUM=m
+CONFIG_CAN_PHYTIUM_PLATFORM=m
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+# CONFIG_BT_LE is not set
+CONFIG_BT_LEDS=y
+# CONFIG_BT_DEBUGFS is not set
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NFC=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCIE_ALTERA=y
+CONFIG_PCIE_ALTERA_MSI=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_PHYTIUM_QUADSPI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_FC=y
+CONFIG_NVME_TCP=y
+CONFIG_NVME_TARGET=y
+CONFIG_NVME_TARGET_PASSTHRU=y
+CONFIG_NVME_TARGET_LOOP=y
+CONFIG_NVME_TARGET_FC=y
+CONFIG_NVME_TARGET_FCLOOP=y
+CONFIG_NVME_TARGET_TCP=y
+CONFIG_SRAM=y
+CONFIG_PCI_ENDPOINT_TEST=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_UACCE=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_MEGARAID_SAS=y
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_SATA_SIL24=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_TUN=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_AMD_XGBE=y
+CONFIG_ATL1C=m
+CONFIG_BCMGENET=m
+CONFIG_BNX2X=m
+CONFIG_MACB=y
+CONFIG_THUNDER_NIC_PF=y
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGBVF=m
+CONFIG_IXGB=m
+CONFIG_IXGBE=m
+CONFIG_IXGBEVF=m
+CONFIG_I40E=m
+CONFIG_I40EVF=m
+CONFIG_MVMDIO=y
+CONFIG_SKY2=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_CORE_EN=y
+CONFIG_QCOM_EMAC=m
+CONFIG_RMNET=m
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+CONFIG_STMMAC_ETH=m
+CONFIG_AQUANTIA_PHY=y
+CONFIG_BROADCOM_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MICREL_PHY=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_REALTEK_PHY=m
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_PPP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_QMI_WWAN=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_BRCMFMAC=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_RTL_CARDS=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_RTL8821CS=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_CROS_EC=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_INPUT_MISC=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_HISI_V2 is not set
+CONFIG_HW_RANDOM_PHYTIUM=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_PHYTIUM_PLATFORM=y
+CONFIG_I3C=m
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_PHYTIUM_PLAT=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_MAX77620=y
+CONFIG_GPIO_ALTERA=m
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_MB86S7X=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_WCD934X=m
+CONFIG_GPIO_XGENE=y
+# CONFIG_GPIO_PHYTIUM_SGPIO is not set
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_BD9571MWV=m
+CONFIG_GPIO_MAX77620=y
+CONFIG_W1=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_INA3221=m
+CONFIG_SENSORS_PHYTIUM=m
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ARM_SBSA_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_ARM_SMC_WATCHDOG=y
+CONFIG_MFD_BD9571MWV=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_HI6421_PMIC=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_ROHM_BD718XX=y
+CONFIG_MFD_WCD934X=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BD718XX=y
+CONFIG_REGULATOR_BD9571MWV=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_HI6421V530=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_MAX8973=y
+CONFIG_REGULATOR_PCA9450=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+# CONFIG_DVB_NET is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_IMX219=m
+CONFIG_VIDEO_OV5645=m
+CONFIG_DRM=y
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_MALI_DISPLAY=m
+CONFIG_DRM_RCAR_DW_HDMI=m
+CONFIG_DRM_RCAR_LVDS=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_NWL_MIPI_DSI=m
+CONFIG_DRM_SII902X=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_THINE_THC63LVD1024=m
+CONFIG_DRM_TI_SN65DSI86=m
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_PHYTIUM=y
+CONFIG_DRM_LEGACY=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_EFI=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_PHYTIUM_I2S=y
+CONFIG_SND_PMDK_ES8388=y
+CONFIG_SND_PMDK_ES8336=y
+CONFIG_SND_PMDK_DP=y
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_TAS571X=m
+CONFIG_SND_SOC_WCD934X=m
+CONFIG_SND_SOC_WM8904=m
+CONFIG_SND_SOC_WSA881X=m
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_I2C_HID=m
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_PHYTIUM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CH341=y
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_SNP_UDC_PLAT=y
+CONFIG_USB_BDC_UDC=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_TYPEC=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_HD3SS3220=m
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_HI3798CV200=y
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_EDAC=y
+CONFIG_EDAC_GHES=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_RK808=m
+CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_RV8803=m
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_DRV_SD3068=m
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_CROS_EC=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_BCM_SBA_RAID=m
+CONFIG_FSL_EDMA=y
+CONFIG_MV_XOR_V2=y
+CONFIG_PL330_DMA=y
+CONFIG_UIO=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_AEC=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_MF624=m
+CONFIG_VFIO=y
+CONFIG_VFIO_PCI=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_STAGING=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_CHARDEV=m
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_CLK_QORIQ=y
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_VC5=y
+CONFIG_COMMON_CLK_BD718XX=m
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_PHYTIUM=y
+CONFIG_ARM_MHU=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PHYTIUM_MBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_REMOTEPROC=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_SOUNDWIRE=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_TI=y
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON_USBC_CROS_EC=y
+CONFIG_MEMORY=y
+CONFIG_IIO=y
+CONFIG_MAX9611=m
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_PHYTIUM_ADC=m
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_SENSORS_ISL29018=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_MPL3115=m
+CONFIG_PWM=y
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_PHYTIUM=m
+CONFIG_PHY_XGENE=y
+CONFIG_PHY_FSL_IMX8MQ_USB=y
+CONFIG_PHY_MIXEL_MIPI_DPHY=m
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_SAMSUNG_USB2=y
+CONFIG_ARM_SMMU_V3_PMU=m
+CONFIG_FPGA=y
+CONFIG_FPGA_BRIDGE=m
+CONFIG_ALTERA_FREEZE_BRIDGE=m
+CONFIG_FPGA_REGION=m
+CONFIG_OF_FPGA_REGION=m
+CONFIG_MUX_MMIO=y
+CONFIG_SLIM_QCOM_CTRL=m
+CONFIG_INTERCONNECT=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_OVERLAY_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_EFIVAR_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=y
+CONFIG_CRYPTO_DEV_CCREE=m
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
+CONFIG_CRYPTO_DEV_HISI_ZIP=m
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+CONFIG_INDIRECT_PIO=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
diff --git a/target/linux/phytium/files-5.10/drivers/char/hw_random/phytium-rng.c b/target/linux/phytium/files-5.10/drivers/char/hw_random/phytium-rng.c
new file mode 100644
index 00000000000000..5b5e896516b934
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/char/hw_random/phytium-rng.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SoC RNG Driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/bits.h>
+#include <linux/err.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/random.h>
+#include <linux/string.h>
+
+#define	TRNG_CR			0x00
+#define  TRNG_CR_RNGEN		BIT(0)
+#define  TRNG_CR_ROSEN_MASK	GENMASK(7, 4)
+#define  TRNG_CR_DIEN		BIT(16)
+#define  TRNG_CR_ERIEN		BIT(17)
+#define  TRNG_CR_IRQEN		BIT(24)
+#define TRNG_MSEL		0x04
+#define  TRNG_MSEL_MSEL		BIT(0)
+#define TRNG_SR			0x08
+#define  TRNG_SR_HTF		BIT(0)
+#define  TRNG_SR_DRDY		BIT(1)
+#define  TRNG_SR_ERERR		BIT(3)
+#define TRNG_DR			0x0C
+#define TRNG_RESEED		0x40
+#define  TRNG_RESEED_RSED	BIT(0)
+
+#define DELAY	10
+#define TIMEOUT	100
+
+static int msel;
+module_param(msel, int, 0444);
+MODULE_PARM_DESC(msel, "Phytium RNG mode selection: 0 - TRNG. 1 - PRNG.");
+
+struct phytium_rng {
+	struct hwrng rng;
+	void __iomem *base;
+};
+
+static int phytium_rng_init(struct hwrng *rng)
+{
+	struct phytium_rng *priv = container_of(rng, struct phytium_rng, rng);
+	u32 reg;
+
+	/* Mode Selection */
+	reg = msel ? TRNG_MSEL_MSEL : 0;
+	writel(reg, priv->base + TRNG_MSEL);
+
+	/* If PRGN mode is on, do reseed operations */
+	if (msel)
+		writel(TRNG_RESEED_RSED, priv->base + TRNG_RESEED);
+
+	/* Clear status */
+	writel(0x7, priv->base + TRNG_SR);
+
+	/* Enable TRNG */
+	reg = readl(priv->base + TRNG_CR) | TRNG_CR_ROSEN_MASK | TRNG_CR_RNGEN;
+	writel(reg, priv->base + TRNG_CR);
+
+	return 0;
+}
+
+static void phytium_rng_cleanup(struct hwrng *rng)
+{
+	struct phytium_rng *priv = container_of(rng, struct phytium_rng, rng);
+
+	writel(0x7, priv->base + TRNG_SR);
+}
+
+static int phytium_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	struct phytium_rng *priv = container_of(rng, struct phytium_rng, rng);
+	u32 reg;
+	int ret = 0;
+
+	/* TRNG can generate at most 8*32bit random number per time */
+	max = max > 32 ? 32 : max;
+
+	reg = readl(priv->base + TRNG_SR);
+	if (!(reg & TRNG_SR_DRDY) && wait) {
+		ret = readl_poll_timeout(priv->base + TRNG_SR, reg,
+					 reg & TRNG_SR_DRDY, DELAY, TIMEOUT);
+		if (ret) {
+			dev_err((struct device *)priv->rng.priv,
+				"%s: timeout %x!\n", __func__, reg);
+			return -EIO;
+		}
+	}
+
+	while (max >= 4) {
+		*(u32 *)buf = readl(priv->base + TRNG_DR);
+
+		ret += sizeof(u32);
+		buf += sizeof(u32);
+		max -= sizeof(u32);
+	}
+
+	/* Clear DRDY by writing 1 */
+	writel(reg | TRNG_SR_DRDY, priv->base + TRNG_SR);
+
+	return ret;
+}
+
+static int phytium_rng_probe(struct platform_device *pdev)
+{
+	struct phytium_rng *priv;
+	struct resource *mem;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, priv);
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->rng.name = pdev->name;
+	priv->rng.init = phytium_rng_init;
+	priv->rng.cleanup = phytium_rng_cleanup;
+	priv->rng.read = phytium_rng_read;
+	priv->rng.priv = (unsigned long)&pdev->dev;
+	priv->rng.quality = 1000;
+
+	return devm_hwrng_register(&pdev->dev, &priv->rng);
+}
+
+static const struct of_device_id phytium_rng_dt_ids[] = {
+	{ .compatible = "phytium,rng" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_rng_dt_ids);
+
+static struct platform_driver phytium_rng_driver = {
+	.probe = phytium_rng_probe,
+	.driver = {
+		.name = "phytium-rng",
+		.of_match_table = of_match_ptr(phytium_rng_dt_ids),
+	}
+};
+module_platform_driver(phytium_rng_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Phytium random number generator driver");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/char/ipmi/bt_bmc_phytium.c b/target/linux/phytium/files-5.10/drivers/char/ipmi/bt_bmc_phytium.c
new file mode 100755
index 00000000000000..8d650475b63581
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/char/ipmi/bt_bmc_phytium.c
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ *
+ * Derived from drivers/char/ipmi/bt-bmc.c
+ *   Copyright (c) 2015-2016, IBM Corporation.
+ */
+
+#include <linux/atomic.h>
+#include <linux/bt-bmc.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/regmap.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+
+/*
+ * This is a BMC device used to communicate to the host
+ */
+#define DEVICE_NAME	"ipmi-bt-host"
+
+#define BT_IO_BASE	0xe4
+#define BT_IRQ		10
+
+#define LPC_HICR0		0x00
+#define		LPC_HICR0_LPC3E		BIT(7)
+#define		LPC_HICR0_LPC2E		BIT(6)
+#define		LPC_HICR0_LPC1E		BIT(5)
+#define		LPC_HICR0_SDWNE		BIT(3) /* 0:disable, 1:enable for HICR1_SDWNB */
+#define		LPC_HICR0_PMEE		BIT(2) /* 0:disable, 1:enable for HICR1_PMEB */
+
+#define LPC_HICR2		0x08
+#define		LPC_HICR2_IBFIF3	BIT(3) /* 0:normal, 1:enable irq 3*/
+
+#define LPC_HICR4		0x10
+#define		LPC_HICR4_LADR12AS	BIT(7)
+#define		LPC_HICR4_KCSENBL	BIT(2)
+#define		LPC_BTENABLE		BIT(0) /* share bt channel enable, 0:disable, 1:enable */
+#define LPC_LADR3H_BT	0x014
+#define LPC_LADR3L_BT	0x018
+
+#define BT_CR1		0x4C
+#define   BT_CR1_IRQ_H2B		0x04
+#define   BT_CR1_IRQ_HWRST		0x40
+
+#define BT_CSR1		0x54
+#define   BT_CSR1_IRQ_H2B		0x04
+#define   BT_CSR1_IRQ_HWRST		0x40
+
+#define BT_CTRL		0x58
+#define   BT_CTRL_B_BUSY		0x80
+#define   BT_CTRL_H_BUSY		0x40
+#define   BT_CTRL_OEM0			0x20
+#define   BT_CTRL_SMS_ATN		0x10
+#define   BT_CTRL_B2H_ATN		0x08
+#define   BT_CTRL_H2B_ATN		0x04
+#define   BT_CTRL_CLR_RD_PTR		0x02
+#define   BT_CTRL_CLR_WR_PTR		0x01
+#define BT_BMC2HOST	0x5C
+#define BT_HOST2BMC	0x98
+#define BT_INTMASK	0x60
+#define   BT_INTMASK_B2H_IRQEN		0x01
+#define   BT_INTMASK_B2H_IRQ		0x02
+#define   BT_INTMASK_BMC_HWRST		0x80
+
+#define BT_BMC_BUFFER_SIZE 256
+
+struct bt_bmc {
+	struct device		dev;
+	struct miscdevice	miscdev;
+	struct regmap		*map;
+	int			irq;
+	wait_queue_head_t	queue;
+	struct timer_list	poll_timer;
+	struct mutex		mutex;
+};
+
+static atomic_t open_count = ATOMIC_INIT(0);
+
+static const struct regmap_config bt_regmap_cfg = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
+{
+	uint32_t val = 0;
+	int rc;
+
+	rc = regmap_read(bt_bmc->map, reg, &val);
+	WARN(rc != 0, "regmap_read() failed: %d\n", rc);
+
+	return rc == 0 ? (u8) val : 0;
+}
+
+static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
+{
+	int rc;
+
+	rc = regmap_write(bt_bmc->map, reg, data);
+	WARN(rc != 0, "regmap_write() failed: %d\n", rc);
+}
+
+static void clr_rd_ptr(struct bt_bmc *bt_bmc)
+{
+	bt_outb(bt_bmc, BT_CTRL_CLR_RD_PTR, BT_CTRL);
+}
+
+static void clr_wr_ptr(struct bt_bmc *bt_bmc)
+{
+	bt_outb(bt_bmc, BT_CTRL_CLR_WR_PTR, BT_CTRL);
+}
+
+static void clr_h2b_atn(struct bt_bmc *bt_bmc)
+{
+	bt_outb(bt_bmc, 0, BT_CTRL);
+}
+
+static void set_b_busy(struct bt_bmc *bt_bmc)
+{
+	if (!(bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY))
+		bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
+}
+
+static void clr_b_busy(struct bt_bmc *bt_bmc)
+{
+	if (bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY)
+		bt_outb(bt_bmc, 0, BT_CTRL);
+}
+
+static void set_b2h_atn(struct bt_bmc *bt_bmc)
+{
+	bt_outb(bt_bmc, BT_CTRL_B2H_ATN, BT_CTRL);
+}
+
+static u8 bt_read(struct bt_bmc *bt_bmc)
+{
+	return bt_inb(bt_bmc, BT_HOST2BMC);
+}
+
+static ssize_t bt_readn(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
+{
+	int i;
+
+	for (i = 0; i < n; i++)
+		buf[i] = bt_read(bt_bmc);
+	return n;
+}
+
+static void bt_write(struct bt_bmc *bt_bmc, u8 c)
+{
+	bt_outb(bt_bmc, c, BT_BMC2HOST);
+}
+
+static ssize_t bt_writen(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
+{
+	int i;
+
+	for (i = 0; i < n; i++)
+		bt_write(bt_bmc, buf[i]);
+	return n;
+}
+
+static void set_sms_atn(struct bt_bmc *bt_bmc)
+{
+	bt_outb(bt_bmc, BT_CTRL_SMS_ATN, BT_CTRL);
+}
+
+static struct bt_bmc *file_bt_bmc(struct file *file)
+{
+	return container_of(file->private_data, struct bt_bmc, miscdev);
+}
+
+static int bt_bmc_open(struct inode *inode, struct file *file)
+{
+	struct bt_bmc *bt_bmc = file_bt_bmc(file);
+
+	if (atomic_inc_return(&open_count) == 1) {
+		clr_b_busy(bt_bmc);
+		return 0;
+	}
+
+	atomic_dec(&open_count);
+
+	return -EBUSY;
+}
+
+/*
+ * The BT (Block Transfer) interface means that entire messages are
+ * buffered by the host before a notification is sent to the BMC that
+ * there is data to be read. The first byte is the length and the
+ * message data follows. The read operation just tries to capture the
+ * whole before returning it to userspace.
+ *
+ * BT Message format :
+ *
+ *    Byte 1  Byte 2     Byte 3  Byte 4  Byte 5:N
+ *    Length  NetFn/LUN  Seq     Cmd     Data
+ *
+ */
+static ssize_t bt_bmc_read(struct file *file, char __user *buf,
+			   size_t count, loff_t *ppos)
+{
+	struct bt_bmc *bt_bmc = file_bt_bmc(file);
+	u8 len;
+	int len_byte = 1;
+	u8 kbuffer[BT_BMC_BUFFER_SIZE];
+	ssize_t ret = 0;
+	ssize_t nread;
+
+	WARN_ON(*ppos);
+
+	if (wait_event_interruptible(bt_bmc->queue,
+				     bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_H2B_ATN))
+		return -ERESTARTSYS;
+
+	mutex_lock(&bt_bmc->mutex);
+
+	if (unlikely(!(bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_H2B_ATN))) {
+		ret = -EIO;
+		goto out_unlock;
+	}
+
+	set_b_busy(bt_bmc);
+	clr_h2b_atn(bt_bmc);
+	clr_rd_ptr(bt_bmc);
+
+	/*
+	 * The BT frames start with the message length, which does not
+	 * include the length byte.
+	 */
+	kbuffer[0] = bt_read(bt_bmc);
+	len = kbuffer[0];
+
+	/* We pass the length back to userspace as well */
+	if (len + 1 > count)
+		len = count - 1;
+
+	while (len) {
+		nread = min_t(ssize_t, len, sizeof(kbuffer) - len_byte);
+
+		bt_readn(bt_bmc, kbuffer + len_byte, nread);
+
+		if (copy_to_user(buf, kbuffer, nread + len_byte)) {
+			ret = -EFAULT;
+			break;
+		}
+		len -= nread;
+		buf += nread + len_byte;
+		ret += nread + len_byte;
+		len_byte = 0;
+	}
+
+	clr_b_busy(bt_bmc);
+
+out_unlock:
+	mutex_unlock(&bt_bmc->mutex);
+	return ret;
+}
+
+/*
+ * BT Message response format :
+ *
+ *    Byte 1  Byte 2     Byte 3  Byte 4  Byte 5  Byte 6:N
+ *    Length  NetFn/LUN  Seq     Cmd     Code    Data
+ */
+static ssize_t bt_bmc_write(struct file *file, const char __user *buf,
+			    size_t count, loff_t *ppos)
+{
+	struct bt_bmc *bt_bmc = file_bt_bmc(file);
+	u8 kbuffer[BT_BMC_BUFFER_SIZE];
+	ssize_t ret = 0;
+	ssize_t nwritten;
+
+	/*
+	 * send a minimum response size
+	 */
+	if (count < 5)
+		return -EINVAL;
+
+	WARN_ON(*ppos);
+
+	/*
+	 * There's no interrupt for clearing bmc busy so we have to
+	 * poll
+	 */
+	if (wait_event_interruptible(bt_bmc->queue,
+				     !(bt_inb(bt_bmc, BT_CTRL) &
+				       (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN))))
+		return -ERESTARTSYS;
+
+	mutex_lock(&bt_bmc->mutex);
+
+	if (unlikely(bt_inb(bt_bmc, BT_CTRL) &
+		     (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN))) {
+		ret = -EIO;
+		goto out_unlock;
+	}
+
+	clr_wr_ptr(bt_bmc);
+
+	while (count) {
+		nwritten = min_t(ssize_t, count, sizeof(kbuffer));
+		if (copy_from_user(&kbuffer, buf, nwritten)) {
+			ret = -EFAULT;
+			break;
+		}
+
+		bt_writen(bt_bmc, kbuffer, nwritten);
+
+		count -= nwritten;
+		buf += nwritten;
+		ret += nwritten;
+	}
+
+	set_b2h_atn(bt_bmc);
+
+out_unlock:
+	mutex_unlock(&bt_bmc->mutex);
+	return ret;
+}
+
+static long bt_bmc_ioctl(struct file *file, unsigned int cmd,
+			 unsigned long param)
+{
+	struct bt_bmc *bt_bmc = file_bt_bmc(file);
+
+	switch (cmd) {
+	case BT_BMC_IOCTL_SMS_ATN:
+		set_sms_atn(bt_bmc);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int bt_bmc_release(struct inode *inode, struct file *file)
+{
+	struct bt_bmc *bt_bmc = file_bt_bmc(file);
+
+	atomic_dec(&open_count);
+	set_b_busy(bt_bmc);
+	return 0;
+}
+
+static __poll_t bt_bmc_poll(struct file *file, poll_table *wait)
+{
+	struct bt_bmc *bt_bmc = file_bt_bmc(file);
+	__poll_t mask = 0;
+	u8 ctrl;
+
+	poll_wait(file, &bt_bmc->queue, wait);
+
+	ctrl = bt_inb(bt_bmc, BT_CTRL);
+
+	if (ctrl & BT_CTRL_H2B_ATN)
+		mask |= EPOLLIN;
+
+	if (!(ctrl & (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN)))
+		mask |= EPOLLOUT;
+
+	return mask;
+}
+
+static const struct file_operations bt_bmc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= bt_bmc_open,
+	.read		= bt_bmc_read,
+	.write		= bt_bmc_write,
+	.release	= bt_bmc_release,
+	.poll		= bt_bmc_poll,
+	.unlocked_ioctl	= bt_bmc_ioctl,
+};
+
+static void poll_timer(struct timer_list *t)
+{
+	struct bt_bmc *bt_bmc = from_timer(bt_bmc, t, poll_timer);
+
+	bt_bmc->poll_timer.expires += msecs_to_jiffies(500);
+	wake_up(&bt_bmc->queue);
+	add_timer(&bt_bmc->poll_timer);
+}
+
+static irqreturn_t bt_bmc_irq(int irq, void *arg)
+{
+	struct bt_bmc *bt_bmc = arg;
+	u32 reg, intmsk;
+	int rc;
+
+	rc = regmap_read(bt_bmc->map, BT_CR1, &reg);
+	if (rc)
+		return IRQ_NONE;
+
+	reg &= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HWRST;
+	if (!reg)
+		return IRQ_NONE;
+
+	/* ack pending IRQs */
+	regmap_write(bt_bmc->map, BT_CR1, 0);
+
+	if (reg & BT_CR1_IRQ_HWRST) {
+		regmap_read(bt_bmc->map, BT_INTMASK, &intmsk);
+		if (intmsk & BT_INTMASK_BMC_HWRST)
+			regmap_write(bt_bmc->map, BT_INTMASK, 0);
+	}
+
+	wake_up(&bt_bmc->queue);
+	return IRQ_HANDLED;
+}
+
+static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
+			     struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int rc;
+
+	bt_bmc->irq = platform_get_irq(pdev, 0);
+	if (!bt_bmc->irq)
+		return -ENODEV;
+
+	rc = devm_request_irq(dev, bt_bmc->irq, bt_bmc_irq, IRQF_SHARED,
+			      DEVICE_NAME, bt_bmc);
+	if (rc < 0) {
+		dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
+		bt_bmc->irq = 0;
+		return rc;
+	}
+
+	/*
+	 * Configure IRQs on the bmc clearing the H2B and HBUSY bits;
+	 * H2B will be asserted when the bmc has data for us; HBUSY
+	 * will be cleared (along with B2H) when we can write the next
+	 * message to the BT buffer
+	 */
+	rc = regmap_update_bits(bt_bmc->map,  BT_CSR1,
+							BT_CSR1_IRQ_H2B | BT_CSR1_IRQ_HWRST,
+							BT_CSR1_IRQ_H2B | BT_CSR1_IRQ_HWRST);
+
+	return rc;
+}
+
+static int bt_bmc_probe(struct platform_device *pdev)
+{
+	struct bt_bmc *bt_bmc;
+	struct device *dev;
+	int rc;
+
+	if (!pdev || !pdev->dev.of_node)
+		return -ENODEV;
+
+	dev = &pdev->dev;
+	dev_info(dev, "Found bt bmc device\n");
+
+	bt_bmc = devm_kzalloc(dev, sizeof(*bt_bmc), GFP_KERNEL);
+	if (!bt_bmc)
+		return -ENOMEM;
+
+	dev_set_drvdata(&pdev->dev, bt_bmc);
+
+	bt_bmc->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
+
+	mutex_init(&bt_bmc->mutex);
+	init_waitqueue_head(&bt_bmc->queue);
+
+	bt_bmc->miscdev.minor	= MISC_DYNAMIC_MINOR,
+		bt_bmc->miscdev.name	= DEVICE_NAME,
+		bt_bmc->miscdev.fops	= &bt_bmc_fops,
+		bt_bmc->miscdev.parent = dev;
+	rc = misc_register(&bt_bmc->miscdev);
+	if (rc) {
+		dev_err(dev, "Unable to register misc device\n");
+		return rc;
+	}
+
+	bt_bmc_config_irq(bt_bmc, pdev);
+
+	if (bt_bmc->irq) {
+		dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
+	} else {
+		dev_info(dev, "No IRQ; using timer\n");
+		timer_setup(&bt_bmc->poll_timer, poll_timer, 0);
+		bt_bmc->poll_timer.expires = jiffies + msecs_to_jiffies(10);
+		add_timer(&bt_bmc->poll_timer);
+	}
+
+	regmap_update_bits(bt_bmc->map,  LPC_HICR0, LPC_HICR0_LPC3E, LPC_HICR0_LPC3E);
+	regmap_update_bits(bt_bmc->map,  LPC_HICR4, LPC_BTENABLE, LPC_BTENABLE);
+	regmap_write(bt_bmc->map,  LPC_LADR3H_BT, BT_IO_BASE >> 8);
+	regmap_write(bt_bmc->map,  LPC_LADR3L_BT, BT_IO_BASE);
+	regmap_update_bits(bt_bmc->map,  LPC_HICR2, LPC_HICR2_IBFIF3, LPC_HICR2_IBFIF3);
+	clr_b_busy(bt_bmc);
+
+	return 0;
+}
+
+static int bt_bmc_remove(struct platform_device *pdev)
+{
+	struct bt_bmc *bt_bmc = dev_get_drvdata(&pdev->dev);
+
+	misc_deregister(&bt_bmc->miscdev);
+	if (!bt_bmc->irq)
+		del_timer_sync(&bt_bmc->poll_timer);
+
+	return 0;
+}
+
+static const struct of_device_id bt_bmc_match[] = {
+	{ .compatible = "phytium,bt-bmc" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, bt_bmc_match);
+
+static struct platform_driver bt_bmc_driver = {
+	.driver = {
+		.name		= DEVICE_NAME,
+		.of_match_table = bt_bmc_match,
+	},
+	.probe = bt_bmc_probe,
+	.remove = bt_bmc_remove,
+};
+
+module_platform_driver(bt_bmc_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn");
+MODULE_DESCRIPTION("Linux device interface to the BT interface");
diff --git a/target/linux/phytium/files-5.10/drivers/char/ipmi/kcs_bmc_phytium.c b/target/linux/phytium/files-5.10/drivers/char/ipmi/kcs_bmc_phytium.c
new file mode 100755
index 00000000000000..17e29f6e4e6370
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/char/ipmi/kcs_bmc_phytium.c
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ *
+ * Derived from drivers/char/ipmi/kcs_bmc_aspeed.c
+ *   Copyright (c) 2015-2018, Intel Corporation.
+ */
+
+#define pr_fmt(fmt) "phytium-kcs-bmc: " fmt
+
+#include <linux/atomic.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/regmap.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+
+#include "kcs_bmc.h"
+
+#define DEVICE_NAME     "phytium-kcs-bmc"
+
+#define KCS_CHANNEL_MAX     4
+
+/* mapped to lpc-bmc@0 IO space */
+#define LPC_HICR0		0x000
+#define		LPC_HICR0_LPC3E		BIT(7)
+#define		LPC_HICR0_LPC2E		BIT(6)
+#define		LPC_HICR0_LPC1E		BIT(5)
+#define		LPC_HICR0_SDWNE		BIT(3) /* 0:disable, 1:enable for HICR1_SDWNB */
+#define		LPC_HICR0_PMEE		BIT(2) /* 0:disable, 1:enable for HICR1_PMEB */
+#define LPC_HICR1		0x004
+#define		LPC_HICR1_LPCBSY	BIT(7) /* 0:idle, 1:trans busy */
+#define		LPC_HICR1_IRQBSY	BIT(5) /* 0:idle, 1:trans data */
+#define		LPC_HICR1_LPCSWRST	BIT(4) /* 0:normal, 1:reset */
+#define		LPC_HICR1_SDWNB		BIT(3) /* 0:normal, 1:software shutdown */
+#define		LPC_HICR1_PMEB		BIT(2) /* 0:LPCPD low, 1:LPCPD high */
+#define	LPC_HICR2		0x008
+#define		LPC_LPCSWRST_ERRIRQ	BIT(6) /* 0:normal, 1:reset irq */
+#define		LPC_SDWN_ERRIRQ		BIT(5) /* 0:normal, 1:lpcpd irq */
+#define		LPC_ABRT_ERRIRQ         BIT(4) /* 0:normal, 1:lframe low when busy*/
+#define		LPC_HICR2_IBFIF3	BIT(3) /* 0:normal, 1:enable irq 3*/
+#define		LPC_HICR2_IBFIF2	BIT(2)
+#define		LPC_HICR2_IBFIF1	BIT(1)
+/* 0:normal,1:enable err irq-reset,power down,abort */
+#define		LPC_HICR2_ERRIE		BIT(0)
+#define LPC_HICR3		0x00C
+#define		LPC_LFRAME_STATUS	BIT(7) /* R */
+#define		LPC_SERIRQ_STATUS	BIT(5) /* R */
+#define		LPC_LREST_STATUS	BIT(4) /* R */
+#define		LPC_LPCPD_STATUS	BIT(3) /* R */
+#define		LPC_PME_STATUS		BIT(2) /* R */
+#define LPC_HICR4		0x010
+#define		LPC_HICR4_LADR12AS	BIT(7)
+#define		LPC_HICR4_KCSENBL	BIT(2)
+#define		LPC_BTENABLE		BIT(0) /* share bt channel enable, 0:disable, 1:enable */
+#define LPC_LADR3H           0x014
+#define LPC_LADR3L           0x018
+#define LPC_LADR12H          0x01C
+#define LPC_LADR12L          0x020
+#define LPC_IDR1             0x024
+#define LPC_IDR2             0x028
+#define LPC_IDR3             0x02C
+#define LPC_ODR1             0x030
+#define LPC_ODR2             0x034
+#define LPC_ODR3             0x038
+#define LPC_STR1             0x03C
+#define LPC_STR2             0x040
+#define LPC_STR3             0x044
+
+#define LPC_HICRB            0x80
+#define		LPC_HICRB_IBFIF4         BIT(1)
+#define		LPC_HICRB_LPC4E          BIT(0)
+#define LPC_LADR4            0x88
+#define LPC_IDR4             0x8c
+#define LPC_ODR4             0x90
+#define LPC_STR4             0x94
+
+struct phytium_kcs_bmc {
+	struct regmap *map;
+};
+
+static u8 phytium_kcs_inb(struct kcs_bmc *kcs_bmc, u32 reg)
+{
+	struct phytium_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc);
+	u32 val = 0;
+	int rc;
+
+	rc = regmap_read(priv->map, reg, &val);
+	WARN(rc != 0, "regmap_read() failed: %d\n", rc);
+
+	return rc == 0 ? (u8) val : 0;
+}
+
+static void phytium_kcs_outb(struct kcs_bmc *kcs_bmc, u32 reg, u8 data)
+{
+	struct phytium_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc);
+	int rc;
+
+	rc = regmap_write(priv->map, reg, data);
+	WARN(rc != 0, "regmap_write() failed: %d\n", rc);
+}
+
+/*
+ * Background:
+ *   we note D for Data, and C for Cmd/Status, default rules are
+ *     A. KCS1 / KCS2 ( D / C:X / X+4 )
+ *        D / C : CA0h / CA4h
+ *        D / C : CA8h / CACh
+ *     B. KCS3 ( D / C:XX2h / XX3h )
+ *        D / C : CA2h / CA3h
+ *        D / C : CB2h / CB3h -use
+ *     C. KCS4
+ *        D / C : CA4h / CA5h
+ *        D / C : CB0h / CB1h -use
+ */
+static void phytium_kcs_set_address(struct kcs_bmc *kcs_bmc, u16 addr)
+{
+	struct phytium_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc);
+
+	switch (kcs_bmc->channel) {
+	case 1:
+		regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS, 0);
+		regmap_write(priv->map, LPC_LADR12H, addr >> 8);
+		regmap_write(priv->map, LPC_LADR12L, addr & 0xFF);
+		break;
+	case 2:
+		regmap_update_bits(priv->map, LPC_HICR4,
+				   LPC_HICR4_LADR12AS, LPC_HICR4_LADR12AS);
+		regmap_write(priv->map, LPC_LADR12H, addr >> 8);
+		regmap_write(priv->map, LPC_LADR12L, addr & 0xFF);
+		break;
+	case 3:
+		regmap_write(priv->map, LPC_LADR3H, addr >> 8);
+		regmap_write(priv->map, LPC_LADR3L, addr & 0xFF);
+		break;
+	case 4:
+		regmap_write(priv->map, LPC_LADR4, ((addr + 1) << 16) |
+			addr);
+		break;
+	default:
+		break;
+	}
+}
+
+static void phytium_kcs_enable_channel(struct kcs_bmc *kcs_bmc, bool enable)
+{
+	struct phytium_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc);
+
+	switch (kcs_bmc->channel) {
+	case 1:
+		if (enable) {
+			regmap_update_bits(priv->map, LPC_HICR2,
+					   LPC_HICR2_IBFIF1, LPC_HICR2_IBFIF1);
+			regmap_update_bits(priv->map, LPC_HICR0,
+					   LPC_HICR0_LPC1E, LPC_HICR0_LPC1E);
+		} else {
+			regmap_update_bits(priv->map, LPC_HICR0,
+					   LPC_HICR0_LPC1E, 0);
+			regmap_update_bits(priv->map, LPC_HICR2,
+					   LPC_HICR2_IBFIF1, 0);
+		}
+		break;
+	case 2:
+		if (enable) {
+			regmap_update_bits(priv->map, LPC_HICR2,
+					LPC_HICR2_IBFIF2, LPC_HICR2_IBFIF2);
+			regmap_update_bits(priv->map, LPC_HICR0,
+					LPC_HICR0_LPC2E, LPC_HICR0_LPC2E);
+		} else {
+			regmap_update_bits(priv->map, LPC_HICR0,
+					LPC_HICR0_LPC2E, 0);
+			regmap_update_bits(priv->map, LPC_HICR2,
+					LPC_HICR2_IBFIF2, 0);
+		}
+		break;
+	case 3:
+		if (enable) {
+			regmap_update_bits(priv->map, LPC_HICR2,
+					   LPC_HICR2_IBFIF3, LPC_HICR2_IBFIF3);
+			regmap_update_bits(priv->map, LPC_HICR0,
+					   LPC_HICR0_LPC3E, LPC_HICR0_LPC3E);
+			regmap_update_bits(priv->map, LPC_HICR4,
+					   LPC_HICR4_KCSENBL, LPC_HICR4_KCSENBL);
+		} else {
+			regmap_update_bits(priv->map, LPC_HICR0,
+					   LPC_HICR0_LPC3E, 0);
+			regmap_update_bits(priv->map, LPC_HICR4,
+					   LPC_HICR4_KCSENBL, 0);
+			regmap_update_bits(priv->map, LPC_HICR2,
+					   LPC_HICR2_IBFIF3, 0);
+		}
+		break;
+	case 4:
+		if (enable)
+			regmap_update_bits(priv->map, LPC_HICRB,
+					   LPC_HICRB_IBFIF4 | LPC_HICRB_LPC4E,
+					   LPC_HICRB_IBFIF4 | LPC_HICRB_LPC4E);
+		else
+			regmap_update_bits(priv->map, LPC_HICRB,
+					   LPC_HICRB_IBFIF4 | LPC_HICRB_LPC4E,
+					   0);
+		break;
+	default:
+		break;
+	}
+}
+
+static irqreturn_t phytium_kcs_irq(int irq, void *arg)
+{
+	struct kcs_bmc *kcs_bmc = arg;
+
+	if (!kcs_bmc_handle_event(kcs_bmc))
+		return IRQ_HANDLED;
+
+	return IRQ_NONE;
+}
+
+static int phytium_kcs_config_irq(struct kcs_bmc *kcs_bmc, struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int irq;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	return devm_request_irq(dev, irq, phytium_kcs_irq, IRQF_SHARED,
+				dev_name(dev), kcs_bmc);
+}
+
+static const struct kcs_ioreg phytium_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = {
+	{ .idr = LPC_IDR1, .odr = LPC_ODR1, .str = LPC_STR1 },
+	{ .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 },
+	{ .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 },
+	{ .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 },
+};
+
+static int phytium_kcs_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct phytium_kcs_bmc *priv;
+	struct kcs_bmc *kcs_bmc;
+	u32 chan, addr;
+	int rc;
+
+	rc = of_property_read_u32(dev->of_node, "kcs_chan", &chan);
+	if ((rc != 0) || (chan == 0 || chan > KCS_CHANNEL_MAX)) {
+		dev_err(dev, "no valid 'kcs_chan' configured\n");
+		return -ENODEV;
+	}
+
+	rc = of_property_read_u32(dev->of_node, "kcs_addr", &addr);
+	if (rc) {
+		dev_err(dev, "no valid 'kcs_addr' configured\n");
+		return -ENODEV;
+	}
+
+	kcs_bmc = kcs_bmc_alloc(dev, sizeof(*priv), chan);
+	if (!kcs_bmc)
+		return -ENOMEM;
+
+	priv = kcs_bmc_priv(kcs_bmc);
+	priv->map = syscon_node_to_regmap(dev->parent->of_node);
+	if (IS_ERR(priv->map)) {
+		dev_err(dev, "Couldn't get regmap\n");
+		return -ENODEV;
+	}
+
+	kcs_bmc->ioreg = phytium_kcs_bmc_ioregs[chan - 1];
+	kcs_bmc->io_inputb = phytium_kcs_inb;
+	kcs_bmc->io_outputb = phytium_kcs_outb;
+
+	dev_set_drvdata(dev, kcs_bmc);
+
+	phytium_kcs_set_address(kcs_bmc, addr);
+	phytium_kcs_enable_channel(kcs_bmc, true);
+	rc = phytium_kcs_config_irq(kcs_bmc, pdev);
+	if (rc)
+		return rc;
+
+	rc = misc_register(&kcs_bmc->miscdev);
+	if (rc) {
+		dev_err(dev, "Unable to register device\n");
+		return rc;
+	}
+
+	pr_info("channel=%u addr=0x%x idr=0x%x odr=0x%x str=0x%x\n",
+		chan, addr, kcs_bmc->ioreg.idr, kcs_bmc->ioreg.odr, kcs_bmc->ioreg.str);
+
+	return 0;
+}
+
+static int phytium_kcs_remove(struct platform_device *pdev)
+{
+	struct kcs_bmc *kcs_bmc = dev_get_drvdata(&pdev->dev);
+
+	misc_deregister(&kcs_bmc->miscdev);
+
+	return 0;
+}
+
+static const struct of_device_id phytium_kcs_bmc_match[] = {
+	{ .compatible = "phytium,kcs-bmc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_kcs_bmc_match);
+
+static struct platform_driver phytium_kcs_bmc_driver = {
+	.driver = {
+		.name           = DEVICE_NAME,
+		.of_match_table = phytium_kcs_bmc_match,
+	},
+	.probe  = phytium_kcs_probe,
+	.remove = phytium_kcs_remove,
+};
+module_platform_driver(phytium_kcs_bmc_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium device interface to the KCS BMC device");
diff --git a/target/linux/phytium/files-5.10/drivers/dma/phytium/Makefile b/target/linux/phytium/files-5.10/drivers/dma/phytium/Makefile
new file mode 100644
index 00000000000000..71ba9b9fcd4062
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/dma/phytium/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHYTIUM_DDMA) += phytium-ddmac.o
diff --git a/target/linux/phytium/files-5.10/drivers/dma/phytium/phytium-ddmac.c b/target/linux/phytium/files-5.10/drivers/dma/phytium/phytium-ddmac.c
new file mode 100644
index 00000000000000..9ff66bdc96e582
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/dma/phytium/phytium-ddmac.c
@@ -0,0 +1,945 @@
+// SPDX-License-Identifier:  GPL-2.0
+/*
+ * Phytium Device DDMA Controller driver.
+ *
+ * Copyright (c) 2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dmapool.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/completion.h>
+#include <asm/barrier.h>
+#include "phytium-ddmac.h"
+
+
+static inline struct phytium_ddma_device *to_ddma_device(struct dma_chan *chan)
+{
+	return container_of(chan->device, struct phytium_ddma_device, dma_dev);
+}
+
+static inline struct phytium_ddma_chan *to_ddma_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct phytium_ddma_chan, vchan.chan);
+}
+
+static inline struct phytium_ddma_desc *to_ddma_desc(struct virt_dma_desc *vd)
+{
+	return container_of(vd, struct phytium_ddma_desc, vdesc);
+}
+
+static inline struct device *chan_to_dev(struct phytium_ddma_chan *chan)
+{
+	return chan->vchan.chan.device->dev;
+}
+
+static inline struct phytium_ddma_device *chan_to_ddma(
+		struct phytium_ddma_chan *chan)
+{
+	return to_ddma_device(&chan->vchan.chan);
+}
+
+static inline void phytium_ddma_iowrite32(
+		const struct phytium_ddma_device *ddma,
+		const u32 reg, const u32 val)
+{
+	iowrite32(val, ddma->base + reg);
+}
+
+static inline u32 phytium_ddma_ioread32(const struct phytium_ddma_device *ddma,
+					const u32 reg)
+{
+	return ioread32(ddma->base + reg);
+}
+
+static inline void phytium_chan_iowrite32(const struct phytium_ddma_chan *chan,
+					const u32 reg, const u32 val)
+{
+	iowrite32(val, chan->base + reg);
+}
+
+static inline u32 phytium_chan_ioread32(const struct phytium_ddma_chan *chan,
+					const u32 reg)
+{
+	return ioread32(chan->base + reg);
+}
+
+static void phytium_ddma_disable(const struct phytium_ddma_device *ddma)
+{
+	dev_dbg(ddma->dev, "ddma disable\n");
+	phytium_ddma_iowrite32(ddma, DMA_CTL, !DMA_CTL_EN);
+}
+
+static void phytium_ddma_enable(const struct phytium_ddma_device *ddma)
+{
+	dev_dbg(ddma->dev, "ddma enable\n");
+	phytium_ddma_iowrite32(ddma, DMA_CTL, DMA_CTL_EN);
+}
+
+static void phytium_ddma_reset(const struct phytium_ddma_device *ddma)
+{
+	u32 val = 0;
+
+	dev_dbg(ddma->dev, "dma reset\n");
+	val = phytium_ddma_ioread32(ddma, DMA_CTL);
+	val |= DMA_CTL_SRST;
+	phytium_ddma_iowrite32(ddma, DMA_CTL, val);
+
+	udelay(10);
+	val &= ~DMA_CTL_SRST;
+	phytium_ddma_iowrite32(ddma, DMA_CTL, val);
+}
+
+static void phytium_ddma_irq_disable(const struct phytium_ddma_device *ddma)
+{
+	u32 val = 0;
+
+	dev_dbg(ddma->dev, "ddma irq disable\n");
+	val = phytium_ddma_ioread32(ddma, DMA_MASK_INT);
+	val |= DMA_INT_EN;
+	phytium_ddma_iowrite32(ddma, DMA_MASK_INT, val);
+}
+
+static void phytium_ddma_irq_enable(const struct phytium_ddma_device *ddma)
+{
+	u32 val = 0;
+
+	dev_dbg(ddma->dev, "ddma irq enable\n");
+	val = phytium_ddma_ioread32(ddma, DMA_MASK_INT);
+	val &= ~DMA_INT_EN;
+	phytium_ddma_iowrite32(ddma, DMA_MASK_INT, val);
+}
+
+static u32 phytium_ddma_irq_read(const struct phytium_ddma_device *ddma)
+{
+	u32 val = 0;
+
+	val = phytium_ddma_ioread32(ddma, DMA_STAT);
+
+	return val;
+}
+
+static void phytium_chan_irq_disable(struct phytium_ddma_chan *chan)
+{
+	u32 val = 0;
+
+	dev_dbg(chan_to_dev(chan), "channel %d irq disable\n", chan->id);
+	val = phytium_ddma_ioread32(chan_to_ddma(chan), DMA_MASK_INT);
+	val |= DMA_INT_CHAL_EN(chan->id);
+	phytium_ddma_iowrite32(chan_to_ddma(chan), DMA_MASK_INT, val);
+}
+
+static void phytium_chan_irq_enable(struct phytium_ddma_chan *chan)
+{
+	u32 val = 0;
+
+	dev_dbg(chan_to_dev(chan), "channel %d irq enable\n", chan->id);
+	val = phytium_ddma_ioread32(chan_to_ddma(chan), DMA_MASK_INT);
+	val &= ~DMA_INT_CHAL_EN(chan->id);
+	phytium_ddma_iowrite32(chan_to_ddma(chan), DMA_MASK_INT, val);
+}
+
+static void phytium_chan_irq_clear(struct phytium_ddma_chan *chan)
+{
+	u32 val = 0;
+
+	dev_dbg(chan_to_dev(chan), "channel %d irq clear\n", chan->id);
+	val = DMA_STAT_CHAL(chan->id);
+	phytium_ddma_iowrite32(chan_to_ddma(chan), DMA_STAT, val);
+}
+
+static int phytium_chan_disable(struct phytium_ddma_chan *chan)
+{
+	u32 val = 0;
+	int ret = 0;
+
+	dev_dbg(chan_to_dev(chan), "channel %d disable\n", chan->id);
+	val = phytium_chan_ioread32(chan, DMA_CHALX_CTL);
+	if (val | DMA_CHAL_EN) {
+		val &= ~DMA_CHAL_EN;
+		phytium_chan_iowrite32(chan, DMA_CHALX_CTL, val);
+
+		ret = readl_relaxed_poll_timeout_atomic(
+			chan->base + DMA_CHALX_CTL, val,
+			!(val & DMA_CHAL_EN), 0, 100000);
+	}
+	return ret;
+}
+
+static void phytium_chan_enable(struct phytium_ddma_chan *chan)
+{
+	u32 val = 0;
+
+	dev_dbg(chan_to_dev(chan), "channel %d enable\n", chan->id);
+	val = phytium_chan_ioread32(chan, DMA_CHALX_CTL);
+	val |= DMA_CHAL_EN;
+	phytium_chan_iowrite32(chan, DMA_CHALX_CTL, val);
+}
+
+static bool phytium_chan_is_running(const struct phytium_ddma_chan *chan)
+{
+	u32 val;
+
+	val = phytium_chan_ioread32(chan, DMA_CHALX_CTL);
+
+	if (val & DMA_CHAL_EN)
+		return true;
+	else
+		return false;
+}
+
+static void phytium_chan_reset(struct phytium_ddma_chan *chan)
+{
+	u32 val = 0;
+
+	dev_dbg(chan_to_dev(chan), "channel %d reset\n", chan->id);
+	val = phytium_chan_ioread32(chan, DMA_CHALX_CTL);
+	val |= DMA_CHAL_SRST;
+	phytium_chan_iowrite32(chan, DMA_CHALX_CTL, val);
+
+	udelay(10);
+	val &= ~DMA_CHAL_SRST;
+	phytium_chan_iowrite32(chan, DMA_CHALX_CTL, val);
+}
+
+static void phytium_ddma_vdesc_free(struct virt_dma_desc *vd)
+{
+	kfree(to_ddma_desc(vd));
+}
+
+static int phytium_chan_pause(struct dma_chan *chan)
+{
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	int ret = 0;
+
+	ret = phytium_chan_disable(pchan);
+	pchan->busy = false;
+	pchan->is_pasued = true;
+
+	return ret;
+}
+
+static int phytium_chan_resume(struct dma_chan *chan)
+{
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+
+	phytium_chan_enable(pchan);
+	pchan->is_pasued = false;
+
+	return 0;
+}
+
+static void phytium_chan_start_xfer(struct phytium_ddma_chan *chan)
+{
+	struct virt_dma_desc *vdesc = NULL;
+	struct phytium_ddma_sg_req *sg_req = NULL;
+	char *tmp = NULL;
+	int i = 0;
+	unsigned long flags = 0;
+
+	/* chan first xfer settings */
+	if (!chan->desc) {
+		vdesc = vchan_next_desc(&chan->vchan);
+		if (!vdesc)
+			return;
+
+		list_del(&vdesc->node);
+		chan->desc = to_ddma_desc(vdesc);
+		chan->next_sg = 0;
+		chan->current_sg = NULL;
+		dev_dbg(chan_to_dev(chan), "xfer start\n");
+	}
+
+	if (chan->next_sg == chan->desc->num_sgs)
+		chan->next_sg = 0;
+
+	sg_req = &chan->desc->sg_req[chan->next_sg];
+	chan->current_sg = sg_req;
+	/* fill to 4 bytes */
+	switch (sg_req->direction) {
+	case DMA_MEM_TO_DEV:
+		tmp = phys_to_virt(sg_req->mem_addr_l);
+		memset(chan->buf, 0, sg_req->len * 4);
+		for (i = 0; i < sg_req->len; i++)
+			chan->buf[i * 4] = tmp[i];
+		break;
+
+	case DMA_DEV_TO_MEM:
+		memset(chan->buf, 0, sg_req->len * 4);
+		break;
+
+	default:
+		break;
+	}
+
+	/* start transfer */
+	phytium_chan_iowrite32(chan, DMA_CHALX_DDR_LWADDR,
+			chan->paddr & 0xFFFFFFFF);
+	phytium_chan_iowrite32(chan, DMA_CHALX_DDR_UPADDR,
+			(chan->paddr >> 32) & 0xFFFFFFFF);
+	phytium_chan_iowrite32(chan, DMA_CHALX_DEV_ADDR, sg_req->dev_addr);
+	phytium_chan_iowrite32(chan, DMA_CHALX_TS, sg_req->len * 4);
+
+	spin_lock_irqsave(&chan_to_ddma(chan)->lock, flags);
+	phytium_chan_irq_enable(chan);
+	spin_unlock_irqrestore(&chan_to_ddma(chan)->lock, flags);
+	phytium_chan_enable(chan);
+
+	chan->next_sg++;
+	chan->busy = true;
+}
+
+static void phytium_chan_xfer_done(struct phytium_ddma_chan *chan)
+{
+	struct phytium_ddma_sg_req *sg_req = chan->current_sg;
+	char *tmp = NULL;
+	int i = 0;
+
+	if (chan->desc) {
+		if (sg_req->direction ==  DMA_DEV_TO_MEM) {
+			tmp = phys_to_virt(sg_req->mem_addr_l);
+			for (i = 0; i < sg_req->len; i++)
+				tmp[i] = chan->buf[i * 4];
+		}
+
+		chan->busy = false;
+		if (chan->next_sg == chan->desc->num_sgs) {
+			dev_dbg(chan_to_dev(chan), "xfer complete\n");
+			vchan_cookie_complete(&chan->desc->vdesc);
+			chan->desc = NULL;
+			chan->current_sg = NULL;
+		}
+		phytium_chan_disable(chan);
+		phytium_chan_irq_clear(chan);
+		phytium_chan_start_xfer(chan);
+	}
+}
+
+static void phytium_dma_hw_init(struct phytium_ddma_device *ddma)
+{
+	u32 i = 0;
+	int ret = 0;
+
+	phytium_ddma_disable(ddma);
+	phytium_ddma_reset(ddma);
+	phytium_ddma_irq_enable(ddma);
+	phytium_ddma_enable(ddma);
+
+	for (i = 0; i < ddma->dma_channels; i++) {
+		phytium_chan_irq_disable(&ddma->chan[i]);
+		ret = phytium_chan_disable(&ddma->chan[i]);
+		if (ret)
+			dev_err(ddma->dev, "can't disable channel %d\n", i);
+	}
+}
+
+static size_t phytium_ddma_desc_residue(struct phytium_ddma_chan *chan)
+{
+	u32 trans_cnt = 0;
+	u32 residue = 0;
+	int i = 0;
+
+	trans_cnt = phytium_chan_ioread32(chan, DMA_CHALX_TRANS_CNT);
+	residue = chan->current_sg->len - trans_cnt;
+
+	for (i = chan->next_sg; i < chan->desc->num_sgs; i++)
+		residue += chan->desc->sg_req[i].len;
+
+	return residue;
+}
+
+static enum dma_status phytium_ddma_tx_status(struct dma_chan *chan,
+					   dma_cookie_t cookie,
+					   struct dma_tx_state *txstate)
+{
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	struct virt_dma_desc *vd = NULL;
+	enum dma_status ret = 0;
+	unsigned long flags = 0;
+	size_t residue = 0;
+
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if ((ret == DMA_COMPLETE) || !txstate)
+		return ret;
+
+	spin_lock_irqsave(&pchan->vchan.lock, flags);
+	vd = vchan_find_desc(&pchan->vchan, cookie);
+	if (pchan->desc && cookie == pchan->desc->vdesc.tx.cookie)
+		residue = phytium_ddma_desc_residue(pchan);
+
+	dma_set_residue(txstate, residue);
+	spin_unlock_irqrestore(&pchan->vchan.lock, flags);
+
+	if (pchan->is_pasued && ret == DMA_IN_PROGRESS)
+		ret = DMA_PAUSED;
+
+	return ret;
+}
+
+static void phytium_ddma_issue_pending(struct dma_chan *chan)
+{
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(&pchan->vchan.lock, flags);
+
+	if (vchan_issue_pending(&pchan->vchan) && !pchan->desc && !pchan->busy)
+		phytium_chan_start_xfer(pchan);
+
+	spin_unlock_irqrestore(&pchan->vchan.lock, flags);
+}
+
+static int phytium_ddma_terminate_all(struct dma_chan *chan)
+{
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	unsigned long flags = 0;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&pchan->vchan.lock, flags);
+	if (pchan->desc) {
+		vchan_terminate_vdesc(&pchan->desc->vdesc);
+		if (pchan->busy) {
+			u32 tmp_ctl, timeout;
+			phytium_chan_disable(pchan);
+			/* save some registers, reset will clear it */
+			timeout = phytium_chan_ioread32(pchan,
+						DMA_CHALX_TIMEOUT_CNT);
+			tmp_ctl = phytium_chan_ioread32(pchan,
+						DMA_CHALX_CTL);
+			spin_lock(&chan_to_ddma(pchan)->lock);
+			phytium_chan_irq_disable(pchan);
+			spin_unlock(&chan_to_ddma(pchan)->lock);
+			/* need reset when terminate */
+			phytium_chan_reset(pchan);
+			phytium_chan_irq_clear(pchan);
+			/* recover it */
+			phytium_chan_iowrite32(pchan,
+						DMA_CHALX_CTL, tmp_ctl);
+			phytium_chan_iowrite32(pchan,
+						DMA_CHALX_TIMEOUT_CNT, timeout);
+			pchan->busy = false;
+		}
+		pchan->desc = NULL;
+	}
+
+	vchan_get_all_descriptors(&pchan->vchan, &head);
+	spin_unlock_irqrestore(&pchan->vchan.lock, flags);
+	vchan_dma_desc_free_list(&pchan->vchan, &head);
+
+	return 0;
+}
+
+static int phytium_ddma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct phytium_ddma_device *ddma = to_ddma_device(chan);
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	u32 bind_status = 0;
+	int ret = 0;
+	unsigned long flags = 0;
+
+	bind_status = phytium_ddma_ioread32(ddma, DMA_CHAL_BIND);
+
+	if ((pchan->is_used) || (bind_status & BIT(pchan->id))) {
+		dev_err(ddma->dev, "channel %d already used\n", pchan->id);
+		ret = -EBUSY;
+		goto out;
+	}
+
+	/* prepare channel */
+	ret = phytium_chan_disable(pchan);
+	if (ret) {
+		dev_err(ddma->dev, "can't disable channel %d\n", pchan->id);
+		goto out;
+	}
+	phytium_chan_reset(pchan);
+	phytium_chan_irq_clear(pchan);
+
+	/* channel bind */
+	spin_lock_irqsave(&chan_to_ddma(pchan)->lock, flags);
+	bind_status |= BIT(pchan->id);
+	phytium_ddma_iowrite32(ddma, DMA_CHAL_BIND, bind_status);
+	pchan->is_used = true;
+	spin_unlock_irqrestore(&chan_to_ddma(pchan)->lock, flags);
+
+	/* alloc dma memory */
+	pchan->buf = dma_alloc_coherent(ddma->dev, 4 * PAGE_SIZE, &pchan->paddr,
+					GFP_KERNEL);
+	if (!pchan->buf) {
+		ret = -EBUSY;
+		dev_err(ddma->dev, "failed to alloc dma memory\n");
+	}
+
+	dev_info(ddma->dev, "alloc channel %d\n", pchan->id);
+
+out:
+	return ret;
+}
+
+static void phytium_ddma_free_chan_resources(struct dma_chan *chan)
+{
+	struct phytium_ddma_device *ddma = to_ddma_device(chan);
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	u32 bind_status = 0;
+	unsigned long flags = 0;
+
+	if (!pchan->is_used)
+		return;
+
+	dev_dbg(ddma->dev, "free channel %d\n", pchan->id);
+	spin_lock_irqsave(&chan_to_ddma(pchan)->lock, flags);
+	bind_status = phytium_ddma_ioread32(ddma, DMA_CHAL_BIND);
+	bind_status &= ~BIT(pchan->id);
+	phytium_ddma_iowrite32(ddma, DMA_CHAL_BIND, bind_status);
+	spin_unlock_irqrestore(&chan_to_ddma(pchan)->lock, flags);
+
+	phytium_chan_disable(pchan);
+
+	spin_lock_irqsave(&chan_to_ddma(pchan)->lock, flags);
+	phytium_chan_irq_disable(pchan);
+	spin_unlock_irqrestore(&chan_to_ddma(pchan)->lock, flags);
+
+	vchan_free_chan_resources(to_virt_chan(chan));
+	pchan->is_used = false;
+
+	if (pchan->buf)
+		dma_free_coherent(ddma->dev, 4 * PAGE_SIZE,
+				pchan->buf, pchan->paddr);
+}
+
+static int phytium_ddma_slave_config(struct dma_chan *chan,
+				  struct dma_slave_config *config)
+{
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	u32 chal_cfg = 0;
+	u32 req_mode = 0;
+	const u32 timeout = 0xffff;
+	unsigned long flag = 0;
+
+	/* Check if chan will be configured for slave transfers */
+	if (!is_slave_direction(config->direction))
+		return -EINVAL;
+
+	memcpy(&pchan->dma_config, config, sizeof(*config));
+
+	/* set channel config reg */
+	spin_lock_irqsave(&chan_to_ddma(pchan)->lock, flag);
+	if (pchan->id > 3) {
+		chal_cfg = phytium_ddma_ioread32(chan_to_ddma(pchan),
+				DMA_CHAL_CFG_H);
+		chal_cfg &= ~(0xFF << ((pchan->id - 4) * 8));
+		chal_cfg |= DMA_CHAL_SEL((pchan->id - 4), pchan->request_line);
+		chal_cfg |= DMA_CHAL_SEL_EN(pchan->id - 4);
+		phytium_ddma_iowrite32(chan_to_ddma(pchan), DMA_CHAL_CFG_H,
+				chal_cfg);
+	} else {
+		chal_cfg = phytium_ddma_ioread32(chan_to_ddma(pchan),
+				DMA_CHAL_CFG_L);
+		chal_cfg &= ~(0xFF << (pchan->id * 8));
+		chal_cfg |= DMA_CHAL_SEL((pchan->id), pchan->request_line);
+		chal_cfg |= DMA_CHAL_SEL_EN(pchan->id);
+		phytium_ddma_iowrite32(chan_to_ddma(pchan), DMA_CHAL_CFG_L,
+				chal_cfg);
+	}
+	spin_unlock_irqrestore(&chan_to_ddma(pchan)->lock, flag);
+
+	/* set channel mode */
+	req_mode = (config->direction == DMA_DEV_TO_MEM) ?
+		DMA_RX_REQ : DMA_TX_REQ;
+	phytium_chan_iowrite32(pchan, DMA_CHALX_CTL, req_mode << 2);
+
+	/* set channel timeout */
+	phytium_chan_iowrite32(pchan, DMA_CHALX_TIMEOUT_CNT,
+			timeout | DMA_CHAL_TIMEOUT_EN);
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *phytium_ddma_prep_slave_sg(
+	struct dma_chan *chan, struct scatterlist *sgl,
+	u32 sg_len, enum dma_transfer_direction direction,
+	unsigned long flags, void *context)
+{
+	struct phytium_ddma_device *ddma = to_ddma_device(chan);
+	struct phytium_ddma_chan *pchan = to_ddma_chan(chan);
+	struct dma_slave_config	*sconfig = &pchan->dma_config;
+	struct phytium_ddma_desc *desc = NULL;
+	struct scatterlist *sg = NULL;
+	int i = 0;
+	char *tmp;
+
+	if (unlikely(!is_slave_direction(direction))) {
+		dev_err(ddma->dev, "invalid dma direction\n");
+		return NULL;
+	}
+
+	if (unlikely(sg_len < 1)) {
+		dev_err(ddma->dev, "invalid segment length: %d\n", sg_len);
+		return NULL;
+	}
+
+	desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT);
+	if (!desc)
+		return NULL;
+
+	/* set sg list */
+	for_each_sg(sgl, sg, sg_len, i) {
+		tmp = phys_to_virt(sg_dma_address(sg));
+		desc->sg_req[i].direction = direction;
+
+		switch (direction) {
+		case DMA_MEM_TO_DEV:
+			desc->sg_req[i].len = sg_dma_len(sg);
+			desc->sg_req[i].mem_addr_l =
+				sg_dma_address(sg) & 0xFFFFFFFF;
+			desc->sg_req[i].mem_addr_h =
+				(sg_dma_address(sg) >> 32) & 0xFFFFFFFF;
+			desc->sg_req[i].dev_addr =
+				sconfig->dst_addr & 0xFFFFFFFF;
+			break;
+
+		case DMA_DEV_TO_MEM:
+			desc->sg_req[i].len = sg_dma_len(sg);
+			desc->sg_req[i].mem_addr_l =
+				sg_dma_address(sg) & 0xFFFFFFFF;
+			desc->sg_req[i].mem_addr_h =
+				(sg_dma_address(sg) >> 32) & 0xFFFFFFFF;
+			desc->sg_req[i].dev_addr =
+				sconfig->src_addr & 0xFFFFFFFF;
+			break;
+
+		default:
+			return NULL;
+		}
+	}
+
+	desc->num_sgs = sg_len;
+
+	return vchan_tx_prep(&pchan->vchan, &desc->vdesc, flags);
+}
+
+static irqreturn_t phytium_dma_interrupt(int irq, void *dev_id)
+{
+	struct phytium_ddma_device *ddma = dev_id;
+	struct phytium_ddma_chan *chan;
+	u32 irq_status = 0;
+	u32 i = 0;
+	u32 val = 0;
+
+	phytium_ddma_irq_disable(ddma);
+
+	irq_status = phytium_ddma_irq_read(ddma);
+	val = phytium_ddma_ioread32(ddma, DMA_CTL);
+
+	/* Poll, clear and process every chanel interrupt status */
+	for (i = 0; i < ddma->dma_channels; i++) {
+		if (!(irq_status & BIT(i * 4)))
+			continue;
+
+		chan = &ddma->chan[i];
+		phytium_chan_xfer_done(chan);
+	}
+
+	phytium_ddma_irq_enable(ddma);
+
+	return IRQ_HANDLED;
+}
+
+
+static struct dma_chan *phytium_ddma_of_xlate(struct of_phandle_args *dma_spec,
+						struct of_dma *ofdma)
+{
+	struct phytium_ddma_device *ddma = ofdma->of_dma_data;
+	struct device *dev = ddma->dev;
+	struct phytium_ddma_chan *chan = NULL;
+	struct dma_chan *c = NULL;
+	u32 channel_id = 0;
+
+	channel_id = dma_spec->args[0];
+
+	if (channel_id > ddma->dma_channels) {
+		dev_err(dev, "bad channel %d\n", channel_id);
+		return NULL;
+	}
+
+	chan = &ddma->chan[channel_id];
+	chan->request_line = dma_spec->args[1];
+	c = dma_get_slave_channel(&chan->vchan.chan);
+	if (!c) {
+		dev_err(dev, "no more channels available\n");
+		return NULL;
+	}
+
+	return c;
+}
+
+static int phytium_ddma_probe(struct platform_device *pdev)
+{
+	struct phytium_ddma_device *ddma;
+	struct dma_device *dma_dev;
+	struct resource *mem;
+	u32 i = 0;
+	int ret = 0;
+	u32 nr_channels = 0;
+
+	ddma = devm_kzalloc(&pdev->dev, sizeof(*ddma), GFP_KERNEL);
+	if (!ddma) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	dma_dev = &ddma->dma_dev;
+	ddma->dev = &pdev->dev;
+
+	spin_lock_init(&ddma->lock);
+
+	ddma->irq = platform_get_irq(pdev, 0);
+	if (ddma->irq < 0) {
+		dev_err(&pdev->dev, "no irq resource\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	ddma->base = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(ddma->base)) {
+		dev_err(&pdev->dev, "no resource address");
+		ret = PTR_ERR(ddma->base);
+		goto out;
+	}
+
+	ret = of_property_read_u32(pdev->dev.of_node, "dma-channels",
+			&nr_channels);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"can't get the number of dma channels: %d\n", ret);
+		goto out;
+	}
+
+	if (nr_channels > DDMA_MAX_NR_PCHANNELS) {
+		dev_warn(&pdev->dev, "over the max number of channels\n");
+		nr_channels = DDMA_MAX_NR_PCHANNELS;
+	}
+
+	ddma->dma_channels = DDMA_MAX_NR_PCHANNELS;
+
+	ret = devm_request_irq(&pdev->dev, ddma->irq, phytium_dma_interrupt,
+			       IRQF_SHARED, dev_name(&pdev->dev), ddma);
+	if (ret) {
+		dev_err(&pdev->dev, "could not to request irq %d", ddma->irq);
+		goto out;
+	}
+
+	/* Set capabilities */
+	dma_cap_set(DMA_SLAVE, ddma->dma_dev.cap_mask);
+
+	/* DMA capabilities */
+	dma_dev->dev = ddma->dev;
+	dma_dev->chancnt = ddma->dma_channels;
+	dma_dev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+	dma_dev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+	dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+	dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+
+	/* function callback */
+	dma_dev->device_tx_status = phytium_ddma_tx_status;
+	dma_dev->device_issue_pending = phytium_ddma_issue_pending;
+	dma_dev->device_terminate_all = phytium_ddma_terminate_all;
+	dma_dev->device_alloc_chan_resources =
+		phytium_ddma_alloc_chan_resources;
+	dma_dev->device_free_chan_resources = phytium_ddma_free_chan_resources;
+	dma_dev->device_config = phytium_ddma_slave_config;
+	dma_dev->device_prep_slave_sg = phytium_ddma_prep_slave_sg;
+	dma_dev->device_pause = phytium_chan_pause;
+	dma_dev->device_resume = phytium_chan_resume;
+
+	/* init dma physical channels */
+	INIT_LIST_HEAD(&dma_dev->channels);
+	ddma->chan = devm_kcalloc(ddma->dev, ddma->dma_channels,
+				sizeof(*ddma->chan), GFP_KERNEL);
+	if (!ddma->chan) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	for (i = 0; i < ddma->dma_channels; i++) {
+		ddma->chan[i].id = i;
+		ddma->chan[i].buf = NULL;
+		ddma->chan[i].base = ddma->base + DMA_REG_LEN +
+			i * CHAN_REG_LEN;
+		ddma->chan[i].vchan.desc_free = phytium_ddma_vdesc_free;
+		ddma->chan[i].desc = NULL;
+		ddma->chan[i].current_sg = NULL;
+		vchan_init(&ddma->chan[i].vchan, dma_dev);
+	}
+
+	phytium_dma_hw_init(ddma);
+
+	ret = dma_async_device_register(dma_dev);
+	if (ret)
+		goto out;
+
+	ret = of_dma_controller_register(pdev->dev.of_node,
+			phytium_ddma_of_xlate, ddma);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"phytium ddma of register failed %d\n", ret);
+		goto err_unregister;
+	}
+
+	platform_set_drvdata(pdev, ddma);
+	dev_info(ddma->dev, "phytium DDMA Controller registered\n");
+
+	return 0;
+
+err_unregister:
+	dma_async_device_unregister(dma_dev);
+
+out:
+	return ret;
+}
+
+static void phytium_ddma_chan_remove(struct phytium_ddma_chan *chan)
+{
+	phytium_chan_irq_disable(chan);
+	phytium_chan_disable(chan);
+
+	if (chan->buf)
+		dma_free_coherent(chan_to_dev(chan), 4 * PAGE_SIZE, chan->buf,
+				chan->paddr);
+
+	tasklet_kill(&chan->vchan.task);
+	list_del(&chan->vchan.chan.device_node);
+}
+
+static int phytium_ddma_remove(struct platform_device *pdev)
+{
+	struct phytium_ddma_device *ddma = platform_get_drvdata(pdev);
+	struct phytium_ddma_chan *chan = NULL;
+	int i = 0;
+
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&ddma->dma_dev);
+
+	for (i = 0; i < ddma->dma_channels; i++) {
+		chan = &ddma->chan[i];
+		phytium_ddma_chan_remove(chan);
+	}
+
+	phytium_ddma_irq_disable(ddma);
+	phytium_ddma_disable(ddma);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_ddma_suspend(struct device *dev)
+{
+	struct phytium_ddma_device *ddma = dev_get_drvdata(dev);
+	int i = 0;
+
+	for (i = 0; i < ddma->dma_channels; i++) {
+		if (phytium_chan_is_running(&ddma->chan[i])) {
+			dev_warn(dev,
+				"suspend is prevented by channel %d\n", i);
+			return -EBUSY;
+		}
+	}
+
+	ddma->dma_reg.dma_chal_cfg0 =
+		phytium_ddma_ioread32(ddma, DMA_CHAL_CFG_L);
+	ddma->dma_reg.dma_chal_bind =
+		phytium_ddma_ioread32(ddma, DMA_CHAL_BIND);
+	ddma->dma_reg.dma_chal_cfg1 =
+		phytium_ddma_ioread32(ddma, DMA_CHAL_CFG_H);
+
+	for (i = 0; i < ddma->dma_channels; i++) {
+		struct phytium_ddma_chan *chan = &ddma->chan[i];
+
+		if (!chan->is_used)
+			continue;
+		ddma->dma_chal_reg[i].dma_chalx_ctl =
+			phytium_chan_ioread32(chan, DMA_CHALX_CTL);
+		ddma->dma_chal_reg[i].dma_chalx_timeout_cnt =
+			phytium_chan_ioread32(chan, DMA_CHALX_TIMEOUT_CNT);
+	}
+
+	phytium_ddma_irq_disable(ddma);
+	phytium_ddma_disable(ddma);
+	pm_runtime_force_suspend(dev);
+
+	return 0;
+}
+
+static int phytium_ddma_resume(struct device *dev)
+{
+	struct phytium_ddma_device *ddma = dev_get_drvdata(dev);
+	u32 i = 0;
+	int ret = 0;
+
+	phytium_dma_hw_init(ddma);
+	phytium_ddma_iowrite32(ddma, DMA_CHAL_CFG_L,
+		ddma->dma_reg.dma_chal_cfg0);
+	phytium_ddma_iowrite32(ddma, DMA_CHAL_BIND,
+		ddma->dma_reg.dma_chal_bind);
+	phytium_ddma_iowrite32(ddma, DMA_CHAL_CFG_H,
+		ddma->dma_reg.dma_chal_cfg1);
+
+	for (i = 0; i < ddma->dma_channels; i++) {
+		struct phytium_ddma_chan *chan = &ddma->chan[i];
+
+		if (!chan->is_used)
+			continue;
+		phytium_chan_iowrite32(chan, DMA_CHALX_CTL,
+			ddma->dma_chal_reg[i].dma_chalx_ctl);
+		phytium_chan_iowrite32(chan, DMA_CHALX_TIMEOUT_CNT,
+			ddma->dma_chal_reg[i].dma_chalx_timeout_cnt);
+	}
+
+	ret = pm_runtime_force_resume(dev);
+
+	return ret;
+}
+#endif
+
+static const struct dev_pm_ops phytium_ddma_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(phytium_ddma_suspend,
+			phytium_ddma_resume)
+};
+
+static const struct of_device_id phytium_dma_of_id_table[] = {
+	{ .compatible = "phytium,ddma" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, phytium_dma_of_id_table);
+
+static struct platform_driver phytium_driver = {
+	.probe		= phytium_ddma_probe,
+	.remove		= phytium_ddma_remove,
+	.driver = {
+		.name	= "phytium-ddma",
+		.of_match_table = of_match_ptr(phytium_dma_of_id_table),
+		.pm = &phytium_ddma_pm_ops,
+	},
+};
+
+module_platform_driver(phytium_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium DDMA Controller platform driver");
+MODULE_AUTHOR("HuangJie <huangjie1663@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/dma/phytium/phytium-ddmac.h b/target/linux/phytium/files-5.10/drivers/dma/phytium/phytium-ddmac.h
new file mode 100644
index 00000000000000..81bc0e19e64961
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/dma/phytium/phytium-ddmac.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Phytium Device DDMA Controller driver.
+ *
+ * Copyright (c) 2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef _PHYTIUM_DDMAC_H
+#define _PHYTIUM_DDMAC_H
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/dmaengine.h>
+#include <linux/types.h>
+#include "../virt-dma.h"
+
+/* the number of physical channel */
+#define DDMA_MAX_NR_PCHANNELS	8
+
+#define DMAC_MAX_MASTERS	1
+#define DMAC_MAX_BLK_SIZE	PAGE_SIZE
+
+#define CHAN_REG_LEN		0x40
+#define DMA_REG_LEN		0x40
+
+#define DMA_CTL			0x00
+#define DMA_CHAL_CFG_L		0x04
+#define DMA_CHAL_CFG_H		0x28
+#define DMA_STAT		0x08
+#define DMA_MASK_INT		0x0C
+#define DMA_CHAL_BIND		0x20
+#define DMA_GCAP		0x24
+
+#define DMA_CHALX_DDR_UPADDR	0x00
+#define DMA_CHALX_DDR_LWADDR	0x04
+#define DMA_CHALX_DEV_ADDR	0x08
+#define DMA_CHALX_TS		0x0C
+#define DMA_CHALX_CRT_UPADDR	0x10
+#define DMA_CHALX_CRT_LWADDR	0x14
+#define DMA_CHALX_CTL		0x18
+#define DMA_CHALX_STS		0x1C
+#define DMA_CHALX_TIMEOUT_CNT	0x20
+#define DMA_CHALX_TRANS_CNT	0x24
+
+#define DMA_CTL_EN		BIT(0)
+#define DMA_CTL_SRST		BIT(1)
+
+#define DMA_CHAL_SEL(id, x)	(min_t(unsigned int, x, 0x7F) << ((id) * 8))
+#define DMA_CHAL_SEL_EN(id)	BIT((id) * 8 + 7)
+
+#define DMA_STAT_CHAL(id)	BIT((id) * 4)
+
+#define DMA_INT_EN		BIT(31)
+#define DMA_INT_CHAL_EN(id)	BIT(id)
+
+#define DMA_CHAL_EN		BIT(0)
+#define DMA_CHAL_SRST		BIT(1)
+#define DMA_CHAL_MODE		BIT(2)
+
+#define DMA_RX_REQ		1
+#define DMA_TX_REQ		0
+
+#define DMA_CHAL_TIMEOUT_EN	BIT(31)
+#define DMA_CHAL_TIMEOUT_CNT(x)	min_t(unsigned int, x, 0xFFFFF)
+
+#define DMA_TIMEOUT		10
+
+/**
+ * struct phytium_ddma_sg_req - scatter-gatter list data info
+ * @len: number of bytes to transform
+ * @mem_addr_l: bus address low 32bit
+ * @mem_addr_h: bus address high 32bit
+ * @dev_addr: dma cousumer data reg addr
+ * @direction: dma transmit direction
+ */
+struct phytium_ddma_sg_req {
+	u32 len;
+	u32 mem_addr_l;
+	u32 mem_addr_h;
+	u32 dev_addr;
+	enum dma_transfer_direction direction;
+};
+
+/**
+ * struct phytium_ddma_desc - the struct holding info describing ddma request
+ * descriptor
+ * @vdesc: ddma request descriptor
+ * @num_sgs: the size of scatter-gatter list
+ * @sg_req: use to save scatter-gatter list info
+ */
+struct phytium_ddma_desc {
+	struct virt_dma_desc vdesc;
+	u32 num_sgs;
+	struct phytium_ddma_sg_req sg_req[];
+};
+
+/**
+ * struct phytium_ddma_chan - the struct holding info describing dma channel
+ * @vchan: virtual dma channel
+ * @base: the mapped register I/O of dma physical channel
+ * @id: the id of ddma physical channel
+ * @request_line: the request line of ddma channel
+ * @desc: the transform request descriptor
+ * @dma_config: config parameters for dma channel
+ * @busy: the channel busy flag, this flag set when channel is tansferring
+ * @is_used: the channel bind flag, this flag set when channel binded
+ * @next_sg: the index of next scatter-gatter
+ * @current_sg: use to save the current transfer scatter-gatter info
+ * @paddr: use to align data between dma provider and consumer
+ */
+struct phytium_ddma_chan {
+	struct virt_dma_chan vchan;
+	void __iomem *base;
+	u32 id;
+	u32 request_line;
+	struct phytium_ddma_desc *desc;
+	struct dma_slave_config dma_config;
+	bool busy;
+	bool is_used;
+	bool is_pasued;
+	u32 next_sg;
+	struct phytium_ddma_sg_req *current_sg;
+	dma_addr_t paddr;
+	char *buf;
+};
+
+struct global_reg {
+	u32 dma_chal_cfg0;
+	u32 dma_chal_bind;
+	u32 dma_chal_cfg1;
+};
+
+struct channel_reg {
+	u32 dma_chalx_ctl;
+	u32 dma_chalx_timeout_cnt;
+};
+
+/**
+ * struct phytium_ddma_device - the struct holding info describing DDMA device
+ * @dma_dev: an instance for struct dma_device
+ * @irq: the irq that DDMA using
+ * @base: the mapped register I/O base of this DDMA
+ * @core_clk: DDMA clock
+ * @dma_channels: the number of DDMA physical channels
+ * @chan: the phyical channels of DDMA
+ * @lock: spinlock to lock when set global registers
+ * @dma_reg: store global register value which need recover after resume
+ * @dma_chal_reg: store channel register value which need recover after resume
+ */
+struct phytium_ddma_device {
+	struct dma_device dma_dev;
+	struct device *dev;
+	int	irq;
+	void __iomem *base;
+	struct clk *core_clk;
+	u32 dma_channels;
+	struct phytium_ddma_chan *chan;
+	spinlock_t lock;
+	struct global_reg dma_reg;
+	struct channel_reg dma_chal_reg[DDMA_MAX_NR_PCHANNELS];
+};
+
+#endif /* _PHYTIUM_DDMAC_H */
diff --git a/target/linux/phytium/files-5.10/drivers/edac/phytium_edac.c b/target/linux/phytium/files-5.10/drivers/edac/phytium_edac.c
new file mode 100644
index 00000000000000..d16ac658d780b9
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/edac/phytium_edac.c
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Phytium Pe220x EDAC (error detection and correction)
+ *
+ * Copyright (c) 2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/ctype.h>
+#include <linux/edac.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <ras/ras_event.h>
+#include <linux/uaccess.h>
+#include "edac_module.h"
+
+#define EDAC_MOD_STR			"phytium_edac"
+
+/* register offset */
+#define ERR_STATUS(n)			(0x10 + ((n) * 64))
+#define ERR_CTLR(n)			(0x08 + ((n) * 64))
+#define ERR_MISC0(n)			(0x20 + ((n) * 64))
+#define ERR_INJECT			0x7C
+#define ERR_DEVID			0xFC8
+#define ERR_GSR				0xE00
+
+#define CTLR_ED				BIT(0)
+#define CTLR_UI				BIT(2)
+#define CTLR_CFI			BIT(8)
+
+#define MISC0_CEC(x)			((u64)(x) << 32)
+
+#define ERR_STATUS_CLEAR		GENMASK(31, 0)
+
+#define CORRECTED_ERROR			0
+#define UNCORRECTED_ERROR		1
+
+#define MAX_ERR_GROUP			3
+
+struct phytium_edac {
+	struct device		*dev;
+	void __iomem		**ras_base;
+	struct dentry		*dfs;
+	struct edac_device_ctl_info *edac_dev;
+};
+
+struct ras_error_info {
+	u32 index;
+	u32 error_type;
+	const char *error_str;
+};
+
+/* error severity definition */
+enum {
+	SEV_NO = 0x0,
+	SEV_CORRECTED = 0x1,
+	SEV_RECOVERABLE = 0x2,
+	SEV_PANIC = 0x3,
+};
+
+/* soc error record */
+static const struct ras_error_info pe220x_ras_soc_error[] = {
+	{ 0, UNCORRECTED_ERROR, "lsd_nfc_ras_error" },
+	{ 1, UNCORRECTED_ERROR, "lsd_lpc_ras_long_wait_to" },
+	{ 2, UNCORRECTED_ERROR, "lsd_lpc_ras_short_wait_to" },
+	{ 3, UNCORRECTED_ERROR, "lsd_lpc_ras_sync_err" },
+	{ 4, UNCORRECTED_ERROR, "lsd_lbc_ras_err" },
+	{ 5, UNCORRECTED_ERROR, "usb3_err_0" },
+	{ 6, UNCORRECTED_ERROR, "usb3_err_1" },
+	{ 7, UNCORRECTED_ERROR, "gsd_gmu_mac0_asf_nonfatal_int" },
+	{ 8, UNCORRECTED_ERROR, "gsd_gmu_mac0_asf_fatal_int" },
+	{ 9, UNCORRECTED_ERROR, "gsd_gmu_mac0_asf_trans_to_err" },
+	{ 10, UNCORRECTED_ERROR, "gsd_gmu_mac0_asf_protocol_err" },
+	{ 11, UNCORRECTED_ERROR, "gsd_gmu_mac1_asf_nonfatal_int" },
+	{ 12, UNCORRECTED_ERROR, "gsd_gmu_mac1_asf_fatal_int" },
+	{ 13, UNCORRECTED_ERROR, "gsd_gmu_mac1_asf_trans_to_err" },
+	{ 14, UNCORRECTED_ERROR, "gsd_gmu_mac1_asf_protocol_err" },
+	{ 15, UNCORRECTED_ERROR, "gsd_gmu_mac2_asf_nonfatal_int" },
+	{ 16, UNCORRECTED_ERROR, "gsd_gmu_mac2_asf_fatal_int" },
+	{ 17, UNCORRECTED_ERROR, "gsd_gmu_mac2_asf_trans_to_err" },
+	{ 18, UNCORRECTED_ERROR, "gsd_gmu_mac2_asf_protocol_err" },
+	{ 19, UNCORRECTED_ERROR, "gsd_gmu_mac3_asf_nonfatal_int" },
+	{ 20, UNCORRECTED_ERROR, "gsd_gmu_mac3_asf_fatal_int" },
+	{ 21, UNCORRECTED_ERROR, "gsd_gmu_mac3_asf_trans_to_err" },
+	{ 22, UNCORRECTED_ERROR, "gsd_gmu_mac3_asf_protocol_err" },
+	{ 23, CORRECTED_ERROR, "dmu_ras_ecc_corrected_error" },
+	{ 24, UNCORRECTED_ERROR, "dmu_ras_ecc_uncorrected_error" },
+	{ 25, UNCORRECTED_ERROR, "cci_ras_nERRIRQ" },
+	{ 26, UNCORRECTED_ERROR, "smmu_tcu_ras_irpt" },
+	{ 27, UNCORRECTED_ERROR, "smmu_tbu0_ras_irpt" },
+	{ 28, UNCORRECTED_ERROR, "smmu_tbu1_ras_irpt" },
+	{ 29, UNCORRECTED_ERROR, "smmu_tbu2_ras_irpt" },
+	{ 30, UNCORRECTED_ERROR, "ocm_sram_ue" },
+	{ 31, CORRECTED_ERROR, "ocm_sram_ce" },
+	{ 32, UNCORRECTED_ERROR, "int_axim_err" },
+	{ 33, UNCORRECTED_ERROR, "int_fatal_error" },
+	{ 34, UNCORRECTED_ERROR, "nEXTERRIRQ_clust0" },
+	{ 35, UNCORRECTED_ERROR, "nINTERRIRQ_clust0" },
+	{ 36, UNCORRECTED_ERROR, "nEXTERRIRQ_clust1" },
+	{ 37, UNCORRECTED_ERROR, "nINTERRIRQ_clust1" },
+	{ 38, UNCORRECTED_ERROR, "nEXTERRIRQ_clust2" },
+	{ 39, UNCORRECTED_ERROR, "nINTERRIRQ_clust2" },
+	{ 40, UNCORRECTED_ERROR, "ams_ame0_ras_err" },
+	{ 41, UNCORRECTED_ERROR, "ams_ame1_ras_err" },
+	{ 42, UNCORRECTED_ERROR, "ams_amer_ras_err" },
+	{ 43, UNCORRECTED_ERROR, "ras_err_ame1" },
+};
+
+/* pcie controller error record */
+static const struct ras_error_info pe220x_ras_peu_psu_error[] = {
+	{ 0, CORRECTED_ERROR, "pio_rd_addr_error" },
+	{ 1, UNCORRECTED_ERROR, "pio_wr_addr_error" },
+	{ 2, CORRECTED_ERROR, "pio_rd_timeout" },
+	{ 3, CORRECTED_ERROR, "pio_wr_timeout" },
+	{ 4, CORRECTED_ERROR, "axi_b_rsp_error" },
+	{ 5, CORRECTED_ERROR, "axi_r_rsp_error" },
+};
+
+static const struct ras_error_info pe220x_ras_peu_error[] = {
+	{ 0, CORRECTED_ERROR, "pio_rd_addr_error" },
+	{ 1, UNCORRECTED_ERROR, "pio_wr_addr_error" },
+	{ 2, CORRECTED_ERROR, "pio_rd_timeout" },
+	{ 3, CORRECTED_ERROR, "pio_wr_timeout" },
+	{ 4, CORRECTED_ERROR, "axi_b_rsp_error" },
+	{ 5, CORRECTED_ERROR, "axi_r_rsp_error" },
+};
+
+static const struct ras_error_info *pe220x_ras_error[] = {
+	pe220x_ras_soc_error, pe220x_ras_peu_psu_error, pe220x_ras_peu_error
+};
+
+static inline unsigned int get_error_num(const struct phytium_edac *edac,
+					int err_group)
+{
+	unsigned int error_num = 0;
+
+	error_num = readl(edac->ras_base[err_group] + ERR_DEVID);
+
+	return error_num;
+}
+
+static inline void phytium_ras_setup(const struct phytium_edac *edac)
+{
+	u64 val = 0;
+	unsigned int i = 0;
+	/*
+	 * enable error report and generate interrupt for corrected error event
+	 * first error record owned by node present the node configuration
+	 */
+	for (i = 0; i < MAX_ERR_GROUP; i++) {
+		val = readq(edac->ras_base[i] + ERR_CTLR(0));
+		val |= CTLR_ED | CTLR_UI | CTLR_CFI;
+		writeq(val, edac->ras_base[i] + ERR_CTLR(0));
+	}
+}
+
+static ssize_t phytium_edac_inject_ctrl_write(struct file *filp,
+						const char __user *buf,
+						size_t size, loff_t *ppos)
+{
+	int ret = 0;
+	int res = 0;
+	unsigned int error_group = 0;
+	unsigned int error_id = 0;
+	unsigned int error_num = 0;
+	struct phytium_edac *edac = filp->private_data;
+	char str[255];
+	char *p_str = str;
+	char *tmp = NULL;
+
+	if (size > 255) {
+		ret = -EFAULT;
+		goto out;
+	}
+
+	if (copy_from_user(str, buf, size)) {
+		ret = -EFAULT;
+		goto out;
+	} else {
+		*ppos += size;
+		ret = size;
+	}
+	str[size] = '\0';
+
+	tmp = strsep(&p_str, ",");
+	if (!tmp)
+		goto out;
+
+	res = kstrtouint(tmp, 0, &error_group);
+	if (res || error_group >= MAX_ERR_GROUP) {
+		dev_err(edac->dev, "invalid error group parameters");
+		goto out;
+	}
+
+	res = kstrtouint(p_str, 0, &error_id);
+	if (res) {
+		dev_err(edac->dev, "invalid error id parameters");
+		goto out;
+	}
+
+	error_num = get_error_num(edac, error_group);
+	if (error_id >= error_num) {
+		dev_err(edac->dev, "invalid ras error id.\n");
+		goto out;
+	}
+
+	dev_dbg(edac->dev, "inject group%d, error_id: %d\n",
+			error_group, error_id);
+
+	if (pe220x_ras_error[error_group][error_id].error_type ==
+			CORRECTED_ERROR) {
+		writeq(MISC0_CEC(0xFF),
+			edac->ras_base[error_group] + ERR_MISC0(error_id));
+	}
+
+	writel(error_id, edac->ras_base[error_group] + ERR_INJECT);
+
+out:
+	return ret;
+}
+
+static const struct file_operations phytium_edac_debug_inject_fops[] = {
+	{
+	.open = simple_open,
+	.write = phytium_edac_inject_ctrl_write,
+	.llseek = generic_file_llseek, },
+	{ }
+};
+
+static void phytium_edac_create_debugfs_nodes(struct phytium_edac *edac)
+{
+	if (!IS_ENABLED(CONFIG_EDAC_DEBUG) || !edac->dfs) {
+		dev_info(edac->dev, "edac debug is disable");
+		return;
+	}
+
+	edac_debugfs_create_file("error_inject_ctrl", S_IWUSR, edac->dfs, edac,
+				 &phytium_edac_debug_inject_fops[0]);
+}
+
+static int phytium_edac_device_add(struct phytium_edac *edac)
+{
+	struct edac_device_ctl_info *edac_dev;
+	int res = 0;
+
+	edac_dev = edac_device_alloc_ctl_info(
+			sizeof(struct edac_device_ctl_info),
+			"ras", 1, "soc", 1, 0, NULL,
+			0, edac_device_alloc_index());
+	if (!edac_dev)
+		res = -ENOMEM;
+
+	edac_dev->dev = edac->dev;
+	edac_dev->mod_name = EDAC_MOD_STR;
+	edac_dev->ctl_name = "phytium ras";
+	edac_dev->dev_name = "soc";
+
+	phytium_edac_create_debugfs_nodes(edac);
+
+	res = edac_device_add_device(edac_dev);
+	if (res > 0) {
+		dev_err(edac->dev, "edac_device_add_device failed\n");
+		goto err_free;
+	}
+
+	edac->edac_dev = edac_dev;
+	dev_info(edac->dev, "phytium edac device registered\n");
+	return 0;
+
+err_free:
+	edac_device_free_ctl_info(edac_dev);
+	return res;
+}
+
+static int phytium_edac_device_remove(struct phytium_edac *edac)
+{
+	struct edac_device_ctl_info *edac_dev = edac->edac_dev;
+
+	debugfs_remove_recursive(edac->dfs);
+	edac_device_del_device(edac_dev->dev);
+	edac_device_free_ctl_info(edac_dev);
+	return 0;
+}
+
+static int get_error_id(struct phytium_edac *edac, int *error_id,
+						int *error_group)
+{
+	unsigned int error_num = 0;
+	u64 error_bit = 0;
+	int ret = 0;
+	int i = 0;
+	int err_id = 0;
+
+	/* Iterate over the ras node to check error status */
+	for (i = 0; i < MAX_ERR_GROUP; i++) {
+		error_num = get_error_num(edac, i);
+		error_bit = readq(edac->ras_base[i] + ERR_GSR);
+		for (err_id = 0; err_id < error_num; err_id++) {
+			if (!(error_bit & BIT(err_id)))
+				continue;
+			else
+				break;
+		}
+		if (err_id < error_num) {
+			*error_id = err_id;
+			*error_group = i;
+			break;
+		}
+	}
+
+	if (i >= MAX_ERR_GROUP) {
+		ret = -1;
+		dev_warn(edac->dev, "no error detect.\n");
+	}
+
+	return ret;
+}
+
+static void phytium_edac_error_report(struct phytium_edac *edac,
+				const int error_id,
+				const int error_group)
+{
+	const struct ras_error_info *err_info =
+		pe220x_ras_error[error_group];
+
+	if (err_info[error_id].error_type == UNCORRECTED_ERROR) {
+		edac_printk(KERN_CRIT, EDAC_MOD_STR, "uncorrected error: %s\n",
+			err_info[error_id].error_str);
+		edac_device_handle_ue(edac->edac_dev, 0, 0,
+				err_info[error_id].error_str);
+		/* Report the error via the trace interface */
+		if (IS_ENABLED(CONFIG_RAS))
+			trace_non_standard_event(&NULL_UUID_LE, &NULL_UUID_LE,
+					EDAC_MOD_STR, SEV_RECOVERABLE,
+					err_info[error_id].error_str,
+					strlen(err_info[error_id].error_str));
+	} else {
+		edac_printk(KERN_CRIT, EDAC_MOD_STR, "corrected error: %s\n",
+			err_info[error_id].error_str);
+		edac_device_handle_ce(edac->edac_dev, 0, 0,
+				err_info[error_id].error_str);
+		/* Report the error via the trace interface */
+		if (IS_ENABLED(CONFIG_RAS))
+			trace_non_standard_event(&NULL_UUID_LE, &NULL_UUID_LE,
+					EDAC_MOD_STR, SEV_CORRECTED,
+					err_info[error_id].error_str,
+					strlen(err_info[error_id].error_str));
+	}
+}
+
+/*
+ * clear error status and set correct error counter to 0xFE for trigger
+ * interrupt when next correct error event
+ */
+static void phytium_edac_clear_error_status(struct phytium_edac *edac,
+					const int error_id,
+					const int error_group)
+{
+	writeq(MISC0_CEC(0XFE), edac->ras_base[error_group] +
+			ERR_MISC0(error_id));
+	writeq(GENMASK(31, 0), edac->ras_base[error_group] +
+			ERR_STATUS(error_id));
+}
+
+static irqreturn_t phytium_edac_isr(int irq, void *dev_id)
+{
+	struct phytium_edac *edac = dev_id;
+	int ret = 0;
+	int error_group;
+	int error_id;
+
+	ret = get_error_id(edac, &error_id, &error_group);
+	if (ret < 0)
+		goto out;
+
+	phytium_edac_error_report(edac, error_id, error_group);
+	phytium_edac_clear_error_status(edac, error_id, error_group);
+
+out:
+	return IRQ_HANDLED;
+}
+
+static int phytium_edac_probe(struct platform_device *pdev)
+{
+	struct phytium_edac *edac;
+	struct resource *res;
+	int ret = 0;
+	int irq_cnt = 0;
+	int irq = 0;
+	int i = 0;
+
+	edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
+	if (!edac) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	edac->dev = &pdev->dev;
+	platform_set_drvdata(pdev, edac);
+
+	edac->ras_base = devm_kcalloc(&pdev->dev, 3,
+				sizeof(*edac->ras_base), GFP_KERNEL);
+	if (!edac->ras_base) {
+		return -ENOMEM;
+		goto out;
+	}
+
+	for (i = 0; i < MAX_ERR_GROUP; i++) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+		edac->ras_base[i] = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(edac->ras_base[i])) {
+			dev_err(&pdev->dev, "no resource address\n");
+			ret = PTR_ERR(edac->ras_base[i]);
+			goto out;
+		}
+	}
+
+	edac->dfs = edac_debugfs_create_dir(EDAC_MOD_STR);
+
+	ret = phytium_edac_device_add(edac);
+	if (ret) {
+		dev_err(&pdev->dev, "can't add edac device");
+		goto out;
+	}
+
+	phytium_ras_setup(edac);
+
+	irq_cnt = platform_irq_count(pdev);
+	if (irq_cnt < 0) {
+		dev_err(&pdev->dev, "no irq resource\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	for (i = 0; i < irq_cnt; i++) {
+		irq = platform_get_irq(pdev, i);
+		if (irq < 0) {
+			dev_err(&pdev->dev, "invalid irq resource\n");
+			ret = -EINVAL;
+			goto out;
+		}
+		ret = devm_request_irq(&pdev->dev, irq,
+					  phytium_edac_isr, IRQF_SHARED,
+					  EDAC_MOD_STR, edac);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"could not request irq %d\n", irq);
+			goto out;
+		}
+	}
+
+out:
+	return ret;
+}
+
+static int phytium_edac_remove(struct platform_device *pdev)
+{
+	struct phytium_edac *edac = dev_get_drvdata(&pdev->dev);
+
+	phytium_edac_device_remove(edac);
+
+	return 0;
+}
+
+static const struct of_device_id phytium_edac_of_match[] = {
+	{ .compatible = "phytium,pe220x-edac" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, phytium_edac_of_match);
+
+static struct platform_driver phytium_edac_driver = {
+	.probe = phytium_edac_probe,
+	.remove = phytium_edac_remove,
+	.driver = {
+		.name = "phytium-edac",
+		.of_match_table = phytium_edac_of_match,
+	},
+};
+
+module_platform_driver(phytium_edac_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Huangjie <huangjie1663@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium Pe220x EDAC driver");
diff --git a/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-core.c b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-core.c
new file mode 100644
index 00000000000000..648e564dffc0e9
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-core.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+
+#include "gpio-phytium-core.h"
+
+static int get_pin_location(struct phytium_gpio *gpio, unsigned int offset,
+		     struct pin_loc *pl)
+{
+	int ret;
+
+	if (offset < gpio->ngpio[0]) {
+		pl->port = 0;
+		pl->offset = offset;
+		ret = 0;
+	} else if (offset < (gpio->ngpio[0] + gpio->ngpio[1])) {
+		pl->port = 1;
+		pl->offset = offset - gpio->ngpio[0];
+		ret = 0;
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void phytium_gpio_toggle_trigger(struct phytium_gpio *gpio,
+				 unsigned int offset)
+{
+	struct gpio_chip *gc;
+	u32 pol;
+	int val;
+
+	/* Only port A can provide interrupt source */
+	if (offset >= gpio->ngpio[0])
+		return;
+
+	gc = &gpio->gc;
+
+	pol = readl(gpio->regs + GPIO_INT_POLARITY);
+	/* Just read the current value right out of the data register */
+	val = gc->get(gc, offset);
+	if (val)
+		pol &= ~BIT(offset);
+	else
+		pol |= BIT(offset);
+
+	writel(pol, gpio->regs + GPIO_INT_POLARITY);
+}
+
+int phytium_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct pin_loc loc;
+	void __iomem *dat;
+
+	if (get_pin_location(gpio, offset, &loc))
+		return -EINVAL;
+
+	dat = gpio->regs + GPIO_EXT_PORTA + (loc.port * GPIO_PORT_STRIDE);
+
+	return !!(readl(dat) & BIT(loc.offset));
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_get);
+
+void phytium_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct pin_loc loc;
+	void __iomem *dr;
+	unsigned long flags;
+	u32 mask;
+
+	if (get_pin_location(gpio, offset, &loc))
+		return;
+	dr = gpio->regs + GPIO_SWPORTA_DR + (loc.port * GPIO_PORT_STRIDE);
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	if (value)
+		mask = readl(dr) | BIT(loc.offset);
+	else
+		mask = readl(dr) & ~BIT(loc.offset);
+
+	writel(mask, dr);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_set);
+
+int phytium_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct pin_loc loc;
+	unsigned long flags;
+	void __iomem *ddr;
+
+	if (get_pin_location(gpio, offset, &loc))
+		return -EINVAL;
+	ddr = gpio->regs + GPIO_SWPORTA_DDR + (loc.port * GPIO_PORT_STRIDE);
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	writel(readl(ddr) & ~(BIT(loc.offset)), ddr);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_direction_input);
+
+int phytium_gpio_direction_output(struct gpio_chip *gc, unsigned int offset,
+				  int value)
+{
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct pin_loc loc;
+	unsigned long flags;
+	void __iomem *ddr;
+
+	if (get_pin_location(gpio, offset, &loc))
+		return -EINVAL;
+	ddr = gpio->regs + GPIO_SWPORTA_DDR + (loc.port * GPIO_PORT_STRIDE);
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	writel(readl(ddr) | BIT(loc.offset), ddr);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	phytium_gpio_set(gc, offset, value);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_direction_output);
+
+void phytium_gpio_irq_ack(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	u32 val = BIT(irqd_to_hwirq(d));
+
+	raw_spin_lock(&gpio->lock);
+
+	writel(val, gpio->regs + GPIO_PORTA_EOI);
+
+	raw_spin_unlock(&gpio->lock);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_ack);
+
+void phytium_gpio_irq_mask(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	u32 val;
+
+	/* Only port A can provide interrupt source */
+	if (irqd_to_hwirq(d) >= gpio->ngpio[0])
+		return;
+
+	raw_spin_lock(&gpio->lock);
+
+	val = readl(gpio->regs + GPIO_INTMASK);
+	val |= BIT(irqd_to_hwirq(d));
+	writel(val, gpio->regs + GPIO_INTMASK);
+
+	raw_spin_unlock(&gpio->lock);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_mask);
+
+void phytium_gpio_irq_unmask(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	u32 val;
+
+	/* Only port A can provide interrupt source */
+	if (irqd_to_hwirq(d) >= gpio->ngpio[0])
+		return;
+
+	raw_spin_lock(&gpio->lock);
+
+	val = readl(gpio->regs + GPIO_INTMASK);
+	val &= ~BIT(irqd_to_hwirq(d));
+	writel(val, gpio->regs + GPIO_INTMASK);
+
+	raw_spin_unlock(&gpio->lock);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_unmask);
+
+int phytium_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	int hwirq = irqd_to_hwirq(d);
+	unsigned long flags, lvl, pol;
+
+	if (hwirq < 0 || hwirq >= gpio->ngpio[0])
+		return -EINVAL;
+
+	if ((flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
+	    (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
+		dev_err(gc->parent,
+			"trying to configure line %d for both level and edge detection, choose one!\n",
+			hwirq);
+		return -EINVAL;
+	}
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	lvl = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
+	pol = readl(gpio->regs + GPIO_INT_POLARITY);
+
+	switch (flow_type) {
+	case IRQ_TYPE_EDGE_BOTH:
+		lvl |= BIT(hwirq);
+		phytium_gpio_toggle_trigger(gpio, hwirq);
+		irq_set_handler_locked(d, handle_edge_irq);
+		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", hwirq);
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		lvl |= BIT(hwirq);
+		pol |= BIT(hwirq);
+		irq_set_handler_locked(d, handle_edge_irq);
+		dev_dbg(gc->parent, "line %d: IRQ on RISING edge\n", hwirq);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		lvl |= BIT(hwirq);
+		pol &= ~BIT(hwirq);
+		irq_set_handler_locked(d, handle_edge_irq);
+		dev_dbg(gc->parent, "line %d: IRQ on FALLING edge\n", hwirq);
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		lvl &= ~BIT(hwirq);
+		pol |= BIT(hwirq);
+		irq_set_handler_locked(d, handle_level_irq);
+		dev_dbg(gc->parent, "line %d: IRQ on HIGH level\n", hwirq);
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		lvl &= ~BIT(hwirq);
+		pol &= ~BIT(hwirq);
+		irq_set_handler_locked(d, handle_level_irq);
+		dev_dbg(gc->parent, "line %d: IRQ on LOW level\n", hwirq);
+		break;
+	}
+
+	writel(lvl, gpio->regs + GPIO_INTTYPE_LEVEL);
+	if (flow_type != IRQ_TYPE_EDGE_BOTH)
+		writel(pol, gpio->regs + GPIO_INT_POLARITY);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_set_type);
+
+void phytium_gpio_irq_enable(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	unsigned long flags;
+	u32 val;
+
+	/* Only port A can provide interrupt source */
+	if (irqd_to_hwirq(d) >= gpio->ngpio[0])
+		return;
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	val = readl(gpio->regs + GPIO_INTEN);
+	val |= BIT(irqd_to_hwirq(d));
+	writel(val, gpio->regs + GPIO_INTEN);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_enable);
+
+void phytium_gpio_irq_disable(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	unsigned long flags;
+	u32 val;
+
+	/* Only port A can provide interrupt source */
+	if (irqd_to_hwirq(d) >= gpio->ngpio[0])
+		return;
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	val = readl(gpio->regs + GPIO_INTEN);
+	val &= ~BIT(irqd_to_hwirq(d));
+	writel(val, gpio->regs + GPIO_INTEN);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_disable);
+
+void phytium_gpio_irq_handler(struct irq_desc *desc)
+{
+	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct irq_chip *irqchip = irq_desc_get_chip(desc);
+	unsigned long pending;
+	int offset;
+
+	chained_irq_enter(irqchip, desc);
+
+	pending = readl(gpio->regs + GPIO_INTSTATUS);
+	if (pending) {
+		for_each_set_bit(offset, &pending, gpio->ngpio[0]) {
+			int gpio_irq = irq_find_mapping(gc->irq.domain,
+							offset);
+			generic_handle_irq(gpio_irq);
+
+			if ((irq_get_trigger_type(gpio_irq) &
+			    IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+				phytium_gpio_toggle_trigger(gpio, offset);
+		}
+	}
+
+	chained_irq_exit(irqchip, desc);
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_handler);
+
+int phytium_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct pin_loc loc;
+	void __iomem *ddr;
+
+	if (get_pin_location(gpio, offset, &loc))
+		return -EINVAL;
+	ddr = gpio->regs + GPIO_SWPORTA_DDR + (loc.port * GPIO_PORT_STRIDE);
+
+	return !(readl(ddr) & BIT(loc.offset));
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_get_direction);
+
+#if CONFIG_SMP
+int
+phytium_gpio_irq_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force)
+{
+	struct gpio_chip *chip_data = irq_data_get_irq_chip_data(d);
+	struct irq_chip *chip = irq_get_chip(*(chip_data->irq.parents));
+	struct irq_data *data = irq_get_irq_data(*(chip_data->irq.parents));
+
+	if (chip && chip->irq_set_affinity)
+		return chip->irq_set_affinity(data, mask_val, force);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_set_affinity);
+#endif
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium GPIO Controller core");
diff --git a/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-core.h b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-core.h
new file mode 100644
index 00000000000000..cafca7807e2782
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-core.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef _GPIO_PHYTIUM_H
+#define _GPIO_PHYTIUM_H
+
+#include <linux/gpio/driver.h>
+#include <linux/spinlock.h>
+
+#include "gpiolib.h"
+
+#define GPIO_SWPORTA_DR		0x00 /* WR Port A Output Data Register */
+#define GPIO_SWPORTA_DDR	0x04 /* WR Port A Data Direction Register */
+#define GPIO_EXT_PORTA		0x08 /* RO Port A Input Data Register */
+#define GPIO_SWPORTB_DR		0x0c /* WR Port B Output Data Register */
+#define GPIO_SWPORTB_DDR	0x10 /* WR Port B Data Direction Register */
+#define GPIO_EXT_PORTB		0x14 /* RO Port B Input Data Register */
+
+#define GPIO_INTEN		0x18 /* WR Port A Interrput Enable Register */
+#define GPIO_INTMASK		0x1c /* WR Port A Interrupt Mask Register */
+#define GPIO_INTTYPE_LEVEL	0x20 /* WR Port A Interrupt Level Register */
+#define GPIO_INT_POLARITY	0x24 /* WR Port A Interrupt Polarity Register */
+#define GPIO_INTSTATUS		0x28 /* RO Port A Interrupt Status Register */
+#define GPIO_RAW_INTSTATUS	0x2c /* RO Port A Raw Interrupt Status Register */
+#define GPIO_LS_SYNC		0x30 /* WR Level-sensitive Synchronization Enable Register */
+#define GPIO_DEBOUNCE		0x34 /* WR Debounce Enable Register */
+#define GPIO_PORTA_EOI		0x38 /* WO Port A Clear Interrupt Register */
+
+#define MAX_NPORTS		2
+#define NGPIO_DEFAULT		8
+#define NGPIO_MAX		32
+#define GPIO_PORT_STRIDE	(GPIO_EXT_PORTB - GPIO_EXT_PORTA)
+
+struct pin_loc {
+	unsigned int port;
+	unsigned int offset;
+};
+
+#ifdef CONFIG_PM_SLEEP
+struct phytium_gpio_ctx {
+	u32 swporta_dr;
+	u32 swporta_ddr;
+	u32 ext_porta;
+	u32 swportb_dr;
+	u32 swportb_ddr;
+	u32 ext_portb;
+	u32 inten;
+	u32 intmask;
+	u32 inttype_level;
+	u32 int_polarity;
+	u32 intstatus;
+	u32 raw_intstatus;
+	u32 ls_sync;
+	u32 debounce;
+};
+#endif
+
+struct phytium_gpio {
+	raw_spinlock_t		lock;
+	void __iomem		*regs;
+	struct gpio_chip	gc;
+	struct irq_chip		irq_chip;
+	unsigned int		ngpio[2];
+	int			irq[32];
+#ifdef CONFIG_PM_SLEEP
+	struct phytium_gpio_ctx	ctx;
+#endif
+};
+
+int phytium_gpio_get(struct gpio_chip *gc, unsigned int offset);
+void phytium_gpio_set(struct gpio_chip *gc, unsigned int offset, int value);
+
+int phytium_gpio_get_direction(struct gpio_chip *gc, unsigned int offset);
+int phytium_gpio_direction_input(struct gpio_chip *gc, unsigned int offset);
+int phytium_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value);
+
+void phytium_gpio_irq_ack(struct irq_data *d);
+void phytium_gpio_irq_mask(struct irq_data *d);
+void phytium_gpio_irq_unmask(struct irq_data *d);
+int phytium_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type);
+void phytium_gpio_irq_enable(struct irq_data *d);
+void phytium_gpio_irq_disable(struct irq_data *d);
+void phytium_gpio_irq_handler(struct irq_desc *desc);
+int phytium_gpio_irq_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force);
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-pci.c b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-pci.c
new file mode 100644
index 00000000000000..60563c59ae6028
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-pci.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include "gpio-phytium-core.h"
+
+static int phytium_gpio_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct device *dev = &pdev->dev;
+	struct phytium_gpio *gpio;
+	struct gpio_irq_chip *girq;
+	int err;
+
+	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+	if (!gpio)
+		return -ENOMEM;
+
+	err = pcim_enable_device(pdev);
+	if (err) {
+		dev_err(dev, "Failed to enable PCI device: err %d\n", err);
+		goto out;
+	}
+
+	err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
+	if (err) {
+		dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
+		goto out;
+	}
+
+	gpio->regs = pcim_iomap_table(pdev)[0];
+	if (!gpio->regs) {
+		dev_err(dev, "Cannot map PCI resource\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	err = pci_enable_msi(pdev);
+	if (err < 0)
+		goto out;
+
+	pci_set_master(pdev);
+
+	gpio->irq[0] = pdev->irq;
+	if (gpio->irq[0] < 0)
+		dev_warn(dev, "no irq is found.\n");
+
+	/* There is only one group of Pins at the moment. */
+	gpio->ngpio[0] = NGPIO_MAX;
+
+	/* irq_chip support */
+	gpio->irq_chip.name = dev_name(dev);
+	gpio->irq_chip.irq_ack = phytium_gpio_irq_ack;
+	gpio->irq_chip.irq_mask = phytium_gpio_irq_mask;
+	gpio->irq_chip.irq_unmask = phytium_gpio_irq_unmask;
+	gpio->irq_chip.irq_set_type = phytium_gpio_irq_set_type;
+	gpio->irq_chip.irq_enable = phytium_gpio_irq_enable;
+	gpio->irq_chip.irq_disable = phytium_gpio_irq_disable;
+
+	raw_spin_lock_init(&gpio->lock);
+
+	gpio->gc.base = -1;
+	gpio->gc.get_direction = phytium_gpio_get_direction;
+	gpio->gc.direction_input = phytium_gpio_direction_input;
+	gpio->gc.direction_output = phytium_gpio_direction_output;
+	gpio->gc.get = phytium_gpio_get;
+	gpio->gc.set = phytium_gpio_set;
+	gpio->gc.ngpio = gpio->ngpio[0] + gpio->ngpio[1];
+	gpio->gc.label = dev_name(dev);
+	gpio->gc.parent = dev;
+	gpio->gc.owner = THIS_MODULE;
+
+	girq = &gpio->gc.irq;
+	girq->handler = handle_bad_irq;
+	girq->default_type = IRQ_TYPE_NONE;
+
+	girq->num_parents = 1;
+	girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
+				     sizeof(*girq->parents), GFP_KERNEL);
+	if (!girq->parents)
+		return -ENOMEM;
+	girq->parents[0] = gpio->irq[0];
+	girq->parent_handler = phytium_gpio_irq_handler;
+
+	girq->chip = &gpio->irq_chip;
+
+	err = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
+	if (err)
+		goto out;
+
+	dev_info(dev, "Phytium PCI GPIO controller @%pa registered\n",
+		&gpio->regs);
+
+	pci_set_drvdata(pdev, gpio);
+
+out:
+	return err;
+}
+
+static const struct pci_device_id phytium_gpio_pci_ids[] = {
+	{ PCI_DEVICE(0x1DB7, 0xDC31) },
+	{ 0 }
+};
+MODULE_DEVICE_TABLE(pci, phytium_gpio_pci_ids);
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_gpio_pci_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct phytium_gpio *gpio = pci_get_drvdata(pdev);
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	gpio->ctx.swporta_dr = readl(gpio->regs + GPIO_SWPORTA_DR);
+	gpio->ctx.swporta_ddr = readl(gpio->regs + GPIO_SWPORTA_DDR);
+	gpio->ctx.ext_porta = readl(gpio->regs + GPIO_EXT_PORTA);
+	gpio->ctx.swportb_dr = readl(gpio->regs + GPIO_SWPORTB_DR);
+	gpio->ctx.swportb_ddr = readl(gpio->regs + GPIO_SWPORTB_DDR);
+	gpio->ctx.ext_portb = readl(gpio->regs + GPIO_EXT_PORTB);
+
+	gpio->ctx.inten = readl(gpio->regs + GPIO_INTEN);
+	gpio->ctx.intmask = readl(gpio->regs + GPIO_INTMASK);
+	gpio->ctx.inttype_level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
+	gpio->ctx.int_polarity = readl(gpio->regs + GPIO_INT_POLARITY);
+	gpio->ctx.debounce = readl(gpio->regs + GPIO_DEBOUNCE);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+
+static int phytium_gpio_pci_resume(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct phytium_gpio *gpio = pci_get_drvdata(pdev);
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	writel(gpio->ctx.swporta_dr, gpio->regs + GPIO_SWPORTA_DR);
+	writel(gpio->ctx.swporta_ddr, gpio->regs + GPIO_SWPORTA_DDR);
+	writel(gpio->ctx.ext_porta, gpio->regs + GPIO_EXT_PORTA);
+	writel(gpio->ctx.swportb_dr, gpio->regs + GPIO_SWPORTB_DR);
+	writel(gpio->ctx.swportb_ddr, gpio->regs + GPIO_SWPORTB_DDR);
+	writel(gpio->ctx.ext_portb, gpio->regs + GPIO_EXT_PORTB);
+
+	writel(gpio->ctx.inten, gpio->regs + GPIO_INTEN);
+	writel(gpio->ctx.intmask, gpio->regs + GPIO_INTMASK);
+	writel(gpio->ctx.inttype_level, gpio->regs + GPIO_INTTYPE_LEVEL);
+	writel(gpio->ctx.int_polarity, gpio->regs + GPIO_INT_POLARITY);
+	writel(gpio->ctx.debounce, gpio->regs + GPIO_DEBOUNCE);
+
+	writel(0xffffffff, gpio->regs + GPIO_PORTA_EOI);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_gpio_pci_pm_ops,
+			 phytium_gpio_pci_suspend,
+			 phytium_gpio_pci_resume);
+
+static struct pci_driver phytium_gpio_pci_driver = {
+	.name		= "gpio-phytium-pci",
+	.id_table	= phytium_gpio_pci_ids,
+	.probe		= phytium_gpio_pci_probe,
+	.driver		= {
+		.pm	= &phytium_gpio_pci_pm_ops,
+	},
+};
+
+module_pci_driver(phytium_gpio_pci_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium GPIO PCI Driver");
diff --git a/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-platform.c b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-platform.c
new file mode 100644
index 00000000000000..0d77eb885249e4
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-platform.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support functions for Phytium GPIO
+ *
+ * Copyright (c) 2019-2023 Phytium Technology Co., Ltd.
+ *
+ * Derived from drivers/gpio/gpio-pl061.c
+ *   Copyright (C) 2008, 2009 Provigent Ltd.
+ */
+
+#include <linux/acpi.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#include "gpio-phytium-core.h"
+
+static const struct of_device_id phytium_gpio_of_match[] = {
+	{ .compatible = "phytium,gpio", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_gpio_of_match);
+
+static const struct acpi_device_id phytium_gpio_acpi_match[] = {
+	{ "PHYT0001", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, phytium_gpio_acpi_match);
+
+static int phytium_gpio_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phytium_gpio *gpio;
+	struct gpio_irq_chip *girq;
+	struct fwnode_handle *fwnode;
+	int err, irq_count;
+
+	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+	if (!gpio)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(gpio->regs))
+		return PTR_ERR(gpio->regs);
+
+	if (!device_get_child_node_count(dev))
+		return -ENODEV;
+
+	device_for_each_child_node(dev, fwnode) {
+		int idx;
+
+		if (fwnode_property_read_u32(fwnode, "reg", &idx) ||
+		    idx >= MAX_NPORTS) {
+			dev_err(dev, "missing/invalid port index\n");
+			fwnode_handle_put(fwnode);
+			return -EINVAL;
+		}
+
+		if (fwnode_property_read_u32(fwnode, "ngpios", &gpio->ngpio[idx]) &&
+			fwnode_property_read_u32(fwnode, "nr-gpios", &gpio->ngpio[idx])) {
+			dev_info(dev,
+				 "failed to get number of gpios for Port%c\n",
+				 idx ? 'B' : 'A');
+			gpio->ngpio[idx] = NGPIO_DEFAULT;
+		}
+	}
+
+	/* irq_chip support */
+	gpio->irq_chip.name = dev_name(dev);
+	gpio->irq_chip.irq_ack = phytium_gpio_irq_ack;
+	gpio->irq_chip.irq_mask = phytium_gpio_irq_mask;
+	gpio->irq_chip.irq_unmask = phytium_gpio_irq_unmask;
+	gpio->irq_chip.irq_set_type = phytium_gpio_irq_set_type;
+	gpio->irq_chip.irq_enable = phytium_gpio_irq_enable;
+	gpio->irq_chip.irq_disable = phytium_gpio_irq_disable;
+#ifdef CONFIG_SMP
+	/* TODO: use irq_chip_set_affinity_parent instead? */
+	gpio->irq_chip.irq_set_affinity = phytium_gpio_irq_set_affinity;
+#endif
+	raw_spin_lock_init(&gpio->lock);
+
+	gpio->gc.base = -1;
+	gpio->gc.get_direction = phytium_gpio_get_direction;
+	gpio->gc.direction_input = phytium_gpio_direction_input;
+	gpio->gc.direction_output = phytium_gpio_direction_output;
+	gpio->gc.get = phytium_gpio_get;
+	gpio->gc.set = phytium_gpio_set;
+	gpio->gc.ngpio = gpio->ngpio[0] + gpio->ngpio[1];
+	gpio->gc.label = dev_name(dev);
+	gpio->gc.parent = dev;
+	gpio->gc.owner = THIS_MODULE;
+
+	girq = &gpio->gc.irq;
+	girq->handler = handle_bad_irq;
+	girq->default_type = IRQ_TYPE_NONE;
+
+	for (irq_count = 0; irq_count < platform_irq_count(pdev); irq_count++) {
+		gpio->irq[irq_count] = -ENXIO;
+		gpio->irq[irq_count] = platform_get_irq(pdev, irq_count);
+		if (gpio->irq[irq_count] < 0) {
+			//dev_warn(dev, "no irq is found.\n");
+			break;
+		}
+	};
+
+	girq->num_parents = irq_count;
+	girq->parents = gpio->irq;
+	girq->parent_handler = phytium_gpio_irq_handler;
+
+	girq->chip = &gpio->irq_chip;
+
+	err = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
+	if (err)
+		return err;
+
+	platform_set_drvdata(pdev, gpio);
+	dev_info(dev, "Phytium GPIO controller @%pa registered\n",
+		&res->start);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_gpio_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct phytium_gpio *gpio = platform_get_drvdata(pdev);
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	gpio->ctx.swporta_dr = readl(gpio->regs + GPIO_SWPORTA_DR);
+	gpio->ctx.swporta_ddr = readl(gpio->regs + GPIO_SWPORTA_DDR);
+	gpio->ctx.ext_porta = readl(gpio->regs + GPIO_EXT_PORTA);
+	gpio->ctx.swportb_dr = readl(gpio->regs + GPIO_SWPORTB_DR);
+	gpio->ctx.swportb_ddr = readl(gpio->regs + GPIO_SWPORTB_DDR);
+	gpio->ctx.ext_portb = readl(gpio->regs + GPIO_EXT_PORTB);
+
+	gpio->ctx.inten = readl(gpio->regs + GPIO_INTEN);
+	gpio->ctx.intmask = readl(gpio->regs + GPIO_INTMASK);
+	gpio->ctx.inttype_level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
+	gpio->ctx.int_polarity = readl(gpio->regs + GPIO_INT_POLARITY);
+	gpio->ctx.debounce = readl(gpio->regs + GPIO_DEBOUNCE);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+
+static int phytium_gpio_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct phytium_gpio *gpio = platform_get_drvdata(pdev);
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&gpio->lock, flags);
+
+	writel(gpio->ctx.swporta_dr, gpio->regs + GPIO_SWPORTA_DR);
+	writel(gpio->ctx.swporta_ddr, gpio->regs + GPIO_SWPORTA_DDR);
+	writel(gpio->ctx.ext_porta, gpio->regs + GPIO_EXT_PORTA);
+	writel(gpio->ctx.swportb_dr, gpio->regs + GPIO_SWPORTB_DR);
+	writel(gpio->ctx.swportb_ddr, gpio->regs + GPIO_SWPORTB_DDR);
+	writel(gpio->ctx.ext_portb, gpio->regs + GPIO_EXT_PORTB);
+
+	writel(gpio->ctx.inten, gpio->regs + GPIO_INTEN);
+	writel(gpio->ctx.intmask, gpio->regs + GPIO_INTMASK);
+	writel(gpio->ctx.inttype_level, gpio->regs + GPIO_INTTYPE_LEVEL);
+	writel(gpio->ctx.int_polarity, gpio->regs + GPIO_INT_POLARITY);
+	writel(gpio->ctx.debounce, gpio->regs + GPIO_DEBOUNCE);
+
+	writel(0xffffffff, gpio->regs + GPIO_PORTA_EOI);
+
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_gpio_pm_ops, phytium_gpio_suspend,
+			 phytium_gpio_resume);
+
+static struct platform_driver phytium_gpio_driver = {
+	.driver		= {
+		.name	= "gpio-phytium-platform",
+		.pm	= &phytium_gpio_pm_ops,
+		.of_match_table = of_match_ptr(phytium_gpio_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_gpio_acpi_match),
+	},
+	.probe		= phytium_gpio_probe,
+};
+
+module_platform_driver(phytium_gpio_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium GPIO driver");
diff --git a/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-sgpio.c b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-sgpio.c
new file mode 100644
index 00000000000000..689cb10843e681
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpio/gpio-phytium-sgpio.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SGPIO Driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/gpio/driver.h>
+#include <linux/hashtable.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+
+#define SGPIO_CTL0_REG			0x00
+#define  SGPIO_CTL0_REG_ENABLE		BIT(0)
+#define  SGPIO_CTL0_REG_RX_DISABLE	BIT(1)
+#define  SGPIO_CTL0_REG_L3_L0		GENMASK(11, 8)
+#define  SGPIO_CTL0_REG_CLK_DIV_NUM	GENMASK(31, 12)
+#define SGPIO_CTL1_REG			0x04
+#define  SGPIO_CTL1_REG_READY		BIT(0)
+#define  SGPIO_CTL1_REG_W_UPDATA	BIT(1)
+#define  SGPIO_CTL1_REG_OP_MODE		BIT(2)
+#define  SGPIO_CTL1_REG_OP_STATE	BIT(3)
+#define  SGPIO_CTL1_REG_BIT_NUM		GENMASK(14, 8)
+#define  SGPIO_CTL1_REG_INTERVAL_TIMER	GENMASK(31, 16)
+#define SGPIO_SOFT_RESET_REG		0x08
+#define  SGPIO_SOFT_RESET_REG_MASK	BIT(0)
+#define SGPIO_IRQ_REG			0x0c
+#define  SGPIO_IRQ_REG_MASK		BIT(0)
+#define SGPIO_IRQ_M_REG			0x10
+#define  SGPIO_IRQ_M_REG_MASK		BIT(0)
+#define SGPIO_WDATA0_REG		0x14
+#define SGPIO_WDATA_REG(x)		(SGPIO_WDATA0_REG + ((x) == 2 ? 3 : (x))* 4) // 0x14, 0x18, 0x20
+#define SGPIO_RDATA0_REG		0x24
+#define SGPIO_RDATA_REG(x)		(SGPIO_RDATA0_REG + (x) * 4)
+
+#define DEFAULT_L3_L0 0
+
+#define GPIO_GROUP(x)	((x) >> 6)
+#define GPIO_OFFSET(x)	((x) & GENMASK(5, 0))
+#define GPIO_BIT(x)	BIT(GPIO_OFFSET(x) >> 1)
+
+struct phytium_sgpio {
+	struct gpio_chip gc;
+	void __iomem *regs;
+	unsigned int ngpios;
+	struct clk *pclk;
+
+	struct mutex lock;
+	struct completion completion;
+};
+
+static bool phytium_sgpio_is_input(unsigned int offset)
+{
+	return !(offset % 2);
+}
+
+static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
+{
+	struct phytium_sgpio *gpio = gpiochip_get_data(gc);
+	u32 reg;
+	int rc = 0;
+
+	if (phytium_sgpio_is_input(offset))
+		return -EINVAL;
+
+	reinit_completion(&gpio->completion);
+
+	/*
+	 * Since this is an output, read the cached value from rdata,
+	 * then update value.
+	 */
+	/* cached data from wdata? */
+	reg = readl(gpio->regs + SGPIO_WDATA_REG(GPIO_GROUP(offset)));
+	if (val)
+		reg |= GPIO_BIT(offset);
+	else
+		reg &= GPIO_BIT(offset);
+	writel(reg, gpio->regs + SGPIO_WDATA_REG(GPIO_GROUP(offset)));
+
+	/* Start transmission and wait for completion */
+	writel(readl(gpio->regs + SGPIO_CTL1_REG) | SGPIO_CTL1_REG_W_UPDATA,
+	       gpio->regs + SGPIO_CTL1_REG);
+	if (!wait_for_completion_timeout(&gpio->completion, msecs_to_jiffies(1000)))
+		rc = -EINVAL;
+
+	return rc;
+}
+
+static int phytium_sgpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+	return phytium_sgpio_is_input(offset) ? 0 : -EINVAL;
+}
+
+static int phytium_sgpio_direction_output(struct gpio_chip *gc, unsigned int offset, int val)
+{
+	struct phytium_sgpio *gpio = gpiochip_get_data(gc);
+	int rc;
+
+	mutex_lock(&gpio->lock);
+
+	/*
+	 * No special action is required for setting the direction; we'll
+	 * error-out in sgpio_set_value if this isn't an output GPIO
+	 */
+	rc = sgpio_set_value(&gpio->gc, offset, val);
+
+	mutex_unlock(&gpio->lock);
+
+	return rc;
+}
+
+static int phytium_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+	return !!phytium_sgpio_is_input(offset);
+}
+
+static int phytium_sgpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+	struct phytium_sgpio *gpio = gpiochip_get_data(gc);
+	int rc = 0;
+	u32 val, ctl0;
+
+	mutex_lock(&gpio->lock);
+
+	if (!phytium_sgpio_is_input(offset)) {
+		val = readl(gpio->regs + SGPIO_WDATA_REG(GPIO_GROUP(offset)));
+		rc = !!(val & GPIO_BIT(offset));
+		mutex_unlock(&gpio->lock);
+		return rc;
+	}
+
+	reinit_completion(&gpio->completion);
+
+	/* Enable Rx */
+	ctl0 = readl(gpio->regs + SGPIO_CTL0_REG);
+	writel(ctl0 & ~SGPIO_CTL0_REG_RX_DISABLE, gpio->regs + SGPIO_CTL0_REG);
+
+	/* Start reading transaction and wait for completion */
+	writel(readl(gpio->regs + SGPIO_CTL1_REG) | SGPIO_CTL1_REG_W_UPDATA,
+	       gpio->regs + SGPIO_CTL1_REG);
+	if (!wait_for_completion_timeout(&gpio->completion, msecs_to_jiffies(1000))) {
+		rc = -EINVAL;
+		goto err;
+	}
+
+	val = readl(gpio->regs + SGPIO_RDATA_REG(GPIO_GROUP(offset)));
+	rc = !!(val & GPIO_BIT(offset));
+
+err:
+	/* Disalbe Rx to hold the value */
+	writel(ctl0 | SGPIO_CTL0_REG_RX_DISABLE, gpio->regs + SGPIO_CTL0_REG);
+	mutex_unlock(&gpio->lock);
+
+	return rc;
+}
+
+static void phytium_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
+{
+	struct phytium_sgpio *gpio = gpiochip_get_data(gc);
+
+	mutex_lock(&gpio->lock);
+
+	sgpio_set_value(gc, offset, val);
+
+	mutex_unlock(&gpio->lock);
+}
+
+static irqreturn_t phytium_sgpio_irq_handler(int irq, void *data)
+{
+	struct phytium_sgpio *gpio = data;
+
+	if (!readl(gpio->regs + SGPIO_IRQ_REG))
+		return IRQ_NONE;
+
+	/* Clear the interrupt */
+	writel(0, gpio->regs + SGPIO_IRQ_REG);
+
+	/* Check if tx/rx has been done */
+	if (!(readl(gpio->regs + SGPIO_CTL1_REG) & SGPIO_CTL1_REG_OP_STATE))
+		complete(&gpio->completion);
+
+	return IRQ_HANDLED;
+}
+
+static int phytium_sgpio_probe(struct platform_device *pdev)
+{
+	u32 pclk_freq, sclk_freq, clk_div;
+	struct phytium_sgpio *gpio;
+	struct resource *res;
+	struct device *dev = &pdev->dev;
+	int rc;
+
+	gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
+	if (!gpio)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(gpio->regs))
+		return PTR_ERR(gpio->regs);
+
+	if (devm_request_irq(dev, platform_get_irq(pdev, 0),
+			     phytium_sgpio_irq_handler,
+			     IRQF_SHARED, dev_name(dev), gpio)) {
+		dev_err(dev, "failed to request IRQ\n");
+		return -ENOENT;
+	}
+
+	rc = fwnode_property_read_u32(dev_fwnode(dev), "ngpios", &gpio->ngpios);
+	if (rc < 0) {
+		dev_err(dev, "Could not read ngpios property\n");
+		return -EINVAL;
+	} else if (gpio->ngpios % 32) {
+		dev_err(&pdev->dev, "Number of GPIOs not multiple of 32: %d\n",
+			gpio->ngpios);
+		return -EINVAL;
+	}
+
+	rc = fwnode_property_read_u32(dev_fwnode(dev), "bus-frequency", &sclk_freq);
+	if (rc < 0) {
+		dev_err(dev, "Could not read bus-frequency property\n");
+		return -EINVAL;
+	}
+
+	gpio->pclk = devm_clk_get(dev, NULL);
+	if (IS_ERR(gpio->pclk)) {
+		dev_err(dev, "Could not get the APB clock property\n");
+		return PTR_ERR(gpio->pclk);
+	}
+	rc = clk_prepare_enable(gpio->pclk);
+	if (rc) {
+		dev_err(dev, "failed to enable pclk: %d\n", rc);
+		return rc;
+	}
+	pclk_freq = clk_get_rate(gpio->pclk);
+
+	/*
+	 * From the datasheet:
+	 *   (pclk / 2) / (clk_div + 1) = sclk
+	 */
+	if (sclk_freq == 0) {
+		dev_err(dev, "SCLK should not be 0\n");
+		return -EINVAL;
+	}
+
+	clk_div = (pclk_freq / (sclk_freq * 2)) - 1;
+	if (clk_div > (1 << 20) - 1) {
+		dev_err(dev, "clk_div is overflow\n");
+		return -EINVAL;
+	}
+
+	writel(FIELD_PREP(SGPIO_CTL0_REG_CLK_DIV_NUM, clk_div) |
+	       FIELD_PREP(SGPIO_CTL0_REG_L3_L0, DEFAULT_L3_L0) |
+	       SGPIO_CTL0_REG_RX_DISABLE | SGPIO_CTL0_REG_ENABLE,
+	       gpio->regs + SGPIO_CTL0_REG);
+
+	writel(FIELD_PREP(SGPIO_CTL1_REG_BIT_NUM, gpio->ngpios) |
+	       SGPIO_CTL1_REG_READY, gpio->regs + SGPIO_CTL1_REG);
+
+	mutex_init(&gpio->lock);
+	init_completion(&gpio->completion);
+	platform_set_drvdata(pdev, gpio);
+
+	gpio->gc.parent = dev;
+	gpio->gc.base = -1;
+	gpio->gc.ngpio = gpio->ngpios * 2;
+	gpio->gc.label = dev_name(dev);
+	gpio->gc.direction_input = phytium_sgpio_direction_input;
+	gpio->gc.direction_output = phytium_sgpio_direction_output;
+	gpio->gc.get_direction = phytium_sgpio_get_direction;
+	gpio->gc.get = phytium_sgpio_get;
+	gpio->gc.set = phytium_sgpio_set;
+
+	return devm_gpiochip_add_data(dev, &gpio->gc, gpio);
+}
+
+static const struct of_device_id phytium_sgpio_of_match[] = {
+	{ .compatible = "phytium,sgpio", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_sgpio_of_match);
+
+static struct platform_driver phytium_sgpio_driver = {
+	.driver = {
+		.name = KBUILD_MODNAME,
+		.of_match_table = of_match_ptr(phytium_sgpio_of_match),
+	},
+	.probe = phytium_sgpio_probe,
+};
+module_platform_driver(phytium_sgpio_driver);
+
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium SGPIO driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/Kconfig b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/Kconfig
new file mode 100644
index 00000000000000..e3024feb69d0e0
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/Kconfig
@@ -0,0 +1,7 @@
+config DRM_PHYTIUM
+	tristate "DRM Support for Phytium Graphics Card"
+	depends on DRM
+	select DRM_KMS_HELPER
+	help
+	  Choose this option if you have a phytium graphics card.
+	  This driver provides kernel mode setting and buffer management to userspace.
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/Makefile b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/Makefile
new file mode 100644
index 00000000000000..2dc7ea1118cd4c
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/Makefile
@@ -0,0 +1,18 @@
+phytium-dc-drm-y := phytium_display_drv.o \
+		    phytium_plane.o \
+		    phytium_crtc.o \
+		    phytium_dp.o \
+		    phytium_fb.o \
+		    phytium_gem.o \
+		    phytium_fbdev.o \
+		    phytium_debugfs.o \
+		    px210_dp.o \
+		    phytium_panel.o \
+		    px210_dc.o \
+		    phytium_pci.o \
+		    pe220x_dp.o \
+		    pe220x_dc.o \
+		    phytium_platform.o
+
+obj-$(CONFIG_DRM_PHYTIUM) += phytium-dc-drm.o
+CFLAGS_REMOVE_phytium_crtc.o += -mgeneral-regs-only
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dc.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dc.c
new file mode 100644
index 00000000000000..6bb18f0fdb19af
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dc.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium Pe220x display controller DRM driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <asm/neon.h>
+#include <linux/delay.h>
+#include "phytium_display_drv.h"
+#include "pe220x_reg.h"
+#include "phytium_crtc.h"
+#include "phytium_plane.h"
+#include "phytium_fb.h"
+#include "phytium_gem.h"
+
+void pe220x_dc_hw_disable(struct drm_crtc *crtc);
+
+static const unsigned int pe220x_primary_formats[] = {
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_RGBA1010102,
+	DRM_FORMAT_BGRA1010102,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_RGBA8888,
+	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_BGRX8888,
+	DRM_FORMAT_ARGB4444,
+	DRM_FORMAT_ABGR4444,
+	DRM_FORMAT_RGBA4444,
+	DRM_FORMAT_BGRA4444,
+	DRM_FORMAT_XRGB4444,
+	DRM_FORMAT_XBGR4444,
+	DRM_FORMAT_RGBX4444,
+	DRM_FORMAT_BGRX4444,
+	DRM_FORMAT_ARGB1555,
+	DRM_FORMAT_ABGR1555,
+	DRM_FORMAT_RGBA5551,
+	DRM_FORMAT_BGRA5551,
+	DRM_FORMAT_XRGB1555,
+	DRM_FORMAT_XBGR1555,
+	DRM_FORMAT_RGBX5551,
+	DRM_FORMAT_BGRX5551,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+};
+
+static uint64_t pe220x_primary_formats_modifiers[] = {
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static uint64_t pe220x_cursor_formats_modifiers[] = {
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const unsigned int pe220x_cursor_formats[] = {
+	DRM_FORMAT_ARGB8888,
+};
+
+void pe220x_dc_hw_vram_init(struct phytium_display_private *priv, resource_size_t vram_addr,
+			   resource_size_t vram_size)
+{
+	uint32_t config;
+	uint32_t group_offset = priv->address_transform_base;
+
+	phytium_writel_reg(priv, (vram_addr & SRC_ADDR_MASK) >> SRC_ADDR_OFFSET,
+			   group_offset, PE220X_DC_ADDRESS_TRANSFORM_SRC_ADDR);
+	phytium_writel_reg(priv, (vram_size >> SIZE_OFFSET) | ADDRESS_TRANSFORM_ENABLE,
+			   group_offset, PE220X_DC_ADDRESS_TRANSFORM_SIZE);
+	config = phytium_readl_reg(priv, group_offset, PE220X_DC_ADDRESS_TRANSFORM_DST_ADDR);
+	phytium_writel_reg(priv, config, group_offset, PE220X_DC_ADDRESS_TRANSFORM_DST_ADDR);
+}
+
+void pe220x_dc_hw_config_pix_clock(struct drm_crtc *crtc, int clock)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+	int ret = 0;
+
+	/* config pix clock */
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_PIXEL_CLOCK | (clock & PIXEL_CLOCK_MASK),
+			   0, PE220X_DC_CMD_REGISTER(phys_pipe));
+	ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(phys_pipe),
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to set pixel clock\n", __func__);
+}
+
+void pe220x_dc_hw_reset(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int config = 0;
+	int phys_pipe = phytium_crtc->phys_pipe;
+
+	/* disable pixel clock for bmc mode */
+	if (phys_pipe == 0)
+		pe220x_dc_hw_disable(crtc);
+
+	config = phytium_readl_reg(priv, 0, PE220X_DC_CLOCK_CONTROL);
+	config &= (~(DC0_CORE_RESET | DC1_CORE_RESET | AXI_RESET | AHB_RESET));
+
+	if (phys_pipe == 0) {
+		phytium_writel_reg(priv, config | DC0_CORE_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC0_CORE_RESET | AXI_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC0_CORE_RESET | AXI_RESET | AHB_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC0_CORE_RESET | AXI_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC0_CORE_RESET,
+				      0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config, 0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+	} else {
+		phytium_writel_reg(priv, config | DC1_CORE_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC1_CORE_RESET | AXI_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC1_CORE_RESET | AXI_RESET | AHB_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC1_CORE_RESET | AXI_RESET,
+				   0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config | DC1_CORE_RESET,
+				      0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config, 0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+	}
+}
+
+void pe220x_dc_hw_disable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int config = 0;
+	int phys_pipe = phytium_crtc->phys_pipe;
+
+	/* clear framebuffer */
+	phytium_writel_reg(priv, CLEAR_VALUE_BLACK, priv->dc_reg_base[phys_pipe],
+			   PHYTIUM_DC_FRAMEBUFFER_CLEARVALUE);
+	config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe],
+				   PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	config |= FRAMEBUFFER_CLEAR;
+	phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe],
+			   PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+
+	/* disable cursor */
+	config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe], PHYTIUM_DC_CURSOR_CONFIG);
+	config = ((config & (~CURSOR_FORMAT_MASK)) | CURSOR_FORMAT_DISABLED);
+	phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe], PHYTIUM_DC_CURSOR_CONFIG);
+	mdelay(20);
+
+	/* reset pix clock */
+	pe220x_dc_hw_config_pix_clock(crtc, 0);
+
+	if (phys_pipe == 0) {
+		config = phytium_readl_reg(priv, 0, PE220X_DC_CLOCK_CONTROL);
+		phytium_writel_reg(priv, config | DC0_CORE_RESET, 0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config & (~DC0_CORE_RESET), 0, PE220X_DC_CLOCK_CONTROL);
+	} else {
+		config = phytium_readl_reg(priv, 0, PE220X_DC_CLOCK_CONTROL);
+		phytium_writel_reg(priv, config | DC1_CORE_RESET, 0, PE220X_DC_CLOCK_CONTROL);
+		udelay(20);
+		phytium_writel_reg(priv, config & (~DC1_CORE_RESET), 0, PE220X_DC_CLOCK_CONTROL);
+	}
+	udelay(20);
+}
+
+int pe220x_dc_hw_fb_format_check(const struct drm_mode_fb_cmd2 *mode_cmd, int count)
+{
+	int ret = 0;
+
+	if (mode_cmd->modifier[count] != DRM_FORMAT_MOD_LINEAR) {
+		DRM_ERROR("unsupported fb modifier 0x%llx\n", mode_cmd->modifier[count]);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+void pe220x_dc_hw_plane_get_primary_format(const uint64_t **format_modifiers,
+					  const uint32_t **formats,
+					  uint32_t *format_count)
+{
+	*format_modifiers = pe220x_primary_formats_modifiers;
+	*formats = pe220x_primary_formats;
+	*format_count = ARRAY_SIZE(pe220x_primary_formats);
+}
+
+void pe220x_dc_hw_plane_get_cursor_format(const uint64_t **format_modifiers,
+					 const uint32_t **formats,
+					 uint32_t *format_count)
+{
+	*format_modifiers = pe220x_cursor_formats_modifiers;
+	*formats = pe220x_cursor_formats;
+	*format_count = ARRAY_SIZE(pe220x_cursor_formats);
+}
+
+void pe220x_dc_hw_update_primary_hi_addr(struct drm_plane *plane)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	int phys_pipe = phytium_plane->phys_pipe;
+
+	phytium_writel_reg(priv, (phytium_plane->iova[0] >> PREFIX_SHIFT) & PREFIX_MASK,
+			   priv->dc_reg_base[phys_pipe], PE220X_DC_FRAMEBUFFER_Y_HI_ADDRESS);
+
+	phytium_writel_reg(priv, (phytium_plane->iova[1] >> U_PREFIX_SHIFT) & U_PREFIX_MASK,
+			   priv->dc_reg_base[phys_pipe], PE220X_DC_FRAMEBUFFER_U_HI_ADDRESS);
+
+	phytium_writel_reg(priv, (phytium_plane->iova[2] >> V_PREFIX_SHIFT) & V_PREFIX_MASK,
+			   priv->dc_reg_base[phys_pipe], PE220X_DC_FRAMEBUFFER_V_HI_ADDRESS);
+}
+
+void pe220x_dc_hw_update_cursor_hi_addr(struct drm_plane *plane, uint64_t iova)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	int phys_pipe = phytium_plane->phys_pipe;
+	int config;
+
+	config = ((iova >> CURSOR_PREFIX_SHIFT) & CURSOR_PREFIX_MASK);
+	phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe], PE220X_DC_CURSOR_HI_ADDRESS);
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dc.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dc.h
new file mode 100644
index 00000000000000..76b6700a40a158
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium Pe220x display controller DRM driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PE220X_DC_H__
+#define __PE220X_DC_H__
+
+#define PE220X_DC_PIX_CLOCK_MAX				(594000)
+#define PE220X_DC_HDISPLAY_MAX				3840
+#define PE220X_DC_VDISPLAY_MAX				2160
+#define PE220X_DC_ADDRESS_MASK				0x7f
+
+extern void pe220x_dc_hw_vram_init(struct phytium_display_private *priv,
+				  resource_size_t vram_addr,
+				  resource_size_t vram_size);
+extern void pe220x_dc_hw_config_pix_clock(struct drm_crtc *crtc, int clock);
+extern void pe220x_dc_hw_disable(struct drm_crtc *crtc);
+extern int pe220x_dc_hw_fb_format_check(const struct drm_mode_fb_cmd2 *mode_cmd, int count);
+extern void pe220x_dc_hw_plane_get_primary_format(const uint64_t **format_modifiers,
+						 const uint32_t **formats,
+						 uint32_t *format_count);
+extern void pe220x_dc_hw_plane_get_cursor_format(const uint64_t **format_modifiers,
+						const uint32_t **formats,
+						uint32_t *format_count);
+extern void pe220x_dc_hw_update_primary_hi_addr(struct drm_plane *plane);
+extern void pe220x_dc_hw_update_cursor_hi_addr(struct drm_plane *plane, uint64_t iova);
+void pe220x_dc_hw_reset(struct drm_crtc *crtc);
+#endif /* __PE220X_DC_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dp.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dp.c
new file mode 100644
index 00000000000000..19f38fc01106cc
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dp.c
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium display port DRM driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include "phytium_display_drv.h"
+#include "pe220x_reg.h"
+#include "phytium_dp.h"
+#include "pe220x_dp.h"
+
+static uint8_t pe220x_dp_source_lane_count[2] = {1, 1};
+
+/* [reg][ling_rate 1.62->8.1] */
+static int vco_val[12][4] = {
+	{0x0509, 0x0509, 0x0509, 0x0509}, /* CP_PADJ		 */
+	{0x0f00, 0x0f00, 0x0f00, 0x0f00}, /* CP_IADJ		 */
+	{0x0F08, 0x0F08, 0x0F08, 0x0F08}, /* FILT_PADJ		 */
+	{0x0061, 0x006C, 0x006C, 0x0051}, /* INTDIV		 */
+	{0x3333, 0x0000, 0x0000, 0x0000}, /* FRACDIVL		 */
+	{0x0000, 0x0000, 0x0000, 0x0000}, /* FRACDIVH		 */
+	{0x0042, 0x0048, 0x0048, 0x0036}, /* HIGH_THR		 */
+	{0x0002, 0x0002, 0x0002, 0x0002}, /* PDIAG_CTRL		 */
+	{0x0c5e, 0x0c5e, 0x0c5e, 0x0c5e}, /* VCOCAL_PLLCNT_START */
+	{0x00c7, 0x00c7, 0x00c7, 0x00c7}, /* LOCK_PEFCNT	 */
+	{0x00c7, 0x00c7, 0x00c7, 0x00c7}, /* LOCK_PLLCNT_START	 */
+	{0x0005, 0x0005, 0x0005, 0x0005}, /* LOCK_PLLCNT_THR	 */
+};
+
+/* [link_rate][swing][emphasis] */
+static int mgnfs_val[4][4][4] = {
+	/* 1.62Gbps */
+	{
+		{0x0026, 0x001f, 0x0012, 0x0000},
+		{0x0013, 0x0013, 0x0000, 0x0000},
+		{0x0006, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+	/* 2.7Gbps */
+	{
+		{0x0026, 0x001f, 0x0012, 0x0000},
+		{0x0013, 0x0013, 0x0000, 0x0000},
+		{0x0006, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+	/* 5.4Gbps */
+	{
+		{0x001f, 0x0013, 0x005, 0x0000},
+		{0x0018, 0x006, 0x0000, 0x0000},
+		{0x000c, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+	/* 8.1Gbps */
+	{
+		{0x0026, 0x0013, 0x005, 0x0000},
+		{0x0013, 0x006, 0x0000, 0x0000},
+		{0x0006, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+};
+
+/* [link_rate][swing][emphasis] */
+static int cpost_val[4][4][4] = {
+	/* 1.62Gbps */
+	{
+		{0x0000, 0x0014, 0x0020, 0x002a},
+		{0x0000, 0x0010, 0x001f, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+	/* 2.7Gbps */
+	{
+		{0x0000, 0x0014, 0x0020, 0x002a},
+		{0x0000, 0x0010, 0x001f, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+	/* 5.4Gbps */
+	{
+		{0x0005, 0x0014, 0x0022, 0x002e},
+		{0x0000, 0x0013, 0x0020, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+	/* 8.1Gbps */
+	{
+		{0x0000, 0x0014, 0x0022, 0x002e},
+		{0x0000, 0x0013, 0x0020, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+};
+
+static int pe220x_dp_hw_set_phy_lane_and_rate(struct phytium_dp_device *phytium_dp,
+					     uint8_t link_lane_count, uint32_t link_rate)
+{
+	int port = phytium_dp->port%2;
+	int i = 0, data, tmp, tmp1, index = 0, mask = 0;
+	int timeout = 500, ret = 0;
+
+	/* set pma powerdown */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (A3_POWERDOWN3 << (i * A3_POWERDOWN3_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PMA0_POWER(port), data);
+
+	/* lane pll disable */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+		data |= (PLL_EN << (i * PLL_EN_SHIFT));
+		mask |= (((1<<PLL_EN_SHIFT) - 1) << (i * PLL_EN_SHIFT));
+	}
+	data &= ~mask;
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_EN(port), data);
+
+	/* pma pll disable */
+	data = CONTROL_ENABLE & (~CONTROL_ENABLE_MASK);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PMA_CONTROL(port), data);
+
+	/* read pma pll disable state */
+	mdelay(2);
+	phytium_phy_readl(phytium_dp, PE220X_PHY_PMA_CONTROL2(port));
+
+	/* config link rate */
+	switch (link_rate) {
+	case 810000:
+		tmp = PLL_LINK_RATE_810000;
+		tmp1 = HSCLK_LINK_RATE_810000;
+		index = 3;
+		break;
+	case 540000:
+		tmp = PLL_LINK_RATE_540000;
+		tmp1 = HSCLK_LINK_RATE_540000;
+		index = 2;
+		break;
+	case 270000:
+		tmp = PLL_LINK_RATE_270000;
+		tmp1 = HSCLK_LINK_RATE_270000;
+		index = 1;
+		break;
+	case 162000:
+		tmp = PLL_LINK_RATE_162000;
+		tmp1 = HSCLK_LINK_RATE_162000;
+		index = 0;
+		break;
+	default:
+		DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+		tmp = PLL_LINK_RATE_162000;
+		tmp1 = HSCLK_LINK_RATE_162000;
+		index = 0;
+		break;
+	}
+
+	/* config analog pll for link0 */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CLK_SEL(port), tmp);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_HSCLK0_SEL(port), HSCLK_LINK_0);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_HSCLK0_DIV(port), tmp1);
+
+	/* config digital pll for link0 */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLLDRC0_CTRL(port), PLLDRC_LINK0);
+
+	/* common for all rate */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_DSM_M0(port), PLL0_DSM_M0);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_VCOCAL_START(port),
+			   PLL0_VCOCAL_START);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_VCOCAL_CTRL(port),
+			   PLL0_VCOCAL_CTRL);
+
+	/* different for all rate */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CP_PADJ(port),
+			   vco_val[0][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CP_IADJ(port),
+			   vco_val[1][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CP_FILT_PADJ(port),
+			   vco_val[2][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_INTDIV(port),
+			   vco_val[3][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_FRACDIVL(port),
+			   vco_val[4][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_FRACDIVH(port),
+			   vco_val[5][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_HIGH_THR(port),
+			   vco_val[6][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_PDIAG_CTRL(port),
+			   vco_val[7][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_VCOCAL_PLLCNT_START(port),
+			   vco_val[8][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_LOCK_PEFCNT(port),
+			   vco_val[9][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_LOCK_PLLCNT_START(port),
+			   vco_val[10][index]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_LOCK_PLLCNT_THR(port),
+			   vco_val[11][index]);
+
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_PSC_A0(port),
+			   PLL0_TX_PSC_A0);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_PSC_A2(port),
+			   PLL0_TX_PSC_A2);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_PSC_A3(port),
+			   PLL0_TX_PSC_A3);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_A0(port),
+			   PLL0_RX_PSC_A0);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_A2(port),
+			   PLL0_RX_PSC_A2);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_A3(port),
+			   PLL0_RX_PSC_A3);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_CAL(port),
+			   PLL0_RX_PSC_CAL);
+
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_XCVR_CTRL(port),
+			   PLL0_XCVR_CTRL);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_GCSM1_CTRL(port),
+			   PLL0_RX_GCSM1_CTRL);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_GCSM2_CTRL(port),
+			   PLL0_RX_GCSM2_CTRL);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PERGCSM_CTRL(port),
+			   PLL0_RX_PERGCSM_CTRL);
+
+	/* pma pll enable */
+	data = CONTROL_ENABLE;
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PMA_CONTROL(port), data);
+
+	/* lane pll enable */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (PLL_EN << (i * PLL_EN_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_EN(port), data);
+
+	/* set pma power active */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (A0_ACTIVE << (i * A0_ACTIVE_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PMA0_POWER(port), data);
+
+	mask = PLL0_LOCK_DONE;
+	do {
+		mdelay(1);
+		timeout--;
+		tmp = phytium_phy_readl(phytium_dp, PE220X_PHY_PMA_CONTROL2(port));
+	} while ((!(tmp & mask)) && timeout);
+
+	if (timeout == 0) {
+		DRM_ERROR("dp(%d) phy pll lock failed\n", port);
+		ret = -1;
+	}
+	udelay(1);
+
+	return ret;
+}
+
+static void pe220x_dp_hw_set_phy_lane_setting(struct phytium_dp_device *phytium_dp,
+					     uint32_t link_rate, uint8_t train_set)
+{
+	int port = phytium_dp->port % 3;
+	int voltage_swing = 0;
+	int pre_emphasis = 0, link_rate_index = 0;
+
+	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+		voltage_swing = 1;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+		voltage_swing = 2;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+		voltage_swing = 3;
+		break;
+	default:
+		voltage_swing = 0;
+		break;
+	}
+
+	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
+	case DP_TRAIN_PRE_EMPH_LEVEL_1:
+		pre_emphasis = 1;
+		break;
+	case DP_TRAIN_PRE_EMPH_LEVEL_2:
+		pre_emphasis = 2;
+		break;
+	case DP_TRAIN_PRE_EMPH_LEVEL_3:
+		pre_emphasis = 3;
+		break;
+	default:
+		pre_emphasis = 0;
+		break;
+	}
+
+	switch (link_rate) {
+	case 810000:
+		link_rate_index = 3;
+		break;
+	case 540000:
+		link_rate_index = 2;
+		break;
+	case 270000:
+		link_rate_index = 1;
+		break;
+	case 162000:
+		link_rate_index = 0;
+		break;
+	default:
+		DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+		link_rate_index = 2;
+		break;
+	}
+
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_DIAG_ACYA(port), LOCK);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_TXCC_CTRL(port), TX_TXCC_CTRL);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_DRV(port), TX_DRV);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_MGNFS(port),
+			   mgnfs_val[link_rate_index][voltage_swing][pre_emphasis]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_CPOST(port),
+			   cpost_val[link_rate_index][voltage_swing][pre_emphasis]);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_DIAG_ACYA(port), UNLOCK);
+}
+
+static int pe220x_dp_hw_init_phy(struct phytium_dp_device *phytium_dp)
+{
+	int port = phytium_dp->port;
+	int i = 0, data, tmp, mask;
+	int timeout = 500, ret = 0;
+
+	phytium_phy_writel(phytium_dp, PE220X_PHY_APB_RESET(port), APB_RESET);
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PIPE_RESET(port), RESET);
+
+	/* config lane to dp mode */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (LANE_BIT << (i * LANE_BIT_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_MODE(port), data);
+
+	/* pll clock enable */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (PLL_EN << (i * PLL_EN_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_EN(port), data);
+
+	/* config input 20 bit */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (BIT_20 << (i * BIT_20_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PMA_WIDTH(port), data);
+
+	/* config lane active power state */
+	data = 0;
+	for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+		data |= (A0_ACTIVE << (i * A0_ACTIVE_SHIFT));
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PMA0_POWER(port), data);
+
+	/* link reset */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_LINK_RESET(port), LINK_RESET);
+
+	phytium_phy_writel(phytium_dp, PE220X_PHY_SGMII_DPSEL_INIT(port), DP_SEL);
+
+	/* config single link */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_CFG(port), SINGLE_LINK);
+
+	/* pipe reset */
+	phytium_phy_writel(phytium_dp, PE220X_PHY_PIPE_RESET(port), RESET_DEASSERT);
+
+	mask = PLL0_LOCK_DONE;
+	do {
+		mdelay(1);
+		timeout--;
+		tmp = phytium_phy_readl(phytium_dp, PE220X_PHY_PMA_CONTROL2(port));
+	} while ((!(tmp & mask)) && timeout);
+
+	if (timeout == 0) {
+		DRM_ERROR("reset dp(%d) phy failed\n", port);
+		ret = -1;
+	}
+	udelay(1);
+
+	return ret;
+}
+
+static void pe220x_dp_hw_poweron_panel(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	int ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | PANEL_POWER_ENABLE,
+			   0, PE220X_DC_CMD_REGISTER(port));
+	ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to poweron panel\n", __func__);
+}
+
+static void pe220x_dp_hw_poweroff_panel(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	int ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | PANEL_POWER_DISABLE,
+			   0, PE220X_DC_CMD_REGISTER(port));
+	ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to poweroff panel\n", __func__);
+}
+
+static void pe220x_dp_hw_enable_backlight(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | BACKLIGHT_ENABLE,
+			   0, PE220X_DC_CMD_REGISTER(port));
+	ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to enable backlight\n", __func__);
+}
+
+static void pe220x_dp_hw_disable_backlight(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	int ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | BACKLIGHT_DISABLE,
+			   0, PE220X_DC_CMD_REGISTER(port));
+	ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to disable backlight\n", __func__);
+}
+
+static uint32_t pe220x_dp_hw_get_backlight(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int config;
+	uint32_t group_offset = priv->address_transform_base;
+
+	config = phytium_readl_reg(priv, group_offset, PE220X_DC_ADDRESS_TRANSFORM_BACKLIGHT_VALUE);
+	return ((config >> BACKLIGHT_VALUE_SHIFT) & BACKLIGHT_VALUE_MASK);
+}
+
+static int pe220x_dp_hw_set_backlight(struct phytium_dp_device *phytium_dp, uint32_t level)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	int config = 0;
+	int ret = 0;
+
+	if (level > PE220X_DP_BACKLIGHT_MAX) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	config = FLAG_REQUEST | CMD_BACKLIGHT | ((level & BACKLIGHT_MASK) << BACKLIGHT_SHIFT);
+	phytium_writel_reg(priv, config, 0, PE220X_DC_CMD_REGISTER(port));
+	ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to set backlight\n", __func__);
+out:
+	return ret;
+}
+
+bool pe220x_dp_hw_spread_is_enable(struct phytium_dp_device *phytium_dp)
+{
+	return false;
+}
+
+int pe220x_dp_hw_reset(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, DP_RESET, group_offset, PE220X_DP_CONTROLLER_RESET);
+	udelay(500);
+	phytium_writel_reg(priv, AUX_CLK_DIVIDER_100, group_offset, PHYTIUM_DP_AUX_CLK_DIVIDER);
+	phytium_writel_reg(priv, SUPPORT_EDP_1_4, group_offset, PHYTIUM_EDP_CRC_ENABLE);
+
+	return 0;
+}
+
+uint8_t pe220x_dp_hw_get_source_lane_count(struct phytium_dp_device *phytium_dp)
+{
+	return pe220x_dp_source_lane_count[phytium_dp->port];
+}
+
+static struct phytium_dp_func pe220x_dp_funcs = {
+	.dp_hw_get_source_lane_count = pe220x_dp_hw_get_source_lane_count,
+	.dp_hw_reset = pe220x_dp_hw_reset,
+	.dp_hw_spread_is_enable = pe220x_dp_hw_spread_is_enable,
+	.dp_hw_set_backlight = pe220x_dp_hw_set_backlight,
+	.dp_hw_get_backlight = pe220x_dp_hw_get_backlight,
+	.dp_hw_disable_backlight = pe220x_dp_hw_disable_backlight,
+	.dp_hw_enable_backlight = pe220x_dp_hw_enable_backlight,
+	.dp_hw_poweroff_panel = pe220x_dp_hw_poweroff_panel,
+	.dp_hw_poweron_panel = pe220x_dp_hw_poweron_panel,
+	.dp_hw_init_phy = pe220x_dp_hw_init_phy,
+	.dp_hw_set_phy_lane_setting = pe220x_dp_hw_set_phy_lane_setting,
+	.dp_hw_set_phy_lane_and_rate = pe220x_dp_hw_set_phy_lane_and_rate,
+};
+
+void pe220x_dp_func_register(struct phytium_dp_device *phytium_dp)
+{
+	phytium_dp->funcs = &pe220x_dp_funcs;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dp.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dp.h
new file mode 100644
index 00000000000000..a79bf5b5e3ab8d
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_dp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium display port DRM driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PE220X_DP_H__
+#define __PE220X_DP_H__
+
+#define PE220X_DP_BACKLIGHT_MAX				100
+
+void pe220x_dp_func_register(struct phytium_dp_device *phytium_dp);
+#endif /* __PE220X_DP_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_reg.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_reg.h
new file mode 100644
index 00000000000000..8dfbd41a5350ff
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/pe220x_reg.h
@@ -0,0 +1,209 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium Pe220x display engine register
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PE220X_REG_H__
+#define __PE220X_REG_H__
+
+#include "phytium_reg.h"
+
+/* dc register */
+#define PE220X_DC_CLOCK_CONTROL				0x0000
+#define DC1_CORE_RESET					(1<<18)
+#define DC0_CORE_RESET					(1<<17)
+#define AXI_RESET					(1<<16)
+#define AHB_RESET					(1<<12)
+
+#define PE220X_DC_CMD_REGISTER(pipe)			(PE220X_DC_BASE(0) + 0x00F0 + 0x4*(pipe))
+#define FLAG_REPLY					(1<<31)
+#define FLAG_REQUEST					(1<<30)
+#define CMD_PIXEL_CLOCK					(0x0 << 28)
+#define CMD_BACKLIGHT					(0x1 << 28)
+#define CMD_DC_DP_RESET					(0x3 << 28)
+#define BACKLIGHT_SHIFT					21
+#define BACKLIGHT_MASK					0x7f
+#define BACKLIGHT_MAX					100
+#define BACKLIGHT_ENABLE				(101 << BACKLIGHT_SHIFT)
+#define BACKLIGHT_DISABLE				(102 << BACKLIGHT_SHIFT)
+#define PANEL_POWER_ENABLE				(103 << BACKLIGHT_SHIFT)
+#define PANEL_POWER_DISABLE				(104 << BACKLIGHT_SHIFT)
+#define PIXEL_CLOCK_MASK				(0x1fffff)
+
+#define PE220X_DC_FRAMEBUFFER_Y_HI_ADDRESS		0x1404
+#define PREFIX_MASK					0xff
+#define PREFIX_SHIFT					32
+
+#define	PE220X_DC_CURSOR_HI_ADDRESS			0x1490
+#define CURSOR_PREFIX_MASK				0xff
+#define CURSOR_PREFIX_SHIFT				32
+
+#define PE220X_DC_FRAMEBUFFER_U_HI_ADDRESS		0x1534
+#define U_PREFIX_MASK					0xff
+#define U_PREFIX_SHIFT					32
+
+#define PE220X_DC_FRAMEBUFFER_V_HI_ADDRESS		0x153c
+#define V_PREFIX_MASK					0xff
+#define V_PREFIX_SHIFT					32
+
+/* dp register */
+#define PE220X_DP_CONTROLLER_RESET			0x0850
+#define DP_RESET					0x1
+
+/* address transform register */
+#define PE220X_DC_ADDRESS_TRANSFORM_SRC_ADDR		0x0
+#define SRC_ADDR_OFFSET					22
+#define SRC_ADDR_MASK					0xffffffffff
+
+#define PE220X_DC_ADDRESS_TRANSFORM_SIZE			0x4
+#define ADDRESS_TRANSFORM_ENABLE			(0x1 << 31)
+#define SIZE_OFFSET					22
+
+#define PE220X_DC_ADDRESS_TRANSFORM_DST_ADDR		0x8
+#define DST_ADDR_OFFSET					22
+
+#define PE220X_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS	0x48
+#define DC_DP_RESET_STATUS(pipe)			(1 << pipe)
+#define DP_SPREAD_ENABLE(pipe)				(0x8 << pipe)
+
+#define PE220X_DC_ADDRESS_TRANSFORM_BACKLIGHT_VALUE	0x4c
+#define BACKLIGHT_VALUE_MASK				(0x7f)
+#define BACKLIGHT_VALUE_SHIFT				16
+
+/* phy register start */
+#define PE220X_PHY_BASE(pipe)				(0x100000*pipe)
+
+#define PE220X_PHY_PIPE_RESET(pipe)			(PE220X_PHY_BASE(pipe) + 0x40254)
+#define RESET						0x0
+#define RESET_DEASSERT					0x1
+
+#define PE220X_PHY_MODE(pipe)				(PE220X_PHY_BASE(pipe) + 0x40034)
+#define LANE_BIT					(0x3)
+#define LANE_BIT_SHIFT					0x2
+
+#define PE220X_PHY_LINK_CFG(pipe)			(PE220X_PHY_BASE(pipe) + 0x40044)
+#define LANE_MASTER					0x1
+#define LANE_MASTER_SHIFT				1
+
+#define PE220X_PHY_PLL_EN(pipe)				(PE220X_PHY_BASE(pipe) + 0x40214)
+#define PLL_EN						0x1
+#define PLL_EN_SHIFT					1
+
+#define PE220X_PHY_PMA_WIDTH(pipe)			(PE220X_PHY_BASE(pipe) + 0x4021c)
+#define	BIT_20						0x5
+#define	BIT_20_SHIFT					4
+
+#define PE220X_PHY_PLL_SOURCE_SEL(pipe)			(PE220X_PHY_BASE(pipe) + 0x4004C)
+
+#define PE220X_PHY_PMA0_POWER(pipe)			(PE220X_PHY_BASE(pipe) + 0x402bc)
+#define	A0_ACTIVE					0x1
+#define	A0_ACTIVE_SHIFT					8
+#define	A3_POWERDOWN3					0x8
+#define	A3_POWERDOWN3_SHIFT				8
+
+#define PE220X_PHY_LINK_RESET(pipe)			(PE220X_PHY_BASE(pipe) + 0x40258)
+#define LINK_RESET					0x1
+#define LINK_RESET_MASK					0x1
+#define LINTK_RESET_SHIFT				0x1
+
+#define PE220X_PHY_SGMII_DPSEL_INIT(pipe)		(PE220X_PHY_BASE(pipe) + 0x40260)
+#define DP_SEL						0x1
+
+#define PE220X_PHY_APB_RESET(pipe)			(PE220X_PHY_BASE(pipe) + 0x40250)
+#define	APB_RESET					0x1
+
+/* phy origin register */
+#define PE220X_PHY_PLL_CFG(pipe)				(PE220X_PHY_BASE(pipe) + 0x30038)
+#define SINGLE_LINK					0x0
+
+#define PE220X_PHY_PMA_CONTROL(pipe)			(PE220X_PHY_BASE(pipe) + 0x3800c)
+#define CONTROL_ENABLE					0x1
+#define CONTROL_ENABLE_MASK				0x1
+#define CONTROL_ENABLE_SHIFT				0x1
+
+#define PE220X_PHY_PMA_CONTROL2(pipe)			(PE220X_PHY_BASE(pipe) + 0x38004)
+#define PLL0_LOCK_DONE					(0x1 << 6)
+
+#define PE220X_PHY_PLL0_CLK_SEL(pipe)			(PE220X_PHY_BASE(pipe) + 0X684)
+#define PLL_LINK_RATE_162000				0xf01
+#define PLL_LINK_RATE_270000				0x701
+#define PLL_LINK_RATE_540000				0x301
+#define PLL_LINK_RATE_810000				0x200
+
+#define PE220X_PHY_HSCLK0_SEL(pipe)			(PE220X_PHY_BASE(pipe) + 0x18398)
+#define HSCLK_LINK_0					0x0
+#define HSCLK_LINK_1					0x1
+
+#define PE220X_PHY_HSCLK0_DIV(pipe)			(PE220X_PHY_BASE(pipe) + 0x1839c)
+#define HSCLK_LINK_RATE_162000				0x2
+#define HSCLK_LINK_RATE_270000				0x1
+#define HSCLK_LINK_RATE_540000				0x0
+#define HSCLK_LINK_RATE_810000				0x0
+
+#define PE220X_PHY_PLLDRC0_CTRL(pipe)			(PE220X_PHY_BASE(pipe) + 0x18394)
+#define PLLDRC_LINK0					0x1
+#define PLLDRC_LINK1					0x9
+
+#define PE220X_PHY_PLL0_DSM_M0(pipe)			(PE220X_PHY_BASE(pipe) + 0x250)
+#define PLL0_DSM_M0					0x4
+#define PE220X_PHY_PLL0_VCOCAL_START(pipe)		(PE220X_PHY_BASE(pipe) + 0x218)
+#define PLL0_VCOCAL_START				0xc5e
+#define PE220X_PHY_PLL0_VCOCAL_CTRL(pipe)		(PE220X_PHY_BASE(pipe) + 0x208)
+#define PLL0_VCOCAL_CTRL				0x3
+
+#define PE220X_PHY_PLL0_CP_PADJ(pipe)			(PE220X_PHY_BASE(pipe) + 0x690)
+#define PE220X_PHY_PLL0_CP_IADJ(pipe)			(PE220X_PHY_BASE(pipe) + 0x694)
+#define PE220X_PHY_PLL0_CP_FILT_PADJ(pipe)		(PE220X_PHY_BASE(pipe) + 0x698)
+#define PE220X_PHY_PLL0_INTDIV(pipe)			(PE220X_PHY_BASE(pipe) + 0x240)
+#define PE220X_PHY_PLL0_FRACDIVL(pipe)			(PE220X_PHY_BASE(pipe) + 0x244)
+#define PE220X_PHY_PLL0_FRACDIVH(pipe)			(PE220X_PHY_BASE(pipe) + 0x248)
+#define PE220X_PHY_PLL0_HIGH_THR(pipe)			(PE220X_PHY_BASE(pipe) + 0x24c)
+#define PE220X_PHY_PLL0_PDIAG_CTRL(pipe)			(PE220X_PHY_BASE(pipe) + 0x680)
+#define PE220X_PHY_PLL0_VCOCAL_PLLCNT_START(pipe)	(PE220X_PHY_BASE(pipe) + 0x220)
+#define PE220X_PHY_PLL0_LOCK_PEFCNT(pipe)		(PE220X_PHY_BASE(pipe) + 0x270)
+#define PE220X_PHY_PLL0_LOCK_PLLCNT_START(pipe)		(PE220X_PHY_BASE(pipe) + 0x278)
+#define PE220X_PHY_PLL0_LOCK_PLLCNT_THR(pipe)		(PE220X_PHY_BASE(pipe) + 0x27c)
+
+#define	PE220X_PHY_PLL0_TX_PSC_A0(pipe)			(PE220X_PHY_BASE(pipe) + 0x18400)
+#define PLL0_TX_PSC_A0					0xfb
+#define	PE220X_PHY_PLL0_TX_PSC_A2(pipe)			(PE220X_PHY_BASE(pipe) + 0x18408)
+#define PLL0_TX_PSC_A2					0x4aa
+#define	PE220X_PHY_PLL0_TX_PSC_A3(pipe)			(PE220X_PHY_BASE(pipe) + 0x1840c)
+#define PLL0_TX_PSC_A3					0x4aa
+#define	PE220X_PHY_PLL0_RX_PSC_A0(pipe)			(PE220X_PHY_BASE(pipe) + 0x28000)
+#define PLL0_RX_PSC_A0					0x0
+#define	PE220X_PHY_PLL0_RX_PSC_A2(pipe)			(PE220X_PHY_BASE(pipe) + 0x28008)
+#define PLL0_RX_PSC_A2					0x0
+#define	PE220X_PHY_PLL0_RX_PSC_A3(pipe)			(PE220X_PHY_BASE(pipe) + 0x2800C)
+#define PLL0_RX_PSC_A3					0x0
+#define	PE220X_PHY_PLL0_RX_PSC_CAL(pipe)			(PE220X_PHY_BASE(pipe) + 0x28018)
+#define PLL0_RX_PSC_CAL					0x0
+
+#define PE220X_PHY_PLL0_XCVR_CTRL(pipe)			(PE220X_PHY_BASE(pipe) + 0x183a8)
+#define PLL0_XCVR_CTRL					0xf
+
+#define PE220X_PHY_PLL0_RX_GCSM1_CTRL(pipe)		(PE220X_PHY_BASE(pipe) + 0x28420)
+#define PLL0_RX_GCSM1_CTRL				0x0
+#define PE220X_PHY_PLL0_RX_GCSM2_CTRL(pipe)		(PE220X_PHY_BASE(pipe) + 0x28440)
+#define PLL0_RX_GCSM2_CTRL				0x0
+#define PE220X_PHY_PLL0_RX_PERGCSM_CTRL(pipe)		(PE220X_PHY_BASE(pipe) + 0x28460)
+#define PLL0_RX_PERGCSM_CTRL				0x0
+
+/* swing and emphasis */
+#define PE220X_PHY_PLL0_TX_DIAG_ACYA(pipe)		(PE220X_PHY_BASE(pipe) + 0x1879c)
+#define LOCK						1
+#define UNLOCK						0
+
+#define PE220X_PHY_PLL0_TX_TXCC_CTRL(pipe)		(PE220X_PHY_BASE(pipe) + 0x18100)
+#define TX_TXCC_CTRL					0x8a4
+
+#define PE220X_PHY_PLL0_TX_DRV(pipe)			(PE220X_PHY_BASE(pipe) + 0x18318)
+#define TX_DRV						0x3
+
+#define PE220X_PHY_PLL0_TX_MGNFS(pipe)			(PE220X_PHY_BASE(pipe) + 0x18140)
+
+#define PE220X_PHY_PLL0_TX_CPOST(pipe)			(PE220X_PHY_BASE(pipe) + 0x18130)
+
+#endif /* __PE220X_REG_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_crtc.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_crtc.c
new file mode 100644
index 00000000000000..f2ed42d6bd87f3
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_crtc.c
@@ -0,0 +1,829 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <asm/neon.h>
+#include <drm/drm_vblank.h>
+#include "phytium_display_drv.h"
+#include "phytium_crtc.h"
+#include "phytium_plane.h"
+#include "phytium_dp.h"
+#include "px210_dc.h"
+#include "pe220x_dc.h"
+#include "phytium_reg.h"
+
+#define MAXKERNELSIZE		9
+#define SUBPIXELINDEXBITS	5
+#define SUBPIXELCOUNT		(1 << SUBPIXELINDEXBITS)
+#define SUBPIXELLOADCOUNT	(SUBPIXELCOUNT / 2 + 1)
+#define WEIGHTSTATECOUNT	(((SUBPIXELLOADCOUNT * MAXKERNELSIZE + 1) & ~1) / 2)
+#define KERNELTABLESIZE		(SUBPIXELLOADCOUNT * MAXKERNELSIZE * sizeof(uint16_t))
+#define PHYALIGN(n, align)	(((n) + ((align) - 1)) & ~((align) - 1))
+#define KERNELSTATES		(PHYALIGN(KERNELTABLESIZE + 4, 8))
+#define PHYPI			3.14159265358979323846f
+
+#define MATH_Add(X, Y)			(float)((X) + (Y))
+#define MATH_Multiply(X, Y)		(float)((X) * (Y))
+#define MATH_Divide(X, Y)		(float)((X) / (Y))
+#define MATH_DivideFromUInteger(X, Y)	((float)(X) / (float)(Y))
+#define MATH_I2Float(X)		(float)(X)
+
+struct filter_blit_array {
+	uint8_t kernelSize;
+	uint32_t scaleFactor;
+	uint32_t *kernelStates;
+};
+
+static uint32_t dc_scaling_get_factor(uint32_t src_size, uint32_t dst_size)
+{
+	uint32_t factor = 0;
+
+	factor = ((src_size - 1) << SCALE_FACTOR_SRC_OFFSET) / (dst_size - 1);
+
+	return factor;
+}
+
+static float dc_sint(float x)
+{
+	const float B = 1.2732395477;
+	const float C = -0.4052847346;
+	const float P = 0.2310792853;
+	float y;
+
+	if (x < 0)
+		y = B*x - C*x*x;
+	else
+		y = B*x + C*x*x;
+	if (y < 0)
+		y = P * (y * (0 - y) - y) + y;
+	else
+		y = P * (y * y - y) + y;
+	return y;
+}
+
+static float dc_sinc_filter(float x, int radius)
+{
+	float pit, pitd, f1, f2, result;
+	float f_radius = MATH_I2Float(radius);
+
+	if (x == 0.0f) {
+		result = 1.0f;
+	} else if ((x < -f_radius) || (x > f_radius)) {
+		result = 0.0f;
+	} else {
+		pit  = MATH_Multiply(PHYPI, x);
+		pitd = MATH_Divide(pit, f_radius);
+		f1 = MATH_Divide(dc_sint(pit), pit);
+		f2 = MATH_Divide(dc_sint(pitd), pitd);
+		result = MATH_Multiply(f1, f2);
+	}
+
+	return result;
+}
+
+static int dc_calculate_sync_table(
+	uint8_t kernel_size,
+	uint32_t src_size,
+	uint32_t dst_size,
+	struct filter_blit_array *kernel_info)
+{
+	uint32_t scale_factor;
+	float f_scale;
+	int kernel_half;
+	float f_subpixel_step;
+	float f_subpixel_offset;
+	uint32_t subpixel_pos;
+	int kernel_pos;
+	int padding;
+	uint16_t *kernel_array;
+	int range = 0;
+
+	do {
+		/* Compute the scale factor. */
+		scale_factor = dc_scaling_get_factor(src_size, dst_size);
+
+		/* Same kernel size and ratio as before? */
+		if ((kernel_info->kernelSize  == kernel_size) &&
+		(kernel_info->scaleFactor == kernel_size)) {
+			break;
+		}
+
+		/* check the array */
+		if (kernel_info->kernelStates == NULL)
+			break;
+
+		/* Store new parameters. */
+		kernel_info->kernelSize  = kernel_size;
+		kernel_info->scaleFactor = scale_factor;
+
+		/* Compute the scale factor. */
+		f_scale = MATH_DivideFromUInteger(dst_size, src_size);
+
+		/* Adjust the factor for magnification. */
+		if (f_scale > 1.0f)
+			f_scale = 1.0f;
+
+		/* Calculate the kernel half. */
+		kernel_half = (int) (kernel_info->kernelSize >> 1);
+
+		/* Calculate the subpixel step. */
+		f_subpixel_step = MATH_Divide(1.0f, MATH_I2Float(SUBPIXELCOUNT));
+
+		/* Init the subpixel offset. */
+		f_subpixel_offset = 0.5f;
+
+		/* Determine kernel padding size. */
+		padding = (MAXKERNELSIZE - kernel_info->kernelSize) / 2;
+
+		/* Set initial kernel array pointer. */
+		kernel_array = (uint16_t *) (kernel_info->kernelStates + 1);
+
+		/* Loop through each subpixel. */
+		for (subpixel_pos = 0; subpixel_pos < SUBPIXELLOADCOUNT; subpixel_pos++) {
+			/* Define a temporary set of weights. */
+			float fSubpixelSet[MAXKERNELSIZE];
+
+			/* Init the sum of all weights for the current subpixel. */
+			float fWeightSum = 0.0f;
+			uint16_t weightSum = 0;
+			short int adjustCount, adjustFrom;
+			short int adjustment;
+
+			/* Compute weights. */
+			for (kernel_pos = 0; kernel_pos < MAXKERNELSIZE; kernel_pos++) {
+				/* Determine the current index. */
+				int index = kernel_pos - padding;
+
+				/* Pad with zeros. */
+				if ((index < 0) || (index >= kernel_info->kernelSize)) {
+					fSubpixelSet[kernel_pos] = 0.0f;
+				} else {
+					if (kernel_info->kernelSize == 1) {
+						fSubpixelSet[kernel_pos] = 1.0f;
+					} else {
+						/* Compute the x position for filter function. */
+						float fX = MATH_Add(
+							MATH_I2Float(index - kernel_half),
+							f_subpixel_offset);
+						fX = MATH_Multiply(fX, f_scale);
+
+						/* Compute the weight. */
+						fSubpixelSet[kernel_pos] = dc_sinc_filter(fX,
+									   kernel_half);
+					}
+
+					/* Update the sum of weights. */
+					fWeightSum = MATH_Add(fWeightSum,
+								      fSubpixelSet[kernel_pos]);
+				}
+			}
+
+			/* Adjust weights so that the sum will be 1.0. */
+			for (kernel_pos = 0; kernel_pos < MAXKERNELSIZE; kernel_pos++) {
+				/* Normalize the current weight. */
+				float fWeight = MATH_Divide(fSubpixelSet[kernel_pos],
+								    fWeightSum);
+
+				/* Convert the weight to fixed point and store in the table. */
+				if (fWeight == 0.0f)
+					kernel_array[kernel_pos] = 0x0000;
+				else if (fWeight >= 1.0f)
+					kernel_array[kernel_pos] = 0x4000;
+				else if (fWeight <= -1.0f)
+					kernel_array[kernel_pos] = 0xC000;
+				else
+					kernel_array[kernel_pos] =
+						(int16_t) MATH_Multiply(fWeight, 16384.0f);
+				weightSum += kernel_array[kernel_pos];
+			}
+
+			/* Adjust the fixed point coefficients. */
+			adjustCount = 0x4000 - weightSum;
+			if (adjustCount < 0) {
+				adjustCount = -adjustCount;
+				adjustment = -1;
+			} else {
+				adjustment = 1;
+			}
+
+			adjustFrom = (MAXKERNELSIZE - adjustCount) / 2;
+			for (kernel_pos = 0; kernel_pos < adjustCount; kernel_pos++) {
+				range = (MAXKERNELSIZE*subpixel_pos + adjustFrom + kernel_pos) *
+					sizeof(uint16_t);
+				if ((range >= 0) && (range < KERNELTABLESIZE))
+					kernel_array[adjustFrom + kernel_pos] += adjustment;
+				else
+					DRM_ERROR("%s failed\n", __func__);
+			}
+
+			kernel_array += MAXKERNELSIZE;
+
+			/* Advance to the next subpixel. */
+			f_subpixel_offset = MATH_Add(f_subpixel_offset, -f_subpixel_step);
+		}
+	} while (0);
+
+	return 0;
+}
+
+static void phytium_dc_scaling_config(struct drm_crtc *crtc,
+				     struct drm_crtc_state *old_state)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+	uint32_t group_offset = priv->dc_reg_base[phys_pipe];
+	uint32_t scale_factor_x, scale_factor_y, i;
+	uint32_t kernelStates[128];
+	struct filter_blit_array kernel_info_width;
+	void *tmp =  NULL;
+
+	if (mode->hdisplay != mode->crtc_hdisplay || mode->vdisplay != mode->crtc_vdisplay) {
+		phytium_crtc->src_width = mode->hdisplay;
+		phytium_crtc->src_height = mode->vdisplay;
+		phytium_crtc->dst_width = mode->crtc_hdisplay;
+		phytium_crtc->dst_height = mode->crtc_vdisplay;
+
+		phytium_crtc->dst_x = (mode->crtc_hdisplay - phytium_crtc->dst_width) / 2;
+		phytium_crtc->dst_y = (mode->crtc_vdisplay - phytium_crtc->dst_height) / 2;
+
+		scale_factor_x = dc_scaling_get_factor(phytium_crtc->src_width,
+								 phytium_crtc->dst_width);
+		scale_factor_y = dc_scaling_get_factor(phytium_crtc->src_height,
+								 phytium_crtc->dst_height);
+		if (scale_factor_y > (SCALE_FACTOR_Y_MAX << SCALE_FACTOR_SRC_OFFSET))
+			scale_factor_y = (SCALE_FACTOR_Y_MAX << SCALE_FACTOR_SRC_OFFSET);
+
+		phytium_writel_reg(priv, scale_factor_x & SCALE_FACTOR_X_MASK,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_SCALE_FACTOR_X);
+		phytium_writel_reg(priv, scale_factor_y & SCALE_FACTOR_Y_MASK,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_SCALE_FACTOR_Y);
+		phytium_writel_reg(priv, FRAMEBUFFER_TAP,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_SCALECONFIG);
+
+		tmp = kmalloc(KERNELSTATES, GFP_KERNEL);
+		if (!tmp) {
+			DRM_ERROR("malloc %ld failed\n", KERNELSTATES);
+			return;
+		}
+
+		memset(&kernel_info_width, 0, sizeof(struct filter_blit_array));
+		kernel_info_width.kernelStates = tmp;
+		memset(kernel_info_width.kernelStates, 0, KERNELSTATES);
+		kernel_neon_begin();
+		dc_calculate_sync_table(FRAMEBUFFER_HORIZONTAL_FILTER_TAP,
+					phytium_crtc->src_width,
+					phytium_crtc->dst_width,
+					&kernel_info_width);
+		memset(kernelStates, 0, sizeof(kernelStates));
+		memcpy(kernelStates, kernel_info_width.kernelStates + 1, KERNELSTATES - 4);
+		kernel_neon_end();
+		phytium_writel_reg(priv, HORI_FILTER_INDEX,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_HORI_FILTER_INDEX);
+		for (i = 0; i < 128; i++) {
+			phytium_writel_reg(priv, kernelStates[i],
+					   group_offset, PHYTIUM_DC_FRAMEBUFFER_HORI_FILTER);
+		}
+
+		memset(&kernel_info_width, 0, sizeof(struct filter_blit_array));
+		kernel_info_width.kernelStates = tmp;
+		memset(kernel_info_width.kernelStates, 0, KERNELSTATES);
+		kernel_neon_begin();
+		dc_calculate_sync_table(FRAMEBUFFER_FILTER_TAP, phytium_crtc->src_height,
+				     phytium_crtc->dst_height, &kernel_info_width);
+		memset(kernelStates, 0, sizeof(kernelStates));
+		memcpy(kernelStates, kernel_info_width.kernelStates + 1, KERNELSTATES - 4);
+		kernel_neon_end();
+		phytium_writel_reg(priv, VERT_FILTER_INDEX,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_VERT_FILTER_INDEX);
+		for (i = 0; i < 128; i++)
+			phytium_writel_reg(priv, kernelStates[i],
+					   group_offset, PHYTIUM_DC_FRAMEBUFFER_VERT_FILTER);
+		phytium_writel_reg(priv, INITIALOFFSET,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_INITIALOFFSET);
+		kfree(tmp);
+		phytium_crtc->scale_enable = true;
+	} else {
+		phytium_crtc->scale_enable = false;
+	}
+}
+
+static void phytium_crtc_gamma_set(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+	uint32_t group_offset = priv->dc_reg_base[phys_pipe];
+	uint32_t config = 0, data;
+	struct drm_crtc_state *state = crtc->state;
+	struct drm_color_lut *lut;
+	unsigned long flags;
+	uint32_t active_line = 0, timeout = 500;
+	int i;
+
+	if (state->gamma_lut) {
+		if (WARN((state->gamma_lut->length/sizeof(struct drm_color_lut) != GAMMA_INDEX_MAX),
+			"gamma size is not match\n"))
+			return;
+		lut = (struct drm_color_lut *)state->gamma_lut->data;
+
+		config = phytium_readl_reg(priv, group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+		if (config & FRAMEBUFFER_OUTPUT) {
+			struct drm_display_mode *mode = &state->adjusted_mode;
+			uint32_t frame_time;
+			uint32_t value_a, value_b;
+
+			frame_time = mode->crtc_vtotal * mode->crtc_htotal / mode->crtc_clock;
+			value_b = (frame_time - 2) * mode->crtc_vtotal;
+			local_irq_save(flags);
+			do {
+				active_line = phytium_readl_reg(priv, group_offset,
+								PHYTIUM_DC_LOCATION);
+				active_line = active_line >> LOVATION_Y_SHIFT;
+				value_a = (mode->crtc_vblank_end - mode->crtc_vblank_start +
+					   active_line) * frame_time;
+				if (value_a < value_b)
+					break;
+				local_irq_restore(flags);
+				udelay(1000);
+				timeout--;
+				local_irq_save(flags);
+			} while (timeout);
+
+			if (timeout == 0)
+				DRM_ERROR("wait gamma active line timeout\n");
+		}
+
+		phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DC_GAMMA_INDEX);
+		for (i = 0; i < GAMMA_INDEX_MAX; i++) {
+			data = ((lut[i].red >> 6) & GAMMA_RED_MASK) << GAMMA_RED_SHIFT;
+			data |= (((lut[i].green >> 6) & GAMMA_GREEN_MASK) << GAMMA_GREEN_SHIFT);
+			data |= (((lut[i].blue >> 6) & GAMMA_BLUE_MASK) << GAMMA_BLUE_SHIFT);
+			phytium_writel_reg(priv, data, group_offset, PHYTIUM_DC_GAMMA_DATA);
+		}
+
+		if (config & FRAMEBUFFER_OUTPUT)
+			local_irq_restore(flags);
+	}
+}
+
+static void phytium_crtc_gamma_init(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+	uint32_t group_offset = priv->dc_reg_base[phys_pipe];
+	struct drm_crtc_state *state = crtc->state;
+	uint32_t config = 0, data;
+	uint16_t *red, *green, *blue;
+	unsigned long flags;
+	uint32_t active_line = 0, timeout = 500;
+	int i;
+
+	if (WARN((crtc->gamma_size != GAMMA_INDEX_MAX), "gamma size is not match\n"))
+		return;
+
+	red = crtc->gamma_store;
+	green = red + crtc->gamma_size;
+	blue = green + crtc->gamma_size;
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	if (config & FRAMEBUFFER_OUTPUT) {
+		struct drm_display_mode *mode = &state->adjusted_mode;
+		uint32_t frame_time;
+		uint32_t value_a, value_b;
+
+		frame_time = mode->crtc_vtotal * mode->crtc_htotal / mode->crtc_clock;
+		value_b = (frame_time - 2) * mode->crtc_vtotal;
+		local_irq_save(flags);
+		do {
+			active_line = phytium_readl_reg(priv, group_offset, PHYTIUM_DC_LOCATION);
+			active_line = active_line >> LOVATION_Y_SHIFT;
+			value_a = (mode->crtc_vblank_end - mode->crtc_vblank_start +
+				   active_line) * frame_time;
+			if (value_a < value_b)
+				break;
+			local_irq_restore(flags);
+			udelay(1000);
+			timeout--;
+			local_irq_save(flags);
+		} while (timeout);
+
+		if (timeout == 0)
+			DRM_ERROR("wait gamma active line timeout\n");
+	}
+
+	phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DC_GAMMA_INDEX);
+	for (i = 0; i < GAMMA_INDEX_MAX; i++) {
+		data = ((*red++ >> 6) & GAMMA_RED_MASK) << GAMMA_RED_SHIFT;
+		data |= (((*green++ >> 6) & GAMMA_GREEN_MASK) << GAMMA_GREEN_SHIFT);
+		data |= (((*blue++ >> 6) & GAMMA_BLUE_MASK) << GAMMA_BLUE_SHIFT);
+		phytium_writel_reg(priv, data, group_offset, PHYTIUM_DC_GAMMA_DATA);
+	}
+
+	if (config & FRAMEBUFFER_OUTPUT)
+		local_irq_restore(flags);
+}
+
+static void phytium_crtc_destroy(struct drm_crtc *crtc)
+{
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+
+	drm_crtc_cleanup(crtc);
+	kfree(phytium_crtc);
+}
+
+struct drm_crtc_state *
+phytium_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
+{
+	struct phytium_crtc_state *phytium_crtc_state = NULL;
+
+	phytium_crtc_state = kmemdup(crtc->state, sizeof(*phytium_crtc_state),
+				     GFP_KERNEL);
+	if (!phytium_crtc_state)
+		return NULL;
+	__drm_atomic_helper_crtc_duplicate_state(crtc,
+						 &phytium_crtc_state->base);
+
+	return &phytium_crtc_state->base;
+}
+
+void
+phytium_crtc_atomic_destroy_state(struct drm_crtc *crtc,
+					       struct drm_crtc_state *state)
+{
+	struct phytium_crtc_state *phytium_crtc_state =
+					to_phytium_crtc_state(state);
+
+	phytium_crtc_state = to_phytium_crtc_state(state);
+	__drm_atomic_helper_crtc_destroy_state(state);
+	kfree(phytium_crtc_state);
+}
+
+static int phytium_enable_vblank(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+
+	phytium_writel_reg(priv, INT_ENABLE, priv->dc_reg_base[phys_pipe], PHYTIUM_DC_INT_ENABLE);
+
+	return 0;
+}
+
+static void phytium_disable_vblank(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+
+	phytium_writel_reg(priv, INT_DISABLE, priv->dc_reg_base[phys_pipe],
+			   PHYTIUM_DC_INT_ENABLE);
+}
+
+static const struct drm_crtc_funcs phytium_crtc_funcs = {
+	.gamma_set		= drm_atomic_helper_legacy_gamma_set,
+	.set_config		= drm_atomic_helper_set_config,
+	.destroy		= phytium_crtc_destroy,
+	.page_flip		= drm_atomic_helper_page_flip,
+	.reset			= drm_atomic_helper_crtc_reset,
+	.atomic_duplicate_state = phytium_crtc_atomic_duplicate_state,
+	.atomic_destroy_state   = phytium_crtc_atomic_destroy_state,
+	.enable_vblank          = phytium_enable_vblank,
+	.disable_vblank         = phytium_disable_vblank,
+};
+
+static void
+phytium_crtc_atomic_enable(struct drm_crtc *crtc,
+				     struct drm_crtc_state *old_state)
+{
+	struct drm_atomic_state *state = old_state->state;
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+	struct drm_connector_state *new_conn_state;
+	struct drm_connector *conn;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+	uint32_t group_offset = priv->dc_reg_base[phys_pipe];
+	int config = 0, i = 0;
+
+	for_each_new_connector_in_state(state, conn, new_conn_state, i) {
+		if (new_conn_state->crtc != crtc)
+			continue;
+
+		switch (conn->display_info.bpc) {
+		case 10:
+			phytium_crtc->bpc = DP_RGB101010;
+			break;
+		case 6:
+			phytium_crtc->bpc = DP_RGB666;
+			break;
+		default:
+			phytium_crtc->bpc = DP_RGB888;
+			break;
+		}
+	}
+
+	/* config pix clock */
+	phytium_crtc->dc_hw_config_pix_clock(crtc, mode->clock);
+
+	phytium_dc_scaling_config(crtc, old_state);
+	config = ((mode->crtc_hdisplay & HDISPLAY_END_MASK) << HDISPLAY_END_SHIFT)
+		| ((mode->crtc_htotal&HDISPLAY_TOTAL_MASK) << HDISPLAY_TOTAL_SHIFT);
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_HDISPLAY);
+	config = ((mode->crtc_hsync_start & HSYNC_START_MASK) << HSYNC_START_SHIFT)
+			| ((mode->crtc_hsync_end & HSYNC_END_MASK) << HSYNC_END_SHIFT)
+			| HSYNC_PULSE_ENABLED;
+	config |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : HSYNC_NEGATIVE;
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_HSYNC);
+	config = ((mode->crtc_vdisplay & VDISPLAY_END_MASK) << VDISPLAY_END_SHIFT)
+		| ((mode->crtc_vtotal & VDISPLAY_TOTAL_MASK) << VDISPLAY_TOTAL_SHIFT);
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_VDISPLAY);
+	config = ((mode->crtc_vsync_start & VSYNC_START_MASK) << VSYNC_START_SHIFT)
+		| ((mode->crtc_vsync_end & VSYNC_END_MASK) << VSYNC_END_SHIFT)
+		| VSYNC_PULSE_ENABLED;
+	config |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : VSYNC_NEGATIVE;
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_VSYNC);
+	config = PANEL_DATAENABLE_ENABLE | PANEL_DATA_ENABLE | PANEL_CLOCK_ENABLE;
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_PANEL_CONFIG);
+	config = phytium_crtc->bpc | OUTPUT_DP;
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_DP_CONFIG);
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+
+	if (crtc->state->active)
+		config |= FRAMEBUFFER_OUTPUT | FRAMEBUFFER_RESET;
+	else
+		config &= (~(FRAMEBUFFER_OUTPUT | FRAMEBUFFER_RESET));
+
+	if (phytium_crtc->scale_enable)
+		config |= FRAMEBUFFER_SCALE_ENABLE;
+	else
+		config &= (~FRAMEBUFFER_SCALE_ENABLE);
+
+	config |= FRAMEBUFFER_GAMMA_ENABLE;
+
+	if (crtc->state->gamma_lut)
+		phytium_crtc_gamma_set(crtc);
+	else
+		phytium_crtc_gamma_init(crtc);
+
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	drm_crtc_vblank_on(crtc);
+}
+
+static void
+phytium_crtc_atomic_disable(struct drm_crtc *crtc,
+				       struct drm_crtc_state *old_state)
+{
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+
+	drm_crtc_vblank_off(crtc);
+	phytium_crtc->dc_hw_disable(crtc);
+}
+
+static void phytium_crtc_update_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
+						       const struct drm_display_mode *native_mode)
+{
+	if (native_mode->clock == drm_mode->clock &&
+		native_mode->htotal == drm_mode->htotal &&
+		native_mode->vtotal == drm_mode->vtotal) {
+		drm_mode->crtc_hdisplay = native_mode->crtc_hdisplay;
+		drm_mode->crtc_vdisplay = native_mode->crtc_vdisplay;
+		drm_mode->crtc_clock = native_mode->crtc_clock;
+		drm_mode->crtc_hblank_start = native_mode->crtc_hblank_start;
+		drm_mode->crtc_hblank_end = native_mode->crtc_hblank_end;
+		drm_mode->crtc_hsync_start =  native_mode->crtc_hsync_start;
+		drm_mode->crtc_hsync_end = native_mode->crtc_hsync_end;
+		drm_mode->crtc_htotal = native_mode->crtc_htotal;
+		drm_mode->crtc_hskew = native_mode->crtc_hskew;
+		drm_mode->crtc_vblank_start = native_mode->crtc_vblank_start;
+		drm_mode->crtc_vblank_end = native_mode->crtc_vblank_end;
+		drm_mode->crtc_vsync_start = native_mode->crtc_vsync_start;
+		drm_mode->crtc_vsync_end = native_mode->crtc_vsync_end;
+		drm_mode->crtc_vtotal = native_mode->crtc_vtotal;
+	}
+}
+
+static int
+phytium_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
+{
+	struct drm_atomic_state *state = crtc_state->state;
+	struct drm_plane_state *new_plane_state = NULL;
+	int ret = 0;
+	struct drm_connector *connector;
+	struct drm_connector_state *new_con_state;
+	uint32_t i;
+	struct phytium_dp_device *phytium_dp = NULL;
+
+	for_each_new_connector_in_state(state, connector, new_con_state, i) {
+		if (new_con_state->crtc == crtc) {
+			phytium_dp = connector_to_dp_device(connector);
+			break;
+		}
+	}
+	if (phytium_dp)
+		phytium_crtc_update_timing_for_drm_display_mode(&crtc_state->adjusted_mode,
+								&phytium_dp->native_mode);
+
+	new_plane_state = drm_atomic_get_new_plane_state(crtc_state->state,
+							crtc->primary);
+	if (crtc_state->enable && new_plane_state && !new_plane_state->crtc) {
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	return 0;
+fail:
+	return ret;
+}
+
+static void
+phytium_crtc_atomic_begin(struct drm_crtc *crtc,
+				    struct drm_crtc_state *old_crtc_state)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe, config;
+	uint32_t group_offset = priv->dc_reg_base[phys_pipe];
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	if (config & FRAMEBUFFER_RESET) {
+		phytium_writel_reg(priv, config | FRAMEBUFFER_VALID_PENDING,
+				   group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	}
+}
+
+static void phytium_crtc_atomic_flush(struct drm_crtc *crtc,
+				struct drm_crtc_state *old_crtc_state)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	struct phytium_crtc_state *phytium_crtc_state = NULL;
+	int phys_pipe = phytium_crtc->phys_pipe, config;
+	uint32_t group_offset = priv->dc_reg_base[phys_pipe];
+
+	DRM_DEBUG_KMS("crtc->state active:%d enable:%d\n",
+		       crtc->state->active, crtc->state->enable);
+	phytium_crtc_state = to_phytium_crtc_state(crtc->state);
+
+	if (crtc->state->color_mgmt_changed)
+		phytium_crtc_gamma_set(crtc);
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	phytium_writel_reg(priv, config&(~FRAMEBUFFER_VALID_PENDING),
+			   group_offset, PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+
+	if (crtc->state->event) {
+		DRM_DEBUG_KMS("vblank->refcount:%d\n",
+			       atomic_read(&dev->vblank[0].refcount));
+		spin_lock_irq(&dev->event_lock);
+		if (drm_crtc_vblank_get(crtc) == 0)
+			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
+		else
+			drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+		spin_unlock_irq(&dev->event_lock);
+	}
+}
+
+static enum drm_mode_status
+phytium_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+
+	if (mode->crtc_clock > priv->info.crtc_clock_max)
+		return MODE_CLOCK_HIGH;
+
+	if (mode->hdisplay > priv->info.hdisplay_max)
+		return MODE_BAD_HVALUE;
+
+	if (mode->vdisplay > priv->info.vdisplay_max)
+		return MODE_BAD_VVALUE;
+
+	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+		return MODE_NO_INTERLACE;
+
+	return MODE_OK;
+}
+
+static const struct drm_crtc_helper_funcs phytium_crtc_helper_funcs = {
+	.mode_valid	= phytium_crtc_mode_valid,
+	.atomic_check	= phytium_crtc_atomic_check,
+	.atomic_begin	= phytium_crtc_atomic_begin,
+	.atomic_flush	= phytium_crtc_atomic_flush,
+	.atomic_enable	= phytium_crtc_atomic_enable,
+	.atomic_disable	= phytium_crtc_atomic_disable,
+};
+
+void phytium_crtc_resume(struct drm_device *drm_dev)
+{
+	struct drm_crtc *crtc;
+	struct phytium_crtc *phytium_crtc = NULL;
+
+	drm_for_each_crtc(crtc, drm_dev) {
+		phytium_crtc = to_phytium_crtc(crtc);
+		if (phytium_crtc->dc_hw_reset)
+			phytium_crtc->dc_hw_reset(crtc);
+		phytium_crtc_gamma_init(crtc);
+	}
+}
+
+int phytium_crtc_init(struct drm_device *dev, int phys_pipe)
+{
+	struct phytium_crtc *phytium_crtc;
+	struct phytium_crtc_state *phytium_crtc_state;
+	struct phytium_plane *phytium_primary_plane = NULL;
+	struct phytium_plane *phytium_cursor_plane = NULL;
+	struct phytium_display_private *priv = dev->dev_private;
+	int ret;
+
+	phytium_crtc = kzalloc(sizeof(*phytium_crtc), GFP_KERNEL);
+	if (!phytium_crtc) {
+		ret = -ENOMEM;
+		goto failed_malloc_crtc;
+	}
+
+	phytium_crtc_state = kzalloc(sizeof(*phytium_crtc_state), GFP_KERNEL);
+	if (!phytium_crtc_state) {
+		ret = -ENOMEM;
+		goto failed_malloc_crtc_state;
+	}
+
+	phytium_crtc_state->base.crtc = &phytium_crtc->base;
+	phytium_crtc->base.state = &phytium_crtc_state->base;
+	phytium_crtc->phys_pipe = phys_pipe;
+
+	if (IS_PX210(priv)) {
+		phytium_crtc->dc_hw_config_pix_clock = px210_dc_hw_config_pix_clock;
+		phytium_crtc->dc_hw_disable = px210_dc_hw_disable;
+		phytium_crtc->dc_hw_reset = NULL;
+		priv->dc_reg_base[phys_pipe] = PX210_DC_BASE(phys_pipe);
+		priv->dcreq_reg_base[phys_pipe] = PX210_DCREQ_BASE(phys_pipe);
+		priv->address_transform_base = PX210_ADDRESS_TRANSFORM_BASE;
+	} else if (IS_PE220X(priv)) {
+		phytium_crtc->dc_hw_config_pix_clock = pe220x_dc_hw_config_pix_clock;
+		phytium_crtc->dc_hw_disable = pe220x_dc_hw_disable;
+		phytium_crtc->dc_hw_reset = pe220x_dc_hw_reset;
+		priv->dc_reg_base[phys_pipe] = PE220X_DC_BASE(phys_pipe);
+		priv->dcreq_reg_base[phys_pipe] = 0x0;
+		priv->address_transform_base = PE220X_ADDRESS_TRANSFORM_BASE;
+	}
+
+	phytium_primary_plane = phytium_primary_plane_create(dev, phys_pipe);
+	if (IS_ERR(phytium_primary_plane)) {
+		ret = PTR_ERR(phytium_primary_plane);
+		DRM_ERROR("create primary plane failed, phys_pipe(%d)\n", phys_pipe);
+		goto failed_create_primary;
+	}
+
+	phytium_cursor_plane = phytium_cursor_plane_create(dev, phys_pipe);
+	if (IS_ERR(phytium_cursor_plane)) {
+		ret = PTR_ERR(phytium_cursor_plane);
+		DRM_ERROR("create cursor plane failed, phys_pipe(%d)\n", phys_pipe);
+		goto failed_create_cursor;
+	}
+
+	ret = drm_crtc_init_with_planes(dev, &phytium_crtc->base,
+					&phytium_primary_plane->base,
+					&phytium_cursor_plane->base,
+					&phytium_crtc_funcs,
+					"phys_pipe %d", phys_pipe);
+
+	if (ret) {
+		DRM_ERROR("init crtc with plane failed, phys_pipe(%d)\n", phys_pipe);
+		goto failed_crtc_init;
+	}
+	drm_crtc_helper_add(&phytium_crtc->base, &phytium_crtc_helper_funcs);
+	drm_crtc_vblank_reset(&phytium_crtc->base);
+	drm_mode_crtc_set_gamma_size(&phytium_crtc->base, GAMMA_INDEX_MAX);
+	drm_crtc_enable_color_mgmt(&phytium_crtc->base, 0, false, GAMMA_INDEX_MAX);
+	if (phytium_crtc->dc_hw_reset)
+		phytium_crtc->dc_hw_reset(&phytium_crtc->base);
+
+	return 0;
+
+failed_crtc_init:
+failed_create_cursor:
+	/* drm_mode_config_cleanup() will free any crtcs/planes already initialized */
+failed_create_primary:
+	kfree(phytium_crtc_state);
+failed_malloc_crtc_state:
+	kfree(phytium_crtc);
+failed_malloc_crtc:
+	return ret;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_crtc.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_crtc.h
new file mode 100644
index 00000000000000..86f894ba5d7068
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_crtc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_CRTC_H__
+#define __PHYTIUM_CRTC_H__
+
+struct phytium_crtc {
+	struct drm_crtc base;
+	int phys_pipe;
+	unsigned int bpc;
+
+	/* scale */
+	uint32_t src_width;
+	uint32_t src_height;
+	uint32_t dst_width;
+	uint32_t dst_height;
+	uint32_t dst_x;
+	uint32_t dst_y;
+	bool scale_enable;
+	bool reserve[3];
+
+	void (*dc_hw_config_pix_clock)(struct drm_crtc *crtc, int clock);
+	void (*dc_hw_disable)(struct drm_crtc *crtc);
+	void (*dc_hw_reset)(struct drm_crtc *crtc);
+};
+
+struct phytium_crtc_state {
+	struct drm_crtc_state base;
+};
+
+#define to_phytium_crtc(x) container_of(x, struct phytium_crtc, base)
+#define to_phytium_crtc_state(x) container_of(x, struct phytium_crtc_state, base)
+
+void phytium_crtc_resume(struct drm_device *drm_dev);
+int phytium_crtc_init(struct drm_device *dev, int pipe);
+#endif /* __PHYTIUM_CRTC_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_debugfs.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_debugfs.c
new file mode 100644
index 00000000000000..13657a76812f61
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_debugfs.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <drm/drm_file.h>
+#include "phytium_display_drv.h"
+#include "phytium_dp.h"
+#include "phytium_reg.h"
+
+const char *const mem_state[PHYTIUM_MEM_STATE_TYPE_COUNT] = {
+	"Memory_Vram_Total",
+	"Memory_Vram_Alloc",
+	"Memory_System_Carveout_Total",
+	"Memory_System_Carveout_Alloc",
+	"Memory_System_Alloc",
+};
+
+static ssize_t
+phytium_dp_register_write(struct file *filp,
+				 const char __user *ubuf,
+				 size_t len,
+				 loff_t *ppos)
+{
+	char tmp[16];
+
+	if (len >= sizeof(tmp))
+		return -EINVAL;
+
+	memset(tmp, 0, sizeof(tmp));
+	if (copy_from_user(tmp, ubuf, len))
+		return -EFAULT;
+	tmp[len] = '\0';
+
+	return len;
+}
+
+static int phytium_dp_register_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_M_VID,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_M_VID));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_N_VID,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_N_VID));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_TRANSFER_UNIT_SIZE,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_TRANSFER_UNIT_SIZE));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_DATA_COUNT,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_DATA_COUNT));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_MAIN_LINK_HTOTAL,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_HTOTAL));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_MAIN_LINK_HRES,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_HRES));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_MAIN_LINK_HSWIDTH,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_HSWIDTH));
+	seq_printf(m, "addr:h0x%08x	h0x%08x\n", PHYTIUM_DP_MAIN_LINK_HSTART,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_HSTART));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_VTOTAL,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_VTOTAL));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_VRES,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_VRES));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_VSWIDTH,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_VSWIDTH));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_VSTART,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_VSTART));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_POLARITY,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_POLARITY));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_MISC0,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_MISC0));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_MAIN_LINK_MISC1,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_MAIN_LINK_MISC1));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_USER_SYNC_POLARITY,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_USER_SYNC_POLARITY));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_VIDEO_STREAM_ENABLE,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_VIDEO_STREAM_ENABLE));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SECONDARY_STREAM_ENABLE,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE));
+	seq_puts(m, "audio:\n");
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_INPUT_SELECT,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_INPUT_SELECT));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_DIRECT_CLKDIV,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_DIRECT_CLKDIV));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CHANNEL_COUNT,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CHANNEL_COUNT));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CHANNEL_MAP,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CHANNEL_MAP));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_DATA_WINDOW,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_DATA_WINDOW));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CS_CATEGORY_CODE,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CS_CATEGORY_CODE));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_MAUD,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_MAUD));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_NAUD,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_NAUD));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CLOCK_MODE,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CLOCK_MODE));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CS_SOURCE_FORMAT,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CS_SOURCE_FORMAT));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CS_LENGTH_ORIG_FREQ,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CS_LENGTH_ORIG_FREQ));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_CS_FREQ_CLOCK_ACCURACY,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_CS_FREQ_CLOCK_ACCURACY));
+	seq_printf(m, "addr:h'0x%08x	h'0x%08x\n", PHYTIUM_DP_SEC_AUDIO_ENABLE,
+		   phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_AUDIO_ENABLE));
+
+	return 0;
+}
+
+static int phytium_dp_register_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_dp_register_show, inode->i_private);
+}
+
+static const struct file_operations phytium_dp_register_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_dp_register_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = phytium_dp_register_write,
+};
+
+static ssize_t
+phytium_dp_trigger_train_fail_write(struct file *filp,
+				 const char __user *ubuf,
+				 size_t len,
+				 loff_t *ppos)
+{
+	struct seq_file *m = filp->private_data;
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	char tmp[16];
+
+	if (len >= sizeof(tmp))
+		return -EINVAL;
+
+	memset(tmp, 0, sizeof(tmp));
+	if (copy_from_user(tmp, ubuf, len))
+		return -EFAULT;
+	tmp[len] = '\0';
+
+	if (kstrtouint(tmp, 10, &phytium_dp->trigger_train_fail) != 0)
+		return -EINVAL;
+
+	return len;
+}
+
+static int phytium_dp_trigger_train_fail_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	seq_printf(m, "trigger_train_fail: %d\n", phytium_dp->trigger_train_fail);
+	seq_printf(m, "train_retry_count: %d\n", phytium_dp->train_retry_count);
+
+	return 0;
+}
+
+static int phytium_dp_trigger_train_fail_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_dp_trigger_train_fail_show, inode->i_private);
+}
+
+static const struct file_operations phytium_dp_trigger_train_fail_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_dp_trigger_train_fail_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = phytium_dp_trigger_train_fail_write,
+};
+
+static int phytium_edp_backlight_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	if (!phytium_dp->is_edp)
+		return -ENODEV;
+
+	mutex_lock(&phytium_dp->panel.panel_lock);
+	seq_printf(m, "backlight: %s\n", phytium_dp->panel.backlight_enabled?"enabled":"disabled");
+	mutex_unlock(&phytium_dp->panel.panel_lock);
+
+	return 0;
+}
+
+static int phytium_edp_backlight_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_edp_backlight_show, inode->i_private);
+}
+
+static const struct file_operations phytium_edp_backlight_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_edp_backlight_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int phytium_edp_power_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	if (!phytium_dp->is_edp)
+		return -ENODEV;
+
+	mutex_lock(&phytium_dp->panel.panel_lock);
+	seq_printf(m, "power: %s\n", phytium_dp->panel.power_enabled?"enabled":"disabled");
+	mutex_unlock(&phytium_dp->panel.panel_lock);
+
+	return 0;
+}
+
+static int phytium_edp_power_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_edp_power_show, inode->i_private);
+}
+
+static const struct file_operations phytium_edp_power_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_edp_power_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+struct dpcd_block {
+	/* DPCD dump start address. */
+	unsigned int offset;
+	/* DPCD dump end address, inclusive. If unset, .size will be used. */
+	unsigned int end;
+	/* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
+	size_t size;
+	/* Only valid for eDP. */
+	bool edp;
+};
+
+static const struct dpcd_block phytium_dpcd_debug[] = {
+	{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
+	{ .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
+	{ .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
+	{ .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
+	{ .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
+	{ .offset = DP_SET_POWER },
+	{ .offset = DP_EDP_DPCD_REV },
+	{ .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
+	{ .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
+	{ .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
+	{ .offset = DP_DEVICE_SERVICE_IRQ_VECTOR, .size = 1 },
+	{ .offset = DP_TEST_REQUEST, .end = DP_TEST_PATTERN },
+};
+
+static int phytium_dpcd_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	uint8_t buf[16], i;
+	ssize_t err;
+
+	if (connector->status != connector_status_connected)
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(phytium_dpcd_debug); i++) {
+		const struct dpcd_block *b = &phytium_dpcd_debug[i];
+		size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
+
+		if (WARN_ON(size > sizeof(buf)))
+			continue;
+
+		err = drm_dp_dpcd_read(&phytium_dp->aux, b->offset, buf, size);
+		if (err <= 0) {
+			DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
+				   size, b->offset, err);
+			continue;
+		}
+
+		seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
+	}
+
+	return 0;
+}
+
+static int phytium_dpcd_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_dpcd_show, inode->i_private);
+}
+
+static const struct file_operations phytium_dpcd_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_dpcd_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static ssize_t
+phytium_dp_state_write(struct file *filp,
+				 const char __user *ubuf,
+				 size_t len,
+				 loff_t *ppos)
+{
+	char tmp[16];
+
+	if (len >= sizeof(tmp))
+		return -EINVAL;
+
+	memset(tmp, 0, sizeof(tmp));
+	if (copy_from_user(tmp, ubuf, len))
+		return -EFAULT;
+	tmp[len] = '\0';
+
+	return len;
+}
+
+static int phytium_dp_state_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	seq_printf(m, "port number: %d\n", phytium_dp->port);
+	seq_printf(m, "source_max_lane_count: %d\n", phytium_dp->source_max_lane_count);
+	seq_printf(m, "max_source_rates: %d\n",
+		   phytium_dp->source_rates[phytium_dp->num_source_rates-1]);
+	if (connector->status == connector_status_connected) {
+		seq_printf(m, "sink_max_lane_count: %d\n", phytium_dp->sink_max_lane_count);
+		seq_printf(m, "max_sink_rates: %d\n",
+			   phytium_dp->sink_rates[phytium_dp->num_sink_rates-1]);
+		seq_printf(m, "link_rate: %d\n", phytium_dp->link_rate);
+		seq_printf(m, "link_lane_count: %d\n", phytium_dp->link_lane_count);
+		seq_printf(m, "train_set[0]: %d\n", phytium_dp->train_set[0]);
+		seq_printf(m, "has_audio: %s\n", phytium_dp->has_audio?"yes":"no");
+	}
+
+	return 0;
+}
+
+static int phytium_dp_state_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_dp_state_show, inode->i_private);
+}
+
+static const struct file_operations phytium_dp_state_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_dp_state_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = phytium_dp_state_write,
+};
+
+static const struct phytium_debugfs_files {
+	const char *name;
+	const struct file_operations *fops;
+} phytium_debugfs_connector_files[] = {
+	{"dp_state", &phytium_dp_state_fops},
+	{"dpcd", &phytium_dpcd_fops},
+	{"dp_register", &phytium_dp_register_fops},
+	{"dp_trigger_train_fail", &phytium_dp_trigger_train_fail_fops},
+};
+
+static const struct phytium_debugfs_files phytium_edp_debugfs_connector_files[] = {
+	{"edp_power", &phytium_edp_power_fops},
+	{"edp_backlight", &phytium_edp_backlight_fops},
+};
+
+int phytium_debugfs_connector_add(struct drm_connector *connector)
+{
+	struct dentry *root = connector->debugfs_entry;
+	struct dentry *ent;
+	int i;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	if (!root)
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(phytium_debugfs_connector_files); i++) {
+		ent = debugfs_create_file(phytium_debugfs_connector_files[i].name,
+					  0644,
+					  root,
+					  connector,
+					  phytium_debugfs_connector_files[i].fops);
+		if (!ent)
+			return -ENOMEM;
+	}
+
+	if (phytium_dp->is_edp)
+		for (i = 0; i < ARRAY_SIZE(phytium_edp_debugfs_connector_files); i++) {
+			ent = debugfs_create_file(phytium_edp_debugfs_connector_files[i].name,
+						  0644,
+						  root,
+						  connector,
+						  phytium_edp_debugfs_connector_files[i].fops);
+			if (!ent)
+				return -ENOMEM;
+		}
+
+	return 0;
+}
+
+static int phytium_mem_state_show(struct seq_file *m, void *data)
+{
+	struct phytium_display_private *priv = m->private;
+	uint8_t i;
+
+	for (i = 0; i < ARRAY_SIZE(mem_state); i++)
+		seq_printf(m, "%-34s %10lld\n", mem_state[i], priv->mem_state[i]);
+
+	return 0;
+}
+
+static int phytium_mem_state_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, phytium_mem_state_show, inode->i_private);
+}
+
+static const struct file_operations phytium_mem_state_fops = {
+	.owner = THIS_MODULE,
+	.open = phytium_mem_state_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static const struct phytium_debugfs_files phytium_debugfs_display_files[] = {
+	{"mem_state", &phytium_mem_state_fops},
+};
+
+int phytium_debugfs_display_register(struct phytium_display_private *priv)
+{
+	struct drm_minor *minor = priv->dev->primary;
+	struct dentry *root = minor->debugfs_root;
+	struct dentry *ent;
+
+	if (!root)
+		return -ENODEV;
+
+	ent = debugfs_create_file(phytium_debugfs_display_files[0].name,
+				  0644,
+				  root,
+				  priv,
+				  phytium_debugfs_display_files[0].fops);
+	if (!ent)
+		return -ENOMEM;
+
+	return 0;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_debugfs.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_debugfs.h
new file mode 100644
index 00000000000000..aa8e2922ec257e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_debugfs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_DEBUGFS_H__
+#define __PHYTIUM_DEBUGFS_H__
+
+int phytium_debugfs_connector_add(struct drm_connector *connector);
+int phytium_debugfs_display_register(struct phytium_display_private *priv);
+
+#endif /* __PHYTIUM_DEBUGFS_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_display_drv.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_display_drv.c
new file mode 100644
index 00000000000000..d3c654b427c09b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_display_drv.c
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_irq.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_drv.h>
+#include <linux/atomic.h>
+#include <drm/drm_atomic.h>
+#include <linux/workqueue.h>
+#include <linux/pci.h>
+#include "phytium_display_drv.h"
+#include "phytium_plane.h"
+#include "phytium_crtc.h"
+#include "phytium_dp.h"
+#include "phytium_gem.h"
+#include "phytium_fb.h"
+#include "phytium_fbdev.h"
+#include "phytium_reg.h"
+#include "phytium_pci.h"
+#include "phytium_platform.h"
+#include "phytium_debugfs.h"
+
+int dc_fake_mode_enable;
+module_param(dc_fake_mode_enable, int, 0644);
+MODULE_PARM_DESC(dc_fake_mode_enable, "Enable DC fake mode (0-disabled; 1-enabled; default-0)");
+
+int dc_fast_training_check = 1;
+module_param(dc_fast_training_check, int, 0644);
+MODULE_PARM_DESC(dc_fast_training_check, "Check dp fast training (0-disabled; 1-enabled; default-1)");
+
+int num_source_rates = 4;
+module_param(num_source_rates, int, 0644);
+MODULE_PARM_DESC(num_source_rates, "set the source max rates (1-1.62Gbps; 2-2.7Gbps; 3-5.4Gbps; 4-8.1Gbps; default-4)");
+
+int source_max_lane_count = 4;
+module_param(source_max_lane_count, int, 0644);
+MODULE_PARM_DESC(source_max_lane_count, "set the source lane count (1-1lane; 2-2lane; 4-4lane; default-4)");
+
+int link_dynamic_adjust;
+module_param(link_dynamic_adjust, int, 0644);
+MODULE_PARM_DESC(link_dynamic_adjust, "dynamic select the train pamameter according to the display mode (0-disabled; 1-enabled; default-1)");
+
+int phytium_wait_cmd_done(struct phytium_display_private *priv,
+				    uint32_t register_offset,
+				    uint32_t request_bit,
+				    uint32_t reply_bit)
+{
+	int timeout = 500, config = 0, ret = 0;
+
+	do {
+		mdelay(1);
+		timeout--;
+		config = phytium_readl_reg(priv, 0, register_offset);
+	} while ((!(config & reply_bit)) && timeout);
+
+	phytium_writel_reg(priv, config & (~request_bit), 0, register_offset);
+
+	if (timeout == 0) {
+		DRM_ERROR("wait cmd reply timeout\n");
+		ret = -EBUSY;
+	} else {
+		timeout = 500;
+		do {
+			mdelay(1);
+			timeout--;
+			config = phytium_readl_reg(priv, 0, register_offset);
+		} while ((config & reply_bit) && timeout);
+		if (timeout == 0) {
+			DRM_ERROR("clear cmd timeout\n");
+			ret = -EBUSY;
+		}
+	}
+	mdelay(5);
+
+	return ret;
+}
+
+static void phytium_irq_preinstall(struct drm_device *dev)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	int i, status;
+
+	for_each_pipe_masked(priv, i) {
+		status = phytium_readl_reg(priv, priv->dc_reg_base[i], PHYTIUM_DC_INT_STATUS);
+		phytium_writel_reg(priv, INT_DISABLE, priv->dc_reg_base[i], PHYTIUM_DC_INT_ENABLE);
+	}
+}
+
+static void phytium_irq_uninstall(struct drm_device *dev)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	int i, status;
+
+	for_each_pipe_masked(priv, i) {
+		status = phytium_readl_reg(priv, priv->dc_reg_base[i], PHYTIUM_DC_INT_STATUS);
+		phytium_writel_reg(priv, INT_DISABLE, priv->dc_reg_base[i], PHYTIUM_DC_INT_ENABLE);
+	}
+}
+
+static irqreturn_t phytium_display_irq_handler(int irq, void *data)
+{
+	struct drm_device *dev = data;
+	struct phytium_display_private *priv = dev->dev_private;
+	bool enabled = 0;
+	int i = 0, virt_pipe = 0;
+	irqreturn_t ret = IRQ_NONE, ret1 = IRQ_NONE;
+
+	for_each_pipe_masked(priv, i) {
+		enabled = phytium_readl_reg(priv, priv->dc_reg_base[i], PHYTIUM_DC_INT_STATUS);
+		if (enabled & INT_STATUS) {
+			virt_pipe = phytium_get_virt_pipe(priv, i);
+			if (virt_pipe < 0)
+				return IRQ_NONE;
+			drm_handle_vblank(dev, virt_pipe);
+			ret = IRQ_HANDLED;
+			if (priv->dc_hw_clear_msi_irq)
+				priv->dc_hw_clear_msi_irq(priv, i);
+		}
+	}
+
+	ret1 = phytium_dp_hpd_irq_handler(priv);
+	if (ret == IRQ_HANDLED || ret1 == IRQ_HANDLED)
+		return IRQ_HANDLED;
+
+	return IRQ_NONE;
+}
+
+static const struct drm_mode_config_funcs phytium_mode_funcs = {
+	.fb_create		= phytium_fb_create,
+	.output_poll_changed	= drm_fb_helper_output_poll_changed,
+	.atomic_check		= drm_atomic_helper_check,
+	.atomic_commit		= drm_atomic_helper_commit,
+};
+
+static void phytium_atomic_commit_tail(struct drm_atomic_state *state)
+{
+	struct drm_device *dev = state->dev;
+
+	drm_atomic_helper_commit_modeset_disables(dev, state);
+	drm_atomic_helper_commit_planes(dev, state, false);
+	drm_atomic_helper_commit_modeset_enables(dev, state);
+	drm_atomic_helper_commit_hw_done(state);
+	drm_atomic_helper_wait_for_flip_done(dev, state);
+	drm_atomic_helper_cleanup_planes(dev, state);
+}
+
+static struct drm_mode_config_helper_funcs phytium_mode_config_helpers = {
+	.atomic_commit_tail = phytium_atomic_commit_tail,
+};
+
+static int phytium_modeset_init(struct drm_device *dev)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	int i = 0, ret;
+
+	drm_mode_config_init(dev);
+	dev->mode_config.min_width = 0;
+	dev->mode_config.min_height = 0;
+	dev->mode_config.max_width = 16384;
+	dev->mode_config.max_height = 16384;
+	dev->mode_config.cursor_width = 32;
+	dev->mode_config.cursor_height = 32;
+
+	dev->mode_config.preferred_depth = 24;
+	dev->mode_config.prefer_shadow = 1;
+	dev->mode_config.allow_fb_modifiers = true;
+
+	dev->mode_config.funcs	= &phytium_mode_funcs;
+	dev->mode_config.helper_private = &phytium_mode_config_helpers;
+
+	for_each_pipe_masked(priv, i) {
+		ret = phytium_crtc_init(dev, i);
+		if (ret) {
+			DRM_ERROR("phytium_crtc_init(pipe %d) return failed\n", i);
+			goto failed_crtc_init;
+		}
+	}
+
+	for_each_pipe_masked(priv, i) {
+		ret = phytium_dp_init(dev, i);
+		if (ret) {
+			DRM_ERROR("phytium_dp_init(pipe %d) return failed\n", i);
+			goto failed_dp_init;
+		}
+	}
+
+	drm_mode_config_reset(dev);
+
+	return 0;
+failed_dp_init:
+failed_crtc_init:
+	drm_mode_config_cleanup(dev);
+	return ret;
+}
+
+int phytium_get_virt_pipe(struct phytium_display_private *priv, int phys_pipe)
+{
+	int i = 0;
+	int virt_pipe = 0;
+
+	for_each_pipe_masked(priv, i) {
+		if (i != phys_pipe)
+			virt_pipe++;
+		else
+			return virt_pipe;
+	}
+
+	DRM_ERROR("%s %d failed\n", __func__, phys_pipe);
+	return -EINVAL;
+}
+
+int phytium_get_phys_pipe(struct phytium_display_private *priv, int virt_pipe)
+{
+	int i = 0;
+	int tmp = 0;
+
+	for_each_pipe_masked(priv, i) {
+		if (tmp != virt_pipe)
+			tmp++;
+		else
+			return i;
+	}
+
+	DRM_ERROR("%s %d failed\n", __func__, virt_pipe);
+	return -EINVAL;
+}
+
+static int phytium_display_load(struct drm_device *dev, unsigned long flags)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	int ret = 0;
+
+	ret = drm_vblank_init(dev, priv->info.num_pipes);
+	if (ret) {
+		DRM_ERROR("vblank init failed\n");
+		goto failed_vblank_init;
+	}
+
+	ret = phytium_modeset_init(dev);
+	if (ret) {
+		DRM_ERROR("phytium_modeset_init failed\n");
+		goto failed_modeset_init;
+	}
+
+	if (priv->support_memory_type & MEMORY_TYPE_VRAM)
+		priv->vram_hw_init(priv);
+
+	ret = drm_irq_install(dev, priv->irq);
+	if (ret) {
+		DRM_ERROR("install irq failed\n");
+		goto failed_irq_install;
+	}
+
+	ret = phytium_drm_fbdev_init(dev);
+	if (ret)
+		DRM_ERROR("failed to init dev\n");
+
+	phytium_debugfs_display_register(priv);
+
+	return ret;
+
+failed_irq_install:
+	drm_mode_config_cleanup(dev);
+failed_modeset_init:
+failed_vblank_init:
+	return ret;
+}
+
+static void phytium_display_unload(struct drm_device *dev)
+{
+	phytium_drm_fbdev_fini(dev);
+	drm_irq_uninstall(dev);
+	drm_mode_config_cleanup(dev);
+}
+
+static const struct drm_ioctl_desc phytium_ioctls[] = {
+	/* for test, none so far */
+};
+
+static const struct file_operations phytium_drm_driver_fops = {
+	.owner		= THIS_MODULE,
+	.open		= drm_open,
+	.release	= drm_release,
+	.unlocked_ioctl	= drm_ioctl,
+	.compat_ioctl	= drm_compat_ioctl,
+	.poll		= drm_poll,
+	.read		= drm_read,
+	.llseek		= no_llseek,
+	.mmap		= phytium_gem_mmap,
+};
+
+struct drm_driver phytium_display_drm_driver = {
+	.driver_features	= DRIVER_HAVE_IRQ   |
+				  DRIVER_MODESET    |
+				  DRIVER_ATOMIC     |
+				  DRIVER_GEM,
+	.load			= phytium_display_load,
+	.unload			= phytium_display_unload,
+	.lastclose		= drm_fb_helper_lastclose,
+	.irq_handler		= phytium_display_irq_handler,
+	.irq_preinstall		= phytium_irq_preinstall,
+	.irq_uninstall		= phytium_irq_uninstall,
+	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
+	.gem_prime_export	= drm_gem_prime_export,
+	.gem_prime_import	= drm_gem_prime_import,
+	.gem_prime_import_sg_table = phytium_gem_prime_import_sg_table,
+	.gem_prime_mmap		= phytium_gem_prime_mmap,
+	.dumb_create		= phytium_gem_dumb_create,
+	.dumb_destroy		= phytium_gem_dumb_destroy,
+	.ioctls			= phytium_ioctls,
+	.num_ioctls		= ARRAY_SIZE(phytium_ioctls),
+	.fops			= &phytium_drm_driver_fops,
+	.name			= DRV_NAME,
+	.desc			= DRV_DESC,
+	.date			= DRV_DATE,
+	.major			= DRV_MAJOR,
+	.minor			= DRV_MINOR,
+};
+
+static void phytium_display_shutdown(struct drm_device *dev)
+{
+	drm_atomic_helper_shutdown(dev);
+}
+
+static int phytium_display_pm_suspend(struct drm_device *dev)
+{
+	struct drm_atomic_state *state;
+	struct phytium_display_private *priv = dev->dev_private;
+	int ret, ret1;
+
+	phytium_dp_hpd_irq_setup(dev, false);
+	cancel_work_sync(&priv->hotplug_work);
+	drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 1);
+	state = drm_atomic_helper_suspend(dev);
+	if (IS_ERR(state)) {
+		DRM_ERROR("drm_atomic_helper_suspend failed: %ld\n", PTR_ERR(state));
+		ret = PTR_ERR(state);
+		goto suspend_failed;
+	}
+	dev->mode_config.suspend_state = state;
+	ret = phytium_gem_suspend(dev);
+	if (ret) {
+		DRM_ERROR("phytium_gem_suspend failed: %d\n", ret);
+		goto gem_suspend_failed;
+	}
+
+	return 0;
+
+gem_suspend_failed:
+	ret1 = drm_atomic_helper_resume(dev, dev->mode_config.suspend_state);
+	if (ret1)
+		DRM_ERROR("Failed to resume (%d)\n", ret1);
+	dev->mode_config.suspend_state = NULL;
+suspend_failed:
+	drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
+	phytium_dp_hpd_irq_setup(dev, true);
+
+	return ret;
+}
+
+static int phytium_display_pm_resume(struct drm_device *dev)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	int ret = 0;
+
+	if (WARN_ON(!dev->mode_config.suspend_state))
+		return -EINVAL;
+
+	ret = phytium_dp_resume(dev);
+	if (ret)
+		return -EIO;
+
+	phytium_crtc_resume(dev);
+	phytium_gem_resume(dev);
+
+	if (priv->support_memory_type & MEMORY_TYPE_VRAM)
+		priv->vram_hw_init(priv);
+
+	ret = drm_atomic_helper_resume(dev, dev->mode_config.suspend_state);
+	if (ret) {
+		DRM_ERROR("Failed to resume (%d)\n", ret);
+		return ret;
+	}
+
+	dev->mode_config.suspend_state = NULL;
+	drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
+	phytium_dp_hpd_irq_setup(dev, true);
+
+	return 0;
+}
+
+void phytium_display_private_init(struct phytium_display_private *priv, struct drm_device *dev)
+{
+	INIT_LIST_HEAD(&priv->gem_list_head);
+	spin_lock_init(&priv->hotplug_irq_lock);
+	INIT_WORK(&priv->hotplug_work, phytium_dp_hpd_work_func);
+	memset(priv->mem_state, 0, sizeof(priv->mem_state));
+	priv->dev = dev;
+	priv->display_shutdown = phytium_display_shutdown;
+	priv->display_pm_suspend = phytium_display_pm_suspend;
+	priv->display_pm_resume = phytium_display_pm_resume;
+}
+
+static int __init phytium_display_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&phytium_platform_driver);
+	if (ret)
+		return ret;
+
+	ret = pci_register_driver(&phytium_pci_driver);
+
+	return ret;
+}
+
+static void __exit phytium_display_exit(void)
+{
+	pci_unregister_driver(&phytium_pci_driver);
+
+	platform_driver_unregister(&phytium_platform_driver);
+}
+
+module_init(phytium_display_init);
+module_exit(phytium_display_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Yang Xun <yangxun@phytium.com.cn>");
+MODULE_AUTHOR("Shaojun Yang <yangshaojun@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium Display Controller");
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_display_drv.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_display_drv.h
new file mode 100644
index 00000000000000..ee1d0e0fab86f9
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_display_drv.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_DISPLAY_DRV_H__
+#define __PHYTIUM_DISPLAY_DRV_H__
+
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+#include <drm/drmP.h>
+#endif
+#include <drm/drm_print.h>
+#include <drm/drm_fb_helper.h>
+
+#define DEBUG_LOG 0
+
+#define PHYTIUM_FORMAT_MAX_PLANE	3
+#define DP_MAX_DOWNSTREAM_PORTS		0x10
+
+#define DRV_NAME	"dc"
+#define DRV_DESC	"phytium dc"
+#define DRV_DATE	"20201220"
+#define DRV_MAJOR	1
+#define DRV_MINOR	1
+
+/* come from GPU */
+#define	DRM_FORMAT_MOD_VENDOR_PHYTIUM	0x92
+
+/* dc:mode0 8x8 16bpp  gpu: FBCDC_8X8_V10 */
+#define	DRM_FORMAT_MOD_PHYTIUM_TILE_MODE0_FBCDC	fourcc_mod_code(PHYTIUM, 21)
+/* dc:mode3 8x4 32bpp  gpu: FBCDC_16X4_v10 */
+#define	DRM_FORMAT_MOD_PHYTIUM_TILE_MODE3_FBCDC	fourcc_mod_code(PHYTIUM, 22)
+
+#define	PIPE_MASK_SHIFT			0x0
+#define	PIPE_MASK_MASK			0x7
+#define	EDP_MASK_SHIFT			0x3
+#define	EDP_MASK_MASK			0x7
+
+enum phytium_platform {
+	PHYTIUM_PLATFORM_UNINITIALIZED = 0,
+	PHYTIUM_PLATFORM_PX210,
+	PHYTIUM_PLATFORM_PE220X,
+};
+
+enum phytium_mem_state_type {
+	PHYTIUM_MEM_VRAM_TOTAL = 0,
+	PHYTIUM_MEM_VRAM_ALLOC,
+	PHYTIUM_MEM_SYSTEM_CARVEOUT_TOTAL,
+	PHYTIUM_MEM_SYSTEM_CARVEOUT_ALLOC,
+	PHYTIUM_MEM_SYSTEM_UNIFIED_ALLOC,
+	PHYTIUM_MEM_STATE_TYPE_COUNT,
+};
+
+#define MEMORY_TYPE_VRAM		0x1
+#define MEMORY_TYPE_SYSTEM_CARVEOUT	0x2
+#define MEMORY_TYPE_SYSTEM_UNIFIED	0x4
+
+#define IS_PLATFORM(priv, p) ((priv)->info.platform_mask & BIT(p))
+
+#define IS_PX210(priv)		IS_PLATFORM(priv, PHYTIUM_PLATFORM_PX210)
+#define IS_PE220X(priv)		IS_PLATFORM(priv, PHYTIUM_PLATFORM_PE220X)
+
+struct phytium_device_info {
+	unsigned char platform_mask;
+	unsigned char pipe_mask;
+	unsigned char num_pipes;
+	unsigned char total_pipes;
+	unsigned char edp_mask;
+	unsigned int crtc_clock_max;
+	unsigned int hdisplay_max;
+	unsigned int vdisplay_max;
+	unsigned int backlight_max;
+	unsigned long address_mask;
+};
+
+struct phytium_display_private {
+	/* hw */
+	void __iomem *regs;
+	void __iomem *vram_addr;
+	struct phytium_device_info info;
+	char support_memory_type;
+	char reserve[3];
+	uint32_t dc_reg_base[3];
+	uint32_t dcreq_reg_base[3];
+	uint32_t dp_reg_base[3];
+	uint32_t address_transform_base;
+	uint32_t phy_access_base[3];
+
+	/* drm */
+	struct drm_device *dev;
+	int irq;
+
+	/* fb_dev */
+	struct drm_fb_helper fbdev_helper;
+	struct phytium_gem_object *fbdev_phytium_gem;
+
+	int save_reg[3];
+	struct list_head gem_list_head;
+
+	struct work_struct hotplug_work;
+	spinlock_t hotplug_irq_lock;
+
+	void (*vram_hw_init)(struct phytium_display_private *priv);
+	void (*display_shutdown)(struct drm_device *dev);
+	int (*display_pm_suspend)(struct drm_device *dev);
+	int (*display_pm_resume)(struct drm_device *dev);
+	void (*dc_hw_clear_msi_irq)(struct phytium_display_private *priv, uint32_t phys_pipe);
+	int (*dc_hw_fb_format_check)(const struct drm_mode_fb_cmd2 *mode_cmd, int count);
+
+	struct gen_pool *memory_pool;
+	resource_size_t pool_phys_addr;
+	resource_size_t pool_size;
+	void *pool_virt_addr;
+	uint64_t mem_state[PHYTIUM_MEM_STATE_TYPE_COUNT];
+
+	/* DMA info */
+	int dma_inited;
+	struct dma_chan *dma_chan;
+};
+
+static inline unsigned int
+phytium_readl_reg(struct phytium_display_private *priv, uint32_t group_offset, uint32_t reg_offset)
+{
+	unsigned int data;
+
+	data = readl(priv->regs + group_offset + reg_offset);
+#if DEBUG_LOG
+	pr_info("Read 32'h%08x 32'h%08x\n", group_offset + reg_offset, data);
+#endif
+	return data;
+}
+
+static inline void
+phytium_writel_reg(struct phytium_display_private *priv, uint32_t data,
+			    uint32_t group_offset, uint32_t reg_offset)
+{
+
+	writel(data, priv->regs + group_offset + reg_offset);
+#if DEBUG_LOG
+	pr_info("Write 32'h%08x 32'h%08x\n", group_offset + reg_offset, data);
+#endif
+}
+
+static inline void
+phytium_writeb_reg(struct phytium_display_private *priv, uint8_t data,
+			   uint32_t group_offset, uint32_t reg_offset)
+{
+	writeb(data, priv->regs + group_offset + reg_offset);
+#if DEBUG_LOG
+	pr_info("Write 32'h%08x 8'h%08x\n", group_offset + reg_offset, data);
+#endif
+}
+
+#define for_each_pipe(__dev_priv, __p) \
+	for ((__p) = 0; (__p) < __dev_priv->info.total_pipes; (__p)++)
+
+#define for_each_pipe_masked(__dev_priv, __p) \
+	for ((__p) = 0; (__p) < __dev_priv->info.total_pipes; (__p)++) \
+		for_each_if((__dev_priv->info.pipe_mask) & BIT(__p))
+
+int phytium_get_virt_pipe(struct phytium_display_private *priv, int phys_pipe);
+int phytium_get_phys_pipe(struct phytium_display_private *priv, int virt_pipe);
+int phytium_wait_cmd_done(struct phytium_display_private *priv,
+				    uint32_t register_offset,
+				    uint32_t request_bit,
+				    uint32_t reply_bit);
+void phytium_display_private_init(struct phytium_display_private *priv, struct drm_device *dev);
+
+extern struct drm_driver phytium_display_drm_driver;
+extern int dc_fake_mode_enable;
+extern int dc_fast_training_check;
+extern int num_source_rates;
+extern int source_max_lane_count;
+extern int link_dynamic_adjust;
+
+#endif /* __PHYTIUM_DISPLAY_DRV_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_dp.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_dp.c
new file mode 100644
index 00000000000000..96fe440cd06ca8
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_dp.c
@@ -0,0 +1,2662 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/version.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_modes.h>
+#include <sound/hdmi-codec.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+#include <drm/drm_probe_helper.h>
+#endif
+#include "phytium_display_drv.h"
+#include "phytium_dp.h"
+#include "phytium_debugfs.h"
+#include "px210_dp.h"
+#include "pe220x_dp.h"
+#include "phytium_panel.h"
+#include "phytium_reg.h"
+
+static void phytium_dp_aux_init(struct phytium_dp_device *phytium_dp);
+static void handle_plugged_change(struct phytium_dp_device *phytium_dp, bool plugged);
+static bool phytium_edp_init_connector(struct phytium_dp_device *phytium_dp);
+static void phytium_edp_fini_connector(struct phytium_dp_device *phytium_dp);
+static void phytium_edp_panel_poweroff(struct phytium_dp_device *phytium_dp);
+static void phytium_dp_audio_codec_fini(struct phytium_dp_device *phytium_dp);
+
+static int phytium_rate[] = {162000, 270000, 540000, 810000};
+static int codec_id = PHYTIUM_DP_AUDIO_ID;
+
+void phytium_phy_writel(struct phytium_dp_device *phytium_dp, uint32_t address, uint32_t data)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->phy_access_base[port];
+
+#if DEBUG_LOG
+	pr_info("phy address write: 0x%x data:0x%x\n", address, data);
+#endif
+	phytium_writel_reg(priv, address, group_offset, PHYTIUM_PHY_ACCESS_ADDRESS);
+	phytium_writel_reg(priv, data, group_offset, PHYTIUM_PHY_WRITE_DATA);
+	phytium_writel_reg(priv, ACCESS_WRITE, group_offset, PHYTIUM_PHY_ACCESS_CTRL);
+	udelay(10);
+}
+
+uint32_t phytium_phy_readl(struct phytium_dp_device *phytium_dp, uint32_t address)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->phy_access_base[port];
+	uint32_t data;
+
+	phytium_writel_reg(priv, address, group_offset, PHYTIUM_PHY_ACCESS_ADDRESS);
+	phytium_writel_reg(priv, ACCESS_READ, group_offset, PHYTIUM_PHY_ACCESS_CTRL);
+	udelay(10);
+	data = phytium_readl_reg(priv, group_offset, PHYTIUM_PHY_READ_DATA);
+#if DEBUG_LOG
+	pr_info("phy address read: 0x%x data:0x%x\n", address, data);
+#endif
+
+	return data;
+}
+
+static int
+phytium_dp_hw_aux_transfer_write(struct phytium_dp_device *phytium_dp, struct drm_dp_aux_msg *msg)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+	unsigned int i = 0, j = 0;
+	unsigned int cmd = 0;
+	unsigned int aux_status = 0, interrupt_status = 0;
+	unsigned char *data = msg->buffer;
+	int count_timeout = 0;
+	long ret = 0;
+
+	for (i = 0; i < 3; i++) {
+		/* clear PX210_DP_INTERRUPT_RAW_STATUS */
+		phytium_readl_reg(priv, group_offset, PHYTIUM_DP_INTERRUPT_STATUS);
+		phytium_writel_reg(priv, msg->address, group_offset, PHYTIUM_DP_AUX_ADDRESS);
+		for (j = 0; j < msg->size; j++)
+			phytium_writeb_reg(priv, data[j], group_offset, PHYTIUM_DP_AUX_WRITE_FIFO);
+
+		cmd = ((msg->request & COMMAND_MASK) << COMMAND_SHIFT);
+		if (msg->size == 0)
+			cmd |= ADDRESS_ONLY;
+		else
+			cmd |= (msg->size-1) & BYTE_COUNT_MASK;
+		phytium_writel_reg(priv, cmd, group_offset, PHYTIUM_DP_AUX_COMMAND);
+
+		count_timeout = 0;
+		do {
+			mdelay(5);
+			interrupt_status = phytium_readl_reg(priv, group_offset,
+							PHYTIUM_DP_INTERRUPT_RAW_STATUS);
+			aux_status = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_AUX_STATUS);
+			if ((aux_status & REPLY_RECEIVED) || (aux_status & REPLY_ERROR)
+			    || (interrupt_status & REPLY_TIMEOUT)) {
+				DRM_DEBUG_KMS("aux wait exit\n");
+				break;
+			}
+			count_timeout++;
+		} while (count_timeout < 6);
+
+		phytium_readl_reg(priv, group_offset, PHYTIUM_DP_INTERRUPT_STATUS);
+		if (interrupt_status & REPLY_TIMEOUT) {
+			DRM_DEBUG_KMS("aux write reply timeout\n");
+			continue;
+		} else if (aux_status & REPLY_ERROR) {
+			DRM_DEBUG_KMS("aux write reply error\n");
+			continue;
+		} else if (aux_status & REPLY_RECEIVED) {
+			DRM_DEBUG_KMS("aux write reply received succussful\n");
+			break;
+		}
+	}
+
+	if (interrupt_status & REPLY_TIMEOUT) {
+		DRM_NOTE("aux(%d) write reply timeout\n", phytium_dp->port);
+		ret = -EIO;
+		goto out;
+	} else if (aux_status & REPLY_ERROR) {
+		DRM_ERROR("aux(%d) write reply error\n", phytium_dp->port);
+		ret = -EIO;
+		goto out;
+	} else if ((aux_status & REPLY_RECEIVED) != REPLY_RECEIVED) {
+		DRM_ERROR("aux(%d) write reply no response\n", phytium_dp->port);
+		ret = -EIO;
+		goto out;
+	}
+
+	msg->reply = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_AUX_REPLY_CODE);
+	ret = msg->size;
+out:
+	return ret;
+}
+
+static int
+phytium_dp_hw_aux_transfer_read(struct phytium_dp_device *phytium_dp, struct drm_dp_aux_msg *msg)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+	unsigned int i = 0;
+	unsigned int cmd = 0;
+	unsigned int aux_status = 0, interrupt_status = 0;
+	unsigned char *data = msg->buffer;
+	int count_timeout = 0;
+	long ret = 0;
+
+	for (i = 0; i < 3; i++) {
+		phytium_readl_reg(priv, group_offset, PHYTIUM_DP_INTERRUPT_STATUS);
+		phytium_writel_reg(priv, msg->address, group_offset, PHYTIUM_DP_AUX_ADDRESS);
+		cmd = ((msg->request & COMMAND_MASK) << COMMAND_SHIFT);
+		if (msg->size == 0)
+			cmd |= ADDRESS_ONLY;
+		else
+			cmd |= ((msg->size-1) & BYTE_COUNT_MASK);
+		phytium_writel_reg(priv, cmd, group_offset, PHYTIUM_DP_AUX_COMMAND);
+
+		count_timeout = 0;
+		do {
+			mdelay(5);
+			interrupt_status = phytium_readl_reg(priv, group_offset,
+							     PHYTIUM_DP_INTERRUPT_RAW_STATUS);
+			aux_status = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_AUX_STATUS);
+			if ((aux_status & REPLY_RECEIVED) || (aux_status & REPLY_ERROR)
+			   || (interrupt_status & REPLY_TIMEOUT)) {
+				DRM_DEBUG_KMS("aux wait exit\n");
+				break;
+			}
+			count_timeout++;
+		} while (count_timeout < 6);
+
+		phytium_readl_reg(priv, group_offset, PHYTIUM_DP_INTERRUPT_STATUS);
+		if (interrupt_status & REPLY_TIMEOUT) {
+			DRM_DEBUG_KMS("aux read reply timeout\n");
+			continue;
+		} else if (aux_status & REPLY_ERROR) {
+			DRM_DEBUG_KMS("aux read reply error\n");
+			continue;
+		} else if (aux_status & REPLY_RECEIVED) {
+			DRM_DEBUG_KMS("aux read reply received succussful\n");
+			break;
+		}
+	}
+
+	if (interrupt_status & REPLY_TIMEOUT) {
+		DRM_NOTE("aux(%d) read reply timeout\n", phytium_dp->port);
+		ret = -EIO;
+		goto out;
+	} else if (aux_status & REPLY_ERROR) {
+		DRM_ERROR("aux(%d) read reply error\n", phytium_dp->port);
+		ret = -EIO;
+		goto out;
+	} else if ((aux_status & REPLY_RECEIVED) != REPLY_RECEIVED) {
+		DRM_ERROR("aux(%d) read reply no response\n", phytium_dp->port);
+		ret = -EIO;
+		goto out;
+	}
+
+	msg->reply = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_AUX_REPLY_CODE);
+	ret = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_AUX_REPLY_DATA_COUNT);
+
+	if (ret > msg->size) {
+		ret = msg->size;
+	} else if (ret != msg->size) {
+		DRM_DEBUG_KMS("aux read count error(ret:0x%lx != 0x%lx)\n", ret, msg->size);
+		ret = -EBUSY;
+		goto out;
+	}
+
+	for (i = 0; i < ret; i++)
+		data[i] = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_AUX_REPLY_DATA);
+
+out:
+	return ret;
+}
+
+static void phytium_get_native_mode(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_display_mode *t, *mode;
+	struct drm_connector *connector = &phytium_dp->connector;
+	struct drm_display_mode *native_mode = &phytium_dp->native_mode;
+
+	list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
+		if (mode->type & DRM_MODE_TYPE_PREFERRED) {
+			if (mode->hdisplay != native_mode->hdisplay ||
+			    mode->vdisplay != native_mode->vdisplay) {
+				memcpy(native_mode, mode, sizeof(*mode));
+				drm_mode_set_crtcinfo(native_mode, 0);
+			}
+			break;
+		}
+	}
+
+	if (&mode->head == &connector->probed_modes)
+		native_mode->clock = 0;
+}
+
+static int phytium_connector_add_common_modes(struct phytium_dp_device *phytium_dp)
+{
+	int i = 0, ret = 0;
+	struct drm_device *dev =  phytium_dp->dev;
+	struct drm_display_mode *mode = NULL, *current_mode = NULL;
+	struct drm_display_mode *native_mode = &phytium_dp->native_mode;
+	bool mode_existed = false;
+	struct mode_size {
+		char name[DRM_DISPLAY_MODE_LEN];
+		int w;
+		int h;
+	} common_mode[] = {
+		{  "640x480",  640,  480},
+		{  "800x600",  800,  600},
+		{ "1024x768", 1024,  768},
+		{ "1280x720", 1280,  720},
+		{ "1280x800", 1280,  800},
+		{"1280x1024", 1280, 1024},
+		{ "1440x900", 1440,  900},
+		{"1680x1050", 1680, 1050},
+		{"1600x1200", 1600, 1200},
+		{"1920x1080", 1920, 1080},
+		{"1920x1200", 1920, 1200}
+	};
+
+	if (native_mode->clock == 0)
+		return ret;
+
+	for (i = 0; i < ARRAY_SIZE(common_mode); i++) {
+		mode_existed = false;
+
+		if (common_mode[i].w > native_mode->hdisplay ||
+		    common_mode[i].h > native_mode->vdisplay ||
+		    (common_mode[i].w == native_mode->hdisplay &&
+		    common_mode[i].h == native_mode->vdisplay))
+			continue;
+
+		list_for_each_entry(current_mode, &phytium_dp->connector.probed_modes, head) {
+			if (common_mode[i].w == current_mode->hdisplay &&
+			    common_mode[i].h == current_mode->vdisplay) {
+				mode_existed = true;
+				break;
+			}
+		}
+
+		if (mode_existed)
+			continue;
+
+		mode = drm_mode_duplicate(dev, native_mode);
+		if (mode == NULL)
+			continue;
+
+		mode->hdisplay = common_mode[i].w;
+		mode->vdisplay = common_mode[i].h;
+		mode->type &= ~DRM_MODE_TYPE_PREFERRED;
+		strncpy(mode->name, common_mode[i].name, DRM_DISPLAY_MODE_LEN);
+		drm_mode_probed_add(&phytium_dp->connector, mode);
+		ret++;
+	}
+
+	return ret;
+}
+
+static int phytium_connector_get_modes(struct drm_connector *connector)
+{
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	struct edid *edid;
+	int ret = 0;
+
+	if (phytium_dp->is_edp)
+		edid = phytium_dp->edp_edid;
+	else
+		edid = drm_get_edid(connector, &phytium_dp->aux.ddc);
+
+	if (edid && drm_edid_is_valid(edid)) {
+		drm_connector_update_edid_property(connector, edid);
+		ret = drm_add_edid_modes(connector, edid);
+		phytium_dp->has_audio = drm_detect_monitor_audio(edid);
+		phytium_get_native_mode(phytium_dp);
+		if (dc_fake_mode_enable)
+			ret += phytium_connector_add_common_modes(phytium_dp);
+	} else {
+		drm_connector_update_edid_property(connector, NULL);
+		phytium_dp->has_audio = false;
+	}
+
+	if (!phytium_dp->is_edp)
+		kfree(edid);
+
+	return ret;
+}
+
+static struct drm_encoder *phytium_dp_best_encoder(struct drm_connector *connector)
+{
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	return &phytium_dp->encoder;
+}
+
+static const
+struct drm_connector_helper_funcs phytium_connector_helper_funcs = {
+	.get_modes  = phytium_connector_get_modes,
+	.best_encoder = phytium_dp_best_encoder,
+};
+
+static void phytium_dp_set_sink_rates(struct phytium_dp_device *phytium_dp)
+{
+	static const int dp_rates[] = {162000, 270000, 540000, 810000};
+	int i, max_rate;
+
+	max_rate = drm_dp_bw_code_to_link_rate(phytium_dp->dpcd[DP_MAX_LINK_RATE]);
+	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
+		if (dp_rates[i] > max_rate)
+			break;
+		phytium_dp->sink_rates[i] = dp_rates[i];
+	}
+	phytium_dp->num_sink_rates = i;
+}
+
+static int get_common_rates(const int *source_rates, int source_len, const int *sink_rates,
+				  int sink_len, int *common_rates)
+{
+	int i = 0, j = 0, k = 0;
+
+	while (i < source_len && j < sink_len) {
+		if (source_rates[i] == sink_rates[j]) {
+			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
+				return k;
+			common_rates[k] = source_rates[i];
+			++k;
+			++i;
+			++j;
+		} else if (source_rates[i] < sink_rates[j]) {
+			++i;
+		} else {
+			++j;
+		}
+	}
+	return k;
+}
+
+static void phytium_dp_set_common_rates(struct phytium_dp_device *phytium_dp)
+{
+	WARN_ON(!phytium_dp->num_source_rates || !phytium_dp->num_sink_rates);
+
+	phytium_dp->num_common_rates = get_common_rates(phytium_dp->source_rates,
+							phytium_dp->num_source_rates,
+							phytium_dp->sink_rates,
+							phytium_dp->num_sink_rates,
+							phytium_dp->common_rates);
+
+	if (WARN_ON(phytium_dp->num_common_rates == 0)) {
+		phytium_dp->common_rates[0] = 162000;
+		phytium_dp->num_common_rates = 1;
+	}
+}
+
+static bool phytium_dp_get_dpcd(struct phytium_dp_device *phytium_dp)
+{
+	int ret;
+	unsigned char sink_count = 0;
+
+	/* get dpcd capability,but don't check data error; so check revision */
+	ret = drm_dp_dpcd_read(&phytium_dp->aux, 0x00, phytium_dp->dpcd,
+			       sizeof(phytium_dp->dpcd));
+	if (ret < 0) {
+		DRM_ERROR("port %d get DPCD capability fail\n", phytium_dp->port);
+		return false;
+	}
+
+	if (phytium_dp->dpcd[DP_DPCD_REV] == 0) {
+		DRM_ERROR("DPCD data error: 0x%x\n", phytium_dp->dpcd[DP_DPCD_REV]);
+		return false;
+	}
+
+	/* parse sink support link */
+	phytium_dp_set_sink_rates(phytium_dp);
+	phytium_dp_set_common_rates(phytium_dp);
+	phytium_dp->sink_max_lane_count = drm_dp_max_lane_count(phytium_dp->dpcd);
+	phytium_dp->common_max_lane_count = min(phytium_dp->source_max_lane_count,
+						phytium_dp->sink_max_lane_count);
+
+	/* get dpcd sink count */
+	if (drm_dp_dpcd_readb(&phytium_dp->aux, DP_SINK_COUNT, &sink_count) <= 0) {
+		DRM_ERROR("get DPCD sink_count fail\n");
+		return false;
+	}
+
+	phytium_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
+	if (!phytium_dp->sink_count) {
+		DRM_ERROR("DPCD sink_count should not be zero\n");
+		return false;
+	}
+
+	if (!drm_dp_is_branch(phytium_dp->dpcd))
+		return true;
+
+	if (phytium_dp->dpcd[DP_DPCD_REV] == 0x10)
+		return true;
+
+	/* get downstream port for branch device */
+	ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_DOWNSTREAM_PORT_0,
+			       phytium_dp->downstream_ports, DP_MAX_DOWNSTREAM_PORTS);
+	if (ret < 0) {
+		DRM_ERROR("get DPCD DFP fail\n");
+		return false;
+	}
+
+	return true;
+}
+
+static enum drm_connector_status
+phytium_dp_detect_dpcd(struct phytium_dp_device *phytium_dp)
+{
+	if (!phytium_dp_get_dpcd(phytium_dp))
+		return connector_status_disconnected;
+
+	if (!drm_dp_is_branch(phytium_dp->dpcd))
+		return connector_status_connected;
+
+	if (phytium_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
+		return phytium_dp->sink_count ? connector_status_connected
+			: connector_status_disconnected;
+	}
+	return connector_status_connected;
+}
+
+static void phytium_get_adjust_train(struct phytium_dp_device *phytium_dp,
+				const uint8_t link_status[DP_LINK_STATUS_SIZE], uint8_t lane_count)
+{
+	unsigned char v = 0;
+	unsigned char p = 0;
+	int lane;
+	unsigned char voltage_max;
+	unsigned char preemph_max;
+
+	/* find max value */
+	for (lane = 0; lane < lane_count; lane++) {
+		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
+		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
+
+		if (this_v > v)
+			v = this_v;
+		if (this_p > p)
+			p = this_p;
+	}
+	voltage_max = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
+	if (v >= voltage_max)
+		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+	preemph_max = DP_TRAIN_PRE_EMPH_LEVEL_3;
+	if (p >= preemph_max)
+		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+	for (lane = 0; lane < 4; lane++)
+		phytium_dp->train_set[lane] = v | p;
+}
+
+bool phytium_dp_coding_8b10b_need_enable(unsigned char test_pattern)
+{
+	switch (test_pattern) {
+	case PHYTIUM_PHY_TP_D10_2:
+	case PHYTIUM_PHY_TP_SYMBOL_ERROR:
+	case PHYTIUM_PHY_TP_CP2520_1:
+	case PHYTIUM_PHY_TP_CP2520_2:
+	case PHYTIUM_PHY_TP_CP2520_3:
+		return true;
+	case PHYTIUM_PHY_TP_PRBS7:
+	case PHYTIUM_PHY_TP_80BIT_CUSTOM:
+		return false;
+	default:
+		return false;
+	}
+}
+
+bool phytium_dp_scrambled_need_enable(unsigned char test_pattern)
+{
+	switch (test_pattern) {
+	case PHYTIUM_PHY_TP_SYMBOL_ERROR:
+	case PHYTIUM_PHY_TP_CP2520_1:
+	case PHYTIUM_PHY_TP_CP2520_2:
+	case PHYTIUM_PHY_TP_CP2520_3:
+		return true;
+	case PHYTIUM_PHY_TP_D10_2:
+	case PHYTIUM_PHY_TP_PRBS7:
+	case PHYTIUM_PHY_TP_80BIT_CUSTOM:
+		return false;
+	default:
+		return false;
+	}
+}
+
+static void phytium_dp_hw_set_lane_setting(struct phytium_dp_device *phytium_dp,
+							 uint32_t link_rate,
+							 uint8_t train_set)
+{
+	phytium_dp->funcs->dp_hw_set_phy_lane_setting(phytium_dp, link_rate, train_set);
+}
+
+static void phytium_dp_hw_set_link(struct phytium_dp_device *phytium_dp,
+					     uint8_t lane_count,
+					     uint32_t link_rate)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, ret = 0, retry = 3;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, lane_count,
+			   group_offset, PHYTIUM_DP_LANE_COUNT_SET);
+	phytium_writel_reg(priv,
+			   drm_dp_link_rate_to_bw_code(link_rate),
+			   group_offset, PHYTIUM_DP_LINK_BW_SET);
+
+	if (drm_dp_enhanced_frame_cap(phytium_dp->dpcd))
+		phytium_writel_reg(priv, ENHANCED_FRAME_ENABLE,
+				   group_offset, PHYTIUM_DP_ENHANCED_FRAME_EN);
+	else
+		phytium_writel_reg(priv, ENHANCED_FRAME_DISABLE,
+				   group_offset, PHYTIUM_DP_ENHANCED_FRAME_EN);
+
+try_again:
+	ret = phytium_dp->funcs->dp_hw_set_phy_lane_and_rate(phytium_dp, lane_count, link_rate);
+	if ((ret < 0) && retry) {
+		retry--;
+		goto try_again;
+	}
+}
+
+static void phytium_dp_hw_set_test_pattern(struct phytium_dp_device *phytium_dp,
+							 uint8_t lane_count,
+							 uint8_t test_pattern,
+							 uint8_t *custom_pattern,
+							 uint32_t custom_pattern_size)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, val = 0, tmp = 0, i;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	if ((test_pattern == PHYTIUM_PHY_TP_80BIT_CUSTOM)
+	    && custom_pattern && (custom_pattern_size > 0)) {
+		val = *(int *)custom_pattern;
+		phytium_writel_reg(priv, val, group_offset, PHYTIUM_DP_CUSTOM_80BIT_PATTERN_0);
+		val = *(int *)(custom_pattern + 4);
+		phytium_writel_reg(priv, val, group_offset, PHYTIUM_DP_CUSTOM_80BIT_PATTERN_1);
+		val = *(short int *)(custom_pattern + 8);
+		phytium_writel_reg(priv, val, group_offset, PHYTIUM_DP_CUSTOM_80BIT_PATTERN_2);
+	}
+
+	if (test_pattern == PHYTIUM_PHY_TP_D10_2 || test_pattern == PHYTIUM_PHY_TP_PRBS7
+		|| test_pattern == PHYTIUM_PHY_TP_80BIT_CUSTOM)
+		phytium_writel_reg(priv, SCRAMBLING_DISABLE, group_offset,
+				   PHYTIUM_DP_SCRAMBLING_DISABLE);
+	else
+		phytium_writel_reg(priv, SCRAMBLING_ENABLE, group_offset,
+				   PHYTIUM_DP_SCRAMBLING_DISABLE);
+
+	tmp = test_pattern - PHYTIUM_PHY_TP_NONE + TEST_PATTERN_NONE;
+	val = 0;
+	for (i = 0; i < lane_count; i++)
+		val |= (tmp << (TEST_PATTERN_LANE_SHIFT * i));
+	phytium_writel_reg(priv, val, group_offset, PHYTIUM_DP_LINK_QUAL_PATTERN_SET);
+}
+
+static void phytium_dp_hw_set_train_pattern(struct phytium_dp_device *phytium_dp,
+							  uint8_t train_pattern)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, tmp = 0;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	/* Scrambling is disabled for TPS1/TPS2/3 and enabled for TPS4 */
+	if (train_pattern == DP_TRAINING_PATTERN_4
+	    || train_pattern == DP_TRAINING_PATTERN_DISABLE) {
+		phytium_writel_reg(priv, SCRAMBLING_ENABLE, group_offset,
+				   PHYTIUM_DP_SCRAMBLING_DISABLE);
+		phytium_writel_reg(priv, SCRAMBLER_RESET, group_offset,
+				   PHYTIUM_DP_FORCE_SCRAMBLER_RESET);
+	} else {
+		phytium_writel_reg(priv, SCRAMBLING_DISABLE, group_offset,
+				   PHYTIUM_DP_SCRAMBLING_DISABLE);
+	}
+	switch (train_pattern) {
+	case DP_TRAINING_PATTERN_DISABLE:
+		tmp = TRAINING_OFF;
+		break;
+	case DP_TRAINING_PATTERN_1:
+		tmp = TRAINING_PATTERN_1;
+		break;
+	case DP_TRAINING_PATTERN_2:
+		tmp = TRAINING_PATTERN_2;
+		break;
+	case DP_TRAINING_PATTERN_3:
+		tmp = TRAINING_PATTERN_3;
+		break;
+	case DP_TRAINING_PATTERN_4:
+		tmp = TRAINING_PATTERN_4;
+		break;
+	default:
+		tmp = TRAINING_OFF;
+		break;
+	}
+
+	phytium_writel_reg(priv, tmp, group_offset, PHYTIUM_DP_TRAINING_PATTERN_SET);
+}
+
+void phytium_dp_hw_enable_audio(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	int config = 0, config1, data_window = 0;
+	const struct dp_audio_n_m *n_m = NULL;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SEC_AUDIO_ENABLE);
+	phytium_writel_reg(priv, CHANNEL_MUTE_ENABLE, group_offset, PHYTIUM_DP_SEC_AUDIO_ENABLE);
+
+	data_window = 90*(phytium_dp->link_rate)/100
+			*(phytium_dp->mode.htotal - phytium_dp->mode.hdisplay)
+			/phytium_dp->mode.clock/4;
+
+	phytium_writel_reg(priv, data_window, group_offset, PHYTIUM_DP_SEC_DATA_WINDOW);
+
+	n_m = phytium_dp_audio_get_n_m(phytium_dp->link_rate, phytium_dp->audio_info.sample_rate);
+	if (n_m == NULL) {
+		DRM_NOTE("can not get n_m for link_rate(%d) and sample_rate(%d)\n",
+				phytium_dp->link_rate, phytium_dp->audio_info.sample_rate);
+		phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DP_SEC_MAUD);
+		phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DP_SEC_NAUD);
+	} else {
+		phytium_writel_reg(priv, n_m->m, group_offset, PHYTIUM_DP_SEC_MAUD);
+		phytium_writel_reg(priv, n_m->n, group_offset, PHYTIUM_DP_SEC_NAUD);
+	}
+
+	config1 = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE);
+	phytium_writel_reg(priv, SECONDARY_STREAM_DISABLE,
+			   group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE);
+	phytium_writel_reg(priv, config1, group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE);
+	phytium_writel_reg(priv, config, group_offset, PHYTIUM_DP_SEC_AUDIO_ENABLE);
+}
+
+static void phytium_dp_hw_audio_shutdown(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, SECONDARY_STREAM_DISABLE,
+			   group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE);
+}
+
+static void phytium_dp_hw_audio_digital_mute(struct phytium_dp_device *phytium_dp, bool enable)
+{
+	struct phytium_display_private *priv = phytium_dp->dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	if (enable)
+		phytium_writel_reg(priv, CHANNEL_MUTE_ENABLE,
+				   group_offset, PHYTIUM_DP_SEC_AUDIO_ENABLE);
+	else
+		phytium_writel_reg(priv, SEC_AUDIO_ENABLE,
+				   group_offset, PHYTIUM_DP_SEC_AUDIO_ENABLE);
+}
+
+static int
+phytium_dp_hw_audio_hw_params(struct phytium_dp_device *phytium_dp, struct audio_info audio_info)
+{
+	struct phytium_display_private *priv = phytium_dp->dev->dev_private;
+	int port = phytium_dp->port;
+	int ret = 0, data_window = 0;
+	const struct dp_audio_n_m *n_m = NULL;
+	uint32_t fs, ws, fs_accurac;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	DRM_DEBUG_KMS("%s:set port%d sample_rate(%d) channels(%d) sample_width(%d)\n",
+			__func__, phytium_dp->port, audio_info.sample_rate,
+			audio_info.channels, audio_info.sample_width);
+
+	phytium_writel_reg(priv, INPUT_SELECT_I2S, group_offset, PHYTIUM_DP_SEC_INPUT_SELECT);
+	phytium_writel_reg(priv, APB_CLOCK/audio_info.sample_rate,
+			   group_offset, PHYTIUM_DP_SEC_DIRECT_CLKDIV);
+	phytium_writel_reg(priv, audio_info.channels & CHANNEL_MASK,
+			   group_offset, PHYTIUM_DP_SEC_CHANNEL_COUNT);
+	phytium_writel_reg(priv, CHANNEL_MAP_DEFAULT, group_offset, PHYTIUM_DP_SEC_CHANNEL_MAP);
+	data_window = 90*(phytium_dp->link_rate)/100
+			*(phytium_dp->mode.htotal - phytium_dp->mode.hdisplay)
+			/phytium_dp->mode.clock/4;
+	phytium_writel_reg(priv, data_window, group_offset, PHYTIUM_DP_SEC_DATA_WINDOW);
+	phytium_writel_reg(priv, 0xb5, group_offset, PHYTIUM_DP_SEC_CS_CATEGORY_CODE);
+
+	phytium_writel_reg(priv, CLOCK_MODE_SYNC, group_offset, PHYTIUM_DP_SEC_CLOCK_MODE);
+	phytium_writel_reg(priv, CS_SOURCE_FORMAT_DEFAULT,
+			   group_offset, PHYTIUM_DP_SEC_CS_SOURCE_FORMAT);
+
+	switch (audio_info.sample_rate) {
+	case 32000:
+		fs = ORIG_FREQ_32000;
+		fs_accurac = SAMPLING_FREQ_32000;
+		break;
+	case 44100:
+		fs = ORIG_FREQ_44100;
+		fs_accurac = SAMPLING_FREQ_44100;
+		break;
+	case 48000:
+		fs = ORIG_FREQ_48000;
+		fs_accurac = SAMPLING_FREQ_48000;
+		break;
+	case 96000:
+		fs = ORIG_FREQ_96000;
+		fs_accurac = SAMPLING_FREQ_96000;
+		break;
+	case 176400:
+		fs = ORIG_FREQ_176400;
+		fs_accurac = SAMPLING_FREQ_176400;
+		break;
+	case 192000:
+		fs = ORIG_FREQ_192000;
+		fs_accurac = SAMPLING_FREQ_192000;
+		break;
+	default:
+		DRM_ERROR("dp not support sample_rate %d\n", audio_info.sample_rate);
+		goto out;
+	}
+
+	switch (audio_info.sample_width) {
+	case 16:
+		ws = WORD_LENGTH_16;
+		break;
+	case 18:
+		ws = WORD_LENGTH_18;
+		break;
+	case 20:
+		ws = WORD_LENGTH_20;
+		break;
+	case 24:
+		ws = WORD_LENGTH_24;
+		break;
+	default:
+		DRM_ERROR("dp not support sample_width %d\n", audio_info.sample_width);
+		goto out;
+	}
+
+	phytium_writel_reg(priv, ((fs&ORIG_FREQ_MASK)<<ORIG_FREQ_SHIFT)
+			   | ((ws&WORD_LENGTH_MASK) << WORD_LENGTH_SHIFT),
+			   group_offset, PHYTIUM_DP_SEC_CS_LENGTH_ORIG_FREQ);
+	phytium_writel_reg(priv, (fs_accurac&SAMPLING_FREQ_MASK) << SAMPLING_FREQ_SHIFT,
+			   group_offset, PHYTIUM_DP_SEC_CS_FREQ_CLOCK_ACCURACY);
+
+	n_m = phytium_dp_audio_get_n_m(phytium_dp->link_rate, audio_info.sample_rate);
+	if (n_m == NULL) {
+		DRM_NOTE("can not get n_m for link_rate(%d) and sample_rate(%d)\n",
+			       phytium_dp->link_rate, audio_info.sample_rate);
+		phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DP_SEC_MAUD);
+		phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DP_SEC_NAUD);
+
+	} else {
+		phytium_writel_reg(priv, n_m->m, group_offset, PHYTIUM_DP_SEC_MAUD);
+		phytium_writel_reg(priv, n_m->n, group_offset, PHYTIUM_DP_SEC_NAUD);
+	}
+	phytium_writel_reg(priv, SECONDARY_STREAM_ENABLE,
+			   group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE);
+	phytium_dp->audio_info = audio_info;
+
+	return 0;
+
+out:
+	phytium_writel_reg(priv, SECONDARY_STREAM_DISABLE,
+			   group_offset, PHYTIUM_DP_SECONDARY_STREAM_ENABLE);
+
+	return ret;
+}
+
+void phytium_dp_hw_disable_video(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, SST_MST_SOURCE_0_DISABLE,
+			   group_offset, PHYTIUM_DP_VIDEO_STREAM_ENABLE);
+}
+
+bool phytium_dp_hw_video_is_enable(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, config;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_VIDEO_STREAM_ENABLE);
+	return config ? true : false;
+}
+
+void phytium_dp_hw_enable_video(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, SST_MST_SOURCE_0_ENABLE,
+			   group_offset, PHYTIUM_DP_VIDEO_STREAM_ENABLE);
+	phytium_writel_reg(priv, LINK_SOFT_RESET, group_offset, PHYTIUM_DP_SOFT_RESET);
+}
+
+void phytium_dp_hw_config_video(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+	unsigned long link_bw, date_rate = 0;
+	struct drm_display_info *display_info = &phytium_dp->connector.display_info;
+	unsigned char tu_size = 64;
+	unsigned long data_per_tu = 0;
+	int symbols_per_tu, frac_symbols_per_tu, symbol_count, udc, value;
+
+	/* cal M/N and tu_size */
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_clock/10, group_offset, PHYTIUM_DP_M_VID);
+	phytium_writel_reg(priv, phytium_dp->link_rate/10, group_offset, PHYTIUM_DP_N_VID);
+	link_bw = phytium_dp->link_rate * phytium_dp->link_lane_count;
+	date_rate = (phytium_dp->mode.crtc_clock * display_info->bpc * 3)/8;
+
+	/* mul 10 for register setting */
+	data_per_tu = 10*tu_size * date_rate/link_bw;
+	symbols_per_tu = (data_per_tu/10)&0xff;
+	if (symbols_per_tu == 63)
+		frac_symbols_per_tu = 0;
+	else
+		frac_symbols_per_tu = (data_per_tu%10*16/10) & 0xf;
+	phytium_writel_reg(priv, frac_symbols_per_tu<<24 | symbols_per_tu<<16 | tu_size,
+			   group_offset, PHYTIUM_DP_TRANSFER_UNIT_SIZE);
+
+	symbol_count = (phytium_dp->mode.crtc_hdisplay*display_info->bpc*3 + 7)/8;
+	udc = (symbol_count + phytium_dp->link_lane_count - 1)/phytium_dp->link_lane_count;
+	phytium_writel_reg(priv, udc, group_offset, PHYTIUM_DP_DATA_COUNT);
+
+	/* config main stream attributes */
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_htotal,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_HTOTAL);
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_hdisplay,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_HRES);
+	phytium_writel_reg(priv,
+			   phytium_dp->mode.crtc_hsync_end - phytium_dp->mode.crtc_hsync_start,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_HSWIDTH);
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_htotal - phytium_dp->mode.crtc_hsync_start,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_HSTART);
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_vtotal,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_VTOTAL);
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_vdisplay,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_VRES);
+	phytium_writel_reg(priv,
+			   phytium_dp->mode.crtc_vsync_end - phytium_dp->mode.crtc_vsync_start,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_VSWIDTH);
+	phytium_writel_reg(priv, phytium_dp->mode.crtc_vtotal - phytium_dp->mode.crtc_vsync_start,
+			   group_offset, PHYTIUM_DP_MAIN_LINK_VSTART);
+
+	value = 0;
+	if (phytium_dp->mode.flags & DRM_MODE_FLAG_PHSYNC)
+		value = value & (~HSYNC_POLARITY_LOW);
+	else
+		value = value | HSYNC_POLARITY_LOW;
+
+	if (phytium_dp->mode.flags & DRM_MODE_FLAG_PVSYNC)
+		value = value & (~VSYNC_POLARITY_LOW);
+	else
+		value = value | VSYNC_POLARITY_LOW;
+	phytium_writel_reg(priv, value, group_offset, PHYTIUM_DP_MAIN_LINK_POLARITY);
+
+	switch (display_info->bpc) {
+	case 10:
+		value = (MISC0_BIT_DEPTH_10BIT << MISC0_BIT_DEPTH_OFFSET);
+		break;
+	case 6:
+		value = (MISC0_BIT_DEPTH_6BIT << MISC0_BIT_DEPTH_OFFSET);
+		break;
+	default:
+		value = (MISC0_BIT_DEPTH_8BIT << MISC0_BIT_DEPTH_OFFSET);
+		break;
+	}
+	value |= (MISC0_COMPONENT_FORMAT_RGB << MISC0_COMPONENT_FORMAT_SHIFT)
+		| MISC0_SYNCHRONOUS_CLOCK;
+	phytium_writel_reg(priv, value, group_offset, PHYTIUM_DP_MAIN_LINK_MISC0);
+	phytium_writel_reg(priv, 0, group_offset, PHYTIUM_DP_MAIN_LINK_MISC1);
+
+	value = USER_ODDEVEN_POLARITY_HIGH | USER_DATA_ENABLE_POLARITY_HIGH;
+	if (phytium_dp->mode.flags & DRM_MODE_FLAG_PHSYNC)
+		value = value | USER_HSYNC_POLARITY_HIGH;
+	else
+		value = value & (~USER_HSYNC_POLARITY_HIGH);
+	if (phytium_dp->mode.flags & DRM_MODE_FLAG_PVSYNC)
+		value = value | USER_VSYNC_POLARITY_HIGH;
+	else
+		value = value & (~USER_VSYNC_POLARITY_HIGH);
+	phytium_writel_reg(priv, value, group_offset, PHYTIUM_DP_USER_SYNC_POLARITY);
+}
+
+void phytium_dp_hw_disable_output(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, TRANSMITTER_OUTPUT_DISABLE,
+			   group_offset, PHYTIUM_DP_TRANSMITTER_OUTPUT_ENABLE);
+	phytium_writel_reg(priv, LINK_SOFT_RESET, group_offset, PHYTIUM_DP_SOFT_RESET);
+}
+
+void phytium_dp_hw_enable_output(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, LINK_SOFT_RESET, group_offset, PHYTIUM_DP_SOFT_RESET);
+	phytium_writel_reg(priv, TRANSMITTER_OUTPUT_ENABLE,
+			   group_offset, PHYTIUM_DP_TRANSMITTER_OUTPUT_ENABLE);
+}
+
+void phytium_dp_hw_enable_input_source(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_writel_reg(priv, VIRTUAL_SOURCE_0_ENABLE,
+			   group_offset, PHYTIUM_INPUT_SOURCE_ENABLE);
+}
+
+void phytium_dp_hw_disable_input_source(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+
+	phytium_writel_reg(priv, (~VIRTUAL_SOURCE_0_ENABLE)&VIRTUAL_SOURCE_0_ENABLE_MASK,
+			   priv->dp_reg_base[port], PHYTIUM_INPUT_SOURCE_ENABLE);
+}
+
+bool phytium_dp_hw_output_is_enable(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+	int config = 0;
+
+	config = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_TRANSMITTER_OUTPUT_ENABLE);
+	return config ? true : false;
+}
+
+static void phytium_dp_hw_get_hpd_state(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t val = 0, raw_state = 0;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	val = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_INTERRUPT_RAW_STATUS);
+
+	/* maybe miss hpd, so used for clear PHYTIUM_DP_INTERRUPT_RAW_STATUS */
+	phytium_readl_reg(priv, group_offset, PHYTIUM_DP_INTERRUPT_STATUS);
+	raw_state = phytium_readl_reg(priv, group_offset, PHYTIUM_DP_SINK_HPD_STATE);
+	if (val & HPD_EVENT)
+		phytium_dp->dp_hpd_state.hpd_event_state = true;
+
+	if (val & HPD_IRQ)
+		phytium_dp->dp_hpd_state.hpd_irq_state = true;
+
+	if (raw_state & HPD_CONNECT)
+		phytium_dp->dp_hpd_state.hpd_raw_state = true;
+	else
+		phytium_dp->dp_hpd_state.hpd_raw_state = false;
+}
+
+void phytium_dp_hw_hpd_irq_setup(struct phytium_dp_device *phytium_dp, bool enable)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dp_reg_base[port];
+
+	phytium_dp->dp_hpd_state.hpd_irq_enable = enable;
+	if (enable)
+		phytium_writel_reg(priv, HPD_OTHER_MASK, group_offset, PHYTIUM_DP_INTERRUPT_MASK);
+	else
+		phytium_writel_reg(priv, HPD_IRQ_MASK|HPD_EVENT_MASK|HPD_OTHER_MASK,
+				   group_offset, PHYTIUM_DP_INTERRUPT_MASK);
+}
+
+int phytium_dp_hw_init(struct phytium_dp_device *phytium_dp)
+{
+	int ret = 0;
+	uint8_t count = 0;
+
+	phytium_dp->source_rates = phytium_rate;
+	phytium_dp->num_source_rates = num_source_rates;
+	count = phytium_dp->funcs->dp_hw_get_source_lane_count(phytium_dp);
+	phytium_dp->source_max_lane_count = count;
+
+	ret = phytium_dp->funcs->dp_hw_reset(phytium_dp);
+	if (ret)
+		goto out;
+	ret = phytium_dp->funcs->dp_hw_init_phy(phytium_dp);
+	if (ret)
+		goto out;
+
+	phytium_dp->fast_train_support = false;
+	phytium_dp->hw_spread_enable = phytium_dp->funcs->dp_hw_spread_is_enable(phytium_dp);
+
+out:
+	return ret;
+}
+
+static int phytium_dp_dpcd_get_tp_link(struct phytium_dp_device *phytium_dp,
+						    uint8_t *test_lane_count,
+						    uint32_t *test_link_rate)
+{
+	uint8_t test_link_bw;
+	int ret;
+
+	ret = drm_dp_dpcd_readb(&phytium_dp->aux, DP_TEST_LANE_COUNT,
+				   test_lane_count);
+	if (ret <= 0) {
+		DRM_DEBUG_KMS("test pattern Lane count read failed(%d)\n", ret);
+		goto failed;
+	}
+
+	ret = drm_dp_dpcd_readb(&phytium_dp->aux, DP_TEST_LINK_RATE,
+				   &test_link_bw);
+	if (ret <= 0) {
+		DRM_DEBUG_KMS("test pattern link rate read failed(%d)\n", ret);
+		goto failed;
+	}
+	*test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
+
+	return 0;
+failed:
+	return ret;
+}
+
+static int phytium_dp_dpcd_set_link(struct phytium_dp_device *phytium_dp,
+					       uint8_t lane_count, uint32_t link_rate)
+{
+	uint8_t link_config[2];
+	int ret = 0;
+
+	link_config[0] = drm_dp_link_rate_to_bw_code(link_rate);
+	link_config[1] = lane_count;
+	if (drm_dp_enhanced_frame_cap(phytium_dp->dpcd)) {
+		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+	}
+	ret = drm_dp_dpcd_write(&phytium_dp->aux, DP_LINK_BW_SET, link_config, 2);
+	if (ret < 0) {
+		DRM_NOTE("write dpcd DP_LINK_BW_SET fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	if (phytium_dp->hw_spread_enable)
+		link_config[0] = DP_SPREAD_AMP_0_5;
+	else
+		link_config[0] = 0;
+	link_config[1] = DP_SET_ANSI_8B10B;
+	ret = drm_dp_dpcd_write(&phytium_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
+	if (ret < 0) {
+		DRM_ERROR("write DP_DOWNSPREAD_CTRL fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	return 0;
+failed:
+	return ret;
+}
+
+static int phytium_dp_dpcd_set_test_pattern(struct phytium_dp_device *phytium_dp,
+							   uint8_t test_pattern)
+{
+	unsigned char value;
+	int ret;
+
+	if (phytium_dp_coding_8b10b_need_enable(test_pattern))
+		value = DP_SET_ANSI_8B10B;
+	else
+		value = 0;
+	ret = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value);
+	if (ret < 0) {
+		DRM_ERROR("write DP_MAIN_LINK_CHANNEL_CODING_SET fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	if (phytium_dp_scrambled_need_enable(test_pattern))
+		value = DP_TRAINING_PATTERN_DISABLE;
+	else
+		value = (DP_TRAINING_PATTERN_DISABLE | DP_LINK_SCRAMBLING_DISABLE);
+
+	ret = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_TRAINING_PATTERN_SET, value);
+	if (ret < 0) {
+		DRM_ERROR("write DP_TRAINING_PATTERN_SET fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	ret = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_LINK_QUAL_LANE0_SET, test_pattern);
+	if (ret < 0) {
+		DRM_ERROR("write DP_TRAINING_PATTERN_SET fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	return 0;
+failed:
+	return ret;
+}
+
+static int phytium_dp_dpcd_set_train_pattern(struct phytium_dp_device *phytium_dp,
+						     uint8_t train_pattern)
+{
+	uint8_t value;
+	int ret;
+
+	/* Scrambling is disabled for TPS1/2/3 and enabled for TPS4 */
+	if (train_pattern == DP_TRAINING_PATTERN_4 || train_pattern == DP_TRAINING_PATTERN_DISABLE)
+		value = train_pattern;
+	else
+		value = (train_pattern | DP_LINK_SCRAMBLING_DISABLE);
+
+	ret = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_TRAINING_PATTERN_SET, value);
+	if (ret < 0) {
+		DRM_NOTE("write DP_TRAINING_PATTERN_SET fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	return 0;
+failed:
+	return ret;
+}
+
+static int
+phytium_dp_dpcd_set_lane_setting(struct phytium_dp_device *phytium_dp, uint8_t *train_set)
+{
+	int ret = 0;
+
+	ret =  drm_dp_dpcd_write(&phytium_dp->aux, DP_TRAINING_LANE0_SET,
+				 phytium_dp->train_set, 4);
+	if (ret < 0) {
+		DRM_ERROR("write DP_TRAINING_LANE0_SET fail: ret:%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int
+phytium_dp_dpcd_get_adjust_request(struct phytium_dp_device *phytium_dp, uint8_t lane_count)
+{
+	int ret = 0;
+	uint8_t link_status[DP_LINK_STATUS_SIZE];
+
+	ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_LANE0_1_STATUS,
+		       link_status, DP_LINK_STATUS_SIZE);
+	if (ret < 0) {
+		DRM_ERROR("failed to get link status(DP_LANE0_1_STATUS)\n");
+		goto failed;
+	}
+	phytium_get_adjust_train(phytium_dp, link_status, lane_count);
+
+	return 0;
+failed:
+	return ret;
+}
+
+void phytium_dp_dpcd_sink_dpms(struct phytium_dp_device *phytium_dp, int mode)
+{
+	int ret, i;
+
+	if (phytium_dp->dpcd[DP_DPCD_REV] < 0x11)
+		return;
+	if (mode != DRM_MODE_DPMS_ON) {
+		ret = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
+	} else {
+		for (i = 0; i < 3; i++) {
+			ret = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
+			if (ret == 1)
+				break;
+			msleep(20);
+		}
+	}
+
+	if (ret != 1)
+		DRM_DEBUG_KMS("failed to %s sink power state\n",
+			       mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
+}
+
+static bool phytium_dp_link_training_clock_recovery(struct phytium_dp_device *phytium_dp)
+{
+	int ret;
+	unsigned char voltage, max_vswing_tries;
+	int voltage_tries;
+
+	/* clear the test pattern */
+	phytium_dp_hw_set_test_pattern(phytium_dp, phytium_dp->link_lane_count,
+				       PHYTIUM_PHY_TP_NONE, NULL, 0);
+
+	/* config source and sink's link rate and lane count */
+	phytium_dp_hw_set_link(phytium_dp, phytium_dp->link_lane_count, phytium_dp->link_rate);
+	ret = phytium_dp_dpcd_set_link(phytium_dp, phytium_dp->link_lane_count,
+				       phytium_dp->link_rate);
+	if (ret < 0) {
+		DRM_NOTE("phytium_dp_dpcd_set_link failed(ret=%d)\n", ret);
+		return false;
+	}
+
+	/* config source's voltage swing and pre-emphasis(103-106) */
+	memset(phytium_dp->train_set, 0, sizeof(phytium_dp->train_set));
+	phytium_dp_hw_set_lane_setting(phytium_dp, phytium_dp->link_rate,
+				       phytium_dp->train_set[0]);
+
+	/* config train pattern */
+	phytium_dp_hw_set_train_pattern(phytium_dp, DP_TRAINING_PATTERN_1);
+	ret = phytium_dp_dpcd_set_train_pattern(phytium_dp, DP_TRAINING_PATTERN_1);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_train_pattern fail: ret:%d\n", ret);
+		return false;
+	}
+
+	/* config sink's voltage swing and pre-emphasis(103-106) */
+	ret = phytium_dp_dpcd_set_lane_setting(phytium_dp, phytium_dp->train_set);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_lane_setting fail: ret:%d\n", ret);
+		return false;
+	}
+
+	voltage_tries = 1;
+	max_vswing_tries = 0;
+	for (;;) {
+		unsigned char link_status[DP_LINK_STATUS_SIZE];
+		drm_dp_link_train_clock_recovery_delay(phytium_dp->dpcd);
+		/* get link status 0x202-0x207 */
+		ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_LANE0_1_STATUS,
+				       link_status, DP_LINK_STATUS_SIZE);
+		if (ret < 0) {
+			DRM_ERROR("failed to get link status(DP_LANE0_1_STATUS)\n");
+			return false;
+		}
+
+		if (drm_dp_clock_recovery_ok(link_status, phytium_dp->link_lane_count)) {
+			DRM_DEBUG_KMS("clock revorery ok\n");
+			return true;
+		}
+
+		if (voltage_tries == 5) {
+			DRM_DEBUG_KMS("Same voltage tried 5 times\n");
+			return false;
+		}
+
+		if (max_vswing_tries == 1) {
+			DRM_DEBUG_KMS("Max Voltage Swing reached\n");
+			return false;
+		}
+
+		voltage = phytium_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+
+		/* config source and sink's voltage swing and pre-emphasis(103-106) */
+		phytium_get_adjust_train(phytium_dp, link_status, phytium_dp->link_lane_count);
+		phytium_dp_hw_set_lane_setting(phytium_dp, phytium_dp->link_rate,
+					       phytium_dp->train_set[0]);
+		ret = phytium_dp_dpcd_set_lane_setting(phytium_dp, phytium_dp->train_set);
+		if (ret < 0) {
+			DRM_ERROR("phytium_dp_dpcd_set_lane_setting fail: ret:%d\n", ret);
+			return false;
+		}
+
+		if ((phytium_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage)
+			++voltage_tries;
+		else
+			voltage_tries = 1;
+
+		if (phytium_dp->train_set[0] & DP_TRAIN_MAX_SWING_REACHED)
+			++max_vswing_tries;
+
+		DRM_DEBUG_KMS("try train_set:0x%x voltage_tries:%d max_vswing_tries:%d\n",
+			       phytium_dp->train_set[0], voltage_tries, max_vswing_tries);
+	}
+}
+
+static unsigned int phytium_dp_get_training_pattern(struct phytium_dp_device *phytium_dp)
+{
+	bool sink_tps3, sink_tps4;
+
+	sink_tps4 = drm_dp_tps4_supported(phytium_dp->dpcd);
+	if (sink_tps4)
+		return DP_TRAINING_PATTERN_4;
+	else if (phytium_dp->link_rate == 810000)
+		DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
+
+	sink_tps3 = drm_dp_tps3_supported(phytium_dp->dpcd);
+	if (sink_tps3)
+		return DP_TRAINING_PATTERN_3;
+	else if (phytium_dp->link_rate >= 540000)
+		DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
+
+	return DP_TRAINING_PATTERN_2;
+}
+
+static bool phytium_dp_link_training_channel_equalization(struct phytium_dp_device *phytium_dp)
+{
+	unsigned int training_pattern;
+	int tries, ret;
+	unsigned char link_status[DP_LINK_STATUS_SIZE];
+	bool channel_eq = false;
+
+	/* config source and sink's voltage swing and pre-emphasis(103-106), from clock recovery */
+	phytium_dp_hw_set_lane_setting(phytium_dp, phytium_dp->link_rate,
+				       phytium_dp->train_set[0]);
+	ret = phytium_dp_dpcd_set_lane_setting(phytium_dp, phytium_dp->train_set);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_lane_setting fail: ret:%d\n", ret);
+		return channel_eq;
+	}
+
+	/* config source and sink's train_pattern x */
+	training_pattern = phytium_dp_get_training_pattern(phytium_dp);
+	phytium_dp_hw_set_train_pattern(phytium_dp, training_pattern);
+	ret = phytium_dp_dpcd_set_train_pattern(phytium_dp, training_pattern);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_train_pattern fail: ret:%d\n", ret);
+		return channel_eq;
+	}
+
+	for (tries = 0; tries < 5; tries++) {
+		drm_dp_link_train_channel_eq_delay(phytium_dp->dpcd);
+
+		/* get link status 0x202-0x207 */
+		ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_LANE0_1_STATUS,
+				       link_status, DP_LINK_STATUS_SIZE);
+		if (ret < 0) {
+			DRM_ERROR("failed to get link status(DP_LANE0_1_STATUS)\n");
+			break;
+		}
+
+		/* Make sure clock is still ok */
+		if (!drm_dp_clock_recovery_ok(link_status, phytium_dp->link_lane_count)) {
+			DRM_DEBUG_KMS("CR check failed, cannot continue channel equalization\n");
+			break;
+		}
+
+		if (drm_dp_channel_eq_ok(link_status, phytium_dp->link_lane_count)) {
+			channel_eq = true;
+			DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
+			break;
+		}
+
+		/* config source and sink's voltage swing and pre-emphasis(103-106) */
+		phytium_get_adjust_train(phytium_dp, link_status, phytium_dp->link_lane_count);
+		phytium_dp_hw_set_lane_setting(phytium_dp, phytium_dp->link_rate,
+					       phytium_dp->train_set[0]);
+		ret = phytium_dp_dpcd_set_lane_setting(phytium_dp, phytium_dp->train_set);
+		if (ret < 0) {
+			DRM_ERROR("phytium_dp_dpcd_set_lane_setting fail: ret:%d\n", ret);
+			break;
+		}
+	}
+
+	/* Try 5 times, else fail and try at lower BW */
+	if (tries == 5)
+		DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
+
+	return channel_eq;
+}
+
+static void phytium_dp_train_retry_work_fn(struct work_struct *work)
+{
+	struct phytium_dp_device *phytium_dp = train_retry_to_dp_device(work);
+	struct drm_connector *connector;
+
+	connector = &phytium_dp->connector;
+	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name);
+	mutex_lock(&connector->dev->mode_config.mutex);
+	drm_connector_set_link_status_property(connector, DRM_MODE_LINK_STATUS_BAD);
+	mutex_unlock(&connector->dev->mode_config.mutex);
+	drm_kms_helper_hotplug_event(connector->dev);
+}
+
+/* return index of rate in rates array, or -1 if not found */
+static int phytium_dp_rate_index(const int *rates, int len, int rate)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (rate == rates[i])
+			return i;
+
+	return -1;
+}
+
+int phytium_dp_get_link_train_fallback_values(struct phytium_dp_device *phytium_dp)
+{
+	int index, ret = 0;
+
+	if (phytium_dp->is_edp) {
+		phytium_dp->train_retry_count++;
+		DRM_INFO("Retrying Link training for eDP(%d) with same parameters\n",
+			  phytium_dp->port);
+		goto out;
+	} else {
+		index = phytium_dp_rate_index(phytium_dp->common_rates,
+				    phytium_dp->num_common_rates,
+				    phytium_dp->link_rate);
+		if (index > 0) {
+			phytium_dp->link_rate = phytium_dp->common_rates[index - 1];
+		} else if (phytium_dp->link_lane_count > 1) {
+			phytium_dp->link_rate = phytium_dp->max_link_rate;
+			phytium_dp->link_lane_count = phytium_dp->link_lane_count >> 1;
+		} else {
+			phytium_dp->train_retry_count++;
+			phytium_dp->link_rate = phytium_dp->max_link_rate;
+			phytium_dp->link_lane_count = phytium_dp->max_link_lane_count;
+			DRM_INFO("Retrying Link training for DP(%d) with maximal parameters\n",
+				  phytium_dp->port);
+			ret = -1;
+		}
+	}
+
+out:
+	return ret;
+}
+
+static int
+phytium_dp_stop_link_train(struct phytium_dp_device *phytium_dp)
+{
+	int ret;
+
+	/* config source and sink's train_pattern x: DP_TRAINING_PATTERN_DISABLE */
+	phytium_dp_hw_set_train_pattern(phytium_dp, DP_TRAINING_PATTERN_DISABLE);
+
+	ret = phytium_dp_dpcd_set_train_pattern(phytium_dp, DP_TRAINING_PATTERN_DISABLE);
+	if (ret < 0) {
+		DRM_NOTE("phytium_dp_dpcd_set_train_pattern fail: ret:%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int phytium_dp_start_link_train(struct phytium_dp_device *phytium_dp)
+{
+	int ret = 0;
+
+	phytium_dp_hw_disable_output(phytium_dp);
+	phytium_dp_hw_disable_input_source(phytium_dp);
+	phytium_dp_hw_disable_video(phytium_dp);
+	phytium_dp_hw_enable_input_source(phytium_dp);
+	phytium_dp_hw_enable_output(phytium_dp);
+	phytium_dp_dpcd_sink_dpms(phytium_dp, DRM_MODE_DPMS_OFF);
+	phytium_dp_dpcd_sink_dpms(phytium_dp, DRM_MODE_DPMS_ON);
+
+	if (!phytium_dp_link_training_clock_recovery(phytium_dp))
+		goto failure_handling;
+
+	if (!phytium_dp_link_training_channel_equalization(phytium_dp))
+		goto failure_handling;
+
+	ret = phytium_dp_stop_link_train(phytium_dp);
+	if (ret < 0) {
+		DRM_NOTE("phytium_dp_stop_link_train failed: ret = %d\n", ret);
+		goto out;
+	}
+
+	if (phytium_dp->trigger_train_fail) {
+		phytium_dp->trigger_train_fail--;
+		goto failure_handling;
+	}
+	phytium_dp->train_retry_count = 0;
+
+	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Pass at Link Rate = %d, Lane count = %d\n",
+		      phytium_dp->connector.base.id,
+		      phytium_dp->connector.name, phytium_dp->link_rate,
+		      phytium_dp->link_lane_count);
+
+	return 0;
+
+failure_handling:
+	DRM_INFO("[CONNECTOR:%d:%s] Link Training failed at Link Rate = %d, Lane count = %d",
+	      phytium_dp->connector.base.id,
+	      phytium_dp->connector.name,
+	      phytium_dp->link_rate, phytium_dp->link_lane_count);
+
+	ret = phytium_dp_stop_link_train(phytium_dp);
+	if (ret < 0) {
+		DRM_NOTE("phytium_dp_stop_link_train failed: ret = %d\n", ret);
+		goto out;
+	}
+
+	phytium_dp_get_link_train_fallback_values(phytium_dp);
+	if (phytium_dp->train_retry_count < 5)
+		schedule_work(&phytium_dp->train_retry_work);
+	else
+		DRM_ERROR("DP(%d) Link Training Unsuccessful, and stop Training\n",
+			   phytium_dp->port);
+
+out:
+	return -1;
+}
+
+static bool phytium_dp_needs_link_retrain(struct phytium_dp_device *phytium_dp)
+{
+	unsigned char link_status[DP_LINK_STATUS_SIZE];
+	int ret = 0;
+
+	/* get link status 0x202-0x207 */
+	ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_LANE0_1_STATUS,
+			       link_status, DP_LINK_STATUS_SIZE);
+	if (ret < 0) {
+		DRM_ERROR("failed to get link status(DP_LANE0_1_STATUS)\n");
+		return true;
+	}
+
+	if ((phytium_dp->link_rate == 0) ||  (phytium_dp->link_lane_count == 0)) {
+		DRM_DEBUG_KMS("link_rate(%d) or lane_count(%d) is invalid\n",
+			       phytium_dp->link_rate, phytium_dp->link_lane_count);
+		return true;
+	}
+
+	/* Make sure clock is still ok */
+	if (!drm_dp_clock_recovery_ok(link_status, phytium_dp->link_lane_count)) {
+		DRM_DEBUG_KMS("Clock recovery check failed\n");
+		return true;
+	}
+
+	if (!drm_dp_channel_eq_ok(link_status, phytium_dp->link_lane_count)) {
+		DRM_DEBUG_KMS("Channel EQ check failed\n");
+		return true;
+	}
+
+	if (!phytium_dp_hw_output_is_enable(phytium_dp)) {
+		DRM_DEBUG_KMS("check DP output enable failed\n");
+		return true;
+	}
+	return false;
+}
+
+static bool
+phytium_dp_get_sink_irq(struct phytium_dp_device *phytium_dp, u8 *sink_irq_vector)
+{
+	return drm_dp_dpcd_readb(&phytium_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
+				 sink_irq_vector) == 1;
+}
+
+static uint8_t phytium_dp_autotest_phy_pattern(struct phytium_dp_device *phytium_dp)
+{
+	union phytium_phy_tp phytium_phy_tp;
+	int ret;
+	unsigned char test_80_bit_pattern[
+		(DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
+		DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
+	unsigned char test_pattern;
+	unsigned int offset;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+	offset = DP_TEST_PHY_PATTERN;
+#else
+	offset = DP_PHY_TEST_PATTERN;
+#endif
+
+	ret = drm_dp_dpcd_read(&phytium_dp->aux, offset,
+				   &phytium_phy_tp.raw,
+				   sizeof(phytium_phy_tp));
+	if (ret <= 0) {
+		DRM_DEBUG_KMS("Could not read DP_TEST_PHY_PATTERN\n");
+		goto failed;
+	}
+
+	test_pattern = phytium_phy_tp.bits.PATTERN;
+
+	if (test_pattern == PHYTIUM_PHY_TP_80BIT_CUSTOM) {
+		ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+					   test_80_bit_pattern,
+					   sizeof(test_80_bit_pattern));
+		if (ret <= 0) {
+			DRM_DEBUG_KMS("Could not read DP_TEST_PHY_PATTERN\n");
+			goto failed;
+		}
+	}
+
+	/* config source and sink's link rate and link count */
+	ret = phytium_dp_dpcd_get_tp_link(phytium_dp, &phytium_dp->compliance.test_lane_count,
+				    &phytium_dp->compliance.test_link_rate);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_get_tp_link fail: ret:%d\n", ret);
+		goto failed;
+	}
+
+	phytium_dp_hw_set_link(phytium_dp, phytium_dp->compliance.test_lane_count,
+			       phytium_dp->compliance.test_link_rate);
+	ret = phytium_dp_dpcd_set_link(phytium_dp, phytium_dp->compliance.test_lane_count,
+				       phytium_dp->compliance.test_link_rate);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_link fail: ret:%d\n", ret);
+		goto failed_dpcd_set_link;
+	}
+
+	/* config source and sink's lane setting: voltage swing and pre-emphasis */
+	ret = phytium_dp_dpcd_get_adjust_request(phytium_dp,
+						 phytium_dp->compliance.test_lane_count);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_get_adjust_request fail: ret:%d\n", ret);
+		goto failed_dpcd_get_adjust_request;
+	}
+	phytium_dp_hw_set_lane_setting(phytium_dp, phytium_dp->compliance.test_link_rate,
+				       phytium_dp->train_set[0]);
+	ret = phytium_dp_dpcd_set_lane_setting(phytium_dp, phytium_dp->train_set);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_lane_setting fail: ret:%d\n", ret);
+		goto failed_dpcd_set_lane_setting;
+	}
+
+	/* config test pattern */
+	phytium_dp_hw_set_test_pattern(phytium_dp, phytium_dp->compliance.test_lane_count,
+				       test_pattern, test_80_bit_pattern,
+				       sizeof(test_80_bit_pattern));
+	ret = phytium_dp_dpcd_set_test_pattern(phytium_dp, test_pattern);
+	if (ret < 0) {
+		DRM_ERROR("phytium_dp_dpcd_set_test_pattern fail: ret:%d\n", ret);
+		goto failed_dpcd_set_tp;
+	}
+
+	return DP_TEST_ACK;
+
+failed_dpcd_set_tp:
+	phytium_dp_hw_set_test_pattern(phytium_dp, phytium_dp->compliance.test_lane_count,
+				       PHYTIUM_PHY_TP_NONE, test_80_bit_pattern,
+				       sizeof(test_80_bit_pattern));
+failed_dpcd_set_link:
+failed_dpcd_set_lane_setting:
+failed_dpcd_get_adjust_request:
+failed:
+	return DP_TEST_NAK;
+}
+
+static void phytium_dp_handle_test_request(struct phytium_dp_device *phytium_dp)
+{
+	uint8_t response = DP_TEST_NAK;
+	uint8_t request = 0;
+	int status;
+
+	status = drm_dp_dpcd_readb(&phytium_dp->aux, DP_TEST_REQUEST, &request);
+	if (status <= 0) {
+		DRM_DEBUG_KMS("Could not read test request from sink\n");
+		goto update_status;
+	}
+
+	switch (request) {
+	case DP_TEST_LINK_TRAINING:
+	case DP_TEST_LINK_VIDEO_PATTERN:
+	case DP_TEST_LINK_EDID_READ:
+		DRM_DEBUG_KMS("Not support test request '%02x'\n", request);
+		response = DP_TEST_NAK;
+		break;
+	case DP_TEST_LINK_PHY_TEST_PATTERN:
+		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
+		response = phytium_dp_autotest_phy_pattern(phytium_dp);
+		break;
+	default:
+		DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
+		break;
+	}
+
+update_status:
+	status = drm_dp_dpcd_writeb(&phytium_dp->aux, DP_TEST_RESPONSE, response);
+	if (status <= 0)
+		DRM_DEBUG_KMS("Could not write test response to sink\n");
+
+}
+
+static int phytium_dp_long_pulse(struct drm_connector *connector, bool hpd_raw_state)
+{
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	enum drm_connector_status status = connector->status;
+	bool video_enable = false;
+	uint32_t index = 0;
+
+	if (phytium_dp->is_edp)
+		status = connector_status_connected;
+	else if (hpd_raw_state) {
+		if (!phytium_dp_needs_link_retrain(phytium_dp)) {
+			status = connector_status_connected;
+			goto out;
+		}
+	} else {
+		status = connector_status_disconnected;
+		goto out;
+	}
+
+	if (!phytium_dp->is_edp) {
+		status = phytium_dp_detect_dpcd(phytium_dp);
+		if (status == connector_status_disconnected)
+			goto out;
+
+		index = phytium_dp->num_common_rates-1;
+		phytium_dp->max_link_rate = phytium_dp->common_rates[index];
+		phytium_dp->max_link_lane_count = phytium_dp->common_max_lane_count;
+		phytium_dp->link_rate = phytium_dp->max_link_rate;
+		phytium_dp->link_lane_count = phytium_dp->max_link_lane_count;
+		DRM_DEBUG_KMS("common_max_lane_count: %d, common_max_rate:%d\n",
+			       phytium_dp->max_link_lane_count, phytium_dp->max_link_rate);
+
+		video_enable = phytium_dp_hw_video_is_enable(phytium_dp);
+		phytium_dp_start_link_train(phytium_dp);
+
+		if (video_enable) {
+			mdelay(2);
+			phytium_dp_hw_enable_video(phytium_dp);
+		}
+	}
+
+out:
+	return status;
+}
+
+static int phytium_dp_short_pulse(struct drm_connector *connector)
+{
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	enum drm_connector_status status = connector->status;
+	u8 sink_irq_vector = 0;
+	bool video_enable = false;
+
+	/* handle the test pattern */
+	if (phytium_dp_get_sink_irq(phytium_dp, &sink_irq_vector) &&
+	    sink_irq_vector != 0) {
+		drm_dp_dpcd_writeb(&phytium_dp->aux,
+				   DP_DEVICE_SERVICE_IRQ_VECTOR,
+				   sink_irq_vector);
+		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
+			phytium_dp_handle_test_request(phytium_dp);
+		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
+			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
+	}
+	if (!phytium_dp_needs_link_retrain(phytium_dp)) {
+		status = connector_status_connected;
+		goto out;
+	}
+
+	video_enable = phytium_dp_hw_video_is_enable(phytium_dp);
+	phytium_dp_start_link_train(phytium_dp);
+	if (video_enable) {
+		mdelay(2);
+		phytium_dp_hw_enable_video(phytium_dp);
+	}
+
+out:
+	return status;
+}
+
+void phytium_dp_hpd_poll_handler(struct phytium_display_private *priv)
+{
+	struct drm_device *dev = priv->dev;
+	struct drm_connector_list_iter conn_iter;
+	struct drm_connector *connector;
+	enum drm_connector_status old_status;
+	bool changed = false;
+
+	mutex_lock(&dev->mode_config.mutex);
+	DRM_DEBUG_KMS("running encoder hotplug poll functions\n");
+	drm_connector_list_iter_begin(dev, &conn_iter);
+	drm_for_each_connector_iter(connector, &conn_iter) {
+		if (connector->force)
+			continue;
+		old_status = connector->status;
+		connector->status = drm_helper_probe_detect(connector, NULL, false);
+		if (old_status != connector->status) {
+			const char *old, *new;
+
+			old = drm_get_connector_status_name(old_status);
+			new = drm_get_connector_status_name(connector->status);
+			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
+					connector->base.id,
+					connector->name,
+					old, new);
+			changed = true;
+		}
+	}
+	drm_connector_list_iter_end(&conn_iter);
+	mutex_unlock(&dev->mode_config.mutex);
+
+	if (changed)
+		drm_kms_helper_hotplug_event(dev);
+}
+
+void phytium_dp_hpd_irq_setup(struct drm_device *dev, bool enable)
+{
+	struct phytium_dp_device *phytium_dp;
+	struct drm_encoder *encoder;
+	struct phytium_display_private *priv = dev->dev_private;
+	bool handler = false;
+	bool hpd_raw_state_old = false;
+
+	/* We might have missed any hotplugs that happened, so polling and handler */
+	if (enable) {
+		spin_lock_irq(&priv->hotplug_irq_lock);
+
+		drm_for_each_encoder(encoder, dev) {
+			phytium_dp = encoder_to_dp_device(encoder);
+			if (!phytium_dp->dp_hpd_state.hpd_irq_enable) {
+				hpd_raw_state_old = phytium_dp->dp_hpd_state.hpd_raw_state;
+				phytium_dp_hw_get_hpd_state(phytium_dp);
+				if (phytium_dp->dp_hpd_state.hpd_event_state
+				|| phytium_dp->dp_hpd_state.hpd_irq_state
+				|| (hpd_raw_state_old != phytium_dp->dp_hpd_state.hpd_raw_state)) {
+					handler = true;
+				}
+			}
+		}
+		spin_unlock_irq(&priv->hotplug_irq_lock);
+		if (handler)
+			phytium_dp_hpd_poll_handler(priv);
+	}
+
+	drm_for_each_encoder(encoder, dev) {
+		phytium_dp = encoder_to_dp_device(encoder);
+		phytium_dp_hw_hpd_irq_setup(phytium_dp, enable);
+	}
+}
+
+void phytium_dp_hpd_work_func(struct work_struct *work)
+{
+	struct phytium_display_private *priv =
+		container_of(work, struct phytium_display_private, hotplug_work);
+	struct drm_device *dev = priv->dev;
+	struct drm_connector_list_iter conn_iter;
+	struct drm_connector *connector;
+	enum drm_connector_status old_status;
+	bool changed = false;
+
+	mutex_lock(&dev->mode_config.mutex);
+	DRM_DEBUG_KMS("running encoder hotplug work functions\n");
+	drm_connector_list_iter_begin(dev, &conn_iter);
+	drm_for_each_connector_iter(connector, &conn_iter) {
+		if (connector->force)
+			continue;
+		old_status = connector->status;
+		connector->status = drm_helper_probe_detect(connector, NULL, false);
+		if (old_status != connector->status) {
+			const char *old, *new;
+
+			old = drm_get_connector_status_name(old_status);
+			new = drm_get_connector_status_name(connector->status);
+			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
+					connector->base.id,
+					connector->name,
+					old, new);
+			changed = true;
+		}
+	}
+	drm_connector_list_iter_end(&conn_iter);
+	mutex_unlock(&dev->mode_config.mutex);
+
+	if (changed)
+		drm_kms_helper_hotplug_event(dev);
+
+	phytium_dp_hpd_irq_setup(dev, true);
+}
+
+irqreturn_t phytium_dp_hpd_irq_handler(struct phytium_display_private *priv)
+{
+	struct drm_encoder *encoder = NULL;
+	struct phytium_dp_device *phytium_dp = NULL;
+	struct drm_device *dev = priv->dev;
+	bool handler = false;
+
+	spin_lock(&priv->hotplug_irq_lock);
+
+	drm_for_each_encoder(encoder, dev) {
+		phytium_dp = encoder_to_dp_device(encoder);
+		if (phytium_dp->dp_hpd_state.hpd_irq_enable) {
+			phytium_dp_hw_get_hpd_state(phytium_dp);
+			if (phytium_dp->dp_hpd_state.hpd_event_state
+			|| phytium_dp->dp_hpd_state.hpd_irq_state) {
+				handler = true;
+			}
+		}
+	}
+	spin_unlock(&priv->hotplug_irq_lock);
+
+	if (handler) {
+		phytium_dp_hpd_irq_setup(dev, false);
+		schedule_work(&priv->hotplug_work);
+		return IRQ_HANDLED;
+	}
+	return IRQ_NONE;
+}
+
+
+static void phytium_dp_fast_link_train_detect(struct phytium_dp_device *phytium_dp)
+{
+	phytium_dp->fast_train_support = !!(phytium_dp->dpcd[DP_MAX_DOWNSPREAD]
+					    & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
+	DRM_DEBUG_KMS("fast link training %s\n",
+		       phytium_dp->fast_train_support ? "supported" : "unsupported");
+}
+
+bool phytium_dp_fast_link_train(struct phytium_dp_device *phytium_dp)
+{
+	int ret = 0;
+	unsigned int training_pattern;
+
+	/* clear the test pattern */
+	phytium_dp_hw_set_test_pattern(phytium_dp, phytium_dp->link_lane_count,
+				       PHYTIUM_PHY_TP_NONE, NULL, 0);
+
+	/* config source and sink's link rate and lane count */
+	phytium_dp_hw_set_link(phytium_dp, phytium_dp->link_lane_count, phytium_dp->link_rate);
+
+	/* config source and sink's voltage swing and pre-emphasis(103-106) */
+	phytium_dp_hw_set_lane_setting(phytium_dp, phytium_dp->link_rate,
+				       phytium_dp->train_set[0]);
+
+	/* config train pattern */
+	phytium_dp_hw_set_train_pattern(phytium_dp, DP_TRAINING_PATTERN_1);
+	usleep_range(500, 600);
+
+	training_pattern = phytium_dp_get_training_pattern(phytium_dp);
+	phytium_dp_hw_set_train_pattern(phytium_dp, training_pattern);
+	usleep_range(500, 600);
+
+	phytium_dp_hw_set_train_pattern(phytium_dp, DP_TRAINING_PATTERN_DISABLE);
+
+	if (dc_fast_training_check) {
+		unsigned char link_status[DP_LINK_STATUS_SIZE];
+
+		ret = drm_dp_dpcd_read(&phytium_dp->aux, DP_LANE0_1_STATUS,
+				       link_status, DP_LINK_STATUS_SIZE);
+		if (ret < 0) {
+			DRM_ERROR("failed to get link status(DP_LANE0_1_STATUS)\n");
+			return false;
+		}
+
+		if (!drm_dp_clock_recovery_ok(link_status, phytium_dp->link_lane_count)) {
+			DRM_DEBUG_KMS("check clock recovery failed\n");
+			return false;
+		}
+
+		if (!drm_dp_channel_eq_ok(link_status, phytium_dp->link_lane_count)) {
+			DRM_DEBUG_KMS("check channel equalization failed\n");
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static enum drm_connector_status
+phytium_connector_detect(struct drm_connector *connector, bool force)
+{
+	enum drm_connector_status status = connector->status;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+	bool hpd_event_state, hpd_irq_state, hpd_raw_state;
+	struct drm_device *dev = phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	bool plugged = true;
+
+	spin_lock_irq(&priv->hotplug_irq_lock);
+	hpd_event_state = phytium_dp->dp_hpd_state.hpd_event_state;
+	hpd_irq_state = phytium_dp->dp_hpd_state.hpd_irq_state;
+	hpd_raw_state = phytium_dp->dp_hpd_state.hpd_raw_state;
+	phytium_dp->dp_hpd_state.hpd_event_state = false;
+	phytium_dp->dp_hpd_state.hpd_irq_state = false;
+	spin_unlock_irq(&priv->hotplug_irq_lock);
+
+	if (hpd_event_state)
+		status = phytium_dp_long_pulse(connector, hpd_raw_state);
+
+	if (hpd_irq_state)
+		status = phytium_dp_short_pulse(connector);
+
+	if (status == connector_status_unknown)
+		status = connector_status_disconnected;
+
+	if ((!phytium_dp->is_edp) && (!hpd_raw_state))
+		status = connector_status_disconnected;
+
+	if (connector->status != status) {
+		if ((status == connector_status_connected) && phytium_dp->has_audio)
+			plugged = true;
+		else
+			plugged = false;
+
+		handle_plugged_change(phytium_dp, plugged);
+	}
+
+	return status;
+}
+
+static void
+phytium_connector_destroy(struct drm_connector *connector)
+{
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	drm_connector_cleanup(connector);
+	kfree(phytium_dp);
+}
+
+static int
+phytium_dp_connector_register(struct drm_connector *connector)
+{
+	int ret;
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	phytium_dp_aux_init(phytium_dp);
+	if (phytium_dp->is_edp) {
+		phytium_edp_init_connector(phytium_dp);
+		ret = phytium_edp_backlight_device_register(phytium_dp);
+		if (ret)
+			DRM_ERROR("failed to register port(%d) backlight device(ret=%d)\n",
+				   phytium_dp->port, ret);
+	}
+
+	ret = phytium_debugfs_connector_add(connector);
+	if (ret)
+		DRM_ERROR("failed to register phytium connector debugfs(ret=%d)\n", ret);
+
+	return 0;
+}
+
+static void
+phytium_dp_connector_unregister(struct drm_connector *connector)
+{
+	struct phytium_dp_device *phytium_dp = connector_to_dp_device(connector);
+
+	if (phytium_dp->is_edp) {
+		phytium_edp_backlight_device_unregister(phytium_dp);
+		phytium_edp_fini_connector(phytium_dp);
+	}
+	drm_dp_aux_unregister(&phytium_dp->aux);
+}
+
+static const struct drm_connector_funcs phytium_connector_funcs = {
+	.dpms			= drm_helper_connector_dpms,
+	.detect			= phytium_connector_detect,
+	.fill_modes		= drm_helper_probe_single_connector_modes,
+	.destroy		= phytium_connector_destroy,
+	.reset			= drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
+	.late_register		= phytium_dp_connector_register,
+	.early_unregister	= phytium_dp_connector_unregister,
+};
+
+static void phytium_dp_encoder_mode_set(struct drm_encoder *encoder,
+						    struct drm_display_mode *mode,
+						    struct drm_display_mode *adjusted)
+{
+	struct phytium_dp_device *dp = encoder_to_dp_device(encoder);
+
+	drm_mode_copy(&dp->mode, adjusted);
+}
+
+static void phytium_edp_panel_poweron(struct phytium_dp_device *phytium_dp)
+{
+	phytium_panel_poweron(&phytium_dp->panel);
+}
+
+static void phytium_edp_panel_poweroff(struct phytium_dp_device *phytium_dp)
+{
+	phytium_panel_poweroff(&phytium_dp->panel);
+}
+
+static void phytium_edp_backlight_on(struct phytium_dp_device *phytium_dp)
+{
+	phytium_panel_enable_backlight(&phytium_dp->panel);
+}
+
+static void phytium_edp_backlight_off(struct phytium_dp_device *phytium_dp)
+{
+	phytium_panel_disable_backlight(&phytium_dp->panel);
+}
+
+static void phytium_encoder_disable(struct drm_encoder *encoder)
+{
+	struct phytium_dp_device *phytium_dp = encoder_to_dp_device(encoder);
+
+	if (phytium_dp->is_edp)
+		phytium_edp_backlight_off(phytium_dp);
+
+	phytium_dp_hw_disable_video(phytium_dp);
+
+	mdelay(50);
+
+	if (phytium_dp->is_edp)
+		phytium_edp_panel_poweroff(phytium_dp);
+}
+
+void phytium_dp_adjust_link_train_parameter(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_display_info *display_info = &phytium_dp->connector.display_info;
+	unsigned long link_bw, date_rate = 0, bs_limit, bs_request;
+	int rate = 0;
+
+	bs_request = phytium_dp->mode.crtc_htotal/(phytium_dp->mode.crtc_clock/1000);
+	date_rate = (phytium_dp->mode.crtc_clock * display_info->bpc * 3)/8;
+
+	for (;;) {
+		bs_limit = 8192 / (phytium_dp->link_rate/1000);
+		link_bw = phytium_dp->link_rate * phytium_dp->link_lane_count;
+		rate = 10 * date_rate / link_bw;
+		DRM_DEBUG_KMS("adjust link rate(%d), lane count(%d)\n",
+			       phytium_dp->link_rate, phytium_dp->link_lane_count);
+		DRM_DEBUG_KMS("for crtc_clock(%d) bs_request(%ld) bs_limit(%ld) rate(%d)\n",
+			       phytium_dp->mode.crtc_clock, bs_request, bs_limit, rate);
+		if ((link_dynamic_adjust && (bs_request < bs_limit) && rate < 10) ||
+		   ((!link_dynamic_adjust) && (rate < 10)))
+			break;
+		phytium_dp_get_link_train_fallback_values(phytium_dp);
+	}
+
+	DRM_DEBUG_KMS("Try link training at Link Rate = %d, Lane count = %d\n",
+		       phytium_dp->link_rate, phytium_dp->link_lane_count);
+}
+
+static void phytium_encoder_enable(struct drm_encoder *encoder)
+{
+	struct phytium_dp_device *phytium_dp = encoder_to_dp_device(encoder);
+	int ret = 0;
+
+	phytium_dp_hw_disable_video(phytium_dp);
+
+	if (phytium_dp->is_edp) {
+		phytium_edp_panel_poweron(phytium_dp);
+		if (phytium_dp->fast_train_support)
+			phytium_dp_fast_link_train(phytium_dp);
+		else
+			ret = phytium_dp_start_link_train(phytium_dp);
+		mdelay(2);
+		phytium_dp_fast_link_train_detect(phytium_dp);
+	} else {
+		phytium_dp_adjust_link_train_parameter(phytium_dp);
+		ret = phytium_dp_start_link_train(phytium_dp);
+		mdelay(2);
+	}
+
+	phytium_dp_hw_config_video(phytium_dp);
+	if (ret == 0) {
+		phytium_dp_hw_enable_video(phytium_dp);
+		if (phytium_dp->has_audio)
+			phytium_dp_hw_enable_audio(phytium_dp);
+	}
+
+	if (phytium_dp->is_edp) {
+		phytium_edp_backlight_on(phytium_dp);
+	}
+}
+
+enum drm_mode_status
+phytium_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode)
+{
+	struct phytium_dp_device *phytium_dp = encoder_to_dp_device(encoder);
+	struct drm_display_info *display_info = &phytium_dp->connector.display_info;
+	unsigned int requested, actual;
+
+	switch (display_info->bpc) {
+	case 10:
+	case 6:
+	case 8:
+		break;
+	default:
+		DRM_INFO("not support bpc(%d)\n", display_info->bpc);
+		display_info->bpc = 8;
+		break;
+	}
+
+	if ((display_info->color_formats & DRM_COLOR_FORMAT_RGB444) == 0) {
+		DRM_INFO("not support color_format(%d)\n", display_info->color_formats);
+		display_info->color_formats = DRM_COLOR_FORMAT_RGB444;
+	}
+
+	requested = mode->clock * display_info->bpc * 3 / 1000;
+	actual = phytium_dp->max_link_rate * phytium_dp->max_link_lane_count / 100;
+	actual = actual * 8 / 10;
+	if (requested >= actual) {
+		DRM_DEBUG_KMS("requested=%d, actual=%d, clock=%d\n", requested, actual,
+				mode->clock);
+		return MODE_CLOCK_HIGH;
+	}
+
+	if (dc_fake_mode_enable &&
+		(phytium_dp->native_mode.clock == mode->clock) &&
+		(phytium_dp->native_mode.htotal == mode->htotal) &&
+		(phytium_dp->native_mode.vtotal == mode->vtotal))
+		return MODE_OK;
+
+	if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
+		return MODE_BAD_HVALUE;
+
+	if ((mode->hdisplay == 1024) && (mode->clock > 78000))
+		return MODE_BAD_HVALUE;
+
+	if ((mode->hdisplay < 640) || (mode->vdisplay < 480))
+		return MODE_BAD_HVALUE;
+
+	return MODE_OK;
+}
+
+static const struct drm_encoder_helper_funcs phytium_encoder_helper_funcs = {
+	.mode_set = phytium_dp_encoder_mode_set,
+	.disable = phytium_encoder_disable,
+	.enable  = phytium_encoder_enable,
+	.mode_valid = phytium_encoder_mode_valid,
+};
+
+void phytium_dp_encoder_destroy(struct drm_encoder *encoder)
+{
+	struct phytium_dp_device *phytium_dp = encoder_to_dp_device(encoder);
+
+	phytium_dp_audio_codec_fini(phytium_dp);
+	drm_encoder_cleanup(encoder);
+}
+
+static const struct drm_encoder_funcs phytium_encoder_funcs = {
+	.destroy = phytium_dp_encoder_destroy,
+};
+
+static const struct dp_audio_n_m phytium_dp_audio_n_m[] = {
+	{ 32000,  162000, 1024, 10125 },
+	{ 44100,  162000, 784,  5625  },
+	{ 48000,  162000, 512,  3375  },
+	{ 64000,  162000, 2048, 10125 },
+	{ 88200,  162000, 1568, 5625  },
+	{ 96000,  162000, 1024, 3375  },
+	{ 128000, 162000, 4096, 10125 },
+	{ 176400, 162000, 3136, 5625  },
+	{ 192000, 162000, 2048, 3375  },
+	{ 32000,  270000, 1024, 16875 },
+	{ 44100,  270000, 784,  9375  },
+	{ 48000,  270000, 512,  5625  },
+	{ 64000,  270000, 2048, 16875 },
+	{ 88200,  270000, 1568, 9375  },
+	{ 96000,  270000, 1024, 5625  },
+	{ 128000, 270000, 4096, 16875 },
+	{ 176400, 270000, 3136, 9375  },
+	{ 192000, 270000, 2048, 5625  },
+	{ 32000,  540000, 1024, 33750 },
+	{ 44100,  540000, 784,  18750 },
+	{ 48000,  540000, 512,  11250 },
+	{ 64000,  540000, 2048, 33750 },
+	{ 88200,  540000, 1568, 18750 },
+	{ 96000,  540000, 1024, 11250 },
+	{ 128000, 540000, 4096, 33750 },
+	{ 176400, 540000, 3136, 18750 },
+	{ 192000, 540000, 2048, 11250 },
+	{ 32000,  810000, 1024, 50625 },
+	{ 44100,  810000, 784,  28125 },
+	{ 48000,  810000, 512,  16875 },
+	{ 64000,  810000, 2048, 50625 },
+	{ 88200,  810000, 1568, 28125 },
+	{ 96000,  810000, 1024, 16875 },
+	{ 128000, 810000, 4096, 50625 },
+	{ 176400, 810000, 3136, 28125 },
+	{ 192000, 810000, 2048, 16875 },
+};
+
+static int phytium_dp_audio_get_eld(struct device *dev, void *data, u8 *buf, size_t len)
+{
+	struct phytium_dp_device *phytium_dp = data;
+
+	memcpy(buf, phytium_dp->connector.eld, min(sizeof(phytium_dp->connector.eld), len));
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+static int phytium_dp_audio_digital_mute(struct device *dev, void *data, bool enable)
+{
+	struct phytium_dp_device *phytium_dp = data;
+
+	phytium_dp_hw_audio_digital_mute(phytium_dp, enable);
+
+	return 0;
+}
+#else
+static int phytium_dp_audio_mute_stream(struct device *dev, void *data, bool enable, int direction)
+{
+	struct phytium_dp_device *phytium_dp = data;
+
+	phytium_dp_hw_audio_digital_mute(phytium_dp, enable);
+
+	return 0;
+}
+#endif
+
+const struct dp_audio_n_m *phytium_dp_audio_get_n_m(int link_rate, int sample_rate)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(phytium_dp_audio_n_m); i++) {
+		if (sample_rate == phytium_dp_audio_n_m[i].sample_rate
+			&& link_rate == phytium_dp_audio_n_m[i].link_rate)
+			return &phytium_dp_audio_n_m[i];
+	}
+
+	return NULL;
+}
+
+static int phytium_dp_audio_hw_params(struct device *dev, void *data,
+						 struct hdmi_codec_daifmt *daifmt,
+						 struct hdmi_codec_params *params)
+{
+	struct phytium_dp_device *phytium_dp = data;
+	int ret = 0;
+	struct audio_info audio_info = {
+		.sample_width = params->sample_width,
+		.sample_rate = params->sample_rate,
+		.channels = params->channels,
+	};
+
+	if (daifmt->fmt != HDMI_I2S) {
+		DRM_ERROR("invalid audio format %d\n", daifmt->fmt);
+		ret = -EINVAL;
+		goto failed;
+	}
+
+	ret = phytium_dp_hw_audio_hw_params(phytium_dp, audio_info);
+
+failed:
+	return ret;
+}
+
+static void phytium_dp_audio_shutdown(struct device *dev, void *data)
+{
+	struct phytium_dp_device *phytium_dp = data;
+
+	phytium_dp_hw_audio_shutdown(phytium_dp);
+}
+
+static void handle_plugged_change(struct phytium_dp_device *phytium_dp, bool plugged)
+{
+	if (phytium_dp->plugged_cb && phytium_dp->codec_dev)
+		phytium_dp->plugged_cb(phytium_dp->codec_dev, plugged);
+}
+
+static int phytium_dp_audio_hook_plugged_cb(struct device *dev, void *data,
+				       hdmi_codec_plugged_cb fn,
+				       struct device *codec_dev)
+{
+	struct phytium_dp_device *phytium_dp = data;
+	bool plugged;
+
+	phytium_dp->plugged_cb = fn;
+	phytium_dp->codec_dev = codec_dev;
+
+	if ((phytium_dp->connector.status == connector_status_connected) && phytium_dp->has_audio)
+		plugged = true;
+	else
+		plugged = false;
+
+	handle_plugged_change(phytium_dp, plugged);
+	return 0;
+}
+
+
+static const struct hdmi_codec_ops phytium_audio_codec_ops = {
+	.hw_params = phytium_dp_audio_hw_params,
+	.audio_shutdown = phytium_dp_audio_shutdown,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+	.digital_mute = phytium_dp_audio_digital_mute,
+#else
+	.mute_stream = phytium_dp_audio_mute_stream,
+#endif
+	.get_eld = phytium_dp_audio_get_eld,
+	.hook_plugged_cb = phytium_dp_audio_hook_plugged_cb,
+};
+
+static int phytium_dp_audio_codec_init(struct phytium_dp_device *phytium_dp,
+				       const int port)
+{
+	struct device *dev = phytium_dp->dev->dev;
+	struct hdmi_codec_pdata codec_data = {
+		.i2s = 1,
+		.spdif = 0,
+		.ops = &phytium_audio_codec_ops,
+		.max_i2s_channels = 2,
+		.data = phytium_dp,
+	};
+
+	phytium_dp->audio_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
+							       codec_id + port,
+							       &codec_data, sizeof(codec_data));
+
+	return PTR_ERR_OR_ZERO(phytium_dp->audio_pdev);
+}
+
+static void phytium_dp_audio_codec_fini(struct phytium_dp_device *phytium_dp)
+{
+	if (!PTR_ERR_OR_ZERO(phytium_dp->audio_pdev))
+		platform_device_unregister(phytium_dp->audio_pdev);
+	phytium_dp->audio_pdev = NULL;
+}
+
+static long phytium_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+{
+	struct phytium_dp_device *phytium_dp = container_of(aux, struct phytium_dp_device, aux);
+	long ret = 0;
+
+	DRM_DEBUG_KMS("msg->size: 0x%lx\n", msg->size);
+
+	if (WARN_ON(msg->size > 16))
+		return -E2BIG;
+
+	switch (msg->request & ~DP_AUX_I2C_MOT) {
+	case DP_AUX_NATIVE_WRITE:
+	case DP_AUX_I2C_WRITE:
+	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
+		ret = phytium_dp_hw_aux_transfer_write(phytium_dp, msg);
+		DRM_DEBUG_KMS("aux write reply:0x%x ret:0x%lx\n", msg->reply, ret);
+		break;
+	case DP_AUX_NATIVE_READ:
+	case DP_AUX_I2C_READ:
+		ret = phytium_dp_hw_aux_transfer_read(phytium_dp, msg);
+		DRM_DEBUG_KMS("aux read ret:0x%lx\n", ret);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static void phytium_dp_aux_init(struct phytium_dp_device *phytium_dp)
+{
+	drm_dp_aux_init(&phytium_dp->aux);
+	phytium_dp->aux.name = kasprintf(GFP_KERNEL, "dp-%d", phytium_dp->port);
+	phytium_dp->aux.transfer = phytium_dp_aux_transfer;
+}
+
+int phytium_get_encoder_crtc_mask(struct phytium_dp_device *phytium_dp, int port)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int i, mask = 0;
+
+	for_each_pipe_masked(priv, i) {
+		if (i != port)
+			mask++;
+		else
+			break;
+	}
+
+	return BIT(mask);
+}
+
+static bool phytium_dp_is_edp(struct phytium_dp_device *phytium_dp, int port)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+
+	if (priv->info.edp_mask & BIT(port))
+		return true;
+	else
+		return false;
+}
+
+static bool phytium_edp_init_connector(struct phytium_dp_device *phytium_dp)
+{
+	enum drm_connector_status status;
+	struct drm_connector *connector = &phytium_dp->connector;
+
+	phytium_edp_panel_poweron(phytium_dp);
+
+	status = phytium_dp_detect_dpcd(phytium_dp);
+	if (status == connector_status_disconnected) {
+		DRM_ERROR("detect edp dpcd failed\n");
+		return false;
+	}
+
+	phytium_dp->edp_edid = drm_get_edid(connector, &phytium_dp->aux.ddc);
+	if (!phytium_dp->edp_edid) {
+		DRM_ERROR("get edp edid failed\n");
+		return false;
+	}
+
+	connector->status = status;
+	phytium_dp->max_link_rate = phytium_dp->common_rates[phytium_dp->num_common_rates-1];
+	phytium_dp->max_link_lane_count = phytium_dp->common_max_lane_count;
+	phytium_dp->link_rate = phytium_dp->max_link_rate;
+	phytium_dp->link_lane_count = phytium_dp->max_link_lane_count;
+	DRM_DEBUG_KMS("common_max_lane_count: %d, common_max_rate:%d\n",
+		       phytium_dp->max_link_lane_count, phytium_dp->max_link_rate);
+
+	return true;
+}
+
+static void phytium_edp_fini_connector(struct phytium_dp_device *phytium_dp)
+{
+	if (phytium_dp->edp_edid)
+		kfree(phytium_dp->edp_edid);
+
+	phytium_dp->edp_edid = NULL;
+	phytium_edp_panel_poweroff(phytium_dp);
+
+	return;
+}
+
+int phytium_dp_resume(struct drm_device *drm_dev)
+{
+	struct phytium_dp_device *phytium_dp;
+	struct drm_encoder *encoder;
+	int ret = 0;
+
+	drm_for_each_encoder(encoder, drm_dev) {
+		phytium_dp = encoder_to_dp_device(encoder);
+		if (phytium_dp->is_edp) {
+			phytium_edp_backlight_off(phytium_dp);
+			phytium_edp_panel_poweroff(phytium_dp);
+		}
+		ret = phytium_dp_hw_init(phytium_dp);
+		if (ret) {
+			DRM_ERROR("failed to initialize dp %d\n", phytium_dp->port);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+int phytium_dp_init(struct drm_device *dev, int port)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_dp_device *phytium_dp = NULL;
+	int ret, type;
+
+	DRM_DEBUG_KMS("%s: port %d\n", __func__, port);
+	phytium_dp = kzalloc(sizeof(*phytium_dp), GFP_KERNEL);
+	if (!phytium_dp) {
+		ret = -ENOMEM;
+		goto failed_malloc_dp;
+	}
+
+	phytium_dp->dev = dev;
+	phytium_dp->port = port;
+
+	if (IS_PX210(priv)) {
+		px210_dp_func_register(phytium_dp);
+		priv->dp_reg_base[port] = PX210_DP_BASE(port);
+		priv->phy_access_base[port] = PX210_PHY_ACCESS_BASE(port);
+	} else if (IS_PE220X(priv)) {
+		pe220x_dp_func_register(phytium_dp);
+		priv->dp_reg_base[port] = PE220X_DP_BASE(port);
+		priv->phy_access_base[port] = PE220X_PHY_ACCESS_BASE(port);
+	}
+
+	if (phytium_dp_is_edp(phytium_dp, port)) {
+		phytium_dp->is_edp = true;
+		type = DRM_MODE_CONNECTOR_eDP;
+		phytium_dp_panel_init_backlight_funcs(phytium_dp);
+		phytium_edp_backlight_off(phytium_dp);
+		phytium_edp_panel_poweroff(phytium_dp);
+	} else {
+		phytium_dp->is_edp = false;
+		type = DRM_MODE_CONNECTOR_DisplayPort;
+	}
+
+	ret = phytium_dp_hw_init(phytium_dp);
+	if (ret) {
+		DRM_ERROR("failed to initialize dp %d\n", phytium_dp->port);
+		goto failed_init_dp;
+	}
+
+	ret = drm_encoder_init(dev, &phytium_dp->encoder,
+			       &phytium_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS, "DP %d", port);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		goto failed_encoder_init;
+	}
+	drm_encoder_helper_add(&phytium_dp->encoder, &phytium_encoder_helper_funcs);
+	phytium_dp->encoder.possible_crtcs = phytium_get_encoder_crtc_mask(phytium_dp, port);
+
+	phytium_dp->connector.dpms   = DRM_MODE_DPMS_OFF;
+	phytium_dp->connector.polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
+	ret = drm_connector_init(dev, &phytium_dp->connector, &phytium_connector_funcs,
+				 type);
+	if (ret) {
+		DRM_ERROR("failed to initialize connector with drm\n");
+		goto failed_connector_init;
+	}
+	drm_connector_helper_add(&phytium_dp->connector, &phytium_connector_helper_funcs);
+	drm_connector_attach_encoder(&phytium_dp->connector, &phytium_dp->encoder);
+
+	ret = phytium_dp_audio_codec_init(phytium_dp, port);
+	if (ret) {
+		DRM_ERROR("failed to initialize audio codec\n");
+		goto failed_connector_init;
+	}
+
+	phytium_dp->train_retry_count = 0;
+	INIT_WORK(&phytium_dp->train_retry_work, phytium_dp_train_retry_work_fn);
+	drm_connector_register(&phytium_dp->connector);
+
+	return 0;
+failed_connector_init:
+failed_encoder_init:
+failed_init_dp:
+	kfree(phytium_dp);
+failed_malloc_dp:
+	return ret;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_dp.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_dp.h
new file mode 100644
index 00000000000000..3433f294424bb5
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_dp.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_DP_H__
+#define __PHYTIUM_DP_H__
+
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_encoder.h>
+#include <sound/hdmi-codec.h>
+
+struct phytium_dp_device;
+
+#include "phytium_panel.h"
+
+struct audio_info {
+	int sample_rate;
+	int channels;
+	int sample_width;
+};
+
+struct dp_audio_n_m {
+	int sample_rate;
+	int link_rate;
+	u16 m;
+	u16 n;
+};
+
+struct phytium_dp_compliance {
+	unsigned long test_type;
+	uint32_t test_link_rate;
+	u8 test_lane_count;
+	bool test_active;
+	u8 reserve[2];
+};
+
+struct phytium_dp_func {
+	uint8_t (*dp_hw_get_source_lane_count)(struct phytium_dp_device *phytium_dp);
+	int (*dp_hw_reset)(struct phytium_dp_device *phytium_dp);
+	bool (*dp_hw_spread_is_enable)(struct phytium_dp_device *phytium_dp);
+	int (*dp_hw_set_backlight)(struct phytium_dp_device *phytium_dp, uint32_t level);
+	uint32_t (*dp_hw_get_backlight)(struct phytium_dp_device *phytium_dp);
+	void (*dp_hw_disable_backlight)(struct phytium_dp_device *phytium_dp);
+	void (*dp_hw_enable_backlight)(struct phytium_dp_device *phytium_dp);
+	void (*dp_hw_poweroff_panel)(struct phytium_dp_device *phytium_dp);
+	void (*dp_hw_poweron_panel)(struct phytium_dp_device *phytium_dp);
+	int (*dp_hw_init_phy)(struct phytium_dp_device *phytium_dp);
+	void (*dp_hw_set_phy_lane_setting)(struct phytium_dp_device *phytium_dp,
+					   uint32_t link_rate, uint8_t train_set);
+	int (*dp_hw_set_phy_lane_and_rate)(struct phytium_dp_device *phytium_dp,
+					   uint8_t link_lane_count,
+					   uint32_t link_rate);
+};
+
+struct phytium_dp_hpd_state {
+	bool hpd_event_state;
+	bool hpd_irq_state;
+	bool hpd_raw_state;
+	bool hpd_irq_enable;
+};
+
+struct phytium_dp_device {
+	struct drm_device *dev;
+	struct drm_encoder encoder;
+	struct drm_connector connector;
+	int port;
+	struct drm_display_mode mode;
+	bool	link_trained;
+	bool	detect_done;
+	bool	is_edp;
+	bool	reserve0;
+	struct drm_dp_aux aux;
+	unsigned char dpcd[DP_RECEIVER_CAP_SIZE];
+	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+	unsigned char downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+	unsigned char sink_count;
+
+	int *source_rates;
+	int num_source_rates;
+	int sink_rates[DP_MAX_SUPPORTED_RATES];
+	int num_sink_rates;
+	int common_rates[DP_MAX_SUPPORTED_RATES];
+	int num_common_rates;
+
+	int source_max_lane_count;
+	int sink_max_lane_count;
+	int common_max_lane_count;
+
+	int max_link_rate;
+	int max_link_lane_count;
+	int link_rate;
+	int link_lane_count;
+	struct work_struct train_retry_work;
+	int train_retry_count;
+	uint32_t trigger_train_fail;
+
+	unsigned char train_set[4];
+	struct edid *edp_edid;
+	bool has_audio;
+	bool fast_train_support;
+	bool hw_spread_enable;
+	bool reserve[1];
+	struct platform_device *audio_pdev;
+	struct audio_info audio_info;
+	hdmi_codec_plugged_cb plugged_cb;
+	struct device *codec_dev;
+	struct phytium_dp_compliance compliance;
+	struct phytium_dp_func *funcs;
+	struct phytium_dp_hpd_state dp_hpd_state;
+
+	struct phytium_panel panel;
+	struct drm_display_mode native_mode;
+};
+
+union phytium_phy_tp {
+	struct {
+		/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
+		 * and 3 bits for DP1.2.
+		 */
+		uint8_t PATTERN	:3;
+		uint8_t RESERVED	:5;
+	} bits;
+	uint8_t raw;
+};
+
+/* PHY test patterns
+ * The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
+ */
+enum phytium_dpcd_phy_tp {
+	PHYTIUM_PHY_TP_NONE = 0,
+	PHYTIUM_PHY_TP_D10_2,
+	PHYTIUM_PHY_TP_SYMBOL_ERROR,
+	PHYTIUM_PHY_TP_PRBS7,
+	PHYTIUM_PHY_TP_80BIT_CUSTOM,
+	PHYTIUM_PHY_TP_CP2520_1,
+	PHYTIUM_PHY_TP_CP2520_2,
+	PHYTIUM_PHY_TP_CP2520_3,
+};
+#define PHYTIUM_DP_AUDIO_ID	(('P' << 24) + ('H' << 16) + ('Y' << 8))
+#define encoder_to_dp_device(x) container_of(x, struct phytium_dp_device, encoder)
+#define connector_to_dp_device(x) container_of(x, struct phytium_dp_device, connector)
+#define panel_to_dp_device(x) container_of(x, struct phytium_dp_device, panel)
+#define train_retry_to_dp_device(x)	container_of(x, struct phytium_dp_device, train_retry_work)
+void phytium_phy_writel(struct phytium_dp_device *phytium_dp, uint32_t address, uint32_t data);
+uint32_t phytium_phy_readl(struct phytium_dp_device *phytium_dp, uint32_t address);
+
+int phytium_dp_init(struct drm_device *dev, int pipe);
+int phytium_dp_resume(struct drm_device *drm_dev);
+void phytium_dp_hpd_irq_setup(struct drm_device *dev, bool enable);
+irqreturn_t phytium_dp_hpd_irq_handler(struct phytium_display_private *priv);
+void phytium_dp_hpd_work_func(struct work_struct *work);
+const struct dp_audio_n_m *phytium_dp_audio_get_n_m(int link_rate, int sample_rate);
+#endif /* __PHYTIUM_DP_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fb.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fb.c
new file mode 100644
index 00000000000000..724c02720d6b2c
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fb.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_gem.h>
+#include <drm/drm_modeset_helper.h>
+#include <drm/drm_fourcc.h>
+#include "phytium_display_drv.h"
+#include "phytium_fb.h"
+#include "phytium_gem.h"
+
+static int
+phytium_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file_priv,
+				   unsigned int *handle)
+{
+	struct phytium_framebuffer *phytium_fb = to_phytium_framebuffer(fb);
+
+	return drm_gem_handle_create(file_priv, &phytium_fb->phytium_gem_obj[0]->base, handle);
+}
+
+static void phytium_fb_destroy(struct drm_framebuffer *fb)
+{
+	struct phytium_framebuffer *phytium_fb = to_phytium_framebuffer(fb);
+	int i, num_planes;
+	struct drm_gem_object *obj = NULL;
+	const struct drm_format_info *info;
+
+	info = drm_format_info(fb->format->format);
+	num_planes = info ? info->num_planes : 1;
+
+	for (i = 0; i < num_planes; i++) {
+		obj = &phytium_fb->phytium_gem_obj[i]->base;
+		if (obj)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+			drm_gem_object_put(obj);
+#else
+			drm_gem_object_unreference_unlocked(obj);
+#endif
+	}
+
+	drm_framebuffer_cleanup(fb);
+	kfree(phytium_fb);
+}
+
+static struct drm_framebuffer_funcs viv_fb_funcs = {
+	.create_handle	= phytium_fb_create_handle,
+	.destroy	= phytium_fb_destroy,
+};
+
+struct phytium_framebuffer *
+phytium_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd,
+		       struct phytium_gem_object **phytium_gem_obj, unsigned int num_planes)
+{
+	struct phytium_framebuffer *phytium_fb;
+	int ret = 0, i;
+
+	phytium_fb = kzalloc(sizeof(*phytium_fb), GFP_KERNEL);
+	if (!phytium_fb)
+		return ERR_PTR(-ENOMEM);
+
+	drm_helper_mode_fill_fb_struct(dev, &phytium_fb->base, mode_cmd);
+
+	ret = drm_framebuffer_init(dev, &phytium_fb->base, &viv_fb_funcs);
+
+	if (ret) {
+		DRM_ERROR("Failed to initialize framebuffer: %d\n", ret);
+		kfree(phytium_fb);
+		return ERR_PTR(ret);
+	}
+
+	for (i = 0; i < num_planes; i++) {
+		phytium_fb->phytium_gem_obj[i] = phytium_gem_obj[i];
+		phytium_fb->base.obj[i] = &phytium_gem_obj[i]->base;
+	}
+	return phytium_fb;
+}
+
+struct drm_framebuffer *
+phytium_fb_create(struct drm_device *dev, struct drm_file *file_priv,
+			 const struct drm_mode_fb_cmd2 *mode_cmd)
+{
+	int ret = 0, i, num_planes;
+	struct drm_gem_object *obj;
+	unsigned int hsub, vsub, size;
+	struct phytium_gem_object *phytium_gem_obj[PHYTIUM_FORMAT_MAX_PLANE] = {0};
+	struct phytium_framebuffer *phytium_fb;
+	struct phytium_display_private *priv = dev->dev_private;
+	const struct drm_format_info *info;
+
+	info = drm_format_info(mode_cmd->pixel_format);
+	hsub = info ? info->hsub : 1;
+	vsub = info ? info->vsub : 1;
+	num_planes = info ? info->num_planes : 1;
+	num_planes = min(num_planes, PHYTIUM_FORMAT_MAX_PLANE);
+
+	for (i = 0; i < num_planes; i++) {
+		unsigned int height = mode_cmd->height / (i ? vsub : 1);
+
+		size = height * mode_cmd->pitches[i] + mode_cmd->offsets[i];
+		obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]);
+		if (!obj) {
+			DRM_ERROR("Failed to lookup GEM object\n");
+			ret = -ENXIO;
+			goto error;
+		}
+
+		if (obj->size < size) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+			drm_gem_object_put(obj);
+#else
+			drm_gem_object_unreference_unlocked(obj);
+#endif
+			ret = -EINVAL;
+			goto error;
+		}
+
+		phytium_gem_obj[i] = to_phytium_gem_obj(obj);
+
+		ret = priv->dc_hw_fb_format_check(mode_cmd, i);
+		if (ret < 0)
+			goto error;
+	}
+
+	phytium_fb = phytium_fb_alloc(dev, mode_cmd, phytium_gem_obj, i);
+	if (IS_ERR(phytium_fb)) {
+		DRM_DEBUG_KMS("phytium_fb_alloc failed\n");
+		ret = PTR_ERR(phytium_fb);
+		goto error;
+	}
+
+	return &phytium_fb->base;
+error:
+	for (i--; i >= 0; i--)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+		drm_gem_object_put(&phytium_gem_obj[i]->base);
+#else
+		drm_gem_object_unreference_unlocked(&phytium_gem_obj[i]->base);
+#endif
+
+	return ERR_PTR(ret);
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fb.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fb.h
new file mode 100644
index 00000000000000..054b0ab15a00b2
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fb.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_FB_H__
+#define __PHYTIUM_FB_H__
+
+#include <drm/drm_framebuffer.h>
+
+struct phytium_framebuffer {
+	struct drm_framebuffer base;
+	struct phytium_gem_object *phytium_gem_obj[PHYTIUM_FORMAT_MAX_PLANE];
+};
+
+#define	to_phytium_framebuffer(fb)	container_of(fb, struct phytium_framebuffer, base)
+
+struct phytium_framebuffer *phytium_fb_alloc(struct drm_device *dev,
+						   const struct drm_mode_fb_cmd2 *mode_cmd,
+						   struct phytium_gem_object **phytium_gem_obj,
+						   unsigned int num_planes);
+
+struct drm_framebuffer *phytium_fb_create(struct drm_device *dev, struct drm_file *file_priv,
+						 const struct drm_mode_fb_cmd2 *mode_cmd);
+#endif /* __PHYTIUM_FB_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fbdev.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fbdev.c
new file mode 100644
index 00000000000000..dd0c2920813200
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fbdev.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fourcc.h>
+#include "phytium_display_drv.h"
+#include "phytium_gem.h"
+#include "phytium_fb.h"
+
+
+#define	PHYTIUM_MAX_CONNECTOR	1
+#define	helper_to_drm_private(x) container_of(x, struct phytium_display_private, fbdev_helper)
+
+static int phytium_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct drm_fb_helper *helper = info->par;
+	struct phytium_display_private *priv = helper_to_drm_private(helper);
+
+	return phytium_gem_mmap_obj(&priv->fbdev_phytium_gem->base, vma);
+}
+
+static struct fb_ops phytium_fbdev_ops = {
+	.owner = THIS_MODULE,
+	 DRM_FB_HELPER_DEFAULT_OPS,
+	.fb_mmap = phytium_fbdev_mmap,
+	.fb_fillrect = drm_fb_helper_cfb_fillrect,
+	.fb_copyarea = drm_fb_helper_cfb_copyarea,
+	.fb_imageblit = drm_fb_helper_cfb_imageblit,
+};
+
+static int
+phytium_drm_fbdev_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes)
+{
+	struct phytium_display_private *priv = helper_to_drm_private(helper);
+	struct drm_device *dev = helper->dev;
+	unsigned int bytes_per_pixel;
+	struct drm_mode_fb_cmd2	mode_cmd = {0};
+	struct phytium_framebuffer *phytium_fb =  NULL;
+	struct fb_info *fbi =  NULL;
+	struct drm_framebuffer *fb = NULL;
+	size_t size = 0;
+	int ret = 0;
+	unsigned long offset;
+
+	bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);
+	mode_cmd.width = sizes->surface_width;
+	mode_cmd.height = sizes->surface_height;
+	mode_cmd.pitches[0] =  ALIGN(sizes->surface_width * bytes_per_pixel, 128);
+	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth);
+	size = PAGE_ALIGN(mode_cmd.pitches[0] * mode_cmd.height);
+
+	ret = mutex_lock_interruptible(&dev->struct_mutex);
+	if (ret < 0) {
+		DRM_ERROR("failed to get mutex lock\n");
+		return ret;
+	}
+
+	priv->fbdev_phytium_gem = phytium_gem_create_object(dev, size);
+	if (!priv->fbdev_phytium_gem) {
+		DRM_ERROR("failed to create gem object\n");
+		return -ENOMEM;
+	}
+	mutex_unlock(&dev->struct_mutex);
+
+	fbi = drm_fb_helper_alloc_fbi(helper);
+	if (IS_ERR(fbi)) {
+		DRM_DEV_ERROR(dev->dev, "Failed to create framebuffer info.");
+		ret = PTR_ERR(fbi);
+		goto out;
+	}
+
+	phytium_fb = phytium_fb_alloc(dev, &mode_cmd, &priv->fbdev_phytium_gem, 1);
+	if (IS_ERR(phytium_fb)) {
+		DRM_DEV_ERROR(dev->dev, "Failed to alloc DRM framebuffer.\n");
+		ret = PTR_ERR(phytium_fb);
+		goto out;
+	}
+
+	helper->fb = &(phytium_fb->base);
+	fbi->par = helper;
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->fbops = &phytium_fbdev_ops;
+
+	fb = helper->fb;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+	drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth);
+	drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height);
+#else
+	drm_fb_helper_fill_info(fbi, helper, sizes);
+#endif
+
+	offset = fbi->var.xoffset * bytes_per_pixel;
+	offset += fbi->var.yoffset * fb->pitches[0];
+	dev->mode_config.fb_base = 0;
+	fbi->screen_base = priv->fbdev_phytium_gem->vaddr + offset;
+	fbi->screen_size = priv->fbdev_phytium_gem->base.size;
+	fbi->fix.smem_len = priv->fbdev_phytium_gem->base.size;
+	DRM_DEBUG_KMS("FB [%dx%d]-%d kvaddr=%pa offset=%ld size=%zu\n", fb->width, fb->height,
+		       fb->format->depth, &priv->fbdev_phytium_gem->iova, offset, size);
+	fbi->skip_vt_switch = true;
+
+	return 0;
+out:
+	phytium_gem_free_object(&priv->fbdev_phytium_gem->base);
+	return ret;
+}
+
+static const struct drm_fb_helper_funcs phytium_drm_fb_helper_funcs = {
+	.fb_probe = phytium_drm_fbdev_create,
+};
+
+int phytium_drm_fbdev_init(struct drm_device *dev)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	struct drm_fb_helper *helper;
+	int ret;
+
+	if (!dev->mode_config.num_crtc || !dev->mode_config.num_connector)
+		return -EINVAL;
+
+	helper = &priv->fbdev_helper;
+	drm_fb_helper_prepare(dev, helper, &phytium_drm_fb_helper_funcs);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+	ret = drm_fb_helper_init(dev, helper, PHYTIUM_MAX_CONNECTOR);
+#else
+	ret = drm_fb_helper_init(dev, helper);
+#endif
+	if (ret < 0) {
+		DRM_DEV_ERROR(dev->dev, "Failed to initialize drm fb helper -ret %d\n", ret);
+		return ret;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+	ret = drm_fb_helper_single_add_all_connectors(helper);
+	if (ret < 0) {
+		DRM_DEV_ERROR(dev->dev, "Failed to add connectors - %d/\n", ret);
+		goto err_drm_fb_helper_fini;
+	}
+#endif
+	ret = drm_fb_helper_initial_config(helper, 32);
+	return ret;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
+err_drm_fb_helper_fini:
+	drm_fb_helper_fini(helper);
+	return ret;
+#endif
+}
+
+void phytium_drm_fbdev_fini(struct drm_device *dev)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	struct drm_fb_helper *helper;
+
+	helper = &priv->fbdev_helper;
+	drm_fb_helper_unregister_fbi(helper);
+
+	if (helper->fb)
+		drm_framebuffer_put(helper->fb);
+
+	drm_fb_helper_fini(helper);
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fbdev.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fbdev.h
new file mode 100644
index 00000000000000..81070502c8e07a
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_fbdev.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef	_PHYTIUM_FBDEV_H
+#define _PHYTIUM_FBDEV_H
+
+int phytium_drm_fbdev_init(struct drm_device *dev);
+void phytium_drm_fbdev_fini(struct drm_device *dev);
+
+#endif /* _PHYTIUM_FBDEV_H */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_gem.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_gem.c
new file mode 100644
index 00000000000000..cc51b0f96d22d7
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_gem.c
@@ -0,0 +1,535 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/dma-buf.h>
+#include <linux/vmalloc.h>
+#include <linux/version.h>
+#include <linux/mm_types.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+#include <linux/genalloc.h>
+#include <drm/drm_prime.h>
+#include <linux/dmaengine.h>
+#include <linux/completion.h>
+#include "phytium_display_drv.h"
+#include "phytium_gem.h"
+
+#define VRAM_POOL_ALLOC_ORDER 12
+
+int phytium_memory_pool_alloc(struct phytium_display_private *priv, void **pvaddr,
+					phys_addr_t *phys_addr, uint64_t size)
+{
+	unsigned long vaddr;
+
+	vaddr = gen_pool_alloc(priv->memory_pool, size);
+	if (!vaddr)
+		return -ENOMEM;
+
+	*phys_addr = gen_pool_virt_to_phys(priv->memory_pool, vaddr);
+
+	*pvaddr = (void *)vaddr;
+	return 0;
+}
+
+void phytium_memory_pool_free(struct phytium_display_private *priv, void *vaddr, uint64_t size)
+{
+	gen_pool_free(priv->memory_pool, (unsigned long)vaddr, size);
+}
+
+int phytium_memory_pool_init(struct device *dev, struct phytium_display_private *priv)
+{
+	int ret = 0;
+
+	priv->memory_pool = gen_pool_create(VRAM_POOL_ALLOC_ORDER, -1);
+	if (priv->memory_pool == NULL) {
+		DRM_ERROR("fail to create memory pool\n");
+		ret = -1;
+		goto failed_create_pool;
+	}
+
+	ret = gen_pool_add_virt(priv->memory_pool, (unsigned long)priv->pool_virt_addr,
+				priv->pool_phys_addr, priv->pool_size, -1);
+	if (ret) {
+		DRM_ERROR("fail to add vram pool\n");
+		ret = -1;
+		goto failed_add_pool_virt;
+	}
+
+	return 0;
+
+failed_add_pool_virt:
+	gen_pool_destroy(priv->memory_pool);
+
+failed_create_pool:
+	return ret;
+}
+
+void phytium_memory_pool_fini(struct device *dev, struct phytium_display_private *priv)
+{
+	gen_pool_destroy(priv->memory_pool);
+}
+
+struct sg_table *
+phytium_gem_prime_get_sg_table(struct drm_gem_object *obj)
+{
+	struct phytium_gem_object *phytium_gem_obj = to_phytium_gem_obj(obj);
+	struct sg_table *sgt;
+	struct drm_device *dev = obj->dev;
+	int ret;
+	struct page *page = NULL;
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		DRM_DEBUG_KMS("malloc sgt fail\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	if ((phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM) ||
+	    (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT)) {
+		ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
+		if (ret) {
+			DRM_ERROR("failed to allocate sg\n");
+			goto sgt_free;
+		}
+		page = phys_to_page(phytium_gem_obj->phys_addr);
+		sg_set_page(sgt->sgl, page, PAGE_ALIGN(phytium_gem_obj->size), 0);
+	} else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_UNIFIED) {
+		ret = dma_get_sgtable_attrs(dev->dev, sgt, phytium_gem_obj->vaddr,
+				    phytium_gem_obj->iova, phytium_gem_obj->size,
+				    DMA_ATTR_WRITE_COMBINE);
+		if (ret) {
+			DRM_ERROR("failed to allocate sgt, %d\n", ret);
+			goto sgt_free;
+		}
+	}
+
+	return sgt;
+sgt_free:
+	kfree(sgt);
+	return ERR_PTR(ret);
+}
+
+struct drm_gem_object *
+phytium_gem_prime_import_sg_table(struct drm_device *dev,
+					       struct dma_buf_attachment *attach,
+					       struct sg_table *sgt)
+{
+	struct phytium_gem_object *phytium_gem_obj = NULL;
+	struct scatterlist *s;
+	dma_addr_t expected;
+	int ret, i;
+
+	phytium_gem_obj = kzalloc(sizeof(*phytium_gem_obj), GFP_KERNEL);
+	if (!phytium_gem_obj) {
+		DRM_ERROR("failed to allocate phytium_gem_obj\n");
+		ret = -ENOMEM;
+		goto failed_malloc;
+	}
+
+	ret = drm_gem_object_init(dev, &phytium_gem_obj->base, attach->dmabuf->size);
+	if (ret) {
+		DRM_ERROR("failed to initialize drm gem object: %d\n", ret);
+		goto failed_object_init;
+	}
+
+	expected = sg_dma_address(sgt->sgl);
+	for_each_sg(sgt->sgl, s, sgt->nents, i) {
+		if (sg_dma_address(s) != expected) {
+			DRM_ERROR("sg_table is not contiguous");
+			ret = -EINVAL;
+			goto failed_check_continue;
+		}
+		expected = sg_dma_address(s) + sg_dma_len(s);
+	}
+
+	phytium_gem_obj->iova = sg_dma_address(sgt->sgl);
+	phytium_gem_obj->sgt = sgt;
+
+	return &phytium_gem_obj->base;
+failed_check_continue:
+	drm_gem_object_release(&phytium_gem_obj->base);
+failed_object_init:
+	kfree(phytium_gem_obj);
+failed_malloc:
+	return ERR_PTR(ret);
+}
+
+void *phytium_gem_prime_vmap(struct drm_gem_object *obj)
+{
+	struct phytium_gem_object *phytium_obj = to_phytium_gem_obj(obj);
+
+	return phytium_obj->vaddr;
+}
+
+void phytium_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
+{
+	return;
+}
+
+int phytium_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+	int ret = 0;
+
+	ret = drm_gem_mmap_obj(obj, obj->size, vma);
+	if (ret < 0)
+		return ret;
+
+	return phytium_gem_mmap_obj(obj, vma);
+}
+
+static void phytium_dma_callback(void *callback_param)
+{
+	struct completion *comp = callback_param;
+
+	complete(comp);
+}
+
+int phytium_dma_transfer(struct drm_device *drm_dev, int dev_to_mem, void *addr,
+			 dma_addr_t iova, uint64_t size)
+{
+	struct phytium_display_private *priv = drm_dev->dev_private;
+	struct dma_chan *dma_chan = priv->dma_chan;
+	struct sg_table st;
+	struct scatterlist *sgl;
+	int ret = 0, timeout;
+	uint32_t nents, i;
+	struct dma_slave_config cfg = {0};
+	struct dma_async_tx_descriptor *desc;
+	struct completion comp;
+	enum dma_data_direction dir;
+	size_t min = 0;
+
+	nents = DIV_ROUND_UP(size, PAGE_SIZE);
+	ret = sg_alloc_table(&st, nents, GFP_KERNEL);
+	if (ret) {
+		DRM_ERROR("failed to allocate sg_table\n");
+		ret = -ENOMEM;
+		goto failed_sg_alloc_table;
+	}
+
+	for_each_sg(st.sgl, sgl, st.nents, i) {
+		min = min_t(size_t, size, PAGE_SIZE - offset_in_page(addr));
+		sg_set_page(sgl, vmalloc_to_page(addr), min, offset_in_page(addr));
+		addr += min;
+		size -= min;
+	}
+
+	memset(&cfg, 0, sizeof(cfg));
+	if (dev_to_mem) {
+		cfg.direction = DMA_DEV_TO_MEM;
+		cfg.src_addr = iova;
+		cfg.dst_addr = 0;
+		dir = DMA_FROM_DEVICE;
+	} else {
+		cfg.direction = DMA_MEM_TO_DEV;
+		cfg.src_addr = 0;
+		cfg.dst_addr = iova;
+		dir = DMA_TO_DEVICE;
+	}
+
+	dmaengine_slave_config(dma_chan, &cfg);
+
+	nents = dma_map_sg(dma_chan->device->dev, st.sgl, st.nents, dir);
+	if (!nents) {
+		DRM_DEV_ERROR(drm_dev->dev, "failed to dma_map_sg for dmaengine\n");
+		ret = -EINVAL;
+		goto failed_dma_map_sg;
+	}
+	st.nents = nents;
+	dma_sync_sg_for_device(dma_chan->device->dev, st.sgl, st.nents, dir);
+
+	sgl = st.sgl;
+	desc = dmaengine_prep_slave_sg(dma_chan,
+					st.sgl,
+					st.nents,
+					cfg.direction,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!desc) {
+		DRM_DEV_ERROR(drm_dev->dev, "failed to dmaengine_prep_slave_sg\n");
+		ret = -EINVAL;
+		goto failed_prep_slave_sg;
+	}
+	init_completion(&comp);
+	desc->callback = phytium_dma_callback;
+	desc->callback_param = &comp;
+
+	dmaengine_submit(desc);
+	dma_async_issue_pending(dma_chan);
+
+	timeout = wait_for_completion_timeout(&comp, 2 * HZ);
+	if (timeout == 0) {
+		DRM_DEV_ERROR(drm_dev->dev, "wait for dma callback timeout\n");
+		ret = -EIO;
+	}
+	dma_sync_sg_for_cpu(dma_chan->device->dev, st.sgl, st.nents, dir);
+
+failed_prep_slave_sg:
+	dma_unmap_sg(dma_chan->device->dev, st.sgl, st.nents, dir);
+failed_dma_map_sg:
+	sg_free_table(&st);
+failed_sg_alloc_table:
+	return ret;
+}
+
+int phytium_gem_suspend(struct drm_device *drm_dev)
+{
+	struct phytium_display_private *priv = drm_dev->dev_private;
+	struct phytium_gem_object *phytium_gem_obj = NULL;
+	int ret = 0;
+
+	list_for_each_entry(phytium_gem_obj, &priv->gem_list_head, list) {
+		if (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM)
+			continue;
+
+		phytium_gem_obj->vaddr_save = vmalloc(phytium_gem_obj->size);
+		if (!phytium_gem_obj->vaddr_save)
+			goto malloc_failed;
+
+		if (priv->dma_inited)
+			ret = phytium_dma_transfer(drm_dev, 1, phytium_gem_obj->vaddr_save,
+						   phytium_gem_obj->iova, phytium_gem_obj->size);
+
+		if ((!priv->dma_inited) || ret)
+			memcpy(phytium_gem_obj->vaddr_save, phytium_gem_obj->vaddr,
+			       phytium_gem_obj->size);
+	}
+
+	return 0;
+malloc_failed:
+	list_for_each_entry(phytium_gem_obj, &priv->gem_list_head, list) {
+		if (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM)
+			continue;
+
+		if (phytium_gem_obj->vaddr_save) {
+			vfree(phytium_gem_obj->vaddr_save);
+			phytium_gem_obj->vaddr_save = NULL;
+		}
+	}
+	return -ENOMEM;
+}
+
+void phytium_gem_resume(struct drm_device *drm_dev)
+{
+	struct phytium_display_private *priv = drm_dev->dev_private;
+	struct phytium_gem_object *phytium_gem_obj = NULL;
+
+	list_for_each_entry(phytium_gem_obj, &priv->gem_list_head, list) {
+		if (phytium_gem_obj->memory_type != MEMORY_TYPE_VRAM)
+			continue;
+
+		memcpy(phytium_gem_obj->vaddr, phytium_gem_obj->vaddr_save, phytium_gem_obj->size);
+		vfree(phytium_gem_obj->vaddr_save);
+		phytium_gem_obj->vaddr_save = NULL;
+	}
+}
+
+void phytium_gem_free_object(struct drm_gem_object *obj)
+{
+	struct phytium_gem_object *phytium_gem_obj = to_phytium_gem_obj(obj);
+	struct drm_device *dev = obj->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	uint64_t size = phytium_gem_obj->size;
+
+	DRM_DEBUG_KMS("free phytium_gem_obj iova:0x%pa size:0x%lx\n",
+		      &phytium_gem_obj->iova, phytium_gem_obj->size);
+	if (phytium_gem_obj->vaddr) {
+		if (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM) {
+			phytium_memory_pool_free(priv, phytium_gem_obj->vaddr, size);
+			priv->mem_state[PHYTIUM_MEM_VRAM_ALLOC] -= size;
+		} else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT) {
+			dma_unmap_page(dev->dev, phytium_gem_obj->iova, size, DMA_TO_DEVICE);
+			phytium_memory_pool_free(priv, phytium_gem_obj->vaddr, size);
+			priv->mem_state[PHYTIUM_MEM_SYSTEM_CARVEOUT_ALLOC] -= size;
+		} else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_UNIFIED) {
+			dma_free_attrs(dev->dev, size, phytium_gem_obj->vaddr,
+				       phytium_gem_obj->iova, 0);
+			priv->mem_state[PHYTIUM_MEM_SYSTEM_UNIFIED_ALLOC] -= size;
+		}
+		list_del(&phytium_gem_obj->list);
+	} else if (obj->import_attach)
+		drm_prime_gem_destroy(obj, phytium_gem_obj->sgt);
+	drm_gem_object_release(obj);
+	kfree(phytium_gem_obj);
+}
+
+int phytium_gem_mmap_obj(struct drm_gem_object *obj, struct vm_area_struct *vma)
+{
+	int ret = 0;
+	struct phytium_gem_object *phytium_gem_obj = to_phytium_gem_obj(obj);
+	unsigned long pfn = PHYS_PFN(phytium_gem_obj->phys_addr);
+	/*
+	 * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
+	 * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
+	 * the whole buffer.
+	 */
+	vma->vm_flags &= ~VM_PFNMAP;
+	vma->vm_pgoff = 0;
+	vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
+
+	if (phytium_gem_obj->memory_type == MEMORY_TYPE_VRAM) {
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+		ret = remap_pfn_range(vma, vma->vm_start, pfn,
+			       vma->vm_end - vma->vm_start, vma->vm_page_prot);
+	} else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT) {
+		ret = remap_pfn_range(vma, vma->vm_start, pfn,
+				      vma->vm_end - vma->vm_start, vma->vm_page_prot);
+	} else if (phytium_gem_obj->memory_type == MEMORY_TYPE_SYSTEM_UNIFIED) {
+		ret = dma_mmap_attrs(obj->dev->dev, vma, phytium_gem_obj->vaddr,
+				     phytium_gem_obj->iova, vma->vm_end - vma->vm_start, 0);
+	}
+	if (ret)
+		drm_gem_vm_close(vma);
+
+	return ret;
+}
+
+int phytium_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	int ret = 0;
+
+	ret = drm_gem_mmap(filp, vma);
+	if (ret < 0)
+		return ret;
+
+	return phytium_gem_mmap_obj(vma->vm_private_data, vma);
+}
+
+int phytium_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev, uint32_t handle)
+{
+	return drm_gem_dumb_destroy(file, dev, handle);
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+static const struct vm_operations_struct phytium_vm_ops = {
+	.open   = drm_gem_vm_open,
+	.close  = drm_gem_vm_close,
+};
+
+static const struct drm_gem_object_funcs phytium_drm_gem_object_funcs = {
+	.free = phytium_gem_free_object,
+	.get_sg_table = phytium_gem_prime_get_sg_table,
+	.vmap = phytium_gem_prime_vmap,
+	.vunmap = phytium_gem_prime_vunmap,
+	.vm_ops = &phytium_vm_ops,
+};
+#endif
+
+struct phytium_gem_object *phytium_gem_create_object(struct drm_device *dev, unsigned long size)
+{
+	struct phytium_gem_object *phytium_gem_obj = NULL;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct page *page = NULL;
+	int ret = 0;
+
+	phytium_gem_obj = kzalloc(sizeof(*phytium_gem_obj), GFP_KERNEL);
+	if (!phytium_gem_obj) {
+		DRM_ERROR("failed to allocate phytium_gem_obj\n");
+		ret = -ENOMEM;
+		goto error;
+	}
+
+	ret = drm_gem_object_init(dev, &phytium_gem_obj->base, size);
+	if (ret) {
+		DRM_ERROR("failed to initialize drm gem object: %d\n", ret);
+		goto failed_object_init;
+	}
+
+	if (priv->support_memory_type & MEMORY_TYPE_VRAM) {
+		ret = phytium_memory_pool_alloc(priv, &phytium_gem_obj->vaddr,
+						&phytium_gem_obj->phys_addr, size);
+		if (ret) {
+			DRM_ERROR("fail to allocate vram buffer with size %lx\n", size);
+			goto failed_dma_alloc;
+		}
+		phytium_gem_obj->iova = phytium_gem_obj->phys_addr;
+		phytium_gem_obj->memory_type = MEMORY_TYPE_VRAM;
+		priv->mem_state[PHYTIUM_MEM_VRAM_ALLOC] += size;
+	} else if (priv->support_memory_type & MEMORY_TYPE_SYSTEM_CARVEOUT) {
+		ret = phytium_memory_pool_alloc(priv, &phytium_gem_obj->vaddr,
+						&phytium_gem_obj->phys_addr, size);
+		if (ret) {
+			DRM_ERROR("fail to allocate carveout memory with size %lx\n", size);
+			goto failed_dma_alloc;
+		}
+		page = phys_to_page(phytium_gem_obj->phys_addr);
+		phytium_gem_obj->iova = dma_map_page(dev->dev, page, 0, size, DMA_TO_DEVICE);
+		if (dma_mapping_error(dev->dev, phytium_gem_obj->iova)) {
+			DRM_ERROR("fail to dma map carveout memory with size %lx\n", size);
+			phytium_memory_pool_free(priv, phytium_gem_obj->vaddr, size);
+			ret = -ENOMEM;
+			goto failed_dma_alloc;
+		}
+		phytium_gem_obj->memory_type = MEMORY_TYPE_SYSTEM_CARVEOUT;
+		priv->mem_state[PHYTIUM_MEM_SYSTEM_CARVEOUT_ALLOC] += size;
+	} else if (priv->support_memory_type & MEMORY_TYPE_SYSTEM_UNIFIED) {
+		phytium_gem_obj->vaddr = dma_alloc_attrs(dev->dev, size, &phytium_gem_obj->iova,
+					 GFP_KERNEL, 0);
+		if (!phytium_gem_obj->vaddr) {
+			DRM_ERROR("fail to allocate unified buffer with size %lx\n", size);
+			ret = -ENOMEM;
+			goto failed_dma_alloc;
+		}
+		phytium_gem_obj->memory_type = MEMORY_TYPE_SYSTEM_UNIFIED;
+		priv->mem_state[PHYTIUM_MEM_SYSTEM_UNIFIED_ALLOC] += size;
+	} else {
+		DRM_ERROR("fail to allocate buffer with size %lx\n", size);
+		ret = -ENOMEM;
+		goto failed_dma_alloc;
+	}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+	phytium_gem_obj->base.funcs = &phytium_drm_gem_object_funcs;
+#endif
+
+	phytium_gem_obj->size = size;
+	list_add_tail(&phytium_gem_obj->list, &priv->gem_list_head);
+	DRM_DEBUG_KMS("phytium_gem_obj iova:0x%pa size:0x%lx\n",
+		       &phytium_gem_obj->iova, phytium_gem_obj->size);
+	return phytium_gem_obj;
+
+failed_dma_alloc:
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+	drm_gem_object_put(&phytium_gem_obj->base);
+#else
+	drm_gem_object_unreference_unlocked(&phytium_gem_obj->base);
+#endif
+
+	return ERR_PTR(ret);
+failed_object_init:
+	kfree(phytium_gem_obj);
+error:
+	return ERR_PTR(ret);
+}
+
+int phytium_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
+				     struct drm_mode_create_dumb *args)
+{
+	int size = 0;
+	struct phytium_gem_object *phytium_gem_obj = NULL;
+	int ret = 0;
+
+	args->pitch = ALIGN(args->width*DIV_ROUND_UP(args->bpp, 8), 128);
+	args->size = args->pitch * args->height;
+	size = PAGE_ALIGN(args->size);
+	phytium_gem_obj = phytium_gem_create_object(dev, size);
+	if (IS_ERR(phytium_gem_obj))
+		return PTR_ERR(phytium_gem_obj);
+	ret = drm_gem_handle_create(file, &phytium_gem_obj->base, &args->handle);
+	if (ret) {
+		DRM_ERROR("failed to drm_gem_handle_create\n");
+		goto failed_gem_handle;
+	}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
+	drm_gem_object_put(&phytium_gem_obj->base);
+#else
+	drm_gem_object_unreference_unlocked(&phytium_gem_obj->base);
+#endif
+
+	return 0;
+failed_gem_handle:
+	phytium_gem_free_object(&phytium_gem_obj->base);
+	return ret;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_gem.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_gem.h
new file mode 100644
index 00000000000000..cd34f4a4539f97
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_gem.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_GEM_H__
+#define __PHYTIUM_GEM_H__
+
+#include <drm/drm_gem.h>
+
+struct phytium_gem_object {
+	struct drm_gem_object base;
+	phys_addr_t phys_addr;
+	dma_addr_t iova;
+	void *vaddr;
+	unsigned long size;
+	struct sg_table *sgt;
+	char memory_type;
+	char reserve[3];
+	struct list_head list;
+	void *vaddr_save;
+};
+
+#define	to_phytium_gem_obj(obj)		container_of(obj, struct phytium_gem_object, base)
+
+int phytium_memory_pool_init(struct device *dev, struct phytium_display_private *priv);
+void phytium_memory_pool_fini(struct device *dev, struct phytium_display_private *priv);
+int phytium_gem_mmap_obj(struct drm_gem_object *obj, struct vm_area_struct *vma);
+int phytium_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+void phytium_gem_free_object(struct drm_gem_object *obj);
+struct sg_table *phytium_gem_prime_get_sg_table(struct drm_gem_object *obj);
+struct drm_gem_object *phytium_gem_prime_import_sg_table(struct drm_device *dev,
+					struct dma_buf_attachment *attach, struct sg_table *sgt);
+void phytium_gem_free_object(struct drm_gem_object *obj);
+int phytium_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev, unsigned int handle);
+struct phytium_gem_object *phytium_gem_create_object(struct drm_device *dev, unsigned long size);
+int phytium_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
+				     struct drm_mode_create_dumb *args);
+void *phytium_gem_prime_vmap(struct drm_gem_object *obj);
+void phytium_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
+int phytium_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
+int phytium_gem_suspend(struct drm_device *drm_dev);
+void phytium_gem_resume(struct drm_device *drm_dev);
+#endif /* __PHYTIUM_GEM_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_panel.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_panel.c
new file mode 100644
index 00000000000000..16783b24a4d374
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_panel.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_modes.h>
+#include "phytium_display_drv.h"
+#include "phytium_dp.h"
+#include "phytium_panel.h"
+
+static int
+phytium_dp_aux_set_backlight(struct phytium_panel *panel, unsigned int level)
+{
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+	unsigned char vals[2] = { 0x0 };
+
+	vals[0] = level;
+	if (phytium_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+		vals[0] = (level & 0xFF00) >> 8;
+		vals[1] = (level & 0xFF);
+	}
+
+	if (drm_dp_dpcd_write(&phytium_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			       vals, sizeof(vals)) < 0) {
+		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static unsigned int phytium_dp_aux_get_backlight(struct phytium_panel *panel)
+{
+	unsigned char read_val[2] = { 0x0 };
+	unsigned char level = 0;
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	if (drm_dp_dpcd_read(&phytium_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			     &read_val, sizeof(read_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+			       DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+		return 0;
+	}
+
+	level = read_val[0];
+	if (phytium_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		level = (read_val[0] << 8 | read_val[1]);
+
+	return level;
+}
+
+static void set_aux_backlight_enable(struct phytium_panel *panel, bool enable)
+{
+	u8 reg_val = 0;
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	if (!(phytium_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
+		return;
+
+	if (drm_dp_dpcd_readb(&phytium_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			      &reg_val) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				     DP_EDP_DISPLAY_CONTROL_REGISTER);
+		return;
+	}
+
+	if (enable)
+		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+	else
+		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+	if (drm_dp_dpcd_writeb(&phytium_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			       reg_val) != 1) {
+		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
+			       enable ? "enable" : "disable");
+	}
+}
+
+static void phytium_dp_aux_enable_backlight(struct phytium_panel *panel)
+{
+	unsigned char dpcd_buf, new_dpcd_buf, edp_backlight_mode;
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	if (drm_dp_dpcd_readb(&phytium_dp->aux,
+			      DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+			       DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+		return;
+	}
+
+	new_dpcd_buf = dpcd_buf;
+	edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
+
+	switch (edp_backlight_mode) {
+	case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
+	case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
+	case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
+		new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
+		new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+		break;
+
+	/* Do nothing when it is already DPCD mode */
+	case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD:
+	default:
+		break;
+	}
+
+	if (new_dpcd_buf != dpcd_buf) {
+		if (drm_dp_dpcd_writeb(&phytium_dp->aux,
+			DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
+			DRM_DEBUG_KMS("Failed to write aux backlight mode\n");
+		}
+	}
+
+	set_aux_backlight_enable(panel, true);
+	phytium_dp_aux_set_backlight(panel, panel->level);
+}
+
+static void phytium_dp_aux_disable_backlight(struct phytium_panel *panel)
+{
+	set_aux_backlight_enable(panel, false);
+}
+
+static void phytium_dp_aux_setup_backlight(struct phytium_panel *panel)
+{
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	if (phytium_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		phytium_dp->panel.max = 0xFFFF;
+	else
+		phytium_dp->panel.max = 0xFF;
+
+	phytium_dp->panel.min = 0;
+	phytium_dp->panel.level = phytium_dp_aux_get_backlight(panel);
+	phytium_dp->panel.backlight_enabled = (phytium_dp->panel.level != 0);
+}
+
+static void phytium_dp_hw_poweron_panel(struct phytium_panel *panel)
+{
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	phytium_dp->funcs->dp_hw_poweron_panel(phytium_dp);
+}
+
+static void phytium_dp_hw_poweroff_panel(struct phytium_panel *panel)
+{
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	phytium_dp->funcs->dp_hw_poweroff_panel(phytium_dp);
+}
+
+static int
+phytium_dp_hw_set_backlight(struct phytium_panel *panel, uint32_t level)
+{
+	int ret;
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	ret = phytium_dp->funcs->dp_hw_set_backlight(phytium_dp, level);
+
+	return ret;
+}
+
+static uint32_t phytium_dp_hw_get_backlight(struct phytium_panel *panel)
+{
+	uint32_t ret;
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	ret = phytium_dp->funcs->dp_hw_get_backlight(phytium_dp);
+
+	return ret;
+}
+
+static void phytium_dp_hw_enable_backlight(struct phytium_panel *panel)
+{
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	phytium_dp->funcs->dp_hw_set_backlight(phytium_dp, phytium_dp->panel.level);
+	phytium_dp->funcs->dp_hw_enable_backlight(phytium_dp);
+}
+
+static void phytium_dp_hw_disable_backlight(struct phytium_panel *panel)
+{
+	struct phytium_dp_device *phytium_dp = panel_to_dp_device(panel);
+
+	phytium_dp->funcs->dp_hw_disable_backlight(phytium_dp);
+}
+
+static void phytium_dp_hw_setup_backlight(struct phytium_panel *panel)
+{
+	struct drm_device *dev = panel->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+
+	panel->max = priv->info.backlight_max;
+	panel->min = 0;
+	panel->level = phytium_dp_hw_get_backlight(panel);
+}
+
+void phytium_dp_panel_init_backlight_funcs(struct phytium_dp_device *phytium_dp)
+{
+	if (phytium_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
+	   (phytium_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
+	   !(phytium_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
+		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
+		phytium_dp->panel.setup_backlight = phytium_dp_aux_setup_backlight;
+		phytium_dp->panel.enable_backlight = phytium_dp_aux_enable_backlight;
+		phytium_dp->panel.disable_backlight = phytium_dp_aux_disable_backlight;
+		phytium_dp->panel.set_backlight = phytium_dp_aux_set_backlight;
+		phytium_dp->panel.get_backlight = phytium_dp_aux_get_backlight;
+	} else {
+		DRM_DEBUG_KMS("SE Backlight Control Supported!\n");
+		phytium_dp->panel.setup_backlight = phytium_dp_hw_setup_backlight;
+		phytium_dp->panel.enable_backlight = phytium_dp_hw_enable_backlight;
+		phytium_dp->panel.disable_backlight = phytium_dp_hw_disable_backlight;
+		phytium_dp->panel.set_backlight = phytium_dp_hw_set_backlight;
+		phytium_dp->panel.get_backlight = phytium_dp_hw_get_backlight;
+	}
+	phytium_dp->panel.poweron = phytium_dp_hw_poweron_panel;
+	phytium_dp->panel.poweroff = phytium_dp_hw_poweroff_panel;
+	mutex_init(&phytium_dp->panel.panel_lock);
+	phytium_dp->panel.dev = phytium_dp->dev;
+
+	/* Upper limits from eDP 1.3 spec */
+	phytium_dp->panel.panel_power_up_delay = 210; /* t1_t3 */
+	phytium_dp->panel.backlight_on_delay = 50; /* t7 */
+	phytium_dp->panel.backlight_off_delay = 50;
+	phytium_dp->panel.panel_power_down_delay = 0; /* t10 */
+	phytium_dp->panel.panel_power_cycle_delay = 510; /* t11 + t12 */
+}
+
+void phytium_dp_panel_release_backlight_funcs(struct phytium_dp_device *phytium_dp)
+{
+	phytium_dp->panel.setup_backlight = NULL;
+	phytium_dp->panel.enable_backlight = NULL;
+	phytium_dp->panel.disable_backlight = NULL;
+	phytium_dp->panel.set_backlight = NULL;
+	phytium_dp->panel.get_backlight = NULL;
+	phytium_dp->panel.poweron = NULL;
+	phytium_dp->panel.poweroff = NULL;
+}
+
+void phytium_panel_enable_backlight(struct phytium_panel *panel)
+{
+
+	if (panel->enable_backlight) {
+		mutex_lock(&panel->panel_lock);
+		msleep(panel->backlight_on_delay);
+		panel->enable_backlight(panel);
+		panel->backlight_enabled = true;
+		mutex_unlock(&panel->panel_lock);
+	}
+}
+
+void phytium_panel_disable_backlight(struct phytium_panel *panel)
+{
+	if (panel->disable_backlight) {
+		mutex_lock(&panel->panel_lock);
+		panel->disable_backlight(panel);
+		panel->backlight_enabled = false;
+		msleep(panel->backlight_off_delay);
+		mutex_unlock(&panel->panel_lock);
+	}
+}
+
+void phytium_panel_poweron(struct phytium_panel *panel)
+{
+	if (panel->poweron) {
+		mutex_lock(&panel->panel_lock);
+		panel->poweron(panel);
+		panel->power_enabled = true;
+		msleep(panel->panel_power_up_delay);
+		mutex_unlock(&panel->panel_lock);
+	}
+}
+
+void phytium_panel_poweroff(struct phytium_panel *panel)
+{
+	if (panel->poweroff) {
+		mutex_lock(&panel->panel_lock);
+		msleep(panel->panel_power_down_delay);
+		panel->poweroff(panel);
+		panel->power_enabled = false;
+		mutex_unlock(&panel->panel_lock);
+	}
+}
+
+static uint32_t phytium_scale(uint32_t source_val,
+		      uint32_t source_min, uint32_t source_max,
+		      uint32_t target_min, uint32_t target_max)
+{
+	uint64_t target_val;
+
+	WARN_ON(source_min > source_max);
+	WARN_ON(target_min > target_max);
+
+	/* defensive */
+	source_val = clamp(source_val, source_min, source_max);
+
+	/* avoid overflows */
+	target_val = mul_u32_u32(source_val - source_min, target_max - target_min);
+	target_val = DIV_ROUND_CLOSEST_ULL(target_val, source_max - source_min);
+	target_val += target_min;
+
+	return target_val;
+}
+
+static inline uint32_t
+phytium_scale_hw_to_user(struct phytium_panel *panel, uint32_t hw_level, uint32_t user_max)
+{
+	return phytium_scale(hw_level, panel->min, panel->max,
+			      0, user_max);
+}
+
+static inline uint32_t
+phytium_scale_user_to_hw(struct phytium_panel *panel, u32 user_level, u32 user_max)
+{
+	return phytium_scale(user_level, 0, user_max,
+			      panel->min, panel->max);
+}
+
+static int phytium_backlight_device_update_status(struct backlight_device *bd)
+{
+	struct phytium_panel *panel = bl_get_data(bd);
+	struct drm_device *dev = panel->dev;
+	uint32_t hw_level = 0;
+	int ret = 0;
+
+	DRM_DEBUG_KMS("updating phytium_backlight, brightness=%d/%d\n",
+		       bd->props.brightness, bd->props.max_brightness);
+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+	hw_level = phytium_scale_user_to_hw(panel, bd->props.brightness, bd->props.max_brightness);
+
+	if ((panel->set_backlight) && (panel->backlight_enabled)) {
+		mutex_lock(&panel->panel_lock);
+		ret = panel->set_backlight(panel, hw_level);
+		panel->level = hw_level;
+		mutex_unlock(&panel->panel_lock);
+	}
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static int phytium_backlight_device_get_brightness(struct backlight_device *bd)
+{
+	struct phytium_panel *panel = bl_get_data(bd);
+	struct drm_device *dev = panel->dev;
+	uint32_t hw_level = 0;
+	int ret;
+
+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+	if (panel->get_backlight && panel->backlight_enabled) {
+		mutex_lock(&panel->panel_lock);
+		hw_level = panel->get_backlight(panel);
+		panel->level = hw_level;
+		mutex_unlock(&panel->panel_lock);
+	}
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	ret = phytium_scale_hw_to_user(panel, hw_level, bd->props.max_brightness);
+	DRM_DEBUG_KMS("get phytium_backlight, brightness=%d/%d\n",
+		       ret, bd->props.max_brightness);
+
+	return ret;
+}
+
+static const struct backlight_ops phytium_backlight_device_ops = {
+	.update_status = phytium_backlight_device_update_status,
+	.get_brightness = phytium_backlight_device_get_brightness,
+};
+
+int phytium_edp_backlight_device_register(struct phytium_dp_device *phytium_dp)
+{
+	struct backlight_properties props;
+	char bl_name[16];
+
+	if (phytium_dp->panel.setup_backlight) {
+		mutex_lock(&phytium_dp->panel.panel_lock);
+		phytium_dp->panel.setup_backlight(&phytium_dp->panel);
+		mutex_unlock(&phytium_dp->panel.panel_lock);
+	} else {
+		return -EINVAL;
+	}
+
+	memset(&props, 0, sizeof(props));
+	props.max_brightness = PHYTIUM_MAX_BL_LEVEL;
+	props.type = BACKLIGHT_RAW;
+	props.brightness = phytium_scale_hw_to_user(&phytium_dp->panel, phytium_dp->panel.level,
+						    props.max_brightness);
+	snprintf(bl_name, sizeof(bl_name), "phytium_bl%d", phytium_dp->port);
+
+	phytium_dp->panel.bl_device =
+		backlight_device_register(bl_name,
+					  phytium_dp->connector.kdev,
+					  &phytium_dp->panel,
+					  &phytium_backlight_device_ops,
+					  &props);
+
+	if (IS_ERR(phytium_dp->panel.bl_device)) {
+		DRM_ERROR("Failed to register backlight: %ld\n",
+			    PTR_ERR(phytium_dp->panel.bl_device));
+		phytium_dp->panel.bl_device = NULL;
+		return -ENODEV;
+	}
+
+	DRM_DEBUG_KMS("Connector %s backlight sysfs interface registered\n",
+		       phytium_dp->connector.name);
+
+	return 0;
+}
+
+void phytium_edp_backlight_device_unregister(struct phytium_dp_device *phytium_dp)
+{
+	if (phytium_dp->panel.bl_device) {
+		backlight_device_unregister(phytium_dp->panel.bl_device);
+		phytium_dp->panel.bl_device = NULL;
+	}
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_panel.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_panel.h
new file mode 100644
index 00000000000000..91760e26dcf186
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_panel.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_PANEL_H__
+#define __PHYTIUM_PANEL_H__
+#include "phytium_dp.h"
+
+#define PHYTIUM_MAX_BL_LEVEL		0xFF
+
+struct phytium_panel {
+	struct drm_device *dev;
+	bool backlight_enabled;
+	bool power_enabled;
+	bool reserve1[2];
+	unsigned int min;
+	unsigned int level;
+	unsigned int max;
+	struct backlight_device *bl_device;
+	void (*setup_backlight)(struct phytium_panel *panel);
+	uint32_t (*get_backlight)(struct phytium_panel *panel);
+	int (*set_backlight)(struct phytium_panel *panel, uint32_t level);
+	void (*disable_backlight)(struct phytium_panel *panel);
+	void (*enable_backlight)(struct phytium_panel *panel);
+	void (*poweron)(struct phytium_panel *panel);
+	void (*poweroff)(struct phytium_panel *panel);
+	struct mutex panel_lock;
+	uint32_t panel_power_up_delay;
+	uint32_t backlight_on_delay;
+	uint32_t backlight_off_delay;
+	uint32_t panel_power_down_delay;
+	uint32_t panel_power_cycle_delay;
+};
+
+void phytium_dp_panel_init_backlight_funcs(struct phytium_dp_device *phytium_dp);
+void phytium_panel_release_backlight_funcs(struct phytium_dp_device *phytium_dp);
+int phytium_edp_backlight_device_register(struct phytium_dp_device *phytium_dp);
+void phytium_edp_backlight_device_unregister(struct phytium_dp_device *phytium_dp);
+void phytium_panel_enable_backlight(struct phytium_panel *panel);
+void phytium_panel_disable_backlight(struct phytium_panel *panel);
+void phytium_panel_poweron(struct phytium_panel *panel);
+void phytium_panel_poweroff(struct phytium_panel *panel);
+
+#endif /* __PHYTIUM_PANEL_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_pci.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_pci.c
new file mode 100644
index 00000000000000..22e4fd79b2d666
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_pci.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/pci.h>
+#include <drm/drm_drv.h>
+#include <linux/dmaengine.h>
+#include "phytium_display_drv.h"
+#include "phytium_pci.h"
+#include "phytium_dp.h"
+#include "phytium_gem.h"
+#include "px210_dc.h"
+#include "px210_dp.h"
+#include "pe220x_dc.h"
+#include "pe220x_dp.h"
+
+int dc_msi_enable;
+module_param(dc_msi_enable, int, 0644);
+MODULE_PARM_DESC(dc_msi_enable, "Enable DC msi interrupt (0-disabled; 1-enabled; default-0)");
+
+void phytium_pci_vram_hw_init(struct phytium_display_private *priv)
+{
+	struct phytium_pci_private *pci_priv = to_pci_priv(priv);
+
+	pci_priv->dc_hw_vram_init(priv, priv->pool_phys_addr, priv->pool_size);
+}
+
+int phytium_pci_vram_init(struct pci_dev *pdev, struct phytium_display_private *priv)
+{
+	int ret = 0;
+
+	priv->pool_phys_addr = pci_resource_start(pdev, 2);
+	priv->pool_size = pci_resource_len(pdev, 2);
+	if ((priv->pool_phys_addr != 0) && (priv->pool_size != 0)) {
+		priv->pool_virt_addr = devm_ioremap_wc(&pdev->dev, priv->pool_phys_addr,
+						       priv->pool_size);
+		if (priv->pool_virt_addr == NULL) {
+			DRM_ERROR("pci vram ioremap fail, addr:0x%llx, size:0x%llx\n",
+				   priv->pool_phys_addr, priv->pool_size);
+			ret = -EINVAL;
+			goto failed_ioremap;
+		}
+		ret = phytium_memory_pool_init(&pdev->dev, priv);
+		if (ret)
+			goto failed_init_memory_pool;
+
+		priv->mem_state[PHYTIUM_MEM_VRAM_TOTAL] = priv->pool_size;
+		priv->support_memory_type = MEMORY_TYPE_VRAM;
+		priv->vram_hw_init = phytium_pci_vram_hw_init;
+	} else {
+		DRM_DEBUG_KMS("not support vram\n");
+		priv->pool_virt_addr = NULL;
+		priv->mem_state[PHYTIUM_MEM_VRAM_TOTAL] = 0;
+		priv->support_memory_type = MEMORY_TYPE_SYSTEM_UNIFIED;
+		priv->vram_hw_init = NULL;
+	}
+
+	return 0;
+
+failed_init_memory_pool:
+	devm_iounmap(&pdev->dev, priv->pool_virt_addr);
+failed_ioremap:
+	return ret;
+}
+
+void phytium_pci_vram_fini(struct pci_dev *pdev, struct phytium_display_private *priv)
+{
+	if (priv->support_memory_type == MEMORY_TYPE_VRAM) {
+		phytium_memory_pool_fini(&pdev->dev, priv);
+		devm_iounmap(&pdev->dev, priv->pool_virt_addr);
+	}
+}
+
+static bool phytium_pci_dma_chan_filter(struct dma_chan *chan, void *param)
+{
+	struct phytium_dma_slave *s = param;
+
+	if (s->dma_dev != chan->device->dev)
+		return false;
+
+	if (s->chan_id ==  chan->chan_id)
+		return true;
+	else
+		return false;
+}
+
+int phytium_pci_dma_init(struct phytium_display_private *priv)
+{
+	struct pci_dev *dma_dev, *gpu_dev;
+	struct drm_device *drm_dev =  priv->dev;
+	dma_cap_mask_t mask;
+	struct phytium_dma_slave s;
+	int ret = 0;
+	u16 cmd;
+
+	/* check px210 gpu enable */
+	gpu_dev = pci_get_device(PCI_VENDOR_ID_PHYTIUM, 0xdc20, NULL);
+	if (!gpu_dev) {
+		DRM_INFO("failed to get gpu_dev\n");
+		ret = -ENODEV;
+		goto failed;
+	}
+
+	pci_read_config_word(gpu_dev, PCI_COMMAND, &cmd);
+	if (!(cmd & PCI_COMMAND_MASTER)) {
+		DRM_INFO("gpu_dev master is disabled\n");
+		ret = -ENODEV;
+		goto failed;
+	}
+
+	dma_dev = pci_get_device(PCI_VENDOR_ID_PHYTIUM, 0xdc3c, NULL);
+	if (!dma_dev) {
+		DRM_INFO("failed to get dma_dev\n");
+		ret = -ENODEV;
+		goto failed;
+	}
+
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	s.dma_dev = &dma_dev->dev;
+	s.chan_id = 2;
+	priv->dma_chan = dma_request_channel(mask, phytium_pci_dma_chan_filter, &s);
+	if (!priv->dma_chan) {
+		DRM_DEV_ERROR(drm_dev->dev, "failed to request dma chan\n");
+		ret = -EBUSY;
+		goto failed;
+	}
+	priv->dma_inited = 1;
+
+failed:
+	return ret;
+}
+
+void phytium_pci_dma_fini(struct phytium_display_private *priv)
+{
+	if (priv->dma_inited)
+		dma_release_channel(priv->dma_chan);
+	priv->dma_inited = 0;
+	priv->dma_chan =  NULL;
+}
+
+static struct phytium_display_private*
+phytium_pci_private_init(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+	struct drm_device *dev = pci_get_drvdata(pdev);
+	struct phytium_display_private *priv = NULL;
+	struct phytium_pci_private *pci_priv = NULL;
+	struct phytium_device_info *phytium_info = (struct phytium_device_info *)ent->driver_data;
+	int i = 0;
+	resource_size_t io_addr, io_size;
+
+	pci_priv = devm_kzalloc(&pdev->dev, sizeof(*pci_priv), GFP_KERNEL);
+	if (!pci_priv) {
+		DRM_ERROR("no memory to allocate for drm_display_private\n");
+		goto failed_malloc_priv;
+	}
+
+	memset(pci_priv, 0, sizeof(*pci_priv));
+	priv = &pci_priv->base;
+	phytium_display_private_init(priv, dev);
+
+	memcpy(&(priv->info), phytium_info, sizeof(struct phytium_device_info));
+	DRM_DEBUG_KMS("priv->info.num_pipes :%d\n", priv->info.num_pipes);
+	priv->info.pipe_mask = ((pdev->subsystem_device >> PIPE_MASK_SHIFT) & PIPE_MASK_MASK);
+	priv->info.edp_mask = ((pdev->subsystem_device >> EDP_MASK_SHIFT) & EDP_MASK_MASK);
+	priv->info.num_pipes = 0;
+	for_each_pipe_masked(priv, i)
+		priv->info.num_pipes++;
+	if (priv->info.num_pipes == 0) {
+		DRM_ERROR("num_pipes is zero, so exit init\n");
+		goto failed_init_numpipe;
+	}
+
+	io_addr = pci_resource_start(pdev, 0);
+	io_size = pci_resource_len(pdev, 0);
+	priv->regs = ioremap(io_addr, io_size);
+	if (priv->regs == NULL) {
+		DRM_ERROR("pci bar0 ioremap fail, addr:0x%llx, size:0x%llx\n", io_addr, io_size);
+		goto failed_ioremap;
+	}
+
+	priv->irq = pdev->irq;
+	if (IS_PX210(priv)) {
+		pci_priv->dc_hw_vram_init = px210_dc_hw_vram_init;
+		priv->dc_hw_clear_msi_irq = px210_dc_hw_clear_msi_irq;
+		priv->dc_hw_fb_format_check = px210_dc_hw_fb_format_check;
+	} else if (IS_PE220X(priv)) {
+		pci_priv->dc_hw_vram_init = pe220x_dc_hw_vram_init;
+		priv->dc_hw_clear_msi_irq = NULL;
+		priv->dc_hw_fb_format_check = pe220x_dc_hw_fb_format_check;
+	}
+
+	return priv;
+
+failed_ioremap:
+failed_init_numpipe:
+	devm_kfree(&pdev->dev, pci_priv);
+failed_malloc_priv:
+	return NULL;
+}
+
+static void
+phytium_pci_private_fini(struct pci_dev *pdev, struct phytium_display_private *priv)
+{
+	struct phytium_pci_private *pci_priv = to_pci_priv(priv);
+
+	if (priv->regs)
+		iounmap(priv->regs);
+
+	devm_kfree(&pdev->dev, pci_priv);
+}
+
+static int phytium_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+	struct phytium_display_private *priv = NULL;
+	struct drm_device *dev = NULL;
+	int ret = 0;
+
+	dev = drm_dev_alloc(&phytium_display_drm_driver, &pdev->dev);
+	if (IS_ERR(dev)) {
+		DRM_ERROR("failed to allocate drm_device\n");
+		return PTR_ERR(dev);
+	}
+	dev->pdev = pdev;
+	pci_set_drvdata(pdev, dev);
+	pci_set_master(pdev);
+	ret = pci_enable_device(pdev);
+	if (ret) {
+		DRM_ERROR("pci enbale device fail\n");
+		goto failed_enable_device;
+	}
+
+	if (dc_msi_enable) {
+		ret = pci_enable_msi(pdev);
+		if (ret)
+			DRM_ERROR("pci enbale msi fail\n");
+	}
+
+	dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
+
+	priv = phytium_pci_private_init(pdev, ent);
+	if (priv)
+		dev->dev_private = priv;
+	else
+		goto failed_pci_private_init;
+
+	ret = phytium_pci_vram_init(pdev, priv);
+	if (ret) {
+		DRM_ERROR("failed to init pci vram\n");
+		goto failed_pci_vram_init;
+	}
+
+	ret = drm_dev_register(dev, 0);
+	if (ret) {
+		DRM_ERROR("failed to register drm dev\n");
+		goto failed_register_drm;
+	}
+
+	phytium_dp_hpd_irq_setup(dev, true);
+
+	return 0;
+
+failed_register_drm:
+	phytium_pci_vram_fini(pdev, priv);
+failed_pci_vram_init:
+	phytium_pci_private_fini(pdev, priv);
+failed_pci_private_init:
+	if (pdev->msi_enabled)
+		pci_disable_msi(pdev);
+	pci_disable_device(pdev);
+failed_enable_device:
+	pci_set_drvdata(pdev, NULL);
+	drm_dev_put(dev);
+
+	return -1;
+}
+
+static void phytium_pci_remove(struct pci_dev *pdev)
+{
+	struct drm_device *dev = pci_get_drvdata(pdev);
+	struct phytium_display_private *priv = dev->dev_private;
+
+	phytium_dp_hpd_irq_setup(dev, false);
+	cancel_work_sync(&priv->hotplug_work);
+	drm_dev_unregister(dev);
+	phytium_pci_vram_fini(pdev, priv);
+	phytium_pci_private_fini(pdev, priv);
+	if (pdev->msi_enabled)
+		pci_disable_msi(pdev);
+	pci_disable_device(pdev);
+	pci_set_drvdata(pdev, NULL);
+	drm_dev_put(dev);
+}
+
+static void phytium_pci_shutdown(struct pci_dev *pdev)
+{
+	struct drm_device *dev = pci_get_drvdata(pdev);
+	struct phytium_display_private *priv = dev->dev_private;
+
+	priv->display_shutdown(dev);
+}
+
+static int phytium_pci_pm_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+	struct phytium_display_private *priv = drm_dev->dev_private;
+	int ret = 0;
+
+	if (IS_PX210(priv))
+		phytium_pci_dma_init(priv);
+
+	ret = priv->display_pm_suspend(drm_dev);
+	if (ret < 0)
+		goto out;
+
+	pci_save_state(pdev);
+	pci_disable_device(pdev);
+	pci_set_power_state(pdev, PCI_D3hot);
+	udelay(200);
+
+out:
+	return ret;
+}
+
+static int phytium_pci_pm_resume(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+	struct phytium_display_private *priv = drm_dev->dev_private;
+	int ret = 0;
+
+	pci_set_power_state(pdev, PCI_D0);
+	pci_restore_state(pdev);
+	ret = pci_enable_device(pdev);
+	if (ret)
+		return ret;
+	pci_set_master(pdev);
+
+	ret = priv->display_pm_resume(drm_dev);
+	if (IS_PX210(priv))
+		phytium_pci_dma_fini(priv);
+
+	return ret;
+}
+
+static const struct dev_pm_ops phytium_pci_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_pci_pm_suspend, phytium_pci_pm_resume)
+};
+
+static const struct phytium_device_info px210_info = {
+	.platform_mask = BIT(PHYTIUM_PLATFORM_PX210),
+	.total_pipes = 3,
+	.crtc_clock_max = PX210_DC_PIX_CLOCK_MAX,
+	.hdisplay_max = PX210_DC_HDISPLAY_MAX,
+	.vdisplay_max = PX210_DC_VDISPLAY_MAX,
+	.address_mask = PX210_DC_ADDRESS_MASK,
+	.backlight_max = PX210_DP_BACKLIGHT_MAX,
+};
+
+static const struct phytium_device_info pe220x_info = {
+	.platform_mask = BIT(PHYTIUM_PLATFORM_PE220X),
+	.total_pipes = 2,
+	.crtc_clock_max = PE220X_DC_PIX_CLOCK_MAX,
+	.hdisplay_max = PE220X_DC_HDISPLAY_MAX,
+	.vdisplay_max = PE220X_DC_VDISPLAY_MAX,
+	.address_mask = PE220X_DC_ADDRESS_MASK,
+	.backlight_max = PE220X_DP_BACKLIGHT_MAX,
+};
+
+static const struct pci_device_id phytium_display_pci_ids[] = {
+	{ PCI_VDEVICE(PHYTIUM, 0xdc22), (kernel_ulong_t)&px210_info },
+	{ PCI_VDEVICE(PHYTIUM, 0xdc3e), (kernel_ulong_t)&pe220x_info },
+	{ /* End: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, phytium_display_pci_ids);
+
+struct pci_driver phytium_pci_driver = {
+	.name = "phytium_display_pci",
+	.id_table = phytium_display_pci_ids,
+	.probe = phytium_pci_probe,
+	.remove = phytium_pci_remove,
+	.shutdown = phytium_pci_shutdown,
+	.driver.pm = &phytium_pci_pm_ops,
+};
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_pci.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_pci.h
new file mode 100644
index 00000000000000..ad116dfcb5e979
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_pci.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_PCI_H__
+#define __PHYTIUM_PCI_H__
+
+#include "phytium_display_drv.h"
+
+struct phytium_pci_private {
+	struct phytium_display_private base;
+	void (*dc_hw_vram_init)(struct phytium_display_private *priv, resource_size_t vram_addr,
+				resource_size_t vram_size);
+};
+
+struct phytium_dma_slave {
+	struct device *dma_dev;
+	u32 chan_id;
+};
+
+#define	to_pci_priv(priv)		container_of(priv, struct phytium_pci_private, base)
+
+extern struct pci_driver phytium_pci_driver;
+#endif /* __PHYTIUM_PCI_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_plane.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_plane.c
new file mode 100644
index 00000000000000..950db0487bc700
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_plane.c
@@ -0,0 +1,683 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_fourcc.h>
+
+#include <linux/dma-buf.h>
+
+#include "phytium_display_drv.h"
+#include "phytium_plane.h"
+#include "phytium_fb.h"
+#include "phytium_gem.h"
+#include "phytium_crtc.h"
+#include "px210_dc.h"
+#include "pe220x_dc.h"
+#include "phytium_reg.h"
+
+#define PHYTIUM_CURS_W_SIZE 32
+#define PHYTIUM_CURS_H_SIZE 32
+
+void phytium_plane_destroy(struct drm_plane *plane)
+{
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+
+	drm_plane_cleanup(plane);
+	kfree(phytium_plane);
+}
+
+/**
+ * phytium_plane_atomic_get_property - fetch plane property value
+ * @plane: plane to fetch property for
+ * @state: state containing the property value
+ * @property: property to look up
+ * @val: pointer to write property value into
+ *
+ * The DRM core does not store shadow copies of properties for
+ * atomic-capable drivers.  This entrypoint is used to fetch
+ * the current value of a driver-specific plane property.
+ */
+static int
+phytium_plane_atomic_get_property(struct drm_plane *plane,
+					const struct drm_plane_state *state,
+					struct drm_property *property,
+					uint64_t *val)
+{
+	DRM_DEBUG_KMS("Unknown plane property [PROP:%d:%s]\n", property->base.id, property->name);
+	return -EINVAL;
+}
+
+/**
+ * phytium_plane_atomic_set_property - set plane property value
+ * @plane: plane to set property for
+ * @state: state to update property value in
+ * @property: property to set
+ * @val: value to set property to
+ *
+ * Writes the specified property value for a plane into the provided atomic
+ * state object.
+ *
+ * Returns 0 on success, -EINVAL on unrecognized properties
+ */
+int
+phytium_plane_atomic_set_property(struct drm_plane *plane,
+					struct drm_plane_state *state,
+					struct drm_property *property,
+					uint64_t val)
+{
+	DRM_DEBUG_KMS("Unknown plane property [PROP:%d:%s]\n", property->base.id, property->name);
+	return -EINVAL;
+}
+
+struct drm_plane_state *
+phytium_plane_atomic_duplicate_state(struct drm_plane *plane)
+{
+	struct drm_plane_state *state = NULL;
+	struct phytium_plane_state *phytium_state = NULL;
+
+	phytium_state = kmemdup(plane->state, sizeof(*phytium_state), GFP_KERNEL);
+
+	if (!phytium_state)
+		return NULL;
+
+	state = &phytium_state->base;
+	if (state->fb)
+		drm_framebuffer_get(state->fb);
+
+	state->fence = NULL;
+	state->commit = NULL;
+
+	return state;
+}
+
+void
+phytium_plane_atomic_destroy_state(struct drm_plane *plane, struct drm_plane_state *state)
+{
+	struct phytium_plane_state *phytium_state = to_phytium_plane_state(state);
+
+	__drm_atomic_helper_plane_destroy_state(state);
+	kfree(phytium_state);
+}
+
+static bool phytium_plane_format_mod_supported(struct drm_plane *plane,
+						uint32_t format, uint64_t modifier)
+{
+	if (modifier == DRM_FORMAT_MOD_LINEAR)
+		return true;
+
+	if (modifier == DRM_FORMAT_MOD_PHYTIUM_TILE_MODE3_FBCDC) {
+		switch (format) {
+		case DRM_FORMAT_ARGB2101010:
+		case DRM_FORMAT_ABGR2101010:
+		case DRM_FORMAT_RGBA1010102:
+		case DRM_FORMAT_BGRA1010102:
+		case DRM_FORMAT_ARGB8888:
+		case DRM_FORMAT_ABGR8888:
+		case DRM_FORMAT_RGBA8888:
+		case DRM_FORMAT_BGRA8888:
+		case DRM_FORMAT_XRGB8888:
+		case DRM_FORMAT_XBGR8888:
+		case DRM_FORMAT_RGBX8888:
+		case DRM_FORMAT_BGRX8888:
+			return true;
+		default:
+			return false;
+		}
+	}
+
+	return false;
+}
+
+const struct drm_plane_funcs phytium_plane_funcs = {
+	.update_plane		= drm_atomic_helper_update_plane,
+	.disable_plane		= drm_atomic_helper_disable_plane,
+	.destroy		= phytium_plane_destroy,
+	.reset			= drm_atomic_helper_plane_reset,
+	.atomic_get_property	= phytium_plane_atomic_get_property,
+	.atomic_set_property	= phytium_plane_atomic_set_property,
+	.atomic_duplicate_state	= phytium_plane_atomic_duplicate_state,
+	.atomic_destroy_state	= phytium_plane_atomic_destroy_state,
+	.format_mod_supported	= phytium_plane_format_mod_supported,
+};
+
+static int phytium_plane_prepare_fb(struct drm_plane *plane,
+					       struct drm_plane_state *state)
+{
+	struct dma_buf *dma_buf;
+	struct dma_fence *fence;
+
+	if (!state->fb)
+		return 0;
+	dma_buf = to_phytium_framebuffer(state->fb)->phytium_gem_obj[0]->base.dma_buf;
+	if (dma_buf) {
+		fence = dma_resv_get_excl_rcu(dma_buf->resv);
+		drm_atomic_set_fence_for_plane(state, fence);
+	}
+
+	return 0;
+}
+
+static int
+phytium_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct drm_framebuffer *fb = state->fb;
+	struct drm_crtc *crtc = state->crtc;
+	struct drm_crtc_state *crtc_state;
+	int src_x, src_y, src_w, src_h;
+	unsigned long base_offset;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+
+	if ((!fb) || (!crtc))
+		return 0;
+
+	crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+		src_w = state->src_w >> 16;
+		src_h = state->src_h >> 16;
+		if (phytium_crtc->scale_enable)
+			return -EINVAL;
+		if ((src_w != PHYTIUM_CURS_W_SIZE) || (src_h != PHYTIUM_CURS_W_SIZE)) {
+			DRM_INFO("Invalid cursor size(%d, %d)\n", src_w, src_h);
+			return -EINVAL;
+		}
+	} else if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
+		src_x = state->src_x >> 16;
+		src_y = state->src_y >> 16;
+		src_w = state->src_w >> 16;
+		src_h = state->src_h >> 16;
+
+		base_offset = src_x * fb->format->cpp[0] + src_y*fb->pitches[0];
+		if (base_offset & (priv->info.address_mask)) {
+			DRM_ERROR("fb base address is not aligned by 0x%lx byte\n",
+				   priv->info.address_mask);
+			return -EINVAL;
+		}
+
+		if (src_w != state->crtc_w || src_h != state->crtc_h) {
+			DRM_ERROR("scale not support: crtc_w(0x%x)/h(0x%x) src_w(0x%x)/h(0x%x)\n",
+				   state->crtc_w, state->crtc_h, src_w, src_h);
+			return -EINVAL;
+		}
+
+		if ((state->crtc_x < 0) || (state->crtc_y < 0)) {
+			DRM_ERROR("crtc_x(0x%x)/y(0x%x) of drm plane state is invalid\n",
+				   state->crtc_x, state->crtc_y);
+			return -EINVAL;
+		}
+
+		if ((state->crtc_x + state->crtc_w > crtc_state->adjusted_mode.hdisplay)
+			|| (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay)) {
+			DRM_ERROR("plane out of crtc region\n");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static void phytium_dc_get_plane_parameter(struct drm_plane *plane)
+{
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	struct drm_framebuffer *fb = plane->state->fb;
+	struct phytium_framebuffer *phytium_fb = to_phytium_framebuffer(fb);
+	struct phytium_gem_object *phytium_gem_obj = NULL;
+	int i, num_planes = 0;
+	const struct drm_format_info *info;
+
+	info = drm_format_info(fb->format->format);
+	num_planes = info ? info->num_planes : 1;
+
+	for (i = 0; i < num_planes; i++) {
+		phytium_gem_obj = phytium_fb->phytium_gem_obj[i];
+		phytium_plane->iova[i] =  phytium_gem_obj->iova + fb->offsets[i];
+		phytium_plane->size[i] = phytium_gem_obj->size - fb->offsets[i];
+
+		if (fb->modifier == DRM_FORMAT_MOD_PHYTIUM_TILE_MODE0_FBCDC)
+			phytium_plane->tiling[i] = FRAMEBUFFER_TILE_MODE0;
+		else if (fb->modifier == DRM_FORMAT_MOD_PHYTIUM_TILE_MODE3_FBCDC)
+			phytium_plane->tiling[i] = FRAMEBUFFER_TILE_MODE3;
+		else if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+			phytium_plane->tiling[i] = FRAMEBUFFER_LINEAR;
+		else
+			phytium_plane->tiling[i] = FRAMEBUFFER_LINEAR;
+
+		if (i == 0) {
+			switch (fb->format->format) {
+			case DRM_FORMAT_ARGB2101010:
+			case DRM_FORMAT_ABGR2101010:
+			case DRM_FORMAT_RGBA1010102:
+			case DRM_FORMAT_BGRA1010102:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_ARGB2101010;
+				break;
+
+			case DRM_FORMAT_ARGB8888:
+			case DRM_FORMAT_ABGR8888:
+			case DRM_FORMAT_RGBA8888:
+			case DRM_FORMAT_BGRA8888:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_ARGB8888;
+				break;
+
+			case DRM_FORMAT_XRGB8888:
+			case DRM_FORMAT_XBGR8888:
+			case DRM_FORMAT_RGBX8888:
+			case DRM_FORMAT_BGRX8888:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_XRGB8888;
+				break;
+
+			case DRM_FORMAT_ARGB4444:
+			case DRM_FORMAT_ABGR4444:
+			case DRM_FORMAT_RGBA4444:
+			case DRM_FORMAT_BGRA4444:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_ARGB4444;
+				break;
+
+			case DRM_FORMAT_XRGB4444:
+			case DRM_FORMAT_XBGR4444:
+			case DRM_FORMAT_RGBX4444:
+			case DRM_FORMAT_BGRX4444:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_XRGB4444;
+				break;
+
+			case DRM_FORMAT_ARGB1555:
+			case DRM_FORMAT_ABGR1555:
+			case DRM_FORMAT_RGBA5551:
+			case DRM_FORMAT_BGRA5551:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_ARGB1555;
+				break;
+
+			case DRM_FORMAT_XRGB1555:
+			case DRM_FORMAT_XBGR1555:
+			case DRM_FORMAT_RGBX5551:
+			case DRM_FORMAT_BGRX5551:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_XRGB1555;
+				break;
+
+			case DRM_FORMAT_RGB565:
+			case DRM_FORMAT_BGR565:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_RGB565;
+				break;
+
+			case DRM_FORMAT_YUYV:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_YUYV;
+				break;
+
+			case DRM_FORMAT_UYVY:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_UYVY;
+				break;
+			case DRM_FORMAT_NV16:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_NV16;
+				break;
+			case DRM_FORMAT_NV12:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_NV12;
+				break;
+			case DRM_FORMAT_NV21:
+				phytium_plane->format = FRAMEBUFFER_FORMAT_NV12;
+				break;
+			default:
+				DRM_ERROR("unsupported pixel format (format = %d)\n",
+					  fb->format->format);
+				return;
+			}
+
+			switch (fb->format->format) {
+			case DRM_FORMAT_ARGB2101010:
+			case DRM_FORMAT_ARGB8888:
+			case DRM_FORMAT_XRGB8888:
+			case DRM_FORMAT_ARGB4444:
+			case DRM_FORMAT_XRGB4444:
+			case DRM_FORMAT_ARGB1555:
+			case DRM_FORMAT_XRGB1555:
+			case DRM_FORMAT_RGB565:
+				phytium_plane->swizzle = FRAMEBUFFER_SWIZZLE_ARGB;
+				phytium_plane->uv_swizzle = FRAMEBUFFER_UVSWIZZLE_DISABLE;
+				break;
+
+			case DRM_FORMAT_ABGR2101010:
+			case DRM_FORMAT_ABGR8888:
+			case DRM_FORMAT_XBGR8888:
+			case DRM_FORMAT_ABGR4444:
+			case DRM_FORMAT_XBGR4444:
+			case DRM_FORMAT_ABGR1555:
+			case DRM_FORMAT_XBGR1555:
+			case DRM_FORMAT_BGR565:
+				phytium_plane->swizzle = FRAMEBUFFER_SWIZZLE_ABGR;
+				phytium_plane->uv_swizzle = FRAMEBUFFER_UVSWIZZLE_DISABLE;
+				break;
+
+			case DRM_FORMAT_RGBA1010102:
+			case DRM_FORMAT_RGBA8888:
+			case DRM_FORMAT_RGBX8888:
+			case DRM_FORMAT_RGBA4444:
+			case DRM_FORMAT_RGBX4444:
+			case DRM_FORMAT_RGBA5551:
+			case DRM_FORMAT_RGBX5551:
+				phytium_plane->swizzle = FRAMEBUFFER_SWIZZLE_RGBA;
+				phytium_plane->uv_swizzle = FRAMEBUFFER_UVSWIZZLE_DISABLE;
+				break;
+
+			case DRM_FORMAT_BGRA1010102:
+			case DRM_FORMAT_BGRA8888:
+			case DRM_FORMAT_BGRX8888:
+			case DRM_FORMAT_BGRA4444:
+			case DRM_FORMAT_BGRX4444:
+			case DRM_FORMAT_BGRA5551:
+			case DRM_FORMAT_BGRX5551:
+				phytium_plane->swizzle = FRAMEBUFFER_SWIZZLE_BGRA;
+				phytium_plane->uv_swizzle = FRAMEBUFFER_UVSWIZZLE_DISABLE;
+				break;
+
+			case DRM_FORMAT_YUYV:
+			case DRM_FORMAT_UYVY:
+			case DRM_FORMAT_NV16:
+			case DRM_FORMAT_NV12:
+				phytium_plane->swizzle = FRAMEBUFFER_SWIZZLE_ARGB;
+				phytium_plane->uv_swizzle = FRAMEBUFFER_UVSWIZZLE_DISABLE;
+				break;
+
+			default:
+				DRM_ERROR("unsupported pixel format (format = %d)\n",
+					   fb->format->format);
+				return;
+			}
+		}
+	}
+}
+
+static void phytium_dc_primary_plane_update(struct drm_plane *plane)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	struct drm_framebuffer *fb = plane->state->fb;
+	int phys_pipe = phytium_plane->phys_pipe;
+	int src_x, src_y, crtc_x, crtc_y, crtc_w, crtc_h;
+	unsigned long base_offset;
+	int config;
+
+	src_x = plane->state->src_x >> 16;
+	src_y = plane->state->src_y >> 16;
+	crtc_x = plane->state->crtc_x;
+	crtc_y = plane->state->crtc_y;
+	crtc_w = plane->state->crtc_w;
+	crtc_h = plane->state->crtc_h;
+
+	if (phytium_plane->dc_hw_update_dcreq)
+		phytium_plane->dc_hw_update_dcreq(plane);
+	phytium_plane->dc_hw_update_primary_hi_addr(plane);
+
+	/* config dc */
+	/* Y */
+	base_offset = src_x * fb->format->cpp[0] + src_y*fb->pitches[0];
+	phytium_writel_reg(priv, (phytium_plane->iova[0] + base_offset) & ADDRESS_MASK,
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_Y_ADDRESS);
+	phytium_writel_reg(priv, ALIGN(fb->pitches[0], 128),
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_Y_STRIDE);
+
+	/* U */
+	phytium_writel_reg(priv, phytium_plane->iova[1] & 0xffffffff,
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_U_ADDRESS);
+	phytium_writel_reg(priv, ALIGN(fb->pitches[1], 128),
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_U_STRIDE);
+
+	/* V */
+	phytium_writel_reg(priv, phytium_plane->iova[2] & 0xffffffff,
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_V_ADDRESS);
+	phytium_writel_reg(priv, ALIGN(fb->pitches[2], 128),
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_V_STRIDE);
+
+	/* size */
+	phytium_writel_reg(priv, (crtc_w & WIDTH_MASK) | ((crtc_h&HEIGHT_MASK) << HEIGHT_SHIFT),
+			   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_FRAMEBUFFER_SIZE);
+	/* config */
+	config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe],
+				   PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	config &= ~(FRAMEBUFFER_FORMAT_MASK << FRAMEBUFFER_FORMAT_SHIFT);
+	config |= (phytium_plane->format << FRAMEBUFFER_FORMAT_SHIFT);
+	config &= ~(1 << FRAMEBUFFER_UVSWIZZLE_SHIFT);
+	config |= (phytium_plane->uv_swizzle << FRAMEBUFFER_UVSWIZZLE_SHIFT);
+	config &= ~(FRAMEBUFFER_SWIZZLE_MASK << FRAMEBUFFER_SWIZZLE_SHIFT);
+	config |= (phytium_plane->swizzle << FRAMEBUFFER_SWIZZLE_SHIFT);
+	config &= ~(FRAMEBUFFER_TILE_MODE_MASK << FRAMEBUFFER_TILE_MODE_SHIFT);
+	config |= (phytium_plane->tiling[0] << FRAMEBUFFER_TILE_MODE_SHIFT);
+	config &= (~FRAMEBUFFER_CLEAR);
+	phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe],
+			   PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+}
+
+static void phytium_dc_cursor_plane_update(struct drm_plane *plane)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	struct drm_framebuffer *fb = plane->state->fb;
+	int phys_pipe = phytium_plane->phys_pipe;
+	int config;
+	unsigned long iova;
+
+	phytium_plane->enable = 1;
+	phytium_plane->cursor_hot_x = fb->hot_x;
+	phytium_plane->cursor_hot_y = fb->hot_y;
+	phytium_plane->cursor_x = plane->state->crtc_x + fb->hot_x;
+	phytium_plane->cursor_y = plane->state->crtc_y + fb->hot_y;
+
+	if (phytium_plane->cursor_x < 0) {
+		phytium_plane->cursor_hot_x = plane->state->crtc_w - 1;
+		phytium_plane->cursor_x = plane->state->crtc_x + phytium_plane->cursor_hot_x;
+	}
+
+	if (phytium_plane->cursor_y < 0) {
+		phytium_plane->cursor_hot_y = plane->state->crtc_h - 1;
+		phytium_plane->cursor_y = plane->state->crtc_y + phytium_plane->cursor_hot_y;
+	}
+
+	config = CURSOR_FORMAT_ARGB8888 |
+		((phytium_plane->cursor_hot_y & CURSOR_HOT_Y_MASK) << CURSOR_HOT_Y_SHIFT) |
+		((phytium_plane->cursor_hot_x & CURSOR_HOT_X_MASK) << CURSOR_HOT_X_SHIFT);
+	phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe], PHYTIUM_DC_CURSOR_CONFIG);
+
+	config = ((phytium_plane->cursor_x & CURSOR_X_MASK) << CURSOR_X_SHIFT) |
+		 ((phytium_plane->cursor_y & CURSOR_Y_MASK) << CURSOR_Y_SHIFT);
+	phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe],
+			   PHYTIUM_DC_CURSOR_LOCATION);
+	iova = phytium_plane->iova[0];
+	phytium_writel_reg(priv, iova & 0xffffffff, priv->dc_reg_base[phys_pipe],
+			   PHYTIUM_DC_CURSOR_ADDRESS);
+	if (phytium_plane->dc_hw_update_cursor_hi_addr)
+		phytium_plane->dc_hw_update_cursor_hi_addr(plane, iova);
+}
+
+static void phytium_plane_atomic_update(struct drm_plane *plane,
+						   struct drm_plane_state *old_state)
+{
+	struct drm_framebuffer *fb, *old_fb;
+
+	DRM_DEBUG_KMS("update plane: type=%d\n", plane->type);
+	if (!plane->state->crtc || !plane->state->fb)
+		return;
+
+	fb = plane->state->fb;
+	old_fb = old_state->fb;
+
+	if (fb)
+		drm_framebuffer_get(fb);
+	if (old_fb)
+		drm_framebuffer_put(old_fb);
+
+	phytium_dc_get_plane_parameter(plane);
+
+	if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+		phytium_dc_primary_plane_update(plane);
+	else if (plane->type == DRM_PLANE_TYPE_CURSOR)
+		phytium_dc_cursor_plane_update(plane);
+}
+
+static void phytium_plane_atomic_disable(struct drm_plane *plane,
+						    struct drm_plane_state *old_state)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	int phys_pipe = phytium_plane->phys_pipe;
+	int config;
+	struct drm_framebuffer *old_fb;
+
+	old_fb = old_state->fb;
+	if (old_fb)
+		drm_framebuffer_put(old_fb);
+
+	if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
+		phytium_writel_reg(priv, CLEAR_VALUE_RED, priv->dc_reg_base[phys_pipe],
+				   PHYTIUM_DC_FRAMEBUFFER_CLEARVALUE);
+		config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe],
+					   PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+		config |= FRAMEBUFFER_CLEAR;
+		phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe],
+				   PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+	} else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+		phytium_writel_reg(priv, CURSOR_FORMAT_DISABLED,
+				   priv->dc_reg_base[phys_pipe], PHYTIUM_DC_CURSOR_CONFIG);
+	}
+}
+
+const struct drm_plane_helper_funcs phytium_plane_helper_funcs = {
+	.prepare_fb =  phytium_plane_prepare_fb,
+	.atomic_check	= phytium_plane_atomic_check,
+	.atomic_update	= phytium_plane_atomic_update,
+	.atomic_disable	= phytium_plane_atomic_disable,
+};
+
+struct phytium_plane *phytium_primary_plane_create(struct drm_device *dev, int phys_pipe)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = NULL;
+	struct phytium_plane_state *phytium_plane_state = NULL;
+	int ret = 0;
+	unsigned int flags = 0;
+	const uint32_t *formats = NULL;
+	uint32_t format_count;
+	const uint64_t *format_modifiers;
+
+	phytium_plane = kzalloc(sizeof(*phytium_plane), GFP_KERNEL);
+	if (!phytium_plane) {
+		ret = -ENOMEM;
+		goto failed_malloc_plane;
+	}
+
+	phytium_plane_state = kzalloc(sizeof(*phytium_plane_state), GFP_KERNEL);
+	if (!phytium_plane_state) {
+		ret = -ENOMEM;
+		goto failed_malloc_plane_state;
+	}
+	phytium_plane_state->base.plane = &phytium_plane->base;
+	phytium_plane_state->base.rotation = DRM_MODE_ROTATE_0;
+	phytium_plane->base.state = &phytium_plane_state->base;
+	phytium_plane->phys_pipe = phys_pipe;
+
+	if (IS_PX210(priv)) {
+		phytium_plane->dc_hw_plane_get_format = px210_dc_hw_plane_get_primary_format;
+		phytium_plane->dc_hw_update_dcreq = px210_dc_hw_update_dcreq;
+		phytium_plane->dc_hw_update_primary_hi_addr = px210_dc_hw_update_primary_hi_addr;
+		phytium_plane->dc_hw_update_cursor_hi_addr = NULL;
+	}  else if (IS_PE220X(priv)) {
+		phytium_plane->dc_hw_plane_get_format = pe220x_dc_hw_plane_get_primary_format;
+		phytium_plane->dc_hw_update_dcreq = NULL;
+		phytium_plane->dc_hw_update_primary_hi_addr = pe220x_dc_hw_update_primary_hi_addr;
+		phytium_plane->dc_hw_update_cursor_hi_addr = NULL;
+	}
+
+	phytium_plane->dc_hw_plane_get_format(&format_modifiers, &formats, &format_count);
+	ret = drm_universal_plane_init(dev, &phytium_plane->base, 0x0,
+				       &phytium_plane_funcs, formats,
+				       format_count,
+				       format_modifiers,
+				       DRM_PLANE_TYPE_PRIMARY, "primary %d", phys_pipe);
+
+	if (ret)
+		goto failed_plane_init;
+
+	flags = DRM_MODE_ROTATE_0;
+	drm_plane_create_rotation_property(&phytium_plane->base, DRM_MODE_ROTATE_0, flags);
+	drm_plane_helper_add(&phytium_plane->base, &phytium_plane_helper_funcs);
+
+	return phytium_plane;
+failed_plane_init:
+	kfree(phytium_plane_state);
+failed_malloc_plane_state:
+	kfree(phytium_plane);
+failed_malloc_plane:
+	return ERR_PTR(ret);
+}
+
+struct phytium_plane *phytium_cursor_plane_create(struct drm_device *dev, int phys_pipe)
+{
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = NULL;
+	struct phytium_plane_state *phytium_plane_state = NULL;
+	int ret = 0;
+	unsigned int flags = 0;
+	const uint32_t *formats = NULL;
+	uint32_t format_count;
+	const uint64_t *format_modifiers;
+
+	phytium_plane = kzalloc(sizeof(*phytium_plane), GFP_KERNEL);
+	if (!phytium_plane) {
+		ret = -ENOMEM;
+		goto failed_malloc_plane;
+	}
+
+	phytium_plane_state = kzalloc(sizeof(*phytium_plane_state), GFP_KERNEL);
+	if (!phytium_plane_state) {
+		ret = -ENOMEM;
+		goto failed_malloc_plane_state;
+	}
+	phytium_plane_state->base.plane = &phytium_plane->base;
+	phytium_plane_state->base.rotation = DRM_MODE_ROTATE_0;
+	phytium_plane->base.state = &phytium_plane_state->base;
+	phytium_plane->phys_pipe = phys_pipe;
+
+	if (IS_PX210(priv)) {
+		phytium_plane->dc_hw_plane_get_format = px210_dc_hw_plane_get_cursor_format;
+		phytium_plane->dc_hw_update_dcreq = NULL;
+		phytium_plane->dc_hw_update_primary_hi_addr = NULL;
+		phytium_plane->dc_hw_update_cursor_hi_addr = NULL;
+	} else if (IS_PE220X(priv)) {
+		phytium_plane->dc_hw_plane_get_format = pe220x_dc_hw_plane_get_cursor_format;
+		phytium_plane->dc_hw_update_dcreq = NULL;
+		phytium_plane->dc_hw_update_primary_hi_addr = NULL;
+		phytium_plane->dc_hw_update_cursor_hi_addr = pe220x_dc_hw_update_cursor_hi_addr;
+	}
+
+	phytium_plane->dc_hw_plane_get_format(&format_modifiers, &formats, &format_count);
+	ret = drm_universal_plane_init(dev, &phytium_plane->base, 0x0,
+				       &phytium_plane_funcs,
+				       formats, format_count,
+				       format_modifiers,
+				       DRM_PLANE_TYPE_CURSOR, "cursor %d", phys_pipe);
+
+	if (ret)
+		goto failed_plane_init;
+
+	flags = DRM_MODE_ROTATE_0;
+	drm_plane_create_rotation_property(&phytium_plane->base, DRM_MODE_ROTATE_0, flags);
+	drm_plane_helper_add(&phytium_plane->base, &phytium_plane_helper_funcs);
+
+	return phytium_plane;
+failed_plane_init:
+	kfree(phytium_plane_state);
+failed_malloc_plane_state:
+	kfree(phytium_plane);
+failed_malloc_plane:
+	return ERR_PTR(ret);
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_plane.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_plane.h
new file mode 100644
index 00000000000000..ee8786ced54ca0
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_plane.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_PLANE_H__
+#define __PHYTIUM_PLANE_H__
+
+struct phytium_plane {
+	struct drm_plane base;
+	int phys_pipe;
+	unsigned long iova[PHYTIUM_FORMAT_MAX_PLANE];
+	unsigned long size[PHYTIUM_FORMAT_MAX_PLANE];
+	unsigned int format;
+	unsigned int tiling[PHYTIUM_FORMAT_MAX_PLANE];
+	unsigned int swizzle;
+	unsigned int uv_swizzle;
+	unsigned int rot_angle;
+
+	/* only for cursor */
+	bool enable;
+	bool reserve[3];
+	int cursor_x;
+	int cursor_y;
+	int cursor_hot_x;
+	int cursor_hot_y;
+
+	void (*dc_hw_plane_get_format)(const uint64_t **format_modifiers,
+				       const uint32_t **formats,
+				       uint32_t *format_count);
+	void (*dc_hw_update_dcreq)(struct drm_plane *plane);
+	void (*dc_hw_update_primary_hi_addr)(struct drm_plane *plane);
+	void (*dc_hw_update_cursor_hi_addr)(struct drm_plane *plane, uint64_t iova);
+};
+
+struct phytium_plane_state {
+	struct drm_plane_state base;
+};
+
+#define	to_phytium_plane(x)		container_of(x, struct phytium_plane, base)
+#define	to_phytium_plane_state(x)	container_of(x, struct phytium_plane_state, base)
+
+struct phytium_plane *phytium_primary_plane_create(struct drm_device *dev, int pipe);
+struct phytium_plane *phytium_cursor_plane_create(struct drm_device *dev, int pipe);
+#endif /* __PHYTIUM_PLANE_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_platform.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_platform.c
new file mode 100644
index 00000000000000..27815ecc9c5007
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_platform.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium display engine DRM driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/of_device.h>
+#include <linux/acpi.h>
+#include <drm/drm_drv.h>
+#include <linux/dma-mapping.h>
+#include "phytium_display_drv.h"
+#include "phytium_platform.h"
+#include "phytium_dp.h"
+#include "phytium_gem.h"
+#include "pe220x_dc.h"
+#include "pe220x_dp.h"
+
+int phytium_platform_carveout_mem_init(struct platform_device *pdev,
+						      struct phytium_display_private *priv)
+{
+	struct resource *res;
+	int ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res) {
+		priv->pool_size = resource_size(res);
+		priv->pool_phys_addr = res->start;
+	}
+
+	if ((priv->pool_phys_addr != 0) && (priv->pool_size != 0)) {
+		priv->pool_virt_addr = ioremap_cache(priv->pool_phys_addr, priv->pool_size);
+		if (priv->pool_virt_addr == NULL) {
+			DRM_ERROR("failed to remap carveout mem(0x%llx)\n", priv->pool_phys_addr);
+			ret = -EINVAL;
+			goto failed_ioremap;
+		}
+		ret = phytium_memory_pool_init(&pdev->dev, priv);
+		if (ret)
+			goto failed_init_memory_pool;
+
+		priv->mem_state[PHYTIUM_MEM_SYSTEM_CARVEOUT_TOTAL] = priv->pool_size;
+		priv->support_memory_type = MEMORY_TYPE_SYSTEM_CARVEOUT;
+		priv->vram_hw_init = NULL;
+	} else {
+		DRM_DEBUG_KMS("not support carveout memory\n");
+		priv->mem_state[PHYTIUM_MEM_SYSTEM_CARVEOUT_TOTAL] = 0;
+		priv->support_memory_type = MEMORY_TYPE_SYSTEM_UNIFIED;
+		priv->vram_hw_init = NULL;
+	}
+
+	return 0;
+
+failed_init_memory_pool:
+	iounmap(priv->pool_virt_addr);
+failed_ioremap:
+	return ret;
+}
+
+void phytium_platform_carveout_mem_fini(struct platform_device *pdev,
+						       struct phytium_display_private *priv)
+{
+	if (priv->support_memory_type == MEMORY_TYPE_SYSTEM_CARVEOUT) {
+		phytium_memory_pool_fini(&pdev->dev, priv);
+		iounmap(priv->pool_virt_addr);
+	}
+}
+
+static struct phytium_display_private *
+phytium_platform_private_init(struct platform_device *pdev)
+{
+	struct drm_device *dev = dev_get_drvdata(&pdev->dev);
+	struct device_node *node;
+	struct fwnode_handle *np;
+	struct phytium_display_private *priv = NULL;
+	struct phytium_platform_private *platform_priv = NULL;
+	struct phytium_device_info *phytium_info = NULL;
+	int i = 0, ret = 0;
+	struct resource *res;
+
+	platform_priv = devm_kzalloc(&pdev->dev, sizeof(*platform_priv), GFP_KERNEL);
+	if (!platform_priv) {
+		DRM_ERROR("no memory to allocate for phytium_platform_private\n");
+		goto exit;
+	}
+
+	memset(platform_priv, 0, sizeof(*platform_priv));
+	priv = &platform_priv->base;
+	phytium_display_private_init(priv, dev);
+
+	if (pdev->dev.of_node) {
+		phytium_info = (struct phytium_device_info *)of_device_get_match_data(&pdev->dev);
+		if (!phytium_info) {
+			DRM_ERROR("failed to get dts id data(phytium_info)\n");
+			goto failed;
+		}
+
+		memcpy(&(priv->info), phytium_info, sizeof(struct phytium_device_info));
+		node = pdev->dev.of_node;
+		ret = of_property_read_u8(node, "pipe_mask", &priv->info.pipe_mask);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing pipe_mask property from dts\n");
+			goto failed;
+		}
+
+		ret = of_property_read_u8(node, "edp_mask", &priv->info.edp_mask);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing edp_mask property from dts\n");
+			goto failed;
+		}
+	} else if (has_acpi_companion(&pdev->dev)) {
+		phytium_info = (struct phytium_device_info *)acpi_device_get_match_data(&pdev->dev);
+		if (!phytium_info) {
+			DRM_ERROR("failed to get acpi id data(phytium_info)\n");
+			goto failed;
+		}
+
+		memcpy(&(priv->info), phytium_info, sizeof(struct phytium_device_info));
+		np = dev_fwnode(&(pdev->dev));
+		ret = fwnode_property_read_u8(np, "pipe_mask", &priv->info.pipe_mask);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing pipe_mask property from acpi\n");
+			goto failed;
+		}
+		ret = fwnode_property_read_u8(np, "edp_mask", &priv->info.edp_mask);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing edp_mask property from acpi\n");
+			goto failed;
+		}
+	}
+
+	priv->info.num_pipes = 0;
+	for_each_pipe_masked(priv, i)
+		priv->info.num_pipes++;
+	if (priv->info.num_pipes == 0) {
+		DRM_ERROR("num_pipes is zero, so exit init\n");
+		goto failed;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (priv->regs == NULL) {
+		DRM_ERROR("ioremap fail, addr:0x%llx, size:0x%llx\n", res->start, res->end);
+		goto failed;
+	}
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		goto failed;
+	}
+
+	if (IS_PE220X(priv)) {
+		priv->dc_hw_clear_msi_irq = NULL;
+		priv->dc_hw_fb_format_check = pe220x_dc_hw_fb_format_check;
+	}
+
+	return priv;
+
+failed:
+	devm_kfree(&pdev->dev, platform_priv);
+exit:
+	return NULL;
+}
+
+static void phytium_platform_private_fini(struct platform_device *pdev)
+{
+	struct drm_device *dev = dev_get_drvdata(&pdev->dev);
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_platform_private *platform_priv = to_platform_priv(priv);
+
+	devm_kfree(&pdev->dev, platform_priv);
+}
+
+static int phytium_platform_probe(struct platform_device *pdev)
+{
+	struct phytium_display_private *priv = NULL;
+	struct drm_device *dev = NULL;
+	int ret = 0;
+
+	dev = drm_dev_alloc(&phytium_display_drm_driver, &pdev->dev);
+	if (IS_ERR(dev)) {
+		DRM_ERROR("failed to allocate drm_device\n");
+		return PTR_ERR(dev);
+	}
+
+	dev_set_drvdata(&pdev->dev, dev);
+	dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
+
+	priv = phytium_platform_private_init(pdev);
+	if (priv)
+		dev->dev_private = priv;
+	else
+		goto failed_platform_private_init;
+
+	ret = phytium_platform_carveout_mem_init(pdev, priv);
+	if (ret) {
+		DRM_ERROR("failed to init system carveout memory\n");
+		goto failed_carveout_mem_init;
+	}
+
+	ret = drm_dev_register(dev, 0);
+	if (ret) {
+		DRM_ERROR("failed to register drm dev\n");
+		goto failed_register_drm;
+	}
+
+	phytium_dp_hpd_irq_setup(dev, true);
+
+	return 0;
+
+failed_register_drm:
+	phytium_platform_carveout_mem_fini(pdev, priv);
+failed_carveout_mem_init:
+	phytium_platform_private_fini(pdev);
+failed_platform_private_init:
+	dev_set_drvdata(&pdev->dev, NULL);
+	drm_dev_put(dev);
+	return -1;
+}
+
+static int phytium_platform_remove(struct platform_device *pdev)
+{
+	struct drm_device *dev = dev_get_drvdata(&pdev->dev);
+	struct phytium_display_private *priv = dev->dev_private;
+
+	phytium_dp_hpd_irq_setup(dev, false);
+	cancel_work_sync(&priv->hotplug_work);
+	drm_dev_unregister(dev);
+	phytium_platform_private_fini(pdev);
+	dev_set_drvdata(&pdev->dev, NULL);
+	drm_dev_put(dev);
+
+	return 0;
+}
+
+static void phytium_platform_shutdown(struct platform_device *pdev)
+{
+	struct drm_device *dev = dev_get_drvdata(&pdev->dev);
+	struct phytium_display_private *priv = dev->dev_private;
+
+	priv->display_shutdown(dev);
+}
+
+static int phytium_platform_pm_suspend(struct device *dev)
+{
+	struct drm_device *drm_dev = dev_get_drvdata(dev);
+	struct phytium_display_private *priv = drm_dev->dev_private;
+
+	return priv->display_pm_suspend(drm_dev);
+}
+
+static int phytium_platform_pm_resume(struct device *dev)
+{
+	struct drm_device *drm_dev = dev_get_drvdata(dev);
+	struct phytium_display_private *priv = drm_dev->dev_private;
+
+	return priv->display_pm_resume(drm_dev);
+}
+
+static const struct dev_pm_ops phytium_platform_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_platform_pm_suspend, phytium_platform_pm_resume)
+};
+
+static const struct phytium_device_info pe220x_info = {
+	.platform_mask = BIT(PHYTIUM_PLATFORM_PE220X),
+	.total_pipes = 2,
+	.crtc_clock_max = PE220X_DC_PIX_CLOCK_MAX,
+	.hdisplay_max = PE220X_DC_HDISPLAY_MAX,
+	.vdisplay_max = PE220X_DC_VDISPLAY_MAX,
+	.address_mask = PE220X_DC_ADDRESS_MASK,
+	.backlight_max = PE220X_DP_BACKLIGHT_MAX,
+};
+
+static const struct of_device_id display_of_match[] = {
+	{
+		.compatible = "phytium,dc",
+		.data = (void*)&pe220x_info,
+	},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, display_of_match);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id display_acpi_ids[] = {
+	{
+		.id = "PHYT0015",
+		.driver_data = (kernel_ulong_t)&pe220x_info,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(acpi, display_acpi_ids);
+#else
+#define display_acpi_ids NULL
+#endif
+
+struct platform_driver phytium_platform_driver = {
+	.driver = {
+		.name = "phytium_display_platform",
+		.of_match_table = of_match_ptr(display_of_match),
+		.acpi_match_table = ACPI_PTR(display_acpi_ids),
+	},
+	.probe = phytium_platform_probe,
+	.remove = phytium_platform_remove,
+	.shutdown = phytium_platform_shutdown,
+	.driver.pm = &phytium_platform_pm_ops,
+};
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_platform.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_platform.h
new file mode 100644
index 00000000000000..e752f79130db5e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_platform.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_PLATFORM_H__
+#define __PHYTIUM_PLATFORM_H__
+
+struct phytium_platform_private {
+	struct phytium_display_private base;
+};
+
+#define	to_platform_priv(priv)		container_of(priv, struct phytium_platform_private, base)
+
+extern struct platform_driver phytium_platform_driver;
+
+#endif /* __PHYTIUM_PLATFORM_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_reg.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_reg.h
new file mode 100644
index 00000000000000..28735acee149ac
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/phytium_reg.h
@@ -0,0 +1,366 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_REG_H__
+#define __PHYTIUM_REG_H__
+
+/******************************register base******************************************/
+#define PX210_PIPE_BASE(pipe)				(0x8000*pipe)
+#define PX210_DC_BASE(pipe)				(PX210_PIPE_BASE(pipe) + 0x0000)
+#define PX210_DCREQ_BASE(pipe)				(PX210_PIPE_BASE(pipe) + 0x2000)
+#define PX210_DP_BASE(pipe)				(PX210_PIPE_BASE(pipe) + 0x3000)
+#define PX210_ADDRESS_TRANSFORM_BASE			0x4000
+#define PX210_PHY_ACCESS_BASE(pipe)			(PX210_PIPE_BASE(pipe) + 0x5000)
+
+#define PE220X_DC_BASE(pipe)				(0x1000*pipe)
+#define PE220X_DP_BASE(pipe)				(0x4000 + 0x1000*pipe)
+#define PE220X_ADDRESS_TRANSFORM_BASE			0x8000
+#define PE220X_PHY_ACCESS_BASE(pipe)			(0x6000 + 0x1000*pipe)
+/******************************register base end******************************************/
+
+/******************************dc register start******************************************/
+#define PHYTIUM_DC_FRAMEBUFFER_Y_ADDRESS		0x1400
+	#define ADDRESS_MASK					0xffffff80
+#define PHYTIUM_DC_FRAMEBUFFER_Y_STRIDE			0x1408
+#define	PHYTIUM_DC_PANEL_CONFIG				0x1418
+	#define	PANEL_DATAENABLE_ENABLE				(1<<0)
+	#define	PANEL_DATA_ENABLE				(1<<4)
+	#define PANEL_CLOCK_ENABLE				(1<<8)
+#define PHYTIUM_DC_HDISPLAY				0x1430
+	#define HDISPLAY_END_SHIFT				0
+	#define HDISPLAY_END_MASK				0x7fff
+	#define HDISPLAY_TOTAL_SHIFT				16
+	#define HDISPLAY_TOTAL_MASK				0x7fff
+#define	PHYTIUM_DC_HSYNC				0x1438
+	#define HSYNC_START_SHIFT				0
+	#define HSYNC_START_MASK				0x7fff
+	#define HSYNC_END_SHIFT					15
+	#define HSYNC_END_MASK					0x7fff
+	#define HSYNC_PULSE_ENABLED				(1<<30)
+	#define HSYNC_NEGATIVE					(1<<31)
+#define	PHYTIUM_DC_VDISPLAY				0x1440
+	#define VDISPLAY_END_SHIFT				0
+	#define VDISPLAY_END_MASK				0x7fff
+	#define VDISPLAY_TOTAL_SHIFT				16
+	#define VDISPLAY_TOTAL_MASK				0x7fff
+#define	PHYTIUM_DC_VSYNC				0x1448
+	#define VSYNC_START_SHIFT				0
+	#define VSYNC_START_MASK				0x7fff
+	#define VSYNC_END_SHIFT					15
+	#define VSYNC_END_MASK					0x7fff
+	#define VSYNC_PULSE_ENABLED				(1<<30)
+	#define VSYNC_NEGATIVE					(1<<31)
+#define	PHYTIUM_DC_LOCATION				0x1450
+	#define LOVATION_Y_SHIFT				16
+#define	PHYTIUM_DC_GAMMA_INDEX				0x1458
+	#define GAMMA_INDEX_MAX					256
+#define	PHYTIUM_DC_GAMMA_DATA				0x1460
+	#define GAMMA_BLUE_SHIFT				0
+	#define GAMMA_BLUE_MASK					0x3ff
+	#define GAMMA_GREEN_SHIFT				10
+	#define GAMMA_GREEN_MASK				0x3ff
+	#define GAMMA_RED_SHIFT					20
+	#define GAMMA_RED_MASK					0x3ff
+#define PHYTIUM_DC_CURSOR_CONFIG			0x1468
+	#define CURSOR_FORMAT_DISABLED				0x0
+	#define CURSOR_FORMAT_MASKMODE				0x3
+	#define CURSOR_FORMAT_ARGB8888				0x2
+	#define CURSOR_FORMAT_MASK				0x3
+	#define	CURSOR_HOT_Y_SHIFT				8
+	#define CURSOR_HOT_Y_MASK				0x1f
+	#define	CURSOR_HOT_X_SHIFT				16
+	#define CURSOR_HOT_X_MASK				0x1f
+#define	PHYTIUM_DC_CURSOR_ADDRESS			0x146c
+#define	PHYTIUM_DC_CURSOR_LOCATION			0x1470
+	#define CURSOR_X_SHIFT					0
+	#define	CURSOR_X_MASK					0x7fff
+	#define CURSOR_Y_SHIFT					16
+	#define	CURSOR_Y_MASK					0x7fff
+#define	PHYTIUM_DC_CURSOR_BACKGROUND			0x1474
+#define PHYTIUM_DC_CURSOR_FOREGROUND			0x1478
+#define PHYTIUM_DC_INT_STATUS				0x147c
+	#define INT_STATUS					0x1
+#define	PHYTIUM_DC_INT_ENABLE				0x1480
+	#define INT_ENABLE					0x1
+	#define INT_DISABLE					0x0
+
+#define PHYTIUM_DC_FRAMEBUFFER_CONFIG			0x1518
+	#define FRAMEBUFFER_OUTPUT				BIT(0)
+	#define FRAMEBUFFER_GAMMA_ENABLE			BIT(2)
+	#define FRAMEBUFFER_VALID_PENDING			BIT(3)
+	#define FRAMEBUFFER_RESET				BIT(4)
+	#define FRAMEBUFFER_PROGRESS				BIT(6)
+	#define FRAMEBUFFER_ROT_ANGLE_SHIFT			(11)
+	#define FRAMEBUFFER_ROT_ANGLE_MASK			(0x7)
+	#define FRAMEBUFFER_ROT_ANGLE_ROT0			(0)
+	#define FRAMEBUFFER_ROT_ANGLE_FLIP_X			(1)
+	#define FRAMEBUFFER_ROT_ANGLE_FLIP_Y			(2)
+	#define FRAMEBUFFER_TILE_MODE_SHIFT			(17)
+	#define FRAMEBUFFER_TILE_MODE_MASK			(0x1f)
+	#define FRAMEBUFFER_LINEAR				0
+	#define FRAMEBUFFER_TILE_MODE0				4
+	#define FRAMEBUFFER_TILE_MODE3				7
+	#define FRAMEBUFFER_FORMAT_SHIFT			26
+	#define FRAMEBUFFER_FORMAT_MASK				0x3f
+	#define FRAMEBUFFER_FORMAT_XRGB4444			0x0
+	#define FRAMEBUFFER_FORMAT_ARGB4444			0x1
+	#define FRAMEBUFFER_FORMAT_XRGB1555			0x2
+	#define FRAMEBUFFER_FORMAT_ARGB1555			0x3
+	#define FRAMEBUFFER_FORMAT_RGB565			0x4
+	#define	FRAMEBUFFER_FORMAT_XRGB8888			0x5
+	#define FRAMEBUFFER_FORMAT_ARGB8888			0x6
+	#define FRAMEBUFFER_FORMAT_YUYV				0x7
+	#define FRAMEBUFFER_FORMAT_UYVY				0x8
+	#define FRAMEBUFFER_FORMAT_NV12				0x11
+	#define FRAMEBUFFER_FORMAT_NV16				0x12
+	#define FRAMEBUFFER_FORMAT_ARGB2101010			0x16
+	#define FRAMEBUFFER_SWIZZLE_SHIFT			23
+	#define FRAMEBUFFER_SWIZZLE_MASK			0x3
+	#define	FRAMEBUFFER_SWIZZLE_ARGB			0
+	#define	FRAMEBUFFER_SWIZZLE_RGBA			1
+	#define	FRAMEBUFFER_SWIZZLE_ABGR			2
+	#define	FRAMEBUFFER_SWIZZLE_BGRA			3
+	#define FRAMEBUFFER_UVSWIZZLE_SHIFT			25
+	#define FRAMEBUFFER_UVSWIZZLE_DISABLE			0
+	#define FRAMEBUFFER_UVSWIZZLE_ENABLE			1
+	#define FRAMEBUFFER_CLEAR				BIT(8)
+	#define FRAMEBUFFER_SCALE_ENABLE			BIT(22)
+#define PHYTIUM_DC_FRAMEBUFFER_SCALECONFIG		0x1520
+	#define FRAMEBUFFER_FILTER_TAP				3
+	#define FRAMEBUFFER_HORIZONTAL_FILTER_TAP		3
+	#define FRAMEBUFFER_TAP					0x33
+#define	PHYTIUM_DC_FRAMEBUFFER_U_ADDRESS		0x1530
+#define PHYTIUM_DC_FRAMEBUFFER_V_ADDRESS		0x1538
+#define PHYTIUM_DC_OVERLAY_CONFIG			0x1540
+	#define	PX210_DC_OVERLAY_ENABLE				BIT(24)
+
+#define PHYTIUM_DC_FRAMEBUFFER_U_STRIDE			0x1800
+#define PHYTIUM_DC_FRAMEBUFFER_V_STRIDE			0x1808
+#define PHYTIUM_DC_FRAMEBUFFER_SIZE			0x1810
+	#define WIDTH_SHIFT					0
+	#define WIDTH_MASK					0x7fff
+	#define HEIGHT_SHIFT					15
+	#define HEIGHT_MASK					0x7fff
+
+#define PHYTIUM_DC_FRAMEBUFFER_SCALE_FACTOR_X		0x1828
+	#define SCALE_FACTOR_X_MASK				0x7fffffff
+#define PHYTIUM_DC_FRAMEBUFFER_SCALE_FACTOR_Y		0x1830
+	#define SCALE_FACTOR_Y_MASK				0x7fffffff
+	#define SCALE_FACTOR_Y_MAX				0x3
+	#define SCALE_FACTOR_SRC_OFFSET				16
+
+#define PHYTIUM_DC_FRAMEBUFFER_HORI_FILTER_INDEX	0x1838
+	#define HORI_FILTER_INDEX				0x0
+#define PHYTIUM_DC_FRAMEBUFFER_HORI_FILTER		0x1a00
+#define PHYTIUM_DC_FRAMEBUFFER_VERT_FILTER_INDEX	0x1a08
+	#define VERT_FILTER_INDEX				0x0
+#define PHYTIUM_DC_FRAMEBUFFER_VERT_FILTER		0x1a10
+#define PHYTIUM_DC_FRAMEBUFFER_CLEARVALUE		0x1a18
+	#define CLEAR_VALUE_RED					0x00ff0000
+	#define CLEAR_VALUE_GREEN				0x0000ff00
+	#define CLEAR_VALUE_BLACK				0x00000000
+#define PHYTIUM_DC_FRAMEBUFFER_INITIALOFFSET		0x1a20
+	#define INITIALOFFSET					(0x8000 | (0X8000 << 16))
+#define PHYTIUM_DC_DP_CONFIG				0x1cd0
+	#define	OUTPUT_DP					(1<<3)
+	#define DP_RGB666					(0x1)
+	#define DP_RGB888					(0x2)
+	#define DP_RGB101010					(0x3)
+/******************************dc register end********************************************/
+
+/******************************phy access register****************************************/
+#define	PHYTIUM_PHY_ACCESS_ADDRESS			0x0000
+#define	PHYTIUM_PHY_WRITE_DATA				0x0004
+#define	PHYTIUM_PHY_READ_DATA				0x0008
+#define	PHYTIUM_PHY_ACCESS_CTRL				0x000c
+	#define ACCESS_WRITE					(1<<0)
+	#define ACCESS_READ					(1<<1)
+/******************************phy access register end*************************************/
+
+/******************************dp register start******************************************/
+#define PHYTIUM_DP_LINK_BW_SET				0x0000
+#define PHYTIUM_DP_LANE_COUNT_SET			0x0004
+#define PHYTIUM_DP_ENHANCED_FRAME_EN			0x0008
+	#define ENHANCED_FRAME_ENABLE				0x1
+	#define ENHANCED_FRAME_DISABLE				0x0
+#define PHYTIUM_DP_TRAINING_PATTERN_SET			0x000c
+	#define TRAINING_OFF					0x0
+	#define TRAINING_PATTERN_1				0x1
+	#define TRAINING_PATTERN_2				0x2
+	#define TRAINING_PATTERN_3				0x3
+	#define TRAINING_PATTERN_4				0x4
+#define PHYTIUM_DP_LINK_QUAL_PATTERN_SET		0x0010
+	#define TEST_PATTERN_NONE				0x0
+	#define TEST_PATTERN_D10_2				0x1
+	#define TEST_PATTERN_SYMBOL_ERROR			0x2
+	#define TEST_PATTERN_PRBS7				0x3
+	#define TEST_PATTERN_80BIT_CUSTOM			0x4
+	#define TEST_PATTERN_CP2520_1				0x5
+	#define TEST_PATTERN_CP2520_2				0x6
+	#define TEST_PATTERN_CP2520_3				0x7
+	#define TEST_PATTERN_LANE_SHIFT				8
+#define PHYTIUM_DP_SCRAMBLING_DISABLE			0x0014
+	#define SCRAMBLING_ENABLE				0x0
+	#define SCRAMBLING_DISABLE				0x1
+#define PHYTIUM_DP_DOWNSPREAD_CTRL			0x0018
+#define PHYTIUM_DP_ALT_SCRAMBLER_RESET			0x001c
+#define PHYTIUM_DP_HBR2_SCRAMBLER_RESET			0x0020
+#define PHYTIUM_DP_DISPLAYPORT_VERSION			0x0024
+#define PHYTIUM_DP_CUSTOM_80BIT_PATTERN_0		0x0030
+#define PHYTIUM_DP_CUSTOM_80BIT_PATTERN_1		0x0034
+#define PHYTIUM_DP_CUSTOM_80BIT_PATTERN_2		0x0038
+#define PHYTIUM_DP_TRANSMITTER_OUTPUT_ENABLE		0x0080
+	#define TRANSMITTER_OUTPUT_ENABLE			BIT(0)
+	#define TRANSMITTER_OUTPUT_DISABLE			0
+#define PHYTIUM_DP_VIDEO_STREAM_ENABLE			0x0084
+	#define SST_MST_SOURCE_0_ENABLE				BIT(0)
+	#define SST_MST_SOURCE_0_ENABLE_MASK			0x1
+	#define SST_MST_SOURCE_0_DISABLE			0
+#define PHYTIUM_DP_SECONDARY_STREAM_ENABLE		0x0088
+	#define SECONDARY_STREAM_ENABLE				0x1
+	#define SECONDARY_STREAM_DISABLE			0x0
+#define PHYTIUM_DP_SEC_DATA_WINDOW			0x008C
+#define PHYTIUM_DP_SOFT_RESET				0x0090
+	#define LINK_SOFT_RESET					(0x1 << 0)
+	#define VIDEO_SOFT_RESET				(0x1 << 1)
+#define PHYTIUM_INPUT_SOURCE_ENABLE			0x0094
+	#define VIRTUAL_SOURCE_0_ENABLE				BIT(0)
+	#define VIRTUAL_SOURCE_0_ENABLE_MASK			0x1
+#define PHYTIUM_DP_FORCE_SCRAMBLER_RESET		0x00C0
+	#define SCRAMBLER_RESET					BIT(0)
+#define PHYTIUM_DP_SOURCE_CONTROL_STATUS		0x00C4
+#define PHYTIUM_DP_DATA_CONTROL				0x00C8
+#define PHYTIUM_DP_CORE_CAPABILITY			0x00F8
+#define PHYTIUM_DP_CORE_ID				0x00FC
+#define PHYTIUM_DP_AUX_COMMAND				0x0100
+	#define BYTE_COUNT_MASK					0xf
+	#define COMMAND_SHIFT					8
+	#define COMMAND_MASK					0xf
+	#define ADDRESS_ONLY					(1<<12)
+#define PHYTIUM_DP_AUX_WRITE_FIFO			0x0104
+#define PHYTIUM_DP_AUX_ADDRESS				0x0108
+#define PHYTIUM_DP_AUX_CLK_DIVIDER			0x010C
+	#define	AUX_CLK_DIVIDER					48
+	#define AUX_CLK_DIVIDER_100				100
+#define PHYTIUM_DP_SINK_HPD_STATE			0x0128
+	#define HPD_CONNECT					0x1
+	#define HPD_DISCONNECT					0x0
+#define PHYTIUM_DP_INTERRUPT_RAW_STATUS			0x0130
+	#define REPLY_TIMEOUT					(1<<3)
+	#define DP_STATUS_REQUEST_IN_PROGRESS			(1<<1)
+	#define HPD_STATE					(0<<1)
+#define PHYTIUM_DP_AUX_REPLY_DATA			0x0134
+#define PHYTIUM_DP_AUX_REPLY_CODE			0x0138
+	#define AUX_NATIVE_ACK					(0x0<<0)
+	#define AUX_NATIVE_NACK					(0x1<<0)
+	#define AUX_NATIVE_DEFER				(0x2<<0)
+	#define	AUX_NATIVE_MASK					(0x3 << 0)
+	#define AUX_I2C_ACK					(0x0<<2)
+	#define AUX_I2C_NACK					(0x1<<2)
+	#define AUX_I2C_DEFER					(0x2<<2)
+	#define AUX_I2C_MASK					(0x3 << 2)
+#define PHYTIUM_DP_INTERRUPT_STATUS			0x0140
+	#define HPD_IRQ						(1<<1)
+	#define HPD_EVENT					(1<<0)
+#define PHYTIUM_DP_INTERRUPT_MASK			0x0144
+	#define HPD_IRQ_MASK					(1<<1)
+	#define HPD_EVENT_MASK					(1<<0)
+	#define HPD_OTHER_MASK					0x3c
+#define PHYTIUM_DP_AUX_REPLY_DATA_COUNT			0x0148
+#define PHYTIUM_DP_AUX_STATUS				0x014C
+	#define REPLY_RECEIVED					0x1
+	#define REPLY_IN_PROGRESS				0x2
+	#define REQUEST_IN_PROGRESS				0x4
+	#define REPLY_ERROR					0x8
+#define PHYTIUM_DP_AUX_TIMER				0x0158
+#define PHYTIUM_DP_MAIN_LINK_HTOTAL			0x0180
+#define PHYTIUM_DP_MAIN_LINK_VTOTAL			0x0184
+#define PHYTIUM_DP_MAIN_LINK_POLARITY			0x0188
+	#define	VSYNC_POLARITY_LOW				BIT(1)
+	#define	HSYNC_POLARITY_LOW				BIT(0)
+#define PHYTIUM_DP_MAIN_LINK_HSWIDTH			0x018C
+#define PHYTIUM_DP_MAIN_LINK_VSWIDTH			0x0190
+#define PHYTIUM_DP_MAIN_LINK_HRES			0x0194
+#define PHYTIUM_DP_MAIN_LINK_VRES			0x0198
+#define PHYTIUM_DP_MAIN_LINK_HSTART			0x019C
+#define PHYTIUM_DP_MAIN_LINK_VSTART			0x01A0
+#define PHYTIUM_DP_MAIN_LINK_MISC0			0x01A4
+	#define MISC0_SYNCHRONOUS_CLOCK				BIT(0)
+	#define MISC0_BIT_DEPTH_OFFSET				5
+	#define MISC0_BIT_DEPTH_6BIT				0x0
+	#define	MISC0_BIT_DEPTH_8BIT				0x1
+	#define MISC0_BIT_DEPTH_10BIT				0x2
+	#define MISC0_COMPONENT_FORMAT_SHIFT			1
+	#define MISC0_COMPONENT_FORMAT_RGB			0x0
+#define PHYTIUM_DP_MAIN_LINK_MISC1			0x01A8
+#define PHYTIUM_DP_M_VID				0x01AC
+#define PHYTIUM_DP_TRANSFER_UNIT_SIZE			0x01B0
+#define PHYTIUM_DP_N_VID				0x01B4
+#define PHYTIUM_DP_USER_PIXEL_WIDTH			0x01B8
+#define PHYTIUM_DP_DATA_COUNT				0x01BC
+#define PHYTIUM_DP_INTERLACED				0x01C0
+#define PHYTIUM_DP_USER_SYNC_POLARITY			0x01C4
+	#define USER_ODDEVEN_POLARITY_HIGH			BIT(3)
+	#define USER_DATA_ENABLE_POLARITY_HIGH			BIT(2)
+	#define USER_VSYNC_POLARITY_HIGH			BIT(1)
+	#define USER_HSYNC_POLARITY_HIGH			BIT(0)
+#define PHYTIUM_DP_USER_CONTROL				0x01C8
+#define PHYTIUM_EDP_CRC_ENABLE				0x01D0
+	#define SUPPORT_EDP_1_4					BIT(1)
+#define PHYTIUM_EDP_CRC_RED				0x01D4
+#define PHYTIUM_EDP_CRC_GREEN				0x01D8
+#define PHYTIUM_EDP_CRC_BLUE				0x01DC
+#define PHYTIUM_DP_SEC_AUDIO_ENABLE			0x0300
+	#define SEC_AUDIO_ENABLE				BIT(0)
+	#define CHANNEL_MUTE_ENABLE				BIT(1)
+#define PHYTIUM_DP_SEC_INPUT_SELECT			0x0304
+	#define INPUT_SELECT_I2S				0x0
+#define PHYTIUM_DP_SEC_CHANNEL_COUNT			0x0308
+	#define CHANNEL_2					0x2
+	#define CHANNEL_2_LFE					0x3
+	#define CHANNEL_5_1					0x6
+	#define CHANNEL_7_1					0x7
+	#define CHANNEL_MASK					0xf
+#define PHYTIUM_DP_SEC_DIRECT_CLKDIV			0x030c
+	#define APB_CLOCK					48000000
+#define PHYTIUM_DP_SEC_MAUD				0x0318
+#define PHYTIUM_DP_SEC_NAUD				0x031c
+#define PHYTIUM_DP_SEC_CLOCK_MODE			0x0320
+	#define CLOCK_MODE_SYNC					0x1
+#define PHYTIUM_DP_SEC_CS_SOURCE_FORMAT			0x0340
+	#define CS_SOURCE_FORMAT_DEFAULT			0x0
+#define PHYTIUM_DP_SEC_CS_CATEGORY_CODE			0x0344
+#define PHYTIUM_DP_SEC_CS_LENGTH_ORIG_FREQ		0x0348
+	#define ORIG_FREQ_32000					0xc
+	#define ORIG_FREQ_44100					0xf
+	#define ORIG_FREQ_48000					0xd
+	#define ORIG_FREQ_88200					0x7
+	#define ORIG_FREQ_96000					0x5
+	#define ORIG_FREQ_176400				0x3
+	#define ORIG_FREQ_192000				0x1
+	#define ORIG_FREQ_MASK					0xf
+	#define ORIG_FREQ_SHIFT					0
+	#define WORD_LENGTH_16					0x4
+	#define WORD_LENGTH_18					0x2
+	#define WORD_LENGTH_20					0xc
+	#define WORD_LENGTH_24					0xd
+	#define WORD_LENGTH_MASK				0xf
+	#define WORD_LENGTH_SHIFT				4
+#define PHYTIUM_DP_SEC_CS_FREQ_CLOCK_ACCURACY		0x034c // not used
+	#define SAMPLING_FREQ_32000				0xc
+	#define SAMPLING_FREQ_44100				0x0
+	#define SAMPLING_FREQ_48000				0x4
+	#define SAMPLING_FREQ_88200				0x1
+	#define SAMPLING_FREQ_96000				0x5
+	#define SAMPLING_FREQ_176400				0x3
+	#define SAMPLING_FREQ_192000				0x7
+	#define SAMPLING_FREQ_MASK				0xf
+	#define SAMPLING_FREQ_SHIFT				4
+#define PHYTIUM_DP_SEC_CHANNEL_MAP			0x035C
+	#define CHANNEL_MAP_DEFAULT				0x87654321
+/******************************dp register end********************************************/
+
+#endif /* __PHYTIUM_REG_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dc.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dc.c
new file mode 100644
index 00000000000000..5c55f223ef5731
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dc.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <asm/neon.h>
+#include <linux/delay.h>
+#include "phytium_display_drv.h"
+#include "px210_reg.h"
+#include "phytium_crtc.h"
+#include "phytium_plane.h"
+#include "phytium_fb.h"
+#include "phytium_gem.h"
+
+static const unsigned int px210_primary_formats[] = {
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_RGBA1010102,
+	DRM_FORMAT_BGRA1010102,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_RGBA8888,
+	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_BGRX8888,
+	DRM_FORMAT_ARGB4444,
+	DRM_FORMAT_ABGR4444,
+	DRM_FORMAT_RGBA4444,
+	DRM_FORMAT_BGRA4444,
+	DRM_FORMAT_XRGB4444,
+	DRM_FORMAT_XBGR4444,
+	DRM_FORMAT_RGBX4444,
+	DRM_FORMAT_BGRX4444,
+	DRM_FORMAT_ARGB1555,
+	DRM_FORMAT_ABGR1555,
+	DRM_FORMAT_RGBA5551,
+	DRM_FORMAT_BGRA5551,
+	DRM_FORMAT_XRGB1555,
+	DRM_FORMAT_XBGR1555,
+	DRM_FORMAT_RGBX5551,
+	DRM_FORMAT_BGRX5551,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_BGR565,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_UYVY,
+};
+
+static uint64_t px210_primary_formats_modifiers[] = {
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_PHYTIUM_TILE_MODE0_FBCDC,
+	DRM_FORMAT_MOD_PHYTIUM_TILE_MODE3_FBCDC,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static uint64_t px210_cursor_formats_modifiers[] = {
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const unsigned int px210_cursor_formats[] = {
+	DRM_FORMAT_ARGB8888,
+};
+
+void px210_dc_hw_vram_init(struct phytium_display_private *priv, resource_size_t vram_addr,
+				   resource_size_t vram_size)
+{
+	uint32_t config;
+	uint32_t group_offset = priv->address_transform_base;
+
+	config = phytium_readl_reg(priv, group_offset,
+				   PX210_GPU_ADDRESS_TRANSFORM_SRC_ADDR);
+	if (config)
+		phytium_writel_reg(priv, config, group_offset,
+				   PX210_GPU_ADDRESS_TRANSFORM_SRC_ADDR);
+
+	config = phytium_readl_reg(priv, group_offset,
+				   PX210_GPU_ADDRESS_TRANSFORM_SIZE);
+	if (config)
+		phytium_writel_reg(priv, config, group_offset,
+				   PX210_GPU_ADDRESS_TRANSFORM_SIZE);
+
+	config = phytium_readl_reg(priv, group_offset,
+				   PX210_GPU_ADDRESS_TRANSFORM_DST_ADDR);
+	if (config)
+		phytium_writel_reg(priv, config, group_offset,
+				   PX210_GPU_ADDRESS_TRANSFORM_DST_ADDR);
+
+	phytium_writel_reg(priv, (vram_addr & SRC_ADDR_MASK) >> SRC_ADDR_OFFSET,
+			   group_offset, PX210_DC_ADDRESS_TRANSFORM_SRC_ADDR);
+	phytium_writel_reg(priv, (vram_size >> SIZE_OFFSET) | ADDRESS_TRANSFORM_ENABLE,
+			   group_offset, PX210_DC_ADDRESS_TRANSFORM_SIZE);
+	config = phytium_readl_reg(priv, group_offset, PX210_DC_ADDRESS_TRANSFORM_DST_ADDR);
+	phytium_writel_reg(priv, config, group_offset, PX210_DC_ADDRESS_TRANSFORM_DST_ADDR);
+}
+
+void px210_dc_hw_clear_msi_irq(struct phytium_display_private *priv, uint32_t phys_pipe)
+{
+	phytium_writel_reg(priv, MSI_CLEAR, priv->dcreq_reg_base[phys_pipe], PX210_DCREQ_MSI_CLEAR);
+}
+
+void px210_dc_hw_config_pix_clock(struct drm_crtc *crtc, int clock)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int phys_pipe = phytium_crtc->phys_pipe;
+	uint32_t group_offset = priv->dcreq_reg_base[phys_pipe];
+	int ret = 0;
+
+	/* config pix clock */
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_PIXEL_CLOCK | (clock & PIXEL_CLOCK_MASK),
+			   group_offset, PX210_DCREQ_CMD_REGISTER);
+	ret = phytium_wait_cmd_done(priv, group_offset + PX210_DCREQ_CMD_REGISTER,
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to set pixel clock\n", __func__);
+}
+
+void px210_dc_hw_disable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+	int reset_timeout = 100;
+	int config = 0;
+	int phys_pipe = phytium_crtc->phys_pipe;
+
+	// reset dc
+	config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe], PX210_DC_CLOCK_CONTROL);
+	phytium_writel_reg(priv, config | SOFT_RESET, priv->dc_reg_base[phys_pipe],
+			   PX210_DC_CLOCK_CONTROL);
+	phytium_writel_reg(priv, 0, priv->dc_reg_base[phys_pipe], PX210_DC_CLOCK_CONTROL);
+	do {
+		config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe], PX210_DC_CLOCK_IDLE);
+		if (config | IS_IDLE)
+			break;
+		mdelay(1);
+		reset_timeout--;
+	} while (reset_timeout);
+
+	/* reset pix clock */
+	px210_dc_hw_config_pix_clock(crtc, 0);
+
+	// reset dc
+	reset_timeout = 100;
+	config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe], PX210_DC_CLOCK_CONTROL);
+	phytium_writel_reg(priv, config | SOFT_RESET, priv->dc_reg_base[phys_pipe],
+			   PX210_DC_CLOCK_CONTROL);
+	phytium_writel_reg(priv, 0, priv->dc_reg_base[phys_pipe], PX210_DC_CLOCK_CONTROL);
+	do {
+		config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe], PX210_DC_CLOCK_IDLE);
+		if (config | IS_IDLE)
+			break;
+		mdelay(1);
+		reset_timeout--;
+	} while (reset_timeout);
+
+	/* reset dcreq */
+	phytium_writel_reg(priv, DCREQ_PLAN_A, priv->dcreq_reg_base[phys_pipe], PX210_DCREQ_PLAN);
+	phytium_writel_reg(priv, 0, priv->dcreq_reg_base[phys_pipe], PX210_DCREQ_CONTROL);
+	phytium_writel_reg(priv, DCREQ_RESET, priv->dcreq_reg_base[phys_pipe], PX210_DCREQ_RESET);
+	msleep(20);
+	phytium_writel_reg(priv, (~DCREQ_RESET)&DCREQ_RESET_MASK,
+			   priv->dcreq_reg_base[phys_pipe], PX210_DCREQ_RESET);
+}
+
+int px210_dc_hw_fb_format_check(const struct drm_mode_fb_cmd2 *mode_cmd, int count)
+{
+	int ret = 0;
+
+	switch (mode_cmd->modifier[count]) {
+	case DRM_FORMAT_MOD_PHYTIUM_TILE_MODE0_FBCDC:
+		switch (mode_cmd->pixel_format) {
+		case DRM_FORMAT_ARGB4444:
+		case DRM_FORMAT_ABGR4444:
+		case DRM_FORMAT_RGBA4444:
+		case DRM_FORMAT_BGRA4444:
+		case DRM_FORMAT_XRGB4444:
+		case DRM_FORMAT_XBGR4444:
+		case DRM_FORMAT_RGBX4444:
+		case DRM_FORMAT_BGRX4444:
+		case DRM_FORMAT_ARGB1555:
+		case DRM_FORMAT_ABGR1555:
+		case DRM_FORMAT_RGBA5551:
+		case DRM_FORMAT_BGRA5551:
+		case DRM_FORMAT_XRGB1555:
+		case DRM_FORMAT_XBGR1555:
+		case DRM_FORMAT_RGBX5551:
+		case DRM_FORMAT_BGRX5551:
+		case DRM_FORMAT_RGB565:
+		case DRM_FORMAT_BGR565:
+		case DRM_FORMAT_YUYV:
+		case DRM_FORMAT_UYVY:
+			break;
+		default:
+			DRM_ERROR("TILE_MODE0_FBCDC not support DRM_FORMAT %d",
+				   mode_cmd->pixel_format);
+			ret = -EINVAL;
+			goto error;
+		}
+		break;
+	case DRM_FORMAT_MOD_PHYTIUM_TILE_MODE3_FBCDC:
+		switch (mode_cmd->pixel_format) {
+		case DRM_FORMAT_ARGB2101010:
+		case DRM_FORMAT_ABGR2101010:
+		case DRM_FORMAT_RGBA1010102:
+		case DRM_FORMAT_BGRA1010102:
+		case DRM_FORMAT_ARGB8888:
+		case DRM_FORMAT_ABGR8888:
+		case DRM_FORMAT_RGBA8888:
+		case DRM_FORMAT_BGRA8888:
+		case DRM_FORMAT_XRGB8888:
+		case DRM_FORMAT_XBGR8888:
+		case DRM_FORMAT_RGBX8888:
+		case DRM_FORMAT_BGRX8888:
+			break;
+		default:
+			DRM_ERROR("TILE_MODE3_FBCDC not support DRM_FORMAT %d",
+				   mode_cmd->pixel_format);
+			ret = -EINVAL;
+			goto error;
+		}
+		break;
+	case DRM_FORMAT_MOD_LINEAR:
+		break;
+	default:
+		DRM_ERROR("unsupported fb modifier 0x%llx\n", mode_cmd->modifier[0]);
+		ret = -EINVAL;
+		goto error;
+	}
+
+	return 0;
+error:
+	return ret;
+}
+
+void px210_dc_hw_plane_get_primary_format(const uint64_t **format_modifiers,
+							 const uint32_t **formats,
+							 uint32_t *format_count)
+{
+	*format_modifiers = px210_primary_formats_modifiers;
+	*formats = px210_primary_formats;
+	*format_count = ARRAY_SIZE(px210_primary_formats);
+}
+
+void px210_dc_hw_plane_get_cursor_format(const uint64_t **format_modifiers,
+							const uint32_t **formats,
+							uint32_t *format_count)
+{
+	*format_modifiers = px210_cursor_formats_modifiers;
+	*formats = px210_cursor_formats;
+	*format_count = ARRAY_SIZE(px210_cursor_formats);
+}
+
+void px210_dc_hw_update_dcreq(struct drm_plane *plane)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	int phys_pipe = phytium_plane->phys_pipe;
+	uint32_t group_offset = priv->dcreq_reg_base[phys_pipe];
+	int config;
+
+	if (phytium_plane->tiling[0] == FRAMEBUFFER_LINEAR) {
+		phytium_writel_reg(priv, DCREQ_MODE_LINEAR,
+				   group_offset, PX210_DCREQ_PLANE0_CONFIG);
+	} else {
+		config = DCREQ_NO_LOSSY;
+		if (phytium_plane->tiling[0] == FRAMEBUFFER_TILE_MODE0)
+			config |= DCREQ_TILE_TYPE_MODE0;
+		else if (phytium_plane->tiling[0] == FRAMEBUFFER_TILE_MODE3)
+			config |= DCREQ_TILE_TYPE_MODE3;
+		else
+			config |= DCREQ_TILE_TYPE_MODE0;
+
+		switch (phytium_plane->format) {
+		case FRAMEBUFFER_FORMAT_ARGB8888:
+		case FRAMEBUFFER_FORMAT_XRGB8888:
+			config |= DCREQ_COLOURFORMAT_BGRA8888;
+			break;
+		case FRAMEBUFFER_FORMAT_ARGB2101010:
+			config |= DCREQ_COLOURFORMAT_ARGB2101010;
+			break;
+		case FRAMEBUFFER_FORMAT_XRGB4444:
+		case FRAMEBUFFER_FORMAT_ARGB4444:
+			config |= DCREQ_COLOURFORMAT_ARGB4444;
+			break;
+		case FRAMEBUFFER_FORMAT_XRGB1555:
+		case FRAMEBUFFER_FORMAT_ARGB1555:
+			config |= DCREQ_COLOURFORMAT_ARGB1555;
+			break;
+		case FRAMEBUFFER_FORMAT_RGB565:
+			config |= DCREQ_COLOURFORMAT_RGB565;
+			break;
+		case FRAMEBUFFER_FORMAT_YUYV:
+			config |= DCREQ_COLOURFORMAT_YUYV;
+			break;
+		case FRAMEBUFFER_FORMAT_UYVY:
+			config |= DCREQ_COLOURFORMAT_UYVY;
+			break;
+		}
+		config |= DCREQ_ARGBSWIZZLE_ARGB;
+		config |= DCREQ_MODE_TILE;
+		phytium_writel_reg(priv, phytium_plane->iova[0] & 0xffffffff,
+				   group_offset, PX210_DCREQ_PLANE0_ADDR_START);
+		phytium_writel_reg(priv, (phytium_plane->iova[0] + phytium_plane->size[0]) &
+				   0xffffffff, group_offset, PX210_DCREQ_PLANE0_ADDR_END);
+		phytium_writel_reg(priv, config, group_offset, PX210_DCREQ_PLANE0_CONFIG);
+	}
+}
+
+void px210_dc_hw_update_primary_hi_addr(struct drm_plane *plane)
+{
+	struct drm_device *dev = plane->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+	int phys_pipe = phytium_plane->phys_pipe;
+
+	phytium_writel_reg(priv, (phytium_plane->iova[0] >> PREFIX_SHIFT) & PREFIX_MASK,
+			   priv->dcreq_reg_base[phys_pipe], PX210_DCREQ_PIX_DMA_PREFIX);
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dc.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dc.h
new file mode 100644
index 00000000000000..acb2dd6cb5c903
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PX210_DC_H__
+#define __PX210_DC_H__
+
+#define PX210_DC_PIX_CLOCK_MAX				(594000)
+#define PX210_DC_HDISPLAY_MAX				3840
+#define PX210_DC_VDISPLAY_MAX				2160
+#define PX210_DC_ADDRESS_MASK				0x7f
+
+extern void px210_dc_hw_vram_init(struct phytium_display_private *priv,
+					   resource_size_t vram_addr,
+					   resource_size_t vram_size);
+extern void px210_dc_hw_clear_msi_irq(struct phytium_display_private *priv, uint32_t phys_pipe);
+extern void px210_dc_hw_config_pix_clock(struct drm_crtc *crtc, int clock);
+extern void px210_dc_hw_disable(struct drm_crtc *crtc);
+extern int px210_dc_hw_fb_format_check(const struct drm_mode_fb_cmd2 *mode_cmd, int count);
+extern void px210_dc_hw_plane_get_primary_format(const uint64_t **format_modifiers,
+								const uint32_t **formats,
+								uint32_t *format_count);
+extern void px210_dc_hw_plane_get_cursor_format(const uint64_t **format_modifiers,
+							       const uint32_t **formats,
+							       uint32_t *format_count);
+void px210_dc_hw_update_dcreq(struct drm_plane *plane);
+void px210_dc_hw_update_primary_hi_addr(struct drm_plane *plane);
+#endif /* __PX210_DC_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dp.c b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dp.c
new file mode 100644
index 00000000000000..d7bd04eac2a847
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dp.c
@@ -0,0 +1,920 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include "phytium_display_drv.h"
+#include "px210_reg.h"
+#include "phytium_dp.h"
+#include "px210_dp.h"
+
+static uint8_t px210_dp_source_lane_count[3] = {4, 4, 1};
+
+/* [reg][ling_rate 1.62->8.1] */
+static int vco_val[12][4] = {
+	{0x0509, 0x0509, 0x0509, 0x0509}, // CP_PADJ
+	{0x0f00, 0x0f00, 0x0f00, 0x0f00}, // CP_IADJ
+	{0x0F08, 0x0F08, 0x0F08, 0x0F08}, // FILT_PADJ
+	{0x0061, 0x006C, 0x006C, 0x0051}, // INTDIV
+	{0x3333, 0x0000, 0x0000, 0x0000}, // FRACDIVL
+	{0x0000, 0x0000, 0x0000, 0x0000}, // FRACDIVH
+	{0x0042, 0x0048, 0x0048, 0x0036}, // HIGH_THR
+	{0x0002, 0x0002, 0x0002, 0x0002}, // PDIAG_CTRL
+	{0x0c5e, 0x0c5e, 0x0c5e, 0x0c5e}, // VCOCAL_PLLCNT_START
+	{0x00c7, 0x00c7, 0x00c7, 0x00c7}, // LOCK_PEFCNT
+	{0x00c7, 0x00c7, 0x00c7, 0x00c7}, // LOCK_PLLCNT_START
+	{0x0005, 0x0005, 0x0005, 0x0005}, // LOCK_PLLCNT_THR
+};
+
+static int mgnfs_val[4][4][4] = // [link_rate][swing][emphasis]
+{
+	/* 1.62Gbps */
+	{
+		{0x0026, 0x001f, 0x0012, 0x0000},
+		{0x0013, 0x0013, 0x0000, 0x0000},
+		{0x0006, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+
+	/* 2.7Gbps */
+	{
+		{0x0026, 0x001f, 0x0012, 0x0000},
+		{0x0013, 0x0013, 0x0000, 0x0000},
+		{0x0006, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+
+	/* 5.4Gbps */
+	{
+		{0x0026, 0x0013, 0x005, 0x0000},
+		{0x0018, 0x006, 0x0000, 0x0000},
+		{0x000c, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+
+	/* 8.1Gbps */
+	{
+		{0x0026, 0x0013, 0x005, 0x0000},
+		{0x0013, 0x006, 0x0000, 0x0000},
+		{0x0006, 0x0000, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+};
+
+static int cpost_val[4][4][4] = // [link_rate][swing][emphasis]
+{
+	/* 1.62Gbps */
+	{
+		{0x0000, 0x0014, 0x0020, 0x002a},
+		{0x0000, 0x0010, 0x001f, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+
+	/* 2.7Gbps */
+	{
+		{0x0000, 0x0014, 0x0020, 0x002a},
+		{0x0000, 0x0010, 0x001f, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+
+	/* 5.4Gbps */
+	{
+		{0x0000, 0x0014, 0x0022, 0x002e},
+		{0x0000, 0x0013, 0x0020, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+
+	/* 8.1Gbps */
+	{
+		{0x0000, 0x0014, 0x0022, 0x002e},
+		{0x0000, 0x0013, 0x0020, 0x0000},
+		{0x0000, 0x0013, 0x0000, 0x0000},
+		{0x0000, 0x0000, 0x0000, 0x0000},
+	},
+};
+
+static int px210_dp_hw_set_phy_lane_and_rate(struct phytium_dp_device *phytium_dp,
+							uint8_t link_lane_count,
+							uint32_t link_rate)
+{
+	int port = phytium_dp->port%3;
+	int i = 0, data, tmp, tmp1, index = 0, mask;
+	int timeout = 500, ret = 0;
+
+	if (port == 0 || port == 1) {
+		/* set pma powerdown */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (A3_POWERDOWN3 << i*A3_POWERDOWN3_SHIFT);
+			mask |= (((1<<A3_POWERDOWN3_SHIFT) - 1) << (i*A3_POWERDOWN3_SHIFT));
+		}
+		if (port == 0) {
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA0_POWER);
+			tmp = (tmp & (~mask)) | data;
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PMA0_POWER, tmp);
+		} else {
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA1_POWER);
+			tmp = (tmp & (~mask)) | data;
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PMA1_POWER, tmp);
+		}
+
+		/* lane pll disable */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (PLL_EN << i*PLL_EN_SHIFT);
+			mask |= (((1<<PLL_EN_SHIFT) - 1) << (i*PLL_EN_SHIFT));
+		}
+		mask = (mask << (port*PLL_EN_SHIFT*4));
+		data = (data << (port*PLL_EN_SHIFT*4));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PLL_EN);
+		tmp = (tmp & (~mask));
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL_EN, tmp);
+
+		/* pma pll disable */
+		mask = (CONTROL_ENABLE << (port*CONTROL_ENABLE_SHIFT));
+		data = (CONTROL_ENABLE << (port*CONTROL_ENABLE_SHIFT));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA_CONTROL);
+		tmp = (tmp & (~mask));
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PMA_CONTROL, tmp);
+
+		/* read pma pll disable state */
+		mdelay(2);
+		phytium_phy_readl(phytium_dp, PX210_PHY0_PMA_CONTROL2);
+
+		/* config link rate */
+		switch (link_rate) {
+		case 810000:
+			tmp = PLL_LINK_RATE_810000;
+			tmp1 = HSCLK_LINK_RATE_810000;
+			index = 3;
+			break;
+		case 540000:
+			tmp = PLL_LINK_RATE_540000;
+			tmp1 = HSCLK_LINK_RATE_540000;
+			index = 2;
+			break;
+		case 270000:
+			tmp = PLL_LINK_RATE_270000;
+			tmp1 = HSCLK_LINK_RATE_270000;
+			index = 1;
+			break;
+		case 162000:
+			tmp = PLL_LINK_RATE_162000;
+			tmp1 = HSCLK_LINK_RATE_162000;
+			index = 0;
+			break;
+		default:
+			DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+			tmp = PLL_LINK_RATE_162000;
+			tmp1 = HSCLK_LINK_RATE_162000;
+			index = 0;
+			break;
+		}
+		if (port == 0) {
+			/* config analog pll for link0 */
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_CLK_SEL, tmp);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_HSCLK0_SEL, HSCLK_LINK_0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_HSCLK0_DIV, tmp1);
+
+			/* config digital pll for link0 */
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLLDRC0_CTRL, PLLDRC_LINK0);
+
+			/* common for all rate */
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_DSM_M0, PLL0_DSM_M0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_VCOCAL_START,
+					   PLL0_VCOCAL_START);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_VCOCAL_CTRL,
+					   PLL0_VCOCAL_CTRL);
+
+			/* different for all rate */
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_CP_PADJ,
+					   vco_val[0][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_CP_IADJ,
+					   vco_val[1][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_CP_FILT_PADJ,
+					   vco_val[2][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_INTDIV,
+					   vco_val[3][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_FRACDIVL,
+					   vco_val[4][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_FRACDIVH,
+					   vco_val[5][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_HIGH_THR,
+					   vco_val[6][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_PDIAG_CTRL,
+					   vco_val[7][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_VCOCAL_PLLCNT_START,
+					   vco_val[8][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_LOCK_PEFCNT,
+					   vco_val[9][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_LOCK_PLLCNT_START,
+					   vco_val[10][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_LOCK_PLLCNT_THR,
+					   vco_val[11][index]);
+
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_PSC_A0,
+					   PLL0_TX_PSC_A0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_PSC_A2,
+					   PLL0_TX_PSC_A2);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_PSC_A3,
+					   PLL0_TX_PSC_A3);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_PSC_A0,
+					   PLL0_RX_PSC_A0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_PSC_A2,
+					   PLL0_RX_PSC_A2);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_PSC_A3,
+					   PLL0_RX_PSC_A3);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_PSC_CAL,
+					   PLL0_RX_PSC_CAL);
+
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_XCVR_CTRL,
+					   PLL0_XCVR_CTRL);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_GCSM1_CTRL,
+					   PLL0_RX_GCSM1_CTRL);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_GCSM2_CTRL,
+					   PLL0_RX_GCSM2_CTRL);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_RX_PERGCSM_CTRL,
+					   PLL0_RX_PERGCSM_CTRL);
+		} else if (port == 1) {
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_CLK_SEL, tmp);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_HSCLK1_SEL, HSCLK_LINK_1);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_HSCLK1_DIV, tmp1);
+
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLLDRC1_CTRL, PLLDRC_LINK1);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_DSM_M0, PLL1_DSM_M0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_VCOCAL_START,
+					   PLL1_VCOCAL_START);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_VCOCAL_CTRL,
+					   PLL1_VCOCAL_CTRL);
+
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_CP_PADJ,
+					   vco_val[0][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_CP_IADJ,
+					   vco_val[1][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_CP_FILT_PADJ,
+					   vco_val[2][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_INTDIV,
+					   vco_val[3][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_FRACDIVL,
+					   vco_val[4][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_FRACDIVH,
+					   vco_val[5][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_HIGH_THR,
+					   vco_val[6][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_PDIAG_CTRL,
+					   vco_val[7][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_VCOCAL_PLLCNT_START,
+					   vco_val[8][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_LOCK_PEFCNT,
+					   vco_val[9][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_LOCK_PLLCNT_START,
+					   vco_val[10][index]);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_LOCK_PLLCNT_THR,
+					   vco_val[11][index]);
+
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_PSC_A0,
+					   PLL1_TX_PSC_A0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_PSC_A2,
+					   PLL1_TX_PSC_A2);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_PSC_A3,
+					   PLL1_TX_PSC_A3);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_PSC_A0,
+					   PLL1_RX_PSC_A0);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_PSC_A2,
+					   PLL1_RX_PSC_A2);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_PSC_A3,
+					   PLL1_RX_PSC_A3);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_PSC_CAL,
+					   PLL1_RX_PSC_CAL);
+
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_XCVR_CTRL,
+					   PLL1_XCVR_CTRL);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_GCSM1_CTRL,
+					   PLL1_RX_GCSM1_CTRL);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_GCSM2_CTRL,
+					   PLL1_RX_GCSM2_CTRL);
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_RX_PERGCSM_CTRL,
+					   PLL1_RX_PERGCSM_CTRL);
+		}
+
+		/* pma pll enable */
+		data = 0;
+		mask = 0;
+		mask = (CONTROL_ENABLE << (port*CONTROL_ENABLE_SHIFT));
+		data = (CONTROL_ENABLE << (port*CONTROL_ENABLE_SHIFT));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA_CONTROL);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PMA_CONTROL, tmp);
+
+		/* lane pll enable */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (PLL_EN << i*PLL_EN_SHIFT);
+			mask |= (((1<<PLL_EN_SHIFT) - 1) << (i*PLL_EN_SHIFT));
+		}
+		mask = (mask << (port*PLL_EN_SHIFT*4));
+		data = (data << (port*PLL_EN_SHIFT*4));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PLL_EN);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL_EN, tmp);
+
+		/* set pma power active */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (A0_ACTIVE << i*A0_ACTIVE_SHIFT);
+			mask |= (((1<<A0_ACTIVE_SHIFT) - 1) << (i*A0_ACTIVE_SHIFT));
+		}
+		if (port == 0) {
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA0_POWER);
+			tmp = (tmp & (~mask)) | data;
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PMA0_POWER, tmp);
+			mask = PLL0_LOCK_DONE;
+		} else {
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA1_POWER);
+			tmp = (tmp & (~mask)) | data;
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PMA1_POWER, tmp);
+			mask = PLL1_LOCK_DONE;
+		}
+
+		do {
+			mdelay(1);
+			timeout--;
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA_CONTROL2);
+		} while ((!(tmp & mask)) && timeout);
+
+		if (timeout == 0) {
+			DRM_ERROR("dp(%d) phy pll lock failed\n", port);
+			ret = -1;
+		}
+		udelay(1);
+	} else {
+		/* set pma powerdown */
+		mask = PHY1_A3_POWERDOWN3_MASK << PHY1_A3_POWERDOWN3_SHIFT;
+		data = PHY1_A3_POWERDOWN3 << PHY1_A3_POWERDOWN3_SHIFT;
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_MISC);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_MISC, tmp);
+
+		/* lane pll disable */
+		mask = PHY1_PLL_EN_MASK << PHY1_PLL_EN_SHIFT;
+		data = PHY1_PLL_EN << PHY1_PLL_EN_SHIFT;
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_MISC);
+		tmp = (tmp & (~mask));
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_MISC, tmp);
+
+		/* pma pll disable */
+		mask = (CONTROL_ENABLE << 0*CONTROL_ENABLE_SHIFT); // link config
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_CONTROL);
+		tmp = (tmp & (~mask));
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_CONTROL, tmp);
+
+		/* read pma pll disable state */
+		mdelay(2);
+		phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_CONTROL2);
+
+		/* config link rate */
+		switch (link_rate) {
+		case 810000:
+			tmp = PLL_LINK_RATE_810000;
+			tmp1 = HSCLK_LINK_RATE_810000;
+			index = 3;
+			break;
+		case 540000:
+			tmp = PLL_LINK_RATE_540000;
+			tmp1 = HSCLK_LINK_RATE_540000;
+			index = 2;
+			break;
+		case 270000:
+			tmp = PLL_LINK_RATE_270000;
+			tmp1 = HSCLK_LINK_RATE_270000;
+			index = 1;
+			break;
+		case 162000:
+			tmp = PLL_LINK_RATE_162000;
+			tmp1 = HSCLK_LINK_RATE_162000;
+			index = 0;
+			break;
+		default:
+			DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+			tmp = PLL_LINK_RATE_162000;
+			tmp1 = HSCLK_LINK_RATE_162000;
+			index = 0;
+			break;
+		}
+
+		/* config analog pll for link0 */
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL_CLK_SEL, tmp);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_HSCLK_SEL, HSCLK_LINK_0);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_HSCLK_DIV, tmp1);
+
+		/* config digital pll for link0 */
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLLDRC_CTRL, PLLDRC_LINK0);
+
+		/* common for all rate */
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_DSM_M0, PLL0_DSM_M0);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_VCOCAL_START, PLL0_VCOCAL_START);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_VCOCAL_CTRL, PLL0_VCOCAL_CTRL);
+
+		/* different for all rate */
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_CP_PADJ, vco_val[0][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_CP_IADJ, vco_val[1][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_CP_FILT_PADJ, vco_val[2][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_INTDIV, vco_val[3][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_FRACDIVL, vco_val[4][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_FRACDIVH, vco_val[5][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_HIGH_THR, vco_val[6][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_PDIAG_CTRL, vco_val[7][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_VCOCAL_PLLCNT_START,
+				   vco_val[8][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_LOCK_PEFCNT, vco_val[9][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_LOCK_PLLCNT_START,
+				   vco_val[10][index]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_LOCK_PLLCNT_THR,
+				   vco_val[11][index]);
+
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_PSC_A0, PLL0_TX_PSC_A0);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_PSC_A2, PLL0_TX_PSC_A2);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_PSC_A3, PLL0_TX_PSC_A3);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_PSC_A0, PLL0_RX_PSC_A0);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_PSC_A2, PLL0_RX_PSC_A2);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_PSC_A3, PLL0_RX_PSC_A3);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_PSC_CAL, PLL0_RX_PSC_CAL);
+
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_XCVR_CTRL, PLL0_XCVR_CTRL);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_GCSM1_CTRL,
+				   PLL0_RX_GCSM1_CTRL);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_GCSM2_CTRL,
+				   PLL0_RX_GCSM2_CTRL);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_RX_PERGCSM_CTRL,
+				   PLL0_RX_PERGCSM_CTRL);
+
+		/* pma pll enable */
+		data = 0;
+		mask = 0;
+		mask = (CONTROL_ENABLE << (0*CONTROL_ENABLE_SHIFT));
+		data = (CONTROL_ENABLE << (0*CONTROL_ENABLE_SHIFT));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_CONTROL);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_CONTROL, tmp);
+
+		/* lane pll enable */
+		mask = PHY1_PLL_EN_MASK << PHY1_PLL_EN_SHIFT;
+		data = PHY1_PLL_EN << PHY1_PLL_EN_SHIFT;
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_MISC);
+		tmp = ((tmp & (~mask)) | data);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_MISC, tmp);
+
+		/* set pma power active */
+		mask = PHY1_A0_ACTIVE_MASK << PHY1_A0_ACTIVE_SHIFT;
+		data = PHY1_A0_ACTIVE << PHY1_A0_ACTIVE_SHIFT;
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_MISC);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_MISC, tmp);
+
+		mask = PLL0_LOCK_DONE;
+		do {
+			mdelay(1);
+			timeout--;
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_CONTROL2);
+		} while ((!(tmp & mask)) && timeout);
+
+		if (timeout == 0) {
+			DRM_ERROR("dp(%d) phy pll lock failed\n", port);
+			ret = -1;
+		}
+		udelay(1);
+	}
+
+	return ret;
+}
+
+static void px210_dp_hw_set_phy_lane_setting(struct phytium_dp_device *phytium_dp,
+						      uint32_t link_rate,
+						      uint8_t train_set)
+{
+	int port = phytium_dp->port%3;
+	int voltage_swing = 0;
+	int pre_emphasis = 0, link_rate_index = 0;
+
+	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+	default:
+		voltage_swing = 0;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+		voltage_swing = 1;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+		voltage_swing = 2;
+		break;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+		voltage_swing = 3;
+		break;
+	}
+	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
+	case DP_TRAIN_PRE_EMPH_LEVEL_0:
+	default:
+		pre_emphasis = 0;
+		break;
+	case DP_TRAIN_PRE_EMPH_LEVEL_1:
+		pre_emphasis = 1;
+		break;
+	case DP_TRAIN_PRE_EMPH_LEVEL_2:
+		pre_emphasis = 2;
+		break;
+	case DP_TRAIN_PRE_EMPH_LEVEL_3:
+		pre_emphasis = 3;
+		break;
+	}
+
+	switch (link_rate) {
+	case 810000:
+		link_rate_index = 3;
+		break;
+	case 540000:
+		link_rate_index = 2;
+		break;
+	case 270000:
+		link_rate_index = 1;
+		break;
+	case 162000:
+		link_rate_index = 0;
+		break;
+	default:
+		DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+		link_rate_index = 2;
+		break;
+	}
+
+	if (port == 0) {
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_DIAG_ACYA, LOCK);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_TXCC_CTRL, TX_TXCC_CTRL);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_DRV, TX_DRV);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_MGNFS,
+				mgnfs_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_CPOST,
+				cpost_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL0_TX_DIAG_ACYA, UNLOCK);
+
+	} else if (port == 1) {
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_DIAG_ACYA, LOCK);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_TXCC_CTRL, TX_TXCC_CTRL);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_DRV, TX_DRV);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_MGNFS,
+				mgnfs_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_CPOST,
+				cpost_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_CPOST1,
+				cpost_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL1_TX_DIAG_ACYA, UNLOCK);
+	} else {
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_DIAG_ACYA, LOCK);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_TXCC_CTRL, TX_TXCC_CTRL);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_DRV, TX_DRV);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_MGNFS,
+				mgnfs_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_CPOST,
+				cpost_val[link_rate_index][voltage_swing][pre_emphasis]);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL0_TX_DIAG_ACYA, UNLOCK);
+	}
+}
+
+static int px210_dp_hw_init_phy(struct phytium_dp_device *phytium_dp)
+{
+	int port = phytium_dp->port;
+	int i = 0, data, tmp, mask;
+	int timeout = 500, ret = 0;
+
+	if (port == 0 || port == 1) {
+		phytium_phy_writel(phytium_dp, PX210_PHY0_APB_RESET, APB_RESET);
+
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PIPE_RESET, RESET);
+
+		/* config lane to dp mode */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (LANE_BIT << i*LANE_BIT_SHIFT);
+			mask |= (((1<<LANE_BIT_SHIFT) - 1) << (i*LANE_BIT_SHIFT));
+		}
+		mask = (mask << (port*LANE_BIT_SHIFT*4));
+		data = (data << (port*LANE_BIT_SHIFT*4));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_MODE);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY0_MODE, tmp);
+
+		/* config lane master or slave */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (LANE_MASTER << i*LANE_MASTER_SHIFT);
+			mask |= (((1<<LANE_MASTER_SHIFT) - 1) << (i*LANE_MASTER_SHIFT));
+		}
+		mask = (mask << (port*LANE_MASTER_SHIFT*4));
+		data = (data << (port*LANE_MASTER_SHIFT*4));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_LINK_CFG);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY0_LINK_CFG, tmp);
+
+		/* pll clock enable */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (PLL_EN << i*PLL_EN_SHIFT);
+			mask |= (((1<<PLL_EN_SHIFT) - 1) << (i*PLL_EN_SHIFT));
+		}
+		mask = (mask << (port*PLL_EN_SHIFT*4));
+		data = (data << (port*PLL_EN_SHIFT*4));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PLL_EN);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PLL_EN, tmp);
+
+		/* config input 20 bit */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (BIT_20 << i*BIT_20_SHIFT);
+			mask |= (((1<<BIT_20_SHIFT) - 1) << (i*BIT_20_SHIFT));
+		}
+		mask = (mask << (port*BIT_20_SHIFT*4));
+		data = (data << (port*BIT_20_SHIFT*4));
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA_WIDTH);
+		tmp = (tmp & (~mask)) | data;
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PMA_WIDTH, tmp);
+
+		/* config lane active power state */
+		data = 0;
+		mask = 0;
+		for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+			data |= (A0_ACTIVE << i*A0_ACTIVE_SHIFT);
+			mask |= (((1<<A0_ACTIVE_SHIFT) - 1) << (i*A0_ACTIVE_SHIFT));
+		}
+		if (port == 0) {
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA0_POWER);
+			tmp = (tmp & (~mask)) | data;
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PMA0_POWER, tmp);
+		} else {
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA1_POWER);
+			tmp = (tmp & (~mask)) | data;
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PMA1_POWER, tmp);
+		}
+
+		/* link reset */
+		mask = (LINK_RESET_MASK << (0*LINTK_RESET_SHIFT)) |
+			(LINK_RESET_MASK << (1*LINTK_RESET_SHIFT));
+		data = (LINK_RESET << (0*LINTK_RESET_SHIFT)) |
+			(LINK_RESET << (1*LINTK_RESET_SHIFT));
+		tmp = (data & mask);
+		phytium_phy_writel(phytium_dp, PX210_PHY0_LINK_RESET, tmp);
+
+		/* config double link */
+		if (port == 0)
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL_CFG, SINGLE_LINK);
+		else if (port == 1)
+			phytium_phy_writel(phytium_dp, PX210_PHY0_PLL_CFG, DOUBLE_LINK);
+
+		/* pipe reset */
+		phytium_phy_writel(phytium_dp, PX210_PHY0_PIPE_RESET, RESET_DEASSERT);
+
+		if (port ==  0)
+			mask = PLL0_LOCK_DONE;
+		else
+			mask = PLL1_LOCK_DONE;
+
+		do {
+			mdelay(1);
+			timeout--;
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY0_PMA_CONTROL2);
+		} while ((!(tmp & mask)) && timeout);
+
+		if (timeout == 0) {
+			DRM_ERROR("reset dp(%d) phy failed\n", port);
+			ret = -1;
+		}
+		udelay(1);
+	} else {
+		/* APB reset */
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_APB_RESET);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_APB_RESET, tmp & (~PHY1_APB_RESET));
+		phytium_phy_writel(phytium_dp, PX210_PHY1_APB_RESET, tmp | PHY1_APB_RESET);
+
+		/* pipe reset */
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PIPE_RESET);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PIPE_RESET,
+				   tmp & (~PHY1_PIPE_RESET_DEASSERT));
+
+		/* config MODE/SEL to dp */
+		mask = PHY1_DP_LANE_BIT << PHY1_DP_LANE_BIT_SHIFT;
+		data = PHY1_DP_LANE_BIT << PHY1_DP_LANE_BIT_SHIFT;
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_SEL);
+		tmp = (tmp & (~mask));
+		phytium_phy_writel(phytium_dp, PX210_PHY1_SEL, tmp);
+
+		/* config pll clock enable,  input 20 bit, lane active power state */
+		tmp = (PHY1_PLL_EN << PHY1_PLL_EN_SHIFT) | (PHY1_BIT_20 << PHY1_BIT_20_SHIFT)
+			| (PHY1_A0_ACTIVE << PHY1_A0_ACTIVE_SHIFT);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PMA_MISC, tmp);
+
+		/* config single link */
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PLL_CFG, SINGLE_LINK);
+
+		/* pipe reset */
+		tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PIPE_RESET);
+		phytium_phy_writel(phytium_dp, PX210_PHY1_PIPE_RESET,
+				   tmp | PHY1_PIPE_RESET_DEASSERT);
+
+		mask = PLL0_LOCK_DONE;
+		do {
+			mdelay(1);
+			timeout--;
+			tmp = phytium_phy_readl(phytium_dp, PX210_PHY1_PMA_CONTROL2);
+		} while ((!(tmp & mask)) && timeout);
+
+		if (timeout == 0) {
+			DRM_ERROR("reset dp(%d) phy failed\n", port);
+			ret = -1;
+		}
+		udelay(1);
+	}
+
+	mdelay(10);
+
+	return ret;
+}
+
+static void px210_dp_hw_poweron_panel(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dcreq_reg_base[port];
+	int ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | PANEL_POWER_ENABLE,
+			   group_offset, PX210_DCREQ_CMD_REGISTER);
+	ret = phytium_wait_cmd_done(priv, group_offset + PX210_DCREQ_CMD_REGISTER,
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to poweron panel\n", __func__);
+}
+
+static void px210_dp_hw_poweroff_panel(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dcreq_reg_base[port];
+	int ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | PANEL_POWER_DISABLE,
+			   group_offset, PX210_DCREQ_CMD_REGISTER);
+	ret = phytium_wait_cmd_done(priv, group_offset + PX210_DCREQ_CMD_REGISTER,
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to poweroff panel\n", __func__);
+}
+
+static void px210_dp_hw_enable_backlight(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, ret = 0;
+	uint32_t group_offset = priv->dcreq_reg_base[port];
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | BACKLIGHT_ENABLE,
+			   group_offset, PX210_DCREQ_CMD_REGISTER);
+	ret = phytium_wait_cmd_done(priv, group_offset + PX210_DCREQ_CMD_REGISTER,
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to enable backlight\n", __func__);
+}
+
+static void px210_dp_hw_disable_backlight(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dcreq_reg_base[port];
+	int ret = 0;
+
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | BACKLIGHT_DISABLE,
+			   group_offset, PX210_DCREQ_CMD_REGISTER);
+	ret = phytium_wait_cmd_done(priv, group_offset + PX210_DCREQ_CMD_REGISTER,
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to disable backlight\n", __func__);
+}
+
+static uint32_t px210_dp_hw_get_backlight(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int config;
+	uint32_t group_offset = priv->address_transform_base;
+
+	config = phytium_readl_reg(priv, group_offset, PX210_DC_ADDRESS_TRANSFORM_BACKLIGHT_VALUE);
+	return ((config >> BACKLIGHT_VALUE_SHIFT) & BACKLIGHT_VALUE_MASK);
+}
+
+static int px210_dp_hw_set_backlight(struct phytium_dp_device *phytium_dp, uint32_t level)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	uint32_t group_offset = priv->dcreq_reg_base[port];
+	int config = 0;
+	int ret = 0;
+
+	if (level > PX210_DP_BACKLIGHT_MAX) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	config = FLAG_REQUEST | CMD_BACKLIGHT | ((level & BACKLIGHT_MASK) << BACKLIGHT_SHIFT);
+	phytium_writel_reg(priv, config, group_offset, PX210_DCREQ_CMD_REGISTER);
+	ret = phytium_wait_cmd_done(priv, group_offset + PX210_DCREQ_CMD_REGISTER,
+				    FLAG_REQUEST, FLAG_REPLY);
+	if (ret < 0)
+		DRM_ERROR("%s: failed to set backlight\n", __func__);
+
+out:
+	return ret;
+}
+
+bool px210_dp_hw_spread_is_enable(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port, config;
+	uint32_t group_offset = priv->address_transform_base;
+
+	config = phytium_readl_reg(priv, group_offset, PX210_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS);
+
+	return ((config & DP_SPREAD_ENABLE(port)) ? true:false);
+}
+
+int px210_dp_hw_reset(struct phytium_dp_device *phytium_dp)
+{
+	struct drm_device *dev =  phytium_dp->dev;
+	struct phytium_display_private *priv = dev->dev_private;
+	int port = phytium_dp->port;
+	int timeout = 100, config, ret = 0;
+	uint32_t group_offset = priv->address_transform_base;
+	uint32_t group_offset_dp = priv->dp_reg_base[port];
+
+	config = phytium_readl_reg(priv, group_offset, PX210_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS);
+	config &= (~DC_DP_RESET_STATUS(port));
+
+	phytium_writel_reg(priv, config, group_offset, PX210_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS);
+	phytium_writel_reg(priv, FLAG_REQUEST | CMD_DC_DP_RESET,
+			   priv->dcreq_reg_base[port], PX210_DCREQ_CMD_REGISTER);
+	do {
+		mdelay(10);
+		timeout--;
+		config = phytium_readl_reg(priv, group_offset,
+					   PX210_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS);
+		if (config & DC_DP_RESET_STATUS(port))
+			break;
+	} while (timeout);
+	if (timeout == 0) {
+		DRM_ERROR("reset dc/dp pipe(%d) failed\n", port);
+		ret = -1;
+	}
+
+	phytium_writel_reg(priv, AUX_CLK_DIVIDER, group_offset_dp, PHYTIUM_DP_AUX_CLK_DIVIDER);
+
+	return ret;
+}
+
+uint8_t px210_dp_hw_get_source_lane_count(struct phytium_dp_device *phytium_dp)
+{
+	return px210_dp_source_lane_count[phytium_dp->port];
+}
+
+static struct phytium_dp_func px210_dp_funcs = {
+	.dp_hw_get_source_lane_count = px210_dp_hw_get_source_lane_count,
+	.dp_hw_reset = px210_dp_hw_reset,
+	.dp_hw_spread_is_enable = px210_dp_hw_spread_is_enable,
+	.dp_hw_set_backlight = px210_dp_hw_set_backlight,
+	.dp_hw_get_backlight = px210_dp_hw_get_backlight,
+	.dp_hw_disable_backlight = px210_dp_hw_disable_backlight,
+	.dp_hw_enable_backlight = px210_dp_hw_enable_backlight,
+	.dp_hw_poweroff_panel = px210_dp_hw_poweroff_panel,
+	.dp_hw_poweron_panel = px210_dp_hw_poweron_panel,
+	.dp_hw_init_phy = px210_dp_hw_init_phy,
+	.dp_hw_set_phy_lane_setting = px210_dp_hw_set_phy_lane_setting,
+	.dp_hw_set_phy_lane_and_rate = px210_dp_hw_set_phy_lane_and_rate,
+};
+
+void px210_dp_func_register(struct phytium_dp_device *phytium_dp)
+{
+	phytium_dp->funcs = &px210_dp_funcs;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dp.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dp.h
new file mode 100644
index 00000000000000..4ad65397f1aa23
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_dp.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PX210_DP_H__
+#define __PX210_DP_H__
+
+#define PX210_DP_BACKLIGHT_MAX				100
+
+void px210_dp_func_register(struct phytium_dp_device *phytium_dp);
+#endif /* __PX210_DP_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_reg.h b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_reg.h
new file mode 100644
index 00000000000000..5556b3ee5c1db8
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/gpu/drm/phytium/px210_reg.h
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium display drm driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PX210_REG_H__
+#define __PX210_REG_H__
+
+#include "phytium_reg.h"
+
+/******************************dc register start******************************************/
+#define PX210_DC_CLOCK_CONTROL				0x0000
+	#define SOFT_RESET					(1<<12)
+#define PX210_DC_CLOCK_IDLE				0x0004
+	#define IS_IDLE						(1<<16)
+/******************************dc register end********************************************/
+
+/******************************dcreq register start**************************************/
+#define PX210_DCREQ_PLANE0_ADDR_START			0x00
+#define PX210_DCREQ_PLANE0_ADDR_END			0x04
+#define PX210_DCREQ_PLANE1_ADDR_START			0x08
+#define PX210_DCREQ_PLANE1_ADDR_END			0x0c
+#define	PX210_DCREQ_PLANE0_CONFIG			0x10
+	#define DCREQ_NO_LOSSY					(0 << 0)
+	#define DCREQ_LOSSY					(1 << 0)
+	#define DCREQ_TILE_TYPE_MASK				(0x3 << 1)
+	#define DCREQ_TILE_TYPE_MODE0				(0x1 << 1)
+	#define DCREQ_TILE_TYPE_MODE3				(0x2 << 1)
+	#define	DCREQ_COLOURFORMAT_MASK				(0x7f << 8)
+	#define DCREQ_COLOURFORMAT_RGB565			(0x5 << 8)
+	#define DCREQ_COLOURFORMAT_ARGB1555			(0x4 << 8)
+	#define DCREQ_COLOURFORMAT_ARGB4444			(0x02 << 8)
+	#define	DCREQ_COLOURFORMAT_BGRA8888			(0x29 << 8)
+	#define DCREQ_COLOURFORMAT_ARGB2101010			(0xe << 8)
+	#define DCREQ_COLOURFORMAT_YUYV				(0x59 << 8)
+	#define DCREQ_COLOURFORMAT_UYVY				(0x5b << 8)
+	#define	DCREQ_ARGBSWIZZLE_MASK				(0xf << 4)
+	#define	DCREQ_ARGBSWIZZLE_ARGB				(0X0 << 4)
+	#define	DCREQ_ARGBSWIZZLE_BGRA				(0XC << 4)
+	#define	DCREQ_MODE_MASK					(1 << 16)
+	#define DCREQ_MODE_LINEAR				(0 << 16)
+	#define DCREQ_MODE_TILE					(1 << 16)
+#define	PX210_DCREQ_PLANE1_CONFIG(pipe)			0x14
+#define PX210_DCREQ_PLANE0_CLEAR_COLOR_L			0x18
+#define PX210_DCREQ_PLANE0_CLEAR_COLOR_H			0x1C
+#define PX210_DCREQ_PLANE1_CLEAR_COLOR_L			0x20
+#define PX210_DCREQ_PLANE1_CLEAR_COLOR_H			0x24
+#define PX210_DCREQ_CMD_REGISTER				0x38
+	#define FLAG_REPLY					(1<<31)
+	#define FLAG_REQUEST					(1<<30)
+	#define CMD_PIXEL_CLOCK					(0x0 << 28)
+	#define CMD_BACKLIGHT					(0x1 << 28)
+	#define CMD_DC_DP_RESET					(0x3 << 28)
+	#define BACKLIGHT_SHIFT					21
+	#define BACKLIGHT_MASK					0x7f
+	#define BACKLIGHT_MAX					100
+	#define BACKLIGHT_ENABLE				(101 << BACKLIGHT_SHIFT)
+	#define BACKLIGHT_DISABLE				(102 << BACKLIGHT_SHIFT)
+	#define PANEL_POWER_ENABLE				(103 << BACKLIGHT_SHIFT)
+	#define PANEL_POWER_DISABLE				(104 << BACKLIGHT_SHIFT)
+	#define PIXEL_CLOCK_MASK				(0x1fffff)
+#define PX210_DCREQ_FBCD_CLOCK_CONFIG			0x3c
+#define PX210_DCREQ_PIX_DMA_PREFIX			0x50
+	#define PREFIX_MASK					0xff
+	#define PREFIX_SHIFT					32
+#define PX210_DCREQ_FRAME_START				0x54
+#define PX210_DCREQ_FILTER_CONFIG			0x58
+#define PX210_DCREQ_CONTROL				0x5C
+	#define DC_REQ_ENABLE					(1<<0)
+#define PX210_DCREQ_MSI_CLEAR				0x60
+	#define MSI_CLEAR					0x0
+#define	PX210_DCREQ_RESET				0x68
+	#define DCREQ_RESET					(0x3 << 0)
+	#define DCREQ_RESET_MASK				0x3
+#define PX210_DCREQ_PLAN					0x94
+	#define DCREQ_PLAN_A					0x0
+	#define DCREQ_PLAN_B					0X5
+/******************************dcreq register end**************************************/
+
+/******************************address transform register start**************************/
+#define PX210_GPU_ADDRESS_TRANSFORM_SRC_ADDR		0x0
+#define PX210_GPU_ADDRESS_TRANSFORM_SIZE			0x4
+#define PX210_GPU_ADDRESS_TRANSFORM_DST_ADDR		0x8
+
+#define PX210_DC_ADDRESS_TRANSFORM_SRC_ADDR		0x24
+	#define SRC_ADDR_OFFSET					22
+	#define SRC_ADDR_MASK					0xffffffffff
+#define PX210_DC_ADDRESS_TRANSFORM_SIZE			0x28
+	#define ADDRESS_TRANSFORM_ENABLE			(0x1 << 31)
+	#define SIZE_OFFSET					22
+#define PX210_DC_ADDRESS_TRANSFORM_DST_ADDR		0x2c
+	#define DST_ADDR_OFFSET					22
+#define PX210_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS	0x48
+	#define DC_DP_RESET_STATUS(pipe)			(1 << pipe)
+	#define DP_SPREAD_ENABLE(pipe)				(0x8 << pipe)
+#define PX210_DC_ADDRESS_TRANSFORM_BACKLIGHT_VALUE	0x4c
+	#define BACKLIGHT_VALUE_MASK				(0x7f)
+	#define BACKLIGHT_VALUE_SHIFT				16
+/******************************address transform register end**************************/
+
+/******************************phy register start******************************************/
+/* self define */
+#define PX210_PHY0_PIPE_RESET					0x40104
+	#define RESET						0x0
+	#define RESET_DEASSERT					0x1
+#define PX210_PHY1_PIPE_RESET				0x100100
+	#define PHY1_PIPE_RESET					0x0
+	#define PHY1_PIPE_RESET_DEASSERT			0x4
+
+#define PX210_PHY1_EN_REFCLK				0x100070
+
+#define	PX210_PHY0_MODE					0x40088
+	#define LANE_BIT					(0x3)
+	#define LANE_BIT_SHIFT					0x2
+#define	PX210_PHY1_SEL					0x100004
+	#define PHY1_DP_LANE_BIT				0x1
+	#define PHY1_DP_LANE_BIT_SHIFT				2
+
+#define	PX210_PHY0_LINK_CFG				0x40044
+	#define LANE_MASTER					0x1
+	#define LANE_MASTER_SHIFT				1
+
+#define PX210_PHY0_PLL_EN				0x40010
+	#define PLL_EN						0x1
+	#define PLL_EN_SHIFT					1
+#define PX210_PHY0_PMA_WIDTH				0x40020
+	#define	BIT_20						0x5
+	#define	BIT_20_SHIFT					4
+
+#define PX210_PHY0_PMA0_POWER				0x40014
+#define PX210_PHY0_PMA1_POWER				0x40018
+	#define	A0_ACTIVE					0x1
+	#define	A0_ACTIVE_SHIFT					8
+	#define	A3_POWERDOWN3					0x8
+	#define	A3_POWERDOWN3_SHIFT				8
+
+#define PX210_PHY1_PMA_MISC				0x1000a0
+	#define PHY1_PLL_EN					0x1
+	#define PHY1_PLL_EN_MASK				1
+	#define PHY1_PLL_EN_SHIFT				8
+	#define PHY1_BIT_20					0x5
+	#define PHY1_BIT_20_SHIFT				9
+	#define PHY1_A0_ACTIVE					0x1
+	#define PHY1_A0_ACTIVE_SHIFT				2
+	#define PHY1_A0_ACTIVE_MASK				0x3f
+	#define PHY1_A3_POWERDOWN3				0x8
+	#define PHY1_A3_POWERDOWN3_MASK				0x3f
+	#define PHY1_A3_POWERDOWN3_SHIFT			2
+
+#define PX210_PHY0_LINK_RESET				0x40108
+	#define LINK_RESET					0x1
+	#define LINK_RESET_MASK					0x1
+	#define LINTK_RESET_SHIFT				0x1
+
+#define PX210_PHY0_APB_RESET				0x40100
+	#define	APB_RESET					0x1
+#define PX210_PHY1_APB_RESET				0x100104
+	#define PHY1_APB_RESET					0x4
+
+/* phy origin register */
+#define PX210_PHY0_PLL_CFG				0x30038
+#define PX210_PHY1_PLL_CFG				0xb0038
+	#define SINGLE_LINK					0x0
+	#define DOUBLE_LINK					0x2
+
+#define PX210_PHY0_PMA_CONTROL				0x3800c
+#define PX210_PHY1_PMA_CONTROL				0xb800c
+	#define CONTROL_ENABLE					0x1
+	#define CONTROL_ENABLE_MASK				0x1
+	#define CONTROL_ENABLE_SHIFT				0x1
+
+#define PX210_PHY0_PMA_CONTROL2				0x38004
+#define PX210_PHY1_PMA_CONTROL2				0xb8004
+	#define PLL0_LOCK_DONE					(0x1 << 6)
+	#define PLL1_LOCK_DONE					(0x1 << 7)
+
+#define PX210_PHY0_PLL0_CLK_SEL				0X684
+#define PX210_PHY0_PLL1_CLK_SEL				0x704
+#define PX210_PHY1_PLL_CLK_SEL				0X80684
+	#define PLL_LINK_RATE_162000				0xf01
+	#define PLL_LINK_RATE_270000				0x701
+	#define PLL_LINK_RATE_540000				0x301
+	#define PLL_LINK_RATE_810000				0x200
+
+#define PX210_PHY0_HSCLK0_SEL				0x18398
+#define PX210_PHY0_HSCLK1_SEL				0x1a398
+#define PX210_PHY1_HSCLK_SEL				0x90398
+	#define HSCLK_LINK_0					0x0
+	#define HSCLK_LINK_1					0x1
+
+#define PX210_PHY0_HSCLK0_DIV				0x1839c
+#define PX210_PHY0_HSCLK1_DIV				0x1a39c
+#define PX210_PHY1_HSCLK_DIV				0x9039c
+	#define HSCLK_LINK_RATE_162000				0x2
+	#define HSCLK_LINK_RATE_270000				0x1
+	#define HSCLK_LINK_RATE_540000				0x0
+	#define HSCLK_LINK_RATE_810000				0x0
+
+#define PX210_PHY0_PLLDRC0_CTRL				0x18394
+#define PX210_PHY0_PLLDRC1_CTRL				0x1a394
+#define PX210_PHY1_PLLDRC_CTRL				0x90394
+	#define PLLDRC_LINK0					0x1
+	#define PLLDRC_LINK1					0x9
+
+#define PX210_PHY0_PLL0_DSM_M0				0x250
+#define PX210_PHY1_PLL0_DSM_M0				0x80250
+	#define PLL0_DSM_M0					0x4
+#define PX210_PHY0_PLL0_VCOCAL_START			0x218
+#define PX210_PHY1_PLL0_VCOCAL_START			0x80218
+	#define PLL0_VCOCAL_START				0xc5e
+#define PX210_PHY0_PLL0_VCOCAL_CTRL			0x208
+#define PX210_PHY1_PLL0_VCOCAL_CTRL			0x80208
+	#define PLL0_VCOCAL_CTRL				0x3
+
+#define PX210_PHY0_PLL1_DSM_M0				0x350
+	#define PLL1_DSM_M0					0x4
+#define PX210_PHY0_PLL1_VCOCAL_START			0x318
+	#define PLL1_VCOCAL_START				0xc5e
+#define PX210_PHY0_PLL1_VCOCAL_CTRL			0x308
+	#define PLL1_VCOCAL_CTRL				0x3
+
+#define PX210_PHY0_PLL0_CP_PADJ				0x690
+#define PX210_PHY0_PLL0_CP_IADJ				0x694
+#define PX210_PHY0_PLL0_CP_FILT_PADJ			0x698
+#define PX210_PHY0_PLL0_INTDIV				0x240
+#define PX210_PHY0_PLL0_FRACDIVL				0x244
+#define PX210_PHY0_PLL0_FRACDIVH				0x248
+#define PX210_PHY0_PLL0_HIGH_THR				0x24c
+#define PX210_PHY0_PLL0_PDIAG_CTRL			0x680
+#define PX210_PHY0_PLL0_VCOCAL_PLLCNT_START		0x220
+#define PX210_PHY0_PLL0_LOCK_PEFCNT			0x270
+#define PX210_PHY0_PLL0_LOCK_PLLCNT_START		0x278
+#define PX210_PHY0_PLL0_LOCK_PLLCNT_THR			0x27c
+
+#define PX210_PHY0_PLL1_CP_PADJ				0x710
+#define PX210_PHY0_PLL1_CP_IADJ				0x714
+#define PX210_PHY0_PLL1_CP_FILT_PADJ			0x718
+#define PX210_PHY0_PLL1_INTDIV				0x340
+#define PX210_PHY0_PLL1_FRACDIVL				0x344
+#define PX210_PHY0_PLL1_FRACDIVH				0x348
+#define PX210_PHY0_PLL1_HIGH_THR				0x34c
+#define PX210_PHY0_PLL1_PDIAG_CTRL			0x700
+#define PX210_PHY0_PLL1_VCOCAL_PLLCNT_START		0x320
+#define PX210_PHY0_PLL1_LOCK_PEFCNT			0x370
+#define PX210_PHY0_PLL1_LOCK_PLLCNT_START		0x378
+#define PX210_PHY0_PLL1_LOCK_PLLCNT_THR			0x37c
+
+#define PX210_PHY1_PLL0_CP_PADJ				0x80690
+#define PX210_PHY1_PLL0_CP_IADJ				0x80694
+#define PX210_PHY1_PLL0_CP_FILT_PADJ			0x80698
+#define PX210_PHY1_PLL0_INTDIV				0x80240
+#define PX210_PHY1_PLL0_FRACDIVL				0x80244
+#define PX210_PHY1_PLL0_FRACDIVH				0x80248
+#define PX210_PHY1_PLL0_HIGH_THR				0x8024c
+#define PX210_PHY1_PLL0_PDIAG_CTRL			0x80680
+#define PX210_PHY1_PLL0_VCOCAL_PLLCNT_START		0x80220
+#define PX210_PHY1_PLL0_LOCK_PEFCNT			0x80270
+#define PX210_PHY1_PLL0_LOCK_PLLCNT_START		0x80278
+#define PX210_PHY1_PLL0_LOCK_PLLCNT_THR			0x8027c
+
+#define	PX210_PHY0_PLL0_TX_PSC_A0			0x18400
+#define	PX210_PHY1_PLL0_TX_PSC_A0			0x90400
+	#define PLL0_TX_PSC_A0					0xfb
+#define	PX210_PHY0_PLL0_TX_PSC_A2			0x18408
+#define	PX210_PHY1_PLL0_TX_PSC_A2			0x90408
+	#define PLL0_TX_PSC_A2					0x4aa
+#define	PX210_PHY0_PLL0_TX_PSC_A3			0x1840c
+#define	PX210_PHY1_PLL0_TX_PSC_A3			0x9040c
+	#define PLL0_TX_PSC_A3					0x4aa
+#define	PX210_PHY0_PLL0_RX_PSC_A0			0x28000
+#define	PX210_PHY1_PLL0_RX_PSC_A0			0xa0000
+	#define PLL0_RX_PSC_A0					0x0
+#define	PX210_PHY0_PLL0_RX_PSC_A2			0x28008
+#define	PX210_PHY1_PLL0_RX_PSC_A2			0xa0008
+	#define PLL0_RX_PSC_A2					0x0
+#define	PX210_PHY0_PLL0_RX_PSC_A3			0x2800C
+#define	PX210_PHY1_PLL0_RX_PSC_A3			0xa000C
+	#define PLL0_RX_PSC_A3					0x0
+#define	PX210_PHY0_PLL0_RX_PSC_CAL			0x28018
+#define	PX210_PHY1_PLL0_RX_PSC_CAL			0xa0018
+	#define PLL0_RX_PSC_CAL					0x0
+
+#define	PX210_PHY0_PLL1_TX_PSC_A0			0x1a400
+	#define PLL1_TX_PSC_A0					0xfb
+#define	PX210_PHY0_PLL1_TX_PSC_A2			0x1a408
+	#define PLL1_TX_PSC_A2					0x4aa
+#define	PX210_PHY0_PLL1_TX_PSC_A3			0x1a40c
+	#define PLL1_TX_PSC_A3					0x4aa
+#define	PX210_PHY0_PLL1_RX_PSC_A0			0x2a000
+	#define PLL1_RX_PSC_A0					0x0
+#define	PX210_PHY0_PLL1_RX_PSC_A2			0x2a008
+	#define PLL1_RX_PSC_A2					0x0
+#define	PX210_PHY0_PLL1_RX_PSC_A3			0x2a00C
+	#define PLL1_RX_PSC_A3					0x0
+#define	PX210_PHY0_PLL1_RX_PSC_CAL			0x2a018
+	#define PLL1_RX_PSC_CAL					0x0
+
+#define PX210_PHY0_PLL0_XCVR_CTRL			0x183a8
+#define PX210_PHY1_PLL0_XCVR_CTRL			0x903a8
+	#define PLL0_XCVR_CTRL					0xf
+#define PX210_PHY0_PLL1_XCVR_CTRL			0x1a3a8
+	#define PLL1_XCVR_CTRL					0xf
+
+#define PX210_PHY0_PLL0_RX_GCSM1_CTRL			0x28420
+#define PX210_PHY1_PLL0_RX_GCSM1_CTRL			0xa0420
+	#define PLL0_RX_GCSM1_CTRL				0x0
+#define PX210_PHY0_PLL0_RX_GCSM2_CTRL			0x28440
+#define PX210_PHY1_PLL0_RX_GCSM2_CTRL			0xa0440
+	#define PLL0_RX_GCSM2_CTRL				0x0
+#define PX210_PHY0_PLL0_RX_PERGCSM_CTRL			0x28460
+#define PX210_PHY1_PLL0_RX_PERGCSM_CTRL			0xa0460
+	#define PLL0_RX_PERGCSM_CTRL				0x0
+
+#define PX210_PHY0_PLL1_RX_GCSM1_CTRL			0x2a420
+	#define PLL1_RX_GCSM1_CTRL				0x0
+#define PX210_PHY0_PLL1_RX_GCSM2_CTRL			0x2a440
+	#define PLL1_RX_GCSM2_CTRL				0x0
+#define PX210_PHY0_PLL1_RX_PERGCSM_CTRL			0x2a460
+	#define PLL1_RX_PERGCSM_CTRL				0x0
+
+/* swing and emphasis */
+#define PX210_PHY0_PLL0_TX_DIAG_ACYA			0x1879c
+#define PX210_PHY0_PLL1_TX_DIAG_ACYA			0x1a79c
+#define PX210_PHY1_PLL0_TX_DIAG_ACYA			0x9079c
+	#define LOCK						1
+	#define UNLOCK						0
+
+#define PX210_PHY0_PLL0_TX_TXCC_CTRL			0x18100
+#define PX210_PHY0_PLL1_TX_TXCC_CTRL			0x1a100
+#define PX210_PHY1_PLL0_TX_TXCC_CTRL			0x90100
+	#define TX_TXCC_CTRL					0x8a4
+
+#define PX210_PHY0_PLL0_TX_DRV				0x18318
+#define PX210_PHY0_PLL1_TX_DRV				0x1a318
+#define PX210_PHY1_PLL0_TX_DRV				0x90318
+	#define TX_DRV						0x3
+
+#define PX210_PHY0_PLL0_TX_MGNFS				0x18140
+#define PX210_PHY0_PLL1_TX_MGNFS				0x1a140
+#define PX210_PHY1_PLL0_TX_MGNFS				0x90140
+
+#define PX210_PHY0_PLL0_TX_CPOST				0x18130
+#define PX210_PHY0_PLL1_TX_CPOST				0x1a130
+#define PX210_PHY0_PLL1_TX_CPOST1			0x1a13c
+#define PX210_PHY1_PLL0_TX_CPOST				0x90130
+
+/******************************phy register end********************************************/
+#endif /* __PX210_REG_H__ */
diff --git a/target/linux/phytium/files-5.10/drivers/hwmon/tacho-phytium.c b/target/linux/phytium/files-5.10/drivers/hwmon/tacho-phytium.c
new file mode 100644
index 00000000000000..cbfbe0b8250f54
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/hwmon/tacho-phytium.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Hwmon driver for Phytium tachometer.
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/acpi.h>
+
+#define	TIMER_CTRL_REG	0x00
+#define		TIMER_CTRL_MODE_SHIFT		0//0:1
+#define		TIMER_CTRL_RESET_SHIFT		BIT(2)
+#define		TIMER_CTRL_FORCE_SHIFT		BIT(3)
+#define		TIMER_CTRL_CAPTURE_EN_SHIFT	BIT(4)
+#define		TIMER_CTRL_CAPTURE_CNT_SHIFT	5//5:11
+#define		TIMER_CTRL_ANTI_JITTER_SHIFT	18//18:19
+#define		TIMER_CTRL_TACHO_MODE_SHIFT	20//20:21
+#define		TIMER_CTRL_TIMER_CNT_MODE_SHIFT	BIT(22)
+#define		TIMER_CTRL_BIT_SET_SHIFT	24
+#define		TIMER_CTRL_CNT_EN_SHIFT		BIT(25)
+#define		TIMER_CTRL_CNT_CLR_SHIFT	BIT(26)
+#define		TIMER_CTRL_TIMER_MODE_SHIFT	BIT(27)
+#define		TIMER_CTRL_PULSE_NUM_SHIFT	28//28:30
+#define		TIMER_CTRL_TACHO_EN_SHIFT	BIT(31)
+#define	TIMER_TACHO_RES_REG	0x04
+#define		TIMER_TACHO_RES_VALID_SHIFT	BIT(31)
+#define		TIMER_TACHO_RES_MASK	GENMASK(30, 0)
+#define	TIMER_CMP_VALUE_UP_REG	0x08
+#define	TIMER_CMP_VALUE_LOW_REG	0x1C
+#define	TIMER_CNT_VALUE_UP_REG	0x20
+#define	TIMER_CNT_VALUE_LOW_REG	0x24
+#define	TIMER_INT_MASK_REG	0x28
+#define	TIMER_INT_STAT_REG	0x2C
+#define		TIMER_INT_CAPTURE_SHIFT		BIT(5)
+#define		TIMER_INT_CYC_COMP_SHIFT	BIT(4)
+#define		TIMER_INT_ONE_COMP_SHIFT	BIT(3)
+#define		TIMER_INT_ROLLOVER_SHIFT	BIT(2)
+#define		TIMER_INT_TACHO_UNDER_SHIFT	BIT(1)
+#define		TIMER_INT_TACHO_OVER_SHIFT	BIT(0)
+#define	TIMER_TACHO_OVER_REG	0x30
+#define	TIMER_TACHO_UNDER_REG	0x34
+#define	TIMER_START_VALUE_REG	0x38
+
+#define	TIMER_INT_CLR_MASK	GENMASK(5, 0)
+
+enum tacho_modes {
+tacho_mode = 1,
+capture_mode,
+};
+
+enum edge_modes {
+rising_edge,
+falling_edge,
+double_edge,
+};
+
+struct phytium_tacho {
+	struct device *dev;
+	struct device *hwmon;
+	void __iomem *base;
+	struct clk *clk;
+	u32 freq;
+	int irq;
+	u8 work_mode;
+	u8 edge_mode;
+	u32 debounce;
+};
+
+static u16 capture_count;
+
+static void phytium_tacho_init(struct phytium_tacho *tacho)
+{
+	u32 val;
+
+	if (tacho->work_mode == tacho_mode) {
+		val = (TIMER_CTRL_TACHO_EN_SHIFT |
+			       TIMER_CTRL_CNT_EN_SHIFT |
+			       (tacho->edge_mode << TIMER_CTRL_TACHO_MODE_SHIFT) |
+			       (tacho->debounce << TIMER_CTRL_ANTI_JITTER_SHIFT) |
+			       (tacho->work_mode << TIMER_CTRL_MODE_SHIFT));
+		writel_relaxed(val, tacho->base + TIMER_CTRL_REG);
+		writel_relaxed(0x2faf07f, tacho->base + TIMER_CMP_VALUE_LOW_REG);
+	} else {
+		val = (TIMER_CTRL_TACHO_EN_SHIFT |
+			       TIMER_CTRL_CNT_EN_SHIFT |
+			       (tacho->edge_mode << TIMER_CTRL_TACHO_MODE_SHIFT) |
+			       (tacho->debounce << TIMER_CTRL_ANTI_JITTER_SHIFT) |
+			       TIMER_CTRL_CAPTURE_EN_SHIFT |
+			       (0x7f << TIMER_CTRL_CAPTURE_CNT_SHIFT) |
+			       (tacho->work_mode << TIMER_CTRL_MODE_SHIFT)),
+		writel_relaxed(val, tacho->base + TIMER_CTRL_REG);
+		writel_relaxed(0x20, tacho->base + TIMER_INT_MASK_REG);
+	}
+}
+
+static int phytium_get_fan_tach_rpm(struct phytium_tacho *priv)
+{
+	u64 raw_data, tach_div, clk_source;
+	u8 mode, both;
+	unsigned long timeout;
+	unsigned long loopcounter;
+
+	timeout = jiffies + msecs_to_jiffies(500);
+
+	for (loopcounter = 0;; loopcounter++) {
+		raw_data = readl_relaxed(priv->base + TIMER_TACHO_RES_REG);
+
+		if (raw_data & TIMER_TACHO_RES_VALID_SHIFT)
+			break;
+
+		if (time_after(jiffies, timeout))
+			return -ETIMEDOUT;
+
+		if (loopcounter > 3000)
+			msleep(20);
+		else {
+			udelay(100);
+			cond_resched();
+		}
+	}
+
+	raw_data = raw_data & TIMER_TACHO_RES_MASK;
+	clk_source = priv->freq;
+	mode = priv->edge_mode;
+	both = (mode == double_edge) ? 1 : 0;
+	tach_div = 1 << both;
+
+	if (raw_data == 0)
+		return 0;
+
+	return (clk_source * 60 * raw_data) / 0x2faf080 / tach_div;
+}
+
+static ssize_t show_rpm(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	int rpm;
+	struct phytium_tacho *priv = dev_get_drvdata(dev);
+
+	rpm = phytium_get_fan_tach_rpm(priv);
+	if (rpm < 0)
+		return rpm;
+
+	return sprintf(buf, "%d\n", rpm);
+}
+
+static SENSOR_DEVICE_ATTR(fan_input, 0444,
+		show_rpm, NULL, 0);
+
+static struct attribute *tacho_dev_attrs[] = {
+	&sensor_dev_attr_fan_input.dev_attr.attr,
+	NULL
+};
+
+static umode_t tacho_dev_is_visible(struct kobject *kobj,
+			      struct attribute *a, int index)
+{
+	return a->mode;
+}
+
+static const struct attribute_group tacho_group = {
+	.attrs = tacho_dev_attrs,
+	.is_visible = tacho_dev_is_visible,
+};
+
+static const struct attribute_group *tacho_groups[] = {
+	&tacho_group,
+	NULL
+};
+
+static irqreturn_t capture_irq_handler(int irq, void *dev_id)
+{
+	struct phytium_tacho *priv = dev_id;
+	u32 status = readl_relaxed(priv->base + TIMER_INT_STAT_REG);
+
+	if (status & TIMER_INT_CAPTURE_SHIFT) {
+		capture_count++;
+
+		if (capture_count == 0)
+			dev_err(priv->dev, "Capture counter is overflowed");
+
+		writel_relaxed(status, priv->base + TIMER_INT_STAT_REG);
+		return IRQ_HANDLED;
+	}
+	return IRQ_NONE;
+}
+
+static ssize_t show_capture(struct device *dev, struct device_attribute *attr,
+			char *buf)
+{
+	int cnt;
+	struct phytium_tacho *priv = dev_get_drvdata(dev);
+
+	cnt = capture_count * 0x7f + readl_relaxed(priv->base + TIMER_CNT_VALUE_LOW_REG);
+
+	return sprintf(buf, "%d\n", cnt);
+}
+
+static SENSOR_DEVICE_ATTR(capture_input, 0444,
+		show_capture, NULL, 0);
+
+static struct attribute *capture_dev_attrs[] = {
+	&sensor_dev_attr_capture_input.dev_attr.attr,
+	NULL
+};
+
+static umode_t capture_dev_is_visible(struct kobject *kobj,
+			      struct attribute *a, int index)
+{
+	return a->mode;
+}
+
+static const struct attribute_group capture_group = {
+	.attrs = capture_dev_attrs,
+	.is_visible = capture_dev_is_visible,
+};
+
+static const struct attribute_group *capture_groups[] = {
+	&capture_group,
+	NULL
+};
+
+static int phytium_tacho_get_work_mode(struct phytium_tacho *tacho)
+{
+	struct fwnode_handle *nc = dev_fwnode(tacho->dev);
+
+	if (fwnode_property_read_bool(nc, "tacho"))
+		return tacho_mode;
+	if (fwnode_property_read_bool(nc, "capture"))
+		return capture_mode;
+	return tacho_mode;
+}
+
+static int phytium_tacho_get_edge_mode(struct phytium_tacho *tacho)
+{
+	struct fwnode_handle *nc = dev_fwnode(tacho->dev);
+
+	if (fwnode_property_read_bool(nc, "up"))
+		return rising_edge;
+	if (fwnode_property_read_bool(nc, "down"))
+		return falling_edge;
+	if (fwnode_property_read_bool(nc, "double"))
+		return double_edge;
+	return rising_edge;
+}
+
+static int phytium_tacho_get_debounce(struct phytium_tacho *tacho)
+{
+	u32 value;
+	struct fwnode_handle *nc = dev_fwnode(tacho->dev);
+
+	if (!fwnode_property_read_u32(nc, "debounce-level", &value))
+		return value;
+	else
+		return 0;
+}
+
+static void phytium_tacho_get_of_data(struct phytium_tacho *tacho)
+{
+	tacho->work_mode = phytium_tacho_get_work_mode(tacho);
+	tacho->edge_mode = phytium_tacho_get_edge_mode(tacho);
+	tacho->debounce = phytium_tacho_get_debounce(tacho);
+}
+
+static int phytium_tacho_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct phytium_tacho *tacho;
+	int ret;
+
+	tacho = devm_kzalloc(dev, sizeof(*tacho), GFP_KERNEL);
+	if (!tacho)
+		return -ENOMEM;
+
+	tacho->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOENT;
+
+	tacho->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(tacho->base)) {
+		dev_err(&pdev->dev, "region map failed\n");
+		return PTR_ERR(tacho->base);
+	}
+	if (dev->of_node) {
+		tacho->clk = devm_clk_get(&pdev->dev, NULL);
+		if (IS_ERR(tacho->clk))
+			return PTR_ERR(tacho->clk);
+		ret = clk_prepare_enable(tacho->clk);
+		if (ret)
+			return ret;
+
+		tacho->freq = clk_get_rate(tacho->clk);
+	} else if (has_acpi_companion(dev)){
+		if(fwnode_property_read_u32(dev_fwnode(dev),"clock-frequency", (u32 *)&(tacho->freq) ) <0)
+			tacho->freq = 50000000;
+    }
+
+	tacho->irq = platform_get_irq(pdev, 0);
+	if (tacho->irq < 0) {
+		dev_err(&pdev->dev, "no irq resource?\n");
+		return tacho->irq;
+	}
+
+	ret = devm_request_irq(dev, tacho->irq, capture_irq_handler,
+			       0, "phytium_tacho", tacho);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot request IRQ\n");
+		return ret;
+	}
+
+	phytium_tacho_get_of_data(tacho);
+
+	phytium_tacho_init(tacho);
+
+	if (tacho->work_mode == tacho_mode)
+		tacho->hwmon = devm_hwmon_device_register_with_groups(dev,
+						       "phytium_tacho",
+						       tacho, tacho_groups);
+	else
+		tacho->hwmon = devm_hwmon_device_register_with_groups(dev,
+						       "phytium_capture",
+						       tacho, capture_groups);
+
+	platform_set_drvdata(pdev, tacho);
+
+	return PTR_ERR_OR_ZERO(tacho->hwmon);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_tacho_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int phytium_tacho_resume(struct device *dev)
+{
+	struct phytium_tacho *tacho = dev_get_drvdata(dev);
+
+	phytium_tacho_init(tacho);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_tacho_pm, phytium_tacho_suspend, phytium_tacho_resume);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_tacho_acpi_ids[] = {
+       { "PHYT0033", 0 },
+       { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_tacho_acpi_ids);
+#endif
+
+static const struct of_device_id tacho_of_match[] = {
+	{ .compatible = "phytium,tacho", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, tacho_of_match);
+
+static struct platform_driver phytium_tacho_driver = {
+	.probe		= phytium_tacho_probe,
+	.driver	= {
+		.name	= "phytium_tacho",
+		.pm	= &phytium_tacho_pm,
+		.of_match_table = of_match_ptr(tacho_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_tacho_acpi_ids),
+	},
+};
+
+module_platform_driver(phytium_tacho_driver);
+
+MODULE_AUTHOR("Zhang Yiqun <zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium tachometer driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/hwspinlock/phytium_hwspinlock.c b/target/linux/phytium/files-5.10/drivers/hwspinlock/phytium_hwspinlock.c
new file mode 100644
index 00000000000000..cea34c51afe3d7
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/hwspinlock/phytium_hwspinlock.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium hardware spinlock driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/hwspinlock.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/acpi.h>
+
+#include "hwspinlock_internal.h"
+
+/* Spinlock register offsets */
+#define LOCK_BASE	0x10
+
+#define SEMA_NOTTAKEN	(0)	/* free */
+#define SEMA_TAKEN	(1)	/* locked */
+
+static int phytium_hwspinlock_trylock(struct hwspinlock *lock)
+{
+	void __iomem *lock_addr = lock->priv;
+
+	/* attempt to acquire the lock by reading its value */
+	return (readl(lock_addr) == SEMA_NOTTAKEN);
+}
+
+static void phytium_hwspinlock_unlock(struct hwspinlock *lock)
+{
+	void __iomem *lock_addr = lock->priv;
+
+	/* release the lock by writing 0 to it */
+	writel(SEMA_NOTTAKEN, lock_addr);
+}
+
+static void phytium_hwspinlock_relax(struct hwspinlock *lock)
+{
+	ndelay(50);
+}
+
+static const struct hwspinlock_ops phytium_hwspinlock_ops = {
+	.trylock = phytium_hwspinlock_trylock,
+	.unlock = phytium_hwspinlock_unlock,
+	.relax = phytium_hwspinlock_relax,
+};
+
+static ssize_t phytium_hwlock_test_store(struct device *dev,
+                        struct device_attribute *attr, const char *buf, size_t count)
+{
+    struct hwspinlock *hwlock = NULL;
+    int ret;
+
+    /* dynamically assign a hwspinlock */
+    hwlock = hwspin_lock_request();
+    if (!hwlock) {
+        pr_err("%s can't request hwlock\n", __func__);
+        return -ENODEV;
+    }
+    ret = hwspin_lock_timeout(hwlock, 1000);
+    if (ret < 0) {
+        pr_err("do lock fail\n");
+        goto err;
+    }
+    pr_info("do lock success\n");
+
+    ret = hwspin_trylock(hwlock);
+    if (ret == -EINVAL) {
+        pr_err("lock invalid\n");
+        goto err;
+    }
+    else
+        pr_info("lock status is %s before, than unlock it\n", ret ? "locked" : "no use");
+
+    pr_info("do lock test pass\n");
+err:
+    hwspin_unlock(hwlock);
+    hwspin_lock_free(hwlock);
+    return count;
+}
+
+static DEVICE_ATTR_WO(phytium_hwlock_test);
+
+
+static int phytium_hwspinlock_probe(struct platform_device *pdev)
+{
+	struct fwnode_handle *np = dev_fwnode(&(pdev->dev));
+	struct hwspinlock_device *bank;
+	struct hwspinlock *hwlock;
+	struct resource *res;
+	void __iomem *io_base;
+	int num_locks, i, ret;
+
+	if (!np)
+		return -ENODEV;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	io_base = ioremap(res->start, resource_size(res));
+	if (!io_base)
+		return -ENOMEM;
+
+	/*
+	 * make sure the module is enabled and clocked before reading
+	 * the module SYSSTATUS register
+	 */
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(&pdev->dev);
+		goto iounmap_base;
+	}
+
+	/* Determine number of locks */
+	if (fwnode_property_read_u32(np, "nr-locks", &num_locks)) {
+		dev_err(&pdev->dev, "missing/invalid number of locks\n");
+		ret = -EINVAL;
+		goto iounmap_base;
+	}
+
+	/*
+	 * runtime PM will make sure the clock of this module is
+	 * enabled again iff at least one lock is requested
+	 */
+	ret = pm_runtime_put(&pdev->dev);
+	if (ret < 0)
+		goto iounmap_base;
+
+	bank = kzalloc(struct_size(bank, lock, num_locks), GFP_KERNEL);
+	if (!bank) {
+		ret = -ENOMEM;
+		goto iounmap_base;
+	}
+
+	platform_set_drvdata(pdev, bank);
+
+	for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) {
+		/* Set register address of each lock */
+		hwlock->priv = io_base + LOCK_BASE + sizeof(u32) * i;
+	}
+
+	ret = hwspin_lock_register(bank, &pdev->dev, &phytium_hwspinlock_ops,
+				   0, num_locks);
+	if (ret)
+		goto reg_fail;
+
+	ret = device_create_file(&pdev->dev, &dev_attr_phytium_hwlock_test);
+	return ret;
+reg_fail:
+	kfree(bank);
+iounmap_base:
+	iounmap(io_base);
+	return ret;
+}
+
+static int phytium_hwspinlock_remove(struct platform_device *pdev)
+{
+	struct hwspinlock_device *bank = platform_get_drvdata(pdev);
+	void __iomem *io_base = bank->lock[0].priv - LOCK_BASE;
+	int ret;
+
+	ret = hwspin_lock_unregister(bank);
+	if (ret) {
+		dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	iounmap(io_base);
+	kfree(bank);
+
+	return 0;
+}
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_hwspinlock_acpi_ids[] = {
+       { "PHYT0027", 0 },
+       { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_hwspinlock_acpi_ids);
+#endif
+
+static const struct of_device_id phytium_hwspinlock_of_match[] = {
+	{ .compatible = "phytium,hwspinlock", },
+	{ /* end */ },
+};
+MODULE_DEVICE_TABLE(of, phytium_hwspinlock_of_match);
+
+static struct platform_driver phytium_hwspinlock_driver = {
+	.probe		= phytium_hwspinlock_probe,
+	.remove		= phytium_hwspinlock_remove,
+	.driver		= {
+		.name	= "phytium_hwspinlock",
+		.of_match_table = of_match_ptr(phytium_hwspinlock_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_hwspinlock_acpi_ids),
+	},
+};
+
+static int __init phytium_hwspinlock_init(void)
+{
+	return platform_driver_register(&phytium_hwspinlock_driver);
+}
+postcore_initcall(phytium_hwspinlock_init);
+
+static void __exit phytium_hwspinlock_exit(void)
+{
+	platform_driver_unregister(&phytium_hwspinlock_driver);
+}
+module_exit(phytium_hwspinlock_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Hardware spinlock driver for Phytium");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-common.c b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-common.c
new file mode 100644
index 00000000000000..5c3ee375846c2f
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-common.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Phytium I2C adapter driver.
+ *
+ * Based on the TI DAVINCI I2C adapter driver.
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/swab.h>
+
+#include "i2c-phytium-core.h"
+
+static char *abort_sources[] = {
+	[ABRT_7B_ADDR_NOACK] =
+		"slave address not acknowledged (7bit mode)",
+	[ABRT_10ADDR1_NOACK] =
+		"first address byte not acknowledged (10bit mode)",
+	[ABRT_10ADDR2_NOACK] =
+		"second address byte not acknowledged (10bit mode)",
+	[ABRT_TXDATA_NOACK] =
+		"data not acknowledged",
+	[ABRT_GCALL_NOACK] =
+		"no acknowledgment for a general call",
+	[ABRT_GCALL_READ] =
+		"read after general call",
+	[ABRT_SBYTE_ACKDET] =
+		"start byte acknowledged",
+	[ABRT_SBYTE_NORSTRT] =
+		"trying to send start byte when restart is disabled",
+	[ABRT_10B_RD_NORSTRT] =
+		"trying to read when restart is disabled (10bit mode)",
+	[ABRT_MASTER_DIS] =
+		"trying to use disabled adapter",
+	[ARB_LOST] =
+		"lost arbitration",
+	[ABRT_SLAVE_FLUSH_TXFIFO] =
+		"read command so flush old data in the TX FIFO",
+	[ABRT_SLAVE_ARBLOST] =
+		"slave lost the bus while transmitting data to a remote master",
+	[ABRT_SLAVE_RD_INTX] =
+		"incorrect slave-transmitter mode configuration",
+};
+
+u32 phytium_readl(struct phytium_i2c_dev *dev, int offset)
+{
+	return readl_relaxed(dev->base + offset);
+}
+
+void phytium_writel(struct phytium_i2c_dev *dev, u32 b, int offset)
+{
+	writel_relaxed(b, dev->base + offset);
+}
+
+u32 i2c_phytium_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
+{
+	if (cond)
+		return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
+	else
+		return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000 - 3 + offset;
+}
+
+u32 i2c_phytium_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
+{
+	return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
+}
+
+int i2c_phytium_set_sda_hold(struct phytium_i2c_dev *dev)
+{
+	if (!dev->sda_hold_time) {
+		/* Keep previous hold time setting if no one set it */
+		dev->sda_hold_time = phytium_readl(dev, IC_SDA_HOLD);
+	}
+
+	if (!(dev->sda_hold_time & IC_SDA_HOLD_RX_MASK))
+		dev->sda_hold_time |= 1 << IC_SDA_HOLD_RX_SHIFT;
+
+	dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
+		dev->sda_hold_time & ~(u32)IC_SDA_HOLD_RX_MASK,
+		dev->sda_hold_time >> IC_SDA_HOLD_RX_SHIFT);
+
+	return 0;
+}
+
+void __i2c_phytium_disable(struct phytium_i2c_dev *dev)
+{
+	int timeout = 100;
+
+	do {
+		__i2c_phytium_disable_nowait(dev);
+		if ((phytium_readl(dev, IC_ENABLE_STATUS) & 1) == 0)
+			return;
+
+		/*
+		 * Wait 10 times the signaling period of the highest I2C
+		 * transfer supported by the driver (for 400KHz this is
+		 * 25us).
+		 */
+		usleep_range(25, 250);
+	} while (timeout--);
+
+	dev_warn(dev->dev, "timeout in disabling adapter\n");
+}
+
+unsigned long i2c_phytium_clk_rate(struct phytium_i2c_dev *dev)
+{
+	if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
+		return 0;
+	return dev->get_clk_rate_khz(dev);
+}
+
+int i2c_phytium_prepare_clk(struct phytium_i2c_dev *dev, bool prepare)
+{
+	if (IS_ERR(dev->clk))
+		return PTR_ERR(dev->clk);
+
+	if (prepare)
+		return clk_prepare_enable(dev->clk);
+
+	clk_disable_unprepare(dev->clk);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(i2c_phytium_prepare_clk);
+
+int i2c_phytium_wait_bus_not_busy(struct phytium_i2c_dev *dev)
+{
+	int timeout = 20; /* 20 ms */
+
+	while (phytium_readl(dev, IC_STATUS) & IC_STATUS_ACTIVITY) {
+		if (timeout <= 0) {
+			dev_warn(dev->dev, "timeout waiting for bus ready\n");
+			i2c_recover_bus(&dev->adapter);
+
+			if (phytium_readl(dev, IC_STATUS) & IC_STATUS_ACTIVITY)
+				return -ETIMEDOUT;
+			return 0;
+		}
+		timeout--;
+		usleep_range(1000, 1100);
+	}
+
+	return 0;
+}
+
+int i2c_phytium_handle_tx_abort(struct phytium_i2c_dev *dev)
+{
+	unsigned long abort_source = dev->abort_source;
+	int i;
+
+	if (abort_source & IC_TX_ABRT_NOACK) {
+		for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
+			dev_dbg(dev->dev,
+				"%s: %s\n", __func__, abort_sources[i]);
+		return -EREMOTEIO;
+	}
+
+	for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
+		dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
+
+	if (abort_source & IC_TX_ARB_LOST)
+		return -EAGAIN;
+	else if (abort_source & IC_TX_ABRT_GCALL_READ)
+		return -EINVAL;
+	else
+		return -EIO;
+
+	return 0;
+}
+
+u32 i2c_phytium_func(struct i2c_adapter *adapter)
+{
+	struct phytium_i2c_dev *dev = i2c_get_adapdata(adapter);
+
+	return dev->functionality;
+}
+
+void i2c_phytium_disable(struct phytium_i2c_dev *dev)
+{
+	/* Disable controller */
+	__i2c_phytium_disable(dev);
+
+	/* Disable all interrupts */
+	phytium_writel(dev, 0, IC_INTR_MASK);
+	phytium_readl(dev, IC_CLR_INTR);
+}
+
+void i2c_phytium_disable_int(struct phytium_i2c_dev *dev)
+{
+	phytium_writel(dev, 0, IC_INTR_MASK);
+}
+
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium I2C bus adapter core");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-core.h b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-core.h
new file mode 100644
index 00000000000000..de07ae71870bbc
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-core.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium I2C adapter driver.
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/i2c.h>
+#include <linux/pm_qos.h>
+#include <linux/i2c-smbus.h>
+
+#define IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |		\
+				  I2C_FUNC_SMBUS_BYTE |		\
+				  I2C_FUNC_SMBUS_BYTE_DATA |	\
+				  I2C_FUNC_SMBUS_WORD_DATA |	\
+				  I2C_FUNC_SMBUS_BLOCK_DATA |	\
+				  I2C_FUNC_SMBUS_I2C_BLOCK)
+
+#define IC_CON_MASTER			0x1
+#define IC_CON_SPEED_STD		0x2
+#define IC_CON_SPEED_FAST		0x4
+#define IC_CON_SPEED_HIGH		0x6
+#define IC_CON_SPEED_MASK		0x6
+#define IC_CON_10BITADDR_SLAVE		0x8
+#define IC_CON_10BITADDR_MASTER		0x10
+#define IC_CON_RESTART_EN		0x20
+#define IC_CON_SLAVE_DISABLE		0x40
+#define IC_CON_STOP_DET_IFADDRESSED	0x80
+#define IC_CON_TX_EMPTY_CTRL		0x100
+#define IC_CON_RX_FIFO_FULL_HLD_CTRL	0x200
+
+#define IC_CON				0x0
+#define IC_TAR				0x4
+#define IC_SAR				0x8
+#define IC_DATA_CMD			0x10
+#define IC_SS_SCL_HCNT			0x14
+#define IC_SS_SCL_LCNT			0x18
+#define IC_FS_SCL_HCNT			0x1c
+#define IC_FS_SCL_LCNT			0x20
+#define IC_HS_SCL_HCNT			0x24
+#define IC_HS_SCL_LCNT			0x28
+#define IC_INTR_STAT			0x2c
+#define IC_INTR_MASK			0x30
+#define IC_RAW_INTR_STAT		0x34
+#define IC_RX_TL			0x38
+#define IC_TX_TL			0x3c
+#define IC_CLR_INTR			0x40
+#define IC_CLR_RX_UNDER			0x44
+#define IC_CLR_RX_OVER			0x48
+#define IC_CLR_TX_OVER			0x4c
+#define IC_CLR_RD_REQ			0x50
+#define IC_CLR_TX_ABRT			0x54
+#define IC_CLR_RX_DONE			0x58
+#define IC_CLR_ACTIVITY			0x5c
+#define IC_CLR_STOP_DET			0x60
+#define IC_CLR_START_DET		0x64
+#define IC_CLR_GEN_CALL			0x68
+#define IC_ENABLE			0x6c
+#define IC_STATUS			0x70
+#define IC_TXFLR			0x74
+#define IC_RXFLR			0x78
+#define IC_SDA_HOLD			0x7c
+#define IC_TX_ABRT_SOURCE		0x80
+#define IC_ENABLE_STATUS		0x9c
+#define IC_SMBCLK_LOW_MEXT		0xa8
+#define IC_SMBCLK_LOW_TIMEOUT		0xac
+#define IC_SMBDAT_STUCK_TIMEOUT		0xb4
+#define IC_CLR_SMBCLK_EXT_LOW_TIMEOUT	0xbc
+#define IC_CLR_SMBCLK_TMO_LOW_TIMEOUT	0xc0
+#define IC_CLR_SMBDAT_LOW_TIMEOUT	0xc4
+#define IC_CLR_SMBALERT_IN_N		0xd0
+
+#define IC_INTR_RX_UNDER		0x001
+#define IC_INTR_RX_OVER			0x002
+#define IC_INTR_RX_FULL			0x004
+#define IC_INTR_TX_OVER			0x008
+#define IC_INTR_TX_EMPTY		0x010
+#define IC_INTR_RD_REQ			0x020
+#define IC_INTR_TX_ABRT			0x040
+#define IC_INTR_RX_DONE			0x080
+#define IC_INTR_ACTIVITY		0x100
+#define IC_INTR_STOP_DET		0x200
+#define IC_INTR_START_DET		0x400
+#define IC_INTR_GEN_CALL		0x800
+#define IC_INTR_SMBCLK_EXT_LOW_TIMEOUT	0x1000
+#define IC_INTR_SMBCLK_TMO_LOW_TIMEOUT	0x2000
+#define IC_INTR_SMBSDA_LOW_TIMEOUT	0x4000
+#define IC_INTR_SMBALERT_IN_N		0x20000
+
+#define IC_INTR_DEFAULT_MASK		(IC_INTR_RX_FULL | \
+					 IC_INTR_TX_ABRT | \
+					 IC_INTR_STOP_DET)
+#define IC_INTR_MASTER_MASK		(IC_INTR_DEFAULT_MASK | \
+					 IC_INTR_TX_EMPTY)
+#define IC_INTR_SLAVE_MASK		(IC_INTR_DEFAULT_MASK | \
+					 IC_INTR_RX_DONE | \
+					 IC_INTR_RX_UNDER | \
+					 IC_INTR_RD_REQ)
+#define IC_INTR_SMBUS_MASK		(IC_INTR_MASTER_MASK | \
+					 IC_INTR_SMBCLK_EXT_LOW_TIMEOUT | \
+					 IC_INTR_SMBCLK_TMO_LOW_TIMEOUT | \
+					 IC_INTR_SMBSDA_LOW_TIMEOUT)
+
+#define IC_STATUS_ACTIVITY		0x1
+#define IC_STATUS_TFE			BIT(2)
+#define IC_STATUS_MASTER_ACTIVITY	BIT(5)
+#define IC_STATUS_SLAVE_ACTIVITY	BIT(6)
+
+#define IC_SDA_HOLD_RX_SHIFT		16
+#define IC_SDA_HOLD_RX_MASK		GENMASK(23, IC_SDA_HOLD_RX_SHIFT)
+
+#define IC_ERR_TX_ABRT			0x1
+
+#define IC_TAR_10BITADDR_MASTER		BIT(12)
+
+#define IC_COMP_PARAM_1_SPEED_MODE_HIGH	(BIT(2) | BIT(3))
+#define IC_COMP_PARAM_1_SPEED_MODE_MASK	GENMASK(3, 2)
+
+#define STATUS_IDLE			0x0
+#define STATUS_WRITE_IN_PROGRESS	0x1
+#define STATUS_READ_IN_PROGRESS		0x2
+
+/*
+ * operation modes
+ */
+#define PHYTIUM_IC_MASTER		0
+#define PHYTIUM_IC_SLAVE		1
+
+#define ABRT_7B_ADDR_NOACK		0
+#define ABRT_10ADDR1_NOACK		1
+#define ABRT_10ADDR2_NOACK		2
+#define ABRT_TXDATA_NOACK		3
+#define ABRT_GCALL_NOACK		4
+#define ABRT_GCALL_READ			5
+#define ABRT_SBYTE_ACKDET		7
+#define ABRT_SBYTE_NORSTRT		9
+#define ABRT_10B_RD_NORSTRT		10
+#define ABRT_MASTER_DIS			11
+#define ARB_LOST			12
+#define ABRT_SLAVE_FLUSH_TXFIFO		13
+#define ABRT_SLAVE_ARBLOST		14
+#define ABRT_SLAVE_RD_INTX		15
+
+#define IC_TX_ABRT_7B_ADDR_NOACK	(1UL << ABRT_7B_ADDR_NOACK)
+#define IC_TX_ABRT_10ADDR1_NOACK	(1UL << ABRT_10ADDR1_NOACK)
+#define IC_TX_ABRT_10ADDR2_NOACK	(1UL << ABRT_10ADDR2_NOACK)
+#define IC_TX_ABRT_TXDATA_NOACK		(1UL << ABRT_TXDATA_NOACK)
+#define IC_TX_ABRT_GCALL_NOACK		(1UL << ABRT_GCALL_NOACK)
+#define IC_TX_ABRT_GCALL_READ		(1UL << ABRT_GCALL_READ)
+#define IC_TX_ABRT_SBYTE_ACKDET		(1UL << ABRT_SBYTE_ACKDET)
+#define IC_TX_ABRT_SBYTE_NORSTRT	(1UL << ABRT_SBYTE_NORSTRT)
+#define IC_TX_ABRT_10B_RD_NORSTRT	(1UL << ABRT_10B_RD_NORSTRT)
+#define IC_TX_ABRT_MASTER_DIS		(1UL << ABRT_MASTER_DIS)
+#define IC_TX_ARB_LOST			(1UL << ARB_LOST)
+#define IC_RX_ABRT_SLAVE_RD_INTX	(1UL << ABRT_SLAVE_RD_INTX)
+#define IC_RX_ABRT_SLAVE_ARBLOST	(1UL << ABRT_SLAVE_ARBLOST)
+#define IC_RX_ABRT_SLAVE_FLUSH_TXFIFO	(1UL << ABRT_SLAVE_FLUSH_TXFIFO)
+
+#define IC_TX_ABRT_NOACK		(IC_TX_ABRT_7B_ADDR_NOACK | \
+					 IC_TX_ABRT_10ADDR1_NOACK | \
+					 IC_TX_ABRT_10ADDR2_NOACK | \
+					 IC_TX_ABRT_TXDATA_NOACK | \
+					 IC_TX_ABRT_GCALL_NOACK)
+#define CONTROLLER_TYPE_IIC		0
+#define CONTROLLER_TYPE_SMBUS		1
+
+struct phytium_i2c_dev {
+	struct device		*dev;
+	void __iomem		*base;
+	int			irq;
+	u32			flags;
+	struct completion	cmd_complete;
+	struct clk		*clk;
+	struct reset_control	*rst;
+	int			mode;
+	struct i2c_client	*slave;
+	u32			(*get_clk_rate_khz)(struct phytium_i2c_dev *dev);
+
+	struct i2c_adapter	adapter;
+	struct i2c_client	*ara;
+	struct i2c_smbus_alert_setup alert_data;
+
+	struct phytium_pci_i2c *controller;
+
+	unsigned int		status;
+	int			cmd_err;
+	u32			abort_source;
+
+	struct i2c_msg		*msgs;
+	int			msgs_num;
+	int			msg_write_idx;
+	int			msg_read_idx;
+	int			msg_err;
+	u32			tx_buf_len;
+	u8			*tx_buf;
+	u32			rx_buf_len;
+	u8			*rx_buf;
+
+	u32			master_cfg;
+	u32			slave_cfg;
+	u32			functionality;
+	unsigned int		tx_fifo_depth;
+	unsigned int		rx_fifo_depth;
+	int			rx_outstanding;
+
+	struct i2c_timings	timings;
+	u32			sda_hold_time;
+	u16			ss_hcnt;
+	u16			ss_lcnt;
+	u16			fs_hcnt;
+	u16			fs_lcnt;
+	u16			fp_hcnt;
+	u16			fp_lcnt;
+	u16			hs_hcnt;
+	u16			hs_lcnt;
+
+	bool			pm_disabled;
+	void			(*disable)(struct phytium_i2c_dev *dev);
+	void			(*disable_int)(struct phytium_i2c_dev *dev);
+	int			(*init)(struct phytium_i2c_dev *dev);
+};
+
+#define ACCESS_INTR_MASK	0x00000004
+
+#define DEFAULT_CLOCK_FREQUENCY	48000000
+
+u32 phytium_readl(struct phytium_i2c_dev *dev, int offset);
+void phytium_writel(struct phytium_i2c_dev *dev, u32 b, int offset);
+unsigned long i2c_phytium_clk_rate(struct phytium_i2c_dev *dev);
+int i2c_phytium_prepare_clk(struct phytium_i2c_dev *dev, bool prepare);
+int i2c_phytium_wait_bus_not_busy(struct phytium_i2c_dev *dev);
+int i2c_phytium_handle_tx_abort(struct phytium_i2c_dev *dev);
+u32 i2c_phytium_func(struct i2c_adapter *adap);
+void i2c_phytium_disable(struct phytium_i2c_dev *dev);
+void i2c_phytium_disable_int(struct phytium_i2c_dev *dev);
+int i2c_phytium_set_sda_hold(struct phytium_i2c_dev *dev);
+u32 i2c_phytium_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
+u32 i2c_phytium_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
+
+static inline void __i2c_phytium_enable(struct phytium_i2c_dev *dev)
+{
+	phytium_writel(dev, 1, IC_ENABLE);
+}
+
+static inline void __i2c_phytium_disable_nowait(struct phytium_i2c_dev *dev)
+{
+	phytium_writel(dev, 0, IC_ENABLE);
+}
+
+void __i2c_phytium_disable(struct phytium_i2c_dev *dev);
+
+extern int i2c_phytium_probe(struct phytium_i2c_dev *dev);
+
+extern int i2c_phytium_probe_slave(struct phytium_i2c_dev *dev);
diff --git a/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-master.c b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-master.c
new file mode 100644
index 00000000000000..9cab525020ab49
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-master.c
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium I2C adapter driver.
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include "i2c-phytium-core.h"
+
+static int i2c_phytium_init_master(struct phytium_i2c_dev *dev)
+{
+	/* Disable the adapter */
+	__i2c_phytium_disable(dev);
+
+	/* Write standard speed timing parameters */
+	phytium_writel(dev, dev->ss_hcnt, IC_SS_SCL_HCNT);
+	phytium_writel(dev, dev->ss_lcnt, IC_SS_SCL_LCNT);
+
+	/* Write fast mode/fast mode plus timing parameters */
+	phytium_writel(dev, dev->fs_hcnt, IC_FS_SCL_HCNT);
+	phytium_writel(dev, dev->fs_lcnt, IC_FS_SCL_LCNT);
+
+	/* Write high speed timing parameters if supported */
+	if (dev->hs_hcnt && dev->hs_hcnt) {
+		phytium_writel(dev, dev->hs_hcnt, IC_HS_SCL_HCNT);
+		phytium_writel(dev, dev->hs_lcnt, IC_HS_SCL_LCNT);
+	}
+
+	/* Write SDA hold time if supported */
+	if (dev->sda_hold_time)
+		phytium_writel(dev, dev->sda_hold_time, IC_SDA_HOLD);
+
+	/* Configure Tx/Rx FIFO threshold levels */
+	phytium_writel(dev, dev->tx_fifo_depth >> 1, IC_TX_TL);
+	phytium_writel(dev, 0, IC_RX_TL);
+
+	/* Configure the I2C master */
+	phytium_writel(dev, dev->master_cfg, IC_CON);
+
+	return 0;
+}
+
+static void i2c_phytium_xfer_init(struct phytium_i2c_dev *dev)
+{
+	struct i2c_msg *msgs = dev->msgs;
+	u32 ic_con, ic_tar = 0;
+
+	/* Disable the adapter */
+	__i2c_phytium_disable(dev);
+
+	/* If the slave address is 10-bit address, enable 10BITADDR */
+	ic_con = phytium_readl(dev, IC_CON);
+	if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
+		ic_con |= IC_CON_10BITADDR_MASTER;
+		ic_tar = IC_TAR_10BITADDR_MASTER;
+	} else {
+		ic_con &= ~IC_CON_10BITADDR_MASTER;
+	}
+
+	phytium_writel(dev, ic_con, IC_CON);
+
+	/*
+	 * Set the slave (target) address and enable 10-bit addressing mode
+	 * if applicable.
+	 */
+	phytium_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, IC_TAR);
+
+	/* Enforce disabled interrupts */
+	i2c_phytium_disable_int(dev);
+
+	/* Enable the adapter */
+	__i2c_phytium_enable(dev);
+
+	/* Dummy read */
+	phytium_readl(dev, IC_ENABLE_STATUS);
+
+	/* Clear and enable interrupts */
+	phytium_readl(dev, IC_CLR_INTR);
+	phytium_writel(dev, IC_INTR_SMBUS_MASK, IC_INTR_MASK);
+}
+
+static void i2c_phytium_xfer_msg(struct phytium_i2c_dev *dev)
+{
+	struct i2c_msg *msgs = dev->msgs;
+	u32 intr_mask;
+	int tx_limit, rx_limit;
+	u32 addr = msgs[dev->msg_write_idx].addr;
+	u32 buf_len = dev->tx_buf_len;
+	u8 *buf = dev->tx_buf;
+	bool need_restart = false;
+
+	intr_mask = IC_INTR_MASTER_MASK;
+
+	for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
+		u32 flags = msgs[dev->msg_write_idx].flags;
+
+		if (msgs[dev->msg_write_idx].addr != addr) {
+			dev_err(dev->dev,
+				"%s: invalid target address\n", __func__);
+			dev->msg_err = -EINVAL;
+			break;
+		}
+
+		if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
+			/* new i2c_msg */
+			buf = msgs[dev->msg_write_idx].buf;
+			buf_len = msgs[dev->msg_write_idx].len;
+
+			if ((dev->master_cfg & IC_CON_RESTART_EN) &&
+			    (dev->msg_write_idx > 0))
+				need_restart = true;
+		}
+
+		tx_limit = dev->tx_fifo_depth - phytium_readl(dev, IC_TXFLR);
+		rx_limit = dev->tx_fifo_depth - phytium_readl(dev, IC_RXFLR);
+
+		while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
+			u32 cmd = 0;
+
+			if (dev->msg_write_idx == dev->msgs_num - 1 &&
+			    buf_len == 1 && !(flags & I2C_M_RECV_LEN))
+				cmd |= BIT(9);
+
+			if (need_restart) {
+				cmd |= BIT(10);
+				need_restart = false;
+			}
+
+			if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
+				/* avoid rx buffer overrun */
+				if (dev->rx_outstanding >= dev->rx_fifo_depth)
+					break;
+
+				phytium_writel(dev, cmd | 0x100, IC_DATA_CMD);
+				rx_limit--;
+				dev->rx_outstanding++;
+			} else {
+				phytium_writel(dev, cmd | *buf++, IC_DATA_CMD);
+			}
+			tx_limit--;
+			buf_len--;
+		}
+
+		dev->tx_buf = buf;
+		dev->tx_buf_len = buf_len;
+
+		/*
+		 * Because we don't know the buffer length in the
+		 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
+		 * the transaction here.
+		 */
+		if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
+			/* more bytes to be written */
+			dev->status |= STATUS_WRITE_IN_PROGRESS;
+			break;
+		}
+
+		dev->status &= ~STATUS_WRITE_IN_PROGRESS;
+	}
+
+	if (dev->msg_write_idx == dev->msgs_num)
+		intr_mask &= ~IC_INTR_TX_EMPTY;
+
+	if (dev->msg_err)
+		intr_mask = 0;
+
+	phytium_writel(dev, intr_mask,  IC_INTR_MASK);
+}
+
+static u8 i2c_phytium_recv_len(struct phytium_i2c_dev *dev, u8 len)
+{
+	struct i2c_msg *msgs = dev->msgs;
+	u32 flags = msgs[dev->msg_read_idx].flags;
+
+	/*
+	 * Adjust the buffer length and mask the flag
+	 * after receiving the first byte.
+	 */
+	len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
+	dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
+	msgs[dev->msg_read_idx].len = len;
+	msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
+
+	return len;
+}
+
+static void i2c_phytium_read(struct phytium_i2c_dev *dev)
+{
+	struct i2c_msg *msgs = dev->msgs;
+	int rx_valid;
+
+	for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
+		u32 len;
+		u8 *buf;
+
+		if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
+			continue;
+
+		if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
+			len = msgs[dev->msg_read_idx].len;
+			buf = msgs[dev->msg_read_idx].buf;
+		} else {
+			len = dev->rx_buf_len;
+			buf = dev->rx_buf;
+		}
+
+		rx_valid = phytium_readl(dev, IC_RXFLR);
+
+		for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
+			u32 flags = msgs[dev->msg_read_idx].flags;
+
+			*buf = phytium_readl(dev, IC_DATA_CMD);
+			/* Ensure length byte is a valid value */
+			if (flags & I2C_M_RECV_LEN &&
+				*buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
+				len = i2c_phytium_recv_len(dev, *buf);
+			}
+			buf++;
+			dev->rx_outstanding--;
+		}
+
+		if (len > 0) {
+			dev->status |= STATUS_READ_IN_PROGRESS;
+			dev->rx_buf_len = len;
+			dev->rx_buf = buf;
+			break;
+		}
+
+		dev->status &= ~STATUS_READ_IN_PROGRESS;
+	}
+}
+
+static int i2c_phytium_xfer(struct i2c_adapter *adapter, struct i2c_msg msgs[], int num)
+{
+	struct phytium_i2c_dev *dev = i2c_get_adapdata(adapter);
+	int ret;
+
+	dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
+
+	pm_runtime_get_sync(dev->dev);
+
+	reinit_completion(&dev->cmd_complete);
+	dev->msgs = msgs;
+	dev->msgs_num = num;
+	dev->cmd_err = 0;
+	dev->msg_write_idx = 0;
+	dev->msg_read_idx = 0;
+	dev->msg_err = 0;
+	dev->status = STATUS_IDLE;
+	dev->abort_source = 0;
+	dev->rx_outstanding = 0;
+
+	ret = i2c_phytium_wait_bus_not_busy(dev);
+	if (ret < 0)
+		goto done;
+
+	/* Start the transfers */
+	i2c_phytium_xfer_init(dev);
+
+	/* Wait for tx to complete */
+	if (!wait_for_completion_timeout(&dev->cmd_complete, adapter->timeout)) {
+		dev_err(dev->dev, "controller timed out\n");
+		i2c_recover_bus(&dev->adapter);
+		i2c_phytium_init_master(dev);
+		ret = -ETIMEDOUT;
+		goto done;
+	}
+
+	__i2c_phytium_disable_nowait(dev);
+
+	if (dev->msg_err) {
+		ret = dev->msg_err;
+		goto done;
+	}
+
+	if (likely(!dev->cmd_err && !dev->status)) {
+		ret = num;
+		goto done;
+	}
+
+	/* We have got an error */
+	if (dev->cmd_err == IC_ERR_TX_ABRT) {
+		ret = i2c_phytium_handle_tx_abort(dev);
+		goto done;
+	}
+
+	if (dev->status)
+		dev_err(dev->dev, "transfer terminated early.\n");
+
+	ret = -EIO;
+
+done:
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
+
+	return ret;
+}
+
+static const struct i2c_algorithm i2c_phytium_algo = {
+	.master_xfer = i2c_phytium_xfer,
+	.functionality = i2c_phytium_func,
+};
+
+static const struct i2c_adapter_quirks i2c_phytium_quirks = {
+	.flags = I2C_AQ_NO_ZERO_LEN,
+};
+
+static u32 i2c_phytium_read_clear_intrbits(struct phytium_i2c_dev *dev)
+{
+	u32 stat;
+
+	stat = phytium_readl(dev, IC_INTR_STAT);
+
+	if (stat & IC_INTR_RX_UNDER)
+		phytium_readl(dev, IC_CLR_RX_UNDER);
+	if (stat & IC_INTR_RX_OVER)
+		phytium_readl(dev, IC_CLR_RX_OVER);
+	if (stat & IC_INTR_TX_OVER)
+		phytium_readl(dev, IC_CLR_TX_OVER);
+	if (stat & IC_INTR_RD_REQ)
+		phytium_readl(dev, IC_CLR_RD_REQ);
+	if (stat & IC_INTR_TX_ABRT) {
+		dev->abort_source = phytium_readl(dev, IC_TX_ABRT_SOURCE);
+		phytium_readl(dev, IC_CLR_TX_ABRT);
+	}
+	if (stat & IC_INTR_RX_DONE)
+		phytium_readl(dev, IC_CLR_RX_DONE);
+	if (stat & IC_INTR_ACTIVITY)
+		phytium_readl(dev, IC_CLR_ACTIVITY);
+	if (stat & IC_INTR_STOP_DET)
+		phytium_readl(dev, IC_CLR_STOP_DET);
+	if (stat & IC_INTR_START_DET)
+		phytium_readl(dev, IC_CLR_START_DET);
+	if (stat & IC_INTR_GEN_CALL)
+		phytium_readl(dev, IC_CLR_GEN_CALL);
+	if (stat & IC_INTR_SMBCLK_EXT_LOW_TIMEOUT)
+		phytium_readl(dev, IC_CLR_SMBCLK_EXT_LOW_TIMEOUT);
+	if (stat & IC_INTR_SMBCLK_TMO_LOW_TIMEOUT)
+		phytium_readl(dev, IC_CLR_SMBCLK_TMO_LOW_TIMEOUT);
+	if (stat & IC_INTR_SMBSDA_LOW_TIMEOUT)
+		phytium_readl(dev, IC_CLR_SMBDAT_LOW_TIMEOUT);
+	if (stat & IC_INTR_SMBALERT_IN_N)
+		phytium_readl(dev, IC_CLR_SMBALERT_IN_N);
+
+	return stat;
+}
+
+static int i2c_phytium_irq_handler_master(struct phytium_i2c_dev *dev)
+{
+	u32 stat;
+
+	stat = i2c_phytium_read_clear_intrbits(dev);
+
+	/* SMBus interrupt */
+	if (stat & (IC_INTR_SMBCLK_EXT_LOW_TIMEOUT | IC_INTR_SMBCLK_TMO_LOW_TIMEOUT)) {
+		phytium_writel(dev, phytium_readl(dev, IC_ENABLE) & (~BIT(6)),
+			       IC_ENABLE);
+		phytium_writel(dev, phytium_readl(dev, IC_ENABLE) | BIT(4),
+			       IC_ENABLE);
+		goto abort;
+	}
+
+	if (stat & IC_INTR_SMBSDA_LOW_TIMEOUT) {
+		phytium_writel(dev, phytium_readl(dev, IC_ENABLE) | BIT(6),
+			       IC_ENABLE);
+		goto abort;
+	}
+
+	if (stat & IC_INTR_SMBALERT_IN_N && dev->ara)
+		i2c_handle_smbus_alert(dev->ara);
+
+	if (stat & IC_INTR_TX_ABRT) {
+		dev->cmd_err |= IC_ERR_TX_ABRT;
+		dev->status = STATUS_IDLE;
+
+		/* Anytime TX_ABRT is set, the contents of the tx/rx
+		 * buffers are flushed. Make sure to skip them.
+		 */
+		phytium_writel(dev, 0, IC_INTR_MASK);
+		goto abort;
+	}
+
+	if (stat & IC_INTR_RX_FULL)
+		i2c_phytium_read(dev);
+
+	if (stat & IC_INTR_TX_EMPTY)
+		i2c_phytium_xfer_msg(dev);
+
+abort:
+	if ((stat & (IC_INTR_TX_ABRT | IC_INTR_STOP_DET)) ||
+	    dev->msg_err)
+		complete(&dev->cmd_complete);
+	else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
+		/* Workaround to trigger pending interrupt */
+		stat = phytium_readl(dev, IC_INTR_MASK);
+		i2c_phytium_disable_int(dev);
+		phytium_writel(dev, stat, IC_INTR_MASK);
+	}
+
+	return 0;
+}
+
+static int i2c_phytium_set_timings_master(struct phytium_i2c_dev *dev)
+{
+	const char *mode_str, *fp_str = "";
+	u32 sda_falling_time, scl_falling_time;
+	struct i2c_timings *t = &dev->timings;
+	u32 ic_clk;
+	int ret;
+
+	/* Set standard and fast speed dividers for high/low periods */
+	sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
+	scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
+
+	/* Calculate SCL timing parameters for standard mode if not set */
+	if (!dev->ss_hcnt || !dev->ss_lcnt) {
+		ic_clk = i2c_phytium_clk_rate(dev);
+		dev->ss_hcnt =
+			i2c_phytium_scl_hcnt(ic_clk,
+					4000, /* tHD;STA = tHIGH = 4.0 us */
+					sda_falling_time,
+					0,	/* 0: DW default, 1: Ideal */
+					0);	/* No offset */
+		dev->ss_lcnt =
+			i2c_phytium_scl_lcnt(ic_clk,
+					4700,	/* tLOW = 4.7 us */
+					scl_falling_time,
+					0);	/* No offset */
+	}
+	dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
+		dev->ss_hcnt, dev->ss_lcnt);
+	/*
+	 * Set SCL timing parameters for fast mode or fast mode plus. Only
+	 * difference is the timing parameter values since the registers are
+	 * the same.
+	 */
+	if (t->bus_freq_hz == 1000000) {
+		/*
+		 * Check are fast mode plus parameters available and use
+		 * fast mode if not.
+		 */
+		if (dev->fp_hcnt && dev->fp_lcnt) {
+			dev->fs_hcnt = dev->fp_hcnt;
+			dev->fs_lcnt = dev->fp_lcnt;
+			fp_str = " Plus";
+		}
+	}
+	/*
+	 * Calculate SCL timing parameters for fast mode if not set. They are
+	 * needed also in high speed mode.
+	 */
+	if (!dev->fs_hcnt || !dev->fs_lcnt) {
+		ic_clk = i2c_phytium_clk_rate(dev);
+		dev->fs_hcnt =
+			i2c_phytium_scl_hcnt(ic_clk,
+					600,	/* tHD;STA = tHIGH = 0.6 us */
+					sda_falling_time,
+					0,	/* 0: DW default, 1: Ideal */
+					0);	/* No offset */
+		dev->fs_lcnt =
+			i2c_phytium_scl_lcnt(ic_clk,
+					1300,	/* tLOW = 1.3 us */
+					scl_falling_time,
+					0);	/* No offset */
+	}
+	dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
+		fp_str, dev->fs_hcnt, dev->fs_lcnt);
+
+	if (dev->hs_hcnt && dev->hs_lcnt)
+		dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
+			dev->hs_hcnt, dev->hs_lcnt);
+
+	ret = i2c_phytium_set_sda_hold(dev);
+	if (ret)
+		goto out;
+
+	switch (dev->master_cfg & IC_CON_SPEED_MASK) {
+	case IC_CON_SPEED_STD:
+		mode_str = "Standard Mode";
+		break;
+	case IC_CON_SPEED_HIGH:
+		mode_str = "High Speed Mode";
+		break;
+	default:
+		mode_str = "Fast Mode";
+	}
+	dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
+
+out:
+	return ret;
+}
+
+static irqreturn_t i2c_phytium_isr(int this_irq, void *dev_id)
+{
+	struct phytium_i2c_dev *dev = dev_id;
+	u32 stat, enabled;
+
+	enabled = phytium_readl(dev, IC_ENABLE);
+	stat = phytium_readl(dev, IC_RAW_INTR_STAT);
+	if (!enabled || !(stat & ~IC_INTR_ACTIVITY))
+		return IRQ_NONE;
+
+	i2c_phytium_irq_handler_master(dev);
+
+	return IRQ_HANDLED;
+}
+
+int i2c_phytium_probe(struct phytium_i2c_dev *dev)
+{
+	struct i2c_adapter *adapter = &dev->adapter;
+	unsigned long irq_flags;
+	int ret;
+
+	init_completion(&dev->cmd_complete);
+
+	dev->init = i2c_phytium_init_master;
+	dev->disable = i2c_phytium_disable;
+	dev->disable_int = i2c_phytium_disable_int;
+
+	ret = i2c_phytium_set_timings_master(dev);
+	if (ret)
+		return ret;
+
+	ret = dev->init(dev);
+	if (ret)
+		return ret;
+
+	/* XXX: should be initialized in firmware, remove it in future */
+#define DEFAULT_TIMEOUT	(DEFAULT_CLOCK_FREQUENCY / 1000 * 35)
+	phytium_writel(dev, DEFAULT_TIMEOUT, IC_SMBCLK_LOW_MEXT);
+	phytium_writel(dev, DEFAULT_TIMEOUT, IC_SMBCLK_LOW_TIMEOUT);
+	phytium_writel(dev, DEFAULT_TIMEOUT, IC_SMBDAT_STUCK_TIMEOUT);
+
+	snprintf(adapter->name, sizeof(adapter->name), "Phytium I2C adapter");
+	adapter->retries = 3;
+	adapter->algo = &i2c_phytium_algo;
+	adapter->quirks = &i2c_phytium_quirks;
+	adapter->dev.parent = dev->dev;
+	i2c_set_adapdata(adapter, dev);
+
+	irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
+
+	i2c_phytium_disable_int(dev);
+	ret = devm_request_irq(dev->dev, dev->irq, i2c_phytium_isr, irq_flags,
+			       dev_name(dev->dev), dev);
+	if (ret) {
+		dev_err(dev->dev, "failed to request irq %i: %d\n", dev->irq, ret);
+		return ret;
+	}
+
+	/*
+	 * Increment PM usage count during adapter registration in order to
+	 * avoid possible spurious runtime suspend when adapter device is
+	 * registered to the device core and immediate resume in case bus has
+	 * registered I2C slaves that do I2C transfers in their probe.
+	 */
+	pm_runtime_get_noresume(dev->dev);
+	ret = i2c_add_numbered_adapter(adapter);
+	if (ret)
+		dev_err(dev->dev, "fail to add adapter: %d\n", ret);
+	pm_runtime_put_noidle(dev->dev);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i2c_phytium_probe);
+
+MODULE_DESCRIPTION("Phytium I2C bus master adapter");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-pci.c b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-pci.c
new file mode 100644
index 00000000000000..b0482b82b6ac14
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-pci.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * PCI driver for Phytium I2C adapter.
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/acpi.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/pm_runtime.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include "i2c-phytium-core.h"
+
+#define DRV_NAME "i2c-phytium-pci"
+
+enum phytium_pci_ctl_id_t {
+	octopus_i2c,
+};
+
+struct scl_sda_cfg {
+	u32 ss_hcnt;
+	u32 fs_hcnt;
+	u32 ss_lcnt;
+	u32 fs_lcnt;
+	u32 sda_hold;
+};
+
+struct phytium_pci_i2c {
+	u32 bus_num;
+	u32 bus_cfg;
+	u32 tx_fifo_depth;
+	u32 rx_fifo_depth;
+	u32 clk_khz;
+	u32 functionality;
+	u32 flags;
+	struct scl_sda_cfg *scl_sda_cfg;
+	int (*setup)(struct pci_dev *pdev, struct phytium_pci_i2c *c);
+};
+
+/* Octopus HCNT/LCNT/SDA hold time */
+static struct scl_sda_cfg octopus_config = {
+	.ss_hcnt = 0x190,
+	.ss_lcnt = 0x1d6,
+	.fs_hcnt = 0x3c,
+	.fs_lcnt = 0x82,
+	.sda_hold = 0x0, // XXX
+};
+
+static int octopus_setup(struct pci_dev *pdev, struct phytium_pci_i2c *c)
+{
+	struct phytium_i2c_dev *i2c = pci_get_drvdata(pdev);
+	struct i2c_client *ara;
+
+	if (pdev->device == 0xdc32) {
+		/*
+		 * Since we have already register the adapter, the dev->irq
+		 * must be valid.
+		 */
+		i2c->alert_data.irq = i2c->irq;
+
+		ara = i2c_new_smbus_alert_device(&i2c->adapter, &i2c->alert_data);
+		if (IS_ERR(ara))
+			return PTR_ERR(ara);
+
+		i2c->ara = ara;
+	}
+
+	return 0;
+}
+
+static struct phytium_pci_i2c pci_ctrl_info[] = {
+	[octopus_i2c] = {
+		.bus_num	= -1,
+		.bus_cfg	= IC_CON_MASTER | IC_CON_SLAVE_DISABLE |
+				  IC_CON_RESTART_EN | IC_CON_SPEED_FAST,
+		.tx_fifo_depth	= 7,
+		.rx_fifo_depth	= 7,
+		.functionality	= I2C_FUNC_10BIT_ADDR,
+		.clk_khz	= 48000000,
+		.scl_sda_cfg	= &octopus_config,
+		.setup		= octopus_setup,
+	},
+};
+
+#ifdef CONFIG_PM
+static int i2c_phytium_pci_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct phytium_i2c_dev *i_dev = pci_get_drvdata(pdev);
+
+	i_dev->disable(i_dev);
+
+	return 0;
+}
+
+static int i2c_phytium_pci_resume(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct phytium_i2c_dev *i_dev = pci_get_drvdata(pdev);
+
+	return i_dev->init(i_dev);
+}
+#endif
+
+static UNIVERSAL_DEV_PM_OPS(i2c_phytium_pm_ops, i2c_phytium_pci_suspend,
+			    i2c_phytium_pci_resume, NULL);
+
+static u32 i2c_phytium_get_clk_rate_khz(struct phytium_i2c_dev *dev)
+{
+	return dev->controller->clk_khz;
+}
+
+static int i2c_phytium_pci_probe(struct pci_dev *pdev,
+			    const struct pci_device_id *id)
+{
+	struct phytium_i2c_dev *dev;
+	struct i2c_adapter *adapter;
+	struct phytium_pci_i2c *controller;
+	struct scl_sda_cfg *cfg;
+	int ret;
+
+	if (id->driver_data >= ARRAY_SIZE(pci_ctrl_info)) {
+		dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
+			id->driver_data);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	controller = &pci_ctrl_info[id->driver_data];
+
+	ret = pcim_enable_device(pdev);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n", ret);
+		goto out;
+	}
+
+	ret = pcim_iomap_regions(pdev, 0x1, pci_name(pdev));
+	if (ret) {
+		dev_err(&pdev->dev, "I/O memory remapping failed\n");
+		goto out;
+	}
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(struct phytium_i2c_dev), GFP_KERNEL);
+	if (!dev) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	dev->controller = controller;
+	dev->get_clk_rate_khz = i2c_phytium_get_clk_rate_khz;
+	dev->base = pcim_iomap_table(pdev)[0];
+	dev->dev = &pdev->dev;
+	dev->irq = pdev->irq;
+	dev->flags |= controller->flags;
+
+	dev->functionality = controller->functionality | IC_DEFAULT_FUNCTIONALITY;
+	dev->master_cfg = controller->bus_cfg;
+	if (controller->scl_sda_cfg) {
+		cfg = controller->scl_sda_cfg;
+		dev->ss_hcnt = cfg->ss_hcnt;
+		dev->fs_hcnt = cfg->fs_hcnt;
+		dev->ss_lcnt = cfg->ss_lcnt;
+		dev->fs_lcnt = cfg->fs_lcnt;
+		dev->sda_hold_time = cfg->sda_hold;
+	}
+
+	pci_set_drvdata(pdev, dev);
+
+	dev->tx_fifo_depth = controller->tx_fifo_depth;
+	dev->rx_fifo_depth = controller->rx_fifo_depth;
+
+	adapter = &dev->adapter;
+	adapter->owner = THIS_MODULE;
+	adapter->class = 0;
+	ACPI_COMPANION_SET(&adapter->dev, ACPI_COMPANION(&pdev->dev));
+	adapter->nr = controller->bus_num;
+
+	ret = i2c_phytium_probe(dev);
+	if (ret)
+		goto out;
+
+	if (controller->setup) {
+		ret = controller->setup(pdev, controller);
+		if (ret)
+			goto out;
+	}
+
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_put_autosuspend(&pdev->dev);
+	pm_runtime_allow(&pdev->dev);
+
+out:
+	return ret;
+}
+
+static void i2c_phytium_pci_remove(struct pci_dev *pdev)
+{
+	struct phytium_i2c_dev *dev = pci_get_drvdata(pdev);
+
+	dev->disable(dev);
+	pm_runtime_forbid(&pdev->dev);
+	pm_runtime_get_noresume(&pdev->dev);
+
+	i2c_del_adapter(&dev->adapter);
+}
+
+static const struct pci_device_id i2_phytium_pci_ids[] = {
+	{ PCI_DEVICE(0x1db7, 0xdc32), 0, 0, octopus_i2c },
+	{ PCI_DEVICE(0x1db7, 0xdc30), 0, 0, octopus_i2c },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, i2_phytium_pci_ids);
+
+static struct pci_driver phytium_i2c_driver = {
+	.name		= DRV_NAME,
+	.id_table	= i2_phytium_pci_ids,
+	.probe		= i2c_phytium_pci_probe,
+	.remove		= i2c_phytium_pci_remove,
+	.driver         = {
+		.pm     = &i2c_phytium_pm_ops,
+	},
+};
+
+module_pci_driver(phytium_i2c_driver);
+
+MODULE_ALIAS("i2c-phytium-pci");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium PCI I2C bus adapter");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-platform.c b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-platform.c
new file mode 100644
index 00000000000000..cb13c287a788e9
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-platform.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Phytium I2C adapter driver.
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/acpi.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dmi.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/reset.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/suspend.h>
+
+#include "i2c-phytium-core.h"
+
+#define DRV_NAME "i2c-phytium-platform"
+
+static u32 i2c_phytium_get_clk_rate_khz(struct phytium_i2c_dev *dev)
+{
+	return clk_get_rate(dev->clk)/1000;
+}
+
+#ifdef CONFIG_ACPI
+static void phytium_i2c_acpi_params(struct platform_device *pdev, char method[],
+				    u16 *hcnt, u16 *lcnt, u32 *sda_hold)
+{
+	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
+	acpi_handle handle = ACPI_HANDLE(&pdev->dev);
+	union acpi_object *obj;
+
+	if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
+		return;
+
+	obj = (union acpi_object *)buf.pointer;
+	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
+		const union acpi_object *objs = obj->package.elements;
+
+		*hcnt = (u16)objs[0].integer.value;
+		*lcnt = (u16)objs[1].integer.value;
+		*sda_hold = (u32)objs[2].integer.value;
+	}
+
+	kfree(buf.pointer);
+}
+
+static int phytium_i2c_acpi_configure(struct platform_device *pdev)
+{
+	struct phytium_i2c_dev *dev = platform_get_drvdata(pdev);
+	struct i2c_timings *t = &dev->timings;
+	u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
+	acpi_handle handle = ACPI_HANDLE(&pdev->dev);
+	const struct acpi_device_id *id;
+	struct acpi_device *adev;
+
+	dev->adapter.nr = -1;
+	dev->tx_fifo_depth = 32;
+	dev->rx_fifo_depth = 32;
+
+	/*
+	 * Try to get SDA hold time and *CNT values from an ACPI method for
+	 * selected speed modes.
+	 */
+	phytium_i2c_acpi_params(pdev, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
+	phytium_i2c_acpi_params(pdev, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
+	phytium_i2c_acpi_params(pdev, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
+	phytium_i2c_acpi_params(pdev, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
+
+	switch (t->bus_freq_hz) {
+	case 100000:
+		dev->sda_hold_time = ss_ht;
+		break;
+	case 1000000:
+		dev->sda_hold_time = fp_ht;
+		break;
+	case 3400000:
+		dev->sda_hold_time = hs_ht;
+		break;
+	case 400000:
+	default:
+		dev->sda_hold_time = fs_ht;
+		break;
+	}
+
+	id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev);
+	if (id && id->driver_data)
+		dev->flags |= (u32)id->driver_data;
+
+	if (acpi_bus_get_device(handle, &adev))
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct acpi_device_id phytium_i2c_acpi_match[] = {
+	{ "PHYT0038", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, phytium_i2c_acpi_match);
+#else
+static inline int phytium_i2c_acpi_configure(struct platform_device *pdev)
+{
+	return -ENODEV;
+}
+#endif
+
+static void i2c_phytium_configure_master(struct phytium_i2c_dev *dev)
+{
+	struct i2c_timings *t = &dev->timings;
+
+	dev->functionality = I2C_FUNC_10BIT_ADDR | IC_DEFAULT_FUNCTIONALITY;
+
+	dev->master_cfg = IC_CON_MASTER | IC_CON_SLAVE_DISABLE |
+			  IC_CON_RESTART_EN;
+
+	dev->mode = PHYTIUM_IC_MASTER;
+
+	switch (t->bus_freq_hz) {
+	case 100000:
+		dev->master_cfg |= IC_CON_SPEED_STD;
+		break;
+	case 3400000:
+		dev->master_cfg |= IC_CON_SPEED_HIGH;
+		break;
+	default:
+		dev->master_cfg |= IC_CON_SPEED_FAST;
+	}
+}
+
+static void i2c_phytium_configure_slave(struct phytium_i2c_dev *dev)
+{
+	dev->functionality = I2C_FUNC_SLAVE | IC_DEFAULT_FUNCTIONALITY;
+
+	dev->slave_cfg = IC_CON_RX_FIFO_FULL_HLD_CTRL |
+			 IC_CON_RESTART_EN | IC_CON_STOP_DET_IFADDRESSED;
+
+	dev->mode = PHYTIUM_IC_SLAVE;
+}
+
+static int phytium_i2c_plat_probe(struct platform_device *pdev)
+{
+	struct i2c_adapter *adap;
+	struct phytium_i2c_dev *dev;
+	struct i2c_timings *t;
+	u32 acpi_speed;
+	struct resource *mem;
+	int irq, ret, i;
+	static const int supported_speeds[] = {
+		0, 100000, 400000, 1000000, 3400000
+	};
+
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(struct phytium_i2c_dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dev->base = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(dev->base))
+		return PTR_ERR(dev->base);
+
+	dev->dev = &pdev->dev;
+	dev->irq = irq;
+	platform_set_drvdata(pdev, dev);
+
+	dev->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(dev->rst)) {
+		if (PTR_ERR(dev->rst) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+	} else {
+		reset_control_deassert(dev->rst);
+	}
+
+	t = &dev->timings;
+	i2c_parse_fw_timings(&pdev->dev, t, false);
+
+	acpi_speed = i2c_acpi_find_bus_speed(&pdev->dev);
+	/*
+	 * Some DSTDs use a non standard speed, round down to the lowest
+	 * standard speed.
+	 */
+	for (i = 1; i < ARRAY_SIZE(supported_speeds); i++) {
+		if (acpi_speed < supported_speeds[i])
+			break;
+	}
+	acpi_speed = supported_speeds[i - 1];
+
+	/*
+	 * Find bus speed from the "clock-frequency" device property, ACPI
+	 * or by using fast mode if neither is set.
+	 */
+	if (acpi_speed && t->bus_freq_hz)
+		t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
+	else if (acpi_speed || t->bus_freq_hz)
+		t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
+	else
+		t->bus_freq_hz = 400000;
+
+	if (has_acpi_companion(&pdev->dev))
+		phytium_i2c_acpi_configure(pdev);
+
+	/*
+	 * Only standard mode at 100kHz, fast mode at 400kHz,
+	 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
+	 */
+	if (t->bus_freq_hz != 100000 && t->bus_freq_hz != 400000 &&
+	    t->bus_freq_hz != 1000000 && t->bus_freq_hz != 3400000) {
+		dev_err(&pdev->dev,
+			"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
+			t->bus_freq_hz);
+		ret = -EINVAL;
+		goto exit_reset;
+	}
+
+	if (i2c_detect_slave_mode(&pdev->dev))
+		i2c_phytium_configure_slave(dev);
+	else
+		i2c_phytium_configure_master(dev);
+
+	dev->clk = devm_clk_get(&pdev->dev, NULL);
+	if (!i2c_phytium_prepare_clk(dev, true)) {
+		u64 clk_khz;
+
+		dev->get_clk_rate_khz = i2c_phytium_get_clk_rate_khz;
+		clk_khz = dev->get_clk_rate_khz(dev);
+
+		if (!dev->sda_hold_time && t->sda_hold_ns)
+			dev->sda_hold_time =
+				div_u64(clk_khz * t->sda_hold_ns + 500000, 1000000);
+	}
+
+	dev->tx_fifo_depth = 7;
+	dev->rx_fifo_depth = 7;
+	dev->adapter.nr = pdev->id;
+
+	adap = &dev->adapter;
+	adap->owner = THIS_MODULE;
+	adap->class = I2C_CLASS_DEPRECATED;
+	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
+	adap->dev.of_node = pdev->dev.of_node;
+
+	dev_pm_set_driver_flags(&pdev->dev,
+				DPM_FLAG_SMART_PREPARE |
+				DPM_FLAG_SMART_SUSPEND |
+				DPM_FLAG_MAY_SKIP_RESUME);
+
+	/* The code below assumes runtime PM to be disabled. */
+	WARN_ON(pm_runtime_enabled(&pdev->dev));
+
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_set_active(&pdev->dev);
+
+	pm_runtime_enable(&pdev->dev);
+
+	if (dev->mode == PHYTIUM_IC_SLAVE)
+		ret = i2c_phytium_probe_slave(dev);
+	else
+		ret = i2c_phytium_probe(dev);
+
+	if (ret)
+		goto exit_probe;
+
+	return ret;
+
+exit_probe:
+	pm_runtime_disable(dev->dev);
+exit_reset:
+	if (!IS_ERR_OR_NULL(dev->rst))
+		reset_control_assert(dev->rst);
+	return ret;
+}
+
+static int phytium_i2c_plat_remove(struct platform_device *pdev)
+{
+	struct phytium_i2c_dev *dev = platform_get_drvdata(pdev);
+
+	pm_runtime_get_sync(&pdev->dev);
+
+	i2c_del_adapter(&dev->adapter);
+
+	dev->disable(dev);
+
+	pm_runtime_dont_use_autosuspend(&pdev->dev);
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(dev->dev);
+
+	if (!IS_ERR_OR_NULL(dev->rst))
+		reset_control_assert(dev->rst);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id phytium_i2c_of_match[] = {
+	{ .compatible = "phytium,i2c", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, phytium_i2c_of_match);
+#endif
+
+static int __maybe_unused phytium_i2c_plat_suspend(struct device *dev)
+{
+	struct phytium_i2c_dev *idev = dev_get_drvdata(dev);
+
+	idev->disable(idev);
+	i2c_phytium_prepare_clk(idev, false);
+
+	return 0;
+}
+
+static int __maybe_unused phytium_i2c_plat_resume(struct device *dev)
+{
+	struct phytium_i2c_dev *idev = dev_get_drvdata(dev);
+
+	i2c_phytium_prepare_clk(idev, true);
+
+	idev->init(idev);
+
+	return 0;
+}
+
+static const struct dev_pm_ops phytium_i2c_dev_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(phytium_i2c_plat_suspend,
+				     phytium_i2c_plat_resume)
+	SET_RUNTIME_PM_OPS(phytium_i2c_plat_suspend,
+			   phytium_i2c_plat_resume, NULL)
+};
+
+static struct platform_driver phytium_i2c_driver = {
+	.probe = phytium_i2c_plat_probe,
+	.remove = phytium_i2c_plat_remove,
+	.driver = {
+		.name = DRV_NAME,
+		.of_match_table = of_match_ptr(phytium_i2c_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_i2c_acpi_match),
+		.pm = &phytium_i2c_dev_pm_ops,
+	},
+};
+module_platform_driver(phytium_i2c_driver);
+
+MODULE_ALIAS("platform:i2c-phytium");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium I2C bus adapter");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-slave.c b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-slave.c
new file mode 100644
index 00000000000000..a9409f55c6522e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/i2c/busses/i2c-phytium-slave.c
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium I2C adapter driver (slave only).
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+
+#include "i2c-phytium-core.h"
+
+static void i2c_phytium_configure_fifo_slave(struct phytium_i2c_dev *dev)
+{
+	/* Configure Tx/Rx FIFO threshold levels. */
+	phytium_writel(dev, 0, IC_TX_TL);
+	phytium_writel(dev, 0, IC_RX_TL);
+
+	/* Configure the I2C slave. */
+	phytium_writel(dev, dev->slave_cfg, IC_CON);
+	phytium_writel(dev, IC_INTR_SLAVE_MASK, IC_INTR_MASK);
+}
+
+static int i2c_phytium_init_slave(struct phytium_i2c_dev *dev)
+{
+	/* Disable the adapter. */
+	__i2c_phytium_disable(dev);
+
+	/* Write SDA hold time if supported */
+	if (dev->sda_hold_time)
+		phytium_writel(dev, dev->sda_hold_time, IC_SDA_HOLD);
+
+	i2c_phytium_configure_fifo_slave(dev);
+
+	return 0;
+}
+
+static int i2c_phytium_reg_slave(struct i2c_client *slave)
+{
+	struct phytium_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
+
+	if (dev->slave)
+		return -EBUSY;
+	if (slave->flags & I2C_CLIENT_TEN)
+		return -EAFNOSUPPORT;
+	pm_runtime_get_sync(dev->dev);
+
+	/*
+	 * Set slave address in the IC_SAR register,
+	 * the address to which the i2c responds.
+	 */
+	__i2c_phytium_disable_nowait(dev);
+	phytium_writel(dev, slave->addr, IC_SAR);
+	dev->slave = slave;
+
+	__i2c_phytium_enable(dev);
+
+	dev->cmd_err = 0;
+	dev->msg_write_idx = 0;
+	dev->msg_read_idx = 0;
+	dev->msg_err = 0;
+	dev->status = STATUS_IDLE;
+	dev->abort_source = 0;
+	dev->rx_outstanding = 0;
+
+	return 0;
+}
+
+static int i2c_phytium_unreg_slave(struct i2c_client *slave)
+{
+	struct phytium_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
+
+	dev->disable_int(dev);
+	dev->disable(dev);
+	dev->slave = NULL;
+	pm_runtime_put(dev->dev);
+
+	return 0;
+}
+
+static u32 i2c_phytium_read_clear_intrbits_slave(struct phytium_i2c_dev *dev)
+{
+	u32 stat;
+
+	/*
+	 * The IC_INTR_STAT register just indicates "enabled" interrupts.
+	 * Ths unmasked raw version of interrupt status bits are available
+	 * in the IC_RAW_INTR_STAT register.
+	 *
+	 * That is,
+	 *   stat = phytium_readl(IC_INTR_STAT);
+	 * equals to,
+	 *   stat = phytium_readl(IC_RAW_INTR_STAT) & phytium_readl(IC_INTR_MASK);
+	 *
+	 * The raw version might be useful for debugging purposes.
+	 */
+	stat = phytium_readl(dev, IC_INTR_STAT);
+
+	/*
+	 * Do not use the IC_CLR_INTR register to clear interrupts, or
+	 * you'll miss some interrupts, triggered during the period from
+	 * phytium_readl(IC_INTR_STAT) to phytium_readl(IC_CLR_INTR).
+	 *
+	 * Instead, use the separately-prepared IC_CLR_* registers.
+	 */
+	if (stat & IC_INTR_TX_ABRT)
+		phytium_readl(dev, IC_CLR_TX_ABRT);
+	if (stat & IC_INTR_RX_UNDER)
+		phytium_readl(dev, IC_CLR_RX_UNDER);
+	if (stat & IC_INTR_RX_OVER)
+		phytium_readl(dev, IC_CLR_RX_OVER);
+	if (stat & IC_INTR_TX_OVER)
+		phytium_readl(dev, IC_CLR_TX_OVER);
+	if (stat & IC_INTR_RX_DONE)
+		phytium_readl(dev, IC_CLR_RX_DONE);
+	if (stat & IC_INTR_ACTIVITY)
+		phytium_readl(dev, IC_CLR_ACTIVITY);
+	if (stat & IC_INTR_STOP_DET)
+		phytium_readl(dev, IC_CLR_STOP_DET);
+	if (stat & IC_INTR_START_DET)
+		phytium_readl(dev, IC_CLR_START_DET);
+	if (stat & IC_INTR_GEN_CALL)
+		phytium_readl(dev, IC_CLR_GEN_CALL);
+
+	return stat;
+}
+
+/*
+ * Interrupt service routine. This gets called whenever an I2C slave interrupt
+ * occurs.
+ */
+static int i2c_phytium_irq_handler_slave(struct phytium_i2c_dev *dev)
+{
+	u32 raw_stat, stat, enabled;
+	u8 val, slave_activity;
+
+	stat = phytium_readl(dev, IC_INTR_STAT);
+	enabled = phytium_readl(dev, IC_ENABLE);
+	raw_stat = phytium_readl(dev, IC_RAW_INTR_STAT);
+	slave_activity = ((phytium_readl(dev, IC_STATUS) &
+		IC_STATUS_SLAVE_ACTIVITY) >> 6);
+
+	if (!enabled || !(raw_stat & ~IC_INTR_ACTIVITY) || !dev->slave)
+		return 0;
+
+	dev_dbg(dev->dev,
+		"%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n",
+		enabled, slave_activity, raw_stat, stat);
+
+	if ((stat & IC_INTR_RX_FULL) && (stat & IC_INTR_STOP_DET))
+		i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val);
+
+	if (stat & IC_INTR_RD_REQ) {
+		if (slave_activity) {
+			if (stat & IC_INTR_RX_FULL) {
+				val = phytium_readl(dev, IC_DATA_CMD);
+
+				if (!i2c_slave_event(dev->slave,
+						     I2C_SLAVE_WRITE_RECEIVED,
+						     &val)) {
+					dev_vdbg(dev->dev, "Byte %X acked!",
+						 val);
+				}
+				phytium_readl(dev, IC_CLR_RD_REQ);
+				stat = i2c_phytium_read_clear_intrbits_slave(dev);
+			} else {
+				phytium_readl(dev, IC_CLR_RD_REQ);
+				phytium_readl(dev, IC_CLR_RX_UNDER);
+				stat = i2c_phytium_read_clear_intrbits_slave(dev);
+			}
+			if (!i2c_slave_event(dev->slave,
+					     I2C_SLAVE_READ_REQUESTED,
+					     &val))
+				phytium_writel(dev, val, IC_DATA_CMD);
+		}
+	}
+
+	if (stat & IC_INTR_RX_DONE) {
+		if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
+				     &val))
+			phytium_readl(dev, IC_CLR_RX_DONE);
+
+		i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
+		stat = i2c_phytium_read_clear_intrbits_slave(dev);
+		return 1;
+	}
+
+	if (stat & IC_INTR_RX_FULL) {
+		val = phytium_readl(dev, IC_DATA_CMD);
+		if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
+				     &val))
+			dev_vdbg(dev->dev, "Byte %X acked!", val);
+	} else {
+		i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
+		stat = i2c_phytium_read_clear_intrbits_slave(dev);
+	}
+
+	return 1;
+}
+
+static irqreturn_t i2c_phytium_isr_slave(int this_irq, void *dev_id)
+{
+	struct phytium_i2c_dev *dev = dev_id;
+	int ret;
+
+	i2c_phytium_read_clear_intrbits_slave(dev);
+	ret = i2c_phytium_irq_handler_slave(dev);
+	if (ret > 0)
+		complete(&dev->cmd_complete);
+
+	return IRQ_RETVAL(ret);
+}
+
+static const struct i2c_algorithm i2c_phytium_algo = {
+	.functionality = i2c_phytium_func,
+	.reg_slave = i2c_phytium_reg_slave,
+	.unreg_slave = i2c_phytium_unreg_slave,
+};
+
+int i2c_phytium_probe_slave(struct phytium_i2c_dev *dev)
+{
+	struct i2c_adapter *adap = &dev->adapter;
+	int ret;
+
+	init_completion(&dev->cmd_complete);
+
+	dev->init = i2c_phytium_init_slave;
+	dev->disable = i2c_phytium_disable;
+	dev->disable_int = i2c_phytium_disable_int;
+
+	ret = dev->init(dev);
+	if (ret)
+		return ret;
+
+	snprintf(adap->name, sizeof(adap->name),
+		 "Phytium I2C Slave adapter");
+	adap->retries = 3;
+	adap->algo = &i2c_phytium_algo;
+	adap->dev.parent = dev->dev;
+	i2c_set_adapdata(adap, dev);
+
+	ret = devm_request_irq(dev->dev, dev->irq, i2c_phytium_isr_slave,
+			       IRQF_SHARED, dev_name(dev->dev), dev);
+	if (ret) {
+		dev_err(dev->dev, "failure requesting irq %i: %d\n",
+			dev->irq, ret);
+		return ret;
+	}
+
+	ret = i2c_add_numbered_adapter(adap);
+	if (ret)
+		dev_err(dev->dev, "failure adding adapter: %d\n", ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i2c_phytium_probe_slave);
diff --git a/target/linux/phytium/files-5.10/drivers/iio/adc/phytium-adc.c b/target/linux/phytium/files-5.10/drivers/iio/adc/phytium-adc.c
new file mode 100755
index 00000000000000..b9d8923c9179dc
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/iio/adc/phytium-adc.c
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium ADC device driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/events.h>
+#include <linux/iio/buffer.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/triggered_buffer.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iio/sysfs.h>
+
+/* ADC register */
+#define ADC_CTRL_REG				0x00
+#define   ADC_CTRL_REG_PD_EN			BIT(31)
+#define   ADC_CTRL_REG_CH_ONLY_S(x)		((x & 0x7) << 16)
+#define   ADC_CTRL_REG_CLK_DIV(x)		((x) << 12)
+#define   ADC_CTRL_REG_CHANNEL_EN(x)		BIT((x) + 4)
+#define   ADC_CTRL_REG_CH_ONLY_EN		BIT(3)
+#define   ADC_CTRL_REG_SINGLE_EN		BIT(2)
+#define   ADC_CTRL_REG_SINGLE_SEL		BIT(1)
+#define   ADC_CTRL_REG_SOC_EN			BIT(0)
+#define ADC_INTER_REG				0x04
+#define ADC_STATE_REG				0x08
+#define   ADC_STATE_REG_B_STA(x)		((x) << 8)
+#define   ADC_STATE_REG_EOC_STA			BIT(7)
+#define   ADC_STATE_REG_S_STA(x)		((x) << 4)
+#define   ADC_STATE_REG_SOC_STA			BIT(3)
+#define   ADC_STATE_REG_ERR_STA			BIT(2)
+#define   ADC_STATE_REG_COV_FINISH_STA		BIT(1)
+#define   ADC_STATE_REG_ADCCTL_BUSY_STA		BIT(0)
+#define ADC_ERRCLR_REG				0x0c
+#define ADC_LEVEL_REG(x)			(0x10 + ((x) << 2))
+#define   ADC_LEVEL_REG_HIGH_LEVEL(x)		((x) << 16)
+#define   ADC_LEVEL_REG_LOW_LEVEL(x)		(x)
+#define ADC_INTRMASK_REG			0x30
+#define   ADC_INTRMASK_REG_ERR_INTR_MASK	BIT(24)
+#define   ADC_INTRMASK_REG_ULIMIT_OFF(x)	BIT(9 + ((x) << 1))
+#define   ADC_INTRMASK_REG_DLIMIT_MASK(x)	BIT(8 + ((x) << 1))
+#define   ADC_INTRMASK_REG_COVFIN_MASK(x)	BIT((x))
+#define ADC_INTR_REG				0x34
+#define   ADC_INTR_REG_ERR			BIT(24)
+#define   ADC_INTR_REG_ULIMIT(x)		BIT(9 + ((x) << 1))
+#define   ADC_INTR_REG_DLIMIT(x)		BIT(8 + ((x) << 1))
+#define   ADC_INTR_REG_LIMIT_MASK		GENMASK(23, 8)
+#define   ADC_INTR_REG_COVFIN(x)		BIT((x))
+#define   ADC_INTR_REG_COVFIN_MASK		GENMASK(7, 0)
+#define ADC_COV_RESULT_REG(x)			(0x38 + ((x) << 2))
+#define   ADC_COV_RESULT_REG_MASK		GENMASK(9, 0)
+#define ADC_FINISH_CNT_REG(x)			(0x58 + ((x) << 2))
+#define ADC_HIS_LIMIT_REG(x)			(0x78 + ((x) << 2))
+
+#define PHYTIUM_MAX_CHANNELS	8
+#define PHYTIUM_ADC_TIMEOUT	usecs_to_jiffies(1000 * 1000)
+
+static const struct iio_event_spec phytium_adc_event[] = {
+	{
+		.type = IIO_EV_TYPE_THRESH,
+		.dir = IIO_EV_DIR_RISING,
+		.mask_separate = BIT(IIO_EV_INFO_VALUE),
+	}, {
+		.type = IIO_EV_TYPE_THRESH,
+		.dir = IIO_EV_DIR_FALLING,
+		.mask_separate = BIT(IIO_EV_INFO_VALUE),
+	},
+};
+
+struct phytium_adc_data {
+	const struct iio_chan_spec *channels;
+	u8 num_channels;
+};
+
+struct phytium_adc {
+	struct device *dev;
+	void __iomem *regs;
+	struct clk *adc_clk;
+
+	u32 interval;
+	u16 thresh_high[PHYTIUM_MAX_CHANNELS];
+	u16 thresh_low[PHYTIUM_MAX_CHANNELS];
+	u16 last_val[PHYTIUM_MAX_CHANNELS];
+	const struct phytium_adc_data *data;
+	u16 *scan_data;
+
+	struct completion completion;
+	struct mutex lock;
+};
+
+static ssize_t phytium_adc_show_conv_interval(struct iio_dev *indio_dev,
+					      uintptr_t priv,
+					      struct iio_chan_spec const *ch,
+					      char *buf)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+
+	return sprintf(buf, "%u\n", adc->interval);
+}
+
+static ssize_t phytium_adc_store_conv_interval(struct iio_dev *indio_dev,
+					       uintptr_t priv,
+					       struct iio_chan_spec const *ch,
+					       const char *buf, size_t len)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	u32 interval;
+	int ret;
+
+	ret = kstrtou32(buf, 0, &interval);
+	if (ret < 0)
+		return ret;
+
+	mutex_lock(&adc->lock);
+	adc->interval = interval;
+	mutex_unlock(&adc->lock);
+
+	return len;
+}
+
+static const struct iio_chan_spec_ext_info phytium_adc_ext_info[] = {
+	{
+		.name  = "conv_interval",
+		.read  = phytium_adc_show_conv_interval,
+		.write = phytium_adc_store_conv_interval,
+	},
+	{ /* sentinel */ }
+};
+
+static int phytium_adc_parse_properties(struct platform_device *pdev, struct phytium_adc *adc)
+{
+	struct iio_chan_spec *chan_array;
+	struct fwnode_handle *fwnode;
+	struct phytium_adc_data *data;
+	unsigned int channel;
+	int num_channels;
+	int ret, i = 0;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	num_channels = device_get_child_node_count(&pdev->dev);
+	if (!num_channels) {
+		dev_err(&pdev->dev, "no channel children\n");
+		return -ENODEV;
+	}
+
+	if (num_channels > PHYTIUM_MAX_CHANNELS) {
+		dev_err(&pdev->dev, "num of channel children out of range\n");
+		return -EINVAL;
+	}
+
+	chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),
+				  GFP_KERNEL);
+	if (!chan_array)
+		return -ENOMEM;
+
+	device_for_each_child_node(&pdev->dev, fwnode) {
+		ret = fwnode_property_read_u32(fwnode, "reg", &channel);
+		if (ret)
+			return ret;
+
+		if (channel >= PHYTIUM_MAX_CHANNELS)
+			return -EINVAL;
+
+		chan_array[i].type = IIO_VOLTAGE;
+		chan_array[i].indexed = 1;
+		chan_array[i].channel = channel;
+		chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
+		chan_array[i].event_spec = phytium_adc_event;
+		chan_array[i].num_event_specs = ARRAY_SIZE(phytium_adc_event);
+		chan_array[i].scan_index = channel;
+		chan_array[i].scan_type.sign = 'u';
+		chan_array[i].scan_type.realbits = 10;
+		chan_array[i].scan_type.storagebits = 16;
+		chan_array[i].scan_type.endianness = IIO_LE;
+		chan_array[i].ext_info = phytium_adc_ext_info;
+		i++;
+	}
+
+	data->num_channels = num_channels;
+	data->channels = chan_array;
+	adc->data = data;
+
+	return 0;
+}
+
+static void phytium_adc_start_stop(struct phytium_adc *adc, bool start)
+{
+	u32 ctrl;
+
+	ctrl = readl(adc->regs + ADC_CTRL_REG);
+	if (start)
+		ctrl |= ADC_CTRL_REG_SOC_EN | ADC_CTRL_REG_SINGLE_EN;
+	else
+		ctrl &= ~ADC_CTRL_REG_SOC_EN;
+	/* Start conversion */
+	writel(ctrl, adc->regs + ADC_CTRL_REG);
+}
+
+static void phytium_adc_power_setup(struct phytium_adc *adc, bool on)
+{
+	u32 reg;
+
+	reg = readl(adc->regs + ADC_CTRL_REG);
+	if (on)
+		reg &= ~ADC_CTRL_REG_PD_EN;
+	else
+		reg |= ADC_CTRL_REG_PD_EN;
+	writel(reg, adc->regs + ADC_CTRL_REG);
+}
+
+static int phytium_adc_hw_init(struct phytium_adc *adc)
+{
+	int ret;
+	u32 reg;
+
+	ret = clk_prepare_enable(adc->adc_clk);
+	if (ret)
+		return ret;
+
+	/*
+	 * Setup ctrl register:
+	 * - Power up conversion module
+	 * - Set the division by 4 as default
+	 */
+	reg = ADC_CTRL_REG_CLK_DIV(4);
+	writel(reg, adc->regs + ADC_CTRL_REG);
+
+	/* Set all the interrupt mask, unmask them when necessary. */
+	writel(0x1ffffff, adc->regs + ADC_INTRMASK_REG);
+
+	/* Set default conversion interval */
+	adc->interval = (clk_get_rate(adc->adc_clk) * 1000) / NSEC_PER_SEC;
+
+	phytium_adc_power_setup(adc, true);
+
+	return 0;
+}
+
+static void phytium_adc_intrmask_setup(struct phytium_adc *adc, unsigned long chan_mask, bool on)
+{
+	u32 reg;
+	u16 limit_mask = 0;
+	int ch;
+
+	for_each_set_bit(ch, &chan_mask, PHYTIUM_MAX_CHANNELS)
+		limit_mask |= BIT(ch << 1) | BIT((ch << 1) + 1);
+
+	reg = readl(adc->regs + ADC_INTRMASK_REG);
+	if (on)
+		reg &= ~(ADC_INTRMASK_REG_ERR_INTR_MASK |
+			 (limit_mask << 8) | chan_mask);
+	else
+		reg |= (ADC_INTRMASK_REG_ERR_INTR_MASK |
+			(limit_mask << 8) | chan_mask);
+	writel(reg, adc->regs + ADC_INTRMASK_REG);
+}
+
+static void phytium_adc_single_conv_setup(struct phytium_adc *adc, u8 ch)
+{
+	u32 reg;
+
+	/*
+	 * Setup control register:
+	 * - Single conversion mode selection
+	 * - Single conversion enable
+	 * - Fixed channel conversion
+	 * - Target channel
+	 */
+	reg = readl(adc->regs + ADC_CTRL_REG);
+
+	/* Clean ch_only_s bits */
+	reg &= ~ADC_CTRL_REG_CH_ONLY_S(7);
+
+	/* Clean channel_en bit */
+	reg &= 0xFFF00F;
+
+	reg |=  ADC_CTRL_REG_SINGLE_SEL | ADC_CTRL_REG_SINGLE_EN |
+		ADC_CTRL_REG_CH_ONLY_EN | ADC_CTRL_REG_CH_ONLY_S(ch) | ADC_CTRL_REG_CHANNEL_EN(ch);
+	writel(reg, adc->regs + ADC_CTRL_REG);
+}
+
+static int phytium_adc_single_conv(struct iio_dev *indio_dev, u8 ch)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	int ret;
+
+	ret = iio_device_claim_direct_mode(indio_dev);
+	if (ret)
+		return ret;
+	mutex_lock(&adc->lock);
+
+	phytium_adc_intrmask_setup(adc, BIT(ch), true);
+	reinit_completion(&adc->completion);
+	phytium_adc_single_conv_setup(adc, ch);
+	phytium_adc_start_stop(adc, true);
+
+	if (!wait_for_completion_timeout(&adc->completion, PHYTIUM_ADC_TIMEOUT))
+		ret = -ETIMEDOUT;
+
+	phytium_adc_start_stop(adc, false);
+	phytium_adc_intrmask_setup(adc, BIT(ch), false);
+
+	mutex_unlock(&adc->lock);
+	iio_device_release_direct_mode(indio_dev);
+
+	return ret;
+}
+
+static int phytium_adc_read_raw(struct iio_dev *indio_dev,
+				struct iio_chan_spec const *chan,
+				int *val, int *val2, long mask)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	int ret;
+
+	switch (mask) {
+	case IIO_CHAN_INFO_RAW:
+		if (chan->type != IIO_VOLTAGE)
+			return -EINVAL;
+
+		ret = phytium_adc_single_conv(indio_dev, chan->channel);
+		if (ret)
+			return ret;
+		*val = adc->last_val[chan->channel];
+
+		return IIO_VAL_INT;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int phytium_read_thresh(struct iio_dev *indio_dev,
+			       const struct iio_chan_spec *chan,
+			       enum iio_event_type type,
+			       enum iio_event_direction dir,
+			       enum iio_event_info iinfo, int *val, int *val2)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+
+	if (dir == IIO_EV_DIR_FALLING)
+		*val = adc->thresh_low[chan->channel];
+	else
+		*val = adc->thresh_high[chan->channel];
+
+	return IIO_VAL_INT;
+}
+
+static int phytium_write_thresh(struct iio_dev *indio_dev,
+				     const struct iio_chan_spec *chan,
+				     enum iio_event_type type,
+				     enum iio_event_direction dir,
+				     enum iio_event_info einfo, int val, int val2)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	u32 thresh;
+
+	switch (dir) {
+	case IIO_EV_DIR_FALLING:
+		adc->thresh_low[chan->channel] = val;
+		thresh = readl(adc->regs + ADC_LEVEL_REG(chan->channel)) & 0x3ff0000;
+		thresh |= ADC_LEVEL_REG_LOW_LEVEL(val);
+		writel(thresh, adc->regs + ADC_LEVEL_REG(chan->channel));
+		break;
+	case IIO_EV_DIR_RISING:
+		adc->thresh_high[chan->channel] = val;
+		thresh = readl(adc->regs + ADC_LEVEL_REG(chan->channel)) & 0xffff;
+		thresh |= ADC_LEVEL_REG_HIGH_LEVEL(val);
+		writel(thresh, adc->regs + ADC_LEVEL_REG(chan->channel));
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int phytium_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *mask)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	unsigned int n;
+
+	n = bitmap_weight(mask, indio_dev->masklength);
+
+	kfree(adc->scan_data);
+	adc->scan_data = kcalloc(n, sizeof(*adc->scan_data), GFP_KERNEL);
+	if (!adc->scan_data)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static const u64 phytium_adc_event_codes[] = {
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 4,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 4,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 5,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 5,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 6,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 6,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 7,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
+	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 7,
+			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
+};
+
+static irqreturn_t phytium_adc_threaded_irq(int irq, void *data)
+{
+	struct iio_dev *indio_dev = data;
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	s64 timestamp = iio_get_time_ns(indio_dev);
+	unsigned long status;
+	int ch;
+	u32 intr;
+
+	intr = readl(adc->regs + ADC_INTR_REG);
+
+	if (intr & ADC_INTR_REG_ERR) {
+		dev_err(adc->dev, "conversion error: ADC_INTR_REG(0x%x)\n", intr);
+		writel(ADC_INTR_REG_ERR, adc->regs + ADC_INTR_REG);
+		return IRQ_HANDLED;
+	}
+
+	status = (intr & ADC_INTR_REG_LIMIT_MASK) >> 8;
+	if (status) {
+		for_each_set_bit(ch, &status, PHYTIUM_MAX_CHANNELS * 2)
+			iio_push_event(indio_dev, phytium_adc_event_codes[ch], timestamp);
+	}
+
+	status = intr & ADC_INTR_REG_COVFIN_MASK;
+	if (status) {
+		for_each_set_bit(ch, &status, PHYTIUM_MAX_CHANNELS)
+			adc->last_val[ch] = readl(adc->regs + ADC_COV_RESULT_REG(ch)) &
+					    ADC_COV_RESULT_REG_MASK;
+
+		if (iio_buffer_enabled(indio_dev))
+			iio_trigger_poll(indio_dev->trig);
+		else
+			complete(&adc->completion);
+	}
+
+	/* Clear all the interrupts */
+	writel(status, adc->regs + ADC_INTR_REG);
+
+	return IRQ_HANDLED;
+}
+
+static void phytium_adc_cont_conv_setup(struct phytium_adc *adc,
+					unsigned long chan_mask,
+					u32 interval)
+{
+	u32 reg;
+
+	/*
+	 * Setup control register:
+	 * - Continuous conversion mode
+	 * - Multi-channel rotation mode
+	 * - Channel enablement
+	 */
+	reg = readl(adc->regs + ADC_CTRL_REG);
+	reg &= ~(ADC_CTRL_REG_SINGLE_SEL | ADC_CTRL_REG_SINGLE_EN |
+		 ADC_CTRL_REG_CH_ONLY_EN);
+	reg |= chan_mask << 4;
+	writel(reg, adc->regs + ADC_CTRL_REG);
+
+	/* Setup interval between two conversions */
+	writel(interval, adc->regs + ADC_INTER_REG);
+}
+
+static int phytium_adc_preenable(struct iio_dev *indio_dev)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	unsigned long scan_mask = *indio_dev->active_scan_mask;
+
+	phytium_adc_cont_conv_setup(adc, scan_mask & 0xff, adc->interval);
+	phytium_adc_intrmask_setup(adc, scan_mask & 0xff, true);
+
+	return 0;
+}
+
+static int phytium_adc_postenable(struct iio_dev *indio_dev)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+
+	phytium_adc_start_stop(adc, true);
+
+	return 0;
+}
+
+static int phytium_adc_postdisable(struct iio_dev *indio_dev)
+{
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	unsigned long scan_mask = *indio_dev->active_scan_mask;
+
+	phytium_adc_start_stop(adc, false);
+	phytium_adc_intrmask_setup(adc, scan_mask & 0xff, false);
+
+	return 0;
+}
+
+static const struct iio_buffer_setup_ops phytium_buffer_setup_ops = {
+	.preenable = &phytium_adc_preenable,
+	.postenable = &phytium_adc_postenable,
+	.postdisable = &phytium_adc_postdisable,
+};
+
+static irqreturn_t phytium_adc_trigger_handler(int irq, void *p)
+{
+	struct iio_poll_func *pf = p;
+	struct iio_dev *indio_dev = pf->indio_dev;
+	struct phytium_adc *adc = iio_priv(indio_dev);
+	int i, j = 0;
+
+	if (!adc->scan_data)
+		goto out;
+
+	for_each_set_bit(i, indio_dev->active_scan_mask, indio_dev->masklength)
+		adc->scan_data[j++] = adc->last_val[i];
+
+	iio_push_to_buffers(indio_dev, adc->scan_data);
+
+out:
+	iio_trigger_notify_done(indio_dev->trig);
+
+	return IRQ_HANDLED;
+}
+
+static const struct iio_info phytium_adc_iio_info = {
+	.read_raw = &phytium_adc_read_raw,
+	.read_event_value = &phytium_read_thresh,
+	.write_event_value = &phytium_write_thresh,
+	.update_scan_mode = &phytium_update_scan_mode,
+};
+
+static int phytium_adc_probe(struct platform_device *pdev)
+{
+	struct phytium_adc *adc;
+	struct iio_dev *indio_dev;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	int ret;
+
+	indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
+	if (!indio_dev)
+		return -ENOMEM;
+
+	adc = iio_priv(indio_dev);
+	adc->dev = dev;
+
+	ret = phytium_adc_parse_properties(pdev, adc);
+	if (ret)
+		return ret;
+
+	mutex_init(&adc->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	adc->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(adc->regs))
+		return PTR_ERR(adc->regs);
+
+	adc->adc_clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(adc->adc_clk))
+		return PTR_ERR(adc->adc_clk);
+
+	init_completion(&adc->completion);
+
+	indio_dev->name = dev_name(dev);
+	indio_dev->info = &phytium_adc_iio_info;
+	indio_dev->modes = INDIO_DIRECT_MODE;
+	indio_dev->channels = adc->data->channels;
+	indio_dev->num_channels = adc->data->num_channels;
+
+	platform_set_drvdata(pdev, indio_dev);
+
+	ret = devm_request_threaded_irq(adc->dev, platform_get_irq(pdev, 0),
+					NULL, phytium_adc_threaded_irq, IRQF_ONESHOT,
+					dev_name(dev), indio_dev);
+	if (ret)
+		return ret;
+
+	ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
+					      &iio_pollfunc_store_time,
+					      phytium_adc_trigger_handler,
+					      &phytium_buffer_setup_ops);
+	if (ret)
+		return ret;
+
+	ret = phytium_adc_hw_init(adc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to initialize Phytium ADC, %d\n", ret);
+		return ret;
+	}
+
+	return iio_device_register(indio_dev);
+}
+
+static int phytium_adc_remove(struct platform_device *pdev)
+{
+	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+	struct phytium_adc *adc = iio_priv(indio_dev);
+
+	phytium_adc_power_setup(adc, false);
+	iio_device_unregister(indio_dev);
+	kfree(adc->scan_data);
+
+	return 0;
+}
+
+static const struct of_device_id phytium_of_match[] = {
+	{ .compatible = "phytium,adc", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, phytium_of_match);
+
+#ifdef CONFIG_PM
+static int phytium_adc_suspend(struct device *dev)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct phytium_adc *adc = iio_priv(indio_dev);
+
+	phytium_adc_power_setup(adc, false);
+	clk_disable_unprepare(adc->adc_clk);
+
+	return 0;
+}
+
+static int phytium_adc_resume(struct device *dev)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct phytium_adc *adc = iio_priv(indio_dev);
+
+	clk_prepare_enable(adc->adc_clk);
+	phytium_adc_power_setup(adc, true);
+
+	return 0;
+}
+#endif
+
+SIMPLE_DEV_PM_OPS(phytium_adc_pm_ops, phytium_adc_suspend, phytium_adc_resume);
+
+static struct platform_driver phytium_adc_driver = {
+	.driver		= {
+		.name		= "phytium_adc",
+		.of_match_table	= phytium_of_match,
+		.pm		= &phytium_adc_pm_ops,
+	},
+	.probe		= phytium_adc_probe,
+	.remove		= phytium_adc_remove,
+};
+module_platform_driver(phytium_adc_driver);
+
+MODULE_AUTHOR("Yang Liu <yangliu2021@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium ADC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/input/keyboard/phytium-keypad.c b/target/linux/phytium/files-5.10/drivers/input/keyboard/phytium-keypad.c
new file mode 100644
index 00000000000000..e5ae4a27c587c8
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/input/keyboard/phytium-keypad.c
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Phytium keypad port.
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/acpi.h>
+
+/*
+ * Keypad Controller registers
+ */
+#define KPCR		0x00 /* Keypad Control Register */
+
+#define KPSR		0x04 /* Keypad Status Register */
+#define KBD_STAT_KPKD	(0x1 << 0) /* Key Press Interrupt Status bit (w1c) */
+#define KBD_STAT_KPKR	(0x1 << 1) /* Key Release Interrupt Status bit (w1c) */
+#define KBD_STAT_KDSC	(0x1 << 2) /* Key Depress Synch Chain Status bit (w1c)*/
+#define KBD_STAT_KRSS	(0x1 << 3) /* Key Release Synch Status bit (w1c)*/
+#define KBD_STAT_KDIE	(0x1 << 8) /* Key Depress Interrupt Enable Status bit */
+#define KBD_STAT_KRIE	(0x1 << 9) /* Key Release Interrupt Enable */
+
+#define KDDR		0x08 /* Keypad Data Direction Register */
+#define KPDR		0x0C /* Keypad Data Register */
+
+#define MAX_MATRIX_KEY_ROWS	8
+#define MAX_MATRIX_KEY_COLS	8
+
+#define MAX_MATRIX_KEY_NUM	(MAX_MATRIX_KEY_ROWS * MAX_MATRIX_KEY_COLS)
+
+struct phytium_keypad {
+	struct input_dev *input_dev;
+	void __iomem *mmio_base;
+
+	int			irq;
+	struct timer_list	check_matrix_timer;
+
+	/*
+	 * The matrix is stable only if no changes are detected after
+	 * PHYTIUM_KEYPAD_SCANS_FOR_STABILITY scans
+	 */
+#define PHYTIUM_KEYPAD_SCANS_FOR_STABILITY 3
+
+	int			stable_count;
+
+	bool			enabled;
+
+	unsigned int	n_rows;
+	unsigned int	n_cols;
+	int		row_shift;
+
+	/* Masks for enabled rows/cols */
+	unsigned short		rows_en_mask;
+	unsigned short		cols_en_mask;
+
+	unsigned short		keycodes[MAX_MATRIX_KEY_NUM];
+
+	/*
+	 * Matrix states:
+	 * -stable: achieved after a complete debounce process.
+	 * -unstable: used in the debouncing process.
+	 */
+	unsigned short		matrix_stable_state[MAX_MATRIX_KEY_COLS];
+	unsigned short		matrix_unstable_state[MAX_MATRIX_KEY_COLS];
+};
+
+static u32 phytium_read(struct phytium_keypad *keypad, int reg)
+{
+	return readl(keypad->mmio_base + reg);
+}
+
+static void phytium_write(struct phytium_keypad *keypad,  u32 value, int reg)
+{
+	writel(value, keypad->mmio_base + reg);
+}
+
+/* Scan the matrix and return the new state in *matrix_volatile_state. */
+static void phytium_keypad_scan_matrix(struct phytium_keypad *keypad,
+				       unsigned short *matrix_volatile_state)
+{
+	int col;
+	u32 reg_val;
+
+	for (col = 0; col < keypad->n_cols; col++) {
+		if ((keypad->cols_en_mask & (1 << col)) == 0)
+			continue;
+		/*
+		 * Discharge keypad capacitance:
+		 * 2. write 0s on KDDR[KCD], configure columns as input.
+		 */
+		reg_val = phytium_read(keypad, KDDR);
+		reg_val = 0x00000000;
+		phytium_write(keypad, reg_val, KDDR);
+
+		/*
+		 * 3. Write a single column to 0, others to 1.
+		 * 4. Sample row inputs and save data.
+		 * 5. Repeat steps 3 - 4 for remaining columns.
+		 */
+		reg_val = 0;
+		reg_val |= (1 << (16 + col));
+		phytium_write(keypad, reg_val, KDDR);
+		reg_val = phytium_read(keypad, KPDR);
+		reg_val = 0x00000000;
+		phytium_write(keypad, reg_val, KPDR);
+
+		/*
+		 * Delay added to avoid propagating the 0 from column to row
+		 * when scanning.
+		 */
+		udelay(5);
+
+		/*
+		 * 1s in matrix_volatile_state[col] means key pressures
+		 * throw data from non enabled rows.
+		 */
+		reg_val = phytium_read(keypad, KPDR);
+		matrix_volatile_state[col] = (~reg_val) & keypad->rows_en_mask;
+	}
+
+	/*
+	 * Return in standby mode:
+	 * 6. write 0s to columns
+	 */
+	/* Configure columns as output, output 0 */
+	reg_val = 0;
+	reg_val |= (keypad->cols_en_mask & 0xffff) << 16;
+	phytium_write(keypad, reg_val, KDDR);
+	phytium_write(keypad, 0x00000000, KPDR);
+}
+
+/*
+ * Compare the new matrix state (volatile) with the stable one stored in
+ * keypad->matrix_stable_state and fire events if changes are detected.
+ */
+static void phytium_keypad_fire_events(struct phytium_keypad *keypad,
+				       unsigned short *matrix_volatile_state)
+{
+	struct input_dev *input_dev = keypad->input_dev;
+	int row, col;
+
+	for (col = 0; col < keypad->n_cols; col++) {
+		unsigned short bits_changed;
+		int code;
+
+		if ((keypad->cols_en_mask & (1 << col)) == 0)
+			continue; /* Column is not enabled */
+
+		bits_changed = keypad->matrix_stable_state[col] ^
+						matrix_volatile_state[col];
+
+		if (bits_changed == 0)
+			continue; /* Column does not contain changes */
+
+		for (row = 0; row < keypad->n_rows; row++) {
+			if ((keypad->rows_en_mask & (1 << row)) == 0)
+				continue; /* Row is not enabled */
+			if ((bits_changed & (1 << row)) == 0)
+				continue; /* Row does not contain changes */
+
+			code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+			input_event(input_dev, EV_MSC, MSC_SCAN, code);
+			input_report_key(input_dev, keypad->keycodes[code],
+					 matrix_volatile_state[col] & (1 << row));
+			dev_dbg(&input_dev->dev, "Event code: %d, val: %d",
+				keypad->keycodes[code],
+				matrix_volatile_state[col] & (1 << row));
+		}
+	}
+	input_sync(input_dev);
+}
+
+/*
+ * phytium_keypad_check_for_events is the timer handler.
+ */
+static void phytium_keypad_check_for_events(struct timer_list *t)
+{
+	struct phytium_keypad *keypad = from_timer(keypad, t, check_matrix_timer);
+	unsigned short matrix_volatile_state[MAX_MATRIX_KEY_COLS];
+	u32 reg_val;
+	bool state_changed, is_zero_matrix;
+	int i;
+
+	memset(matrix_volatile_state, 0, sizeof(matrix_volatile_state));
+
+	phytium_keypad_scan_matrix(keypad, matrix_volatile_state);
+
+	state_changed = false;
+	for (i = 0; i < keypad->n_cols; i++) {
+		if ((keypad->cols_en_mask & (1 << i)) == 0)
+			continue;
+
+		if (keypad->matrix_unstable_state[i] ^ matrix_volatile_state[i]) {
+			state_changed = true;
+			break;
+		}
+	}
+
+	/*
+	 * If the matrix state is changed from the previous scan
+	 *   (Re)Begin the debouncing process, saving the new state in
+	 *    keypad->matrix_unstable_state.
+	 * else
+	 *   Increase the count of number of scans with a stable state.
+	 */
+	if (state_changed) {
+		memcpy(keypad->matrix_unstable_state, matrix_volatile_state,
+			sizeof(matrix_volatile_state));
+		keypad->stable_count = 0;
+	} else {
+		keypad->stable_count++;
+	}
+
+	/*
+	 * If the matrix is not as stable as we want reschedule scan
+	 * in the near future.
+	 */
+	if (keypad->stable_count < PHYTIUM_KEYPAD_SCANS_FOR_STABILITY) {
+		mod_timer(&keypad->check_matrix_timer,
+			  jiffies + msecs_to_jiffies(10));
+		return;
+	}
+
+	/*
+	 * If the matrix state is stable, fire the events and save the new
+	 * stable state. Note, if the matrix is kept stable for longer
+	 * (keypad->stable_count > PHYTIUM_KEYPAD_SCANS_FOR_STABILITY) all
+	 * events have already been generated.
+	 */
+	if (keypad->stable_count == PHYTIUM_KEYPAD_SCANS_FOR_STABILITY) {
+		phytium_keypad_fire_events(keypad, matrix_volatile_state);
+		memcpy(keypad->matrix_stable_state, matrix_volatile_state,
+			sizeof(matrix_volatile_state));
+	}
+
+	is_zero_matrix = true;
+	for (i = 0; i < keypad->n_cols; i++) {
+		if (matrix_volatile_state[i] != 0) {
+			is_zero_matrix = false;
+			break;
+		}
+	}
+
+	if (is_zero_matrix) {
+		/*
+		 * All keys have been released. Enable only the KDI
+		 * interrupt for future key presses (clear the KDI
+		 * status bit and its sync chain before that).
+		 */
+		reg_val = phytium_read(keypad, KPSR);
+		reg_val |= KBD_STAT_KPKD | KBD_STAT_KDSC;
+		phytium_write(keypad, reg_val, KPSR);
+
+		reg_val = phytium_read(keypad, KPSR);
+		reg_val |= KBD_STAT_KDIE;
+		reg_val &= ~KBD_STAT_KRIE;
+		phytium_write(keypad, reg_val, KPSR);
+	} else {
+		/*
+		 * Some keys are still pressed. Schedule a rescan in
+		 * attempt to detect multiple key presses and enable
+		 * the KRI interrupt to react quickly to key release
+		 * event.
+		 */
+		mod_timer(&keypad->check_matrix_timer,
+			  jiffies + msecs_to_jiffies(60));
+
+		reg_val = phytium_read(keypad, KPSR);
+		reg_val |= KBD_STAT_KPKR | KBD_STAT_KRSS;
+		phytium_write(keypad, reg_val, KPSR);
+
+		reg_val = phytium_read(keypad, KPSR);
+		reg_val |= KBD_STAT_KRIE;
+		reg_val &= ~KBD_STAT_KDIE;
+		phytium_write(keypad, reg_val, KPSR);
+	}
+}
+
+static irqreturn_t phytium_keypad_irq_handler(int irq, void *dev_id)
+{
+	struct phytium_keypad *keypad = dev_id;
+	u32 reg_val;
+
+	reg_val = phytium_read(keypad, KPSR);
+	/* Disable both interrupt types */
+	reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE);
+	/* Clear interrupts status bits */
+	reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD;
+	phytium_write(keypad, reg_val,  KPSR);
+
+	if (keypad->enabled) {
+		/* The matrix is supposed to be changed */
+		keypad->stable_count = 0;
+
+		/* Schedule the scanning procedure near in the future */
+		mod_timer(&keypad->check_matrix_timer,
+			  jiffies + msecs_to_jiffies(2));
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void phytium_keypad_config(struct phytium_keypad *keypad)
+{
+	u32 reg_val;
+
+	/*
+	 * Include enabled rows in interrupt generation (KPCR[15:0])
+	 * Configure keypad columns as open-drain (KPCR[31:16])
+	 */
+	reg_val = phytium_read(keypad, KPCR);
+	reg_val |= keypad->rows_en_mask & 0xffff;	  /* rows */
+	reg_val |= (keypad->cols_en_mask & 0xffff) << 16; /* cols */
+	phytium_write(keypad, reg_val, KPCR);
+
+	/* Configure columns as output, output 0 */
+	reg_val = 0;
+	reg_val |= (keypad->cols_en_mask & 0xffff) << 16;
+	phytium_write(keypad, reg_val, KDDR);
+	phytium_write(keypad, 0x00000000, KPDR);
+
+	/*
+	 * Clear Key Depress and Key Release status bit.
+	 * Clear both synchronizer chain.
+	 */
+	reg_val = phytium_read(keypad, KPSR);
+	reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD |
+		   KBD_STAT_KDSC | KBD_STAT_KRSS;
+	phytium_write(keypad, reg_val, KPSR);
+
+	/* Enable KDI and disable KRI (avoid false release events). */
+	reg_val |= KBD_STAT_KDIE;
+	reg_val &= ~KBD_STAT_KRIE;
+	phytium_write(keypad, reg_val, KPSR);
+}
+
+static void phytium_keypad_inhibit(struct phytium_keypad *keypad)
+{
+	unsigned short reg_val;
+
+	/* Inhibit KDI and KRI interrupts. */
+	reg_val = phytium_read(keypad, KPSR);
+	reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE);
+	reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD;
+	phytium_write(keypad, reg_val, KPSR);
+}
+
+static void phytium_keypad_close(struct input_dev *dev)
+{
+	struct phytium_keypad *keypad = input_get_drvdata(dev);
+
+	dev_dbg(&dev->dev, ">%s\n", __func__);
+
+	/* Mark keypad as being inactive */
+	keypad->enabled = false;
+	synchronize_irq(keypad->irq);
+	del_timer_sync(&keypad->check_matrix_timer);
+
+	phytium_keypad_inhibit(keypad);
+}
+
+static int phytium_keypad_open(struct input_dev *dev)
+{
+	struct phytium_keypad *keypad = input_get_drvdata(dev);
+
+	dev_dbg(&dev->dev, ">%s\n", __func__);
+
+	/* We became active from now */
+	keypad->enabled = true;
+
+	phytium_keypad_config(keypad);
+
+	/* Sanity control, not all the rows must be activated now. */
+	if ((phytium_read(keypad, KPDR) & keypad->rows_en_mask) == 0) {
+		dev_err(&dev->dev,
+			"too many keys pressed, control pins initialisation\n");
+		goto open_err;
+	}
+
+	return 0;
+
+open_err:
+	phytium_keypad_close(dev);
+	return -EIO;
+}
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_keypad_acpi_ids[] = {
+       { "PHYT0028", 0 },
+       { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_keypad_acpi_ids);
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id phytium_keypad_of_match[] = {
+	{ .compatible = "phytium,keypad", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, phytium_keypad_of_match);
+#endif
+
+static int phytium_keypad_probe(struct platform_device *pdev)
+{
+	const struct matrix_keymap_data *keymap_data = dev_get_platdata(&pdev->dev);
+	struct phytium_keypad *keypad;
+	struct input_dev *input_dev;
+	struct resource *res;
+	int irq, error, i, row, col;
+
+	if (!keymap_data && !pdev->dev.of_node && !has_acpi_companion(&pdev->dev)) {
+		dev_err(&pdev->dev, "no keymap defined\n");
+		return -EINVAL;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "no irq defined in platform data\n");
+		return irq;
+	}
+
+	input_dev = devm_input_allocate_device(&pdev->dev);
+	if (!input_dev) {
+		dev_err(&pdev->dev, "failed to allocate the input device\n");
+		return -ENOMEM;
+	}
+
+	keypad = devm_kzalloc(&pdev->dev, sizeof(*keypad), GFP_KERNEL);
+	if (!keypad)
+		return -ENOMEM;
+
+	keypad->input_dev = input_dev;
+	keypad->irq = irq;
+	keypad->stable_count = 0;
+
+	timer_setup(&keypad->check_matrix_timer,
+		    phytium_keypad_check_for_events, 0);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	keypad->mmio_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(keypad->mmio_base))
+		return PTR_ERR(keypad->mmio_base);
+
+	/* Init the Input device */
+	input_dev->name = pdev->name;
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->dev.parent = &pdev->dev;
+	input_dev->open = phytium_keypad_open;
+	input_dev->close = phytium_keypad_close;
+
+	error = matrix_keypad_parse_properties(&pdev->dev, &keypad->n_rows, &keypad->n_cols);
+	if (error) {
+		dev_err(&pdev->dev, "failed to parse phytium kp params\n");
+		return error;
+	}
+
+	error = matrix_keypad_build_keymap(keymap_data, NULL,
+					   keypad->n_rows,
+					   keypad->n_cols,
+					   keypad->keycodes, input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to build keymap\n");
+		return error;
+	}
+
+	keypad->row_shift = get_count_order(keypad->n_cols);
+
+	/* Search for rows and cols enabled */
+	for (row = 0; row < keypad->n_rows; row++) {
+		for (col = 0; col <  keypad->n_cols; col++) {
+			i = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+			if (keypad->keycodes[i] != KEY_RESERVED) {
+				keypad->rows_en_mask |= 1 << row;
+				keypad->cols_en_mask |= 1 << col;
+			}
+		}
+	}
+
+	__set_bit(EV_REP, input_dev->evbit);
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+	input_set_drvdata(input_dev, keypad);
+
+	phytium_keypad_inhibit(keypad);
+
+	error = devm_request_irq(&pdev->dev, irq, phytium_keypad_irq_handler, 0,
+			    pdev->name, keypad);
+	if (error) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		return error;
+	}
+
+	/* Register the input device */
+	error = input_register_device(input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		return error;
+	}
+
+	platform_set_drvdata(pdev, keypad);
+	device_init_wakeup(&pdev->dev, 1);
+
+	return 0;
+}
+
+static int phytium_keypad_remove(struct platform_device *pdev)
+{
+	struct phytium_keypad *keypad = platform_get_drvdata(pdev);
+
+	input_unregister_device(keypad->input_dev);
+	devm_kfree(&pdev->dev, keypad);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_keypad_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct phytium_keypad *keypad = platform_get_drvdata(pdev);
+	struct input_dev *input_dev = keypad->input_dev;
+
+	mutex_lock(&input_dev->mutex);
+
+	if (input_dev->users)
+		phytium_keypad_inhibit(keypad);
+
+	mutex_unlock(&input_dev->mutex);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(keypad->irq);
+
+	return 0;
+}
+
+static int phytium_keypad_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct phytium_keypad *keypad = platform_get_drvdata(pdev);
+	struct input_dev *input_dev = keypad->input_dev;
+	int ret = 0;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(keypad->irq);
+
+	mutex_lock(&input_dev->mutex);
+
+	if (input_dev->users)
+		phytium_keypad_config(keypad);
+
+	mutex_unlock(&input_dev->mutex);
+
+	return ret;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_keypad_pm_ops, phytium_keypad_suspend, phytium_keypad_resume);
+
+static struct platform_driver phytium_keypad_driver = {
+	.driver		= {
+		.name	= "phytium-keypad",
+		.pm	= &phytium_keypad_pm_ops,
+		.of_match_table = of_match_ptr(phytium_keypad_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_keypad_acpi_ids),
+	},
+	.probe      = phytium_keypad_probe,
+	.remove     = phytium_keypad_remove,
+};
+module_platform_driver(phytium_keypad_driver);
+
+MODULE_AUTHOR("Song Wenting <songwenting@phytium.com>");
+MODULE_DESCRIPTION("PHYTIUM Keypad Port Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:phytium-keypad");
diff --git a/target/linux/phytium/files-5.10/drivers/input/serio/phytium-ps2.c b/target/linux/phytium/files-5.10/drivers/input/serio/phytium-ps2.c
new file mode 100644
index 00000000000000..d08433d954d704
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/input/serio/phytium-ps2.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Phytium PS/2 keyboard controller driver.
+ *
+ * Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/input.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/serio.h>
+#include <linux/delay.h>
+
+#define DRV_NAME	"phytium_ps2_pci"
+
+#define REG_STAT		0x0
+#define  REG_STAT_TX_TIMEOUT	0x1
+#define  REG_STAT_RX_TIMEOUT	0x2
+#define  REG_STAT_TX_FULL	0x4
+#define REG_CTRL		0x4
+#define  REG_CTRL_RESET	0x1
+#define  REG_CTRL_TX_TIMEOUT	0x2
+#define  REG_CTRL_RX_TIMEOUT	0x4
+#define  REG_CTRL_RX_INTR	0x8
+#define REG_INTR		0x8
+#define  REG_INTR_TIMEOUT	0x1
+#define  REG_INTR_RX		0x2
+#define REG_TX			0xc
+#define REG_RX			0x10
+#define REG_TIMER_VAL		0x14
+
+#define REG_CTRL_ENABLE		(REG_CTRL_TX_TIMEOUT|REG_CTRL_RX_TIMEOUT|REG_CTRL_RX_INTR)
+#define REG_DATA_PARITY		0x100
+
+#define STAT_RX_COUNTER(stat)	((stat >> 8) & 0x1f)
+
+struct phytium_ps2_data {
+	void __iomem *base;
+	struct serio *io;
+	struct pci_dev *dev;
+};
+
+static irqreturn_t phytium_ps2_irq(int irq, void *devid)
+{
+	struct phytium_ps2_data *ps2if = devid;
+	u32 status, scancode, val = 0;
+	unsigned int flag;
+	int i, rxcount;
+
+	status = readl(ps2if->base + REG_STAT);
+	if (!status)
+		return IRQ_NONE;
+
+	/* Check if there is timeout interrupt */
+	if (status & (REG_STAT_RX_TIMEOUT|REG_STAT_TX_TIMEOUT))
+		val |= REG_INTR_TIMEOUT;
+
+	rxcount = STAT_RX_COUNTER(status);
+	for (i = 0; i < rxcount; i++) {
+		scancode = readl(ps2if->base + REG_RX) & 0x1ff;
+
+		if  (rxcount <= 16 && scancode != 0x1ff) {
+			flag = ((scancode & REG_DATA_PARITY) ? SERIO_PARITY : 0);
+			serio_interrupt(ps2if->io, scancode & 0xff, flag);
+		}
+	}
+
+	val |= REG_INTR_RX;
+	writel(val, ps2if->base + REG_INTR);
+
+	return IRQ_HANDLED;
+}
+
+int phytium_ps2_write(struct serio *serio, unsigned char val)
+{
+	struct phytium_ps2_data *ps2if = serio->port_data;
+	unsigned int stat;
+
+	do {
+		stat = readl(ps2if->base + REG_STAT);
+		cpu_relax();
+	} while (stat & REG_STAT_TX_FULL);
+
+	writel(val, ps2if->base + REG_TX);
+
+	return 0;
+}
+
+int phytium_ps2_open(struct serio *io)
+{
+	struct phytium_ps2_data *ps2if = io->port_data;
+
+	writel(REG_CTRL_RESET, ps2if->base + REG_CTRL);
+	/* Wait 4ms for the controller to be reset */
+	usleep_range(4000, 6000);
+	writel(REG_CTRL_ENABLE, ps2if->base + REG_CTRL);
+
+	return 0;
+}
+
+void phytium_ps2_close(struct serio *io)
+{
+	struct phytium_ps2_data *ps2if = io->port_data;
+
+	writel(0, ps2if->base + REG_CTRL);
+}
+
+static int phytium_pci_ps2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct phytium_ps2_data *ps2if;
+	struct serio *serio;
+	int ret;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		goto out;
+
+	ret = pcim_iomap_regions(pdev, 0x1, DRV_NAME);
+	if (ret)
+		goto out;
+
+	ps2if = devm_kzalloc(&pdev->dev, sizeof(struct phytium_ps2_data), GFP_KERNEL);
+	serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
+	if (!ps2if || !serio) {
+		ret = -ENOMEM;
+		goto free;
+	}
+
+	serio->id.type = SERIO_8042;
+	serio->write = phytium_ps2_write;
+	serio->open = phytium_ps2_open;
+	serio->close = phytium_ps2_close;
+	strscpy(serio->name, pci_name(pdev), sizeof(serio->name));
+	strscpy(serio->phys, dev_name(&pdev->dev), sizeof(serio->phys));
+	serio->port_data = ps2if;
+	serio->dev.parent = &pdev->dev;
+	ps2if->io = serio;
+	ps2if->dev = pdev;
+	ps2if->base = pcim_iomap_table(pdev)[0];
+
+	ret = devm_request_irq(&pdev->dev, pdev->irq, phytium_ps2_irq,
+			       IRQF_SHARED, DRV_NAME, ps2if);
+	if (ret) {
+		dev_err(&pdev->dev, "could not request IRQ %d\n", pdev->irq);
+		goto free;
+	}
+
+	pci_set_drvdata(pdev, ps2if);
+	serio_register_port(ps2if->io);
+
+	return 0;
+
+free:
+	kfree(serio);
+out:
+	return ret;
+}
+
+static void phytium_pci_ps2_remove(struct pci_dev *pdev)
+{
+	struct phytium_ps2_data *ps2if = pci_get_drvdata(pdev);
+
+	serio_unregister_port(ps2if->io);
+	pcim_iounmap_regions(pdev, 0x1);
+}
+
+static const struct pci_device_id phytium_pci_ps2_ids[] = {
+	{ PCI_VDEVICE(PHYTIUM, 0xdc34) },
+	{},
+};
+MODULE_DEVICE_TABLE(pci, phytium_pci_ps2_ids);
+
+static struct pci_driver phytium_pci_ps2_driver = {
+	.name			= DRV_NAME,
+	.id_table		= phytium_pci_ps2_ids,
+	.probe			= phytium_pci_ps2_probe,
+	.remove			= phytium_pci_ps2_remove,
+};
+module_pci_driver(phytium_pci_ps2_driver);
+
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium PCI PS/2 controller driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/irqchip/irq-phytium-ixic.c b/target/linux/phytium/files-5.10/drivers/irqchip/irq-phytium-ixic.c
new file mode 100755
index 00000000000000..7862df80fb46cf
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/irqchip/irq-phytium-ixic.c
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Phytium PCIe legacy INTx interrupt controller
+ *
+ * Copyright (c) 2020-2023, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define NUM_IRQS		4
+
+#define CTR_BANK_NUM		6
+#define CTR_BANK_SIZE		0x10000
+#define CTR_BANK_ISTATUS_LOCAL	0x184
+
+#define HPB_INTX_STATUS_0	0x0
+#define HPB_INTX_STATUS_1	0x1000
+
+struct ixic_irq_data {
+	void __iomem *ctr;
+	void __iomem *hpb;
+	u32 spi_base;
+};
+
+static void phytium_ixic_irq_eoi(struct irq_data *d)
+{
+	struct ixic_irq_data *data = irq_data_get_irq_chip_data(d);
+	unsigned int intx = irqd_to_hwirq(d);
+	u32 gstatus = readl(data->hpb) | (readl(data->hpb + HPB_INTX_STATUS_1) << 12);
+	u32 imask, istatus;
+	int i;
+
+	WARN_ON(intx >= NUM_IRQS);
+	imask = 1 << (3 - intx);
+	istatus = (1 << intx) << 24;
+	for (i = 0; i < CTR_BANK_NUM; i++, gstatus >>= 4) {
+		if (gstatus & imask)
+			writel(istatus, data->ctr + CTR_BANK_SIZE*i + CTR_BANK_ISTATUS_LOCAL);
+	}
+
+	irq_chip_eoi_parent(d);
+}
+
+static struct irq_chip phytium_ixic_irq_chip = {
+	.name = "IXIU",
+	.irq_eoi = phytium_ixic_irq_eoi,
+	.irq_mask = irq_chip_mask_parent,
+	.irq_unmask = irq_chip_unmask_parent,
+	.irq_set_type = irq_chip_set_type_parent,
+	.irq_set_affinity = irq_chip_set_affinity_parent,
+	.flags = IRQCHIP_MASK_ON_SUSPEND,
+};
+
+static int phytium_ixic_translate(struct irq_domain *domain,
+				  struct irq_fwspec *fwspec,
+				  unsigned long *hwirq,
+				  unsigned int *type)
+{
+	struct ixic_irq_data *info = domain->host_data;
+
+	if (is_of_node(fwspec->fwnode)) {
+		if (fwspec->param_count != 3)
+			return -EINVAL;
+
+		if (fwspec->param[0] != GIC_SPI)
+			return -EINVAL; /* No PPI should point to this domain */
+
+		*hwirq = fwspec->param[1] - info->spi_base;
+		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+	} else {
+		if (fwspec->param_count != 2)
+			return -EINVAL;
+		*hwirq = fwspec->param[0] - info->spi_base;
+		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
+	}
+
+	return 0;
+}
+
+static int phytium_ixic_alloc(struct irq_domain *dom, unsigned int virq,
+			      unsigned int nr_irqs, void *data)
+{
+	struct irq_fwspec *fwspec = data;
+	struct irq_fwspec parent_fwspec;
+	struct ixic_irq_data *info = dom->host_data;
+	irq_hw_number_t hwirq;
+
+	/* We assume the device use the parent's format directly */
+	parent_fwspec = *fwspec;
+	if (is_of_node(dom->parent->fwnode)) {
+		if (fwspec->param_count != 3)
+			return -EINVAL; /* Not GIC compliant */
+		if (fwspec->param[0] != GIC_SPI)
+			return -EINVAL; /* No PPI should point to this domain */
+
+		/* Get the local hwirq of IXIC */
+		hwirq = fwspec->param[1] - info->spi_base;
+	} else {
+		hwirq = fwspec->param[0] - info->spi_base;
+	}
+	WARN_ON(nr_irqs != 1);
+	irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &phytium_ixic_irq_chip, info);
+
+	parent_fwspec.fwnode = dom->parent->fwnode;
+	return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
+}
+
+static const struct irq_domain_ops ixic_domain_ops = {
+	.translate = phytium_ixic_translate,
+	.alloc	= phytium_ixic_alloc,
+	.free	= irq_domain_free_irqs_common,
+};
+
+static struct ixic_irq_data *phytium_ixic_init(const struct fwnode_handle *fwnode,
+					      struct resource *ctr, struct resource *hpb)
+{
+	struct ixic_irq_data *data;
+	int err;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return ERR_PTR(-ENOMEM);
+
+	if (fwnode_property_read_u32_array(fwnode, "intx-spi-base",
+					   &data->spi_base, 1)) {
+		err = -ENODEV;
+		goto out_free;
+	}
+
+	data->ctr = ioremap(ctr->start, resource_size(ctr));
+	if (!data->ctr) {
+		err = -ENODEV;
+		goto out_free;
+	}
+
+	data->hpb = ioremap(hpb->start, resource_size(hpb));
+	if (!data->hpb) {
+		err = -ENODEV;
+		goto out_free;
+	}
+
+	return data;
+
+out_free:
+	kfree(data);
+	return ERR_PTR(err);
+}
+
+static int __init phytium_ixic_dt_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	struct irq_domain *pd, *d;
+	struct ixic_irq_data *data;
+	struct resource ctr, hpb;
+
+	if (!parent) {
+		pr_err("%pOF: no parent, giving up\n", node);
+		return -ENODEV;
+	}
+
+	pd = irq_find_host(parent);
+	if (!pd) {
+		pr_err("%pOF: unable to obtain parent domain\n", node);
+		return -ENXIO;
+	}
+
+	if (of_address_to_resource(node, 0, &ctr)) {
+		pr_err("%pOF: failed to parse 'ctr' memory resource\n", node);
+		return -ENXIO;
+	}
+
+	if (of_address_to_resource(node, 1, &hpb)) {
+		pr_err("%pOF: failed to parse 'hpb' memory resource\n", node);
+		return -ENXIO;
+	}
+
+	data = phytium_ixic_init(of_node_to_fwnode(node), &ctr, &hpb);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	d = irq_domain_add_hierarchy(pd, 0, NUM_IRQS, node, &ixic_domain_ops, data);
+	if (!d) {
+		pr_err("%pOF: failed to allocate domain\n", node);
+		goto out_unmap;
+	}
+
+	pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS, parent);
+
+	return 0;
+
+out_unmap:
+	iounmap(data->ctr);
+	iounmap(data->hpb);
+	kfree(data);
+	return -ENOMEM;
+}
+IRQCHIP_DECLARE(ixic, "phytium,ixic", phytium_ixic_dt_init);
+
+#ifdef CONFIG_ACPI
+static int phytium_ixic_acpi_probe(struct platform_device *pdev)
+{
+	struct irq_domain *domain;
+	struct ixic_irq_data *data;
+	struct resource *ctr, *hpb;
+
+	ctr = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!ctr) {
+		dev_err(&pdev->dev, "failed to parse 'ctr' memory resource\n");
+		return -ENXIO;
+	}
+
+	hpb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!hpb) {
+		dev_err(&pdev->dev, "failed to parse 'hpb' memory resource\n");
+		return -ENXIO;
+	}
+
+	data = phytium_ixic_init(dev_fwnode(&pdev->dev), ctr, hpb);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	domain = acpi_irq_create_hierarchy(0, NUM_IRQS, dev_fwnode(&pdev->dev),
+					   &ixic_domain_ops, data);
+	if (!domain) {
+		dev_err(&pdev->dev, "failed to create IRQ domain\n");
+		goto out_unmap;
+	}
+
+	dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS);
+
+	return 0;
+
+out_unmap:
+	iounmap(data->ctr);
+	iounmap(data->hpb);
+	kfree(data);
+	return -ENOMEM;
+}
+
+static const struct acpi_device_id phytium_ixic_acpi_ids[] = {
+	{ "PHYT0013" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(acpi, phytium_ixic_acpi_ids);
+
+static struct platform_driver phytium_ixic_driver = {
+	.driver = {
+		.name = "phytium-ixic",
+		.acpi_match_table = phytium_ixic_acpi_ids,
+	},
+	.probe = phytium_ixic_acpi_probe,
+};
+builtin_platform_driver(phytium_ixic_driver);
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/mailbox/phytium-mailbox.c b/target/linux/phytium/files-5.10/drivers/mailbox/phytium-mailbox.c
new file mode 100644
index 00000000000000..21549e25b0560f
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mailbox/phytium-mailbox.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SoC mailbox driver
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#define INTR_STAT	0x0
+#define INTR_SET	0x8
+#define INTR_CLR	0x10
+
+#define TX_REG		0x100
+
+#define NR_CHANS	1
+
+static spinlock_t lock;
+
+struct phytium_mbox_link {
+	unsigned int irq;
+	void __iomem *tx_reg;
+	void __iomem *rx_reg;
+};
+
+struct phytium_mbox {
+	void __iomem *base;
+	struct phytium_mbox_link mlink;
+	struct mbox_chan chan;
+	struct mbox_controller mbox;
+};
+
+static irqreturn_t phytium_mbox_rx_irq(int irq, void *ch)
+{
+	struct mbox_chan *chan = ch;
+	struct phytium_mbox_link *mlink = chan->con_priv;
+	u32 val;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(&lock, flags);
+	val = readl_relaxed(mlink->rx_reg + INTR_STAT);
+	spin_unlock_irqrestore(&lock, flags);
+	if (!val)
+		return IRQ_NONE;
+
+	mbox_chan_received_data(chan, (void *)&val);
+
+	spin_lock_irqsave(&lock, flags);
+	writel_relaxed(val, mlink->rx_reg + INTR_CLR);
+	spin_unlock_irqrestore(&lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int phytium_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+	struct phytium_mbox_link *mlink = chan->con_priv;
+	u32 *arg = data;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(&lock, flags);
+	writel_relaxed(*arg, mlink->tx_reg + INTR_SET);
+	spin_unlock_irqrestore(&lock, flags);
+
+	return 0;
+}
+
+static int phytium_mbox_startup(struct mbox_chan *chan)
+{
+	struct phytium_mbox_link *mlink = chan->con_priv;
+	u32 val;
+	int ret;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(&lock, flags);
+	val = readl_relaxed(mlink->tx_reg + INTR_STAT);
+	writel_relaxed(val, mlink->tx_reg + INTR_CLR);
+	spin_unlock_irqrestore(&lock, flags);
+
+	ret = request_irq(mlink->irq, phytium_mbox_rx_irq,
+			  IRQF_SHARED, "phytium_mbox_link", chan);
+	if (ret) {
+		dev_err(chan->mbox->dev,
+			"Unable to acquire IRQ %d\n", mlink->irq);
+	}
+
+	return ret;
+}
+
+static void phytium_mbox_shutdown(struct mbox_chan *chan)
+{
+	struct phytium_mbox_link *mlink = chan->con_priv;
+
+	free_irq(mlink->irq, chan);
+}
+
+static bool phytium_mbox_last_tx_done(struct mbox_chan *chan)
+{
+	unsigned long flags;
+	struct phytium_mbox_link *mlink = chan->con_priv;
+	u32 val;
+
+	spin_lock_irqsave(&lock, flags);
+	val = readl_relaxed(mlink->tx_reg + INTR_STAT);
+	spin_unlock_irqrestore(&lock, flags);
+
+	return (val == (u32)(1U << 31));
+}
+
+static const struct mbox_chan_ops phytium_mbox_ops = {
+	.send_data = phytium_mbox_send_data,
+	.startup = phytium_mbox_startup,
+	.shutdown = phytium_mbox_shutdown,
+	.last_tx_done = phytium_mbox_last_tx_done,
+};
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_mbox_acpi_match[] = {
+	{ "PHYT0009", 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_mbox_acpi_match);
+#endif
+
+static const struct of_device_id phytium_mbox_of_match[] = {
+	{ .compatible = "phytium,mbox", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, phytium_mbox_of_match);
+
+static int phytium_mbox_probe(struct platform_device *pdev)
+{
+	struct phytium_mbox *mbox;
+	struct resource *res;
+	int err, irq;
+
+	spin_lock_init(&lock);
+
+	/* Allocate memory for device */
+	mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
+	if (!mbox)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mbox->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mbox->base)) {
+		dev_err(&pdev->dev, "ioremap base failed\n");
+		return PTR_ERR(mbox->base);
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "cannot obtain irq\n");
+		return irq;
+	}
+
+	mbox->chan.con_priv = &mbox->mlink;
+	mbox->mlink.irq = irq;
+	mbox->mlink.rx_reg = mbox->base;
+	mbox->mlink.tx_reg = mbox->mlink.rx_reg + TX_REG;
+
+	mbox->mbox.dev = &pdev->dev;
+	mbox->mbox.chans = &mbox->chan;
+	mbox->mbox.num_chans = NR_CHANS;
+	mbox->mbox.ops = &phytium_mbox_ops;
+	mbox->mbox.txdone_irq = false;
+	mbox->mbox.txdone_poll = true;
+	mbox->mbox.txpoll_period = 1;
+
+	platform_set_drvdata(pdev, mbox);
+
+	err = mbox_controller_register(&mbox->mbox);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to register mailboxes %d\n", err);
+		goto fail;
+	}
+
+	dev_info(&pdev->dev, "Phytium SoC Mailbox registered\n");
+fail:
+	return err;
+}
+
+static int phytium_mbox_remove(struct platform_device *pdev)
+{
+	struct phytium_mbox *mbox = platform_get_drvdata(pdev);
+
+	mbox_controller_unregister(&mbox->mbox);
+
+	return 0;
+}
+
+static struct platform_driver phytium_mbox_driver = {
+	.probe = phytium_mbox_probe,
+	.remove = phytium_mbox_remove,
+	.driver = {
+		.name = "phytium-mbox",
+		.of_match_table = of_match_ptr(phytium_mbox_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_mbox_acpi_match),
+	},
+};
+
+module_platform_driver(phytium_mbox_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium SoC Mailbox Driver");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/Makefile b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/Makefile
new file mode 100644
index 00000000000000..d9f50a1aaba354
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+phytium_jpeg-objs := phytium_jpeg_core.o
+obj-$(CONFIG_VIDEO_PHYTIUM_JPEG) += phytium_jpeg.o
diff --git a/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c
new file mode 100644
index 00000000000000..b0324a6d0d8577
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.c
@@ -0,0 +1,1379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Phytium JPEG Encoder Engine
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include "phytium_jpeg_reg.h"
+#include "phytium_jpeg_core.h"
+#include <linux/arm-smccc.h>
+
+static u32 phytium_jpeg_header[PHYTIUM_JPEG_HEADER_SIZE] = {
+	0xe0ffd8ff, 0x464a0100, 0x01004649, 0x01000001,
+	0x00000100, 0x4300dbff, 0x0c0b1000, 0x100a0c0e,
+	0x120e0d0e, 0x18131011, 0x16181a28, 0x23311816,
+	0x3a281d25, 0x393c3d33, 0x40373833, 0x404e5c48,
+	0x37455744, 0x516d5038, 0x67625f57, 0x4d3e6768,
+	0x64707971, 0x67655c78, 0x00dbff63, 0x12110143,
+	0x18151812, 0x2f1a1a2f, 0x42384263, 0x63636363,
+	0x63636363, 0x63636363, 0x63636363, 0x63636363,
+	0x63636363, 0x63636363, 0x63636363, 0x63636363,
+	0x63636363, 0x63636363, 0x63636363, 0xc0ff6363,
+	/* h_index(40) indicates high 8 bits of the height
+	 * w_index(41) contains the low 8 bits of the height,
+	 * and the width. For example, height 480(0x01e0)
+	 * locates at 0x<01> 081100 and 0x038002 <e0>.
+	 * width 640 (0x0280) locates at 0x03 <80> <02> e0.
+	 */
+
+	/* 0x0200 <11> 01 is a field marks YUV mode */
+	0x01081100, 0x038002e0, 0x02001101, 0x11030111,
+	0x00c4ff01, 0x0100001f, 0x01010105, 0x00010101,
+	0x00000000, 0x01000000, 0x05040302, 0x09080706,
+	0xc4ff0b0a, 0x00011f00, 0x01010103, 0x01010101,
+	0x00000101, 0x00000000, 0x04030201, 0x08070605,
+	0xff0b0a09, 0x10b500c4, 0x03010200, 0x03040203,
+	0x04040505, 0x7d010000, 0x00030201, 0x12051104,
+	0x06413121, 0x07615113, 0x32147122, 0x08a19181,
+	0xc1b14223, 0xf0d15215, 0x72623324, 0x160a0982,
+	0x1a191817, 0x28272625, 0x35342a29, 0x39383736,
+	0x4544433a, 0x49484746, 0x5554534a, 0x59585756,
+	0x6564635a, 0x69686766, 0x7574736a, 0x79787776,
+	0x8584837a, 0x89888786, 0x9493928a, 0x98979695,
+	0xa3a29a99, 0xa7a6a5a4, 0xb2aaa9a8, 0xb6b5b4b3,
+	0xbab9b8b7, 0xc5c4c3c2, 0xc9c8c7c6, 0xd4d3d2ca,
+	0xd8d7d6d5, 0xe2e1dad9, 0xe6e5e4e3, 0xeae9e8e7,
+	0xf4f3f2f1, 0xf8f7f6f5, 0xc4fffaf9, 0x0011b500,
+	0x04020102, 0x07040304, 0x00040405, 0x00770201,
+	0x11030201, 0x31210504, 0x51411206, 0x13716107,
+	0x08813222, 0xa1914214, 0x2309c1b1, 0x15f05233,
+	0x0ad17262, 0xe1342416, 0x1817f125, 0x27261a19,
+	0x352a2928, 0x39383736, 0x4544433a, 0x49484746,
+	0x5554534a, 0x59585756, 0x6564635a, 0x69686766,
+	0x7574736a, 0x79787776, 0x8483827a, 0x88878685,
+	0x93928a89, 0x97969594, 0xa29a9998, 0xa6a5a4a3,
+	0xaaa9a8a7, 0xb5b4b3b2, 0xb9b8b7b6, 0xc4c3c2ba,
+	0xc8c7c6c5, 0xd3d2cac9, 0xd7d6d5d4, 0xe2dad9d8,
+	0xe6e5e4e3, 0xeae9e8e7, 0xf5f4f3f2, 0xf9f8f7f6,
+	0x00fefffa, 0x0000008f, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0xdaff0000, 0x01030c00, 0x03110200, 0x003f0011
+};
+
+static char yuv_mode_str[YUV_MODE_STR_LEN] = { "yuv444" };
+
+module_param_string(yuv_mode, yuv_mode_str, sizeof(yuv_mode_str), 0444);
+MODULE_PARM_DESC(yuv_mode, "Users select one mode from such modes as 'yuv444', or 'yuv422', or 'yuv420'. If no mode is set, the driver adapts defaults mode 'yuv444'.");
+
+static u32 phytium_jpeg_read(struct phytium_jpeg_dev *jpeg_dev, u32 reg)
+{
+	u32 reg_val = readl(jpeg_dev->base_addr + reg);
+
+	dev_dbg(jpeg_dev->dev, "read 0x%p + 0x%x -->val[0x%x]\n",
+		  jpeg_dev->base_addr, reg, reg_val);
+
+	return reg_val;
+}
+
+static void phytium_jpeg_write(struct phytium_jpeg_dev *jpeg_dev,
+				u32 reg, u32 val)
+{
+	writel(val, jpeg_dev->base_addr + reg);
+	dev_dbg(jpeg_dev->dev, "write 0x%x to addr 0x%p + 0x%x\n",
+		  val, jpeg_dev->base_addr, reg);
+}
+
+static void phytium_jpeg_update(struct phytium_jpeg_dev *jpeg_dev, u32 reg,
+				u32 clear, u32 bits)
+{
+	u32 reg_val = readl(jpeg_dev->base_addr + reg);
+	u32 tmp = reg_val;
+
+	reg_val &= ~clear;
+	reg_val |= bits;
+	writel(reg_val, jpeg_dev->base_addr + reg);
+
+	dev_dbg(jpeg_dev->dev, "the val of addr 0x%p + 0x%x, from 0x%x to 0x%x\n",
+		  jpeg_dev->base_addr, reg, tmp, readl(jpeg_dev->base_addr + reg));
+}
+
+static void phytium_jpeg_init_regs(struct phytium_jpeg_dev *jpeg_dev)
+{
+	u32 transform_info = 0;
+	u32 disable_all_interrupt = 0;
+	u32 clear_all_interrupt = INT_FIFO_OVERFLOW | INT_OCM_BUF_OVERFLOW |
+			INT_JPEG_ENCODE_COMPLETE | INT_VIDEO_FORMAT_CHANGE;
+	u32 rate_to_reg = 0;
+
+	/* First, disable the JPEG engine, set bit0 = 0*/
+	phytium_jpeg_write(jpeg_dev, TRANSFORM_INFO_REG, transform_info);
+
+	/* Second, set VGAvideo_source_information. bit1 = 0 marks VGA */
+	transform_info |= 0;
+
+	/* Third, set AXI burst length bit[16:22]= 0xf , default value*/
+	transform_info |= (0xF << TRANS_AXI_LEN_SHIFT) & TRANSINFO_AXI_LEN;
+
+	/* Fourth, the default sampling format is YUV422, set bit13 to 0 */
+	/* ignore setting sampling interval */
+	phytium_jpeg_write(jpeg_dev, TRANSFORM_INFO_REG, transform_info);
+	udelay(5);
+
+	/* Fifth, setting frame rate.
+	 *   Linux driver prohibit float point operations. So use the
+	 *   format: reg_val = (1 second * 10^8 / frame_rate / 134 *100)
+	 *   write reg_val to register. then enable Highest bit31 = 1
+	 */
+	if (jpeg_dev->frame_rate) {
+		rate_to_reg = 100000000 / jpeg_dev->frame_rate / 134 * 100;
+		rate_to_reg |= FRAME_SAMPLE_CTRL_EN;
+		phytium_jpeg_write(jpeg_dev, FRAME_SAMPLE_CTRL, rate_to_reg);
+	}
+	/* Sixth, HUFF_MODE, driver needn't to configure, ignore */
+
+	/* disable all interrupts  and then clear all interrupts */
+	phytium_jpeg_write(jpeg_dev, INT_STATUS_CTRL_REG,
+			   disable_all_interrupt);
+	udelay(5);
+	phytium_jpeg_write(jpeg_dev, INT_STATUS_CTRL_REG, clear_all_interrupt);
+
+	/* Seventh, Sample_mode, hardware default is yuv444 */
+	 jpeg_dev->yuv420 = false;
+}
+
+/* Turn on the clock of the jpeg engine */
+static void phytium_jpeg_on(struct phytium_jpeg_dev *jpeg_dev)
+{
+	if (test_bit(VIDEO_CLOCKS_ON, &jpeg_dev->status))
+		return;
+
+	/* Turn on the relevant clocks */
+	set_bit(VIDEO_CLOCKS_ON, &jpeg_dev->status);
+}
+
+/* Disable the jpeg engine */
+static void phytium_jpeg_off(struct phytium_jpeg_dev *jpeg_dev)
+{
+	u32 disable_all_interrupt = 0;
+	u32 clear_all_interrupt = INT_FIFO_OVERFLOW | INT_OCM_BUF_OVERFLOW |
+			INT_JPEG_ENCODE_COMPLETE | INT_VIDEO_FORMAT_CHANGE;
+
+	if (!test_bit(VIDEO_CLOCKS_ON, &jpeg_dev->status)) {
+		dev_info(jpeg_dev->dev, "JPEG Engine is already off.\n");
+		return;
+	}
+
+	/* disable all interrupt */
+	phytium_jpeg_write(jpeg_dev, INT_STATUS_CTRL_REG, disable_all_interrupt);
+	/* clear all interrupt */
+	phytium_jpeg_write(jpeg_dev, INT_STATUS_CTRL_REG, clear_all_interrupt);
+	/* disable JPEG engine */
+	phytium_jpeg_update(jpeg_dev, TRANSFORM_INFO_REG, TRANSINFO_ENABLE_ENGINE, 0);
+
+	clear_bit(VIDEO_CLOCKS_ON, &jpeg_dev->status);
+	/* wait 50 ms */
+	mdelay(50);
+	/* C08 bit7 1:busy */
+}
+
+static inline void phytium_jpeg_enable_source_detecting(struct phytium_jpeg_dev *jpeg_dev)
+{
+	/*
+	 * Enable the dectection to discovery
+	 * the source resolution is changed
+	 */
+	//phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG, 0, DETECT_RESOLUTION_CHANGE_EN);
+	phytium_jpeg_update(jpeg_dev, TRANSFORM_INFO_REG, 0, TRANSINFO_SRC_SELECT);
+}
+
+#define res_check(val) \
+	test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(val)->status)
+
+static void phytium_jpeg_get_resolution(struct phytium_jpeg_dev *jpeg_dev)
+{
+	u32 source_info;
+	u32 width;
+	u32 height;
+	struct v4l2_bt_timings *detected_timings = &jpeg_dev->detected_timings;
+
+	/* Before get a new resolution, maybe need to wait 10 us */
+	detected_timings->width = MIN_WIDTH;
+	detected_timings->height = MIN_HEIGHT;
+	jpeg_dev->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
+
+
+	phytium_jpeg_enable_source_detecting(jpeg_dev);
+	source_info = phytium_jpeg_read(jpeg_dev, SRC_VGA_INFO_REG);
+	width = (source_info & SRC_HOR_PIXELS) >> SRC_WIDTH_SHIFT;
+	height = (source_info & SRC_VER_PIXELS) >> SRC_HEIGHT_SHIFT;
+
+	if (width * height != 0) {
+		detected_timings->width = width;
+		detected_timings->height = height;
+	}
+
+	jpeg_dev->v4l2_input_status = 0;
+
+	/*
+	 * Resolution is changed will trigger an interrupt, resolution detecting
+	 * also is disable during process interrupt. So re-enable.
+	 */
+	phytium_jpeg_enable_source_detecting(jpeg_dev);
+	dev_info(jpeg_dev->dev, "Change resolution: %uX%u\n", width, height);
+}
+
+static void phytium_jpeg_set_resolution(struct phytium_jpeg_dev *jpeg_dev)
+{
+	struct v4l2_bt_timings  *active_timings = &jpeg_dev->active_timings;
+	int i;
+	int src_addrs[OCM_BUF_NUM];
+	/*
+	 * The OCM address space is 0x30C0_0000 ~ 0x30C7_FFFF, JPEG Engine uses the
+	 * high-bottom address. src_0 uses 0x30C4_0000 ~ 0x30c6_0000 (total capacity is
+	 * 128KB, greater than the requirements of the largest resolution). src_1 uses
+	 * 0x30C6_0000 ~ 0x30C7_FFFF.
+	 */
+
+	/* The OCM address should shift right 8 bits */
+	for (i = 0; i < OCM_BUF_NUM; i++)
+		src_addrs[i] = jpeg_dev->src_addrs[i].dma_addr >> OCM_BUF_SHIFT;
+
+	phytium_jpeg_write(jpeg_dev, OCM_BUF0_ADDR, src_addrs[0]);
+	phytium_jpeg_write(jpeg_dev, OCM_BUF1_ADDR, src_addrs[1]);
+
+	/*
+	 * In the worst case, the size of one image will be compressed to 25% the
+	 * raw image's size. When a pixel is 4-byte, no need to divide 4.
+	 */
+	jpeg_dev->max_compressed_size = active_timings->width * active_timings->height;
+}
+
+/* The below functions is implemented for various v4l2 ioctl operations */
+static int phytium_jpeg_querycap(struct file *file, void *priv,
+				 struct v4l2_capability *cap)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	strscpy(cap->driver, PHYTIUM_JPEG_NAME, sizeof(cap->driver));
+	strscpy(cap->card, "Phytium JPEG Engine", sizeof(cap->card));
+	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", dev_name(jpeg_dev->dev));
+
+	return 0;
+}
+
+static int phytium_jpeg_enum_format(struct file *file, void *priv,
+				    struct v4l2_fmtdesc *f)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	if (f->index) {
+		dev_err(jpeg_dev->dev, "Failed to enum format\n");
+		return -EINVAL;
+	}
+
+	f->pixelformat = V4L2_PIX_FMT_JPEG;
+
+	return 0;
+}
+
+static int phytium_jpeg_get_format(struct file *file, void *priv,
+				   struct v4l2_format *f)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	f->fmt.pix = jpeg_dev->pix_fmt;
+
+	return 0;
+}
+
+static int phytium_jpeg_enum_input(struct file *file, void *priv,
+				struct v4l2_input *input)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	if (input->index) {
+		dev_err(jpeg_dev->dev, "failed to enum input\n");
+		return -EINVAL;
+	}
+
+	strscpy(input->name, "Host DC Capture", sizeof(input->name));
+	input->type = V4L2_INPUT_TYPE_CAMERA;
+	input->capabilities = V4L2_IN_CAP_DV_TIMINGS;
+	input->status = jpeg_dev->v4l2_input_status;
+
+	return 0;
+}
+
+static int phytium_jpeg_get_input(struct file *file, void *priv,
+				  unsigned int *i)
+{
+	*i = 0;
+	return 0;
+}
+
+static int phytium_jpeg_set_input(struct file *file, void *priv,
+				  unsigned int i)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	if (i != 0) {
+		dev_err(jpeg_dev->dev, "Failed to set input\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int phytium_jpeg_get_parm(struct file *file, void *priv,
+			struct v4l2_streamparm *stream)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+	/* Readbuffers num is 3 */
+	stream->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
+	stream->parm.capture.readbuffers = CAPTURE_BUF_NUMBER;
+	stream->parm.capture.timeperframe.denominator = 1;
+
+	if (jpeg_dev->frame_rate == 0)
+		stream->parm.capture.timeperframe.denominator = MAX_FRAME_RATE;
+	else
+		stream->parm.capture.timeperframe.denominator = jpeg_dev->frame_rate;
+
+	return 0;
+}
+
+static int phytium_jpeg_set_parm(struct file *file, void *priv,
+				struct v4l2_streamparm *stream)
+{
+	unsigned int frame_rate = 0;
+	u32 rate_to_reg = 0;
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+	 /* Readbuffers num is 3 */
+	stream->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
+	stream->parm.capture.readbuffers = CAPTURE_BUF_NUMBER;
+
+	if (stream->parm.capture.timeperframe.numerator)
+		frame_rate = stream->parm.capture.timeperframe.denominator /
+			stream->parm.capture.timeperframe.numerator;
+
+	if (frame_rate == 0 || frame_rate > MAX_FRAME_RATE) {
+		frame_rate = MAX_FRAME_RATE;
+		stream->parm.capture.timeperframe.denominator = MAX_FRAME_RATE;
+		stream->parm.capture.timeperframe.numerator = 1;
+	}
+	/*
+	 *   reg_val = (1 second * 10^9 / frame_rate / 13.4)
+	 *   Linux driver prohibit float point operations. So use the
+	 *   format: reg_val = (1 second * 10^8 / frame_rate / 134 *100)
+	 *   write reg_val to register. then enable Highest bit31 = 1
+	 */
+	if (jpeg_dev->frame_rate != frame_rate) {
+		jpeg_dev->frame_rate = frame_rate;
+		rate_to_reg = 100000000 / jpeg_dev->frame_rate / 134 * 100;
+		rate_to_reg |= FRAME_SAMPLE_CTRL_EN;
+		phytium_jpeg_write(jpeg_dev, FRAME_SAMPLE_CTRL, rate_to_reg);
+	}
+
+	return 0;
+}
+
+static int phytium_jpeg_enum_framesizes(struct file *file, void *priv,
+					struct v4l2_frmsizeenum *fsize)
+
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	if (fsize->index != 0) {
+		dev_err(jpeg_dev->dev, "Failed to enum framesize.\n");
+		return -EINVAL;
+	}
+
+	if (fsize->pixel_format != V4L2_PIX_FMT_JPEG) {
+		dev_err(jpeg_dev->dev, "enum framesize pixel_format is not JPEG");
+		return -EINVAL;
+	}
+
+	fsize->discrete.width = jpeg_dev->pix_fmt.width;
+	fsize->discrete.height = jpeg_dev->pix_fmt.height;
+	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+
+	return 0;
+
+}
+
+static int phytium_jpeg_enum_frameintervals(struct file *file, void *priv,
+					    struct v4l2_frmivalenum *fival)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	if (fival->index != 0) {
+		dev_err(jpeg_dev->dev, "enum frame intervals failed\n");
+		return -EINVAL;
+	}
+
+	if (fival->width != jpeg_dev->detected_timings.width ||
+		fival->height != jpeg_dev->detected_timings.height) {
+		dev_err(jpeg_dev->dev, "interval isn't same with the detected_timings.\n");
+		return -EINVAL;
+	}
+
+	if (fival->pixel_format != V4L2_PIX_FMT_JPEG) {
+		dev_err(jpeg_dev->dev, "enum frame interval pixel fomat is incorrect.\n");
+		return -EINVAL;
+	}
+
+	fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
+	fival->stepwise.min.denominator = MAX_FRAME_RATE;
+	fival->stepwise.min.numerator = 1;
+	fival->stepwise.max.denominator = 1;
+	fival->stepwise.max.numerator = 1;
+	fival->stepwise.step = fival->stepwise.max;
+
+	return 0;
+}
+
+static int phytium_jpeg_set_dv_timings(struct file *file, void *priv,
+				       struct v4l2_dv_timings *timings)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	/* the params are passed from user space are same with hardware's params */
+	if (timings->bt.width == jpeg_dev->active_timings.width &&
+	    timings->bt.height == jpeg_dev->active_timings.height)
+		return 0;
+
+	if (vb2_is_busy(&jpeg_dev->queue)) {
+		dev_err(jpeg_dev->dev, "queue is busy during setting dv timings.\n");
+		return -EBUSY;
+	}
+
+	jpeg_dev->active_timings = timings->bt;
+	phytium_jpeg_set_resolution(jpeg_dev);
+	jpeg_dev->pix_fmt.width = timings->bt.width;
+	jpeg_dev->pix_fmt.height = timings->bt.height;
+	jpeg_dev->pix_fmt.sizeimage = jpeg_dev->max_compressed_size;
+	timings->type = V4L2_DV_BT_656_1120;
+
+	return 0;
+}
+
+static int phytium_jpeg_get_dv_timings(struct file *file, void *priv,
+				       struct v4l2_dv_timings *timings)
+{
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	timings->type = V4L2_DV_BT_656_1120;
+	timings->bt = jpeg_dev->active_timings;
+
+	return 0;
+}
+
+static int phytium_jpeg_query_dv_timings(struct file *file, void *priv,
+					 struct v4l2_dv_timings *timings)
+{
+	int ret;
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	/*
+	 * This blocks only if the driver is currently in the process of
+	 * detecting a new resolution; in the event of no signal or timeout
+	 * this function is woken up.
+	 */
+	if ((file->f_flags & O_NONBLOCK) &&
+	    test_bit(VIDEO_RES_CHANGE, &jpeg_dev->status))
+		return -EAGAIN;
+
+	ret = wait_event_interruptible(jpeg_dev->wait, !test_bit(VIDEO_RES_CHANGE,
+				       &jpeg_dev->status));
+	if (ret) {
+		dev_err(jpeg_dev->dev, "Failed to query dv timing\n");
+		return -EINTR;
+	}
+
+	timings->type = V4L2_DV_BT_656_1120;
+	timings->bt = jpeg_dev->detected_timings;
+
+	return jpeg_dev->v4l2_input_status ? -ENOLINK : 0;
+}
+
+static const struct v4l2_dv_timings_cap phytium_jpeg_timings_cap = {
+	.type = V4L2_DV_BT_656_1120,
+	.bt = {
+		.min_width = MIN_WIDTH,
+		.max_width = MAX_WIDTH,
+		.min_height = MIN_HEIGHT,
+		.max_height = MAX_HEIGHT,
+		.min_pixelclock = 6574080, /* 640 x 480 x 24Hz */
+		.max_pixelclock = 1244160000, /* 1920 x 1080 x 60Hz */
+		.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
+			V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
+		.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
+			V4L2_DV_BT_CAP_REDUCED_BLANKING |
+			V4L2_DV_BT_CAP_CUSTOM,
+	},
+};
+
+static int phytium_jpeg_enum_dv_timings(struct file *file, void *priv,
+				struct v4l2_enum_dv_timings *timings)
+{
+	return v4l2_enum_dv_timings_cap(timings, &phytium_jpeg_timings_cap,
+					NULL, NULL);
+}
+
+static int phytium_jpeg_dv_timings_cap(struct file *file, void *priv,
+				struct v4l2_dv_timings_cap *cap)
+{
+	*cap = phytium_jpeg_timings_cap;
+
+	return 0;
+}
+
+/* The function is used to notify DV that video resolution is altered */
+static int phytium_jpeg_sub_event(struct v4l2_fh *fh,
+				  const struct v4l2_event_subscription *sub)
+{
+	switch (sub->type) {
+	case V4L2_EVENT_SOURCE_CHANGE:
+		return v4l2_src_change_event_subscribe(fh, sub);
+	default:
+		break;
+	}
+
+	return v4l2_ctrl_subscribe_event(fh, sub);
+}
+
+static const struct v4l2_ioctl_ops phytium_jpeg_ioctl_ops = {
+	.vidioc_querycap = phytium_jpeg_querycap,
+	.vidioc_enum_fmt_vid_cap = phytium_jpeg_enum_format,
+	.vidioc_g_fmt_vid_cap = phytium_jpeg_get_format,
+	.vidioc_s_fmt_vid_cap = phytium_jpeg_get_format,
+	.vidioc_try_fmt_vid_cap = phytium_jpeg_get_format,
+	.vidioc_reqbufs = vb2_ioctl_reqbufs,
+	.vidioc_querybuf = vb2_ioctl_querybuf,
+	.vidioc_qbuf = vb2_ioctl_qbuf,
+	.vidioc_expbuf = vb2_ioctl_expbuf,
+	.vidioc_dqbuf = vb2_ioctl_dqbuf,
+	.vidioc_create_bufs = vb2_ioctl_create_bufs,
+	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+	.vidioc_streamon = vb2_ioctl_streamon,
+	.vidioc_streamoff = vb2_ioctl_streamoff,
+	.vidioc_enum_input = phytium_jpeg_enum_input,
+	.vidioc_g_input = phytium_jpeg_get_input,
+	.vidioc_s_input = phytium_jpeg_set_input,
+	.vidioc_g_parm = phytium_jpeg_get_parm,
+	.vidioc_s_parm = phytium_jpeg_set_parm,
+	.vidioc_enum_framesizes = phytium_jpeg_enum_framesizes,
+	.vidioc_enum_frameintervals = phytium_jpeg_enum_frameintervals,
+	.vidioc_s_dv_timings = phytium_jpeg_set_dv_timings,
+	.vidioc_g_dv_timings = phytium_jpeg_get_dv_timings,
+	.vidioc_query_dv_timings = phytium_jpeg_query_dv_timings,
+	.vidioc_enum_dv_timings = phytium_jpeg_enum_dv_timings,
+	.vidioc_dv_timings_cap = phytium_jpeg_dv_timings_cap,
+	.vidioc_subscribe_event = phytium_jpeg_sub_event,
+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static void phytium_jpeg_init_jpeg_quant(struct phytium_jpeg_dev *jpeg_dev)
+{
+	const u32 y_quant_table[QUANT_REG_NUM] = {
+	    0x08000000, 0x0ba2e8ba, 0x0aaaaaab, 0x09249249, 0x0aaaaaab,
+	    0x0ccccccc, 0x08000000, 0x09249249, 0x09d89d8a, 0x09249249,
+	    0x071c71c7, 0x07878788, 0x08000000, 0x06bca1af, 0x05555555,
+	    0x03333333, 0x04ec4ec5, 0x05555555, 0x05d1745d, 0x05d1745d,
+	    0x05555555, 0x029cbc15, 0x03a83a84, 0x03759f23, 0x0469ee58,
+	    0x03333333, 0x0234f72c, 0x02828283, 0x02192e2a, 0x02222222,
+	    0x023ee090, 0x02828283, 0x02492492, 0x0253c825, 0x02000000,
+	    0x01c71c72, 0x01642c86, 0x01a41a42, 0x02000000, 0x01e1e1e2,
+	    0x0178a4c8, 0x01dae607, 0x0253c825, 0x02492492, 0x0199999a,
+	    0x012c9fb5, 0x01948b10, 0x0178a4c8, 0x0158ed23, 0x014e5e0a,
+	    0x013e22cc, 0x013b13b1, 0x013e22cc, 0x02108421, 0x01a98ef6,
+	    0x0121fb78, 0x010ecf57, 0x01249249, 0x013e22cc, 0x01111111,
+	    0x01642c86, 0x01446f86, 0x013e22cc, 0x014afd6a
+	};
+
+	const u32 c_quant_table[QUANT_REG_NUM] = {
+	    0x07878788, 0x071c71c7, 0x071c71c7, 0x05555555, 0x06186186,
+	    0x05555555, 0x02b93105, 0x04ec4ec5, 0x04ec4ec5, 0x02b93105,
+	    0x014afd6a, 0x01f07c1f, 0x02492492, 0x01f07c1f, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a,
+	    0x014afd6a, 0x014afd6a, 0x014afd6a, 0x014afd6a
+	};
+	int i;
+
+	for (i = 0; i < QUANT_REG_NUM; i++) {
+		phytium_jpeg_write(jpeg_dev, Y_QUANT_INDEX_ADDR_REG(i), y_quant_table[i]);
+		phytium_jpeg_write(jpeg_dev, C_QUANT_INDEX_ADDR_REG(i), c_quant_table[i]);
+	}
+
+}
+
+static void phytium_jpeg_start(struct phytium_jpeg_dev *jpeg_dev)
+{
+	phytium_jpeg_on(jpeg_dev);
+	phytium_jpeg_init_regs(jpeg_dev);
+
+	/* Resolution set to 640x480 if no signal is found */
+	phytium_jpeg_get_resolution(jpeg_dev);
+
+	/* Set timings since the device is being opened for the first tiime */
+	jpeg_dev->active_timings =  jpeg_dev->detected_timings;
+	phytium_jpeg_set_resolution(jpeg_dev);
+
+	jpeg_dev->pix_fmt.width = jpeg_dev->active_timings.width;
+	jpeg_dev->pix_fmt.height = jpeg_dev->active_timings.height;
+	jpeg_dev->pix_fmt.sizeimage = jpeg_dev->max_compressed_size;
+}
+
+static void phytium_jpeg_stop(struct phytium_jpeg_dev *jpeg_dev)
+{
+	set_bit(VIDEO_STOPPED, &jpeg_dev->status);
+	cancel_delayed_work_sync(&jpeg_dev->res_work);
+
+	phytium_jpeg_off(jpeg_dev);
+
+	jpeg_dev->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
+	jpeg_dev->status = 0;
+}
+
+static int phytium_jpeg_open(struct file *file)
+{
+	int ret;
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	mutex_lock(&jpeg_dev->video_lock);
+
+	ret = v4l2_fh_open(file);
+	if (ret != 0) {
+		mutex_unlock(&jpeg_dev->video_lock);
+		dev_err(jpeg_dev->dev, "Failed to open the phytium jpeg device.\n");
+		return ret;
+	}
+
+	if (v4l2_fh_is_singular_file(file))
+		phytium_jpeg_start(jpeg_dev);
+
+	mutex_unlock(&jpeg_dev->video_lock);
+
+	return 0;
+}
+
+static int phytium_jpeg_release(struct file *file)
+{
+	int ret;
+	struct phytium_jpeg_dev *jpeg_dev = video_drvdata(file);
+
+	mutex_lock(&jpeg_dev->video_lock);
+
+	if (v4l2_fh_is_singular_file(file))
+		phytium_jpeg_stop(jpeg_dev);
+
+	ret = _vb2_fop_release(file, NULL);
+	mutex_unlock(&jpeg_dev->video_lock);
+
+	return ret;
+}
+
+
+static const struct v4l2_file_operations phytium_jpeg_fops = {
+	.owner = THIS_MODULE,
+	.read = vb2_fop_read,
+	.poll = vb2_fop_poll,
+	.unlocked_ioctl = video_ioctl2,
+	.mmap = vb2_fop_mmap,
+	.open = phytium_jpeg_open,
+	.release = phytium_jpeg_release,
+};
+
+static void phytium_jpeg_update_jpeg_header(u32 width, u32 height)
+{
+	const int h_index = PHYTIUM_JPEG_HEADER_H_INDEX;
+	const int w_index = PHYTIUM_JPEG_HEADER_W_INDEX;
+
+	/* the high 8 bits of the height locates at bit24~bit31 */
+	phytium_jpeg_header[h_index] = phytium_jpeg_header[h_index] & 0x00FFFFFF;
+	phytium_jpeg_header[h_index] |= ((height >> 8) & 0xFF) << 24;
+
+	/* the low 8 bits of the height locates at bit0~bit7 */
+	phytium_jpeg_header[w_index] = phytium_jpeg_header[w_index] & 0xFF000000;
+	phytium_jpeg_header[w_index] |= height & 0xFF;
+
+	/* the high 8 bits of the width locates at bit8~bit15 */
+	phytium_jpeg_header[w_index] |= ((width >> 8) & 0xFF) << 8;
+	/* the low 8 bits of the width locates at bit16~bit24 */
+	phytium_jpeg_header[w_index] |= (width & 0xFF) << 16;
+}
+
+static void phytium_jpeg_fill_header(struct phytium_jpeg_dev *jpeg_dev,
+				     struct phytium_jpeg_buffer *jpeg_buf)
+{
+	void *vbuf = vb2_plane_vaddr(&jpeg_buf->vb.vb2_buf, 0);
+	u32 width = jpeg_dev->active_timings.width;
+	u32 height = jpeg_dev->active_timings.height;
+
+	/* update the contents of the phytium jpeg header according to the resolution */
+	phytium_jpeg_update_jpeg_header(width, height);
+
+	/* replenish the contents of the JPEG header */
+	memcpy(vbuf, phytium_jpeg_header, PHYTIUM_JPEG_HEADER_LEN);
+}
+
+static int phytium_jpeg_start_frame(struct phytium_jpeg_dev *jpeg_dev)
+{
+	dma_addr_t dst_addr;
+	unsigned long status;
+	struct phytium_jpeg_buffer *jpeg_buf;
+
+	if (jpeg_dev->v4l2_input_status) {
+		dev_err(jpeg_dev->dev, "No signal; needn't start frame\n");
+		return 0;
+	}
+
+	spin_lock_irqsave(&jpeg_dev->hw_lock, status);
+	jpeg_buf = list_first_entry_or_null(&jpeg_dev->buffers,
+					    struct phytium_jpeg_buffer, link);
+	if (jpeg_buf == NULL) {
+		spin_unlock_irqrestore(&jpeg_dev->hw_lock, status);
+		dev_err(jpeg_dev->dev, "No buffers; doesn't start frame\n");
+		return -EPROTO;
+	}
+
+	set_bit(VIDEO_FRAME_INPRG, &jpeg_dev->status);
+	dst_addr = vb2_dma_contig_plane_dma_addr(&jpeg_buf->vb.vb2_buf, 0);
+	spin_unlock_irqrestore(&jpeg_dev->hw_lock, status);
+
+	/*
+	 * Because the JPEG Engine is unable to add a JPEG header, the phytium
+	 * jpeg driver is required to fill the contents of a JPEG header before
+	 * the jpeg engine write datas to the dma address.
+	 */
+	phytium_jpeg_fill_header(jpeg_dev, jpeg_buf);
+	dst_addr += PHYTIUM_JPEG_HEADER_LEN;
+	/*
+	 * The ikvm application only using the last frame, so the driver replenish
+	 * one output register with a dma address.
+	 */
+	dst_addr >>= JPEG_DST_ADDR_SHIFT;
+	phytium_jpeg_write(jpeg_dev, BUF_LIST_INDEX_ADDR(VB_BUF_NO), dst_addr);
+	/* Enable the validilty of the buffer marked with index */
+	phytium_jpeg_write(jpeg_dev, BUF_LIST_INDEX_CTRL_STS_ADDR(VB_BUF_NO),
+						STS_JPEG_BUF_HIGH_LEVEL_VALID);
+	/* Enable the interruption which is used to identify an image was compressed */
+	phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG, 0, STS_VE_JPEG_CODE_COMP_EN);
+	/* Enable JPEG, start to capture and compress */
+	phytium_jpeg_update(jpeg_dev, TRANSFORM_INFO_REG, TRANSINFO_ENABLE_ENGINE, 1);
+
+	return 0;
+}
+
+static void phytium_jpeg_resolution_work(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct phytium_jpeg_dev *jpeg_dev = container_of(dwork,
+						struct phytium_jpeg_dev, res_work);
+	u32 input_status = jpeg_dev->v4l2_input_status;
+
+	phytium_jpeg_on(jpeg_dev);
+
+	/* Exit early in the case no clients remain */
+	if (test_bit(VIDEO_STOPPED, &jpeg_dev->status))
+		goto done;
+
+	phytium_jpeg_init_regs(jpeg_dev);
+	phytium_jpeg_get_resolution(jpeg_dev);
+
+	/* if source's resolution is changed, the event should be enqueued */
+	if (jpeg_dev->detected_timings.width != jpeg_dev->active_timings.width ||
+		jpeg_dev->detected_timings.height != jpeg_dev->active_timings.height ||
+		input_status != jpeg_dev->v4l2_input_status) {
+
+		static const struct v4l2_event event = {
+			.type = V4L2_EVENT_SOURCE_CHANGE,
+			.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
+		};
+		v4l2_event_queue(&jpeg_dev->vdev, &event);
+		clear_bit(VIDEO_FRAME_INPRG, &jpeg_dev->status);
+		dev_info(jpeg_dev->dev, "event notifies changing resolution\n");
+	} else if (test_bit(VIDEO_STREAMING, &jpeg_dev->status)) {
+		/* No resolution change so just restart streaming */
+		dev_info(jpeg_dev->dev, "resolution doesn't change\n");
+		phytium_jpeg_set_resolution(jpeg_dev);
+		phytium_jpeg_start_frame(jpeg_dev);
+	}
+
+done:
+	clear_bit(VIDEO_RES_CHANGE, &jpeg_dev->status);
+	wake_up_interruptible_all(&jpeg_dev->wait);
+}
+
+static int phytium_jpeg_queue_setup(struct vb2_queue *q,
+				    unsigned int *num_buffers,
+				    unsigned int *num_planes,
+				    unsigned int sizes[],
+				    struct device *alloc_devs[])
+{
+	struct phytium_jpeg_dev *jpeg_dev = vb2_get_drv_priv(q);
+
+	if (*num_planes) {
+		if (sizes[0] < jpeg_dev->max_compressed_size) {
+			v4l2_err(&jpeg_dev->v4l2_dev, "queue v4l2_buf's size is invalid\n");
+			return -EINVAL;
+		}
+	}
+
+	*num_planes = 1;
+	sizes[0] = jpeg_dev->max_compressed_size;
+	return 0;
+}
+
+static int phytium_jpeg_buf_prepare(struct vb2_buffer *vb)
+{
+	struct phytium_jpeg_dev *jpeg_dev = vb2_get_drv_priv(vb->vb2_queue);
+
+	if (vb2_plane_size(vb, 0) < jpeg_dev->max_compressed_size) {
+		v4l2_err(&jpeg_dev->v4l2_dev, "failed to prepare buffer\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static inline struct phytium_jpeg_buffer *
+phytium_vb2buf_to_dstbuf(struct vb2_v4l2_buffer *buf)
+{
+	return  container_of(buf, struct phytium_jpeg_buffer, vb);
+}
+
+static void phytium_jpeg_buf_queue(struct vb2_buffer *vb)
+{
+	bool empty;
+	struct phytium_jpeg_dev *jpeg_dev = vb2_get_drv_priv(vb->vb2_queue);
+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+	struct phytium_jpeg_buffer *jpeg_buf = phytium_vb2buf_to_dstbuf(vbuf);
+	unsigned long status;
+
+	spin_lock_irqsave(&jpeg_dev->hw_lock, status);
+	empty = list_empty(&jpeg_dev->buffers);
+	list_add_tail(&jpeg_buf->link, &jpeg_dev->buffers);
+	spin_unlock_irqrestore(&jpeg_dev->hw_lock, status);
+
+	/* the empty ensures the address of the first node's vb2_v4l2_buf
+	 * in the list is written to output register
+	 */
+	if (test_bit(VIDEO_STREAMING, &jpeg_dev->status) &&
+	    (!test_bit(VIDEO_FRAME_INPRG, &jpeg_dev->status)) &&
+	    empty)
+		phytium_jpeg_start_frame(jpeg_dev);
+}
+
+static void phytium_jpeg_bufs_done(struct phytium_jpeg_dev *jpeg_dev,
+				   enum vb2_buffer_state state)
+{
+	unsigned long flags;
+	struct phytium_jpeg_buffer *buf;
+
+	spin_lock_irqsave(&jpeg_dev->hw_lock, flags);
+
+	list_for_each_entry(buf, &jpeg_dev->buffers, link)
+		vb2_buffer_done(&buf->vb.vb2_buf, state);
+
+	INIT_LIST_HEAD(&jpeg_dev->buffers);
+
+	spin_unlock_irqrestore(&jpeg_dev->hw_lock, flags);
+}
+
+static void phytium_jpeg_irq_res_change(struct phytium_jpeg_dev *jpeg_dev,
+					ulong delay)
+{
+	dev_info(jpeg_dev->dev, "Source resolution is changed, resetting\n");
+	set_bit(VIDEO_RES_CHANGE, &jpeg_dev->status);
+
+	phytium_jpeg_off(jpeg_dev);
+
+	schedule_delayed_work(&jpeg_dev->res_work, delay);
+}
+
+static irqreturn_t phytium_jpeg_irq(int irq, void *arg)
+{
+	struct phytium_jpeg_dev *jpeg_dev = arg;
+	u32 status;
+	struct phytium_jpeg_buffer *buf;
+	u32 frame_size;
+
+	if (test_bit(VIDEO_POWEROFF, &jpeg_dev->status)) {
+		dev_info(jpeg_dev->dev, "jpeg engine is requested to poweroff\n");
+		return IRQ_HANDLED;
+	}
+
+	status = phytium_jpeg_read(jpeg_dev, INT_STATUS_CTRL_REG);
+
+	if (status & INT_VIDEO_FORMAT_CHANGE) {
+		dev_info(jpeg_dev->dev, "receive resolution changed interrupt\n");
+		phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG,
+				DETECT_RESOLUTION_CHANGE_EN, 0);
+		phytium_jpeg_write(jpeg_dev, INT_STATUS_CTRL_REG, INT_VIDEO_FORMAT_CHANGE);
+		phytium_jpeg_irq_res_change(jpeg_dev, RESOLUTION_CHANGE_DELAY);
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * JPEG engine finish compressing a image JPEG encoding to trigger
+	 * a interruption. the status identifies the buffer number. Currently,
+	 * the driver uses one buffer.
+	 *
+	 * Note: Because the JPEG doesn't support adding a JPEG header, and
+	 * driver is also unable to add a JPEG header to vb2_buffers. One
+	 * solution is that a JPEG header is added by an application.
+	 */
+	if (status & INT_JPEG_COMP_BUF_LIST_NO) {
+		frame_size = phytium_jpeg_read(jpeg_dev, jpeg_dev->comp_size_read);
+		frame_size &= JPEG_BUF_CAPACITY_SIZE;
+		frame_size >>= JPEG_BUF_CAPACITY_SIZE_SHIFT;
+		spin_lock(&jpeg_dev->hw_lock);
+		clear_bit(VIDEO_FRAME_INPRG, &jpeg_dev->status);
+		/* Delete first node from the queue */
+		buf = list_first_entry_or_null(&jpeg_dev->buffers,
+					       struct phytium_jpeg_buffer, link);
+		if (buf != NULL) {
+			frame_size += PHYTIUM_JPEG_HEADER_LEN;
+			vb2_set_plane_payload(&buf->vb.vb2_buf, 0, frame_size);
+			if (!list_is_last(&buf->link, &jpeg_dev->buffers)) {
+				buf->vb.vb2_buf.timestamp = ktime_get_ns();
+				buf->vb.sequence = jpeg_dev->sequence++;
+				buf->vb.field = V4L2_FIELD_NONE;
+				vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+				list_del(&buf->link);
+			}
+		}
+
+		spin_unlock(&jpeg_dev->hw_lock);
+		/* Disable JPEG engine */
+		phytium_jpeg_update(jpeg_dev, TRANSFORM_INFO_REG, TRANSINFO_ENABLE_ENGINE, 0);
+		/* Disable interruption */
+		phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG, STS_VE_JPEG_CODE_COMP_EN, 0);
+		/* clear all interruption of the hardware's buffers */
+		phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG, INT_JPEG_ENCODE_COMPLETE, 1);
+
+		status &= ~INT_JPEG_COMP_BUF_LIST_NO;
+		if (test_bit(VIDEO_STREAMING,  &jpeg_dev->status) && buf)
+			phytium_jpeg_start_frame(jpeg_dev);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/* VIDIOC_STREAMON, all vb2_v4l2_buf' states are queue */
+static int phytium_jpeg_start_streaming(struct vb2_queue *q, unsigned int count)
+{
+	int ret;
+	struct phytium_jpeg_dev *jpeg_dev = vb2_get_drv_priv(q);
+
+	jpeg_dev->sequence = 0;
+	ret = phytium_jpeg_start_frame(jpeg_dev);
+	if (ret != 0) {
+		phytium_jpeg_bufs_done(jpeg_dev, VB2_BUF_STATE_QUEUED);
+		return ret;
+	}
+
+	/* set the states of the jpeg engine */
+	set_bit(VIDEO_STREAMING, &jpeg_dev->status);
+	return ret;
+}
+
+static void phytium_jpeg_stop_streaming(struct vb2_queue *q)
+{
+	int ret;
+	struct phytium_jpeg_dev *jpeg_dev = vb2_get_drv_priv(q);
+
+	clear_bit(VIDEO_STREAMING, &jpeg_dev->status);
+	ret = wait_event_timeout(jpeg_dev->wait,
+				 !test_bit(VIDEO_FRAME_INPRG, &jpeg_dev->status),
+				 STOP_TIMEOUT);
+
+	/* time out */
+	if (ret == 0) {
+		dev_err(jpeg_dev->dev, "Timed out when stopping streaming.\n");
+		/*
+		 * Need to force stop any DMA and try and get HW into a good states
+		 * for future calls to start streaming again.
+		 */
+		phytium_jpeg_off(jpeg_dev);
+		phytium_jpeg_on(jpeg_dev);
+		phytium_jpeg_init_regs(jpeg_dev);
+		phytium_jpeg_get_resolution(jpeg_dev);
+	}
+	/* first stop jpeg, wait, the free buffer */
+	phytium_jpeg_bufs_done(jpeg_dev, VB2_BUF_STATE_ERROR);
+}
+
+static const struct vb2_ops phytium_jpeg_vb2_ops = {
+	.queue_setup = phytium_jpeg_queue_setup,
+	.wait_prepare = vb2_ops_wait_prepare,
+	.wait_finish = vb2_ops_wait_finish,
+	.buf_prepare = phytium_jpeg_buf_prepare,
+	.buf_queue = phytium_jpeg_buf_queue,
+	.start_streaming = phytium_jpeg_start_streaming,
+	.stop_streaming = phytium_jpeg_stop_streaming,
+};
+
+static void phytium_jpeg_set_yuv_mode(struct phytium_jpeg_dev *jpeg_dev)
+{
+	const char *mode = yuv_mode_str;
+	enum jpeg_yuv_mode yuv_mode;
+
+	if (strstr(mode, "yuv422") != NULL)
+		yuv_mode = YUV422;
+	else if (strstr(mode, "yuv420") != NULL)
+		yuv_mode = YUV420;
+	else
+		yuv_mode = YUV444;
+
+	/* set the yuv mode register */
+	phytium_jpeg_write(jpeg_dev, SAMPLE_MODE_REG, yuv_mode);
+
+	/* update the field which indicates YUV mode locates in the JPEG header. */
+	phytium_jpeg_header[YUVID] &= 0xFFFF00FF;
+	if (yuv_mode == YUV422)
+		phytium_jpeg_header[YUVID] |= 0x2100;
+	else if (yuv_mode == YUV420)
+		phytium_jpeg_header[YUVID] |= 0x2200;
+	else
+		phytium_jpeg_header[YUVID] |= 0x1100;
+
+}
+
+static irqreturn_t phytium_jpeg_timer31_irq(int irq, void *arg)
+{
+	struct phytium_jpeg_dev *jpeg_dev = arg;
+
+	/* disable timer interrupt */
+	writel(0, jpeg_dev->timer31_addr);
+
+	/* clear timer interrupt status */
+	writel(0x8, jpeg_dev->timer31_addr + 0x2c);
+
+	/* clear JPEG Engine's  poweroff status */
+	clear_bit(VIDEO_POWEROFF, &jpeg_dev->status);
+	dev_info(jpeg_dev->dev, "timer31 set jpeg status 0x%lx\n", jpeg_dev->status);
+
+	/* JPEG Engine is poweron, reconfig quntization table and YUV mode */
+	phytium_jpeg_init_jpeg_quant(jpeg_dev);
+	phytium_jpeg_set_yuv_mode(jpeg_dev);
+	phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG, 0, DETECT_RESOLUTION_CHANGE_EN);
+	phytium_jpeg_update(jpeg_dev, TRANSFORM_INFO_REG, 0, TRANSINFO_SRC_SELECT);
+
+	dev_info(jpeg_dev->dev, "reconfigure quant table and yuv mode\n");
+
+	return IRQ_HANDLED;
+}
+
+static int phytium_jpeg_parser_timer31_irq(struct phytium_jpeg_dev *jpeg_dev)
+{
+	int irq;
+	int ret;
+	struct device *dev = jpeg_dev->dev;
+
+	irq = irq_of_parse_and_map(dev->of_node, 2);
+	if (!irq) {
+		dev_err(dev, "Failed to get timer31 IRQ\n");
+		return -ENODEV;
+	}
+
+	ret = devm_request_threaded_irq(dev, irq, NULL, phytium_jpeg_timer31_irq,
+			IRQF_ONESHOT, PHYTIUM_JPEG_NAME, jpeg_dev);
+	if (ret < 0)
+		dev_err(dev, "Failed to request timer31 IRQ %d\n", irq);
+
+	return ret;
+}
+
+static irqreturn_t phytium_jpeg_timer30_irq(int irq, void *arg)
+{
+	struct phytium_jpeg_dev *jpeg_dev = arg;
+	struct arm_smccc_res res;
+
+	/* disable timer interrupt */
+	writel(0, jpeg_dev->timer30_addr);
+	/* clear timer interrupt status */
+	writel(0x8, jpeg_dev->timer30_addr + 0x2c);
+
+	/* Disable interruption */
+	phytium_jpeg_update(jpeg_dev, INT_STATUS_CTRL_REG, STS_VE_JPEG_CODE_COMP_EN, 0);
+
+	/* call SE to poweroff JPEG Engine */
+	arm_smccc_smc(0xc300fff4, 0x9, 0x2, 0x80000020, 0, 0, 0, 0, &res);
+
+	/* set JPEG Engine's status is poweroff */
+	set_bit(VIDEO_POWEROFF, &jpeg_dev->status);
+	dev_info(jpeg_dev->dev, "timer30 set jpeg status 0x%lx\n", jpeg_dev->status);
+
+	return IRQ_HANDLED;
+}
+
+static int phytium_jpeg_parser_timer30_irq(struct phytium_jpeg_dev *jpeg_dev)
+{
+	int irq;
+	int ret;
+	struct device *dev = jpeg_dev->dev;
+
+	irq = irq_of_parse_and_map(dev->of_node, 1);
+	if (!irq) {
+		dev_err(dev, "Failed to get timer30 IRQ\n");
+		return -ENODEV;
+	}
+
+	ret = devm_request_threaded_irq(dev, irq, NULL, phytium_jpeg_timer30_irq,
+			IRQF_ONESHOT, PHYTIUM_JPEG_NAME, jpeg_dev);
+	if (ret < 0)
+		dev_err(dev, "Failed to request timer30 IRQ %d\n", irq);
+
+	return ret;
+}
+
+static int phytium_jpeg_init(struct phytium_jpeg_dev *jpeg_dev)
+{
+	int irq;
+	int ret;
+	struct device *dev = jpeg_dev->dev;
+	u32 ocm_buf_addr[OCM_BUF_NUM];
+	int i;
+
+	irq = irq_of_parse_and_map(dev->of_node, 0);
+	if (!irq) {
+		dev_err(dev, "Failed to get IRQ\n");
+		return -ENODEV;
+	}
+
+	ret = devm_request_threaded_irq(dev, irq, NULL, phytium_jpeg_irq,
+				IRQF_ONESHOT, PHYTIUM_JPEG_NAME, jpeg_dev);
+	if (ret < 0) {
+		dev_err(dev, "Failed to request IRQ %d\n", irq);
+		return ret;
+	}
+
+	ret = phytium_jpeg_parser_timer30_irq(jpeg_dev);
+	if (ret < 0)
+		return ret;
+
+	ret = phytium_jpeg_parser_timer31_irq(jpeg_dev);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_u32_array(dev->of_node, "phytium,ocm-buf-addr",
+					ocm_buf_addr, OCM_BUF_NUM);
+	if (ret != 0) {
+		dev_err(dev, "Failed to get the OCM address from device tree node.\n");
+		return ret;
+	}
+
+	for (i = 0; i < OCM_BUF_NUM; i++)
+		jpeg_dev->src_addrs[i].dma_addr = ocm_buf_addr[i];
+
+	/* CMA memory for JPEG device */
+	of_reserved_mem_device_init(dev);
+	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+	if (ret != 0) {
+		dev_err(dev, "Failed to set DMA mask\n");
+		return ret;
+	}
+
+	/* Initializing JPEG Y and CbCr quantization table */
+	phytium_jpeg_init_jpeg_quant(jpeg_dev);
+
+	/* Select YUV mode */
+	phytium_jpeg_set_yuv_mode(jpeg_dev);
+	dev_info(dev, "successfully initialize jpeg engine\n");
+	return 0;
+
+}
+
+
+static int phytium_jpeg_setup_video(struct phytium_jpeg_dev *jpeg_dev)
+{
+	struct v4l2_device *v4l2_dev = &jpeg_dev->v4l2_dev;
+	struct vb2_queue *dst_vq = &jpeg_dev->queue;
+	struct video_device *vdev = &jpeg_dev->vdev;
+	int ret;
+
+	jpeg_dev->pix_fmt.pixelformat = V4L2_PIX_FMT_JPEG;
+	jpeg_dev->pix_fmt.field = V4L2_FIELD_NONE;
+	jpeg_dev->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB; /* maybe ARGB */
+	jpeg_dev->pix_fmt.quantization =  V4L2_QUANTIZATION_FULL_RANGE;
+	jpeg_dev->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
+
+	ret = v4l2_device_register(jpeg_dev->dev, v4l2_dev);
+	if (ret != 0) {
+		dev_err(jpeg_dev->dev, "Failed to register v4l2 device\n");
+		return ret;
+	}
+
+	/* Register how many v4l2 controls to a handler */
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	dst_vq->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
+	dst_vq->dev = v4l2_dev->dev;
+	dst_vq->lock = &jpeg_dev->video_lock;
+	dst_vq->ops = &phytium_jpeg_vb2_ops;
+	dst_vq->mem_ops = &vb2_dma_contig_memops;
+	dst_vq->drv_priv = jpeg_dev;
+	dst_vq->buf_struct_size = sizeof(struct phytium_jpeg_buffer);
+	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+	dst_vq->min_buffers_needed = CAPTURE_BUF_NUMBER;
+	ret = vb2_queue_init(dst_vq);
+	if (ret) {
+		dev_err(jpeg_dev->dev, "Failed to init vb2 queue\n");
+		goto err_v4l2_register;
+	}
+
+	vdev->queue = dst_vq;
+	vdev->fops = &phytium_jpeg_fops;
+	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
+			    V4L2_CAP_STREAMING;
+	vdev->v4l2_dev = v4l2_dev;
+	strscpy(vdev->name, PHYTIUM_JPEG_NAME, sizeof(vdev->name));
+	vdev->vfl_type = VFL_TYPE_VIDEO;
+	vdev->vfl_dir = VFL_DIR_RX;
+	vdev->release = video_device_release_empty;
+	vdev->ioctl_ops = &phytium_jpeg_ioctl_ops;
+	vdev->lock = &jpeg_dev->video_lock;
+
+	video_set_drvdata(vdev, jpeg_dev);
+	ret = video_register_device(vdev, VFL_TYPE_VIDEO, 0);
+	if (ret != 0) {
+		dev_err(jpeg_dev->dev, "Failed to register video device\n");
+		goto err_video_register;
+	}
+
+	v4l2_info(v4l2_dev, "phytium JPEG registered as /dev/video%d (%d, %d)\n",
+			jpeg_dev->vdev.num, VIDEO_MAJOR, jpeg_dev->vdev.minor);
+	return ret;
+
+err_video_register:
+	vb2_queue_release(dst_vq);
+
+err_v4l2_register:
+	v4l2_device_unregister(v4l2_dev);
+	return ret;
+}
+
+static const struct phytium_jpeg_config phytium_jpeg_config = {
+	.comp_size_read = BUF_LIST_INDEX_CTRL_STS_ADDR(VB_BUF_NO),
+};
+
+static const struct of_device_id phytium_jpeg_match[] = {
+	{
+	    .compatible = "phytium,jpeg",
+	    .data = &phytium_jpeg_config,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, phytium_jpeg_match);
+
+static int phytium_jpeg_probe(struct platform_device *pdev)
+{
+	struct phytium_jpeg_dev *jpeg_dev;
+	const struct of_device_id *match;
+	const struct phytium_jpeg_config *config;
+	struct resource *res;
+	int ret;
+
+	jpeg_dev = devm_kzalloc(&pdev->dev, sizeof(*jpeg_dev), GFP_KERNEL);
+	if (jpeg_dev == NULL)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	jpeg_dev->base_addr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(jpeg_dev->base_addr)) {
+		dev_err(jpeg_dev->dev, "Failed to ioremap.\n");
+		return PTR_ERR(jpeg_dev->base_addr);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	jpeg_dev->timer30_addr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(jpeg_dev->base_addr)) {
+		dev_err(jpeg_dev->dev, "Failed to parse timer30.\n");
+		return PTR_ERR(jpeg_dev->timer30_addr);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	jpeg_dev->timer31_addr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(jpeg_dev->base_addr)) {
+		dev_err(jpeg_dev->dev, "Failed to parse timer30.\n");
+		return PTR_ERR(jpeg_dev->timer31_addr);
+	}
+	match = of_match_node(phytium_jpeg_match, pdev->dev.of_node);
+	if (match == NULL) {
+		dev_err(jpeg_dev->dev, "Failed to match.\n");
+		return -EINVAL;
+	}
+
+	config = match->data;
+	jpeg_dev->comp_size_read = config->comp_size_read;
+
+	jpeg_dev->frame_rate = 30;
+	jpeg_dev->dev = &pdev->dev;
+	spin_lock_init(&jpeg_dev->hw_lock);
+	mutex_init(&jpeg_dev->video_lock);
+	init_waitqueue_head(&jpeg_dev->wait);
+	INIT_DELAYED_WORK(&jpeg_dev->res_work, phytium_jpeg_resolution_work);
+	INIT_LIST_HEAD(&jpeg_dev->buffers);
+
+	ret = phytium_jpeg_init(jpeg_dev);
+	if (ret != 0) {
+		dev_err(jpeg_dev->dev, "Failed to initialize the JPEG engine.\n");
+		return ret;
+	}
+
+	ret = phytium_jpeg_setup_video(jpeg_dev);
+
+	return ret;
+}
+
+#define to_phytium_jpeg(x) container_of((x), struct phytium_jpeg_dev, v4l2_dev)
+static int phytium_jpeg_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
+	struct phytium_jpeg_dev *jpeg_dev = to_phytium_jpeg(v4l2_dev);
+
+	phytium_jpeg_off(jpeg_dev);
+
+	video_unregister_device(&jpeg_dev->vdev);
+
+	vb2_queue_release(&jpeg_dev->queue);
+
+	v4l2_device_unregister(v4l2_dev);
+
+	of_reserved_mem_device_release(dev);
+
+	return 0;
+}
+
+static struct platform_driver phytium_jpeg_driver = {
+	.probe = phytium_jpeg_probe,
+	.remove =  phytium_jpeg_remove,
+	.driver =  {
+	    .name = PHYTIUM_JPEG_NAME,
+	    .of_match_table = phytium_jpeg_match,
+	},
+};
+
+module_platform_driver(phytium_jpeg_driver);
+
+MODULE_DESCRIPTION("Phytium JPEG Encoder driver");
+MODULE_AUTHOR("Wang Min <wangmin@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h
new file mode 100644
index 00000000000000..1c2b55b651f81b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_core.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef _PHYTIUM_JPEG_CORE_H
+#define _PHYTIUM_JPEG_CORE_H
+
+#include <linux/atomic.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/v4l2-controls.h>
+#include <linux/videodev2.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-dv-timings.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+
+#define PHYTIUM_JPEG_NAME       "phytium-jpeg"
+#define MAX_FRAME_RATE          60
+#define MAX_HEIGHT              1080
+#define MAX_WIDTH               1920
+#define MIN_HEIGHT              480
+#define MIN_WIDTH               640
+#define MIN_PIXEL_CLOCK         (640 * 480 * 60)     /* 640 x 480 x 60Hz */
+#define MAX_PIXEL_CLOCK         (1920 * 1080 * 60)   /* 1920 x 1080 x 60Hz */
+
+#define SOURCE_RESOLUTION_DETECT_TIMEOUT    msecs_to_jiffies(500)
+#define RESOLUTION_CHANGE_DELAY             msecs_to_jiffies(0)
+#define INVALID_RESOLUTION_DELAY            msecs_to_jiffies(250)
+#define STOP_TIMEOUT                        msecs_to_jiffies(1000)
+
+#define INVALID_RESOLUTION_RETRIES   2
+#define CAPTURE_BUF_NUMBER           3  /* using how many buffers */
+#define VB_BUF_NO                    0  /* there are 16 buffer, use which one */
+
+/* The below macros are defined for the JPEG header of the phytium JPEG Engine */
+#define PHYTIUM_JPEG_HEADER_LEN		(256 * 3)
+#define PHYTIUM_JPEG_HEADER_SIZE        (PHYTIUM_JPEG_HEADER_LEN / sizeof(u32))
+#define PHYTIUM_JPEG_HEADER_H_INDEX     40
+#define PHYTIUM_JPEG_HEADER_W_INDEX     41
+
+/* There are two ocm buffers that are used for storaging the inputing video data */
+#define OCM_BUF_NUM			2
+
+enum phytium_jpeg_status {
+	VIDEO_MODE_DETECT_DONE,
+	VIDEO_RES_CHANGE,
+	VIDEO_RES_DETECT,
+	VIDEO_STREAMING,
+	VIDEO_FRAME_INPRG,
+	VIDEO_STOPPED,
+	VIDEO_CLOCKS_ON,
+	VIDEO_POWEROFF,
+};
+
+struct phytium_jpeg_addr {
+	unsigned int size;
+	dma_addr_t  dma_addr;
+	void    *virt_addr;
+};
+
+struct phytium_jpeg_buffer {
+	struct vb2_v4l2_buffer vb;
+	struct list_head link;
+};
+
+/**
+ * struct phytium_jpeg - JPEG IP abstraction
+ * @lock:	  the mutex protecting this structure
+ * @hw_lock:	  spinlock protecting the hw device resource
+ * @workqueue:	  decode work queue
+ * @dev:	  JPEG device
+ * @v4l2_dev:	  v4l2 device for mem2mem mode
+ * @m2m_dev:	  v4l2 mem2mem device data
+ * @alloc_ctx:	  videobuf2 memory allocator's context
+ * @dec_vdev:	  video device node for decoder mem2mem mode
+ * @dec_reg_base: JPEG registers mapping
+ * @clk_jdec:	  JPEG hw working clock
+ * @clk_jdec_smi: JPEG SMI bus clock
+ * @larb:	  SMI device
+ */
+struct phytium_jpeg_dev {
+	void __iomem *base_addr;
+	struct device *dev;
+	struct v4l2_device v4l2_dev;
+	struct v4l2_pix_format pix_fmt;
+	struct v4l2_bt_timings active_timings;
+	struct v4l2_bt_timings detected_timings;
+	u32    v4l2_input_status;
+	struct vb2_queue queue;
+	struct video_device vdev;
+	/* v4l2 and videobuf2 lock, protect the structure*/
+	struct mutex video_lock;
+	u32 jpeg_mode;
+	u32 comp_size_read;
+	wait_queue_head_t wait;
+	/* buffer list lock, protecting the hw device resource */
+	spinlock_t hw_lock;
+	struct delayed_work res_work;
+	struct list_head buffers;
+	unsigned long status;
+	unsigned int sequence;
+	unsigned int max_compressed_size;
+	struct phytium_jpeg_addr src_addrs[OCM_BUF_NUM];
+	struct phytium_jpeg_addr dst_addrs[16];
+
+	bool yuv420;
+	unsigned int frame_rate;
+	void __iomem *timer30_addr;
+	void __iomem *timer31_addr;
+};
+
+struct phytium_jpeg_config {
+	u32 jpeg_mode;
+	u32 comp_size_read;
+};
+
+#define		YUV_MODE_STR_LEN	8
+#define		YUVID			42
+
+enum jpeg_yuv_mode {
+	YUV444 = 0x0,
+	YUV422 = 0x1,
+	YUV420 = 0x2
+};
+
+#endif  /* _PHYTIUM_JPEG_CORE_H */
diff --git a/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h
new file mode 100644
index 00000000000000..3567badf9eb501
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/media/platform/phytium-jpeg/phytium_jpeg_reg.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef _PHYTIUM_JPEG_REG_H
+#define _PHYTIUM_JPEG_REG_H
+
+#include <linux/bits.h>
+/* define the all kinds of control registers in a JPEG soc */
+
+/* The register is used to set the information of the video comes from main memory */
+#define SRC_DDR_INFO_REG	0x00000800
+
+/* The register is used to get the information of the video comes from external VGA */
+#define SRC_VGA_INFO_REG	0x00000894
+
+#define SRC_FORMAT		BIT(0)		 /* 0:RGB888, 1:RGB565 */
+#define SRC_DE_POLARITY		BIT(1)		 /* 0:low level is effect, other */
+#define SRC_HS_POLARITY		BIT(2)		 /* 0:low level is effect, other */
+#define SRC_VS_POLARITY		BIT(3)		 /* 0:low level is effect, other */
+#define SRC_HOR_PIXELS		GENMASK(15, 4)	 /* the number of the horizontal pixels */
+#define SRC_WIDTH_SHIFT		4		 /* shift right to get width */
+#define SRC_VER_PIXELS		GENMASK(26, 16)	 /* the number of the vertical pixels */
+#define SRC_HEIGHT_SHIFT	16		 /* shift right to get height */
+/* The below bit fields is only used by image comes from main memory */
+#define SRC_COMP_DDR_IMG_EN	BIT(27)		 /* 0: disable to JPEG compression, others */
+
+/* marks which ocm buffer is occupied to store an image */
+#define SRC_DDR_IMG2OCM_VALID	GENMASK(29, 28)
+
+/* The register controls starting work of the JPEG engine */
+#define TRANSFORM_INFO_REG	0x00000804
+#define TRANSINFO_ENABLE_ENGINE	BIT(0)	 /* 1: enable the JPEG engine */
+/* 1: video comes from external VGA, 0: video comes from DDR */
+#define TRANSINFO_SRC_SELECT	BIT(1)
+/* 0: video comes from external VGA is cached to OCM, 1: DDR */
+#define TRANSINFO_IMAGE_STORE	BIT(2)
+#define TRANSINFO_FRAME_RATE	GENMASK(9, 4)    /* the value notes frame rate */
+#define TRANSINFO_BLOCK_SIZE	BIT(12)          /* 0: 8x8, 1: 16x16 */
+#define TRANSINFO_ENABLE_YUV422	BIT(13)          /* 1: JPEG block is populated YUV422 */
+/* support burst with the values such as 1, 2, 4, 8, 16, 32, 64. using default value 0xf */
+#define TRANSINFO_AXI_LEN	GENMASK(22, 16)
+#define TRANS_AXI_LEN_SHIFT	16
+
+/* The interrupt and status register */
+#define INT_STATUS_CTRL_REG		0x00000808
+#define INT_FIFO_OVERFLOW		BIT(0)	/* video fifo overflow, write 1 to clear */
+#define INT_OCM_BUF_OVERFLOW		BIT(1)	/* ocm buffer overflow, write 1 to clear */
+/* JPEG engine complete compression, write 1 to clear */
+#define INT_JPEG_ENCODE_COMPLETE	BIT(2)
+/* in VGA mode, video's format is changed */
+#define INT_VIDEO_FORMAT_CHANGE		BIT(3)
+/* enable the interrupt of th video fifo overflow and source resolution */
+#define DETECT_RESOLUTION_CHANGE_EN	BIT(4)
+/* enable the interrupt of the ocm buffer overflow */
+#define STS_VE_OCM_BUF_OVERFLOW_EN	BIT(5)
+/* enable the interrupt of the JPEG complete compression */
+#define STS_VE_JPEG_CODE_COMP_EN	BIT(6)
+/* in VGA mode, the bit notes ocm buff is busy */
+#define STS_VE_OCM_BUF_BUSY		BIT(7)
+/* in VGA mode, the bit notes sequence number of the frame */
+#define STS_VE_CUR_FRAME_NUMBER		GENMASK(9, 8)
+/* in VGA mode, the bit notes sequence number of the cached frame */
+#define STS_VE_BUF_CACHE_NUMBER		GENMASK(11, 10)
+/* in VGA mode, the buffer number in buffer list */
+#define STS_JPEG_COMP_BUF_NO		GENMASK(15, 12)
+#define INT_JPEG_COMP_BUF_LIST_NO	GENMASK(31, 16)	/* the interrupt number of the buffer */
+
+#define OCM_BUF0_ADDR	0x0000080C
+#define OCM_BUF1_ADDR	0x00000810
+#define OCM_BUF_SHIFT	8
+
+#define BUF_LIST_BASE_ADDR	0x00000814
+
+#define PHYTIUM_BUF_LIST_ACTRL_AND_STS_BASE_ADDR_REG	0x00000818
+#define STS_JPEG_BUF_HIGH_LEVEL_VALID		BIT(0)		/* Hight levle is validity */
+#define JPEG_BUF_CAPACITY_SIZE			GENMASK(29, 8)	/* the capacity of the  buffer */
+#define JPEG_BUF_CAPACITY_SIZE_SHIFT		8
+
+/* There are 16 buffers in the buffer list, the width between each other' address is 8 bytes */
+#define BUF_LIST_ADDR_OFFSET		0x8
+#define BUF_LIST_CTRL_AND_STS_OFFSET	0x8
+
+/* Get the address of the specific index buffer */
+#define BUF_LIST_INDEX_ADDR(index)  \
+	(BUF_LIST_BASE_ADDR + (index) * BUF_LIST_ADDR_OFFSET)
+
+#define JPEG_DST_ADDR_SHIFT    8
+
+#define BUF_LIST_INDEX_CTRL_STS_ADDR(index)  \
+	(PHYTIUM_BUF_LIST_ACTRL_AND_STS_BASE_ADDR_REG + (index) * BUF_LIST_CTRL_AND_STS_OFFSET)
+
+#define FRAME_SAMPLE_CTRL	0x00000898
+#define FRAME_SAMPLE_CTRL_EN	BIT(31)
+#define FRAME_SAMPLE_INTERVAL	GENMASK(30, 0)
+
+/* The below registers are all related to quantilize */
+#define HUFF_MODE_REG		0x300
+#define SAMPLE_MODE_REG		0x304
+
+#define Y_QUANT_BASE_ADDR_REG	0x400
+#define C_QUANT_BASE_ADDR_REG	0x500
+
+#define QUANT_REG_NUM		64
+
+#define Y_QUANT_INDEX_ADDR_REG(index)   \
+	(Y_QUANT_BASE_ADDR_REG + 4 * (index))
+
+#define C_QUANT_INDEX_ADDR_REG(index)   \
+	(C_QUANT_BASE_ADDR_REG + 4 * (index))
+
+#endif  /* _PHYTIUM_JPEG_REG_H */
diff --git a/target/linux/phytium/files-5.10/drivers/mfd/phytium_px210_i2s_lsd.c b/target/linux/phytium/files-5.10/drivers/mfd/phytium_px210_i2s_lsd.c
new file mode 100644
index 00000000000000..a76b5d7708f19e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mfd/phytium_px210_i2s_lsd.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium I2S LSD MFD driver over PCI bus
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/mfd/core.h>
+
+struct phytium_px210_mfd {
+	struct device		*dev;
+};
+
+struct pdata_px210_mfd {
+	struct device		*dev;
+	char			*name;
+	int			clk_base;
+};
+
+static struct resource phytium_px210_i2s_res0[] = {
+	[0] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct mfd_cell phytium_px210_mfd_cells[] = {
+	{
+		.id = 0,
+		.name = "phytium-i2s",
+		.of_compatible = "phytium,i2s",
+		.resources = phytium_px210_i2s_res0,
+		.num_resources = ARRAY_SIZE(phytium_px210_i2s_res0),
+		.ignore_resource_conflicts = true,
+	},
+};
+
+static void phytium_px210_i2s_setup(struct pci_dev *pdev)
+{
+	struct mfd_cell *cell = &phytium_px210_mfd_cells[0];
+	struct resource *res = (struct resource *)cell->resources;
+	struct pdata_px210_mfd *pdata;
+
+	res[0].start = pci_resource_start(pdev, 0);
+	res[0].end = pci_resource_start(pdev, 0) + 0x0fff;
+
+	res[1].start = pci_resource_start(pdev, 0) + 0x1000;
+	res[1].end = pci_resource_start(pdev, 0) + 0x1fff;
+
+	res[2].start = pdev->irq;
+	res[2].end = pdev->irq;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+
+	pdata->dev = &pdev->dev;
+	pdata->name = "phytium-i2s-lsd";
+	pdata->clk_base = 480000000;
+
+	cell->platform_data = pdata;
+	cell->pdata_size = sizeof(*pdata);
+}
+
+static int phytium_px210_mfd_probe(struct pci_dev *pdev,
+				 const struct pci_device_id *id)
+{
+	struct phytium_px210_mfd *phytium_mfd;
+	int ret;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	pci_set_master(pdev);
+
+	phytium_mfd = devm_kzalloc(&pdev->dev, sizeof(*phytium_mfd), GFP_KERNEL);
+	if (!phytium_mfd)
+		return -ENOMEM;
+
+	phytium_mfd->dev = &pdev->dev;
+	dev_set_drvdata(&pdev->dev, phytium_mfd);
+
+	phytium_px210_i2s_setup(pdev);
+
+	ret = mfd_add_devices(&pdev->dev, 0, phytium_px210_mfd_cells,
+			      ARRAY_SIZE(phytium_px210_mfd_cells), NULL, 0,
+			      NULL);
+	if (ret)
+		return 0;
+
+	return 0;
+}
+
+
+static void phytium_px210_mfd_remove(struct pci_dev *pdev)
+{
+	mfd_remove_devices(&pdev->dev);
+}
+
+static const struct pci_device_id phytium_px210_mfd_ids[] = {
+	{
+		.vendor		= 0x1DB7,
+		.device		= 0xDC2B,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.class		= 0x3,
+		.class_mask	= 0,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(pci, phytium_px210_mfd_ids);
+
+static struct pci_driver phytium_i2s_lsd_mfd_driver = {
+	.name		= "phytium_px210_mfd_i2s",
+	.id_table	= phytium_px210_mfd_ids,
+	.probe		= phytium_px210_mfd_probe,
+	.remove		= phytium_px210_mfd_remove,
+};
+
+module_pci_driver(phytium_i2s_lsd_mfd_driver);
+
+MODULE_AUTHOR("Yiqun Zhang <zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium Px210 MFD PCI driver for I2S-LSD");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/mfd/phytium_px210_i2s_mmd.c b/target/linux/phytium/files-5.10/drivers/mfd/phytium_px210_i2s_mmd.c
new file mode 100644
index 00000000000000..4020686d4ce2e8
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mfd/phytium_px210_i2s_mmd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium I2S MMD MFD driver over PCI bus
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/mfd/core.h>
+
+struct phytium_px210_mfd {
+	struct device		*dev;
+};
+
+struct pdata_px210_mfd {
+	struct device		*dev;
+	char			*name;
+	int			clk_base;
+};
+
+static struct resource phytium_px210_i2s_res0[] = {
+	[0] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct resource phytium_px210_i2s_res1[] = {
+	[0] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct resource phytium_px210_i2s_res2[] = {
+	[0] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct mfd_cell phytium_px210_mfd_cells[] = {
+	{
+		.id = 1,
+		.name = "phytium-i2s",
+		.of_compatible = "phytium,i2s",
+		.resources = phytium_px210_i2s_res0,
+		.num_resources = ARRAY_SIZE(phytium_px210_i2s_res0),
+		.ignore_resource_conflicts = true,
+	},
+	{
+		.id = 2,
+		.name = "phytium-i2s",
+		.of_compatible = "phytium,i2s",
+		.resources = phytium_px210_i2s_res1,
+		.num_resources = ARRAY_SIZE(phytium_px210_i2s_res1),
+		.ignore_resource_conflicts = true,
+	},
+	{
+		.id = 3,
+		.name = "phytium-i2s",
+		.of_compatible = "phytium,i2s",
+		.resources = phytium_px210_i2s_res2,
+		.num_resources = ARRAY_SIZE(phytium_px210_i2s_res2),
+		.ignore_resource_conflicts = true,
+	},
+};
+
+static void phytium_px210_i2s_setup(struct pci_dev *pdev, int i)
+{
+	struct mfd_cell *cell = &phytium_px210_mfd_cells[i];
+	struct resource *res = (struct resource *)cell->resources;
+	struct pdata_px210_mfd *pdata;
+
+	res[0].start = pci_resource_start(pdev, 0) + 0x2000 * i + 0x1000;
+	res[0].end = pci_resource_start(pdev, 0) + 0x2000 * i + 0x1fff;
+
+	res[1].start = pci_resource_start(pdev, 0) + 0x2000 * i;
+	res[1].end = pci_resource_start(pdev, 0) + 0x2000 * i + 0x0fff;
+
+	res[2].start = pdev->irq;
+	res[2].end = pdev->irq;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+
+	pdata->dev = &pdev->dev;
+	pdata->clk_base = 600000000;
+	switch (i) {
+	case 0:
+		pdata->name = "phytium-i2s-dp0";
+		break;
+	case 1:
+		pdata->name = "phytium-i2s-dp1";
+		break;
+	case 2:
+		pdata->name = "phytium-i2s-dp2";
+		break;
+	default:
+		break;
+	}
+
+	cell->platform_data = pdata;
+	cell->pdata_size = sizeof(*pdata);
+}
+
+static int phytium_px210_mfd_probe(struct pci_dev *pdev,
+				 const struct pci_device_id *id)
+{
+	struct phytium_px210_mfd *phytium_mfd;
+	int i;
+	int ret;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	pci_set_master(pdev);
+
+	phytium_mfd = devm_kzalloc(&pdev->dev, sizeof(*phytium_mfd), GFP_KERNEL);
+	if (!phytium_mfd)
+		return -ENOMEM;
+
+	phytium_mfd->dev = &pdev->dev;
+	dev_set_drvdata(&pdev->dev, phytium_mfd);
+
+	for (i = 0; i < 3; i++)
+		phytium_px210_i2s_setup(pdev, i);
+
+	ret = mfd_add_devices(&pdev->dev, 0, phytium_px210_mfd_cells,
+			      ARRAY_SIZE(phytium_px210_mfd_cells), NULL, 0,
+			      NULL);
+	if (ret)
+		return 0;
+
+	return 0;
+}
+
+
+static void phytium_px210_mfd_remove(struct pci_dev *pdev)
+{
+	mfd_remove_devices(&pdev->dev);
+}
+
+static const struct pci_device_id phytium_px210_mfd_ids[] = {
+	{
+		.vendor		= 0x1DB7,
+		.device		= 0xDC23,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.class		= 0x3,
+		.class_mask	= 0,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(pci, phytium_px210_mfd_ids);
+
+static struct pci_driver phytium_i2s_mmd_mfd_driver = {
+	.name		= "phytium_px210_mfd_mmd",
+	.id_table	= phytium_px210_mfd_ids,
+	.probe		= phytium_px210_mfd_probe,
+	.remove		= phytium_px210_mfd_remove,
+};
+
+module_pci_driver(phytium_i2s_mmd_mfd_driver);
+
+MODULE_AUTHOR("Yiqun Zhang <zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium Px210 MFD PCI driver for I2S-DP");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci-pci.c b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci-pci.c
new file mode 100644
index 00000000000000..b397a25700d819
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci-pci.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Phytium Multimedia Card Interface PCI driver
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include "phytium-mci.h"
+
+static u32 sd_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23 |
+		     MMC_CAP_4_BIT_DATA;
+static u32 sd_caps2 = MMC_CAP2_NO_MMC;
+
+static u32 emmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_WAIT_WHILE_BUSY |
+		       MMC_CAP_CMD23 | MMC_CAP_HW_RESET | MMC_CAP_MMC_HIGHSPEED |
+		       MMC_CAP_NONREMOVABLE;
+static u32 emmc_caps2 = MMC_CAP2_NO_SDIO | MMC_CAP2_NO_SD;
+
+#define PCI_BAR_NO 0
+
+#if defined CONFIG_PM && defined CONFIG_PM_SLEEP
+static const struct dev_pm_ops phytium_mci_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_mci_suspend,
+				phytium_mci_resume)
+	SET_RUNTIME_PM_OPS(phytium_mci_runtime_suspend,
+			   phytium_mci_runtime_resume, NULL)
+};
+#else
+#define phytium_mci_dev_pm_ops NULL
+#endif
+
+static int
+phytium_mci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
+{
+	struct phytium_mci_host *host;
+	struct mmc_host *mmc;
+	int ret;
+
+	ret = pcim_enable_device(pdev);
+
+	if (ret)
+		return ret;
+	pci_set_master(pdev);
+
+	mmc = mmc_alloc_host(sizeof(struct phytium_mci_host), &pdev->dev);
+
+	if (!mmc)
+		return -ENOMEM;
+
+	host = mmc_priv(mmc);
+
+	pci_enable_msi(pdev);
+
+	host->irq = pdev->irq;
+	host->irq_flags = IRQF_SHARED;
+	host->dev = &pdev->dev;
+	ret = pcim_iomap_regions(pdev, 1 << PCI_BAR_NO, pci_name(pdev));
+
+	if (ret) {
+		dev_err(&pdev->dev, "I/O memory remapping failed\n");
+		goto host_free;
+	}
+
+	host->base = pcim_iomap_table(pdev)[PCI_BAR_NO];
+	host->is_use_dma = 1;
+	host->is_device_x100 = 1;
+
+	if (pdev->devfn == 2) {
+		host->caps = emmc_caps;
+		host->caps2 = emmc_caps2;
+	} else {
+		host->caps = sd_caps;
+		host->caps2 = sd_caps2;
+		mmc->f_max = 25000000; /* stable frequency */
+	}
+
+	host->mmc = mmc;
+	host->clk_rate = MCI_CLK;
+
+	dev_info(&pdev->dev, "%s %d: [bar %d] addr: 0x%llx size: 0x%llx km: 0x%llx devfn:%d\n",
+		 __func__, __LINE__, PCI_BAR_NO, pci_resource_start(pdev, 0),
+		 pci_resource_len(pdev, 0), (uint64_t)host->base, pdev->devfn);
+
+	dev_dbg(&pdev->dev, "%s %d:irq:0x%x\n", __func__, __LINE__, host->irq);
+
+	ret = phytium_mci_common_probe(host);
+
+	if (ret == MCI_REALEASE_MEM) {
+		ret = -ENOMEM;
+		goto release_mem;
+	} else if (ret) {
+		goto release;
+	}
+	pci_set_drvdata(pdev, mmc);
+	dev_info(&pdev->dev, "%s %d: probe phytium mci successful.\n", __func__, __LINE__);
+	return 0;
+
+release:
+	phytium_mci_deinit_hw(host);
+release_mem:
+
+	if (host->dma.adma_table) {
+		dma_free_coherent(&pdev->dev,
+					MAX_BD_NUM * sizeof(struct phytium_adma2_64_desc),
+					host->dma.adma_table, host->dma.adma_addr);
+	}
+host_free:
+	mmc_free_host(mmc);
+	pci_disable_device(pdev);
+	return ret;
+}
+
+static void phytium_mci_pci_remove(struct pci_dev *pdev)
+{
+	struct phytium_mci_host *host;
+	struct mmc_host *mmc;
+
+	mmc = pci_get_drvdata(pdev);
+	if (!mmc) {
+		dev_info(&pdev->dev, "%s %d: mmc is null.\n", __func__, __LINE__);
+		return;
+	}
+	host = mmc_priv(mmc);
+	if (!host) {
+		dev_info(&pdev->dev, "%s %d: host is null.\n", __func__, __LINE__);
+		mmc_remove_host(mmc);
+		mmc_free_host(mmc);
+		return;
+	}
+
+	del_timer(&host->hotplug_timer);
+
+	mmc_remove_host(host->mmc);
+
+	if (host->dma.adma_table) {
+		dma_free_coherent(&pdev->dev,
+				  MAX_BD_NUM * sizeof(struct phytium_adma2_64_desc),
+				  host->dma.adma_table, host->dma.adma_addr);
+	}
+	phytium_mci_deinit_hw(host);
+	mmc_free_host(mmc);
+	pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id phytium_mci_pci_tbl[] = {
+	{
+		PCI_DEVICE(PCI_VENDOR_ID_PHYTIUM, 0xdc28),
+		.class		= 0x5,
+		.class_mask	= 0,
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(pci, phytium_mci_pci_tbl);
+
+static struct pci_driver phytium_mci_pci_driver = {
+	.name		= "phytium-mci-pci",
+	.id_table	= phytium_mci_pci_tbl,
+	.probe		= phytium_mci_pci_probe,
+	.remove		= phytium_mci_pci_remove,
+	.driver	= {
+		.pm	= &phytium_mci_dev_pm_ops,
+	}
+};
+module_pci_driver(phytium_mci_pci_driver);
+
+MODULE_DESCRIPTION("Phytium Multimedia Card Interface PCI driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci-plat.c b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci-plat.c
new file mode 100644
index 00000000000000..d4d51adbf8f985
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci-plat.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Phytium Multimedia Card Interface PCI driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/acpi.h>
+#include <linux/dma-mapping.h>
+#include "phytium-mci.h"
+
+static u32 mci_caps = MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY;
+
+#if defined CONFIG_PM && defined CONFIG_PM_SLEEP
+
+static const struct dev_pm_ops phytium_mci_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_mci_suspend,
+				phytium_mci_resume)
+	SET_RUNTIME_PM_OPS(phytium_mci_runtime_suspend,
+			   phytium_mci_runtime_resume, NULL)
+};
+#else
+#define phytium_mci_dev_pm_ops NULL
+#endif
+
+static int phytium_mci_probe(struct platform_device *pdev)
+{
+	struct mmc_host *mmc;
+	struct phytium_mci_host *host;
+	struct resource *res;
+	const struct acpi_device_id *match;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	mmc = mmc_alloc_host(sizeof(struct phytium_mci_host), &pdev->dev);
+	if (!mmc)
+		return -ENOMEM;
+	host = mmc_priv(mmc);
+	ret = mmc_of_parse(mmc);
+	if (ret)
+		goto host_free;
+
+	if (dev->of_node) {
+		host->src_clk = devm_clk_get(&pdev->dev, "phytium_mci_clk");
+		if (IS_ERR(host->src_clk)) {
+			ret = PTR_ERR(host->src_clk);
+			goto host_free;
+		}
+
+		host->clk_rate = clk_get_rate(host->src_clk);
+	} else if (has_acpi_companion(dev)) {
+		match = acpi_match_device(dev->driver->acpi_match_table, dev);
+		if (!match) {
+			dev_err(dev, "Error ACPI match data is missing\n");
+			return -ENODEV;
+		}
+		host->clk_rate = 1200000000;
+	}
+
+	host->is_use_dma = 1;
+	host->is_device_x100 = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	host->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(host->base)) {
+		ret = PTR_ERR(host->base);
+		goto host_free;
+	}
+
+	host->irq = platform_get_irq(pdev, 0);
+
+	if (host->irq < 0) {
+		ret = -EINVAL;
+		goto host_free;
+	}
+	host->irq_flags = IRQF_SHARED;
+	dev_dbg(&pdev->dev, "%s %d:irq:%d\n", __func__, __LINE__, host->irq);
+	host->dev = &pdev->dev;
+	host->caps = mci_caps;
+	host->mmc = mmc;
+	ret = phytium_mci_common_probe(host);
+	if (ret == MCI_REALEASE_MEM) {
+		ret = -ENOMEM;
+		goto release_mem;
+	} else if (ret) {
+		goto release;
+	}
+	platform_set_drvdata(pdev, mmc);
+	dev_info(&pdev->dev, "%s %d: probe phytium mci successful.\n", __func__, __LINE__);
+	return 0;
+
+release:
+	phytium_mci_deinit_hw(host);
+release_mem:
+	if (host->dma.adma_table) {
+		dma_free_coherent(&pdev->dev,
+				  MAX_BD_NUM * sizeof(struct phytium_adma2_64_desc),
+				  host->dma.adma_table, host->dma.adma_addr);
+	}
+host_free:
+	mmc_free_host(mmc);
+	return ret;
+}
+
+static int phytium_mci_remove(struct platform_device *pdev)
+{
+	struct mmc_host *mmc;
+	struct phytium_mci_host *host;
+
+	mmc = platform_get_drvdata(pdev);
+	if (!mmc) {
+		dev_info(&pdev->dev, "%s %d: mmc is null.\n", __func__, __LINE__);
+		return -1;
+	}
+	host = mmc_priv(mmc);
+	if (!host) {
+		dev_info(&pdev->dev, "%s %d: host is null.\n", __func__, __LINE__);
+		mmc_remove_host(mmc);
+		mmc_free_host(mmc);
+		return -1;
+	}
+	del_timer(&host->hotplug_timer);
+	del_timer_sync(&host->timeout_timer);
+	mmc_remove_host(host->mmc);
+
+	if (host->dma.adma_table) {
+		dma_free_coherent(&pdev->dev,
+				  MAX_BD_NUM * sizeof(struct phytium_adma2_64_desc),
+				  host->dma.adma_table, host->dma.adma_addr);
+	}
+	phytium_mci_deinit_hw(host);
+	mmc_free_host(mmc);
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+static const struct of_device_id phytium_mci_of_ids[] = {
+	{   .compatible =  "phytium,mci", },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, phytium_mci_of_ids);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_mci_acpi_ids[] = {
+        { .id = "PHYT0017" },
+        { }
+};
+
+MODULE_DEVICE_TABLE(acpi, phytium_mci_acpi_ids);
+#else
+#define phytium_mci_acpi_ids NULL
+#endif
+
+static struct platform_driver phytium_mci_driver = {
+	.probe = phytium_mci_probe,
+	.remove = phytium_mci_remove,
+	.driver = {
+		.name = "phytium-mci-platform",
+		.of_match_table = phytium_mci_of_ids,
+		.acpi_match_table = phytium_mci_acpi_ids,
+		.pm = &phytium_mci_dev_pm_ops,
+	},
+};
+
+module_platform_driver(phytium_mci_driver);
+
+MODULE_DESCRIPTION("Phytium Multimedia Card Interface driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci.c b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci.c
new file mode 100644
index 00000000000000..22ec14694c7999
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci.c
@@ -0,0 +1,1564 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Phytium Multimedia Card Interface
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/moduleparam.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/acpi.h>
+#include <linux/timer.h>
+#include <linux/swab.h>
+#include <linux/pci.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+#include <linux/delay.h>
+#include "phytium-mci.h"
+
+static const u32 cmd_ints_mask = MCI_INT_MASK_RE | MCI_INT_MASK_CMD | MCI_INT_MASK_RCRC |
+				 MCI_INT_MASK_RTO | MCI_INT_MASK_HTO | MCI_RAW_INTS_HLE;
+
+static const u32 data_ints_mask = MCI_INT_MASK_DTO | MCI_INT_MASK_DCRC | MCI_INT_MASK_DRTO |
+				  MCI_INT_MASK_SBE_BCI;
+static const u32 cmd_err_ints_mask = MCI_INT_MASK_RTO | MCI_INT_MASK_RCRC | MCI_INT_MASK_RE |
+				     MCI_INT_MASK_DCRC | MCI_INT_MASK_DRTO |
+				     MCI_MASKED_INTS_SBE_BCI;
+
+static const u32 dmac_ints_mask = MCI_DMAC_INT_ENA_FBE | MCI_DMAC_INT_ENA_DU |
+				  MCI_DMAC_INT_ENA_NIS | MCI_DMAC_INT_ENA_AIS;
+static const u32 dmac_err_ints_mask = MCI_DMAC_INT_ENA_FBE | MCI_DMAC_INT_ENA_DU |
+				      MCI_DMAC_INT_ENA_AIS;
+
+static void phytium_mci_cmd_next(struct phytium_mci_host *host,
+				  struct mmc_request *mrq,
+				  struct mmc_command *cmd);
+static void phytium_mci_adma_reset(struct phytium_mci_host *host);
+static void phytium_mci_send_cmd(struct phytium_mci_host *host, u32 cmd, u32 arg);
+static bool phytium_mci_data_xfer_done(struct phytium_mci_host *host, u32 events,
+					struct mmc_request *mrq, struct mmc_data *data);
+static void phytium_mci_init_adma_table(struct phytium_mci_host *host,
+					 struct phytium_mci_dma *dma);
+static void phytium_mci_init_hw(struct phytium_mci_host *host);
+static int phytium_mci_get_cd(struct mmc_host *mmc);
+static int phytium_mci_err_irq(struct phytium_mci_host *host, u32 dmac_events, u32 events);
+
+static void sdr_set_bits(void __iomem *reg, u32 bs)
+{
+	u32 val = readl(reg);
+
+	val |= bs;
+	writel(val, reg);
+}
+
+static void sdr_clr_bits(void __iomem *reg, u32 bs)
+{
+	u32 val = readl(reg);
+
+	val &= ~bs;
+	writel(val, reg);
+}
+
+static void phytium_mci_reset_hw(struct phytium_mci_host *host)
+{
+	sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_FIFO_RESET | MCI_CNTRL_DMA_RESET);
+
+	while (readl(host->base + MCI_CNTRL) & (MCI_CNTRL_FIFO_RESET | MCI_CNTRL_DMA_RESET))
+		cpu_relax();
+	phytium_mci_send_cmd(host, MCI_CMD_UPD_CLK, 0);
+}
+
+static void phytium_mci_update_external_clk(struct phytium_mci_host *host, u32 uhs_reg_value)
+{
+	writel(0, host->base + MCI_UHS_REG_EXT);
+	writel(uhs_reg_value, host->base + MCI_UHS_REG_EXT);
+	while (!(readl(host->base + MCI_CCLK_RDY) & 0x1))
+		cpu_relax();
+}
+
+static void phytium_mci_prepare_data(struct phytium_mci_host *host,
+				      struct mmc_request *mrq)
+{
+	struct mmc_data *data = mrq->data;
+
+	if (!(data->host_cookie & MCI_PREPARE_FLAG)) {
+		data->host_cookie |= MCI_PREPARE_FLAG;
+		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
+					    mmc_get_dma_dir(data));
+	}
+}
+
+static void phytium_mci_unprepare_data(struct phytium_mci_host *host,
+					struct mmc_request *mrq)
+{
+	struct mmc_data *data = mrq->data;
+
+	if (data->host_cookie & MCI_ASYNC_FLAG)
+		return;
+
+	if (data->host_cookie & MCI_PREPARE_FLAG) {
+		dma_unmap_sg(host->dev, data->sg, data->sg_len, mmc_get_dma_dir(data));
+		data->host_cookie &= ~MCI_PREPARE_FLAG;
+	}
+}
+
+static void phytium_mci_send_cmd(struct phytium_mci_host *host, u32 cmd, u32 arg)
+{
+	int rc;
+	u32 data;
+
+	writel(arg, host->base + MCI_CMDARG);
+	wmb(); /* drain writebuffer */
+
+	rc = readl_relaxed_poll_timeout(host->base + MCI_STATUS,
+					 data,
+					 !(data & MCI_STATUS_CARD_BUSY),
+					 0, 100 * 1000);
+	if (rc == -ETIMEDOUT)
+		pr_debug("%s %d, timeout mci_status: 0x%08x\n", __func__, __LINE__, data);
+
+	writel(MCI_CMD_START | cmd, host->base + MCI_CMD);
+
+	rc = readl_relaxed_poll_timeout(host->base + MCI_CMD,
+					 data,
+					 !(data & MCI_CMD_START),
+					 0, 100 * 1000);
+	if (rc == -ETIMEDOUT)
+		pr_debug("%s %d, timeout mci_cmd: 0x%08x\n", __func__, __LINE__, data);
+}
+
+static void phytium_mci_update_cmd11(struct phytium_mci_host *host, u32 cmd)
+{
+	writel(MCI_CMD_START | cmd, host->base + MCI_CMD);
+
+	while (readl(host->base + MCI_CMD) & MCI_CMD_START)
+		cpu_relax();
+}
+
+static void phytium_mci_set_clk(struct phytium_mci_host *host, struct mmc_ios *ios)
+{
+	u32 div = 0xff, drv = 0, sample = 0;
+	unsigned long clk_rate;
+	u32 mci_cmd_bits = MCI_CMD_UPD_CLK;
+	u32 cmd_reg;
+	u32 cur_cmd_index;
+	u32 first_uhs_div, tmp_ext_reg;
+
+	cmd_reg = readl(host->base + MCI_CMD);
+	cur_cmd_index = cmd_reg & 0x3F;
+
+	if (cur_cmd_index == SD_SWITCH_VOLTAGE)
+		mci_cmd_bits |= MCI_CMD_VOLT_SWITCH;
+	if (ios->clock) {
+		if (host->current_ios_clk == ios->clock)
+			return;
+
+		dev_dbg(host->dev, "will change clock, host->clk_rate: %ld, ios->clock: %d\n",
+			host->clk_rate, ios->clock);
+
+		if (ios->clock >= 25000000)
+			tmp_ext_reg = 0x202;
+		else if (ios->clock == 400000)
+			tmp_ext_reg = 0x502;
+		else
+			tmp_ext_reg = 0x302;
+
+		phytium_mci_update_external_clk(host, tmp_ext_reg);
+		sdr_clr_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+
+		if (cur_cmd_index == SD_SWITCH_VOLTAGE)
+			phytium_mci_update_cmd11(host, mci_cmd_bits | cmd_reg);
+		else
+			phytium_mci_send_cmd(host, mci_cmd_bits, 0);
+
+		clk_rate = host->clk_rate;
+		first_uhs_div = 1 + ((tmp_ext_reg >> 8)&0xFF);
+		div = clk_rate / (2 * first_uhs_div * ios->clock);
+		if (div > 2) {
+			sample = div / 2 + 1;
+			drv = sample - 1;
+			writel((sample << 16) | (drv << 8) | (div & 0xff),
+			       host->base + MCI_CLKDIV);
+		} else if (div == 2) {
+			drv = 0;
+			sample = 1;
+			writel((drv << 8) | (sample << 16) | (div & 0xff),
+			       host->base + MCI_CLKDIV);
+		}
+
+		dev_dbg(host->dev, "UHS_REG_EXT ext: %x, CLKDIV: %x\n",
+			readl(host->base + MCI_UHS_REG_EXT), readl(host->base + MCI_CLKDIV));
+
+		sdr_set_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+
+		if (cur_cmd_index == SD_SWITCH_VOLTAGE)
+			phytium_mci_update_cmd11(host, mci_cmd_bits | cmd_reg);
+		else
+			phytium_mci_send_cmd(host, mci_cmd_bits, 0);
+
+		host->current_ios_clk = ios->clock;
+
+		dev_dbg(host->dev, "host->clk_rate: %ld, ios->clock: %d\n",
+			host->clk_rate, ios->clock);
+	} else {
+		host->current_ios_clk = 0;
+		sdr_clr_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+
+		if (cur_cmd_index == SD_SWITCH_VOLTAGE)
+			phytium_mci_update_cmd11(host, mci_cmd_bits | cmd_reg);
+		else
+			phytium_mci_send_cmd(host, mci_cmd_bits, 0);
+
+		sdr_clr_bits(host->base + MCI_UHS_REG_EXT, MCI_EXT_CLK_ENABLE);
+		dev_dbg(host->dev, "host->clk_rate: %ld, ios->clock: %d\n",
+			host->clk_rate, ios->clock);
+	}
+}
+
+static inline u32
+phytium_mci_cmd_find_resp(struct phytium_mci_host *host,
+			  struct mmc_request *mrq,
+			  struct mmc_command *cmd)
+{
+	u32 resp;
+
+	switch (mmc_resp_type(cmd)) {
+	case MMC_RSP_R1:
+	case MMC_RSP_R1B:
+		resp = 0x5;
+		break;
+
+	case MMC_RSP_R2:
+		resp = 0x7;
+		break;
+
+	case MMC_RSP_R3:
+		resp = 0x1;
+		break;
+
+	case MMC_RSP_NONE:
+	default:
+		resp = 0x0;
+		break;
+	}
+
+	return resp;
+}
+
+static inline
+u32 phytium_mci_cmd_prepare_raw_cmd(struct phytium_mci_host *host,
+				     struct mmc_request *mrq,
+				     struct mmc_command *cmd)
+{
+	u32 opcode = cmd->opcode;
+	u32 resp = phytium_mci_cmd_find_resp(host, mrq, cmd);
+	u32 rawcmd = ((opcode & 0x3f) | ((resp & 0x7) << 6));
+
+	if (opcode == MMC_GO_INACTIVE_STATE ||
+	    (opcode == SD_IO_RW_DIRECT && ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
+		rawcmd |= (0x1 << 14);
+	else if (opcode == SD_SWITCH_VOLTAGE)
+		rawcmd |= (0x1 << 28);
+
+	if (test_and_clear_bit(MCI_CARD_NEED_INIT, &host->flags))
+		rawcmd |= (0x1 << 15);
+
+	if (cmd->data) {
+		struct mmc_data *data = cmd->data;
+
+		rawcmd |= (0x1 << 9);
+
+		if (data->flags & MMC_DATA_WRITE)
+			rawcmd |= (0x1 << 10);
+	}
+
+	return (rawcmd | (0x1 << 29) | (0x1 << 31));
+}
+
+static inline void
+phytium_mci_adma_write_desc(struct phytium_mci_host *host,
+			     struct phytium_adma2_64_desc *desc,
+			     dma_addr_t addr, u32 len, u32 attribute)
+{
+	desc->attribute = attribute;
+	desc->len = len;
+	desc->addr_lo = lower_32_bits(addr);
+	desc->addr_hi = upper_32_bits(addr);
+	dev_dbg(host->dev, "%s %d:addr_lo:0x%x ddr_hi:0x%x\n", __func__,
+		__LINE__,  desc->addr_lo, desc->addr_hi);
+
+	if ((attribute == 0x80000004) || (attribute == 0x8000000c)) {
+		desc->desc_lo = 0;
+		desc->desc_hi = 0;
+	}
+}
+
+static void
+phytium_mci_data_sg_write_2_admc_table(struct phytium_mci_host *host, struct mmc_data *data)
+{
+	struct phytium_adma2_64_desc *desc;
+	u32 dma_len, i;
+	dma_addr_t dma_address;
+	struct scatterlist *sg;
+
+	phytium_mci_init_adma_table(host, &host->dma);
+
+	desc = host->dma.adma_table;
+	for_each_sg(data->sg, sg, data->sg_count, i) {
+		dma_address = sg_dma_address(sg);
+		dma_len = sg_dma_len(sg);
+
+		if (i == 0) {
+			if (sg_is_last(sg) || (data->sg_count == 1 && dma_len == SD_BLOCK_SIZE))
+				phytium_mci_adma_write_desc(host, desc, dma_address,
+							     dma_len, 0x8000000c);
+			else
+				phytium_mci_adma_write_desc(host, desc, dma_address,
+							     dma_len, 0x8000001a);
+		} else if (sg_is_last(sg)) {
+			phytium_mci_adma_write_desc(host, desc, dma_address,
+						     dma_len, 0x80000004);
+		} else {
+			phytium_mci_adma_write_desc(host, desc, dma_address,
+						     dma_len, 0x80000012);
+		}
+
+		desc++;
+	}
+}
+
+static void
+phytium_mci_data_sg_write_2_fifo(struct phytium_mci_host *host, struct mmc_data *data)
+{
+	struct scatterlist *sg;
+	u32 dma_len, i, j;
+	u32 *virt_addr;
+
+	if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
+		writel(0x1<<10, host->base + MCI_CMD);
+		for_each_sg(data->sg, sg, data->sg_count, i) {
+			dma_len = sg_dma_len(sg);
+			virt_addr = sg_virt(data->sg);
+			for (j = 0; j < (dma_len / 4); j++) {
+				writel(*virt_addr, host->base + MCI_DATA);
+				virt_addr++;
+			}
+		}
+	}
+}
+
+static void phytium_mci_restart_clk(struct phytium_mci_host *host)
+{
+	u32 clk_div, uhs;
+
+	while (readl(host->base + MCI_CMD) & MCI_CMD_START)
+		cpu_relax();
+	sdr_clr_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+	clk_div = readl(host->base + MCI_CLKDIV);
+	uhs = readl(host->base + MCI_UHS_REG_EXT);
+	writel(0, host->base + MCI_UHS_REG_EXT);
+	writel(uhs, host->base + MCI_UHS_REG_EXT);
+	while (!(readl(host->base + MCI_CCLK_RDY) & 0x1))
+		cpu_relax();
+
+	writel(clk_div, host->base + MCI_CLKDIV);
+	sdr_set_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+	writel(MCI_CMD_START | MCI_CMD_UPD_CLK, host->base + MCI_CMD);
+	while (readl(host->base + MCI_CMD) & MCI_CMD_START)
+		cpu_relax();
+}
+
+static int
+phytim_mci_start_multiple_write(struct phytium_mci_host *host,
+				struct mmc_request *mrq, u32 cnts, u32 offset)
+{
+	u32 rawcmd, cmd_status;
+	struct mmc_command *cmd = mrq->cmd;
+	u32 *rsp = cmd->resp;
+	unsigned long deadline_time;
+
+	if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && readl(host->base + MCI_CARD_DETECT))
+		return -ESHUTDOWN;
+
+	while ((readl(host->base + MCI_STATUS) & (MCI_STATUS_CARD_BUSY)))
+		cpu_relax();
+
+	writel(0xffffe, host->base + MCI_RAW_INTS);
+	rawcmd = phytium_mci_cmd_prepare_raw_cmd(host, mrq, cmd);
+	writel(mrq->data->blksz, host->base + MCI_BLKSIZ);
+	writel(cnts * mrq->data->blksz, host->base + MCI_BYTCNT);
+	writel(cmd->arg + offset, host->base + MCI_CMDARG);
+	writel(rawcmd, host->base + MCI_CMD);
+	deadline_time = jiffies + msecs_to_jiffies(200);
+
+	cmd_status = readl(host->base + MCI_RAW_INTS);
+	while (!(cmd_status & MCI_MASKED_INTS_CMD)) {
+		if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
+		    readl(host->base + MCI_CARD_DETECT))
+			return -ESHUTDOWN;
+
+		cmd_status = readl(host->base + MCI_RAW_INTS);
+		if (cmd_err_ints_mask & cmd_status)
+			return -ESHUTDOWN;
+
+		if (cmd_status & MCI_MASKED_INTS_CMD)
+			break;
+
+		if (time_after(jiffies, deadline_time))
+			return -ESHUTDOWN;
+	}
+
+	if (cmd_status & MCI_MASKED_INTS_CMD) {
+		if (cmd->flags & MMC_RSP_136) {
+			rsp[3] = readl(host->base + MCI_RESP0);
+			rsp[2] = readl(host->base + MCI_RESP1);
+			rsp[1] = readl(host->base + MCI_RESP2);
+			rsp[0] = readl(host->base + MCI_RESP3);
+		} else {
+			rsp[0] = readl(host->base + MCI_RESP0);
+		}
+	}
+	deadline_time = jiffies + msecs_to_jiffies(1000);
+	while (!(cmd_status & MCI_MASKED_INTS_DTO)) {
+		if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
+		    readl(host->base + MCI_CARD_DETECT))
+			return -ESHUTDOWN;
+		cmd_status = readl(host->base + MCI_RAW_INTS);
+		if (cmd_err_ints_mask & cmd_status)
+			return -ESHUTDOWN;
+		if (cmd_status & MCI_MASKED_INTS_DTO)
+			return 0;
+		if (time_after(jiffies, deadline_time))
+			return -ESHUTDOWN;
+	}
+	return 0;
+}
+
+static int
+phytium_mci_start_sbc_stop_cmd(struct phytium_mci_host *host, struct mmc_request *mrq,
+			       struct mmc_command *cmd, u32 arg)
+{
+	u32 rawcmd, cmd_status;
+	u32 *rsp = cmd->resp;
+	unsigned long deadline_time;
+
+	writel(0xffffe, host->base + MCI_RAW_INTS);
+
+	while ((readl(host->base + MCI_STATUS) & (MCI_STATUS_CARD_BUSY)))
+		cpu_relax();
+
+	rawcmd = phytium_mci_cmd_prepare_raw_cmd(host, mrq, cmd);
+	writel(arg, host->base + MCI_CMDARG);
+	writel(rawcmd, host->base + MCI_CMD);
+
+	deadline_time = jiffies + msecs_to_jiffies(200);
+	cmd_status = readl(host->base + MCI_RAW_INTS);
+	while (!(cmd_status & MCI_MASKED_INTS_CMD)) {
+		if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
+		    readl(host->base + MCI_CARD_DETECT))
+			return -ENOMEDIUM;
+
+		cmd_status = readl(host->base + MCI_RAW_INTS);
+		if (cmd_err_ints_mask & cmd_status)
+			return -ETIMEDOUT;
+
+		if (cmd_status & MCI_MASKED_INTS_CMD)
+			break;
+
+		if (time_after(jiffies, deadline_time))
+			return -ETIMEDOUT;
+	}
+
+	if (cmd_status & MCI_MASKED_INTS_CMD) {
+		if (cmd->flags & MMC_RSP_136) {
+			rsp[3] = readl(host->base + MCI_RESP0);
+			rsp[2] = readl(host->base + MCI_RESP1);
+			rsp[1] = readl(host->base + MCI_RESP2);
+			rsp[0] = readl(host->base + MCI_RESP3);
+		} else {
+			rsp[0] = readl(host->base + MCI_RESP0);
+		}
+	}
+
+	if (cmd_err_ints_mask & cmd_status)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static void
+phytium_mci_start_write_multiple_non_dma(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	struct mmc_data *data = mrq->data;
+	u32 write_cnts, last_cnts;
+	u32 i, j, k, send_cnt_one_sg, block_offset;
+	int ret = 0, dma_len;
+	struct scatterlist *sg;
+	u32 *virt_addr = NULL;
+
+	write_cnts = data->blocks / 4;
+	(data->blocks % 4) ? write_cnts++ : write_cnts;
+	last_cnts = data->blocks % 4;
+	if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && readl(host->base + MCI_CARD_DETECT)) {
+		ret = -ENOMEDIUM;
+		goto write_err;
+	}
+
+	dev_dbg(host->dev, "%s: cmd:%d, block counts:%d\n",
+		__func__, mrq->cmd->opcode, data->blocks);
+
+	sdr_clr_bits(host->base + MCI_CNTRL, MCI_CNTRL_USE_INTERNAL_DMAC);
+	sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_FIFO_RESET);
+	while (readl(host->base + MCI_CNTRL) & MCI_CNTRL_FIFO_RESET)
+		cpu_relax();
+	sdr_clr_bits(host->base + MCI_BUS_MODE, MCI_BUS_MODE_DE);
+
+	if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
+		block_offset = 0;
+		for_each_sg(data->sg, sg, data->sg_count, i) {
+			/* Each SG data transfor starts */
+			dma_len = sg_dma_len(sg);
+			send_cnt_one_sg = (dma_len / MCI_MAX_FIFO_CNT) + 1;
+			virt_addr = sg_virt(sg);
+			for (k = 0; k < send_cnt_one_sg; k++) {
+				if (dma_len && dma_len >= MCI_MAX_FIFO_CNT) {
+					/*first write sbc cmd*/
+					ret = phytium_mci_start_sbc_stop_cmd(host, mrq,
+									     mrq->sbc, 4);
+					if (ret)
+						goto write_err;
+					writel(0x1 << 10, host->base + MCI_CMD);
+					for (j = 0; j < (MCI_MAX_FIFO_CNT / 4); j++) {
+						writel(*virt_addr, host->base + MCI_DATA);
+						virt_addr++;
+					}
+
+					/*second write cmd25 here*/
+					ret = phytim_mci_start_multiple_write(host, mrq, 4,
+									      block_offset);
+					if (ret)
+						goto write_err;
+					block_offset += 4;
+					dma_len -= MCI_MAX_FIFO_CNT;
+				} else if (dma_len > 0) {
+					/*first write sbc cmd*/
+					last_cnts = dma_len / 512;
+					ret = phytium_mci_start_sbc_stop_cmd(host, mrq, mrq->sbc,
+									     last_cnts);
+					if (ret)
+						goto write_err;
+					writel(0x1 << 10, host->base + MCI_CMD);
+					for (j = 0; j < (dma_len / 4); j++) {
+						writel(*virt_addr, host->base + MCI_DATA);
+						virt_addr++;
+					}
+					/*second write cmd25 here*/
+					ret = phytim_mci_start_multiple_write(host, mrq, last_cnts,
+									      block_offset);
+					if (ret)
+						goto write_err;
+					block_offset += last_cnts;
+					dma_len = 0;
+				} else {
+					dev_dbg(host->dev, "%s: sg %d end\n", __func__, i);
+					break;
+				}
+			}
+		}
+	}
+
+write_err:
+	host->data = NULL;
+	host->cmd = NULL;
+	host->mrq = NULL;
+	writel(0xffffe, host->base + MCI_RAW_INTS);
+	if (ret) {
+		data->bytes_xfered = 0;
+		if (ret == -ESHUTDOWN) {
+			sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_FIFO_RESET);
+			while (readl(host->base + MCI_CNTRL) & MCI_CNTRL_FIFO_RESET)
+				cpu_relax();
+
+			sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_CONTROLLER_RESET);
+			while (readl(host->base + MCI_STATUS) & MCI_STATUS_CARD_BUSY)
+				sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_CONTROLLER_RESET);
+			phytium_mci_restart_clk(host);
+			phytium_mci_start_sbc_stop_cmd(host, mrq, mrq->stop, mrq->stop->arg);
+		}
+		data->error = -ETIMEDOUT;
+		mrq->cmd->error = -ETIMEDOUT;
+		mmc_request_done(host->mmc, mrq);
+		return;
+	}
+	data->bytes_xfered = data->blocks * data->blksz;
+	mmc_request_done(host->mmc, mrq);
+}
+
+static void
+phytium_mci_start_data(struct phytium_mci_host *host, struct mmc_request *mrq,
+			struct mmc_command *cmd, struct mmc_data *data)
+{
+	bool read;
+	u32 rawcmd;
+	unsigned long flags;
+
+
+	WARN_ON(host->cmd);
+	host->cmd = cmd;
+	cmd->error = 0;
+	WARN_ON(host->data);
+	host->data = data;
+	read = data->flags & MMC_DATA_READ;
+
+	if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && readl(host->base + MCI_CARD_DETECT)) {
+		phytium_mci_err_irq(host, 0, MCI_INT_MASK_RTO);
+		return;
+	}
+	/* clear interrupts */
+	writel(0xffffe, host->base + MCI_RAW_INTS);
+
+	sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_FIFO_RESET | MCI_CNTRL_DMA_RESET);
+
+	while (readl(host->base + MCI_CNTRL) & (MCI_CNTRL_FIFO_RESET | MCI_CNTRL_DMA_RESET))
+		cpu_relax();
+
+	if (host->adtc_type == COMMOM_ADTC)
+		sdr_clr_bits(host->base + MCI_CNTRL, MCI_CNTRL_USE_INTERNAL_DMAC);
+	else
+		sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_USE_INTERNAL_DMAC);
+	wmb(); /* drain writebuffer */
+	sdr_clr_bits(host->base + MCI_CNTRL, MCI_CNTRL_INT_ENABLE);
+
+	rawcmd = phytium_mci_cmd_prepare_raw_cmd(host, mrq, cmd);
+	if (host->is_use_dma && host->adtc_type == BLOCK_RW_ADTC)
+		phytium_mci_data_sg_write_2_admc_table(host, data);
+	else
+		phytium_mci_data_sg_write_2_fifo(host, data);
+
+	spin_lock_irqsave(&host->lock, flags);
+	sdr_set_bits(host->base + MCI_INT_MASK, cmd_ints_mask | data_ints_mask);
+	if (host->is_use_dma && host->adtc_type == BLOCK_RW_ADTC) {
+		sdr_set_bits(host->base + MCI_DMAC_INT_ENA, dmac_ints_mask);
+		/* Enable the IDMAC */
+		sdr_set_bits(host->base + MCI_BUS_MODE, MCI_BUS_MODE_DE);
+		writel((u32)host->dma.adma_addr, host->base + MCI_DESC_LIST_ADDRL);
+		writel((u32)(host->dma.adma_addr >> 32), host->base + MCI_DESC_LIST_ADDRH);
+	}
+	writel(mrq->data->blksz, host->base + MCI_BLKSIZ);
+	writel(mrq->data->blocks * mrq->data->blksz, host->base + MCI_BYTCNT);
+	sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_INT_ENABLE);
+	writel(cmd->arg, host->base + MCI_CMDARG);
+	wmb(); /* drain writebuffer */
+	writel(rawcmd, host->base + MCI_CMD);
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	mod_timer(&host->timeout_timer,
+		jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS));
+}
+
+static void phytium_mci_track_cmd_data(struct phytium_mci_host *host,
+					struct mmc_command *cmd,
+					struct mmc_data *data)
+{
+	if (host->error)
+		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
+			__func__, cmd->opcode, cmd->arg, host->error);
+}
+
+static void phytium_mci_request_done(struct phytium_mci_host *host, struct mmc_request *mrq)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+	del_timer(&host->timeout_timer);
+	host->mrq = NULL;
+	if (host->cmd)
+		host->cmd = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+	phytium_mci_track_cmd_data(host, mrq->cmd, mrq->data);
+
+	if (mrq->data)
+		phytium_mci_unprepare_data(host, mrq);
+
+	mmc_request_done(host->mmc, mrq);
+}
+
+static bool phytium_mci_cmd_done(struct phytium_mci_host *host, int events,
+				 struct mmc_request *mrq, struct mmc_command *cmd)
+{
+	bool done = false;
+	unsigned long flags;
+	u32 *rsp = cmd->resp;
+
+	if (!(events & (MCI_RAW_INTS_RCRC | MCI_RAW_INTS_RE | MCI_RAW_INTS_CMD |
+	      MCI_RAW_INTS_RTO | MCI_INT_MASK_HTO))) {
+		dev_err(host->dev, "No interrupt generation:h%x\n", events);
+		return done;
+	}
+
+	spin_lock_irqsave(&host->lock, flags);
+	done = !host->cmd;
+	host->cmd = NULL;
+	if (done) {
+		spin_unlock_irqrestore(&host->lock, flags);
+		return true;
+	}
+	sdr_clr_bits(host->base + MCI_INT_MASK, cmd_ints_mask);
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (cmd->flags & MMC_RSP_PRESENT) {
+		if (cmd->flags & MMC_RSP_136) {
+			rsp[3] = readl(host->base + MCI_RESP0);
+			rsp[2] = readl(host->base + MCI_RESP1);
+			rsp[1] = readl(host->base + MCI_RESP2);
+			rsp[0] = readl(host->base + MCI_RESP3);
+		} else {
+			/*
+			 * Sometimes get ACMD41 cmd done irq but the respose index still the APP_CMD,
+			 * so polling the mci status entill the respose index change.
+			 */
+			if (cmd->opcode == SD_APP_OP_COND) {
+				int polling_cnt = 20;
+				while (MMC_APP_CMD == MCI_STATUS_RESPOSE_INDEX(readl(host->base + MCI_STATUS))) {
+					udelay(100);
+					polling_cnt --;
+					if (polling_cnt == 0) {
+						dev_info(host->dev, "hw respose index not equal cmd opcode, respose value may error\n");
+						break;
+					}
+				}
+			}
+			rsp[0] = readl(host->base + MCI_RESP0);
+		}
+
+		if (cmd->opcode == SD_SEND_RELATIVE_ADDR)
+			host->current_rca = rsp[0] & 0xFFFF0000;
+	}
+	if (!(events & (MCI_RAW_INTS_CMD | MCI_INT_MASK_HTO))) {
+		if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && (events & MCI_RAW_INTS_RTO)
+		   && readl(host->base + MCI_CARD_DETECT)) {
+			cmd->error = -ENOMEDIUM;
+			rsp[0] = 0;
+		} else if (events & MCI_RAW_INTS_RTO ||
+		    (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
+		     cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) {
+			cmd->error = -ETIMEDOUT;
+		} else if (events & MCI_RAW_INTS_RCRC) {
+			cmd->error = -EILSEQ;
+		} else {
+			cmd->error = -ETIMEDOUT;
+		}
+	}
+	phytium_mci_cmd_next(host, mrq, cmd);
+	return true;
+}
+
+static void phytium_mci_start_command(struct phytium_mci_host *host,
+				       struct mmc_request *mrq,
+				       struct mmc_command *cmd)
+{
+	u32 rawcmd;
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+	WARN_ON(host->cmd);
+	host->cmd = cmd;
+	cmd->error = 0;
+	writel(0xffffe, host->base + MCI_RAW_INTS);
+
+	rawcmd = phytium_mci_cmd_prepare_raw_cmd(host, mrq, cmd);
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE) && readl(host->base + MCI_CARD_DETECT)) {
+		phytium_mci_cmd_done(host, MCI_RAW_INTS_RTO, mrq, cmd);
+		return;
+	}
+
+	spin_lock_irqsave(&host->lock, flags);
+	sdr_set_bits(host->base + MCI_INT_MASK, cmd_ints_mask);
+	writel(cmd->arg, host->base + MCI_CMDARG);
+	writel(rawcmd, host->base + MCI_CMD);
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	mod_timer(&host->timeout_timer,
+		jiffies + msecs_to_jiffies(MMC_REQ_TIMEOUT_MS));
+}
+
+static void
+phytium_mci_cmd_next(struct phytium_mci_host *host, struct mmc_request *mrq,
+		      struct mmc_command *cmd)
+{
+	if ((cmd->error && !(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
+		cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) ||
+		(mrq->sbc && mrq->sbc->error)) {
+		phytium_mci_request_done(host, mrq);
+	} else if (cmd == mrq->sbc) {
+		if ((mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) ||
+		    (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) ||
+		    (mrq->cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
+		    (mrq->cmd->opcode == MMC_WRITE_BLOCK)) {
+			dev_dbg(host->dev, "%s %d:sbc done and next cmd :%d length:%d\n",
+				__func__, __LINE__, mrq->cmd->opcode, mrq->data->sg->length);
+			phytium_mci_prepare_data(host, mrq);
+			if (host->is_use_dma)
+				host->adtc_type = BLOCK_RW_ADTC;
+			else
+				host->adtc_type = COMMOM_ADTC;
+			phytium_mci_start_data(host, mrq, mrq->cmd, mrq->data);
+		} else {
+			dev_err(host->dev, "%s %d:ERROR: cmd %d followers the SBC\n",
+				__func__, __LINE__, cmd->opcode);
+		}
+	} else if (!cmd->data) {
+		phytium_mci_request_done(host, mrq);
+	}
+}
+
+static void phytium_mci_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	u32 data;
+	int rc;
+
+	host->error = 0;
+	WARN_ON(host->mrq);
+	host->mrq = mrq;
+
+	rc = readl_relaxed_poll_timeout(host->base + MCI_STATUS,
+					 data,
+					 !(data & MCI_STATUS_CARD_BUSY),
+					 0, 500 * 1000);
+	if (rc == -ETIMEDOUT)
+		pr_debug("%s %d, timeout mci_status: 0x%08x\n", __func__, __LINE__, data);
+
+	dev_dbg(host->dev, "%s %d: cmd:%d arg:0x%x\n", __func__, __LINE__,
+		mrq->cmd->opcode, mrq->cmd->arg);
+
+	if (host->is_device_x100 && mrq->sbc && mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) {
+		phytium_mci_start_write_multiple_non_dma(mmc, mrq);
+		return;
+	}
+
+	if (mrq->sbc) {
+		phytium_mci_start_command(host, mrq, mrq->sbc);
+		return;
+	}
+	if (mrq->data) {
+		phytium_mci_prepare_data(host, mrq);
+
+		if ((mrq->data->sg->length >= 512) && host->is_use_dma &&
+			((mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) ||
+			(mrq->cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
+			(mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) ||
+			(mrq->cmd->opcode == MMC_WRITE_BLOCK) ||
+			(mrq->cmd->opcode == SD_IO_RW_EXTENDED)))
+
+			host->adtc_type = BLOCK_RW_ADTC;
+		else
+			host->adtc_type = COMMOM_ADTC;
+
+		phytium_mci_start_data(host, mrq, mrq->cmd, mrq->data);
+		return;
+	}
+	phytium_mci_start_command(host, mrq, mrq->cmd);
+}
+
+static void phytium_mci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	struct mmc_data *data = mrq->data;
+
+	if (!data)
+		return;
+
+	phytium_mci_prepare_data(host, mrq);
+	data->host_cookie |= MCI_ASYNC_FLAG;
+}
+
+static void phytium_mci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
+				  int err)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	struct mmc_data *data = mrq->data;
+
+	if (!data)
+		return;
+
+	if (data->host_cookie & MCI_ASYNC_FLAG) {
+		data->host_cookie &= ~MCI_ASYNC_FLAG;
+		phytium_mci_unprepare_data(host, mrq);
+	}
+}
+
+static void phytium_mci_data_read_without_dma(struct phytium_mci_host *host,
+					      struct mmc_data *data)
+{
+	u32 length, i, data_val, dma_len, tmp = 0;
+	u32 *virt_addr;
+	unsigned long flags;
+	struct scatterlist *sg;
+
+	length = data->blocks * data->blksz;
+
+	if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
+		spin_lock_irqsave(&host->lock, flags);
+		if (data->host_cookie & MCI_ASYNC_FLAG) {
+			tmp = MCI_ASYNC_FLAG;
+			phytium_mci_post_req(host->mmc, data->mrq, 0);
+		} else {
+			phytium_mci_unprepare_data(host, data->mrq);
+		}
+
+		for_each_sg(data->sg, sg, data->sg_count, i) {
+			dma_len = sg_dma_len(sg);
+			virt_addr = sg_virt(data->sg);
+
+			for (i = 0; i < (dma_len / 4); i++) {
+				data_val = readl(host->base + MCI_DATA);
+				memcpy(virt_addr, &data_val, 4);
+				++virt_addr;
+			}
+		}
+
+		if (tmp & MCI_ASYNC_FLAG)
+			phytium_mci_pre_req(host->mmc, data->mrq);
+		else
+			phytium_mci_prepare_data(host, data->mrq);
+
+		spin_unlock_irqrestore(&host->lock, flags);
+	}
+	data->bytes_xfered = length;
+}
+
+static void phytium_mci_data_xfer_next(struct phytium_mci_host *host,
+					struct mmc_request *mrq,
+					struct mmc_data *data)
+{
+	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop &&
+	    (data->error || !mrq->sbc)) {
+		while ((readl(host->base + MCI_STATUS) & (MCI_STATUS_CARD_BUSY)))
+			cpu_relax();
+		phytium_mci_start_command(host, mrq, mrq->stop);
+	} else {
+		phytium_mci_request_done(host, mrq);
+	}
+}
+
+static bool phytium_mci_data_xfer_done(struct phytium_mci_host *host, u32 events,
+					struct mmc_request *mrq, struct mmc_data *data)
+{
+	unsigned long flags;
+	bool done;
+
+	unsigned int check_data = events & (MCI_RAW_INTS_DTO | MCI_RAW_INTS_RCRC |
+					    MCI_RAW_INTS_DCRC | MCI_RAW_INTS_RE |
+					    MCI_RAW_INTS_DRTO | MCI_RAW_INTS_EBE |
+					    MCI_DMAC_STATUS_AIS | MCI_DMAC_STATUS_DU |
+					    MCI_RAW_INTS_SBE_BCI | MCI_INT_MASK_RTO);
+
+	spin_lock_irqsave(&host->lock, flags);
+	done = !host->data;
+
+	if (check_data || host->data)
+		host->data = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (done)
+		return true;
+	if (check_data) {
+		spin_lock_irqsave(&host->lock, flags);
+		sdr_clr_bits(host->base + MCI_DMAC_INT_ENA, dmac_ints_mask);
+		sdr_clr_bits(host->base + MCI_INT_MASK, data_ints_mask);
+		/* Stop the IDMAC running */
+		sdr_clr_bits(host->base + MCI_BUS_MODE, MCI_BUS_MODE_DE);
+		dev_dbg(host->dev, "DMA stop\n");
+		spin_unlock_irqrestore(&host->lock, flags);
+
+		if (events & MCI_RAW_INTS_DTO) {
+			if (!host->is_use_dma ||
+			    (host->is_use_dma && host->adtc_type == COMMOM_ADTC &&
+			     (mrq->cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC))
+				phytium_mci_data_read_without_dma(host, data);
+			else
+				data->bytes_xfered = data->blocks * data->blksz;
+		} else {
+			data->bytes_xfered = 0;
+			if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE)
+			    && readl(host->base + MCI_CARD_DETECT)
+			    && (events & cmd_err_ints_mask)) {
+				data->error = -ENOMEDIUM;
+				data->mrq->cmd->error =  -ENOMEDIUM;
+			} else if (events & (MCI_RAW_INTS_DCRC | MCI_RAW_INTS_EBE |
+					   MCI_RAW_INTS_SBE_BCI)) {
+				data->error = -EILSEQ;
+				host->cmd = NULL;
+			} else {
+				data->error = -ETIMEDOUT;
+				host->cmd = NULL;
+			}
+		}
+
+		phytium_mci_data_xfer_next(host, mrq, data);
+		done = true;
+	}
+	return done;
+}
+
+static int phytium_mci_card_busy(struct mmc_host *mmc)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	u32 status;
+
+	status = readl(host->base + MCI_STATUS);
+
+	return !!(status & MCI_STATUS_CARD_BUSY);
+}
+
+static void __phytium_mci_enable_sdio_irq(struct phytium_mci_host *host, int enable)
+{
+	if (enable)
+		sdr_set_bits(host->base + MCI_INT_MASK, MCI_INT_MASK_SDIO);
+	else
+		sdr_clr_bits(host->base + MCI_INT_MASK, MCI_INT_MASK_SDIO);
+}
+
+static void phytium_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+	struct phytium_mci_host *host  = mmc_priv(mmc);
+
+	__phytium_mci_enable_sdio_irq(host, enable);
+}
+
+static void hotplug_timer_func(struct timer_list *t)
+{
+	struct phytium_mci_host *host;
+	u32 status;
+
+	host = from_timer(host, t, hotplug_timer);
+	if (!host)
+		return;
+
+	status = readl(host->base + MCI_CARD_DETECT);
+
+	if (status & 0x1) {
+		if (host->mmc->card) {
+			cancel_delayed_work(&host->mmc->detect);
+			mmc_detect_change(host->mmc, msecs_to_jiffies(100));
+		}
+	} else {
+		cancel_delayed_work(&host->mmc->detect);
+		mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+	}
+}
+
+static void phytium_mci_request_timeout(struct timer_list *t)
+{
+	struct phytium_mci_host *host = from_timer(host, t, timeout_timer);
+
+	dev_err(host->dev, "request timeout\n");
+	if (host->mrq) {
+		dev_err(host->dev, "aborting mrq=%p cmd=%d\n",
+				host->mrq, host->mrq->cmd->opcode);
+		if (host->cmd) {
+			dev_err(host->dev, "aborting cmd=%d\n", host->cmd->opcode);
+			phytium_mci_cmd_done(host, MCI_RAW_INTS_RTO, host->mrq, host->cmd);
+		} else if (host->data) {
+			dev_err(host->dev, "abort data: cmd%d; %d blocks\n",
+					host->mrq->cmd->opcode, host->data->blocks);
+			phytium_mci_data_xfer_done(host, MCI_RAW_INTS_RTO, host->mrq,
+					host->data);
+		}
+	}
+}
+
+static int phytium_mci_err_irq(struct phytium_mci_host *host, u32 dmac_events, u32 events)
+{
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+
+	mrq = host->mrq;
+	cmd = host->cmd;
+	data = host->data;
+
+	if (cmd && (cmd == mrq->sbc)) {
+		phytium_mci_cmd_done(host, MCI_RAW_INTS_RTO, mrq, mrq->sbc);
+	} else if (cmd && (cmd == mrq->stop)) {
+		phytium_mci_cmd_done(host, MCI_RAW_INTS_RTO, mrq, mrq->stop);
+	} else if (data) {
+		data->error = -ETIMEDOUT;
+		if ((data->flags & MMC_DATA_READ) == MMC_DATA_READ ||
+		    (data->flags & MMC_DATA_WRITE) == MMC_DATA_WRITE)
+			phytium_mci_data_xfer_done(host, events | dmac_events, mrq, data);
+	} else if (cmd) {
+		phytium_mci_cmd_done(host, MCI_RAW_INTS_RTO, mrq, mrq->cmd);
+	}
+
+	return 0;
+}
+
+static irqreturn_t phytium_mci_irq(int irq, void *dev_id)
+{
+	struct phytium_mci_host *host = (struct phytium_mci_host *) dev_id;
+	unsigned long flags;
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+	u32 events, event_mask, dmac_events, dmac_evt_mask;
+
+	if (!host)
+		return IRQ_NONE;
+	writel(0, host->base + 0xfd0);
+
+	spin_lock_irqsave(&host->lock, flags);
+	events = readl(host->base + MCI_RAW_INTS);
+	dmac_events = readl(host->base + MCI_DMAC_STATUS);
+	event_mask = readl(host->base + MCI_INT_MASK);
+	dmac_evt_mask = readl(host->base + MCI_DMAC_INT_ENA);
+	if ((!events) && (!(dmac_events&0x1fff))) {
+		spin_unlock_irqrestore(&host->lock, flags);
+		return IRQ_NONE;
+	}
+	dev_dbg(host->dev, "%s:events:%x,mask:0x%x,dmac_events:%x,dmac_mask:0x%x,cmd:%d\n",
+		__func__, events, event_mask, dmac_events, dmac_evt_mask,
+		host->mrq ? host->mrq->cmd->opcode : 255);
+
+	mrq = host->mrq;
+	cmd = host->cmd;
+	data = host->data;
+
+#if 0
+	if (((events & event_mask) & MCI_RAW_INTS_SDIO) &&
+	    ((events == 0x10001) || (events == 0x10000) || (events == 0x10040))) {
+		writel(events, host->base + MCI_RAW_INTS);
+		__phytium_mci_enable_sdio_irq(host, 0);
+		sdio_signal_irq(host->mmc);
+		spin_unlock_irqrestore(&host->lock, flags);
+		goto irq_out;
+	}
+#endif
+	if ((events & event_mask) & MCI_RAW_INTS_SDIO) {
+		__phytium_mci_enable_sdio_irq(host, 0);
+	}
+
+
+	writel(events, host->base + MCI_RAW_INTS);
+	writel(dmac_events, host->base + MCI_DMAC_STATUS);
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if ((events & event_mask) & MCI_RAW_INTS_SDIO) {
+		sdio_signal_irq(host->mmc);
+	}
+
+	if (((events & event_mask) == 0) && ((dmac_evt_mask & dmac_events) == 0))
+		goto irq_out;
+
+	if (((events & event_mask) & MCI_RAW_INTS_CD) &&
+	    !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) {
+		mod_timer(&host->hotplug_timer, jiffies + usecs_to_jiffies(20000));
+		dev_dbg(host->dev, "sd status changed here ! status:[%d] [%s %d]",
+			readl(host->base + MCI_CARD_DETECT), __func__, __LINE__);
+
+		if ((events & event_mask) == MCI_RAW_INTS_CD)
+			goto irq_out;
+	}
+
+	if (!mrq) {
+		if (events & MCI_RAW_INTS_HLE)
+			dev_dbg(host->dev,
+				"%s: MRQ=NULL and HW write locked, events=%08x,event_mask=%08x\n",
+				__func__, events, event_mask);
+		else
+			dev_dbg(host->dev, "%s: MRQ=NULL events:%08X evt_mask=%08X,sd_status:%d\n",
+				__func__, events, event_mask, readl(host->base + MCI_CARD_DETECT));
+		goto irq_out;
+	}
+
+	if ((dmac_events & dmac_err_ints_mask) || (events & cmd_err_ints_mask)) {
+		dev_dbg(host->dev, "ERR:events:%x,mask:0x%x,dmac_evts:%x,dmac_mask:0x%x,cmd:%d\n",
+			events, event_mask, dmac_events, dmac_evt_mask, mrq->cmd->opcode);
+		phytium_mci_err_irq(host, dmac_events & dmac_err_ints_mask,
+						    events & cmd_err_ints_mask);
+		goto irq_out;
+	}
+
+	if ((events & MCI_MASKED_INTS_DTO) && (events & MCI_MASKED_INTS_CMD)) {
+		phytium_mci_cmd_done(host, events, mrq, cmd);
+		phytium_mci_data_xfer_done(host, (events & data_ints_mask) |
+					    (dmac_events & dmac_ints_mask), mrq, data);
+	} else if (events & MCI_MASKED_INTS_CMD ||
+		  ((events & MCI_INT_MASK_HTO) && (cmd->opcode == SD_SWITCH_VOLTAGE))) {
+		phytium_mci_cmd_done(host, events, mrq, cmd);
+	} else if (events & MCI_MASKED_INTS_DTO) {
+		phytium_mci_data_xfer_done(host, (events & data_ints_mask) |
+					    (dmac_events & dmac_ints_mask), mrq, data);
+	}
+
+irq_out:
+	return IRQ_HANDLED;
+}
+
+static void phytium_mci_init_hw(struct phytium_mci_host *host)
+{
+	u32 val;
+	int uhs_reg_value = 0x502;
+
+	writel(MCI_SET_FIFOTH(0x2, 0x7, 0x100), host->base + MCI_FIFOTH);
+	writel(0x800001, host->base + MCI_CARD_THRCTL);
+	sdr_clr_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+	phytium_mci_update_external_clk(host, uhs_reg_value);
+
+	sdr_set_bits(host->base + MCI_PWREN, MCI_PWREN_ENABLE);
+	sdr_set_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+	sdr_set_bits(host->base + MCI_UHS_REG_EXT, MCI_EXT_CLK_ENABLE);
+	sdr_clr_bits(host->base + MCI_UHS_REG, MCI_UHS_REG_VOLT);
+
+	phytium_mci_reset_hw(host);
+
+	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
+		sdr_set_bits(host->base + MCI_CARD_RESET, MCI_CARD_RESET_ENABLE);
+	else
+		sdr_clr_bits(host->base + MCI_CARD_RESET, MCI_CARD_RESET_ENABLE);
+
+	writel(0, host->base + MCI_INT_MASK);
+	val = readl(host->base + MCI_RAW_INTS);
+	writel(val, host->base + MCI_RAW_INTS);
+	writel(0, host->base + MCI_DMAC_INT_ENA);
+	val = readl(host->base + MCI_DMAC_STATUS);
+	writel(val, host->base + MCI_DMAC_STATUS);
+	if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE))
+		writel(MCI_INT_MASK_CD, host->base + MCI_INT_MASK);
+
+	sdr_set_bits(host->base + MCI_CNTRL, MCI_CNTRL_INT_ENABLE |
+		     MCI_CNTRL_USE_INTERNAL_DMAC);
+
+	writel(0xFFFFFFFF, host->base + MCI_TMOUT);
+	dev_info(host->dev, "init hardware done!");
+
+}
+
+void phytium_mci_deinit_hw(struct phytium_mci_host *host)
+{
+	u32 val;
+
+	sdr_clr_bits(host->base + MCI_PWREN, MCI_PWREN_ENABLE);
+	sdr_clr_bits(host->base + MCI_CLKENA, MCI_CLKENA_CCLK_ENABLE);
+	sdr_clr_bits(host->base + MCI_UHS_REG_EXT, MCI_EXT_CLK_ENABLE);
+	sdr_clr_bits(host->base + MCI_UHS_REG, MCI_UHS_REG_VOLT);
+	writel(0, host->base + MCI_INT_MASK);
+	val = readl(host->base + MCI_RAW_INTS);
+	writel(val, host->base + MCI_RAW_INTS);
+	writel(0, host->base + MCI_DMAC_INT_ENA);
+	val = readl(host->base + MCI_DMAC_STATUS);
+	writel(val, host->base + MCI_DMAC_STATUS);
+	if (!(host->mmc->caps & MMC_CAP_NONREMOVABLE))
+		writel(MCI_INT_MASK_CD, host->base + MCI_INT_MASK);
+}
+EXPORT_SYMBOL_GPL(phytium_mci_deinit_hw);
+
+static void phytium_mci_adma_reset(struct phytium_mci_host *host)
+{
+	u32 bmod = readl(host->base + MCI_BUS_MODE);
+
+	bmod |= MCI_BUS_MODE_SWR;
+	writel(bmod, host->base + MCI_BUS_MODE);
+}
+
+static void phytium_mci_init_adma_table(struct phytium_mci_host *host,
+					 struct phytium_mci_dma *dma)
+{
+	struct phytium_adma2_64_desc *adma_table = dma->adma_table;
+	dma_addr_t dma_addr;
+	int i;
+
+	memset(adma_table, 0, sizeof(struct phytium_adma2_64_desc) * MAX_BD_NUM);
+
+	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
+		dma_addr = dma->adma_addr + sizeof(*adma_table) * (i + 1);
+		adma_table[i].desc_lo = lower_32_bits(dma_addr);
+		adma_table[i].desc_hi = upper_32_bits(dma_addr);
+		adma_table[i].attribute = 0;
+		adma_table[i].NON1 = 0;
+		adma_table[i].len = 0;
+		adma_table[i].NON2 = 0;
+	}
+
+	phytium_mci_adma_reset(host);
+}
+
+static void phytium_mci_set_buswidth(struct phytium_mci_host *host, u32 width)
+{
+	u32 val;
+
+	switch (width) {
+	case MMC_BUS_WIDTH_1:
+		val = MCI_BUS_1BITS;
+		break;
+
+	case MMC_BUS_WIDTH_4:
+		val = MCI_BUS_4BITS;
+		break;
+
+	case MMC_BUS_WIDTH_8:
+		val = MCI_BUS_8BITS;
+		break;
+	default:
+		val = MCI_BUS_4BITS;
+		break;
+	}
+	writel(val, host->base + MCI_CTYPE);
+	dev_dbg(host->dev, "Bus Width = %d, set value:0x%x\n", width, val);
+}
+
+static void phytium_mci_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+
+	if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50)
+		sdr_set_bits(host->base + MCI_UHS_REG, MCI_UHS_REG_DDR);
+	else
+		sdr_clr_bits(host->base + MCI_UHS_REG, MCI_UHS_REG_DDR);
+
+	phytium_mci_set_buswidth(host, ios->bus_width);
+
+	switch (ios->power_mode) {
+	case MMC_POWER_UP:
+		set_bit(MCI_CARD_NEED_INIT, &host->flags);
+		writel(MCI_POWER_ON, host->base + MCI_PWREN);
+		break;
+
+	case MMC_POWER_ON:
+		break;
+
+	case MMC_POWER_OFF:
+		writel(MCI_POWER_OFF, host->base + MCI_PWREN);
+		break;
+
+	default:
+		break;
+	}
+	phytium_mci_set_clk(host, ios);
+}
+
+static void phytium_mci_ack_sdio_irq(struct mmc_host *mmc)
+{
+	unsigned long flags;
+	struct phytium_mci_host *host = mmc_priv(mmc);
+
+	spin_lock_irqsave(&host->lock, flags);
+	__phytium_mci_enable_sdio_irq(host, 1);
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static int phytium_mci_get_cd(struct mmc_host *mmc)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	u32 status;
+
+	if (mmc->caps & MMC_CAP_NONREMOVABLE)
+		return 1;
+
+	status = readl(host->base + MCI_CARD_DETECT);
+
+	if ((status & 0x1) == 0x1)
+		return 0;
+
+	return 1;
+}
+
+static int phytium_mci_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	unsigned int is_voltage_180 = 0;
+
+	is_voltage_180 = readl(host->base + MCI_UHS_REG);
+	if ((mmc->caps & MMC_CAP_NONREMOVABLE) && (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180))
+		return -EINVAL;
+
+	if ((ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) && (is_voltage_180 & 0x1))
+		sdr_clr_bits(host->base + MCI_UHS_REG, MCI_UHS_REG_VOLT);
+	else if ((ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) && (!(is_voltage_180 & 0x1)))
+		sdr_set_bits(host->base + MCI_UHS_REG, MCI_UHS_REG_VOLT);
+	else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_120)
+		return -EINVAL;
+	return 0;
+}
+
+static void phytium_mci_hw_reset(struct mmc_host *mmc)
+{
+	struct phytium_mci_host *host = mmc_priv(mmc);
+	u32 reset_flag;
+
+	if (host->is_use_dma) {
+		reset_flag = MCI_CNTRL_FIFO_RESET | MCI_CNTRL_DMA_RESET;
+		phytium_mci_adma_reset(host);
+		sdr_set_bits(host->base + MCI_CNTRL, reset_flag);
+	} else {
+		reset_flag = MCI_CNTRL_FIFO_RESET;
+		sdr_set_bits(host->base + MCI_CNTRL, reset_flag);
+	}
+
+	while (readl(host->base + MCI_CNTRL) & reset_flag)
+		cpu_relax();
+
+	sdr_clr_bits(host->base + MCI_CARD_RESET, MCI_CARD_RESET_ENABLE);
+	udelay(5);
+	sdr_set_bits(host->base + MCI_CARD_RESET, MCI_CARD_RESET_ENABLE);
+	usleep_range(200, 300);
+}
+
+#ifdef CONFIG_PM_SLEEP
+int phytium_mci_suspend(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_mci_host *host = mmc_priv(mmc);
+
+	phytium_mci_deinit_hw(host);
+	return 0;
+}
+EXPORT_SYMBOL(phytium_mci_suspend);
+
+int phytium_mci_resume(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_mci_host *host = mmc_priv(mmc);
+
+	phytium_mci_init_hw(host);
+	return 0;
+}
+EXPORT_SYMBOL(phytium_mci_resume);
+
+#endif
+
+#ifdef CONFIG_PM
+int phytium_mci_runtime_suspend(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_mci_host *host = mmc_priv(mmc);
+
+	phytium_mci_deinit_hw(host);
+	return 0;
+}
+EXPORT_SYMBOL(phytium_mci_runtime_suspend);
+
+int phytium_mci_runtime_resume(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_mci_host *host = mmc_priv(mmc);
+
+	phytium_mci_init_hw(host);
+	return 0;
+}
+EXPORT_SYMBOL(phytium_mci_runtime_resume);
+
+#endif
+
+static struct mmc_host_ops phytium_mci_ops = {
+	.post_req = phytium_mci_post_req,
+	.pre_req = phytium_mci_pre_req,
+	.request = phytium_mci_ops_request,
+	.set_ios = phytium_mci_ops_set_ios,
+	.get_cd = phytium_mci_get_cd,
+	.enable_sdio_irq = phytium_mci_enable_sdio_irq,
+	.ack_sdio_irq = phytium_mci_ack_sdio_irq,
+	.card_busy = phytium_mci_card_busy,
+	.start_signal_voltage_switch = phytium_mci_ops_switch_volt,
+	.hw_reset = phytium_mci_hw_reset,
+};
+
+int phytium_mci_common_probe(struct phytium_mci_host *host)
+{
+	struct mmc_host *mmc = host->mmc;
+	struct device *dev = host->dev;
+	int ret;
+
+	dma_set_mask(dev, DMA_BIT_MASK(64));
+	dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
+
+	timer_setup(&host->hotplug_timer, hotplug_timer_func, 0);
+	timer_setup(&host->timeout_timer, phytium_mci_request_timeout, 0);
+
+	mmc->f_min = MCI_F_MIN;
+	if (!mmc->f_max)
+		mmc->f_max = MCI_F_MAX;
+
+	mmc->ops = &phytium_mci_ops;
+	mmc->ocr_avail_sdio = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->ocr_avail_mmc = MMC_VDD_165_195;
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	mmc->caps |= host->caps;
+
+	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
+		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
+		dev_dbg(host->dev, "%s %d: MMC_CAP_SDIO_IRQ\n", __func__, __LINE__);
+	}
+	mmc->caps2 |= host->caps2;
+	if (host->is_use_dma) {
+		/* MMC core transfer sizes tunable parameters */
+		mmc->max_segs = MAX_BD_NUM;
+		mmc->max_seg_size = 4 * 1024;
+		mmc->max_blk_size = 512;
+		mmc->max_req_size = 512 * 1024;
+		mmc->max_blk_count = mmc->max_req_size / 512;
+		host->dma.adma_table = dma_alloc_coherent(host->dev,
+							  MAX_BD_NUM *
+							  sizeof(struct phytium_adma2_64_desc),
+							  &host->dma.adma_addr, GFP_KERNEL);
+		if (!host->dma.adma_table)
+			return MCI_REALEASE_MEM;
+
+		host->dma.desc_sz = ADMA2_64_DESC_SZ;
+		phytium_mci_init_adma_table(host, &host->dma);
+	} else {
+		mmc->max_segs = MAX_BD_NUM;
+		mmc->max_seg_size = 4 * 1024;
+		mmc->max_blk_size = 512;
+		mmc->max_req_size = 4 * 512;
+		mmc->max_blk_count = mmc->max_req_size / 512;
+	}
+
+	spin_lock_init(&host->lock);
+
+	phytium_mci_init_hw(host);
+	ret = devm_request_irq(host->dev, host->irq, phytium_mci_irq,
+			       host->irq_flags, "phytium-mci", host);
+
+	if (ret)
+		return ret;
+
+	ret = mmc_add_host(mmc);
+
+	if (ret) {
+		dev_err(host->dev, "%s %d: mmc add host!\n", __func__, __LINE__);
+		return ret;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(phytium_mci_common_probe);
+
+MODULE_DESCRIPTION("Phytium Multimedia Card Interface driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci.h b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci.h
new file mode 100644
index 00000000000000..5423597ecb97b1
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-mci.h
@@ -0,0 +1,357 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Driver for Phytium Multimedia Card Interface
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_MCI_H
+#define __PHYTIUM_MCI_H
+
+#include <linux/scatterlist.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/host.h>
+
+/*------------------------------------------------------*/
+/* Common Definition					*/
+/*------------------------------------------------------*/
+#define MAX_BD_NUM		128
+#define SD_BLOCK_SIZE		512
+
+#define MCI_BUS_1BITS          0x0
+#define MCI_BUS_4BITS          0x1
+#define MCI_BUS_8BITS          (0x1 << 16)
+
+#define MCI_SD_DRV_VALUE       0
+#define MCI_SD_SAMP_VALUE_MAX  0
+#define MCI_SD_SAMP_VALUE_MIN  0
+
+#define MCI_TIMEOUT_CMD_VALUE  0xFFFFFFFF
+#define MCI_POWER_ON           1
+#define MCI_POWER_OFF          0
+
+#define MCI_PREPARE_FLAG		(0x1 << 0)
+#define MCI_ASYNC_FLAG			(0x1 << 1)
+#define MCI_MMAP_FLAG			(0x1 << 2)
+
+#define MCI_CMD_TIMEOUT	(HZ/10 * 50)	/* 100ms x5 */
+#define MCI_DATA_TIMEOUT	(HZ    * 10)	/* 1000ms x5 */
+
+#define MCI_CMD_TYPE_ADTC      0x2
+
+#define MCI_F_MIN		400000
+#define MCI_F_MAX		50000000
+
+#define MCI_CLK		1200000000
+#define MCI_REALEASE_MEM	0x1
+#define MCI_MAX_FIFO_CNT	0x800
+
+/* FIFOTH register defines */
+#define MCI_SET_FIFOTH(m, r, t)	(((m) & 0x7) << 28 | \
+					 ((r) & 0xFFF) << 16 | ((t) & 0xFFF))
+/* Card read threshold */
+#define MCI_SET_THLD(v, x)		(((v) & 0xFFF) << 16 | (x))
+#define MCI_CARD_WR_THR_EN		BIT(2)
+#define MCI_CARD_RD_THR_EN		BIT(0)
+
+/*----------------------------------------------------------------------*/
+/* Register Offset							*/
+/*----------------------------------------------------------------------*/
+#define MCI_CNTRL		0x00 /* the controller config reg */
+#define MCI_PWREN		0x04 /* the power enable reg */
+#define MCI_CLKDIV		0x08 /* the clock divider reg */
+#define MCI_CLKENA		0x10 /* the clock enable reg */
+#define MCI_TMOUT		0x14 /* the timeout reg */
+#define MCI_CTYPE		0x18 /* the card type reg */
+#define MCI_BLKSIZ		0x1C /* the block size reg */
+#define MCI_BYTCNT		0x20 /* the byte count reg */
+#define MCI_INT_MASK		0x24 /* the interrupt mask reg */
+#define MCI_CMDARG		0x28 /* the command argument reg */
+#define MCI_CMD		0x2C /* the command reg */
+#define MCI_RESP0		0x30 /* the response reg0 */
+#define MCI_RESP1		0x34 /* the response reg1 */
+#define MCI_RESP2		0x38 /* the response reg2 */
+#define MCI_RESP3		0X3C /* the response reg3 */
+#define MCI_MASKED_INTS	0x40 /* the masked interrupt status reg */
+#define MCI_RAW_INTS		0x44 /* the raw interrupt status reg */
+#define MCI_STATUS		0x48 /* the status reg	*/
+#define MCI_FIFOTH		0x4C /* the FIFO threshold watermark reg */
+#define MCI_CARD_DETECT	0x50 /* the card detect reg */
+#define MCI_CARD_WRTPRT	0x54 /* the card write protect reg */
+#define MCI_CCLK_RDY		0x58 /* first div is ready? 1:ready,0:not ready*/
+#define MCI_TRAN_CARD_CNT	0x5C /* the transferred CIU card byte count reg */
+#define MCI_TRAN_FIFO_CNT	0x60 /* the transferred host to FIFO byte count reg  */
+#define MCI_DEBNCE		0x64 /* the debounce count reg */
+#define MCI_UID		0x68 /* the user ID reg */
+#define MCI_VID		0x6C /* the controller version ID reg */
+#define MCI_HWCONF		0x70 /* the hardware configuration reg */
+#define MCI_UHS_REG		0x74 /* the UHS-I reg */
+#define MCI_CARD_RESET		0x78 /* the card reset reg */
+#define MCI_BUS_MODE		0x80 /* the bus mode reg */
+#define MCI_DESC_LIST_ADDRL	0x88 /* the descriptor list low base address reg */
+#define MCI_DESC_LIST_ADDRH	0x8C /* the descriptor list high base address reg */
+#define MCI_DMAC_STATUS	0x90 /* the internal DMAC status reg */
+#define MCI_DMAC_INT_ENA	0x94 /* the internal DMAC interrupt enable reg */
+#define MCI_CUR_DESC_ADDRL	0x98 /* the current host descriptor low address reg */
+#define MCI_CUR_DESC_ADDRH	0x9C /* the current host descriptor high address reg */
+#define MCI_CUR_BUF_ADDRL	0xA0 /* the current buffer low address reg */
+#define MCI_CUR_BUF_ADDRH	0xA4 /* the current buffer high address reg */
+#define MCI_CARD_THRCTL	0x100 /* the card threshold control reg */
+#define MCI_UHS_REG_EXT	0x108 /* the UHS register extension */
+#define MCI_EMMC_DDR_REG	0x10C /* the EMMC DDR reg */
+#define MCI_ENABLE_SHIFT	0x110 /* the enable phase shift reg */
+#define MCI_DATA		0x200 /* the data FIFO access */
+
+/* Command register defines */
+#define MCI_CMD_START			BIT(31)
+#define MCI_CMD_USE_HOLD_REG		BIT(29)
+#define MCI_CMD_VOLT_SWITCH		BIT(28)
+#define MCI_CMD_CCS_EXP		BIT(23)
+#define MCI_CMD_CEATA_RD		BIT(22)
+#define MCI_CMD_UPD_CLK		BIT(21)
+#define MCI_CMD_INIT			BIT(15)
+#define MCI_CMD_STOP			BIT(14)
+#define MCI_CMD_PRV_DAT_WAIT		BIT(13)
+#define MCI_CMD_SEND_STOP		BIT(12)
+#define MCI_CMD_STRM_MODE		BIT(11)
+#define MCI_CMD_DAT_WR			BIT(10)
+#define MCI_CMD_DAT_EXP		BIT(9)
+#define MCI_CMD_RESP_CRC		BIT(8)
+#define MCI_CMD_RESP_LONG		BIT(7)
+#define MCI_CMD_RESP_EXP		BIT(6)
+#define MCI_CMD_INDX(n)		((n) & 0x1F)
+
+/*------------------------------------------------------*/
+/* Register Mask					*/
+/*------------------------------------------------------*/
+/* MCI_CNTRL mask */
+#define MCI_CNTRL_CONTROLLER_RESET	(0x1 << 0) /* RW */
+#define MCI_CNTRL_FIFO_RESET		(0x1 << 1) /* RW */
+#define MCI_CNTRL_DMA_RESET			(0x1 << 2) /* RW */
+#define MCI_CNTRL_RES				(0x1 << 3) /*  */
+#define MCI_CNTRL_INT_ENABLE		(0x1 << 4) /* RW */
+#define MCI_CNTRL_DMA_ENABLE		(0x1 << 5) /* RW */
+#define MCI_CNTRL_READ_WAIT			(0x1 << 6) /* RW */
+#define MCI_CNTRL_SEND_IRQ_RESPONSE	(0x1 << 7) /* RW */
+#define MCI_CNTRL_ABORT_READ_DATA	(0x1 << 8) /* RW */
+#define MCI_CNTRL_ENDIAN			(0x1 << 11) /* RW */
+//#define MCI_CNTRL_CARD_VOLTAGE_A	(0xF << 16) /* RW */
+//#define MCI_CNTRL_CARD_VOLTAGE_B	(0xF << 20) /* RW */
+#define MCI_CNTRL_ENABLE_OD_PULLUP	(0x1 << 24) /* RW */
+#define MCI_CNTRL_USE_INTERNAL_DMAC	(0x1 << 25) /* RW */
+
+/* MCI_PWREN mask */
+#define MCI_PWREN_ENABLE		(0x1 << 0)  /* RW */
+
+/* MCI_CLKENA mask */
+#define MCI_CLKENA_CCLK_ENABLE		(0x1 << 0) /* RW */
+#define MCI_CLKENA_CCLK_LOW_POWER	(0x1 << 16) /* RW */
+#define MCI_EXT_CLK_ENABLE		(0x1 << 1)
+
+/* MCI_INT_MASK mask */
+#define MCI_INT_MASK_CD		(0x1 << 0) /* RW */
+#define MCI_INT_MASK_RE		(0x1 << 1) /* RW */
+#define MCI_INT_MASK_CMD		(0x1 << 2) /* RW */
+#define MCI_INT_MASK_DTO		(0x1 << 3) /* RW */
+#define MCI_INT_MASK_TXDR		(0x1 << 4) /* RW */
+#define MCI_INT_MASK_RXDR		(0x1 << 5) /* RW */
+#define MCI_INT_MASK_RCRC		(0x1 << 6) /* RW */
+#define MCI_INT_MASK_DCRC		(0x1 << 7) /* RW */
+#define MCI_INT_MASK_RTO		(0x1 << 8) /* RW */
+#define MCI_INT_MASK_DRTO		(0x1 << 9) /* RW */
+#define MCI_INT_MASK_HTO		(0x1 << 10) /* RW */
+#define MCI_INT_MASK_FRUN		(0x1 << 11) /* RW */
+#define MCI_INT_MASK_HLE		(0x1 << 12) /* RW */
+#define MCI_INT_MASK_SBE_BCI		(0x1 << 13) /* RW */
+#define MCI_INT_MASK_ACD		(0x1 << 14) /* RW */
+#define MCI_INT_MASK_EBE		(0x1 << 15) /* RW */
+#define MCI_INT_MASK_SDIO		(0x1 << 16) /* RW */
+
+/* MCI_MASKED_INTS mask */
+#define MCI_MASKED_INTS_CD		(0x1 << 0) /* RO */
+#define MCI_MASKED_INTS_RE		(0x1 << 1) /* RO */
+#define MCI_MASKED_INTS_CMD		(0x1 << 2) /* RO */
+#define MCI_MASKED_INTS_DTO		(0x1 << 3) /* RO */
+#define MCI_MASKED_INTS_TXDR		(0x1 << 4) /* RO */
+#define MCI_MASKED_INTS_RXDR		(0x1 << 5) /* RO */
+#define MCI_MASKED_INTS_RCRC		(0x1 << 6) /* RO */
+#define MCI_MASKED_INTS_DCRC		(0x1 << 7) /* RO */
+#define MCI_MASKED_INTS_RTO		(0x1 << 8) /* RO */
+#define MCI_MASKED_INTS_DRTO		(0x1 << 9) /* RO */
+#define MCI_MASKED_INTS_HTO		(0x1 << 10) /* RO */
+#define MCI_MASKED_INTS_FRUN		(0x1 << 11) /* RO */
+#define MCI_MASKED_INTS_HLE		(0x1 << 12) /* RO */
+#define MCI_MASKED_INTS_SBE_BCI	(0x1 << 13) /* RO */
+#define MCI_MASKED_INTS_ACD		(0x1 << 14) /* RO */
+#define MCI_MASKED_INTS_EBE		(0x1 << 15) /* RO */
+#define MCI_MASKED_INTS_SDIO		(0x1 << 16) /* RO */
+
+/* MCI_RAW_INTS mask */
+#define MCI_RAW_INTS_CD		(0x1 << 0) /* W1C */
+#define MCI_RAW_INTS_RE		(0x1 << 1) /* W1C */
+#define MCI_RAW_INTS_CMD		(0x1 << 2) /* W1C */
+#define MCI_RAW_INTS_DTO		(0x1 << 3) /* W1C */
+#define MCI_RAW_INTS_TXDR		(0x1 << 4) /* W1C */
+#define MCI_RAW_INTS_RXDR		(0x1 << 5) /* W1C */
+#define MCI_RAW_INTS_RCRC		(0x1 << 6) /* W1C */
+#define MCI_RAW_INTS_DCRC		(0x1 << 7) /* W1C */
+#define MCI_RAW_INTS_RTO		(0x1 << 8) /* W1C */
+#define MCI_RAW_INTS_DRTO		(0x1 << 9) /* W1C */
+#define MCI_RAW_INTS_HTO		(0x1 << 10) /* W1C */
+#define MCI_RAW_INTS_FRUN		(0x1 << 11) /* W1C */
+#define MCI_RAW_INTS_HLE		(0x1 << 12) /* W1C */
+#define MCI_RAW_INTS_SBE_BCI		(0x1 << 13) /* W1C */
+#define MCI_RAW_INTS_ACD		(0x1 << 14) /* W1C */
+#define MCI_RAW_INTS_EBE		(0x1 << 15) /* W1C */
+#define MCI_RAW_INTS_SDIO		(0x1 << 16)  /* W1C */
+
+/* MCI_STATUS mask */
+#define MCI_STATUS_FIFO_RX		(0x1 << 0) /* RO */
+#define MCI_STATUS_FIFO_TX		(0x1 << 1) /* RO */
+#define MCI_STATUS_FIFO_EMPTY		(0x1 << 2) /* RO */
+#define MCI_STATUS_FIFO_FULL		(0x1 << 3) /* RO */
+#define MCI_STATUS_CARD_STATUS		(0x1 << 8) /* RO */
+#define MCI_STATUS_CARD_BUSY		(0x1 << 9) /* RO */
+#define MCI_STATUS_DATA_BUSY		(0x1 << 10) /* RO */
+#define MCI_STATUS_RESPOSE_INDEX_OFFSET		(11)
+#define MCI_STATUS_RESPOSE_INDEX_MASK		(0x3f << MCI_STATUS_RESPOSE_INDEX_OFFSET) /* RO */
+#define MCI_STATUS_RESPOSE_INDEX(reg)		(((reg) & MCI_STATUS_RESPOSE_INDEX_MASK) >> MCI_STATUS_RESPOSE_INDEX_OFFSET)
+#define MCI_STATUS_DMA_ACK		(0x1 << 31) /* RO */
+#define MCI_STATUS_DMA_REQ		(0x1 << 32) /* RO */
+
+/* MCI_UHS_REG mask */
+#define MCI_UHS_REG_VOLT		(0x1 << 0) /* RW */
+#define MCI_UHS_REG_DDR		(0x1 << 16) /* RW */
+
+/* MCI_CARD_RESET mask */
+#define MCI_CARD_RESET_ENABLE		(0x1 << 0) /* RW */
+
+/* MCI_BUS_MODE mask */
+#define MCI_BUS_MODE_SWR		(0x1 << 0) /* RW */
+#define MCI_BUS_MODE_FB		(0x1 << 1) /* RW */
+#define MCI_BUS_MODE_DE		(0x1 << 7) /* RW */
+
+/* MCI_DMAC_STATUS mask */
+#define MCI_DMAC_STATUS_TI		(0x1 << 0) /* RW */
+#define MCI_DMAC_STATUS_RI		(0x1 << 1) /* RW */
+#define MCI_DMAC_STATUS_FBE		(0x1 << 2) /* RW */
+#define MCI_DMAC_STATUS_DU		(0x1 << 4) /* RW */
+#define MCI_DMAC_STATUS_NIS		(0x1 << 8) /* RW */
+#define MCI_DMAC_STATUS_AIS		(0x1 << 9) /* RW */
+
+/* MCI_DMAC_INT_ENA mask */
+#define MCI_DMAC_INT_ENA_TI		(0x1 << 0) /* RW */
+#define MCI_DMAC_INT_ENA_RI		(0x1 << 1) /* RW */
+#define MCI_DMAC_INT_ENA_FBE		(0x1 << 2) /* RW */
+#define MCI_DMAC_INT_ENA_DU		(0x1 << 4) /* RW */
+#define MCI_DMAC_INT_ENA_CES		(0x1 << 5) /* RW */
+#define MCI_DMAC_INT_ENA_NIS		(0x1 << 8) /* RW */
+#define MCI_DMAC_INT_ENA_AIS		(0x1 << 9) /* RW */
+
+/* MCI_CARD_THRCTL mask */
+#define MCI_CARD_THRCTL_CARDRD		(0x1 << 0) /* RW */
+#define MCI_CARD_THRCTL_BUSY_CLR	(0x1 << 1) /* RW */
+#define MCI_CARD_THRCTL_CARDWR		(0x1 << 2) /* RW */
+
+/* MCI_UHS_REG_EXT mask */
+#define MCI_UHS_REG_EXT_MMC_VOLT	(0x1 << 0) /* RW */
+#define MCI_UHS_REG_EXT_CLK_ENA	(0x1 << 1) /* RW */
+
+/* MCI_EMMC_DDR_REG mask */
+#define MCI_EMMC_DDR_CYCLE		(0x1 << 0) /* RW */
+
+/*--------------------------------------*/
+/*		Structure Type		*/
+/*--------------------------------------*/
+/* Maximum segments assuming a 512KiB maximum requisition */
+/* size and a minimum4KiB page size. */
+#define MCI_MAX_SEGS		128
+/* ADMA2 64-bit DMA descriptor size */
+#define ADMA2_64_DESC_SZ	32
+
+/* mmc request timeout 5000ms */
+#define MMC_REQ_TIMEOUT_MS 5000
+
+/* Each descriptor can transfer up to 4KB of data in chained mode */
+/*ADMA2 64-bit descriptor.*/
+struct phytium_adma2_64_desc {
+	u32 attribute;
+#define IDMAC_DES0_DIC	BIT(1)
+#define IDMAC_DES0_LD	BIT(2)
+#define IDMAC_DES0_FD	BIT(3)
+#define IDMAC_DES0_CH	BIT(4)
+#define IDMAC_DES0_ER	BIT(5)
+#define IDMAC_DES0_CES	BIT(30)
+#define IDMAC_DES0_OWN	BIT(31)
+	u32	NON1;
+	u32	len;
+	u32	NON2;
+	u32	addr_lo; /* Lower 32-bits of Buffer Address Pointer 1*/
+	u32	addr_hi; /* Upper 32-bits of Buffer Address Pointer 1*/
+	u32	desc_lo; /* Lower 32-bits of Next Descriptor Address */
+	u32	desc_hi; /* Upper 32-bits of Next Descriptor Address */
+} __packed __aligned(4);
+
+struct phytium_mci_dma {
+	struct scatterlist *sg;	/* I/O scatter list */
+	/* ADMA descriptor table, pointer to adma_table array */
+	struct phytium_adma2_64_desc *adma_table;
+	/* Mapped ADMA descr. table, the physical address of adma_table array */
+	dma_addr_t adma_addr;
+	unsigned int desc_sz;	/* ADMA descriptor size */
+};
+
+enum adtc_t {
+	COMMOM_ADTC	= 0,
+	BLOCK_RW_ADTC	= 1
+};
+
+struct phytium_mci_host {
+	struct device *dev;
+	struct mmc_host *mmc;
+	u32 caps;
+	u32 caps2;
+	spinlock_t lock;
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+	int error;
+	void __iomem *base;		    /* host base address */
+	void *adma_table1;
+	dma_addr_t adma_addr1;
+	struct phytium_mci_dma dma_rx;	/* dma channel */
+	struct phytium_mci_dma dma_tx;	/* dma channel */
+	struct phytium_mci_dma dma;	/* dma channel */
+	u64 dma_mask;
+	bool vqmmc_enabled;
+	u32 *sg_virt_addr;
+	enum adtc_t adtc_type;      /* 0:common adtc cmd; 1:block r/w adtc cmd;*/
+	struct timer_list hotplug_timer;
+	struct timer_list timeout_timer;
+	struct delayed_work req_timeout;
+	int irq;		    /* host interrupt */
+	u32 current_rca;    /*the current rca value*/
+	u32 current_ios_clk;
+	u32 is_use_dma;
+	u32 is_device_x100;
+	struct clk *src_clk;	    /* phytium_mci source clock */
+	unsigned long clk_rate;
+	unsigned long clk_div;
+	unsigned long irq_flags;
+	unsigned long flags;
+#define MCI_CARD_NEED_INIT	1
+
+};
+
+int phytium_mci_common_probe(struct phytium_mci_host *host);
+void phytium_mci_deinit_hw(struct phytium_mci_host *host);
+int phytium_mci_runtime_suspend(struct device *dev);
+int phytium_mci_runtime_resume(struct device *dev);
+int phytium_mci_resume(struct device *dev);
+int phytium_mci_suspend(struct device *dev);
+
+#endif /* __PHYTIUM_MCI_HW_H */
diff --git a/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-sdci.c b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-sdci.c
new file mode 100755
index 00000000000000..929162b8d5bf8a
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-sdci.c
@@ -0,0 +1,1433 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SD Card Interface dirver
+ *
+ * Copyright (c) 2019-2023, Phytium Technology Co.,Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/acpi.h>
+#include <linux/timer.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+
+#include "phytium-sdci.h"
+
+static const u32 cmd_ints_mask = SDCI_SDCI_NORMAL_ISER_ECC_EN | SDCI_SDCI_NORMAL_ISER_EEI_EN;
+static const u32 data_ints_mask = SDCI_BD_ISER_ETRS_EN;
+static const u32 err_ints_mask = SDCI_ERROR_ISER_ECTE_EN | SDCI_ERROR_ISR_CCRCE_EN |
+				  SDCI_ERROR_ISR_CIR_EN | SDCI_ERROR_ISR_CNR_EN;
+
+static void hotplug_timer_func(struct timer_list *t);
+static bool phytium_sdci_private_send_cmd(struct phytium_sdci_host *host,
+					  u32 cmd, u32 resp_type, u32 arg);
+static bool phytium_sdci_cmd_done(struct phytium_sdci_host *host, int events,
+				  struct mmc_request *mrq,
+				  struct mmc_command *cmd);
+static bool phytium_sdci_data_xfer_done(struct phytium_sdci_host *host,
+					u32 events, struct mmc_request *mrq,
+					struct mmc_data *data);
+static void phytium_sdci_cmd_next(struct phytium_sdci_host *host,
+				  struct mmc_request *mrq,
+				  struct mmc_command *cmd);
+
+static int phytium_sdci_cmd13_process(struct phytium_sdci_host *host,
+				       struct mmc_request *mrq,
+				       struct mmc_data *data,
+				       u32 wait_timeout_ms,
+				       u32 send_once_time_ms);
+
+static int phytium_sd_error(struct phytium_sdci_host *host)
+{
+	int temp;
+
+	temp = readl(host->base + SDCI_NORMAL_ISR);
+	dev_err(host->dev, "[%s %d]SDCI_NORMAL_ISR:%x\n", __func__, __LINE__, temp);
+	temp = readl(host->base + SDCI_BD_ISR);
+	temp = readl(host->base + SDCI_ERROR_ISR);
+	dev_err(host->dev, "[%s %d]SDCI_ERROR_ISR:%x\n", __func__, __LINE__, temp);
+	temp = readl(host->base + SDCI_BD_ISR);
+	dev_err(host->dev, "[%s %d]SDCI_BD_ISR:%x\n", __func__, __LINE__, temp);
+	temp = readl(host->base + SDCI_RESP0);
+	dev_err(host->dev, "[%s %d]SDCI_RESP0:%x\n", __func__, __LINE__, temp);
+
+	return 0;
+}
+
+static void sdr_set_bits(void __iomem *reg, u32 bs)
+{
+	u32 val;
+
+	val = readl(reg);
+	val |= bs;
+
+	writel(val, reg);
+}
+
+static void sdr_clr_bits(void __iomem *reg, u32 bs)
+{
+	u32 val;
+
+	val = readl(reg);
+	val &= ~bs;
+
+	writel(val, reg);
+}
+
+static void phytium_sdci_reset_hw(struct phytium_sdci_host *host)
+{
+	sdr_set_bits(host->base + SDCI_SOFTWARE,
+		     SDCI_SOFTWARE_SRST);
+	sdr_clr_bits(host->base + SDCI_SOFTWARE,
+		     SDCI_SOFTWARE_SRST);
+	while (!(readl(host->base + SDCI_STATUS) & SDCI_STATUS_IDIE))
+		cpu_relax();
+}
+
+static void phytium_sdci_prepare_data(struct phytium_sdci_host *host,
+				      struct mmc_request *mrq)
+{
+	struct mmc_data *data = mrq->data;
+	bool read;
+
+	read = (data->flags & MMC_DATA_READ) != 0;
+	data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
+				    read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
+}
+
+static void phytium_sdci_unprepare_data(struct phytium_sdci_host *host,
+					struct mmc_request *mrq)
+{
+	bool read;
+	struct mmc_data *data = mrq->data;
+
+	read = (data->flags & MMC_DATA_READ) != 0;
+	dma_unmap_sg(host->dev, data->sg, data->sg_len,
+		     read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
+}
+
+static void phytium_sdci_set_clk(struct phytium_sdci_host *host,
+				 struct mmc_ios *ios)
+{
+	unsigned long clk_rate;
+	u32 div = 0xffffffff, div_reg;
+
+	if (ios->clock) {
+		clk_rate = host->clk_rate;
+		div = ((clk_rate / (2 * ios->clock)) - 1);
+		div_reg = readl(host->base + SDCI_CLOCK_D);
+		if (div_reg == div)
+			return;
+		writel(div, host->base + SDCI_CLOCK_D);
+		writel(0, host->base + SDCI_SD_DRV);
+		writel(5, host->base + SDCI_SD_SAMP);
+
+		sdr_set_bits(host->base + SDCI_SOFTWARE, SDCI_SOFTWARE_SRST);
+		sdr_clr_bits(host->base + SDCI_SOFTWARE, SDCI_SOFTWARE_SRST);
+		while (!(readl(host->base + SDCI_STATUS) & SDCI_STATUS_IDIE))
+			cpu_relax();
+		dev_dbg(host->dev, "host->clk_rate: %ld, ios->clock: %d\n",
+			host->clk_rate, ios->clock);
+	}
+}
+
+
+static inline u32 phytium_sdci_cmd_find_resp(struct phytium_sdci_host *host,
+					     struct mmc_request *mrq,
+					     struct mmc_command *cmd)
+{
+	u32 resp;
+
+	switch (mmc_resp_type(cmd)) {
+	case MMC_RSP_R1:
+		resp = 0x2;
+		break;
+	case MMC_RSP_R1B:
+		resp = 0x2;
+		break;
+	case MMC_RSP_R2:
+		resp = 0x1;
+		break;
+	case MMC_RSP_R3:
+		resp = 0x3;
+		break;
+	case MMC_RSP_NONE:
+	default:
+		resp = 0x0;
+		break;
+	}
+
+	return resp;
+}
+
+static inline u32 phytium_sdci_cmd_prepare_raw_cmd(struct phytium_sdci_host *host,
+		struct mmc_request *mrq, struct mmc_command *cmd)
+{
+	/*
+	 * rawcmd :
+	 *   trty << 14 | opcode << 8 | cmdw << 6 | cice << 4 | crce << 3 | resp
+	 */
+	u32 resp, rawcmd;
+	u32 opcode = cmd->opcode;
+
+	resp = phytium_sdci_cmd_find_resp(host, mrq, cmd);
+	rawcmd = ((opcode << 8) | resp);
+
+	if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC)
+		rawcmd = (rawcmd | (SDCI_CMD_TYPE_ADTC << 14));
+
+	return rawcmd;
+}
+
+static void
+phytium_sdci_unexpected_error_handler(struct phytium_sdci_host *host,
+				       struct mmc_request *mrq,
+				       struct mmc_data *data,
+				       int err_type)
+{
+	unsigned long flags;
+	int error;
+
+	spin_lock_irqsave(&host->lock, flags);
+	host->mrq = NULL;
+	host->cmd = NULL;
+	host->data = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (err_type & ERR_CARD_ABSENT) {
+		host->mmc->detect_change = 1;
+		dev_dbg(host->dev, "SD is absent when send cmd:%d\n", mrq->cmd->opcode);
+	}
+
+	switch (err_type) {
+	case ERR_CARD_ABSENT:
+		error = -ENOMEDIUM;
+		break;
+	case ERR_TIMEOUT:
+		error = -ETIMEDOUT;
+		break;
+	case ERR_CMD_RESPONED:
+		error = -EIO;
+		break;
+	default:
+		error = -ETIMEDOUT;
+		break;
+	}
+
+	if (data) {
+		data->error = error;
+		phytium_sdci_unprepare_data(host, mrq);
+
+		if ((data->flags & MMC_DATA_READ) == MMC_DATA_READ ||
+		    (data->flags & MMC_DATA_WRITE) == MMC_DATA_WRITE)
+			phytium_sdci_data_xfer_done(host, SDCI_BD_ISR_TRS_R, mrq, data);
+	} else {
+		mrq->cmd->error = error;
+	}
+
+	mmc_request_done(host->mmc, mrq);
+}
+
+static bool phytium_sdci_start_data(struct phytium_sdci_host *host, struct mmc_request *mrq,
+			    struct mmc_command *cmd, struct mmc_data *data)
+{
+	bool read, res;
+	u32 sg_dma_addrh, sg_dma_addrl;
+	u32 sd_block_addrh, sd_block_addrl;
+	u32 temp, timeout, sd_status;
+	u32 block_cnt = 0;
+	u32 sd_block_addr = cmd->arg;
+	u32 private_cmd, resp_type, arg;
+	u32 j, dma_len;
+	unsigned long deadline_time;
+	dma_addr_t dma_address;
+	struct scatterlist *sg;
+	int ret;
+
+	WARN_ON(host->cmd);
+	host->cmd = cmd;
+
+	WARN_ON(host->data);
+	host->data = data;
+	read = data->flags & MMC_DATA_READ;
+
+	for_each_sg(data->sg, sg, data->sg_count, j) {
+		writel(0, host->base + SDCI_COMMAND);
+
+		dma_address = sg_dma_address(sg);
+		sg_dma_addrh = (u32) (dma_address >> 32);
+		sg_dma_addrl = (u32) dma_address;
+
+		dma_len = sg_dma_len(sg);
+		block_cnt = (dma_len / SD_BLOCK_SIZE);
+
+		sd_block_addrh = 0;
+		sd_block_addrl = sd_block_addr;
+
+		sdr_set_bits(host->base + SDCI_SOFTWARE, SDCI_SOFTWARE_BDRST);
+		sdr_clr_bits(host->base + SDCI_SOFTWARE, SDCI_SOFTWARE_BDRST);
+		writel(block_cnt, host->base + SDCI_BLK_CNT);
+
+		if ((mrq->data->flags & MMC_DATA_READ) == MMC_DATA_READ) {
+			writel(sg_dma_addrl, host->base + SDCI_BD_RX);
+			writel(sg_dma_addrh, host->base + SDCI_BD_RX);
+			writel(sd_block_addrl, host->base + SDCI_BD_RX);
+			writel(sd_block_addrh, host->base + SDCI_BD_RX);
+			timeout = 100 * block_cnt;
+		} else {
+			timeout = 250 * block_cnt;
+			ret = phytium_sdci_cmd13_process(host, mrq, data, timeout, 1);
+			if (ret != SDCI_CMD13_OK)
+				return false;
+
+			writel(sg_dma_addrl, host->base + SDCI_BD_TX);
+			writel(sg_dma_addrh, host->base + SDCI_BD_TX);
+			writel(sd_block_addrl, host->base + SDCI_BD_TX);
+			writel(sd_block_addrh, host->base + SDCI_BD_TX);
+		}
+
+		deadline_time = jiffies + msecs_to_jiffies(timeout);
+
+		temp = readl(host->base + SDCI_BD_ISR);
+		if ((mrq->data->flags & MMC_DATA_READ) == MMC_DATA_READ) {
+			while ((temp & SDCI_BD_ISR_TRS_R) != SDCI_BD_ISR_TRS_R) {
+				sd_status = readl(host->base + SDCI_STATUS);
+				if (sd_status & SDCI_STATUS_CDSL) {
+					phytium_sdci_unexpected_error_handler(host, mrq, data,
+									      ERR_CARD_ABSENT);
+					if (temp & SDCI_BD_ISR_DAIS)
+						writel(1, host->base + SDCI_BD_ISR);
+					return false;
+				}
+
+				temp = readl(host->base + SDCI_BD_ISR);
+				if (time_after(jiffies, deadline_time)) {
+					phytium_sdci_unexpected_error_handler(host, mrq, data,
+									      ERR_TIMEOUT);
+					dev_err(host->dev,
+						"Read Data timeout:jiffies:0x%lx,dt_jiffies: 0x%lx, BD_isr_reg:0x%x,cmd:%d, REG_D0:0x%x\n",
+						jiffies, jiffies - deadline_time, temp,
+						cmd->opcode, readl(host->base + SDCI_STATUS));
+
+					return false;
+				}
+			}
+		} else {
+			while ((temp & SDCI_BD_ISR_TRS_W) != SDCI_BD_ISR_TRS_W) {
+				sd_status = readl(host->base + SDCI_STATUS);
+				if (sd_status & SDCI_STATUS_CDSL) {
+					phytium_sdci_unexpected_error_handler(host, mrq, data,
+									      ERR_CARD_ABSENT);
+					dev_err(host->dev, "[%s][%d]: Card absent ! cmd(%d)\n",
+						__func__, __LINE__, mrq->cmd->opcode);
+					return false;
+				}
+
+				temp = readl(host->base + SDCI_BD_ISR);
+				if (time_after(jiffies, deadline_time)) {
+					phytium_sdci_unexpected_error_handler(host, mrq, data,
+									      ERR_TIMEOUT);
+					dev_err(host->dev,
+						"Write Date timeout: jiffies:0x%lx,dt_jiffies: 0x%lx,BD_isr_reg:0x%x\n",
+						jiffies, jiffies - deadline_time, temp);
+					return false;
+				}
+			}
+		}
+		writel(1, host->base + SDCI_BD_ISR);
+		writel(1, host->base + SDCI_NORMAL_ISR);
+		sd_block_addr = sd_block_addr + block_cnt;
+
+		if (j < (data->sg_count - 1) && 1 < block_cnt) {
+			private_cmd = MMC_STOP_TRANSMISSION;
+			resp_type = 0x2;
+			arg = 0;
+			res = phytium_sdci_private_send_cmd(host, private_cmd,
+							    resp_type, arg);
+			if (!res) {
+				sd_status = readl(host->base + SDCI_STATUS);
+				if (sd_status & SDCI_STATUS_CDSL) {
+					phytium_sdci_unexpected_error_handler(host, mrq, data,
+									      ERR_CARD_ABSENT);
+					writel(1, host->base + SDCI_BD_ISR);
+					dev_err(host->dev,
+						"[%s][%d]:Card absent ! private_cmd(%d)\n",
+						__func__, __LINE__, private_cmd);
+				} else {
+					phytium_sdci_unexpected_error_handler(host, mrq, data,
+									      ERR_CMD_RESPONED);
+					dev_err(host->dev,
+						"[%s][%d] cmd(%d) response errored\n",
+						__func__, __LINE__, mrq->cmd->opcode);
+					phytium_sd_error(host);
+				}
+				writel(1, host->base + SDCI_NORMAL_ISR);
+				return false;
+			}
+			writel(1, host->base + SDCI_NORMAL_ISR);
+		}
+	}
+
+	host->is_multi_rw_only_one_blkcnt = false;
+
+	if ((cmd->opcode == MMC_READ_MULTIPLE_BLOCK && block_cnt == 1) ||
+	    (cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK && block_cnt == 1))
+		host->is_multi_rw_only_one_blkcnt = true;
+
+	phytium_sdci_cmd_done(host, SDCI_NORMAL_ISR_CC, mrq, cmd);
+	if ((mrq->data->flags & MMC_DATA_READ) == MMC_DATA_READ)
+		phytium_sdci_data_xfer_done(host, SDCI_BD_ISR_TRS_R,
+					    mrq, data);
+	else
+		phytium_sdci_data_xfer_done(host, SDCI_BD_ISR_TRS_W,
+					    mrq, data);
+
+	return true;
+}
+
+static int phytium_sdci_auto_cmd_done(struct phytium_sdci_host *host,
+				      int events, struct mmc_command *cmd)
+{
+	u32 *rsp = cmd->resp;
+
+	rsp[0] = readl(host->base + SDCI_RESP0);
+
+	if (events & SDCI_NORMAL_ISR_CC)
+		cmd->error = 0;
+	else {
+		phytium_sdci_reset_hw(host);
+		dev_err(host->dev,
+			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
+			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
+	}
+
+	return cmd->error;
+}
+
+static void phytium_sdci_track_cmd_data(struct phytium_sdci_host *host,
+					struct mmc_command *cmd,
+					struct mmc_data *data)
+{
+	if (host->error)
+		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
+			__func__, cmd->opcode, cmd->arg, host->error);
+}
+
+static void phytium_sdci_request_done(struct phytium_sdci_host *host,
+				      struct mmc_request *mrq)
+{
+	unsigned long flags;
+
+	dev_dbg(host->dev,
+		"%s_%d:mrq->cmd->opcode:%d, mrq->cmd->arg:0x%x resp 0x%x 0x%x 0x%x 0x%x\n",
+		__func__, __LINE__, mrq->cmd->opcode, mrq->cmd->arg,
+		mrq->cmd->resp[0], mrq->cmd->resp[1], mrq->cmd->resp[2],
+		mrq->cmd->resp[3]);
+
+	spin_lock_irqsave(&host->lock, flags);
+	host->mrq = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	phytium_sdci_track_cmd_data(host, mrq->cmd, mrq->data);
+	if (mrq->data)
+		phytium_sdci_unprepare_data(host, mrq);
+	mmc_request_done(host->mmc, mrq);
+}
+
+static bool
+phytium_sdci_auto_command_done(struct phytium_sdci_host *host, int events,
+			       struct mmc_request *mrq, struct mmc_command *cmd)
+{
+	u32 *rsp = cmd->resp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&host->lock, flags);
+	host->cmd = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	sdr_clr_bits(host->base + SDCI_NORMAL_ISER, cmd_ints_mask);
+
+	rsp[0] = 0x900;
+	phytium_sdci_request_done(host, mrq);
+	return true;
+}
+
+/* returns true if command is fully handled; returns false otherwise */
+static bool phytium_sdci_cmd_done(struct phytium_sdci_host *host, int events,
+				  struct mmc_request *mrq,
+				  struct mmc_command *cmd)
+{
+	bool done = false;
+	bool sbc_error;
+	unsigned long flags;
+	u32 *rsp = cmd->resp;
+
+	if (mrq->sbc && cmd == mrq->cmd &&
+	    (events & SDCI_NORMAL_ISR_CC))
+		phytium_sdci_auto_cmd_done(host, events, mrq->sbc);
+
+	sbc_error = mrq->sbc && mrq->sbc->error;
+
+	if (!sbc_error && !(events & (SDCI_NORMAL_ISR_CC |
+				      SDCI_NORMAL_ISR_CR |
+				      SDCI_NORMAL_ISR_TIMEOUT)))
+		return done;
+
+	spin_lock_irqsave(&host->lock, flags);
+	done = !host->cmd;
+	host->cmd = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (done)
+		return true;
+
+	sdr_clr_bits(host->base + SDCI_NORMAL_ISER, cmd_ints_mask);
+
+	if (cmd->flags & MMC_RSP_PRESENT) {
+		if (cmd->flags & MMC_RSP_136) {
+			rsp[0] = readl(host->base + SDCI_RESP0);
+			rsp[1] = readl(host->base + SDCI_RESP1);
+			rsp[2] = readl(host->base + SDCI_RESP2);
+			rsp[3] = readl(host->base + SDCI_RESP3);
+		} else
+			rsp[0] = readl(host->base + SDCI_RESP0);
+
+		if (cmd->opcode == SD_SEND_RELATIVE_ADDR)
+			host->current_rca = rsp[0] & 0xFFFF0000;
+	}
+
+	if (!sbc_error &&
+	    !(events & SDCI_NORMAL_ISR_CC) &&
+	    (events & SDCI_NORMAL_ISR_TIMEOUT))
+		cmd->error = -ETIMEDOUT;
+
+	if (cmd->error)
+		dev_dbg(host->dev,
+			"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
+			__func__, cmd->opcode, cmd->arg, rsp[0],
+			cmd->error);
+
+	phytium_sdci_cmd_next(host, mrq, cmd);
+
+	return true;
+}
+
+static bool set_databus_width(struct phytium_sdci_host *host)
+{
+	bool res;
+	u32 cmd, resp_type, arg;
+
+	cmd = SD_APP_SET_BUS_WIDTH;
+	resp_type = 0x2;
+	arg = 0x2;
+	res = phytium_sdci_private_send_cmd(host, cmd, resp_type, arg);
+	if (!res)
+		return false;
+
+	cmd = MMC_APP_CMD;
+	resp_type = 0x2;
+	arg = host->current_rca;
+	res = phytium_sdci_private_send_cmd(host, cmd, resp_type, arg);
+	if (!res)
+		return false;
+
+	return true;
+}
+
+
+static void phytium_sdci_start_command(struct phytium_sdci_host *host,
+				       struct mmc_request *mrq,
+				       struct mmc_command *cmd)
+{
+	u32 rawcmd;
+	struct mmc_data *data = mrq->data;
+	dma_addr_t dma_adtc_buf;
+	u32 dma_bufh, dma_bufl, block_cnt = 0;
+
+	WARN_ON(host->cmd);
+	host->cmd = cmd;
+
+	cmd->error = 0;
+	rawcmd = phytium_sdci_cmd_prepare_raw_cmd(host, mrq, cmd);
+	if (cmd->opcode == MMC_STOP_TRANSMISSION ||
+	    cmd->opcode == MMC_SEND_STATUS)
+		writel(1, host->base + SDCI_ERROR_ISR);
+	sdr_set_bits(host->base + SDCI_NORMAL_ISER, cmd_ints_mask);
+	writel(rawcmd, host->base + SDCI_COMMAND);
+
+	if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
+		WARN_ON(host->data);
+		host->data = data;
+
+		dma_adtc_buf = host->dma_rx.bd_addr;
+		dma_bufh = (u32) (dma_adtc_buf >> 32);
+		dma_bufl = (u32) dma_adtc_buf;
+		block_cnt = mrq->data->blocks;
+		sdr_set_bits(host->base + SDCI_BD_ISER, data_ints_mask);
+		writel(block_cnt, host->base + SDCI_BLK_CNT);
+
+		if ((mrq->data->flags & MMC_DATA_READ) == MMC_DATA_READ) {
+			writel(dma_bufl, host->base + SDCI_BD_RX);
+			writel(dma_bufh, host->base + SDCI_BD_RX);
+			writel(cmd->arg, host->base + SDCI_BD_RX);
+			writel(0, host->base + SDCI_BD_RX);
+		} else {
+			writel(dma_bufl, host->base + SDCI_BD_TX);
+			writel(dma_bufh, host->base + SDCI_BD_TX);
+			writel(cmd->arg, host->base + SDCI_BD_TX);
+			writel(0, host->base + SDCI_BD_TX);
+		}
+	} else {
+		writel(cmd->arg, host->base + SDCI_ARGUMENT);
+	}
+}
+
+static void phytium_sdci_cmd_next(struct phytium_sdci_host *host,
+				  struct mmc_request *mrq,
+				  struct mmc_command *cmd)
+{
+	if (cmd->error || (mrq->sbc && mrq->sbc->error))
+		phytium_sdci_request_done(host, mrq);
+	else if (cmd == mrq->sbc)
+		phytium_sdci_start_command(host, mrq, mrq->cmd);
+	else if (!cmd->data)
+		phytium_sdci_request_done(host, mrq);
+}
+
+static int phytium_sdci_cmd13_process(struct phytium_sdci_host *host,
+				       struct mmc_request *mrq,
+				       struct mmc_data *data,
+				       u32 wait_timeout_ms,
+				       u32 send_once_time_ms)
+{
+	u32 private_cmd, resp_type, arg, temp, sd_status;
+	unsigned long deadline_time;
+	bool res;
+
+	deadline_time = jiffies + msecs_to_jiffies(wait_timeout_ms);
+
+	do {
+		private_cmd = MMC_SEND_STATUS;
+		resp_type = 0x2;
+		arg = host->current_rca;
+
+		res = phytium_sdci_private_send_cmd(host, private_cmd, resp_type, arg);
+		if (!res) {
+			sd_status = readl(host->base + SDCI_STATUS);
+			if (sd_status & SDCI_STATUS_CDSL) {
+				phytium_sdci_unexpected_error_handler(host, mrq, data,
+								      ERR_CARD_ABSENT);
+				dev_err(host->dev,
+					"[%s][%d] Card absent! private_cmd(%d)\n",
+					__func__, __LINE__, private_cmd);
+			} else {
+				phytium_sdci_unexpected_error_handler(host, mrq, data,
+								      ERR_CMD_RESPONED);
+
+				dev_err(host->dev,
+					"[%s][%d] private_cmd(%d) response errored\n",
+					__func__, __LINE__, private_cmd);
+				phytium_sd_error(host);
+			}
+			writel(1, host->base + SDCI_BD_ISR);
+			return SDCI_CMD13_FAILED;
+		}
+
+		temp = readl(host->base + SDCI_RESP0);
+
+		if (time_after(jiffies, deadline_time)) {
+
+			if (mrq->cmd->opcode == MMC_SEND_STATUS)
+				return SDCI_CMD13_OK;
+
+			dev_err(host->dev,
+				"SD card is not in transfer mode,timeout:%d,rsp[0]:%x\n",
+				wait_timeout_ms, temp);
+
+			phytium_sdci_unexpected_error_handler(host, mrq, data,
+							      ERR_TIMEOUT);
+			phytium_sd_error(host);
+			return SDCI_CMD13_FAILED;
+		}
+
+		writel(1, host->base + SDCI_NORMAL_ISR);
+
+		if (CARD_TRAN_STATE != (temp & CARD_CURRENT_STATE) && send_once_time_ms)
+			mdelay(send_once_time_ms);
+
+	} while (CARD_TRAN_STATE != (temp & CARD_CURRENT_STATE));
+
+	return SDCI_CMD13_OK;
+}
+
+static void phytium_sdci_ops_request(struct mmc_host *mmc,
+				     struct mmc_request *mrq)
+{
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+	unsigned long flags;
+	bool res;
+	u32 status_sd;
+	int res_cmd13;
+
+	host->error = 0;
+	WARN_ON(host->mrq);
+	host->mrq = mrq;
+
+	dev_dbg(host->dev, "%s: mrq->cmd->opcode: %d, mrq->cmd->arg: 0x%x\n",
+		__func__, mrq->cmd->opcode, mrq->cmd->arg);
+
+	if (mrq->cmd->opcode == MMC_SEND_STATUS &&
+	    (mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_ADTC) {
+		u32 status = readl(host->base + SDCI_STATUS);
+
+		if (status & SDCI_STATUS_CDSL) {
+			phytium_sdci_unexpected_error_handler(host, mrq, NULL,
+							      ERR_CARD_ABSENT);
+			return;
+		}
+
+		res_cmd13 = phytium_sdci_cmd13_process(host, mrq, NULL, 400, 5);
+		if (res_cmd13 == SDCI_CMD13_FAILED)
+			return;
+	} else if (mrq->cmd->opcode == MMC_STOP_TRANSMISSION) {
+		status_sd = readl(host->base + SDCI_STATUS);
+		if (status_sd & SDCI_STATUS_CDSL) {
+			phytium_sdci_unexpected_error_handler(host, mrq, NULL,
+							      ERR_CARD_ABSENT);
+			return;
+		}
+	}
+
+	if (mrq->data) {
+		phytium_sdci_prepare_data(host, mrq);
+		if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
+		    mrq->cmd->opcode == MMC_READ_SINGLE_BLOCK ||
+		    mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
+		    mrq->cmd->opcode == MMC_WRITE_BLOCK) {
+			host->adtc_type = BLOCK_RW_ADTC;
+			phytium_sdci_start_data(host, mrq,
+						mrq->cmd, mrq->data);
+			return;
+		}
+		host->adtc_type = COMMOM_ADTC;
+	}
+
+	if (mrq->cmd->opcode == SD_IO_RW_DIRECT ||
+	    mrq->cmd->opcode == SD_IO_SEND_OP_COND) {
+		spin_lock_irqsave(&host->lock, flags);
+		host->mrq = NULL;
+		host->cmd = NULL;
+		spin_unlock_irqrestore(&host->lock, flags);
+		mrq->cmd->error = -EINVAL;
+		mmc_request_done(host->mmc, mrq);
+
+		return;
+	}
+
+	if (mrq->cmd->opcode == SD_APP_SEND_SCR) {
+		res = set_databus_width(host);
+		if (!res) {
+			phytium_sdci_unexpected_error_handler(host, mrq, NULL, ERR_CMD_RESPONED);
+			return;
+		}
+	}
+
+	/* if SBC is required, we have HW option and SW option.
+	 * if HW option is enabled, and SBC does not have "special" flags,
+	 * use HW option,  otherwise use SW option
+	 */
+	if (mrq->sbc &&
+	    (!mmc_card_mmc(mmc->card) || (mrq->sbc->arg & 0xFFFF0000)))
+		phytium_sdci_start_command(host, mrq, mrq->sbc);
+	else
+		phytium_sdci_start_command(host, mrq, mrq->cmd);
+}
+
+static void phytium_sdci_data_xfer_next(struct phytium_sdci_host *host,
+					struct mmc_request *mrq,
+					struct mmc_data *data)
+{
+	if (mmc_op_multi(mrq->cmd->opcode) &&
+	    mrq->stop && !mrq->stop->error &&
+	    !mrq->sbc && host->is_multi_rw_only_one_blkcnt) {
+		host->is_multi_rw_only_one_blkcnt = false;
+		phytium_sdci_auto_command_done(host, SDCI_NORMAL_ISR_CC, mrq, mrq->stop);
+	} else if (mmc_op_multi(mrq->cmd->opcode) &&
+		   mrq->stop && !mrq->stop->error &&
+		   !mrq->sbc)
+		phytium_sdci_start_command(host, mrq, mrq->stop);
+	else
+		phytium_sdci_request_done(host, mrq);
+}
+
+static inline void get_data_buffer(struct mmc_data *data,
+				   u32 *bytes, u32 **pointer)
+{
+	struct scatterlist *sg;
+
+	sg = &data->sg[0];
+	*bytes = sg->length;
+	*pointer = sg_virt(sg);
+}
+
+static bool phytium_sdci_data_xfer_done(struct phytium_sdci_host *host,
+					u32 events, struct mmc_request *mrq,
+					struct mmc_data *data)
+{
+	struct mmc_command *stop = data->stop;
+	unsigned long flags;
+	bool done;
+	unsigned int check_data;
+	u32 sg_length, i;
+	u32 *sg_virt_addr;
+
+	check_data = events & (SDCI_BD_ISR_TRS_R | SDCI_BD_ISR_TRS_W | SDCI_BD_ISR_EDTE);
+
+	spin_lock_irqsave(&host->lock, flags);
+	done = !host->data;
+	if (check_data)
+		host->data = NULL;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (done)
+		return true;
+
+	if (check_data || (stop && stop->error)) {
+		sdr_clr_bits(host->base + SDCI_BD_ISER, data_ints_mask);
+		dev_dbg(host->dev, "DMA stop\n");
+
+		if (((events & SDCI_BD_ISR_TRS_R) ||
+		     (events & SDCI_BD_ISR_TRS_W)) &&
+		     (!stop || !stop->error)) {
+			if ((mrq->cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC &&
+			    (host->adtc_type == COMMOM_ADTC)) {
+				get_data_buffer(data, &sg_length,
+						&host->sg_virt_addr);
+				sg_virt_addr = host->sg_virt_addr;
+
+				for (i = 0; i < (sg_length/4); i++) {
+					*sg_virt_addr = host->dma_rx.buf[i];
+					sg_virt_addr++;
+				}
+			}
+			data->bytes_xfered = data->blocks * data->blksz;
+		} else {
+			dev_dbg(host->dev, "interrupt events: %x\n", events);
+			phytium_sdci_reset_hw(host);
+			data->bytes_xfered = 0;
+			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
+				__func__, mrq->cmd->opcode, data->blocks);
+			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
+				(int)data->error, data->bytes_xfered);
+		}
+
+		phytium_sdci_data_xfer_next(host, mrq, data);
+		done = true;
+	}
+
+	return done;
+}
+
+
+static int phytium_sdci_card_busy(struct mmc_host *mmc)
+{
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+	u32 status;
+
+	/* check if any pin between dat[0:3] is low */
+	status = readl(host->base + SDCI_STATUS);
+	if (((status >> 20) & 0xf) != 0xf)
+		return 1;
+
+	return 0;
+}
+
+static void phytium_sdci_request_timeout(struct work_struct *work)
+{
+	struct phytium_sdci_host *host;
+
+	host = container_of(work, struct phytium_sdci_host, req_timeout.work);
+	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
+	if (host->mrq) {
+		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
+			host->mrq, host->mrq->cmd->opcode);
+		if (host->cmd) {
+			dev_err(host->dev, "%s: aborting cmd=%d\n",
+				__func__, host->cmd->opcode);
+			phytium_sdci_cmd_done(host, SDCI_NORMAL_ISR_TIMEOUT,
+					      host->mrq, host->cmd);
+		} else if (host->data) {
+			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
+				__func__, host->mrq->cmd->opcode,
+				host->data->blocks);
+			phytium_sdci_data_xfer_done(host, SDCI_BD_ISR_EDTE,
+						    host->mrq, host->data);
+		}
+	}
+}
+
+static void hotplug_timer_func(struct timer_list *t)
+{
+	struct phytium_sdci_host *host;
+	u32 status;
+
+	host = from_timer(host, t, hotplug_timer);
+	if (!host)
+		dev_err(host->dev, "%s: Not find host!\n", __func__);
+	status = readl(host->base + SDCI_STATUS);
+
+	if (status & SDCI_STATUS_CDSL) { /* card absent */
+		if (host->mmc->card) {
+			cancel_delayed_work(&host->mmc->detect);
+			mmc_detect_change(host->mmc,
+					msecs_to_jiffies(100));
+		}
+	} else { /* card insert */
+		cancel_delayed_work(&host->mmc->detect);
+		mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+	}
+}
+
+static irqreturn_t phytium_sdci_irq(int irq, void *dev_id)
+{
+	struct phytium_sdci_host *host = (struct phytium_sdci_host *) dev_id;
+	unsigned long flags;
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	u32 events;
+
+	if (!host)
+		return IRQ_NONE;
+
+	spin_lock_irqsave(&host->lock, flags);
+	events = readl(host->base + SDCI_NORMAL_ISR);
+	/* clear interrupts */
+	writel(1, host->base + SDCI_NORMAL_ISR);
+
+	mrq = host->mrq;
+	cmd = host->cmd;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (events & (SDCI_NORMAL_ISR_CR | SDCI_NORMAL_ISR_CI)) {
+		mod_timer(&host->hotplug_timer,
+			  jiffies + usecs_to_jiffies(30000));
+		goto irq_out;
+	}
+
+	if (!(events & cmd_ints_mask))
+		goto irq_out;
+
+	if (!mrq) {
+		dev_err(host->dev, "%s: MRQ=NULL; events=%08X\n",
+			__func__, events);
+		WARN_ON(1);
+		goto irq_out;
+	}
+
+	dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
+
+	if (cmd)
+		phytium_sdci_cmd_done(host, events, mrq, cmd);
+
+irq_out:
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t phytium_sdci_dma_irq(int irq, void *dev_id)
+{
+	struct phytium_sdci_host *host = (struct phytium_sdci_host *) dev_id;
+	unsigned long flags;
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+	u32 events;
+
+	spin_lock_irqsave(&host->lock, flags);
+	events = readl(host->base + SDCI_BD_ISR);
+	writel(1, host->base + SDCI_BD_ISR);
+
+	mrq = host->mrq;
+	cmd = host->cmd;
+	data = host->data;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (!(events & data_ints_mask))
+		goto dma_irq_out;
+
+	if (!mrq) {
+		dev_err(host->dev,
+			"%s: MRQ=NULL; events=%08X\n",
+			__func__, events);
+		goto dma_irq_out;
+	}
+
+	dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
+
+	if (data)
+		phytium_sdci_data_xfer_done(host, events, mrq, data);
+
+dma_irq_out:
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t phytium_sdci_err_irq(int irq, void *dev_id)
+{
+	struct phytium_sdci_host *host = (struct phytium_sdci_host *) dev_id;
+	unsigned long flags;
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+	u32 events;
+
+	if (!host)
+		return IRQ_NONE;
+
+	spin_lock_irqsave(&host->lock, flags);
+	events = readl(host->base + SDCI_ERROR_ISR);
+	mrq = host->mrq;
+	cmd = host->cmd;
+	data = host->data;
+	spin_unlock_irqrestore(&host->lock, flags);
+
+	if (!(events&err_ints_mask))
+		goto err_irq_out;
+
+	if (!mrq) {
+		sdr_clr_bits(host->base + SDCI_NORMAL_ISER, SDCI_NORMAL_ISR_EI);
+		writel(1, host->base + SDCI_ERROR_ISR);
+		dev_err(host->dev, "%s: MRQ=NULL; events=%08X\n", __func__, events);
+		goto err_irq_out;
+	}
+	sdr_clr_bits(host->base + SDCI_NORMAL_ISER, SDCI_NORMAL_ISR_EI);
+	if (data) {
+		dev_err(host->dev,
+			"[%s][%d]:  cmd(%d); %d read blocks, status:%x,flag:%x\n",
+			__func__, __LINE__, mrq->cmd->opcode, data->blocks, events, data->flags);
+		data->error = -ETIMEDOUT;
+		if ((data->flags & MMC_DATA_READ) == MMC_DATA_READ ||
+		    (data->flags & MMC_DATA_WRITE) == MMC_DATA_WRITE)
+			phytium_sdci_data_xfer_done(host, SDCI_BD_ISR_EDTE | SDCI_BD_ISR_TRS_R,
+						    mrq, data);
+		mrq->cmd->error = -ETIMEDOUT;
+		mmc_request_done(host->mmc, mrq);
+	} else if (cmd) {
+		phytium_sdci_cmd_done(host, SDCI_NORMAL_ISR_TIMEOUT, mrq, cmd);
+	}
+
+	writel(1, host->base + SDCI_NORMAL_ISR);
+	writel(1, host->base + SDCI_ERROR_ISR);
+err_irq_out:
+	return IRQ_HANDLED;
+}
+
+static void phytium_sdci_init_hw(struct phytium_sdci_host *host)
+{
+	u32 val;
+
+	/* Reset */
+	phytium_sdci_reset_hw(host);
+
+	val = SDCI_SEN_CREFR_VAL | SDCI_SEN_DEBNCE_VAL;
+	writel(val, host->base + SDCI_SD_SEN);
+
+	/* Disable and clear all interrupts */
+	writel(0, host->base + SDCI_NORMAL_ISER);
+	writel(0, host->base + SDCI_ERROR_ISER);
+	writel(0, host->base + SDCI_BD_ISER);
+
+	writel(1, host->base + SDCI_NORMAL_ISR);
+	writel(1, host->base + SDCI_ERROR_ISR);
+	writel(1, host->base + SDCI_BD_ISR);
+
+	sdr_set_bits(host->base + SDCI_NORMAL_ISER,
+		     SDCI_SDCI_NORMAL_ISER_ECI|SDCI_SDCI_NORMAL_ISER_ECR);
+	/* Configure default cmd timeout to 0.1(s)s = val/25M */
+	val = SDCI_F_MAX / 10;
+	writel(val, host->base + SDCI_TIMEOUT_CMD);
+	writel(SDCI_TIMEOUT_DATA_VALUE, host->base + SDCI_TIMEOUT_DATA);
+
+	val = 0x0F00;
+	writel(val, host->base + SDCI_CONTROLLER);
+
+	dev_dbg(host->dev, "init hardware done!");
+}
+
+static void phytium_sdci_deinit_hw(struct phytium_sdci_host *host)
+{
+	/* Disable and clear all interrupts */
+	writel(0, host->base + SDCI_NORMAL_ISER);
+	writel(0, host->base + SDCI_ERROR_ISER);
+	writel(0, host->base + SDCI_BD_ISER);
+
+	writel(0, host->base + SDCI_NORMAL_ISR);
+	writel(0, host->base + SDCI_ERROR_ISR);
+	writel(0, host->base + SDCI_BD_ISR);
+}
+
+static void phytium_sdci_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+
+	if (ios->bus_width == MMC_BUS_WIDTH_4)
+		mmc->caps = mmc->caps & (~MMC_CAP_4_BIT_DATA);
+
+	/* Suspend/Resume will do power off/on */
+	switch (ios->power_mode) {
+	case MMC_POWER_UP:
+		writel(SDCI_POWER_ON, host->base + SDCI_POWER);
+		break;
+	case MMC_POWER_ON:
+		phytium_sdci_set_clk(host, ios);
+		break;
+	case MMC_POWER_OFF:
+		writel(SDCI_POWER_OFF, host->base + SDCI_POWER);
+		break;
+	default:
+		break;
+	}
+}
+
+static int phytium_sdci_get_cd(struct mmc_host *mmc)
+{
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+	u32 status = readl(host->base + SDCI_STATUS);
+
+	if (((status >> 19) & 0x1) == 0x1)
+		return 0;
+
+	return 1;
+}
+
+static void phytium_sdci_hw_reset(struct mmc_host *mmc)
+{
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+
+	sdr_set_bits(host->base + SDCI_SOFTWARE, SDCI_SOFTWARE_SRST);
+	sdr_clr_bits(host->base + SDCI_SOFTWARE, SDCI_SOFTWARE_SRST);
+	while (!(readl(host->base + SDCI_STATUS) & SDCI_STATUS_IDIE))
+		cpu_relax();
+}
+
+static struct mmc_host_ops phytium_sdci_ops = {
+	.request = phytium_sdci_ops_request,
+	.set_ios = phytium_sdci_ops_set_ios,
+	.get_cd = phytium_sdci_get_cd,
+	.card_busy = phytium_sdci_card_busy,
+	.hw_reset = phytium_sdci_hw_reset,
+};
+
+static bool phytium_sdci_private_send_cmd(struct phytium_sdci_host *host,
+					  u32 cmd, u32 resp_type, u32 arg)
+{
+	u32 temp, sd_cmd, sd_arg, sd_status;
+	unsigned long deadline_time;
+
+	writel(1, host->base + SDCI_NORMAL_ISR);
+	writel(1, host->base + SDCI_ERROR_ISR);
+
+	sd_cmd = (cmd << 8) | resp_type;
+	sd_arg = arg;
+	writel(sd_cmd, host->base + SDCI_COMMAND);
+	writel(sd_arg, host->base + SDCI_ARGUMENT);
+
+	if (cmd == MMC_STOP_TRANSMISSION)
+		deadline_time = jiffies + msecs_to_jiffies(1000);
+	else
+		deadline_time = jiffies + msecs_to_jiffies(100);
+
+	temp = readl(host->base + SDCI_NORMAL_ISR);
+	while ((temp & SDCI_NORMAL_ISR_CC) != SDCI_NORMAL_ISR_CC) {
+		sd_status = readl(host->base + SDCI_STATUS);
+		if (sd_status & SDCI_STATUS_CDSL)
+			return false;
+
+		temp = readl(host->base + SDCI_NORMAL_ISR);
+		if (time_after(jiffies, deadline_time))
+			return false;
+
+		if (cmd == MMC_STOP_TRANSMISSION)
+			mdelay(1);
+	}
+
+	return true;
+}
+
+static int phytium_sdci_probe(struct platform_device *pdev)
+{
+	struct mmc_host *mmc;
+	struct phytium_sdci_host *host;
+	struct resource *res;
+	int ret;
+	const struct acpi_device_id *match;
+	struct device *dev = &pdev->dev;
+
+	/* Allocate MMC host for this device */
+	mmc = mmc_alloc_host(sizeof(struct phytium_sdci_host), &pdev->dev);
+	if (!mmc)
+		return -ENOMEM;
+
+	host = mmc_priv(mmc);
+	ret = mmc_of_parse(mmc);
+	if (ret)
+		goto host_free;
+
+	if (dev->of_node) {
+		host->src_clk = devm_clk_get(&pdev->dev, "phytium_sdc_clk");
+		if (IS_ERR(host->src_clk)) {
+			ret = PTR_ERR(host->src_clk);
+			goto host_free;
+		}
+
+		host->clk_rate = clk_get_rate(host->src_clk);
+		if (device_property_read_bool(dev, "no-dma-coherent"))
+			dev->dma_coherent = false;
+	} else if (has_acpi_companion(dev)) {
+		match = acpi_match_device(dev->driver->acpi_match_table, dev);
+		if (!match) {
+			dev_err(dev, "Error ACPI match data is missing\n");
+			return -ENODEV;
+		}
+
+		acpi_dma_configure(dev, DEV_DMA_NOT_SUPPORTED);
+
+		host->clk_rate = 600000000;
+	} else {
+		dev_err(&pdev->dev, "No DT found\n");
+		return -EINVAL;
+	}
+
+	dma_set_mask(dev, DMA_BIT_MASK(40));
+	dma_set_coherent_mask(dev, DMA_BIT_MASK(40));
+
+	timer_setup(&host->hotplug_timer, hotplug_timer_func, 0);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	host->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(host->base)) {
+		ret = PTR_ERR(host->base);
+		goto host_free;
+	}
+
+	host->irq = platform_get_irq(pdev, 1);
+	if (host->irq < 0) {
+		ret = -EINVAL;
+		goto host_free;
+	}
+
+	host->irq_err = platform_get_irq(pdev, 2);
+	if (host->irq_err < 0) {
+		ret = -EINVAL;
+		goto host_free;
+	}
+
+	host->irq_bd = platform_get_irq(pdev, 0);
+	if (host->irq_bd < 0) {
+		ret = -EINVAL;
+		goto host_free;
+	}
+
+	host->dev = &pdev->dev;
+	host->mmc = mmc;
+
+	if ((4 * SDCI_F_MAX) > host->clk_rate)
+		host->clk_div	= 1;
+	else
+		host->clk_div	= ((host->clk_rate / (2 * SDCI_F_MAX)) - 1);
+
+	/* Set host parameters to mmc */
+	mmc->f_min = SDCI_F_MIN;
+	mmc->f_max = (host->clk_rate / ((host->clk_div + 1) * 2));
+	mmc->ops = &phytium_sdci_ops;
+	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	mmc->caps |= host->caps;
+	/* MMC core transfer sizes tunable parameters */
+	mmc->max_segs = MAX_BD_NUM;
+	mmc->max_seg_size = 512 * 1024;
+	mmc->max_blk_size = 512;
+	mmc->max_req_size = 512 * 1024;
+	mmc->max_blk_count = mmc->max_req_size / 512;
+
+	host->dma_rx.buf = dma_alloc_coherent(&pdev->dev,
+					       MAX_BD_NUM,
+					       &host->dma_rx.bd_addr,
+					       GFP_KERNEL);
+	if (!host->dma_rx.buf) {
+		ret = -ENOMEM;
+		goto release_mem;
+	}
+
+	host->cmd_timeout = msecs_to_jiffies(100);
+	host->data_timeout = msecs_to_jiffies(250);
+
+	INIT_DELAYED_WORK(&host->req_timeout, phytium_sdci_request_timeout);
+	spin_lock_init(&host->lock);
+
+	platform_set_drvdata(pdev, mmc);
+	phytium_sdci_init_hw(host);
+
+	ret = devm_request_irq(&pdev->dev, host->irq, phytium_sdci_irq,
+			       IRQF_SHARED, pdev->name, host);
+	if (ret)
+		goto release;
+
+	ret = devm_request_irq(&pdev->dev, host->irq_err, phytium_sdci_err_irq,
+			       IRQF_SHARED, pdev->name, host);
+	if (ret)
+		goto release;
+
+	ret = devm_request_irq(&pdev->dev, host->irq_bd, phytium_sdci_dma_irq,
+			       IRQF_SHARED, pdev->name, host);
+	if (ret)
+		goto release;
+
+	ret = mmc_add_host(mmc);
+	if (ret)
+		goto release;
+
+	return 0;
+
+release:
+	platform_set_drvdata(pdev, NULL);
+	phytium_sdci_deinit_hw(host);
+release_mem:
+	if (host->dma_rx.buf)
+		dma_free_coherent(&pdev->dev, MAX_BD_NUM,
+				  host->dma_rx.buf,
+				  host->dma_rx.bd_addr);
+host_free:
+	mmc_free_host(mmc);
+
+	return ret;
+}
+
+static int phytium_sdci_remove(struct platform_device *pdev)
+{
+	struct mmc_host *mmc;
+	struct phytium_sdci_host *host;
+
+	mmc = platform_get_drvdata(pdev);
+	host = mmc_priv(mmc);
+
+	cancel_delayed_work_sync(&host->req_timeout);
+	platform_set_drvdata(pdev, NULL);
+	mmc_remove_host(host->mmc);
+	phytium_sdci_deinit_hw(host);
+
+	if (host->dma_rx.buf)
+		dma_free_coherent(&pdev->dev, MAX_BD_NUM,
+				  host->dma_rx.buf, host->dma_rx.bd_addr);
+
+	mmc_free_host(host->mmc);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_sdci_suspend(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+
+	phytium_sdci_deinit_hw(host);
+	return 0;
+}
+
+static int phytium_sdci_resume(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+
+	phytium_sdci_init_hw(host);
+	mmc->caps = mmc->caps | MMC_CAP_4_BIT_DATA;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PM
+static int phytium_sdci_runtime_suspend(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+
+	phytium_sdci_deinit_hw(host);
+
+	return 0;
+}
+
+static int phytium_sdci_runtime_resume(struct device *dev)
+{
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct phytium_sdci_host *host = mmc_priv(mmc);
+
+	phytium_sdci_init_hw(host);
+
+	return 0;
+}
+
+static const struct dev_pm_ops phytium_sdci_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_sdci_suspend,
+				phytium_sdci_resume)
+	SET_RUNTIME_PM_OPS(phytium_sdci_runtime_suspend,
+			   phytium_sdci_runtime_resume, NULL)
+};
+#else
+#define phytium_sdci_dev_pm_ops NULL
+#endif
+
+static const struct of_device_id phytium_sdci_of_ids[] = {
+	{ .compatible = "phytium,sdci", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_sdci_of_ids);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_sdci_acpi_ids[] = {
+	{ .id = "PHYT0005" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(acpi, phytium_sdci_acpi_ids);
+#else
+#define phytium_sdci_acpi_ids NULL
+#endif
+
+static struct platform_driver phytium_sdci_driver = {
+	.probe = phytium_sdci_probe,
+	.remove = phytium_sdci_remove,
+	.driver = {
+		.name = "sdci-phytium",
+		.of_match_table = phytium_sdci_of_ids,
+		.acpi_match_table = phytium_sdci_acpi_ids,
+		.pm = &phytium_sdci_dev_pm_ops,
+	},
+};
+
+module_platform_driver(phytium_sdci_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium SD Card Interface driver");
diff --git a/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-sdci.h b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-sdci.h
new file mode 100755
index 00000000000000..be0e9aa65e2e6a
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mmc/host/phytium-sdci.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium SD Card Interface driver
+ *
+ * Copyright (c) 2019-2023, Phytium Technology Co.,Ltd.
+ */
+
+/*---------------------------------------------------------------------------*/
+/* Common Definition                                                         */
+/*---------------------------------------------------------------------------*/
+#define MAX_BD_NUM           0x1000
+#define SD_BLOCK_SIZE        512
+
+/*---------------------------------------------------------------------------*/
+/* Register Offset                                                           */
+/*---------------------------------------------------------------------------*/
+#define SDCI_CONTROLLER      0x00  /* controller config reg                  */
+#define SDCI_ARGUMENT        0x04  /* argument reg                           */
+#define SDCI_COMMAND         0x08  /* command reg                            */
+#define SDCI_CLOCK_D         0x0C  /* clock divide reg                       */
+#define SDCI_SOFTWARE        0x10  /* controller reset reg                   */
+#define SDCI_POWER           0X14  /* POWRE CONTROL REG                      */
+#define SDCI_TIMEOUT_CMD     0x18  /* cmd timeout config reg                 */
+#define SDCI_TIMEOUT_DATA    0x1C  /* data timeout reg                       */
+#define SDCI_NORMAL_ISER     0x20  /* normal ISR config reg                  */
+#define SDCI_ERROR_ISER      0x24  /* erroe ISR config reg                   */
+#define SDCI_BD_ISER         0x28  /* BD ISR config reg                      */
+#define SDCI_CAPA            0x2C  /* BD ISR config reg                      */
+#define SDCI_SD_DRV          0x30  /* SD card driving phase position reg     */
+#define SDCI_SD_SAMP         0x34  /* SD card sampling phase position reg    */
+#define SDCI_SD_SEN          0x38  /* SD card detection reg                  */
+#define SDCI_HDS_AXI         0x3C  /* AXI boundary config reg                */
+#define SDCI_BD_RX           0x40  /* BD rx addr reg                         */
+#define SDCI_BD_TX           0x60  /* BD tx addr reg                         */
+#define SDCI_BLK_CNT         0x80  /* r/w block num reg                      */
+#define SDCI_NORMAL_ISR      0xC0  /* normal ISR status reg                  */
+#define SDCI_ERROR_ISR       0xC4  /* error ISR status reg                   */
+#define SDCI_BD_ISR          0xC8  /* BD ISR status reg                      */
+#define SDCI_BD_STATUS       0xCC  /* BD descriptor status reg               */
+#define SDCI_STATUS          0xD0  /* status reg                             */
+#define SDCI_BLOCK           0xD4  /* block len reg                          */
+#define SDCI_RESP0           0xE0  /* response reg0                          */
+#define SDCI_RESP1           0xE4  /* response reg1                          */
+#define SDCI_RESP2           0xE8  /* response reg2                          */
+#define SDCI_RESP3           0XEC  /* response reg3                          */
+
+/*---------------------------------------------------------------------------*/
+/* Register Mask                                                             */
+/*---------------------------------------------------------------------------*/
+/* SDCI_CONTROLLER mask */
+#define SDCI_CONTROLLER_ECRCWR		(0x1 << 0)	/* RW */
+#define SDCI_CONTROLLER_ECRCRD		(0x1 << 1)	/* RW */
+#define SDCI_CONTROLLER_RESEDE		(0x1 << 2)	/* RW */
+#define SDCI_CONTROLLER_PERMDR		(0x3 << 8)	/* RW */
+#define SDCI_CONTROLLER_PERMDX		(0x3 << 10)	/* RW */
+
+/* SDCI_SOFTWARE mask */
+#define SDCI_SOFTWARE_SRST		(0x1 << 0)	/* RW */
+#define SDCI_SOFTWARE_SCRST		(0x1 << 1)	/* RW */
+#define SDCI_SOFTWARE_BDRST		(0x1 << 2)	/* RW */
+#define SDCI_SOFTWARE_CFCLF		(0x1 << 3)	/* RW */
+#define SDCI_SOFTWARE_SDRST		(0x1 << 4)	/* RW */
+
+/* SDCI_NORMAL_ISER mask */
+#define SDCI_SDCI_NORMAL_ISER_ECC_EN	(0x1 << 0)	/* RW */
+#define SDCI_SDCI_NORMAL_ISER_ECR	(0x1 << 1)	/* RW */
+#define SDCI_SDCI_NORMAL_ISER_ECI	(0x1 << 2)	/* RW */
+#define SDCI_SDCI_NORMAL_ISER_EEI_EN	(0x1 << 15)	/* RW */
+
+/* SDCI_NORMAL_ISR mask */
+#define SDCI_NORMAL_ISR_CC		(0x1 << 0)	/* R  */
+#define SDCI_NORMAL_ISR_CR		(0x1 << 1)	/* R  */
+#define SDCI_NORMAL_ISR_CI		(0x1 << 2)	/* R  */
+#define SDCI_NORMAL_ISR_TIMEOUT		(0x1 << 3)	/* R  */
+#define SDCI_NORMAL_ISR_EI		(0x1 << 15)	/* R  */
+
+/* SDCI_ERROR_ISER mask */
+#define SDCI_ERROR_ISER_ECTE_EN		(0x1 << 0)	/* RW */
+#define SDCI_ERROR_ISR_CCRCE_EN		(0x1 << 1)	/* RW */
+#define SDCI_ERROR_ISR_CIR_EN		(0x1 << 3)	/* RW */
+#define SDCI_ERROR_ISR_CNR_EN		(0x1 << 4)	/* RW */
+/* SDCI_ERROR_ISR mask */
+#define SDCI_ERROR_ISR_CTE		(0x1 << 0)	/* R  */
+#define SDCI_ERROR_ISR_CCRCE		(0x1 << 1)	/* R  */
+#define SDCI_ERROR_ISR_CIR		(0x1 << 3)	/* R  */
+#define SDCI_ERROR_ISR_CNR		(0x1 << 4)	/* R  */
+
+/* SDCI_BD_ISER mask */
+#define SDCI_BD_ISER_ETRS_EN		(0x1 << 8)	/* RW */
+#define SDCI_BD_ISER_DATFRAX_EN		(0x1 << 7)	/* RW */
+
+/* SDCI_BD_ISR mask */
+#define SDCI_BD_ISR_TRS_W		(0x1 << 0)	/* R  */
+#define SDCI_BD_ISR_TRS_R		(0x1 << 8)	/* R  */
+#define SDCI_BD_ISR_EDTE		(0x1 << 3)	/* R  */
+#define SDCI_BD_ISR_DAIS		(0x1 << 15)	/* R  */
+#define SDCI_BD_ISR_DATFRAX		(0x1 << 7)	/* R  */
+
+/* SDCI_HDS_AXI mask */
+#define SDCI_HDS_AXI_AWDOMAIN		(0x1 << 0)	/* RW */
+#define SDCI_HDS_AXI_ARDOMAIN		(0x1 << 12)	/* RW */
+#define SDCI_HDS_AXI_AWCACHE		(0x6 << 24)	/* RW */
+#define SDCI_HDS_AXI_ARCACHE		(0xB << 28)	/* RW */
+
+/* SDCI_STATUS mask */
+#define SDCI_STATUS_CMD_BUSY		(0x0 << 0)	/* R  */
+#define SDCI_STATUS_CMD_READY		(0x1 << 0)	/* R  */
+#define SDCI_STATUS_IDIE		(0x1 << 12)	/* R  */
+#define SDCI_CARD_BUSY_IN_PRG		(0x1 << 20)	/* R D0 BUSY:0,IDLE:1 */
+
+/* SDCI_STATUS */
+#define SDCI_STATUS_CDSL		(0x1 << 19)	/* R  */
+
+/*---------------------------------------------------------------------------*/
+/* Register Value                                                            */
+/*---------------------------------------------------------------------------*/
+#define SDCI_SD_DRV_VALUE		0
+#define SDCI_SD_SAMP_VALUE_MAX		50
+#define SDCI_SD_SAMP_VALUE_MIN		0
+
+#define SDCI_TIMEOUT_CMD_VALUE		0xFFFFFFFF
+#define SDCI_TIMEOUT_DATA_VALUE		0xFFFFFFFF
+#define SDCI_POWER_ON			1
+#define SDCI_POWER_OFF			0
+
+#define SDCI_CMD_TIMEOUT		10
+#define SDCI_DAT_TIMEOUT		5000
+
+#define SDCI_CMD_TYPE_ADTC		0x2
+
+#define SDCI_F_MIN			400000
+#define SDCI_F_MAX			25000000
+
+#define SDCI_SEN_CREFR_VAL		(0x1 << 1)
+#define SDCI_SEN_DEBNCE_VAL		(0xB << 8)
+
+#define CARD_CURRENT_STATE		(0xF << 9)
+#define CARD_PRG_STATE			(0x7 << 9)
+#define CARD_TRAN_STATE		(0x4 << 9)
+
+#define SDCI_CMD13_OK			1
+#define SDCI_CMD13_FAILED		0
+
+#define ERR_TIMEOUT			(0x1 << 0)
+#define ERR_CARD_ABSENT		(0x1 << 1)
+#define ERR_CMD_RESPONED		(0x1 << 2)
+
+/*---------------------------------------------------------------------------*/
+/*  Structure Type                                                           */
+/*---------------------------------------------------------------------------*/
+struct phytium_sdci_dma {
+	struct scatterlist *sg;
+	u32 *buf;
+	dma_addr_t bd_addr;
+	size_t bytes;
+};
+
+enum adtc_type {
+	COMMOM_ADTC = 0,
+	BLOCK_RW_ADTC,
+};
+
+struct phytium_sdci_host {
+	struct device *dev;
+	struct mmc_host *mmc;
+	u32 caps;
+	spinlock_t lock;
+
+	struct mmc_request *mrq;
+	struct mmc_command *cmd;
+	struct mmc_data *data;
+	int error;
+
+	void __iomem *base;
+
+	struct phytium_sdci_dma dma_rx;
+	struct phytium_sdci_dma dma_tx;
+
+	u32 *sg_virt_addr;
+	enum adtc_type adtc_type;
+
+	struct timer_list hotplug_timer;
+
+	struct delayed_work req_timeout;
+	u32 cmd_timeout;
+	u32 data_timeout;
+
+	int irq;
+	int irq_err;
+	int irq_bd;
+
+	struct clk *src_clk;
+	unsigned long clk_rate;
+	unsigned long clk_div;
+	unsigned long real_rate;
+
+	u32 current_rca;
+	bool is_multi_rw_only_one_blkcnt;
+};
+
diff --git a/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand.c b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand.c
new file mode 100644
index 00000000000000..68728e7ed498c2
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand.c
@@ -0,0 +1,2167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Core driver for Phytium NAND flash controller
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
+#include <linux/time.h>
+#include <linux/mutex.h>
+
+#include "phytium_nand.h"
+
+#define NFC_DATA_CMD_DEBUG 0
+
+u16 timing_asy_mode0[TIMING_ASY_NUM] = {	/* x100 pass, sample: 1 */
+	0x03, 0x03, 0x28, 0x28, 0x03, 0x03, 0x06, 0x06, 0x28, 0x70, 0x30, 0x50};
+u16 timing_asy_mode1[TIMING_ASY_NUM] = {	/* x100 pass, sample: 1 */
+	0x03, 0x03, 0x14, 0x14, 0x03, 0x03, 0x06, 0x06, 0x14, 0x70, 0x30, 0x28};
+u16 timing_asy_mode2[TIMING_ASY_NUM] = {	/* x100 pass, sample: 7/8 (unlic) */
+	0x03, 0x03, 0x0D, 0x0D, 0x03, 0x03, 0x06, 0x06, 0x0D, 0x70, 0x20, 0x1A};
+u16 timing_asy_mode3[TIMING_ASY_NUM] = {	/* x100 pass, sample: 4-7 */
+	0x03, 0x03, 0x0A, 0x0A, 0x03, 0x03, 0x06, 0x06, 0x0A, 0x70, 0x20, 0x14};
+u16 timing_asy_mode4[TIMING_ASY_NUM] = {	/* x100 1.8v pass */
+	0x03, 0x03, 0x08, 0x08, 0x03, 0x03, 0x06, 0x06, 0x08, 0x70, 0x15, 0x10};
+u16 timing_asy_mode5[TIMING_ASY_NUM] = {	/* x100 1.8v pass */
+	0x03, 0x03, 0x07, 0x07, 0x03, 0x03, 0x06, 0x06, 0x07, 0x20, 0x15, 0x0E};
+u16 timing_syn_mode0[TIMING_SYN_NUM] = {	/* x100 1.8v pass */
+	0x20, 0x41, 0x05, 0x20, 0x10, 0x19, 0x62, 0x40, 0x38, 0x20, 0x00, 0x09,
+	0x50, 0x20};
+u16 timing_syn_mode1[TIMING_SYN_NUM] = {	/* x100 1.8v pass */
+	0x18, 0x32, 0x06, 0x18, 0x0C, 0x10, 0x76, 0x40, 0x2A, 0x1E, 0x00, 0x12,
+	0x24, 0x18};
+u16 timing_syn_mode2[TIMING_SYN_NUM] = {	/* x100 1.8v pass */
+	0x10, 0x0A, 0x04, 0x10, 0x08, 0x0A, 0x6E, 0x50, 0x1D, 0x10, 0x00, 0x0C,
+	0x18, 0x10};
+u16 timing_syn_mode3[TIMING_SYN_NUM] = {	/* x100 1.8v pass */
+	0x0C, 0x1A, 0x02, 0x0C, 0x06, 0x08, 0x78, 0x7C, 0x15, 0x0C, 0x00, 0x08,
+	0x12, 0x0C};
+u16 timing_syn_mode4[TIMING_SYN_NUM] = {	/* x100 1.8v failed */
+	0x08, 0x17, 0x05, 0x08, 0x04, 0x01, 0x73, 0x40, 0x0C, 0x08, 0x00, 0x06,
+	0x0C, 0x10};
+u16 timing_tog_ddr_mode0[TIMING_TOG_NUM] = {	/* 600M clk */
+	0x14, 0x0a, 0x08, 0x08, 0xc8, 0xc8, 0x08, 0x08, 0x20, 0x0a, 0x14, 0x08};
+
+static u32 nfc_ecc_errover;
+static u32 nfc_ecc_err;
+static u32 nfc_irq_st;
+static u32 nfc_irq_en;
+static u32 nfc_irq_complete;
+
+static DECLARE_WAIT_QUEUE_HEAD(wait_done);
+
+/*
+ * Internal helper to conditionnally apply a delay (from the above structure,
+ * most of the time).
+ */
+static void cond_delay(unsigned int ns)
+{
+	if (!ns)
+		return;
+
+	if (ns < 10000)
+		ndelay(ns);
+	else
+		udelay(DIV_ROUND_UP(ns, 1000));
+}
+
+static inline struct phytium_nfc *to_phytium_nfc(struct nand_controller *ctrl)
+{
+	return container_of(ctrl, struct phytium_nfc, controller);
+}
+
+static inline struct phytium_nand_chip *to_phytium_nand(struct nand_chip *chip)
+{
+	return container_of(chip, struct phytium_nand_chip, chip);
+}
+
+static u32 phytium_read(struct phytium_nfc *nfc, u32 reg)
+{
+	return readl_relaxed(nfc->regs + reg);
+}
+
+static void phytium_write(struct phytium_nfc *nfc, u32 reg, u32 value)
+{
+	return writel_relaxed(value, nfc->regs + reg);
+}
+
+static inline int phytium_wait_busy(struct phytium_nfc *nfc)
+{
+	u32 status;
+
+	if (nfc_ecc_errover) {
+		nfc_ecc_errover = 0;
+		return 0;
+	}
+
+	return readl_relaxed_poll_timeout(nfc->regs + NDSR, status,
+			!(status & NDSR_BUSY), 10, 10000);
+}
+
+static void phytium_nfc_disable_int(struct phytium_nfc *nfc, u32 int_mask)
+{
+	u32 reg;
+
+	reg = phytium_read(nfc, NDIR_MASK);
+	phytium_write(nfc, NDIR_MASK, reg | int_mask);
+}
+
+static void phytium_nfc_enable_int(struct phytium_nfc *nfc, u32 int_mask)
+{
+	u32 reg;
+
+	reg = phytium_read(nfc, NDIR_MASK);
+	phytium_write(nfc, NDIR_MASK, reg & (~int_mask));
+}
+
+static void phytium_nfc_clear_int(struct phytium_nfc *nfc, u32 int_mask)
+{
+	phytium_write(nfc, NDIR_MASK, int_mask);
+}
+
+static int phytium_nfc_cmd_correct(struct phytium_nfc_op *nfc_op)
+{
+	if (!nfc_op)
+		return -EINVAL;
+
+	if (nfc_op->cmd_len == 0x01) {
+		nfc_op->cmd[1] = nfc_op->cmd[0];
+		nfc_op->cmd[0] = 0;
+	}
+
+	return 0;
+}
+
+static int phytium_nfc_addr_correct(struct phytium_nfc_op *nfc_op)
+{
+	u32 len;
+	int i, j;
+
+	if (!nfc_op)
+		return -EINVAL;
+
+	len = nfc_op->addr_len > PHYTIUM_NFC_ADDR_MAX_LEN ?
+		  PHYTIUM_NFC_ADDR_MAX_LEN : nfc_op->addr_len;
+
+	if (len == PHYTIUM_NFC_ADDR_MAX_LEN)
+		return 0;
+
+	for (i = len-1, j = PHYTIUM_NFC_ADDR_MAX_LEN - 1; i >= 0; i--, j--) {
+		nfc_op->addr[j] = nfc_op->addr[i];
+		nfc_op->addr[i] = 0;
+	}
+
+	return 0;
+}
+
+static void phytium_nfc_parse_instructions(struct nand_chip *chip,
+					   const struct nand_subop *subop,
+					   struct phytium_nfc_op *nfc_op)
+{
+	struct nand_op_instr *instr = NULL;
+	bool first_cmd = true;
+	u32 op_id;
+	int i;
+
+	/* Reset the input structure as most of its fields will be OR'ed */
+	memset(nfc_op, 0, sizeof(struct phytium_nfc_op));
+
+	for (op_id = 0; op_id < subop->ninstrs; op_id++) {
+		unsigned int offset, naddrs;
+		const u8 *addrs;
+		int len;
+
+		instr = (struct nand_op_instr *)&subop->instrs[op_id];
+
+		switch (instr->type) {
+		case NAND_OP_CMD_INSTR:
+			if (first_cmd) {
+				nfc_op->cmd[0] = instr->ctx.cmd.opcode;
+			} else {
+				nfc_op->cmd[1] = instr->ctx.cmd.opcode;
+				nfc_op->cmd_ctrl.nfc_ctrl.dbc = 1;
+			}
+
+			nfc_op->cle_ale_delay_ns = instr->delay_ns;
+			first_cmd = false;
+			nfc_op->cmd_len++;
+
+			break;
+
+		case NAND_OP_ADDR_INSTR:
+			offset = nand_subop_get_addr_start_off(subop, op_id);
+			naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
+			addrs = &instr->ctx.addr.addrs[offset];
+
+			nfc_op->cmd_ctrl.nfc_ctrl.addr_cyc = naddrs;
+
+			for (i = 0; i < min_t(u32, PHYTIUM_NFC_ADDR_MAX_LEN, naddrs); i++)
+				nfc_op->addr[i] = addrs[i];
+
+			nfc_op->cle_ale_delay_ns = instr->delay_ns;
+
+			nfc_op->addr_len = naddrs;
+			break;
+
+		case NAND_OP_DATA_IN_INSTR:
+			nfc_op->data_instr = instr;
+			nfc_op->data_instr_idx = op_id;
+			nfc_op->cmd_ctrl.nfc_ctrl.dc = 1;
+			len = nand_subop_get_data_len(subop, op_id);
+			nfc_op->page_cnt = len;
+			nfc_op->data_delay_ns = instr->delay_ns;
+
+			break;
+
+		case NAND_OP_DATA_OUT_INSTR:
+			nfc_op->data_instr = instr;
+			nfc_op->data_instr_idx = op_id;
+			nfc_op->cmd_ctrl.nfc_ctrl.dc = 1;
+			len = nand_subop_get_data_len(subop, op_id);
+			nfc_op->page_cnt = len;
+			nfc_op->data_delay_ns = instr->delay_ns;
+			break;
+
+		case NAND_OP_WAITRDY_INSTR:
+			nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
+			nfc_op->rdy_delay_ns = instr->delay_ns;
+			break;
+		}
+	}
+}
+
+int phytium_nfc_prepare_cmd(struct nand_chip *chip,
+			    struct phytium_nfc_op *nfc_op,
+			    enum dma_data_direction direction)
+{
+	struct phytium_nand_chip *phytium_nand = to_phytium_nand(chip);
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	int i;
+
+	phytium_nfc_cmd_correct(nfc_op);
+	phytium_nfc_addr_correct(nfc_op);
+
+	nfc_op->cmd_ctrl.nfc_ctrl.csel = 0x0F ^ (0x01 << phytium_nand->selected_die);
+
+	for (i = 0; i < PHYTIUM_NFC_ADDR_MAX_LEN; i++)
+		nfc_op->mem_addr_first[i] = (nfc->dma_phy_addr >> (8 * i)) & 0xFF;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_prepare_cmd);
+
+#if NFC_DATA_CMD_DEBUG
+
+static int phytium_nfc_cmd_dump(struct phytium_nfc *nfc,
+				struct phytium_nfc_op *nfc_op, u8 *buf)
+{
+	u8 *p;
+	u8 str[1024] = {0};
+	int i;
+
+	sprintf(str, "Phytium NFC cmd dump:\n");
+	sprintf(str, "%s cmd0:%x, cmd1:%x, ctrl:%x, page_cnt:%d\n",
+		str, nfc_op->cmd[0], nfc_op->cmd[1], nfc_op->cmd_ctrl.ctrl, nfc_op->page_cnt);
+
+	p = &nfc_op->addr[0];
+	sprintf(str, "%s addr:%02x %02x %02x %02x %02x\n",
+		str, p[0], p[1], p[2], p[3], p[4]);
+
+	p = &nfc_op->mem_addr_first[0];
+	sprintf(str, "%s mem_addr_first:%02x %02x %02x %02x %02x\n",
+		str, p[0], p[1], p[2], p[3], p[4]);
+
+	for (i = 0; i < PHYTIUM_NFC_DSP_SIZE; i++)
+		sprintf(str, "%s %02x", str, buf[i]);
+
+	dev_info(nfc->dev, "%s\n", str);
+
+	return 0;
+}
+
+int phytium_nfc_data_dump(struct phytium_nfc *nfc, u8 *buf, u32 len)
+{
+	u8 str[1024] = {0};
+	int i;
+
+	len = len > 512 ? 512 : len;
+
+	sprintf(str, "Phytium NFC data dump: %d\n", len);
+	for (i = 0; i < len; i++) {
+		if (i && (i%128 == 0)) {
+			dev_info(nfc->dev, "next:\n%s\n", str);
+			memset(str, 0, 1024);
+		}
+
+		if (i && (i%16 == 0))
+			sprintf(str, "%s\n", str);
+		sprintf(str, "%s %02x", str, buf[i]);
+	}
+
+	dev_info(nfc->dev, "%s\n", str);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_data_dump);
+#else
+#define phytium_nfc_cmd_dump(...)
+#define phytium_nfc_data_dump(...)
+#endif
+
+int phytium_nfc_send_cmd(struct nand_chip *chip,
+			 struct phytium_nfc_op *nfc_op)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	u32 value = 0;
+
+	memset((u8 *)nfc->dsp_addr, 0, PAGE_SIZE);
+	memcpy((u8 *)nfc->dsp_addr, (u8 *)nfc_op, PHYTIUM_NFC_DSP_SIZE);
+
+	phytium_nfc_cmd_dump(nfc, nfc_op, (u8 *)nfc->dsp_addr);
+
+	if (phytium_wait_busy(nfc) != 0) {
+		dev_err(nfc->dev, "NFC was always busy\n");
+		dev_err(nfc->dev, "NFC state: %x\n", phytium_read(nfc, NDSR));
+		dev_err(nfc->dev, "NFC debug: %x\n", phytium_read(nfc, ND_DEBUG));
+		return 0;
+	}
+
+	spin_lock(&nfc->spinlock);
+	value = nfc->dsp_phy_addr & 0xFFFFFFFF;
+	phytium_write(nfc, NDAR0, value);
+
+	/* Don't modify NDAR1_DMA_RLEN & NDAR1_DMA_WLEN */
+	value  = phytium_read(nfc, NDAR1);
+	value |= NDAR1_H8((nfc->dsp_phy_addr >> 32) & 0xFF);
+	phytium_write(nfc, NDAR1, value);
+
+	phytium_nfc_enable_int(nfc,  NDIR_CMD_FINISH_MASK);
+
+	value |= NDAR1_DMA_EN;
+	phytium_write(nfc, NDAR1, value);
+	spin_unlock(&nfc->spinlock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_send_cmd);
+
+int phytium_nfc_prepare_cmd2(struct nand_chip *chip,
+			     struct phytium_nfc_op *nfc_op,
+			     enum dma_data_direction direction,
+			     u32 cmd_num)
+{
+	struct phytium_nand_chip *phytium_nand = to_phytium_nand(chip);
+	int i;
+
+	for (i = 0; i < cmd_num; i++) {
+		phytium_nfc_cmd_correct(nfc_op);
+		phytium_nfc_addr_correct(nfc_op);
+		nfc_op->cmd_ctrl.nfc_ctrl.csel = 0x0F ^ (0x01 << phytium_nand->selected_die);
+		nfc_op++;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_prepare_cmd2);
+
+int phytium_nfc_send_cmd2(struct nand_chip *chip,
+			  struct phytium_nfc_op *nfc_op,
+			  u32 cmd_num)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	u32 value = 0;
+	int i;
+
+	memset((u8 *)nfc->dsp_addr, 0, PAGE_SIZE);
+
+	for (i = 0; i < cmd_num; i++) {
+		memcpy((u8 *)nfc->dsp_addr + i*PHYTIUM_NFC_DSP_SIZE,
+			(u8 *)nfc_op, PHYTIUM_NFC_DSP_SIZE);
+		phytium_nfc_cmd_dump(nfc, nfc_op, (u8 *)nfc->dsp_addr + i*PHYTIUM_NFC_DSP_SIZE);
+		nfc_op++;
+	}
+
+	if (phytium_wait_busy(nfc) != 0) {
+		dev_err(nfc->dev, "NFC was always busy\n");
+		dev_err(nfc->dev, "NFC state: %x\n", phytium_read(nfc, NDSR));
+		dev_err(nfc->dev, "NFC debug: %x\n", phytium_read(nfc, ND_DEBUG));
+		return 0;
+	}
+
+	spin_lock(&nfc->spinlock);
+	value = nfc->dsp_phy_addr & 0xFFFFFFFF;
+	phytium_write(nfc, NDAR0, value);
+
+	/* Don't modify NDAR1_DMA_RLEN & NDAR1_DMA_WLEN */
+	value  = phytium_read(nfc, NDAR1);
+	value |= NDAR1_H8((nfc->dsp_phy_addr >> 32) & 0xFF);
+	phytium_write(nfc, NDAR1, value);
+
+	phytium_nfc_enable_int(nfc, NDIR_DMA_FINISH_MASK | NDIR_ECC_ERR_MASK);
+
+	value |= NDAR1_DMA_EN;
+	phytium_write(nfc, NDAR1, value);
+	spin_unlock(&nfc->spinlock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_send_cmd2);
+
+int phytium_nfc_wait_op(struct nand_chip *chip,
+			u32 timeout_ms)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	int ret;
+
+	/* Timeout is expressed in ms */
+	if (!timeout_ms)
+		timeout_ms = IRQ_TIMEOUT;
+	else if (timeout_ms > 1000)
+		timeout_ms = 1000;
+	else if (timeout_ms < 100)
+		timeout_ms = 100;
+
+	ret = wait_event_interruptible_timeout(wait_done, nfc_irq_complete,
+					  msecs_to_jiffies(timeout_ms));
+	nfc_irq_complete = false;
+
+	if (!ret) {
+		dev_err(nfc->dev, "Timeout waiting for RB signal\n");
+		dev_err(nfc->dev, "NFC state: %x\n", phytium_read(nfc, NDSR));
+		dev_err(nfc->dev, "NFC irq state: %x, irq en:%x\n",
+			phytium_read(nfc, NDIR), phytium_read(nfc, NDIR_MASK));
+		dev_err(nfc->dev, "NFC debug: %x\n", phytium_read(nfc, ND_DEBUG));
+
+		phytium_nfc_clear_int(nfc, NDIR_ALL_INT(nfc->caps->int_mask_bits));
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_wait_op);
+
+static int phytium_nfc_xfer_data_pio(struct phytium_nfc *nfc,
+				     const struct nand_subop *subop,
+				     struct phytium_nfc_op *nfc_op)
+{
+	const struct nand_op_instr *instr = nfc_op->data_instr;
+	unsigned int op_id = nfc_op->data_instr_idx;
+	unsigned int len = nand_subop_get_data_len(subop, op_id);
+	unsigned int offset = nand_subop_get_data_start_off(subop, op_id);
+	bool reading = (instr->type == NAND_OP_DATA_IN_INSTR);
+
+	if (reading) {
+		u8 *in = instr->ctx.data.buf.in + offset;
+
+		memcpy(in, nfc->dma_buf, len);
+
+		nfc->dma_offset = 0;
+	} else {
+		const u8 *out = instr->ctx.data.buf.out + offset;
+
+		memcpy(nfc->dma_buf, out, len);
+	}
+
+	return 0;
+}
+
+static int memcpy_to_reg16(struct phytium_nfc *nfc, u32 reg, u16 *buf, size_t len)
+{
+	int i;
+	u32 val = 0;
+
+	if (!nfc || !buf || (len >= 16))
+		return -EINVAL;
+
+	for (i = 0; i < len; i++) {
+		val = (val << 16) + buf[i];
+		if (i % 2) {
+			phytium_write(nfc, reg, val);
+			val = 0;
+			reg += 4;
+		}
+	}
+
+	return 0;
+}
+
+int phytium_nfc_default_data_interface(struct phytium_nfc *nfc)
+{
+	int value;
+
+	value = phytium_read(nfc, NDCR0);
+	value &= (~NDCR0_IN_MODE(3));
+	value |= NDCR0_IN_MODE(nfc->inter_mode);
+	phytium_write(nfc, NDCR0, value);
+
+	value = phytium_read(nfc, NDCR1);
+	value &= (~NDCR1_SAMPL_PHASE(0xFFFF));
+
+	switch (nfc->inter_mode) {
+	case ASYN_SDR:
+		if (nfc->timing_mode == ASY_MODE4) {
+			memcpy_to_reg16(nfc, NDTR0, timing_asy_mode4, TIMING_ASY_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(4));
+		} else if (nfc->timing_mode == ASY_MODE3) {
+			memcpy_to_reg16(nfc, NDTR0, timing_asy_mode3, TIMING_ASY_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(5));
+		} else if (nfc->timing_mode == ASY_MODE2) {
+			memcpy_to_reg16(nfc, NDTR0, timing_asy_mode2, TIMING_ASY_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(3));
+		} else if (nfc->timing_mode == ASY_MODE1) {
+			memcpy_to_reg16(nfc, NDTR0, timing_asy_mode1, TIMING_ASY_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(2));
+		} else {
+			memcpy_to_reg16(nfc, NDTR0, timing_asy_mode0, TIMING_ASY_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(1));
+		}
+		phytium_write(nfc, ND_INTERVAL_TIME, 0x01);
+		break;
+	case ONFI_DDR:
+		if (nfc->timing_mode == SYN_MODE4) {
+			memcpy_to_reg16(nfc, NDTR6, timing_syn_mode4, TIMING_SYN_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(0x0D));
+			phytium_write(nfc, ND_INTERVAL_TIME, 0x30);
+		} else if (nfc->timing_mode == SYN_MODE3) {
+			memcpy_to_reg16(nfc, NDTR6, timing_syn_mode3, TIMING_SYN_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(0x05));
+			phytium_write(nfc, ND_INTERVAL_TIME, 0x18);
+		} else if (nfc->timing_mode == SYN_MODE2) {
+			memcpy_to_reg16(nfc, NDTR6, timing_syn_mode2, TIMING_SYN_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(0x08));
+			phytium_write(nfc, ND_INTERVAL_TIME, 0x20);
+		} else if (nfc->timing_mode == SYN_MODE1) {
+			memcpy_to_reg16(nfc, NDTR6, timing_syn_mode1, TIMING_SYN_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(0x12));
+			phytium_write(nfc, ND_INTERVAL_TIME, 0x40);
+		} else {
+			memcpy_to_reg16(nfc, NDTR6, timing_syn_mode0, TIMING_SYN_NUM);
+			phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(0x12));
+			phytium_write(nfc, ND_INTERVAL_TIME, 0x40);
+		}
+		break;
+	case TOG_ASYN_DDR:
+		phytium_write(nfc, NDCR1, value | NDCR1_SAMPL_PHASE(8));
+		phytium_write(nfc, ND_INTERVAL_TIME, 0xC8);
+		memcpy_to_reg16(nfc, NDTR13, timing_tog_ddr_mode0, TIMING_TOG_NUM);
+		break;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_default_data_interface);
+
+static int phytium_nfc_naked_waitrdy_exec(struct nand_chip *chip,
+					  const struct nand_subop *subop)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	int ret = 0;
+
+	phytium_nfc_parse_instructions(chip, subop, &nfc_op);
+
+	dev_info(nfc->dev, "Phytium nand command 0x%02x 0x%02x.\n",
+		 nfc_op.cmd[0], nfc_op.cmd[1]);
+
+	switch (nfc_op.cmd[0]) {
+	case NAND_CMD_PARAM:
+		memset(nfc->dma_buf, 0, PAGE_SIZE);
+		direction = DMA_FROM_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ_PARAM;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		if (nfc->inter_pro == NAND_ONFI)
+			nfc_op.page_cnt = 3 * sizeof(struct nand_onfi_params);
+		else if (nfc->inter_pro == NAND_JEDEC)
+			nfc_op.page_cnt = 3 * sizeof(struct nand_jedec_params);
+		if (nfc_op.page_cnt)
+			nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+		nfc->dma_offset = 0;
+		break;
+	case NAND_CMD_SET_FEATURES:
+		direction = DMA_TO_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_SET_FTR;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+		if (nfc->inter_mode != ASYN_SDR) {
+			dev_err(nfc->dev, "Not support SET_FEATURES command!\n");
+			return 0;
+		}
+		break;
+	case NAND_CMD_GET_FEATURES:
+		direction = DMA_FROM_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_GET_FTR;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+		break;
+	case NAND_CMD_READ0:
+		if (nfc_op.cmd[1] == NAND_CMD_READSTART) { /* large page */
+			direction = DMA_FROM_DEVICE;
+			nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ;
+			nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		} else if (nfc_op.cmd[1] == NAND_CMD_SEQIN) { /* program page begin */
+			nfc_op.cmd[0] = NAND_CMD_SEQIN;
+			nfc_op.cmd[1] = NAND_CMD_PAGEPROG;
+			direction = DMA_TO_DEVICE;
+			nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_PAGE_PRO;
+			nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		} else {   /* small page */
+			direction = DMA_FROM_DEVICE;
+			nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ;
+			nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		}
+		break;
+	case NAND_CMD_RNDOUT: /* change read column  */
+		direction = DMA_FROM_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_CH_READ_COL;
+		nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+		break;
+	case NAND_CMD_READSTART:   /* large page */
+		direction = DMA_FROM_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		break;
+	case NAND_CMD_RNDOUTSTART:  /* change read column  */
+		direction = DMA_FROM_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_CH_READ_COL;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		nfc->dma_offset = nfc_op.addr[1];
+		nfc->dma_offset = (nfc->dma_offset << 8) + nfc_op.addr[0];
+		break;
+	case NAND_CMD_SEQIN:  /* program begin */
+		if (nfc_op.cmd[0] == NAND_CMD_READ0) {
+			nfc_op.cmd[0] = NAND_CMD_SEQIN;
+			nfc_op.cmd[1] = NAND_CMD_PAGEPROG;
+		}
+		direction = DMA_TO_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_PAGE_PRO;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		break;
+	case NAND_CMD_RNDIN:  /* change write column  */
+		direction = DMA_TO_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_CH_WR_COL;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		break;
+	case NAND_CMD_PAGEPROG: /* program end */
+		nfc_op.cmd[0] = NAND_CMD_RNDIN;
+		nfc_op.cmd[1] = NAND_CMD_PAGEPROG;
+		direction = DMA_TO_DEVICE;
+		nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_PAGE_PRO;
+		nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+		break;
+	default:
+		dev_err(nfc->dev, "Not support cmd %d.\n", nfc_op.cmd[1]);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if ((nfc_op.data_instr) && (direction == DMA_TO_DEVICE))
+		phytium_nfc_xfer_data_pio(nfc, subop, &nfc_op);
+
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+	nfc_op.rdy_timeout_ms = nfc_op.rdy_timeout_ms;
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		goto out;
+
+	cond_delay(nfc_op.rdy_delay_ns);
+
+	if ((nfc_op.data_instr) && (direction == DMA_FROM_DEVICE))
+		phytium_nfc_xfer_data_pio(nfc, subop, &nfc_op);
+
+out:
+	return ret;
+}
+
+static int phytium_nfc_read_id_type_exec(struct nand_chip *chip,
+					 const struct nand_subop *subop)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	u16 read_len = 0;
+	int ret;
+	u8 *buf = nfc->dma_buf;
+
+	memset(nfc->dma_buf, 0, PAGE_SIZE);
+	direction = DMA_FROM_DEVICE;
+
+	phytium_nfc_parse_instructions(chip, subop, &nfc_op);
+	read_len = nfc_op.page_cnt;
+	nfc_op.page_cnt = (read_len & 0x03) ? ((read_len & 0xFFFC) + 4) : read_len;
+
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ_ID;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 0;
+
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		return ret;
+
+	cond_delay(nfc_op.rdy_delay_ns);
+
+	if (!strncmp(nfc->dma_buf, "ONFI", 4)) {
+		nfc->inter_pro = NAND_ONFI;
+	} else if (!strncmp(nfc->dma_buf, "JEDEC", 5)) {
+		nfc->inter_pro = NAND_JEDEC;
+		if (buf[5] == 1)
+			nfc->inter_mode = ASYN_SDR;
+		else if (buf[5] == 2)
+			nfc->inter_mode = TOG_ASYN_DDR;
+		else if (buf[5] == 4)
+			nfc->inter_mode = ASYN_SDR;
+	} else {
+		nfc->inter_pro = NAND_OTHER;
+	}
+
+	dev_info(nfc->dev, "Nand protocol: %d, interface mode: %d\n",
+		 nfc->inter_pro, nfc->inter_mode);
+
+	phytium_nfc_xfer_data_pio(nfc, subop, &nfc_op);
+
+	return 0;
+}
+
+static int phytium_nfc_read_status_exec(struct nand_chip *chip,
+					const struct nand_subop *subop)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	u16 read_len = 0;
+	u32 timeout, count = 0;
+	int ret = 0;
+
+	direction = DMA_FROM_DEVICE;
+
+	phytium_nfc_parse_instructions(chip, subop, &nfc_op);
+	read_len = nfc_op.page_cnt;
+	nfc_op.page_cnt = (read_len & 0x03) ? ((read_len & 0xFFFC) + 4) : read_len;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ_STATUS;
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+
+read_status_retry:
+	count++;
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+	timeout = nfc_op.rdy_timeout_ms ? nfc_op.rdy_timeout_ms : 10;
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		goto out;
+
+	phytium_nfc_xfer_data_pio(nfc, subop, &nfc_op);
+
+	if (0xE0 != *(u8 *)(nfc->dma_buf)) {
+		dev_info(nfc->dev, "Retry to read status (%x)\n", *(u8 *)(nfc->dma_buf));
+
+		if (count < 10)
+			goto read_status_retry;
+	}
+
+out:
+	return ret;
+}
+
+static int phytium_nfc_reset_cmd_type_exec(struct nand_chip *chip,
+					   const struct nand_subop *subop)
+{
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+
+	phytium_nfc_parse_instructions(chip, subop, &nfc_op);
+
+	direction = DMA_NONE;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_RESET;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+
+	return phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+}
+
+static int phytium_nfc_erase_cmd_type_exec(struct nand_chip *chip,
+					   const struct nand_subop *subop)
+{
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+
+	phytium_nfc_parse_instructions(chip, subop, &nfc_op);
+	direction = DMA_NONE;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_ERASE;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs  = 1;
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+
+	return phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+}
+
+static int phytium_nfc_data_in_type_exec(struct nand_chip *chip,
+					 const struct nand_subop *subop)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nfc_op nfc_op;
+	struct nand_op_instr *instr;
+	unsigned int op_id;
+	unsigned int len;
+	unsigned int offset;
+	u8 *in = NULL;
+
+	phytium_nfc_parse_instructions(chip, subop, &nfc_op);
+	if (nfc_op.data_instr->type != NAND_OP_DATA_IN_INSTR) {
+		dev_err(nfc->dev, "Phytium nfc instrs parser failed!\n");
+		return -EINVAL;
+	}
+
+	instr = nfc_op.data_instr;
+	op_id = nfc_op.data_instr_idx;
+	len = nand_subop_get_data_len(subop, op_id);
+	offset = nand_subop_get_data_start_off(subop, op_id);
+	in = instr->ctx.data.buf.in + offset;
+
+	phytium_nfc_cmd_dump(nfc, &nfc_op, (u8 *)nfc->dsp_addr);
+
+	memcpy(in, nfc->dma_buf + nfc->dma_offset, len);
+	nfc->dma_offset += len;
+	phytium_nfc_data_dump(nfc, in, len);
+
+	return 0;
+}
+
+static const struct nand_op_parser phytium_nfc_op_parser = NAND_OP_PARSER(
+	/* Naked commands not supported, use a function for each pattern */
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_read_id_type_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, PHYTIUM_NFC_ADDR_MAX_LEN),
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_erase_cmd_type_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, PHYTIUM_NFC_ADDR_MAX_LEN),
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_read_status_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_reset_cmd_type_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_naked_waitrdy_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, PHYTIUM_NFC_ADDR_MAX_LEN),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false),
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_naked_waitrdy_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, PHYTIUM_NFC_ADDR_MAX_LEN),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_naked_waitrdy_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, PHYTIUM_NFC_ADDR_MAX_LEN),
+		NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 8),
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_naked_waitrdy_exec,
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_ADDR_ELEM(false, PHYTIUM_NFC_ADDR_MAX_LEN),
+		NAND_OP_PARSER_PAT_CMD_ELEM(false),
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
+	NAND_OP_PARSER_PATTERN(
+		phytium_nfc_data_in_type_exec,
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
+	);
+
+static int phytium_nfc_exec_op(struct nand_chip *chip,
+			       const struct nand_operation *op,
+			       bool check_only)
+{
+	return nand_op_parser_exec_op(chip, &phytium_nfc_op_parser,
+				      op, check_only);
+}
+
+static int phytium_nfc_reset(struct phytium_nfc *nfc)
+{
+	u32 value;
+
+	phytium_write(nfc, NDIR_MASK, NDIR_ALL_INT(nfc->caps->int_mask_bits));
+	phytium_write(nfc, NDSR, NDIR_ALL_INT(nfc->caps->int_mask_bits));
+
+	phytium_write(nfc, ND_ERR_CLR, 0x0F);
+	phytium_write(nfc, NDFIFO_CLR, 1);
+
+	value = phytium_read(nfc, NDCR0);
+	phytium_write(nfc, NDCR0, value & ~(NDCR0_ECC_EN | NDCR0_SPARE_EN));
+
+	return 0;
+}
+
+static void phytium_nfc_select_chip(struct nand_chip *chip, int die_nr)
+{
+	struct phytium_nand_chip *phytium_nand = to_phytium_nand(chip);
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+
+	dev_dbg(nfc->dev, "Phytium nand selected chip %d\n", die_nr);
+
+	if (chip == nfc->selected_chip && die_nr == phytium_nand->selected_die)
+		return;
+
+	if (die_nr < 0 || die_nr >= phytium_nand->nsels) {
+		nfc->selected_chip = NULL;
+		phytium_nand->selected_die = -1;
+		return;
+	}
+
+	phytium_nfc_reset(nfc);
+
+	nfc->selected_chip = chip;
+	phytium_nand->selected_die = die_nr;
+}
+
+static int phytium_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (section)
+		return -ERANGE;
+
+	oobregion->length = chip->ecc.total;
+	oobregion->offset = mtd->oobsize - oobregion->length;
+
+	return 0;
+}
+
+static int phytium_nand_ooblayout_free(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if (section)
+		return -ERANGE;
+
+	/*
+	 * Bootrom looks in bytes 0 & 5 for bad blocks for the
+	 * 4KB page / 4bit BCH combination.
+	 */
+	if (mtd->writesize >= SZ_4K)
+		oobregion->offset = 6;
+	else
+		oobregion->offset = 2;
+
+	oobregion->length = mtd->oobsize - chip->ecc.total - oobregion->offset;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops phytium_nand_ooblayout_ops = {
+	.ecc = phytium_nand_ooblayout_ecc,
+	.free = phytium_nand_ooblayout_free,
+};
+
+static void phytium_nfc_enable_hw_ecc(struct nand_chip *chip)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	u32 ndcr0 = phytium_read(nfc, NDCR0);
+
+	if (!(ndcr0 & NDCR0_ECC_EN))
+		phytium_write(nfc, NDCR0, ndcr0 | NDCR0_ECC_EN);
+}
+
+static void phytium_nfc_disable_hw_ecc(struct nand_chip *chip)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	u32 ndcr0 = phytium_read(nfc, NDCR0);
+
+	if (ndcr0 & NDCR0_ECC_EN)
+		phytium_write(nfc, NDCR0, ndcr0 & ~NDCR0_ECC_EN);
+}
+
+
+irqreturn_t phytium_nfc_isr(int irq, void *dev_id)
+{
+	struct phytium_nfc *nfc = dev_id;
+	u32 st = phytium_read(nfc, NDIR);
+	u32 ien = (~phytium_read(nfc, NDIR_MASK)) & NDIR_ALL_INT(nfc->caps->int_mask_bits);
+
+	if (!(st & ien))
+		return IRQ_NONE;
+
+	nfc_irq_st = st;
+	nfc_irq_en = ien;
+	phytium_nfc_disable_int(nfc, st & NDIR_ALL_INT(nfc->caps->int_mask_bits));
+	phytium_write(nfc, 0xFD0, 0);
+
+	if (st & (NDIR_CMD_FINISH | NDIR_DMA_FINISH)) {
+		if (st & NDIR_ECC_ERR)
+			nfc_ecc_err = 1;
+		phytium_write(nfc, NDIR, st);
+		nfc_irq_complete = 1;
+	} else if (st & (NDIR_FIFO_TIMEOUT | NDIR_PGFINISH)) {
+		phytium_write(nfc, NDIR, st);
+		phytium_nfc_enable_int(nfc, (~st) & (NDIR_DMA_FINISH_MASK |
+						     NDIR_PGFINISH_MASK |
+						     NDIR_FIFO_TIMEOUT_MASK |
+						     NDIR_CMD_FINISH_MASK));
+		nfc_irq_complete = 0;
+	} else if (st & NDIR_ECC_ERR) {
+		phytium_write(nfc, ND_ERR_CLR, 0x08);
+		phytium_write(nfc, NDIR, st);
+		phytium_write(nfc, NDFIFO_CLR, 0x01);
+		nfc_irq_complete = 1;
+		nfc_ecc_errover = 1;
+	} else {
+		phytium_write(nfc, NDIR, st);
+		nfc_irq_complete = 1;
+	}
+
+	wake_up(&wait_done);
+
+	return IRQ_HANDLED;
+}
+EXPORT_SYMBOL(phytium_nfc_isr);
+
+static int phytium_nfc_hw_ecc_correct(struct nand_chip *chip,
+				char *buf, int len)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	u32 i, j, value, tmp;
+	u32 ecc_err_reg_nums;
+	int stat = 0;
+
+	if (!buf)
+		return -EINVAL;
+
+	if (nfc->caps->hw_ver == 1)
+		ecc_err_reg_nums = 2;
+	else
+		ecc_err_reg_nums = 4;
+
+	for (i = 0; i < chip->ecc.steps; i++) {
+		for (j = 0; j < ecc_err_reg_nums; j++) {
+			value = phytium_read(nfc, 0xB8 + 4 * (ecc_err_reg_nums * i + j));
+			dev_info(nfc->dev, "ECC_FLAG: offset:%x value:0x%08x\n",
+				 0xB8 + 4 * (2 * i + j), value);
+
+			tmp = value & 0xFFFF;
+			if (tmp && (tmp <= 4096)) {
+				tmp--;
+				stat++;
+				buf[chip->ecc.size * i + (tmp >> 3)] ^= (0x01 << tmp % 8);
+				dev_info(nfc->dev, "ECC_CORRECT %x %02x\n",
+					 chip->ecc.size * i + (tmp >> 3),
+					 buf[chip->ecc.size * i + (tmp >> 3)]);
+				dev_info(nfc->dev, "ECC_CORRECT xor %x %02x\n",
+					 0x01 << (tmp % 8), buf[chip->ecc.size * i + (tmp >> 3)]);
+			} else if (tmp > 4096) {
+				dev_info(nfc->dev, "ECC_CORRECT offset > 4096!\n");
+			}
+
+			tmp = (value >> 16) & 0xFFFF;
+			if (tmp && (tmp <= 4096)) {
+				tmp--;
+				stat++;
+				buf[chip->ecc.size * i + (tmp >> 3)] ^= (0x01 << tmp % 8);
+				dev_info(nfc->dev, "ECC_CORRECT %x %02x\n",
+					 chip->ecc.size * i + (tmp >> 3),
+					 buf[chip->ecc.size * i + (tmp >> 3)]);
+				dev_info(nfc->dev, "ECC_CORRECT xor %x %02x\n",
+					 chip->ecc.size * i + (tmp >> 3),
+					 buf[chip->ecc.size * i + (tmp >> 3)]);
+			} else if (tmp > 4096) {
+				dev_info(nfc->dev, "ECC_CORRECT offset > 4096!\n");
+			}
+		}
+	}
+
+	return stat;
+}
+
+static int phytium_nand_page_read(struct mtd_info *mtd, struct nand_chip *chip,
+				  u8 *buf, u8 *oob_buf, int oob_len, int page,
+				  bool read)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nand_chip *phytium_nand = NULL;
+	const struct nand_sdr_timings *sdr = NULL;
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	int ret = 0;
+
+	memset(&nfc_op, 0, sizeof(nfc_op));
+	phytium_nand = to_phytium_nand(chip);
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
+
+	memset(nfc->dma_buf, 0x0, mtd->writesize + mtd->oobsize);
+	direction  = DMA_FROM_DEVICE;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ;
+	nfc_op.cmd[0] = NAND_CMD_READ0;
+	nfc_op.cmd[1] = NAND_CMD_READSTART;
+	nfc_op.cmd_len  = 2;
+	nfc_op.cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max);
+	nfc_op.rdy_timeout_ms = PSEC_TO_MSEC(sdr->tR_max);
+	nfc_op.rdy_delay_ns = PSEC_TO_NSEC(sdr->tRR_min);
+
+	nfc_op.cmd_ctrl.nfc_ctrl.dbc = 1;
+	nfc_op.addr[2] = page;
+	nfc_op.addr[3] = page >> 8;
+	nfc_op.addr[4] = page >> 16;
+	nfc_op.addr_len = 5;
+	nfc_op.cmd_ctrl.nfc_ctrl.addr_cyc = 0x05;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs = 1;
+
+	nfc_op.page_cnt = mtd->writesize;
+	nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+	nfc_op.cmd_ctrl.nfc_ctrl.ecc_en = 0;
+
+	/* For data read/program */
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		return ret;
+
+	if ((direction == DMA_FROM_DEVICE) && buf)
+		memcpy(buf, nfc->dma_buf, mtd->writesize);
+
+	return ret;
+}
+
+static int phytium_nand_oob_read(struct mtd_info *mtd, struct nand_chip *chip,
+				 u8 *buf, u8 *oob_buf, int oob_len, int page,
+				 bool read)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nand_chip *phytium_nand = NULL;
+	const struct nand_sdr_timings *sdr = NULL;
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	int ret = 0;
+
+	memset(&nfc_op, 0, sizeof(nfc_op));
+	phytium_nand = to_phytium_nand(chip);
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
+
+	memset(nfc->dma_buf, 0x00, mtd->writesize + mtd->oobsize);
+	direction  = DMA_FROM_DEVICE;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ;
+	nfc_op.cmd[0] = NAND_CMD_READ0;
+	nfc_op.cmd[1] = NAND_CMD_READSTART;
+	nfc_op.cmd_len  = 2;
+	nfc_op.cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max);
+	nfc_op.rdy_timeout_ms = PSEC_TO_MSEC(sdr->tR_max);
+	nfc_op.rdy_delay_ns = PSEC_TO_NSEC(sdr->tRR_min);
+
+	nfc_op.cmd_ctrl.nfc_ctrl.dbc = 1;
+	nfc_op.addr[2] = page;
+	nfc_op.addr[3] = page >> 8;
+	nfc_op.addr[4] = page >> 16;
+	nfc_op.addr_len = 5;
+	nfc_op.cmd_ctrl.nfc_ctrl.addr_cyc = 0x05;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs = 1;
+
+	nfc_op.page_cnt = oob_len;
+	nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+	nfc_op.cmd_ctrl.nfc_ctrl.ecc_en = 0;
+	nfc_op.addr[0] = mtd->writesize & 0xFF;
+	nfc_op.addr[1] = (mtd->writesize >> 8) & 0xFF;
+
+	/* For data read/program */
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		return ret;
+
+	cond_delay(nfc_op.rdy_delay_ns);
+
+	if (direction == DMA_FROM_DEVICE)
+		memcpy(oob_buf, nfc->dma_buf, oob_len);
+
+	return ret;
+}
+
+static int phytium_nand_get_ecc_total(struct mtd_info *mtd,
+				 struct nand_ecc_ctrl *ecc)
+{
+	int ecc_total = 0;
+
+	switch (mtd->writesize) {
+	case 0x200:
+		if (ecc->strength == 8)
+			ecc_total = 0x0D;
+		else if (ecc->strength == 4)
+			ecc_total = 7;
+		else if (ecc->strength == 2)
+			ecc_total = 4;
+		else
+			ecc_total = 0;
+		break;
+	case 0x800:
+		if (ecc->strength == 8)
+			ecc_total = 0x34;
+		else if (ecc->strength == 4)
+			ecc_total = 0x1a;
+		else if (ecc->strength == 2)
+			ecc_total = 0xd;
+		else
+			ecc_total = 0;
+	break;
+	case 0x1000:
+		if (ecc->strength == 8)
+			ecc_total = 0x68;
+		else if (ecc->strength == 4)
+			ecc_total = 0x34;
+		else if (ecc->strength == 2)
+			ecc_total = 0x1a;
+		else
+			ecc_total = 0;
+		break;
+	case 0x2000:
+		if (ecc->strength == 8)
+			ecc_total = 0xD0;
+		else if (ecc->strength == 4)
+			ecc_total = 0x68;
+		else if (ecc->strength == 2)
+			ecc_total = 0x34;
+		else
+			ecc_total = 0;
+		break;
+	case 0x4000:
+		if (ecc->strength == 8)
+			ecc_total = 0x1A0;
+		if (ecc->strength == 4)
+			ecc_total = 0xD0;
+		else if (ecc->strength == 2)
+			ecc_total = 0x68;
+		else
+			ecc_total = 0;
+		break;
+	default:
+			ecc_total = 0;
+		break;
+	}
+
+	return ecc_total;
+}
+
+static int phytium_nand_page_read_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+					u8 *buf, u8 *oob_buf, int oob_len, int page,
+					bool read)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nand_chip *phytium_nand = NULL;
+	const struct nand_sdr_timings *sdr = NULL;
+	struct phytium_nfc_op *nfc_op = NULL;
+	enum dma_data_direction direction;
+	u32 ecc_offset;
+	int max_bitflips = 0;
+	u32 nfc_state = 0;
+	int ret = 0;
+	int i;
+
+	phytium_nand = to_phytium_nand(chip);
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
+
+	ecc_offset = phytium_nand->ecc.offset;
+	memset(nfc->dma_buf, 0x00, mtd->writesize + mtd->oobsize);
+	nfc_op = kzalloc(2 * sizeof(struct phytium_nfc_op), GFP_KERNEL);
+	if (!nfc_op) {
+		dev_err(nfc->dev, "Can't malloc space for phytium_nfc_op\n");
+		return 0;
+	}
+
+	nfc_op->cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max);
+	nfc_op->rdy_timeout_ms = PSEC_TO_MSEC(sdr->tR_max);
+	nfc_op->rdy_delay_ns = PSEC_TO_NSEC(sdr->tRR_min);
+
+	direction  = DMA_FROM_DEVICE;
+	nfc_op->cmd_ctrl.nfc_ctrl.cmd_type = TYPE_READ;
+	nfc_op->cmd[0] = NAND_CMD_READ0;
+	nfc_op->cmd[1] = NAND_CMD_READSTART;
+	nfc_op->cmd_len  = 2;
+	nfc_op->addr_len = 5;
+	nfc_op->cmd_ctrl.nfc_ctrl.dbc = 1;
+	nfc_op->addr[2] = page;
+	nfc_op->addr[3] = page >> 8;
+	nfc_op->addr[4] = page >> 16;
+	nfc_op->cmd_ctrl.nfc_ctrl.addr_cyc = 0x05;
+	nfc_op->cmd_ctrl.nfc_ctrl.dc = 1;
+	nfc_op->cmd_ctrl.nfc_ctrl.auto_rs = 1;
+	nfc_op->page_cnt = mtd->writesize;
+	nfc_op->cmd_ctrl.nfc_ctrl.nc = 1;
+	for (i = 0; i < PHYTIUM_NFC_ADDR_MAX_LEN; i++)
+		nfc_op->mem_addr_first[i] = (nfc->dma_phy_addr >> (8 * i)) & 0xFF;
+
+	nfc_op++;
+	memcpy(nfc_op, nfc_op - 1, sizeof(struct phytium_nfc_op));
+	nfc_op->cmd_ctrl.nfc_ctrl.cmd_type = TYPE_CH_READ_COL;
+	nfc_op->cmd[0] = NAND_CMD_RNDOUT;
+	nfc_op->cmd[1] = NAND_CMD_RNDOUTSTART;
+	memset(&nfc_op->addr, 0, PHYTIUM_NFC_ADDR_MAX_LEN);
+	nfc_op->addr_len = 2;
+	nfc_op->addr[0] = mtd->writesize + phytium_nand->ecc.offset;
+	nfc_op->addr[1] = (mtd->writesize + phytium_nand->ecc.offset) >> 8;
+	nfc_op->cmd_ctrl.nfc_ctrl.addr_cyc = 0x02;
+	nfc_op->page_cnt = phytium_nand_get_ecc_total(mtd, &chip->ecc);
+	nfc_op->cmd_ctrl.nfc_ctrl.nc = 0;
+	nfc_op->cmd_ctrl.nfc_ctrl.auto_rs = 0;
+	nfc_op->cmd_ctrl.nfc_ctrl.ecc_en = 1;
+	for (i = 0; i < PHYTIUM_NFC_ADDR_MAX_LEN; i++)
+		nfc_op->mem_addr_first[i] =
+			((nfc->dma_phy_addr + mtd->writesize) >> (8 * i)) & 0xFF;
+
+	nfc_op--;
+	phytium_nfc_prepare_cmd2(chip, nfc_op, direction, 2);
+	phytium_nfc_send_cmd2(chip, nfc_op, 2);
+	cond_delay(nfc_op->cle_ale_delay_ns);
+
+	ret = phytium_nfc_wait_op(chip, nfc_op->rdy_timeout_ms);
+	if (ret){
+		kfree(nfc_op);
+		return ret;
+	}
+
+	cond_delay(nfc_op->rdy_delay_ns*1000);
+
+	if ((direction == DMA_FROM_DEVICE) && buf) {
+		nfc_state = phytium_read(nfc, NDSR);
+		if ((nfc_state & NDSR_ECC_ERROVER) || (nfc_ecc_errover == 1)) {
+			for (i = 0; i < mtd->writesize/16; i++) {
+				if (0xFF != *(u8 *)(nfc->dma_buf + i)) {
+					dev_info(nfc->dev, "NFC: NDSR_ECC_ERROVER %x\n", page);
+					mtd->ecc_stats.failed++;
+					mtd->ecc_stats.corrected += max_bitflips;
+					break;
+				}
+			}
+		} else if (nfc_state & NDSR_ECC_ERR) {
+			max_bitflips = phytium_nfc_hw_ecc_correct(chip,
+						nfc->dma_buf, mtd->writesize);
+			mtd->ecc_stats.corrected += max_bitflips;
+			dev_info(nfc->dev, "NFC: NDSR_ECC_ERR page:%x, bit:%d\n",
+						page, max_bitflips);
+		}
+
+		memcpy(buf, nfc->dma_buf, mtd->writesize);
+	}
+
+	kfree(nfc_op);
+	return max_bitflips;
+}
+
+static int phytium_nand_page_write(struct mtd_info *mtd, struct nand_chip *chip,
+				   const u8 *buf, u8 *oob_buf, int oob_len, int page,
+				   bool read)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nand_chip *phytium_nand = NULL;
+	const struct nand_sdr_timings *sdr = NULL;
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	int ret = 0;
+
+	memset(&nfc_op, 0, sizeof(nfc_op));
+	phytium_nand = to_phytium_nand(chip);
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
+
+	memcpy(nfc->dma_buf, buf, mtd->writesize);
+	direction  = DMA_TO_DEVICE;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_PAGE_PRO;
+	nfc_op.cmd[0] = NAND_CMD_SEQIN;
+	nfc_op.cmd[1] = NAND_CMD_PAGEPROG;
+	nfc_op.cmd_len  = 2;
+	nfc_op.addr_len = 5;
+	nfc_op.cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max);
+	nfc_op.rdy_timeout_ms = PSEC_TO_MSEC(sdr->tPROG_max);
+	nfc_op.rdy_delay_ns = 0;
+
+	nfc_op.cmd_ctrl.nfc_ctrl.dbc = 1;
+	nfc_op.addr[2] = page;
+	nfc_op.addr[3] = page >> 8;
+	nfc_op.addr[4] = page >> 16;
+	nfc_op.cmd_ctrl.nfc_ctrl.addr_cyc = 0x05;
+	nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs = 1;
+	nfc_op.page_cnt = mtd->writesize;
+
+	/* For data read/program */
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		goto out;
+
+	cond_delay(nfc_op.rdy_delay_ns);
+out:
+	return ret;
+}
+
+static int phytium_nand_oob_write(struct mtd_info *mtd, struct nand_chip *chip,
+				  u8 *buf, u8 *oob_buf, int oob_len, int page,
+				  bool read)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nand_chip *phytium_nand = NULL;
+	const struct nand_sdr_timings *sdr = NULL;
+	struct phytium_nfc_op nfc_op;
+	enum dma_data_direction direction;
+	int ret = 0;
+
+	memset(&nfc_op, 0, sizeof(nfc_op));
+	phytium_nand = to_phytium_nand(chip);
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
+
+	direction  = DMA_TO_DEVICE;
+	nfc_op.cmd_ctrl.nfc_ctrl.cmd_type = TYPE_PAGE_PRO;
+	nfc_op.cmd[0] = NAND_CMD_SEQIN;
+	nfc_op.cmd[1] = NAND_CMD_PAGEPROG;
+	nfc_op.cmd_len  = 2;
+	nfc_op.addr_len = 5;
+	nfc_op.cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max);
+	nfc_op.rdy_timeout_ms = PSEC_TO_MSEC(sdr->tPROG_max);
+	nfc_op.rdy_delay_ns = 0;
+
+	nfc_op.cmd_ctrl.nfc_ctrl.dbc = 1;
+	nfc_op.addr[2] = page;
+	nfc_op.addr[3] = page >> 8;
+	nfc_op.addr[4] = page >> 16;
+	nfc_op.cmd_ctrl.nfc_ctrl.addr_cyc = 0x05;
+	nfc_op.cmd_ctrl.nfc_ctrl.dc = 1;
+	nfc_op.cmd_ctrl.nfc_ctrl.auto_rs = 1;
+
+	nfc_op.page_cnt = oob_len;
+	nfc_op.cmd_ctrl.nfc_ctrl.ecc_en = 0;
+	nfc_op.addr[0] = mtd->writesize & 0xFF;
+	nfc_op.addr[1] = (mtd->writesize >> 8) & 0xFF;
+	nfc_op.cmd_ctrl.nfc_ctrl.ecc_en = 0;
+	memcpy(nfc->dma_buf, oob_buf, mtd->oobsize);
+
+	/* For data read/program */
+	phytium_nfc_prepare_cmd(chip, &nfc_op, direction);
+	phytium_nfc_send_cmd(chip, &nfc_op);
+	cond_delay(nfc_op.cle_ale_delay_ns);
+
+	ret = phytium_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
+	if (ret)
+		goto out;
+
+	cond_delay(nfc_op.rdy_delay_ns);
+out:
+	return ret;
+}
+
+static int phytium_nand_page_write_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+					 const u8 *buf, u8 *oob_buf, int oob_len, int page,
+					 bool read)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	struct phytium_nand_chip *phytium_nand = NULL;
+	const struct nand_sdr_timings *sdr = NULL;
+	struct phytium_nfc_op *nfc_op;
+	enum dma_data_direction direction;
+	u32 ecc_offset;
+	int ret = 0;
+	int i;
+
+	phytium_nand = to_phytium_nand(chip);
+	sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
+	ecc_offset = phytium_nand->ecc.offset;
+
+	nfc_op = kzalloc(2 * sizeof(struct phytium_nfc_op), GFP_KERNEL);
+	if (!nfc_op) {
+		dev_err(nfc->dev, "Can't malloc space for phytium_nfc_op\n");
+		return 0;
+	}
+
+	nfc_op->cle_ale_delay_ns = PSEC_TO_NSEC(sdr->tWB_max);
+	nfc_op->rdy_timeout_ms = PSEC_TO_MSEC(sdr->tR_max);
+	nfc_op->rdy_delay_ns = PSEC_TO_NSEC(sdr->tRR_min);
+
+	direction = DMA_TO_DEVICE;
+	nfc_op->cmd_ctrl.nfc_ctrl.cmd_type = TYPE_CH_ROW_ADDR;
+	nfc_op->cmd[0] = NAND_CMD_SEQIN;
+	nfc_op->cmd_len  = 1;
+	nfc_op->addr_len = 5;
+	nfc_op->cmd_ctrl.nfc_ctrl.dbc = 0;
+	nfc_op->addr[2] = page;
+	nfc_op->addr[3] = page >> 8;
+	nfc_op->addr[4] = page >> 16;
+	nfc_op->cmd_ctrl.nfc_ctrl.addr_cyc = 0x05;
+	nfc_op->cmd_ctrl.nfc_ctrl.auto_rs = 0;
+	nfc_op->cmd_ctrl.nfc_ctrl.nc = 1;
+	for (i = 0; i < PHYTIUM_NFC_ADDR_MAX_LEN; i++)
+		nfc_op->mem_addr_first[i] = (nfc->dma_phy_addr >> (8 * i)) & 0xFF;
+
+	/* The first dsp must have data to transfer */
+	memcpy(nfc->dma_buf, buf, mtd->writesize);
+	nfc_op->page_cnt = mtd->writesize;
+	nfc_op->cmd_ctrl.nfc_ctrl.dc = 1;
+
+	nfc_op++;
+	memcpy(nfc_op, nfc_op - 1, sizeof(struct phytium_nfc_op));
+	nfc_op->cmd_ctrl.nfc_ctrl.cmd_type = TYPE_PAGE_PRO;
+	nfc_op->cmd_ctrl.nfc_ctrl.dbc = 1;
+	nfc_op->cmd_ctrl.nfc_ctrl.auto_rs = 1;
+	nfc_op->cmd[0] = NAND_CMD_RNDIN;
+	nfc_op->cmd[1] = NAND_CMD_PAGEPROG;
+	memset(&nfc_op->addr, 0, PHYTIUM_NFC_ADDR_MAX_LEN);
+	nfc_op->addr_len = 2;
+	nfc_op->cmd_len = 2;
+	nfc_op->addr[0] = mtd->writesize + ecc_offset;
+	nfc_op->addr[1] = (mtd->writesize + ecc_offset) >> 8;
+	nfc_op->cmd_ctrl.nfc_ctrl.addr_cyc = 0x02;
+	nfc_op->page_cnt = phytium_nand_get_ecc_total(mtd, &chip->ecc);
+	nfc_op->cmd_ctrl.nfc_ctrl.nc = 0;
+	nfc_op->cmd_ctrl.nfc_ctrl.dc = 1;
+	nfc_op->cmd_ctrl.nfc_ctrl.ecc_en = 1;
+	for (i = 0; i < PHYTIUM_NFC_ADDR_MAX_LEN; i++)
+		nfc_op->mem_addr_first[i] =
+			((nfc->dma_phy_addr + mtd->writesize + ecc_offset) >> (8 * i)) & 0xFF;
+
+	/* when enable ECC, must offer ecc_offset of oob, but no oobdata */
+	nfc_op--;
+	phytium_nfc_prepare_cmd2(chip, nfc_op, direction, 2);
+	phytium_nfc_send_cmd2(chip, nfc_op, 2);
+	cond_delay(nfc_op->cle_ale_delay_ns);
+
+	ret = phytium_nfc_wait_op(chip, nfc_op->rdy_timeout_ms);
+	if (ret)
+		goto out;
+
+	cond_delay(nfc_op->rdy_delay_ns*1000);
+out:
+	kfree(nfc_op);
+	return ret;
+}
+
+static int phytium_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip,
+						u8 *buf, int oob_required, int page)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	u32 oob_len = oob_required ? mtd->oobsize : 0;
+	int ret;
+
+	ret = phytium_nand_page_read(mtd, chip, buf, NULL, 0, page, true);
+	if (oob_required)
+		ret = phytium_nand_oob_read(mtd, chip, NULL, chip->oob_poi,
+					    oob_len, page, true);
+
+	phytium_nfc_data_dump(to_phytium_nfc(chip->controller), buf, mtd->writesize);
+
+	return ret;
+}
+
+static int phytium_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
+{
+	int ret;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+
+	/* Invalidate page cache */
+	chip->pagecache.page = -1;
+	memset(chip->oob_poi, 0xFF, mtd->oobsize);
+
+	ret = phytium_nand_oob_read(mtd, chip, NULL, chip->oob_poi,
+				    mtd->oobsize, page, true);
+
+	phytium_nfc_data_dump(to_phytium_nfc(chip->controller), chip->oob_poi, mtd->oobsize);
+
+	return ret;
+}
+
+static int phytium_nfc_hw_ecc_bch_read_page(struct nand_chip *chip,
+					    u8 *buf, int oob_required, int page)
+{
+	int ret;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	u32  oob_len = oob_required ? mtd->oobsize : 0;
+	struct phytium_nand_chip *phytium_nand = NULL;
+
+	phytium_nand = to_phytium_nand(chip);
+
+	phytium_nfc_enable_hw_ecc(chip);
+	cond_delay(20*1000);
+
+	ret = phytium_nand_page_read_hwecc(mtd, chip, buf, NULL,
+					   0, page, true);
+
+	phytium_nfc_disable_hw_ecc(chip);
+
+	if (oob_required) {
+		oob_len = mtd->oobsize;
+		ret = phytium_nand_oob_read(mtd, chip, NULL, chip->oob_poi,
+					    oob_len, page, true);
+	}
+
+	phytium_nfc_data_dump(to_phytium_nfc(chip->controller), buf, mtd->writesize);
+
+	return ret;
+}
+
+static int phytium_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip,
+					    int page)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	u32 oob_len = mtd->oobsize;
+	int ret;
+
+	ret = phytium_nand_oob_read(mtd, chip, NULL, chip->oob_poi,
+				    oob_len, page, true);
+
+	phytium_nfc_data_dump(to_phytium_nfc(chip->controller), chip->oob_poi, oob_len);
+
+	return ret;
+}
+
+static int phytium_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip,
+						 const u8 *buf, int oob_required, int page)
+{
+	void *oob_buf = oob_required ? chip->oob_poi : NULL;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+
+	if (oob_required)
+		phytium_nand_oob_write(mtd, chip, NULL, oob_buf,
+				       mtd->oobsize, page, false);
+
+	return phytium_nand_page_write(mtd, chip, buf, NULL,
+				       0, page, false);
+}
+
+static int phytium_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
+					     const u8 *buf, int oob_required, int page)
+{
+	int ret;
+	void *oob_buf = oob_required ? chip->oob_poi : NULL;
+	u32 oob_len;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+
+	if (oob_required) {
+		oob_len = mtd->oobsize;
+		phytium_nand_oob_write(mtd, chip, NULL, oob_buf,
+				       oob_len, page, false);
+	}
+
+	phytium_nfc_enable_hw_ecc(chip);
+
+	cond_delay(20*1000);
+
+	ret = phytium_nand_page_write_hwecc(mtd, chip, buf, NULL,
+					    0, page, false);
+
+	phytium_nfc_disable_hw_ecc(chip);
+
+	return ret;
+}
+
+static int phytium_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip, int page)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	return phytium_nand_oob_write(mtd, chip, NULL, chip->oob_poi,
+				      mtd->oobsize, page, false);
+}
+
+static int phytium_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
+{
+	struct phytium_nand_chip *phytium_nand = to_phytium_nand(chip);
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	u32 oob_len = mtd->oobsize - phytium_nand->ecc.length;
+
+	return phytium_nand_oob_write(mtd, chip, NULL, chip->oob_poi,
+				      oob_len, page, false);
+}
+
+static int phytium_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
+					 struct nand_ecc_ctrl *ecc)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	if ((mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE))
+		return -ENOTSUPP;
+
+	chip->ecc.algo = NAND_ECC_ALGO_BCH;
+	ecc->read_page_raw = phytium_nfc_hw_ecc_bch_read_page_raw;
+	ecc->read_page = phytium_nfc_hw_ecc_bch_read_page;
+	ecc->read_oob_raw = phytium_nfc_hw_ecc_bch_read_oob_raw;
+	ecc->read_oob = phytium_nfc_hw_ecc_bch_read_oob;
+	ecc->write_page_raw = phytium_nfc_hw_ecc_bch_write_page_raw;
+	ecc->write_page = phytium_nfc_hw_ecc_bch_write_page;
+	ecc->write_oob_raw = phytium_nfc_hw_ecc_bch_write_oob_raw;
+	ecc->write_oob = phytium_nfc_hw_ecc_bch_write_oob;
+
+	return 0;
+}
+
+static int phytium_nand_ecc_init(struct mtd_info *mtd,
+				 struct nand_ecc_ctrl *ecc)
+{
+	int ret = 0;
+
+	mtd_set_ooblayout(mtd, &phytium_nand_ooblayout_ops);
+
+	switch (ecc->engine_type) {
+	case NAND_ECC_ENGINE_TYPE_ON_HOST:
+		ret = phytium_nand_hw_ecc_ctrl_init(mtd, ecc);
+		break;
+	case NAND_ECC_ENGINE_TYPE_NONE:
+		ecc->read_page_raw = phytium_nfc_hw_ecc_bch_read_page_raw;
+		ecc->read_oob_raw = phytium_nfc_hw_ecc_bch_read_oob;
+		ecc->write_page_raw = phytium_nfc_hw_ecc_bch_write_page_raw;
+		ecc->write_oob_raw = phytium_nfc_hw_ecc_bch_write_oob_raw;
+		ecc->read_page = ecc->read_page_raw;
+		ecc->read_oob = ecc->read_oob_raw;
+		ecc->write_page = ecc->write_page_raw;
+		ecc->write_oob = ecc->write_oob_raw;
+		break;
+	case NAND_ECC_ENGINE_TYPE_SOFT:
+	case NAND_ECC_ENGINE_TYPE_ON_DIE:
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static u8 bbt_pattern[] = {'P', 'H', 'Y', 'b', 't', '0' };
+static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'Y', 'H', 'P' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs =	8,
+	.len = 6,
+	.veroffs = 14,
+	.maxblocks = 8,	/* Last 8 blocks in each chip */
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs =	8,
+	.len = 6,
+	.veroffs = 14,
+	.maxblocks = 8,	/* Last 8 blocks in each chip */
+	.pattern = bbt_mirror_pattern
+};
+
+static int phytium_nand_attach_chip(struct nand_chip *chip)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	struct phytium_nand_chip *phytium_nand = to_phytium_nand(chip);
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	u32 value;
+	int ret = 0;
+
+	if (nfc->caps->flash_bbt)
+		chip->bbt_options |= NAND_BBT_USE_FLASH;
+
+	if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+		/*
+		 * We'll use a bad block table stored in-flash and don't
+		 * allow writing the bad block marker to the flash.
+		 */
+		chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
+		chip->bbt_td = &bbt_main_descr;
+		chip->bbt_md = &bbt_mirror_descr;
+	}
+
+	if (chip->options & NAND_BUSWIDTH_16)
+		phytium_nand->ndcr |= NDCR0_WIDTH;
+
+	/*
+	 * On small page NANDs, only one cycle is needed to pass the
+	 * column address.
+	 */
+	if (mtd->writesize <= 512)
+		phytium_nand->addr_cyc = 1;
+	else
+		phytium_nand->addr_cyc = 2;
+
+	/*
+	 * Now add the number of cycles needed to pass the row
+	 * address.
+	 *
+	 * Addressing a chip using CS 2 or 3 should also need the third row
+	 * cycle but due to inconsistance in the documentation and lack of
+	 * hardware to test this situation, this case is not supported.
+	 */
+	if (chip->options & NAND_ROW_ADDR_3)
+		phytium_nand->addr_cyc += 3;
+	else
+		phytium_nand->addr_cyc += 2;
+
+	if (nfc->caps) {
+		if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
+			chip->ecc.size = nfc->caps->ecc_step_size ?
+					 nfc->caps->ecc_step_size :
+					 chip->ecc.size;
+			chip->ecc.strength = nfc->caps->ecc_strength ?
+					     nfc->caps->ecc_strength :
+					     chip->ecc.strength;
+			chip->ecc.strength = nfc->caps->ecc_strength;
+			chip->ecc.bytes = 7;
+		} else {
+			chip->ecc.size = 512;
+			chip->ecc.strength = 1;
+			chip->ecc.bytes = 0;
+		}
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+	}
+
+	if (nfc->caps->hw_ver == 1) {
+		if (chip->ecc.strength == 0x04)
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(4);
+		else if (chip->ecc.strength == 0x02)
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(2);
+		else
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(0);
+	} else {
+		if (chip->ecc.strength == 0x08)
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(7);
+		else if (chip->ecc.strength == 0x04)
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(3);
+		else if (chip->ecc.strength == 0x02)
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(1);
+		else
+			phytium_nand->ndcr |= NDCR0_ECC_STREN(0);
+	}
+
+	value = phytium_read(nfc, NDCR0);
+	value &= ~NDCR0_EN;
+	phytium_write(nfc, NDCR0, value);
+
+	value &= ~NDCR0_ECC_STREN(7);
+	value |= phytium_nand->ndcr;
+	phytium_write(nfc, NDCR0, value | NDCR0_EN);
+
+	ret = phytium_nand_ecc_init(mtd, &chip->ecc);
+	if (ret) {
+		dev_err(nfc->dev, "ECC init failed: %d\n", ret);
+		goto out;
+	}
+
+	/*
+	 * Subpage write not available with hardware ECC, prohibit also
+	 * subpage read as in userspace subpage access would still be
+	 * allowed and subpage write, if used, would lead to numerous
+	 * uncorrectable ECC errors.
+	 */
+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
+		chip->options |= NAND_NO_SUBPAGE_WRITE;
+
+	/*
+	 * We keep the MTD name unchanged to avoid breaking platforms
+	 * where the MTD cmdline parser is used and the bootloader
+	 * has not been updated to use the new naming scheme.
+	 */
+	if (nfc->caps->legacy_of_bindings)
+		mtd->name = "phytium_nand-0";
+
+out:
+	return ret;
+}
+
+static int phytium_nfc_setup_interface(struct nand_chip *chip, int chipnr,
+					    const struct nand_interface_config *conf)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	unsigned int period_ns = 2;
+	const struct nand_sdr_timings *sdr;
+	struct phytium_nfc_timings nfc_tmg;
+	int read_delay;
+
+	sdr = nand_get_sdr_timings(conf);
+	if (IS_ERR(sdr))
+		return PTR_ERR(sdr);
+
+	nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
+	nfc_tmg.tRH = nfc_tmg.tRP;
+	nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
+	nfc_tmg.tWH = nfc_tmg.tWP;
+	nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
+	nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
+	nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
+	dev_info(nfc->dev, "[nfc_tmg]tRP: %d, tRH:%d, tWP:%d tWH:%d\n",
+		nfc_tmg.tRP, nfc_tmg.tRH, nfc_tmg.tWP, nfc_tmg.tWH);
+	dev_info(nfc->dev, "[nfc_tmg]tCS: %d, tCH:%d, tADL:%d\n",
+		nfc_tmg.tCS, nfc_tmg.tCH, nfc_tmg.tADL);
+
+	read_delay = sdr->tRC_min >= 30000 ?
+		MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH;
+
+	nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
+	nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
+				 period_ns) - 2,
+	nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
+				 period_ns);
+	dev_info(nfc->dev, "[nfc_tmg]tAR: %d, tWHR:%d, tRHW:%d\n",
+		nfc_tmg.tAR, nfc_tmg.tWHR, nfc_tmg.tRHW);
+
+	nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
+
+	if (chipnr < 0)
+		return 0;
+
+	if (nfc_tmg.tWP > 0x10)
+		nfc->timing_mode = ASY_MODE1;
+	else if (nfc_tmg.tWP < 0x0D)
+		nfc->timing_mode = ASY_MODE3;
+
+	if (nfc->inter_mode == ONFI_DDR)
+		nfc->timing_mode = SYN_MODE3;
+
+	phytium_nfc_default_data_interface(nfc);
+
+	return 0;
+}
+
+static const struct nand_controller_ops phytium_nand_controller_ops = {
+	.attach_chip = phytium_nand_attach_chip,
+	.exec_op = phytium_nfc_exec_op,
+	.setup_interface = phytium_nfc_setup_interface,
+};
+
+static void phytium_nand_chips_cleanup(struct phytium_nfc *nfc)
+{
+	struct phytium_nand_chip *entry, *temp;
+	int ret;
+
+	list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
+		ret = mtd_device_unregister(nand_to_mtd(&entry->chip));
+		WARN_ON(ret);
+		nand_cleanup(&entry->chip);
+		list_del(&entry->node);
+	}
+}
+
+static int phytium_nfc_init_dma(struct phytium_nfc *nfc)
+{
+	int ret;
+
+	ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(64));
+	if (ret)
+		return ret;
+
+	nfc->dsp_addr = dma_alloc_coherent(nfc->dev, PAGE_SIZE,
+					&nfc->dsp_phy_addr, GFP_KERNEL | GFP_DMA);
+	if (!nfc->dsp_addr)
+		return -ENOMEM;
+
+	nfc->dma_buf = dma_alloc_coherent(nfc->dev, MAX_CHUNK_SIZE,
+					&nfc->dma_phy_addr, GFP_KERNEL | GFP_DMA);
+	if (!nfc->dma_buf)
+		return -ENOMEM;
+
+	dev_info(nfc->dev, "NFC address dsp_phy_addr:%llx, dma_phy_addr:%llx\n",
+					nfc->dsp_phy_addr, nfc->dma_phy_addr);
+
+	return 0;
+}
+
+int phytium_nfc_init(struct phytium_nfc *nfc)
+{
+	u32 value;
+
+	nfc->inter_mode = ASYN_SDR;
+	nfc->timing_mode = ASY_MODE0;
+
+	value = phytium_read(nfc, NDCR1);
+	value &= (~NDCR1_SAMPL_PHASE(0xFFFF));
+	value &= ~NDCR1_ECC_DATA_FIRST_EN;
+	value |= NDCR1_SAMPL_PHASE(1);
+	value |= NDCR1_ECC_BYPASS;
+	phytium_write(nfc, NDCR1, value);
+	phytium_write(nfc, ND_INTERVAL_TIME, 1);
+	phytium_write(nfc, NDFIFO_LEVEL0, 4);
+	phytium_write(nfc, NDFIFO_LEVEL1, 4);
+	phytium_write(nfc, NDFIFO_CLR, 1);
+	phytium_write(nfc, ND_ERR_CLR, 1);
+
+	/* Configure the DMA  */
+	phytium_nfc_init_dma(nfc);
+
+
+
+	phytium_nfc_reset(nfc);
+
+	value = phytium_read(nfc, NDCR0);
+	value &= (~NDCR0_IN_MODE(3));
+	value |= NDCR0_IN_MODE(nfc->inter_mode);
+	value |= NDCR0_EN;
+
+	phytium_write(nfc, NDCR0, value);
+
+	nfc_ecc_errover = 0;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nfc_init);
+
+static int phytium_nand_chip_init(struct phytium_nfc *nfc)
+{
+	struct device *dev = nfc->dev;
+	struct phytium_nand_chip *phytium_nand;
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+	int ret;
+
+	/* Alloc the nand chip structure */
+	phytium_nand = devm_kzalloc(dev, sizeof(*phytium_nand), GFP_KERNEL);
+	if (!phytium_nand)
+		return -ENOMEM;
+
+	phytium_nand->nsels = 1;
+	phytium_nand->selected_die = -1;
+
+	chip = &phytium_nand->chip;
+	chip->controller = &nfc->controller;
+	chip->legacy.select_chip = phytium_nfc_select_chip;
+	phytium_nfc_default_data_interface(nfc);
+
+	mtd = nand_to_mtd(chip);
+	mtd->dev.parent = dev;
+	mtd->owner = THIS_MODULE;
+
+	/*
+	 * Default to HW ECC engine mode. If the nand-ecc-mode property is given
+	 * in the DT node, this entry will be overwritten in nand_scan_ident().
+	 */
+	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+
+	chip->options |= NAND_BUSWIDTH_AUTO;
+	chip->options |= NAND_SKIP_BBTSCAN;
+	chip->bbt_options |= NAND_BBT_NO_OOB;
+
+	ret = nand_scan(chip, phytium_nand->nsels);
+	if (ret) {
+		dev_err(dev, "could not scan the nand chip\n");
+		goto out;
+	}
+
+	if (nfc->caps->parts) {
+		ret = mtd_device_register(mtd, nfc->caps->parts, nfc->caps->nr_parts - 1);
+	} else if (dev->of_node) {
+		nand_set_flash_node(chip, dev->of_node);
+		ret = mtd_device_register(mtd, NULL, 0);
+	} else {
+		ret = -EINVAL;
+	}
+
+	if (ret) {
+		dev_err(dev, "failed to register mtd device: %d\n", ret);
+		nand_cleanup(chip);
+		return ret;
+	}
+
+	phytium_nand->ecc.length = phytium_nand_get_ecc_total(mtd, &chip->ecc);
+	phytium_nand->ecc.offset = mtd->oobsize - phytium_nand->ecc.length;
+	chip->ecc.total = phytium_nand_get_ecc_total(mtd, &chip->ecc);
+
+	mtd_ooblayout_ecc(mtd, 0, &phytium_nand->ecc);
+
+	dev_info(dev, "ooblayout ecc offset: %x, length: %x\n",
+		 phytium_nand->ecc.offset, phytium_nand->ecc.length);
+
+out:
+	list_add_tail(&phytium_nand->node, &nfc->chips);
+	return 0;
+}
+
+int phytium_nand_init(struct phytium_nfc *nfc)
+{
+	int ret;
+
+	nand_controller_init(&nfc->controller);
+	nfc->controller.ops = &phytium_nand_controller_ops;
+	INIT_LIST_HEAD(&nfc->chips);
+
+	/* Init the controller and then probe the chips */
+	ret = phytium_nfc_init(nfc);
+	if (ret)
+		goto out;
+
+	ret = phytium_nand_chip_init(nfc);
+	if (ret)
+		goto out;
+
+	spin_lock_init(&nfc->spinlock);
+
+out:
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phytium_nand_init);
+
+int phytium_nand_remove(struct phytium_nfc *nfc)
+{
+	phytium_nand_chips_cleanup(nfc);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nand_remove);
+
+static int phytium_nfc_wait_ndrun(struct nand_chip *chip)
+{
+	struct phytium_nfc *nfc = to_phytium_nfc(chip->controller);
+	int ret = 0;
+	u32 val;
+
+	ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
+					 (val & NDSR_RB) == 0,
+					 0, 100 * 1000);
+	if (ret) {
+		dev_err(nfc->dev, "Timeout on NAND controller run mode\n");
+		ret = -EAGAIN;
+	}
+
+	return ret;
+}
+
+int phytium_nand_prepare(struct phytium_nfc *nfc)
+{
+	struct phytium_nand_chip *chip = NULL;
+
+	list_for_each_entry(chip, &nfc->chips, node)
+		phytium_nfc_wait_ndrun(&chip->chip);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nand_prepare);
+
+int phytium_nand_resume(struct phytium_nfc *nfc)
+{
+	nfc->selected_chip = NULL;
+	phytium_nfc_init(nfc);
+	phytium_nfc_default_data_interface(nfc);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_nand_resume);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium NAND controller platform driver");
+MODULE_AUTHOR("Zhu Mingshuai <zhumingshuai@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand.h b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand.h
new file mode 100644
index 00000000000000..963d555a2aca00
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand.h
@@ -0,0 +1,449 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium NAND flash controller driver
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+#ifndef PHYTIUM_NAND_H
+#define PHYTIUM_NAND_H
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/of_platform.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <asm/unaligned.h>
+#include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
+#include <linux/mtd/partitions.h>
+
+/* NFC does not support transfers of larger chunks at a time */
+#define MAX_PAGE_NUM		16
+#define MAX_CHUNK_SIZE		((1024 + 76) * 16)
+
+#define POLL_PERIOD		0
+#define POLL_TIMEOUT		100000
+/* Interrupt maximum wait period in ms */
+#define IRQ_TIMEOUT		1000
+
+/* Latency in clock cycles between SoC pins and NFC logic */
+#define MIN_RD_DEL_CNT		3
+
+#define PHYTIUM_NFC_ADDR_MAX_LEN 5
+#define PHYTIUM_NFC_DSP_SIZE     16
+
+/* NAND controller flash control register */
+#define NDCR0			0x00
+#define NDCR0_EN		BIT(0)
+#define NDCR0_WIDTH		BIT(1)
+#define NDCR0_IN_MODE(x)	(min_t(u32, x, 0x3) << 2)
+#define NDCR0_ECC_EN		BIT(4)
+#define NDCR0_ECC_STREN(x)	(min_t(u32, x, 0x7) << 5)
+#define NDCR0_SPARE_EN		BIT(8)
+#define NDCR0_SPARE_SIZE(x)	(min_t(u32, x, 0xFFF) << 9)
+#define NDCR0_GENERIC_FIELDS_MASK
+
+#define NDCR1			0x04
+#define NDCR1_SAMPL_PHASE(x)	min_t(u32, x, 0xFFFF)
+#define NDCR1_ECC_DATA_FIRST_EN BIT(16)
+#define NDCR1_RB_SHARE_EN       BIT(17)
+#define NDCR1_ECC_BYPASS        BIT(18)
+
+#define NDAR0			0x08
+
+#define NDAR1			0x0C
+#define NDAR1_H8(x)		min_t(u32, x, 0xFF)
+#define NDAR1_DMA_EN		BIT(8)
+#define NDAR1_EMPTY(x)		(min_t(u32, x, 0x7F) << 9)
+#define NDAR1_DMA_RLEN(x)	(min_t(u32, x, 0xFF) << 9)
+#define NDAR1_DMA_WLEN(x)	(min_t(u32, x, 0xFF) << 9)
+
+#define NDTR0			0x10
+#define NDTR0_TCS_TCLS(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR0_TCLS_TWP(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR1			0x14
+#define NDTR1_TWH(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR1_TWP(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR2			0x18
+#define NDTR2_TCH_TCLH(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR2_TCLH_TWH(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR3			0x1c
+#define NDTR3_TDQ_EN(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR3_TCH_TWH(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR4			0x20
+#define NDTR4_TWHR_SMX(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR4_TREH(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR5			0x24
+#define NDTR5_TRC(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR5_TADL_SMX(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR6			0x28
+#define NDTR6_TCAD_TCS_SMX(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR6_RES(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR7			0x2c
+#define NDTR7_TCK(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR7_TDQ_EN(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR8			0x30
+#define NDTR8_TCAD_TCK_SMX(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR8_HF_TCK(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR9			0x34
+#define NDTR9_TWHR(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR9_TCCS_TCALS_SMX(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR10			0x38
+#define NDTR10_TCK(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR10_MTCK(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR11			0x3c
+#define NDTR11_TCK_TCALS(x)	(min_t(u32, x, 0xFFFF) << 16)
+#define NDTR11_RES(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR12			0x40
+#define NDTR12_TWRCK(x)		(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR12_RES(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR13			0x44
+#define NDTR13_TWRHCA(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR13_TRLCA(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR14			0x48
+#define NDTR14_TWRHCE(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR14_RES(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR15			0x4c
+#define NDTR15_TCDQSS_TWPRE_TDS(x) (min_t(u32, x, 0xFFFF) << 0)
+#define NDTR15_HFTDSC(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR16			0x50
+#define NDTR16_TWPST_TDH(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR16_TWPSTH(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR17			0x54
+#define NDTR17_TCS_TRPRE(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR17_TRELDQS(x)	(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDTR18			0x58
+#define NDTR18_TRPST_TDQSRE(x)	(min_t(u32, x, 0xFFFF) << 0)
+#define NDTR18_RES(x)		(min_t(u32, x, 0xFFFF) << 16)
+
+#define NDFIFO			0x5c
+#define NDFIFO_REV		(min_t(u32, x, 0) << 12)
+#define NDFIFO_FULL		BIT(11)
+#define NDFIFO_EMP		BIT(10)
+#define NDFIFO_CNT(x)		(min_t(u32, x, 0x3F) << 0)
+
+#define ND_INTERVAL_TIME	0x60
+#define NDCMD_INTERVAL_TIME	0x64
+#define NDFIFO_TIMEOUT		0x68
+#define NDFIFO_LEVEL0		0x6c
+#define NDFIFO_LEVEL1		0x70
+#define NDWP			0x74
+#define NDFIFO_CLR		0x78
+
+#define NDSR			0x7c
+#define NDSR_BUSY		BIT(0)
+#define NDSR_DMA_BUSY		BIT(1)
+#define NDSR_DMA_PGFINISH	BIT(2)
+#define NDSR_DMA_FINISH		BIT(3)
+#define NDSR_FIFO_EMP		BIT(4)
+#define NDSR_FIFO_FULL		BIT(5)
+#define NDSR_FIFO_TIMEOUT	BIT(6)
+#define NDSR_CS(x)		(min_t(u32, x, 0xF) << 7)
+#define NDSR_CMD_PGFINISH	BIT(11)
+#define NDSR_PG_PGFINISH	BIT(12)
+#define NDSR_RE			BIT(13)
+#define NDSR_DQS		BIT(14)
+#define NDSR_RB			BIT(15)
+#define NDSR_ECC_BUSY		BIT(16)
+#define NDSR_ECC_FINISH		BIT(17)
+#define NDSR_ECC_RIGHT		BIT(18)
+#define NDSR_ECC_ERR		BIT(19)
+#define NDSR_ECC_ERROVER	BIT(20)
+#define NDSR_AXI_DSP_ERR	BIT(21)
+#define NDSR_AXI_RD_ERR		BIT(22)
+#define NDSR_AXI_WR_ERR		BIT(23)
+#define NDSR_RB_STATUS(x)       (min_t(u32, x, 0xF) << 24)
+#define NDSR_PROT_ERR           BIT(28)
+#define NDSR_ECC_BYPASS         BIT(29)
+
+#define NDIR_MASK		0x80
+#define NDIR_BUSY_MASK		BIT(0)
+#define NDIR_DMA_BUSY_MASK	BIT(1)
+#define NDIR_DMA_PGFINISH_MASK	BIT(2)
+#define NDIR_DMA_FINISH_MASK	BIT(3)
+#define NDIR_FIFO_EMP_MASK	BIT(4)
+#define NDIR_FIFO_FULL_MASK	BIT(5)
+#define NDIR_FIFO_TIMEOUT_MASK	BIT(6)
+#define NDIR_CMD_FINISH_MASK	BIT(7)
+#define NDIR_PGFINISH_MASK	BIT(8)
+#define NDIR_RE_MASK		BIT(9)
+#define NDIR_DQS_MASK		BIT(10)
+#define NDIR_RB_MASK		BIT(11)
+#define NDIR_ECC_FINISH_MASK	BIT(12)
+#define NDIR_ECC_ERR_MASK	BIT(13)
+
+#define NDIR			0x84
+#define NDIR_ALL_INT(x)		GENMASK(x, 0)
+#define NDIR_BUSY		BIT(0)
+#define NDIR_DMA_BUSY		BIT(1)
+#define NDIR_DMA_PGFINISH	BIT(2)
+#define NDIR_DMA_FINISH		BIT(3)
+#define NDIR_FIFO_EMP		BIT(4)
+#define NDIR_FIFO_FULL		BIT(5)
+#define NDIR_FIFO_TIMEOUT	BIT(6)
+#define NDIR_CMD_FINISH		BIT(7)
+#define NDIR_PGFINISH		BIT(8)
+#define NDIR_RE			BIT(9)
+#define NDIR_DQS		BIT(10)
+#define NDIR_RB			BIT(11)
+#define NDIR_ECC_FINISH		BIT(12)
+#define NDIR_ECC_ERR		BIT(13)
+
+#define ND_DEBUG		0x88
+
+#define ND_ERR_CLR		0x8c
+#define ND_DSP_ERR_CLR		BIT(0)
+#define ND_AXI_RD_ERR_CLR	BIT(1)
+#define ND_AXI_WR_ERR_CLR	BIT(2)
+#define ND_ECC_ERR_CLR		BIT(3)
+
+#define NDCR_PAGE_SZ(x)		(x >= 2048 ? BIT(24) : 0)
+
+enum nand_inter_pro {
+	NAND_ONFI,
+	NAND_JEDEC,
+	NAND_OTHER,
+};
+
+enum nand_inter_mode {
+	ASYN_SDR,
+	ONFI_DDR,
+	TOG_ASYN_DDR,
+};
+
+enum asy_timing_mode {
+	ASY_MODE0,
+	ASY_MODE1,
+	ASY_MODE2,
+	ASY_MODE3,
+	ASY_MODE4,
+};
+
+enum onfi_syn_timing_mode {
+	SYN_MODE0 = 0x10,
+	SYN_MODE1,
+	SYN_MODE2,
+	SYN_MODE3,
+	SYN_MODE4,
+};
+
+/**
+ * NAND controller timings expressed in NAND Controller clock cycles
+ *
+ * @tRP:	ND_nRE pulse width
+ * @tRH:	ND_nRE high duration
+ * @tWP:	ND_nWE pulse time
+ * @tWH:	ND_nWE high duration
+ * @tCS:	Enable signal setup time
+ * @tCH:	Enable signal hold time
+ * @tADL:	Address to write data delay
+ * @tAR:	ND_ALE low to ND_nRE low delay
+ * @tWHR:	ND_nWE high to ND_nRE low for status read
+ * @tRHW:	ND_nRE high duration, read to write delay
+ * @tR:		ND_nWE high to ND_nRE low for read
+ */
+struct phytium_nfc_timings {
+	u16 tRP;
+	u16 tRH;
+	u16 tWP;       /* NDTR1_TWP */
+	u16 tWH;       /* NDTR1_TWH */
+	u16 tCS;
+	u16 tCH;
+	u16 tADL;
+	u16 tAR;
+	u16 tWHR;
+	u16 tRHW;
+	u16 tR;
+};
+
+/**
+ * NAND chip structure: stores NAND chip device related information
+ *
+ * @chip:		Base NAND chip structure
+ * @node:		Used to store NAND chips into a list
+ * @ndcr:		Controller register value for this NAND chip
+ * @ndtr0:		Timing registers 0 value for this NAND chip
+ * @ndtr1:		Timing registers 1 value for this NAND chip
+ * @selected_die:	Current active CS
+ * @nsels:		Number of CS lines required by the NAND chip
+ */
+struct phytium_nand_chip {
+	struct nand_chip chip;
+	struct list_head node;
+	u32 ndcr;
+	u32 ndtr0;
+	u32 ndtr1;
+	int addr_cyc;
+	int selected_die;
+	unsigned int nsels;
+	struct mtd_oob_region ecc;
+};
+
+/**
+ * NAND controller capabilities for distinction between compatible strings
+ *
+ * @max_cs_nb:		Number of Chip Select lines available
+ * @max_rb_nb:		Number of Ready/Busy lines available
+ * @legacy_of_bindings:	Indicates if DT parsing must be done using the old
+ *			fashion way
+ * @flash_bbt:
+ * @ecc_strength:
+ * @ecc_step_size:
+ * @parts:
+ * @nr_parts:
+ */
+struct phytium_nfc_caps {
+	unsigned int hw_ver;
+	unsigned int int_mask_bits;
+	unsigned int max_cs_nb;
+	unsigned int max_rb_nb;
+	bool legacy_of_bindings;
+	bool flash_bbt;
+	int ecc_strength;
+	int ecc_step_size;
+	struct mtd_partition *parts;
+	unsigned int nr_parts;
+};
+
+/**
+ * NAND controller structure: stores Marvell NAND controller information
+ *
+ * @controller:		Base controller structure
+ * @dev:		Parent device (used to print error messages)
+ * @regs:		NAND controller registers
+ * @reg_clk:		Regiters clock
+ * @complete:		Completion object to wait for NAND controller events
+ * @chips:		List containing all the NAND chips attached to
+ *			this NAND controller
+ * @caps:		NAND controller capabilities for each compatible string
+ * @dma_buf:		32-bit aligned buffer for DMA transfers (NFCv1 only)
+ */
+struct phytium_nfc {
+	struct nand_controller controller;
+	struct device *dev;
+	void __iomem *regs;
+	int irq;
+	struct list_head chips;
+	struct nand_chip *selected_chip;
+	struct phytium_nfc_caps *caps;
+
+	void *dsp_addr;
+	dma_addr_t dsp_phy_addr;
+
+	void *dma_buf;
+	u32 dma_offset;
+	dma_addr_t dma_phy_addr;
+
+	enum nand_inter_pro inter_pro;
+	enum nand_inter_mode inter_mode;
+	u32 timing_mode;
+
+	spinlock_t spinlock;
+};
+
+/**
+ * Derives a duration in numbers of clock cycles.
+ *
+ * @ps: Duration in pico-seconds
+ * @period_ns:  Clock period in nano-seconds
+ *
+ * Convert the duration in nano-seconds, then divide by the period and
+ * return the number of clock periods.
+ */
+#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns))
+#define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \
+						     period_ns))
+
+struct phytium_nfc_cmd_ctrl {
+	u16 csel:4;
+	u16 dbc:1;
+	u16 addr_cyc:3;
+	u16 nc:1;
+#define TYPE_RESET         0x00
+#define TYPE_SET_FTR       0x01
+#define TYPE_GET_FTR       0x02
+#define TYPE_READ_ID       0x03
+#define TYPE_PAGE_PRO      0x04
+#define TYPE_ERASE         0x05
+#define TYPE_READ          0x06
+#define TYPE_TOGGLE        0x07
+#define TYPE_READ_PARAM    0x02
+#define TYPE_READ_STATUS   0x03
+#define TYPE_CH_READ_COL   0x03
+#define TYPE_CH_ROW_ADDR   0x01
+#define TYPE_CH_WR_COL     0x01
+	u16 cmd_type:4;
+	u16 dc:1;
+	u16 auto_rs:1;
+	u16 ecc_en:1;
+};
+
+/**
+ * NAND driver structure filled during the parsing of the ->exec_op() subop
+ * subset of instructions.
+ *
+ * @cle_ale_delay_ns:	Optional delay after the last CMD or ADDR cycle
+ * @rdy_timeout_ms:	Timeout for waits on Ready/Busy pin
+ * @rdy_delay_ns:	Optional delay after waiting for the RB pin
+ * @data_delay_ns:	Optional delay after the data xfer
+ * @data_instr_idx:	Index of the data instruction in the subop
+ * @data_instr:		Pointer to the data instruction in the subop
+ */
+struct phytium_nfc_op {
+	u8 cmd[2];
+	union {
+		u16 ctrl;
+		struct phytium_nfc_cmd_ctrl nfc_ctrl;
+	} cmd_ctrl;
+	u8 addr[PHYTIUM_NFC_ADDR_MAX_LEN];
+	u16 page_cnt;
+	u8 mem_addr_first[PHYTIUM_NFC_ADDR_MAX_LEN];
+
+	u32 cmd_len;
+	u32 addr_len;
+
+	u32 cle_ale_delay_ns;
+	u32 rdy_timeout_ms;
+	u32 rdy_delay_ns;
+	u32 data_delay_ns;
+	u32 data_instr_idx;
+	struct nand_op_instr *data_instr;
+} __attribute__ ((__packed__));
+
+#define TIMING_ASY_NUM 12
+#define TIMING_SYN_NUM 14
+#define TIMING_TOG_NUM 12
+
+#define TMP_DMA_DEBUG 0    /* Temporary dma space */
+
+int phytium_nand_init(struct phytium_nfc *nfc);
+int phytium_nand_remove(struct phytium_nfc *nfc);
+int phytium_nand_prepare(struct phytium_nfc *nfc);
+int phytium_nand_suspend(struct phytium_nfc *nfc);
+int phytium_nand_resume(struct phytium_nfc *nfc);
+
+irqreturn_t phytium_nfc_isr(int irq, void *dev_id);
+
+#endif /* NAND_PHYTIUM_NAND_H */
diff --git a/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand_pci.c b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand_pci.c
new file mode 100644
index 00000000000000..6ce76dd15161a1
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand_pci.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCI driver for Phytium NAND flash controller
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/device.h>
+
+#include "phytium_nand.h"
+
+#define DRV_NAME	"phytium_nand_pci"
+
+static struct mtd_partition partition_info[] = {
+	{
+		.name = "Flash partition 1",
+		.offset =  0x0000000,
+		.size =    0x4000000 },
+	{
+		.name = "Flash partition 2",
+		.offset =  0x4000000,
+		.size =    0x8000000 },
+	{
+		.name = "Flash partition 3",
+		.offset =  0x8000000,
+		.size =    0x10000000 },
+	{
+		.name = "Flash partition 4",
+		.offset =  0x10000000,
+		.size =    0x12000000 },
+	{
+		.name = "Flash partition 5",
+		.offset =  0x12000000,
+		.size =    0x14000000 },
+};
+
+static struct phytium_nfc_caps x100_nfc_caps = {
+	.hw_ver = 1,
+	.int_mask_bits = 13,
+	.max_cs_nb = 2,
+	.max_rb_nb = 1,
+	.legacy_of_bindings = true,
+	.ecc_strength = 4,
+	.ecc_step_size = 512,
+	.nr_parts = 5,
+	.parts = partition_info,
+};
+
+static int phytium_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
+{
+	struct phytium_nfc *nfc;
+	int ret;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	ret = pcim_iomap_regions(pdev, 0x1, pci_name(pdev));
+	if (ret) {
+		dev_err(&pdev->dev, "I/O memory remapping failed\n");
+		return ret;
+	}
+
+	pci_set_master(pdev);
+	pci_try_set_mwi(pdev);
+
+	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
+	if (ret)
+		return ret;
+
+	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
+	if (ret)
+		return ret;
+
+	nfc = devm_kzalloc(&pdev->dev, sizeof(struct phytium_nfc),
+			   GFP_KERNEL);
+	if (!nfc)
+		return -ENOMEM;
+
+	nfc->dev = &pdev->dev;
+	nfc->regs = pcim_iomap_table(pdev)[0];
+	nfc->irq = pdev->irq;
+	nfc->caps = &x100_nfc_caps;
+
+	ret = devm_request_irq(nfc->dev, nfc->irq, phytium_nfc_isr,
+			       IRQF_SHARED, "phytium-nfc-pci", nfc);
+	if (ret) {
+		dev_err(nfc->dev, "Failed to register NFC interrupt.\n");
+		return ret;
+	}
+
+	ret = phytium_nand_init(nfc);
+	if (ret)
+		return ret;
+
+	pci_set_drvdata(pdev, nfc);
+
+	return ret;
+}
+
+static void phytium_pci_remove(struct pci_dev *pdev)
+{
+	struct phytium_nfc *nfc = pci_get_drvdata(pdev);
+	int ret;
+
+	ret = phytium_nand_remove(nfc);
+	if (ret)
+		dev_warn(&pdev->dev, "can't remove device properly: %d\n", ret);
+}
+
+static int __maybe_unused phytium_nfc_prepare(struct device *dev)
+{
+	struct pci_dev *pci = to_pci_dev(dev);
+	struct phytium_nfc *nfc = pci_get_drvdata(pci);
+	int ret;
+
+	ret = phytium_nand_prepare(nfc);
+
+	return 0;
+}
+
+static int __maybe_unused phytium_nfc_resume(struct device *dev)
+{
+	struct pci_dev *pci = to_pci_dev(dev);
+	struct phytium_nfc *nfc = pci_get_drvdata(pci);
+	int ret;
+
+	ret = phytium_nand_resume(nfc);
+
+	return ret;
+}
+
+static const struct dev_pm_ops phytium_pci_dev_pm_ops = {
+	.prepare = phytium_nfc_prepare,
+	.resume = phytium_nfc_resume,
+};
+
+static const struct pci_device_id phytium_pci_id_table[] = {
+	{ PCI_VDEVICE(PHYTIUM, 0xdc29) },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, phytium_pci_id_table);
+
+static struct pci_driver phytium_pci_driver = {
+	.name		= DRV_NAME,
+	.id_table	= phytium_pci_id_table,
+	.probe		= phytium_pci_probe,
+	.remove		= phytium_pci_remove,
+	.driver	= {
+		.pm	= &phytium_pci_dev_pm_ops,
+	},
+};
+module_pci_driver(phytium_pci_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PCI driver for Phytium NAND controller");
+MODULE_AUTHOR("Zhu Mingshuai <zhumingshuai@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand_plat.c b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand_plat.c
new file mode 100644
index 00000000000000..b3fde07b4aeb18
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mtd/nand/raw/phytium_nand_plat.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Core driver for Phytium NAND flash controller
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/acpi.h>
+#include <linux/acpi_dma.h>
+
+#include "phytium_nand.h"
+
+#define DRV_NAME	"phytium_nand_plat"
+
+static int phytium_nfc_plat_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *r;
+	struct phytium_nfc *nfc;
+	unsigned int ecc_strength;
+	unsigned int ecc_step_size;
+	int ret;
+
+	nfc = devm_kzalloc(&pdev->dev, sizeof(struct phytium_nfc),
+			   GFP_KERNEL);
+	if (!nfc)
+		return -ENOMEM;
+
+	nfc->dev = dev;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	nfc->regs = devm_ioremap_resource(dev, r);
+	if (IS_ERR(nfc->regs))
+		return PTR_ERR(nfc->regs);
+
+	dev_info(nfc->dev, "NFC register address :%p, phy address:%llx\n",
+				nfc->regs, r->start);
+
+	nfc->irq = platform_get_irq(pdev, 0);
+	if (nfc->irq < 0) {
+		dev_err(dev, "failed to retrieve irq\n");
+		return nfc->irq;
+	}
+
+	ret = devm_request_irq(dev, nfc->irq, phytium_nfc_isr, 0,
+			       "phytium-nfc-plat", nfc);
+	if (ret) {
+		dev_err(nfc->dev, "Failed to register NFC interrupt.\n");
+		return ret;
+	}
+
+	nfc->caps = devm_kzalloc(dev, sizeof(struct phytium_nfc_caps), GFP_KERNEL);
+	if (!nfc->caps)
+		return -ENOMEM;
+
+	/* Currently hard-coded parameters */
+	nfc->caps->hw_ver = 2;
+	nfc->caps->int_mask_bits = 17;
+	nfc->caps->max_cs_nb = 4;
+	nfc->caps->max_rb_nb = 4;
+	nfc->caps->nr_parts = 0;
+	nfc->caps->parts = NULL;
+
+	device_property_read_u32(&pdev->dev, "nand-ecc-strength", &ecc_strength);
+	nfc->caps->ecc_strength = ecc_strength ? ecc_strength : 8;
+
+	device_property_read_u32(&pdev->dev, "nand-ecc-step-size", &ecc_step_size);
+	nfc->caps->ecc_step_size = ecc_step_size ? ecc_step_size : 512;
+
+	ret = phytium_nand_init(nfc);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, nfc);
+
+	return ret;
+}
+
+static int phytium_nfc_plat_remove(struct platform_device *pdev)
+{
+	struct phytium_nfc *nfc = platform_get_drvdata(pdev);
+
+	return phytium_nand_remove(nfc);
+}
+
+static int __maybe_unused phytium_nfc_plat_prepare(struct device *dev)
+{
+	struct phytium_nfc *nfc = dev_get_drvdata(dev);
+
+	return phytium_nand_prepare(nfc);
+}
+
+static int __maybe_unused phytium_nfc_plat_resume(struct device *dev)
+{
+	struct phytium_nfc *nfc = dev_get_drvdata(dev);
+	int ret;
+
+	ret = phytium_nand_resume(nfc);
+
+	return ret;
+}
+
+static const struct dev_pm_ops phytium_dev_pm_ops = {
+	.prepare = phytium_nfc_plat_prepare,
+	.resume = phytium_nfc_plat_resume,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id phytium_nfc_of_ids[] = {
+	{ .compatible = "phytium,nfc", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, phytium_nfc_of_ids);
+#endif
+
+static struct platform_driver phytium_nfc_plat_driver = {
+	.driver	= {
+		.name		= DRV_NAME,
+		.of_match_table = phytium_nfc_of_ids,
+		.pm		= &phytium_dev_pm_ops,
+	},
+	.probe = phytium_nfc_plat_probe,
+	.remove	= phytium_nfc_plat_remove,
+};
+module_platform_driver(phytium_nfc_plat_driver)
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium NAND controller Platform driver");
+MODULE_AUTHOR("Zhu Mingshuai <zhumingshuai@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/drivers/mtd/spi-nor/boya.c b/target/linux/phytium/files-5.10/drivers/mtd/spi-nor/boya.c
new file mode 100644
index 00000000000000..db8c0c21866524
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mtd/spi-nor/boya.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ */
+
+#include <linux/mtd/spi-nor.h>
+
+#include "core.h"
+
+static const struct flash_info boya_parts[] = {
+	/* Boya Microelectronics Memory Series */
+	{ "by25q64as",  INFO(0x684017, 0, 64 * 1024,  128, SECT_4K) },
+	{ "by25q128as", INFO(0x684018, 0, 64 * 1024,  256, SECT_4K) },
+};
+
+const struct spi_nor_manufacturer spi_nor_boya = {
+	.name = "boya",
+	.parts = boya_parts,
+	.nparts = ARRAY_SIZE(boya_parts),
+};
diff --git a/target/linux/phytium/files-5.10/drivers/mtd/spi-nor/controllers/phytium-quadspi.c b/target/linux/phytium/files-5.10/drivers/mtd/spi-nor/controllers/phytium-quadspi.c
new file mode 100644
index 00000000000000..67937d8b69905a
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/mtd/spi-nor/controllers/phytium-quadspi.c
@@ -0,0 +1,1024 @@
+/*
+ * Phytium SPI core controller driver.
+ *
+ * Copyright (c) 2019-2023 Phytium Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/sizes.h>
+#include <linux/spinlock.h>
+#include <linux/swab.h>
+#include <linux/acpi.h>
+
+#define QSPI_FLASH_CAP_REG   0x000
+#define QSPI_RD_CFG_REG      0x004
+#define QSPI_WR_CFG_REG      0x008
+#define QSPI_FLUSH_REG       0x00C
+#define QSPI_CMD_PORT_REG    0x010
+#define QSPI_ADDR_PORT_REG   0x014
+#define QSPI_HD_PORT_REG     0x018
+#define QSPI_LD_PORT_REG     0x01C
+#define QSPI_FUN_SET_REG     0x020
+#define QSPI_WIP_REG         0x024
+#define QSPI_WP_REG          0x028
+#define QSPI_MODE_REG        0x02C
+
+#define QSPI_FLASH_CAP_NUM_SHIFT	3
+#define QSPI_FLASH_CAP_NUM_MASK		(0x3 << QSPI_FLASH_CAP_NUM_SHIFT)
+#define QSPI_FLASH_CAP_CAP_SHIFT	0
+#define QSPI_FLASH_CAP_CAP_MASK		(0x7 << QSPI_FLASH_CAP_CAP_SHIFT)
+
+#define QSPI_RD_CFG_RD_CMD_SHIFT	24
+#define QSPI_RD_CFG_RD_CMD_MASK		(0xFF << QSPI_RD_CFG_RD_CMD_SHIFT)
+#define QSPI_RD_CFG_RD_THROUGH_SHIFT	23
+#define QSPI_RD_CFG_RD_THROUGH_MASK	(0x01 << QSPI_RD_CFG_RD_THROUGH_SHIFT)
+#define QSPI_RD_CFG_RD_TRANSFER_SHIFT	20
+#define QSPI_RD_CFG_RD_TRANSFER_MASK	(0x07 << QSPI_RD_CFG_RD_TRANSFER_SHIFT)
+#define QSPI_RD_CFG_RD_ADDR_SEL_SHIFT	19
+#define QSPI_RD_CFG_RD_ADDR_SEL_MASK	(0x1 << QSPI_RD_CFG_RD_ADDR_SEL_SHIFT)
+#define QSPI_RD_CFG_RD_LATENCY_SHIFT	18
+#define QSPI_RD_CFG_RD_LATENCY_MASK	(0x1 << QSPI_RD_CFG_RD_LATENCY_SHIFT)
+#define QSPI_RD_CFG_MODE_BYTE_SHIFT	17
+#define QSPI_RD_CFG_MODE_BYTE_MASK	(0x1 << QSPI_RD_CFG_MODE_BYTE_SHIFT)
+#define QSPI_RD_CFG_CMD_SIGN_SHIFT	9
+#define QSPI_RD_CFG_CMD_SIGN_MASK	(0xFF << QSPI_RD_CFG_CMD_SIGN_SHIFT)
+#define QSPI_RD_CFG_DUMMY_SHIFT		4
+#define QSPI_RD_CFG_DUMMY_MASK		(0x1F << QSPI_RD_CFG_DUMMY_SHIFT)
+#define QSPI_RD_CFG_D_BUFFER_SHIFT	3
+#define QSPI_RD_CFG_D_BUFFER_MASK	(0x1 << QSPI_RD_CFG_D_BUFFER_SHIFT)
+#define QSPI_RD_CFG_RD_SCK_SEL_SHIFT	0
+#define QSPI_RD_CFG_RD_SCK_SEL_MASK	(0x3 << QSPI_RD_CFG_RD_SCK_SEL_SHIFT)
+
+#define QSPI_WR_CFG_WR_CMD_SHIFT	24
+#define QSPI_WR_CFG_WR_CMD_MASK		(0xFF << QSPI_WR_CFG_WR_CMD_SHIFT)
+#define QSPI_WR_CFG_WR_WAIT_SHIFT	9
+#define QSPI_WR_CFG_WR_WAIT_MASK	(0x01 << QSPI_WR_CFG_WR_WAIT_SHIFT)
+#define QSPI_WR_CFG_WR_THROUGH_SHIFT	8
+#define QSPI_WR_CFG_WR_THROUGH_MAS	(0x01 << QSPI_WR_CFG_WR_THROUGH_SHIFT)
+#define QSPI_WR_CFG_WR_TRANSFER_SHIFT	5
+#define QSPI_WR_CFG_WR_TRANSFER_MASK	(0X7 << QSPI_WR_CFG_WR_TRANSFER_SHIFT)
+#define QSPI_WR_CFG_WR_ADDR_SEL_SHIFT	4
+#define QSPI_WR_CFG_WR_ADDR_SEL_MASK	(0x1 << QSPI_WR_CFG_WR_ADDR_SEL_SHIFT)
+#define QSPI_WR_CFG_WR_MODE_SHIFT	3
+#define QSPI_WR_CFG_WR_MODE		(0x01 << QSPI_WR_CFG_WR_MODE_SHIFT)
+#define QSPI_WR_CFG_WR_SCK_SEL_SHIFT	0
+#define QSPI_WR_CFG_WR_SCK_SEL_MASK	(0x7 << QSPI_WR_CFG_WR_SCK_SEL_SHIFT)
+
+#define QSPI_FLUSH_EN			(0x1 << 0)
+
+#define QSPI_CMD_PORT_CMD_SHIFT		24
+#define QSPI_CMD_PORT_CMD_MASK		(0xFF << QSPI_CMD_PORT_CMD_SHIFT)
+#define QSPI_CMD_PORT_WAIT_SHIFT	22
+#define QSPI_CMD_PORT_WAIT_MASK		(0x1 << QSPI_CMD_PORT_WAIT_SHIFT)
+#define QSPI_CMD_PORT_THROUGH_SHIFT	21
+#define QSPI_CMD_PORT_THROUGH_MASK	(0x1 << QSPI_CMD_PORT_THROUGH_SHIFT)
+#define QSPI_CMD_PORT_CS_SHIFT		19
+#define QSPI_CMD_PORT_CS_MASK		(0x3 << QSPI_CMD_PORT_CS_SHIFT)
+#define QSPI_CMD_PORT_TRANSFER_SHIFT	16
+#define QSPI_CMD_PORT_TRANSFER_MASK	(0x7 << QSPI_CMD_PORT_TRANSFER_SHIFT)
+#define QSPI_CMD_PORT_CMD_ADDR_SHIFT	15
+#define QSPI_CMD_PORT_CMD_ADDR_MASK	(0x1 << QSPI_CMD_PORT_CMD_ADDR_SHIFT)
+#define QSPI_CMD_PORT_LATENCY_SHIFT	14
+#define QSPI_CMD_PORT_LATENCY_MASK	(0x1 << QSPI_CMD_PORT_LATENCY_SHIFT)
+#define QSPI_CMD_PORT_DATA_TRANSFER_SHIFT	13
+#define QSPI_CMD_PORT_DATA_TRANSFER_MASK	(0x1 << 13)
+#define QSPI_CMD_PORT_SEL_SHIFT		12
+#define QSPI_CMD_PORT_SEL_MASK		(0x1 << QSPI_CMD_PORT_SEL_SHIFT)
+#define QSPI_CMD_PORT_DUMMY_SHIFT	7
+#define QSPI_CMD_PORT_DUMMY_MASK	(0x1F << QSPI_CMD_PORT_DUMMY_SHIFT)
+#define QSPI_CMD_PORT_DUMMY(x)		(((x) << QSPI_CMD_PORT_DUMMY_SHIFT) & QSPI_CMD_PORT_DUMMY_MASK)
+#define QSPI_CMD_PORT_P_BUFFER_SHIFT	6
+#define QSPI_CMD_PORT_P_BUFFER_MASK	(0x1 << QSPI_CMD_PORT_P_BUFFER_SHIFT)
+#define QSPI_CMD_PORT_RW_NUM_SHIFT	3
+#define QSPI_CMD_PORT_RW_NUM_MASK	(0x7 << QSPI_CMD_PORT_RW_NUM_SHIFT)
+#define QSPI_CMD_PORT_SCK_SEL_SHIFT	0
+#define QSPI_CMD_PORT_SCK_SEL_MASK	(0x7 << QSPI_CMD_PORT_SCK_SEL_SHIFT)
+
+#define QSPI_FUN_SET_HOLD_SHIFT		24
+#define QSPI_FUN_SET_HOLD_MASK		(0xFF << QSPI_FUN_SET_HOLD_SHIFT)
+#define QSPI_FUN_SET_SETUP_SHIFT	16
+#define QSPI_FUN_SET_SETUP_MASK		(0xFF << QSPI_FUN_SET_SETUP_SHIFT)
+#define QSPI_FUN_SET_DELAY_SHIFT	0
+#define QSPI_FUN_SET_DELAY_MASK		(0xFFFF << QSPI_FUN_SET_DELAY_SHIFT)
+
+#define QSPI_WIP_W_CMD_SHIFT		24
+#define QSPI_WIP_W_CMD_MASK		(0xFF << QSPI_WIP_W_CMD_SHIFT)
+#define QSPI_WIP_W_TRANSFER_SHIFT	3
+#define QSPI_WIP_W_TRANSFER_MASK	(0x3 << QSPI_WIP_W_TRANSFER_SHIFT)
+#define QSPI_WIP_W_SCK_SEL_SHIFT      	0
+#define QSPI_WIP_W_SCK_SEL_MASK		(0x7 << QSPI_WIP_W_SCK_SEL_SHIFT)
+
+#define QSPI_WP_EN_SHIFT		17
+#define QSPI_WP_EN_MASK			(0x1 << QSPI_WP_EN_SHIFT)
+#define QSPI_WP_IO2_SHIFT		16
+#define QSPI_WP_IO2_MASK		(0x1 << QSPI_WP_IO2_SHIFT)
+#define QSPI_WP_HOLD_SHIFT		8
+#define QSPI_WP_HOLD_MASK		(0xFF << QSPI_WP_HOLD_SHIFT)
+#define QSPI_WP_SETUP_SHIFT		0
+#define QSPI_WP_SETUP_MASK		(0xFF << QSPI_WP_SETUP_SHIFT)
+
+#define QSPI_MODE_VALID_SHIFT		8
+#define QSPI_MODE_VALID_MASK		(0xFF << QSPI_MODE_VALID_SHIFT)
+#define QSPI_MODE_SHIFT			0
+#define QSPI_MODE_MASK			(0xFF << QSPI_MODE_SHIFT)
+
+#define FSIZE_VAL(size)			(__fls(size) - 1)
+
+#define PHYTIUM_MAX_MMAP_S		SZ_512M
+#define PHYTIUM_MAX_NORCHIP		4
+
+#define PHYTIUM_QSPI_FIFO_SZ		32
+#define PHYTIUM_QSPI_FIFO_TIMEOUT_US	50000
+#define PHYTIUM_QSPI_BUSY_TIMEOUT_US	100000
+
+#define PHYTIUM_SCK_SEL			0x05
+#define PHYTIUM_CMD_SCK_SEL		0x07
+
+#define PHYTIUM_FMODE_MM		0x01
+#define PHYTIUM_FMODE_IN		0x02
+
+/*
+ * the codes of the different commands
+ */
+#define CMD_WRDI	  0x04
+#define CMD_RDID	  0x9F
+#define CMD_RDSR	  0x05
+#define CMD_WREN	  0x06
+#define CMD_RDAR	  0x65
+#define CMD_P4E           0x20
+#define CMD_4P4E          0x21
+#define CMD_BE      	  0x60
+#define CMD_4BE           0xC7
+#define	CMD_READ          0x03
+#define	CMD_FAST_READ     0x0B
+#define	CMD_QOR           0x6B
+#define	CMD_QIOR          0xEB
+#define CMD_DDRFR         0x0D
+#define	CMD_DDRQIOQ       0xED
+#define	CMD_PP            0x02
+#define	CMD_QPP           0x32
+#define	CMD_SE            0xD8
+#define	CMD_4FAST_READ    0x0C
+#define	CMD_4READ         0x13
+#define	CMD_4QOR          0x6C
+#define	CMD_4QIOR         0xEC
+#define	CMD_4DDRFR        0x0E
+#define	CMD_4DDRQIOR      0xEE
+#define	CMD_4PP           0x12
+#define	CMD_4QPP          0x34
+#define	CMD_4SE           0xDC
+
+#define PHYTIUM_QSPI_1_1_1	0
+#define PHYTIUM_QSPI_1_1_2	1
+#define PHYTIUM_QSPI_1_1_4	2
+#define PHYTIUM_QSPI_1_2_2	3
+#define PHYTIUM_QSPI_1_4_4	4
+#define PHYTIUM_QSPI_2_2_2	5
+#define PHYTIUM_QSPI_4_4_4	6
+
+struct phytium_qspi_flash {
+	struct spi_nor nor;
+	struct phytium_qspi *qspi;
+	u32 cs;
+	u32 fsize;
+	u32 presc;
+	u32 clk_div;
+	u32 read_mode;
+	bool registered;
+	u32 prefetch_limit;
+	u32 addr_width;
+	u32 read_cmd;
+};
+
+struct phytium_qspi {
+	struct device *dev;
+	void __iomem *io_base;
+	void __iomem *mm_base;
+	resource_size_t mm_size;
+	u32 nor_num;
+	struct clk *clk;
+	u32 clk_rate;
+	struct phytium_qspi_flash flash[PHYTIUM_MAX_NORCHIP];
+
+	spinlock_t spinlock;
+
+	/*
+	 * to protect device configuration, could be different between
+	 * 2 flash access (bk1, bk2)
+	 */
+	struct mutex lock;
+};
+
+/* Need to enable p_buffer */
+static int memcpy_from_ftreg(struct phytium_qspi *qspi, u_char *buf, size_t len)
+{
+	int i;
+	u32 val = 0;
+
+	if (!qspi || !buf)
+		return -EINVAL;
+
+	for (i = 0; i < len; i++) {
+		if (0 == i % 4)
+			val = readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG);
+
+		buf[i] = (u_char) (val >> (i % 4) * 8) & 0xFF;
+	}
+
+	return 0;
+}
+
+/* Not to enable p_buffer */
+static int memcpy_to_ftreg(struct phytium_qspi *qspi, const u8 *buf, size_t len)
+{
+	u32 val = 0;
+
+	if (!qspi || !buf || (len >= 8))
+		return -EINVAL;
+
+	if (1 == len) {
+		val = buf[0];
+	} else if (2 == len) {
+		val = buf[1];
+		val = (val << 8) + buf[0];
+	} else if (3 == len) {
+		val = buf[2];
+		val = (val << 8) + buf[1];
+		val = (val << 8) + buf[0];
+	} else if (4 == len) {
+		val = buf[3];
+		val = (val << 8) + buf[2];
+		val = (val << 8) + buf[1];
+		val = (val << 8) + buf[0];
+	}
+
+	writel_relaxed(val, qspi->io_base + QSPI_LD_PORT_REG);
+
+	return 0;
+}
+
+static int phytium_qspi_wait_cmd(struct phytium_qspi *qspi,
+				struct phytium_qspi_flash *flash)
+{
+	u32 cmd = 0;
+	u32 cnt = 0;
+
+	cmd |= CMD_RDSR << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT);
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+
+	cnt = PHYTIUM_QSPI_BUSY_TIMEOUT_US / 10;
+	while (readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG) & 0x01) {
+		udelay(10);
+		cnt--;
+		if (!cnt) {
+			dev_err(qspi->dev, "wait command process timeout\n");
+			break;
+		}
+	}
+
+	return !cnt;
+}
+
+static int phytium_qspi_cmd_enable(struct phytium_qspi *qspi)
+{
+	u32 val = 0;
+
+	writel_relaxed(val, qspi->io_base + QSPI_LD_PORT_REG);
+
+	return 0;
+}
+
+static int phytium_qspi_write_enable(struct phytium_qspi *qspi,
+				struct phytium_qspi_flash *flash)
+{
+	u32 cmd = 0;
+
+	cmd  = CMD_WREN << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+
+	return 0;
+}
+
+static int phytium_qspi_write_disable(struct phytium_qspi *qspi,
+				struct phytium_qspi_flash *flash)
+{
+	u32 cmd = 0;
+
+	cmd  = CMD_WRDI << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+
+	return 0;
+}
+
+static int phytium_qspi_read_flash_id(struct phytium_qspi *qspi,
+		struct phytium_qspi_flash *flash, u8 opcode, u8 *buf, int len)
+{
+	u32 cmd = 0;
+	unsigned long iflags;
+
+	cmd  = opcode << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT);
+	cmd |= BIT(QSPI_CMD_PORT_P_BUFFER_SHIFT);
+	cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+
+	spin_lock_irqsave(&qspi->spinlock, iflags);
+	memcpy_from_ftreg(qspi, buf, len);
+	spin_unlock_irqrestore(&qspi->spinlock, iflags);
+
+	dev_dbg(qspi->dev, "read flash id:%x\n", *(u32 *)buf);
+	return 0;
+}
+
+static int phytium_qspi_read_flash_sfdp(struct phytium_qspi *qspi,
+	struct phytium_qspi_flash *flash, struct spi_nor *nor, loff_t from, u8 *buf, int len)
+{
+	unsigned long iflags;
+	u32 cmd = 0;
+	u8 opcode = nor->read_opcode;
+
+	cmd  = opcode << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT);
+	cmd |= BIT(QSPI_CMD_PORT_P_BUFFER_SHIFT);
+	cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT);
+	cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+	cmd |= BIT(QSPI_CMD_PORT_LATENCY_SHIFT);
+	cmd |= QSPI_CMD_PORT_DUMMY(nor->read_dummy - 1);
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	writel_relaxed(from, qspi->io_base + QSPI_ADDR_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+
+	spin_lock_irqsave(&qspi->spinlock, iflags);
+	memcpy_from_ftreg(qspi, buf, len);
+	spin_unlock_irqrestore(&qspi->spinlock, iflags);
+
+	dev_dbg(qspi->dev, "read flash sfdp:0x%llx 0x%llx\n",
+			*(u64 *)buf, *(u64 *)(buf + 8));
+	return len;
+}
+
+static int phytium_qspi_read_flash_sr1(struct phytium_qspi *qspi,
+		struct phytium_qspi_flash *flash,  u8 opcode, u8 *buf, int len)
+{
+	u32 cmd = 0;
+	u32 val;
+
+	cmd  = opcode << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT);
+	cmd |= (len << QSPI_CMD_PORT_RW_NUM_SHIFT) & QSPI_CMD_PORT_RW_NUM_MASK;
+	cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+
+	val = readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG);
+	buf[0] = (u8)val;
+
+	return 0;
+}
+
+static int phytium_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct device *dev = flash->qspi->dev;
+	struct phytium_qspi *qspi = flash->qspi;
+	unsigned long iflags;
+	u32 cmd = 0;
+
+	dev_dbg(dev, "read_reg: cmd:%#.2x buf:%pK len:%#lx\n", opcode, buf, len);
+
+	switch (opcode) {
+	case CMD_RDID:
+		phytium_qspi_read_flash_id(qspi, flash, opcode, buf, len);
+		return 0;
+	case CMD_RDSR:
+		phytium_qspi_read_flash_sr1(qspi, flash, opcode, buf, len);
+		return 0;
+	default:
+		break;
+	}
+
+	cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT);
+	cmd |= BIT(QSPI_CMD_PORT_P_BUFFER_SHIFT);
+	cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+
+	spin_lock_irqsave(&qspi->spinlock, iflags);
+	memcpy_from_ftreg(qspi, buf, len);
+	spin_unlock_irqrestore(&qspi->spinlock, iflags);
+
+	return 0;
+}
+
+static int phytium_qspi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, size_t len)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct device *dev = flash->qspi->dev;
+	struct phytium_qspi *qspi = flash->qspi;
+	u32 cmd = 0;
+
+	dev_dbg(dev, "write_reg: cmd:%#.2x buf:%pK len:%#lx\n", opcode, buf, len);
+
+	switch (opcode) {
+	case CMD_WREN:
+		phytium_qspi_write_enable(qspi, flash);
+		return 0;
+	case CMD_WRDI:
+		phytium_qspi_write_disable(qspi, flash);
+		return 0;
+	default:
+		break;
+	}
+
+	cmd = opcode << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	if ((len > 8) || (NULL == buf)) {
+		dev_err(dev, "data length exceed. commad %x, len:%ld \n", opcode, len);
+		return -EINVAL;
+	} else if (len > 0) {
+		cmd |= ((len - 1) << QSPI_CMD_PORT_RW_NUM_SHIFT) & QSPI_CMD_PORT_RW_NUM_MASK;
+		cmd |= BIT(QSPI_CMD_PORT_DATA_TRANSFER_SHIFT);
+	}
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	memcpy_to_ftreg(qspi, buf, len);
+
+	return 0;
+}
+
+static ssize_t phytium_qspi_read_tmp(struct phytium_qspi *qspi, u32 read_cmd, loff_t from, size_t len, u_char *buf)
+{
+	u32 addr = (u32)from;
+	u64 val = 0;
+
+	if (!qspi)
+		return -1;
+
+	dev_dbg(qspi->dev, "read cmd:%x, addr:%x len:%zx\n", read_cmd, addr, len);
+	writel_relaxed(read_cmd, qspi->io_base + QSPI_RD_CFG_REG);
+
+	memcpy_fromio(buf, qspi->mm_base + addr, len);
+
+	val = *(u64 *)(buf);
+	dev_dbg(qspi->dev, "read val:%llx\n", val);
+
+	return len;
+}
+
+static ssize_t phytium_qspi_read(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct phytium_qspi *qspi = flash->qspi;
+	u32 cmd = nor->read_opcode;
+	u32 addr = (u32)from;
+
+	addr = addr + flash->cs * flash->fsize;
+
+	dev_dbg(qspi->dev, "read(%#.2x): buf:%pK from:%#.8x len:%#zx\n", nor->read_opcode, buf, addr, len);
+
+	cmd = cmd << QSPI_RD_CFG_RD_CMD_SHIFT;
+	cmd |= BIT(QSPI_RD_CFG_D_BUFFER_SHIFT);
+	cmd |= flash->clk_div << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+
+	cmd &= ~QSPI_RD_CFG_RD_TRANSFER_MASK;
+	cmd |= (flash->addr_width << QSPI_RD_CFG_RD_TRANSFER_SHIFT);
+
+	switch (nor->read_opcode) {
+	case CMD_READ:
+	case CMD_FAST_READ:
+	case CMD_QIOR:
+	case CMD_QOR:
+		cmd &= ~QSPI_RD_CFG_RD_ADDR_SEL_MASK;
+		break;
+	case CMD_4READ:
+	case CMD_4FAST_READ:
+	case CMD_4QOR:
+	case CMD_4QIOR:
+		cmd |= BIT(QSPI_RD_CFG_RD_ADDR_SEL_SHIFT);
+		break;
+	case 0x5A:
+		cmd &= ~QSPI_RD_CFG_RD_ADDR_SEL_MASK;
+		return phytium_qspi_read_flash_sfdp(qspi, flash, nor, from, buf, len);
+		break;
+	default:
+		break;
+	}
+
+	if ((PHYTIUM_QSPI_1_1_4 == flash->addr_width) || (PHYTIUM_QSPI_1_4_4 == flash->addr_width)) {
+		cmd |= BIT(QSPI_RD_CFG_RD_LATENCY_SHIFT);
+		cmd &= ~QSPI_RD_CFG_DUMMY_MASK;
+		cmd |= (0x07 << QSPI_RD_CFG_DUMMY_SHIFT);
+	}
+
+	dev_dbg(qspi->dev, "read(%#.2x): cmd:%#x\n", nor->read_opcode, cmd);
+
+	if (cmd != flash->read_cmd)
+		flash->read_cmd = cmd;
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_RD_CFG_REG);
+
+	memcpy_fromio(buf, qspi->mm_base + addr, len);
+
+	return len;
+}
+
+static ssize_t phytium_qspi_write(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct device *dev = flash->qspi->dev;
+	struct phytium_qspi *qspi = flash->qspi;
+	u32 cmd = nor->program_opcode;
+	u32 addr = (u32)to;
+	int i;
+	u_char tmp[8] = {0};
+	size_t mask = 0x03;
+
+	addr = addr + flash->cs * flash->fsize;
+
+	dev_dbg(dev, "write(%#.2x): buf:%p to:%#.8x len:%#zx\n", nor->program_opcode, buf, addr, len);
+
+	if (addr & 0x03) {
+		dev_err(dev, "Addr not four-byte aligned!\n");
+		return -EINVAL;
+	}
+
+	cmd = cmd << QSPI_WR_CFG_WR_CMD_SHIFT;
+	cmd |= BIT(QSPI_WR_CFG_WR_MODE_SHIFT);
+	cmd |= PHYTIUM_CMD_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+
+	switch (nor->program_opcode) {
+	case CMD_PP:
+	case CMD_QPP:
+		cmd &= ~QSPI_WR_CFG_WR_ADDR_SEL_MASK;
+		break;
+	case CMD_4PP:
+	case CMD_4QPP:
+		cmd |= BIT(QSPI_WR_CFG_WR_ADDR_SEL_SHIFT);
+		break;
+	default:
+		dev_err(qspi->dev, "Not support program command:%#x\n", nor->erase_opcode);
+		return -EINVAL;
+	}
+
+	dev_dbg(qspi->dev, "write cmd:%x\n", cmd);
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_WR_CFG_REG);
+
+	for (i = 0; i < len/4; i++)
+		writel_relaxed(*(u32 *)(buf + 4*i), qspi->mm_base + addr + 4*i);
+
+	if (len & mask) {
+		addr = addr + (len & ~mask);
+		phytium_qspi_read_tmp(qspi, flash->read_cmd, addr, 4, &tmp[0]);
+		memcpy(tmp, buf + (len & ~mask), len & mask);
+		writel_relaxed(*(u32 *)(tmp), qspi->mm_base + addr);
+	}
+
+	writel_relaxed(QSPI_FLUSH_EN, qspi->io_base + QSPI_FLUSH_REG);
+
+	phytium_qspi_wait_cmd(qspi, flash);
+
+	return len;
+}
+
+static int phytium_qspi_erase(struct spi_nor *nor, loff_t offs)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct device *dev = flash->qspi->dev;
+	struct phytium_qspi *qspi = flash->qspi;
+	u32 cmd = nor->erase_opcode;
+	u32 addr = (u32)offs;
+
+	dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs);
+
+	phytium_qspi_write_enable(qspi, flash);
+
+	cmd = cmd << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= PHYTIUM_SCK_SEL << QSPI_CMD_PORT_SCK_SEL_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	/* s25fl256s1 not supoort D8, DC, 20, 21 */
+	switch (nor->erase_opcode) {
+	case CMD_SE:
+		cmd &= ~QSPI_CMD_PORT_SEL_MASK;
+		cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT);
+		writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG);
+		break;
+	case CMD_4SE:
+		cmd |= BIT(QSPI_CMD_PORT_SEL_SHIFT);
+		cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT);
+		writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG);
+		break;
+	case CMD_P4E:
+		cmd &= ~QSPI_CMD_PORT_SEL_MASK;
+		cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT);
+		writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG);
+		break;
+	case CMD_4P4E:
+		cmd |= BIT(QSPI_CMD_PORT_SEL_SHIFT);
+		cmd |= BIT(QSPI_CMD_PORT_CMD_ADDR_SHIFT);
+		writel_relaxed(addr, qspi->io_base + QSPI_ADDR_PORT_REG);
+		break;
+	case CMD_BE:
+		cmd &= ~QSPI_CMD_PORT_SEL_MASK;
+		break;
+	case CMD_4BE:
+		cmd |= BIT(QSPI_CMD_PORT_SEL_SHIFT);
+		break;
+	default:
+		dev_err(qspi->dev, "Not support erase command:%#x\n", nor->erase_opcode);
+		return -EINVAL;
+	}
+
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+	phytium_qspi_cmd_enable(qspi);
+	phytium_qspi_wait_cmd(qspi, flash);
+
+	return 0;
+}
+
+static int phytium_qspi_prep(struct spi_nor *nor)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct phytium_qspi *qspi = flash->qspi;
+
+	mutex_lock(&qspi->lock);
+	return 0;
+}
+
+static void phytium_qspi_unprep(struct spi_nor *nor)
+{
+	struct phytium_qspi_flash *flash = nor->priv;
+	struct phytium_qspi *qspi = flash->qspi;
+
+	mutex_unlock(&qspi->lock);
+}
+
+static int phytium_qspi_get_flash_size(struct phytium_qspi *qspi, u32 size)
+{
+	int ret = 0;
+	u32 value;
+
+	switch (size) {
+	case SZ_4M:
+		value = 0;
+		break;
+	case SZ_8M:
+		value = 1;
+		break;
+	case SZ_16M:
+		value = 2;
+		break;
+	case SZ_32M:
+		value = 3;
+		break;
+	case SZ_64M:
+		value = 4;
+		break;
+	case SZ_128M:
+		value = 5;
+		break;
+	case SZ_256M:
+		value = 6;
+		break;
+	case SZ_512M:
+		value = 7;
+		break;
+	default:
+		value = 0;
+		ret = -EINVAL;
+		return ret;
+	}
+
+	return value;
+}
+
+static const struct spi_nor_controller_ops phytium_controller_ops = {
+	.prepare = phytium_qspi_prep,
+	.unprepare = phytium_qspi_unprep,
+	.read_reg = phytium_qspi_read_reg,
+	.write_reg = phytium_qspi_write_reg,
+	.read = phytium_qspi_read,
+	.write = phytium_qspi_write,
+	.erase = phytium_qspi_erase,
+};
+
+static int phytium_qspi_flash_setup(struct phytium_qspi *qspi, struct fwnode_handle *np)
+{
+	struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | SNOR_HWCAPS_PP, };
+	u32 width, presc;
+	u32 cs_num = 0;
+	u32 max_rate = 0;
+	u32 clk_div = 0;
+	u32 flash_cap = 0;
+	u32 addr_width = PHYTIUM_QSPI_1_1_1;
+	struct phytium_qspi_flash *flash;
+	struct mtd_info *mtd;
+	int ret;
+
+	fwnode_property_read_u32(np, "reg", &cs_num);
+	if (cs_num >= PHYTIUM_MAX_NORCHIP)
+		return -EINVAL;
+
+	fwnode_property_read_u32(np, "spi-max-frequency", &max_rate);
+	if (!max_rate)
+		return -EINVAL;
+
+	fwnode_property_read_u32(np, "spi-clk-div", &clk_div);
+	if (!clk_div)
+		clk_div = PHYTIUM_SCK_SEL;
+
+	if (clk_div < 4)
+		return -EINVAL;
+
+	presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1;
+
+	fwnode_property_read_u32(np, "spi-rx-bus-width", &width);
+	if (!width)
+		width = 1;
+
+	if (width == 4) {
+		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
+		addr_width   = PHYTIUM_QSPI_1_1_4;
+	} else if (width == 2) {
+		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
+		addr_width   = PHYTIUM_QSPI_1_1_2;
+	} else if (width != 1)
+		return -EINVAL;
+
+	flash = &qspi->flash[cs_num];
+
+	flash->qspi = qspi;
+	flash->cs = cs_num;
+	flash->presc = presc;
+	flash->clk_div = clk_div;
+	flash->addr_width = addr_width;
+	flash->nor.dev = qspi->dev;
+	if (qspi->dev->of_node)
+		spi_nor_set_flash_node(&flash->nor, qspi->dev->of_node);
+	flash->nor.priv = flash;
+	flash->nor.controller_ops = &phytium_controller_ops;
+
+	ret = spi_nor_scan(&flash->nor, NULL, &hwcaps);
+	if (ret) {
+		dev_err(qspi->dev, "device scan failed\n");
+		return ret;
+	}
+
+	mtd = &flash->nor.mtd;
+
+	flash->fsize = mtd->size;
+	flash->prefetch_limit = mtd->size - PHYTIUM_QSPI_FIFO_SZ;
+
+	ret = phytium_qspi_get_flash_size(flash->qspi, mtd->size);
+	if (ret < 0) {
+		dev_err(qspi->dev, "flash size invalid\n");
+		return ret;
+	}
+
+	flash_cap = cs_num << QSPI_FLASH_CAP_NUM_SHIFT;
+	flash_cap |= ret;
+	writel_relaxed(flash_cap, qspi->io_base + QSPI_FLASH_CAP_REG);
+
+	flash->read_mode = PHYTIUM_FMODE_MM;
+
+	ret = mtd_device_register(mtd, NULL, 0);
+	if (ret) {
+		dev_err(qspi->dev, "mtd device parse failed\n");
+		return ret;
+	}
+
+	flash->registered = true;
+
+	dev_dbg(qspi->dev, "read mm:%s %px cs:%d bus:%d clk-div:%d\n",
+		flash->read_mode == PHYTIUM_FMODE_MM ? "yes" : "no",
+		qspi->mm_base, cs_num, width, clk_div);
+
+	dev_dbg(qspi->dev, "mtd->size:%llx, mtd->erasesize:%x, fsize:%x\n",
+			mtd->size, mtd->erasesize, flash->fsize);
+
+	return 0;
+}
+
+static void phytium_qspi_mtd_free(struct phytium_qspi *qspi)
+{
+	int i;
+
+	for (i = 0; i < PHYTIUM_MAX_NORCHIP; i++)
+		if (qspi->flash[i].registered)
+			mtd_device_unregister(&qspi->flash[i].nor.mtd);
+}
+
+static ssize_t clk_div_show(struct device *dev, struct device_attribute *attr,
+			      char *buf)
+{
+	struct phytium_qspi *qspi = dev_get_drvdata(dev);
+	struct phytium_qspi_flash *flash = &qspi->flash[0];
+
+	return sprintf(buf, "Flash 0 clk-div: %d\n", flash->clk_div);
+}
+
+static ssize_t clk_div_store(struct device *dev,
+			       struct device_attribute *attr, const char *buf,
+			       size_t size)
+{
+	struct phytium_qspi *qspi = dev_get_drvdata(dev);
+	struct phytium_qspi_flash *flash = &qspi->flash[0];
+	long value;
+	char *token;
+	ssize_t status;
+
+	token = strsep ((char **)&buf, " ");
+	if (!token)
+		return -EINVAL;
+
+	status = kstrtol(token, 0, &value);
+	if (status)
+		return status;
+
+	flash->clk_div = (u8)value;
+
+	return size;
+}
+static DEVICE_ATTR_RW(clk_div);
+
+static struct attribute *phytium_qspi_attrs[] = {
+	&dev_attr_clk_div.attr,
+	NULL,
+};
+
+static struct attribute_group phytium_qspi_attr_group = {
+	.attrs = phytium_qspi_attrs,
+};
+
+static int phytium_qspi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fwnode_handle *flash_np;
+	struct phytium_qspi *qspi;
+	struct resource *res;
+	int ret;
+
+	qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
+	if (!qspi)
+		return -ENOMEM;
+
+	qspi->nor_num = device_get_child_node_count(dev);
+	if (!qspi->nor_num || qspi->nor_num > PHYTIUM_MAX_NORCHIP)
+		return -ENODEV;
+
+	if (dev->of_node)
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
+	else if (has_acpi_companion(dev)) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	}
+	qspi->io_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(qspi->io_base))
+		return PTR_ERR(qspi->io_base);
+
+
+	if (dev->of_node)
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
+	else if (has_acpi_companion(dev))
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+	qspi->mm_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(qspi->mm_base))
+		return PTR_ERR(qspi->mm_base);
+
+	qspi->mm_size = resource_size(res);
+
+	if (dev->of_node) {
+		qspi->clk = devm_clk_get(dev, NULL);
+		if (IS_ERR(qspi->clk))
+			return PTR_ERR(qspi->clk);
+
+		qspi->clk_rate = clk_get_rate(qspi->clk);
+		if (!qspi->clk_rate)
+			return -EINVAL;
+
+		ret = clk_prepare_enable(qspi->clk);
+		if (ret) {
+			dev_err(dev, "can not enable the clock\n");
+			return ret;
+		}
+	}
+	else if (has_acpi_companion(dev)) { /* ACPI table not pass clk rate */
+		qspi->clk_rate = 50000000;
+	}
+
+	qspi->dev = dev;
+	platform_set_drvdata(pdev, qspi);
+	mutex_init(&qspi->lock);
+	spin_lock_init(&qspi->spinlock);
+
+	fwnode_for_each_available_child_node(dev_fwnode(dev), flash_np) {
+		ret = phytium_qspi_flash_setup(qspi, flash_np);
+		if (ret) {
+			dev_err(dev, "unable to setup flash chip\n");
+			goto err_flash;
+		}
+	}
+
+	ret = sysfs_create_group(&qspi->dev->kobj, &phytium_qspi_attr_group);
+	if (ret) {
+		dev_err(dev, "unable to create sysfs\n");
+		goto err_flash;
+	}
+
+	return 0;
+
+err_flash:
+	mutex_destroy(&qspi->lock);
+	phytium_qspi_mtd_free(qspi);
+
+	clk_disable_unprepare(qspi->clk);
+	return ret;
+}
+
+static int phytium_qspi_remove(struct platform_device *pdev)
+{
+	struct phytium_qspi *qspi = platform_get_drvdata(pdev);
+
+	sysfs_remove_group(&qspi->dev->kobj, &phytium_qspi_attr_group);
+
+	phytium_qspi_mtd_free(qspi);
+	mutex_destroy(&qspi->lock);
+
+	clk_disable_unprepare(qspi->clk);
+	return 0;
+}
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_qspi_acpi_ids[] = {
+	{ "PHYT0011", 0 },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_qspi_acpi_ids);
+#endif
+
+static const struct of_device_id phytium_qspi_match[] = {
+	{ .compatible = "phytium,qspi" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_qspi_match);
+
+static struct platform_driver phytium_qspi_driver = {
+	.probe	= phytium_qspi_probe,
+	.remove	= phytium_qspi_remove,
+	.driver	= {
+		.name = "phytium-quadspi",
+		.of_match_table = phytium_qspi_match,
+		.acpi_match_table = ACPI_PTR(phytium_qspi_acpi_ids),
+	},
+};
+module_platform_driver(phytium_qspi_driver);
+
+MODULE_AUTHOR("Mingshuai Zhu <zhumingshui@phytium.com.cn>");
+MODULE_AUTHOR("Shaojun Yang <yangshaojun@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium QuadSPI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/net/can/phytium/Kconfig b/target/linux/phytium/files-5.10/drivers/net/can/phytium/Kconfig
new file mode 100644
index 00000000000000..a23216d23c2262
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/can/phytium/Kconfig
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menuconfig CAN_PHYTIUM
+	tristate "Phytium CAN support"
+	help
+	  Say Y here if you want support for Phytium CAN controller framework.
+	  This is common support for devices that embed the Phytium CAN IP.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called phytium_can.
+
+if CAN_PHYTIUM
+
+config CAN_PHYTIUM_PLATFORM
+	tristate "Phytium CAN support for io-mapped devices"
+	depends on HAS_IOMEM
+	help
+	  Say Y here is you want to support for IO Mapped Phytium CAN controller.
+	  This support is for devices that have the Phytium CAN controller IP
+	  embedded into the device and the IP is IO Mapped to the processor.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called phytium_can_platform.
+
+config CAN_PHYTIUM_PCI
+	tristate "Phytium CAN support for PCI devices"
+	depends on PCI
+	help
+	  Say Y here is you want to support for Phytium CAN controller connected
+	  to the PCI bus. This support is for devices that have the Phytium CAN
+	  controller IP embedded into a PCI device.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called phytium_can_pci.
+endif
diff --git a/target/linux/phytium/files-5.10/drivers/net/can/phytium/Makefile b/target/linux/phytium/files-5.10/drivers/net/can/phytium/Makefile
new file mode 100644
index 00000000000000..7ef554fca58e4b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/can/phytium/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the Phytium CAN controller drivers.
+#
+#
+
+obj-$(CONFIG_CAN_PHYTIUM) += phytium_can.o
+obj-$(CONFIG_CAN_PHYTIUM_PLATFORM) += phytium_can_platform.o
+obj-$(CONFIG_CAN_PHYTIUM_PCI) += phytium_can_pci.o
diff --git a/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can.c b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can.c
new file mode 100644
index 00000000000000..95ec7311bfcb73
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can.c
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: GPL-2.0
+/* CAN bus driver for Phytium CAN controller
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/bitfield.h>
+
+#include "phytium_can.h"
+
+/* register definition */
+enum phytium_can_reg {
+	CAN_CTRL		= 0x00,		/* Global control register */
+	CAN_INTR		= 0x04,		/* Interrupt register */
+	CAN_ARB_RATE_CTRL	= 0x08,		/* Arbitration rate control register */
+	CAN_DAT_RATE_CTRL	= 0x0c,		/* Data rate control register */
+	CAN_ACC_ID0		= 0x10,		/* Acceptance identifier0 register */
+	CAN_ACC_ID1		= 0x14,		/* Acceptance identifier1 register */
+	CAN_ACC_ID2		= 0x18,		/* Acceptance identifier2 register */
+	CAN_ACC_ID3		= 0x1c,		/* Acceptance identifier3 register */
+	CAN_ACC_ID0_MASK	= 0x20,		/* Acceptance identifier0 mask register */
+	CAN_ACC_ID1_MASK	= 0x24,		/* Acceptance identifier1 mask register */
+	CAN_ACC_ID2_MASK	= 0x28,		/* Acceptance identifier2 mask register */
+	CAN_ACC_ID3_MASK	= 0x2c,		/* Acceptance identifier3 mask register */
+	CAN_XFER_STS		= 0x30,		/* Transfer status register */
+	CAN_ERR_CNT		= 0x34,		/* Error counter register */
+	CAN_FIFO_CNT		= 0x38,		/* FIFO counter register */
+	CAN_DMA_CTRL		= 0x3c,		/* DMA request control register */
+	CAN_XFER_EN		= 0x40,		/* Transfer enable register */
+	CAN_INTR1		= 0x44,		/* Interrupt register 1 */
+	CAN_FRM_INFO		= 0x48,		/* Frame valid number register */
+	CAN_TIME_OUT		= 0x4c,		/* Timeout register */
+	CAN_TIME_OUT_CNT	= 0x50,		/* Timeout counter register */
+	CAN_INTR2		= 0x54,		/* Interrupt register 2 */
+	CAN_TX_FIFO		= 0x100,	/* TX FIFO shadow register */
+	CAN_RX_FIFO		= 0x200,	/* RX FIFO shadow register */
+	CAN_RX_INFO_FIFO	= 0x300,	/* RX information FIFO shadow register */
+	CAN_PIDR4		= 0xfd0,	/* Peripheral Identification Register 4 */
+	CAN_PIDR0		= 0xfe0,	/* Peripheral Identification Register 0 */
+	CAN_PIDR1		= 0xfe4,	/* Peripheral Identification Register 1 */
+	CAN_PIDR2		= 0xfe8,	/* Peripheral Identification Register 2 */
+	CAN_PIDR3		= 0xfec,	/* Peripheral Identification Register 3 */
+	CAN_CIDR0		= 0xff0,	/* Component Identification Register 0 */
+	CAN_CIDR1		= 0xff4,	/* Component Identification Register 1 */
+	CAN_CIDR2		= 0xff8,	/* Component Identification Register 2 */
+	CAN_CIDR3		= 0xffc,	/* Component Identification Register 3 */
+};
+
+/* Global control register (CTRL) */
+#define CTRL_XFER		BIT(0)	/* Transfer enable */
+#define CTRL_TXREQ		BIT(1)	/* Transmit request */
+#define CTRL_AIME		BIT(2)	/* Acceptance identifier mask enable */
+#define CTRL_TTS		BIT(3)	/* Transmit trigger strategy */
+#define CTRL_RST		BIT(7)	/* Write 1 to soft reset and self clear */
+#define CTRL_RFEIDF		BIT(8)	/* Allow RX frame end interrupt during ID filtered frame */
+#define CTRL_RFEDT		BIT(9)	/* Allow RX frame end interrupt during TX frame */
+#define CTRL_IOF		BIT(10)	/* Ignore overload flag internally */
+#define CTRL_FDCRC		BIT(11)	/* CANFD CRC mode */
+
+/* Interrupt register (INTR) */
+#define INTR_BOIS	BIT(0)  /* Bus off interrupt status */
+#define INTR_PWIS	BIT(1)  /* Passive warning interrupt status */
+#define INTR_PEIS	BIT(2)  /* Passive error interrupt status */
+#define INTR_RFIS	BIT(3)  /* RX FIFO full interrupt status */
+#define INTR_TFIS	BIT(4)  /* TX FIFO empty interrupt status */
+#define INTR_REIS	BIT(5)  /* RX frame end interrupt status */
+#define INTR_TEIS	BIT(6)  /* TX frame end interrupt status */
+#define INTR_EIS	BIT(7)  /* Error interrupt status */
+#define INTR_BOIE	BIT(8)  /* Bus off interrupt enable */
+#define INTR_PWIE	BIT(9)  /* Passive warning interrupt enable */
+#define INTR_PEIE	BIT(10) /* Passive error interrupt enable */
+#define INTR_RFIE	BIT(11) /* RX FIFO full interrupt enable */
+#define INTR_TFIE	BIT(12) /* TX FIFO empty interrupt enable */
+#define INTR_REIE	BIT(13) /* RX frame end interrupt enable */
+#define INTR_TEIE	BIT(14) /* TX frame end interrupt enable */
+#define INTR_EIE	BIT(15) /* Error interrupt enable */
+#define INTR_BOIC	BIT(16) /* Bus off interrupt clear */
+#define INTR_PWIC	BIT(17) /* Passive warning interrupt clear */
+#define INTR_PEIC	BIT(18) /* Passive error interrupt clear */
+#define INTR_RFIC	BIT(19) /* RX FIFO full interrupt clear */
+#define INTR_TFIC	BIT(20) /* TX FIFO empty interrupt clear */
+#define INTR_REIC	BIT(21) /* RX frame end interrupt clear */
+#define INTR_TEIC	BIT(22) /* TX frame end interrupt clear */
+#define INTR_EIC	BIT(23) /* Error interrupt clear */
+
+#define INTR_STATUS_MASK (INTR_BOIS | INTR_PWIS | INTR_PEIS | INTR_RFIS | \
+			  INTR_TFIS | INTR_REIS | INTR_TEIS | INTR_EIS)
+#define INTR_EN_MASK	 (INTR_BOIE | INTR_RFIE | INTR_REIE | INTR_TEIE | \
+			  INTR_EIE)
+#define INTR_CLEAR_MASK	 (INTR_BOIC | INTR_PWIC | INTR_PEIC | INTR_RFIC | \
+			  INTR_TFIC | INTR_REIC | INTR_TEIC | INTR_EIC)
+
+/* Arbitration rate control register (ARB_RATE_CTRL) */
+#define ARB_RATE_CTRL_ARJW	GENMASK(1, 0)	/* Arbitration field resync jump width */
+#define ARB_RATE_CTRL_APRS	GENMASK(4, 2)	/* Arbitration field propagation segment */
+#define ARB_RATE_CTRL_APH1S	GENMASK(7, 5)	/* Arbitration field phase1 segment */
+#define ARB_RATE_CTRL_APH2S	GENMASK(10, 8)	/* Arbitration field phase2 segment */
+#define ARB_RATE_CTRL_APD	GENMASK(28, 16)	/* Arbitration field prescaler divider */
+
+/* Data rate control register (DAT_RATE_CTRL) */
+#define DAT_RATE_CTRL_DRJW	GENMASK(1, 0)	/* Data field resync jump width */
+#define DAT_RATE_CTRL_DPRS	GENMASK(4, 2)	/* Data field propagation segment */
+#define DAT_RATE_CTRL_DPH1S	GENMASK(7, 5)	/* Data field phase1 segment */
+#define DAT_RATE_CTRL_DPH2S	GENMASK(10, 8)	/* Data field phase2 segment */
+#define DAT_RATE_CTRL_DPD	GENMASK(28, 16)	/* Data field prescaler divider */
+
+/* Acceptance identifierX register (ACC_IDX) */
+#define ACC_IDX_AID_MASK	GENMASK(28, 0)	/* Acceptance identifier */
+
+/* Acceptance identifier0 mask register (ACC_ID0_MASK) */
+#define ACC_IDX_MASK_AID_MASK	GENMASK(28, 0)	/* Acceptance identifier mask */
+
+/* Transfer status register (XFER_STS) */
+#define XFER_STS_FRAS		GENMASK(2, 0)	/* Frame status */
+#define XFER_STS_FIES		GENMASK(7, 3)	/* Field status */
+#define  XFER_STS_FIES_IDLE		(0x0)	/* idle */
+#define  XFER_STS_FIES_ARBITRATION	(0x1)	/* arbitration */
+#define  XFER_STS_FIES_TX_CTRL		(0x2)	/* transmit control */
+#define  XFER_STS_FIES_TX_DATA		(0x3)	/* transmit data */
+#define  XFER_STS_FIES_TX_CRC		(0x4)	/* transmit crc */
+#define  XFER_STS_FIES_TX_FRM		(0x5)	/* transmit frame */
+#define  XFER_STS_FIES_RX_CTRL		(0x6)	/* receive control */
+#define  XFER_STS_FIES_RX_DATA		(0x7)	/* receive data */
+#define  XFER_STS_FIES_RX_CRC		(0x8)	/* receive crc */
+#define  XFER_STS_FIES_RX_FRM		(0x9)	/* receive frame */
+#define  XFER_STS_FIES_INTERMISSION	(0xa)	/* intermission */
+#define  XFER_STS_FIES_TX_SUSPD		(0xb)	/* transmit suspend */
+#define  XFER_STS_FIES_BUS_IDLE		(0xc)	/* bus idle */
+#define  XFER_STS_FIES_OVL_FLAG		(0xd)	/* overload flag */
+#define  XFER_STS_FIES_OVL_DLM		(0xe)	/* overload delimiter */
+#define  XFER_STS_FIES_ERR_FLAG		(0xf)	/* error flag */
+#define  XFER_STS_FIES_ERR_DLM		(0x10)	/* error delimiter */
+#define  XFER_STS_FIES_BUS_OFF		(0x11)	/* bus off */
+#define XFER_STS_TS			BIT(8)	/* Transmit status */
+#define XFER_STS_RS			BIT(9)	/* Receive status */
+#define XFER_STS_XFERS			BIT(10)	/* Transfer status */
+
+/* Error counter register (ERR_CNT) */
+#define ERR_CNT_REC		GENMASK(8, 0)	/* Receive error counter */
+#define ERR_CNT_TEC		GENMASK(24, 16)	/* Transmit error counter */
+
+/* FIFO counter register (FIFO_CNT) */
+#define FIFO_CNT_RFN		GENMASK(6, 0)	/* Receive FIFO valid data number */
+#define FIFO_CNT_TFN		GENMASK(22, 16)	/* Transmit FIFO valid data number */
+
+/* DMA request control register (DMA_CTRL) */
+#define DMA_CTRL_RFTH		GENMASK(5, 0)	/* Receive FIFO DMA request threshold */
+#define DMA_CTRL_RFRE		BIT(6)		/* Receive FIFO DMA request enable */
+#define DMA_CTRL_TFTH		GENMASK(21, 16)	/* Transmit FIFO DMA request threshold */
+#define DMA_CTRL_TFRE		BIT(22)		/* Transmit FIFO DMA request enable */
+
+/* Transfer enable register (XFER_EN) */
+#define XFER_EN_XFER		BIT(0)		/* Transfer enable */
+
+/* Interrupt register 1 (INTR1) */
+#define INTR1_RF1IS	BIT(0)	/* RX FIFO 1/4 interrupt status */
+#define INTR1_RF2IS	BIT(1)	/* RX FIFO 1/2 interrupt status */
+#define INTR1_RF3IS	BIT(2)	/* RX FIFO 3/4 interrupt status */
+#define INTR1_RF4IS	BIT(3)	/* RX FIFO full interrupt status */
+#define INTR1_TF1IS	BIT(4)	/* TX FIFO 1/4 interrupt status */
+#define INTR1_TF2IS	BIT(5)	/* TX FIFO 1/2 interrupt status */
+#define INTR1_TF3IS	BIT(6)	/* TX FIFO 3/4 interrupt status */
+#define INTR1_TF4IS	BIT(7)	/* TX FIFO empty interrupt status */
+#define INTR1_RF1IE	BIT(8)	/* RX FIFO 1/4 interrupt enable */
+#define INTR1_RF2IE	BIT(9)	/* RX FIFO 1/2 interrupt enable */
+#define INTR1_RF3IE	BIT(10)	/* RX FIFO 3/4 interrupt enable */
+#define INTR1_RF4IE	BIT(11)	/* RX FIFO full interrupt enable */
+#define INTR1_TF1IE	BIT(12)	/* TX FIFO 1/4 interrupt enable */
+#define INTR1_TF2IE	BIT(13)	/* TX FIFO 1/2 interrupt enable */
+#define INTR1_TF3IE	BIT(14)	/* TX FIFO 3/4 interrupt enable */
+#define INTR1_TF4IE	BIT(15)	/* TX FIFO empty interrupt enable */
+#define INTR1_RF1IC	BIT(16)	/* RX FIFO 1/4 interrupt clear */
+#define INTR1_RF2IC	BIT(17)	/* RX FIFO 1/2 interrupt clear */
+#define INTR1_RF3IC	BIT(18)	/* RX FIFO 3/4 interrupt clear */
+#define INTR1_RF4IC	BIT(19)	/* RX FIFO full interrupt clear */
+#define INTR1_TF1IC	BIT(20)	/* TX FIFO 1/4 interrupt clear */
+#define INTR1_TF2IC	BIT(21)	/* TX FIFO 1/2 interrupt clear */
+#define INTR1_TF3IC	BIT(22)	/* TX FIFO 3/4 interrupt clear */
+#define INTR1_TF4IC	BIT(23)	/* TX FIFO empty interrupt clear */
+#define INTR1_RF1RIS	BIT(24)	/* RX FIFO 1/4 raw interrupt status */
+#define INTR1_RF2RIS	BIT(25)	/* RX FIFO 1/2 raw interrupt status */
+#define INTR1_RF3RIS	BIT(26)	/* RX FIFO 3/4 raw interrupt status */
+#define INTR1_RF4RIS	BIT(27)	/* RX FIFO full raw interrupt status */
+#define INTR1_TF1RIS	BIT(28)	/* TX FIFO 1/4 raw interrupt status */
+#define INTR1_TF2RIS	BIT(29)	/* TX FIFO 1/2 raw interrupt status */
+#define INTR1_TF3RIS	BIT(30)	/* TX FIFO 3/4 raw interrupt status */
+#define INTR1_TF4RIS	BIT(31)	/* TX FIFO empty raw interrupt status */
+
+/* Frame valid number register (FRM_INFO) */
+#define FRM_INFO_RXFC	GENMASK(5, 0)	/* Valid frame number in RX FIFO */
+#define FRM_INFO_SSPD	GENMASK(31, 16)	/* Secondary sample point delay */
+
+/* Interrupt register 2 (INTR2) */
+#define INTR2_TOIS	BIT(0)	/* RX FIFO time out interrupt status */
+#define INTR2_TOIM	BIT(8)	/* RX FIFO time out interrupt mask */
+#define INTR2_TOIC	BIT(16)	/* RX FIFO time out interrupt clear */
+#define INTR2_TORIS	BIT(24)	/* RX FIFO time out raw interrupt status */
+
+/* RX information FIFO shadow register (RX_INFO_FIFO) */
+#define RX_INFO_FIFO_WNORF	GENMASK(4, 0)	/* Word (4-byte) number of current receive frame */
+#define RX_INFO_FIFO_RORF	BIT(5)		/* RTR value of current receive frame */
+#define RX_INFO_FIFO_FORF	BIT(6)		/* FDF value of current receive frame */
+#define RX_INFO_FIFO_IORF	BIT(7)		/* IDE value of current receive frame */
+
+/* Arbitration Bits */
+#define CAN_ID1_MASK		GENMASK(31, 21)	/* Base identifer */
+/* Standard Remote Transmission Request */
+#define CAN_ID1_RTR_MASK	BIT(20)
+/* Extended Substitute remote TXreq */
+#define	CAN_ID2_SRR_MASK	BIT(20)
+#define CAN_IDE_MASK		BIT(19)		/* IDentifier extension flag */
+#define CAN_ID2_MASK		GENMASK(18, 1)	/* Identifier extension */
+/* Extended frames remote TX request */
+#define CAN_ID2_RTR_MASK	BIT(0)
+#define CAN_ID1_FDF_MASK	BIT(18)
+#define CAN_ID1_DLC_MASK	GENMASK(17, 14)
+#define CANFD_ID1_BRS_MASK	BIT(16)
+#define CANFD_ID1_ESI_MASK	BIT(15)
+#define CANFD_ID1_DLC_MASK	GENMASK(14, 11)
+
+#define CAN_ID2_FDF_MASK	BIT(31)
+#define CAN_ID2_DLC_MASK	GENMASK(29, 26)
+#define CANFD_ID2_BRS_MASK	BIT(29)
+#define CANFD_ID2_ESI_MASK	BIT(28)
+#define CANFD_ID2_DLC_MASK	GENMASK(27, 24)
+
+#define CAN_ID1_DLC_OFF		14
+#define CANFD_ID1_DLC_OFF	11
+#define CAN_ID2_DLC_OFF		26
+#define CANFD_ID2_DLC_OFF	24
+
+#define CAN_IDR_ID1_SHIFT       21  /* Standard Messg Identifier */
+#define CAN_IDR_ID2_SHIFT       1   /* Extended Message Identifier */
+#define CAN_IDR_SDLC_SHIFT      14
+#define CAN_IDR_EDLC_SHIFT      26
+
+/* CANFD Standard msg padding 1 */
+#define CANFD_IDR_PAD_MASK	0x000007FF
+#define CAN_IDR_PAD_MASK	0x00003FFF	/* Standard msg padding 1 */
+
+/**
+ * phytium_can_set_reg_bits - set a bit value to the device register
+ * @cdev:	Driver private data structure
+ * @reg:	Register offset
+ * @bs:     The bit mask
+ *
+ * Read data from the particular CAN register
+ * Return: value read from the CAN register
+ */
+static void
+phytium_can_set_reg_bits(const struct phytium_can_dev *cdev,
+			 enum phytium_can_reg reg, u32 bs)
+{
+	u32 val = readl(cdev->base + reg);
+
+	val |= bs;
+	writel(val, cdev->base + reg);
+}
+
+/**
+ * phytium_can_clr_reg_bits - clear a bit value to the device register
+ * @cdev:	Driver private data structure
+ * @reg:	Register offset
+ * @bs:     The bit mask
+ *
+ * Read data from the particular CAN register
+ * Return: value read from the CAN register
+ */
+static void
+phytium_can_clr_reg_bits(const struct phytium_can_dev *cdev,
+			 enum phytium_can_reg reg, u32 bs)
+{
+	u32 val = readl(cdev->base + reg);
+
+	val &= ~bs;
+	writel(val, cdev->base + reg);
+}
+
+static inline u32 phytium_can_read(const struct phytium_can_dev *cdev, enum phytium_can_reg reg)
+{
+	return readl(cdev->base + reg);
+}
+
+static inline void phytium_can_write(const struct phytium_can_dev *cdev, enum phytium_can_reg reg,
+			      u32 val)
+{
+	writel(val, cdev->base + reg);
+}
+
+static inline void phytium_can_enable_all_interrupts(struct phytium_can_dev *cdev)
+{
+	phytium_can_write(cdev, CAN_INTR, INTR_EN_MASK);
+}
+
+static inline void phytium_can_disable_all_interrupt(struct phytium_can_dev *cdev)
+{
+	phytium_can_write(cdev, CAN_INTR, 0x0);
+}
+
+static int phytium_can_get_berr_counter(const struct net_device *dev,
+					struct can_berr_counter *bec)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+
+	bec->rxerr = phytium_can_read(cdev, CAN_ERR_CNT) & ERR_CNT_REC;
+	bec->txerr = (phytium_can_read(cdev, CAN_ERR_CNT) & ERR_CNT_TEC) >> 16;
+
+	return 0;
+}
+
+static int phytium_can_read_fifo(struct net_device *dev)
+{
+	struct net_device_stats *stats = &dev->stats;
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 id, dlc, i;
+
+	/* Read the frame header from FIFO */
+	id = phytium_can_read(cdev, CAN_RX_FIFO);
+	id = be32_to_cpup(&id);
+	if (id & CAN_IDE_MASK) {
+		/* Received an extended frame */
+		dlc = phytium_can_read(cdev, CAN_RX_FIFO);
+		dlc = be32_to_cpup(&dlc);
+		if (dlc & CAN_ID2_FDF_MASK)
+			skb = alloc_canfd_skb(dev, &cf);
+		else
+			skb = alloc_can_skb(dev, (struct can_frame **)&cf);
+
+		if (unlikely(!skb)) {
+			stats->rx_dropped++;
+			return 0;
+		}
+
+		if (dlc & CAN_ID2_FDF_MASK) {
+			/* CAN FD extended frame */
+			if (dlc & CANFD_ID2_BRS_MASK)
+				cf->flags |= CANFD_BRS;
+			if (dlc & CANFD_ID2_ESI_MASK)
+				cf->flags |= CANFD_ESI;
+			cf->len = can_dlc2len((dlc & CANFD_ID2_DLC_MASK) >> CANFD_ID2_DLC_OFF);
+		} else {
+			/* CAN extended frame */
+			cf->len = get_can_dlc((dlc & CAN_ID2_DLC_MASK) >> CAN_ID2_DLC_OFF);
+		}
+
+		cf->can_id = (id & CAN_ID1_MASK) >> 3;
+		cf->can_id |= (id & CAN_ID2_MASK) >> 1;
+		cf->can_id |= CAN_EFF_FLAG;
+
+		if (id & CAN_ID2_RTR_MASK)
+			cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		/* Received a standard frame */
+		if (id & CAN_ID1_FDF_MASK)
+			skb = alloc_canfd_skb(dev, &cf);
+		else
+			skb = alloc_can_skb(dev, (struct can_frame **)&cf);
+
+		if (unlikely(!skb)) {
+			stats->rx_dropped++;
+			return 0;
+		}
+
+		if (id & CAN_ID1_FDF_MASK) {
+			/* CAN FD extended frame */
+			if (id & CANFD_ID1_BRS_MASK)
+				cf->flags |= CANFD_BRS;
+			if (id & CANFD_ID1_ESI_MASK)
+				cf->flags |= CANFD_ESI;
+			cf->len = can_dlc2len((id & CANFD_ID1_DLC_MASK) >> CANFD_ID1_DLC_OFF);
+		} else {
+			/* CAN extended frame */
+			cf->len = get_can_dlc((id & CAN_ID1_DLC_MASK) >> CAN_ID1_DLC_OFF);
+		}
+
+		cf->can_id = (id & CAN_ID1_MASK) >> 21;
+
+		if (id & CAN_ID1_RTR_MASK)
+			cf->can_id |= CAN_RTR_FLAG;
+	}
+
+	if (!(cf->can_id & CAN_RTR_FLAG))
+		/* Receive data frames */
+		for (i = 0; i < cf->len; i += 4)
+			*(__be32 *)(cf->data + i) = phytium_can_read(cdev, CAN_RX_FIFO);
+
+	stats->rx_packets++;
+	stats->rx_bytes += cf->len;
+	netif_receive_skb(skb);
+
+	return 1;
+}
+
+static int phytium_can_do_rx_poll(struct net_device *dev, int quota)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	u32 rxfs, pkts = 0;
+
+	rxfs = phytium_can_read(cdev, CAN_FIFO_CNT) & FIFO_CNT_RFN;
+	if (!rxfs) {
+		netdev_dbg(dev, "no messages in RX FIFO\n");
+		return 0;
+	}
+
+	while ((rxfs != 0) && (quota > 0)) {
+		pkts += phytium_can_read_fifo(dev);
+		quota--;
+		rxfs = phytium_can_read(cdev, CAN_FIFO_CNT) & FIFO_CNT_RFN;
+		netdev_dbg(dev, "Next received %d frame again.\n", rxfs);
+	}
+
+	if (pkts)
+		can_led_event(dev, CAN_LED_EVENT_RX);
+
+	return pkts;
+}
+
+static int phytium_can_rx_handler(struct net_device *dev, int quota)
+{
+	int work_done = 0;
+	int rx_work_or_err;
+
+	/* Handle RX IRQ */
+	rx_work_or_err = phytium_can_do_rx_poll(dev, (quota - work_done));
+	if (rx_work_or_err < 0)
+		return rx_work_or_err;
+
+	work_done += rx_work_or_err;
+
+	return 0;
+}
+
+static int phytium_can_poll(struct napi_struct *napi, int quota)
+{
+	struct net_device *dev = napi->dev;
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	int work_done;
+	unsigned long flags;
+
+	netdev_dbg(dev, "The receive processing is going on !\n");
+
+	work_done = phytium_can_rx_handler(dev, quota);
+
+	/* Don't re-enable interrupts if the driver had a fatal error
+	 * (e.g., FIFO read failure)
+	 */
+	if (work_done >= 0 && work_done < quota) {
+		napi_complete_done(napi, work_done);
+		spin_lock_irqsave(&cdev->lock, flags);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_REIE);
+		spin_unlock_irqrestore(&cdev->lock, flags);
+	}
+
+	return work_done;
+}
+
+static void phytium_can_write_frame(struct phytium_can_dev *cdev)
+{
+	struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;
+	struct net_device *dev = cdev->net;
+	struct net_device_stats *stats = &dev->stats;
+	struct sk_buff *skb = cdev->tx_skb;
+	u32 i, id, dlc = 0, frame_head[2] = {0, 0};
+	u32 data_len;
+
+	data_len = can_len2dlc(cf->len);
+	cdev->tx_skb = NULL;
+
+	/* Watch carefully on the bit sequence */
+	if (cf->can_id & CAN_EFF_FLAG) {
+		/* Extended CAN ID format */
+		id = ((cf->can_id & CAN_EFF_MASK) << 1) & CAN_ID2_MASK;
+		id |= (((cf->can_id & CAN_EFF_MASK) >>
+			(CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) <<
+			CAN_IDR_ID1_SHIFT) & CAN_ID1_MASK;
+
+		/* The substibute remote TX request bit should be "1"
+		 * for extended frames as in the Phytium CAN datasheet
+		 */
+		id |= CAN_IDE_MASK | CAN_ID2_SRR_MASK;
+
+		if (cf->can_id & CAN_RTR_FLAG)
+			/* Extended frames remote TX request */
+			id |= CAN_ID2_RTR_MASK;
+		if ((cdev->can.ctrlmode & CAN_CTRLMODE_FD) &&
+		    can_is_canfd_skb(skb))
+			dlc = data_len << CANFD_ID2_DLC_OFF;
+		else
+			dlc = data_len << CAN_ID2_DLC_OFF;
+
+		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
+			dlc |= CAN_ID2_FDF_MASK;
+			if (cf->flags & CANFD_BRS)
+				dlc |= CANFD_ID2_BRS_MASK;
+			if (cf->flags & CANFD_ESI)
+				dlc |= CANFD_ID2_ESI_MASK;
+		}
+
+		frame_head[0] = cpu_to_be32p(&id);
+		frame_head[1] = cpu_to_be32p(&dlc);
+
+		/* Write the Frame to Phytium CAN TX FIFO */
+		phytium_can_write(cdev, CAN_TX_FIFO, frame_head[0]);
+		phytium_can_write(cdev, CAN_TX_FIFO, frame_head[1]);
+		netdev_dbg(dev, "Write atbitration field [0]:0x%x [1]:0x%x\n",
+			   frame_head[0], frame_head[1]);
+	} else {
+		/* Standard CAN ID format */
+		id = ((cf->can_id & CAN_SFF_MASK) << CAN_IDR_ID1_SHIFT)
+			& CAN_ID1_MASK;
+
+		if (cf->can_id & CAN_RTR_FLAG)
+			/* Standard frames remote TX request */
+			id |= CAN_ID1_RTR_MASK;
+
+		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
+			dlc = (data_len << CANFD_ID1_DLC_OFF)
+				| CANFD_IDR_PAD_MASK;
+		else
+			dlc = (data_len << CAN_ID1_DLC_OFF) | CAN_IDR_PAD_MASK;
+
+		id |= dlc;
+
+		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
+			id |= CAN_ID1_FDF_MASK;
+			if (cf->flags & CANFD_BRS)
+				id |= CANFD_ID1_BRS_MASK;
+			if (cf->flags & CANFD_ESI)
+				id |= CANFD_ID1_ESI_MASK;
+		}
+
+		frame_head[0] =  cpu_to_be32p(&id);
+		/* Write the Frame to Phytium CAN TX FIFO */
+		phytium_can_write(cdev, CAN_TX_FIFO, frame_head[0]);
+		netdev_dbg(dev, "Write atbitration field [0] 0x%x\n",
+			   frame_head[0]);
+	}
+
+	if (!(cf->can_id & CAN_RTR_FLAG)) {
+		netdev_dbg(dev, "Write CAN data frame\n");
+		for (i = 0; i < cf->len; i += 4) {
+			phytium_can_write(cdev, CAN_TX_FIFO,
+					  *(__be32 *)(cf->data + i));
+			netdev_dbg(dev, "[%d]:%x\n", i,
+				   *(__be32 *)(cf->data + i));
+		}
+	}
+
+	stats->tx_bytes += cf->len;
+	stats->tx_packets++;
+	netdev_dbg(dev, "Trigger send message!\n");
+	can_put_echo_skb(skb, dev, 0);
+	can_get_echo_skb(dev, 0);
+	return;
+}
+
+static netdev_tx_t phytium_can_tx_handler(struct phytium_can_dev *cdev)
+{
+	struct net_device *dev = cdev->net;
+	u32 tx_fifo_used;
+	unsigned long flags;
+
+	phytium_can_write_frame(cdev);
+
+	/* Check if the TX buffer is full */
+	tx_fifo_used = 4 * ((phytium_can_read(cdev, CAN_FIFO_CNT) & FIFO_CNT_TFN) >> 16);
+	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
+		if (CAN_FIFO_BYTE_LEN - tx_fifo_used <= KEEP_CANFD_FIFO_MIN_LEN) {
+			netif_stop_queue(dev);
+			spin_lock_irqsave(&cdev->lock, flags);
+			cdev->is_stop_queue_flag = STOP_QUEUE_TRUE;
+			spin_unlock_irqrestore(&cdev->lock, flags);
+		}
+	} else {
+		if (CAN_FIFO_BYTE_LEN - tx_fifo_used  <= KEEP_CAN_FIFO_MIN_LEN) {
+			netif_stop_queue(dev);
+			spin_lock_irqsave(&cdev->lock, flags);
+			cdev->is_stop_queue_flag = STOP_QUEUE_TRUE;
+			spin_unlock_irqrestore(&cdev->lock, flags);
+		}
+	}
+
+	return NETDEV_TX_OK;
+}
+
+/**
+ * phytium_can_tx_interrupt - Tx Done Isr
+ * @ndev:	net_device pointer
+ * @isr:	Interrupt status register value
+ */
+static void phytium_can_tx_interrupt(struct net_device *ndev, u32 isr)
+{
+	struct phytium_can_dev *cdev = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 tx_fifo_used = 0;
+
+	if (isr & INTR_TEIS) {
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_TEIC);
+	}
+
+	/* Check if the TX buffer is full */
+	if (cdev->is_stop_queue_flag) {
+		tx_fifo_used =  4 * ((phytium_can_read(cdev, CAN_FIFO_CNT) & FIFO_CNT_TFN) >> 16);
+		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
+			if (CAN_FIFO_BYTE_LEN - tx_fifo_used > KEEP_CANFD_FIFO_MIN_LEN) {
+				netif_wake_queue(ndev);
+				cdev->is_stop_queue_flag = STOP_QUEUE_FALSE;
+			}
+		} else {
+			if (CAN_FIFO_BYTE_LEN - tx_fifo_used  > KEEP_CAN_FIFO_MIN_LEN) {
+				netif_wake_queue(ndev);
+				cdev->is_stop_queue_flag = STOP_QUEUE_FALSE;
+			}
+		}
+	}
+	netdev_dbg(ndev, "Finish transform packets %lu\n", stats->tx_packets);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static void phytium_can_err_interrupt(struct net_device *ndev, u32 isr)
+{
+	struct phytium_can_dev *cdev = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32  txerr = 0, rxerr = 0;
+
+	skb = alloc_can_err_skb(ndev, &cf);
+
+	rxerr = phytium_can_read(cdev, CAN_ERR_CNT) & ERR_CNT_REC;
+	txerr = ((phytium_can_read(cdev, CAN_ERR_CNT) & ERR_CNT_TEC) >> 16);
+
+	if (isr & INTR_BOIS) {
+		netdev_dbg(ndev, "bus_off %s: txerr :%u rxerr :%u\n",
+			   __func__, txerr, rxerr);
+		cdev->can.state = CAN_STATE_BUS_OFF;
+		cdev->can.can_stats.bus_off++;
+		/* Leave device in Config Mode in bus-off state */
+		phytium_can_write(cdev, CAN_CTRL, CTRL_RST);
+		can_bus_off(ndev);
+		if (skb)
+			cf->can_id |= CAN_ERR_BUSOFF;
+	} else if ((isr & INTR_PEIS) == INTR_PEIS) {
+		netdev_dbg(ndev, "error_passive %s: txerr :%u rxerr :%u\n",
+			   __func__, txerr, rxerr);
+		cdev->can.state = CAN_STATE_ERROR_PASSIVE;
+		cdev->can.can_stats.error_passive++;
+		/* Clear interrupt condition */
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_PEIC);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_PWIC);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_TEIC);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_EIC);
+		if (skb) {
+			cf->can_id |= CAN_ERR_CRTL;
+			cf->data[1] = (rxerr > 127) ?
+					CAN_ERR_CRTL_RX_PASSIVE :
+					CAN_ERR_CRTL_TX_PASSIVE;
+			cf->data[6] = txerr;
+			cf->data[7] = rxerr;
+		}
+	} else if (isr & INTR_PWIS) {
+		netdev_dbg(ndev, "error_warning %s: txerr :%u rxerr :%u\n",
+			   __func__, txerr, rxerr);
+		cdev->can.state = CAN_STATE_ERROR_WARNING;
+		cdev->can.can_stats.error_warning++;
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_PWIC);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_TEIC);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_EIC);
+		if (skb) {
+			cf->can_id |= CAN_ERR_CRTL;
+			cf->data[1] |= (txerr > rxerr) ?
+					CAN_ERR_CRTL_TX_WARNING :
+					CAN_ERR_CRTL_RX_WARNING;
+			cf->data[6] = txerr;
+			cf->data[7] = rxerr;
+		}
+	}
+
+	/* Check for RX FIFO Overflow interrupt */
+	if (isr & INTR_RFIS) {
+		stats->rx_over_errors++;
+		stats->rx_errors++;
+
+		if (skb) {
+			cf->can_id |= CAN_ERR_CRTL;
+			cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
+		}
+	}
+
+	if (skb) {
+		stats->rx_packets++;
+		stats->rx_bytes += cf->can_dlc;
+		netif_rx(skb);
+	}
+}
+
+/**
+ * phytium_can_isr - CAN Isr
+ * @irq:	irq number
+ * @dev_id:	device id poniter
+ *
+ * This is the phytium CAN Isr. It checks for the type of interrupt
+ * and invokes the corresponding ISR.
+ *
+ * Return:
+ * * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
+ */
+static irqreturn_t phytium_can_isr(int irq, void *dev_id)
+{
+	struct net_device *dev = (struct net_device *)dev_id;
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	u32 isr;
+
+	/* Get the interrupt status */
+	isr = phytium_can_read(cdev, CAN_INTR) & INTR_STATUS_MASK;
+	if (!isr)
+		return IRQ_NONE;
+	spin_lock(&cdev->lock);
+	/* Check for FIFO full interrupt and alarm */
+	if ((isr & INTR_RFIS)) {
+		netdev_dbg(dev, "rx_fifo is full!.\n");
+		phytium_can_clr_reg_bits(cdev, CAN_INTR, INTR_RFIE);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_RFIC);
+		napi_schedule(&cdev->napi);
+	}
+
+	/* Check for the type of error interrupt and Processing it */
+	if (isr & (INTR_EIS | INTR_RFIS | INTR_BOIS)) {
+		phytium_can_clr_reg_bits(cdev, CAN_INTR, (INTR_EIE
+					| INTR_RFIE | INTR_BOIE));
+		phytium_can_err_interrupt(dev, isr);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, (INTR_EIC
+					| INTR_RFIC | INTR_BOIC));
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_EIE | INTR_BOIE);
+		spin_unlock(&cdev->lock);
+		return IRQ_HANDLED;
+	}
+
+	/* Check for Tx interrupt and Processing it */
+	if (isr & INTR_TEIS) {
+		phytium_can_tx_interrupt(dev, isr);
+	}
+
+	/* Check for the type of receive interrupt and Processing it */
+	if (isr & INTR_REIS) {
+		phytium_can_clr_reg_bits(cdev, CAN_INTR, INTR_REIE);
+		phytium_can_set_reg_bits(cdev, CAN_INTR, INTR_REIC);
+		napi_schedule(&cdev->napi);
+	}
+	spin_unlock(&cdev->lock);
+	return IRQ_HANDLED;
+}
+
+/**
+ * phytium_can_set_bittiming - CAN set bit timing routine
+ * @dev:	Pointer to net_device structure
+ *
+ * This is the driver set bittiming  routine.
+ * Return: 0 on success and failure value on error
+ */
+static int phytium_can_set_bittiming(struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	const struct can_bittiming *bt = &cdev->can.bittiming;
+	const struct can_bittiming *dbt = &cdev->can.data_bittiming;
+	u32 btr, dbtr;
+	u32 is_config_mode;
+
+	/**
+	 * Check whether Phytium CAN is in configuration mode.
+	 * It cannot set bit timing if Phytium CAN is not in configuration mode.
+	 */
+	is_config_mode = phytium_can_read(cdev, CAN_CTRL) & CTRL_XFER;
+	if (is_config_mode) {
+		netdev_alert(dev, "BUG! Cannot set bittiming - CAN is not in config mode\n");
+		return -EPERM;
+	}
+
+	/* Setting Baud Rate prescalar value in BRPR Register */
+	btr = (bt->brp - 1) << 16;
+
+	/* Setting Time Segment 1 in BTR Register */
+	btr |= (bt->prop_seg - 1) << 2;
+
+	btr |= (bt->phase_seg1 - 1) << 5;
+
+	/* Setting Time Segment 2 in BTR Register */
+	btr |= (bt->phase_seg2 - 1) << 8;
+
+	/* Setting Synchronous jump width in BTR Register */
+	btr |= (bt->sjw - 1);
+
+	dbtr = (dbt->brp - 1) << 16;
+	dbtr |= (dbt->prop_seg - 1) << 2;
+	dbtr |= (dbt->phase_seg1 - 1) << 5;
+	dbtr |= (dbt->phase_seg2 - 1) << 8;
+	dbtr |= (dbt->sjw - 1);
+
+	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
+		phytium_can_write(cdev, CAN_ARB_RATE_CTRL, btr);
+		phytium_can_write(cdev, CAN_DAT_RATE_CTRL, dbtr);
+	} else {
+		phytium_can_write(cdev, CAN_ARB_RATE_CTRL, btr);
+		phytium_can_write(cdev, CAN_DAT_RATE_CTRL, btr);
+	}
+
+	netdev_dbg(dev, "DAT=0x%08x, ARB=0x%08x\n",
+		   phytium_can_read(cdev, CAN_DAT_RATE_CTRL),
+		   phytium_can_read(cdev, CAN_ARB_RATE_CTRL));
+
+	return 0;
+}
+
+/**
+ * phytium_can_start - This the drivers start routine
+ * @dev:	Pointer to net_device structure
+ *
+ * This is the drivers start routine.
+ * Based on the State of the CAN device it puts
+ * the CAN device into a proper mode.
+ *
+ * Return: 0 on success and failure value on error
+ */
+static void phytium_can_start(struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	u32 ctrl;
+
+	/* Disable transfer */
+	ctrl = phytium_can_read(cdev, CAN_CTRL);
+	ctrl &= ~CTRL_XFER;
+	phytium_can_write(cdev, CAN_CTRL, ctrl);
+
+	/* XXX: If CANFD, reset the controller */
+	phytium_can_write(cdev, CAN_CTRL, (ctrl | CTRL_RST));
+
+	/* Bittiming setup */
+	phytium_can_set_bittiming(dev);
+
+	/* Acceptance identifier mask setup */
+	phytium_can_write(cdev, CAN_ACC_ID0_MASK, ACC_IDX_MASK_AID_MASK);
+	phytium_can_write(cdev, CAN_ACC_ID1_MASK, ACC_IDX_MASK_AID_MASK);
+	phytium_can_write(cdev, CAN_ACC_ID2_MASK, ACC_IDX_MASK_AID_MASK);
+	phytium_can_write(cdev, CAN_ACC_ID3_MASK, ACC_IDX_MASK_AID_MASK);
+	ctrl |= CTRL_AIME;
+
+	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
+		ctrl |= CTRL_IOF | CTRL_FDCRC;
+
+	phytium_can_write(cdev, CAN_CTRL, ctrl);
+
+	cdev->can.state = CAN_STATE_ERROR_ACTIVE;
+
+	phytium_can_enable_all_interrupts(cdev);
+
+	if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
+		ctrl |= CTRL_XFER;
+	else
+		ctrl |= CTRL_XFER | CTRL_TXREQ;
+
+	phytium_can_write(cdev, CAN_CTRL, ctrl);
+}
+
+/**
+ * phytium_can_stop - Driver stop routine
+ * @dev:	Pointer to net_device structure
+ *
+ * This is the drivers stop routine. It will disable the
+ * interrupts and put the device into configuration mode.
+ */
+static void phytium_can_stop(struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	u32 ctrl;
+
+	/* Disable all interrupts */
+	phytium_can_disable_all_interrupt(cdev);
+	
+	/* Disable transfer and switch to receive-only mode */
+	ctrl = phytium_can_read(cdev, CAN_CTRL);
+	ctrl &= ~(CTRL_XFER | CTRL_TXREQ);
+	phytium_can_write(cdev, CAN_CTRL, ctrl);
+
+	/* Set the state as STOPPED */
+	cdev->can.state = CAN_STATE_STOPPED;
+}
+
+static void phytium_can_clean(struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+
+	if (cdev->tx_skb) {
+		dev->stats.tx_errors++;
+		can_free_echo_skb(cdev->net, 0);
+		cdev->tx_skb = NULL;
+	}
+}
+
+static int phytium_can_set_mode(struct net_device *dev, enum can_mode mode)
+{
+	switch (mode) {
+	case CAN_MODE_START:
+		phytium_can_clean(dev);
+		phytium_can_start(dev);
+		netif_wake_queue(dev);
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+	return 0;
+}
+
+/**
+ * phytium_can_open - Driver open routine
+ * @dev:	Pointer to net_device structure
+ *
+ * This is the driver open routine.
+ * Return: 0 on success and failure value on error
+ */
+static int phytium_can_open(struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+	int ret;
+
+	ret = pm_runtime_get_sync(cdev->dev);
+	if (ret < 0) {
+		netdev_err(dev, "%s: pm_runtime_get failed(%d)\n",
+					 __func__, ret);
+		return ret;
+	}
+	/* Open the CAN device */
+	ret = open_candev(dev);
+	if (ret) {
+		netdev_err(dev, "failed to open can device\n");
+		goto disable_clk;
+	}
+
+	/* Register interrupt handler */
+	ret = request_irq(dev->irq, phytium_can_isr,
+			  IRQF_SHARED, dev->name, dev);
+	if (ret < 0) {
+		netdev_err(dev, "failed to request interrupt\n");
+		goto fail;
+	}
+
+	/* Start the controller */
+	phytium_can_start(dev);
+
+	can_led_event(dev, CAN_LED_EVENT_OPEN);
+	napi_enable(&cdev->napi);
+	cdev->is_stop_queue_flag = STOP_QUEUE_FALSE;
+	netif_start_queue(dev);
+
+	return 0;
+
+fail:
+	pm_runtime_put(cdev->dev);
+	close_candev(dev);
+disable_clk:
+	pm_runtime_put_sync(cdev->dev);
+	return ret;
+}
+
+/**
+ * phytium_can_close - Driver close routine
+ * @dev:	Pointer to net_device structure
+ *
+ * Return: 0 always
+ */
+static int phytium_can_close(struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+
+	netif_stop_queue(dev);
+	napi_disable(&cdev->napi);
+
+	phytium_can_stop(dev);
+	free_irq(dev->irq, dev);
+	pm_runtime_put_sync(cdev->dev);
+
+	close_candev(dev);
+	can_led_event(dev, CAN_LED_EVENT_STOP);
+
+	return 0;
+}
+
+/**
+ * phytium_can_start_xmit - Starts the transmission
+ *
+ * Return: 0 on success.
+ */
+static netdev_tx_t phytium_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+
+	if (can_dropped_invalid_skb(dev, skb))
+		return NETDEV_TX_OK;
+
+	cdev->tx_skb = skb;
+
+	return phytium_can_tx_handler(cdev);
+}
+
+static const struct net_device_ops phytium_can_netdev_ops = {
+	.ndo_open = phytium_can_open,
+	.ndo_stop = phytium_can_close,
+	.ndo_start_xmit = phytium_can_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int register_phytium_can_dev(struct net_device *dev)
+{
+	dev->flags |= IFF_ECHO;
+	dev->netdev_ops = &phytium_can_netdev_ops;
+
+	return register_candev(dev);
+}
+
+static int phytium_can_dev_setup(struct phytium_can_dev *cdev)
+{
+	struct net_device *dev = cdev->net;
+
+	netif_napi_add(dev, &cdev->napi, phytium_can_poll, 64);
+
+	cdev->can.do_set_mode = phytium_can_set_mode;
+	cdev->can.do_get_berr_counter = phytium_can_get_berr_counter;
+
+	cdev->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
+				       CAN_CTRLMODE_BERR_REPORTING;
+	cdev->can.bittiming_const = cdev->bit_timing;
+
+	if (cdev->fdmode) {
+		cdev->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
+		dev->mtu = CANFD_MTU;
+		cdev->can.ctrlmode = CAN_CTRLMODE_FD;
+		cdev->can.data_bittiming_const = cdev->bit_timing;
+	}
+	spin_lock_init(&cdev->lock);
+	return 0;
+}
+
+struct phytium_can_dev *phytium_can_allocate_dev(struct device *dev, int sizeof_priv,
+						 int tx_fifo_depth)
+{
+	struct phytium_can_dev *cdev = NULL;
+	struct net_device *net_dev;
+
+	/* Allocate the can device struct */
+	net_dev = alloc_candev(sizeof_priv, tx_fifo_depth);
+	if (!net_dev) {
+		dev_err(dev, "Failed to allocate CAN device.\n");
+		goto out;
+	}
+
+	cdev = netdev_priv(net_dev);
+	cdev->net = net_dev;
+	cdev->dev = dev;
+	SET_NETDEV_DEV(net_dev, dev);
+
+out:
+	return cdev;
+}
+EXPORT_SYMBOL(phytium_can_allocate_dev);
+
+void phytium_can_free_dev(struct net_device *net)
+{
+	free_candev(net);
+}
+EXPORT_SYMBOL(phytium_can_free_dev);
+
+int phytium_can_register(struct phytium_can_dev *cdev)
+{
+	int ret;
+
+	ret = phytium_can_dev_setup(cdev);
+	if (ret)
+		goto fail;
+
+	ret = register_phytium_can_dev(cdev->net);
+	if (ret) {
+		dev_err(cdev->dev, "registering %s failed (err=%d)\n",
+			cdev->net->name, ret);
+		goto fail;
+	}
+
+	devm_can_led_init(cdev->net);
+
+	dev_info(cdev->dev, "%s device registered (irq=%d)\n",
+		 KBUILD_MODNAME, cdev->net->irq);
+
+	/* Probe finished
+	 * Stop clocks. They will be reactivated once the device is opened.
+	 */
+	pm_runtime_put_sync(cdev->dev);
+
+	return 0;
+
+fail:
+	pm_runtime_put_sync(cdev->dev);
+	return ret;
+}
+EXPORT_SYMBOL(phytium_can_register);
+
+void phytium_can_unregister(struct phytium_can_dev *cdev)
+{
+	unregister_candev(cdev->net);
+}
+EXPORT_SYMBOL(phytium_can_unregister);
+
+int phytium_can_suspend(struct device *dev)
+{
+	struct net_device *ndev = dev_get_drvdata(dev);
+	struct phytium_can_dev *cdev = netdev_priv(ndev);
+
+	if (netif_running(ndev)) {
+		netif_stop_queue(ndev);
+		netif_device_detach(ndev);
+		phytium_can_stop(ndev);
+		pm_runtime_put_sync(cdev->dev);
+	}
+
+	cdev->can.state = CAN_STATE_SLEEPING;
+
+	return 0;
+}
+EXPORT_SYMBOL(phytium_can_suspend);
+
+int phytium_can_resume(struct device *dev)
+{
+	struct net_device *ndev = dev_get_drvdata(dev);
+	struct phytium_can_dev *cdev = netdev_priv(ndev);
+	int ret;
+
+	cdev->can.state = CAN_STATE_ERROR_ACTIVE;
+
+	if (netif_running(ndev)) {
+		ret = pm_runtime_resume(cdev->dev);
+		if (ret)
+			return ret;
+
+		phytium_can_start(ndev);
+		netif_device_attach(ndev);
+		netif_start_queue(ndev);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(phytium_can_resume);
+
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("CAN bus driver for Phytium CAN controller");
+
diff --git a/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can.h b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can.h
new file mode 100644
index 00000000000000..400571b745dce6
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Phytium CAN controller driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef _PHYTIUM_CAN_H_
+#define _PHYTIUM_CAN_H_
+
+#include <linux/can/core.h>
+#include <linux/can/dev.h>
+
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/iopoll.h>
+
+#define KEEP_CAN_FIFO_MIN_LEN 16
+#define KEEP_CANFD_FIFO_MIN_LEN	128
+#define CAN_FIFO_BYTE_LEN 256
+#define STOP_QUEUE_TRUE		1
+#define STOP_QUEUE_FALSE	0
+
+enum phytium_can_ip_type {
+	PHYTIUM_CAN = 0,
+	PHYTIUM_CANFD,
+};
+
+struct phytium_can_devtype {
+	enum phytium_can_ip_type cantype;
+	const struct can_bittiming_const *bittiming_const;
+};
+
+struct phytium_can_dev {
+	struct can_priv can;
+	unsigned int tx_head;
+	unsigned int tx_tail;
+	unsigned int tx_max;
+	struct napi_struct napi;
+	struct net_device *net;
+	struct device *dev;
+	struct clk *clk;
+
+	struct sk_buff *tx_skb;
+
+	const struct can_bittiming_const *bit_timing;
+	spinlock_t lock;
+	int fdmode;
+	u32 isr;
+	u32 tx_fifo_depth;
+	unsigned int is_stop_queue_flag;
+	struct completion comp;
+	void __iomem *base;
+};
+
+struct phytium_can_dev *phytium_can_allocate_dev(struct device *dev, int sizeof_priv,
+						 int tx_fifo_depth);
+void phytium_can_free_dev(struct net_device *net);
+
+int phytium_can_register(struct phytium_can_dev *cdev);
+void phytium_can_unregister(struct phytium_can_dev *cdev);
+
+int phytium_can_suspend(struct device *dev);
+int phytium_can_resume(struct device *dev);
+#endif /* _PHYTIUM_CAN_H_ */
diff --git a/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can_pci.c b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can_pci.c
new file mode 100644
index 00000000000000..ae4a6f877432c1
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can_pci.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Platform CAN bus driver for Phytium CAN controller
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/pci.h>
+
+#include "phytium_can.h"
+
+struct phytium_can_pci_config {
+	const struct phytium_can_devtype *devtype;
+	unsigned int clock_freq;
+	unsigned int tx_fifo_depth;
+};
+
+#define cdev2priv(dev) container_of(dev, struct phytium_can_pci, cdev)
+
+struct phytium_can_pci {
+	struct phytium_can_dev cdev;
+
+	void __iomem *base;
+};
+
+static const struct can_bittiming_const phytium_bittiming_const_8192 = {
+	.name = "phytium_can",
+	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
+	.tseg1_max = 16,
+	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
+	.tseg2_max = 8,
+	.sjw_max = 4,		/* Synchronisation jump width */
+	.brp_min = 1,		/* Bit-rate prescaler */
+	.brp_max = 8192,
+	.brp_inc = 2,
+};
+
+static const struct phytium_can_devtype phytium_can_pci = {
+	.cantype = PHYTIUM_CAN,
+	.bittiming_const = &phytium_bittiming_const_8192,
+};
+
+static const struct phytium_can_pci_config phytium_can_pci_data = {
+	.devtype = &phytium_can_pci,
+	.clock_freq = 600000000,
+	.tx_fifo_depth = 64,
+};
+
+static int phytium_can_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	const struct phytium_can_pci_config *cfg;
+	struct phytium_can_dev *cdev;
+	struct phytium_can_pci *priv;
+	int ret;
+
+	cfg = (const struct phytium_can_pci_config *)id->driver_data;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		goto err;
+
+	ret = pcim_iomap_regions(pdev, 0x1, pci_name(pdev));
+	if (ret)
+		goto err;
+
+	cdev = phytium_can_allocate_dev(&pdev->dev, sizeof(struct phytium_can_pci),
+					cfg->tx_fifo_depth);
+	if (!cdev)
+		return -ENOMEM;
+
+	priv = cdev2priv(cdev);
+	priv->base = pcim_iomap_table(pdev)[0];
+
+	cdev->dev = &pdev->dev;
+	cdev->fdmode = cfg->devtype->cantype;
+	cdev->bit_timing = cfg->devtype->bittiming_const;
+	cdev->can.clock.freq = cfg->clock_freq;
+	cdev->tx_fifo_depth = cfg->tx_fifo_depth;
+
+	cdev->tx_head = 0;
+	cdev->tx_tail = 0;
+	cdev->tx_max = cfg->tx_fifo_depth;
+
+	cdev->base = priv->base;
+	cdev->net->irq = pdev->irq;
+
+	pci_set_drvdata(pdev, cdev->net);
+
+	if (!pm_runtime_enabled(cdev->dev))
+		pm_runtime_enable(cdev->dev);
+	ret = pm_runtime_get_sync(cdev->dev);
+	if (ret < 0) {
+		netdev_err(cdev->net, "%s: pm_runtime_get failed(%d)\n",
+					__func__, ret);
+		goto err_pmdisable;
+	}
+	ret = phytium_can_register(cdev);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err_pmdisable:
+	pm_runtime_disable(&pdev->dev);
+err:
+	return ret;
+}
+
+static void phytium_can_pci_remove(struct pci_dev *pdev)
+{
+	struct net_device *dev = pci_get_drvdata(pdev);
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+
+	pm_runtime_disable(cdev->dev);
+
+	phytium_can_unregister(cdev);
+	phytium_can_free_dev(cdev->net);
+}
+
+static __maybe_unused int phytium_can_pci_suspend(struct device *dev)
+{
+	return phytium_can_suspend(dev);
+}
+
+static __maybe_unused int phytium_can_pci_resume(struct device *dev)
+{
+	return phytium_can_resume(dev);
+}
+
+static SIMPLE_DEV_PM_OPS(phytium_can_pci_pm_ops,
+			 phytium_can_pci_suspend, phytium_can_pci_resume);
+
+static const struct pci_device_id phytium_can_pci_id_table[] = {
+	{ PCI_VDEVICE(PHYTIUM, 0xdc2d), (kernel_ulong_t)&phytium_can_pci_data, },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(pci, phytium_can_pci_id_table);
+
+static struct pci_driver phytium_can_pci_driver = {
+	.name = KBUILD_MODNAME,
+	.probe = phytium_can_pci_probe,
+	.remove = phytium_can_pci_remove,
+	.id_table = phytium_can_pci_id_table,
+	.driver = {
+		.pm = &phytium_can_pci_pm_ops,
+	},
+};
+
+module_pci_driver(phytium_can_pci_driver);
+
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium CAN driver for PCI-based controllers");
diff --git a/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can_platform.c b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can_platform.c
new file mode 100644
index 00000000000000..ce479af1116242
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/can/phytium/phytium_can_platform.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Platform CAN bus driver for Phytium CAN controller
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/acpi.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+#include "phytium_can.h"
+
+#define cdev2priv(dev) container_of(dev, struct phytium_can_plat, cdev)
+
+struct phytium_can_plat {
+	struct phytium_can_dev cdev;
+	struct phytium_can_devtype *devtype;
+
+	int irq;
+	void __iomem *reg_base;
+};
+
+static const struct can_bittiming_const phytium_bittiming_const_512 = {
+	.name = "phytium_can",
+	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
+	.tseg1_max = 16,
+	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
+	.tseg2_max = 8,
+	.sjw_max = 4,		/* Synchronisation jump width */
+	.brp_min = 1,		/* Bit-rate prescaler */
+	.brp_max = 512,
+	.brp_inc = 2,
+};
+
+static const struct can_bittiming_const phytium_bittiming_const_8192 = {
+	.name = "phytium_can",
+	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
+	.tseg1_max = 16,
+	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
+	.tseg2_max = 8,
+	.sjw_max = 4,		/* Synchronisation jump width */
+	.brp_min = 1,		/* Bit-rate prescaler */
+	.brp_max = 8192,
+	.brp_inc = 2,
+};
+
+static const struct phytium_can_devtype phytium_can_data = {
+	.cantype = PHYTIUM_CAN,
+	.bittiming_const = &phytium_bittiming_const_512,
+};
+
+static const struct phytium_can_devtype phytium_canfd_data = {
+	.cantype = PHYTIUM_CANFD,
+	.bittiming_const = &phytium_bittiming_const_8192,
+};
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_can_acpi_ids[] = {
+	{ "PHYT000A", 0 },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_can_acpi_ids);
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id phytium_can_of_ids[] = {
+	{ .compatible = "phytium,can", .data = &phytium_can_data },
+	{ .compatible = "phytium,canfd", .data = &phytium_canfd_data },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, phytium_can_of_ids);
+#endif
+
+
+static int phytium_can_plat_probe(struct platform_device *pdev)
+{
+	struct phytium_can_dev *cdev;
+	struct phytium_can_plat *priv;
+	struct resource *res;
+	const struct of_device_id *of_id;
+	const struct phytium_can_devtype *devtype = &phytium_can_data;
+	u32 tx_fifo_depth;
+	int ret;
+	const char *mode;
+
+	ret = fwnode_property_read_u32(dev_fwnode(&pdev->dev), "tx-fifo-depth", &tx_fifo_depth);
+	if (ret)
+		tx_fifo_depth = 64;
+
+	cdev = phytium_can_allocate_dev(&pdev->dev, sizeof(struct phytium_can_plat),
+					tx_fifo_depth);
+	if (!cdev)
+		return -ENOMEM;
+
+	priv = cdev2priv(cdev);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	priv->irq = platform_get_irq(pdev, 0);
+	if (IS_ERR(priv->reg_base) || cdev->net->irq < 0) {
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	if (pdev->dev.of_node) {
+		cdev->clk = devm_clk_get(&pdev->dev, "can_clk");
+		if (IS_ERR(cdev->clk)) {
+			dev_err(&pdev->dev, "no clock found\n");
+			ret = -ENODEV;
+			goto fail;
+		}
+		cdev->can.clock.freq = clk_get_rate(cdev->clk);
+
+		of_id = of_match_device(phytium_can_of_ids, &pdev->dev);
+		if (of_id && of_id->data)
+			devtype = of_id->data;
+	} else if (has_acpi_companion(&pdev->dev)) {
+		ret = fwnode_property_read_u32(dev_fwnode(&pdev->dev),
+					       "clock-frequency",
+					       &cdev->can.clock.freq);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to get clock frequency.\n");
+			goto fail;
+		}
+		ret = fwnode_property_read_string(dev_fwnode(&pdev->dev), "mode-select", &mode);
+		if (ret < 0) {
+			dev_info(&pdev->dev, "get mode-select ret: %d\n", ret);
+		}
+		else {
+			if (strncmp("canfd", mode, strlen("canfd")) == 0) {
+				dev_info(&pdev->dev, "use mode-select: canfd\n");
+				devtype = &phytium_canfd_data;
+			}
+		}
+	}
+
+	cdev->tx_fifo_depth = tx_fifo_depth;
+
+	if (devtype->cantype == PHYTIUM_CANFD)
+		cdev->fdmode = 1;
+	else
+		cdev->fdmode = 0;
+
+	if (fwnode_property_present(dev_fwnode(&pdev->dev), "extend_brp"))
+		cdev->bit_timing = &phytium_bittiming_const_8192;
+	else
+		cdev->bit_timing = devtype->bittiming_const;
+	cdev->can.bittiming_const = devtype->bittiming_const;
+	cdev->base = priv->reg_base;
+	cdev->net->irq = priv->irq;
+
+	platform_set_drvdata(pdev, cdev->net);
+
+	pm_runtime_enable(cdev->dev);
+	ret = phytium_can_register(cdev);
+	if (ret)
+		goto out_runtime_disable;
+
+	return ret;
+
+out_runtime_disable:
+	pm_runtime_disable(cdev->dev);
+fail:
+	phytium_can_free_dev(cdev->net);
+	return ret;
+}
+
+static __maybe_unused int phytium_can_plat_suspend(struct device *dev)
+{
+	return phytium_can_suspend(dev);
+}
+
+static __maybe_unused int phytium_can_plat_resume(struct device *dev)
+{
+	return phytium_can_resume(dev);
+}
+
+static int phytium_can_plat_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	struct phytium_can_dev *cdev = netdev_priv(dev);
+
+	phytium_can_unregister(cdev);
+
+	phytium_can_free_dev(cdev->net);
+
+	return 0;
+}
+
+static int __maybe_unused phytium_can_runtime_suspend(struct device *dev)
+{
+	struct net_device *ndev = dev_get_drvdata(dev);
+	struct phytium_can_dev *cdev = netdev_priv(ndev);
+
+	clk_disable_unprepare(cdev->clk);
+
+	return 0;
+}
+
+static int __maybe_unused phytium_can_runtime_resume(struct device *dev)
+{
+	struct net_device *ndev = dev_get_drvdata(dev);
+	struct phytium_can_dev *cdev = netdev_priv(ndev);
+
+	return clk_prepare_enable(cdev->clk);
+}
+
+static const struct dev_pm_ops phytium_can_plat_pm_ops = {
+	SET_RUNTIME_PM_OPS(phytium_can_runtime_suspend,
+			   phytium_can_runtime_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_can_suspend, phytium_can_resume)
+};
+
+static struct platform_driver phytium_can_plat_driver = {
+	.driver = {
+		.name = KBUILD_MODNAME,
+		.of_match_table = of_match_ptr(phytium_can_of_ids),
+		.acpi_match_table = ACPI_PTR(phytium_can_acpi_ids),
+		.pm = &phytium_can_plat_pm_ops,
+	},
+	.probe = phytium_can_plat_probe,
+	.remove = phytium_can_plat_remove,
+};
+
+module_platform_driver(phytium_can_plat_driver);
+
+MODULE_AUTHOR("Cheng Quan <chengquan@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium CAN driver for IO Mapped controllers");
diff --git a/target/linux/phytium/files-5.10/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c b/target/linux/phytium/files-5.10/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c
new file mode 100755
index 00000000000000..0dbf6eef7df5af
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/ethernet/stmicro/stmmac/dwmac-phytium.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SWMAC specific glue layer
+ *
+ * Copyright (c) 2022-2023, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/acpi.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "stmmac.h"
+#include "stmmac_platform.h"
+
+static int phytium_get_mac_mode(struct fwnode_handle *fwnode)
+{
+	const char *pm;
+	int err, i;
+
+	err = fwnode_property_read_string(fwnode, "mac-mode", &pm);
+	if (err < 0)
+		return err;
+
+	for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) {
+		if (!strcasecmp(pm, phy_modes(i)))
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+static int phytium_dwmac_acpi_phy(struct plat_stmmacenet_data *plat,
+		struct fwnode_handle *np, struct device *dev)
+{
+	plat->mdio_bus_data = devm_kzalloc(dev,
+			sizeof(struct stmmac_mdio_bus_data),
+			GFP_KERNEL);
+
+	if (!plat->mdio_bus_data)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int phytium_dwmac_probe(struct platform_device *pdev)
+{
+	struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
+	struct plat_stmmacenet_data *plat;
+	struct stmmac_resources stmmac_res;
+	struct device_node *np = pdev->dev.of_node;
+	u64 clk_freq;
+	char clk_name[20];
+	int ret;
+
+	plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
+	if (!plat)
+		return -ENOMEM;
+
+	plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
+	if (!plat->dma_cfg)
+		return -ENOMEM;
+
+	plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
+	if (!plat->axi)
+		return -ENOMEM;
+
+	plat->phy_interface = device_get_phy_mode(&pdev->dev);
+	if (plat->phy_interface < 0)
+		return plat->phy_interface;
+
+	plat->interface = phytium_get_mac_mode(fwnode);
+	if (plat->interface < 0)
+		plat->interface = plat->phy_interface;
+
+	/* Configure PHY if using device-tree */
+	if (pdev->dev.of_node) {
+		plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
+		plat->phylink_node = np;
+	}
+
+	if (pdev->dev.of_node) {
+		plat->bus_id = of_alias_get_id(np, "ethernet");
+		if (plat->bus_id < 0)
+			plat->bus_id = 0;
+	} else if (fwnode_property_read_u32(fwnode, "bus_id", &plat->bus_id)) {
+		plat->bus_id = 2;
+	}
+
+	plat->phy_addr = -1;
+	plat->clk_csr = -1;
+	plat->has_gmac = 1;
+	plat->enh_desc = 1;
+	plat->bugged_jumbo = 1;
+	plat->pmt = 1;
+	plat->force_sf_dma_mode = 1;
+
+	if (fwnode_property_read_u32(fwnode, "max-speed", &plat->max_speed))
+		plat->max_speed = -1;
+
+	if (fwnode_property_read_u32(fwnode, "max-frame-size", &plat->maxmtu))
+		plat->maxmtu = JUMBO_LEN;
+
+	if (fwnode_property_read_u32(fwnode, "snps,multicast-filter-bins",
+				     &plat->multicast_filter_bins))
+		plat->multicast_filter_bins = HASH_TABLE_SIZE;
+
+	if (fwnode_property_read_u32(fwnode, "snps,perfect-filter-entries",
+				     &plat->unicast_filter_entries))
+		plat->unicast_filter_entries = 1;
+
+	if (fwnode_property_read_u32(fwnode, "tx-fifo-depth", &plat->tx_fifo_size))
+		plat->tx_fifo_size = 0x1000;
+
+	if (fwnode_property_read_u32(fwnode, "rx-fifo-depth", &plat->rx_fifo_size))
+		plat->rx_fifo_size = 0x1000;
+
+	if (phytium_dwmac_acpi_phy(plat, fwnode, &pdev->dev))
+		return -ENODEV;
+
+	plat->rx_queues_to_use = 1;
+	plat->tx_queues_to_use = 1;
+	plat->rx_queues_cfg[0].mode_to_use = MTL_QUEUE_DCB;
+	plat->tx_queues_cfg[0].mode_to_use = MTL_QUEUE_DCB;
+
+	if (fwnode_property_read_u64(fwnode, "clock-frequency", &clk_freq))
+		clk_freq = 125000000;
+
+	/* Set system clock */
+	snprintf(clk_name, sizeof(clk_name), "%s-%d", "stmmaceth", plat->bus_id);
+
+	plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, clk_name, NULL, 0, clk_freq);
+	if (IS_ERR(plat->stmmac_clk)) {
+		dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
+		plat->stmmac_clk = NULL;
+	}
+
+	ret = clk_prepare_enable(plat->stmmac_clk);
+	if (ret) {
+		clk_unregister_fixed_rate(plat->stmmac_clk);
+		return ret;
+	}
+
+	plat->clk_ptp_rate = clk_get_rate(plat->stmmac_clk);
+	plat->clk_ptp_ref = NULL;
+
+	if (fwnode_property_read_u32(fwnode, "snps,pbl", &plat->dma_cfg->pbl))
+		plat->dma_cfg->pbl = 16;
+
+	fwnode_property_read_u32(fwnode, "snps,txpbl", &plat->dma_cfg->txpbl);
+	fwnode_property_read_u32(fwnode, "snps,rxpbl", &plat->dma_cfg->rxpbl);
+
+	plat->dma_cfg->pblx8 = !fwnode_property_read_bool(fwnode, "snps,no-pbl-x8");
+	plat->dma_cfg->aal = fwnode_property_read_bool(fwnode, "snps,aal");
+	plat->dma_cfg->fixed_burst = fwnode_property_read_bool(fwnode, "snps,fixed-burst");
+	plat->dma_cfg->mixed_burst = fwnode_property_read_bool(fwnode, "snps,mixed-burst");
+
+	plat->axi->axi_lpi_en = false;
+	plat->axi->axi_xit_frm = false;
+	plat->axi->axi_wr_osr_lmt = 7;
+	plat->axi->axi_rd_osr_lmt = 7;
+	plat->axi->axi_blen[0] = 16;
+
+	memset(&stmmac_res, 0, sizeof(stmmac_res));
+	stmmac_res.addr = devm_platform_ioremap_resource(pdev, 0);
+	stmmac_res.irq = platform_get_irq(pdev, 0);
+	if (stmmac_res.irq < 0) {
+		dev_err(&pdev->dev, "IRQ not found.\n");
+		return -ENXIO;
+	}
+	stmmac_res.wol_irq = stmmac_res.irq;
+	stmmac_res.lpi_irq = -1;
+
+	return  stmmac_dvr_probe(&pdev->dev, plat, &stmmac_res);
+}
+
+int phytium_dwmac_remove(struct platform_device *pdev)
+{
+	int ret;
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct stmmac_priv *priv = netdev_priv(ndev);
+	struct plat_stmmacenet_data *plat = priv->plat;
+
+	ret = stmmac_pltfr_remove(pdev);
+	clk_unregister_fixed_rate(plat->stmmac_clk);
+	return ret;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id phytium_dwmac_of_match[] = {
+	{ .compatible = "phytium,gmac" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_dwmac_of_match);
+#endif
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_dwmac_acpi_ids[] = {
+	{ .id = "PHYT0004" },
+	{}
+};
+MODULE_DEVICE_TABLE(acpi, phytium_dwmac_acpi_ids);
+#endif
+
+static struct platform_driver phytium_dwmac_driver = {
+	.probe = phytium_dwmac_probe,
+	.remove = phytium_dwmac_remove,
+	.driver = {
+		.name		= "phytium-dwmac",
+		.pm		= &stmmac_pltfr_pm_ops,
+		.of_match_table	= of_match_ptr(phytium_dwmac_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_dwmac_acpi_ids),
+	},
+};
+module_platform_driver(phytium_dwmac_driver);
+
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium DWMAC specific glue layer");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/net/phy/motorcomm.c b/target/linux/phytium/files-5.10/drivers/net/phy/motorcomm.c
new file mode 100755
index 00000000000000..31a64698beba8b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/net/phy/motorcomm.c
@@ -0,0 +1,2387 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * drivers/net/phy/motorcomm.c
+ *
+ * Driver for Motorcomm PHYs
+ *
+ * Author: yinghong.zhang<yinghong.zhang@motor-comm.com>
+ *
+ * Copyright (c) 2019 Motorcomm, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Support : Motorcomm Phys:
+ *        Giga phys: yt8511, yt8521, yt8531, yt8614, yt8618
+ *        100/10 Phys : yt8512, yt8512b, yt8510
+ *        Automotive 100Mb Phys : yt8010
+ *        Automotive 100/10 hyper range Phys: yt8510
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#ifndef LINUX_VERSION_CODE
+#include <linux/version.h>
+#else
+#define KERNEL_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c))
+#endif
+
+/* for wol feature, 20210604 */
+#include <linux/netdevice.h>
+
+#define YT_LINUX_MAJOR         	2
+#define YT_LINUX_MINOR  		2
+#define YT_LINUX_SUBVERSION 	8661
+#define YT_LINUX_VERSIONID  	"2.2.8661"
+
+/********************************************
+ **** configuration section begin ***********/
+
+/* if system depends on ethernet packet to restore from sleep,
+ * please define this macro to 1 otherwise, define it to 0.
+ */
+#define SYS_WAKEUP_BASED_ON_ETH_PKT     0
+
+/* to enable system WOL feature of phy, please define this macro to 1
+ * otherwise, define it to 0.
+ */
+#define YTPHY_WOL_FEATURE_ENABLE        0
+
+/* some GMAC need clock input from PHY, for eg., 125M,
+ * please enable this macro
+ * by degault, it is set to 0
+ * NOTE: this macro will need macro SYS_WAKEUP_BASED_ON_ETH_PKT to set to 1
+ */
+#define GMAC_CLOCK_INPUT_NEEDED         0
+
+/* the max number of yt8521 chip on pcb board
+ * the most case is only 1 chip per board, but
+ * by default, we support up to 8.
+ */
+#define YTPHY_BOARD_MAX_NUM_OF_CHIP_8521    8
+#define YTPHY_BOARD_MAX_NUM_OF_CHIP_8614    4
+
+/* for YT8531 package A xtal init config */
+#define YTPHY8531A_XTAL_INIT                (0)
+
+/**** configuration section end ***********
+ ******************************************/
+
+/* no need to change below */
+#define MOTORCOMM_PHY_ID_MASK           0x00000fff
+#define MOTORCOMM_PHY_ID_8531_MASK      0xffffffff
+#define MOTORCOMM_MPHY_ID_MASK          0x0000ffff
+#define MOTORCOMM_MPHY_ID_MASK_8614     0xffffffff
+#define MOTORCOMM_PHY_ID_MASK_8821      0xffffffff
+
+#define PHY_ID_YT8010                   0x00000309
+#define PHY_ID_YT8010AS                 0x4f51eb19
+#define PHY_ID_YT8510                   0x00000109
+#define PHY_ID_YT8511                   0x0000010a
+#define PHY_ID_YT8512                   0x00000118
+#define PHY_ID_YT8512B                  0x00000128
+#define PHY_ID_YT8521                   0x0000011a
+#define PHY_ID_YT8531S                  0x4f51e91a
+#define PHY_ID_YT8531                   0x4f51e91b
+#define PHY_ID_YT8614                   0x4F51E899
+#define PHY_ID_YT8618                   0x0000e889
+#define PHY_ID_YT8821                   0x4f51ea10
+
+#define REG_PHY_SPEC_STATUS             0x11
+#define REG_DEBUG_ADDR_OFFSET           0x1e
+#define REG_DEBUG_DATA                  0x1f
+
+#define YT8512_EXTREG_LED0              0x40c0
+#define YT8512_EXTREG_LED1              0x40c3
+
+#define YT8512_EXTREG_SLEEP_CONTROL1    0x2027
+
+#define YT_SOFTWARE_RESET               0x8000
+
+#define YT8512_LED0_ACT_BLK_IND         0x1000
+#define YT8512_LED0_DIS_LED_AN_TRY      0x0001
+#define YT8512_LED0_BT_BLK_EN           0x0002
+#define YT8512_LED0_HT_BLK_EN           0x0004
+#define YT8512_LED0_COL_BLK_EN          0x0008
+#define YT8512_LED0_BT_ON_EN            0x0010
+#define YT8512_LED1_BT_ON_EN            0x0010
+#define YT8512_LED1_TXACT_BLK_EN        0x0100
+#define YT8512_LED1_RXACT_BLK_EN        0x0200
+#define YT8512_SPEED_MODE               0xc000
+#define YT8512_DUPLEX                   0x2000
+
+#define YT8512_SPEED_MODE_BIT           14
+#define YT8512_DUPLEX_BIT               13
+#define YT8512_EN_SLEEP_SW_BIT          15
+
+#define YT8521_EXTREG_SLEEP_CONTROL1    0x27
+#define YT8521_EN_SLEEP_SW_BIT          15
+
+#define YT8521_SPEED_MODE               0xc000
+#define YT8521_DUPLEX                   0x2000
+#define YT8521_SPEED_MODE_BIT           14
+#define YT8521_DUPLEX_BIT               13
+#define YT8521_LINK_STATUS_BIT          10
+
+/* based on yt8521 wol feature config register */
+#define YTPHY_UTP_INTR_REG              0x12
+/* WOL Feature Event Interrupt Enable */
+#define YTPHY_WOL_FEATURE_INTR          BIT(6)
+
+/* Magic Packet MAC address registers */
+#define YTPHY_WOL_FEATURE_MACADDR2_4_MAGIC_PACKET    0xa007
+#define YTPHY_WOL_FEATURE_MACADDR1_4_MAGIC_PACKET    0xa008
+#define YTPHY_WOL_FEATURE_MACADDR0_4_MAGIC_PACKET    0xa009
+
+#define YTPHY_WOL_FEATURE_REG_CFG               0xa00a
+#define YTPHY_WOL_FEATURE_TYPE_CFG              BIT(0)    /* WOL TYPE Config */
+#define YTPHY_WOL_FEATURE_ENABLE_CFG            BIT(3)    /* WOL Enable Config */
+#define YTPHY_WOL_FEATURE_INTR_SEL_CFG          BIT(6)    /* WOL Event Interrupt Enable Config */
+#define YTPHY_WOL_FEATURE_WIDTH1_CFG            BIT(1)    /* WOL Pulse Width Config */
+#define YTPHY_WOL_FEATURE_WIDTH2_CFG            BIT(2)    /* WOL Pulse Width Config */
+
+#define YTPHY_REG_SPACE_UTP             0
+#define YTPHY_REG_SPACE_FIBER           2
+
+enum ytphy_wol_feature_trigger_type_e {
+	YTPHY_WOL_FEATURE_PULSE_TRIGGER,
+	YTPHY_WOL_FEATURE_LEVEL_TRIGGER,
+	YTPHY_WOL_FEATURE_TRIGGER_TYPE_MAX
+};
+
+enum ytphy_wol_feature_pulse_width_e {
+	YTPHY_WOL_FEATURE_672MS_PULSE_WIDTH,
+	YTPHY_WOL_FEATURE_336MS_PULSE_WIDTH,
+	YTPHY_WOL_FEATURE_168MS_PULSE_WIDTH,
+	YTPHY_WOL_FEATURE_84MS_PULSE_WIDTH,
+	YTPHY_WOL_FEATURE_PULSE_WIDTH_MAX
+};
+
+struct ytphy_wol_feature_cfg {
+	bool enable;
+	int type;
+	int width;
+};
+
+#if (YTPHY_WOL_FEATURE_ENABLE)
+#undef SYS_WAKEUP_BASED_ON_ETH_PKT
+#define SYS_WAKEUP_BASED_ON_ETH_PKT     1
+#endif
+
+/* YT8521 polling mode */
+#define YT8521_PHY_MODE_FIBER           1 //fiber mode only
+#define YT8521_PHY_MODE_UTP             2 //utp mode only
+#define YT8521_PHY_MODE_POLL            3 //fiber and utp, poll mode
+
+/* below are for bitmap */
+#define YT_PHY_MODE_FIBER               1 //fiber/sgmii mode only
+#define YT_PHY_MODE_UTP                 2 //utp mode only
+#define YT_PHY_MODE_QSGMII              4 //qsgmii mode only
+#define YT_PHY_MODE_POLL                (YT_PHY_MODE_FIBER | YT_PHY_MODE_UTP | YT_PHY_MODE_QSGMII)  //qsgmii, fiber/sgmii and utp, poll mode
+
+/* support automatically check polling mode for yt8521
+ * for Fiber only system, please define YT8521_PHY_MODE_CURR 1
+ * for UTP only system, please define YT8521_PHY_MODE_CURR 2
+ * for combo system, please define YT8521_PHY_MODE_CURR 3
+ */
+#define YTPHY_861X_ABC_VER              0
+#if (YTPHY_861X_ABC_VER)
+static int yt8614_get_port_from_phydev(struct phy_device *phydev);
+#endif
+static int yt8521_hw_strap_polling(struct phy_device *phydev);
+static int yt8614_hw_strap_polling(struct phy_device *phydev);
+#define YT8521_PHY_MODE_CURR    yt8521_hw_strap_polling(phydev)
+#define YT8614_PHY_MODE_CURR    yt8614_hw_strap_polling(phydev)
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+static int ytphy_config_init(struct phy_device *phydev)
+{
+	int val;
+
+	val = phy_read(phydev, 3);
+
+	return 0;
+}
+#endif
+
+
+#if (KERNEL_VERSION(5, 5, 0) > LINUX_VERSION_CODE)
+static inline void phy_lock_mdio_bus(struct phy_device *phydev)
+{
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->bus->mdio_lock);
+#else
+	mutex_lock(&phydev->mdio.bus->mdio_lock);
+#endif
+}
+
+static inline void phy_unlock_mdio_bus(struct phy_device *phydev)
+{
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->bus->mdio_lock);
+#else
+	mutex_unlock(&phydev->mdio.bus->mdio_lock);
+#endif
+}
+#endif
+
+#if (KERNEL_VERSION(4, 16, 0) > LINUX_VERSION_CODE)
+static inline int __phy_read(struct phy_device *phydev, u32 regnum)
+{
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	struct mii_bus *bus = phydev->bus;
+	int addr = phydev->addr;
+	return bus->read(bus, phydev->addr, regnum);
+#else
+	struct mii_bus *bus = phydev->mdio.bus;
+	int addr = phydev->mdio.addr;
+#endif
+	return bus->read(bus, addr, regnum);
+}
+
+static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
+{
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	struct mii_bus *bus = phydev->bus;
+	int addr = phydev->addr;
+#else
+	struct mii_bus *bus = phydev->mdio.bus;
+	int addr = phydev->mdio.addr;
+#endif
+	return bus->write(bus, addr, regnum, val);
+}
+#endif
+
+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
+{
+	int ret;
+
+	phy_lock_mdio_bus(phydev);
+	ret = __phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		goto err_handle;
+
+	ret = __phy_read(phydev, REG_DEBUG_DATA);
+	if (ret < 0)
+		goto err_handle;
+
+err_handle:
+	phy_unlock_mdio_bus(phydev);
+	return ret;
+}
+
+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
+{
+	int ret;
+
+	phy_lock_mdio_bus(phydev);
+	ret = __phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		goto err_handle;
+
+	ret = __phy_write(phydev, REG_DEBUG_DATA, val);
+	if (ret < 0)
+		goto err_handle;
+
+err_handle:
+	phy_unlock_mdio_bus(phydev);
+	return ret;
+}
+
+static int ytphy_soft_reset(struct phy_device *phydev)
+{
+	int ret = 0, val = 0;
+
+	val = phy_read(phydev, MII_BMCR);
+	if (val < 0)
+		return val;
+
+	ret = phy_write(phydev, MII_BMCR, val | BMCR_RESET);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+
+#if (YTPHY8531A_XTAL_INIT)
+static int yt8531a_xtal_init(struct phy_device *phydev)
+{
+	int ret = 0;
+	int val = 0;
+	bool state = false;
+
+	msleep(50);
+
+	do {
+		ret = ytphy_write_ext(phydev, 0xa012, 0x88);
+		if (ret < 0)
+			return ret;
+
+		msleep(100);
+
+		val = ytphy_read_ext(phydev, 0xa012);
+		if (val < 0)
+			return val;
+
+		usleep_range(10000, 20000);
+	} while (val != 0x88);
+
+	ret = ytphy_write_ext(phydev, 0xa012, 0xc8);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+#endif
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+int yt8010_soft_reset(struct phy_device *phydev)
+{
+	ytphy_soft_reset(phydev);
+
+	return 0;
+}
+
+int yt8010AS_soft_reset(struct phy_device *phydev)
+{
+	int ret = 0;
+
+	/* sgmii */
+	ytphy_write_ext(phydev, 0xe, 1);
+	ret = ytphy_soft_reset(phydev);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xe, 0);
+		return ret;
+	}
+
+	/* utp */
+	ytphy_write_ext(phydev, 0xe, 0);
+	ret = ytphy_soft_reset(phydev);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+#endif
+
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+int yt8010_aneg_done(struct phy_device *phydev)
+{
+	int val = 0;
+
+	val = phy_read(phydev, 0x1);
+	val = phy_read(phydev, 0x1);
+
+	return (val < 0) ? val : (val & BMSR_LSTATUS);
+}
+#endif
+
+static int yt8010_config_aneg(struct phy_device *phydev)
+{
+	phydev->speed = SPEED_100;
+	return 0;
+}
+
+static int yt8010_read_status(struct phy_device *phydev)
+{
+	int ret = 0;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	/* for 8010, no definition mii reg 0x04, 0x11, here force 100/full */
+	phydev->speed = SPEED_100;
+	phydev->duplex = DUPLEX_FULL;
+
+	return 0;
+}
+
+static int yt8010AS_config_init(struct phy_device *phydev)
+{
+	phydev->autoneg = AUTONEG_DISABLE;
+
+	return 0;
+}
+
+static int yt8512_led_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	int mask;
+
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
+	if (val < 0)
+		return val;
+
+	val |= YT8512_LED0_ACT_BLK_IND;
+
+	mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
+	YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
+	YT8512_LED0_BT_ON_EN;
+	val &= ~mask;
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
+	if (ret < 0)
+		return ret;
+
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
+	if (val < 0)
+		return val;
+
+	val |= YT8512_LED1_BT_ON_EN;
+
+	mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
+	val &= ~mask;
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED1, val);
+
+	return ret;
+}
+
+static int yt8512_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+	if (ret < 0)
+		return ret;
+
+	ret = yt8512_led_init(phydev);
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
+
+	ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int yt8512_read_status(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	int speed, speed_mode, duplex;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+	if (val < 0)
+		return val;
+
+	duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
+	speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
+	switch (speed_mode) {
+	case 0:
+		speed = SPEED_10;
+		break;
+	case 1:
+		speed = SPEED_100;
+		break;
+	case 2:
+	case 3:
+	default:
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+		speed = -1;
+#else
+		speed = SPEED_UNKNOWN;
+#endif
+		break;
+	}
+
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+int yt8521_soft_reset(struct phy_device *phydev)
+{
+	int ret, val;
+
+	if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_UTP) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		ytphy_soft_reset(phydev);
+	}
+
+	if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_FIBER) {
+		ytphy_write_ext(phydev, 0xa000, 2);
+		ytphy_soft_reset(phydev);
+
+		ytphy_write_ext(phydev, 0xa000, 0);
+	}
+
+	if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_POLL) {
+		val = ytphy_read_ext(phydev, 0xa001);
+		ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
+
+		ytphy_write_ext(phydev, 0xa000, 0);
+		ret = ytphy_soft_reset(phydev);
+	}
+
+	return 0;
+}
+#endif
+
+#if GMAC_CLOCK_INPUT_NEEDED
+static int ytphy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum)
+{
+	int ret;
+	int val;
+
+	ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		return ret;
+
+	val = bus->read(bus, phy_id, REG_DEBUG_DATA);
+
+	return val;
+}
+
+static int ytphy_mii_wr_ext(struct mii_bus *bus
+				int phy_id,
+				u32 regnum,
+				u16 val)
+{
+	int ret;
+
+	ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		return ret;
+
+	ret = bus->write(bus, phy_id, REG_DEBUG_DATA, val);
+
+	return ret;
+}
+
+int yt8511_config_dis_txdelay(struct mii_bus *bus, int phy_id)
+{
+	int ret;
+	int val;
+
+	/* disable auto sleep */
+	val = ytphy_mii_rd_ext(bus, phy_id, 0x27);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(15));
+
+	ret = ytphy_mii_wr_ext(bus, phy_id, 0x27, val);
+	if (ret < 0)
+		return ret;
+
+	/* enable RXC clock when no wire plug */
+	val = ytphy_mii_rd_ext(bus, phy_id, 0xc);
+	if (val < 0)
+		return val;
+
+	/* ext reg 0xc b[7:4]
+	 * Tx Delay time = 150ps * N - 250ps
+	 */
+	val &= ~(0xf << 4);
+	ret = ytphy_mii_wr_ext(bus, phy_id, 0xc, val);
+
+	return ret;
+}
+
+int yt8511_config_out_125m(struct mii_bus *bus, int phy_id)
+{
+	int ret;
+	int val;
+
+	/* disable auto sleep */
+	val = ytphy_mii_rd_ext(bus, phy_id, 0x27);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(15));
+
+	ret = ytphy_mii_wr_ext(bus, phy_id, 0x27, val);
+	if (ret < 0)
+		return ret;
+
+	/* enable RXC clock when no wire plug */
+	val = ytphy_mii_rd_ext(bus, phy_id, 0xc);
+	if (val < 0)
+		return val;
+
+	/* ext reg 0xc.b[2:1]
+	 * 00-----25M from pll;
+	 * 01---- 25M from xtl;(default)
+	 * 10-----62.5M from pll;
+	 * 11----125M from pll(here set to this value)
+	 */
+	val |= (3 << 1);
+	ret = ytphy_mii_wr_ext(bus, phy_id, 0xc, val);
+
+#ifdef YT_8511_INIT_TO_MASTER
+	/* for customer, please enable it based on demand.
+	 * configure to master
+	 */
+
+	/* master/slave config reg*/
+	val = bus->read(bus, phy_id, 0x9);
+	/* to be manual config and force to be master */
+	val |= (0x3<<11);
+	/* take effect until phy soft reset */
+	ret = bus->write(bus, phy_id, 0x9, val);
+	if (ret < 0)
+		return ret;
+#endif
+
+	return ret;
+}
+
+static int yt8511_config_init(struct phy_device *phydev)
+{
+	int ret;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d\n", __func__, phydev->addr);
+#else
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d\n", __func__, phydev->mdio.addr);
+#endif
+
+	return ret;
+}
+#endif /* GMAC_CLOCK_INPUT_NEEDED */
+
+#if (YTPHY_WOL_FEATURE_ENABLE)
+static int ytphy_switch_reg_space(struct phy_device *phydev, int space)
+{
+	int ret;
+
+	if (space == YTPHY_REG_SPACE_UTP)
+		ret = ytphy_write_ext(phydev, 0xa000, 0);
+	else
+		ret = ytphy_write_ext(phydev, 0xa000, 2);
+
+	return ret;
+}
+
+static int ytphy_wol_feature_enable_cfg(struct phy_device *phydev,
+			struct ytphy_wol_feature_cfg wol_cfg)
+{
+	int ret = 0;
+	int val = 0;
+
+	val = ytphy_read_ext(phydev, YTPHY_WOL_FEATURE_REG_CFG);
+	if (val < 0)
+		return val;
+
+	if (wol_cfg.enable) {
+		val |= YTPHY_WOL_FEATURE_ENABLE_CFG;
+
+	if (wol_cfg.type == YTPHY_WOL_FEATURE_LEVEL_TRIGGER) {
+		val &= ~YTPHY_WOL_FEATURE_TYPE_CFG;
+		val &= ~YTPHY_WOL_FEATURE_INTR_SEL_CFG;
+	} else if (wol_cfg.type == YTPHY_WOL_FEATURE_PULSE_TRIGGER) {
+		val |= YTPHY_WOL_FEATURE_TYPE_CFG;
+		val |= YTPHY_WOL_FEATURE_INTR_SEL_CFG;
+
+		if (wol_cfg.width == YTPHY_WOL_FEATURE_84MS_PULSE_WIDTH) {
+			val &= ~YTPHY_WOL_FEATURE_WIDTH1_CFG;
+			val &= ~YTPHY_WOL_FEATURE_WIDTH2_CFG;
+		} else if (wol_cfg.width == YTPHY_WOL_FEATURE_168MS_PULSE_WIDTH) {
+			val |= YTPHY_WOL_FEATURE_WIDTH1_CFG;
+			val &= ~YTPHY_WOL_FEATURE_WIDTH2_CFG;
+		} else if (wol_cfg.width == YTPHY_WOL_FEATURE_336MS_PULSE_WIDTH) {
+			val &= ~YTPHY_WOL_FEATURE_WIDTH1_CFG;
+			val |= YTPHY_WOL_FEATURE_WIDTH2_CFG;
+		} else if (wol_cfg.width == YTPHY_WOL_FEATURE_672MS_PULSE_WIDTH) {
+			val |= YTPHY_WOL_FEATURE_WIDTH1_CFG;
+			val |= YTPHY_WOL_FEATURE_WIDTH2_CFG;
+		}
+	}
+	} else {
+		val &= ~YTPHY_WOL_FEATURE_ENABLE_CFG;
+		val &= ~YTPHY_WOL_FEATURE_INTR_SEL_CFG;
+	}
+
+	ret = ytphy_write_ext(phydev, YTPHY_WOL_FEATURE_REG_CFG, val);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static void ytphy_wol_feature_get(struct phy_device *phydev,
+				struct ethtool_wolinfo *wol)
+{
+	int val = 0;
+
+	wol->supported = WAKE_MAGIC;
+	wol->wolopts = 0;
+
+	val = ytphy_read_ext(phydev, YTPHY_WOL_FEATURE_REG_CFG);
+	if (val < 0)
+		return;
+
+	if (val & YTPHY_WOL_FEATURE_ENABLE_CFG)
+		wol->wolopts |= WAKE_MAGIC;
+
+	//return;
+}
+
+static int ytphy_wol_feature_set(struct phy_device *phydev,
+				struct ethtool_wolinfo *wol)
+{
+	int ret, curr_reg_space, val;
+	struct ytphy_wol_feature_cfg wol_cfg;
+	struct net_device *p_attached_dev = phydev->attached_dev;
+
+	memset(&wol_cfg, 0, sizeof(struct ytphy_wol_feature_cfg));
+	curr_reg_space = ytphy_read_ext(phydev, 0xa000);
+	if (curr_reg_space < 0)
+		return curr_reg_space;
+
+	/* Switch to phy UTP page */
+	ret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP);
+	if (ret < 0)
+		return ret;
+
+	if (wol->wolopts & WAKE_MAGIC) {
+		/* Enable the WOL feature interrupt */
+		val = phy_read(phydev, YTPHY_UTP_INTR_REG);
+		val |= YTPHY_WOL_FEATURE_INTR;
+		ret = phy_write(phydev, YTPHY_UTP_INTR_REG, val);
+		if (ret < 0)
+			return ret;
+
+		/* Set the WOL feature config */
+		wol_cfg.enable = true;
+		wol_cfg.type = YTPHY_WOL_FEATURE_PULSE_TRIGGER;
+		wol_cfg.width = YTPHY_WOL_FEATURE_672MS_PULSE_WIDTH;
+		ret = ytphy_wol_feature_enable_cfg(phydev, wol_cfg);
+		if (ret < 0)
+			return ret;
+
+		/* Store the device address for the magic packet */
+		ret = ytphy_write_ext(phydev, YTPHY_WOL_FEATURE_MACADDR2_4_MAGIC_PACKET,
+			((p_attached_dev->dev_addr[0] << 8) |
+			p_attached_dev->dev_addr[1]));
+		if (ret < 0)
+			return ret;
+		ret = ytphy_write_ext(phydev, YTPHY_WOL_FEATURE_MACADDR1_4_MAGIC_PACKET,
+			((p_attached_dev->dev_addr[2] << 8) |
+			p_attached_dev->dev_addr[3]));
+		if (ret < 0)
+			return ret;
+		ret = ytphy_write_ext(phydev, YTPHY_WOL_FEATURE_MACADDR0_4_MAGIC_PACKET,
+			((p_attached_dev->dev_addr[4] << 8) |
+			p_attached_dev->dev_addr[5]));
+		if (ret < 0)
+			return ret;
+	} else {
+		wol_cfg.enable = false;
+		wol_cfg.type = YTPHY_WOL_FEATURE_TRIGGER_TYPE_MAX;
+		wol_cfg.width = YTPHY_WOL_FEATURE_PULSE_WIDTH_MAX;
+		ret = ytphy_wol_feature_enable_cfg(phydev, wol_cfg);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* Recover to previous register space page */
+	ret = ytphy_switch_reg_space(phydev, curr_reg_space);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+#endif /*(YTPHY_WOL_FEATURE_ENABLE)*/
+
+static int yt8521_hw_strap_polling(struct phy_device *phydev)
+{
+	int val = 0;
+
+	val = ytphy_read_ext(phydev, 0xa001) & 0x7;
+	switch (val) {
+	case 1:
+	case 4:
+	case 5:
+		return YT8521_PHY_MODE_FIBER;
+	case 2:
+	case 6:
+	case 7:
+		return YT8521_PHY_MODE_POLL;
+	case 3:
+	case 0:
+	default:
+		return YT8521_PHY_MODE_UTP;
+	}
+}
+
+
+static int yt8521_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val, hw_strap_mode;
+
+#if (YTPHY_WOL_FEATURE_ENABLE)
+	struct ethtool_wolinfo wol;
+
+	/* set phy wol enable */
+	memset(&wol, 0x0, sizeof(struct ethtool_wolinfo));
+	wol.wolopts |= WAKE_MAGIC;
+	ytphy_wol_feature_set(phydev, &wol);
+#endif
+	if (phydev->force_mode) {
+		hw_strap_mode = ytphy_read_ext(phydev, 0xa001) & 0x7;
+		hw_strap_mode = hw_strap_mode & 0x7ff8;
+		hw_strap_mode = hw_strap_mode |0x140;
+		ytphy_write_ext(phydev, 0xa001, hw_strap_mode);
+	}
+
+	phydev->irq = PHY_POLL;
+	/* NOTE: this function should not be called more than one for each chip. */
+	hw_strap_mode = ytphy_read_ext(phydev, 0xa001) & 0x7;
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+	if (ret < 0)
+		return ret;
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+
+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+	/* enable RXC clock when no wire plug */
+	val = ytphy_read_ext(phydev, 0xc);
+	if (val < 0)
+		return val;
+	val &= ~(1 << 12);
+	ret = ytphy_write_ext(phydev, 0xc, val);
+	if (ret < 0)
+		return ret;
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, strap mode = %d, polling mode = %d\n",
+		__func__, phydev->addr, hw_strap_mode, yt8521_hw_strap_polling(phydev));
+#else
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, strap mode = %d, polling mode = %d\n",
+		__func__, phydev->mdio.addr, hw_strap_mode, yt8521_hw_strap_polling(phydev));
+#endif
+	return ret;
+}
+
+/* for fiber mode, there is no 10M speed mode and
+ * this function is for this purpose.
+ */
+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
+{
+	int speed_mode, duplex;
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	int speed = -1;
+#else
+	int speed = SPEED_UNKNOWN;
+#endif
+
+	if (is_utp)
+		duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;
+	else
+		duplex = 1;
+	speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
+	switch (speed_mode) {
+	case 0:
+		if (is_utp)
+			speed = SPEED_10;
+		break;
+	case 1:
+		speed = SPEED_100;
+		break;
+	case 2:
+		speed = SPEED_1000;
+		break;
+	case 3:
+		break;
+	default:
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+		speed = -1;
+#else
+		speed = SPEED_UNKNOWN;
+#endif
+		break;
+	}
+
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+/* for fiber mode, when speed is 100M, there is no definition for
+ * autonegotiation, and this function handles this case and return
+ * 1 per linux kernel's polling.
+ */
+int yt8521_aneg_done(struct phy_device *phydev)
+{
+	int link_fiber = 0, link_utp = 0;
+
+	/* reading Fiber */
+	ytphy_write_ext(phydev, 0xa000, 2);
+	link_fiber = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
+
+	/* reading UTP */
+	ytphy_write_ext(phydev, 0xa000, 0);
+	if (!link_fiber)
+		link_utp = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	netdev_info(phydev->attached_dev, "%s, phy addr: %d, link_fiber: %d, link_utp: %d\n",
+		__func__, phydev->addr, link_fiber, link_utp);
+#else
+	netdev_info(phydev->attached_dev, "%s, phy addr: %d, link_fiber: %d, link_utp: %d\n",
+		__func__, phydev->mdio.addr, link_fiber, link_utp);
+#endif
+	return !!(link_fiber | link_utp);
+}
+
+static int yt8521_read_status(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	int yt8521_fiber_latch_val;
+	int yt8521_fiber_curr_val;
+	int link;
+	int link_utp = 0, link_fiber = 0;
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
+		/* reading UTP */
+		ret = ytphy_write_ext(phydev, 0xa000, 0);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link) {
+			link_utp = 1;
+			yt8521_adjust_status(phydev, val, 1);
+		} else {
+			link_utp = 0;
+		}
+	} //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) {
+		/* reading Fiber */
+		ret = ytphy_write_ext(phydev, 0xa000, 2);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		//note: below debug information is used to check multiple PHy ports.
+
+		/* for fiber, from 1000m to 100m, there is not link down from 0x11,
+		 * and check reg 1 to identify such case this is important for Linux
+		 * kernel for that, missing linkdown event will cause problem.
+		 */
+		yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);
+		yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link && yt8521_fiber_latch_val != yt8521_fiber_curr_val) {
+			link = 0;
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				__func__, phydev->addr, yt8521_fiber_latch_val, yt8521_fiber_curr_val);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				__func__, phydev->mdio.addr, yt8521_fiber_latch_val, yt8521_fiber_curr_val);
+#endif
+		}
+
+		if (link) {
+			link_fiber = 1;
+			yt8521_adjust_status(phydev, val, 0);
+		} else {
+			link_fiber = 0;
+		}
+	} //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)
+
+	if (link_utp || link_fiber) {
+		if (phydev->link == 0)
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media: %s, mii reg 0x11 = 0x%x\n",
+				__func__, phydev->addr, (link_utp && link_fiber) ? "UNKNOWN MEDIA" : (link_utp ? "UTP" : "Fiber"), (unsigned int)val);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media: %s, mii reg 0x11 = 0x%x\n",
+				__func__, phydev->mdio.addr, (link_utp && link_fiber) ? "UNKNOWN MEDIA" : (link_utp ? "UTP" : "Fiber"), (unsigned int)val);
+#endif
+		phydev->link = 1;
+	} else {
+		if (phydev->link == 1)
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n", __func__, phydev->addr);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n", __func__, phydev->mdio.addr);
+#endif
+		phydev->link = 0;
+	}
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {    //utp or combo
+		if (link_fiber)
+			ytphy_write_ext(phydev, 0xa000, 2);
+		if (link_utp)
+			ytphy_write_ext(phydev, 0xa000, 0);
+	}
+	return 0;
+}
+
+int yt8521_suspend(struct phy_device *phydev)
+{
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	int value;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->lock);
+#else
+	/* no need lock in 4.19 */
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 2);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+int yt8521_resume(struct phy_device *phydev)
+{
+	int value, ret;
+
+	/* disable auto sleep */
+	value = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+	if (value < 0)
+		return value;
+
+	value &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+
+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value);
+	if (ret < 0)
+		return ret;
+
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+
+	/* power down both sds & phy in suspend, power up both too */
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 2);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+static int yt8531S_config_init(struct phy_device *phydev)
+{
+	int ret = 0;
+
+#if (YTPHY8531A_XTAL_INIT)
+	ret = yt8531a_xtal_init(phydev);
+	if (ret < 0)
+		return ret;
+#endif
+
+	ret = yt8521_config_init(phydev);
+
+	return ret;
+}
+
+static int yt8531_config_init(struct phy_device *phydev)
+{
+	int ret = 0;
+
+#if (YTPHY8531A_XTAL_INIT)
+	ret = yt8531a_xtal_init(phydev);
+	if (ret < 0)
+		return ret;
+#endif
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+int yt8618_soft_reset(struct phy_device *phydev)
+{
+	int ret;
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	ret = ytphy_soft_reset(phydev);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+int yt8614_soft_reset(struct phy_device *phydev)
+{
+	int ret;
+
+	/* qsgmii */
+	ytphy_write_ext(phydev, 0xa000, 2);
+	ret = ytphy_soft_reset(phydev);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+
+	/* sgmii */
+	ytphy_write_ext(phydev, 0xa000, 3);
+	ret = ytphy_soft_reset(phydev);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+
+	/* utp */
+	ytphy_write_ext(phydev, 0xa000, 0);
+	ret = ytphy_soft_reset(phydev);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+#endif
+
+static int yt8618_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	unsigned int retries = 12;
+#if (YTPHY_861X_ABC_VER)
+	int port = 0;
+#endif
+
+	phydev->irq = PHY_POLL;
+
+#if (YTPHY_861X_ABC_VER)
+	port = yt8614_get_port_from_phydev(phydev);
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+	if (ret < 0)
+		return ret;
+
+	/* for utp to optimize signal */
+	ret = ytphy_write_ext(phydev, 0x41, 0x33);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x42, 0x66);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x43, 0xaa);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x44, 0xd0d);
+	if (ret < 0)
+		return ret;
+
+#if (YTPHY_861X_ABC_VER)
+	if ((port == 2) || (port == 5)) {
+		ret = ytphy_write_ext(phydev, 0x57, 0x2929);
+		if (ret < 0)
+			return ret;
+	}
+#endif
+
+	val = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, val | BMCR_RESET);
+	do {
+		msleep(50);
+		ret = phy_read(phydev, MII_BMCR);
+		if (ret < 0)
+			return ret;
+	} while ((ret & BMCR_RESET) && --retries);
+	if (ret & BMCR_RESET)
+		return -ETIMEDOUT;
+
+	/* for QSGMII optimization */
+	ytphy_write_ext(phydev, 0xa000, 0x02);
+
+	ret = ytphy_write_ext(phydev, 0x3, 0x4F80);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+	ret = ytphy_write_ext(phydev, 0xe, 0x4F80);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d\n", __func__, phydev->addr);
+#else
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d\n", __func__, phydev->mdio.addr);
+#endif
+	return ret;
+}
+
+static int yt8614_hw_strap_polling(struct phy_device *phydev)
+{
+	int val = 0;
+
+	val = ytphy_read_ext(phydev, 0xa007) & 0xf;
+	switch (val) {
+	case 8:		//4'b1000, Fiber x4 + Copper x4
+	case 12:	//4'b1100, QSGMII x1 + Combo x4 mode;
+	case 13:	//4'b1101, QSGMII x1 + Combo x4 mode;
+		return (YT_PHY_MODE_FIBER | YT_PHY_MODE_UTP);
+	case 14:	//4'b1110, QSGMII x1 + SGMII(MAC) x4 mode;
+	case 11:	//4'b1011, QSGMII x1 + Fiber x4 mode;
+		return YT_PHY_MODE_FIBER;
+	case 9:		//4'b1001, Reserved.
+	case 10:	//4'b1010, QSGMII x1 + Copper x4 mode
+	case 15:	//4'b1111, SGMII(PHY) x4 + Copper x4 mode
+	default:
+		return YT_PHY_MODE_UTP;
+	}
+}
+
+#if (YTPHY_861X_ABC_VER)
+static int yt8614_get_port_from_phydev(struct phy_device *phydev)
+{
+	int tmp = ytphy_read_ext(phydev, 0xa0ff);
+	int phy_addr = 0;
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	phy_addr = (unsigned int)phydev->addr;
+#else
+	phy_addr = (unsigned int)phydev->mdio.addr;
+#endif
+
+	if ((phy_addr - tmp) < 0) {
+		ytphy_write_ext(phydev, 0xa0ff, phy_addr);
+		tmp = phy_addr;
+	}
+
+	return (phy_addr - tmp);
+}
+#endif
+
+static int yt8614_config_init(struct phy_device *phydev)
+{
+	int ret = 0;
+	int val, hw_strap_mode;
+	unsigned int retries = 12;
+#if (YTPHY_861X_ABC_VER)
+	int port = 0;
+#endif
+	phydev->irq = PHY_POLL;
+
+	/* NOTE: this function should not be called more than one for each chip. */
+	hw_strap_mode = ytphy_read_ext(phydev, 0xa007) & 0xf;
+
+#if (YTPHY_861X_ABC_VER)
+	port = yt8614_get_port_from_phydev(phydev);
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+	if (ret < 0)
+		return ret;
+
+	/* for utp to optimize signal */
+	ret = ytphy_write_ext(phydev, 0x41, 0x33);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x42, 0x66);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x43, 0xaa);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x44, 0xd0d);
+	if (ret < 0)
+		return ret;
+
+#if (YTPHY_861X_ABC_VER)
+	if (port == 2) {
+		ret = ytphy_write_ext(phydev, 0x57, 0x2929);
+		if (ret < 0)
+			return ret;
+	}
+#endif
+
+	/* soft reset to take config effect */
+	val = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, val | BMCR_RESET);
+	do {
+		msleep(50);
+		ret = phy_read(phydev, MII_BMCR);
+		if (ret < 0)
+			return ret;
+	} while ((ret & BMCR_RESET) && --retries);
+	if (ret & BMCR_RESET)
+		return -ETIMEDOUT;
+
+	/* for QSGMII optimization */
+	ytphy_write_ext(phydev, 0xa000, 0x02);
+	ret = ytphy_write_ext(phydev, 0x3, 0x4F80);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+	ret = ytphy_write_ext(phydev, 0xe, 0x4F80);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+
+	/* for SGMII optimization */
+	ytphy_write_ext(phydev, 0xa000, 0x03);
+	ret = ytphy_write_ext(phydev, 0x3, 0x2420);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+	ret = ytphy_write_ext(phydev, 0xe, 0x24a0);
+	if (ret < 0) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		return ret;
+	}
+
+	/* back up to utp*/
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, chip mode: %d\n", __func__, phydev->addr, hw_strap_mode);
+#else
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, chip mode: %d\n", __func__, phydev->mdio.addr, hw_strap_mode);
+#endif
+	return ret;
+}
+
+int yt8618_aneg_done(struct phy_device *phydev)
+{
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+	return genphy_aneg_done(phydev);
+#else
+	return 1;
+#endif
+}
+
+int yt8614_aneg_done(struct phy_device *phydev)
+{
+	int link_fiber = 0, link_utp = 0;
+
+	if (YT8614_PHY_MODE_CURR & YT_PHY_MODE_FIBER) {
+		/* reading Fiber */
+		ytphy_write_ext(phydev, 0xa000, 3);
+		link_fiber = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
+	}
+
+	if (YT8614_PHY_MODE_CURR & YT_PHY_MODE_UTP) {
+		/* reading UTP */
+		ytphy_write_ext(phydev, 0xa000, 0);
+		link_utp = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
+	}
+
+	return !!(link_fiber | link_utp);
+}
+
+static int yt8614_read_status(struct phy_device *phydev)
+{
+	int ret;
+	int val, yt8614_fiber_latch_val, yt8614_fiber_curr_val;
+	int link;
+	int link_utp = 0, link_fiber = 0;
+
+	if (YT8614_PHY_MODE_CURR & YT_PHY_MODE_UTP) {
+		/* switch to utp and reading regs  */
+		ret = ytphy_write_ext(phydev, 0xa000, 0);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link) {
+			link_utp = 1;
+			// here is same as 8521 and re-use the function;
+			yt8521_adjust_status(phydev, val, 1);
+		} else {
+			link_utp = 0;
+		}
+	}
+
+	if (YT8614_PHY_MODE_CURR & YT_PHY_MODE_FIBER) {
+		/* reading Fiber/sgmii */
+		ret = ytphy_write_ext(phydev, 0xa000, 3);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		/* for fiber, from 1000m to 100m, there is not link down from 0x11,
+		 * and check reg 1 to identify such case
+		 */
+		yt8614_fiber_latch_val = phy_read(phydev, MII_BMSR);
+		yt8614_fiber_curr_val = phy_read(phydev, MII_BMSR);
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link && yt8614_fiber_latch_val != yt8614_fiber_curr_val) {
+			link = 0;
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				__func__, phydev->addr, yt8614_fiber_latch_val, yt8614_fiber_curr_val);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				__func__, phydev->mdio.addr, yt8614_fiber_latch_val, yt8614_fiber_curr_val);
+#endif
+		}
+
+		if (link) {
+			link_fiber = 1;
+			yt8521_adjust_status(phydev, val, 0);
+		} else {
+			link_fiber = 0;
+		}
+	}
+
+	if (link_utp || link_fiber) {
+		if (phydev->link == 0)
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media %s\n",
+				__func__, phydev->addr, (link_utp && link_fiber) ? "both UTP and Fiber" : (link_utp ? "UTP" : "Fiber"));
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media %s\n",
+				__func__, phydev->mdio.addr, (link_utp && link_fiber) ? "both UTP and Fiber" : (link_utp ? "UTP" : "Fiber"));
+#endif
+		phydev->link = 1;
+	} else {
+		if (phydev->link == 1)
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n", __func__, phydev->addr);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n", __func__, phydev->mdio.addr);
+#endif
+		phydev->link = 0;
+	}
+
+	if (YT8614_PHY_MODE_CURR & YT_PHY_MODE_UTP) {
+		if (link_utp)
+			ytphy_write_ext(phydev, 0xa000, 0);
+	}
+	return 0;
+}
+
+static int yt8618_read_status(struct phy_device *phydev)
+{
+	int ret;
+	/* maybe for 8614 yt8521_fiber_latch_val, yt8521_fiber_curr_val; */
+	int val;
+	int link;
+	int link_utp = 0, link_fiber = 0;
+
+	/* switch to utp and reading regs  */
+	ret = ytphy_write_ext(phydev, 0xa000, 0);
+	if (ret < 0)
+		return ret;
+
+	val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+	if (val < 0)
+		return val;
+
+	link = val & (BIT(YT8521_LINK_STATUS_BIT));
+	if (link) {
+		link_utp = 1;
+		yt8521_adjust_status(phydev, val, 1);
+	} else {
+		link_utp = 0;
+	}
+
+	if (link_utp || link_fiber)
+		phydev->link = 1;
+	else
+		phydev->link = 0;
+
+	return 0;
+}
+
+int yt8618_suspend(struct phy_device *phydev)
+{
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	int value;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->lock);
+#else
+	/* no need lock in 4.19 */
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+int yt8618_resume(struct phy_device *phydev)
+{
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	int value;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+int yt8614_suspend(struct phy_device *phydev)
+{
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	int value;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->lock);
+#else
+	/* no need lock in 4.19 */
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 3);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+int yt8614_resume(struct phy_device *phydev)
+{
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	int value;
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_lock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 3);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	mutex_unlock(&phydev->lock);
+#else
+	/* no need lock/unlock in 4.19 */
+#endif
+#endif /* !(SYS_WAKEUP_BASED_ON_ETH_PKT) */
+
+	return 0;
+}
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+int yt8821_soft_reset(struct phy_device *phydev)
+{
+	int ret, val;
+
+	val = ytphy_read_ext(phydev, 0xa001);
+	ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	ret = ytphy_soft_reset(phydev);
+
+	return ret;
+}
+#endif
+
+static int yt8821_init(struct phy_device *phydev)
+{
+	int ret = 0;
+	int val = 0;
+
+	/* sds pll cfg */
+	ret = ytphy_write_ext(phydev, 0xa050, 0x1000);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa000, 0x2);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x23, 0x47a1);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xbd, 0x3547);
+	if (ret < 0)
+		return ret;
+
+	/* wait 1s */
+	msleep(1000);
+
+	/* calibration dcc */
+	ret = ytphy_write_ext(phydev, 0xbd, 0xa547);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x29, 0x3003);
+	if (ret < 0)
+		return ret;
+
+	/* sds driver swing */
+	ret = ytphy_write_ext(phydev, 0x25, 0x788);
+	if (ret < 0)
+		return ret;
+
+	/* phy cfg */
+	ret = ytphy_write_ext(phydev, 0xa000, 0x0);
+	if (ret < 0)
+		return ret;
+
+	/* phy template cfg */
+	ret = ytphy_write_ext(phydev, 0x471, 0x4545);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x476, 0x4848);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x477, 0x4848);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x478, 0x4848);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x479, 0x4848);
+	if (ret < 0)
+		return ret;
+
+	/* calibrate phy lc pll */
+	ret = ytphy_write_ext(phydev, 0x600, 0x2300);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x8, 0x8041);
+	if (ret < 0)
+		return ret;
+
+	/* prm_small_lng/med */
+	ret = ytphy_write_ext(phydev, 0x388, 0x90);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x387, 0x90);
+	if (ret < 0)
+		return ret;
+
+	/* echo_delay_cfg */
+	ret = ytphy_write_ext(phydev, 0x3, 0xa026);
+	if (ret < 0)
+		return ret;
+
+	/* pbo setting */
+	ret = ytphy_write_ext(phydev, 0x47e, 0x3535);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x47f, 0x3535);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x480, 0x3535);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x481, 0x3535);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x483, 0x2a2a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x484, 0x2a2a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x485, 0x2a2a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x486, 0x2a2a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x488, 0x2121);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x489, 0x2121);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x48a, 0x2121);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x48b, 0x2121);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x48d, 0x1a1a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x48e, 0x1a1a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x48f, 0x1a1a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x490, 0x1a1a);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x492, 0x1515);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x493, 0x1515);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x494, 0x1515);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x495, 0x1515);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x497, 0x1111);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x498, 0x1111);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x499, 0x1111);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x49a, 0x1111);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x49c, 0x0d0d);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x49d, 0x0d0d);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x49e, 0x0d0d);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0x49f, 0x0d0d);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa052, 0x7);
+	if (ret < 0)
+		return ret;
+
+	/* fast link down cfg */
+	ret = ytphy_write_ext(phydev, 0x355, 0x7d07);
+	if (ret < 0)
+		return ret;
+
+	/* soft reset */
+	val = phy_read(phydev, MII_BMCR);
+	if (val < 0)
+		return val;
+	ret = phy_write(phydev, MII_BMCR, val | BMCR_RESET);
+
+	return ret;
+}
+
+static int yt8821_config_init(struct phy_device *phydev)
+{
+	int ret;
+	int val, hw_strap_mode;
+
+	phydev->irq = PHY_POLL;
+
+	/* NOTE: this function should not be called more than one for each chip. */
+	hw_strap_mode = ytphy_read_ext(phydev, 0xa001) & 0x7;
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+	ret = ytphy_config_init(phydev);
+#else
+	ret = genphy_config_init(phydev);
+#endif
+	if (ret < 0)
+		return ret;
+
+	ret = yt8821_init(phydev);
+	if (ret < 0)
+		return ret;
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+
+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, strap mode = %d\n", __func__, phydev->addr, hw_strap_mode);
+#else
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, strap mode = %d\n", __func__, phydev->mdio.addr, hw_strap_mode);
+#endif
+
+	return ret;
+}
+
+/* for fiber mode, there is no 10M speed mode and
+ * this function is for this purpose.
+ */
+static int yt8821_adjust_status(struct phy_device *phydev, int val, int is_utp)
+{
+	int speed_mode, duplex;
+	int speed_mode_bit15_14, speed_mode_bit9;
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+	int speed = -1;
+#else
+	int speed = SPEED_UNKNOWN;
+#endif
+
+	if (is_utp)
+		duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;
+	else
+		duplex = 1;
+
+	/* Bit9-Bit15-Bit14 speed mode 100---2.5G; 010---1000M; 001---100M; 000---10M */
+	speed_mode_bit15_14 = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
+	speed_mode_bit9 = (val & BIT(9)) >> 9;
+	speed_mode = (speed_mode_bit9 << 2) | speed_mode_bit15_14;
+	switch (speed_mode) {
+	case 0:
+		if (is_utp)
+			speed = SPEED_10;
+		break;
+	case 1:
+		speed = SPEED_100;
+		break;
+	case 2:
+		speed = SPEED_1000;
+		break;
+	case 4:
+		speed = SPEED_2500;
+		break;
+	default:
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+		speed = -1;
+#else
+		speed = SPEED_UNKNOWN;
+#endif
+		break;
+	}
+
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+static int yt8821_read_status(struct phy_device *phydev)
+{
+	int ret;
+	int val;
+	int yt8521_fiber_latch_val;
+	int yt8521_fiber_curr_val;
+	int link;
+	int link_utp = 0, link_fiber = 0;
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
+		/* reading UTP */
+		ret = ytphy_write_ext(phydev, 0xa000, 0);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link) {
+			link_utp = 1;
+			yt8821_adjust_status(phydev, val, 1);    /* speed(2500), duplex */
+		} else {
+			link_utp = 0;
+		}
+	} //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) {
+		/* reading Fiber */
+		ret = ytphy_write_ext(phydev, 0xa000, 2);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		//note: below debug information is used to check multiple PHy ports.
+
+		/* for fiber, from 1000m to 100m, there is not link down from 0x11,
+		 * and check reg 1 to identify such case this is important for Linux
+		 * kernel for that, missing linkdown event will cause problem.
+		 */
+		yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);
+		yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link && yt8521_fiber_latch_val != yt8521_fiber_curr_val) {
+			link = 0;
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				__func__, phydev->addr, yt8521_fiber_latch_val, yt8521_fiber_curr_val);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				__func__, phydev->mdio.addr, yt8521_fiber_latch_val, yt8521_fiber_curr_val);
+#endif
+		}
+
+		if (link) {
+			link_fiber = 1;
+			yt8821_adjust_status(phydev, val, 0);
+		} else {
+			link_fiber = 0;
+		}
+	} //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)
+
+	if (link_utp || link_fiber) {
+		if (phydev->link == 0)
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media: %s, mii reg 0x11 = 0x%x\n",
+				__func__, phydev->addr, (link_utp && link_fiber) ? "UNKNOWN MEDIA" : (link_utp ? "UTP" : "Fiber"), (unsigned int)val);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media: %s, mii reg 0x11 = 0x%x\n",
+				__func__, phydev->mdio.addr, (link_utp && link_fiber) ? "UNKNOWN MEDIA" : (link_utp ? "UTP" : "Fiber"), (unsigned int)val);
+#endif
+		phydev->link = 1;
+	} else {
+		if (phydev->link == 1)
+#if (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n", __func__, phydev->addr);
+#else
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n", __func__, phydev->mdio.addr);
+#endif
+
+		phydev->link = 0;
+	}
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
+		if (link_fiber)
+			ytphy_write_ext(phydev, 0xa000, 2);
+		if (link_utp)
+			ytphy_write_ext(phydev, 0xa000, 0);
+	}
+	return 0;
+}
+
+#if (KERNEL_VERSION(5, 1, 21) < LINUX_VERSION_CODE)
+static int yt8821_get_features(struct phy_device *phydev)
+{
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 1);
+	return genphy_read_abilities(phydev);
+}
+#endif
+
+static struct phy_driver ytphy_drvs[] = {
+	{
+		.phy_id         = PHY_ID_YT8010,
+		.name           = "YT8010 Automotive Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_BASIC_FEATURES,
+		.flags          = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset     = yt8010_soft_reset,
+#endif
+		.config_aneg    = yt8010_config_aneg,
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done      = yt8010_aneg_done,
+#endif
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+		.config_init    = ytphy_config_init,
+#else
+		.config_init    = genphy_config_init,
+#endif
+		.read_status    = yt8010_read_status,
+	}, {
+		.phy_id         = PHY_ID_YT8010AS,
+		.name           = "YT8010AS Automotive Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_BASIC_FEATURES,
+		.flags          = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset     = yt8010AS_soft_reset,
+#endif
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done      = yt8010_aneg_done,
+#endif
+		.config_init    = yt8010AS_config_init,
+		.read_status    = yt8010_read_status,
+	}, {
+		.phy_id         = PHY_ID_YT8510,
+		.name           = "YT8510 100/10Mb Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_BASIC_FEATURES,
+		.flags          = PHY_POLL,
+		.config_aneg    = genphy_config_aneg,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+		.config_init    = ytphy_config_init,
+#else
+		.config_init    = genphy_config_init,
+#endif
+		.read_status    = genphy_read_status,
+	}, {
+		.phy_id         = PHY_ID_YT8511,
+		.name           = "YT8511 Gigabit Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_GBIT_FEATURES,
+		.flags          = PHY_POLL,
+		.config_aneg    = genphy_config_aneg,
+#if GMAC_CLOCK_INPUT_NEEDED
+		.config_init    = yt8511_config_init,
+#else
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE) || (KERNEL_VERSION(5, 3, 0) < LINUX_VERSION_CODE)
+		.config_init    = ytphy_config_init,
+#else
+		.config_init    = genphy_config_init,
+#endif
+#endif
+		.read_status    = genphy_read_status,
+		.suspend        = genphy_suspend,
+		.resume         = genphy_resume,
+	}, {
+		.phy_id         = PHY_ID_YT8512,
+		.name           = "YT8512 Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_BASIC_FEATURES,
+		.flags          = PHY_POLL,
+		.config_aneg    = genphy_config_aneg,
+		.config_init    = yt8512_config_init,
+		.read_status    = yt8512_read_status,
+		.suspend        = genphy_suspend,
+		.resume         = genphy_resume,
+	}, {
+		.phy_id         = PHY_ID_YT8512B,
+		.name           = "YT8512B Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_BASIC_FEATURES,
+		.flags          = PHY_POLL,
+		.config_aneg    = genphy_config_aneg,
+		.config_init    = yt8512_config_init,
+		.read_status    = yt8512_read_status,
+		.suspend        = genphy_suspend,
+		.resume         = genphy_resume,
+	}, {
+		.phy_id         = PHY_ID_YT8521,
+		.name           = "YT8521 Ethernet",
+		.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,
+		.features       = PHY_GBIT_FEATURES,
+		.flags          = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset     = yt8521_soft_reset,
+#endif
+		.config_aneg    = genphy_config_aneg,
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done      = yt8521_aneg_done,
+#endif
+		.config_init    = yt8521_config_init,
+		.read_status    = yt8521_read_status,
+		.suspend        = yt8521_suspend,
+		.resume         = yt8521_resume,
+#if (YTPHY_WOL_FEATURE_ENABLE)
+		.get_wol        = &ytphy_wol_feature_get,
+		.set_wol        = &ytphy_wol_feature_set,
+#endif
+	}, {
+		/* same as 8521 */
+		.phy_id        = PHY_ID_YT8531S,
+		.name          = "YT8531S Ethernet",
+		.phy_id_mask   = MOTORCOMM_PHY_ID_MASK,
+		.features      = PHY_GBIT_FEATURES,
+		.flags         = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset    = yt8521_soft_reset,
+#endif
+		.config_aneg   = genphy_config_aneg,
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done     = yt8521_aneg_done,
+#endif
+		.config_init   = yt8531S_config_init,
+		.read_status   = yt8521_read_status,
+		.suspend       = yt8521_suspend,
+		.resume        = yt8521_resume,
+#if (YTPHY_WOL_FEATURE_ENABLE)
+		.get_wol       = &ytphy_wol_feature_get,
+		.set_wol       = &ytphy_wol_feature_set,
+#endif
+	}, {
+		/* same as 8511 */
+		.phy_id        = PHY_ID_YT8531,
+		.name          = "YT8531 Gigabit Ethernet",
+		.phy_id_mask   = MOTORCOMM_PHY_ID_MASK,
+		.features      = PHY_GBIT_FEATURES,
+		.flags         = PHY_POLL,
+		.config_aneg   = genphy_config_aneg,
+
+		.config_init   = yt8531_config_init,
+		.read_status   = genphy_read_status,
+		.suspend       = genphy_suspend,
+		.resume        = genphy_resume,
+#if (YTPHY_WOL_FEATURE_ENABLE)
+		.get_wol       = &ytphy_wol_feature_get,
+		.set_wol       = &ytphy_wol_feature_set,
+#endif
+	}, {
+		.phy_id        = PHY_ID_YT8618,
+		.name          = "YT8618 Ethernet",
+		.phy_id_mask   = MOTORCOMM_MPHY_ID_MASK,
+		.features      = PHY_GBIT_FEATURES,
+		.flags         = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset    = yt8618_soft_reset,
+#endif
+		.config_aneg   = genphy_config_aneg,
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done     = yt8618_aneg_done,
+#endif
+		.config_init   = yt8618_config_init,
+		.read_status   = yt8618_read_status,
+		.suspend       = yt8618_suspend,
+		.resume        = yt8618_resume,
+	},
+	{
+		.phy_id        = PHY_ID_YT8614,
+		.name          = "YT8614 Ethernet",
+		.phy_id_mask   = MOTORCOMM_MPHY_ID_MASK_8614,
+		.features      = PHY_GBIT_FEATURES,
+		.flags         = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset    = yt8614_soft_reset,
+#endif
+		.config_aneg   = genphy_config_aneg,
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done     = yt8614_aneg_done,
+#endif
+		.config_init   = yt8614_config_init,
+		.read_status   = yt8614_read_status,
+		.suspend       = yt8614_suspend,
+		.resume        = yt8614_resume,
+	},
+	{
+		.phy_id        = PHY_ID_YT8821,
+		.name          = "YT8821 2.5Gb Ethernet",
+		.phy_id_mask   = MOTORCOMM_PHY_ID_MASK_8821,
+#if (KERNEL_VERSION(5, 2, 0) > LINUX_VERSION_CODE)
+		.features      = PHY_GBIT_FEATURES,
+#endif
+		.flags         = PHY_POLL,
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+#else
+		.soft_reset    = yt8821_soft_reset,
+#endif
+		.config_aneg   = genphy_config_aneg,
+#if (KERNEL_VERSION(3, 14, 79) < LINUX_VERSION_CODE)
+		.aneg_done     = yt8521_aneg_done,
+#endif
+#if (KERNEL_VERSION(5, 1, 21) < LINUX_VERSION_CODE)
+		.get_features  = yt8821_get_features,
+#endif
+		.config_init   = yt8821_config_init,
+		.read_status   = yt8821_read_status,
+		.suspend       = yt8521_suspend,
+		.resume        = yt8521_resume,
+	},
+};
+
+#if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
+static int ytphy_drivers_register(struct phy_driver *phy_drvs, int size)
+{
+	int i, j;
+	int ret;
+
+	for (i = 0; i < size; i++) {
+		ret = phy_driver_register(&phy_drvs[i]);
+		if (ret)
+			goto err;
+	}
+
+	return 0;
+
+err:
+		for (j = 0; j < i; j++)
+			phy_driver_unregister(&phy_drvs[j]);
+
+	return ret;
+}
+
+static void ytphy_drivers_unregister(struct phy_driver *phy_drvs, int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++)
+		phy_driver_unregister(&phy_drvs[i]);
+}
+
+static int __init ytphy_init(void)
+{
+	return ytphy_drivers_register(ytphy_drvs, ARRAY_SIZE(ytphy_drvs));
+}
+
+static void __exit ytphy_exit(void)
+{
+	ytphy_drivers_unregister(ytphy_drvs, ARRAY_SIZE(ytphy_drvs));
+}
+
+module_init(ytphy_init);
+module_exit(ytphy_exit);
+#else
+/* for linux 4.x */
+module_phy_driver(ytphy_drvs);
+#endif
+
+MODULE_DESCRIPTION("Motorcomm PHY driver");
+MODULE_AUTHOR("Leilei Zhao");
+MODULE_LICENSE("GPL");
+
+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+	{ PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
+	{ PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },
+	{ PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },
+	{ PHY_ID_YT8618, MOTORCOMM_MPHY_ID_MASK },
+	{ PHY_ID_YT8614, MOTORCOMM_MPHY_ID_MASK_8614 },
+	{ PHY_ID_YT8821, MOTORCOMM_PHY_ID_MASK_8821 },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
+
diff --git a/target/linux/phytium/files-5.10/drivers/pwm/pwm-phytium.c b/target/linux/phytium/files-5.10/drivers/pwm/pwm-phytium.c
new file mode 100644
index 00000000000000..d4cc94dde663eb
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/pwm/pwm-phytium.c
@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium PWM driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/export.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/time.h>
+#include <linux/acpi.h>
+
+#define REG_TCNT		0x00
+#define REG_TCTRL		0x04
+#define REG_STAT		0x08
+
+#define REG_TPERIOD		0x0c
+#define REG_PWMCTRL		0x10
+#define REG_PWMCCR		0x14
+
+#define TCTRL_DIV_MASK		0x1ff8
+#define TCTRL_PWMMOD_MASK	0x4
+#define TCTRL_CAPMOD_MASK	0x3
+#define PWM_PERIOD_MASK		0xffff
+#define PWM_DUTY_MASK		0xffff
+#define PWM_MODE_MASK		0x4
+#define PWM_CTRL_INIT		0xc4
+
+#define PWM_NUM  2
+
+#define REG_DBCTRL		0x00
+#define REG_DBCLY		0x04
+#define PWM_UPDBCLY_MASK	0x3ff
+#define PWM_DWDBCLY_MASK	0xffc00
+#define PWM_DB_POLARITY_MASK	0xc
+
+#define PWM_N(x)		((0x400)*(x))
+#define MAX_PARAMETER 2
+
+struct phytium_pwm_state {
+	int rst;
+	int cntmod;
+	int dutymod;
+	unsigned int div;
+	int db_rst;
+	unsigned int updbcly;
+	unsigned int dwdbcly;
+	unsigned int dbpolarity;
+};
+
+struct phytium_pwm_param {
+	int cntmod;
+	int dutymod;
+	unsigned int div;
+	unsigned int updbcly;
+	unsigned int dwdbcly;
+	unsigned int dbpolarity;
+};
+
+struct phytium_pwm_variant {
+	u8 rst_mask;
+	u8 div;
+	int counter_mode;
+	int periodns;
+	int duty_ns;
+	int pwm_mode;
+	u8 duty_mode;
+	int updbcly;
+	int dwdbcly;
+};
+
+struct phytium_pwm_channel {
+	u32 period_ns;
+	u32 duty_ns;
+	u32 tin_ns;
+};
+
+struct phytium_pwm_chip {
+	struct pwm_chip chip;
+	struct pwm_state state_pm[PWM_NUM];
+	struct phytium_pwm_variant variant;
+	struct phytium_pwm_state state;
+	u8 inverter_mask;
+	u8 disabled_mask;
+	int db_init;
+	void __iomem *base;
+	void __iomem *base1;
+	struct phytium_pwm_param parameter[MAX_PARAMETER];
+	unsigned int num_parameters;
+
+	unsigned long clk_rate;
+	struct clk *base_clk;
+};
+
+static inline struct phytium_pwm_chip *to_phytium_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct phytium_pwm_chip, chip);
+}
+
+
+static void pwm_phytium_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	devm_kfree(chip->dev, pwm_get_chip_data(pwm));
+	pwm_set_chip_data(pwm, NULL);
+}
+
+static int pwm_phytium_enable(struct pwm_chip *chip, struct pwm_device *pwm, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+
+	reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
+	reg |= 0x2;
+	our_chip->state_pm[n].enabled = 1;
+	writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
+
+	return 0;
+}
+
+static void pwm_phytium_disable(struct pwm_chip *chip, struct pwm_device *pwm, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+
+	reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
+	reg &= 0xfffffffd;
+	our_chip->state_pm[n].enabled = 0;
+	writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
+}
+
+static void pwm_phytium_dutymod(struct pwm_chip *chip, int dutymod, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+
+	reg = readl(our_chip->base + PWM_N(n) +  REG_PWMCTRL);
+
+	if (dutymod == 0)
+		reg &= 0xfffffeff;
+	else if (dutymod == 1)
+		reg |= 0x100;
+
+	writel(reg, our_chip->base + PWM_N(n) +  REG_PWMCTRL);
+}
+
+static void pwm_phytium_set_div(struct pwm_chip *chip, unsigned int div, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+
+	reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
+	reg &= 0xffff;
+	reg |= (div<<16);
+	writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
+}
+
+static void pwm_phytium_set_tmode(struct pwm_chip *chip, int tmode, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+
+	reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
+	if (tmode == 0)
+		reg &= 0xfffffffb;
+	else if (tmode == 1)
+		reg |= 0x4;
+
+	writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
+}
+
+static void pwm_phytium_set_periodns(struct pwm_chip *chip, unsigned int periodns, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+	int div = our_chip->state.div;
+	u64 cycles;
+
+	cycles = our_chip->clk_rate;
+	cycles *= (periodns / (div + 1));
+	do_div(cycles, NSEC_PER_SEC);
+
+	reg = readl(our_chip->base + PWM_N(n) + REG_TPERIOD);
+	cycles = (cycles & PWM_PERIOD_MASK) - 0x1;
+	our_chip->state_pm[n].period = cycles;
+
+	writel(cycles, our_chip->base + PWM_N(n) + REG_TPERIOD);
+}
+
+static void pwm_phytium_set_duty(struct pwm_chip *chip, unsigned int duty, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+	int div = our_chip->state.div;
+	u64 cycles;
+
+	cycles = our_chip->clk_rate;
+	cycles *= (duty / (div + 1));
+	do_div(cycles, NSEC_PER_SEC);
+
+	reg = readl(our_chip->base + PWM_N(n) + REG_PWMCCR);
+	cycles = (cycles & PWM_DUTY_MASK) - 0x1;
+	our_chip->state_pm[n].duty_cycle = cycles;
+
+	writel(cycles, our_chip->base + PWM_N(n) + REG_PWMCCR);
+}
+
+static int pwm_phytium_set_dbcly(struct pwm_chip *chip, unsigned int updbcly, unsigned int dwdbcly)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+	u64 dbcly, cycles, upcycles, dwcycles;
+
+	reg = readl(our_chip->base + REG_TPERIOD);
+	cycles = our_chip->clk_rate;
+	dbcly &= 0x0;
+	if (updbcly) {
+		upcycles = cycles * updbcly;
+		do_div(upcycles, NSEC_PER_SEC);
+
+		if (upcycles < reg)
+			dbcly |= (upcycles & PWM_UPDBCLY_MASK);
+		else
+			return -EINVAL;
+	}
+
+	if (dwdbcly) {
+		dwcycles = cycles * dwdbcly;
+		do_div(dwcycles, NSEC_PER_SEC);
+
+		if (dwcycles < reg)
+			dbcly |= ((dwcycles << 10) & PWM_DWDBCLY_MASK);
+		else
+			return -EINVAL;
+	}
+
+	writel(dbcly, our_chip->base1 + REG_DBCLY);
+
+	reg = readl(our_chip->base1 + REG_DBCTRL);
+	reg |= 0x30;
+	writel(reg, our_chip->base1 + REG_DBCTRL);
+
+	return 0;
+}
+
+static void pwm_phytium_set_dbpolarity(struct pwm_chip *chip, unsigned int db_polarity)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 reg;
+
+	reg = readl(our_chip->base1 + REG_DBCTRL);
+	reg &= 0x33;
+	reg |= ((db_polarity<<2) & PWM_DB_POLARITY_MASK);
+	writel(reg, our_chip->base1 + REG_DBCTRL);
+}
+
+static int pwm_phytium_init(struct pwm_chip *chip, struct pwm_device *pwm, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+
+	writel(PWM_CTRL_INIT, our_chip->base + PWM_N(n) + REG_PWMCTRL);
+
+	pwm_phytium_dutymod(chip, our_chip->state.dutymod, n);
+	pwm_phytium_set_div(chip, our_chip->state.div, n);
+	pwm_phytium_set_tmode(chip, our_chip->state.cntmod, n);
+
+	return 0;
+}
+
+static int pwm_phytium_db_init(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+
+	pwm_phytium_set_dbcly(chip, our_chip->state.updbcly, our_chip->state.dwdbcly);
+	pwm_phytium_set_dbpolarity(chip, our_chip->state.dbpolarity);
+
+	return 0;
+}
+
+static int __pwm_phytium_config(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	pwm_phytium_init(chip, pwm, 0);
+	pwm_phytium_init(chip, pwm, 1);
+	return 0;
+}
+
+static int pwm_phytium_set_polarity(struct pwm_chip *chip, enum pwm_polarity polarity, int n)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	u32 value;
+
+	value = readl(our_chip->base + PWM_N(n) + REG_PWMCTRL);
+
+	if (polarity == PWM_POLARITY_INVERSED) {
+		value &= 0xffffff0f;
+		value |= 0x30;
+	} else if (polarity == PWM_POLARITY_NORMAL) {
+		value &= 0xffffff0f;
+		value |= 0x40;
+	}
+
+	our_chip->state_pm[n].polarity = polarity;
+	writel(value, our_chip->base + PWM_N(n) + REG_PWMCTRL);
+
+	return 0;
+}
+
+static int pwm_phytium_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+			const struct pwm_state *state)
+{
+	struct phytium_pwm_chip *phytium_pwm = to_phytium_pwm_chip(chip);
+	struct pwm_state cstate;
+	u32 reg;
+	int n;
+
+	pwm_get_state(pwm, &cstate);
+
+	n = pwm->hwpwm & BIT(0);
+
+	if ((state->polarity != cstate.polarity) && !state->enabled)
+		pwm_phytium_set_polarity(chip, state->polarity, n);
+
+	if (state->enabled && !cstate.enabled)
+		pwm_phytium_enable(chip, pwm, n);
+
+	if (!state->enabled && cstate.enabled)
+		pwm_phytium_disable(chip, pwm, n);
+
+	if (state->period != cstate.period) {
+		pwm_phytium_set_periodns(chip, state->period, n);
+		if ((phytium_pwm->db_init == 1) && (n == 0))
+			pwm_phytium_db_init(chip, pwm);
+	}
+
+	if (state->duty_cycle != cstate.duty_cycle) {
+		if (phytium_pwm->state.dutymod == true) {
+			reg = readl(phytium_pwm->base + PWM_N(n) + REG_STAT);
+			if ((reg & 0x8) != 0x8)
+				pwm_phytium_set_duty(chip, state->duty_cycle, n);
+		} else {
+			pwm_phytium_set_duty(chip, state->duty_cycle, n);
+		}
+	}
+
+	return 0;
+}
+
+static int pwm_phytium_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
+	struct phytium_pwm_channel *our_chan;
+
+	our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
+	if (!our_chan)
+		return -ENOMEM;
+
+	pwm_set_chip_data(pwm, our_chan);
+	__pwm_phytium_config(&our_chip->chip, our_chip->chip.pwms);
+
+	return 0;
+}
+
+static const struct pwm_ops pwm_phytium_ops = {
+	.request = pwm_phytium_request,
+	.free    = pwm_phytium_free,
+	.apply   = pwm_phytium_apply,
+	.owner   = THIS_MODULE,
+};
+
+static int phytium_pwm_set_parameter(struct phytium_pwm_chip *priv)
+{
+	unsigned int i;
+
+	for (i = 0; i < priv->num_parameters; i++) {
+		if (priv->parameter[i].updbcly > 0 || priv->parameter[i].dwdbcly > 0) {
+			priv->db_init = 1;
+			priv->state.db_rst = 1;
+		}
+
+		priv->state.cntmod = priv->parameter[i].cntmod;
+		priv->state.dutymod = priv->parameter[i].dutymod;
+		priv->state.div = priv->parameter[i].div;
+		priv->state.updbcly = priv->parameter[i].updbcly;
+		priv->state.dwdbcly = priv->parameter[i].dwdbcly;
+		priv->state.dbpolarity = priv->parameter[i].dbpolarity;
+	}
+	priv->state.rst = 1;
+
+	return 0;
+}
+
+static int pwm_phytium_probe_parameter(struct phytium_pwm_chip *priv,
+				       struct fwnode_handle *np)
+{
+	int nb, ret, array_size;
+	unsigned int i;
+
+	array_size = fwnode_property_read_u32_array(np, "phytium,db", NULL, 0);
+	nb = array_size / (sizeof(struct phytium_pwm_param) / sizeof(u32));
+	if (nb <= 0 || nb > MAX_PARAMETER)
+		return -EINVAL;
+
+	priv->num_parameters = nb;
+	ret = fwnode_property_read_u32_array(np, "phytium,db",
+					 (u32 *)priv->parameter, array_size);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < priv->num_parameters; i++) {
+		if (priv->parameter[i].cntmod > 1 ||
+			priv->parameter[i].dutymod > 1 ||
+			priv->parameter[i].div > 4096 ||
+			priv->parameter[i].dbpolarity > 3)
+			return -EINVAL;
+	}
+
+	return phytium_pwm_set_parameter(priv);
+}
+static int pwm_phytium_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fwnode_handle *np = dev_fwnode(dev);
+	struct phytium_pwm_chip *chip;
+	struct resource *res;
+	int ret;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+
+	if (chip == NULL)
+		return -ENOMEM;
+
+	chip->chip.dev = &pdev->dev;
+	chip->chip.ops = &pwm_phytium_ops;
+	chip->chip.base = -1;
+	chip->chip.npwm = PWM_NUM;
+	chip->inverter_mask = BIT(PWM_NUM) - 1;
+
+	if (dev->of_node) {
+		chip->chip.of_xlate = of_pwm_xlate_with_flags;
+		chip->chip.of_pwm_n_cells = 3;
+	}
+	ret = pwm_phytium_probe_parameter(chip, np);
+	if (ret) {
+		dev_err(dev, "failed to set parameter\n");
+		return ret;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	chip->base1 = devm_ioremap_resource(&pdev->dev, res);
+	chip->base = (chip->base1 + 0x400);
+
+	if (IS_ERR(chip->base)) {
+		dev_err(dev, "failed to get base_addr\n");
+		return PTR_ERR(chip->base);
+	}
+	if (dev->of_node) {
+	chip->base_clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(chip->base_clk)) {
+		dev_err(dev, "failed to get clk\n");
+		return PTR_ERR(chip->base_clk);
+	}
+
+	ret = clk_prepare_enable(chip->base_clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable clk\n");
+		return ret;
+	}
+	chip->clk_rate = clk_get_rate(chip->base_clk);
+	} else if (has_acpi_companion(dev)){
+               if(fwnode_property_read_u32(dev_fwnode(dev),"clock-frequency", (u32 *)&(chip->clk_rate) ) <0)
+                       chip->clk_rate = 50000000;
+	}
+	platform_set_drvdata(pdev, chip);
+
+	ret = pwmchip_add(&chip->chip);
+
+	if (ret < 0) {
+		dev_err(dev, "failed to register PWM chip\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pwm_phytium_remove(struct platform_device *pdev)
+{
+	struct phytium_pwm_chip *chip = platform_get_drvdata(pdev);
+
+	pwmchip_remove(&chip->chip);
+
+	clk_disable_unprepare(chip->base_clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int pwm_phytium_pm_init(struct phytium_pwm_chip *priv)
+{
+	int i;
+
+	__pwm_phytium_config(&priv->chip, priv->chip.pwms);
+	for (i = 0; i < priv->chip.npwm; i++) {
+		writel(priv->state_pm[i].period, priv->base + PWM_N(i) + REG_TPERIOD);
+		if ((priv->db_init == 1) && (i == 0))
+			pwm_phytium_db_init(&priv->chip, priv->chip.pwms);
+		writel(priv->state_pm[i].duty_cycle, priv->base + PWM_N(i) +  REG_PWMCTRL);
+		pwm_phytium_set_polarity(&priv->chip, priv->state_pm[i].polarity, i);
+		if (priv->state_pm[i].enabled)
+			pwm_phytium_enable(&priv->chip, priv->chip.pwms, i);
+	}
+
+	return 0;
+}
+
+static int pwm_phytium_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int pwm_phytium_resume(struct device *dev)
+{
+	struct phytium_pwm_chip *priv = dev_get_drvdata(dev);
+
+	pwm_phytium_pm_init(priv);
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_pwm_dev_pm_ops, pwm_phytium_suspend, pwm_phytium_resume);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_pwm_acpi_ids[] = {
+       { "PHYT0029", 0 },
+       { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(acpi, phytium_pwm_acpi_ids);
+#endif
+
+static const struct of_device_id phytium_pwm_matches[] = {
+	{ .compatible = "phytium,pwm" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, phytium_pwm_matches);
+
+static struct platform_driver pwm_phytium_driver = {
+	.driver = {
+		.name = "phytium-pwm",
+		.pm = &phytium_pwm_dev_pm_ops,
+		.of_match_table = phytium_pwm_matches,
+		.acpi_match_table = ACPI_PTR(phytium_pwm_acpi_ids),
+	},
+	.probe = pwm_phytium_probe,
+	.remove = pwm_phytium_remove,
+};
+module_platform_driver(pwm_phytium_driver);
+
+MODULE_DESCRIPTION("Phytium SoC PWM driver");
+MODULE_AUTHOR("Yang Liu <yangliu2021@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/remoteproc/homo_remoteproc.c b/target/linux/phytium/files-5.10/drivers/remoteproc/homo_remoteproc.c
new file mode 100644
index 00000000000000..056cabdd73b59a
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/remoteproc/homo_remoteproc.c
@@ -0,0 +1,349 @@
+/*
+ * Homogeneous Remote Processor Control Driver
+ *
+ * Copyright (c) 2022-2023 Phytium Technology Co., Ltd.
+ * Author: Shaojun Yang <yangshaojun@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it under the terms
+ * of the GNU General Public License version 2 as published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/arm-smccc.h>
+#include <linux/irqchip/arm-gic-v3.h>
+#include <linux/remoteproc.h>
+#include <linux/psci.h>
+#include <linux/cpu.h>
+#include <linux/cpuhotplug.h>
+
+#include "remoteproc_internal.h"
+
+#define RPROC_RESOURCE_ENTRIES      8
+
+#define PSCI_VERSION                0x84000000
+#define CPU_SUSPEND                 0xc4000001
+#define CPU_OFF                     0x84000002
+#define CPU_ON                      0xc4000003
+#define AFFINITY_INFO               0xc4000004
+#define MIGRATE                     0xc4000005
+
+/* Resource table for the homo remote processors */
+struct homo_resource_table {
+	unsigned int version;
+	unsigned int num;
+	unsigned int reserved[2];
+	unsigned int offset[RPROC_RESOURCE_ENTRIES];
+
+	/* Note: linux kenrel 'struct fw_rsc_vdev' has no 'type' field, here add to align data structre */
+	uint32_t type;
+	/* rpmsg vdev entry */
+	struct fw_rsc_vdev rpmsg_vdev;
+	struct fw_rsc_vdev_vring rpmsg_vring0;
+	struct fw_rsc_vdev_vring rpmsg_vring1;
+};
+
+struct homo_rproc {
+	struct rproc *rproc;
+	struct homo_resource_table *rsc;
+
+	u64 phys_addr;
+	void *addr;
+	u64 size;
+
+	int irq;
+	int cpu;
+};
+
+static int homo_rproc_irq;
+static struct homo_rproc *g_priv;
+static struct work_struct workqueue;
+
+#define MPIDR_TO_SGI_AFFINITY(cluster_id, level)        (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT)
+
+void gicv3_ipi_send_single(int irq, u64 mpidr)
+{
+	u16 tlist = 0;
+	u64 cluster_id;
+	u64 sgi1r;
+
+	/* Ensure stores to Normal memory are visible to other CPUs before sending the IPI. */
+	wmb();
+
+	cluster_id = mpidr & ~0xffUL;
+	tlist |= 1 << (mpidr & 0xf);
+
+	/* Send the IPIs for the target list of this cluster */
+	sgi1r = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
+			MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
+			irq << 24 |
+			MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | tlist);
+	gic_write_sgi1r(sgi1r);
+
+	/* Force the above writes to ICC_SGI1R_EL1 to be executed */
+	isb();
+}
+
+static void homo_rproc_vq_irq(struct work_struct *work)
+{
+	struct homo_rproc *priv = g_priv;
+	struct homo_resource_table *rsc = priv->rsc;
+	struct rproc *rproc = priv->rproc;
+
+	rproc_vq_interrupt(rproc, rsc->rpmsg_vring0.notifyid);
+}
+
+static int homo_rproc_start(struct rproc *rproc)
+{
+	int err;
+	struct homo_rproc *priv = rproc->priv;
+	int phys_cpuid = cpu_logical_map(priv->cpu);
+	struct arm_smccc_res smc_res;
+
+	err = psci_ops.affinity_info(phys_cpuid, 0);
+	if (err == 0)
+		remove_cpu(priv->cpu);
+
+	INIT_WORK(&workqueue, homo_rproc_vq_irq);
+
+	priv->rsc = (struct homo_resource_table *)rproc->table_ptr;
+
+	/* ARMv8 requires to clean D-cache and invalidate I-cache for memory containing new instructions. */
+	flush_icache_range((unsigned long)priv->addr, (unsigned long)(priv->addr + priv->size));
+
+	arm_smccc_smc(CPU_ON, phys_cpuid, (unsigned long long)priv->phys_addr, 0, 0, 0, 0, 0, &smc_res);
+
+	return smc_res.a0;
+}
+
+static int homo_rproc_stop(struct rproc *rproc)
+{
+	int err;
+	struct homo_rproc *priv = rproc->priv;
+
+	err = psci_ops.affinity_info(cpu_logical_map(priv->cpu), 0);
+	if (err == 1)
+		add_cpu(priv->cpu);
+
+	return 0;
+}
+
+static void *homo_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len)
+{
+	struct homo_rproc *priv = rproc->priv;
+
+	return priv->addr + (da - rproc->bootaddr);
+}
+
+static void homo_rproc_kick(struct rproc *rproc, int vqid)
+{
+	struct homo_rproc *priv = rproc->priv;
+
+	if (rproc->state == RPROC_RUNNING)
+		gicv3_ipi_send_single(priv->irq, cpu_logical_map(priv->cpu));
+
+	return ;
+}
+
+static const struct rproc_ops homo_rproc_ops = {
+	.start = homo_rproc_start,
+	.stop = homo_rproc_stop,
+	.kick = homo_rproc_kick,
+	.da_to_va = homo_rproc_da_to_va,
+};
+
+static void __iomem *homo_ioremap_prot(phys_addr_t addr, size_t size, pgprot_t prot)
+{
+	unsigned long offset, vaddr;
+	phys_addr_t last_addr;
+	struct vm_struct *area;
+
+	/* Disallow wrap-around or zero size */
+	last_addr = addr + size - 1;
+	if (!size || last_addr < addr)
+		return NULL;
+
+	/* Page-align mappings */
+	offset = addr & (~PAGE_MASK);
+	addr -= offset;
+	size = PAGE_ALIGN(size + offset);
+
+	area = get_vm_area_caller(size, VM_IOREMAP,
+			__builtin_return_address(0));
+	if (!area)
+		return NULL;
+	vaddr = (unsigned long)area->addr;
+
+	if (ioremap_page_range(vaddr, vaddr + size, addr, prot)) {
+		free_vm_area(area);
+		return NULL;
+	}
+
+	return (void __iomem *)(vaddr + offset);
+}
+
+static irqreturn_t homo_rproc_irq_handler(int irq, void *data)
+{
+	schedule_work(&workqueue);
+	return IRQ_HANDLED;
+}
+
+static int homo_rproc_starting_cpu(unsigned int cpu)
+{
+	enable_percpu_irq(homo_rproc_irq, irq_get_trigger_type(homo_rproc_irq));
+	return 0;
+}
+
+static int homo_rproc_dying_cpu(unsigned int cpu)
+{
+	disable_percpu_irq(homo_rproc_irq);
+	return 0;
+}
+
+static int homo_rproc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node, *p;
+	struct device_node *np_mem;
+	struct resource res;
+	struct rproc *rproc;
+	const char *fw_name;
+	struct homo_rproc *priv;
+	int ret;
+	unsigned int ipi, cpu;
+	struct of_phandle_args oirq;
+
+	ret = rproc_of_parse_firmware(dev, 0, &fw_name);
+	if (ret) {
+		dev_err(dev, "failed to parse firmware-name property, ret = %d\n", ret);
+		return ret;
+	}
+
+	rproc = rproc_alloc(dev, np->name, &homo_rproc_ops, fw_name, sizeof(*priv));
+	if (!rproc)
+		return -ENOMEM;
+
+	rproc->auto_boot = false;
+	rproc->has_iommu = false;
+
+	platform_set_drvdata(pdev, rproc);
+
+	priv = g_priv = rproc->priv;
+	priv->rproc = rproc;
+
+	/* The following values can be modified through devicetree 'homo_rproc' node */
+	if (of_property_read_u32(np, "remote-processor", &cpu)) {
+		dev_err(dev, "not found 'remote-processor' property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(np, "inter-processor-interrupt", &ipi)) {
+		dev_err(dev, "not found 'inter-processor-interrupt' property\n");
+		return -EINVAL;
+	}
+
+	/* The gic-v3 driver has registered the 0-7 range of SGI interrupt for system purpose */
+	if (ipi < 8) {
+		dev_err(dev, "'inter-processor-interrupt' is %d, should be between 9~15\n", ipi);
+		return -EINVAL;
+	}
+
+	priv->cpu = cpu;
+	priv->irq = ipi;
+
+	dev_info(dev, "remote-processor = %d, inter-processor-interrupt = %d\n", cpu, ipi);
+
+	np_mem = of_parse_phandle(np, "memory-region", 0);
+	ret = of_address_to_resource(np_mem, 0, &res);
+	if (ret) {
+		dev_err(dev, "can't find memory-region for Baremetal\n");
+		return ret;
+	}
+
+	priv->rsc = NULL;
+	priv->addr = NULL;
+
+	priv->phys_addr = res.start;
+	priv->size = resource_size(&res);
+
+	/* Map physical memory region reserved for homo remote processor. */
+	priv->addr = homo_ioremap_prot(priv->phys_addr, priv->size, PAGE_KERNEL_EXEC);
+	if (!priv->addr) {
+		dev_err(dev, "ioremap failed\n");
+		return -ENOMEM;
+	}
+	dev_info(dev, "ioremap: phys_addr = %016llx, addr = %llx, size = %lld\n",
+			priv->phys_addr, (u64)(priv->addr), priv->size);
+
+	/* Look for the interrupt parent. */
+	p = of_irq_find_parent(np);
+	if (p == NULL) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	oirq.np = p;
+	oirq.args_count = 1;
+	oirq.args[0] = ipi;
+	homo_rproc_irq = irq_create_of_mapping(&oirq);
+	if (homo_rproc_irq <= 0) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = request_percpu_irq(homo_rproc_irq, homo_rproc_irq_handler, "homo-rproc-ipi", &cpu_number);
+	if (ret) {
+		dev_err(dev, "failed to request percpu irq, status = %d\n", ret);
+		goto err;
+	}
+
+	ret = cpuhp_setup_state(CPUHP_AP_HOMO_RPROC_STARTING, "remoteproc/homo_rproc:starting", homo_rproc_starting_cpu, homo_rproc_dying_cpu);
+	if (ret) {
+		dev_err(dev, "cpuhp setup state failed, status = %d\n", ret);
+		goto err;
+	}
+
+	ret = rproc_add(rproc);
+	if (ret) {
+		dev_err(dev, "failed to add register device with remoteproc core, status = %d\n", ret);
+		goto err;
+	}
+
+	return 0;
+
+err:
+	vunmap((void *)((unsigned long)priv->addr & PAGE_MASK));
+	return ret;
+}
+
+static int homo_rproc_remove(struct platform_device *pdev)
+{
+	struct rproc *rproc = platform_get_drvdata(pdev);
+
+	rproc_del(rproc);
+	rproc_free(rproc);
+
+	return 0;
+}
+
+static const struct of_device_id homo_rproc_ids[] = {
+	{ .compatible = "homo,rproc", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, homo_rproc_ids);
+
+static struct platform_driver homo_rproc_driver = {
+	.probe = homo_rproc_probe,
+	.remove = homo_rproc_remove,
+	.driver = {
+		.name = "homo-rproc",
+		.of_match_table = of_match_ptr(homo_rproc_ids),
+	},
+};
+module_platform_driver(homo_rproc_driver);
+
+MODULE_DESCRIPTION("Homogeneous Remote Processor Control Driver");
+MODULE_AUTHOR("Shaojun Yang <yangshaojun@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/rtc/rtc-sd3068.c b/target/linux/phytium/files-5.10/drivers/rtc/rtc-sd3068.c
new file mode 100755
index 00000000000000..6abd0cd852f3aa
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/rtc/rtc-sd3068.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * rtc-sd3068.c - RTC driver for some mostly-compatible I2C chips.
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/bcd.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/rtc/ds1307.h>
+#include <linux/rtc.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#define SD3068_REG_SC			0x00
+#define SD3068_REG_MN			0x01
+#define SD3068_REG_HR			0x02
+#define SD3068_REG_DW			0x03
+#define SD3068_REG_DM			0x04
+#define SD3068_REG_MO			0x05
+#define SD3068_REG_YR			0x06
+
+#define SD3068_REG_CTRL1		0x0f
+#define SD3068_REG_CTRL2		0x10
+#define SD3068_REG_CTRL3		0x11
+
+#define KEY_WRITE1		0x80
+#define KEY_WRITE2		0x04
+#define KEY_WRITE3		0x80
+
+#define NUM_TIME_REGS	(SD3068_REG_YR - SD3068_REG_SC + 1)
+
+/*
+ * The sd3068 has write protection
+ * and we can choose whether or not to use it.
+ * Write protection is turned off by default.
+ */
+#define WRITE_PROTECT_EN	1
+
+struct sd3068 {
+	struct rtc_device	*rtc;
+	struct regmap		*regmap;
+};
+
+/*
+ * In order to prevent arbitrary modification of the time register,
+ * when modification of the register,
+ * the "write" bit needs to be written in a certain order.
+ * 1. set WRITE1 bit
+ * 2. set WRITE2 bit
+ * 3. set WRITE3 bit
+ */
+static void sd3068_enable_reg_write(struct sd3068 *sd3068)
+{
+	regmap_update_bits(sd3068->regmap, SD3068_REG_CTRL2,
+				KEY_WRITE1, KEY_WRITE1);
+	regmap_update_bits(sd3068->regmap, SD3068_REG_CTRL1,
+				KEY_WRITE2, KEY_WRITE2);
+	regmap_update_bits(sd3068->regmap, SD3068_REG_CTRL1,
+				KEY_WRITE3, KEY_WRITE3);
+}
+
+#if WRITE_PROTECT_EN
+/*
+ * In order to prevent arbitrary modification of the time register,
+ * we should disable the write function.
+ * when disable write,
+ * the "write" bit needs to be clear in a certain order.
+ * 1. clear WRITE2 bit
+ * 2. clear WRITE3 bit
+ * 3. clear WRITE1 bit
+ */
+static void sd3068_disable_reg_write(struct sd3068 *sd3068)
+{
+	regmap_update_bits(sd3068->regmap, SD3068_REG_CTRL1,
+				KEY_WRITE2, 0);
+	regmap_update_bits(sd3068->regmap, SD3068_REG_CTRL1,
+				KEY_WRITE3, 0);
+	regmap_update_bits(sd3068->regmap, SD3068_REG_CTRL2,
+				KEY_WRITE1, 0);
+}
+#endif
+
+static int sd3068_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned char hour;
+	unsigned char rtc_data[NUM_TIME_REGS] = {0};
+	struct i2c_client *client = to_i2c_client(dev);
+	struct sd3068 *sd3068 = i2c_get_clientdata(client);
+	int ret;
+	pr_debug("sd3068 read\n");
+
+	ret = regmap_bulk_read(sd3068->regmap, SD3068_REG_SC, rtc_data,
+					NUM_TIME_REGS);
+	if (ret < 0) {
+		dev_err(dev, "reading from RTC failed with err:%d\n", ret);
+		return ret;
+	}
+
+	tm->tm_sec	= bcd2bin(rtc_data[SD3068_REG_SC] & 0x7F);
+	tm->tm_min	= bcd2bin(rtc_data[SD3068_REG_MN] & 0x7F);
+
+	/*
+	 * The sd3068 supports 12/24 hour mode.
+	 * When getting time,
+	 * we need to convert the 12 hour mode to the 24 hour mode.
+	 */
+	hour = rtc_data[SD3068_REG_HR];
+	if (hour & 0x80) /* 24H MODE */
+		tm->tm_hour = bcd2bin(rtc_data[SD3068_REG_HR] & 0x3F);
+	else if (hour & 0x20) /* 12H MODE PM */
+		tm->tm_hour = bcd2bin(rtc_data[SD3068_REG_HR] & 0x1F) + 12;
+	else /* 12H MODE AM */
+		tm->tm_hour = bcd2bin(rtc_data[SD3068_REG_HR] & 0x1F);
+
+	tm->tm_mday = bcd2bin(rtc_data[SD3068_REG_DM] & 0x3F);
+	tm->tm_wday = rtc_data[SD3068_REG_DW] & 0x07;
+	tm->tm_mon	= bcd2bin(rtc_data[SD3068_REG_MO] & 0x1F) - 1;
+	tm->tm_year = bcd2bin(rtc_data[SD3068_REG_YR]) + 100;
+
+	return 0;
+}
+
+static int sd3068_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned char rtc_data[NUM_TIME_REGS];
+	struct i2c_client *client = to_i2c_client(dev);
+	struct sd3068 *sd3068 = i2c_get_clientdata(client);
+	int ret;
+	pr_debug("sd3068 set\n");
+
+	rtc_data[SD3068_REG_SC] = bin2bcd(tm->tm_sec);
+	rtc_data[SD3068_REG_MN] = bin2bcd(tm->tm_min);
+	rtc_data[SD3068_REG_HR] = bin2bcd(tm->tm_hour) | 0x80;
+	rtc_data[SD3068_REG_DM] = bin2bcd(tm->tm_mday);
+	rtc_data[SD3068_REG_DW] = tm->tm_wday & 0x07;
+	rtc_data[SD3068_REG_MO] = bin2bcd(tm->tm_mon) + 1;
+	rtc_data[SD3068_REG_YR] = bin2bcd(tm->tm_year - 100);
+
+#if WRITE_PROTECT_EN
+	sd3068_enable_reg_write(sd3068);
+#endif
+
+	ret = regmap_bulk_write(sd3068->regmap, SD3068_REG_SC, rtc_data,
+				NUM_TIME_REGS);
+	if (ret < 0) {
+		dev_err(dev, "writing to RTC failed with err:%d\n", ret);
+		return ret;
+	}
+
+#if WRITE_PROTECT_EN
+	sd3068_disable_reg_write(sd3068);
+#endif
+
+	return 0;
+}
+
+static const struct rtc_class_ops sd3068_rtc_ops = {
+	.read_time	= sd3068_rtc_read_time,
+	.set_time	= sd3068_rtc_set_time,
+};
+
+static const struct regmap_config regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = 0x11,
+};
+
+static int sd3068_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	int ret;
+	struct sd3068 *sd3068;
+	unsigned char rtc_data[NUM_TIME_REGS] = {0};
+	pr_debug("probed\n");
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
+		return -ENODEV;
+
+	sd3068 = devm_kzalloc(&client->dev, sizeof(*sd3068), GFP_KERNEL);
+	if (!sd3068)
+		return -ENOMEM;
+
+	sd3068->regmap = devm_regmap_init_i2c(client, &regmap_config);
+	if (IS_ERR(sd3068->regmap)) {
+		dev_err(&client->dev, "regmap allocation failed\n");
+		return PTR_ERR(sd3068->regmap);
+	}
+
+	i2c_set_clientdata(client, sd3068);
+
+	sd3068->rtc = devm_rtc_allocate_device(&client->dev);
+	if (IS_ERR(sd3068->rtc))
+		return PTR_ERR(sd3068->rtc);
+
+	sd3068->rtc->ops = &sd3068_rtc_ops;
+	sd3068->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
+	sd3068->rtc->range_max = RTC_TIMESTAMP_END_2099;
+
+	ret = regmap_bulk_read(sd3068->regmap, SD3068_REG_SC, rtc_data,
+					NUM_TIME_REGS);
+	if (ret < 0) {
+		dev_info(&client->dev, "can not read time data when probe\n");
+		return ret;
+	}
+
+	ret = rtc_register_device(sd3068->rtc);
+	if (ret)
+		return ret;
+
+	sd3068_enable_reg_write(sd3068);
+
+	return 0;
+}
+
+
+static const struct acpi_device_id ds1307_acpi_ids[] = {
+	{ .id = "DS1339", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
+
+static const struct i2c_device_id sd3068_id[] = {
+	{ "sd3068", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c,sd3068_id);
+
+static const struct of_device_id sd3068_of_match[] = {
+	{ .compatible = "wave,sd3068" },
+	{ }
+};
+
+static struct i2c_driver sd3068_driver = {
+	.driver = {
+		.name	= "rtc-sd3068",
+		.of_match_table = of_match_ptr(sd3068_of_match),
+		.acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
+	},
+	.probe		= sd3068_probe,
+	.id_table	= sd3068_id,
+};
+
+module_i2c_driver(sd3068_driver);
+MODULE_DEVICE_TABLE(of, sd3068_of_match);
+
+MODULE_DESCRIPTION("RTC driver for SD3068 and similar chips");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-dma.c b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-dma.c
new file mode 100644
index 00000000000000..4f78d0659ef4f0
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-dma.c
@@ -0,0 +1,555 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Special handling for phytium DMA core
+ *
+ */
+#include <linux/completion.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/irqreturn.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/spi/spi.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include "spi-phytium.h"
+
+#define RX_BUSY		0
+#define RX_BURST_LEVEL	16
+#define TX_BUSY		1
+#define TX_BURST_LEVEL	16
+
+#define DMA_MAX_BUF_SIZE	4096
+
+static void phytium_spi_dma_maxburst_init(struct phytium_spi *fts)
+{
+	struct dma_slave_caps caps;
+	u32 max_burst, def_burst;
+	int ret;
+
+	def_burst = fts->fifo_len / 2;
+
+	ret = dma_get_slave_caps(fts->rxchan, &caps);
+	if (!ret && caps.max_burst)
+		max_burst = caps.max_burst;
+	else
+		max_burst = RX_BURST_LEVEL;
+
+	fts->rxburst = min(max_burst, def_burst);
+	phytium_writel(fts, DMARDLR, 0x0);
+
+	ret = dma_get_slave_caps(fts->txchan, &caps);
+	if (!ret && caps.max_burst)
+		max_burst = caps.max_burst;
+	else
+		max_burst = TX_BURST_LEVEL;
+
+	/*
+	 * Having a Rx DMA channel serviced with higher priority than a Tx DMA
+	 * channel might not be enough to provide a well balanced DMA-based
+	 * SPI transfer interface. There might still be moments when the Tx DMA
+	 * channel is occasionally handled faster than the Rx DMA channel.
+	 * That in its turn will eventually cause the SPI Rx FIFO overflow if
+	 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
+	 * cleared by the Rx DMA channel. In order to fix the problem the Tx
+	 * DMA activity is intentionally slowed down by limiting the SPI Tx
+	 * FIFO depth with a value twice bigger than the Tx burst length.
+	 */
+	fts->txburst = min(max_burst, def_burst);
+	/* set dmatdlr to 0 + 1 */
+	phytium_writel(fts, DMATDLR, 0);
+}
+
+static void phytium_spi_dma_sg_burst_init(struct phytium_spi *fts)
+{
+	struct dma_slave_caps tx = {0}, rx = {0};
+
+	dma_get_slave_caps(fts->txchan, &tx);
+	dma_get_slave_caps(fts->rxchan, &rx);
+
+	if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0)
+		fts->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst);
+	else if (tx.max_sg_burst > 0)
+		fts->dma_sg_burst = tx.max_sg_burst;
+	else if (rx.max_sg_burst > 0)
+		fts->dma_sg_burst = rx.max_sg_burst;
+	else
+		fts->dma_sg_burst = 0;
+}
+
+static int phytium_spi_dma_init(struct device *dev, struct phytium_spi *fts)
+{
+	fts->rxchan = dma_request_chan(dev, "rx");
+	if (IS_ERR_OR_NULL(fts->rxchan))
+		return -ENODEV;
+
+	fts->txchan = dma_request_chan(dev, "tx");
+	if (IS_ERR_OR_NULL(fts->txchan)) {
+		dev_err(dev, "can't request chan\n");
+		dma_release_channel(fts->rxchan);
+		fts->rxchan = NULL;
+		return -ENODEV;
+	}
+
+	fts->master->dma_rx = fts->rxchan;
+	fts->master->dma_tx = fts->txchan;
+	init_completion(&fts->dma_completion);
+
+	phytium_spi_dma_maxburst_init(fts);
+	phytium_spi_dma_sg_burst_init(fts);
+
+	return 0;
+}
+
+static void phytium_spi_dma_exit(struct phytium_spi *fts)
+{
+	if (fts->txchan) {
+		dmaengine_terminate_sync(fts->txchan);
+		dma_release_channel(fts->txchan);
+	}
+
+	if (fts->rxchan) {
+		dmaengine_terminate_sync(fts->rxchan);
+		dma_release_channel(fts->rxchan);
+	}
+}
+
+static irqreturn_t phytium_spi_dma_transfer_handler(struct phytium_spi *fts)
+{
+	phytium_spi_check_status(fts, false);
+
+	complete(&fts->dma_completion);
+
+	return IRQ_HANDLED;
+}
+
+static bool phytium_spi_can_dma(struct spi_controller *master,
+			   struct spi_device *spi, struct spi_transfer *xfer)
+{
+	struct phytium_spi *fts = spi_controller_get_devdata(master);
+
+	return xfer->len > fts->fifo_len;
+}
+
+static enum dma_slave_buswidth phytium_spi_dma_convert_width(u8 n_bytes)
+{
+	if (n_bytes == 1)
+		return DMA_SLAVE_BUSWIDTH_1_BYTE;
+	else if (n_bytes == 2)
+		return DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
+}
+
+static int phytium_spi_dma_wait(struct phytium_spi *fts, unsigned int len,
+					u32 speed)
+{
+	unsigned long long ms;
+
+	ms = len * MSEC_PER_SEC * BITS_PER_BYTE;
+	do_div(ms, speed);
+	ms += ms + 200;
+
+	if (ms > UINT_MAX)
+		ms = UINT_MAX;
+
+	ms = wait_for_completion_timeout(&fts->dma_completion,
+					 msecs_to_jiffies(ms));
+
+	if (ms == 0) {
+		dev_err(&fts->master->cur_msg->spi->dev,
+			"DMA transaction timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static inline bool phytium_spi_dma_tx_busy(struct phytium_spi *fts)
+{
+	return !(phytium_readl(fts, SR) & SR_TF_EMPT);
+}
+
+static int phytium_spi_dma_wait_tx_done(struct phytium_spi *fts,
+				   struct spi_transfer *xfer)
+{
+	int retry = SPI_WAIT_RETRIES;
+	struct spi_delay delay;
+	u32 nents;
+
+	nents = phytium_readl(fts, TXFLR);
+	delay.unit = SPI_DELAY_UNIT_SCK;
+	delay.value = nents * fts->n_bytes * BITS_PER_BYTE;
+
+	while (phytium_spi_dma_tx_busy(fts) && retry--)
+		spi_delay_exec(&delay, xfer);
+
+	if (retry < 0) {
+		dev_err(&fts->master->dev, "Tx hanged up\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * fts->dma_chan_busy is set before the dma transfer starts, callback for tx
+ * channel will clear a corresponding bit.
+ */
+static void phytium_spi_dma_tx_done(void *arg)
+{
+	struct phytium_spi *fts = arg;
+
+	clear_bit(TX_BUSY, &fts->dma_chan_busy);
+	if (test_bit(RX_BUSY, &fts->dma_chan_busy))
+		return;
+
+	complete(&fts->dma_completion);
+}
+
+static int phytium_spi_dma_config_tx(struct phytium_spi *fts)
+{
+	struct dma_slave_config txconf;
+
+	memset(&txconf, 0, sizeof(txconf));
+	txconf.direction = DMA_MEM_TO_DEV;
+	txconf.dst_addr = fts->dma_addr;
+	txconf.dst_maxburst = fts->txburst;
+	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	txconf.dst_addr_width = phytium_spi_dma_convert_width(fts->n_bytes);
+	txconf.device_fc = false;
+
+	return dmaengine_slave_config(fts->txchan, &txconf);
+}
+
+static int phytium_spi_dma_submit_tx(struct phytium_spi *fts, struct scatterlist *sgl,
+				unsigned int nents)
+{
+	struct dma_async_tx_descriptor *txdesc;
+	dma_cookie_t cookie;
+	int ret;
+
+	txdesc = dmaengine_prep_slave_sg(fts->txchan, sgl, nents,
+					 DMA_MEM_TO_DEV,
+					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!txdesc)
+		return -ENOMEM;
+
+	txdesc->callback = phytium_spi_dma_tx_done;
+	txdesc->callback_param = fts;
+
+	cookie = dmaengine_submit(txdesc);
+	ret = dma_submit_error(cookie);
+	if (ret) {
+		dmaengine_terminate_sync(fts->txchan);
+		return ret;
+	}
+
+	set_bit(TX_BUSY, &fts->dma_chan_busy);
+
+	return 0;
+}
+
+static inline bool phytium_spi_dma_rx_busy(struct phytium_spi *fts)
+{
+	return !!(phytium_readl(fts, SR) & SR_RF_NOT_EMPT);
+}
+
+static int phytium_spi_dma_wait_rx_done(struct phytium_spi *fts)
+{
+	int retry = SPI_WAIT_RETRIES;
+	struct spi_delay delay;
+	unsigned long ns, us;
+	u32 nents;
+
+	/*
+	 * It's unlikely that DMA engine is still doing the data fetching, but
+	 * if it's let's give it some reasonable time. The timeout calculation
+	 * is based on the synchronous APB/SSI reference clock rate, on a
+	 * number of data entries left in the Rx FIFO, times a number of clock
+	 * periods normally needed for a single APB read/write transaction
+	 * without PREADY signal utilized (which is true for the phytium APB SSI
+	 * controller).
+	 */
+	nents = phytium_readl(fts, RXFLR);
+	ns = 4U * NSEC_PER_SEC / fts->max_freq * nents;
+	if (ns <= NSEC_PER_USEC) {
+		delay.unit = SPI_DELAY_UNIT_NSECS;
+		delay.value = ns;
+	} else {
+		us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
+		delay.unit = SPI_DELAY_UNIT_USECS;
+		delay.value = clamp_val(us, 0, USHRT_MAX);
+	}
+
+	while (phytium_spi_dma_rx_busy(fts) && retry--)
+		spi_delay_exec(&delay, NULL);
+
+	if (retry < 0) {
+		dev_err(&fts->master->dev, "Rx hanged up, nents = %d\n", nents);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * fts->dma_chan_busy is set before the dma transfer starts, callback for rx
+ * channel will clear a corresponding bit.
+ */
+static void phytium_spi_dma_rx_done(void *arg)
+{
+	struct phytium_spi *fts = arg;
+
+	clear_bit(RX_BUSY, &fts->dma_chan_busy);
+	if (test_bit(TX_BUSY, &fts->dma_chan_busy))
+		return;
+
+	complete(&fts->dma_completion);
+}
+
+static int phytium_spi_dma_config_rx(struct phytium_spi *fts)
+{
+	struct dma_slave_config rxconf;
+
+	memset(&rxconf, 0, sizeof(rxconf));
+	rxconf.direction = DMA_DEV_TO_MEM;
+	rxconf.src_addr = fts->dma_addr;
+	rxconf.src_maxburst = fts->rxburst;
+	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	rxconf.src_addr_width = phytium_spi_dma_convert_width(fts->n_bytes);
+	rxconf.device_fc = false;
+
+	return dmaengine_slave_config(fts->rxchan, &rxconf);
+}
+
+static int phytium_spi_dma_submit_rx(struct phytium_spi *fts, struct scatterlist *sgl,
+				unsigned int nents)
+{
+	struct dma_async_tx_descriptor *rxdesc;
+	dma_cookie_t cookie;
+	int ret;
+
+	rxdesc = dmaengine_prep_slave_sg(fts->rxchan, sgl, nents,
+					 DMA_DEV_TO_MEM,
+					 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!rxdesc)
+		return -ENOMEM;
+
+	rxdesc->callback = phytium_spi_dma_rx_done;
+	rxdesc->callback_param = fts;
+
+	cookie = dmaengine_submit(rxdesc);
+	ret = dma_submit_error(cookie);
+	if (ret) {
+		dmaengine_terminate_sync(fts->rxchan);
+		return ret;
+	}
+
+	set_bit(RX_BUSY, &fts->dma_chan_busy);
+
+	return 0;
+}
+
+static int phytium_spi_dma_setup(struct phytium_spi *fts, struct spi_transfer *xfer)
+{
+	u16 imr, dma_ctrl;
+	int ret;
+
+	if (!xfer->tx_buf)
+		return -EINVAL;
+
+	/* Setup DMA channels */
+	ret = phytium_spi_dma_config_tx(fts);
+	if (ret)
+		return ret;
+
+	if (xfer->rx_buf) {
+		ret = phytium_spi_dma_config_rx(fts);
+		if (ret)
+			return ret;
+	}
+
+	/* Set the DMA handshaking interface */
+	dma_ctrl = SPI_DMA_TDMAE;
+	if (xfer->rx_buf)
+		dma_ctrl |= SPI_DMA_RDMAE;
+	phytium_writel(fts, DMACR, dma_ctrl);
+
+	/* Set the interrupt mask */
+	imr = INT_TXOI;
+	if (xfer->rx_buf)
+		imr |= INT_RXUI | INT_RXOI;
+
+	spi_umask_intr(fts, imr);
+
+	reinit_completion(&fts->dma_completion);
+
+	fts->transfer_handler = phytium_spi_dma_transfer_handler;
+
+	return 0;
+}
+
+static int phytium_spi_dma_transfer_all(struct phytium_spi *fts,
+				   struct spi_transfer *xfer)
+{
+	int ret;
+
+	/* Submit the DMA Tx transfer */
+	ret = phytium_spi_dma_submit_tx(fts, xfer->tx_sg.sgl, xfer->tx_sg.nents);
+	if (ret)
+		goto err_clear_dmac;
+
+	/* Submit the DMA Rx transfer if required */
+	if (xfer->rx_buf) {
+		ret = phytium_spi_dma_submit_rx(fts, xfer->rx_sg.sgl,
+					   xfer->rx_sg.nents);
+		if (ret)
+			goto err_clear_dmac;
+
+		/* rx must be started before tx due to spi instinct */
+		dma_async_issue_pending(fts->rxchan);
+	}
+
+	dma_async_issue_pending(fts->txchan);
+
+	ret = phytium_spi_dma_wait(fts, xfer->len, xfer->effective_speed_hz);
+
+err_clear_dmac:
+	phytium_writel(fts, DMACR, 0);
+
+	return ret;
+}
+
+static int phytium_spi_dma_transfer_one(struct phytium_spi *fts,
+				   struct spi_transfer *xfer)
+{
+	struct scatterlist *tx_sg = NULL, *rx_sg = NULL, tx_tmp, rx_tmp;
+	unsigned int tx_len = 0, rx_len = 0;
+	unsigned int base, len;
+	int ret;
+
+	sg_init_table(&tx_tmp, 1);
+	sg_init_table(&rx_tmp, 1);
+
+	for (base = 0, len = 0; base < xfer->len; base += len) {
+		/* Fetch next Tx DMA data chunk */
+		if (!tx_len) {
+			tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg);
+			sg_dma_address(&tx_tmp) = sg_dma_address(tx_sg);
+			tx_len = sg_dma_len(tx_sg);
+		}
+
+		/* Fetch next Rx DMA data chunk */
+		if (!rx_len) {
+			rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg);
+			sg_dma_address(&rx_tmp) = sg_dma_address(rx_sg);
+			rx_len = sg_dma_len(rx_sg);
+		}
+
+		if ((base + DMA_MAX_BUF_SIZE) > xfer->len)
+			len = xfer->len - base;
+		else
+			len = DMA_MAX_BUF_SIZE;
+
+		len = min3(len, tx_len, rx_len);
+
+		sg_dma_len(&tx_tmp) = len;
+		sg_dma_len(&rx_tmp) = len;
+
+		/* Submit DMA Tx transfer */
+		ret = phytium_spi_dma_submit_tx(fts, &tx_tmp, 1);
+		if (ret)
+			break;
+
+		/* Submit DMA Rx transfer */
+		ret = phytium_spi_dma_submit_rx(fts, &rx_tmp, 1);
+		if (ret)
+			break;
+
+		/* Rx must be started before Tx due to SPI instinct */
+		dma_async_issue_pending(fts->rxchan);
+
+		dma_async_issue_pending(fts->txchan);
+
+		/*
+		 * Here we only need to wait for the DMA transfer to be
+		 * finished since SPI controller is kept enabled during the
+		 * procedure this loop implements and there is no risk to lose
+		 * data left in the Tx/Rx FIFOs.
+		 */
+		ret = phytium_spi_dma_wait(fts, len, xfer->effective_speed_hz);
+		if (ret)
+			break;
+
+		reinit_completion(&fts->dma_completion);
+
+		sg_dma_address(&tx_tmp) += len;
+		sg_dma_address(&rx_tmp) += len;
+		tx_len -= len;
+		rx_len -= len;
+	}
+
+	phytium_writel(fts, DMACR, 0);
+
+	return ret;
+}
+
+static int phytium_spi_dma_transfer(struct phytium_spi *fts, struct spi_transfer *xfer)
+{
+	unsigned int nents;
+	int ret;
+
+	nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents);
+
+	/*
+	 * large transfer length caused spi RX FIFO full event
+	 * transfer 4096 bytes each time
+	 */
+	if (xfer->len <= DMA_MAX_BUF_SIZE)
+		ret = phytium_spi_dma_transfer_all(fts, xfer);
+	else
+		ret = phytium_spi_dma_transfer_one(fts, xfer);
+	if (ret)
+		return ret;
+
+	if (fts->master->cur_msg->status == -EINPROGRESS) {
+		ret = phytium_spi_dma_wait_tx_done(fts, xfer);
+		if (ret)
+			return ret;
+	}
+
+	if (xfer->rx_buf && fts->master->cur_msg->status == -EINPROGRESS)
+		ret = phytium_spi_dma_wait_rx_done(fts);
+
+	return ret;
+}
+
+static void phytium_spi_dma_stop(struct phytium_spi *fts)
+{
+	if (test_bit(TX_BUSY, &fts->dma_chan_busy)) {
+		dmaengine_terminate_sync(fts->txchan);
+		clear_bit(TX_BUSY, &fts->dma_chan_busy);
+	}
+	if (test_bit(RX_BUSY, &fts->dma_chan_busy)) {
+		dmaengine_terminate_sync(fts->rxchan);
+		clear_bit(RX_BUSY, &fts->dma_chan_busy);
+	}
+}
+
+static const struct phytium_spi_dma_ops phytium_spi_dma_generic_ops = {
+	.dma_init	= phytium_spi_dma_init,
+	.dma_exit	= phytium_spi_dma_exit,
+	.dma_setup	= phytium_spi_dma_setup,
+	.can_dma	= phytium_spi_can_dma,
+	.dma_transfer	= phytium_spi_dma_transfer,
+	.dma_stop	= phytium_spi_dma_stop,
+};
+
+void phytium_spi_dmaops_set(struct phytium_spi *fts)
+{
+	fts->dma_ops = &phytium_spi_dma_generic_ops;
+}
+EXPORT_SYMBOL_GPL(phytium_spi_dmaops_set);
+
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-pci.c b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-pci.c
new file mode 100644
index 00000000000000..4b83bc1b5d4204
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-pci.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SPI core controller PCI driver.
+ *
+ * Copyright (c) 2019-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/highmem.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/scatterlist.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/property.h>
+
+#include "spi-phytium.h"
+
+#define DRIVER_NAME "phytium_spi_pci"
+
+static int phytium_spi_pci_probe(struct pci_dev *pdev,
+			    const struct pci_device_id *id)
+{
+	struct phytium_spi *fts;
+	int pci_bar = 0;
+	int ret;
+
+	fts = devm_kzalloc(&pdev->dev, sizeof(struct phytium_spi),
+			GFP_KERNEL);
+	if (!fts)
+		return -ENOMEM;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
+	if (ret) {
+		dev_err(&pdev->dev, "pci iomap failed?\n");
+		return ret;
+	}
+
+	fts->regs = pcim_iomap_table(pdev)[pci_bar];
+	if (IS_ERR(fts->regs)) {
+		dev_err(&pdev->dev, "SPI region map failed\n");
+		return PTR_ERR(fts->regs);
+	}
+
+	fts->irq = pdev->irq;
+	if (fts->irq < 0) {
+		dev_err(&pdev->dev, "no irq resource?\n");
+		return fts->irq; /* -ENXIO */
+	}
+
+	fts->bus_num = -1;
+
+	fts->max_freq = 48000000;
+
+	fts->num_cs = 4;
+
+	fts->global_cs = 1;
+
+	ret = phytium_spi_add_host(&pdev->dev, fts);
+	if (ret)
+		return ret;
+
+	pci_set_drvdata(pdev, fts);
+	return 0;
+}
+
+static void phytium_spi_pci_remove(struct pci_dev *pdev)
+{
+	struct phytium_spi *fts = pci_get_drvdata(pdev);
+
+	phytium_spi_remove_host(fts);
+}
+
+
+#ifdef CONFIG_PM_SLEEP
+static int spi_suspend(struct device *dev)
+{
+	struct phytium_spi *fts = dev_get_drvdata(dev);
+
+	return phytium_spi_suspend_host(fts);
+}
+
+static int spi_resume(struct device *dev)
+{
+	struct phytium_spi *fts = dev_get_drvdata(dev);
+
+	return phytium_spi_resume_host(fts);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_spi_pm_ops, spi_suspend, spi_resume);
+
+static const struct pci_device_id phytium_device_pci_tbl[] = {
+	{ PCI_VDEVICE(PHYTIUM, 0xdc2c) },
+	{},
+};
+
+static struct pci_driver phytium_spi_pci_driver = {
+	.name		= DRIVER_NAME,
+	.id_table	= phytium_device_pci_tbl,
+	.probe		= phytium_spi_pci_probe,
+	.remove		= phytium_spi_pci_remove,
+	.driver		= {
+		.pm = &phytium_spi_pm_ops,
+	}
+};
+
+module_pci_driver(phytium_spi_pci_driver);
+
+MODULE_AUTHOR("Yiqun Zhang <zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("PCI Driver for Phytium SPI controller core");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-plat.c b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-plat.c
new file mode 100644
index 00000000000000..51805f1b0c0f7f
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-plat.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SPI core controller platform driver.
+ *
+ * Copyright (c) 2019-2023 Phytium Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/highmem.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/scatterlist.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <linux/acpi.h>
+
+#include "spi-phytium.h"
+
+#define DRIVER_NAME "phytium_spi"
+
+static int phytium_spi_probe(struct platform_device *pdev)
+{
+	struct phytium_spi *fts;
+	struct resource *mem;
+	int ret;
+	int num_cs;
+	int cs_gpio;
+	int global_cs;
+	int i;
+
+	fts = devm_kzalloc(&pdev->dev, sizeof(struct phytium_spi),
+			GFP_KERNEL);
+	if (!fts)
+		return -ENOMEM;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "no mem resource?\n");
+		return -EINVAL;
+	}
+
+	fts->paddr = mem->start;
+	fts->regs = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(fts->regs)) {
+		dev_err(&pdev->dev, "SPI region map failed\n");
+		return PTR_ERR(fts->regs);
+	}
+
+	fts->irq = platform_get_irq(pdev, 0);
+	if (fts->irq < 0) {
+		dev_err(&pdev->dev, "no irq resource?\n");
+		return fts->irq; /* -ENXIO */
+	}
+
+	if (pdev->dev.of_node) {
+		fts->clk = devm_clk_get(&pdev->dev, NULL);
+
+		if (IS_ERR(fts->clk))
+			return PTR_ERR(fts->clk);
+		ret = clk_prepare_enable(fts->clk);
+		if (ret)
+			return ret;
+
+		fts->max_freq = clk_get_rate(fts->clk);
+	} else if (has_acpi_companion(&pdev->dev)) {
+		fts->max_freq = 48000000;
+	}
+
+	fts->bus_num = pdev->id;
+	device_property_read_u32(&pdev->dev, "reg-io-width", &fts->reg_io_width);
+
+	num_cs = 4;
+	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
+	fts->num_cs = num_cs;
+
+	if (pdev->dev.of_node) {
+		int i;
+
+		for (i = 0; i < fts->num_cs; i++) {
+			cs_gpio = of_get_named_gpio(pdev->dev.of_node,
+					"cs-gpios", i);
+
+			if (cs_gpio == -EPROBE_DEFER) {
+				ret = cs_gpio;
+				goto out;
+			}
+
+			if (gpio_is_valid(cs_gpio)) {
+				ret = devm_gpio_request(&pdev->dev, cs_gpio,
+						dev_name(&pdev->dev));
+				if (ret)
+					goto out;
+			}
+		}
+	} else if(has_acpi_companion(&pdev->dev)) {
+		int n;
+		int *cs;
+		struct gpio_desc *gpiod;
+
+		n = gpiod_count(&pdev->dev, "cs");
+
+		cs = devm_kcalloc(&pdev->dev, n, sizeof(int), GFP_KERNEL);
+		fts->cs = cs;
+
+		for (i = 0; i < n; i++) {
+			gpiod = devm_gpiod_get_index_optional(&pdev->dev, "cs", i,
+							      GPIOD_OUT_LOW);
+
+			if (IS_ERR(gpiod)) {
+				ret = PTR_ERR(gpiod);
+				goto out;
+			}
+
+			cs_gpio = desc_to_gpio(gpiod);
+			cs[i] = cs_gpio;
+		}
+	}
+
+	device_property_read_u32(&pdev->dev, "global-cs", &global_cs);
+	fts->global_cs = global_cs;
+
+	/* check is use dma transfer */
+	if ((device_property_read_string_array(&pdev->dev, "dma-names",
+					NULL, 0) > 0) &&
+		device_property_present(&pdev->dev, "dmas")) {
+		fts->dma_en = true;
+		phytium_spi_dmaops_set(fts);
+	}
+
+	ret = phytium_spi_add_host(&pdev->dev, fts);
+	if (ret)
+		goto out;
+
+	platform_set_drvdata(pdev, fts);
+	return 0;
+
+out:
+	clk_disable_unprepare(fts->clk);
+	return ret;
+}
+
+static int phytium_spi_remove(struct platform_device *pdev)
+{
+	struct phytium_spi *fts = platform_get_drvdata(pdev);
+
+	phytium_spi_remove_host(fts);
+	clk_disable_unprepare(fts->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int spi_suspend(struct device *dev)
+{
+	struct phytium_spi *fts = dev_get_drvdata(dev);
+
+	return phytium_spi_suspend_host(fts);
+}
+
+static int spi_resume(struct device *dev)
+{
+	struct phytium_spi *fts = dev_get_drvdata(dev);
+
+	return phytium_spi_resume_host(fts);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_spi_pm_ops, spi_suspend, spi_resume);
+
+static const struct of_device_id phytium_spi_of_match[] = {
+	{ .compatible = "phytium,spi", .data = (void *)0 },
+	{ /* end of table */}
+};
+MODULE_DEVICE_TABLE(of, phytium_spi_of_match);
+
+static const struct acpi_device_id phytium_spi_acpi_match[] = {
+	{"PHYT000E", 0},
+	{}
+};
+MODULE_DEVICE_TABLE(acpi, phytium_spi_acpi_match);
+
+static struct platform_driver phytium_spi_driver = {
+	.probe		= phytium_spi_probe,
+	.remove		= phytium_spi_remove,
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(phytium_spi_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_spi_acpi_match),
+		.pm = &phytium_spi_pm_ops,
+	},
+};
+module_platform_driver(phytium_spi_driver);
+
+MODULE_AUTHOR("Yiqun Zhang <zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("Platform Driver for Phytium SPI controller core");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-qspi.c b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-qspi.c
new file mode 100755
index 00000000000000..e909a8505d8646
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium-qspi.c
@@ -0,0 +1,801 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium Quad SPI controller driver.
+ *
+ * Copyright (c) 2022-2023, Phytium Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <linux/spi/spi-mem.h>
+#include <linux/mtd/spi-nor.h>
+
+
+#define QSPI_FLASH_CAP_REG		0x00
+#define  QSPI_FLASH_CAP_NUM_SHIFT	3
+#define  QSPI_FLASH_CAP_NUM_MASK	(0x3 << QSPI_FLASH_CAP_NUM_SHIFT)
+#define  QSPI_FLASH_CAP_CAP_SHIFT	0
+#define  QSPI_FLASH_CAP_CAP_MASK	(0x7 << QSPI_FLASH_CAP_CAP_SHIFT)
+
+#define QSPI_RD_CFG_REG			0x04
+#define  QSPI_RD_CFG_RD_CMD_SHIFT	24
+#define  QSPI_RD_CFG_RD_CMD_MASK	(0xff << QSPI_RD_CFG_RD_CMD_SHIFT)
+#define  QSPI_RD_CFG_RD_THROUGH_SHIFT	23
+#define  QSPI_RD_CFG_RD_THROUGH_MASK	(0x1 << QSPI_RD_CFG_RD_THROUGH_SHIFT)
+#define  QSPI_RD_CFG_RD_TRANSFER_SHIFT	20
+#define  QSPI_RD_CFG_RD_TRANSFER_MASK	(0x7 << QSPI_RD_CFG_RD_TRANSFER_SHIFT)
+#define  QSPI_RD_CFG_RD_ADDR_SEL_SHIFT	19
+#define  QSPI_RD_CFG_RD_ADDR_SEL_MASK	(0x1 << QSPI_RD_CFG_RD_ADDR_SEL_SHIFT)
+#define  QSPI_RD_CFG_RD_LATENCY_SHIFT	18
+#define  QSPI_RD_CFG_RD_LATENCY_MASK	(0x1 << QSPI_RD_CFG_RD_LATENCY_SHIFT)
+#define  QSPI_RD_CFG_MODE_BYTE_SHIFT	17
+#define  QSPI_RD_CFG_MODE_BYTE_MASK	(0x1 << QSPI_RD_CFG_MODE_BYTE_SHIFT)
+#define  QSPI_RD_CFG_CMD_SIGN_SHIFT	9
+#define  QSPI_RD_CFG_CMD_SIGN_MASK	(0xff << QSPI_RD_CFG_CMD_SIGN_SHIFT)
+#define  QSPI_RD_CFG_DUMMY_SHIFT	4
+#define  QSPI_RD_CFG_DUMMY_MASK		(0x1f << QSPI_RD_CFG_DUMMY_SHIFT)
+#define  QSPI_RD_CFG_D_BUFFER_SHIFT	3
+#define  QSPI_RD_CFG_D_BUFFER_MASK	(0x1 << QSPI_RD_CFG_D_BUFFER_SHIFT)
+#define  QSPI_RD_CFG_RD_SCK_SEL_SHIFT	0
+#define  QSPI_RD_CFG_RD_SCK_SEL_MASK	(0x7 << QSPI_RD_CFG_RD_SCK_SEL_SHIFT)
+
+#define QSPI_WR_CFG_REG			0x08
+#define  QSPI_WR_CFG_WR_CMD_SHIFT	24
+#define  QSPI_WR_CFG_WR_CMD_MASK	(0xff << QSPI_WR_CFG_WR_CMD_SHIFT)
+#define  QSPI_WR_CFG_WR_WAIT_SHIFT	9
+#define  QSPI_WR_CFG_WR_WAIT_MASK	(0x01 << QSPI_WR_CFG_WR_WAIT_SHIFT)
+#define  QSPI_WR_CFG_WR_THROUGH_SHIFT	8
+#define  QSPI_WR_CFG_WR_THROUGH_MASK	(0x01 << QSPI_WR_CFG_WR_THROUGH_SHIFT)
+#define  QSPI_WR_CFG_WR_TRANSFER_SHIFT	5
+#define  QSPI_WR_CFG_WR_TRANSFER_MASK	(0X7 << QSPI_WR_CFG_WR_TRANSFER_SHIFT)
+#define  QSPI_WR_CFG_WR_ADDR_SEL_SHIFT	4
+#define  QSPI_WR_CFG_WR_ADDR_SEL_MASK	(0x1 << QSPI_WR_CFG_WR_ADDR_SEL_SHIFT)
+#define  QSPI_WR_CFG_WR_MODE_SHIFT	3
+#define  QSPI_WR_CFG_WR_MODE_MASK	(0x1 << QSPI_WR_CFG_WR_MODE_SHIFT)
+#define  QSPI_WR_CFG_WR_SCK_SEL_SHIFT	0
+#define  QSPI_WR_CFG_WR_SCK_SEL_MASK	(0x7 << QSPI_WR_CFG_WR_SCK_SEL_SHIFT)
+
+#define QSPI_FLUSH_REG			0x0c
+#define  QSPI_FLUSH_EN			(0x1 << 0)
+
+#define QSPI_CMD_PORT_REG		0x10
+#define  QSPI_CMD_PORT_CMD_SHIFT	24
+#define  QSPI_CMD_PORT_CMD_MASK		(0xff << QSPI_CMD_PORT_CMD_SHIFT)
+#define  QSPI_CMD_PORT_WAIT_SHIFT	22
+#define  QSPI_CMD_PORT_WAIT_MASK	(0x1 << QSPI_CMD_PORT_WAIT_SHIFT)
+#define  QSPI_CMD_PORT_THROUGH_SHIFT	21
+#define  QSPI_CMD_PORT_THROUGH_MASK	(0x1 << QSPI_CMD_PORT_THROUGH_SHIFT)
+#define  QSPI_CMD_PORT_CS_SHIFT		19
+#define  QSPI_CMD_PORT_CS_MASK		(0x3 << QSPI_CMD_PORT_CS_SHIFT)
+#define  QSPI_CMD_PORT_TRANSFER_SHIFT	16
+#define  QSPI_CMD_PORT_TRANSFER_MASK	(0x7 << QSPI_CMD_PORT_TRANSFER_SHIFT)
+#define  QSPI_CMD_PORT_CMD_ADDR_SHIFT	15
+#define  QSPI_CMD_PORT_CMD_ADDR_MASK	(0x1 << QSPI_CMD_PORT_CMD_ADDR_SHIFT)
+#define  QSPI_CMD_PORT_LATENCY_SHIFT	14
+#define  QSPI_CMD_PORT_LATENCY_MASK	(0x1 << QSPI_CMD_PORT_LATENCY_SHIFT)
+#define  QSPI_CMD_PORT_DATA_XFER_SHIFT	13
+#define  QSPI_CMD_PORT_DATA_XFER_MASK	(0x1 << QSPI_CMD_PORT_DATA_XFER_SHIFT)
+#define  QSPI_CMD_PORT_ADDR_SEL_SHIFT	12
+#define  QSPI_CMD_PORT_ADDR_SEL_MASK	(0x1 << QSPI_CMD_PORT_ADDR_SEL_SHIFT)
+#define  QSPI_CMD_PORT_DUMMY_SHIFT	7
+#define  QSPI_CMD_PORT_DUMMY_MASK	(0x1f << QSPI_CMD_PORT_DUMMY_SHIFT)
+#define  QSPI_CMD_PORT_P_BUFFER_SHIFT	6
+#define  QSPI_CMD_PORT_P_BUFFER_MASK	(0x1 << QSPI_CMD_PORT_P_BUFFER_SHIFT)
+#define  QSPI_CMD_PORT_RW_NUM_SHIFT	3
+#define  QSPI_CMD_PORT_RW_NUM_MASK	(0x7 << QSPI_CMD_PORT_RW_NUM_SHIFT)
+#define  QSPI_CMD_PORT_SCK_SEL_SHIFT	0
+#define  QSPI_CMD_PORT_SCK_SEL_MASK	(0x7 << QSPI_CMD_PORT_SCK_SEL_SHIFT)
+
+#define QSPI_ADDR_PORT_REG		0x14
+#define QSPI_HD_PORT_REG		0x18
+#define QSPI_LD_PORT_REG		0x1c
+
+#define QSPI_FUN_SET_REG		0x20
+#define  QSPI_FUN_SET_HOLD_SHIFT	24
+#define  QSPI_FUN_SET_HOLD_MASK		(0xff << QSPI_FUN_SET_HOLD_SHIFT)
+#define  QSPI_FUN_SET_SETUP_SHIFT	16
+#define  QSPI_FUN_SET_SETUP_MASK	(0xff << QSPI_FUN_SET_SETUP_SHIFT)
+#define  QSPI_FUN_SET_DELAY_SHIFT	0
+#define  QSPI_FUN_SET_DELAY_MASK	(0xffff << QSPI_FUN_SET_DELAY_SHIFT)
+
+#define QSPI_WIP_REG			0x24
+#define  QSPI_WIP_W_CMD_SHIFT		24
+#define  QSPI_WIP_W_CMD_MASK		(0xff << QSPI_WIP_W_CMD_SHIFT)
+#define  QSPI_WIP_W_TRANSFER_SHIFT	3
+#define  QSPI_WIP_W_TRANSFER_MASK	(0x3 << QSPI_WIP_W_TRANSFER_SHIFT)
+#define  QSPI_WIP_W_SCK_SEL_SHIFT	0
+#define  QSPI_WIP_W_SCK_SEL_MASK	(0x7 << QSPI_WIP_W_SCK_SEL_SHIFT)
+
+#define QSPI_WP_REG			0x28
+#define  QSPI_WP_EN_SHIFT		17
+#define  QSPI_WP_EN_MASK		(0x1 << QSPI_WP_EN_SHIFT)
+#define  QSPI_WP_IO2_SHIFT		16
+#define  QSPI_WP_IO2_MASK		(0x1 << QSPI_WP_IO2_SHIFT)
+#define  QSPI_WP_HOLD_SHIFT		8
+#define  QSPI_WP_HOLD_MASK		(0xff << QSPI_WP_HOLD_SHIFT)
+#define  QSPI_WP_SETUP_SHIFT		0
+#define  QSPI_WP_SETUP_MASK		(0xff << QSPI_WP_SETUP_SHIFT)
+
+#define QSPI_MODE_REG			0x2c
+#define  QSPI_MODE_VALID_SHIFT		8
+#define  QSPI_MODE_VALID_MASK		(0xff << QSPI_MODE_VALID_SHIFT)
+#define  QSPI_MODE_SHIFT		0
+#define  QSPI_MODE_MASK			(0xff << QSPI_MODE_SHIFT)
+
+#define PHYTIUM_QSPI_MAX_NORCHIP	4
+#define PHYTIUM_QSPI_MAX_MMAP_SZ	(SZ_256M * PHYTIUM_QSPI_MAX_NORCHIP)
+#define PHYTIUM_QSPI_MAX_XFER_SZ	8
+#define PHYTIUM_QSPI_DEFAULT_SCK_SEL	5
+
+#define XFER_PROTO_1_1_1		0x0
+#define XFER_PROTO_1_1_2		0x1
+#define XFER_PROTO_1_1_4		0x2
+#define XFER_PROTO_1_2_2		0x3
+#define XFER_PROTO_1_4_4		0x4
+#define XFER_PROTO_2_2_2		0x5
+#define XFER_PROTO_4_4_4		0x6
+
+struct phytium_qspi_flash {
+	u32 cs;
+	u32 clk_div;
+
+	void __iomem *base;
+	resource_size_t size;
+	struct spi_device *spi;
+};
+
+struct phytium_qspi {
+	struct device *dev;
+	struct spi_controller *ctrl;
+
+	void __iomem *io_base;
+	void __iomem *mm_base;
+	resource_size_t mm_size;
+	resource_size_t used_size;
+
+	struct clk *clk;
+	u32 clk_rate;
+
+	struct phytium_qspi_flash flash[PHYTIUM_QSPI_MAX_NORCHIP];
+	u8 fnum;
+	bool nodirmap;
+};
+
+static bool phytium_qspi_check_buswidth(u8 width)
+{
+	switch (width) {
+	case 1:
+	case 2:
+	case 4:
+		return 0;
+	}
+
+	return -ENOTSUPP;
+}
+
+static uint phytium_spi_nor_clac_clk_div(int div)
+{
+	uint clk_div = 0;
+
+	if (div <= 2)
+		clk_div = 1;
+	else if (div <= 4)
+		clk_div = 2;
+	else if (div <= 8)
+		clk_div = 3;
+	else if (div <= 16)
+		clk_div = 4;
+	else if (div <= 32)
+		clk_div = 5;
+	else if (div <= 64)
+		clk_div = 6;
+	else if (div <= 128)
+		clk_div = 7;
+	else
+		clk_div = 65535;
+
+	return clk_div;
+}
+
+static int phytium_spi_nor_protocol_encode(const struct spi_mem_op *op, u32 *code)
+{
+	int ret = 0;
+
+	if (op->cmd.buswidth == 1 &&
+	    op->addr.buswidth == 1 &&
+	    op->data.buswidth == 1)
+		*code = XFER_PROTO_1_1_1;
+	else if (op->cmd.buswidth == 1 &&
+		 op->addr.buswidth == 1 &&
+		 op->data.buswidth == 2)
+		*code = XFER_PROTO_1_1_2;
+	else if (op->cmd.buswidth == 1 &&
+		 op->addr.buswidth == 1 &&
+		 op->data.buswidth == 4)
+		*code = XFER_PROTO_1_1_4;
+	else if (op->cmd.buswidth == 1 &&
+		 op->addr.buswidth == 2 &&
+		 op->data.buswidth == 2)
+		*code = XFER_PROTO_1_2_2;
+	else if (op->cmd.buswidth == 1 &&
+		 op->addr.buswidth == 4 &&
+		 op->data.buswidth == 4)
+		*code = XFER_PROTO_1_4_4;
+	else if (op->cmd.buswidth == 2 &&
+		 op->addr.buswidth == 2 &&
+		 op->data.buswidth == 2)
+		*code = XFER_PROTO_2_2_2;
+	else if (op->cmd.buswidth == 4 &&
+		 op->addr.buswidth == 4 &&
+		 op->data.buswidth == 4)
+		*code = XFER_PROTO_4_4_4;
+	else
+		*code = XFER_PROTO_1_1_1;
+
+	return ret;
+}
+
+static int phytium_qspi_flash_capacity_encode(u32 size, u32 *cap)
+{
+	int ret = 0;
+
+	switch (size) {
+	case SZ_4M:
+		*cap = 0x0;
+		break;
+	case SZ_8M:
+		*cap = 0x1;
+		break;
+	case SZ_16M:
+		*cap = 0x2;
+		break;
+	case SZ_32M:
+		*cap = 0x3;
+		break;
+	case SZ_64M:
+		*cap = 0x4;
+		break;
+	case SZ_128M:
+		*cap = 0x5;
+		break;
+	case SZ_256M:
+		*cap = 0x6;
+		break;
+	case SZ_512M:
+		*cap = 0x7;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int phytium_qspi_write_port(struct phytium_qspi *qspi,
+				   const u8 *buf, const size_t len)
+{
+	u32 bouncebuf[2] = { 0 };
+
+	if (len > PHYTIUM_QSPI_MAX_XFER_SZ) {
+		dev_err(qspi->dev, "WRITE data exceeds 8 bytes.\n");
+		return -EINVAL;
+	}
+
+	memcpy(bouncebuf, buf, len);
+
+	if (len > 4)
+		writel_relaxed(bouncebuf[1], qspi->io_base + QSPI_HD_PORT_REG);
+	writel_relaxed(bouncebuf[0], qspi->io_base + QSPI_LD_PORT_REG);
+
+	return 0;
+}
+
+static int phytium_qspi_read_port(struct phytium_qspi *qspi,
+				  u8 *buf, size_t len)
+{
+	u32 bouncebuf[2] = { 0 };
+
+	if (len > PHYTIUM_QSPI_MAX_XFER_SZ) {
+		dev_err(qspi->dev, "READ data exceeds 8 bytes.\n");
+		return -EINVAL;
+	}
+
+	/* Dummy write to LD_PORT register and issue READ ops*/
+	writel_relaxed(0, qspi->io_base + QSPI_LD_PORT_REG);
+
+	/* Read data */
+	bouncebuf[0] = readl_relaxed(qspi->io_base + QSPI_LD_PORT_REG);
+	if (len > 4)
+		bouncebuf[1] = readl_relaxed(qspi->io_base + QSPI_HD_PORT_REG);
+
+	memcpy(buf, bouncebuf, len);
+
+	return 0;
+}
+
+static int phytium_qspi_adjust_op_size(struct spi_mem *mem,
+					  struct spi_mem_op *op)
+{
+	if (op->data.nbytes > PHYTIUM_QSPI_MAX_XFER_SZ)
+		op->data.nbytes = PHYTIUM_QSPI_MAX_XFER_SZ;
+
+	return 0;
+}
+
+static bool phytium_qspi_supports_op(struct spi_mem *mem,
+				     const struct spi_mem_op *op)
+{
+	int ret;
+
+	ret = phytium_qspi_check_buswidth(op->cmd.buswidth);
+
+	if (op->addr.nbytes)
+		ret |= phytium_qspi_check_buswidth(op->addr.buswidth);
+
+	if (op->dummy.nbytes)
+		ret |= phytium_qspi_check_buswidth(op->dummy.buswidth);
+
+	if (op->data.nbytes)
+		ret |= phytium_qspi_check_buswidth(op->data.buswidth);
+
+	if (ret)
+		return false;
+
+	/* Max 32 dummy clock cycles supported */
+	if (op->dummy.nbytes &&
+	    (op->dummy.nbytes * 8 / op->dummy.buswidth > 32))
+		return false;
+
+	return spi_mem_default_supports_op(mem, op);
+}
+
+static int phytium_qspi_exec_op(struct spi_mem *mem,
+				const struct spi_mem_op *op)
+{
+	struct phytium_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
+	struct phytium_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
+	u32 cmd, transfer;
+	int ret;
+
+	dev_dbg(qspi->dev, "cmd:%#x mode: %d.%d.%d.%d addr:%#llx len:%#x\n",
+		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+		op->dummy.buswidth, op->data.buswidth, op->addr.val,
+		op->data.nbytes);
+
+	cmd = op->cmd.opcode << QSPI_CMD_PORT_CMD_SHIFT;
+	cmd |= flash->cs << QSPI_CMD_PORT_CS_SHIFT;
+
+	ret = phytium_spi_nor_protocol_encode(op, &transfer);
+	if (ret) {
+		dev_err(qspi->dev, "Unsupported SPI NOR protocol.\n");
+		goto out;
+	}
+	cmd |= transfer << QSPI_CMD_PORT_TRANSFER_SHIFT;
+
+	if (op->addr.nbytes) {
+		cmd |= QSPI_CMD_PORT_CMD_ADDR_MASK;
+		if (op->addr.nbytes == 4)
+			cmd |= QSPI_CMD_PORT_ADDR_SEL_MASK;
+
+		/* Write target address to ADDR_PORT register */
+		writel_relaxed(op->addr.val, qspi->io_base + QSPI_ADDR_PORT_REG);
+	}
+
+	if (op->dummy.nbytes) {
+		cmd |= QSPI_CMD_PORT_LATENCY_MASK;
+		cmd |= ((op->dummy.nbytes * 8) / op->dummy.buswidth) <<
+			QSPI_CMD_PORT_LATENCY_SHIFT;
+	}
+
+	if (op->data.nbytes) {
+		cmd |= QSPI_CMD_PORT_DATA_XFER_MASK;
+		cmd &= ~QSPI_CMD_PORT_P_BUFFER_MASK;
+		cmd |= (op->data.nbytes-1) << QSPI_CMD_PORT_RW_NUM_SHIFT;
+	}
+
+	cmd |= flash->clk_div;
+	writel_relaxed(cmd, qspi->io_base + QSPI_CMD_PORT_REG);
+
+	if (op->data.dir == SPI_MEM_DATA_IN) {
+		ret = phytium_qspi_read_port(qspi, op->data.buf.in, op->data.nbytes);
+		if (ret) {
+			dev_err(qspi->dev, "Failed to read data from the port.\n");
+			goto out;
+		}
+	} else if (op->data.dir == SPI_MEM_DATA_OUT) {
+		ret = phytium_qspi_write_port(qspi, op->data.buf.out, op->data.nbytes);
+		if (ret) {
+			dev_err(qspi->dev, "Failed to write data to the port.\n");
+			goto out;
+		}
+	} else {
+		/* Dummy write to LD_PORT register and issue the command */
+		writel_relaxed(0, qspi->io_base + QSPI_LD_PORT_REG);
+	}
+
+out:
+	return ret;
+}
+
+static int phytium_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+	struct spi_device *spi = desc->mem->spi;
+	struct phytium_qspi *qspi = spi_controller_get_devdata(spi->master);
+	struct phytium_qspi_flash *flash = &qspi->flash[spi->chip_select];
+	struct spi_nor *nor = spi_mem_get_drvdata(desc->mem);
+	u32 cmd, transfer;
+	int ret = 0;
+
+	if (!qspi->mm_base || !qspi->mm_size) {
+		ret = -EOPNOTSUPP;
+		goto out;
+	}
+
+	if (!flash->base) {
+		flash->base = qspi->mm_base + qspi->used_size;
+		qspi->used_size += nor->mtd.size;
+	}
+
+	/* Setup RD/WR_CFG register */
+	if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
+		cmd = desc->info.op_tmpl.cmd.opcode << QSPI_RD_CFG_RD_CMD_SHIFT;
+		ret = phytium_spi_nor_protocol_encode(&desc->info.op_tmpl, &transfer);
+		if (ret) {
+			dev_err(qspi->dev, "Unsupported SPI NOR protocol.\n");
+			goto out;
+		}
+		cmd |= transfer << QSPI_RD_CFG_RD_TRANSFER_SHIFT;
+
+		if (desc->info.op_tmpl.addr.nbytes == 4)
+			cmd |= QSPI_RD_CFG_RD_ADDR_SEL_MASK;
+
+		if (nor->read_dummy) {
+			cmd |= QSPI_RD_CFG_RD_LATENCY_MASK;
+			cmd |= (nor->read_dummy - 1) << QSPI_RD_CFG_DUMMY_SHIFT;
+		}
+
+		cmd |= QSPI_RD_CFG_D_BUFFER_MASK;
+		cmd |= flash->clk_div & QSPI_RD_CFG_RD_SCK_SEL_MASK;
+
+		writel_relaxed(cmd, qspi->io_base + QSPI_RD_CFG_REG);
+
+		dev_dbg(qspi->dev, "Create read dirmap and setup RD_CFG_REG [%#x].\n", cmd);
+	} else if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
+		cmd = desc->info.op_tmpl.cmd.opcode << QSPI_WR_CFG_WR_CMD_SHIFT;
+		ret = phytium_spi_nor_protocol_encode(&desc->info.op_tmpl, &transfer);
+		if (ret) {
+			dev_err(qspi->dev, "Unsupported SPI NOR protocol.\n");
+			goto out;
+		}
+		cmd |= transfer << QSPI_WR_CFG_WR_TRANSFER_SHIFT;
+
+		if (desc->info.op_tmpl.addr.nbytes == 4)
+			cmd |= QSPI_WR_CFG_WR_ADDR_SEL_MASK;
+
+		cmd |= QSPI_WR_CFG_WR_MODE_MASK;
+		cmd |= flash->clk_div & QSPI_WR_CFG_WR_SCK_SEL_MASK;
+
+		writel_relaxed(cmd, qspi->io_base + QSPI_WR_CFG_REG);
+
+		dev_dbg(qspi->dev, "Create write dirmap and setup WR_CFG_REG [%#x].\n", cmd);
+	} else {
+		ret = -EINVAL;
+	}
+
+out:
+	return ret;
+}
+
+static ssize_t phytium_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+					u64 offs, size_t len, void *buf)
+{
+	struct spi_device *spi = desc->mem->spi;
+	struct phytium_qspi *qspi = spi_controller_get_devdata(spi->master);
+	struct phytium_qspi_flash *flash = &qspi->flash[spi->chip_select];
+
+	void __iomem *src = flash->base + offs;
+	u8 *buf_rx = buf;
+
+	memcpy_fromio(buf_rx, src, len);
+
+	return len;
+}
+
+static ssize_t phytium_qspi_dirmap_write(struct spi_mem_dirmap_desc *desc,
+					 u64 offs, size_t len, const void *buf)
+{
+	struct spi_device *spi = desc->mem->spi;
+	struct phytium_qspi *qspi = spi_controller_get_devdata(spi->master);
+	struct phytium_qspi_flash *flash = &qspi->flash[spi->chip_select];
+
+	void __iomem *dst = flash->base + offs;
+	void __iomem *addr;
+	int i;
+	size_t mask = 0x03;
+	u_char tmp[4] = {0};
+
+	if (offs & 0x03) {
+		dev_err(qspi->dev, "Addr not four-byte aligned!\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < len / 4; i++)
+		writel_relaxed(*(u32 *)(buf + 4 * i), dst + 4 * i);
+
+	if (len & mask) {
+		addr =  dst + (len & ~mask);
+		memcpy(tmp, buf + (len & ~mask), len & mask);
+		writel_relaxed(*(u32 *)(tmp), addr);
+	}
+
+	//write cache data to flash
+	writel_relaxed(QSPI_FLUSH_EN, qspi->io_base + QSPI_FLUSH_REG);
+
+	return len;
+}
+
+static int phytium_qspi_setup(struct spi_device *spi)
+{
+	struct spi_controller *ctrl = spi->master;
+	struct phytium_qspi *qspi = spi_controller_get_devdata(ctrl);
+	struct phytium_qspi_flash *flash;
+	uint clk_div;
+
+	if (ctrl->busy)
+		return -EBUSY;
+
+	flash = &qspi->flash[spi->chip_select];
+
+	flash->cs = spi->chip_select;
+	flash->spi = spi;
+	if (flash->cs >= PHYTIUM_QSPI_MAX_NORCHIP) {
+		dev_err(qspi->dev, "Flash CS is out of range.\n");
+		return -EINVAL;
+	}
+	qspi->fnum++;
+
+
+	if (spi->max_speed_hz) {
+		clk_div = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz);
+		flash->clk_div = phytium_spi_nor_clac_clk_div(clk_div);
+		if (flash->clk_div == 65535) {
+			dev_err(qspi->dev, "qspi maximum frequency setting is error.\n");
+			return -EINVAL;
+		}
+	} else
+		flash->clk_div = PHYTIUM_QSPI_DEFAULT_SCK_SEL;
+
+	return 0;
+}
+
+static struct spi_controller_mem_ops phytium_qspi_mem_ops = {
+	.adjust_op_size = phytium_qspi_adjust_op_size,
+	.supports_op	= phytium_qspi_supports_op,
+	.exec_op	= phytium_qspi_exec_op,
+	.dirmap_create	= phytium_qspi_dirmap_create,
+	.dirmap_read	= phytium_qspi_dirmap_read,
+	.dirmap_write	= phytium_qspi_dirmap_write,
+};
+
+/**
+ * Direct mapping is supported only when all flashes under the controller
+ * are of the same size and the mapping address is continuous. For those
+ * cases which flashes are of different sizes, the driver offered a non-dirmap
+ * mem_ops with which read/write ops is executed through command port.
+ */
+static struct spi_controller_mem_ops phytium_qspi_mem_ops_nodirmap = {
+	.adjust_op_size = phytium_qspi_adjust_op_size,
+	.supports_op	= phytium_qspi_supports_op,
+	.exec_op	= phytium_qspi_exec_op,
+};
+
+/**
+ * phytium_qspi_probe - Probe method for the QSPI driver
+ * @pdev:	Pointer to the platform_device structure
+ *
+ * This function initializes the driver data structures and the hardware.
+ *
+ * Return:	0 on success and error value on failure
+ */
+static int phytium_qspi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct spi_controller *ctrl;
+	struct resource *res;
+	struct phytium_qspi *qspi;
+	int i, ret;
+	u32 flash_cap;
+	struct spi_mem *mem;
+	struct spi_nor *nor;
+
+	ctrl = spi_alloc_master(dev, sizeof(*qspi));
+	if (!ctrl)
+		return -ENOMEM;
+
+	ctrl->mode_bits = SPI_CPOL | SPI_CPHA |
+			  SPI_RX_DUAL | SPI_RX_QUAD |
+			  SPI_TX_DUAL | SPI_TX_QUAD;
+	ctrl->setup = phytium_qspi_setup;
+	ctrl->num_chipselect = PHYTIUM_QSPI_MAX_NORCHIP;
+	ctrl->dev.of_node = dev->of_node;
+
+	qspi = spi_controller_get_devdata(ctrl);
+	qspi->ctrl = ctrl;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
+	qspi->io_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(qspi->io_base)) {
+		ret = PTR_ERR(qspi->io_base);
+		goto probe_master_put;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
+	qspi->mm_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(qspi->mm_base)) {
+		ret = PTR_ERR(qspi->mm_base);
+		goto probe_master_put;
+	}
+
+	qspi->mm_size = resource_size(res);
+	if (qspi->mm_size > PHYTIUM_QSPI_MAX_MMAP_SZ) {
+		ret = -EINVAL;
+		goto probe_master_put;
+	}
+	qspi->used_size = 0;
+
+	qspi->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(qspi->clk)) {
+		ret = PTR_ERR(qspi->clk);
+		goto probe_master_put;
+	}
+
+	qspi->clk_rate = clk_get_rate(qspi->clk);
+	if (!qspi->clk_rate) {
+		ret = -EINVAL;
+		goto probe_master_put;
+	}
+
+	pm_runtime_enable(dev);
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(dev);
+		goto probe_master_put;
+	}
+
+	ret = clk_prepare_enable(qspi->clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable PCLK of the controller.\n");
+		goto probe_clk_failed;
+	}
+
+	qspi->nodirmap = device_property_present(dev, "no-direct-mapping");
+	ctrl->mem_ops = qspi->nodirmap ?
+			&phytium_qspi_mem_ops_nodirmap :
+			&phytium_qspi_mem_ops;
+
+	qspi->dev = dev;
+	platform_set_drvdata(pdev, qspi);
+
+	ret = devm_spi_register_controller(dev, ctrl);
+	if (ret) {
+		dev_err(dev, "failed to register SPI controller: %d\n", ret);
+		goto probe_setup_failed;
+	}
+
+	if (!qspi->nodirmap) {
+		/*
+		 * The controller supports direct mapping access only if all
+		 * flashes are of same size.
+		 */
+
+		i = 0;
+		for (i = 0; qspi->fnum > i && i < PHYTIUM_QSPI_MAX_NORCHIP; i++) {
+			if (qspi->flash[i].spi) {
+				mem = spi_get_drvdata(qspi->flash[i].spi);
+				if (mem) {
+					nor = spi_mem_get_drvdata(mem);
+					if (nor)
+						qspi->flash[i].size = nor->mtd.size;
+				}
+			}
+		}
+
+		for (i = 1; qspi->fnum > i && i < PHYTIUM_QSPI_MAX_NORCHIP; i++) {
+			if (qspi->flash[i].size != qspi->flash[0].size) {
+				dev_err(dev, "Flashes are of different sizes.\n");
+				ret = -EINVAL;
+				goto probe_setup_failed;
+			}
+		}
+
+		ret = phytium_qspi_flash_capacity_encode(qspi->flash[0].size,
+							 &flash_cap);
+		if (ret) {
+			dev_err(dev, "Flash size is invalid.\n");
+			goto probe_setup_failed;
+		}
+
+		flash_cap |= qspi->fnum << QSPI_FLASH_CAP_NUM_SHIFT;
+
+		writel_relaxed(flash_cap, qspi->io_base + QSPI_FLASH_CAP_REG);
+	}
+
+	return 0;
+
+probe_setup_failed:
+	clk_disable_unprepare(qspi->clk);
+probe_clk_failed:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+probe_master_put:
+
+	return ret;
+}
+
+/**
+ * phytium_qspi_remove - Remove method for the QSPI driver
+ * @pdev:	Pointer to the platform_device structure
+ *
+ * This function is called if a device is physically removed from the system
+ * or if the driver module is being unloaded. It free all resources allocated
+ * to the device.
+ *
+ * Return:	0 on success and error value on failure
+ */
+static int phytium_qspi_remove(struct platform_device *pdev)
+{
+	struct phytium_qspi *qspi = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(qspi->clk);
+
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static int __maybe_unused phytium_qspi_suspend(struct device *dev)
+{
+	return pm_runtime_force_suspend(dev);
+}
+
+static int __maybe_unused phytium_qspi_resume(struct device *dev)
+{
+	return pm_runtime_force_resume(dev);
+}
+
+static const struct dev_pm_ops phytium_qspi_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_qspi_suspend,
+				phytium_qspi_resume)
+};
+
+static const struct of_device_id phytium_qspi_of_match[] = {
+	{ .compatible = "phytium,qspi-nor" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_qspi_of_match);
+
+static struct platform_driver phytium_qspi_driver = {
+	.probe = phytium_qspi_probe,
+	.remove = phytium_qspi_remove,
+	.driver = {
+		.name = "phytium-qspi",
+		.of_match_table = of_match_ptr(phytium_qspi_of_match),
+		.pm = &phytium_qspi_pm_ops,
+	},
+};
+module_platform_driver(phytium_qspi_driver);
+
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium Quad SPI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/spi/spi-phytium.c b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium.c
new file mode 100644
index 00000000000000..a6f849c5cf1ae1
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium.c
@@ -0,0 +1,510 @@
+ // SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium SPI core controller driver.
+ *
+ * Copyright (c) 2019-2023 Phytium Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/highmem.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/scatterlist.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <linux/acpi.h>
+#include "spi-phytium.h"
+
+struct phytium_spi_chip {
+	u8 poll_mode;
+	u8 type;
+	void (*cs_control)(u32 command);
+};
+
+struct chip_data {
+	u8 cs;
+	u8 tmode;
+	u8 type;
+
+	u8 poll_mode;
+
+	u16 clk_div;
+	u32 speed_hz;
+	void (*cs_control)(u32 command);
+};
+
+static void phytium_spi_set_cs(struct spi_device *spi, bool enable)
+{
+	struct phytium_spi *fts = spi_master_get_devdata(spi->master);
+	struct chip_data *chip = spi_get_ctldata(spi);
+	u32 origin;
+
+	if (chip && chip->cs_control)
+		chip->cs_control(!enable);
+
+	if (!enable) {
+		phytium_writel(fts, SER, BIT(spi->chip_select));
+		if (fts->global_cs) {
+			origin = phytium_readl(fts, GCSR);
+			phytium_writel(fts, GCSR, origin | (1 << spi->chip_select));
+		}
+	} else {
+		if (fts->global_cs) {
+			origin = phytium_readl(fts, GCSR);
+			phytium_writel(fts, GCSR, origin & ~(1 << spi->chip_select));
+		}
+	}
+}
+
+static inline u32 tx_max(struct phytium_spi *fts)
+{
+	u32 tx_left, tx_room, rxtx_gap;
+
+	tx_left = (fts->tx_end - fts->tx) / fts->n_bytes;
+	tx_room = fts->fifo_len - phytium_readl(fts, TXFLR);
+
+	rxtx_gap =  ((fts->rx_end - fts->rx) - (fts->tx_end - fts->tx))
+			/ fts->n_bytes;
+
+	return min3(tx_left, tx_room, (u32) (fts->fifo_len - rxtx_gap));
+}
+
+static inline u32 rx_max(struct phytium_spi *fts)
+{
+	u32 rx_left = (fts->rx_end - fts->rx) / fts->n_bytes;
+
+	return min_t(u32, rx_left, phytium_readl(fts, RXFLR));
+}
+
+static void phytium_writer(struct phytium_spi *fts)
+{
+	u32 max = tx_max(fts);
+	u16 txw = 0;
+
+	while (max--) {
+		if (fts->tx_end - fts->len) {
+			if (fts->n_bytes == 1)
+				txw = *(u8 *)(fts->tx);
+			else
+				txw = *(u16 *)(fts->tx);
+		}
+		phytium_write_io_reg(fts, DR, txw);
+		fts->tx += fts->n_bytes;
+	}
+}
+
+static void phytium_reader(struct phytium_spi *fts)
+{
+	u32 max = rx_max(fts);
+	u16 rxw;
+
+	while (max--) {
+		rxw = phytium_read_io_reg(fts, DR);
+		if (fts->rx_end - fts->len) {
+			if (fts->n_bytes == 1)
+				*(u8 *)(fts->rx) = rxw;
+			else
+				*(u16 *)(fts->rx) = rxw;
+		}
+		fts->rx += fts->n_bytes;
+	}
+}
+
+int phytium_spi_check_status(struct phytium_spi *fts, bool raw)
+{
+	u32 irq_status;
+	int ret = 0;
+
+	if (raw)
+		irq_status = phytium_readl(fts, RISR);
+	else
+		irq_status = phytium_readl(fts, ISR);
+
+	if (irq_status & INT_RXOI) {
+		dev_err(&fts->master->dev, "RX FIFO overflow detected\n");
+		ret = -EIO;
+	}
+
+	if (irq_status & INT_RXUI) {
+		dev_err(&fts->master->dev, "RX FIFO underflow detected\n");
+		ret = -EIO;
+	}
+
+	if (irq_status & INT_TXOI) {
+		dev_err(&fts->master->dev, "TX FIFO overflow detected\n");
+		ret = -EIO;
+	}
+
+	/* Generically handle the erroneous situation */
+	if (ret) {
+		spi_reset_chip(fts);
+		if (fts->master->cur_msg)
+			fts->master->cur_msg->status = ret;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phytium_spi_check_status);
+
+static void int_error_stop(struct phytium_spi *fts, const char *msg)
+{
+	spi_reset_chip(fts);
+
+	dev_err(&fts->master->dev, "%s\n", msg);
+	fts->master->cur_msg->status = -EIO;
+	spi_finalize_current_transfer(fts->master);
+}
+
+static irqreturn_t interrupt_transfer(struct phytium_spi *fts)
+{
+	u16 irq_status = phytium_readl(fts, ISR);
+
+	if (irq_status & (INT_TXOI | INT_RXOI | INT_RXUI)) {
+		phytium_readl(fts, ICR);
+		int_error_stop(fts, "interrupt_transfer: fifo overrun/underrun");
+		return IRQ_HANDLED;
+	}
+
+	phytium_reader(fts);
+	if (fts->rx_end == fts->rx) {
+		spi_mask_intr(fts, INT_TXEI);
+		spi_finalize_current_transfer(fts->master);
+		return IRQ_HANDLED;
+	}
+	if (irq_status & INT_TXEI) {
+		spi_mask_intr(fts, INT_TXEI);
+		phytium_writer(fts);
+		spi_umask_intr(fts, INT_TXEI);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t phytium_spi_irq(int irq, void *dev_id)
+{
+	struct spi_master *master = dev_id;
+	struct phytium_spi *fts = spi_master_get_devdata(master);
+	u16 irq_status = phytium_readl(fts, ISR) & 0x3f;
+
+	if (!irq_status)
+		return IRQ_NONE;
+
+	if (!master->cur_msg) {
+		spi_mask_intr(fts, INT_TXEI);
+		return IRQ_HANDLED;
+	}
+
+	if (fts->transfer_handler)
+		return fts->transfer_handler(fts);
+	else
+		return IRQ_HANDLED;
+}
+
+static int poll_transfer(struct phytium_spi *fts)
+{
+	do {
+		phytium_writer(fts);
+		phytium_reader(fts);
+		cpu_relax();
+	} while (fts->rx_end > fts->rx);
+
+	return 0;
+}
+
+static int phytium_spi_transfer_one(struct spi_master *master,
+		struct spi_device *spi, struct spi_transfer *transfer)
+{
+	struct phytium_spi *fts = spi_master_get_devdata(master);
+	struct chip_data *chip = spi_get_ctldata(spi);
+	u8 imask = 0;
+	u16 txlevel = 0;
+	u16 clk_div;
+	u32 cr0;
+	int ret = 0;
+
+	fts->dma_mapped = 0;
+	fts->tx = (void *)transfer->tx_buf;
+	fts->tx_end = fts->tx + transfer->len;
+	fts->rx = transfer->rx_buf;
+	fts->rx_end = fts->rx + transfer->len;
+	fts->len = transfer->len;
+
+	spi_enable_chip(fts, 0);
+
+	if (transfer->speed_hz != fts->current_freq) {
+		if (transfer->speed_hz != chip->speed_hz) {
+			clk_div = (fts->max_freq / transfer->speed_hz + 1) &
+				0xfffe;
+
+			chip->speed_hz = transfer->speed_hz;
+			chip->clk_div = clk_div;
+		}
+		fts->current_freq = transfer->speed_hz;
+		spi_set_clk(fts, chip->clk_div);
+	}
+
+	if (transfer->bits_per_word == 8) {
+		fts->n_bytes = 1;
+	} else if (transfer->bits_per_word == 16) {
+		fts->n_bytes = 2;
+	} else {
+		return -EINVAL;
+	}
+
+	cr0 = (transfer->bits_per_word - 1)
+		| (chip->type << FRF_OFFSET)
+		| (spi->mode << MODE_OFFSET)
+		| (chip->tmode << TMOD_OFFSET);
+
+	if (chip->cs_control) {
+		if (fts->rx && fts->tx)
+			chip->tmode = TMOD_TR;
+		else if (fts->rx)
+			chip->tmode = TMOD_RO;
+		else
+			chip->tmode = TMOD_TO;
+
+		cr0 &= ~TMOD_MASK;
+		cr0 |= (chip->tmode << TMOD_OFFSET);
+	}
+
+	phytium_writel(fts, CTRLR0, cr0);
+
+	/* check if current transfer is a DMA transcation */
+	if (master->can_dma && master->can_dma(master, spi, transfer))
+		fts->dma_mapped = master->cur_msg_mapped;
+
+	spi_mask_intr(fts, 0xff);
+
+	/* DMA setup */
+	if (fts->dma_mapped) {
+		ret = fts->dma_ops->dma_setup(fts, transfer);
+		if (ret)
+			return ret;
+	}
+
+	/* interrupt transfer mode setup */
+	if (!chip->poll_mode && !fts->dma_mapped) {
+		txlevel = min_t(u16, fts->fifo_len / 2, fts->len / fts->n_bytes);
+		phytium_writel(fts, TXFLTR, txlevel);
+
+		imask |= INT_TXEI | INT_TXOI |
+			 INT_RXUI | INT_RXOI;
+		spi_umask_intr(fts, imask);
+
+		fts->transfer_handler = interrupt_transfer;
+	}
+
+	spi_enable_chip(fts, 1);
+
+	if (fts->dma_mapped)
+		return fts->dma_ops->dma_transfer(fts, transfer);
+
+	if (chip->poll_mode)
+		return poll_transfer(fts);
+
+	return 1;
+}
+
+static void phytium_spi_handle_err(struct spi_master *master,
+		struct spi_message *msg)
+{
+	struct phytium_spi *fts = spi_master_get_devdata(master);
+
+	if (fts->dma_mapped)
+		fts->dma_ops->dma_stop(fts);
+
+	spi_reset_chip(fts);
+}
+
+static int phytium_spi_setup(struct spi_device *spi)
+{
+	struct phytium_spi_chip *chip_info = NULL;
+	struct chip_data *chip;
+	struct spi_master *master = spi->master;
+	struct phytium_spi *fts = spi_master_get_devdata(master);
+	int ret;
+	u32 cr0;
+
+	spi_enable_chip(fts, 0);
+
+	chip = spi_get_ctldata(spi);
+	if (!chip) {
+		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
+		if (!chip)
+			return -ENOMEM;
+		spi_set_ctldata(spi, chip);
+	}
+
+	chip_info = spi->controller_data;
+
+	if (chip_info) {
+		if (chip_info->cs_control)
+			chip->cs_control = chip_info->cs_control;
+
+		chip->poll_mode = chip_info->poll_mode;
+		chip->type = chip_info->type;
+	}
+
+	chip->tmode = 0;
+
+	cr0 = (spi->bits_per_word - 1) | (chip->type << FRF_OFFSET) |
+	      (spi->mode << MODE_OFFSET) | (chip->tmode << TMOD_OFFSET);
+
+	phytium_writel(fts, CTRLR0, cr0);
+
+	if (gpio_is_valid(spi->cs_gpio)) {
+		ret = gpio_direction_output(spi->cs_gpio,
+				!(spi->mode & SPI_CS_HIGH));
+		if (ret)
+			return ret;
+	}
+
+	spi_enable_chip(fts, 1);
+
+	return 0;
+}
+
+static void phytium_spi_cleanup(struct spi_device *spi)
+{
+	struct chip_data *chip = spi_get_ctldata(spi);
+
+	kfree(chip);
+	spi_set_ctldata(spi, NULL);
+}
+
+static void spi_hw_init(struct device *dev, struct phytium_spi *fts)
+{
+	spi_reset_chip(fts);
+
+	if (!fts->fifo_len) {
+		u32 fifo;
+
+		for (fifo = 1; fifo < 256; fifo++) {
+			phytium_writel(fts, TXFLTR, fifo);
+			if (fifo != phytium_readl(fts, TXFLTR))
+				break;
+		}
+		phytium_writel(fts, TXFLTR, 0);
+
+		fts->fifo_len = (fifo == 1) ? 0 : fifo;
+		dev_dbg(dev, "Detected FIFO size: %u bytes\n", fts->fifo_len);
+	}
+}
+
+int phytium_spi_add_host(struct device *dev, struct phytium_spi *fts)
+{
+	struct spi_master *master;
+	int ret;
+
+	BUG_ON(fts == NULL);
+
+	master = spi_alloc_master(dev, 0);
+	if (!master)
+		return -ENOMEM;
+
+	fts->master = master;
+	fts->dma_addr = (dma_addr_t)(fts->paddr + DR);
+	snprintf(fts->name, sizeof(fts->name), "phytium_spi%d", fts->bus_num);
+
+	ret = request_irq(fts->irq, phytium_spi_irq, IRQF_SHARED, fts->name, master);
+	if (ret < 0) {
+		dev_err(dev, "can not get IRQ\n");
+		goto err_free_master;
+	}
+
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
+	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+	master->bus_num = fts->bus_num;
+	master->num_chipselect = fts->num_cs;
+	master->setup = phytium_spi_setup;
+	master->cleanup = phytium_spi_cleanup;
+	master->set_cs = phytium_spi_set_cs;
+	master->transfer_one = phytium_spi_transfer_one;
+	master->handle_err = phytium_spi_handle_err;
+	master->max_speed_hz = fts->max_freq;
+	master->dev.of_node = dev->of_node;
+	master->dev.fwnode = dev->fwnode;
+	master->flags = SPI_MASTER_GPIO_SS;
+	master->cs_gpios = fts->cs;
+
+	spi_hw_init(dev, fts);
+
+
+	if (fts->dma_ops && fts->dma_ops->dma_init) {
+		ret = fts->dma_ops->dma_init(dev, fts);
+		if (ret) {
+			dev_warn(dev, "DMA init failed\n");
+		} else {
+			master->can_dma = fts->dma_ops->can_dma;
+			master->flags |= SPI_CONTROLLER_MUST_TX;
+		}
+	}
+
+	spi_master_set_devdata(master, fts);
+	ret = devm_spi_register_master(dev, master);
+	if (ret) {
+		dev_err(&master->dev, "problem registering spi master\n");
+		goto err_exit;
+	}
+
+	return 0;
+
+err_exit:
+	if (fts->dma_ops && fts->dma_ops->dma_exit)
+		fts->dma_ops->dma_exit(fts);
+	spi_enable_chip(fts, 0);
+	free_irq(fts->irq, master);
+err_free_master:
+	spi_master_put(master);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phytium_spi_add_host);
+
+void phytium_spi_remove_host(struct phytium_spi *fts)
+{
+	if (fts->dma_ops && fts->dma_ops->dma_exit)
+		fts->dma_ops->dma_exit(fts);
+	spi_shutdown_chip(fts);
+
+	free_irq(fts->irq, fts->master);
+}
+EXPORT_SYMBOL_GPL(phytium_spi_remove_host);
+
+int phytium_spi_suspend_host(struct phytium_spi *fts)
+{
+	int ret;
+
+	ret = spi_controller_suspend(fts->master);
+	if (ret)
+		return ret;
+
+	spi_shutdown_chip(fts);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_spi_suspend_host);
+
+int phytium_spi_resume_host(struct phytium_spi *fts)
+{
+	int ret;
+
+	spi_hw_init(&fts->master->dev, fts);
+	ret = spi_controller_resume(fts->master);
+	if (ret)
+		dev_err(&fts->master->dev, "fail to start queue (%d)\n", ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phytium_spi_resume_host);
+
+MODULE_AUTHOR("Zhu Mingshuai <zhumingshuai@phytium.com.cn>");
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Driver for Phytium SPI controller core");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/drivers/spi/spi-phytium.h b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium.h
new file mode 100644
index 00000000000000..003b08f8c5068c
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/spi/spi-phytium.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef PHYTIUM_SPI_HEADER_H
+#define PHYTIUM_SPI_HEADER_H
+
+#include <linux/io.h>
+#include <linux/scatterlist.h>
+#include <linux/gpio.h>
+
+#define CTRLR0			0x00
+#define SSIENR			0x08
+#define SER				0x10
+#define BAUDR			0x14
+#define TXFLTR			0x18
+#define TXFLR			0x20
+#define RXFLR			0x24
+#define SR				0x28
+#define IMR				0x2c
+#define ISR				0x30
+#define RISR			0x34
+#define ICR				0x48
+#define DMACR			0x4C
+#define DMATDLR			0x50
+#define DMARDLR			0x54
+#define DR				0x60
+#define GCSR			0x100
+
+#define FRF_OFFSET		4
+#define MODE_OFFSET		6
+#define TMOD_OFFSET		8
+
+#define TMOD_MASK		(0x3 << TMOD_OFFSET)
+#define	TMOD_TR			0x0
+#define TMOD_TO			0x1
+#define TMOD_RO			0x2
+
+#define INT_TXEI		(1 << 0)
+#define INT_TXOI		(1 << 1)
+#define INT_RXUI		(1 << 2)
+#define INT_RXOI		(1 << 3)
+
+/* Bit fields in SR, 7 bits */
+#define SR_MASK				0x7f		/* cover 7 bits */
+#define SR_BUSY				(1 << 0)
+#define SR_TF_NOT_FULL		(1 << 1)
+#define SR_TF_EMPT			(1 << 2)
+#define SR_RF_NOT_EMPT		(1 << 3)
+#define SR_RF_FULL			(1 << 4)
+#define SR_TX_ERR			(1 << 5)
+#define SR_DCOL				(1 << 6)
+
+/* Bit fields in DMACR */
+#define SPI_DMA_RDMAE		(1 << 0)
+#define SPI_DMA_TDMAE		(1 << 1)
+
+#define SPI_WAIT_RETRIES	5
+
+struct phytium_spi;
+
+struct phytium_spi_dma_ops {
+	int (*dma_init)(struct device *dev, struct phytium_spi *fts);
+	void (*dma_exit)(struct phytium_spi *fts);
+	int (*dma_setup)(struct phytium_spi *fts, struct spi_transfer *xfer);
+	bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
+			struct spi_transfer *xfer);
+	int (*dma_transfer)(struct phytium_spi *fts, struct spi_transfer *xfer);
+	void (*dma_stop)(struct phytium_spi *fts);
+};
+
+struct phytium_spi {
+	struct spi_master	*master;
+	char			name[16];
+
+	void __iomem		*regs;
+	bool			global_cs;
+	bool dma_en;
+	unsigned long		paddr;
+	int			irq;
+	u32			fifo_len;
+	u32			max_freq;
+
+	u32			reg_io_width;
+	u16			bus_num;
+	u16			num_cs;
+	int			*cs;
+
+	size_t			len;
+	void			*tx;
+	void			*tx_end;
+	void			*rx;
+	void			*rx_end;
+	u8				n_bytes;
+	int				dma_mapped;
+	struct clk		*clk;
+	irqreturn_t		(*transfer_handler)(struct phytium_spi *fts);
+	u32				current_freq; /* frequency in hz */
+
+	/* DMA info */
+	struct dma_chan		*txchan;
+	u32			txburst;
+	struct dma_chan		*rxchan;
+	u32			rxburst;
+	u32			dma_sg_burst;
+	unsigned long	dma_chan_busy;
+	dma_addr_t		dma_addr; /* phy address of the Data register */
+	const struct phytium_spi_dma_ops *dma_ops;
+	struct completion	dma_completion;
+};
+
+static inline u32 phytium_readl(struct phytium_spi *fts, u32 offset)
+{
+	return __raw_readl(fts->regs + offset);
+}
+
+static inline u16 phytium_readw(struct phytium_spi *fts, u32 offset)
+{
+	return __raw_readw(fts->regs + offset);
+}
+
+static inline void phytium_writel(struct phytium_spi *fts, u32 offset, u32 val)
+{
+	__raw_writel(val, fts->regs + offset);
+}
+
+static inline void phytium_writew(struct phytium_spi *fts, u32 offset, u16 val)
+{
+	__raw_writew(val, fts->regs + offset);
+}
+
+static inline u32 phytium_read_io_reg(struct phytium_spi *fts, u32 offset)
+{
+	switch (fts->reg_io_width) {
+	case 2:
+		return phytium_readw(fts, offset);
+	case 4:
+	default:
+		return phytium_readl(fts, offset);
+	}
+}
+
+static inline void phytium_write_io_reg(struct phytium_spi *fts, u32 offset, u32 val)
+{
+	switch (fts->reg_io_width) {
+	case 2:
+		phytium_writew(fts, offset, val);
+		break;
+	case 4:
+	default:
+		phytium_writel(fts, offset, val);
+		break;
+	}
+}
+
+static inline void spi_enable_chip(struct phytium_spi *fts, int enable)
+{
+	phytium_writel(fts, SSIENR, (enable ? 1 : 0));
+}
+
+static inline void spi_set_clk(struct phytium_spi *fts, u16 div)
+{
+	phytium_writel(fts, BAUDR, div);
+}
+
+static inline void spi_mask_intr(struct phytium_spi *fts, u32 mask)
+{
+	u32 new_mask;
+
+	new_mask = phytium_readl(fts, IMR) & ~mask;
+	phytium_writel(fts, IMR, new_mask);
+}
+
+static inline void spi_umask_intr(struct phytium_spi *fts, u32 mask)
+{
+	u32 new_mask;
+
+	new_mask = phytium_readl(fts, IMR) | mask;
+	phytium_writel(fts, IMR, new_mask);
+}
+
+static inline void spi_global_cs(struct phytium_spi *fts)
+{
+	u32 global_cs_en, mask, setmask;
+
+	mask = GENMASK(fts->num_cs-1, 0) << fts->num_cs;
+	setmask = ~GENMASK(fts->num_cs-1, 0);
+	global_cs_en = (phytium_readl(fts, GCSR) | mask) & setmask;
+
+	phytium_writel(fts, GCSR, global_cs_en);
+}
+
+static inline void spi_reset_chip(struct phytium_spi *fts)
+{
+	spi_enable_chip(fts, 0);
+	if (fts->global_cs)
+		spi_global_cs(fts);
+	spi_mask_intr(fts, 0xff);
+	spi_enable_chip(fts, 1);
+}
+
+static inline void spi_shutdown_chip(struct phytium_spi *fts)
+{
+	spi_enable_chip(fts, 0);
+	spi_set_clk(fts, 0);
+	fts->current_freq = 0;
+}
+
+extern int phytium_spi_add_host(struct device *dev, struct phytium_spi *fts);
+extern void phytium_spi_remove_host(struct phytium_spi *fts);
+extern int phytium_spi_suspend_host(struct phytium_spi *fts);
+extern int phytium_spi_resume_host(struct phytium_spi *fts);
+extern void phytium_spi_dmaops_set(struct phytium_spi *fts);
+extern int phytium_spi_check_status(struct phytium_spi *fts, bool raw);
+
+#endif /* PHYTIUM_SPI_HEADER_H */
diff --git a/target/linux/phytium/files-5.10/drivers/tty/serial/phytium-uart.c b/target/linux/phytium/files-5.10/drivers/tty/serial/phytium-uart.c
new file mode 100644
index 00000000000000..084bf9e1f964d7
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/tty/serial/phytium-uart.c
@@ -0,0 +1,922 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Phytium PCI UART controller
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+#define DRV_NAME		"phytium_uart"
+
+#define REG_DR			0x00
+#define REG_FR			0x18
+#define REG_IBRD		0x24
+#define REG_FBRD		0x28
+#define REG_LCRH_RX		0x2c
+#define REG_LCRH_TX		0x2c
+#define REG_CR			0x30
+#define REG_IFLS		0x34
+#define REG_IMSC		0x38
+#define REG_RIS			0x3c
+#define REG_MIS			0x40
+#define REG_ICR			0x44
+
+#define REG_DR_OE		(1 << 11)
+#define REG_DR_BE		(1 << 10)
+#define REG_DR_PE		(1 << 9)
+#define REG_DR_FE		(1 << 8)
+
+#define REG_LCRH_SPS		0x80
+#define REG_LCRH_WLEN_8		0x60
+#define REG_LCRH_WLEN_7		0x40
+#define REG_LCRH_WLEN_6		0x20
+#define REG_LCRH_WLEN_5		0x00
+#define REG_LCRH_FEN		0x10
+#define REG_LCRH_STP2		0x08
+#define REG_LCRH_EPS		0x04
+#define REG_LCRH_PEN		0x02
+#define REG_LCRH_BRK		0x01
+
+#define REG_FR_RI		0x100
+#define REG_FR_TXFE		0x080
+#define REG_FR_RXFF		0x040
+#define REG_FR_TXFF		0x020
+#define REG_FR_RXFE		0x010
+#define REG_FR_BUSY		0x008
+#define REG_FR_DCD		0x004
+#define REG_FR_DSR		0x002
+#define REG_FR_CTS		0x001
+#define REG_FR_TMSK		(REG_FR_TXFF + REG_FR_BUSY)
+
+#define REG_CR_CTSEN		0x8000		/* CTS hardware flow control */
+#define REG_CR_RTSEN		0x4000		/* RTS hardware flow control */
+#define REG_CR_OUT2		0x2000		/* OUT2 */
+#define REG_CR_OUT1		0x1000		/* OUT1 */
+#define REG_CR_RTS		0x0800		/* RTS */
+#define REG_CR_DTR		0x0400		/* DTR */
+#define REG_CR_RXE		0x0200		/* receive enable */
+#define REG_CR_TXE		0x0100		/* transmit enable */
+#define REG_CR_LBE		0x0080		/* loopback enable */
+#define REG_CR_RTIE		0x0040
+#define REG_CR_TIE		0x0020
+#define REG_CR_RIE		0x0010
+#define REG_CR_MSIE		0x0008
+#define REG_CR_IIRLP		0x0004		/* SIR low power mode */
+#define REG_CR_SIREN		0x0002		/* SIR enable */
+#define REG_CR_UARTEN		0x0001		/* UART enable */
+
+#define REG_IFLS_RX1_8		(0 << 3)
+#define REG_IFLS_RX2_8		(1 << 3)
+#define REG_IFLS_RX4_8		(2 << 3)
+#define REG_IFLS_RX6_8		(3 << 3)
+#define REG_IFLS_RX7_8		(4 << 3)
+#define REG_IFLS_TX1_8		(0 << 0)
+#define REG_IFLS_TX2_8		(1 << 0)
+#define REG_IFLS_TX4_8		(2 << 0)
+#define REG_IFLS_TX6_8		(3 << 0)
+
+#define REG_IMSC_OEIM		(1 << 10)	/* overrun error interrupt mask */
+#define REG_IMSC_BEIM		(1 << 9)	/* break error interrupt mask */
+#define REG_IMSC_PEIM		(1 << 8)	/* parity error interrupt mask */
+#define REG_IMSC_FEIM		(1 << 7)	/* framing error interrupt mask */
+#define REG_IMSC_RTIM		(1 << 6)	/* receive timeout interrupt mask */
+#define REG_IMSC_TXIM		(1 << 5)	/* transmit interrupt mask */
+#define REG_IMSC_RXIM		(1 << 4)	/* receive interrupt mask */
+#define REG_IMSC_DSRMIM		(1 << 3)	/* DSR interrupt mask */
+#define REG_IMSC_DCDMIM		(1 << 2)	/* DCD interrupt mask */
+#define REG_IMSC_CTSMIM		(1 << 1)	/* CTS interrupt mask */
+#define REG_IMSC_RIMIM		(1 << 0)	/* RI interrupt mask */
+
+#define REG_ICR_OEIS		(1 << 10)	/* overrun error interrupt status */
+#define REG_ICR_BEIS		(1 << 9)	/* break error interrupt status */
+#define REG_ICR_PEIS		(1 << 8)	/* parity error interrupt status */
+#define REG_ICR_FEIS		(1 << 7)	/* framing error interrupt status */
+#define REG_ICR_RTIS		(1 << 6)	/* receive timeout interrupt status */
+#define REG_ICR_TXIS		(1 << 5)	/* transmit interrupt status */
+#define REG_ICR_RXIS		(1 << 4)	/* receive interrupt status */
+#define REG_ICR_DSRMIS		(1 << 3)	/* DSR interrupt status */
+#define REG_ICR_DCDMIS		(1 << 2)	/* DCD interrupt status */
+#define REG_ICR_CTSMIS		(1 << 1)	/* CTS interrupt status */
+#define REG_ICR_RIMIS		(1 << 0)	/* RI interrupt status */
+
+#define UART_NR			12
+
+#define UART_DR_ERROR		(REG_DR_OE|REG_DR_BE|REG_DR_PE|REG_DR_FE)
+#define UART_DUMMY_DR_RX	(1 << 16)
+
+#define DEFAULT_UARTCLK		48000000	/* 48 MHz */
+
+/*
+ * We wrap our port structure around the generic uart_port.
+ */
+struct phytium_uart_port {
+	struct uart_port	port;
+	unsigned int		im;		/* interrupt mask */
+	unsigned int		old_status;
+	unsigned int		old_cr;		/* state during shutdown */
+	char			type[12];
+};
+
+static unsigned int phytium_uart_read(const struct phytium_uart_port *pup,
+	unsigned int reg)
+{
+	void __iomem *addr = pup->port.membase + reg;
+
+	return readl_relaxed(addr);
+}
+
+static void phytium_uart_write(unsigned int val, const struct phytium_uart_port *pup,
+	unsigned int reg)
+{
+	void __iomem *addr = pup->port.membase + reg;
+
+	writel_relaxed(val, addr);
+}
+
+static int phytium_fifo_to_tty(struct phytium_uart_port *pup)
+{
+	u16 status;
+	unsigned int ch, flag, fifotaken;
+
+	for (fifotaken = 0; fifotaken < 256; fifotaken++) {
+		status = phytium_uart_read(pup, REG_FR);
+		if (status & REG_FR_RXFE)
+			break;
+
+		/* Take chars from the FIFO and update status */
+		ch = phytium_uart_read(pup, REG_DR) | UART_DUMMY_DR_RX;
+		flag = TTY_NORMAL;
+		pup->port.icount.rx++;
+
+		if (unlikely(ch & UART_DR_ERROR)) {
+			if (ch & REG_DR_BE) {
+				ch &= ~(REG_DR_FE | REG_DR_PE);
+				pup->port.icount.brk++;
+				if (uart_handle_break(&pup->port))
+					continue;
+			} else if (ch & REG_DR_PE)
+				pup->port.icount.parity++;
+			else if (ch & REG_DR_FE)
+				pup->port.icount.frame++;
+			if (ch & REG_DR_OE)
+				pup->port.icount.overrun++;
+
+			ch &= pup->port.read_status_mask;
+
+			if (ch & REG_DR_BE)
+				flag = TTY_BREAK;
+			else if (ch & REG_DR_PE)
+				flag = TTY_PARITY;
+			else if (ch & REG_DR_FE)
+				flag = TTY_FRAME;
+		}
+
+		if (uart_handle_sysrq_char(&pup->port, ch & 255))
+			continue;
+
+		uart_insert_char(&pup->port, ch, REG_DR_OE, ch, flag);
+	}
+
+	return fifotaken;
+}
+
+static void phytium_rx_chars(struct phytium_uart_port *pup)
+__releases(&pup->port.lock)
+__acquires(&pup->port.lock)
+{
+	phytium_fifo_to_tty(pup);
+
+	spin_unlock(&pup->port.lock);
+	tty_flip_buffer_push(&pup->port.state->port);
+	spin_lock(&pup->port.lock);
+}
+
+static void phytium_stop_tx(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+	    container_of(port, struct phytium_uart_port, port);
+
+	pup->im &= ~REG_IMSC_TXIM;
+	phytium_uart_write(pup->im, pup, REG_IMSC);
+}
+
+static bool phytium_tx_char(struct phytium_uart_port *pup, unsigned char c,
+			    bool from_irq)
+{
+
+	if (unlikely(!from_irq) &&
+	    phytium_uart_read(pup, REG_FR) & REG_FR_TXFF)
+		return false; /* unable to transmit character */
+
+	phytium_uart_write(c, pup, REG_DR);
+	pup->port.icount.tx++;
+
+	return true;
+}
+
+static bool phytium_tx_chars(struct phytium_uart_port *pup, bool from_irq)
+{
+	struct circ_buf *xmit = &pup->port.state->xmit;
+	int count = pup->port.fifosize >> 1;
+
+	if (pup->port.x_char) {
+		if (!phytium_tx_char(pup, pup->port.x_char, from_irq))
+			return true;
+		pup->port.x_char = 0;
+		--count;
+	}
+	if (uart_circ_empty(xmit) || uart_tx_stopped(&pup->port)) {
+		phytium_stop_tx(&pup->port);
+		return false;
+	}
+
+	do {
+		if (likely(from_irq) && count-- == 0)
+			break;
+
+		if (!phytium_tx_char(pup, xmit->buf[xmit->tail], from_irq))
+			break;
+
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+	} while (!uart_circ_empty(xmit));
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&pup->port);
+
+	if (uart_circ_empty(xmit)) {
+		phytium_stop_tx(&pup->port);
+		return false;
+	}
+	return true;
+}
+
+static void phytium_modem_status(struct phytium_uart_port *pup)
+{
+	unsigned int status, delta;
+
+	status = phytium_uart_read(pup, REG_FR) & (REG_FR_DCD|REG_FR_DSR|REG_FR_CTS);
+
+	delta = status ^ pup->old_status;
+	pup->old_status = status;
+
+	if (!delta)
+		return;
+
+	if (delta & REG_FR_DCD)
+		uart_handle_dcd_change(&pup->port, status & REG_FR_DCD);
+
+	if (delta & REG_FR_DSR)
+		pup->port.icount.dsr++;
+
+	if (delta & REG_FR_CTS)
+		uart_handle_cts_change(&pup->port, status & REG_FR_CTS);
+
+	wake_up_interruptible(&pup->port.state->port.delta_msr_wait);
+}
+
+static irqreturn_t phytium_uart_interrupt(int irq, void *dev_id)
+{
+	struct phytium_uart_port *pup = dev_id;
+	unsigned long flags;
+	unsigned int status, pass_counter = 256;
+	int handled = 0;
+
+	spin_lock_irqsave(&pup->port.lock, flags);
+	status = phytium_uart_read(pup, REG_RIS) & pup->im;
+	if (status) {
+		do {
+			phytium_uart_write(status & ~(REG_ICR_TXIS|REG_ICR_RTIS|REG_ICR_RXIS),
+					   pup, REG_ICR);
+
+			if (status & (REG_ICR_RTIS|REG_ICR_RXIS))
+				phytium_rx_chars(pup);
+
+			if (status & (REG_ICR_DSRMIS|REG_ICR_DCDMIS|
+				      REG_ICR_CTSMIS|REG_ICR_RIMIS))
+				phytium_modem_status(pup);
+			if (status & REG_ICR_TXIS)
+				phytium_tx_chars(pup, true);
+
+			if (pass_counter-- == 0)
+				break;
+
+			status = phytium_uart_read(pup, REG_RIS) & pup->im;
+		} while (status != 0);
+		handled = 1;
+	}
+	spin_unlock_irqrestore(&pup->port.lock, flags);
+
+	return IRQ_RETVAL(handled);
+}
+
+static unsigned int phytium_tx_empty(struct uart_port *port)
+{
+	unsigned int status;
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+
+	status = phytium_uart_read(pup, REG_FR) & (REG_FR_BUSY | REG_FR_TXFF);
+
+	return status ? 0 : TIOCSER_TEMT;
+}
+
+static void phytium_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+	unsigned int cr;
+
+	cr = phytium_uart_read(pup, REG_CR);
+
+#define TIOCMBIT(tiocmbit, uartbit)	\
+	do {				\
+		if (mctrl & tiocmbit)	\
+			cr |= uartbit;	\
+		else			\
+			cr &= ~uartbit;	\
+	} while (0)
+
+	TIOCMBIT(TIOCM_RTS, REG_CR_RTS);
+	TIOCMBIT(TIOCM_DTR, REG_CR_DTR);
+	TIOCMBIT(TIOCM_OUT1, REG_CR_OUT1);
+	TIOCMBIT(TIOCM_OUT2, REG_CR_OUT2);
+	TIOCMBIT(TIOCM_LOOP, REG_CR_LBE);
+
+	if (port->status & UPSTAT_AUTORTS) {
+		/* We need to disable auto-RTS if we want to turn RTS off */
+		TIOCMBIT(TIOCM_RTS, REG_CR_RTSEN);
+	}
+#undef TIOCMBIT
+
+	phytium_uart_write(cr, pup, REG_CR);
+}
+
+static unsigned int phytium_get_mctrl(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+	    container_of(port, struct phytium_uart_port, port);
+	unsigned int cr = 0;
+	unsigned int status = phytium_uart_read(pup, REG_FR);
+
+#define TIOCMBIT(uartbit, tiocmbit)	\
+	do {				\
+		if (status & uartbit)	\
+			cr |= tiocmbit;	\
+	} while (0)
+
+	TIOCMBIT(REG_FR_DCD, TIOCM_CAR);
+	TIOCMBIT(REG_FR_DSR, TIOCM_DSR);
+	TIOCMBIT(REG_FR_CTS, TIOCM_CTS);
+	TIOCMBIT(REG_FR_RI, TIOCM_RNG);
+#undef TIOCMBIT
+	return cr;
+}
+
+static void phytium_start_tx(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+
+	if (phytium_tx_chars(pup, false)) {
+		pup->im |= REG_IMSC_TXIM;
+		phytium_uart_write(pup->im, pup, REG_IMSC);
+	}
+}
+
+static void phytium_stop_rx(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+
+	pup->im &= ~(REG_IMSC_RXIM|REG_IMSC_RTIM|REG_IMSC_FEIM|
+		      REG_IMSC_PEIM|REG_IMSC_BEIM|REG_IMSC_OEIM);
+	phytium_uart_write(pup->im, pup, REG_IMSC);
+}
+
+static void phytium_enable_ms(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+
+	pup->im |= REG_IMSC_RIMIM|REG_IMSC_CTSMIM|REG_IMSC_DCDMIM|REG_IMSC_DSRMIM;
+	phytium_uart_write(pup->im, pup, REG_IMSC);
+}
+
+static void phytium_break_ctl(struct uart_port *port, int break_state)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+	unsigned long flags;
+	unsigned int lcr_h;
+
+	spin_lock_irqsave(&pup->port.lock, flags);
+	lcr_h = phytium_uart_read(pup, REG_LCRH_TX);
+	if (break_state == -1)
+		lcr_h |= REG_LCRH_BRK;
+	else
+		lcr_h &= ~REG_LCRH_BRK;
+	phytium_uart_write(lcr_h, pup, REG_LCRH_TX);
+	spin_unlock_irqrestore(&pup->port.lock, flags);
+}
+
+static int phytium_hwinit(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+
+	/* XXX: more configurable setup method in future */
+	pup->port.uartclk = DEFAULT_UARTCLK;
+
+	/* Clear pending error and receive interrupts */
+	phytium_uart_write(REG_ICR_OEIS | REG_ICR_BEIS | REG_ICR_PEIS |
+			   REG_ICR_FEIS | REG_ICR_RTIS | REG_ICR_RXIS,
+			   pup,  REG_ICR);
+
+	/*
+	 * Save interrupts enable mask, and enable RX interrupts in case if
+	 * the interrupt is used for NMI entry.
+	 */
+	pup->im = phytium_uart_read(pup, REG_IMSC);
+	phytium_uart_write(REG_IMSC_RTIM | REG_IMSC_RXIM, pup, REG_IMSC);
+
+	return 0;
+}
+
+static int phytium_uart_allocate_irq(struct phytium_uart_port *pup)
+{
+	phytium_uart_write(pup->im, pup, REG_IMSC);
+
+	return request_irq(pup->port.irq, phytium_uart_interrupt, IRQF_SHARED, DRV_NAME, pup);
+}
+
+static void phytium_enable_interrtups(struct phytium_uart_port *pup)
+{
+	unsigned int i;
+
+	spin_lock_irq(&pup->port.lock);
+
+	/* Clear out any spuriously appearing RX interrupts */
+	phytium_uart_write(REG_ICR_RTIS | REG_ICR_RXIS, pup, REG_ICR);
+
+	/*
+	 * RXIS is asserted only when the RX FIFO transitions from below
+	 * to above the trigger threshold. If the RX FIFO is already
+	 * full to the threashold this can't happen and RXIS will now be
+	 * stuck off. Drain the RX FIFO explicitly to fix this:
+	 */
+	for (i = 0; i < pup->port.fifosize * 2; i++) {
+		if (phytium_uart_read(pup, REG_FR) & REG_FR_RXFE)
+			break;
+
+		phytium_uart_read(pup, REG_DR);
+	}
+
+	pup->im = REG_IMSC_RTIM | REG_IMSC_RXIM;
+	phytium_uart_write(pup->im, pup, REG_IMSC);
+	spin_unlock_irq(&pup->port.lock);
+}
+
+static int phytium_startup(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+	unsigned int cr;
+	int ret = 0;
+
+	ret = phytium_hwinit(port);
+	if (ret)
+		goto out;
+
+	ret = phytium_uart_allocate_irq(pup);
+	if (ret)
+		goto out;
+
+	phytium_uart_write(REG_IFLS_RX4_8|REG_IFLS_TX4_8, pup, REG_IFLS);
+
+	spin_lock_irq(&pup->port.lock);
+
+	/* restore RTS and DTR */
+	cr = pup->old_cr & (REG_CR_RTS | REG_CR_DTR);
+	cr |= REG_CR_UARTEN | REG_CR_RXE | REG_CR_TXE;
+	phytium_uart_write(cr, pup, REG_CR);
+
+	spin_unlock_irq(&pup->port.lock);
+
+	/* initialise the old status of the modem signals */
+	pup->old_status = phytium_uart_read(pup, REG_FR) & (REG_FR_DCD|REG_FR_DSR|REG_FR_CTS);
+
+	phytium_enable_interrtups(pup);
+
+out:
+	return ret;
+}
+
+static void phytium_shutdown_channel(struct phytium_uart_port *pup,
+				     unsigned int lcrh)
+{
+	unsigned long val;
+
+	val = phytium_uart_read(pup, lcrh);
+	val &= ~(REG_LCRH_BRK | REG_LCRH_FEN);
+	phytium_uart_write(val, pup, lcrh);
+}
+
+static void phytium_disable_uart(struct phytium_uart_port *pup)
+{
+	unsigned int cr;
+
+	pup->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
+	spin_lock_irq(&pup->port.lock);
+	cr = phytium_uart_read(pup, REG_CR);
+	pup->old_cr = cr;
+	cr &= REG_CR_RTS | REG_CR_DTR;
+	cr |= REG_CR_UARTEN | REG_CR_TXE;
+	phytium_uart_write(cr, pup, REG_CR);
+	spin_unlock_irq(&pup->port.lock);
+
+	/*
+	 * disable break condition and fifos
+	 */
+	phytium_shutdown_channel(pup, REG_LCRH_RX);
+}
+
+static void phytium_disable_interrupts(struct phytium_uart_port *pup)
+{
+	spin_lock_irq(&pup->port.lock);
+
+	/* mask all interrupts and clear all pending ones */
+	pup->im = 0;
+	phytium_uart_write(pup->im, pup, REG_IMSC);
+	phytium_uart_write(0xffff, pup, REG_ICR);
+
+	spin_unlock_irq(&pup->port.lock);
+}
+
+static void phytium_shutdown(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+
+	phytium_disable_interrupts(pup);
+
+	free_irq(pup->port.irq, pup);
+
+	phytium_disable_uart(pup);
+
+	if (pup->port.ops->flush_buffer)
+		pup->port.ops->flush_buffer(port);
+}
+
+static void
+phytium_setup_status_masks(struct uart_port *port, struct ktermios *termios)
+{
+	port->read_status_mask = REG_DR_OE | 255;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= REG_DR_FE | REG_DR_PE;
+	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
+		port->read_status_mask |= REG_DR_BE;
+
+	/*
+	 * Characters to ignore
+	 */
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= REG_DR_FE | REG_DR_PE;
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= REG_DR_BE;
+		/*
+		 * If we're ignoring parity and break indicators,
+		 * ignore overruns too (for real raw support).
+		 */
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= REG_DR_OE;
+	}
+
+	/*
+	 * Ignore all characters if CREAD is not set.
+	 */
+	if ((termios->c_cflag & CREAD) == 0)
+		port->ignore_status_mask |= UART_DUMMY_DR_RX;
+}
+
+static void
+phytium_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+	unsigned int lcr_h, old_cr;
+	unsigned long flags;
+	unsigned int baud, quot;
+
+	/* Ask the core to calculate the divisor for us. */
+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+
+	if (baud > port->uartclk/16)
+		quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
+	else
+		quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lcr_h = REG_LCRH_WLEN_5;
+		break;
+	case CS6:
+		lcr_h = REG_LCRH_WLEN_6;
+		break;
+	case CS7:
+		lcr_h = REG_LCRH_WLEN_7;
+		break;
+	default: /* CS8 */
+		lcr_h = REG_LCRH_WLEN_8;
+		break;
+	}
+	if (termios->c_cflag & CSTOPB)
+		lcr_h |= REG_LCRH_STP2;
+	if (termios->c_cflag & PARENB) {
+		lcr_h |= REG_LCRH_PEN;
+		if (!(termios->c_cflag & PARODD))
+			lcr_h |= REG_LCRH_EPS;
+		if (termios->c_cflag & CMSPAR)
+			lcr_h |= REG_LCRH_SPS;
+	}
+	if (pup->port.fifosize > 1)
+		lcr_h |= REG_LCRH_FEN;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	phytium_setup_status_masks(port, termios);
+
+	if (UART_ENABLE_MS(port, termios->c_cflag))
+		phytium_enable_ms(port);
+
+	/* first, disable everything */
+	old_cr = phytium_uart_read(pup, REG_CR);
+	phytium_uart_write(0, pup, REG_CR);
+
+	if (termios->c_cflag & CRTSCTS) {
+		if (old_cr & REG_CR_RTS)
+			old_cr |= REG_CR_RTSEN;
+
+		old_cr |= REG_CR_CTSEN;
+		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
+	} else {
+		old_cr &= ~(REG_CR_CTSEN | REG_CR_RTSEN);
+		port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
+	}
+
+	/* Set baud rate */
+	phytium_uart_write(quot & 0x3f, pup, REG_FBRD);
+	phytium_uart_write(quot >> 6, pup, REG_IBRD);
+
+	phytium_uart_write(lcr_h, pup, REG_LCRH_RX);
+	phytium_uart_write(old_cr, pup, REG_CR);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *phytium_type(struct uart_port *port)
+{
+	struct phytium_uart_port *pup =
+		container_of(port, struct phytium_uart_port, port);
+	return pup->port.type == PORT_PHYTIUM ? pup->type : NULL;
+}
+
+static void phytium_release_port(struct uart_port *port)
+{
+	/* Nothing to release ... */
+}
+
+static int phytium_request_port(struct uart_port *port)
+{
+	/* UARTs always present */
+	return 0;
+}
+
+static void phytium_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_PHYTIUM;
+		phytium_request_port(port);
+	}
+}
+
+static int phytium_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	int ret = 0;
+
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_PHYTIUM)
+		ret = -EINVAL;
+	if (ser->irq < 0 || ser->irq >= nr_irqs)
+		ret = -EINVAL;
+	if (ser->baud_base < 9600)
+		ret = -EINVAL;
+
+	return ret;
+}
+
+static const struct uart_ops phytium_uart_ops = {
+	.tx_empty	= phytium_tx_empty,
+	.set_mctrl	= phytium_set_mctrl,
+	.get_mctrl	= phytium_get_mctrl,
+	.stop_tx	= phytium_stop_tx,
+	.start_tx	= phytium_start_tx,
+	.stop_rx	= phytium_stop_rx,
+	.enable_ms	= phytium_enable_ms,
+	.break_ctl	= phytium_break_ctl,
+	.startup	= phytium_startup,
+	.shutdown	= phytium_shutdown,
+	.set_termios	= phytium_set_termios,
+	.type		= phytium_type,
+	.release_port	= phytium_release_port,
+	.request_port	= phytium_request_port,
+	.config_port	= phytium_config_port,
+	.verify_port	= phytium_verify_port,
+};
+
+static struct phytium_uart_port *uart_ports[UART_NR];
+
+static struct uart_driver phytium_uart = {
+	.owner		= THIS_MODULE,
+	.driver_name	= DRV_NAME,
+	.dev_name	= "ttyFTX",
+	.nr		= UART_NR,
+};
+
+void phytium_unregister_port(struct phytium_uart_port *pup)
+{
+	int i;
+	bool busy = false;
+
+	for (i = 0; i < ARRAY_SIZE(uart_ports); i++) {
+		if (uart_ports[i] == pup)
+			uart_ports[i] = NULL;
+		else if (uart_ports[i])
+			busy = true;
+	}
+
+	if (!busy)
+		uart_unregister_driver(&phytium_uart);
+}
+
+static int phytium_find_free_port(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(uart_ports); i++)
+		if (uart_ports[i] == NULL)
+			return i;
+
+	return -EBUSY;
+}
+
+static int phytium_register_port(struct phytium_uart_port *pup)
+{
+	int rc;
+
+	/* Ensure interrupts from this UART are masked and cleared */
+	phytium_uart_write(0, pup, REG_IMSC);
+	phytium_uart_write(0xffff, pup, REG_ICR);
+
+	if (!phytium_uart.state) {
+		rc = uart_register_driver(&phytium_uart);
+		if (rc < 0) {
+			dev_err(pup->port.dev,
+				"Failed to register Phytium PCI UART driver\n");
+			return rc;
+		}
+	}
+
+	rc = uart_add_one_port(&phytium_uart, &pup->port);
+	if (rc)
+		phytium_unregister_port(pup);
+
+	return rc;
+}
+
+static int phytium_uart_probe(struct pci_dev *pdev,
+			      const struct pci_device_id *id)
+{
+	struct phytium_uart_port *pup;
+	int portnr, rc;
+
+	portnr = phytium_find_free_port();
+	if (portnr < 0)
+		return portnr;
+
+	pup = devm_kzalloc(&pdev->dev, sizeof(struct phytium_uart_port),
+			   GFP_KERNEL);
+	if (!pup)
+		return -ENOMEM;
+
+	rc = pcim_enable_device(pdev);
+	if (rc)
+		return rc;
+
+	rc = pcim_iomap_regions_request_all(pdev, 0x01, pci_name(pdev));
+	if (rc)
+		return rc;
+
+	pup->port.iotype = UPIO_MEM32;
+	pup->port.irq = pdev->irq;
+	pup->port.mapbase = pci_resource_start(pdev, 0);
+	pup->port.membase = pcim_iomap_table(pdev)[0];
+	pup->port.ops = &phytium_uart_ops;
+	pup->port.dev = &pdev->dev;
+	pup->port.fifosize = 32;
+	pup->port.flags = UPF_BOOT_AUTOCONF;
+	pup->port.line = portnr;
+
+	uart_ports[portnr] = pup;
+
+	pup->old_cr = 0;
+	snprintf(pup->type, sizeof(pup->type), "pci-uart");
+
+	pci_set_drvdata(pdev, pup);
+
+	return phytium_register_port(pup);
+}
+
+static void phytium_uart_remove(struct pci_dev *pdev)
+{
+	struct phytium_uart_port *pup = pci_get_drvdata(pdev);
+
+	uart_remove_one_port(&phytium_uart, &pup->port);
+	phytium_unregister_port(pup);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int phytium_uart_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct phytium_uart_port *pup = pci_get_drvdata(pdev);
+
+	if (pup)
+		uart_suspend_port(&phytium_uart, &pup->port);
+
+	return 0;
+}
+
+static int phytium_uart_resume(struct device *dev)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct phytium_uart_port *pup = pci_get_drvdata(pdev);
+
+	if (pup)
+		uart_resume_port(&phytium_uart, &pup->port);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(phytium_dev_pm_ops, phytium_uart_suspend, phytium_uart_resume);
+
+static const struct pci_device_id pci_ids[] = {
+	{ PCI_VDEVICE(PHYTIUM, 0xdc2e) },
+	{ 0 }
+};
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+static struct pci_driver phytium_uart_pci_driver = {
+	.name		= DRV_NAME,
+	.probe		= phytium_uart_probe,
+	.remove		= phytium_uart_remove,
+	.driver	= {
+		.pm	= &phytium_dev_pm_ops,
+	},
+	.id_table	= pci_ids,
+};
+
+static int __init phytium_uart_init(void)
+{
+	pr_info("Serial: Phytium PCI UART driver\n");
+
+	return pci_register_driver(&phytium_uart_pci_driver);
+}
+
+static void __exit phytium_uart_exit(void)
+{
+	pci_unregister_driver(&phytium_uart_pci_driver);
+}
+
+module_init(phytium_uart_init);
+module_exit(phytium_uart_exit);
+
+MODULE_AUTHOR("Chen Baozi <chenbaozi@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium PCI serial port driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/Kconfig b/target/linux/phytium/files-5.10/drivers/usb/phytium/Kconfig
new file mode 100644
index 00000000000000..f131a3f8865a53
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/Kconfig
@@ -0,0 +1,8 @@
+config USB_PHYTIUM
+	tristate "PHYTIUM USB Support"
+	depends on USB && USB_GADGET
+	help
+	  Say Y or M here if your system has a OTG USB Controller based on PHYTIUM SOC.
+
+	  If you choose to build this driver is a dynamically linked modules, the module will
+          be called phytium-usb.ko
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/Makefile b/target/linux/phytium/files-5.10/drivers/usb/phytium/Makefile
new file mode 100644
index 00000000000000..05d422d4a59bc5
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_USB_PHYTIUM) += phytium-usb.o
+
+phytium-usb-y := core.o dma.o platform.o host.o gadget.o
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/core.c b/target/linux/phytium/files-5.10/drivers/usb/phytium/core.c
new file mode 100644
index 00000000000000..c0182c0770e5ef
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/core.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "core.h"
+
+int phytium_core_reset(struct phytium_cusb *config, bool skip_wait)
+{
+	if (!config)
+		return 0;
+
+	spin_lock_init(&config->lock);
+
+	return 0;
+}
+
+uint32_t phytium_read32(uint32_t *address)
+{
+	return readl(address);
+}
+
+void phytium_write32(uint32_t *address, uint32_t value)
+{
+	writel(value, address);
+}
+
+uint16_t phytium_read16(uint16_t *address)
+{
+	return readw(address);
+}
+
+void phytium_write16(uint16_t *address, uint16_t value)
+{
+	writew(value, address);
+}
+
+uint8_t phytium_read8(uint8_t *address)
+{
+	return readb(address);
+}
+
+void phytium_write8(uint8_t *address, uint8_t value)
+{
+	writeb(value, address);
+}
+
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/core.h b/target/linux/phytium/files-5.10/drivers/usb/phytium/core.h
new file mode 100644
index 00000000000000..f563672ccaa996
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/core.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __PHYTIUM_CORE_H__
+#define __PHYTIUM_CORE_H__
+
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include "host_api.h"
+#include "gadget.h"
+
+#define MAX_EPS_CHANNELS	16
+
+struct phytium_ep {
+	struct phytium_cusb	*config;
+	u16			max_packet;
+	u8			ep_num;
+	struct GADGET_EP	*gadget_ep;
+	struct list_head	req_list;
+	struct usb_ep		end_point;
+	char			name[12];
+	u8 is_tx;
+	const struct usb_endpoint_descriptor	*desc;
+	u8			busy;
+};
+
+struct phytium_request {
+	struct usb_request request;
+	struct GADGET_REQ	*gadget_request;
+	struct list_head	list;
+	struct phytium_ep	*ep;
+	struct phytium_cusb	*config;
+	u8			is_tx;
+	u8			epnum;
+};
+
+struct phytium_cusb {
+	struct device		*dev;
+	void __iomem		*regs;
+	void __iomem		*phy_regs;
+	int			irq;
+	spinlock_t		lock;
+	enum usb_dr_mode	dr_mode;
+
+	struct GADGET_OBJ	*gadget_obj;
+	struct GADGET_CFG	gadget_cfg;
+	struct GADGET_CALLBACKS gadget_callbacks;
+	struct GADGET_SYSREQ	gadget_sysreq;
+	struct GADGET_DEV	*gadget_dev;
+	void			*gadget_priv;
+
+	struct usb_gadget	gadget;
+	struct usb_gadget_driver *gadget_driver;
+	struct phytium_ep	endpoints_tx[MAX_EPS_CHANNELS];
+	struct phytium_ep	endpoints_rx[MAX_EPS_CHANNELS];
+	u8			ep0_data_stage_is_tx;
+
+	struct HOST_OBJ		*host_obj;
+	struct HOST_CFG		host_cfg;
+	struct HOST_CALLBACKS	host_callbacks;
+	struct HOST_SYSREQ	host_sysreq;
+	void			*host_priv;
+	struct usb_hcd          *hcd;
+
+	struct DMA_OBJ		*dma_obj;
+	struct DMA_CFG		dma_cfg;
+	struct DMA_CALLBACKS	dma_callbacks;
+	struct DMA_SYSREQ	dma_sysreq;
+	bool	isVhubHost;
+};
+
+int phytium_core_reset(struct phytium_cusb *config, bool skip_wait);
+
+int phytium_host_init(struct phytium_cusb *config);
+int phytium_host_uninit(struct phytium_cusb *config);
+
+#ifdef CONFIG_PM
+int phytium_host_resume(void *priv);
+int phytium_host_suspend(void *priv);
+int phytium_gadget_resume(void *priv);
+int phytium_gadget_suspend(void *priv);
+#endif
+
+int phytium_gadget_init(struct phytium_cusb *config);
+int phytium_gadget_uninit(struct phytium_cusb *config);
+
+uint32_t phytium_read32(uint32_t *address);
+
+void phytium_write32(uint32_t *address, uint32_t value);
+
+uint16_t phytium_read16(uint16_t *address);
+
+void phytium_write16(uint16_t *address, uint16_t value);
+
+uint8_t phytium_read8(uint8_t *address);
+
+void phytium_write8(uint8_t *address, uint8_t value);
+
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/dma.c b/target/linux/phytium/files-5.10/drivers/usb/phytium/dma.c
new file mode 100644
index 00000000000000..2e0d6df3eb344e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/dma.c
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/errno.h>
+#include <linux/string.h>
+#include "core.h"
+#include "dma.h"
+#include "hw-regs.h"
+
+#define TRB_POOL_SIZE (sizeof(struct DMA_Trb) * (NUM_OF_TRB))
+/* burst length 'x' should be multiples of 2 */
+#define TRB_BURST_LENGTH(x)        (((x) & 0xFF) << 24)
+
+#define BUILD_NORMAL_TRB_NO_IOC(trb, data_ptr, data_size, stream_id) { \
+	trb.dmaAddr = data_ptr; \
+	trb.dmaSize = data_size; \
+	trb.ctrl = (stream_id << 16) | TD_TYPE_NORMAL | TDF_CYCLE_BIT; }
+
+#define BUILD_NORMAL_TRB_NO_IOC_CHAIN(trb, data_ptr, data_size, stream_id) { \
+	trb.dmaAddr = data_ptr; \
+	trb.dmaSize = data_size; \
+	trb.ctrl = (stream_id << 16) | TD_TYPE_NORMAL | TDF_CYCLE_BIT | TDF_CHAIN_BIT; }
+
+#define BUILD_NORMAL_TRB(trb, data_ptr, data_size, stream_id) { \
+	trb.dmaAddr = data_ptr; \
+	trb.dmaSize = (data_size) | TRB_BURST_LENGTH(0x80); \
+	trb.ctrl = (stream_id << 16) | TD_TYPE_NORMAL | TDF_CYCLE_BIT |\
+	TDF_INT_ON_COMPLECTION | TDF_INT_ON_SHORT_PACKET; }
+
+#define BUILD_LINK_TRB(trb, target_ptr) { \
+	trb.dmaAddr = target_ptr; \
+	trb.dmaSize = 0; \
+	trb.ctrl = TD_TYPE_LINK | TDF_CYCLE_BIT | TDF_CHAIN_BIT; }
+
+#define BUILD_EMPTY_TRB(trb) { \
+	trb.dmaAddr = 0; \
+	trb.dmaSize = 0; \
+	trb.ctrl = 0; }
+
+
+uint32_t divRoundUp(uint32_t divident, uint32_t divisor)
+{
+	return divisor ? ((divident + divisor - 1) / divisor) : 0;
+}
+
+static inline struct DMA_TrbChainDesc *GetTrbChainDescEntry(struct list_head *list)
+{
+	return (struct DMA_TrbChainDesc *)((uintptr_t)list -
+			(uintptr_t)&(((struct DMA_TrbChainDesc *)0)->chainNode));
+}
+
+static int32_t phytium_dma_probe(struct DMA_CFG *config, struct DMA_SYSREQ *sysReq)
+{
+	if (!sysReq)
+		return -EINVAL;
+
+	sysReq->trbMemSize = TRB_POOL_SIZE;
+	sysReq->privDataSize = sizeof(struct DMA_CONTROLLER);
+
+	return 0;
+}
+
+static int32_t phytium_dma_init(struct DMA_CONTROLLER *priv,
+		const struct DMA_CFG *config, struct DMA_CALLBACKS *callbacks)
+{
+	if (!priv || !config || !callbacks)
+		return -EINVAL;
+
+	if (!config->trbAddr || !config->trbDmaAddr)
+		return -EINVAL;
+
+	memset((void *)priv, 0, sizeof(struct DMA_CONTROLLER));
+	memset((void *)config->trbAddr, 0, TRB_POOL_SIZE);
+
+	priv->trbDMAPoolAddr = config->trbDmaAddr;
+	priv->trbPoolAddr = config->trbAddr;
+	priv->regs = (struct DMARegs *)config->regBase;
+	priv->dmaCfg = *config;
+	priv->dmaDrv = DMA_GetInstance();
+	priv->dmaCallbacks = *callbacks;
+	priv->isHostCtrlMode = 0;
+	return 0;
+}
+
+static void phytium_dma_destroy(struct DMA_CONTROLLER *priv)
+{
+
+}
+
+static int32_t phytium_dma_start(struct DMA_CONTROLLER *priv)
+{
+	int i;
+
+	if (!priv)
+		return -EINVAL;
+
+	priv->dmaMode = DMA_MODE_CHANNEL_INDIVIDUAL;
+	if ((priv->dmaCfg.dmaModeRx & priv->dmaCfg.dmaModeTx) == 0xFFFF) {
+		priv->dmaMode = DMA_MODE_GLOBAL_DMULT;
+		phytium_write32(&priv->regs->conf, DMARF_DMULT);
+	} else if ((priv->dmaCfg.dmaModeRx | priv->dmaCfg.dmaModeTx)) {
+		priv->dmaMode = DMA_MODE_GLOBAL_DSING;
+		phytium_write32(&priv->regs->conf, DMARF_DSING);
+	}
+
+	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
+		if (priv->dmaCfg.dmaModeRx & (1 << i)) {
+			priv->rx[i].dmultEnabled = 1;
+			priv->rx[i].maxTrbLen = TD_DMULT_MAX_TRB_DATA_SIZE;
+			priv->rx[i].maxTdLen = TD_DMULT_MAX_TD_DATA_SIZE;
+		} else {
+			priv->rx[i].dmultEnabled = 0;
+			priv->rx[i].maxTrbLen = TD_SING_MAX_TRB_DATA_SIZE;
+			priv->rx[i].maxTdLen = TD_SING_MAX_TD_DATA_SIZE;
+		}
+		priv->rx[i].lastTransferLength = 0;
+
+		if (priv->dmaCfg.dmaModeTx & (1 << i)) {
+			priv->tx[i].dmultEnabled = 1;
+			priv->tx[i].maxTrbLen = TD_DMULT_MAX_TRB_DATA_SIZE;
+			priv->tx[i].maxTdLen = TD_DMULT_MAX_TD_DATA_SIZE;
+		} else {
+			priv->tx[i].dmultEnabled = 0;
+			priv->tx[i].maxTrbLen = TD_SING_MAX_TRB_DATA_SIZE;
+			priv->tx[i].maxTdLen = TD_SING_MAX_TD_DATA_SIZE;
+		}
+		priv->tx[i].lastTransferLength = 0;
+	}
+
+	return 0;
+}
+
+static uint32_t phytium_dma_stop(struct DMA_CONTROLLER *priv)
+{
+
+	return 0;
+}
+
+static int32_t updateDescBuffer(struct DMA_CONTROLLER *priv,
+		struct DMA_TrbChainDesc *trbChainDesc, uint16_t status)
+{
+	uint32_t ep_sel, i;
+	struct DMA_Channel *channel;
+
+	if (!priv || !trbChainDesc)
+		return -EINVAL;
+
+	channel = trbChainDesc->channel;
+	if (!channel)
+		return -EINVAL;
+
+	if (channel->isIsoc && trbChainDesc->lastTrbIsLink) {
+		if (channel->trbChainDescList.prev == channel->trbChainDescList.next)
+			return 0;
+	}
+
+	for (i = 0; i < trbChainDesc->numOfTrbs; i++) {
+		if (trbChainDesc->framesDesc) {
+			if (trbChainDesc->isoError)
+				trbChainDesc->framesDesc[i].length = 0;
+			else
+				trbChainDesc->framesDesc[i].length =
+					(uint32_t)trbChainDesc->trbPool[i].dmaSize & TD_SIZE_MASK;
+		}
+
+		trbChainDesc->actualLen +=
+			(uint32_t)trbChainDesc->trbPool[i].dmaSize & TD_SIZE_MASK;
+	}
+
+	if (trbChainDesc->isoError)
+		trbChainDesc->actualLen = 0;
+
+	ep_sel = phytium_read32(&priv->regs->ep_sel);
+	channel->lastTransferLength = trbChainDesc->actualLen;
+
+	if (!trbChainDesc->lastTrbIsLink) {
+		if (!list_empty(&trbChainDesc->chainNode)) {
+			for (i = 0; i < trbChainDesc->mapSize; i++)
+				priv->trbChainFreeMap[(trbChainDesc->start >> 3) + i] = 0;
+
+			trbChainDesc->channel->numOfTrbChain--;
+			trbChainDesc->reserved = 0;
+			list_del(&trbChainDesc->chainNode);
+			trbChainDesc = NULL;
+		}
+	}
+
+	if (channel->trbChainDescList.prev == &channel->trbChainDescList)
+		channel->status = DMA_STATUS_FREE;
+
+	if (priv->dmaCallbacks.complete)
+		priv->dmaCallbacks.complete(priv->parent, channel->hwUsbEppNum,
+				channel->isDirTx, false);
+
+	if (channel->trbChainDescList.next != &channel->trbChainDescList) {
+		trbChainDesc = GetTrbChainDescEntry(channel->trbChainDescList.next);
+		if (trbChainDesc && trbChainDesc->lastTrbIsLink) {
+			if (!list_empty(&trbChainDesc->chainNode)) {
+				for (i = 0; i < trbChainDesc->mapSize; i++)
+					priv->trbChainFreeMap[(trbChainDesc->start >> 3) + i] = 0;
+
+				trbChainDesc->channel->numOfTrbChain--;
+				trbChainDesc->reserved = 0;
+				list_del(&trbChainDesc->chainNode);
+			}
+		}
+	}
+
+	phytium_write32(&priv->regs->ep_sel, ep_sel);
+
+	return 0;
+}
+
+static void phytium_dma_isr(struct DMA_CONTROLLER *priv)
+{
+	uint32_t ep_sts, ep_ists, ep_cfg;
+	int i;
+	uint8_t isDirTx, epNum;
+	struct DMA_Channel *channel;
+	struct DMA_TrbChainDesc *trbChainDesc;
+
+	if (!priv)
+		return;
+
+	ep_ists = phytium_read32(&priv->regs->ep_ists);
+	if (!ep_ists) {
+		phytium_write32(&priv->regs->ep_sts, DMARF_EP_IOC |
+				DMARF_EP_ISP | DMARF_EP_TRBERR);
+		return;
+	}
+
+	for (i = 0; i < 32; i++) {
+		if (!(ep_ists & (1 << i)))
+			continue;
+
+		isDirTx = i > 15 ? DMARD_EP_TX : 0u;
+		epNum = isDirTx ? i - 16 : i;
+		phytium_write32(&priv->regs->ep_sel, epNum | isDirTx);
+
+		if (isDirTx)
+			channel = &priv->tx[epNum];
+		else
+			channel = &priv->rx[epNum];
+
+		ep_sts = phytium_read32(&priv->regs->ep_sts);
+
+		if (ep_sts & DMARF_EP_TRBERR)
+			phytium_write32(&priv->regs->ep_sts, DMARF_EP_TRBERR);
+
+		if ((ep_sts & DMARF_EP_IOC) || (ep_sts & DMARF_EP_ISP) || (channel->dmultGuard
+					& DMARF_EP_IOC) || (channel->dmultGuard & DMARF_EP_ISP)) {
+retransmit:
+			phytium_write32(&priv->regs->ep_sts, DMARF_EP_IOC | DMARF_EP_ISP);
+			trbChainDesc = GetTrbChainDescEntry(channel->trbChainDescList.next);
+			if (!(ep_sts & DMARF_EP_TRBERR) && channel->dmultEnabled
+					&& !trbChainDesc->lastTrbIsLink) {
+				if (!priv->isHostCtrlMode && !channel->isDirTx) {
+					channel->dmultGuard = 0;
+					phytium_write32(&priv->regs->ep_sts, DMARF_EP_TRBERR);
+					ep_cfg = phytium_read32(&priv->regs->ep_cfg);
+					ep_cfg &= ~DMARV_EP_ENABLED;
+					phytium_write32(&priv->regs->ep_cfg, (uint32_t)ep_cfg);
+					updateDescBuffer(priv, trbChainDesc, 0);
+					break;
+				}
+				channel->dmultGuard = ep_sts;
+				break;
+			}
+
+			channel->dmultGuard = 0;
+			updateDescBuffer(priv, trbChainDesc, 0);
+		}
+
+		if (ep_sts & DMARF_EP_OUTSMM)
+			phytium_write32(&priv->regs->ep_sts, DMARF_EP_OUTSMM);
+
+		if (ep_sts & DMARF_EP_DESCMIS)
+			phytium_write32(&priv->regs->ep_sts, DMARF_EP_DESCMIS);
+
+		if (ep_sts & DMARF_EP_ISOERR) {
+			phytium_write32(&priv->regs->ep_sts, DMARF_EP_ISOERR);
+			trbChainDesc = GetTrbChainDescEntry(channel->trbChainDescList.next);
+			trbChainDesc->isoError = 1;
+			goto retransmit;
+		}
+	}
+}
+
+static void phytium_dma_errIsr(struct DMA_CONTROLLER *priv, uint8_t irqNr, uint8_t isDirTx)
+{
+	struct DMA_Channel *channel;
+
+	if (!priv)
+		return;
+
+	if (isDirTx)
+		channel = &priv->tx[irqNr];
+	else
+		channel = &priv->rx[irqNr];
+
+	if (channel->status >= DMA_STATUS_BUSY)
+		channel->status = DMA_STATUS_ABORT;
+
+	if (priv->dmaCallbacks.complete) {
+		if (!irqNr && priv->resubmit) {
+			priv->dmaCallbacks.complete(priv->parent, channel->hwUsbEppNum,
+					channel->isDirTx, true);
+			priv->resubmit = false;
+		} else
+			priv->dmaCallbacks.complete(priv->parent, channel->hwUsbEppNum,
+					channel->isDirTx, false);
+	}
+}
+
+static void *phytium_dma_channelAlloc(struct DMA_CONTROLLER *priv,
+		uint8_t isDirTx, uint8_t hwEpNum, uint8_t isIsoc)
+{
+	struct DMA_Channel *channel;
+	uint32_t ep_ien, ep_cfg;
+	uint16_t dmaMode;
+
+	if (!priv || (hwEpNum >= MAX_DMA_CHANNELS))
+		return NULL;
+
+	if (!priv->regs) {
+		pr_err("dma regs is null\n");
+		return NULL;
+	}
+
+	ep_ien = phytium_read32(&priv->regs->ep_ien);
+
+	if (isDirTx) {
+		if (priv->tx[hwEpNum].status > DMA_STATUS_FREE)
+			return NULL;
+
+		channel = &priv->tx[hwEpNum];
+		channel->isDirTx = 0x80;
+		ep_ien |= (0x01 << (hwEpNum + 16));
+		dmaMode = priv->dmaCfg.dmaModeTx;
+	} else {
+		if (priv->rx[hwEpNum].status > DMA_STATUS_FREE)
+			return NULL;
+
+		channel = &priv->rx[hwEpNum];
+		channel->isDirTx = 0x00;
+		ep_ien |= (0x01 << hwEpNum);
+		dmaMode = priv->dmaCfg.dmaModeRx;
+	}
+
+	channel->isIsoc = 0;
+	if (isIsoc)
+		channel->isIsoc = 1;
+
+	INIT_LIST_HEAD(&channel->trbChainDescList);
+	channel->numOfTrbChain = 0;
+	channel->controller = priv;
+	channel->dmultGuard = 0;
+	channel->status = DMA_STATUS_FREE;
+	channel->hwUsbEppNum = hwEpNum;
+
+	phytium_write32(&priv->regs->ep_sel, (uint32_t)hwEpNum | channel->isDirTx);
+	ep_cfg = phytium_read32(&priv->regs->ep_cfg);
+
+	if (priv->dmaMode == DMA_MODE_CHANNEL_INDIVIDUAL) {
+		if (dmaMode & (1 << hwEpNum))
+			ep_cfg |= DMARV_EP_DMULT;
+		else
+			ep_cfg |= DMARV_EP_DSING;
+	}
+
+	phytium_write32(&priv->regs->ep_sts, DMARF_EP_IOC | DMARF_EP_ISP | DMARF_EP_TRBERR);
+	phytium_write32(&priv->regs->ep_cfg, (uint32_t)DMARV_EP_ENABLED | ep_cfg);
+	phytium_write32(&priv->regs->ep_ien, ep_ien);
+	phytium_write32(&priv->regs->ep_sts_en, DMARF_EP_TRBERR);
+
+	return channel;
+}
+
+static int32_t phytium_dma_channelRelease(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel)
+{
+	uint32_t ep_ien, i;
+	struct DMA_TrbChainDesc *trbChainDesc;
+
+	if (!channel || !priv)
+		return -EINVAL;
+
+	ep_ien = phytium_read32(&priv->regs->ep_ien);
+	if (channel->isDirTx)
+		ep_ien &= ~(0x01 << (channel->hwUsbEppNum + 16));
+	else
+		ep_ien &= ~(0x01 << channel->hwUsbEppNum);
+
+	phytium_write32(&priv->regs->ep_sel, (uint32_t)channel->hwUsbEppNum | channel->isDirTx);
+	phytium_write32(&priv->regs->ep_cfg, (uint32_t)0);
+	phytium_write32(&priv->regs->ep_ien, ep_ien);
+	phytium_write32(&priv->regs->ep_sts_en, 0x0);
+	phytium_write32(&priv->regs->ep_cmd, DMARF_EP_EPRST);
+	phytium_write32(&priv->regs->ep_sts, DMARF_EP_IOC | DMARF_EP_ISP |
+			DMARF_EP_TRBERR | DMARF_EP_ISOERR);
+
+	if (channel->status >= DMA_STATUS_BUSY)
+		channel->status = DMA_STATUS_ABORT;
+
+	priv->dmaDrv->dma_channelAbort(priv, channel);
+
+	while (channel->trbChainDescList.next != &channel->trbChainDescList) {
+		trbChainDesc = GetTrbChainDescEntry(channel->trbChainDescList.next);
+		if (trbChainDesc) {
+			if (!list_empty(&trbChainDesc->chainNode)) {
+				for (i = 0; i < trbChainDesc->mapSize; i++)
+					priv->trbChainFreeMap[(trbChainDesc->start >> 3) + i] = 0;
+
+				trbChainDesc->channel->numOfTrbChain--;
+				trbChainDesc->reserved = 0;
+				list_del(&trbChainDesc->chainNode);
+			}
+		}
+	}
+
+	channel->status = DMA_STATUS_UNKNOW;
+
+	return 0;
+}
+
+static void ShowTrbChain(struct DMA_TrbChainDesc *trbChainDesc)
+{
+	int i;
+
+	if (!trbChainDesc)
+		return;
+	pr_debug("Trb Chain %p for channel %p\n", trbChainDesc, trbChainDesc->channel);
+	pr_debug("idx	| trb size	| trb addr	| FLAG: NORMAL  LINK  CHAIN  ALL\n");
+	for (i = 0; i < trbChainDesc->numOfTrbs + 2; i++)
+		pr_debug("%02d	| %08x	| %08x	|	%d	%d	%d	%08x\n",
+			i,
+			trbChainDesc->trbPool[i].dmaSize & TD_SIZE_MASK,
+			trbChainDesc->trbPool[i].dmaAddr,
+			(trbChainDesc->trbPool[i].ctrl & TD_TYPE_NORMAL) ? 1 : 0,
+			(trbChainDesc->trbPool[i].ctrl & TD_TYPE_LINK) ? 1 : 0,
+			(trbChainDesc->trbPool[i].ctrl & TDF_CHAIN_BIT) ? 1 : 0,
+			trbChainDesc->trbPool[i].ctrl);
+}
+
+static uint32_t phytium_dma_NewTd(struct DMA_CONTROLLER *priv,
+		struct DMA_TrbChainDesc *trbChainDesc)
+{
+	uint32_t startAddress, dataSize;
+	struct DMA_Channel *channel;
+	int i = 0;
+	uint32_t tmp = 0;
+
+	if (!priv || !trbChainDesc)
+		return 0;
+
+	startAddress = trbChainDesc->dwStartAddress;
+	channel = trbChainDesc->channel;
+	dataSize = channel->maxTrbLen;
+
+	if (trbChainDesc->numOfTrbs > 1) {
+		for (i = 0; i < (trbChainDesc->numOfTrbs - 1); i++) {
+			if (channel->dmultEnabled) {
+				if (trbChainDesc->framesDesc && priv->isHostCtrlMode
+						&& channel->isIsoc) {
+					BUILD_NORMAL_TRB_NO_IOC(trbChainDesc->trbPool[i],
+							trbChainDesc->dwStartAddress +
+							trbChainDesc->framesDesc[i].offset,
+							trbChainDesc->framesDesc[i].length, 0);
+					continue;
+				} else
+					BUILD_NORMAL_TRB_NO_IOC(trbChainDesc->trbPool[i],
+							startAddress, dataSize, 0);
+			} else
+				BUILD_NORMAL_TRB_NO_IOC_CHAIN(trbChainDesc->trbPool[i],
+						startAddress, dataSize, 0);
+			startAddress += dataSize;
+			tmp += dataSize;
+		}
+	}
+
+	if (trbChainDesc->framesDesc && priv->isHostCtrlMode && channel->isIsoc) {
+		BUILD_NORMAL_TRB(trbChainDesc->trbPool[i],
+				trbChainDesc->dwStartAddress + trbChainDesc->framesDesc[i].offset,
+				trbChainDesc->framesDesc[i].length, 0);
+	} else
+		BUILD_NORMAL_TRB(trbChainDesc->trbPool[i], startAddress,
+				trbChainDesc->len - tmp, 0);
+
+	trbChainDesc->lastTrbIsLink = 0;
+	if (channel->dmultEnabled) {
+		if (channel->isIsoc) {
+			trbChainDesc->lastTrbIsLink = 1;
+			BUILD_LINK_TRB(trbChainDesc->trbPool[i + 1], trbChainDesc->trbDMAAddr);
+		} else
+			BUILD_EMPTY_TRB(trbChainDesc->trbPool[i + 1]);
+	}
+
+	ShowTrbChain(trbChainDesc);
+
+	return 0;
+}
+
+static void phytium_dma_ArmTd(struct DMA_CONTROLLER *priv, struct DMA_TrbChainDesc *trbChainDesc)
+{
+	uint32_t ep_sts, ep_cfg, ep_cmd;
+	struct DMA_TrbChainDesc *startedChain;
+	struct DMA_Trb *lastPrevTrb;
+	struct DMA_Channel *channel;
+
+	if (!priv || !trbChainDesc)
+		return;
+
+	channel = trbChainDesc->channel;
+	phytium_write32(&priv->regs->ep_sel, (channel->isDirTx | channel->hwUsbEppNum));
+
+	ep_sts = phytium_read32(&priv->regs->ep_sts);
+
+	if (channel->status == DMA_STATUS_FREE) {
+		phytium_write32(&priv->regs->ep_sts, DMARF_EP_TRBERR);
+		phytium_write32(&priv->regs->traddr, trbChainDesc->trbDMAAddr);
+		phytium_write32(&priv->regs->ep_sts, DMARF_EP_TRBERR);
+
+		ep_cfg = phytium_read32(&priv->regs->ep_cfg);
+		phytium_write32(&priv->regs->ep_cmd, DMARF_EP_DRDY);
+		if (!(ep_cfg & DMARV_EP_ENABLED)) {
+			ep_cfg |= DMARV_EP_ENABLED;
+			phytium_write32(&priv->regs->ep_cfg, ep_cfg);
+		}
+	} else {
+		if (channel->trbChainDescList.prev != channel->trbChainDescList.next) {
+			startedChain = GetTrbChainDescEntry(channel->trbChainDescList.prev->prev);
+			lastPrevTrb = &startedChain->trbPool[startedChain->numOfTrbs];
+			startedChain->lastTrbIsLink = 1;
+			BUILD_LINK_TRB((*lastPrevTrb), trbChainDesc->trbDMAAddr);
+			ep_cmd = phytium_read32(&priv->regs->ep_cmd);
+			if (!(ep_cmd & DMARF_EP_DRDY)) {
+				phytium_write32(&priv->regs->traddr, trbChainDesc->trbDMAAddr);
+				phytium_write32(&priv->regs->ep_cmd, DMARF_EP_DRDY);
+			}
+			ShowTrbChain(startedChain);
+		}
+	}
+}
+
+static int32_t phytium_dma_TrbChainAlloc(struct DMA_CONTROLLER *priv,
+		struct DMA_Channel *channel, uint32_t numOfTrbs, struct DMA_TrbChainDesc **chain)
+{
+	struct DMA_TrbChainDesc *trbChainDesc = NULL;
+	int i, j;
+	uint32_t mapcount, count = 0;
+
+	if (!priv || !channel)
+		return -ENOMEM;
+
+	for (i = 0; i < TAB_SIZE_OF_DMA_CHAIN; i++) {
+		if (!priv->trbChainDesc[i].reserved) {
+			trbChainDesc = &priv->trbChainDesc[i];
+			break;
+		}
+	}
+
+	if (!trbChainDesc) {
+		pr_err("No Free TRB Chain Descriptor\n");
+		return -ENOMEM;
+	}
+
+	INIT_LIST_HEAD(&trbChainDesc->chainNode);
+	*chain = NULL;
+	mapcount = (numOfTrbs + 2 + 7) >> 3;
+
+	for (i = 0; i < TRB_MAP_SIZE; i++) {
+		if (priv->trbChainFreeMap[i] == 0x0)
+			count++;
+		else
+			count = 0;
+
+		if (count == mapcount)
+			break;
+	}
+
+	if (count != mapcount) {
+		pr_err("No Free TRBs count:0x%x, mapcount:0x%x\n", count, mapcount);
+		return -ENOMEM;
+	}
+
+	trbChainDesc->reserved = 1;
+	trbChainDesc->channel = channel;
+	trbChainDesc->actualLen = 0;
+	trbChainDesc->mapSize = mapcount;
+	trbChainDesc->numOfTrbs = numOfTrbs;
+	trbChainDesc->start = (i + 1 - mapcount) << 3;
+	trbChainDesc->end = trbChainDesc->start;
+	trbChainDesc->trbPool = (struct DMA_Trb *)priv->trbPoolAddr + trbChainDesc->start;
+	trbChainDesc->trbDMAAddr = (uint32_t)(uintptr_t)((struct DMA_Trb *)priv->trbDMAPoolAddr
+			+ trbChainDesc->start);
+	trbChainDesc->isoError = 0;
+
+	list_add_tail(&trbChainDesc->chainNode, &channel->trbChainDescList);
+
+	channel->numOfTrbChain++;
+
+	for (j = 0; j < count; j++)
+		priv->trbChainFreeMap[i - j] = 0xFF;
+
+	*chain = trbChainDesc;
+
+	return 0;
+}
+
+static int32_t phytium_dma_channelProgram(struct DMA_CONTROLLER *priv,
+		struct DMA_Channel *channel, uint16_t packetSize, uintptr_t dmaAddr,
+		uint32_t len, void *framesDesc, uint32_t framesNumber)
+{
+	uint32_t numOfTrbs;
+	uint8_t retval;
+	struct DMA_TrbChainDesc *trbChainDesc;
+
+	if (!priv || !channel)
+		return -EINVAL;
+
+	//printk(KERN_ERR "%s %d\n",__func__,__LINE__);
+	if (framesDesc && priv->isHostCtrlMode && channel->isIsoc)
+		numOfTrbs = framesNumber;
+	else
+		numOfTrbs = divRoundUp(len, channel->maxTrbLen);
+
+	retval = phytium_dma_TrbChainAlloc(priv, channel, numOfTrbs, &trbChainDesc);
+	if (retval)
+		return retval;
+
+	trbChainDesc->dwStartAddress = dmaAddr;
+	trbChainDesc->len = len;
+	trbChainDesc->framesDesc = framesDesc;
+
+	channel->wMaxPacketSize = packetSize;
+	phytium_dma_NewTd(priv, trbChainDesc);
+	channel->lastTransferLength = 0;
+	phytium_dma_ArmTd(priv, trbChainDesc);
+
+	channel->status = DMA_STATUS_BUSY;
+
+	return 0;
+}
+
+static enum DMA_Status phytium_dma_getChannelStatus(struct DMA_CONTROLLER *priv,
+		struct DMA_Channel *channel)
+{
+	uint32_t ep_cmd, ep_sts;
+
+	if (!priv || !channel)
+		return DMA_STATUS_UNKNOW;
+
+	if (channel->status >= DMA_STATUS_BUSY) {
+		phytium_write32(&priv->regs->ep_sel, channel->isDirTx | channel->hwUsbEppNum);
+		ep_cmd = phytium_read32(&priv->regs->ep_cmd);
+		ep_sts = phytium_read32(&priv->regs->ep_sts);
+
+		if ((ep_cmd & DMARF_EP_DRDY) || (ep_sts & DMARF_EP_DBUSY))
+			channel->status = DMA_STATUS_ARMED;
+		else
+			channel->status = DMA_STATUS_BUSY;
+	}
+
+	return channel->status;
+}
+
+static int32_t phytium_dma_channelAbort(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel)
+{
+	struct DMA_TrbChainDesc *trbChainDesc;
+	uint32_t ep_cfg, i;
+
+	if (!priv || !channel)
+		return -EINVAL;
+
+	if (phytium_dma_getChannelStatus(priv, channel) >= DMA_STATUS_BUSY)
+		phytium_write32(&priv->regs->conf, DMARF_RESET);
+
+	phytium_write32(&priv->regs->ep_sel, (uint32_t)(channel->isDirTx | channel->hwUsbEppNum));
+	ep_cfg = phytium_read32(&priv->regs->ep_cfg);
+	ep_cfg &= ~DMARV_EP_ENABLED;
+	phytium_write32(&priv->regs->ep_cfg, ep_cfg);
+	phytium_write32(&priv->regs->ep_sts, 0xFFFFFFFF);
+
+	while (channel->trbChainDescList.next != &channel->trbChainDescList) {
+		trbChainDesc = GetTrbChainDescEntry(channel->trbChainDescList.next);
+		if (trbChainDesc) {
+			if (!list_empty(&trbChainDesc->chainNode)) {
+				for (i = 0; i < trbChainDesc->mapSize; i++)
+					priv->trbChainFreeMap[(trbChainDesc->start >> 3) + i] = 0;
+
+				trbChainDesc->channel->numOfTrbChain--;
+				trbChainDesc->reserved = 0;
+				list_del(&trbChainDesc->chainNode);
+			}
+		}
+	}
+	if (channel->status != DMA_STATUS_UNKNOW)
+		channel->status = DMA_STATUS_FREE;
+
+	return 0;
+}
+
+static int32_t phytium_dma_getActualLength(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel)
+{
+	if (!priv || !channel)
+		return -EINVAL;
+
+	return channel->lastTransferLength;
+}
+
+static int32_t phytium_dma_getMaxLength(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel)
+{
+	if (!priv || !channel)
+		return -EINVAL;
+
+	return channel->maxTdLen;
+}
+
+static int32_t phytium_dma_setMaxLength(struct DMA_CONTROLLER *priv,
+		struct DMA_Channel *channel, uint32_t val)
+{
+	if (!priv || !channel)
+		return -EINVAL;
+
+	if (channel->dmultEnabled)
+		channel->maxTrbLen = val;
+	else
+		channel->maxTrbLen = (val > TD_SING_MAX_TRB_DATA_SIZE) ?
+			TD_SING_MAX_TRB_DATA_SIZE : val;
+
+	return 0;
+}
+
+static void phytium_dma_setParentPriv(struct DMA_CONTROLLER *priv, void *parent)
+{
+	if (!priv)
+		return;
+
+	priv->parent = parent;
+}
+
+void phytium_dma_controllerReset(struct DMA_CONTROLLER *priv)
+{
+	uint32_t conf;
+
+	if (!priv)
+		return;
+
+	conf = phytium_read32(&priv->regs->conf);
+	conf |= DMARF_RESET;
+	phytium_write32(&priv->regs->conf, conf);
+
+	priv->resubmit = true;
+}
+
+void phytium_dma_setHostMode(struct DMA_CONTROLLER *priv)
+{
+	if (!priv)
+		return;
+
+	priv->isHostCtrlMode = 1;
+}
+
+struct DMA_OBJ phytium_dma_Drv = {
+	.dma_probe = phytium_dma_probe,
+	.dma_init = phytium_dma_init,
+	.dma_destroy = phytium_dma_destroy,
+	.dma_start = phytium_dma_start,
+	.dma_stop = phytium_dma_stop,
+	.dma_isr = phytium_dma_isr,
+	.dma_errIsr = phytium_dma_errIsr,
+	.dma_channelAlloc = phytium_dma_channelAlloc,
+	.dma_channelRelease = phytium_dma_channelRelease,
+	.dma_channelProgram = phytium_dma_channelProgram,
+	.dma_channelAbort = phytium_dma_channelAbort,
+	.dma_getChannelStatus = phytium_dma_getChannelStatus,
+	.dma_getActualLength = phytium_dma_getActualLength,
+	.dma_getMaxLength = phytium_dma_getMaxLength,
+	.dma_setMaxLength = phytium_dma_setMaxLength,
+	.dma_setParentPriv = phytium_dma_setParentPriv,
+	.dma_controllerReset = phytium_dma_controllerReset,
+	.dma_setHostMode = phytium_dma_setHostMode,
+};
+
+struct DMA_OBJ *DMA_GetInstance(void)
+{
+	return &phytium_dma_Drv;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/dma.h b/target/linux/phytium/files-5.10/drivers/usb/phytium/dma.h
new file mode 100644
index 00000000000000..073a078c128962
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/dma.h
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __PHYTIUM_DMA_H__
+#define __PHYTIUM_DMA_H__
+
+#include <linux/types.h>
+//#include "list.h"
+
+#define NUM_OF_TRB 1024
+#define TRB_MAP_SIZE ((NUM_OF_TRB + (sizeof(uint8_t) * 8) - 1) / (sizeof(uint8_t) * 8))
+#define MAX_DMA_CHANNELS 16
+#define TAB_SIZE_OF_DMA_CHAIN (MAX_DMA_CHANNELS * 2)
+
+#define DMARD_EP_TX 0x80ul
+#define DMARD_EP_RX 0x00ul
+
+#define DMARF_EP_EPRST	0x00000001ul
+#define DMARF_EP_DRDY	0x00000040ul
+#define DMARF_EP_DFLUSH	0x00000080ul
+
+#define DMARF_EP_IOC		0x4ul
+#define DMARF_EP_ISP		0x8ul
+#define DMARF_EP_DESCMIS	0x10ul
+#define DMARF_EP_TRBERR		0x80ul
+#define DMARF_EP_DBUSY		0x200ul
+#define DMARF_EP_CCS		0x800ul
+#define DMARF_EP_OUTSMM		0x4000ul
+#define DMARF_EP_ISOERR		0x8000ul
+#define DMARF_EP_DTRANS		0x80000000ul
+
+#define DMARV_EP_DISABLED	0ul
+#define DMARV_EP_ENABLED	1ul
+#define DMARV_EP_DSING		0x1000ul
+#define DMARV_EP_DMULT		0x2000ul
+
+#define TD_SIZE_MASK		0x00001FFFF
+
+#define DMARF_RESET		0x00000001ul
+#define DMARF_DSING		0x00000100ul
+#define DMARF_DMULT		0x00000200ul
+
+#define TD_DMULT_MAX_TRB_DATA_SIZE 65536u
+#define TD_DMULT_MAX_TD_DATA_SIZE  (~1u)
+#define TD_SING_MAX_TRB_DATA_SIZE 65536u
+#define TD_SING_MAX_TD_DATA_SIZE 65536u
+
+#define TD_TYPE_NORMAL	0x400L
+#define TD_TYPE_LINK	0x1800L
+#define TDF_CYCLE_BIT	0x1L
+#define TDF_TOGGLE_CYCLE_BIT	0x2L
+#define TDF_INT_ON_SHORT_PACKET	0x4L
+#define TDF_FIFO_MODE		0x8L
+#define TDF_CHAIN_BIT		0x10L
+#define TDF_INT_ON_COMPLECTION	0x20L
+#define TDF_STREAMID_VALID	0x200L
+
+struct DMA_Trb {
+	uint32_t dmaAddr;
+	uint32_t dmaSize; /* 0:16 transfer length; 24:31 burst length */
+	uint32_t ctrl;
+};
+
+enum DMA_Status {
+	DMA_STATUS_UNKNOW,
+	DMA_STATUS_FREE,
+	DMA_STATUS_ABORT,
+	DMA_STATUS_BUSY,
+	DMA_STATUS_ARMED
+};
+
+struct DMA_CFG {
+	uintptr_t regBase;
+	uint16_t dmaModeTx;
+	uint16_t dmaModeRx;
+	void *trbAddr;
+	uintptr_t trbDmaAddr;
+};
+
+struct DMA_SYSREQ {
+	uint32_t privDataSize;
+	uint32_t trbMemSize;
+};
+
+struct DMA_CALLBACKS {
+	void (*complete)(void *pD, uint8_t epNum, uint8_t dir, bool resubmit);
+};
+
+struct DMA_CONTROLLER;
+
+struct DMA_Channel {
+	struct DMA_CONTROLLER *controller;
+	uint16_t wMaxPacketSize;
+	uint8_t hwUsbEppNum;
+	uint8_t isDirTx;
+	uint32_t maxTdLen;
+	uint32_t maxTrbLen;
+	enum DMA_Status status;
+	void *priv;
+	uint32_t dmultGuard;
+	uint8_t dmultEnabled;
+	uint8_t numOfTrbChain;
+	struct list_head trbChainDescList;
+	uint32_t lastTransferLength;
+	uint8_t isIsoc;
+};
+
+struct DMA_OBJ {
+	int32_t (*dma_probe)(struct DMA_CFG *config, struct DMA_SYSREQ *sysReq);
+
+	int32_t (*dma_init)(struct DMA_CONTROLLER *priv, const struct DMA_CFG *config,
+			struct DMA_CALLBACKS *callbacks);
+
+	void (*dma_destroy)(struct DMA_CONTROLLER *priv);
+
+	int32_t (*dma_start)(struct DMA_CONTROLLER *priv);
+
+	uint32_t (*dma_stop)(struct DMA_CONTROLLER *priv);
+
+	void (*dma_isr)(struct DMA_CONTROLLER *priv);
+
+	void (*dma_errIsr)(struct DMA_CONTROLLER *priv, uint8_t irqNr, uint8_t isDirTx);
+
+	void * (*dma_channelAlloc)(struct DMA_CONTROLLER *priv,
+			uint8_t isDirTx, uint8_t hwEpNum, uint8_t isIso);
+
+	int32_t (*dma_channelRelease)(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel);
+
+	int32_t (*dma_channelProgram)(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel,
+			uint16_t packetSize, uintptr_t dmaAddr,
+			uint32_t len, void *framesDesc, uint32_t framesNumber);
+
+	int32_t (*dma_channelAbort)(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel);
+
+	enum DMA_Status (*dma_getChannelStatus)(struct DMA_CONTROLLER *priv,
+			struct DMA_Channel *channel);
+
+	int32_t (*dma_getActualLength)(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel);
+
+	int32_t (*dma_getMaxLength)(struct DMA_CONTROLLER *priv, struct DMA_Channel *channel);
+
+	int32_t (*dma_setMaxLength)(struct DMA_CONTROLLER *priv,
+			struct DMA_Channel *channel, uint32_t val);
+
+	void (*dma_setParentPriv)(struct DMA_CONTROLLER *priv, void *parent);
+
+	void (*dma_controllerReset)(struct DMA_CONTROLLER *priv);
+
+	void (*dma_setHostMode)(struct DMA_CONTROLLER *priv);
+};
+
+enum DMA_Mode {
+	DMA_MODE_GLOBAL_DMULT,
+	DMA_MODE_GLOBAL_DSING,
+	DMA_MODE_CHANNEL_INDIVIDUAL,
+};
+
+struct DMA_TrbFrameDesc {
+	uint32_t length;
+	uint32_t offset;
+};
+
+struct DMA_TrbChainDesc {
+	uint8_t reserved;
+	struct DMA_Channel *channel;
+	struct DMA_Trb	*trbPool;
+	uint32_t trbDMAAddr;
+	uint32_t len;
+	uint32_t dwStartAddress;
+	uint32_t actualLen;
+	uint8_t isoError;
+	uint8_t lastTrbIsLink;
+	uint32_t mapSize;
+	uint32_t numOfTrbs;
+	uint32_t start;
+	uint32_t end;
+	struct DMA_TrbFrameDesc *framesDesc;
+	struct list_head chainNode;
+};
+
+struct DMA_CONTROLLER {
+	struct DMARegs *regs;
+	struct DMA_OBJ *dmaDrv;
+	struct DMA_CFG dmaCfg;
+	struct DMA_CALLBACKS dmaCallbacks;
+	struct DMA_Channel rx[MAX_DMA_CHANNELS];
+	struct DMA_Channel tx[MAX_DMA_CHANNELS];
+	enum DMA_Mode dmaMode;
+	uint8_t isHostCtrlMode;
+	void *parent;
+	void *trbPoolAddr;
+	uintptr_t trbDMAPoolAddr;
+	uint8_t trbChainFreeMap[TRB_MAP_SIZE];
+	struct DMA_TrbChainDesc trbChainDesc[TAB_SIZE_OF_DMA_CHAIN];
+	bool resubmit;
+};
+
+struct DMA_OBJ *DMA_GetInstance(void);
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/gadget.c b/target/linux/phytium/files-5.10/drivers/usb/phytium/gadget.c
new file mode 100644
index 00000000000000..afcb846c8db342
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/gadget.c
@@ -0,0 +1,2538 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/dma-mapping.h>
+#include "gadget.h"
+#include "dma.h"
+#include "core.h"
+#include "hw-regs.h"
+
+#define DRV_NAME "phytium_gadget"
+
+#define GADGET_PRIV_BUFFER_SIZE 64
+#define GADGET_USB_EP_NUMBER_MASK 0xf
+#define DMA_ADDR_INVALID	(~(dma_addr_t)0)
+
+#define GADGET_ESTALL		1
+#define GADGET_EUNHANDLED	2
+#define GADGET_EAUTOACK		3
+#define GADGET_ESHUTDOWN	4
+#define GADGET_ECONNRESET	5
+#define GADGET_EAGAIN		6
+
+static inline struct GadgetEp *toGadgetEp(struct GADGET_EP *gadget_Ep)
+{
+	return (struct GadgetEp *)((uintptr_t)gadget_Ep -
+					((uintptr_t)&((struct GadgetEp *)0)->gadgetEp));
+}
+
+static inline struct GadgetRequest *requestToGadgetRequest(struct GADGET_REQ *req)
+{
+	return (struct GadgetRequest *)((uintptr_t)req -
+					((uintptr_t)&((struct GadgetRequest *)0)->request));
+}
+
+static inline struct GADGET_REQ *listToGadgetRequest(struct list_head *list)
+{
+	return (struct GADGET_REQ *)((uintptr_t)list -
+					((uintptr_t)&((struct GADGET_REQ *)0)->list));
+}
+
+#define listBrowsingRequest(iterator, head, memeber)	\
+	for (iterator = listToGadgetRequest((head)->next); \
+		&iterator->list != (head);	\
+		iterator = listToGadgetRequest(iterator->list.next))
+
+static inline struct GADGET_REQ *gadgetGetNextReq(struct GadgetEp *gadgetEp)
+{
+	struct list_head *list = &gadgetEp->request;
+
+	if (list_empty(list)) {
+		pr_debug("no request available for %s\n", gadgetEp->gadgetEp.name);
+		return NULL;
+	}
+
+	return listToGadgetRequest(list->next);
+}
+
+static inline struct GADGET_REQ *gadgetGetNextEp0Req(struct GADGET_CTRL *priv)
+{
+	struct list_head *queue;
+
+	if (!priv)
+		return NULL;
+
+	queue = &priv->in[0].request;
+
+	if (list_empty(queue))
+		return NULL;
+
+	return listToGadgetRequest(queue->next);
+}
+
+void gadget_giveback(struct phytium_ep *phy_ep, struct usb_request *usb_req, int status)
+{
+	struct phytium_request	*phy_req;
+	struct phytium_cusb	*config;
+	int busy;
+
+	if (!phy_ep || !usb_req)
+		return;
+
+	busy = phy_ep->busy;
+	phy_req = usb_req ? container_of(usb_req, struct phytium_request, request) : NULL;
+	config = phy_req->config;
+
+	list_del(&phy_req->list);
+
+	if (usb_req->status == -EINPROGRESS) {
+		if (status == GADGET_ESHUTDOWN)
+			usb_req->status = -ESHUTDOWN;
+		else if (status == GADGET_ECONNRESET)
+			usb_req->status = -ECONNRESET;
+		else
+			usb_req->status = -phy_req->gadget_request->status;
+	}
+
+	if (usb_req->status == 0)
+		pr_debug("%s done request %p, %d/%d\n", phy_ep->end_point.name,
+				usb_req, usb_req->actual, usb_req->length);
+	else
+		pr_debug("%s request %p, %d/%d fault %d\n", phy_ep->end_point.name,
+				usb_req, usb_req->actual, usb_req->length, usb_req->status);
+
+	usb_gadget_unmap_request(&config->gadget, &phy_req->request, phy_req->is_tx);
+
+	busy = phy_ep->busy;
+	phy_ep->busy = 1;
+
+	spin_unlock(&config->lock);
+
+	if (phy_req->request.complete)
+		phy_req->request.complete(&phy_req->ep->end_point, usb_req);
+
+	spin_lock(&config->lock);
+
+	phy_ep->busy = busy;
+}
+
+static void gadget_callback_complete(struct GADGET_EP *gadget_ep, struct GADGET_REQ *gadget_req)
+{
+	struct phytium_ep	*phy_ep;
+	struct phytium_request	*phy_req;
+	struct usb_request	*usb_req;
+
+	if (!gadget_ep || !gadget_req)
+		return;
+
+	phy_req = gadget_req->context;
+	usb_req = &phy_req->request;
+	phy_ep = phy_req->ep;
+	usb_req->actual = gadget_req->actual;
+	usb_req->length = gadget_req->length;
+
+	gadget_giveback(phy_ep, usb_req, gadget_req->status);
+}
+
+static void gadgetDisconnect(struct GADGET_CTRL *priv)
+{
+	pr_info("Disconnect USB Device Driver\n");
+
+	if (!priv)
+		return;
+
+	priv->gadgetDev.speed = USB_SPEED_UNKNOWN;
+	priv->gadgetDev.state = USB_STATE_NOTATTACHED;
+
+	if (priv->eventCallback.disconnect)
+		priv->eventCallback.disconnect(priv);
+}
+
+static int gadget_get_frame(struct usb_gadget *gadget)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return 0;
+}
+
+static int gadget_wakeup(struct usb_gadget *gadget)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return 0;
+}
+
+static int gadget_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return 0;
+}
+
+static int gadget_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return 0;
+}
+
+static int gadget_pullup(struct usb_gadget *gadget, int is_on)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return 0;
+}
+
+static int gadget_udc_start(struct usb_gadget *gadget, struct usb_gadget_driver *driver)
+{
+	unsigned long flags;
+	struct phytium_cusb *config;
+	struct GADGET_CTRL *priv;
+	uint32_t gen_cfg;
+
+	if (!gadget || !driver)
+		return -EINVAL;
+
+	if (driver->max_speed < USB_SPEED_HIGH)
+		return -EINVAL;
+
+	config = container_of(gadget, struct phytium_cusb, gadget);
+
+	pr_info("registering driver %s\n", driver->function);
+
+	spin_lock_irqsave(&config->lock, flags);
+	config->gadget_driver = driver;
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	config->gadget_obj->gadget_start(config->gadget_priv);
+
+	priv = (struct GADGET_CTRL *)config->gadget_priv;
+	if (priv->phy_regs) {
+		gen_cfg = phytium_read32(&priv->phy_regs->gen_cfg);
+		gen_cfg = gen_cfg & (~BIT(7));
+		phytium_write32(&priv->phy_regs->gen_cfg, gen_cfg);
+	}
+
+	return 0;
+}
+
+static int gadget_udc_stop(struct usb_gadget *gadget)
+{
+	struct phytium_cusb *config;
+	unsigned long flags;
+	struct GADGET_CTRL *priv;
+	uint32_t gen_cfg;
+
+	if (!gadget)
+		return -EINVAL;
+
+	config = container_of(gadget, struct phytium_cusb, gadget);
+
+	priv = (struct GADGET_CTRL *)config->gadget_priv;
+	if (priv->phy_regs) {
+		gen_cfg = phytium_read32(&priv->phy_regs->gen_cfg);
+		gen_cfg = gen_cfg | BIT(7);
+		phytium_write32(&priv->phy_regs->gen_cfg, gen_cfg);
+	}
+	spin_lock_irqsave(&config->lock, flags);
+	config->gadget_driver = NULL;
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+static struct usb_gadget_ops phytium_gadget_ops = {
+	.get_frame	=	gadget_get_frame,
+	.wakeup		=	gadget_wakeup,
+	.vbus_session	=	gadget_vbus_session,
+	.vbus_draw	=	gadget_vbus_draw,
+	.pullup		=	gadget_pullup,
+	.udc_start	=	gadget_udc_start,
+	.udc_stop	=	gadget_udc_stop,
+};
+
+static int gadget_ep_enable(struct usb_ep *ls_ep, const struct usb_endpoint_descriptor *desc)
+{
+	struct phytium_ep *phy_ep = NULL;
+	struct phytium_cusb *config;
+	unsigned long flags;
+
+	if (!ls_ep || !desc)
+		return -EINVAL;
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+
+	if (phy_ep->desc)
+		return -EBUSY;
+
+	spin_lock_irqsave(&config->lock, flags);
+
+	phy_ep->desc = desc;
+	phy_ep->busy = 0;
+	config->gadget_obj->gadget_epEnable(config->gadget_priv, phy_ep->gadget_ep, desc);
+
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+static int gadget_ep_disable(struct usb_ep *ls_ep)
+{
+	struct phytium_ep *phy_ep = NULL;
+	struct phytium_cusb *config;
+	unsigned long flags;
+
+	if (!ls_ep)
+		return -EBUSY;
+
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+
+	spin_lock_irqsave(&config->lock, flags);
+
+	phy_ep->desc = NULL;
+	phy_ep->busy = 0;
+	phy_ep->end_point.desc = NULL;
+	config->gadget_obj->gadget_epDisable(config->gadget_priv, phy_ep->gadget_ep);
+
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+static struct usb_request *gadget_ep_alloc_request(struct usb_ep *ls_ep, gfp_t gfp_flags)
+{
+	struct phytium_ep *phy_ep;
+	struct phytium_cusb *config;
+	struct GADGET_EP *gadget_ep;
+	struct phytium_request *phy_request;
+
+	if (!ls_ep)
+		return NULL;
+
+	pr_info("%s %d\n", __func__, __LINE__);
+	phy_request = kzalloc(sizeof(*phy_request), gfp_flags);
+	if (!phy_request) {
+		pr_err("not enough momory\n");
+		return NULL;
+	}
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+	gadget_ep = phy_ep->gadget_ep;
+
+	INIT_LIST_HEAD(&phy_request->list);
+	phy_request->request.dma = DMA_ADDR_INVALID;
+	phy_request->epnum = phy_ep->ep_num;
+	phy_request->ep = phy_ep;
+	phy_request->config = phy_ep->config;
+
+	config->gadget_obj->gadget_reqAlloc(config->gadget_priv, gadget_ep,
+						&phy_request->gadget_request);
+
+	return &phy_request->request;
+}
+
+static void gadget_ep_free_request(struct usb_ep *ls_ep, struct usb_request *ls_req)
+{
+	struct phytium_ep *phy_ep;
+	struct phytium_cusb *config;
+	struct phytium_request *phy_request;
+
+	if (!ls_ep || !ls_req)
+		return;
+
+	pr_info("%s %d\n", __func__, __LINE__);
+	phy_request = ls_req ? container_of(ls_req, struct phytium_request, request) : NULL;
+	config = phy_request->config;
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+
+	config->gadget_obj->gadget_reqFree(config->gadget_priv, phy_ep->gadget_ep,
+						phy_request->gadget_request);
+	kfree(phy_request);
+}
+
+static int gadget_ep_enqueue(struct usb_ep *ls_ep, struct usb_request *ls_req, gfp_t gfp_flags)
+{
+	struct phytium_ep *phy_ep;
+	struct phytium_cusb *config;
+	struct phytium_request *phy_request;
+	unsigned long flags;
+	int status = 0;
+
+	if (!ls_ep || !ls_req)
+		return -EINVAL;
+
+	if (!ls_req->buf)
+		return -ENODATA;
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+	phy_request = ls_req ? container_of(ls_req, struct phytium_request, request) : NULL;
+	phy_request->config = config;
+
+	if (phy_request->ep != phy_ep)
+		return -EINVAL;
+
+	phy_request->request.actual = 0;
+	phy_request->request.status = -EINPROGRESS;
+	phy_request->epnum = phy_ep->ep_num;
+	phy_request->is_tx = phy_ep->is_tx;
+
+	phy_request->gadget_request->length = ls_req->length;
+	phy_request->gadget_request->status = 0;
+	phy_request->gadget_request->complete = gadget_callback_complete;
+	phy_request->gadget_request->buf = ls_req->buf;
+	phy_request->gadget_request->context = ls_req;
+
+	status = usb_gadget_map_request(&config->gadget, &phy_request->request, phy_request->is_tx);
+
+	if (!phy_ep->desc) {
+		pr_debug("req %p queued to %s while ep %s\n", phy_request, ls_ep->name, "disabled");
+		status = -ESHUTDOWN;
+		usb_gadget_unmap_request(&config->gadget, &phy_request->request,
+					phy_request->is_tx);
+		return status;
+	}
+
+	spin_lock_irqsave(&config->lock, flags);
+
+	phy_request->gadget_request->dma = phy_request->request.dma;
+	list_add_tail(&phy_request->list, &phy_ep->req_list);
+
+	pr_debug("queue to %s (%s), length = %d\n", phy_ep->name,
+			phy_ep->is_tx ? "IN/TX" : "OUT/RX", phy_request->request.length);
+
+	status = config->gadget_obj->gadget_reqQueue(config->gadget_priv, phy_ep->gadget_ep,
+							phy_request->gadget_request);
+
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return status;
+}
+
+static int gadget_ep_dequeue(struct usb_ep *ls_ep, struct usb_request *ls_req)
+{
+	struct phytium_ep *phy_ep;
+	struct phytium_cusb *config;
+	unsigned long flags;
+	int status = 0;
+	struct phytium_request *phy_request;
+	struct phytium_request *phy_next_request;
+
+	if (!ls_ep || !ls_req)
+		return -EINVAL;
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+	phy_request = ls_req ? container_of(ls_req, struct phytium_request, request) : NULL;
+
+	if (phy_request->ep != phy_ep)
+		return -EINVAL;
+
+	spin_lock_irqsave(&config->lock, flags);
+
+	list_for_each_entry(phy_next_request, &phy_ep->req_list, list) {
+		if (phy_next_request == phy_request)
+			break;
+	}
+
+	if (phy_next_request != phy_request) {
+		pr_info("request %p not queued to %s\n", phy_request, ls_ep->name);
+		status = -EINVAL;
+		goto done;
+	}
+
+	status = config->gadget_obj->gadget_reqDequeue(config->gadget_priv, phy_ep->gadget_ep,
+							phy_request->gadget_request);
+done:
+	spin_unlock_irqrestore(&config->lock, flags);
+	return status;
+}
+
+static int gadget_ep_set_halt(struct usb_ep *ls_ep, int value)
+{
+	struct phytium_ep *phy_ep;
+	struct phytium_cusb *config;
+	struct GADGET_EP *gadget_ep = NULL;
+	unsigned long flags;
+	int status = 0;
+
+	if (!ls_ep)
+		return -EINVAL;
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+	gadget_ep = phy_ep->gadget_ep;
+
+	spin_lock_irqsave(&config->lock, flags);
+
+	status = config->gadget_obj->gadget_epSetHalt(config->gadget_priv,
+							phy_ep->gadget_ep, value);
+	if (status > 0) {
+		spin_unlock_irqrestore(&config->lock, flags);
+		return -status;
+	}
+
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+static const struct usb_ep_ops  gadget_ep_ops = {
+	.enable		=	gadget_ep_enable,
+	.disable	=	gadget_ep_disable,
+	.alloc_request	=	gadget_ep_alloc_request,
+	.free_request	=	gadget_ep_free_request,
+	.queue		=	gadget_ep_enqueue,
+	.dequeue	=	gadget_ep_dequeue,
+	.set_halt	=	gadget_ep_set_halt,
+};
+
+static int gadget_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
+{
+	return -EINVAL;
+}
+
+static int gadget_ep0_disable(struct usb_ep *ep)
+{
+	return -EINVAL;
+}
+
+static int gadget_ep0_enqueue(struct usb_ep *ls_ep, struct usb_request *ls_req, gfp_t gfp_flags)
+{
+	struct phytium_ep *phy_ep;
+	struct phytium_request *phy_request;
+	struct phytium_cusb *config;
+	int status = 0;
+	unsigned long flags;
+
+	if (!ls_ep || !ls_req)
+		return -EINVAL;
+
+	phy_ep = ls_ep ? container_of(ls_ep, struct phytium_ep, end_point) : NULL;
+	config = phy_ep->config;
+	phy_request = ls_req ? container_of(ls_req, struct phytium_request, request) : NULL;
+
+	spin_lock_irqsave(&config->lock, flags);
+
+	if (!list_empty(&phy_ep->req_list)) {
+		status = -EBUSY;
+		goto cleanup;
+	}
+
+	phy_request->config = config;
+	phy_request->request.actual = 0;
+	phy_request->gadget_request->actual = 0;
+	phy_request->is_tx = config->ep0_data_stage_is_tx;
+	phy_request->gadget_request->length = phy_request->request.length;
+	phy_request->gadget_request->status = 0;
+	phy_request->gadget_request->complete = gadget_callback_complete;
+	phy_request->gadget_request->buf = phy_request->request.buf;
+	phy_request->gadget_request->context = phy_request;
+
+	status = usb_gadget_map_request(&config->gadget, &phy_request->request, phy_request->is_tx);
+	if (status) {
+		pr_info("failed to map request\n");
+		status = -EINVAL;
+		goto cleanup;
+	}
+
+	phy_request->gadget_request->dma = phy_request->request.dma;
+	list_add_tail(&phy_request->list, &phy_ep->req_list);
+
+	pr_debug("queue to %s (%s), length = %d\n", phy_ep->name,
+			phy_ep->is_tx ? "IN/TX" : "OUT/RX", phy_request->request.length);
+
+	status = config->gadget_obj->gadget_reqQueue(config->gadget_priv, phy_ep->gadget_ep,
+							phy_request->gadget_request);
+	if (status > 0) {
+		status = -status;
+		usb_gadget_unmap_request(&config->gadget, &phy_request->request,
+					phy_request->is_tx);
+		list_del(&phy_request->list);
+		goto cleanup;
+	}
+
+cleanup:
+	spin_unlock_irqrestore(&config->lock, flags);
+	return status;
+}
+
+static int gadget_ep0_dequeue(struct usb_ep *ep, struct usb_request *ls_request)
+{
+	return -EOPNOTSUPP;
+}
+
+static int gadget_ep0_set_halt(struct usb_ep *ep, int value)
+{
+	return -EINVAL;
+}
+
+
+static const struct usb_ep_ops  gadget_ep0_ops = {
+	.enable		=	gadget_ep0_enable,
+	.disable	=	gadget_ep0_disable,
+	.alloc_request	=	gadget_ep_alloc_request,
+	.free_request	=	gadget_ep_free_request,
+	.queue		=	gadget_ep0_enqueue,
+	.dequeue	=	gadget_ep0_dequeue,
+	.set_halt	=	gadget_ep0_set_halt,
+};
+
+static int32_t gadgetWaitForBusyBit(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep)
+{
+	struct GadgetEp *gadgetEp;
+	uint8_t epNum;
+	uint8_t txcs = CS_BUSY;
+	uint8_t buf = 0;
+	uint8_t bufflag = 0;
+
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	epNum = gadgetEp->hwEpNum;
+
+	if (gadgetEp->isInEp || gadgetEp->hwEpNum == 0)
+		return 0;
+
+	buf = phytium_read8(&priv->regs->ep[epNum - 1].txcon) & CON_BUF;
+
+	while ((txcs & CS_BUSY) || (bufflag == 0)) {
+		txcs = phytium_read8(&priv->regs->ep[epNum - 1].txcs);
+
+		if (((txcs & CS_NPAK) >> CS_NPAK_OFFSET) == buf || buf == 0)
+			bufflag = 1;
+		else
+			bufflag = 0;
+	}
+
+	return 0;
+}
+
+static inline void gadgetEpXDataReceive(struct GADGET_CTRL *priv,
+					struct GadgetRequest *gadgetRequest)
+{
+	struct GadgetEp *gadgetEp;
+	struct GADGET_REQ *gadgetReq;
+	uint8_t epType;
+	uint32_t requestSize, channelStatus, chMaxLen;
+
+	if (!priv || !gadgetRequest)
+		return;
+
+	gadgetEp = gadgetRequest->ep;
+	chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, gadgetEp->channel);
+	epType = gadgetEp->gadgetEp.desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	channelStatus = priv->dmaDrv->dma_getChannelStatus(priv->dmaController, gadgetEp->channel);
+
+	gadgetReq = &gadgetRequest->request;
+	if (gadgetReq->actual < gadgetReq->length || gadgetRequest->zlp) {
+		gadgetRequest->zlp = 0;
+		if ((gadgetReq->length - gadgetReq->actual) < chMaxLen)
+			requestSize = gadgetReq->length - gadgetReq->actual;
+		else
+			requestSize = chMaxLen;
+
+		priv->dmaDrv->dma_channelProgram(priv->dmaController, gadgetEp->channel,
+				gadgetEp->gadgetEp.maxPacket,
+				gadgetReq->dma + gadgetReq->actual, requestSize, NULL, 0);
+	}
+}
+
+static inline void gadgetEpXDataSend(struct GADGET_CTRL *priv, struct GadgetRequest *gadgetRequest)
+{
+	struct GadgetEp *gadgetEp;
+	struct GADGET_REQ *gadgetReq;
+	uint8_t epType;
+	uint32_t requestSize, channelStatus, chMaxLen;
+
+	if (!priv || !gadgetRequest)
+		return;
+
+	gadgetEp = gadgetRequest->ep;
+	chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, gadgetEp->channel);
+	epType = gadgetEp->gadgetEp.desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	channelStatus = priv->dmaDrv->dma_getChannelStatus(priv->dmaController, gadgetEp->channel);
+
+	gadgetReq = &gadgetRequest->request;
+	if ((gadgetReq->length - gadgetReq->actual) < chMaxLen)
+		requestSize = gadgetReq->length - gadgetReq->actual;
+	else
+		requestSize = chMaxLen;
+	pr_debug("Transmit/IN %s gadgetReq %p gadgetRequest:%p requestSize:0x%x packetSize:0x%x\n",
+		       gadgetEp->gadgetEp.name, gadgetReq, gadgetRequest,
+		       requestSize, gadgetEp->gadgetEp.maxPacket);
+
+	gadgetRequest->zlp = 0;
+	priv->dmaDrv->dma_channelProgram(priv->dmaController, gadgetEp->channel,
+				gadgetEp->gadgetEp.maxPacket,
+				gadgetReq->dma + gadgetReq->actual, requestSize, NULL, 0);
+}
+
+static int32_t gadgetEpXSetHalt(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+				uint8_t value)
+{
+	struct GadgetEp *gadgetEp;
+	uint8_t epType;
+	struct GADGET_REQ *req = NULL;
+	struct GadgetRequest *gadgetRequest = NULL;
+	uint8_t epNum, txcon, rxcon;
+	uint32_t status = DMA_STATUS_ARMED;
+
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	epType = gadgetEp->gadgetEp.desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	if (epType == USB_ENDPOINT_XFER_ISOC)
+		return -EINVAL;
+
+	pr_debug("%s: %s stall\n", gadget_Ep->name, value ? "set" : "clear");
+	req = gadgetGetNextReq(gadgetEp);
+
+	if (!value)
+		gadgetEp->wedged = 0;
+
+	if (value && gadgetEp->isInEp && req && gadgetEp->state == GADGET_EP_BUSY) {
+		while (status == DMA_STATUS_ARMED)
+			status = priv->dmaDrv->dma_getChannelStatus(priv->dmaController,
+									gadgetEp->channel);
+
+		gadgetWaitForBusyBit(priv, gadget_Ep);
+	}
+
+	epNum = gadgetEp->hwEpNum;
+
+	if (gadgetEp->isInEp) {
+		txcon = phytium_read8(&priv->regs->ep[epNum - 1].txcon);
+		if (value) {
+			phytium_write8(&priv->regs->ep[epNum - 1].txcon, txcon | CON_STALL);
+			phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX | epNum);
+			phytium_write8(&priv->regs->endprst,
+					ENDPRST_IO_TX | epNum | ENDPRST_FIFORST);
+
+		} else {
+			phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX | epNum);
+			phytium_write8(&priv->regs->endprst,
+					ENDPRST_IO_TX | epNum | ENDPRST_TOGRST);
+			phytium_write8(&priv->regs->ep[epNum - 1].txcon, txcon & (~CON_STALL));
+		}
+	} else {
+		rxcon = phytium_read8(&priv->regs->ep[epNum - 1].rxcon);
+		if (value) {
+			phytium_write8(&priv->regs->ep[epNum - 1].rxcon, rxcon | CON_STALL);
+			phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX | epNum);
+			phytium_write8(&priv->regs->endprst, epNum | ENDPRST_FIFORST);
+		} else {
+			phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX | epNum);
+			phytium_write8(&priv->regs->endprst,
+					epNum | ENDPRST_TOGRST | ENDPRST_FIFORST);
+			phytium_write8(&priv->regs->ep[epNum - 1].rxcon, rxcon & (~CON_STALL));
+		}
+	}
+
+	if (gadgetEp->state != GADGET_EP_BUSY && !value && req) {
+		gadgetRequest = requestToGadgetRequest(req);
+		if (gadgetEp->isInEp)
+			gadgetEpXDataSend(priv, gadgetRequest);
+		else
+			gadgetEpXDataReceive(priv, gadgetRequest);
+	}
+
+	return 0;
+}
+
+static int32_t gadgetEp0SetHalt(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+				uint8_t value)
+{
+	struct GadgetEp *gadgetEp;
+
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	if (!list_empty(&gadgetEp->request))
+		return -EBUSY;
+
+	switch (priv->ep0State) {
+	case GADGET_EP0_STAGE_IN:
+	case GADGET_EP0_STAGE_OUT:
+	case GADGET_EP0_STAGE_ACK:
+	case GADGET_EP0_STAGE_STATUSIN:
+	case GADGET_EP0_STAGE_STATUSOUT:
+		priv->ep0State = GADGET_EP0_STAGE_SETUP;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+
+static void gadgetEp0Callback(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		struct GADGET_REQ *req, uint8_t status)
+{
+	if (!priv || !gadgetEp || !req)
+		return;
+
+	priv->ep0State = GADGET_EP0_STAGE_SETUP;
+	list_del(&req->list);
+	gadgetEp->requestsInList--;
+
+	if (req->status == EINPROGRESS)
+		req->status = status;
+
+	if (req->complete)
+		req->complete(&gadgetEp->gadgetEp, req);
+}
+
+static enum usb_device_speed gadgetGetActualSpeed(struct GADGET_CTRL *priv)
+{
+	uint8_t speedctrl;
+
+	if (!priv)
+		return USB_SPEED_UNKNOWN;
+
+	speedctrl = phytium_read8(&priv->regs->speedctrl) & (~SPEEDCTRL_HSDISABLE);
+	switch (speedctrl) {
+	case SPEEDCTRL_HS:
+		return USB_SPEED_HIGH;
+	case SPEEDCTRL_FS:
+		return USB_SPEED_FULL;
+	case SPEEDCTRL_LS:
+		return USB_SPEED_LOW;
+	default:
+		return USB_SPEED_UNKNOWN;
+	}
+}
+
+static int32_t gadgetServiceSetFeatureReq(struct GADGET_CTRL *priv, struct usb_ctrlrequest *setup)
+{
+	uint8_t epNum, isIn;
+	struct GadgetEp *gadgetEp;
+
+	if (!priv || !setup)
+		return 0;
+
+	switch (setup->bRequestType & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		switch (setup->wValue) {
+		case USB_DEVICE_REMOTE_WAKEUP:
+			pr_info("set feature - remote wakup\n");
+			priv->isRemoteWakeup = 1;
+			break;
+		case USB_DEVICE_B_HNP_ENABLE:
+			pr_info("set feature - B HNP Enable\n");
+			pr_info("otg not implement\n");
+			return -EINVAL;
+		case USB_DEVICE_A_HNP_SUPPORT:
+			pr_info("set feature - A HNP support\n");
+			pr_info("otg not implete\n");
+			return -EINVAL;
+		}
+		break;
+	case USB_RECIP_INTERFACE:
+		break;
+	case USB_RECIP_ENDPOINT:
+		epNum = setup->wIndex & 0x0f;
+		isIn = setup->wIndex & USB_DIR_IN;
+		if (epNum == 0 || epNum > 15 || setup->wValue != 0)
+			return -EINVAL;
+
+		gadgetEp = isIn ? &priv->in[epNum] : &priv->out[epNum];
+
+		gadgetEpXSetHalt(priv, &gadgetEp->gadgetEp, 1);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int32_t gadgetServiceClearFeatureReq(struct GADGET_CTRL *priv, struct usb_ctrlrequest *setup)
+{
+	uint8_t epNum, isIn;
+	struct GadgetEp *gadgetEp;
+
+	if (!priv || !setup)
+		return -EINVAL;
+
+	switch (setup->bRequestType & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		if (setup->wValue == USB_DEVICE_B_HNP_ENABLE) {
+			pr_err("otg not implement\n");
+			return -EINVAL;
+		}
+
+		if (setup->wValue != USB_DEVICE_REMOTE_WAKEUP)
+			return GADGET_EUNHANDLED;
+
+		priv->isRemoteWakeup = 0;
+		return GADGET_EAUTOACK;
+	case USB_RECIP_INTERFACE:
+		break;
+	case USB_RECIP_ENDPOINT:
+		pr_info("clear feature wIndex:0x%x wValue:0x%x\n", setup->wIndex, setup->wValue);
+		epNum = setup->wIndex & 0x7f;
+		isIn = setup->wIndex & USB_DIR_IN;
+		if (epNum == 0 || epNum > 15 || setup->wValue != 0)
+			return GADGET_EUNHANDLED;
+
+		gadgetEp = isIn ? &priv->in[epNum] : &priv->out[epNum];
+		if (!gadgetEp->gadgetEp.desc)
+			return -EINVAL;
+
+		if (gadgetEp->wedged)
+			break;
+		gadgetEpXSetHalt(priv, &gadgetEp->gadgetEp, 0);
+		break;
+	default:
+		return GADGET_EUNHANDLED;
+	}
+
+	return 0;
+}
+
+static int32_t gadgetServiceSetupReq(struct GADGET_CTRL *priv, struct usb_ctrlrequest *setup)
+{
+	struct GadgetEp *gadgetEp;
+	uint8_t isIn, epNum;
+	uint8_t rxcon, txcon;
+	int len;
+
+	if (!priv || !setup)
+		return -EINVAL;
+
+	if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+		if (setup->bRequest != USB_REQ_GET_STATUS)
+			return GADGET_EUNHANDLED;
+	} else
+		return GADGET_EUNHANDLED;
+
+	priv->privBuffAddr[1] = 0;
+	priv->privBuffAddr[0] = 0;
+
+	switch (setup->bRequest & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		pr_info("wIndex:0x%x isSelfPowered:%d isRomoteWakeup:%d\n",
+				setup->wIndex, priv->isSelfPowered, priv->isRemoteWakeup);
+
+		if (setup->wIndex == OTG_STS_SELECTOR)
+			priv->privBuffAddr[0] = priv->hostRequestFlag;
+		else {
+			priv->privBuffAddr[0] = priv->isSelfPowered ? USB_DEVICE_SELF_POWERED : 0;
+			priv->privBuffAddr[1] = priv->isRemoteWakeup ? USB_DEVICE_REMOTE_WAKEUP : 0;
+		}
+		break;
+	case USB_RECIP_INTERFACE:
+		break;
+	case USB_RECIP_ENDPOINT:
+		epNum = setup->wIndex & 0x0f;
+		if (!epNum)
+			break;
+
+		isIn = setup->wIndex & USB_DIR_IN;
+
+		gadgetEp = isIn ? &priv->in[epNum] : &priv->out[epNum];
+		if (!gadgetEp->gadgetEp.desc)
+			return -EINVAL;
+
+		if (isIn) {
+			txcon = phytium_read8(&priv->regs->ep[epNum - 1].txcon);
+			priv->privBuffAddr[0] = (txcon & CON_STALL) ? 1 : 0;
+		} else {
+			rxcon = phytium_read8(&priv->regs->ep[epNum - 1].rxcon);
+			priv->privBuffAddr[0] = (rxcon & CON_STALL) ? 1 : 0;
+		}
+		break;
+	default:
+		return GADGET_EUNHANDLED;
+	}
+
+	len = setup->wLength;
+	if (len > 2)
+		len = 2;
+
+	priv->dmaDrv->dma_channelProgram(priv->dmaController, priv->in[0].channel,
+			priv->in[0].gadgetEp.maxPacket, priv->privBuffDma, len, NULL, 0);
+
+	return 0;
+}
+
+static int32_t gadgetGetSetup(struct GADGET_CTRL *priv, struct usb_ctrlrequest *setup)
+{
+	int i;
+	uint8_t ep0cs;
+	struct GADGET_REQ *request = NULL;
+	struct GadgetRequest *gadgetRequest;
+
+	if (!priv || !setup)
+		return -EINVAL;
+
+	phytium_write8(&priv->regs->ep0cs, EP0CS_CHGSET);
+
+	for (i = 0; i < 8; i++)
+		((char *)setup)[i] = phytium_read8(&priv->regs->setupdat[i]);
+
+	ep0cs = phytium_read8(&priv->regs->ep0cs);
+	if (ep0cs & EP0CS_CHGSET) {
+		pr_info("setup flags change: not error\n");
+		return GADGET_EAUTOACK;
+	}
+
+	phytium_write8(&priv->regs->usbirq, USBIR_SUDAV);
+	pr_debug("setup packet: req%02x.%02x v:%04x i:%04x I%d\n", setup->bRequestType,
+			setup->bRequest, setup->wValue, setup->wIndex, setup->wLength);
+
+	request = gadgetGetNextEp0Req(priv);
+	if (request) {
+		gadgetRequest = requestToGadgetRequest(request);
+		pr_info("Previous request has not been finished but new was received\n");
+		gadgetEp0Callback(priv, gadgetRequest->ep, request, 0);
+	}
+
+	if (setup->wLength) {
+		if (setup->bRequestType & USB_DIR_IN)
+			priv->ep0State = GADGET_EP0_STAGE_IN;
+		else
+			priv->ep0State = GADGET_EP0_STAGE_OUT;
+	} else
+		priv->ep0State = GADGET_EP0_STAGE_ACK;
+
+	return 0;
+}
+
+static void gadgetEp0StageSetup(struct GADGET_CTRL *priv)
+{
+	struct usb_ctrlrequest setup;
+	int32_t retval;
+	uint8_t ep0cs;
+
+	if (!priv)
+		return;
+
+	retval = gadgetGetSetup(priv, &setup);
+
+	priv->gadgetDev.speed = gadgetGetActualSpeed(priv);
+
+	switch (priv->ep0State) {
+	case GADGET_EP0_STAGE_ACK:
+		if ((setup.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
+			retval = GADGET_EUNHANDLED;
+		else {
+			switch (setup.bRequest) {
+			case USB_REQ_SET_ADDRESS:
+				priv->deviceAddress = setup.wValue & 0x7F;
+				priv->gadgetDev.state = USB_STATE_ADDRESS;
+				pr_info("set address: %d\n", priv->deviceAddress);
+				retval = GADGET_EAUTOACK;
+				break;
+			case USB_REQ_SET_FEATURE:
+				retval = gadgetServiceSetFeatureReq(priv, &setup);
+				break;
+			case USB_REQ_CLEAR_FEATURE:
+				retval = gadgetServiceClearFeatureReq(priv, &setup);
+				break;
+			default:
+				retval = GADGET_EUNHANDLED;
+				break;
+			}
+		}
+
+		if (retval == GADGET_EUNHANDLED)
+			break;
+		else if (retval == 0)
+			phytium_write8(&priv->regs->ep0cs, EP0CS_HSNAK);
+
+		priv->ep0State = GADGET_EP0_STAGE_SETUP;
+		break;
+	case GADGET_EP0_STAGE_IN:
+		pr_debug("setup data stage in\n");
+		retval = gadgetServiceSetupReq(priv, &setup);
+
+		if (retval == 0)
+			priv->ep0State = GADGET_EP0_STAGE_STATUSOUT;
+		break;
+	case GADGET_EP0_STAGE_OUT:
+		pr_debug("setup data stage out\n");
+		phytium_write8(&priv->regs->ep0Rxbc, 0);
+		retval = GADGET_EUNHANDLED;
+		break;
+	default:
+		if (retval == GADGET_EAUTOACK)
+			return;
+
+		pr_debug("forward request\n");
+		retval = GADGET_EUNHANDLED;
+		break;
+	}
+
+	if (retval == GADGET_EUNHANDLED) {
+		if (priv->eventCallback.setup)
+			retval = priv->eventCallback.setup(priv, &setup);
+
+		if (retval == 0x7FFF) {
+			pr_debug("Respond Delayed not finished yet\n");
+			return;
+		}
+
+		if (retval)
+			retval = GADGET_ESTALL;
+	}
+
+	if (retval == GADGET_EUNHANDLED || retval == GADGET_ESTALL) {
+		pr_debug("request not handled - send stall\n");
+		ep0cs = phytium_read8(&priv->regs->ep0cs);
+		ep0cs |= EP0CS_STALL;
+		phytium_write8(&priv->regs->ep0cs, ep0cs);
+		priv->ep0State = GADGET_EP0_STAGE_SETUP;
+	} else if (priv->ep0State == GADGET_EP0_STAGE_ACK) {
+		priv->ep0State = GADGET_EP0_STAGE_SETUP;
+		phytium_write8(&priv->regs->ep0cs, EP0CS_HSNAK);
+		pr_debug("setup transfer completed\n");
+	}
+}
+static void gadgetEp0DataSend(struct GADGET_CTRL *priv)
+{
+	struct GADGET_REQ *request;
+	uint32_t chMaxLen, requestSize;
+
+	if (!priv)
+		return;
+
+	request = gadgetGetNextEp0Req(priv);
+	if (!request) {
+		pr_debug("Ep0 queue is empty\n");
+		return;
+	}
+
+	if (priv->dmaDrv->dma_getChannelStatus(priv->dmaController, priv->in[0].channel)
+						>= DMA_STATUS_BUSY) {
+		pr_err("transfer is pending now\n");
+		return;
+	}
+
+	chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, priv->in[0].channel);
+	requestSize = (request->length < chMaxLen) ? request->length : chMaxLen;
+	pr_debug("usbRequest;%p requestSize:%d packetSize:%d\n", request, requestSize,
+			priv->in[0].gadgetEp.maxPacket);
+	priv->ep0State = GADGET_EP0_STAGE_STATUSOUT;
+
+	priv->dmaDrv->dma_channelProgram(priv->dmaController, priv->in[0].channel,
+			priv->in[0].gadgetEp.maxPacket, request->dma, requestSize, NULL, 0);
+}
+
+static void gadgetEp0DataReceive(struct GADGET_CTRL *priv)
+{
+	uint32_t chMaxLen, requestSize;
+	struct GADGET_REQ *request;
+
+	if (!priv)
+		return;
+
+	request = gadgetGetNextEp0Req(priv);
+	if (!request) {
+		pr_debug("Ep0 queue is empty\n");
+		return;
+	}
+
+	chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, priv->out[0].channel);
+	requestSize = (request->length < chMaxLen) ? request->length : chMaxLen;
+	pr_debug("usbRequest;%p requestSize:%d packetSize:%d\n", request, requestSize,
+			priv->out[0].gadgetEp.maxPacket);
+	priv->ep0State = GADGET_EP0_STAGE_STATUSIN;
+
+	priv->dmaDrv->dma_channelProgram(priv->dmaController, priv->out[0].channel,
+			priv->out[0].gadgetEp.maxPacket, request->dma, requestSize, NULL, 0);
+}
+
+static uint32_t gadgetEp0Irq(struct GADGET_CTRL *priv)
+{
+	uint8_t usbcs;
+	struct GADGET_REQ *request;
+
+	if (!priv)
+		return 0;
+
+	switch (priv->ep0State) {
+	case GADGET_EP0_STAGE_IN://send data
+		pr_debug("DATA Stage IN\n");
+		gadgetEp0DataSend(priv);
+		break;
+	case GADGET_EP0_STAGE_OUT://receive data
+		pr_debug("DATA Stage OUT\n");
+		gadgetEp0DataReceive(priv);
+		break;
+	case GADGET_EP0_STAGE_STATUSIN:
+		pr_debug("DATA Stage STATUS IN\n");
+		request = gadgetGetNextEp0Req(priv);
+		if (request)
+			request->actual = priv->dmaDrv->dma_getActualLength(priv->dmaController,
+								priv->out[0].channel);
+
+		priv->ep0State = GADGET_EP0_STAGE_SETUP;
+		phytium_write8(&priv->regs->ep0cs, EP0CS_HSNAK);
+		gadgetEp0Callback(priv, &priv->out[0], request, 0);
+		break;
+	case GADGET_EP0_STAGE_STATUSOUT:
+		pr_debug("DATA Stage STATUS OUT\n");
+		request = gadgetGetNextEp0Req(priv);
+		if (request)
+			request->actual = priv->dmaDrv->dma_getActualLength(priv->dmaController,
+								priv->in[0].channel);
+
+		phytium_write8(&priv->regs->ep0cs, EP0CS_HSNAK);
+		if (request)
+			gadgetEp0Callback(priv, &priv->in[0], request, 0);
+		else
+			priv->ep0State = GADGET_EP0_STAGE_SETUP;
+		break;
+	case GADGET_EP0_STAGE_SETUP:
+		pr_debug("DATA Stage SETUP\n");
+		gadgetEp0StageSetup(priv);
+		break;
+	case GADGET_EP0_STAGE_ACK:
+		pr_debug("DATA Stage ACK\n");
+		break;
+	default:
+		pr_debug("DATA Stage UNKNOWN\n");
+		usbcs = phytium_read8(&priv->regs->usbcs);
+		usbcs |= EP0CS_STALL;
+		phytium_write8(&priv->regs->usbcs, usbcs);
+		break;
+	}
+
+	return 0;
+}
+
+static void gadgetEpXCallback(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		struct GADGET_REQ *req, uint32_t status)
+{
+	if (!gadgetEp || !req)
+		return;
+
+	list_del(&req->list);
+	gadgetEp->requestsInList--;
+	req->status = status;
+
+	if (req->complete)
+		req->complete(&gadgetEp->gadgetEp, req);
+}
+
+static void gadgetEpXDataCallback(struct GADGET_CTRL *priv, uint8_t epNum, uint8_t epDir)
+{
+	struct GadgetEp *gadgetEp;
+	struct GADGET_REQ *gadgetReq;
+	uint32_t actual_length = 0;
+	uint32_t chMaxLen = 0;
+	uint8_t epType;
+
+	if (!priv)
+		return;
+
+	pr_debug("%s %d epNum:%d epDir:%d\n", __func__, __LINE__, epNum, epDir);
+	gadgetEp = epDir ? &priv->in[epNum] : &priv->out[epNum];
+
+	gadgetReq = gadgetGetNextReq(gadgetEp);
+	if (!gadgetReq) {
+		pr_debug("%s queue is empty\n", gadgetEp->gadgetEp.name);
+		return;
+	}
+
+	if (gadgetEp->channel) {
+		actual_length = priv->dmaDrv->dma_getActualLength(priv->dmaController,
+				gadgetEp->channel);
+		chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, gadgetEp->channel);
+		gadgetReq->actual += actual_length;
+	}
+
+	if (gadgetReq->actual == gadgetReq->length || actual_length < chMaxLen) {
+		gadgetEpXCallback(priv, gadgetEp, gadgetReq, 0);
+
+		if (gadgetEp->gadgetEp.desc) {
+			epType = gadgetEp->gadgetEp.desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+			if (epType == USB_ENDPOINT_XFER_ISOC)
+				return;
+
+			gadgetReq = gadgetGetNextReq(gadgetEp);
+			gadgetEp->state = GADGET_EP_ALLOCATED;
+			if (!gadgetReq) {
+				pr_debug("%s queue is empty\n", gadgetEp->gadgetEp.name);
+				return;
+			}
+			gadgetEp->state = GADGET_EP_BUSY;
+			if (epDir)
+				gadgetEpXDataSend(priv, requestToGadgetRequest(gadgetReq));
+			else
+				gadgetEpXDataReceive(priv, requestToGadgetRequest(gadgetReq));
+		}
+	} else {
+		if (epDir)
+			gadgetEpXDataSend(priv, requestToGadgetRequest(gadgetReq));
+		else
+			gadgetEpXDataReceive(priv, requestToGadgetRequest(gadgetReq));
+	}
+}
+
+void gadget_CallbackTransfer(void *priv, uint8_t epNum, uint8_t epDir, bool resubmit)
+{
+	if (!epNum)
+		gadgetEp0Irq(priv);
+	else
+		gadgetEpXDataCallback(priv, epNum, epDir);
+}
+
+static void gadgetAbortEndpoint(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp)
+{
+	struct GADGET_REQ *gadgetReq;
+
+	pr_debug("Abort Device endpoint: %s, dma channel: %p\n", gadgetEp->gadgetEp.name,
+			gadgetEp->channel);
+
+	if (gadgetEp->channel && gadgetEp->hwEpNum != 0) {
+		priv->dmaDrv->dma_channelRelease(priv->dmaController, gadgetEp->channel);
+		gadgetEp->channel = NULL;
+	}
+
+	if (gadgetEp->channel && gadgetEp->hwEpNum == 0) {
+		if (priv->releaseEp0Flag == 1) {
+			priv->dmaDrv->dma_channelAbort(priv->dmaController, gadgetEp->channel);
+			priv->dmaDrv->dma_channelAlloc(priv->dmaController, gadgetEp->isInEp,
+					gadgetEp->hwEpNum, 0);
+		}
+	}
+
+	while (gadgetEp->request.next != &gadgetEp->request) {
+		gadgetReq = listToGadgetRequest(gadgetEp->request.next);
+		pr_debug("shutdown request %p form epName:%s\n", gadgetReq,
+				gadgetEp->gadgetEp.name);
+		if (!gadgetEp->gadgetEp.address)
+			gadgetEp0Callback(priv, gadgetEp, gadgetReq, GADGET_ESHUTDOWN);
+		else
+			gadgetEpXCallback(priv, gadgetEp, gadgetReq, GADGET_ESHUTDOWN);
+	}
+
+	gadgetEp->state = GADGET_EP_FREE;
+}
+
+static void gadgetStopActivity(struct GADGET_CTRL *priv)
+{
+	int i = 0;
+	struct GadgetEp *gadgetEp;
+
+	pr_debug("USB Stop Activity\n");
+
+	if (!priv)
+		return;
+
+	for (i = 0; i < 16; i++) {
+		gadgetEp = &priv->in[i];
+		if (gadgetEp->state != GADGET_EP_NOT_IMPLEMENTED)
+			gadgetAbortEndpoint(priv, gadgetEp);
+
+		gadgetEp = &priv->out[i];
+		if (gadgetEp->state != GADGET_EP_NOT_IMPLEMENTED)
+			gadgetAbortEndpoint(priv, gadgetEp);
+	}
+}
+
+
+static int32_t gadgetEp0Enable(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp)
+{
+	uint8_t txien, rxien;
+
+	if (!priv || !gadgetEp)
+		return -EINVAL;
+
+	if (gadgetEp->state != GADGET_EP_FREE)
+		return -EBUSY;
+
+	if (!gadgetEp->isInEp) {
+		rxien = phytium_read16(&priv->regs->rxien);
+		rxien &= ~(1 << gadgetEp->hwEpNum);
+		phytium_write16(&priv->regs->rxien, rxien);
+		phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_IO_TX | FIFOCTRL_FIFOAUTO);
+	} else {
+		txien = phytium_read16(&priv->regs->txien);
+		txien &= ~(1 << gadgetEp->hwEpNum);
+		phytium_write16(&priv->regs->txien, txien);
+		phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO);
+	}
+
+	gadgetEp->gadgetEp.desc = NULL;
+	gadgetEp->state = GADGET_EP_ALLOCATED;
+	gadgetEp->channel = priv->dmaDrv->dma_channelAlloc(priv->dmaController,
+			gadgetEp->isInEp, gadgetEp->hwEpNum, 0);
+	phytium_write8(&priv->regs->ep0maxpack, 0x40);
+
+	return 0;
+}
+
+static int32_t gadgetEpXEnable(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		const struct usb_endpoint_descriptor *desc)
+{
+	uint32_t status = -EINVAL;
+	uint32_t payload;
+	uint16_t type, iso = 0;
+	uint8_t epNum = 0;
+
+	if (!priv || !gadgetEp || !desc)
+		return -EINVAL;
+
+	pr_debug("enable endpoint %s\n", gadgetEp->gadgetEp.name);
+	if (gadgetEp->state != GADGET_EP_FREE) {
+		status = -EBUSY;
+		goto fail;
+	}
+
+	payload = desc->wMaxPacketSize & 0x7ff;
+	if (!payload) {
+		status = -EINVAL;
+		goto fail;
+	}
+
+	epNum = gadgetEp->hwEpNum;
+
+	type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	switch (type) {
+	case USB_ENDPOINT_XFER_ISOC:
+		type = CON_TYPE_ISOC;
+		switch (payload >> 11) {
+		case 0:
+			iso = CON_TYPE_ISOC_1_ISOD;
+			break;
+		case 1:
+			payload *= 2;
+			iso = CON_TYPE_ISOC_2_ISOD;
+			break;
+		case 2:
+			payload *= 3;
+			iso = CON_TYPE_ISOC_3_ISOD;
+			break;
+		}
+		break;
+	case USB_ENDPOINT_XFER_INT:
+		type = CON_TYPE_INT;
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+		type = CON_TYPE_BULK;
+		break;
+	}
+
+	if (desc->bEndpointAddress & USB_DIR_IN) {
+		if (!gadgetEp->isInEp) {
+			status = -ENODEV;
+			goto fail;
+		}
+
+		if (payload > priv->gadgetCfg.epIN[epNum].maxPacketSize) {
+			status = -EINVAL;
+			goto fail;
+		}
+
+		phytium_write16(&priv->regs->txmaxpack[epNum - 1], payload);
+		phytium_write8(&priv->regs->ep[epNum - 1].txcon, CON_VAL | type
+				| iso | (priv->gadgetCfg.epIN[epNum - 1].bufferingValue - 1));
+
+		phytium_write8(&priv->regs->fifoctrl, FIFOCTRL_FIFOAUTO | FIFOCTRL_IO_TX | epNum);
+		phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX | epNum);
+		phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX | epNum |
+				ENDPRST_FIFORST | ENDPRST_TOGRST);
+	} else {
+		if (gadgetEp->isInEp) {
+			status = -ENODEV;
+			goto fail;
+		}
+
+		if (payload > priv->gadgetCfg.epOUT[epNum].maxPacketSize) {
+			status = -EINVAL;
+			goto fail;
+		}
+
+		phytium_write16(&priv->regs->rxmaxpack[epNum - 1], payload);
+		phytium_write8(&priv->regs->ep[epNum - 1].rxcon, CON_VAL | type
+				| iso | (priv->gadgetCfg.epIN[epNum - 1].bufferingValue - 1));
+
+		phytium_write8(&priv->regs->fifoctrl, FIFOCTRL_FIFOAUTO | epNum);
+		phytium_write8(&priv->regs->endprst, epNum);
+		phytium_write8(&priv->regs->endprst, epNum | ENDPRST_FIFORST | ENDPRST_TOGRST);
+	}
+
+	if (priv->dmaController)
+		gadgetEp->channel = priv->dmaDrv->dma_channelAlloc(priv->dmaController,
+				gadgetEp->isInEp, epNum, (type == CON_TYPE_ISOC) ? 1 : 0);
+
+	if (type == CON_TYPE_ISOC) {
+		if (gadgetEp->isInEp) {
+			phytium_write16(&priv->regs->isoautodump, 1 << epNum);
+			phytium_write16(&priv->regs->isodctrl, 1 << epNum);
+		}
+
+		priv->dmaDrv->dma_setMaxLength(priv->dmaController, gadgetEp->channel, payload);
+	}
+
+	gadgetEp->state = GADGET_EP_ALLOCATED;
+	gadgetEp->gadgetEp.desc = desc;
+fail:
+	return status;
+}
+
+static int32_t gadgetEpEnable(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+		const struct usb_endpoint_descriptor *desc)
+{
+	struct GadgetEp *gadgetEp = NULL;
+
+	if (!priv || !gadget_Ep || !desc)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	gadgetEp->wedged = 0;
+
+	if (gadgetEp->hwEpNum)
+		return gadgetEpXEnable(priv, gadgetEp, desc);
+	else
+		return gadgetEp0Enable(priv, gadgetEp);
+}
+
+static int32_t gadgetEpXDisable(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp)
+{
+	uint8_t txcon, rxcon;
+
+	if (!priv || !gadgetEp)
+		return -EINVAL;
+
+	pr_debug("disable endpoint %s\n", gadgetEp->gadgetEp.name);
+	if (gadgetEp->isInEp) {
+		txcon = phytium_read8(&priv->regs->ep[gadgetEp->hwEpNum - 1].txcon);
+		txcon &= ~CON_VAL;
+		phytium_write8(&priv->regs->ep[gadgetEp->hwEpNum - 1].txcon, txcon);
+	} else {
+		rxcon = phytium_read8(&priv->regs->ep[gadgetEp->hwEpNum - 1].rxcon);
+		rxcon &= ~CON_VAL;
+		phytium_write8(&priv->regs->ep[gadgetEp->hwEpNum - 1].rxcon, rxcon);
+	}
+	gadgetAbortEndpoint(priv, gadgetEp);
+	gadgetEp->gadgetEp.desc = 0;
+	gadgetEp->state = GADGET_EP_FREE;
+	return 0;
+}
+
+static int32_t gadgetEp0Disable(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp)
+{
+	if (!priv || !gadgetEp)
+		return -EINVAL;
+
+	pr_debug("disable endpoint %s\n", gadgetEp->gadgetEp.name);
+	gadgetAbortEndpoint(priv, gadgetEp);
+
+	return 0;
+}
+
+static int32_t gadgetEpDisable(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep)
+{
+	struct GadgetEp *gadgetEp = NULL;
+
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	if (gadget_Ep->address == 0)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	gadgetEp->wedged = 0;
+	if (gadgetEp->hwEpNum)
+		return gadgetEpXDisable(priv, gadgetEp);
+	else
+		return gadgetEp0Disable(priv, gadgetEp);
+}
+
+static int32_t gadgetEpXQueue(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		struct GADGET_REQ *req)
+{
+	struct GadgetRequest *gadgetRequest;
+
+	if (!priv || !gadgetEp || !req)
+		return -EINVAL;
+
+	req->actual = 0;
+	req->status = EINPROGRESS;
+
+	gadgetRequest = requestToGadgetRequest(req);
+	gadgetRequest->ep = gadgetEp;
+
+	if (req->length == 0)
+		gadgetRequest->zlp = 1;
+
+	if (gadgetEp->gadgetEp.desc == NULL) {
+		pr_info("%s is disabled - can not queue request %p\n",
+				gadgetEp->gadgetEp.name, req);
+		return -EINVAL;
+	}
+
+	list_add_tail(&req->list, &gadgetEp->request);
+	pr_debug("queue to %s (%s), length:%d\n", gadgetEp->gadgetEp.name,
+			(gadgetEp->isInEp ? "IN/TX" : "OUT/RX"), req->length);
+
+	if ((gadgetEp->state == GADGET_EP_ALLOCATED) && (&req->list == gadgetEp->request.next)) {
+		if (gadgetEp->isInEp) {
+			if (!(phytium_read8(&priv->regs->ep[gadgetEp->hwEpNum - 1].txcon)
+						& CON_STALL)) {
+				gadgetEp->state = GADGET_EP_BUSY;
+				gadgetEpXDataSend(priv, gadgetRequest);
+			}
+		} else {
+			if (!(phytium_read8(&priv->regs->ep[gadgetEp->hwEpNum - 1].rxcon)
+						& CON_STALL)) {
+				gadgetEp->state = GADGET_EP_BUSY;
+				gadgetEpXDataReceive(priv, gadgetRequest);
+			}
+		}
+	} else if (gadgetEp->state == GADGET_EP_BUSY) {
+		if (usb_endpoint_xfer_isoc(gadgetEp->gadgetEp.desc)) {
+			if (gadgetEp->isInEp)
+				gadgetEpXDataSend(priv, gadgetRequest);
+			else
+				gadgetEpXDataReceive(priv, gadgetRequest);
+		}
+	}
+
+	pr_debug("endpoint %s (%s) now is busy - transfer will be waiting in Queue\n",
+			gadgetEp->gadgetEp.name, (gadgetEp->isInEp ? "IN/TX" : "OUT/RX"));
+
+	return 0;
+}
+
+static int32_t gadgetEp0Queue(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		struct GADGET_REQ *req)
+{
+	struct GadgetRequest *gadgetRequest;
+
+	if (!priv || !gadgetEp || !req)
+		return -EINVAL;
+
+	req->actual = 0;
+	req->status = EINPROGRESS;
+
+	if (!list_empty(&gadgetEp->request))
+		return -EBUSY;
+
+	gadgetRequest = requestToGadgetRequest(req);
+	gadgetRequest->ep = gadgetEp;
+
+	switch (priv->ep0State) {
+	case GADGET_EP0_STAGE_OUT:
+	case GADGET_EP0_STAGE_IN:
+	case GADGET_EP0_STAGE_ACK:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	list_add_tail(&req->list, &gadgetEp->request);
+	gadgetEp->requestsInList++;
+
+	pr_debug("queue to %s (%s), length:%d stage:%d\n", gadgetEp->gadgetEp.name,
+			gadgetEp->isInEp ? "IN/TX" : "OUT/RX", req->length, priv->ep0State);
+
+	switch (priv->ep0State) {
+	case GADGET_EP0_STAGE_OUT:
+		gadgetEp0DataReceive(priv);
+		break;
+	case GADGET_EP0_STAGE_IN:
+		gadgetEp0DataSend(priv);
+		break;
+	case GADGET_EP0_STAGE_ACK:
+		if (req->length)
+			return -EINVAL;
+		phytium_write8(&priv->regs->ep0cs, EP0CS_HSNAK);
+		gadgetEp0Callback(priv, gadgetRequest->ep, req, 0);
+		pr_info("control transfer completed\n");
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int32_t gadgetEpQueue(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+		struct GADGET_REQ *req)
+{
+	struct GadgetEp *gadgetEp = NULL;
+
+	if (!priv || !gadget_Ep || !req)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+
+	if (gadget_Ep->address & GADGET_USB_EP_NUMBER_MASK)
+		return gadgetEpXQueue(priv, gadgetEp, req);
+	else
+		return gadgetEp0Queue(priv, gadgetEp, req);
+}
+
+static int32_t gadgetEpXDequeue(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		struct GADGET_REQ *req)
+{
+	struct GadgetRequest *gadgetRequest;
+	struct GADGET_REQ *iterator;
+
+	if (!priv || !gadgetEp || !req)
+		return -EINVAL;
+
+	gadgetRequest = requestToGadgetRequest(req);
+	if (gadgetRequest->ep != gadgetEp)
+		return -EINVAL;
+
+	pr_debug("Dequeue request %p form %s\n", req, gadgetEp->gadgetEp.name);
+
+	listBrowsingRequest(iterator, &gadgetEp->request, list) {
+		if (req == iterator)
+			break;
+	}
+
+	if (req != iterator) {
+		pr_info("request %p not queued to %s\n", req, gadgetEp->gadgetEp.name);
+		return -EINVAL;
+	}
+
+	if (gadgetEp->state == GADGET_EP_BUSY) {
+		priv->dmaDrv->dma_channelAbort(priv->dmaController, gadgetEp->channel);
+		gadgetEp->state = GADGET_EP_ALLOCATED;
+	}
+
+	gadgetEpXCallback(priv, gadgetEp, req, GADGET_ECONNRESET);
+
+	return 0;
+}
+
+static int32_t gadgetEp0Dequeue(struct GADGET_CTRL *priv, struct GadgetEp *gadgetEp,
+		struct GADGET_REQ *req)
+{
+	return 0;
+}
+
+static int32_t gadgetEpDequeue(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+		struct GADGET_REQ *req)
+{
+	struct GadgetEp *gadgetEp = NULL;
+
+	if (!priv || !gadget_Ep || !req)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+
+	if (gadget_Ep->address & GADGET_USB_EP_NUMBER_MASK)
+		return gadgetEpXDequeue(priv, gadgetEp, req);
+	else
+		return gadgetEp0Dequeue(priv, gadgetEp, req);
+}
+
+static int32_t gadgetEpSetHalt(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep, uint8_t value)
+{
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	if (gadget_Ep->address & GADGET_USB_EP_NUMBER_MASK)
+		return gadgetEpXSetHalt(priv, gadget_Ep, value);
+	else
+		return gadgetEp0SetHalt(priv, gadget_Ep, value);
+}
+
+static int32_t gadgetEpSetWedge(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep)
+{
+	struct GadgetEp *gadgetEp = NULL;
+
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	gadgetEp->wedged = 1;
+
+	return gadgetEpSetHalt(priv, gadget_Ep, 1);
+}
+
+static int32_t gadgetEpFifoStatus(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep)
+{
+	if (!priv || !gadget_Ep)
+		return -EINVAL;
+
+	return 0;
+}
+
+static void gadgetEpFifoFlush(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep)
+{
+	if (!priv || !gadget_Ep)
+		return;
+}
+
+static int32_t gadgetEpAllocRequest(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+		struct GADGET_REQ **req)
+{
+	struct GadgetEp *gadgetEp = NULL;
+	struct GadgetRequest *gadgetRequest = NULL;
+
+	if (!priv || !gadget_Ep || !req)
+		return -EINVAL;
+
+	gadgetEp = toGadgetEp(gadget_Ep);
+	if (priv->eventCallback.usbRequestMemAlloc)
+		gadgetRequest = priv->eventCallback.usbRequestMemAlloc(priv,
+				sizeof(*gadgetRequest));
+	if (!gadgetRequest)
+		return -ENOMEM;
+
+	memset(gadgetRequest, 0, sizeof(*gadgetRequest));
+	*req = &gadgetRequest->request;
+	INIT_LIST_HEAD(&gadgetRequest->request.list);
+	gadgetRequest->ep = gadgetEp;
+
+	return 0;
+}
+
+static void gadgetEpFreeRequest(struct GADGET_CTRL *priv, struct GADGET_EP *gadget_Ep,
+		struct GADGET_REQ *req)
+{
+	struct GadgetRequest *gadgetRequest = NULL;
+
+	if (!priv || !gadget_Ep || !req)
+		return;
+
+	gadgetRequest = requestToGadgetRequest(req);
+
+	if (priv->eventCallback.usbRequestMemFree)
+		priv->eventCallback.usbRequestMemFree(priv, gadgetRequest);
+}
+
+static struct GADGET_EP_OPS gadgetEpOps = {
+	.epEnable	=	gadgetEpEnable,
+	.epDisable	=	gadgetEpDisable,
+	.reqQueue	=	gadgetEpQueue,
+	.reqDequeue	=	gadgetEpDequeue,
+	.epSetHalt	=	gadgetEpSetHalt,
+	.epSetWedge	=	gadgetEpSetWedge,
+	.epFifoStatus	=	gadgetEpFifoStatus,
+	.reqAlloc	=	gadgetEpAllocRequest,
+	.reqFree	=	gadgetEpFreeRequest
+};
+
+static void gadgetInitDeviceEp(struct GADGET_CTRL *priv, uint8_t isInEp)
+{
+	uint8_t num;
+	struct GadgetEp *gadgetEp;
+	struct GADGET_EP_CFG epCfg;
+
+	if (!priv)
+		return;
+
+	for (num = 0; num < 16; num++) {
+		gadgetEp = isInEp ? &priv->in[num] : &priv->out[num];
+		if (num) {
+			epCfg = isInEp ? priv->gadgetCfg.epIN[num] : priv->gadgetCfg.epOUT[num];
+			if (!epCfg.bufferingValue) {
+				gadgetEp->state = GADGET_EP_NOT_IMPLEMENTED;
+				gadgetEp->hwEpNum = num;
+				continue;
+			}
+		}
+		INIT_LIST_HEAD(&gadgetEp->gadgetEp.epList);
+		INIT_LIST_HEAD(&gadgetEp->request);
+		gadgetEp->state = GADGET_EP_FREE;
+		gadgetEp->hwEpNum = num;
+		gadgetEp->isInEp = isInEp;
+		gadgetEp->requestsInList = 0;
+		snprintf(gadgetEp->gadgetEp.name, sizeof(gadgetEp->gadgetEp.name),
+				"Ep%d%s", num, isInEp ? "in" : "out");
+		if (!num) {
+			gadgetEp->gadgetEp.maxPacket = priv->gadgetCfg.epIN[num].maxPacketSize;
+			if (isInEp)
+				priv->gadgetDev.ep0 = &gadgetEp->gadgetEp;
+			gadgetEp->gadgetEp.ops = &gadgetEpOps;
+			gadgetEp0Enable(priv, gadgetEp);
+			continue;
+		}
+
+		if (isInEp) {
+			if (epCfg.startBuf)
+				phytium_write16(&priv->regs->txstaddr[num - 1].addr,
+						epCfg.startBuf);
+			phytium_write8(&priv->regs->ep[num - 1].txcon, 0);
+			gadgetEp->gadgetEp.maxPacket = epCfg.maxPacketSize;
+		} else {
+			if (epCfg.startBuf)
+				phytium_write16(&priv->regs->rxstaddr[num - 1].addr,
+						epCfg.startBuf);
+			phytium_write8(&priv->regs->ep[num - 1].rxcon, 0);
+			gadgetEp->gadgetEp.maxPacket = epCfg.maxPacketSize;
+		}
+
+		gadgetEp->gadgetEp.ops = &gadgetEpOps;
+		gadgetEp->gadgetEp.address = isInEp ? (0x80 | num) : num;
+		gadgetEp->gadgetEp.maxburst = 0;
+		gadgetEp->gadgetEp.mult = 0;
+		gadgetEp->gadgetEp.maxStreams = 0;
+		priv->endpointInList++;
+		list_add_tail(&gadgetEp->gadgetEp.epList, &priv->gadgetDev.epList);
+	}
+}
+
+static void gadgetInitEndpoint(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return;
+
+	gadgetInitDeviceEp(priv, 1);
+	gadgetInitDeviceEp(priv, 0);
+}
+
+static void gadgetSetup(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return;
+
+	INIT_LIST_HEAD(&priv->gadgetDev.epList);
+	priv->gadgetDev.state = USB_STATE_NOTATTACHED;
+	priv->gadgetDev.maxSpeed = USB_SPEED_HIGH;
+	priv->gadgetDev.speed = USB_SPEED_FULL;
+	snprintf(priv->gadgetDev.name, sizeof(priv->gadgetDev.name), "Phytium USB SD Driver");
+
+	gadgetInitEndpoint(priv);
+
+	phytium_write8(&priv->regs->ep0maxpack, 0x40);
+	phytium_write16(&priv->regs->rxien, 0);
+	phytium_write16(&priv->regs->txien, 0);
+	phytium_write16(&priv->regs->rxirq, 0xFFFF);
+	phytium_write16(&priv->regs->txirq, 0xFFFF);
+	phytium_write8(&priv->regs->usbirq, 0xEF);
+	phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX);
+	phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST | ENDPRST_IO_TX);
+	phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST);
+	priv->isReady = 1;
+}
+int32_t gadgetInit(struct GADGET_CTRL *priv, struct GADGET_CFG *config,
+		struct GADGET_CALLBACKS *callbacks, struct device *pdev)
+{
+	struct DMA_SYSREQ dmaSysReq;
+	uint8_t usbcs;
+
+	if (!priv || !config || !callbacks)
+		return -EINVAL;
+
+	priv->dev = pdev;
+	priv->eventCallback = *callbacks;
+	priv->gadgetCfg = *config;
+	priv->regs = (struct HW_REGS *)config->regBase;
+	priv->phy_regs = (struct VHUB_REGS *)config->phy_regBase;
+	priv->gadgetDrv = GADGET_GetInstance();
+	priv->dmaDrv = DMA_GetInstance();
+	priv->dmaController = (void *)(priv + 1);
+	priv->dmaCfg.dmaModeRx = 0xFFFF;
+	priv->dmaCfg.dmaModeTx = 0xFFFF;
+	priv->dmaCfg.regBase = config->regBase + 0x400;
+	priv->dmaCfg.trbAddr = config->trbAddr;
+	priv->dmaCfg.trbDmaAddr = config->trbDmaAddr;
+
+	priv->dmaDrv->dma_probe(NULL, &dmaSysReq);
+	priv->privBuffAddr = (uint8_t *)((uintptr_t)config->trbAddr + dmaSysReq.trbMemSize);
+	priv->privBuffDma = (uintptr_t)((uintptr_t)config->trbDmaAddr + dmaSysReq.trbMemSize);
+	priv->dmaCallback.complete = gadget_CallbackTransfer;
+	priv->dmaDrv->dma_init(priv->dmaController, &priv->dmaCfg, &priv->dmaCallback);
+	priv->dmaDrv->dma_setParentPriv(priv->dmaController, priv);
+
+	usbcs = phytium_read8(&priv->regs->usbcs);
+	usbcs |= USBCS_DISCON | USBCS_LPMNYET;
+	phytium_write8(&priv->regs->usbcs, usbcs);
+
+	gadgetSetup(priv);
+
+	usbcs = phytium_read8(&priv->regs->usbcs);
+	usbcs &= USBCS_DISCON;
+	phytium_write8(&priv->regs->usbcs, usbcs);
+
+	return 0;
+}
+
+static void gadgetDestroy(struct GADGET_CTRL *priv)
+{
+	pr_debug("Destroy Device Controller driver\n");
+
+	if (priv)
+		return;
+	gadgetDisconnect(priv);
+
+	gadgetStopActivity(priv);
+
+	phytium_write8(&priv->regs->usbcs, USBCS_DISCON);
+
+	priv->isReady = 0;
+}
+
+static void gadgetStart(struct GADGET_CTRL *priv)
+{
+	uint8_t usbien, usbcs;
+
+	pr_debug("Usb Device Controller start\n");
+	if (!priv)
+		return;
+
+	usbien = phytium_read8(&priv->regs->usbien);
+	usbien |= USBIR_URES | USBIR_SUDAV | USBIR_LPMIR;
+	phytium_write8(&priv->regs->usbien, usbien);
+
+	usbcs = phytium_read8(&priv->regs->usbcs);
+	usbcs &= ~USBCS_DISCON;
+	phytium_write8(&priv->regs->usbcs, usbcs);
+
+	priv->dmaDrv->dma_start(priv->dmaController);
+}
+
+static void gadgetReset(struct GADGET_CTRL *priv)
+{
+	int i = 0;
+
+	pr_debug("Usb Disable Device Activity\n");
+
+	if (!priv)
+		return;
+
+	if (priv->gadgetDev.speed != USB_SPEED_UNKNOWN)
+		gadgetDisconnect(priv);
+
+	priv->gadgetDev.aHnpSupport = 0;
+	priv->gadgetDev.bHnpEnable = 0;
+	priv->gadgetDev.state = USB_STATE_DEFAULT;
+	priv->deviceAddress = 0;
+	priv->ep0State = GADGET_EP0_STAGE_SETUP;
+
+	gadgetStopActivity(priv);
+
+	for (i = 0; i < 1000; i++) {
+		priv->gadgetDev.speed = gadgetGetActualSpeed(priv);
+		if (priv->gadgetDev.speed == USB_SPEED_HIGH)
+			return;
+	}
+}
+
+static void gadgetStop(struct GADGET_CTRL *priv)
+{
+	pr_debug("Usb Device Controller stop\n");
+
+	if (!priv)
+		return;
+
+	if (!priv->isReady)
+		return;
+
+	gadgetReset(priv);
+
+	phytium_write8(&priv->regs->usbien, 0);
+	priv->dmaDrv->dma_stop(priv->dmaController);
+
+	priv->isReady = 0;
+}
+
+static void gadgetIsr(struct GADGET_CTRL *priv)
+{
+	uint8_t usbirq, usbien, usbcs;
+
+	if (!priv)
+		return;
+
+	usbirq = phytium_read8(&priv->regs->usbirq);
+	usbien = phytium_read8(&priv->regs->usbien);
+
+	pr_debug("usbirq:0x%x usbien:0x%x\n", usbirq, usbien);
+
+	usbirq = usbirq & usbien;
+
+	if (!usbirq)
+		goto DMA_IRQ;
+
+	if (usbirq & USBIR_LPMIR) {
+		pr_debug("USBIRQ LPM\n");
+		usbcs = phytium_read8(&priv->regs->usbcs);
+		usbcs &= ~USBCS_LPMNYET;
+		phytium_write8(&priv->regs->usbcs, usbcs);
+		phytium_write8(&priv->regs->usbirq, USBIR_LPMIR);
+	}
+
+	if (usbirq & USBIR_URES) {
+		pr_debug("USBIRQ RESET\n");
+		phytium_write8(&priv->regs->usbirq, USBIR_URES);
+		priv->releaseEp0Flag = 1;
+		gadgetReset(priv);
+		priv->releaseEp0Flag = 0;
+		priv->gadgetDev.state = USB_STATE_DEFAULT;
+		if (priv->eventCallback.connect)
+			priv->eventCallback.connect(priv);
+	}
+
+	if (usbirq & USBIR_HSPEED) {
+		pr_debug("USBIRQ HighSpeed\n");
+		phytium_write8(&priv->regs->usbirq, USBIR_HSPEED);
+		priv->gadgetDev.speed = USB_SPEED_HIGH;
+	}
+
+	if (usbirq & USBIR_SUDAV) {
+		pr_debug("USBIRQ SUDAV\n");
+		priv->ep0State = GADGET_EP0_STAGE_SETUP;
+		gadgetEp0Irq(priv);
+	}
+
+	if (usbirq & USBIR_SOF) {
+		pr_debug("USBIRQ SOF\n");
+		phytium_write8(&priv->regs->usbirq, USBIR_SOF);
+	}
+
+	if (usbirq & USBIR_SUTOK) {
+		pr_debug("USBIRQ SUTOK\n");
+		phytium_write8(&priv->regs->usbirq, USBIR_SUTOK);
+	}
+
+	if (usbirq & USBIR_SUSP) {
+		pr_debug("USBIRQ SUSPEND\n");
+		phytium_write8(&priv->regs->usbirq, USBIR_SUSP);
+	}
+
+	return;
+DMA_IRQ:
+	priv->dmaDrv->dma_isr(priv->dmaController);
+}
+
+static void gadgetGetDevInstance(struct GADGET_CTRL *priv, struct GADGET_DEV **dev)
+{
+	if (!priv || !dev)
+		return;
+
+	*dev = &priv->gadgetDev;
+}
+
+static int32_t gadgetGetFrame(struct GADGET_CTRL *priv, uint32_t *numOfFrame)
+{
+	if (!priv || !numOfFrame)
+		return -EINVAL;
+
+	*numOfFrame = phytium_read16(&priv->regs->frmnr);
+
+	return 0;
+}
+
+static int32_t gadgetWakeUp(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return -EINVAL;
+
+	return -ENOTSUPP;
+}
+
+static int32_t gadgetSetSelfPowered(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return -EINVAL;
+
+	priv->isSelfPowered = 1;
+
+	return 0;
+}
+
+static int32_t gadgetClearSelfPowered(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return -EINVAL;
+
+	priv->isSelfPowered = 0;
+
+	return 0;
+}
+
+static int32_t gadgetVbusSession(struct GADGET_CTRL *priv, uint8_t isActive)
+{
+	if (!priv)
+		return -EINVAL;
+
+	return -ENOTSUPP;
+}
+
+static int32_t gadgetVbusDraw(struct GADGET_CTRL *priv, uint8_t mA)
+{
+	if (!priv)
+		return -EINVAL;
+
+	return -ENOTSUPP;
+}
+
+static int32_t gadgetPullUp(struct GADGET_CTRL *priv, uint8_t isOn)
+{
+	if (!priv)
+		return -EINVAL;
+
+	return -ENOTSUPP;
+}
+
+struct GADGET_OBJ GadgetObj = {
+	.gadget_init	=	gadgetInit,
+	.gadget_destroy =	gadgetDestroy,
+	.gadget_start	=	gadgetStart,
+	.gadget_stop	=	gadgetStop,
+	.gadget_isr	=	gadgetIsr,
+	//endpoint operation
+	.gadget_epEnable	=	gadgetEpEnable,
+	.gadget_epDisable	=	gadgetEpDisable,
+	.gadget_epSetHalt	=	gadgetEpSetHalt,
+	.gadget_epSetWedge	=	gadgetEpSetWedge,
+	.gadget_epFifoStatus	=	gadgetEpFifoStatus,
+	.gadget_epFifoFlush	=	gadgetEpFifoFlush,
+	.gadget_reqQueue	=	gadgetEpQueue,
+	.gadget_reqDequeue	=	gadgetEpDequeue,
+	.gadget_reqAlloc	=	gadgetEpAllocRequest,
+	.gadget_reqFree		=	gadgetEpFreeRequest,
+
+	//Device operations
+	.gadget_getDevInstance =	gadgetGetDevInstance,
+	.gadget_dGetFrame	=	gadgetGetFrame,
+	.gadget_dWakeUp		=	gadgetWakeUp,
+	.gadget_dSetSelfpowered =	gadgetSetSelfPowered,
+	.gadget_dClearSelfpowered =	gadgetClearSelfPowered,
+	.gadget_dVbusSession	=	gadgetVbusSession,
+	.gadget_dVbusDraw	=	gadgetVbusDraw,
+	.gadget_dPullUp		=	gadgetPullUp,
+};
+
+struct GADGET_OBJ *GADGET_GetInstance(void)
+{
+	return &GadgetObj;
+}
+
+static int phytium_gadget_set_default_cfg(struct phytium_cusb *config)
+{
+	int index;
+
+	config->gadget_cfg.regBase = (uintptr_t)config->regs;
+	config->gadget_cfg.phy_regBase = (uintptr_t)config->phy_regs;
+	config->gadget_cfg.dmaInterfaceWidth = GADGET_DMA_32_WIDTH;
+
+	for (index = 0; index < 16; index++) {
+		if (index == 0) {
+			config->gadget_cfg.epIN[index].bufferingValue = 1;
+			config->gadget_cfg.epIN[index].maxPacketSize = 64;
+			config->gadget_cfg.epIN[index].startBuf = 0;
+
+			config->gadget_cfg.epOUT[index].bufferingValue = 1;
+			config->gadget_cfg.epOUT[index].maxPacketSize = 64;
+			config->gadget_cfg.epOUT[index].startBuf = 0;
+		} else {
+			config->gadget_cfg.epIN[index].bufferingValue = 4;
+			config->gadget_cfg.epIN[index].maxPacketSize = 1024;
+			config->gadget_cfg.epIN[index].startBuf = 64 + 4096 * (index - 1);
+
+			config->gadget_cfg.epOUT[index].bufferingValue = 4;
+			config->gadget_cfg.epOUT[index].maxPacketSize = 1024;
+			config->gadget_cfg.epOUT[index].startBuf = 64 + 4096 * (index - 1);
+		}
+	}
+
+	return 0;
+}
+
+void gadget_callback_connect(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return;
+}
+
+void gadget_callback_disconnect(struct GADGET_CTRL *priv)
+{
+	if (!priv)
+		return;
+}
+
+int32_t gadget_callback_setup(struct GADGET_CTRL *priv, struct usb_ctrlrequest *ctrl)
+{
+	struct phytium_cusb *config;
+	int ret = 0;
+
+	if (!priv || !ctrl)
+		return -EINVAL;
+
+	config = dev_get_drvdata(priv->dev);
+	if (!config)
+		return -1;
+
+	if (!config->gadget_driver)
+		return -EOPNOTSUPP;
+
+	if (ctrl->bRequestType & USB_DIR_IN)
+		config->ep0_data_stage_is_tx = 1;
+	else
+		config->ep0_data_stage_is_tx = 0;
+
+	spin_unlock(&config->lock);
+	ret = config->gadget_driver->setup(&config->gadget, ctrl);
+	spin_lock(&config->lock);
+
+	if (ret == 0x7FFF)
+		return ret;
+
+	if (ret < 0)
+		return 1;
+
+	return 0;
+}
+
+void *gadget_callback_usbRequestMemAlloc(struct GADGET_CTRL *priv, u32 size)
+{
+	struct GADGET_REQ *gadget_req = NULL;
+
+	gadget_req = kzalloc(size, GFP_NOWAIT);
+	if (!gadget_req)
+		return NULL;
+
+	return gadget_req;
+}
+
+void gadget_callback_usbRequestMemFree(struct GADGET_CTRL *priv, void *usbReq)
+{
+	if (!usbReq)
+		return;
+
+	kfree(usbReq);
+}
+
+static void init_peripheral_ep(struct phytium_cusb *config,
+		struct phytium_ep *phy_ep, struct GADGET_EP *gadget_ep, int is_tx)
+{
+	if (!config || !phy_ep || !gadget_ep)
+		return;
+
+	memset(phy_ep, 0, sizeof(*phy_ep));
+	phy_ep->config = config;
+	phy_ep->is_tx = is_tx;
+	phy_ep->gadget_ep = gadget_ep;
+	phy_ep->ep_num = gadget_ep->address & 0xF;
+	phy_ep->end_point.maxpacket = gadget_ep->maxPacket;
+	phy_ep->end_point.maxpacket_limit = 1024;
+
+	INIT_LIST_HEAD(&phy_ep->req_list);
+	sprintf(phy_ep->name, "ep%d%s", phy_ep->ep_num, is_tx ? "in" : "out");
+
+	switch (phy_ep->ep_num) {
+	case 0:
+		phy_ep->end_point.caps.type_control = 1;
+		break;
+	case 1:
+		phy_ep->end_point.caps.type_bulk = 1;
+		break;
+	case 2:
+		phy_ep->end_point.caps.type_int = 1;
+		break;
+	case 3:
+		phy_ep->end_point.caps.type_iso = 1;
+		break;
+	default:
+		phy_ep->end_point.caps.type_int = 1;
+		phy_ep->end_point.caps.type_bulk = 1;
+		break;
+	}
+
+	if (is_tx) {
+		phy_ep->end_point.caps.dir_in = 1;
+		phy_ep->end_point.caps.dir_out = 0;
+	} else {
+		phy_ep->end_point.caps.dir_in = 0;
+		phy_ep->end_point.caps.dir_out = 1;
+	}
+
+	phy_ep->end_point.name = phy_ep->name;
+
+	INIT_LIST_HEAD(&phy_ep->end_point.ep_list);
+
+	if (!phy_ep->ep_num) {
+		phy_ep->end_point.ops = &gadget_ep0_ops;
+		config->gadget.ep0 = &phy_ep->end_point;
+
+		if (config->gadget_dev->maxSpeed > USB_SPEED_HIGH)
+			config->gadget.ep0->maxpacket = 9;
+	} else {
+		phy_ep->end_point.ops = &gadget_ep_ops;
+		list_add_tail(&phy_ep->end_point.ep_list, &config->gadget.ep_list);
+	}
+}
+
+static void gadget_init_endpoint(struct phytium_cusb *config)
+{
+	struct list_head *list;
+	struct GADGET_EP *gadget_ep;
+
+	if (!config)
+		return;
+
+	INIT_LIST_HEAD(&(config->gadget.ep_list));
+
+	init_peripheral_ep(config, &config->endpoints_tx[0], config->gadget_dev->ep0, 1);
+	init_peripheral_ep(config, &config->endpoints_rx[0], config->gadget_dev->ep0, 0);
+
+	list_for_each(list, &config->gadget_dev->epList) {
+		gadget_ep = (struct GADGET_EP *)list;
+		if (gadget_ep->address & USB_DIR_IN)
+			init_peripheral_ep(config, &config->endpoints_tx[gadget_ep->address & 0xf],
+					gadget_ep, 1);
+		else
+			init_peripheral_ep(config, &config->endpoints_rx[gadget_ep->address & 0xf],
+					gadget_ep, 0);
+	}
+}
+
+static int gadget_setup(struct phytium_cusb *config)
+{
+	int ret = -1;
+
+	config->gadget_obj->gadget_getDevInstance(config->gadget_priv, &config->gadget_dev);
+	config->gadget.ops = &phytium_gadget_ops;
+	config->gadget.max_speed = config->gadget_dev->maxSpeed;
+	config->gadget.speed = USB_SPEED_HIGH;
+	config->gadget.name = "phytium_gadget";
+	config->gadget.is_otg = 0;
+
+	gadget_init_endpoint(config);
+
+	ret = usb_add_gadget_udc(config->dev, &config->gadget);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	config->gadget.dev.parent = NULL;
+	device_unregister(&config->gadget.dev);
+	return ret;
+}
+
+int phytium_gadget_reinit(struct phytium_cusb *config)
+{
+	struct GADGET_CTRL *ctrl;
+
+	if (!config)
+		return 0;
+
+	ctrl = (struct GADGET_CTRL *)config->gadget_priv;
+	if (!ctrl)
+		return 0;
+
+	gadgetStop(ctrl);
+
+	config->gadget_obj->gadget_init(config->gadget_priv, &config->gadget_cfg,
+			&config->gadget_callbacks, config->dev);
+
+	return 0;
+}
+
+int phytium_gadget_init(struct phytium_cusb *config)
+{
+	int ret;
+
+	if (!config)
+		return 0;
+
+	phytium_gadget_set_default_cfg(config);
+	config->gadget_obj = &GadgetObj;
+
+	config->dma_cfg.regBase = config->gadget_cfg.regBase + 0x400;
+	config->dma_obj = DMA_GetInstance();
+	config->dma_obj->dma_probe(&config->dma_cfg, &config->dma_sysreq);
+
+	config->gadget_sysreq.privDataSize = sizeof(struct GADGET_CTRL);
+	config->gadget_sysreq.trbMemSize = config->dma_sysreq.trbMemSize + GADGET_PRIV_BUFFER_SIZE;
+	config->gadget_sysreq.privDataSize += config->dma_sysreq.privDataSize;
+
+	config->gadget_priv = devm_kzalloc(config->dev,
+			config->gadget_sysreq.privDataSize, GFP_KERNEL);
+	if (!config->gadget_priv) {
+		ret = -ENOMEM;
+		goto err_probe;
+	}
+	config->gadget_cfg.trbAddr = dma_alloc_coherent(config->dev,
+			config->gadget_sysreq.trbMemSize,
+			(dma_addr_t *)&config->gadget_cfg.trbDmaAddr, GFP_KERNEL);
+	if (!config->gadget_cfg.trbAddr) {
+		ret = -ENOMEM;
+		goto err_dma_coherent;
+	}
+
+	config->gadget_callbacks.connect		= gadget_callback_connect;
+	config->gadget_callbacks.disconnect		= gadget_callback_disconnect;
+	config->gadget_callbacks.setup			= gadget_callback_setup;
+	config->gadget_callbacks.usbRequestMemAlloc	= gadget_callback_usbRequestMemAlloc;
+	config->gadget_callbacks.usbRequestMemFree	= gadget_callback_usbRequestMemFree;
+
+	ret = config->gadget_obj->gadget_init(config->gadget_priv, &config->gadget_cfg,
+			&config->gadget_callbacks, config->dev);
+	if (ret) {
+		ret = -ENODEV;
+		goto err_init;
+	}
+
+	//dev_set_drvdata(config->dev, config);
+
+	gadget_setup(config);
+
+	return 0;
+
+err_init:
+	dma_free_coherent(config->dev, config->gadget_sysreq.trbMemSize,
+			config->gadget_cfg.trbAddr, config->gadget_cfg.trbDmaAddr);
+err_dma_coherent:
+err_probe:
+	dev_set_drvdata(config->dev, NULL);
+
+	return ret;
+}
+
+int phytium_gadget_uninit(struct phytium_cusb *config)
+{
+	if (config)
+		usb_del_gadget_udc(&config->gadget);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+int phytium_gadget_resume(void *priv)
+{
+	struct GADGET_CTRL *ctrl;
+	uint32_t gen_cfg;
+	unsigned long flags = 0;
+	struct phytium_cusb *config = (struct phytium_cusb *)priv;
+
+	if (!config)
+		return 0;
+
+	ctrl = (struct GADGET_CTRL *)config->gadget_priv;
+	if (!ctrl)
+		return 0;
+
+	spin_lock_irqsave(&config->lock, flags);
+	phytium_gadget_reinit(config);
+
+	if (config->gadget_driver) {
+		config->gadget_obj->gadget_start(config->gadget_priv);
+		if (ctrl->phy_regs) {
+			gen_cfg = phytium_read32(&ctrl->phy_regs->gen_cfg);
+			gen_cfg = gen_cfg & (~BIT(7));
+			phytium_write32(&ctrl->phy_regs->gen_cfg, gen_cfg);
+		}
+	}
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+int phytium_gadget_suspend(void *priv)
+{
+	return 0;
+}
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/gadget.h b/target/linux/phytium/files-5.10/drivers/usb/phytium/gadget.h
new file mode 100644
index 00000000000000..d87b55ade7a70b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/gadget.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __PHYTIUM_GADGET_H_
+#define __PHYTIUM_GADGET_H_
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include "dma.h"
+
+struct GADGET_CTRL;
+struct GADGET_EP;
+struct GADGET_REQ;
+
+enum GADGET_EP_STATE {
+	GADGET_EP_FREE,
+	GADGET_EP_ALLOCATED,
+	GADGET_EP_BUSY,
+	GADGET_EP_NOT_IMPLEMENTED
+};
+
+enum GADGET_EP0_STAGE {
+	GADGET_EP0_STAGE_SETUP,
+	GADGET_EP0_STAGE_IN,
+	GADGET_EP0_STAGE_OUT,
+	GADGET_EP0_STAGE_STATUSIN,
+	GADGET_EP0_STAGE_STATUSOUT,
+	GADGET_EP0_STAGE_ACK
+};
+
+struct GADGET_EP_OPS {
+	int32_t (*epEnable)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			const struct usb_endpoint_descriptor *desc);
+
+	int32_t (*epDisable)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*epSetHalt)(struct GADGET_CTRL *priv, struct GADGET_EP *ep, uint8_t value);
+
+	int32_t (*epSetWedge)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*epFifoStatus)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*epFifoFlush)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*reqQueue)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ *req);
+
+	int32_t (*reqDequeue)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ *req);
+
+	int32_t (*reqAlloc)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ **req);
+
+	void (*reqFree)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ *req);
+};
+
+struct GADGET_EP {
+	struct list_head epList;
+	char name[255];
+	struct GADGET_EP_OPS *ops;
+	uint16_t maxPacket;
+	uint16_t maxStreams;
+	uint8_t mult;
+	uint8_t maxburst;
+	uint8_t address;
+	const struct usb_endpoint_descriptor *desc;
+	const struct usb_ss_ep_comp_descriptor *compDesc;
+};
+
+enum GADGET_DMAInterfaceWidth {
+	GADGET_DMA_32_WIDTH = 4,
+	GADGET_DMA_64_WIDTH = 8,
+};
+
+struct GADGET_EP_CFG {
+	uint8_t bufferingValue;
+	uint16_t startBuf;
+	uint16_t maxPacketSize;
+};
+
+struct GADGET_CFG {
+	uintptr_t regBase;
+	uintptr_t phy_regBase;
+	struct GADGET_EP_CFG epIN[16];
+	struct GADGET_EP_CFG epOUT[16];
+	enum GADGET_DMAInterfaceWidth dmaInterfaceWidth;
+	void *trbAddr;
+	uintptr_t trbDmaAddr;
+};
+
+struct GADGET_SYSREQ {
+	uint32_t privDataSize;
+	uint32_t trbMemSize;
+};
+
+struct GadgetEp {
+	struct GADGET_EP gadgetEp;
+	enum GADGET_EP_STATE state;
+	uint8_t hwEpNum;
+	uint8_t isInEp;
+	struct list_head request;
+	uint8_t iso_flag;
+	void *channel;
+	uint32_t requestsInList;
+	uint8_t wedged;
+};
+
+struct GADGET_DEV {
+	struct list_head epList;
+	struct GADGET_EP *ep0;
+	unsigned int speed;
+	unsigned int maxSpeed;
+	enum usb_device_state state;
+	uint8_t sgSupported;
+	uint8_t bHnpEnable;
+	uint8_t aHnpSupport;
+	char name[255];
+};
+
+struct GADGET_SgList {
+	uintptr_t link;
+	uint32_t offset;
+	uint32_t length;
+	uintptr_t dmaAddress;
+};
+
+struct GADGET_REQ {
+	struct list_head list;
+	void *buf;
+	uint32_t length;
+	uintptr_t dma;
+	uint32_t numOfSgs;
+	uint32_t numMappedSgs;
+	uint16_t streamId;
+	uint8_t oInterrupt;
+	uint8_t zero;
+	uint8_t shortNotOk;
+	void *context;
+	uint32_t status;
+	uint32_t actual;
+	struct GADGET_SgList *sg;
+	void (*complete)(struct GADGET_EP *ep, struct GADGET_REQ *req);
+};
+
+
+struct GADGET_CALLBACKS {
+	void (*disconnect)(struct GADGET_CTRL *priv);
+
+	void (*connect)(struct GADGET_CTRL *priv);
+
+	int32_t (*setup)(struct GADGET_CTRL *priv,
+			struct usb_ctrlrequest *ctrl);
+
+	void *(*usbRequestMemAlloc)(struct GADGET_CTRL *priv,
+			uint32_t requiredSize);
+
+	void (*usbRequestMemFree)(struct GADGET_CTRL *priv, void *usbRequest);
+};
+
+struct GADGET_OBJ {
+	int32_t (*gadget_init)(struct GADGET_CTRL *priv, struct GADGET_CFG *config,
+			struct GADGET_CALLBACKS *callbacks, struct device *pdev);
+
+	void (*gadget_destroy)(struct GADGET_CTRL *priv);
+
+	void (*gadget_start)(struct GADGET_CTRL *priv);
+
+	void (*gadget_stop)(struct GADGET_CTRL *priv);
+
+	void (*gadget_isr)(struct GADGET_CTRL *priv);
+
+	int32_t (*gadget_epEnable)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			const struct usb_endpoint_descriptor *desc);
+
+	int32_t (*gadget_epDisable)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*gadget_epSetHalt)(struct GADGET_CTRL *priv, struct GADGET_EP *ep, uint8_t value);
+
+	int32_t (*gadget_epSetWedge)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*gadget_epFifoStatus)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	void (*gadget_epFifoFlush)(struct GADGET_CTRL *priv, struct GADGET_EP *ep);
+
+	int32_t (*gadget_reqQueue)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ *req);
+
+	int32_t (*gadget_reqDequeue)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ *req);
+
+	int32_t (*gadget_reqAlloc)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ **req);
+
+	void (*gadget_reqFree)(struct GADGET_CTRL *priv, struct GADGET_EP *ep,
+			struct GADGET_REQ *req);
+
+	void (*gadget_getDevInstance)(struct GADGET_CTRL *priv, struct GADGET_DEV **dev);
+
+	int32_t (*gadget_dGetFrame)(struct GADGET_CTRL *priv, uint32_t *numOfFrame);
+
+	int32_t (*gadget_dWakeUp)(struct GADGET_CTRL *priv);
+
+	int32_t (*gadget_dSetSelfpowered)(struct GADGET_CTRL *priv);
+
+	int32_t (*gadget_dClearSelfpowered)(struct GADGET_CTRL *priv);
+
+	int32_t (*gadget_dVbusSession)(struct GADGET_CTRL *priv, uint8_t isActive);
+
+	int32_t (*gadget_dVbusDraw)(struct GADGET_CTRL *priv, uint8_t mA);
+
+	int32_t (*gadget_dPullUp)(struct GADGET_CTRL *priv, uint8_t isOn);
+
+	void (*gadget_dGetConfigParams)(struct GADGET_CTRL *priv,
+			struct usb_dcd_config_params *configParams);
+};
+
+struct GADGET_CTRL {
+	struct device *dev;
+	struct GADGET_DEV gadgetDev;
+	struct HW_REGS *regs;
+	struct GADGET_OBJ *gadgetDrv;
+	struct GADGET_CFG gadgetCfg;
+	struct GADGET_CALLBACKS eventCallback;
+	struct GadgetEp in[16];
+	struct GadgetEp out[16];
+	enum GADGET_EP0_STAGE ep0State;
+	uint8_t isRemoteWakeup;
+	uint8_t isSelfPowered;
+	uint8_t deviceAddress;
+	struct DMA_OBJ *dmaDrv;
+	void *dmaController;
+	struct DMA_CFG dmaCfg;
+	struct DMA_CALLBACKS dmaCallback;
+	uint8_t releaseEp0Flag;
+	uint8_t isReady;
+	uint8_t *privBuffAddr;
+	uintptr_t privBuffDma;
+	uint8_t endpointInList;
+	uint8_t hostRequestFlag;
+	struct VHUB_REGS *phy_regs;
+};
+
+struct GadgetRequest {
+	struct GADGET_REQ request;
+	struct GadgetEp *ep;
+	struct GADGET_DEV *dev;
+	uint8_t zlp;
+};
+
+struct GADGET_OBJ *GADGET_GetInstance(void);
+
+#endif /* __LINUX_PHYTIUM_GADGET */
+
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/host.c b/target/linux/phytium/files-5.10/drivers/usb/phytium/host.c
new file mode 100644
index 00000000000000..00d97248769ff0
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/host.c
@@ -0,0 +1,2671 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/dma-mapping.h>
+#include <linux/usb.h>
+#include<linux/usb/hcd.h>
+#include <linux/interrupt.h>
+//#include "list.h"
+#include "core.h"
+#include "dma.h"
+#include "hw-regs.h"
+
+#define DRV_NAME "phytium_usb"
+
+#define HOST_GENERIC_EP_CONTROLL 0x00
+#define HOST_GENERIC_EP_ISOC 0x01
+#define HOST_GENERIC_EP_BULK 0x02
+#define HOST_GENERIC_EP_INT 0x03
+
+#define HOST_ESTALL	1
+#define HOST_EUNHANDLED	2
+#define HOST_EAUTOACK	3
+#define HOST_ESHUTDOWN	4
+
+#define HOST_EP_NUM	16
+
+static inline struct HOST_REQ *getUsbRequestEntry(struct list_head *list)
+{
+	return (struct HOST_REQ *)((uintptr_t)list - (uintptr_t)&(((struct HOST_REQ *)0)->list));
+}
+
+static inline struct HOST_EP_PRIV *getUsbHEpPrivEntry(struct list_head *list)
+{
+	struct HOST_EP_PRIV *hostEpPriv;
+
+	if (list_empty(list))
+		return NULL;
+
+	hostEpPriv = (struct HOST_EP_PRIV *)((uintptr_t)list -
+			(uintptr_t)&(((struct HOST_EP_PRIV *)0)->node));
+
+	return hostEpPriv;
+}
+
+static struct HOST_REQ *getNextReq(struct HOST_EP *usbEp)
+{
+	struct list_head *queue;
+
+	if (!usbEp)
+		return NULL;
+
+	queue = &usbEp->reqList;
+
+	if (list_empty(queue))
+		return NULL;
+
+	return getUsbRequestEntry(queue->next);
+}
+
+static void host_SetVbus(struct HOST_CTRL *priv, uint8_t isOn)
+{
+	uint8_t otgctrl = phytium_read8(&priv->regs->otgctrl);
+
+	if (isOn) {
+		if (!(otgctrl & OTGCTRL_BUSREQ) || (otgctrl & OTGCTRL_ABUSDROP)) {
+			otgctrl &= ~OTGCTRL_ABUSDROP;
+			otgctrl |= OTGCTRL_BUSREQ;
+			phytium_write8(&priv->regs->otgctrl, otgctrl);
+		}
+		priv->otgState = HOST_OTG_STATE_A_WAIT_BCON;
+	} else {
+		if ((otgctrl & OTGCTRL_BUSREQ) || (otgctrl & OTGCTRL_ABUSDROP)) {
+			otgctrl |= OTGCTRL_ABUSDROP;
+			otgctrl &= ~OTGCTRL_BUSREQ;
+			phytium_write8(&priv->regs->otgctrl, otgctrl);
+		}
+		priv->otgState = HOST_OTG_STATE_A_IDLE;
+	}
+}
+
+static inline void disconnectHostDetect(struct HOST_CTRL *priv)
+{
+	uint8_t otgctrl, otgstate;
+	uint32_t gen_cfg;
+
+	if (!priv)
+		return;
+
+	otgctrl = phytium_read8(&priv->regs->otgctrl);
+	if ((otgctrl & OTGCTRL_ASETBHNPEN) && priv->otgState == HOST_OTG_STATE_A_SUSPEND)
+		pr_info("Device no Response\n");
+
+	phytium_write8(&priv->regs->otgirq, OTGIRQ_CONIRQ);
+retry:
+	otgstate = phytium_read8(&priv->regs->otgstate);
+	if ((otgstate == HOST_OTG_STATE_A_HOST || otgstate == HOST_OTG_STATE_B_HOST)) {
+		pr_info("IRQ OTG: DisconnIrq Babble\n");
+		goto retry;
+	}
+
+	phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX);
+	phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST | ENDPRST_IO_TX);
+	phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST);
+	phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO | 0 | 0x04);
+	phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO | FIFOCTRL_IO_TX | 0 | 0x04);
+
+	priv->portStatus = USB_PORT_STAT_POWER;
+	priv->portStatus |= USB_PORT_STAT_C_CONNECTION << 16;
+
+	if (priv->hostCallbacks.portStatusChange)
+		priv->hostCallbacks.portStatusChange(priv);
+
+	if (priv->otgState == HOST_OTG_STATE_A_SUSPEND)
+		host_SetVbus(priv, 1);
+
+	priv->otgState = HOST_OTG_STATE_A_IDLE;
+	if (priv->custom_regs) {
+		phytium_write32(&priv->custom_regs->wakeup, 1);
+	} else {
+		gen_cfg = phytium_read32(&priv->vhub_regs->gen_cfg);
+		gen_cfg |= BIT(1);
+		phytium_write32(&priv->vhub_regs->gen_cfg, gen_cfg);
+	}
+}
+
+static inline void A_IdleDetect(struct HOST_CTRL *priv, uint8_t otgstate)
+{
+	uint8_t otgctrl;
+
+	if (!priv)
+		return;
+
+	phytium_write8(&priv->regs->otgirq, OTGIRQ_IDLEIRQ);
+
+	if (otgstate != HOST_OTG_STATE_A_IDLE) {
+		pr_info("IRQ OTG: A_IDLE Babble\n");
+		return;
+	}
+
+	priv->portStatus = 0;
+	otgctrl = phytium_read8(&priv->regs->otgctrl);
+	otgctrl &= ~OTGCTRL_ASETBHNPEN;
+	phytium_write8(&priv->regs->otgctrl, otgctrl);
+
+	host_SetVbus(priv, 1);
+
+	priv->otgState = HOST_OTG_STATE_A_IDLE;
+}
+
+static inline void B_IdleDetect(struct HOST_CTRL *priv, uint8_t otgstate)
+{
+	uint8_t otgctrl, usbcs;
+
+	if (!priv)
+		return;
+
+	phytium_write8(&priv->regs->otgirq, OTGIRQ_IDLEIRQ);
+
+	if (otgstate != HOST_OTG_STATE_B_IDLE) {
+		pr_info("IRQ OTG: B_IDLE Babble\n");
+		return;
+	}
+
+	otgctrl = phytium_read8(&priv->regs->otgctrl);
+	otgctrl &= ~OTGCTRL_ASETBHNPEN;
+	phytium_write8(&priv->regs->otgctrl, otgctrl);
+
+	host_SetVbus(priv, 0);
+
+	priv->otgState = HOST_OTG_STATE_B_IDLE;
+
+	usbcs = phytium_read8(&priv->regs->usbcs);
+	usbcs &= ~USBCS_DISCON;
+	phytium_write8(&priv->regs->usbcs, usbcs);
+}
+
+static uint32_t waitForBusyBit(struct HOST_CTRL *priv, struct HostEp *hwEp)
+{
+	uint8_t *csReg;
+	uint8_t flag = CS_BUSY;
+	uint8_t buf = 0;
+	uint8_t val = CS_BUSY;
+	uint8_t otgstate;
+	uint8_t bufflag = 0;
+
+	if (!priv || !hwEp)
+		return 0;
+
+	if (hwEp->isInEp)
+		return 0;
+
+	if (hwEp->hwEpNum == 0) {
+		csReg = &priv->regs->ep0cs;
+		flag = EP0CS_TXBUSY_MASK;
+		buf = 0;
+	} else {
+		csReg = &priv->regs->ep[hwEp->hwEpNum - 1].txcs;
+		buf = phytium_read8(&priv->regs->ep[hwEp->hwEpNum - 1].txcon) & CON_BUF;
+	}
+
+	while ((val & flag) || bufflag == 0) {
+		otgstate = phytium_read8(&priv->regs->otgstate);
+		if (otgstate != HOST_OTG_STATE_B_HOST && otgstate != HOST_OTG_STATE_A_HOST) {
+			priv->ep0State = HOST_EP0_STAGE_IDLE;
+			return HOST_ESHUTDOWN;
+		}
+
+		val = phytium_read8(csReg);
+		if (((val & CS_NPAK) >> CS_NPAK_OFFSET) == buf || buf == 0)
+			bufflag = 1;
+		else
+			bufflag = 0;
+	}
+
+	return 0;
+}
+
+static inline void connectHostDetect(struct HOST_CTRL *priv, uint8_t otgState)
+{
+	uint32_t gen_cfg;
+
+	if (!priv)
+		return;
+	pr_debug("otgState:0x%x pirv->otgState:0x%x\n", otgState, priv->otgState);
+	if (priv->custom_regs) {
+		phytium_write32(&priv->custom_regs->wakeup, 0);
+	} else {
+		gen_cfg = phytium_read32(&priv->vhub_regs->gen_cfg);
+		gen_cfg &= ~BIT(1);
+		phytium_write32(&priv->vhub_regs->gen_cfg, gen_cfg);
+	}
+
+	phytium_write8(&priv->regs->otgirq, OTGIRQ_CONIRQ);
+
+	if ((otgState != HOST_OTG_STATE_A_HOST) && (otgState != HOST_OTG_STATE_B_HOST))
+		return;
+
+	if ((priv->otgState == HOST_OTG_STATE_A_PERIPHERAL)
+			|| (priv->otgState == HOST_OTG_STATE_B_PERIPHERAL))
+		priv->otgState = otgState;
+
+	priv->ep0State = HOST_EP0_STAGE_IDLE;
+
+	priv->portStatus &= ~(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED |
+			USB_PORT_STAT_ENABLE);
+
+	priv->portStatus |= USB_PORT_STAT_C_CONNECTION | (USB_PORT_STAT_C_CONNECTION << 16);
+	priv->dmaDrv->dma_controllerReset(priv->dmaController);
+	priv->port_resetting = 1;
+	host_SetVbus(priv, 1);
+
+	switch (phytium_read8(&priv->regs->speedctrl)) {
+	case SPEEDCTRL_HS:
+		priv->portStatus |= USB_PORT_STAT_HIGH_SPEED;
+		pr_debug("detect High speed device\n");
+		break;
+	case SPEEDCTRL_FS:
+		priv->portStatus &= ~(USB_PORT_STAT_HIGH_SPEED | USB_PORT_STAT_LOW_SPEED);
+		pr_debug("detect Full speed device\n");
+		break;
+	case SPEEDCTRL_LS:
+		priv->portStatus |= USB_PORT_STAT_LOW_SPEED;
+		pr_debug("detect Low speed device\n");
+		break;
+	}
+
+	priv->vBusErrCnt = 0;
+	priv->dmaDrv->dma_setHostMode(priv->dmaController);
+
+	if (priv->hostCallbacks.portStatusChange)
+		priv->hostCallbacks.portStatusChange(priv);
+
+	priv->otgState = otgState;
+}
+
+static void hostOtgIrq(struct HOST_CTRL *priv)
+{
+	uint8_t otgirq, otgien;
+	uint8_t otgstatus, otgstate;
+	uint8_t otgctrl;
+
+	if (!priv)
+		return;
+
+	otgirq = phytium_read8(&priv->regs->otgirq);
+	otgien = phytium_read8(&priv->regs->otgien);
+	otgstatus = phytium_read8(&priv->regs->otgstatus);
+	otgstate = phytium_read8(&priv->regs->otgstate);
+	otgirq &= otgien;
+
+	if (!otgirq)
+		return;
+
+	if (otgirq & OTGIRQ_BSE0SRPIRQ) {
+		otgirq &= ~OTGIRQ_BSE0SRPIRQ;
+		phytium_write8(&priv->regs->otgirq, OTGIRQ_BSE0SRPIRQ);
+
+		otgctrl = phytium_read8(&priv->regs->otgctrl);
+		otgctrl &= ~OTGIRQ_BSE0SRPIRQ;
+		phytium_write8(&priv->regs->otgctrl, otgctrl);
+	}
+
+	if (otgirq & OTGIRQ_SRPDETIRQ) {
+		otgirq &= ~OTGIRQ_SRPDETIRQ;
+		phytium_write8(&priv->regs->otgirq, OTGIRQ_SRPDETIRQ);
+
+		otgctrl = phytium_read8(&priv->regs->otgctrl);
+		otgctrl &= ~OTGIRQ_SRPDETIRQ;
+		phytium_write8(&priv->regs->otgctrl, otgctrl);
+	}
+
+	if (otgirq & OTGIRQ_VBUSERRIRQ) {
+		otgirq &= ~OTGIRQ_VBUSERRIRQ;
+		phytium_write8(&priv->regs->otgirq, OTGIRQ_VBUSERRIRQ);
+
+		if (otgstate != HOST_OTG_STATE_A_VBUS_ERR) {
+			pr_info("IRQ OTG: VBUS ERROR Babble\n");
+			return;
+		}
+
+		host_SetVbus(priv, 0);
+		priv->otgState = HOST_OTG_STATE_A_VBUS_ERR;
+		if (priv->portStatus & USB_PORT_STAT_CONNECTION) {
+			priv->portStatus = USB_PORT_STAT_POWER | (USB_PORT_STAT_C_CONNECTION << 16);
+			if (priv->hostCallbacks.portStatusChange)
+				priv->hostCallbacks.portStatusChange(priv);
+			return;
+		}
+
+		if (priv->vBusErrCnt >= 3) {
+			priv->vBusErrCnt = 0;
+			pr_info("%s %d VBUS OVER CURRENT\n", __func__, __LINE__);
+			priv->portStatus |= USB_PORT_STAT_OVERCURRENT |
+				(USB_PORT_STAT_C_OVERCURRENT << 16);
+
+			phytium_write8(&priv->regs->otgirq, OTGIRQ_IDLEIRQ);
+		} else {
+			priv->vBusErrCnt++;
+			host_SetVbus(priv, 1);
+			phytium_write8(&priv->regs->otgirq, OTGIRQ_IDLEIRQ);
+		}
+	}
+
+	if (otgirq & OTGIRQ_CONIRQ) {
+		if (priv->otgState == HOST_OTG_STATE_A_HOST ||
+				priv->otgState == HOST_OTG_STATE_B_HOST ||
+				priv->otgState == HOST_OTG_STATE_A_SUSPEND) {
+			if (otgstate == HOST_OTG_STATE_A_WAIT_VFALL ||
+					otgstate == HOST_OTG_STATE_A_WAIT_BCON ||
+					otgstate == HOST_OTG_STATE_A_SUSPEND)
+				disconnectHostDetect(priv);
+		} else if (priv->otgState != HOST_OTG_STATE_A_HOST &&
+				priv->otgState != HOST_OTG_STATE_B_HOST &&
+				priv->otgState != HOST_OTG_STATE_A_SUSPEND)
+			connectHostDetect(priv, otgstate);
+
+		phytium_write8(&priv->regs->otgirq, OTGIRQ_CONIRQ);
+	}
+
+	if (otgirq & OTGIRQ_IDLEIRQ) {
+		if (!(otgstatus & OTGSTATUS_ID))
+			A_IdleDetect(priv, otgstate);
+		else
+			B_IdleDetect(priv, otgstate);
+	}
+
+	phytium_write8(&priv->regs->otgirq, OTGIRQ_IDCHANGEIRQ |
+			OTGIRQ_SRPDETIRQ);
+}
+
+static void hostErrorIrq(struct HOST_CTRL *priv)
+{
+	uint16_t txerrirq, txerrien;
+	uint16_t rxerrirq, rxerrien;
+	uint16_t i, mask;
+
+	if (!priv)
+		return;
+
+	txerrirq = phytium_read16(&priv->regs->txerrirq);
+	txerrien = phytium_read16(&priv->regs->txerrien);
+	txerrirq &= txerrien;
+
+	rxerrirq = phytium_read16(&priv->regs->rxerrirq);
+	rxerrien = phytium_read16(&priv->regs->rxerrien);
+	rxerrirq &= rxerrirq;
+	if (!txerrirq && !rxerrirq)
+		return;
+
+	for (i = 0; i < HOST_EP_NUM; i++) {
+		mask = 1 << i;
+		if (rxerrirq & mask) {
+			phytium_write16(&priv->regs->rxerrirq, mask);
+			rxerrien &= ~mask;
+			phytium_write16(&priv->regs->rxerrien, rxerrien);
+			priv->dmaDrv->dma_errIsr(priv->dmaController, i, 0);
+		}
+
+		if (txerrirq & mask) {
+			phytium_write16(&priv->regs->txerrirq, mask);
+			txerrien &= ~mask;
+			phytium_write16(&priv->regs->txerrien, txerrien);
+			priv->dmaDrv->dma_errIsr(priv->dmaController, i, 1);
+		}
+	}
+}
+
+static uint32_t decodeErrorCode(uint8_t code)
+{
+	uint32_t status = 0;
+
+	switch (code) {
+	case ERR_NONE:
+		status = 0;
+		break;
+	case ERR_CRC:
+		pr_info("CRC Error\n");
+		status = HOST_ESHUTDOWN;
+		break;
+	case ERR_DATA_TOGGLE_MISMATCH:
+		pr_info("Toggle MisMatch Error\n");
+		status = HOST_ESHUTDOWN;
+		break;
+	case ERR_STALL:
+		pr_debug("Stall Error\n");
+		status = HOST_ESTALL;
+		break;
+	case ERR_TIMEOUT:
+		pr_debug("Timeout Error\n");
+		status = HOST_ESHUTDOWN;
+		break;
+	case ERR_PID:
+		pr_info("PID Error\n");
+		status = HOST_ESHUTDOWN;
+		break;
+	case ERR_TOO_LONG_PACKET:
+		pr_info("TOO_LONG_PACKET Error\n");
+		status = HOST_ESHUTDOWN;
+		break;
+	case ERR_DATA_UNDERRUN:
+		pr_info("UNDERRUN Error\n");
+		status = HOST_ESHUTDOWN;
+		break;
+	}
+
+	return status;
+}
+
+static struct HOST_EP_PRIV *getIntTransfer(struct list_head *head)
+{
+	struct list_head *listEntry = NULL;
+	struct HOST_EP_PRIV *usbHEpPriv = NULL;
+	struct HOST_EP_PRIV *usbHEpPrivActual = NULL;
+
+	list_for_each(listEntry, head) {
+		usbHEpPriv = getUsbHEpPrivEntry(listEntry);
+		if (!usbHEpPrivActual)
+			usbHEpPrivActual = usbHEpPriv;
+
+		if (usbHEpPriv->frame < usbHEpPrivActual->frame)
+			usbHEpPrivActual = usbHEpPriv;
+	}
+
+	return usbHEpPrivActual;
+}
+
+static void givebackRequest(struct HOST_CTRL *priv, struct HOST_REQ *usbReq, uint32_t status)
+{
+	if (!priv || !usbReq)
+		return;
+
+	list_del(&usbReq->list);
+
+	if (usbReq->status == EINPROGRESS)
+		usbReq->status = status;
+
+	if (priv->hostCallbacks.givebackRequest)
+		priv->hostCallbacks.givebackRequest(priv, usbReq, status);
+}
+
+static void hostEpProgram(struct HOST_CTRL *priv, struct HostEp *hwEp,
+		struct HOST_REQ *usbReq, uintptr_t dmaBuff, uint32_t length)
+{
+	struct HOST_EP *usbHEp;
+	struct HOST_EP_PRIV *usbEpPriv;
+	uint32_t chMaxLen;
+	uint8_t regCon = 0;
+	uint8_t ep0cs;
+	uint16_t txerrien = 0;
+	uint16_t rxerrien = 0;
+	uint32_t result;
+	uint8_t txsoftimer, rxsoftimer;
+	u8 retval = 0;
+
+	if (!priv || !hwEp || !usbReq)
+		return;
+
+	usbHEp = hwEp->scheduledUsbHEp;
+	usbEpPriv = (struct HOST_EP_PRIV *)usbHEp->hcPriv;
+
+	if (!hwEp->channel) {
+		if (usbEpPriv->type == USB_ENDPOINT_XFER_ISOC)
+			hwEp->channel = priv->dmaDrv->dma_channelAlloc(priv->dmaController,
+					!hwEp->isInEp, hwEp->hwEpNum, 1);
+		else
+			hwEp->channel = priv->dmaDrv->dma_channelAlloc(priv->dmaController,
+					!hwEp->isInEp, hwEp->hwEpNum, 0);
+	}
+
+	chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, hwEp->channel);
+
+	pr_debug("chMaxLen:0x%x buffLength:0x%x\n", chMaxLen, usbReq->buffLength);
+	if (usbReq->buffLength > chMaxLen)
+		length = chMaxLen;
+
+	switch (usbEpPriv->type) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		regCon = CON_TYPE_CONTROL;
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+		regCon = CON_TYPE_BULK;
+		break;
+	case USB_ENDPOINT_XFER_INT:
+		regCon = CON_TYPE_INT;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		if (usbEpPriv->isocEpConfigured)
+			goto dma_program;
+
+		usbEpPriv->isocEpConfigured = 1;
+		regCon = CON_TYPE_ISOC;
+		switch (usbHEp->desc.wMaxPacketSize >> 11) {
+		case 0:
+			regCon |= CON_TYPE_ISOC_1_ISOD;
+			priv->dmaDrv->dma_setMaxLength(priv->dmaController,
+					hwEp->channel, usbEpPriv->maxPacketSize);
+			break;
+		case 1:
+			regCon |= CON_TYPE_ISOC_2_ISOD;
+			priv->dmaDrv->dma_setMaxLength(priv->dmaController,
+					hwEp->channel, 2 * 1024);
+			break;
+		case 2:
+			priv->dmaDrv->dma_setMaxLength(priv->dmaController,
+					hwEp->channel, 3 * 1024);
+			regCon |= CON_TYPE_ISOC_3_ISOD;
+			break;
+		}
+		break;
+	}
+
+	if (usbEpPriv->type != USB_ENDPOINT_XFER_ISOC) {
+		if (!hwEp->hwEpNum) {
+			if (phytium_read8(&priv->regs->ep0cs) & 0x4) {
+				phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO |
+					0 | 0x4);
+				phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO |
+					FIFOCTRL_IO_TX | 0 | 0x4);
+			}
+		}
+		if (waitForBusyBit(priv, hwEp) > 0) {
+			usbReq->status = HOST_ESHUTDOWN;
+			givebackRequest(priv, usbReq, HOST_ESHUTDOWN);
+			pr_info("something error happen\n");
+			return;
+		}
+	}
+
+	if (!hwEp->isInEp) {
+		if (hwEp->hwEpNum) {
+			regCon |= hwEp->hwBuffers - 1;
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].txcon, regCon);
+			if (usbEpPriv->type != USB_ENDPOINT_XFER_ISOC) {
+				retval = priv->hostCallbacks.getEpToggle(priv,
+						usbReq->usbDev, usbEpPriv->epNum, 0);
+				if (retval) {
+					phytium_write8(&priv->regs->endprst, hwEp->hwEpNum |
+						ENDPRST_IO_TX);
+
+					phytium_write8(&priv->regs->endprst, hwEp->hwEpNum |
+						ENDPRST_TOGSETQ | ENDPRST_IO_TX | ENDPRST_FIFORST);
+				} else {
+					phytium_write8(&priv->regs->endprst, hwEp->hwEpNum |
+						ENDPRST_IO_TX);
+
+					phytium_write8(&priv->regs->endprst, hwEp->hwEpNum |
+						ENDPRST_TOGRST | ENDPRST_IO_TX | ENDPRST_FIFORST);
+				}
+			}
+
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].txcon, regCon | CON_VAL);
+			phytium_write16(&priv->regs->txmaxpack[hwEp->hwEpNum - 1],
+					usbEpPriv->maxPacketSize);
+
+			phytium_write8(&priv->regs->epExt[hwEp->hwEpNum - 1].txctrl,
+					usbEpPriv->epNum);
+
+			phytium_write8(&priv->regs->fnaddr, usbEpPriv->faddress);
+
+	//		if (usbEpPriv->type == USB_ENDPOINT_XFER_INT)
+			txsoftimer = phytium_read8(&priv->regs->txsoftimer[hwEp->hwEpNum].ctrl);
+			txsoftimer = txsoftimer | BIT(1);
+			phytium_write8(&priv->regs->txsoftimer[hwEp->hwEpNum].ctrl, txsoftimer);
+
+			phytium_write16(&priv->regs->txsoftimer[hwEp->hwEpNum].timer,
+					usbEpPriv->frame);
+
+			phytium_write8(&priv->regs->txsoftimer[hwEp->hwEpNum].ctrl, 0x83);
+		} else {
+			phytium_write8(&priv->regs->fnaddr, usbEpPriv->faddress);
+			phytium_write8(&priv->regs->ep0maxpack, usbEpPriv->maxPacketSize);
+			phytium_write8(&priv->regs->ep0ctrl, usbEpPriv->epNum);
+
+			if (priv->ep0State == HOST_EP0_STAGE_SETUP) {
+				ep0cs = phytium_read8(&priv->regs->ep0cs);
+				ep0cs |= EP0CS_HCSET;
+				phytium_write8(&priv->regs->ep0cs, ep0cs);
+			}
+		}
+
+		phytium_write16(&priv->regs->txerrirq, 1 << hwEp->hwEpNum);
+		txerrien = phytium_read16(&priv->regs->txerrien);
+		txerrien |= 1 << hwEp->hwEpNum;
+		phytium_write16(&priv->regs->txerrien, txerrien);
+	} else {
+		if (hwEp->hwEpNum) {
+			regCon |= hwEp->hwBuffers - 1;
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcon, regCon);
+
+			if (usbEpPriv->type != USB_ENDPOINT_XFER_ISOC) {
+				if (priv->hostCallbacks.getEpToggle) {
+					retval = priv->hostCallbacks.getEpToggle(priv,
+							usbReq->usbDev, usbEpPriv->epNum, 1);
+					if (retval) {
+						phytium_write8(&priv->regs->endprst, hwEp->hwEpNum);
+						phytium_write8(&priv->regs->endprst, hwEp->hwEpNum |
+								ENDPRST_TOGSETQ | ENDPRST_FIFORST);
+					} else {
+						phytium_write8(&priv->regs->endprst, hwEp->hwEpNum);
+						phytium_write8(&priv->regs->endprst, hwEp->hwEpNum |
+								ENDPRST_TOGRST | ENDPRST_FIFORST);
+					}
+				}
+			}
+
+			phytium_write16(&priv->regs->rxmaxpack[hwEp->hwEpNum - 1],
+					usbEpPriv->maxPacketSize);
+
+			phytium_write8(&priv->regs->epExt[hwEp->hwEpNum - 1].rxctrl,
+					usbEpPriv->epNum);
+
+			phytium_write8(&priv->regs->fnaddr, usbEpPriv->faddress);
+
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcs, 1);
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcs, 1);
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcs, 1);
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcs, 1);
+
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcon, regCon | CON_VAL);
+			rxsoftimer = phytium_read8(&priv->regs->rxsoftimer[hwEp->hwEpNum].ctrl);
+			rxsoftimer = rxsoftimer | BIT(1);
+			phytium_write8(&priv->regs->rxsoftimer[hwEp->hwEpNum].ctrl, rxsoftimer);
+
+			phytium_write16(&priv->regs->rxsoftimer[hwEp->hwEpNum].timer,
+					usbEpPriv->frame);
+
+			phytium_write8(&priv->regs->rxsoftimer[hwEp->hwEpNum].ctrl, 0x83);
+		} else {
+			phytium_write8(&priv->regs->fnaddr, usbEpPriv->faddress);
+			phytium_write8(&priv->regs->ep0maxpack, usbEpPriv->maxPacketSize);
+			phytium_write8(&priv->regs->ep0ctrl, usbEpPriv->epNum);
+
+			if (priv->ep0State == HOST_EP0_STAGE_IN
+					|| priv->ep0State == HOST_EP0_STAGE_STATUSIN)
+				phytium_write8(&priv->regs->ep0cs, EP0CS_HCSETTOGGLE);
+		}
+
+		phytium_write16(&priv->regs->rxerrirq, 1 << hwEp->hwEpNum);
+		rxerrien = phytium_read16(&priv->regs->rxerrien);
+		rxerrien |= 1 << hwEp->hwEpNum;
+		phytium_write16(&priv->regs->rxerrien, rxerrien);
+	}
+dma_program:
+	result = priv->dmaDrv->dma_channelProgram(priv->dmaController, hwEp->channel,
+			usbEpPriv->maxPacketSize, dmaBuff, length,
+			(void *)usbReq->isoFramesDesc, usbReq->isoFramesNumber);
+	if (result) {
+		if (!hwEp->isInEp) {
+			txerrien &= ~(1 << hwEp->hwEpNum);
+			if (hwEp->hwEpNum)
+				phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].txcon, 0x08);
+			phytium_write16(&priv->regs->txerrien, txerrien);
+		} else {
+			rxerrien &= ~(1 << hwEp->hwEpNum);
+			if (hwEp->hwEpNum)
+				phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcon, 0x08);
+			phytium_write16(&priv->regs->rxerrien, rxerrien);
+		}
+
+		priv->dmaDrv->dma_channelRelease(priv->dmaController, hwEp->channel);
+		hwEp->channel = NULL;
+	}
+}
+
+static void hostStartReq(struct HOST_CTRL *priv, struct HOST_REQ *req)
+{
+	uintptr_t dmaBuff;
+	uint32_t length;
+	struct HOST_EP *hostEp;
+	struct HOST_EP_PRIV *hostEpPriv;
+	struct HOST_EP_PRIV *hostNewEpPriv;
+	struct HOST_REQ *usbReq = NULL;
+	struct HostEp *hwEp = NULL;
+	int num;
+
+	if (!priv || !req)
+		return;
+
+	hostEp = req->hcPriv;
+	if (hostEp) {
+		hostEpPriv = (struct HOST_EP_PRIV *)hostEp->hcPriv;
+		if (hostEpPriv) {
+			hostEpPriv->genericHwEp->state = HOST_EP_BUSY;
+			switch (hostEpPriv->type) {
+			case USB_ENDPOINT_XFER_CONTROL:
+				usbReq = getNextReq(hostEp);
+
+				priv->in[HOST_GENERIC_EP_CONTROLL].scheduledUsbHEp = hostEp;
+				priv->ep0State = HOST_EP0_STAGE_SETUP;
+				hostEpPriv->currentHwEp = hostEpPriv->genericHwEp;
+				hostEpPriv->genericHwEp->scheduledUsbHEp = hostEp;
+				dmaBuff = usbReq->setupDma;
+				length = 8;
+				pr_debug("packet info: %02x %02x %04x %04x %04x\n",
+					usbReq->setup->bRequestType,
+					usbReq->setup->bRequest,
+					usbReq->setup->wValue,
+					usbReq->setup->wIndex,
+					usbReq->setup->wLength);
+				hostEpProgram(priv, hostEpPriv->genericHwEp,
+						usbReq, dmaBuff, length);
+				break;
+			case USB_ENDPOINT_XFER_BULK:
+				hwEp = hostEpPriv->genericHwEp;
+				usbReq = getNextReq(hostEp);
+				hostEpPriv->currentHwEp = hwEp;
+				hwEp->scheduledUsbHEp = hostEp;
+				dmaBuff = usbReq->buffDma + usbReq->actualLength;
+				length = usbReq->buffLength - usbReq->actualLength;
+				hostEpProgram(priv, hwEp, usbReq, dmaBuff, length);
+				break;
+			case USB_ENDPOINT_XFER_INT:
+				if (hostEpPriv->genericHwEp->scheduledUsbHEp)
+					return;
+
+				num = req->epNum - 1;
+				if (hostEpPriv->isIn)
+					hostNewEpPriv = getIntTransfer(&priv->intInHEpQueue[num]);
+				else
+					hostNewEpPriv = getIntTransfer(&priv->intOutHEpQueue[num]);
+
+				hostNewEpPriv->currentHwEp = hostEpPriv->genericHwEp;
+				hostEpPriv->genericHwEp->scheduledUsbHEp = hostNewEpPriv->usbHEp;
+				usbReq = getNextReq(hostEp);
+				dmaBuff = usbReq->buffDma + usbReq->actualLength;
+				length = usbReq->buffLength - usbReq->actualLength;
+				hostEpProgram(priv, hostEpPriv->genericHwEp,
+						usbReq, dmaBuff, length);
+				break;
+			case USB_ENDPOINT_XFER_ISOC:
+				hostEpPriv->currentHwEp = hostEpPriv->genericHwEp;
+				hostEpPriv->genericHwEp->scheduledUsbHEp = hostEp;
+				dmaBuff = req->buffDma + req->actualLength;
+				length = req->buffLength - req->actualLength;
+				hostEpProgram(priv, hostEpPriv->genericHwEp, req, dmaBuff, length);
+				break;
+			}
+		}
+	}
+}
+
+
+static void scheduleNextTransfer(struct HOST_CTRL *priv,
+		struct HOST_REQ *usbReq, struct HostEp *hwEp)
+{
+	struct HOST_EP *usbEp;
+	struct HOST_EP_PRIV *usbHEpPriv;
+	uint8_t endprst;
+	uint32_t status;
+	struct HOST_REQ *usbNextReq = NULL;
+
+	if (!priv || !usbReq || !hwEp)
+		return;
+
+	usbEp = hwEp->scheduledUsbHEp;
+	usbHEpPriv = (struct HOST_EP_PRIV *)usbEp->hcPriv;
+	if (!usbHEpPriv)
+		return;
+
+	status = (usbReq->status == EINPROGRESS) ? 0 : usbReq->status;
+	switch (usbHEpPriv->type) {
+	case USB_ENDPOINT_XFER_BULK:
+	case USB_ENDPOINT_XFER_INT:
+		if (hwEp->isInEp) {
+			phytium_write8(&priv->regs->endprst, hwEp->hwEpNum);
+			endprst = (phytium_read8(&priv->regs->endprst) & ENDPRST_TOGSETQ) ? 1 : 0;
+			if (priv->hostCallbacks.setEpToggle)
+				priv->hostCallbacks.setEpToggle(priv, usbReq->usbDev,
+						usbHEpPriv->epNum, usbHEpPriv->isIn, endprst);
+		} else {
+			if (waitForBusyBit(priv, hwEp) > 0) {
+				usbReq->status = HOST_ESHUTDOWN;
+				givebackRequest(priv, usbReq, HOST_ESHUTDOWN);
+				return;
+			}
+
+			phytium_write8(&priv->regs->endprst, hwEp->hwEpNum | ENDPRST_IO_TX);
+			endprst = (phytium_read8(&priv->regs->endprst) & ENDPRST_TOGSETQ) ? 1 : 0;
+			if (priv->hostCallbacks.setEpToggle)
+				priv->hostCallbacks.setEpToggle(priv, usbReq->usbDev,
+						usbHEpPriv->epNum, usbHEpPriv->isIn, endprst);
+		}
+		break;
+	}
+
+	if (usbHEpPriv->transferFinished)
+		givebackRequest(priv, usbReq, status);
+
+	if (list_empty(&usbEp->reqList)) {
+		if (usbHEpPriv->type == USB_ENDPOINT_XFER_CONTROL)
+			hwEp->state = HOST_EP_ALLOCATED;
+		else {
+			if (usbHEpPriv->genericHwEp == hwEp)
+				hwEp->state = HOST_EP_ALLOCATED;
+			else
+				hwEp->state = HOST_EP_FREE;
+		}
+
+		usbHEpPriv->epIsReady = 0;
+		usbHEpPriv->currentHwEp = NULL;
+		hwEp->scheduledUsbHEp = NULL;
+
+		if (hwEp->channel) {
+			priv->dmaDrv->dma_channelRelease(priv->dmaController, hwEp->channel);
+			hwEp->channel = NULL;
+		}
+
+		if (usb_endpoint_xfer_int(&usbEp->desc))
+			list_del(&usbHEpPriv->node);
+		usbHEpPriv = NULL;
+	} else {
+		if (usbHEpPriv->type == USB_ENDPOINT_XFER_INT) {
+			usbHEpPriv->currentHwEp = NULL;
+			hwEp->scheduledUsbHEp = NULL;
+		}
+
+		if (usbHEpPriv->type == USB_ENDPOINT_XFER_ISOC)
+			return;
+	}
+
+	if (usbHEpPriv) {
+		usbNextReq = getNextReq(usbHEpPriv->usbHEp);
+		hostStartReq(priv, usbNextReq);
+	}
+}
+
+static int32_t hostEp0Irq(struct HOST_CTRL *priv, uint8_t isIn)
+{
+	struct HostEp *hwEp;
+	struct HOST_EP *hostEp;
+	struct HOST_REQ *usbReq = NULL;
+	struct HOST_EP_PRIV *usbHEpPriv;
+	uint32_t status, length;
+	uint8_t usbError;
+	uint8_t nextStage = 0;
+	int ret = 0;
+
+	if (!priv)
+		return ret;
+
+	hwEp = isIn ? &priv->in[HOST_GENERIC_EP_CONTROLL] : &priv->out[HOST_GENERIC_EP_CONTROLL];
+	hostEp = hwEp->scheduledUsbHEp;
+	usbHEpPriv = (struct HOST_EP_PRIV *)hostEp->hcPriv;
+
+	usbReq = getNextReq(hostEp);
+	if (!usbReq)
+		return 0;
+
+	usbError = isIn ? phytium_read8(&priv->regs->rx0err) : phytium_read8(&priv->regs->tx0err);
+	usbError = (usbError & ERR_TYPE) >> 2;
+	status = decodeErrorCode(usbError);
+	if (status) {
+		usbReq->status = status;
+
+		if (status == HOST_ESTALL) {
+			ret = 1;
+			priv->dmaDrv->dma_controllerReset(priv->dmaController);
+		}
+
+		phytium_write16(&priv->regs->rxerrirq, 1 << hwEp->hwEpNum);
+		phytium_write16(&priv->regs->txerrirq, 1 << hwEp->hwEpNum);
+
+		phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO | 0 | 0x4);
+		phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO |
+				FIFOCTRL_IO_TX | 0 | 0x4);
+	}
+
+	length = priv->dmaDrv->dma_getActualLength(priv->dmaController, hwEp->channel);
+	priv->dmaDrv->dma_channelRelease(priv->dmaController, hwEp->channel);
+	hwEp->channel = NULL;
+
+	if (usbReq->status == EINPROGRESS && priv->ep0State < HOST_EP0_STAGE_STATUSIN) {
+		nextStage = 0;
+		switch (priv->ep0State) {
+		case HOST_EP0_STAGE_IN:
+			pr_debug("Ep0 Data IN\n");
+			usbHEpPriv->currentHwEp = &priv->out[HOST_GENERIC_EP_CONTROLL];
+			usbReq->actualLength = length;
+			priv->ep0State = HOST_EP0_STAGE_STATUSOUT;
+			break;
+		case HOST_EP0_STAGE_OUT:
+			pr_debug("Ep0 Data OUT\n");
+			usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROLL];
+			usbReq->actualLength = length;
+			priv->ep0State = HOST_EP0_STAGE_STATUSIN;
+			break;
+		case HOST_EP0_STAGE_SETUP:
+			pr_debug("Ep0 Stage Setup\n");
+			if (!usbReq->setup->wLength) {
+				pr_debug("EP0_STAGE_STATUSIN\n");
+				priv->ep0State = HOST_EP0_STAGE_STATUSIN;
+				usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROLL];
+				break;
+			} else if (usbReq->setup->bRequestType & USB_DIR_IN) {
+				pr_debug("EP0_STAGE_STAGE_IN\n");
+				priv->ep0State = HOST_EP0_STAGE_IN;
+				usbHEpPriv->currentHwEp = &priv->in[HOST_GENERIC_EP_CONTROLL];
+				nextStage = 1;
+				break;
+			}
+			priv->ep0State = HOST_EP0_STAGE_OUT;
+			nextStage = 1;
+			break;
+		case HOST_EP0_STAGE_STATUSIN:
+		case HOST_EP0_STAGE_STATUSOUT:
+		case HOST_EP0_STAGE_ACK:
+		case HOST_EP0_STAGE_IDLE:
+		default:
+			pr_debug("EP0 STAGE is %d\n", priv->ep0State);
+			break;
+		}
+
+		if (nextStage) {
+			length = usbReq->buffLength;
+			hostEpProgram(priv, usbHEpPriv->currentHwEp, usbReq,
+					usbReq->buffDma, length);
+		} else
+			hostEpProgram(priv, usbHEpPriv->currentHwEp, usbReq, usbReq->setupDma, 0);
+	} else
+		priv->ep0State = HOST_EP0_STAGE_IDLE;
+
+	if (priv->ep0State == HOST_EP0_STAGE_IDLE || usbReq->status != EINPROGRESS) {
+		usbHEpPriv->transferFinished = 1;
+		scheduleNextTransfer(priv, usbReq, hwEp);
+	}
+
+	return 0;
+}
+
+static void updateTimeIntTransfer(struct list_head *head, struct HOST_EP_PRIV *lastFinished)
+{
+	struct list_head *listEntry = NULL;
+	struct HOST_EP_PRIV *usbHEpPriv = NULL;
+	uint16_t time = lastFinished->frame;
+
+	list_for_each(listEntry, head) {
+		usbHEpPriv = getUsbHEpPrivEntry(listEntry);
+		if (usbHEpPriv == lastFinished) {
+			lastFinished->frame = lastFinished->interval;
+			continue;
+		}
+
+		if (usbHEpPriv->frame < time)
+			usbHEpPriv->frame = 0;
+		else
+			lastFinished->interval = usbHEpPriv->frame;
+	}
+}
+
+static int32_t hostEpXIrq(struct HOST_CTRL *priv, uint8_t hwEpNum, uint8_t isIn, bool resubmit)
+{
+	struct HostEp *hwEp;
+	struct HOST_EP *hostEp;
+	struct HOST_EP_PRIV *usbHEpPriv;
+	struct HOST_REQ *usbReq;
+
+	uint8_t usbError, rxcon, txcon;
+	uint32_t status, length, chMaxLen;
+
+	if (!priv)
+		return -EINVAL;
+
+	hwEp = isIn ? &priv->in[hwEpNum] : &priv->out[hwEpNum];
+	hostEp = hwEp->scheduledUsbHEp;
+	if (!hostEp)
+		return -EINVAL;
+
+	usbHEpPriv = (struct HOST_EP_PRIV *)hostEp->hcPriv;
+
+	usbReq = getNextReq(hostEp);
+	if (!usbReq)
+		return 0;
+
+	if (isIn)
+		usbError = phytium_read8(&priv->regs->epExt[hwEpNum - 1].rxerr);
+	else
+		usbError = phytium_read8(&priv->regs->epExt[hwEpNum - 1].txerr);
+
+	usbError = (usbError & ERR_TYPE) >> 2;
+	status = decodeErrorCode(usbError);
+	if (status) {
+		pr_debug("%s %d Aborting\n", __func__, __LINE__);
+		if (isIn)
+			phytium_write16(&priv->regs->rxerrirq, 1 << hwEpNum);
+		else
+			phytium_write16(&priv->regs->txerrirq, 1 << hwEpNum);
+		priv->dmaDrv->dma_channelAbort(priv->dmaController, hwEp->channel);
+	}
+
+	length = priv->dmaDrv->dma_getActualLength(priv->dmaController, hwEp->channel);
+	chMaxLen = priv->dmaDrv->dma_getMaxLength(priv->dmaController, hwEp->channel);
+
+	if (status != 0)
+		usbReq->status = status;
+
+	usbReq->actualLength += length;
+
+	if (!resubmit)
+		usbHEpPriv->transferFinished = 1;
+
+	if (length == chMaxLen) {
+		if ((usbReq->buffLength - usbReq->actualLength) == 0)
+			usbHEpPriv->transferFinished = 1;
+		else
+			usbHEpPriv->transferFinished = 0;
+	}
+
+	if (usbHEpPriv->type != USB_ENDPOINT_XFER_ISOC) {
+		if (!hwEp->isInEp) {
+			txcon = phytium_read8(&priv->regs->ep[hwEp->hwEpNum - 1].txcon);
+			txcon &= ~CON_VAL;
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].txcon, txcon);
+		} else {
+			rxcon = phytium_read8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcon);
+			rxcon &= ~CON_VAL;
+			phytium_write8(&priv->regs->ep[hwEp->hwEpNum - 1].rxcon, rxcon);
+		}
+		priv->dmaDrv->dma_channelRelease(priv->dmaController, hwEp->channel);
+		hwEp->channel = NULL;
+	}
+
+	if (usbHEpPriv->type == USB_ENDPOINT_XFER_INT) {
+		if (usbHEpPriv->isIn)
+			updateTimeIntTransfer(&priv->intInHEpQueue[hwEp->hwEpNum - 1], usbHEpPriv);
+		else
+			updateTimeIntTransfer(&priv->intOutHEpQueue[hwEp->hwEpNum - 1], usbHEpPriv);
+	}
+
+	scheduleNextTransfer(priv, usbReq, hwEp);
+
+	return 0;
+}
+
+
+static void host_CallbackTransfer(void *priv, uint8_t epNum, uint8_t isDirTx, bool resubmit)
+{
+	struct HOST_CTRL *host_priv = (struct HOST_CTRL *)priv;
+	int i;
+	int ret = 0;
+
+	if (!epNum) {
+		ret = hostEp0Irq(host_priv, !isDirTx);
+		if (resubmit | ret) {
+			for (i = 1; i < HOST_EP_NUM; i++) {
+				hostEpXIrq(host_priv, i, !isDirTx, true);
+				hostEpXIrq(host_priv, i, isDirTx, true);
+			}
+		}
+	} else
+		hostEpXIrq(host_priv, epNum, !isDirTx, false);
+}
+
+static int hc_reset(struct usb_hcd *hcd)
+{
+	hcd->speed = HCD_USB2;
+	hcd->self.root_hub->speed = USB_SPEED_HIGH;
+
+	return 0;
+}
+
+static int hc_start(struct usb_hcd *hcd)
+{
+	hcd->state = HC_STATE_RUNNING;
+	return 0;
+}
+
+static void hc_stop(struct usb_hcd *hcd)
+{
+	struct phytium_cusb *config = *(struct phytium_cusb **)hcd->hcd_priv;
+
+	if (config)
+		config->host_obj->host_stop(config->host_priv);
+
+	if (config->host_cfg.trbAddr) {
+		dma_free_coherent(config->dev, config->host_sysreq.trbMemSize,
+				config->host_cfg.trbAddr, config->host_cfg.trbDmaAddr);
+		config->host_cfg.trbAddr = NULL;
+	}
+
+	if (config->host_priv) {
+		devm_kfree(config->dev, config->host_priv);
+		config->host_priv = NULL;
+	}
+
+	hcd->state = HC_STATE_HALT;
+}
+
+static void hc_shutdown(struct usb_hcd *hcd)
+{
+}
+
+static void host_endpoint_update(struct phytium_cusb *config,
+		struct HOST_USB_DEVICE *udev, struct usb_host_endpoint *ep)
+{
+	int epnum;
+	struct HOST_EP *hostEp;
+
+	if (!config || !udev || !ep)
+		return;
+
+	epnum = usb_endpoint_num(&ep->desc);
+	if (epnum > MAX_INSTANCE_EP_NUM)
+		epnum = MAX_INSTANCE_EP_NUM;
+
+	if (usb_endpoint_dir_out(&ep->desc)) {
+		if (udev->out_ep[epnum] == NULL) {
+			hostEp = kzalloc(sizeof(struct HOST_EP) +
+				config->host_obj->host_epGetPrivateDataSize(config->host_priv),
+				GFP_ATOMIC);
+			udev->out_ep[epnum] = hostEp;
+		} else
+			hostEp = udev->out_ep[epnum];
+	} else {
+		if (udev->in_ep[epnum] == NULL) {
+			hostEp = kzalloc(sizeof(struct HOST_EP) +
+				config->host_obj->host_epGetPrivateDataSize(config->host_priv),
+				GFP_ATOMIC);
+			udev->in_ep[epnum] = hostEp;
+		} else
+			hostEp = udev->in_ep[epnum];
+	}
+
+	hostEp->desc = *(struct usb_endpoint_descriptor *)(&ep->desc);
+	hostEp->userExt = (void *)ep;
+	INIT_LIST_HEAD(&hostEp->reqList);
+	hostEp->hcPriv = &((uint8_t *)hostEp)[sizeof(struct HOST_EP)];
+}
+
+static int hc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
+{
+	unsigned long flags;
+	u32 isoFrameSize;
+	int retval;
+	int index;
+	struct HOST_REQ *req;
+	struct HOST_CTRL *priv;
+	struct HOST_USB_DEVICE *usbDev;
+	struct usb_host_endpoint *host_ep;
+	struct usb_endpoint_descriptor *host_ep_desc;
+	struct phytium_cusb *config = *(struct phytium_cusb **)hcd->hcd_priv;
+
+	if (!config)
+		return -ENODEV;
+
+	priv = config->host_priv;
+	if (!priv)
+		return -ENODEV;
+
+	usbDev = priv->host_devices_table[urb->dev->slot_id];
+	if (!usbDev)
+		return -ENODEV;
+
+	host_ep = urb->ep;
+	host_ep_desc = &host_ep->desc;
+
+	spin_lock_irqsave(&config->lock, flags);
+	retval = usb_hcd_link_urb_to_ep(hcd, urb);
+	if (retval < 0) {
+		spin_unlock_irqrestore(&config->lock, flags);
+		return retval;
+	}
+	spin_unlock_irqrestore(&config->lock, flags);
+	isoFrameSize = urb->number_of_packets * sizeof(struct HOST_ISOFRAMESDESC);
+	req = kzalloc((sizeof(struct HOST_REQ) +
+				isoFrameSize), mem_flags);
+	if (!req) {
+		spin_lock_irqsave(&config->lock, flags);
+		usb_hcd_unlink_urb_from_ep(hcd, urb);
+		spin_unlock_irqrestore(&config->lock, flags);
+		return -ENOMEM;
+	}
+
+	req->isoFramesDesc = NULL;
+	req->isoFramesNumber = urb->number_of_packets;
+	req->epNum = usb_endpoint_num(host_ep_desc);
+	if (req->epNum > MAX_INSTANCE_EP_NUM)
+		req->epNum = MAX_INSTANCE_EP_NUM;
+
+	if (usb_endpoint_dir_in(host_ep_desc)) {
+		if (!usbDev->in_ep[req->epNum])
+			host_endpoint_update(config, usbDev, host_ep);
+	} else {
+		if (!usbDev->out_ep[req->epNum])
+			host_endpoint_update(config, usbDev, host_ep);
+	}
+
+	if (usb_endpoint_xfer_isoc(host_ep_desc)) {
+		req->isoFramesDesc = (struct HOST_ISOFRAMESDESC *)(&req[1]);
+		for (index = 0; index < urb->number_of_packets; index++) {
+			req->isoFramesDesc[index].length = urb->iso_frame_desc[index].length;
+			req->isoFramesDesc[index].offset = urb->iso_frame_desc[index].offset;
+		}
+	}
+
+	spin_lock_irqsave(&config->lock, flags);
+	INIT_LIST_HEAD(&req->list);
+	req->userExt = (void *)urb;
+	req->actualLength = urb->actual_length;
+	req->bufAddress = urb->transfer_buffer;
+	req->buffDma = urb->transfer_dma;
+	req->buffLength = urb->transfer_buffer_length;
+	req->epIsIn = usb_endpoint_dir_in(host_ep_desc);
+	req->eptype = usb_endpoint_type(host_ep_desc);
+	req->faddress = usb_pipedevice(urb->pipe);
+	req->interval = urb->interval;
+	req->reqUnlinked = 0;
+	req->setup = (struct usb_ctrlrequest *)urb->setup_packet;
+	req->setupDma = urb->setup_dma;
+	req->status = EINPROGRESS;
+	req->usbDev = &usbDev->udev;
+	req->usbEp = req->epIsIn ? usbDev->in_ep[req->epNum] : usbDev->out_ep[req->epNum];
+	if (!req->epNum)
+		usbDev->ep0_hep.desc.wMaxPacketSize = urb->dev->ep0.desc.wMaxPacketSize;
+
+	req->hcPriv = (void *)req->usbEp;
+	urb->hcpriv = req;
+	host_ep->hcpriv = (void *)usbDev;
+	retval = config->host_obj->host_reqQueue(config->host_priv, req);
+	if (retval) {
+		usb_hcd_unlink_urb_from_ep(hcd, urb);
+		urb->hcpriv = NULL;
+		spin_unlock_irqrestore(&config->lock, flags);
+		kfree(req);
+		return -retval;
+	}
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+static int hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+{
+	unsigned long flags;
+	struct HOST_CTRL *priv;
+	int ret = 0;
+	struct phytium_cusb *config = *(struct phytium_cusb **)hcd->hcd_priv;
+
+	if (!config)
+		return -ENODEV;
+
+	priv = config->host_priv;
+	if (!priv->host_devices_table[urb->dev->slot_id])
+		return -ENODEV;
+
+	spin_lock_irqsave(&config->lock, flags);
+	if (usb_hcd_check_unlink_urb(hcd, urb, status))
+		goto done;
+
+	if (!urb->hcpriv)
+		goto err_giveback;
+
+	ret = config->host_obj->host_reqDequeue(priv, urb->hcpriv, status);
+	kfree(urb->hcpriv);
+	urb->hcpriv = NULL;
+done:
+	spin_unlock_irqrestore(&config->lock, flags);
+	return ret;
+
+err_giveback:
+	kfree(urb->hcpriv);
+	usb_hcd_unlink_urb_from_ep(hcd, urb);
+	spin_unlock_irqrestore(&config->lock, flags);
+	usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
+	return ret;
+}
+
+static void hc_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ld_ep)
+{
+	struct HOST_USB_DEVICE *usbDev;
+	int ep_num = usb_endpoint_num(&ld_ep->desc);
+
+	if (ep_num > MAX_INSTANCE_EP_NUM)
+		ep_num = MAX_INSTANCE_EP_NUM;
+
+	usbDev = (struct HOST_USB_DEVICE *)ld_ep->hcpriv;
+	if (!usbDev)
+		return;
+
+	if (ld_ep->desc.bEndpointAddress) {
+		if (usb_endpoint_dir_in(&ld_ep->desc)) {
+			if (!usbDev->in_ep[ep_num]) {
+				usbDev->in_ep[ep_num]->userExt = NULL;
+				INIT_LIST_HEAD(&usbDev->in_ep[ep_num]->reqList);
+				kfree(usbDev->in_ep[ep_num]);
+				usbDev->in_ep[ep_num] = NULL;
+			}
+		} else {
+			if (!usbDev->out_ep[ep_num]) {
+				usbDev->out_ep[ep_num]->userExt = NULL;
+				INIT_LIST_HEAD(&usbDev->out_ep[ep_num]->reqList);
+				kfree(usbDev->out_ep[ep_num]);
+				usbDev->out_ep[ep_num] = NULL;
+			}
+		}
+	}
+}
+
+static int hc_get_frame(struct usb_hcd *hcd)
+{
+	return 0;
+}
+
+static int hc_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+{
+	struct HOST_USB_DEVICE *usbDev;
+	struct phytium_cusb *config;
+	struct HOST_CTRL *priv;
+	unsigned long flags = 0;
+	int index;
+	int slot = -EINVAL;
+
+	if (!hcd || !udev)
+		return -EINVAL;
+
+	config = *(struct phytium_cusb **)hcd->hcd_priv;
+	if (!config)
+		return 0;
+
+	spin_lock_irqsave(&config->lock, flags);
+	priv = config->host_priv;
+	for (index = 0; index < MAX_SUPPORTED_DEVICES; index++) {
+		if (priv->host_devices_table[index] == NULL) {
+			slot = index;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	if (slot < 0)
+		return -ENOMEM;
+
+	usbDev = kzalloc((sizeof(struct HOST_USB_DEVICE) +
+				config->host_obj->host_epGetPrivateDataSize(priv)), GFP_KERNEL);
+	if (!usbDev)
+		return -ENOMEM;
+
+	usbDev->ep0_hep.hcPriv = &((uint8_t *)usbDev)[sizeof(struct HOST_USB_DEVICE)];
+	usbDev->udev.userExt = (void *)usbDev;
+	usbDev->ld_udev = udev;
+	usbDev->ld_udev->slot_id = slot;
+	usbDev->ep0_hep.desc.bLength = 7;
+	usbDev->ep0_hep.desc.bDescriptorType = USB_DT_ENDPOINT;
+	usbDev->in_ep[0] = &usbDev->ep0_hep;
+	usbDev->out_ep[0] = &usbDev->ep0_hep;
+	INIT_LIST_HEAD(&usbDev->ep0_hep.reqList);
+
+	priv->host_devices_table[slot] = usbDev;
+
+	return 1;
+}
+
+static void hc_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+{
+	struct HOST_CTRL *priv;
+	struct HOST_USB_DEVICE *usbDev;
+	struct phytium_cusb *config;
+	int i;
+
+	if (!hcd || !udev)
+		return;
+
+	config = *(struct phytium_cusb **)(hcd->hcd_priv);
+	if (!config)
+		return;
+
+	priv = (struct HOST_CTRL *)config->host_priv;
+	usbDev = priv->host_devices_table[udev->slot_id];
+	if (!usbDev)
+		return;
+
+	usbDev->in_ep[0] = NULL;
+	usbDev->out_ep[0] = NULL;
+	for (i = 1; i < HOST_EP_NUM; i++) {
+		if (usbDev->in_ep[i])
+			hc_endpoint_disable(hcd,
+					(struct usb_host_endpoint *)usbDev->in_ep[i]->userExt);
+		if (usbDev->out_ep[i])
+			hc_endpoint_disable(hcd,
+					(struct usb_host_endpoint *)usbDev->out_ep[i]->userExt);
+	}
+
+	priv->host_devices_table[udev->slot_id] = NULL;
+	usbDev->ld_udev->slot_id = 0;
+	usbDev->udev.userExt = (void *)NULL;
+	kfree(usbDev);
+}
+
+static int hc_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
+{
+	struct HOST_CTRL *priv;
+	struct HOST_USB_DEVICE *usb_device;
+	struct phytium_cusb *config;
+
+	if (!hcd || !udev)
+		return -EINVAL;
+
+	config = *(struct phytium_cusb **)hcd->hcd_priv;
+	priv = (struct HOST_CTRL *)config->host_priv;
+	usb_device = priv->host_devices_table[udev->slot_id];
+	if (!usb_device)
+		return -ENODEV;
+
+	usb_device->udev.speed = usb_device->ld_udev->speed;
+	usb_device->udev.devnum = usb_device->ld_udev->devnum;
+
+	if (USB_SPEED_HIGH == usb_device->udev.speed || USB_SPEED_FULL == usb_device->udev.speed)
+		usb_device->ep0_hep.desc.wMaxPacketSize = 64;
+	else
+		usb_device->ep0_hep.desc.wMaxPacketSize = 8;
+
+	pr_debug("speed:%d ep0 wMaxPacketSize:%d\n", usb_device->udev.speed,
+			usb_device->ep0_hep.desc.wMaxPacketSize);
+
+	return 0;
+}
+
+static int hc_update_device(struct usb_hcd *hcd, struct usb_device *udev)
+{
+	struct HOST_CTRL *priv;
+	struct HOST_USB_DEVICE *usb_device;
+	struct phytium_cusb *config;
+
+	if (!hcd || !udev)
+		return -EINVAL;
+
+	config = *(struct phytium_cusb **)(hcd->hcd_priv);
+	priv = (struct HOST_CTRL *)config->host_priv;
+
+	usb_device = priv->host_devices_table[udev->slot_id];
+	if (!usb_device)
+		return -ENODEV;
+
+	usb_device->udev.devnum = udev->devnum;
+
+	return 0;
+}
+
+static int hc_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
+		struct usb_host_endpoint *ep)
+{
+	return 0;
+}
+
+static int hc_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
+		struct usb_host_endpoint *ep)
+{
+	return 0;
+}
+
+static int hc_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+	struct HOST_CTRL *priv;
+	struct phytium_cusb *config = *(struct phytium_cusb **)hcd->hcd_priv;
+
+	if (!config)
+		return 0;
+
+	priv = (struct HOST_CTRL *)config->host_priv;
+	if (!priv)
+		return 0;
+
+	if (priv->portStatus & 0xffff0000) {
+		*buf = 0x02;
+		return 1;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int hc_bus_suspend(struct usb_hcd *hcd)
+{
+	unsigned long flags;
+	struct phytium_cusb *config = *(struct phytium_cusb **)(hcd->hcd_priv);
+
+	if (!config)
+		return 0;
+
+	spin_lock_irqsave(&config->lock, flags);
+	hcd->state = HC_STATE_SUSPENDED;
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+
+static int hc_bus_resume(struct usb_hcd *hcd)
+{
+	unsigned long flags;
+	struct phytium_cusb *config = *(struct phytium_cusb **)(hcd->hcd_priv);
+
+	if (!config)
+		return 0;
+
+	spin_lock_irqsave(&config->lock, flags);
+	hcd->state = HC_STATE_RESUMING;
+	spin_unlock_irqrestore(&config->lock, flags);
+	return 0;
+}
+#endif
+
+static void host_giveback_request(struct HOST_CTRL *priv,
+		struct HOST_REQ *req, uint32_t status)
+{
+	struct urb *urb_req;
+	int urb_status = 0;
+	int i = 0;
+	struct phytium_cusb *config;
+
+	if (!priv || !req)
+		return;
+
+	urb_req = req->userExt;
+	urb_req->actual_length = req->actualLength;
+
+	switch (status) {
+	case HOST_ESTALL:
+		urb_status = -EPIPE;
+		break;
+	case HOST_EUNHANDLED:
+		urb_status = -EPROTO;
+		break;
+	case HOST_ESHUTDOWN:
+		urb_status = -ESHUTDOWN;
+		break;
+	default:
+		urb_status = status;
+	}
+	pr_debug("complete %p %pS (%d) dev%d ep%d%s %d/%d\n",
+			urb_req, urb_req->complete, urb_status,
+			usb_pipedevice(urb_req->pipe),
+			usb_pipeendpoint(urb_req->pipe),
+			usb_pipein(urb_req->pipe) ? "in" : "out",
+			urb_req->actual_length,
+			urb_req->transfer_buffer_length);
+
+	if (usb_endpoint_xfer_isoc(&urb_req->ep->desc)) {
+		for (i = 0; i < urb_req->number_of_packets; i++) {
+			urb_req->iso_frame_desc[i].status = 0;
+			urb_req->iso_frame_desc[i].actual_length = req->isoFramesDesc[i].length;
+		}
+	}
+
+	config = dev_get_drvdata(priv->dev);
+	usb_hcd_unlink_urb_from_ep(config->hcd, urb_req);
+	spin_unlock(&config->lock);
+	usb_hcd_giveback_urb(config->hcd, urb_req, urb_status);
+	kfree(req);
+	spin_lock(&config->lock);
+}
+
+static void host_rh_port_status_change(struct HOST_CTRL *priv)
+{
+	uint32_t statusHub;
+	char *status;
+	uint32_t retval;
+	struct usb_ctrlrequest setup;
+	struct phytium_cusb *config;
+
+	if (!priv)
+		return;
+
+	config = dev_get_drvdata(priv->dev);
+	if (!config)
+		return;
+
+	status = (char *)&statusHub;
+	hc_hub_status_data(config->hcd, status);
+
+	if (status) {
+		setup.bRequestType = USB_TYPE_CLASS | USB_RECIP_OTHER | USB_DIR_IN;//to host
+		setup.bRequest = USB_REQ_GET_STATUS;
+		setup.wValue = 0;
+		setup.wIndex = 1;
+		setup.wLength = 4;
+		retval = config->host_obj->host_vhubControl(priv, &setup, (uint8_t *)&statusHub);
+		if (retval)
+			return;
+
+		if (status[1] & USB_PORT_STAT_C_CONNECTION) {
+			if (status[0] & USB_PORT_STAT_CONNECTION) {
+				if (config->hcd->status_urb)
+					usb_hcd_poll_rh_status(config->hcd);
+				else
+					usb_hcd_resume_root_hub(config->hcd);
+			} else {
+				usb_hcd_resume_root_hub(config->hcd);
+				usb_hcd_poll_rh_status(config->hcd);
+			}
+		}
+	} else
+		usb_hcd_resume_root_hub(config->hcd);
+}
+
+static void host_set_ep_toggle(struct HOST_CTRL *priv,
+		struct HOST_DEVICE *udev, u8 ep_num, u8 is_in, u8 toggle)
+{
+	struct HOST_USB_DEVICE *device;
+
+	if (!priv || !udev)
+		return;
+
+	device = (struct HOST_USB_DEVICE *)udev->userExt;
+
+	usb_settoggle(device->ld_udev, ep_num, !is_in, toggle);
+}
+
+static u8 host_get_ep_toggle(struct HOST_CTRL *priv,
+		struct HOST_DEVICE *udev, u8 ep_num, u8 is_in)
+{
+	struct HOST_USB_DEVICE *device;
+
+	if (!priv || !udev)
+		return 0;
+
+	device = (struct HOST_USB_DEVICE *)udev->userExt;
+
+	return usb_gettoggle(device->ld_udev, ep_num, !is_in);
+}
+
+static uint32_t initEndpoints(struct HOST_CTRL *priv)
+{
+	int epNum;
+
+	if (!priv)
+		return 0;
+
+	priv->hwEpInCount = 0;
+	priv->hwEpOutCount = 0;
+	phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO | 0);
+	phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO | FIFOCTRL_IO_TX | 0);
+
+	for (epNum = 0; epNum < HOST_EP_NUM; epNum++) {
+		priv->in[epNum].isInEp = 1;
+		priv->in[epNum].hwEpNum = epNum;
+		if (priv->hostCfg.epIN[epNum].bufferingValue) {
+			priv->in[epNum].hwMaxPacketSize = priv->hostCfg.epIN[epNum].maxPacketSize;
+			priv->in[epNum].hwBuffers = priv->hostCfg.epIN[epNum].bufferingValue;
+			priv->in[epNum].state = HOST_EP_FREE;
+			priv->in[epNum].channel = NULL;
+			priv->hwEpInCount++;
+
+			if (epNum) {
+				phytium_write16(&priv->regs->rxstaddr[epNum - 1].addr,
+						priv->hostCfg.epIN[epNum].startBuf);
+				phytium_write8(&priv->regs->ep[epNum - 1].rxcon, 0x08);
+				phytium_write8(&priv->regs->fifoctrl, FIFOCTRL_FIFOAUTO | epNum);
+				phytium_write8(&priv->regs->irqmode[epNum - 1].inirqmode, 0x80);
+			}
+		} else
+			priv->in[epNum].state = HOST_EP_NOT_IMPLEMENTED;
+
+		priv->out[epNum].isInEp = 0;
+		priv->out[epNum].hwEpNum = epNum;
+		if (priv->hostCfg.epOUT[epNum].bufferingValue) {
+			priv->out[epNum].hwMaxPacketSize = priv->hostCfg.epOUT[epNum].maxPacketSize;
+			priv->out[epNum].hwBuffers = priv->hostCfg.epOUT[epNum].bufferingValue;
+			priv->out[epNum].state = HOST_EP_FREE;
+			priv->out[epNum].channel = NULL;
+			priv->hwEpInCount++;
+
+			if (epNum) {
+				phytium_write16(&priv->regs->txstaddr[epNum - 1].addr,
+						priv->hostCfg.epOUT[epNum].startBuf);
+				phytium_write8(&priv->regs->ep[epNum - 1].txcon, 0x08);
+				phytium_write8(&priv->regs->fifoctrl,
+						FIFOCTRL_FIFOAUTO | FIFOCTRL_IO_TX | epNum);
+				phytium_write8(&priv->regs->irqmode[epNum - 1].outirqmode, 0x80);
+			}
+		} else
+			priv->out[epNum].state = HOST_EP_NOT_IMPLEMENTED;
+	}
+
+	return 0;
+}
+
+int32_t hostInit(struct HOST_CTRL *priv, struct HOST_CFG *config,
+		struct HOST_CALLBACKS *callbacks, struct device *pdev, bool isVhubHost)
+{
+	int index;
+
+	if (!config || !priv || !callbacks || !pdev)
+		return -EINVAL;
+
+	priv->dev = pdev;
+	priv->hostCallbacks = *callbacks;
+	priv->hostCfg = *config;
+	priv->regs = (struct HW_REGS *)config->regBase;
+	priv->hostDrv = HOST_GetInstance();
+
+	priv->dmaDrv = DMA_GetInstance();
+	priv->dmaCfg.dmaModeRx = 0xFFFF;
+	priv->dmaCfg.dmaModeTx = 0xFFFF;
+	priv->dmaCfg.regBase = config->regBase + 0x400;
+	priv->dmaCfg.trbAddr = config->trbAddr;
+	priv->dmaCfg.trbDmaAddr = config->trbDmaAddr;
+	priv->dmaCallback.complete = host_CallbackTransfer;
+
+	priv->dmaController = (void *)(priv + 1);
+	priv->dmaDrv->dma_init(priv->dmaController, &priv->dmaCfg, &priv->dmaCallback);
+	priv->dmaDrv->dma_setParentPriv(priv->dmaController, priv);
+
+	INIT_LIST_HEAD(&priv->ctrlHEpQueue);
+
+	for (index = 0; index < MAX_INSTANCE_EP_NUM; index++) {
+		INIT_LIST_HEAD(&priv->isoInHEpQueue[index]);
+		INIT_LIST_HEAD(&priv->isoOutHEpQueue[index]);
+		INIT_LIST_HEAD(&priv->intInHEpQueue[index]);
+		INIT_LIST_HEAD(&priv->intOutHEpQueue[index]);
+		INIT_LIST_HEAD(&priv->bulkInHEpQueue[index]);
+		INIT_LIST_HEAD(&priv->bulkOutHEpQueue[index]);
+	}
+
+	phytium_write8(&priv->regs->cpuctrl, BIT(1));
+	phytium_write8(&priv->regs->otgctrl, OTGCTRL_ABUSDROP);
+	phytium_write8(&priv->regs->ep0maxpack, 0x40);
+
+	//disable interrupts
+	phytium_write8(&priv->regs->otgien, 0x0);
+	phytium_write8(&priv->regs->usbien, 0x0);
+	phytium_write16(&priv->regs->txerrien, 0x0);
+	phytium_write16(&priv->regs->rxerrien, 0x0);
+
+	//clear all interrupt except otg idle irq
+	phytium_write8(&priv->regs->otgirq, 0xFE);
+	phytium_write8(&priv->regs->usbirq, 0xFF);
+	phytium_write16(&priv->regs->txerrirq, 0xFF);
+	phytium_write16(&priv->regs->rxerrirq, 0xFF);
+
+	phytium_write8(&priv->regs->tawaitbcon, 0x80);
+
+	initEndpoints(priv);
+	priv->otgState = HOST_OTG_STATE_B_IDLE;
+
+	//reset all endpoint
+	phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX);
+	phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST | ENDPRST_IO_TX);
+	phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST);
+
+	if (isVhubHost)
+		priv->vhub_regs = (struct VHUB_REGS *)(config->phy_regBase);
+	else
+		priv->custom_regs = (struct CUSTOM_REGS *)(config->phy_regBase);
+
+	return 0;
+}
+
+void hostDestroy(struct HOST_CTRL *priv)
+{
+}
+
+void hostStart(struct HOST_CTRL *priv)
+{
+	uint8_t otgstate, usbien;
+
+	if (!priv)
+		return;
+
+	priv->dmaDrv->dma_start(priv->dmaController);
+	usbien = phytium_read8(&priv->regs->usbien);
+	usbien = usbien | USBIR_URES | USBIR_SUSP;
+	phytium_write8(&priv->regs->usbien, usbien);
+retry:
+	otgstate = phytium_read8(&priv->regs->otgstate);
+	switch (otgstate) {
+	case HOST_OTG_STATE_A_IDLE:
+		priv->ep0State = HOST_EP0_STAGE_IDLE;
+		priv->otgState = HOST_OTG_STATE_A_IDLE;
+		phytium_write8(&priv->regs->otgirq, OTGIRQ_IDLEIRQ);
+		host_SetVbus(priv, 1);
+		break;
+	case HOST_OTG_STATE_B_IDLE:
+		host_SetVbus(priv, 1);
+		break;
+	case HOST_OTG_STATE_A_WAIT_VFALL:
+		goto retry;
+	}
+
+	phytium_write8(&priv->regs->otgien, OTGIRQ_CONIRQ |
+			OTGIRQ_VBUSERRIRQ | OTGIRQ_SRPDETIRQ);
+}
+
+void hostStop(struct HOST_CTRL *priv)
+{
+	if (!priv)
+		return;
+
+	phytium_write8(&priv->regs->otgien, 0x0);
+	phytium_write8(&priv->regs->usbien, 0x0);
+	phytium_write16(&priv->regs->txerrien, 0x0);
+	phytium_write16(&priv->regs->rxerrien, 0x0);
+
+	phytium_write8(&priv->regs->otgirq, 0xFE);
+	phytium_write8(&priv->regs->usbirq, 0xFF);
+	phytium_write16(&priv->regs->txerrirq, 0xFF);
+	phytium_write16(&priv->regs->rxerrirq, 0xFF);
+
+	host_SetVbus(priv, 0);
+	priv->dmaDrv->dma_stop(priv->dmaController);
+}
+
+static void handleReset(struct HOST_CTRL *priv)
+{
+	if (!priv)
+		return;
+
+	if (priv->otgState == HOST_OTG_STATE_A_WAIT_BCON
+			|| priv->otgState == HOST_OTG_STATE_B_WAIT_ACON) {
+		switch (phytium_read8(&priv->regs->speedctrl)) {
+		case SPEEDCTRL_HS:
+			priv->portStatus |= USB_PORT_STAT_HIGH_SPEED;
+			break;
+		case SPEEDCTRL_FS:
+			priv->portStatus &= ~(USB_PORT_STAT_HIGH_SPEED | USB_PORT_STAT_LOW_SPEED);
+			break;
+		case SPEEDCTRL_LS:
+			priv->portStatus |= USB_PORT_STAT_LOW_SPEED;
+			break;
+		}
+
+		priv->dmaDrv->dma_setHostMode(priv->dmaController);
+
+		if (priv->hostCallbacks.portStatusChange)
+			priv->hostCallbacks.portStatusChange(priv);
+
+		switch (phytium_read8(&priv->regs->otgstate)) {
+		case HOST_OTG_STATE_B_HOST:
+			priv->otgState = HOST_OTG_STATE_B_HOST;
+			break;
+		case HOST_OTG_STATE_A_HOST:
+			break;
+		default:
+			priv->otgState = HOST_OTG_STATE_A_HOST;
+			break;
+		}
+	}
+}
+
+void hostIsr(struct HOST_CTRL *priv)
+{
+	uint8_t usbirq, usbien;
+
+	if (!priv)
+		return;
+
+	usbirq = phytium_read8(&priv->regs->usbirq);
+	usbien = phytium_read8(&priv->regs->usbien);
+	pr_debug("raw usbirq:0x%x usbien:0x%x\n", usbirq, usbien);
+	usbirq = usbirq & usbien;
+
+	hostErrorIrq(priv);
+	hostOtgIrq(priv);
+
+	if (!usbirq)
+		goto DMA_IRQ;
+
+	if (usbirq & USBIR_URES) {
+		phytium_write8(&priv->regs->usbirq, USBIR_URES);
+		priv->port_resetting = 0;
+		handleReset(priv);
+	}
+
+	if (usbirq & USBIR_SOF)
+		phytium_write8(&priv->regs->usbirq, USBIR_SOF);
+
+	if (usbirq & USBIR_SUSP) {
+		pr_debug("clear suspend irq\n");
+		phytium_write8(&priv->regs->usbirq, USBIR_SUSP);
+		phytium_write8(&priv->regs->clkgate, 0x7);
+	}
+
+	return;
+DMA_IRQ:
+	priv->dmaDrv->dma_isr(priv->dmaController);
+}
+
+int32_t hostEpDisable(struct HOST_CTRL *priv, struct HOST_EP *ep)
+{
+	return 0;
+}
+
+unsigned int get_endpoint_interval(struct usb_endpoint_descriptor desc,
+		int speed)
+{
+	unsigned int interval = 0;
+
+	switch (speed) {
+	case USB_SPEED_HIGH:
+		if (usb_endpoint_xfer_control(&desc) || usb_endpoint_xfer_bulk(&desc)) {
+			if (desc.bInterval == 0)
+				return interval;
+			interval = fls(desc.bInterval) - 1;
+			interval = clamp_val(interval, 0, 15);
+			interval = 1 << interval;
+			if (interval != desc.bInterval)
+				pr_debug("rounding to %d microframes, desc %d microframes\n",
+						interval, desc.bInterval);
+			break;
+		}
+
+		if (usb_endpoint_xfer_isoc(&desc) || usb_endpoint_xfer_int(&desc)) {
+			interval = clamp_val(desc.bInterval, 1, 16) - 1;
+			interval = 1 << interval;
+			if (interval != desc.bInterval - 1)
+				pr_debug("rounding to %d %sframes\n", interval,
+						speed == USB_SPEED_FULL ? "" : "micro");
+		}
+		break;
+	case USB_SPEED_FULL:
+		if (usb_endpoint_xfer_isoc(&desc)) {
+			interval = clamp_val(desc.bInterval, 1, 16) - 1;
+			if (interval != desc.bInterval - 1)
+				pr_debug("rounding to %d %sframes\n", 1 << interval,
+						speed == USB_SPEED_FULL ? "" : "micro");
+			interval += 3;
+			break;
+		}
+	/* fall through */
+	case USB_SPEED_LOW:
+		if (usb_endpoint_xfer_int(&desc) || usb_endpoint_xfer_isoc(&desc)) {
+			interval = fls(desc.bInterval * 8) - 1;
+			interval = clamp_val(interval, 3, 10);
+			if ((1 << interval) != desc.bInterval * 8)
+				pr_debug("rounding to %d microframes, desc %d microframes\n",
+						1 << interval, desc.bInterval);
+		}
+	}
+
+	return interval;
+}
+
+int32_t hostReqQueue(struct HOST_CTRL *priv, struct HOST_REQ *req)
+{
+	struct HOST_EP_PRIV *hostEpPriv;
+	struct list_head *hEpQueue = NULL;
+	uint8_t idleQueue = 0;
+
+	if (!priv || !req)
+		return -EINVAL;
+
+	list_add_tail((struct list_head *)&req->list, (struct list_head *)&req->usbEp->reqList);
+	hostEpPriv = (struct HOST_EP_PRIV *)req->usbEp->hcPriv;
+
+	if (hostEpPriv->epIsReady) {
+		if (usb_endpoint_xfer_isoc(&req->usbEp->desc)) {
+			hostEpPriv->isocEpConfigured = 1;
+			hostStartReq(priv, req);
+		}
+		return 0;
+	}
+
+	hostEpPriv->epIsReady = 1;
+	hostEpPriv->maxPacketSize = req->usbEp->desc.wMaxPacketSize;
+	hostEpPriv->interval = req->interval;
+	hostEpPriv->epNum = req->usbEp->desc.bEndpointAddress & 0xf;
+	hostEpPriv->faddress = req->faddress;
+	hostEpPriv->usbHEp = req->usbEp;
+	hostEpPriv->isIn = req->epIsIn;
+
+	hostEpPriv->frame = get_endpoint_interval(req->usbEp->desc, req->usbDev->speed);
+	hostEpPriv->interval = hostEpPriv->frame;
+	switch (usb_endpoint_type(&req->usbEp->desc)) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		hostEpPriv->isIn = 0;
+		hEpQueue = &priv->ctrlHEpQueue;
+		hostEpPriv->type = USB_ENDPOINT_XFER_CONTROL;
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+		hEpQueue = hostEpPriv->isIn ? &priv->bulkInHEpQueue[req->epNum - 1] :
+			&priv->bulkOutHEpQueue[req->epNum - 1];
+		hostEpPriv->type = USB_ENDPOINT_XFER_BULK;
+		break;
+	case USB_ENDPOINT_XFER_INT:
+		hEpQueue = hostEpPriv->isIn ? &priv->intInHEpQueue[req->epNum - 1] :
+			&priv->intOutHEpQueue[req->epNum - 1];
+		hostEpPriv->type = USB_ENDPOINT_XFER_INT;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		hEpQueue = hostEpPriv->isIn ? &priv->isoInHEpQueue[req->epNum - 1] :
+			&priv->isoOutHEpQueue[req->epNum - 1];
+		hostEpPriv->type = USB_ENDPOINT_XFER_ISOC;
+		break;
+	default:
+		break;
+	}
+
+	if (hostEpPriv->isIn)
+		hostEpPriv->genericHwEp = &priv->in[req->epNum];
+	else
+		hostEpPriv->genericHwEp = &priv->out[req->epNum];
+
+	hostEpPriv->genericHwEp->state = HOST_EP_ALLOCATED;
+	hostEpPriv->genericHwEp->refCount++;
+
+	if (list_empty(hEpQueue)) {
+		if (hostEpPriv->genericHwEp->state == HOST_EP_BUSY) {
+			pr_err("Error:Hardware endpoint %d is busy\n",
+					hostEpPriv->genericHwEp->hwEpNum);
+			return -EINVAL;
+		}
+		idleQueue = 1;
+	}
+
+	if (usb_endpoint_xfer_int(&req->usbEp->desc))
+		list_add_tail(&hostEpPriv->node, hEpQueue);
+
+	if (idleQueue)
+		hostStartReq(priv, req);
+
+	return 0;
+}
+
+static int abortActuallyUsbRequest(struct HOST_CTRL *priv,
+		struct HOST_REQ *req, struct HOST_EP *usbEp)
+{
+	struct HOST_EP_PRIV *usbEpPriv;
+	struct HostEp *hostEp;
+	uint16_t rxerrien = 0;
+	uint16_t txerrien = 0;
+	uint8_t rxcon, txcon;
+
+	if (!priv || !req || !usbEp)
+		return -EINVAL;
+
+	usbEpPriv = (struct HOST_EP_PRIV *)usbEp->hcPriv;
+	hostEp = usbEpPriv->currentHwEp;
+
+	usbEpPriv->transferFinished = 1;
+
+	if (hostEp->isInEp) {
+		if (hostEp->hwEpNum) {
+			rxcon = phytium_read8(&priv->regs->ep[hostEp->hwEpNum - 1].rxcon);
+			rxcon = rxcon & (~BIT(7));
+			phytium_write8(&priv->regs->ep[hostEp->hwEpNum - 1].rxcon, rxcon);
+		}
+		rxerrien = phytium_read16(&priv->regs->rxerrien);
+		rxerrien &= ~(1 << hostEp->hwEpNum);
+		phytium_write16(&priv->regs->rxerrien, rxerrien);
+		phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST |
+				ENDPRST_IO_TX | hostEp->hwEpNum);
+	} else {
+		if (hostEp->hwEpNum) {
+			txcon = phytium_read8(&priv->regs->ep[hostEp->hwEpNum - 1].txcon);
+			txcon = txcon & (~BIT(7));
+			phytium_write8(&priv->regs->ep[hostEp->hwEpNum - 1].txcon, txcon);
+		}
+		txerrien = phytium_read16(&priv->regs->txerrien);
+		txerrien &= ~(1 << hostEp->hwEpNum);
+		phytium_write16(&priv->regs->txerrien, txerrien);
+		phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | hostEp->hwEpNum);
+	}
+
+	scheduleNextTransfer(priv, req, hostEp);
+
+	return 0;
+}
+
+int32_t hostReqDequeue(struct HOST_CTRL *priv, struct HOST_REQ *req, uint32_t status)
+{
+	struct HOST_EP *usbEp;
+	struct HOST_EP_PRIV *usbEpPriv;
+	int ret = 0;
+
+	if (!priv || !req)
+		return -EINVAL;
+
+	usbEp = req->usbEp;
+	usbEpPriv = (struct HOST_EP_PRIV *)usbEp->hcPriv;
+
+	pr_debug("Dequeue usbReq:%p dev%d usbEp%d%s\n", req, req->faddress, req->epNum,
+			req->epIsIn ? "in" : "out");
+
+	if (!usbEpPriv->epIsReady)
+		return 0;
+
+	if (!usbEpPriv->currentHwEp || req->list.prev != &usbEp->reqList) {
+		givebackRequest(priv, req, status);
+		if (list_empty(&usbEp->reqList)) {
+			usbEpPriv->epIsReady = 0;
+			usbEpPriv->currentHwEp = NULL;
+			if (usb_endpoint_xfer_int(&usbEp->desc))
+				list_del(&usbEpPriv->node);
+		}
+	} else
+		ret = abortActuallyUsbRequest(priv, req, usbEp);
+
+	if (usbEpPriv->isocEpConfigured)
+		usbEpPriv->isocEpConfigured = 0;
+
+	return ret;
+}
+
+int32_t hostVHubStatusData(struct HOST_CTRL *priv, uint8_t *status)
+{
+	return 0;
+}
+
+int32_t hostGetDevicePD(struct HOST_CTRL *priv)
+{
+	return 0;
+}
+
+int32_t hostGetPrivateDataSize(struct HOST_CTRL *priv)
+{
+	if (!priv)
+		return 0;
+
+	return sizeof(struct HOST_EP_PRIV);
+}
+
+static int hub_descriptor(struct usb_hub_descriptor *buf)
+{
+	buf->bDescLength = 9;
+	buf->bDescriptorType = 0x29;
+	buf->bNbrPorts = 1;
+	buf->wHubCharacteristics = 0x11;
+	buf->bPwrOn2PwrGood = 5;
+	buf->bHubContrCurrent = 0;
+	buf->u.hs.DeviceRemovable[0] = 0x2;
+
+	return 0;
+}
+
+static int HubPortSuspend(struct HOST_CTRL *priv, u16 on)
+{
+	uint8_t otgctrl;
+
+	if (!priv)
+		return 0;
+
+	otgctrl = phytium_read8(&priv->regs->otgctrl);
+
+	if (on) {
+		otgctrl &= ~OTGCTRL_BUSREQ;
+		otgctrl &= ~OTGCTRL_BHNPEN;
+
+		priv->portStatus |= USB_PORT_STAT_SUSPEND;
+
+		switch (phytium_read8(&priv->regs->otgstate)) {
+		case HOST_OTG_STATE_A_HOST:
+			priv->otgState = HOST_OTG_STATE_A_SUSPEND;
+			otgctrl |= OTGCTRL_ASETBHNPEN;
+			break;
+		case HOST_OTG_STATE_B_HOST:
+			priv->otgState = HOST_OTG_STATE_B_HOST_2;
+			break;
+		default:
+			break;
+		}
+		phytium_write8(&priv->regs->otgctrl, otgctrl);
+	} else {
+		otgctrl |= OTGCTRL_BUSREQ;
+		otgctrl &= ~OTGCTRL_ASETBHNPEN;
+		phytium_write8(&priv->regs->otgctrl, otgctrl);
+		priv->portStatus |= USB_PORT_STAT_RESUME;
+	}
+	return 0;
+}
+
+static void HubPortReset(struct HOST_CTRL *priv, uint8_t on)
+{
+	uint8_t speed;
+
+	if (!priv)
+		return;
+
+	if (on) {
+		phytium_write16(&priv->regs->txerrirq, 0xFFFF);
+		phytium_write16(&priv->regs->txirq, 0xFFFF);
+		phytium_write16(&priv->regs->rxerrirq, 0xFFFF);
+		phytium_write16(&priv->regs->rxirq, 0xFFFF);
+
+		phytium_write8(&priv->regs->endprst, ENDPRST_IO_TX);
+		phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST |
+				ENDPRST_TOGRST | ENDPRST_IO_TX);
+		phytium_write8(&priv->regs->endprst, ENDPRST_FIFORST | ENDPRST_TOGRST);
+		phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO | 0 | 0x04);
+		phytium_write8(&priv->regs->ep0fifoctrl, FIFOCTRL_FIFOAUTO |
+				FIFOCTRL_IO_TX | 0 | 0x04);
+
+		priv->portStatus |= USB_PORT_STAT_RESET;
+		priv->portStatus &= ~USB_PORT_STAT_ENABLE;
+		priv->port_resetting = 0;
+	} else {
+		speed = phytium_read8(&priv->regs->speedctrl);
+		if (speed == SPEEDCTRL_HS)
+			priv->portStatus |= USB_PORT_STAT_HIGH_SPEED;
+		else if (speed == SPEEDCTRL_FS)
+			priv->portStatus &= ~(USB_PORT_STAT_HIGH_SPEED | USB_PORT_STAT_LOW_SPEED);
+		else
+			priv->portStatus |= USB_PORT_STAT_LOW_SPEED;
+
+		priv->portStatus &= ~USB_PORT_STAT_RESET;
+		priv->portStatus |= USB_PORT_STAT_ENABLE | (USB_PORT_STAT_C_RESET << 16)
+			| (USB_PORT_STAT_C_ENABLE << 16);
+
+		if (priv->hostCallbacks.portStatusChange)
+			priv->hostCallbacks.portStatusChange(priv);
+	}
+}
+
+static int get_PortStatus(struct HOST_CTRL *priv, u16 wIndex, uint8_t *buff)
+{
+	uint32_t temp = 0;
+
+	if (!priv || !buff)
+		return 0;
+
+	if ((wIndex & 0xff) != 1)
+		return 1;
+
+	if (priv->portStatus & USB_PORT_STAT_RESET) {
+		if (!priv->port_resetting)
+			HubPortReset(priv, 0);
+	}
+
+	if (priv->portStatus & USB_PORT_STAT_RESUME) {
+		priv->portStatus &= ~(USB_PORT_STAT_SUSPEND | USB_PORT_STAT_RESUME);
+		priv->portStatus |= USB_PORT_STAT_C_SUSPEND << 16;
+		if (priv->hostCallbacks.portStatusChange)
+			priv->hostCallbacks.portStatusChange(priv);
+	}
+
+	temp = priv->portStatus & (~USB_PORT_STAT_RESUME);
+	buff[0] = temp;
+	buff[1] = temp >> 8;
+	buff[2] = temp >> 16;
+	buff[3] = temp >> 24;
+
+	return 0;
+}
+
+static int set_PortFeature(struct HOST_CTRL *priv, u16 wValue, u16 wIndex)
+{
+//	struct HW_Regs *regs = priv->regs;
+
+	if ((wIndex & 0xff) != 1)
+		return 1;
+
+	switch (wValue) {
+	case USB_PORT_FEAT_CONNECTION:
+		break;
+	case USB_PORT_FEAT_ENABLE:
+		break;
+	case USB_PORT_FEAT_SUSPEND:
+		HubPortSuspend(priv, 1);
+		break;
+	case USB_PORT_FEAT_OVER_CURRENT:
+		break;
+	case USB_PORT_FEAT_RESET:
+		HubPortReset(priv, 1);
+		break;
+	case USB_PORT_FEAT_L1:
+		break;
+	case USB_PORT_FEAT_POWER:
+		hostStart(priv);
+		break;
+	case USB_PORT_FEAT_LOWSPEED:
+		break;
+	case USB_PORT_FEAT_C_CONNECTION:
+		break;
+	case USB_PORT_FEAT_C_ENABLE:
+		break;
+	case USB_PORT_FEAT_C_SUSPEND:
+		break;
+	case USB_PORT_FEAT_C_OVER_CURRENT:
+		break;
+	case USB_PORT_FEAT_INDICATOR:
+		break;
+	case USB_PORT_FEAT_C_PORT_L1:
+		break;
+	default:
+		break;
+	}
+	priv->portStatus |= 1 << wValue;
+
+	return 0;
+}
+
+static int Clear_PortFeature(struct HOST_CTRL *priv, u16 wValue, u16 wIndex)
+{
+	if ((wIndex & 0xff) != 1)
+		return 1;
+
+	switch (wValue) {
+	case USB_PORT_FEAT_CONNECTION:
+		break;
+	case USB_PORT_FEAT_ENABLE:
+		break;
+	case USB_PORT_FEAT_SUSPEND:
+		HubPortSuspend(priv, 0);
+		break;
+	case USB_PORT_FEAT_OVER_CURRENT:
+		break;
+	case USB_PORT_FEAT_RESET:
+		break;
+	case USB_PORT_FEAT_L1:
+		break;
+	case USB_PORT_FEAT_POWER:
+		break;
+	case USB_PORT_FEAT_LOWSPEED:
+		break;
+	case USB_PORT_FEAT_C_CONNECTION:
+		break;
+	case USB_PORT_FEAT_C_ENABLE:
+		break;
+	case USB_PORT_FEAT_C_SUSPEND:
+		break;
+	case USB_PORT_FEAT_C_OVER_CURRENT:
+		break;
+	case USB_PORT_FEAT_INDICATOR:
+		break;
+	case USB_PORT_FEAT_C_PORT_L1:
+		break;
+	default:
+		break;
+	}
+	priv->portStatus &= ~(1 << wValue);
+
+	return 0;
+}
+
+static int hc_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+		u16 wIndex, char *buf, u16 wLength)
+{
+	unsigned long flags = 0;
+	int retval = 0;
+	struct HOST_CTRL *priv;
+	struct phytium_cusb *config = *(struct phytium_cusb **)hcd->hcd_priv;
+
+	if (!config)
+		return -EINVAL;
+
+	if (!buf)
+		return -EINVAL;
+
+	if (unlikely(!HCD_HW_ACCESSIBLE(hcd))) {
+		spin_unlock_irqrestore(&config->lock, flags);
+		return -ESHUTDOWN;
+	}
+
+	priv = (struct HOST_CTRL *)config->host_priv;
+	if (!priv)
+		return -EINVAL;
+
+	spin_lock_irqsave(&config->lock, flags);
+	switch (typeReq) {
+	case GetHubStatus:
+		break;
+	case GetPortStatus:
+		get_PortStatus(priv, wIndex, (uint8_t *)buf);
+		break;
+	case GetHubDescriptor:
+		hub_descriptor((struct usb_hub_descriptor *)buf);
+		break;
+	case SetPortFeature:
+		set_PortFeature(priv, wValue, wIndex);
+		break;
+	case ClearPortFeature:
+		retval = Clear_PortFeature(priv, wValue, wIndex);
+		break;
+	case SetHubFeature:
+		break;
+	case ClearHubFeature:
+		break;
+	default:
+		break;
+	}
+
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return retval;
+}
+
+int32_t hostVHubControl(struct HOST_CTRL *priv, struct usb_ctrlrequest *setup, uint8_t *buff)
+{
+	uint16_t request;
+	uint32_t retval = 0;
+
+	if (!priv || !setup || !buff)
+		return -EINVAL;
+
+	request = setup->bRequestType << 0x08 | setup->bRequest;
+	switch (request) {
+	case ClearHubFeature:
+		break;
+	case SetHubFeature:
+		break;
+	case ClearPortFeature:
+		retval = Clear_PortFeature(priv, setup->wValue, setup->wIndex);
+		break;
+	case SetPortFeature:
+		retval = set_PortFeature(priv, setup->wValue, setup->wIndex);
+		break;
+	case GetHubDescriptor:
+		retval = hub_descriptor((struct usb_hub_descriptor *)buff);
+		break;
+	case GetHubStatus:
+		break;
+	case GetPortStatus:
+		retval = get_PortStatus(priv, setup->wIndex, (uint8_t *)buff);
+		break;
+	default:
+		retval = EOPNOTSUPP;
+		break;
+	}
+
+	return retval;
+}
+
+struct HOST_OBJ hostDrv = {
+	.host_init	=	hostInit,
+	.host_destroy	=	hostDestroy,
+	.host_start	=	hostStart,
+	.host_stop	=	hostStop,
+	.host_isr	=	hostIsr,
+
+	//endpoint operation
+	.host_epDisable =	hostEpDisable,
+	.host_reqQueue =	hostReqQueue,
+	.host_reqDequeue =	hostReqDequeue,
+	.host_vhubStatusData =	hostVHubStatusData,
+	.host_vhubControl =	hostVHubControl,
+	.host_getDevicePD =	hostGetDevicePD,
+	.host_epGetPrivateDataSize = hostGetPrivateDataSize,
+};
+
+static struct hc_driver host_driver = {
+	.description	=	"phytium-hcd",
+	.product_desc	=	"Phytium Host USB Driver",
+	.hcd_priv_size	=	sizeof(struct phytium_cusb *),
+	.flags		=	HCD_MEMORY | HCD_USB2 | HCD_DMA,
+	.reset		=	hc_reset,
+	.start		=	hc_start,
+	.stop		=	hc_stop,
+	.shutdown	=	hc_shutdown,
+	.urb_enqueue	=	hc_urb_enqueue,
+	.urb_dequeue	=	hc_urb_dequeue,
+	.endpoint_disable =	hc_endpoint_disable,
+	.get_frame_number =	hc_get_frame,
+	.alloc_dev	=	hc_alloc_dev,
+	.free_dev	=	hc_free_dev,
+	.reset_device	=	hc_reset_device,
+	.update_device	=	hc_update_device,
+	.add_endpoint	=	hc_add_endpoint,
+	.drop_endpoint	=	hc_drop_endpoint,
+	.hub_status_data =	hc_hub_status_data,
+	.hub_control	=	hc_hub_control,
+#ifdef	CONFIG_PM
+	.bus_suspend	=	hc_bus_suspend,
+	.bus_resume	=	hc_bus_resume,
+#endif
+};
+
+static int phytium_host_set_default_cfg(struct phytium_cusb *config)
+{
+	int index;
+
+	config->host_cfg.regBase = (uintptr_t)config->regs;
+	config->host_cfg.phy_regBase = (uintptr_t)config->phy_regs;
+	config->host_cfg.dmultEnabled = 1;
+	config->host_cfg.memoryAlignment = 0;
+	config->host_cfg.dmaSupport = 1;
+	config->host_cfg.isEmbeddedHost = 1;
+
+	for (index = 0; index < HOST_EP_NUM; index++) {
+		if (index == 0) {
+			config->host_cfg.epIN[index].bufferingValue = 1;
+			config->host_cfg.epIN[index].maxPacketSize = 64;
+			config->host_cfg.epIN[index].startBuf = 0;
+
+			config->host_cfg.epOUT[index].bufferingValue = 1;
+			config->host_cfg.epOUT[index].maxPacketSize = 64;
+			config->host_cfg.epOUT[index].startBuf = 0;
+		} else {
+			config->host_cfg.epIN[index].bufferingValue = 2;
+			config->host_cfg.epIN[index].maxPacketSize = 1024;
+			config->host_cfg.epIN[index].startBuf = 64 + 2 * 1024 * (index - 1);
+
+			config->host_cfg.epOUT[index].bufferingValue = 2;
+			config->host_cfg.epOUT[index].maxPacketSize = 1024;
+			config->host_cfg.epOUT[index].startBuf = 64 + 2 * 1024 * (index - 1);
+		}
+	}
+
+	return 0;
+}
+
+static int phytium_host_reinit(struct phytium_cusb *config)
+{
+	struct HOST_CTRL *ctrl;
+
+	if (!config || !config->host_priv)
+		return 0;
+
+	ctrl = (struct HOST_CTRL *)config->host_priv;
+
+	usb_root_hub_lost_power(config->hcd->self.root_hub);
+	hostStop(ctrl);
+
+	ctrl->portStatus = 0;
+
+	config->host_obj->host_init(config->host_priv, &config->host_cfg,
+			&config->host_callbacks, config->dev, config->isVhubHost);
+
+	return 0;
+}
+
+int phytium_host_init(struct phytium_cusb *config)
+{
+	int ret;
+
+	if (!config)
+		return 0;
+
+	phytium_host_set_default_cfg(config);
+	config->host_obj = HOST_GetInstance();
+	config->dma_cfg.regBase = config->host_cfg.regBase + 0x400;
+
+	config->dma_obj = DMA_GetInstance();
+	config->dma_obj->dma_probe(&config->dma_cfg, &config->dma_sysreq);
+
+	config->host_sysreq.privDataSize = sizeof(struct HOST_CTRL);
+	config->host_sysreq.trbMemSize = config->dma_sysreq.trbMemSize;
+	config->host_sysreq.privDataSize += config->dma_sysreq.privDataSize;
+
+	config->host_priv = devm_kzalloc(config->dev, config->host_sysreq.privDataSize, GFP_KERNEL);
+	if (!config->host_priv) {
+		ret = -ENOMEM;
+		goto err_probe;
+	}
+
+	config->host_cfg.trbAddr = dma_alloc_coherent(config->dev, config->host_sysreq.trbMemSize,
+			(dma_addr_t *)&config->host_cfg.trbDmaAddr, GFP_KERNEL);
+	if (!config->host_cfg.trbAddr) {
+		ret = -ENOMEM;
+		goto err_dma_coherent;
+	}
+
+	config->host_callbacks.portStatusChange = host_rh_port_status_change;
+	config->host_callbacks.getEpToggle = host_get_ep_toggle;
+	config->host_callbacks.setEpToggle = host_set_ep_toggle;
+	config->host_callbacks.givebackRequest = host_giveback_request;
+
+	config->host_obj->host_init(config->host_priv, &config->host_cfg,
+			&config->host_callbacks, config->dev, config->isVhubHost);
+
+	config->hcd = usb_create_hcd(&host_driver, config->dev, dev_name(config->dev));
+	if (!config->hcd) {
+		ret = -ENODEV;
+		goto err_host;
+	}
+
+	*config->hcd->hcd_priv = (unsigned long)config;
+	config->hcd->self.uses_pio_for_control = 0;
+	config->hcd->uses_new_polling = 1;
+	config->hcd->has_tt = 1;
+
+	dev_set_drvdata(config->dev, config);
+
+	config->hcd->self.otg_port = 1;
+	config->hcd->power_budget = 500;
+	ret = usb_add_hcd(config->hcd, 0, 0);
+	if (ret < 0)
+		goto err_setup;
+
+	return 0;
+err_setup:
+	usb_put_hcd(config->hcd);
+err_host:
+	config->host_obj->host_destroy(config->host_priv);
+	dma_free_coherent(config->dev, config->host_sysreq.trbMemSize,
+			config->host_cfg.trbAddr, config->host_cfg.trbDmaAddr);
+err_dma_coherent:
+err_probe:
+	dev_set_drvdata(config->dev, NULL);
+	return ret;
+}
+
+int phytium_host_uninit(struct phytium_cusb *config)
+{
+	if (!config)
+		return 0;
+
+	if (config->hcd) {
+		usb_remove_hcd(config->hcd);
+		usb_put_hcd(config->hcd);
+		config->hcd = NULL;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+int phytium_host_resume(void *priv)
+{
+	int otgctrl;
+	struct phytium_cusb *config = (struct phytium_cusb *)priv;
+	struct HOST_CTRL *ctrl = (struct HOST_CTRL *)config->host_priv;
+
+	if (!ctrl)
+		return -EINVAL;
+
+	otgctrl = phytium_read8(&ctrl->regs->otgctrl);
+	otgctrl |= 1;
+	phytium_write8(&ctrl->regs->otgctrl, otgctrl);
+
+	phytium_host_reinit(config);
+
+	return 0;
+}
+
+int phytium_host_suspend(void *priv)
+{
+	int otgctrl;
+	struct phytium_cusb *config = (struct phytium_cusb *)priv;
+	struct HOST_CTRL *ctrl = (struct HOST_CTRL *)config->host_priv;
+
+	if (!ctrl)
+		return -EINVAL;
+
+	otgctrl = phytium_read8(&ctrl->regs->otgctrl);
+	otgctrl = otgctrl & (~1);
+	phytium_write8(&ctrl->regs->otgctrl, otgctrl);
+
+	return 0;
+}
+#endif
+
+struct HOST_OBJ *HOST_GetInstance(void)
+{
+	return &hostDrv;
+}
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/host_api.h b/target/linux/phytium/files-5.10/drivers/usb/phytium/host_api.h
new file mode 100644
index 00000000000000..3d45258278c475
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/host_api.h
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __PHYTIUM_HOST_API_H_
+#define __PHYTIUM_HOST_API_H_
+
+#include <linux/usb/ch9.h>
+//#include "list.h"
+#include "dma.h"
+
+#define MAX_SUPPORTED_DEVICES 16
+#define USB_PORT_STAT_RESUME (1 << 31)
+#define MAX_INSTANCE_EP_NUM 6
+
+enum HOST_OtgState {
+	HOST_OTG_STATE_A_IDLE,
+	HOST_OTG_STATE_A_WAIT_VRISE,
+	HOST_OTG_STATE_A_WAIT_BCON,
+	HOST_OTG_STATE_A_HOST,
+	HOST_OTG_STATE_A_SUSPEND,
+	HOST_OTG_STATE_A_PERIPHERAL,
+	HOST_OTG_STATE_A_VBUS_ERR,
+	HOST_OTG_STATE_A_WAIT_VFALL,
+	HOST_OTG_STATE_B_IDLE = 0x10,
+	HOST_OTG_STATE_B_PERIPHERAL,
+	HOST_OTG_STATE_B_WAIT_ACON,
+	HOST_OTG_STATE_B_HOST,
+	HOST_OTG_STATE_B_HOST_2,
+	HOST_OTG_STATE_B_SRP_INT1,
+	HOST_OTG_STATE_B_SRP_INT2,
+	HOST_OTG_STATE_B_DISCHRG1,
+	HOST_OTG_STATE_B_DISCHRG2,
+	HOST_OTG_STATE_UNKNOWN,
+};
+
+enum HOST_EP0_STAGE {
+	HOST_EP0_STAGE_IDLE,
+	HOST_EP0_STAGE_SETUP,
+	HOST_EP0_STAGE_IN,
+	HOST_EP0_STAGE_OUT,
+	HOST_EP0_STAGE_STATUSIN,
+	HOST_EP0_STAGE_STATUSOUT,
+	HOST_EP0_STAGE_ACK,
+};
+
+enum HOST_EP_STATE {
+	HOST_EP_FREE,
+	HOST_EP_ALLOCATED,
+	HOST_EP_BUSY,
+	HOST_EP_NOT_IMPLEMENTED
+};
+
+struct HOST_DEVICE {
+	uint8_t devnum;
+	uint8_t hubPort;
+	unsigned int speed;
+	struct HOST_DEVICE *parent;
+	void *hcPriv;
+	void *userExt;
+};
+
+struct HOST_EP {
+	struct usb_endpoint_descriptor desc;
+	struct list_head reqList;
+	void *userExt;
+	uint8_t *hcPriv;
+};
+
+struct HOST_USB_DEVICE {
+	struct HOST_EP ep0_hep;
+	struct HOST_EP *in_ep[16];
+	struct HOST_EP *out_ep[16];
+	struct HOST_DEVICE udev;
+	struct usb_device *ld_udev;
+};
+
+struct HostEp {
+	uint8_t name[255];
+	uint8_t hwEpNum;
+	uint8_t hwBuffers;
+	uint16_t hwMaxPacketSize;
+	uint8_t isInEp;
+	void *channel;
+	uint8_t usbEpNum;
+	uint8_t type;
+	uint8_t usbPacketSize;
+	enum HOST_EP_STATE state;
+	struct HOST_EP *scheduledUsbHEp;
+	uint8_t refCount;
+};
+
+struct HOST_ISOFRAMESDESC {
+	uint32_t length;
+	uint32_t offset;
+};
+
+struct HOST_EP_PRIV {
+	struct list_head node;
+	struct HostEp *genericHwEp;
+	struct HostEp *currentHwEp;
+	uint8_t epIsReady;
+	uint8_t isIn;
+	uint8_t type;
+	uint8_t interval;
+	uint8_t epNum;
+	uint8_t faddress;
+	uint16_t maxPacketSize;
+	uint32_t frame;
+	uint8_t hubAddress;
+	uint8_t portAddress;
+	uint8_t split;
+	struct HOST_EP *usbHEp;
+	uint8_t isocEpConfigured;
+	uint8_t transferFinished;
+};
+
+struct HOST_REQ {
+	struct list_head list;
+	struct HOST_EP *usbEp;
+	void *userExt;
+	void *hcPriv;
+	struct HOST_DEVICE *usbDev;
+	struct usb_ctrlrequest *setup;
+	uintptr_t setupDma;
+	void *bufAddress;
+	uintptr_t buffDma;
+	uint32_t buffLength;
+	uint32_t actualLength;
+	uint8_t epIsIn;
+	uint8_t eptype;
+	uint8_t epNum;
+	uint8_t faddress;
+	uint8_t interval;
+	uint8_t status;
+	uint8_t reqUnlinked;
+	struct HOST_ISOFRAMESDESC *isoFramesDesc;
+	uint32_t isoFramesNumber;
+};
+
+struct HOST_SYSREQ {
+	uint32_t privDataSize;
+	uint32_t trbMemSize;
+};
+
+struct HOST_EP_CFG {
+	uint8_t bufferingValue;
+	uint16_t startBuf;
+	uint16_t maxPacketSize;
+};
+
+struct HOST_CFG {
+	uintptr_t regBase;
+	uintptr_t phy_regBase;
+	struct HOST_EP_CFG epIN[16];
+	struct HOST_EP_CFG epOUT[16];
+	uint8_t dmultEnabled;
+	uint8_t memoryAlignment;
+	uint8_t dmaSupport;
+	uint8_t isEmbeddedHost;
+	void *trbAddr;
+	uintptr_t trbDmaAddr;
+};
+
+struct HOST_CTRL;
+
+struct HOST_CALLBACKS {
+	void (*portStatusChange)(struct HOST_CTRL *priv);
+
+	uint8_t (*getEpToggle)(struct HOST_CTRL *priv,
+			struct HOST_DEVICE *usbDev, uint8_t epNum, uint8_t isIn);
+
+	void (*setEpToggle)(struct HOST_CTRL *priv, struct HOST_DEVICE *usbDev,
+			uint8_t epNum, uint8_t isIn, uint8_t toggle);
+
+	void (*givebackRequest)(struct HOST_CTRL *priv,
+			struct HOST_REQ *usbReq, uint32_t status);
+
+	void (*setTimer)(struct HOST_CTRL *priv, uint32_t time, uint8_t id);
+};
+
+struct HOST_OBJ {
+	int32_t (*host_probe)(struct HOST_CFG *config, struct HOST_SYSREQ *sysReq);
+
+	int32_t (*host_init)(struct HOST_CTRL *priv, struct HOST_CFG *config,
+			struct HOST_CALLBACKS *callbacks, struct device *pdev, bool isVhubHost);
+
+	void (*host_destroy)(struct HOST_CTRL *priv);
+
+	void (*host_start)(struct HOST_CTRL *priv);
+
+	void (*host_stop)(struct HOST_CTRL *priv);
+
+	void (*host_isr)(struct HOST_CTRL *priv);
+
+	int32_t (*host_epDisable)(struct HOST_CTRL *priv, struct HOST_EP *ep);
+
+	int32_t (*host_reqQueue)(struct HOST_CTRL *priv, struct HOST_REQ *req);
+
+	int32_t (*host_reqDequeue)(struct HOST_CTRL *priv,
+			struct HOST_REQ *req, uint32_t status);
+
+	int32_t (*host_vhubStatusData)(struct HOST_CTRL *priv, uint8_t *status);
+
+	int32_t (*host_vhubControl)(struct HOST_CTRL *priv,
+			struct usb_ctrlrequest *setup, uint8_t *buff);
+
+	int32_t (*host_getDevicePD)(struct HOST_CTRL *priv);
+
+	int32_t (*host_epGetPrivateDataSize)(struct HOST_CTRL *priv);
+};
+
+struct HOST_CTRL {
+	struct device *dev;
+	struct HW_REGS	*regs;
+	struct HOST_OBJ *hostDrv;
+	struct HOST_CFG hostCfg;
+	struct HOST_CALLBACKS hostCallbacks;
+	struct HostEp in[16];
+	struct HostEp out[16];
+	uint32_t portStatus;
+	struct list_head ctrlHEpQueue;
+	struct list_head isoInHEpQueue[MAX_INSTANCE_EP_NUM];
+	struct list_head isoOutHEpQueue[MAX_INSTANCE_EP_NUM];
+	struct list_head intInHEpQueue[MAX_INSTANCE_EP_NUM];
+	struct list_head intOutHEpQueue[MAX_INSTANCE_EP_NUM];
+	struct list_head bulkInHEpQueue[MAX_INSTANCE_EP_NUM];
+	struct list_head bulkOutHEpQueue[MAX_INSTANCE_EP_NUM];
+	uint8_t hwEpInCount;
+	uint8_t hwEpOutCount;
+	unsigned int speed;
+	enum HOST_OtgState otgState;
+	enum HOST_EP0_STAGE ep0State;
+	uint8_t vBusErrCnt;
+	uint8_t isRemoteWakeup;
+	uint8_t isSelfPowered;
+	uint8_t deviceAddress;
+	struct DMA_OBJ *dmaDrv;
+	void *dmaController;
+	struct DMA_CFG dmaCfg;
+	struct DMA_CALLBACKS dmaCallback;
+	uint8_t port_resetting;
+	struct HOST_USB_DEVICE *host_devices_table[MAX_SUPPORTED_DEVICES];
+	struct CUSTOM_REGS *custom_regs;
+	struct VHUB_REGS *vhub_regs;
+};
+
+struct HOST_OBJ *HOST_GetInstance(void);
+
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/hw-regs.h b/target/linux/phytium/files-5.10/drivers/usb/phytium/hw-regs.h
new file mode 100644
index 00000000000000..8da9f8e9b92537
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/hw-regs.h
@@ -0,0 +1,297 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_PHYTIUM_HW_REGS
+#define __LINUX_PHYTIUM_HW_REGS
+
+#define USBIEN			0x198
+#define USBIEN_SUDAVIE		BIT(0)
+#define USBIEN_SOFIE		BIT(1)
+#define USBIEN_SUTOKIE		BIT(2)
+#define USBIEN_SUSPIE		BIT(3)
+#define USBIEN_URESIE		BIT(4)
+#define USBIEN_HSPEEDIE		BIT(5)
+#define USBIEN_LPMIE		BIT(7)
+
+#define USBCS			0x1a3
+#define USBCS_LSMODE		BIT(0)
+#define USBCS_LPMNYET		BIT(1)
+#define USBCS_SIGSUME		BIT(5)
+#define USBCS_DISCON		BIT(6)
+#define USBCS_WAKESRC		BIT(7)
+
+#define USBIR_SOF		BIT(1)
+#define USBIR_SUSP		BIT(3)
+#define USBIR_URES		BIT(4)
+#define USBIR_HSPEED		BIT(5)
+
+#define USBIR_SUDAV		BIT(0)
+#define USBIR_SUTOK		BIT(2)
+#define USBIR_LPMIR		BIT(7)
+
+#define OTGIRQ_IDLEIRQ		BIT(0)
+#define OTGIRQ_SRPDETIRQ	BIT(1)
+#define OTGIRQ_CONIRQ		BIT(2)
+#define OTGIRQ_LOCSOFIRQ	BIT(2)
+#define OTGIRQ_VBUSERRIRQ	BIT(3)
+#define OTGIRQ_PERIPHIRQ	BIT(4)
+#define OTGIRQ_IDCHANGEIRQ	BIT(5)
+#define OTGIRQ_HOSTDISCON	BIT(6)
+#define OTGIRQ_BSE0SRPIRQ	BIT(7)
+
+#define OTGCTRL_BUSREQ		BIT(0)
+#define OTGCTRL_ABUSDROP	BIT(1)
+#define OTGCTRL_ASETBHNPEN	BIT(2)
+#define OTGCTRL_BHNPEN		BIT(3)
+#define OTGCTRL_SRPVBUSDETEN	BIT(4)
+#define OTGCTRL_SRPDATDETEN	BIT(5)
+#define OTGCTRL_FORCEBCONN	BIT(7)
+
+#define OTGSTATUS_ID		BIT(6)
+
+#define ENDPRST_EP		0x0f
+#define ENDPRST_IO_TX		BIT(4)
+#define ENDPRST_TOGRST		BIT(5)
+#define ENDPRST_FIFORST		BIT(6)
+#define ENDPRST_TOGSETQ		BIT(7)
+
+#define FIFOCTRL_EP		0x0f
+#define FIFOCTRL_IO_TX		BIT(4)
+#define FIFOCTRL_FIFOAUTO	BIT(5)
+
+#define SPEEDCTRL_LS		BIT(0)
+#define SPEEDCTRL_FS		BIT(1)
+#define SPEEDCTRL_HS		BIT(2)
+#define SPEEDCTRL_HSDISABLE	BIT(7)
+
+#define CON_TYPE_CONTROL	0x00
+#define CON_TYPE_ISOC		0x04
+#define CON_TYPE_BULK		0x08
+#define CON_TYPE_INT		0x0C
+#define CON_TYPE_ISOC_1_ISOD	0x00
+#define CON_TYPE_ISOC_2_ISOD	0x10
+#define CON_TYPE_ISOC_3_ISOD	0x20
+#define CON_STALL		0x40
+#define CON_VAL			0x80
+
+#define ERR_TYPE		0x1c
+#define ERR_COUNT		0x03
+#define ERR_RESEND		BIT(6)
+#define ERR_UNDERRIEN		BIT(7)
+
+#define ERR_NONE			0
+#define ERR_CRC				1
+#define ERR_DATA_TOGGLE_MISMATCH	2
+#define ERR_STALL			3
+#define ERR_TIMEOUT			4
+#define ERR_PID				5
+#define ERR_TOO_LONG_PACKET		6
+#define ERR_DATA_UNDERRUN		7
+
+#define EP0CS_HCSETTOGGLE	BIT(6)
+#define EP0CS_HCSET		BIT(4)
+#define EP0CS_RXBUSY_MASK	BIT(3)
+#define EP0CS_TXBUSY_MASK	BIT(2)
+#define EP0CS_STALL		BIT(0)
+#define EP0CS_HSNAK		BIT(1)
+#define EP0CS_DSTALL		BIT(4)
+#define EP0CS_CHGSET		BIT(7)
+
+#define CS_ERR		0x01
+#define CS_BUSY		0x02
+#define CS_NPAK		0x0c
+#define CS_NPAK_OFFSET	0x02
+#define CS_AUTO		0x10
+
+#define CON_BUF_SINGLE	0x00
+#define CON_BUF_DOUBLE	0x01
+#define CON_BUF_TRIPLE	0x02
+#define CON_BUF_QUAD	0x03
+#define CON_BUF	0x03
+
+struct HW_REGS {
+	uint8_t ep0Rxbc;        /*address 0x00*/
+	uint8_t ep0Txbc;        /*address 0x01*/
+	uint8_t ep0cs;          /*address 0x02*/
+	int8_t reserved0;       /*address 0x03*/
+	uint8_t lpmctrll;       /*address 0x04*/
+	uint8_t lpmctrlh;       /*address 0x05*/
+	uint8_t lpmclock;
+	uint8_t ep0fifoctrl;
+	struct ep {             /*address 0x08*/
+		uint16_t rxbc;        //outbc (hcinbc)
+		uint8_t rxcon;
+		uint8_t rxcs;
+		uint16_t txbc;         //inbc  (hcoutbc
+		uint8_t txcon;
+		uint8_t txcs;
+	} ep[15];
+	uint8_t reserved1[4];
+	uint32_t fifodat[15];   /*address 0x84*/
+	uint8_t ep0ctrl;        /*address 0xC0*/
+	uint8_t tx0err;         /*address 0xC1*/
+	uint8_t reserved2;
+	uint8_t rx0err;         /*address 0xC3*/
+	struct epExt {
+		uint8_t txctrl;
+		uint8_t txerr;
+		uint8_t rxctrl;
+		uint8_t rxerr;
+	} epExt[15];
+	uint8_t ep0datatx[64]; /*address 0x100*/
+	uint8_t ep0datarx[64]; /*address 0x140*/
+	uint8_t setupdat[8];    /*address 0x180*/
+	uint16_t txirq;         /*address 0x188*/
+	uint16_t rxirq;         /*address 0x18A*/
+	uint8_t usbirq;         /*address 0x18C*/
+	uint8_t reserved4;
+	uint16_t rxpngirq;      /*address 0x18E*/
+	uint16_t txfullirq;     /*address 0x190*/
+	uint16_t rxemptirq;     /*address 0x192*/
+	uint16_t txien;         /*address 0x194*/
+	uint16_t rxien;         /*address 0x196*/
+	uint8_t usbien;         /*address 0x198*/
+	uint8_t reserved6;
+	uint16_t rxpngien;      /*address 0x19A*/
+	uint16_t txfullien;     /*address 0x19C*/
+	uint16_t rxemptien;     /*address 0x19E*/
+	uint8_t usbivect;       /*address 0x1A0*/
+	uint8_t fifoivect;      /*address 0x1A1*/
+	uint8_t endprst;        /*address 0x1A2*/
+	uint8_t usbcs;          /*address 0x1A3*/
+	uint16_t frmnr;         /*address 0x1A4*/
+	uint8_t fnaddr;         /*address 0x1A6*/
+	uint8_t clkgate;        /*address 0x1A7*/
+	uint8_t fifoctrl;       /*address 0x1A8*/
+	uint8_t speedctrl;      /*address 0x1A9*/
+	uint8_t reserved8[1];   /*address 0x1AA*/
+	uint8_t portctrl;       /*address 0x1AB*/
+	uint16_t hcfrmnr;       /*address 0x1AC*/
+	uint16_t hcfrmremain;   /*address 0x1AE*/
+	uint8_t reserved9[4];   /*address 0x1B0*/
+	uint16_t rxerrirq;      /*address 0x1B4*/
+	uint16_t txerrirq;      /*address 0x1B6*/
+	uint16_t rxerrien;      /*address 0x1B8*/
+	uint16_t txerrien;      /*address 0x1BA*/
+	/*OTG extension*/
+	uint8_t otgirq;         /*address 0x1BC*/
+	uint8_t otgstate;       /*address 0x1BD*/
+	uint8_t otgctrl;        /*address 0x1BE*/
+	uint8_t otgstatus;      /*address 0x1BF*/
+	uint8_t otgien;         /*address 0x1C0*/
+	uint8_t taaidlbdis;     /*address 0x1C1*/
+	uint8_t tawaitbcon;     /*address 0x1C2*/
+	uint8_t tbvbuspls;      /*address 0x1C3*/
+	uint8_t otg2ctrl;       /*address 0x1C4*/
+	uint8_t reserved10[2];  /*address 0x1C5*/
+	uint8_t tbvbusdispls;   /*address 0x1C7*/
+	uint8_t traddr;         /*address 0x1C8*/
+	uint8_t trwdata;        /*address 0x1C9*/
+	uint8_t trrdata;        /*address 0x1CA*/
+	uint8_t trctrl;         /*address 0x1CB*/
+	uint16_t isoautoarm;    /*address 0x1CC*/
+	uint8_t adpbc1ien;      /*address 0x1CE*/
+	uint8_t adpbc2ien;      /*address 0x1CF*/
+	uint8_t adpbcctr0;      /*address 0x1D0*/
+	uint8_t adpbcctr1;      /*address 0x1D1*/
+	uint8_t adpbcctr2;      /*address 0x1D2*/
+	uint8_t adpbc1irq;      /*address 0x1D3*/
+	uint8_t adpbc0status;   /*address 0x1D4*/
+	uint8_t adpbc1status;   /*address 0x1D5*/
+	uint8_t adpbc2status;   /*address 0x1D6*/
+	uint8_t adpbc2irq;      /*address 0x1D7*/
+	uint16_t isodctrl;      /*address 0x1D8*/
+	uint8_t reserved11[2];
+	uint16_t isoautodump;   /*address 0x1DC*/
+	uint8_t reserved12[2];
+	uint8_t ep0maxpack;     /*address 0x1E0*/
+	uint8_t reserved13;
+	uint16_t rxmaxpack[15]; /*address 0x1E2*/
+	struct rxsoftimer { /*address 0x200 to  0x23F*/
+		uint16_t timer;
+		uint8_t reserved;
+		uint8_t ctrl;
+	} rxsoftimer[16];
+
+	struct  txsoftimer { /*address 0x240 to  0x27F*/
+		uint16_t timer;
+		uint8_t reserved;
+		uint8_t ctrl;
+	} txsoftimer[16];
+	uint8_t reserved14[132];
+	struct rxstaddr {       /*address 0x304*/
+		uint16_t addr;
+		uint16_t reserved;
+	} rxstaddr[15];
+	uint8_t reserved15[4];
+	struct txstaddr {       /*address 0x344*/
+		uint16_t addr;
+		uint16_t reserved;
+	} txstaddr[15];
+	int8_t reserved16[4];	/*address 0x380*/
+	struct irqmode {	/*address 0x384*/
+		int8_t inirqmode;
+		int8_t reserved21;
+		int8_t outirqmode;
+		int8_t reserved22;
+	} irqmode[15];
+	/*The Microprocessor control*/
+	uint8_t cpuctrl;         /*address 0x3C0*/
+	int8_t reserved17[15];
+	/*The debug counters and workarounds*/
+	uint8_t debug_rx_bcl;    /*address 0x3D0*/
+	uint8_t debug_rx_bch;    /*address 0x3D1*/
+	uint8_t debug_rx_status; /*address 0x3D2*/
+	uint8_t debug_irq;       /*address 0x3D3*/
+	uint8_t debug_tx_bcl;    /*address 0x3D4*/
+	uint8_t debug_tx_bch;    /*address 0x3D5*/
+	uint8_t debug_tx_status; /*address 0x3D6*/
+	uint8_t debug_ien;       /*address 0x3D7*/
+	uint8_t phywa_en;        /*address 0x3D8*/
+	/*endian*/
+	uint8_t wa1_cnt;       /*address 0x3D9*/
+	int8_t reserved18[2];  /*address 0x3DA*/
+	uint8_t endian_sfr_cs; /*address 0x3DC*/
+	int8_t reserved19[2];    /*address 0x3DD*/
+	uint8_t endian_sfr_s;  /*address 0x3DF*/
+	int8_t reserved20[2];    /*address 0x3E0*/
+	uint16_t txmaxpack[15]; /*address 0x3E2*/
+};
+
+struct CUSTOM_REGS {
+	uint32_t secure_ctrl;	/*address 0x80000*/
+	uint32_t secsid_atst;	/*address 0x80004*/
+	uint32_t nsaid_smmuid;	/*address 0x80008*/
+	uint32_t ace;		/*address 0x8000c*/
+	uint32_t wakeup;	/*address 0x80010*/
+	uint32_t debug;		/*address 0x80014*/
+};
+
+struct VHUB_REGS {
+	uint32_t gen_cfg;	/*address 0x00*/
+	uint32_t gen_st;	/*address 0x04*/
+	uint32_t bc_cfg;	/*address 0x08*/
+	uint32_t bc_st;		/*address 0x0c*/
+	uint32_t adp_cfg;	/*address 0x10*/
+	uint32_t adp_st;	/*address 0x14*/
+	uint32_t dbg_cfg;	/*address 0x18*/
+	uint32_t dbg_st;	/*address 0x1c*/
+	uint32_t utmip_cfg;	/*address 0x20*/
+	uint32_t utmip_st;	/*address 0x24*/
+};
+
+struct DMARegs {
+	uint32_t conf;      /*address 0x400*/
+	uint32_t sts;       /*address 0x404*/
+	uint32_t reserved5[5];
+	uint32_t ep_sel;    /*address 0x41C*/
+	uint32_t traddr;    /*address 0x420*/
+	uint32_t ep_cfg;    /*address 0x424*/
+	uint32_t ep_cmd;    /*address 0x428*/
+	uint32_t ep_sts;    /*address 0x42c*/
+	uint32_t ep_sts_sid;/*address 0x430*/
+	uint32_t ep_sts_en; /*address 0x434*/
+	uint32_t drbl;      /*address 0x438*/
+	uint32_t ep_ien;    /*address 0x43C*/
+	uint32_t ep_ists;   /*address 0x440*/
+};
+
+#endif
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/pci.c b/target/linux/phytium/files-5.10/drivers/usb/phytium/pci.c
new file mode 100644
index 00000000000000..964fd67bfc5321
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/pci.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
+#include <linux/usb/otg.h>
+#include "core.h"
+
+#define PHYTIUM_OTG_USB_LOADED  3
+
+static bool phytium_hw_is_device(struct phytium_cusb *config)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return false;
+}
+
+static bool phytium_hw_is_host(struct phytium_cusb *config)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+
+	return true;
+}
+
+static int phytium_get_dr_mode(struct phytium_cusb *config)
+{
+	enum usb_dr_mode mode;
+
+	config->dr_mode = usb_get_dr_mode(config->dev);
+	if (config->dr_mode == USB_DR_MODE_UNKNOWN)
+		config->dr_mode = USB_DR_MODE_OTG;
+
+	mode = config->dr_mode;
+	if (phytium_hw_is_device(config)) {
+		if (IS_ENABLED(CONFIG_USB_PHYTIUM_HOST)) {
+			dev_err(config->dev, "Controller does not support host mode.\n");
+			return -EINVAL;
+		}
+
+		mode = USB_DR_MODE_PERIPHERAL;
+	} else if (phytium_hw_is_host(config)) {
+		if (IS_ENABLED(CONFIG_USB_PHYTIUM_PERIPHERAL)) {
+			dev_err(config->dev, "Controller does not support device mode.\n");
+			return -EINVAL;
+		}
+		mode = USB_DR_MODE_HOST;
+	} else {
+		if (IS_ENABLED(CONFIG_USB_PHYTIUM_HOST))
+			mode = USB_DR_MODE_HOST;
+		else if (IS_ENABLED(CONFIG_USB_PHYTIUM_PERIPHERAL))
+			mode = USB_DR_MODE_PERIPHERAL;
+	}
+
+	if (mode != config->dr_mode) {
+		dev_warn(config->dev, "Configuration mismatch. dr_mode forced to %s\n",
+		mode == USB_DR_MODE_HOST ? "host" : "device");
+		config->dr_mode = mode;
+	}
+
+	return 0;
+}
+
+static int phytium_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
+{
+	struct phytium_cusb *config;
+	int retval = 0;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	retval = pcim_enable_device(pdev);
+	if (retval < 0) {
+		dev_err(&pdev->dev, "pcim_enable_device failed\n");
+		return -ENODEV;
+	}
+	pci_set_master(pdev);
+
+	config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL);
+	if (!config)
+		return -ENOMEM;
+
+	spin_lock_init(&config->lock);
+	config->dev = &pdev->dev;
+
+	config->irq = pdev->irq;
+	if (config->irq <= 0) {
+		dev_err(config->dev, "getting usb irq failed\n");
+		return config->irq;
+	}
+
+	config->regs = pci_iomap(pdev, 0, 0);
+	if (IS_ERR(config->regs)) {
+		dev_err(config->dev, "map IOMEM resource failed\n");
+		return -1;
+	}
+
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
+		dev_err(&pdev->dev, "failed to set 64-bit dma\n");
+	else if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
+		dev_err(&pdev->dev, "failed to set 32-bit dma\n");
+
+	pci_enable_msi(pdev);
+
+	phytium_get_dr_mode(config);
+
+	phytium_core_reset(config, false);
+
+	if (config->dr_mode == USB_DR_MODE_HOST || config->dr_mode == USB_DR_MODE_OTG)
+		phytium_host_init(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL || config->dr_mode == USB_DR_MODE_OTG)
+		phytium_gadget_init(config);
+
+	dev_set_drvdata(config->dev, config);
+
+	return 0;
+}
+
+static void phytium_pci_remove(struct pci_dev *pdev)
+{
+	struct phytium_cusb *config = dev_get_drvdata(&pdev->dev);
+
+	phytium_get_dr_mode(config);
+	if (config->dr_mode == USB_DR_MODE_HOST || config->dr_mode == USB_DR_MODE_OTG)
+		phytium_host_uninit(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL || config->dr_mode == USB_DR_MODE_OTG)
+		phytium_gadget_uninit(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL || config->dr_mode == USB_DR_MODE_OTG)
+		usb_del_gadget_udc(&config->gadget);
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	pr_info("%s %d\n", __func__, __LINE__);
+}
+
+static void phytium_pci_shutdown(struct pci_dev *pdev)
+{
+	struct phytium_cusb *config;
+
+	config = dev_get_drvdata(&pdev->dev);
+
+	phytium_get_dr_mode(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL || config->dr_mode == USB_DR_MODE_OTG)
+		usb_del_gadget_udc(&config->gadget);
+}
+
+#ifdef CONFIG_PM
+static int phytium_pci_resume(struct pci_dev *pdev)
+{
+	unsigned long flags = 0;
+	struct phytium_cusb *config;
+	int ret = 0;
+
+	config = dev_get_drvdata(&pdev->dev);
+
+	spin_lock_irqsave(&config->lock, flags);
+	ret = phytium_host_resume(config);
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return ret;
+}
+
+static int phytium_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	unsigned long flags = 0;
+	struct phytium_cusb *config;
+	int ret;
+
+	config = dev_get_drvdata(&pdev->dev);
+
+	spin_lock_irqsave(&config->lock, flags);
+	ret = phytium_host_suspend(config);
+	spin_unlock_irqrestore(&config->lock, flags);
+
+	return 0;
+}
+#endif
+
+const struct pci_device_id phytium_pci_id_table[] = {
+	{0x10ee, 0x8012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+	{}
+};
+
+static struct pci_driver phytium_otg_driver = {
+	.name = "phytium_usb",
+	.id_table = phytium_pci_id_table,
+	.probe = phytium_pci_probe,
+	.remove = phytium_pci_remove,
+	.shutdown = phytium_pci_shutdown,
+#ifdef CONFIG_PM
+	.resume	= phytium_pci_resume,
+	.suspend = phytium_pci_suspend,
+#endif
+};
+
+module_pci_driver(phytium_otg_driver);
+
+MODULE_AUTHOR("Chen Zhenhua <chenzhenhua@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium usb pci wrapper");
diff --git a/target/linux/phytium/files-5.10/drivers/usb/phytium/platform.c b/target/linux/phytium/files-5.10/drivers/usb/phytium/platform.c
new file mode 100644
index 00000000000000..7d39e4b6034d19
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/usb/phytium/platform.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-3.0
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+//#include <linux/usb/hcd.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
+#include <linux/usb/otg.h>
+#include <linux/acpi.h>
+#include "core.h"
+#include "hw-regs.h"
+
+#define PHYTIUM_OTG_USB_LOADED  3
+#define USB2_2_BASE_ADDRESS 0x31800000
+
+static const struct of_device_id phytium_otg_of_match[] = {
+	{
+		.compatible = "phytium,usb2",
+	},
+	{},
+};
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_otg_acpi_match[] = {
+	{ "PHYT0037", 0 },
+	{ }
+};
+#endif
+
+static int phytium_get_dr_mode(struct phytium_cusb *config)
+{
+	config->dr_mode = usb_get_dr_mode(config->dev);
+	if (config->dr_mode == USB_DR_MODE_UNKNOWN)
+		config->dr_mode = USB_DR_MODE_PERIPHERAL;
+
+	return 0;
+}
+
+static irqreturn_t platform_usb_irq(int irq, void *dev_id)
+{
+	unsigned long flags;
+	uint8_t otgstate;
+
+	struct phytium_cusb *config = (struct phytium_cusb *)dev_id;
+	struct GADGET_CTRL *gadget_ctrl = config->gadget_priv;
+	struct HOST_CTRL *host_ctrl = config->host_priv;
+
+	if (gadget_ctrl || host_ctrl) {
+		if (host_ctrl)
+			otgstate = phytium_read8(&host_ctrl->regs->otgstate);
+		else
+			otgstate = phytium_read8(&gadget_ctrl->regs->otgstate);
+
+		spin_lock_irqsave(&config->lock, flags);
+		if (otgstate > HOST_OTG_STATE_A_WAIT_VFALL)
+			config->gadget_obj->gadget_isr(config->gadget_priv);
+		else
+			config->host_obj->host_isr(config->host_priv);
+		spin_unlock_irqrestore(&config->lock, flags);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int phytium_driver_probe(struct platform_device *pdev)
+{
+	struct phytium_cusb *config;
+	struct resource *res, *phy_res;
+	int retval = 0;
+
+	config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL);
+	if (!config)
+		return -ENOMEM;
+
+	spin_lock_init(&config->lock);
+	config->dev = &pdev->dev;
+	config->isVhubHost = false;
+
+	config->irq = platform_get_irq(pdev, 0);
+	if (config->irq <= 0) {
+		dev_err(config->dev, "getting usb irq failed\n");
+		return config->irq;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	config->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+	if (IS_ERR(config->regs)) {
+		dev_err(config->dev, "map IOMEM resource failed\n");
+		return -1;
+	}
+
+	phy_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	config->phy_regs = devm_ioremap(&pdev->dev, phy_res->start, resource_size(phy_res));
+	if (IS_ERR(config->phy_regs)) {
+		dev_err(config->dev, "map IOMEM phy resource failed\n");
+		return -1;
+	}
+
+	phytium_get_dr_mode(config);
+
+	phytium_core_reset(config, false);
+
+	if (config->dr_mode == USB_DR_MODE_HOST ||
+	    config->dr_mode == USB_DR_MODE_OTG) {
+		if (res->start == USB2_2_BASE_ADDRESS)
+			config->isVhubHost = true;
+
+		phytium_host_init(config);
+	}
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		phytium_gadget_init(config);
+
+	dev_set_drvdata(&pdev->dev, config);
+
+	if (config->irq > 0) {
+		retval = devm_request_irq(config->dev, config->irq, platform_usb_irq,
+				IRQF_SHARED, "phytium_otg", config);
+		if (retval != 0) {
+			dev_err(config->dev, "request irq %d err %d\n", config->irq, retval);
+			config->irq = 0;
+		}
+	}
+
+	return retval;
+}
+
+static int phytium_driver_remove(struct platform_device *dev)
+{
+	struct phytium_cusb *config = platform_get_drvdata(dev);
+
+	if (!config)
+		return 0;
+
+	phytium_get_dr_mode(config);
+
+	if (config->dr_mode == USB_DR_MODE_HOST ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		phytium_host_uninit(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		phytium_gadget_uninit(config);
+
+	dev_set_drvdata(&dev->dev, NULL);
+	return 0;
+}
+
+static void phytium_driver_shutdown(struct platform_device *dev)
+{
+	pr_info("%s %d\n", __func__, __LINE__);
+}
+
+#ifdef CONFIG_PM
+static int phytium_driver_suspend(struct device *dev)
+{
+	struct phytium_cusb *config;
+	int ret = 0;
+
+	config = dev_get_drvdata(dev);
+
+	if (config->dr_mode == USB_DR_MODE_HOST ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		ret = phytium_host_suspend(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		ret = phytium_gadget_suspend(config);
+
+	return ret;
+}
+
+static int phytium_driver_resume(struct device *dev)
+{
+	struct phytium_cusb *config;
+	int ret = 0;
+
+	config = dev_get_drvdata(dev);
+	if (config->dr_mode == USB_DR_MODE_HOST ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		ret = phytium_host_resume(config);
+
+	if (config->dr_mode == USB_DR_MODE_PERIPHERAL ||
+			config->dr_mode == USB_DR_MODE_OTG)
+		ret = phytium_gadget_resume(config);
+
+	return ret;
+}
+
+static const struct dev_pm_ops phytium_usb_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(phytium_driver_suspend, phytium_driver_resume)
+};
+#endif
+
+static struct platform_driver phytium_otg_driver = {
+	.driver	=	{
+		.name	= "phytium-otg",
+		.of_match_table	= of_match_ptr(phytium_otg_of_match),
+		.acpi_match_table = ACPI_PTR(phytium_otg_acpi_match),
+#ifdef CONFIG_PM
+		.pm	= &phytium_usb_pm_ops,
+#endif
+	},
+	.probe	= phytium_driver_probe,
+	.remove	= phytium_driver_remove,
+	.shutdown	= phytium_driver_shutdown,
+};
+
+module_platform_driver(phytium_otg_driver);
+
+MODULE_AUTHOR("Chen Zhenhua <chenzhenhua@phytium.com.cn>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Phytium usb platform wrapper");
diff --git a/target/linux/phytium/files-5.10/drivers/w1/masters/phytium_w1.c b/target/linux/phytium/files-5.10/drivers/w1/masters/phytium_w1.c
new file mode 100644
index 00000000000000..77badce5c22a3e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/drivers/w1/masters/phytium_w1.c
@@ -0,0 +1,643 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * drivers/w1/masters/phytium_w1m.c
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/acpi.h>
+#include <linux/w1.h>
+
+#define PHY_W1M_CTL                             0x08
+
+/* Simplify mode */
+#define PHY_W1M_CMD                             0x04
+#define PHY_W1M_PWM0_START_B                    0x30
+#define PHY_W1M_PWM0_END_B                      0x34
+#define PHY_W1M_PWM1_START_B                    0x38
+#define PHY_W1M_PWM1_END_B                      0x3c
+#define PHY_W1M_SAMPLE_B                        0x40
+#define PHY_W1M_INT_EN_B                        0x64
+#define PHY_W1M_INT_STATUS_B                    0x74
+#define PHY_W1M_DATA_REG                        0x70
+
+#define PHY_W1M_CMD_ROM_SEARCH                  0xF0
+#define PHY_W1M_CMD_WRITE_BIT                   0x35
+#define PHY_W1M_CMD_WRITE_BYTE                  0x36
+#define PHY_W1M_CMD_RESET_BUS                   0x37
+#define PHY_W1M_CMD_READ_BIT                    0x3A
+#define PHY_W1M_CMD_READ_BYTE                   0x3B
+#define PHY_W1M_SLAVE_ROM_ID                    0x160
+
+#define PHY_W1M_INT_EN_TXCOMPLETE               BIT(6)
+#define PHY_W1M_INT_EN_RXCOMPLETE               BIT(7)
+
+#define PHY_W1M_INT_STATUS_TXCOMPLETE           BIT(6)
+#define PHY_W1M_INT_STATUS_RXCOMPLETE           BIT(7)
+
+#define W1M_MOD_W1                              1
+#define W1M_MOD_PECI                            0
+
+#define PHY_W1M_FLAG_CLEAR                      0
+#define PHY_W1M_FLAG_SET                        1
+#define PHY_W1M_TIMEOUT                         (HZ/5)
+
+#define PHY_W1M_MAX_USER			4
+
+static DECLARE_WAIT_QUEUE_HEAD(w1m_wait_queue);
+
+struct w1m_data {
+	struct device           *dev;
+	void __iomem            *w1m_base;
+	/* lock status update */
+	struct  mutex           w1m_mutex;
+	int                     w1m_usecount;
+	u8                      w1m_irqstatus;
+	/* device lock */
+	spinlock_t              w1m_spinlock;
+	/*
+	 * Used to control the call to phytium_w1m_get and phytium_w1m_put.
+	 * Non-w1 Protocol: Write the CMD|REG_address first, followed by
+	 * the data wrire or read.
+	 */
+	int                     init_trans;
+};
+
+/* W1 register I/O routines */
+static inline u8 phytium_w1m_read(struct w1m_data *w1m_data, u32 offset)
+{
+	return readl(w1m_data->w1m_base + offset);
+}
+
+static inline void phytium_w1m_write(struct w1m_data *w1m_data, u32 offset, u8 val)
+{
+	writel(val, w1m_data->w1m_base + offset);
+}
+
+static inline u8 phytium_w1m_merge(struct w1m_data *w1m_data, u32 offset,
+				   u8 val, u8 mask)
+{
+	u8 new_val = (__raw_readl(w1m_data->w1m_base + offset) & ~mask)
+			| (val & mask);
+	writel(new_val, w1m_data->w1m_base + offset);
+
+	return new_val;
+}
+
+static void w1m_disable_interrupt(struct w1m_data *w1m_data, u32 offset,
+				  u32 mask)
+{
+	u32 ie;
+
+	ie = readl(w1m_data->w1m_base + offset);
+	writel(ie & mask, w1m_data->w1m_base + offset);
+}
+
+/* write out a byte or bit and fill *status with W1M_INT_STATUS */
+static int phytium_write_data(struct w1m_data *w1m_data, u8 val, u8 *status, bool is_bit)
+{
+	int ret;
+	unsigned long irqflags;
+
+	*status = 0;
+
+	spin_lock_irqsave(&w1m_data->w1m_spinlock, irqflags);
+	/* clear interrupt flags via a dummy read */
+	phytium_w1m_read(w1m_data, PHY_W1M_INT_STATUS_B);
+	/* ISR loads it with new INT_STATUS */
+	w1m_data->w1m_irqstatus = 0;
+	spin_unlock_irqrestore(&w1m_data->w1m_spinlock, irqflags);
+
+	phytium_w1m_merge(w1m_data, PHY_W1M_INT_EN_B,
+			  PHY_W1M_INT_EN_TXCOMPLETE,
+			  PHY_W1M_INT_EN_TXCOMPLETE);
+
+	phytium_w1m_write(w1m_data, PHY_W1M_DATA_REG, val);
+	phytium_w1m_write(w1m_data, PHY_W1M_CMD, is_bit ? PHY_W1M_CMD_WRITE_BIT : PHY_W1M_CMD_WRITE_BYTE);
+
+	/* wait for the TXCOMPLETE bit */
+	ret = wait_event_timeout(w1m_wait_queue,
+		w1m_data->w1m_irqstatus, PHY_W1M_TIMEOUT);
+	if (ret == 0) {
+		dev_err(w1m_data->dev, "TX wait elapsed\n");
+		ret = -ETIMEDOUT;
+		goto out;
+	}
+
+	*status = w1m_data->w1m_irqstatus;
+	/* check irqstatus */
+	if (!(*status & PHY_W1M_INT_STATUS_TXCOMPLETE)) {
+		dev_err(w1m_data->dev,
+			"timeout waiting for TXCOMPLETE/RXCOMPLETE, %x", *status);
+		ret = -ETIMEDOUT;
+	}
+
+out:
+	return ret;
+}
+
+static irqreturn_t w1m_isr(int irq, void *_w1m)
+{
+	struct w1m_data *w1m_data = _w1m;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&w1m_data->w1m_spinlock, irqflags);
+	w1m_data->w1m_irqstatus = phytium_w1m_read(w1m_data, PHY_W1M_INT_STATUS_B);
+	spin_unlock_irqrestore(&w1m_data->w1m_spinlock, irqflags);
+
+	phytium_w1m_write(w1m_data, PHY_W1M_INT_STATUS_B, 0x00);
+	if (w1m_data->w1m_irqstatus &
+		(PHY_W1M_INT_STATUS_TXCOMPLETE | PHY_W1M_INT_STATUS_RXCOMPLETE)) {
+		/* wake up sleeping process */
+		wake_up(&w1m_wait_queue);
+	}
+
+	return IRQ_HANDLED;
+}
+
+
+static int phytium_read_data(struct w1m_data *w1m_data, u8 *val, bool is_bit)
+{
+	int ret = 0;
+	u8 status;
+	unsigned long irqflags;
+
+	ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+	if (ret < 0) {
+		ret = -EINTR;
+		goto rtn;
+	}
+
+	if (!w1m_data->w1m_usecount) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	spin_lock_irqsave(&w1m_data->w1m_spinlock, irqflags);
+	/* clear interrupt flags via a dummy read */
+	phytium_w1m_read(w1m_data, PHY_W1M_INT_STATUS_B);
+	/* ISR loads it with new INT_STATUS */
+	w1m_data->w1m_irqstatus = 0;
+	spin_unlock_irqrestore(&w1m_data->w1m_spinlock, irqflags);
+
+	phytium_w1m_merge(w1m_data, PHY_W1M_INT_EN_B,
+			  PHY_W1M_INT_EN_RXCOMPLETE,
+			  PHY_W1M_INT_EN_RXCOMPLETE);
+
+	phytium_w1m_write(w1m_data, PHY_W1M_CMD, is_bit ? PHY_W1M_CMD_READ_BIT : PHY_W1M_CMD_READ_BYTE);
+
+	wait_event_timeout(w1m_wait_queue,
+			   (w1m_data->w1m_irqstatus & PHY_W1M_INT_STATUS_RXCOMPLETE),
+			   PHY_W1M_TIMEOUT);
+
+	status = w1m_data->w1m_irqstatus;
+	/* check irqstatus */
+	if (!(status & PHY_W1M_INT_STATUS_RXCOMPLETE)) {
+		dev_err(w1m_data->dev, "timeout waiting for RXCOMPLETE, %x", status);
+		ret = -ETIMEDOUT;
+		goto out;
+	}
+
+	/* the data is ready. Read it in! */
+	*val = phytium_w1m_read(w1m_data, PHY_W1M_DATA_REG);
+out:
+	mutex_unlock(&w1m_data->w1m_mutex);
+rtn:
+	return ret;
+}
+
+
+static int phytium_w1m_get(struct w1m_data *w1m_data)
+{
+	int ret = 0;
+
+	ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+	if (ret < 0) {
+		ret = -EINTR;
+		goto rtn;
+	}
+
+	if (w1m_data->w1m_usecount == PHY_W1M_MAX_USER) {
+		dev_warn(w1m_data->dev, "attempt to exceed the max use count");
+		ret = -EINVAL;
+		goto out;
+	} else {
+		w1m_data->w1m_usecount++;
+		try_module_get(THIS_MODULE);
+		if (w1m_data->w1m_usecount == 1)
+			pm_runtime_get_sync(w1m_data->dev);
+	}
+
+out:
+	mutex_unlock(&w1m_data->w1m_mutex);
+rtn:
+	return ret;
+}
+
+/* Disable clocks to the module */
+static int phytium_w1m_put(struct w1m_data *w1m_data)
+{
+	int ret = 0;
+
+	ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+	if (ret < 0)
+		return -EINTR;
+
+	if (w1m_data->w1m_usecount == 0) {
+		dev_warn(w1m_data->dev,
+			"attempt to decrement use count when it is zero");
+		ret = -EINVAL;
+	} else {
+		w1m_data->w1m_usecount--;
+		module_put(THIS_MODULE);
+		if (w1m_data->w1m_usecount == 0)
+			pm_runtime_put_sync(w1m_data->dev);
+	}
+	mutex_unlock(&w1m_data->w1m_mutex);
+
+	return ret;
+}
+
+/*
+ * W1 triplet callback function - used for searching ROM addresses.
+ * Registered only when controller is in 1-wire mode.
+ */
+static u8 phytium_w1_triplet(void *_w1m, u8 bdir)
+{
+	u8 id_bit, comp_bit;
+	int err;
+	u8 ret = 0x3; /* no slaves responded */
+	struct w1m_data *w1m_data = _w1m;
+
+	phytium_w1m_get(_w1m);
+
+	err = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+	if (err < 0) {
+		dev_err(w1m_data->dev, "Could not acquire mutex\n");
+		goto rtn;
+	}
+
+	w1m_data->w1m_irqstatus = 0;
+	/* read id_bit */
+	phytium_w1m_merge(w1m_data, PHY_W1M_INT_EN_B,
+			  PHY_W1M_INT_EN_RXCOMPLETE,
+			  PHY_W1M_INT_EN_RXCOMPLETE);
+	phytium_w1m_write(w1m_data, PHY_W1M_CMD, 0x3a);
+
+	err = wait_event_timeout(w1m_wait_queue,
+				 (w1m_data->w1m_irqstatus
+				  & PHY_W1M_INT_STATUS_RXCOMPLETE),
+				 PHY_W1M_TIMEOUT);
+	if (err == 0) {
+		dev_err(w1m_data->dev, "RX wait elapsed\n");
+		goto out;
+	}
+	id_bit = (phytium_w1m_read(_w1m, PHY_W1M_DATA_REG) & 0x01);
+
+	w1m_data->w1m_irqstatus = 0;
+	/* read comp_bit */
+	phytium_w1m_merge(w1m_data, PHY_W1M_INT_EN_B,
+				PHY_W1M_INT_EN_RXCOMPLETE,
+				PHY_W1M_INT_EN_RXCOMPLETE);
+	phytium_w1m_write(w1m_data, PHY_W1M_CMD, 0x3a);
+	err = wait_event_timeout(w1m_wait_queue,
+				 (w1m_data->w1m_irqstatus
+				  & PHY_W1M_INT_STATUS_RXCOMPLETE),
+				 PHY_W1M_TIMEOUT);
+	if (err == 0) {
+		dev_err(w1m_data->dev, "RX wait elapsed\n");
+		goto out;
+	}
+	comp_bit = (phytium_w1m_read(_w1m, PHY_W1M_DATA_REG) & 0x01);
+
+	if (id_bit && comp_bit) {
+		ret = 0x03;  /* no slaves responded */
+		goto out;
+	}
+	if (!id_bit && !comp_bit) {
+		/* Both bits are valid, take the direction given */
+		ret = bdir ? 0x04 : 0;
+	} else {
+		/* Only one bit is valid, take that direction */
+		bdir = id_bit;
+		ret = id_bit ? 0x05 : 0x02;
+	}
+
+	w1m_data->w1m_irqstatus = 0;
+	/* write bdir bit */
+	phytium_w1m_merge(w1m_data, PHY_W1M_INT_EN_B,
+				PHY_W1M_INT_EN_TXCOMPLETE,
+				PHY_W1M_INT_EN_TXCOMPLETE);
+
+	phytium_w1m_write(w1m_data, PHY_W1M_DATA_REG, bdir);
+	phytium_w1m_write(w1m_data, PHY_W1M_CMD, 0x35);
+
+	err = wait_event_timeout(w1m_wait_queue,
+				 (w1m_data->w1m_irqstatus
+				  & PHY_W1M_INT_STATUS_TXCOMPLETE),
+				 PHY_W1M_TIMEOUT);
+	if (err == 0) {
+		dev_err(w1m_data->dev, "TX wait elapsed\n");
+		goto out;
+	}
+
+out:
+	mutex_unlock(&w1m_data->w1m_mutex);
+rtn:
+	phytium_w1m_put(_w1m);
+	return ret;
+}
+
+static u8 phytium_w1_touch_bit(void *_w1m, u8 bit)
+{
+	u8 result = 0;
+	int err;
+	struct w1m_data *w1m_data = _w1m;
+
+	phytium_w1m_get(w1m_data);
+
+	w1m_data->init_trans++;
+
+	err = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+	if (err < 0) {
+		dev_err(w1m_data->dev, "Could not acquired mutex\n");
+		goto rtn;
+	}
+
+	w1m_data->w1m_irqstatus = 0;
+
+	phytium_w1m_merge(w1m_data, PHY_W1M_INT_EN_B,
+			PHY_W1M_INT_EN_RXCOMPLETE,
+			PHY_W1M_INT_EN_RXCOMPLETE);
+	phytium_w1m_write(w1m_data, PHY_W1M_CMD, 0x3a);
+
+	err = wait_event_timeout(w1m_wait_queue,
+			(w1m_data->w1m_irqstatus
+			 & PHY_W1M_INT_STATUS_RXCOMPLETE),
+			PHY_W1M_TIMEOUT);
+	if (err == 0) {
+		dev_info(w1m_data->dev, "Rx wait elapsed\n");
+		goto out;
+	}
+
+	result = (phytium_w1m_read(w1m_data, PHY_W1M_DATA_REG) & 0x01);
+
+	w1m_data->w1m_irqstatus = 0;
+
+out:
+	mutex_unlock(&w1m_data->w1m_mutex);
+
+rtn:
+	phytium_w1m_put(w1m_data);
+
+	return result;
+}
+
+/* reset callback */
+static u8 phytium_w1_reset_bus(void *_w1m)
+{
+	phytium_w1m_get(_w1m);
+	phytium_w1m_write(_w1m, PHY_W1M_CMD, 0x37);
+	mdelay(1);
+	phytium_w1m_put(_w1m);
+	return 0;
+}
+
+/* Read a byte of data from the device */
+static u8 phytium_w1_read_data(void *_w1m, bool is_bit)
+{
+	struct w1m_data *w1m_data = _w1m;
+	u8 val = 0;
+	int ret;
+
+	/* First write to initialize the transfer */
+	if (w1m_data->init_trans == 0)
+		phytium_w1m_get(w1m_data);
+
+	w1m_data->init_trans++;
+	ret = phytium_read_data(w1m_data, &val, is_bit);
+	if (ret) {
+		ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+		if (ret < 0) {
+			dev_err(w1m_data->dev, "Could not acquire mutex\n");
+			return -EINTR;
+		}
+		w1m_data->init_trans = 0;
+		mutex_unlock(&w1m_data->w1m_mutex);
+		phytium_w1m_put(w1m_data);
+		return -1;
+	}
+
+	w1m_disable_interrupt(w1m_data, PHY_W1M_INT_EN_B,
+			      ~((u32)PHY_W1M_INT_EN_RXCOMPLETE));
+
+	/* Write followed by a read, release the module */
+	if (w1m_data->init_trans) {
+		ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+		if (ret < 0) {
+			dev_err(w1m_data->dev, "Could not acquire mutex\n");
+			return -EINTR;
+		}
+		w1m_data->init_trans = 0;
+		mutex_unlock(&w1m_data->w1m_mutex);
+		phytium_w1m_put(w1m_data);
+	}
+
+	return val;
+}
+
+static u8 phytium_w1_read_bit(void *_w1m)
+{
+	return phytium_w1_read_data(_w1m, true);
+}
+
+static u8 phytium_w1_read_byte(void *_w1m)
+{
+	return phytium_w1_read_data(_w1m, false);
+}
+
+/* Write a byte of data to the device */
+static void phytium_w1_write_data(void *_w1m, u8 byte, bool is_bit)
+{
+	struct w1m_data *w1m_data = _w1m;
+	int ret;
+	u8 status;
+
+	/* First write to initialize the transfer */
+	if (w1m_data->init_trans == 0)
+		phytium_w1m_get(w1m_data);
+
+	ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+	if (ret < 0) {
+		dev_err(w1m_data->dev, "Could not acquire mutex\n");
+		return;
+	}
+	mutex_unlock(&w1m_data->w1m_mutex);
+
+	ret = phytium_write_data(w1m_data, byte, &status, is_bit);
+	if (ret < 0) {
+		dev_err(w1m_data->dev, "TX failure:Ctrl status %x\n", status);
+		return;
+	}
+
+	w1m_data->init_trans++;
+	w1m_disable_interrupt(w1m_data, PHY_W1M_INT_EN_B,
+			      ~((u32)PHY_W1M_INT_EN_TXCOMPLETE));
+	/* Second write, data transferred. Release the module */
+	if (w1m_data->init_trans > 1) {
+		phytium_w1m_put(w1m_data);
+		ret = mutex_lock_interruptible(&w1m_data->w1m_mutex);
+		if (ret < 0) {
+			dev_err(w1m_data->dev, "Could not acquire mutex\n");
+			return;
+		}
+		w1m_data->init_trans = 0;
+		mutex_unlock(&w1m_data->w1m_mutex);
+	}
+}
+
+static void phytium_w1_write_bit(void *_w1m, u8 bit)
+{
+	phytium_w1_write_data(_w1m, bit, true);
+}
+
+static void phytium_w1_write_byte(void *_w1m, u8 bit)
+{
+	phytium_w1_write_data(_w1m, bit, false);
+}
+
+static struct w1_bus_master phytium_w1_master = {
+	.read_byte	= phytium_w1_read_byte,
+	.write_byte	= phytium_w1_write_byte,
+	.read_bit	= phytium_w1_read_bit,
+	.write_bit	= phytium_w1_write_bit,
+	.reset_bus	= phytium_w1_reset_bus,
+	.touch_bit	= phytium_w1_touch_bit,
+};
+
+static int phytium_w1m_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct w1m_data *w1m_data;
+	struct resource *res;
+	int ret, irq;
+
+	w1m_data = devm_kzalloc(dev, sizeof(*w1m_data), GFP_KERNEL);
+	if (!w1m_data)
+		return -ENOMEM;
+
+	w1m_data->dev = dev;
+	platform_set_drvdata(pdev, w1m_data);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	w1m_data->w1m_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(w1m_data->w1m_base))
+		return PTR_ERR(w1m_data->w1m_base);
+
+	w1m_data->w1m_usecount = 0;
+	mutex_init(&w1m_data->w1m_mutex);
+
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pm_runtime_get_sync failed\n");
+		goto err_w1;
+	}
+
+	spin_lock_init(&w1m_data->w1m_spinlock);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq	< 0) {
+		dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
+		ret = irq;
+		goto err_irq;
+	}
+
+	ret = devm_request_irq(dev, irq, w1m_isr, 0, "phytium-w1", w1m_data);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "could not request irq\n");
+		goto err_irq;
+	}
+
+	pm_runtime_put_sync(&pdev->dev);
+
+	phytium_w1_master.triplet = phytium_w1_triplet;
+	phytium_w1m_write(w1m_data, PHY_W1M_CTL, 0x10);
+	phytium_w1m_write(w1m_data, PHY_W1M_INT_EN_B, 0x00);
+
+	phytium_w1_master.data = w1m_data;
+
+	ret = w1_add_master_device(&phytium_w1_master);
+	if (ret) {
+		dev_err(&pdev->dev, "Failure in registering w1 master\n");
+		goto err_w1;
+	}
+
+	return 0;
+
+err_irq:
+	pm_runtime_put_sync(&pdev->dev);
+err_w1:
+	pm_runtime_disable(&pdev->dev);
+
+	return ret;
+}
+
+static int phytium_w1m_remove(struct platform_device *pdev)
+{
+	struct w1m_data *w1m_data = platform_get_drvdata(pdev);
+
+	mutex_lock(&w1m_data->w1m_mutex);
+
+	if (w1m_data->w1m_usecount) {
+		dev_warn(&pdev->dev, "removed when use count is not zero\n");
+		mutex_unlock(&w1m_data->w1m_mutex);
+		return -EBUSY;
+	}
+
+	mutex_unlock(&w1m_data->w1m_mutex);
+
+	/* remove module dependency */
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static const struct of_device_id phytium_w1m_dt_ids[] = {
+	{ .compatible = "phytium,w1" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, phytium_w1m_dt_ids);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_w1m_acpi_ids[] = {
+	{ "PHYT0034", 0 },
+	{ }
+};
+#endif
+
+static struct platform_driver phytium_w1m_driver = {
+	.probe = phytium_w1m_probe,
+	.remove = phytium_w1m_remove,
+	.driver = {
+		.name =	"phytium-w1",
+		.of_match_table = phytium_w1m_dt_ids,
+		.acpi_match_table = ACPI_PTR(phytium_w1m_acpi_ids),
+	},
+};
+module_platform_driver(phytium_w1m_driver);
+
+MODULE_AUTHOR("Zhu Mingshuai <zhumingshuai@phytium.com.cn>");
+MODULE_DESCRIPTION("Phytium w1 bus master driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/sound/pci/hda/hda_phytium.c b/target/linux/phytium/files-5.10/sound/pci/hda/hda_phytium.c
new file mode 100644
index 00000000000000..69bfe699d2358e
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/pci/hda/hda_phytium.c
@@ -0,0 +1,1125 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Implementation of primary ALSA driver code for Phytium HD Audio.
+ *
+ * Copyright (c) 2018-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/clocksource.h>
+#include <linux/time.h>
+#include <linux/completion.h>
+#include <linux/of_device.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/hdaudio.h>
+#include <sound/hda_i915.h>
+#include <linux/vgaarb.h>
+#include <linux/vga_switcheroo.h>
+#include <linux/firmware.h>
+#include <linux/acpi.h>
+#include <linux/dma-map-ops.h>
+#include <sound/hda_codec.h>
+#include "hda_controller.h"
+#include "hda_phytium.h"
+
+#include "hda_intel_trace.h"
+
+/* position fix mode */
+enum {
+	POS_FIX_AUTO,
+	POS_FIX_LPIB,
+	POS_FIX_POSBUF,
+	POS_FIX_VIACOMBO,
+	POS_FIX_COMBO,
+};
+
+/* Define IN stream 0 FIFO size offset in VIA controller */
+#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90
+
+/* FT have 4 playback and 4 capture */
+#define FT4C_NUM_CAPTURE	4
+#define FT4C_NUM_PLAYBACK	4
+
+#define DWORD_BYTE_WIDTH 4
+#define BYTE_BIT_WIDTH   8
+
+static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
+static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
+static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
+static char *model[SNDRV_CARDS];
+static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
+static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
+static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
+static int probe_only[SNDRV_CARDS];
+static int jackpoll_ms[SNDRV_CARDS];
+static int single_cmd = -1;
+static int enable_msi = -1;
+#ifdef CONFIG_SND_HDA_INPUT_BEEP
+static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
+					CONFIG_SND_HDA_INPUT_BEEP_MODE};
+#endif
+
+module_param_array(index, int, NULL, 0444);
+MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
+module_param_array(id, charp, NULL, 0444);
+MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
+module_param_array(enable, bool, NULL, 0444);
+MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
+module_param_array(model, charp, NULL, 0444);
+MODULE_PARM_DESC(model, "Use the given board model.");
+module_param_array(position_fix, int, NULL, 0444);
+MODULE_PARM_DESC(position_fix, "DMA pointer read method. (-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
+module_param_array(bdl_pos_adj, int, NULL, 0644);
+MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
+module_param_array(probe_mask, int, NULL, 0444);
+MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
+module_param_array(probe_only, int, NULL, 0444);
+MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
+module_param_array(jackpoll_ms, int, NULL, 0444);
+MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
+module_param(single_cmd, bint, 0444);
+MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
+module_param(enable_msi, bint, 0444);
+MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
+#ifdef CONFIG_SND_HDA_INPUT_BEEP
+module_param_array(beep_mode, bool, NULL, 0444);
+MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode (0=off, 1=on) (default=1).");
+#endif
+
+#define power_save 0
+
+static int align_buffer_size = -1;
+module_param(align_buffer_size, bint, 0644);
+MODULE_PARM_DESC(align_buffer_size,
+		"Force buffer and period sizes to be multiple of 128 bytes.");
+
+/* driver types */
+enum {
+	AZX_DRIVER_ICH,
+	AZX_DRIVER_PCH,
+	AZX_DRIVER_SCH,
+	AZX_DRIVER_HDMI,
+	AZX_DRIVER_ATI,
+	AZX_DRIVER_ATIHDMI,
+	AZX_DRIVER_ATIHDMI_NS,
+	AZX_DRIVER_VIA,
+	AZX_DRIVER_SIS,
+	AZX_DRIVER_ULI,
+	AZX_DRIVER_NVIDIA,
+	AZX_DRIVER_TERA,
+	AZX_DRIVER_CTX,
+	AZX_DRIVER_CTHDA,
+	AZX_DRIVER_CMEDIA,
+	AZX_DRIVER_GENERIC,
+	AZX_DRIVER_FT,
+	AZX_NUM_DRIVERS, /* keep this as last entry */
+};
+
+/* NOP for other archs */
+static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
+				 bool on)
+{
+}
+
+static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
+				   struct snd_pcm_substream *substream, bool on)
+{
+}
+
+static int azx_acquire_irq(struct azx *chip, int do_disconnect);
+
+/* calculate runtime delay from LPIB */
+static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
+				   unsigned int pos)
+{
+	struct snd_pcm_substream *substream = azx_dev->core.substream;
+	int stream = substream->stream;
+	unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
+	int delay;
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+		delay = pos - lpib_pos;
+	else
+		delay = lpib_pos - pos;
+	if (delay < 0) {
+		if (delay >= azx_dev->core.delay_negative_threshold)
+			delay = 0;
+		else
+			delay += azx_dev->core.bufsize;
+	}
+
+	if (delay >= azx_dev->core.period_bytes) {
+		dev_info(chip->card->dev,
+			 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
+			 delay, azx_dev->core.period_bytes);
+		delay = 0;
+		chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
+		chip->get_delay[stream] = NULL;
+	}
+
+	return bytes_to_frames(substream->runtime, delay);
+}
+
+static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
+
+/* called from IRQ */
+static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
+{
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+	int ok;
+
+	ok = azx_position_ok(chip, azx_dev);
+	if (ok == 1) {
+		azx_dev->irq_pending = 0;
+		return ok;
+	} else if (ok == 0) {
+		/* bogus IRQ, process it later */
+		azx_dev->irq_pending = 1;
+		schedule_work(&hda->irq_pending_work);
+	}
+	return 0;
+}
+
+static int azx_ft_link_power(struct azx *chip, bool enable)
+{
+	return 0;
+}
+
+/*
+ * Check whether the current DMA position is acceptable for updating
+ * periods.  Returns non-zero if it's OK.
+ *
+ * Many HD-audio controllers appear pretty inaccurate about
+ * the update-IRQ timing.  The IRQ is issued before actually the
+ * data is processed.  So, we need to process it afterwords in a
+ * workqueue.
+ */
+static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
+{
+	struct snd_pcm_substream *substream = azx_dev->core.substream;
+	int stream = substream->stream;
+	u32 wallclk;
+	unsigned int pos;
+
+	wallclk = (azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk);
+
+	if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
+		return -1;	/* bogus (too early) interrupt */
+
+	if (chip->get_position[stream])
+		pos = chip->get_position[stream](chip, azx_dev);
+	else { /* use the position buffer as default */
+		pos = azx_get_pos_posbuf(chip, azx_dev);
+		if (!pos || pos == (u32)-1) {
+			dev_info(chip->card->dev,
+				 "Invalid position buffer, using LPIB read method instead.\n");
+			chip->get_position[stream] = azx_get_pos_lpib;
+			if (chip->get_position[0] == azx_get_pos_lpib &&
+			    chip->get_position[1] == azx_get_pos_lpib)
+				azx_bus(chip)->use_posbuf = false;
+			pos = azx_get_pos_lpib(chip, azx_dev);
+			chip->get_delay[stream] = NULL;
+		} else {
+			chip->get_position[stream] = azx_get_pos_posbuf;
+			if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
+				chip->get_delay[stream] = azx_get_delay_from_lpib;
+		}
+	}
+
+	if (pos >= azx_dev->core.bufsize)
+		pos = 0;
+
+	if (WARN_ONCE(!azx_dev->core.period_bytes,
+		      "hda-ft: zero azx_dev->period_bytes"))
+		return -1; /* this shouldn't happen! */
+	if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
+	    pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
+		/* NG - it's below the first next period boundary */
+		return chip->bdl_pos_adj ? 0 : -1;
+
+	azx_dev->core.start_wallclk += wallclk;
+
+	return 1; /* OK, it's fine */
+}
+
+static int hda_ft_dma_configure(struct device *dev)
+{
+	const struct of_device_id *match_of;
+	const struct acpi_device_id *match_acpi;
+
+	if (dev->of_node) {
+		match_of = of_match_device(dev->driver->of_match_table, dev);
+		if (!match_of) {
+			dev_err(dev, "Error DT match data is missing\n");
+			return -ENODEV;
+		}
+		set_dma_ops(dev, NULL);
+		/*
+		 * Because there is no way to transfer to non-coherent dma in
+		 * of_dma_configure if 'dma-coherent' is described in DT,
+		 * use acpi_dma_configure to alloc dma_ops correctly.
+		 */
+		acpi_dma_configure(dev, DEV_DMA_NON_COHERENT);
+	} else if (has_acpi_companion(dev)) {
+		match_acpi = acpi_match_device(dev->driver->acpi_match_table, dev);
+		if (!match_acpi) {
+			dev_err(dev, "Error ACPI match data is missing\n");
+			return -ENODEV;
+		}
+		set_dma_ops(dev, NULL);
+		acpi_dma_configure(dev, DEV_DMA_NON_COHERENT);
+	}
+
+	return 0;
+}
+
+/* The work for pending PCM period updates. */
+static void azx_irq_pending_work(struct work_struct *work)
+{
+	struct hda_ft *hda = container_of(work, struct hda_ft, irq_pending_work);
+	struct azx *chip = &hda->chip;
+	struct hdac_bus *bus = azx_bus(chip);
+	struct hdac_stream *s;
+	int pending, ok;
+
+	if (!hda->irq_pending_warned) {
+		dev_info(chip->card->dev,
+			 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
+			 chip->card->number);
+		hda->irq_pending_warned = 1;
+	}
+
+	for (;;) {
+		pending = 0;
+		spin_lock_irq(&bus->reg_lock);
+		list_for_each_entry(s, &bus->stream_list, list) {
+			struct azx_dev *azx_dev = stream_to_azx_dev(s);
+
+			if (!azx_dev->irq_pending ||
+			    !s->substream || !s->running)
+				continue;
+			ok = azx_position_ok(chip, azx_dev);
+			if (ok > 0) {
+				azx_dev->irq_pending = 0;
+				spin_unlock(&bus->reg_lock);
+				snd_pcm_period_elapsed(s->substream);
+				spin_lock(&bus->reg_lock);
+			} else if (ok < 0) {
+				pending = 0;	/* too early */
+			} else {
+				pending++;
+			}
+		}
+		spin_unlock_irq(&bus->reg_lock);
+		if (!pending)
+			return;
+		udelay(1000);
+	}
+}
+
+/* clear irq_pending flags and assure no on-going workq */
+static void azx_clear_irq_pending(struct azx *chip)
+{
+	struct hdac_bus *bus = azx_bus(chip);
+	struct hdac_stream *s;
+
+	spin_lock_irq(&bus->reg_lock);
+	list_for_each_entry(s, &bus->stream_list, list) {
+		struct azx_dev *azx_dev = stream_to_azx_dev(s);
+
+		azx_dev->irq_pending = 0;
+	}
+	spin_unlock_irq(&bus->reg_lock);
+}
+
+static int azx_acquire_irq(struct azx *chip, int do_disconnect)
+{
+	struct hdac_bus *bus = azx_bus(chip);
+
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+	struct platform_device *pdev = to_platform_device(hda->dev);
+	int irq_id = platform_get_irq(pdev, 0);
+	int err;
+
+	err = request_irq(irq_id, azx_interrupt,
+			     IRQF_SHARED, KBUILD_MODNAME, chip);
+	if (err) {
+		dev_err(chip->card->dev,
+			"unable to request IRQ %d, disabling device\n",
+			irq_id);
+		if (do_disconnect)
+			snd_card_disconnect(chip->card);
+		return err;
+	}
+	bus->irq = irq_id;
+
+	return 0;
+}
+
+/* get the current DMA position with correction on VIA chips */
+static unsigned int azx_via_get_position(struct azx *chip,
+					 struct azx_dev *azx_dev)
+{
+	unsigned int link_pos, mini_pos, bound_pos;
+	unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
+	unsigned int fifo_size;
+
+	link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
+	if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		/* Playback, no problem using link position */
+		return link_pos;
+	}
+
+	/* Capture */
+	/* For new chipset,
+	 * use mod to get the DMA position just like old chipset
+	 */
+	mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
+	mod_dma_pos %= azx_dev->core.period_bytes;
+
+	/* azx_dev->fifo_size can't get FIFO size of in stream.
+	 * Get from base address + offset.
+	 */
+	fifo_size = readw(azx_bus(chip)->remap_addr +
+			  VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
+
+	if (azx_dev->insufficient) {
+		/* Link position never gather than FIFO size */
+		if (link_pos <= fifo_size)
+			return 0;
+
+		azx_dev->insufficient = 0;
+	}
+
+	if (link_pos <= fifo_size)
+		mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
+	else
+		mini_pos = link_pos - fifo_size;
+
+	/* Find nearest previous boudary */
+	mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
+	mod_link_pos = link_pos % azx_dev->core.period_bytes;
+	if (mod_link_pos >= fifo_size)
+		bound_pos = link_pos - mod_link_pos;
+	else if (mod_dma_pos >= mod_mini_pos)
+		bound_pos = mini_pos - mod_mini_pos;
+	else {
+		bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
+		if (bound_pos >= azx_dev->core.bufsize)
+			bound_pos = 0;
+	}
+
+	/* Calculate real DMA position we want */
+	return bound_pos + mod_dma_pos;
+}
+
+#ifdef CONFIG_PM
+static DEFINE_MUTEX(card_list_lock);
+static LIST_HEAD(card_list);
+
+static void azx_add_card_list(struct azx *chip)
+{
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+
+	mutex_lock(&card_list_lock);
+	list_add(&hda->list, &card_list);
+	mutex_unlock(&card_list_lock);
+}
+
+static void azx_del_card_list(struct azx *chip)
+{
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+
+	mutex_lock(&card_list_lock);
+	list_del_init(&hda->list);
+	mutex_unlock(&card_list_lock);
+}
+
+#else
+#define azx_add_card_list(chip) /* NOP */
+#define azx_del_card_list(chip) /* NOP */
+#endif /* CONFIG_PM */
+
+#if defined(CONFIG_PM_SLEEP)
+/* power management */
+static int azx_suspend(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+	struct hda_ft *hda;
+	struct hdac_bus *bus;
+
+	if (!card)
+		return 0;
+
+	chip = card->private_data;
+	hda = container_of(chip, struct hda_ft, chip);
+	if (chip->disabled || !chip->running)
+		return 0;
+
+	bus = azx_bus(chip);
+	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
+	azx_clear_irq_pending(chip);
+	azx_stop_chip(chip);
+	if (bus->irq >= 0) {
+		free_irq(bus->irq, (void *)chip);
+		bus->irq = -1;
+	}
+
+	return 0;
+}
+
+static int azx_resume(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+	struct hda_ft *hda;
+	struct hdac_bus *bus;
+	int index;
+	struct snd_pcm_substream *substream;
+	struct azx_dev *azx_dev;
+	int err;
+
+	if (!card)
+		return 0;
+
+	chip = card->private_data;
+	hda = container_of(chip, struct hda_ft, chip);
+	bus = azx_bus(chip);
+	if (chip->disabled || !chip->running)
+		return 0;
+
+	if (azx_acquire_irq(chip, 1) < 0)
+		return -EIO;
+
+	index = chip->dev_index;
+
+	snd_hdac_bus_exit_link_reset(bus);
+	usleep_range(1000, 1200);
+
+	azx_init_chip(chip, 0);
+
+	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
+
+	if (hda->substream && hda->substream->runtime) {
+		substream = hda->substream;
+
+		if (substream->runtime->status->state == SNDRV_PCM_STATE_SUSPENDED) {
+			substream->runtime->status->state =
+				substream->runtime->status->suspended_state;
+			err = substream->ops->prepare(substream);
+			if (err < 0)
+				return err;
+		}
+
+		azx_dev = get_azx_dev(substream);
+		hda->substream = NULL;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+#ifdef CONFIG_PM
+static int azx_runtime_suspend(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+	struct hda_ft *hda;
+
+	if (!card)
+		return 0;
+
+	chip = card->private_data;
+	hda = container_of(chip, struct hda_ft, chip);
+	if (chip->disabled)
+		return 0;
+
+	if (!azx_has_pm_runtime(chip))
+		return 0;
+
+	azx_stop_chip(chip);
+	azx_enter_link_reset(chip);
+	azx_clear_irq_pending(chip);
+
+	return 0;
+}
+
+static int azx_runtime_resume(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+	struct hda_ft *hda;
+	struct hdac_bus *bus;
+	struct hda_codec *codec;
+	int status;
+	int index;
+
+	if (!card)
+		return 0;
+
+	chip = card->private_data;
+	hda = container_of(chip, struct hda_ft, chip);
+	bus = azx_bus(chip);
+	if (chip->disabled)
+		return 0;
+
+	if (!azx_has_pm_runtime(chip))
+		return 0;
+
+	/* Read STATESTS before controller reset */
+	status = azx_readw(chip, STATESTS);
+
+	index = chip->dev_index;
+
+	snd_hdac_bus_exit_link_reset(bus);
+	usleep_range(1000, 1200);
+
+	azx_init_chip(chip, 0);
+
+	if (status) {
+		list_for_each_codec(codec, &chip->bus)
+			if (status & (1 << codec->addr))
+				schedule_delayed_work(&codec->jackpoll_work,
+						      codec->jackpoll_interval);
+	}
+
+	return 0;
+}
+
+static int azx_runtime_idle(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+	struct hda_ft *hda;
+
+	if (!card)
+		return 0;
+
+	chip = card->private_data;
+	hda = container_of(chip, struct hda_ft, chip);
+	if (chip->disabled)
+		return 0;
+
+	if (!azx_has_pm_runtime(chip) ||
+	    azx_bus(chip)->codec_powered || !chip->running)
+		return -EBUSY;
+
+	return 0;
+}
+
+static const struct dev_pm_ops azx_pm = {
+	SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
+	SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
+};
+
+#define hda_ft_pm	(&azx_pm)
+#else
+#define hda_ft_pm	NULL
+#endif /* CONFIG_PM */
+
+static int azx_probe_continue(struct azx *chip);
+
+/*
+ * destructor
+ */
+static int azx_free(struct azx *chip)
+{
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+	struct hdac_bus *bus = azx_bus(chip);
+	struct platform_device *pdev = to_platform_device(hda->dev);
+	struct device *hddev = hda->dev;
+	struct resource *res;
+	resource_size_t size;
+
+	if (azx_has_pm_runtime(chip) && chip->running)
+		pm_runtime_get_noresume(&pdev->dev);
+
+	azx_del_card_list(chip);
+
+	complete_all(&hda->probe_wait);
+
+	if (bus->chip_init) {
+		azx_clear_irq_pending(chip);
+		azx_stop_all_streams(chip);
+		azx_stop_chip(chip);
+	}
+
+	if (bus->irq >= 0) {
+		free_irq(bus->irq, (void*)chip);
+		bus->irq = -1;
+	}
+
+	devm_iounmap(hddev, bus->remap_addr);
+
+	azx_free_stream_pages(chip);
+	azx_free_streams(chip);
+	snd_hdac_bus_exit(bus);
+
+	if (chip->region_requested){
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		size = resource_size(res);
+		devm_release_mem_region(hddev, res->start, size);
+	}
+
+	return 0;
+}
+
+static int azx_dev_disconnect(struct snd_device *device)
+{
+	struct azx *chip = device->device_data;
+
+	chip->bus.shutdown = 1;
+	return 0;
+}
+
+static int azx_dev_free(struct snd_device *device)
+{
+	return azx_free(device->device_data);
+}
+
+static int check_position_fix(struct azx *chip, int fix)
+{
+	switch (fix) {
+	case POS_FIX_AUTO:
+	case POS_FIX_LPIB:
+	case POS_FIX_POSBUF:
+	case POS_FIX_VIACOMBO:
+	case POS_FIX_COMBO:
+		return fix;
+	}
+
+	if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
+		dev_dbg(chip->card->dev, "Using LPIB position fix\n");
+		return POS_FIX_LPIB;
+	}
+	return POS_FIX_AUTO;
+}
+
+static void assign_position_fix(struct azx *chip, int fix)
+{
+	static azx_get_pos_callback_t callbacks[] = {
+		[POS_FIX_AUTO] = NULL,
+		[POS_FIX_LPIB] = azx_get_pos_lpib,
+		[POS_FIX_POSBUF] = azx_get_pos_posbuf,
+		[POS_FIX_VIACOMBO] = azx_via_get_position,
+		[POS_FIX_COMBO] = azx_get_pos_lpib,
+	};
+
+	chip->get_position[0] = chip->get_position[1] = callbacks[fix];
+
+	/* combo mode uses LPIB only for playback */
+	if (fix == POS_FIX_COMBO)
+		chip->get_position[1] = NULL;
+
+	if (fix == POS_FIX_POSBUF &&
+	    (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
+		chip->get_delay[0] = chip->get_delay[1] =
+			azx_get_delay_from_lpib;
+	}
+
+}
+
+#define AZX_FORCE_CODEC_MASK	0x100
+
+static void check_probe_mask(struct azx *chip, int dev)
+{
+	chip->codec_probe_mask = probe_mask[dev];
+
+	/* check forced option */
+	if (chip->codec_probe_mask != -1 &&
+	    (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
+		azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
+		dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
+			 (int)azx_bus(chip)->codec_mask);
+	}
+}
+
+static void azx_probe_work(struct work_struct *work)
+{
+	struct hda_ft *hda = container_of(work, struct hda_ft, probe_work);
+
+	azx_probe_continue(&hda->chip);
+}
+
+/*
+ * constructor
+ */
+static const struct hda_controller_ops axi_hda_ops;
+
+static int hda_ft_create(struct snd_card *card, struct platform_device *pdev,
+			int dev, unsigned int driver_caps,
+			struct azx **rchip)
+{
+	static struct snd_device_ops ops = {
+		.dev_disconnect = azx_dev_disconnect,
+		.dev_free = azx_dev_free,
+	};
+	struct hda_ft *hda;
+	struct azx *chip;
+	int err;
+
+	*rchip = NULL;
+
+	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
+	if (!hda)
+		return -ENOMEM;
+	hda->dev = &pdev->dev;
+	chip = &hda->chip;
+	mutex_init(&chip->open_mutex);
+	chip->card = card;
+	chip->ops = &axi_hda_ops;
+	chip->driver_caps = driver_caps;
+	chip->driver_type = driver_caps & 0xff;
+	chip->dev_index = dev;
+	if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
+		chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
+	INIT_LIST_HEAD(&chip->pcm_list);
+	INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
+	INIT_LIST_HEAD(&hda->list);
+
+	init_completion(&hda->probe_wait);
+	assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
+	check_probe_mask(chip, dev);
+
+	if (single_cmd < 0) /* allow fallback to single_cmd at errors */
+		chip->fallback_to_single_cmd = 0;
+	else /* explicitly set to single_cmd or not */
+		chip->single_cmd = single_cmd;
+
+	if (bdl_pos_adj[dev] < 0) {
+		switch (chip->driver_type) {
+		case AZX_DRIVER_FT:
+			bdl_pos_adj[dev] = 32;
+			break;
+		default:
+			bdl_pos_adj[dev] = 32;
+			break;
+		}
+	}
+	chip->bdl_pos_adj = bdl_pos_adj[dev];
+
+	err = azx_bus_init(chip, model[dev]);
+	if (err < 0) {
+		return err;
+	}
+
+	chip->bus.core.aligned_mmio = 1;
+
+	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
+	if (err < 0) {
+		dev_err(card->dev, "Error creating device [card]!\n");
+		azx_free(chip);
+		return err;
+	}
+
+	/* continue probing in work context as may trigger request module */
+	INIT_WORK(&hda->probe_work, azx_probe_work);
+
+	*rchip = chip;
+
+	return 0;
+}
+
+static int azx_first_init(struct azx *chip)
+{
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+	struct platform_device *pdev = to_platform_device(hda->dev);
+	struct device *hddev = hda->dev;
+
+	int dev = chip->dev_index;
+	bool full_reset;
+
+	struct snd_card *card = chip->card;
+	struct hdac_bus *bus = azx_bus(chip);
+	int err;
+	unsigned short gcap;
+	unsigned int dma_bits = 64;
+
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hda->regs = devm_ioremap_resource(hddev, res);
+	if (IS_ERR(hda->regs))
+		return PTR_ERR(hda->regs);
+	chip->region_requested = 1;
+
+	bus->addr = res->start;
+	bus->remap_addr = hda->regs;
+	if (bus->remap_addr == NULL) {
+		dev_err(card->dev, "ioremap error\n");
+		return -ENXIO;
+	}
+
+	bus->cmd_resend = 1;
+
+	synchronize_irq(bus->irq);
+
+	gcap = azx_readw(chip, GCAP);
+	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
+
+	/* disable 64bit DMA address on some devices */
+	if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
+		dev_dbg(card->dev, "Disabling 64bit DMA\n");
+		gcap &= ~AZX_GCAP_64OK;
+	}
+
+	/* disable buffer size rounding to 128-byte multiples if supported */
+	if (align_buffer_size >= 0)
+		chip->align_buffer_size = !!align_buffer_size;
+	else {
+		if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
+			chip->align_buffer_size = 0;
+		else
+			chip->align_buffer_size = 1;
+	}
+
+	err = hda_ft_dma_configure(hddev);
+	if (err < 0)
+		return err;
+
+	/* allow 64bit DMA address if supported by H/W */
+	if (!(gcap & AZX_GCAP_64OK))
+		dma_bits = 32;
+	if (!dma_set_mask(hddev, DMA_BIT_MASK(dma_bits))) {
+		dma_set_coherent_mask(hddev, DMA_BIT_MASK(dma_bits));
+	} else {
+		dma_set_mask(hddev, DMA_BIT_MASK(32));
+		dma_set_coherent_mask(hddev, DMA_BIT_MASK(32));
+	}
+
+	/* read number of streams from GCAP register instead of using
+	 * hardcoded value
+	 */
+	chip->capture_streams = (gcap >> 8) & 0x0f;
+	chip->playback_streams = (gcap >> 12) & 0x0f;
+	if (!chip->playback_streams && !chip->capture_streams) {
+		/* gcap didn't give any info, switching to old method */
+		chip->playback_streams = FT4C_NUM_PLAYBACK;
+		chip->capture_streams  = FT4C_NUM_CAPTURE;
+	}
+	chip->capture_index_offset = 0;
+	chip->playback_index_offset = chip->capture_streams;
+	chip->num_streams = chip->playback_streams + chip->capture_streams;
+
+	/* initialize streams */
+	err = azx_init_streams(chip);
+	if (err < 0)
+		return err;
+
+	err = azx_alloc_stream_pages(chip);
+	if (err < 0)
+		return err;
+
+	full_reset = (probe_only[dev] & 2) ? false : true;
+	azx_init_chip(chip, full_reset);
+
+	/* codec detection */
+	if (!azx_bus(chip)->codec_mask) {
+		dev_err(card->dev, "no codecs found!\n");
+		return -ENODEV;
+	}
+
+	if (azx_acquire_irq(chip, 0) < 0)
+		return -EBUSY;
+
+	strcpy(card->driver, "ft-hda");
+	strcpy(card->shortname, "ft-hda");
+	snprintf(card->longname, sizeof(card->longname),
+		 "%s at 0x%lx irq %i",
+		 card->shortname, bus->addr, bus->irq);
+
+	return 0;
+}
+
+static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
+			     struct vm_area_struct *area)
+{
+
+}
+
+static const struct hda_controller_ops axi_hda_ops = {
+	.pcm_mmap_prepare = pcm_mmap_prepare,
+	.position_check = azx_position_check,
+	.link_power = azx_ft_link_power,
+};
+
+static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
+
+static int hda_ft_probe(struct platform_device *pdev)
+{
+	const unsigned int driver_flags = AZX_DRIVER_FT;
+	struct snd_card *card;
+	struct hda_ft *hda;
+	struct azx *chip;
+	bool schedule_probe;
+	int err;
+	int dev;
+
+	dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
+
+	if (dev >= SNDRV_CARDS)
+		return -ENODEV;
+	if (!enable[dev]) {
+		set_bit(dev, probed_devs);
+		return -ENOENT;
+	}
+
+	err = snd_card_new(&pdev->dev, index[dev], id[dev], THIS_MODULE,
+			   0, &card);
+	if (err < 0) {
+		dev_err(&pdev->dev, "Error creating card!\n");
+		return err;
+	}
+
+	err = hda_ft_create(card, pdev,dev, driver_flags, &chip);
+	if (err < 0)
+		goto out_free;
+	card->private_data = chip;
+	hda = container_of(chip, struct hda_ft, chip);
+
+	dev_set_drvdata(&pdev->dev, card);
+
+	schedule_probe = !chip->disabled;
+
+	if (schedule_probe)
+		schedule_work(&hda->probe_work);
+
+	set_bit(dev, probed_devs);
+	if (chip->disabled)
+		complete_all(&hda->probe_wait);
+	return 0;
+
+out_free:
+	snd_card_free(card);
+	return err;
+}
+
+/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
+static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
+	[AZX_DRIVER_FT] = 4,
+};
+
+static int azx_probe_continue(struct azx *chip)
+{
+	struct hda_ft *hda = container_of(chip, struct hda_ft, chip);
+	struct device *hddev = hda->dev;
+	int dev = chip->dev_index;
+	int err;
+	struct hdac_bus *bus = azx_bus(chip);
+
+	hda->probe_continued = 1;
+
+	err = azx_first_init(chip);
+	if (err < 0)
+		goto out_free;
+
+#ifdef CONFIG_SND_HDA_INPUT_BEEP
+	chip->beep_mode = beep_mode[dev];
+#endif
+
+	/* create codec instances */
+	err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
+	if (err < 0)
+		goto out_free;
+
+	if ((probe_only[dev] & 1) == 0) {
+		err = azx_codec_configure(chip);
+		if (err < 0)
+			goto out_free;
+	}
+
+	err = snd_card_register(chip->card);
+	if (err < 0)
+		goto out_free;
+
+	chip->running = 1;
+	azx_add_card_list(chip);
+	snd_hda_set_power_save(&chip->bus, power_save * 1000);
+
+	if (azx_has_pm_runtime(chip))
+			pm_runtime_put_noidle(hddev);
+	return err;
+
+out_free:
+	if (bus->irq >= 0) {
+		free_irq(bus->irq, (void *)chip);
+		bus->irq = -1;
+	}
+	return err;
+}
+
+static int hda_ft_remove(struct platform_device *pdev)
+{
+	struct snd_card *card = dev_get_drvdata(&pdev->dev);
+	struct azx *chip;
+	struct hda_ft *hda;
+
+	if (card) {
+		/* cancel the pending probing work */
+		chip = card->private_data;
+		hda = container_of(chip, struct hda_ft, chip);
+		cancel_work_sync(&hda->probe_work);
+		clear_bit(chip->dev_index, probed_devs);
+
+		snd_card_free(card);
+		return 0;
+	}
+	return 0;
+}
+
+static void hda_ft_shutdown(struct platform_device *pdev)
+{
+	struct snd_card *card = dev_get_drvdata(&pdev->dev);
+	struct azx *chip;
+
+	if (!card)
+		return;
+	chip = card->private_data;
+	if (chip && chip->running)
+		azx_stop_chip(chip);
+}
+
+static const struct of_device_id hda_ft_of_match[] = {
+	{ .compatible = "phytium,hda" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, hda_ft_of_match);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id hda_ft_acpi_match[] = {
+	{ .id = "PHYT0006" },
+	{}
+};
+MODULE_DEVICE_TABLE(acpi, hda_ft_acpi_match);
+#else
+#define hda_ft_acpi_match NULL
+#endif
+
+static struct platform_driver ft_platform_hda = {
+	.driver = {
+		.name = "ft-hda",
+		.pm = hda_ft_pm,
+		.of_match_table = hda_ft_of_match,
+		.acpi_match_table = hda_ft_acpi_match,
+	},
+	.probe = hda_ft_probe,
+	.remove = hda_ft_remove,
+	.shutdown = hda_ft_shutdown,
+};
+
+module_platform_driver(ft_platform_hda);
+
+MODULE_DESCRIPTION("FT HDA bus driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/phytium/files-5.10/sound/pci/hda/hda_phytium.h b/target/linux/phytium/files-5.10/sound/pci/hda/hda_phytium.h
new file mode 100644
index 00000000000000..edca12ec6fa7e3
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/pci/hda/hda_phytium.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Implementation of primary ALSA driver code base for Phytium HD Audio.
+ *
+ * Copyright (c) 2018-2023 Phytium Technology Co., Ltd.
+ */
+#ifndef __SOUND_HDA_PHYTIUM_H__
+#define __SOUND_HDA_PHYTIUM_H__
+
+#include "hda_controller.h"
+
+struct hda_ft {
+	struct azx chip;
+	struct snd_pcm_substream *substream;
+	struct device *dev;
+	void __iomem *regs;
+
+	/* for pending irqs */
+	struct work_struct irq_pending_work;
+
+	/* sync probing */
+	struct completion probe_wait;
+	struct work_struct probe_work;
+
+	/* card list (for power_save trigger) */
+	struct list_head list;
+
+	/* extra flags */
+	unsigned int irq_pending_warned:1;
+	unsigned int probe_continued:1;
+
+};
+
+#endif
diff --git a/target/linux/phytium/files-5.10/sound/soc/codecs/es8336.c b/target/linux/phytium/files-5.10/sound/soc/codecs/es8336.c
new file mode 100644
index 00000000000000..719b7de0e37bc3
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/codecs/es8336.c
@@ -0,0 +1,1081 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * es8336.c -- es8336 ALSA SoC audio driver
+ * Copyright Everest Semiconductor Co.,Ltd
+ *           Phytium Information Technology Co.,Ltd
+ *
+ * Author: David Yang <yangxiaohua@everest-semi.com>
+ *         Yiqun Zhang <zhangyiqun@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/of_gpio.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/tlv.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <linux/proc_fs.h>
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/regmap.h>
+#include "es8336.h"
+
+static struct snd_soc_component *es8336_component;
+
+static const struct reg_default es8336_reg_defaults[] = {
+	{0x00, 0x03}, {0x01, 0x03}, {0x02, 0x00}, {0x03, 0x20},
+	{0x04, 0x11}, {0x05, 0x00}, {0x06, 0x11}, {0x07, 0x00},
+	{0x08, 0x00}, {0x09, 0x01}, {0x0a, 0x00}, {0x0b, 0x00},
+	{0x0c, 0xf8}, {0x0d, 0x3f}, {0x0e, 0x00}, {0x0f, 0x00},
+	{0x10, 0x01}, {0x11, 0xfc}, {0x12, 0x28}, {0x13, 0x00},
+	{0x14, 0x00}, {0x15, 0x33}, {0x16, 0x00}, {0x17, 0x00},
+	{0x18, 0x88}, {0x19, 0x06}, {0x1a, 0x22}, {0x1b, 0x03},
+	{0x1c, 0x0f}, {0x1d, 0x00}, {0x1e, 0x80}, {0x1f, 0x80},
+	{0x20, 0x00}, {0x21, 0x00}, {0x22, 0xc0}, {0x23, 0x00},
+	{0x24, 0x01}, {0x25, 0x08}, {0x26, 0x10}, {0x27, 0xc0},
+	{0x28, 0x00}, {0x29, 0x1c}, {0x2a, 0x00}, {0x2b, 0xb0},
+	{0x2c, 0x32}, {0x2d, 0x03}, {0x2e, 0x00}, {0x2f, 0x11},
+	{0x30, 0x10}, {0x31, 0x00}, {0x32, 0x00}, {0x33, 0xc0},
+	{0x34, 0xc0}, {0x35, 0x1f}, {0x36, 0xf7}, {0x37, 0xfd},
+	{0x38, 0xff}, {0x39, 0x1f}, {0x3a, 0xf7}, {0x3b, 0xfd},
+	{0x3c, 0xff}, {0x3d, 0x1f}, {0x3e, 0xf7}, {0x3f, 0xfd},
+	{0x40, 0xff}, {0x41, 0x1f}, {0x42, 0xf7}, {0x43, 0xfd},
+	{0x44, 0xff}, {0x45, 0x1f}, {0x46, 0xf7}, {0x47, 0xfd},
+	{0x48, 0xff}, {0x49, 0x1f}, {0x4a, 0xf7}, {0x4b, 0xfd},
+	{0x4c, 0xff}, {0x4d, 0x00}, {0x4e, 0x00}, {0x4f, 0xff},
+	{0x50, 0x00}, {0x51, 0x00}, {0x52, 0x00}, {0x53, 0x00},
+};
+
+/* codec private data */
+struct es8336_priv {
+	struct regmap *regmap;
+	unsigned int dmic_amic;
+	unsigned int sysclk;
+	struct snd_pcm_hw_constraint_list *sysclk_constraints;
+	struct clk *mclk;
+	int debounce_time;
+	struct delayed_work work;
+
+	struct gpio_desc *spk_ctl_gpio;
+	struct gpio_desc *hp_det_gpio;
+	bool muted;
+	bool hp_inserted;
+
+	u8 mic_src;
+	int pwr_count;
+};
+
+/*
+ * es8336_reset
+ * write value 0xff to reg0x00, the chip will be in reset mode
+ * then, writer 0x00 to reg0x00, unreset the chip
+ */
+static int es8336_reset(struct snd_soc_component *component)
+{
+	snd_soc_component_write(component, ES8336_RESET_REG00, 0x3F);
+	usleep_range(5000, 5500);
+	return snd_soc_component_write(component, ES8336_RESET_REG00, 0x03);
+}
+
+static void es8336_enable_spk(struct es8336_priv *es8336, bool enable)
+{
+	gpiod_set_value(es8336->spk_ctl_gpio, enable);
+}
+
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9600, 50, 1);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -9600, 50, 1);
+static const DECLARE_TLV_DB_SCALE(hpmixer_gain_tlv, -1200, 150, 0);
+static const DECLARE_TLV_DB_SCALE(mic_bst_tlv, 0, 1200, 0);
+
+static unsigned int linin_pga_tlv[] = {
+	TLV_DB_RANGE_HEAD(9),
+	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+	1, 1, TLV_DB_SCALE_ITEM(300, 0, 0),
+	2, 2, TLV_DB_SCALE_ITEM(600, 0, 0),
+	3, 3, TLV_DB_SCALE_ITEM(900, 0, 0),
+	4, 4, TLV_DB_SCALE_ITEM(1200, 0, 0),
+	5, 5, TLV_DB_SCALE_ITEM(1500, 0, 0),
+	6, 6, TLV_DB_SCALE_ITEM(1800, 0, 0),
+	7, 7, TLV_DB_SCALE_ITEM(2100, 0, 0),
+	8, 8, TLV_DB_SCALE_ITEM(2400, 0, 0),
+};
+
+static unsigned int hpout_vol_tlv[] = {
+	TLV_DB_RANGE_HEAD(1),
+	0, 3, TLV_DB_SCALE_ITEM(-4800, 1200, 0),
+};
+
+static const char *const alc_func_txt[] = { "Off", "On" };
+
+static const struct soc_enum alc_func =
+	SOC_ENUM_SINGLE(ES8336_ADC_ALC1_REG29, 6, 2, alc_func_txt);
+
+static const char *const ng_type_txt[] = {
+	"Constant PGA Gain", "Mute ADC Output" };
+
+static const struct soc_enum ng_type =
+	SOC_ENUM_SINGLE(ES8336_ADC_ALC6_REG2E, 6, 2, ng_type_txt);
+
+static const char *const adcpol_txt[] = { "Normal", "Invert" };
+
+static const struct soc_enum adcpol =
+	SOC_ENUM_SINGLE(ES8336_ADC_MUTE_REG26, 1, 2, adcpol_txt);
+
+static const char *const dacpol_txt[] = {
+	"Normal", "R Invert", "L Invert", "L + R Invert" };
+
+static const struct soc_enum dacpol =
+	SOC_ENUM_SINGLE(ES8336_DAC_SET1_REG30, 0, 4, dacpol_txt);
+
+static const struct snd_kcontrol_new es8336_snd_controls[] = {
+	/* HP OUT VOLUME */
+	SOC_DOUBLE_TLV("HP Playback Volume", ES8336_CPHP_ICAL_VOL_REG18,
+		       4, 0, 4, 1, hpout_vol_tlv),
+	/* HPMIXER VOLUME Control */
+	SOC_DOUBLE_TLV("HPMixer Gain", ES8336_HPMIX_VOL_REG16,
+		       0, 4, 7, 0, hpmixer_gain_tlv),
+
+	/* DAC Digital controls */
+	SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8336_DAC_VOLL_REG33,
+			 ES8336_DAC_VOLR_REG34, 0, 0xC0, 1, dac_vol_tlv),
+
+	SOC_SINGLE("Enable DAC Soft Ramp", ES8336_DAC_SET1_REG30, 4, 1, 1),
+	SOC_SINGLE("DAC Soft Ramp Rate", ES8336_DAC_SET1_REG30, 2, 4, 0),
+
+	SOC_ENUM("Playback Polarity", dacpol),
+	SOC_SINGLE("DAC Notch Filter", ES8336_DAC_SET2_REG31, 6, 1, 0),
+	SOC_SINGLE("DAC Double Fs Mode", ES8336_DAC_SET2_REG31, 7, 1, 0),
+	SOC_SINGLE("DAC Volume Control-LeR", ES8336_DAC_SET2_REG31, 2, 1, 0),
+	SOC_SINGLE("DAC Stereo Enhancement", ES8336_DAC_SET3_REG32, 0, 7, 0),
+
+	/* +20dB D2SE PGA Control */
+	SOC_SINGLE_TLV("MIC Boost", ES8336_ADC_D2SEPGA_REG24,
+		       0, 1, 0, mic_bst_tlv),
+	/* 0-+24dB Lineinput PGA Control */
+	SOC_SINGLE_TLV("Input PGA", ES8336_ADC_PGAGAIN_REG23,
+		       4, 8, 0, linin_pga_tlv),
+};
+
+/* Analog Input MUX */
+static const char * const es8336_analog_in_txt[] = {
+	"lin1-rin1",
+	"lin2-rin2",
+	"lin1-rin1 with 15db Boost",
+	"lin2-rin2 with 15db Boost"
+};
+
+static const unsigned int es8336_analog_in_values[] = { 0, 1, 2, 3 };
+
+static const struct soc_enum es8336_analog_input_enum =
+	SOC_VALUE_ENUM_SINGLE(ES8336_ADC_PDN_LINSEL_REG22, 4, 3,
+			      ARRAY_SIZE(es8336_analog_in_txt),
+			      es8336_analog_in_txt,
+			      es8336_analog_in_values);
+
+static const struct snd_kcontrol_new es8336_analog_in_mux_controls =
+	SOC_DAPM_ENUM("Route", es8336_analog_input_enum);
+
+/* Dmic MUX */
+static const char * const es8336_dmic_txt[] = {
+	"dmic disable",
+	"dmic data at high level",
+	"dmic data at low level",
+};
+
+static const unsigned int es8336_dmic_values[] = { 0, 2, 3 };
+
+static const struct soc_enum es8336_dmic_src_enum =
+	SOC_VALUE_ENUM_SINGLE(ES8336_ADC_DMIC_REG25, 0, 3,
+			      ARRAY_SIZE(es8336_dmic_txt),
+			      es8336_dmic_txt,
+			      es8336_dmic_values);
+
+static const struct snd_kcontrol_new es8336_dmic_src_controls =
+	SOC_DAPM_ENUM("Route", es8336_dmic_src_enum);
+
+/* hp mixer mux */
+static const char *const es8336_hpmux_texts[] = {
+	"lin1-rin1",
+	"lin2-rin2",
+	"lin-rin with Boost",
+	"lin-rin with Boost and PGA"
+};
+
+static const unsigned int es8336_hpmux_values[] = { 0, 1, 2, 3 };
+
+static const struct soc_enum es8336_left_hpmux_enum =
+	SOC_VALUE_ENUM_SINGLE(ES8336_HPMIX_SEL_REG13, 4, 7,
+			      ARRAY_SIZE(es8336_hpmux_texts),
+			      es8336_hpmux_texts,
+			      es8336_hpmux_values);
+
+static const struct snd_kcontrol_new es8336_left_hpmux_controls =
+	SOC_DAPM_ENUM("Route", es8336_left_hpmux_enum);
+
+static const struct soc_enum es8336_right_hpmux_enum =
+	SOC_VALUE_ENUM_SINGLE(ES8336_HPMIX_SEL_REG13, 0, 7,
+			      ARRAY_SIZE(es8336_hpmux_texts),
+			      es8336_hpmux_texts,
+			      es8336_hpmux_values);
+
+static const struct snd_kcontrol_new es8336_right_hpmux_controls =
+	SOC_DAPM_ENUM("Route", es8336_right_hpmux_enum);
+
+/* headphone Output Mixer */
+static const struct snd_kcontrol_new es8336_out_left_mix[] = {
+	SOC_DAPM_SINGLE("LLIN Switch", ES8336_HPMIX_SWITCH_REG14,
+			6, 1, 0),
+	SOC_DAPM_SINGLE("Left DAC Switch", ES8336_HPMIX_SWITCH_REG14,
+			7, 1, 0),
+};
+
+static const struct snd_kcontrol_new es8336_out_right_mix[] = {
+	SOC_DAPM_SINGLE("RLIN Switch", ES8336_HPMIX_SWITCH_REG14,
+			2, 1, 0),
+	SOC_DAPM_SINGLE("Right DAC Switch", ES8336_HPMIX_SWITCH_REG14,
+			3, 1, 0),
+};
+
+/* DAC data source mux */
+static const char * const es8336_dacsrc_texts[] = {
+	"LDATA TO LDAC, RDATA TO RDAC",
+	"LDATA TO LDAC, LDATA TO RDAC",
+	"RDATA TO LDAC, RDATA TO RDAC",
+	"RDATA TO LDAC, LDATA TO RDAC",
+};
+
+static const unsigned int es8336_dacsrc_values[] = { 0, 1, 2, 3 };
+
+static const struct soc_enum es8336_dacsrc_mux_enum =
+	SOC_VALUE_ENUM_SINGLE(ES8336_DAC_SET1_REG30, 6, 4,
+			      ARRAY_SIZE(es8336_dacsrc_texts),
+			      es8336_dacsrc_texts,
+			      es8336_dacsrc_values);
+static const struct snd_kcontrol_new es8336_dacsrc_mux_controls =
+	SOC_DAPM_ENUM("Route", es8336_dacsrc_mux_enum);
+
+static const struct snd_soc_dapm_widget es8336_dapm_widgets[] = {
+	/* Input Lines */
+	SND_SOC_DAPM_INPUT("DMIC"),
+	SND_SOC_DAPM_INPUT("MIC1"),
+	SND_SOC_DAPM_INPUT("MIC2"),
+
+	SND_SOC_DAPM_MICBIAS("micbias", SND_SOC_NOPM,
+			     0, 0),
+	/* Input MUX */
+	SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
+			 &es8336_analog_in_mux_controls),
+
+	SND_SOC_DAPM_PGA("Line input PGA", ES8336_ADC_PDN_LINSEL_REG22,
+			 7, 1, NULL, 0),
+
+	/* ADCs */
+	SND_SOC_DAPM_ADC("Mono ADC", NULL, ES8336_ADC_PDN_LINSEL_REG22, 6, 1),
+
+	/* Dmic MUX */
+	SND_SOC_DAPM_MUX("Digital Mic Mux", SND_SOC_NOPM, 0, 0,
+			 &es8336_dmic_src_controls),
+
+	/* Digital Interface */
+	SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture",  1,
+			     SND_SOC_NOPM, 0, 0),
+
+	SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0,
+			    SND_SOC_NOPM, 0, 0),
+
+	/*  DACs DATA SRC MUX */
+	SND_SOC_DAPM_MUX("DAC SRC Mux", SND_SOC_NOPM, 0, 0,
+			 &es8336_dacsrc_mux_controls),
+	/*  DACs  */
+	SND_SOC_DAPM_DAC("Right DAC", NULL, ES8336_DAC_PDN_REG2F, 0, 1),
+	SND_SOC_DAPM_DAC("Left DAC", NULL, ES8336_DAC_PDN_REG2F, 4, 1),
+
+	/* Headphone Output Side */
+	/* hpmux for hp mixer */
+	SND_SOC_DAPM_MUX("Left Hp mux", SND_SOC_NOPM, 0, 0,
+			 &es8336_left_hpmux_controls),
+	SND_SOC_DAPM_MUX("Right Hp mux", SND_SOC_NOPM, 0, 0,
+			 &es8336_right_hpmux_controls),
+	/* Output mixer  */
+	SND_SOC_DAPM_MIXER("Left Hp mixer", ES8336_HPMIX_PDN_REG15,
+			   4, 1, &es8336_out_left_mix[0],
+			   ARRAY_SIZE(es8336_out_left_mix)),
+	SND_SOC_DAPM_MIXER("Right Hp mixer", ES8336_HPMIX_PDN_REG15,
+			   0, 1, &es8336_out_right_mix[0],
+			   ARRAY_SIZE(es8336_out_right_mix)),
+	SND_SOC_DAPM_MIXER("Left Hp mixer2", SND_SOC_NOPM,
+			   4, 1, &es8336_out_left_mix[0],
+			   ARRAY_SIZE(es8336_out_left_mix)),
+	SND_SOC_DAPM_MIXER("Right Hp mixer2", SND_SOC_NOPM,
+			   0, 1, &es8336_out_right_mix[0],
+			   ARRAY_SIZE(es8336_out_right_mix)),
+
+	/* Output charge pump */
+	SND_SOC_DAPM_PGA("HPCP L", ES8336_CPHP_OUTEN_REG17,
+			 6, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("HPCP R", ES8336_CPHP_OUTEN_REG17,
+			 2, 0, NULL, 0),
+
+	/* Output Driver */
+	SND_SOC_DAPM_PGA("HPVOL L", ES8336_CPHP_OUTEN_REG17,
+			 5, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("HPVOL R", ES8336_CPHP_OUTEN_REG17,
+			 1, 0, NULL, 0),
+	/* Output Lines */
+	SND_SOC_DAPM_OUTPUT("HPOL"),
+	SND_SOC_DAPM_OUTPUT("HPOR"),
+};
+
+static const struct snd_soc_dapm_route es8336_dapm_routes[] = {
+	/*
+	 * record route map
+	 */
+	{"MIC1", NULL, "micbias"},
+	{"MIC2", NULL, "micbias"},
+	{"DMIC", NULL, "micbias"},
+
+	{"Differential Mux", "lin1-rin1", "MIC1"},
+	{"Differential Mux", "lin2-rin2", "MIC2"},
+	{"Differential Mux", "lin1-rin1 with 15db Boost", "MIC1"},
+	{"Differential Mux", "lin2-rin2 with 15db Boost", "MIC2"},
+	{"Line input PGA", NULL, "Differential Mux"},
+
+	{"Mono ADC", NULL, "Line input PGA"},
+
+	{"Digital Mic Mux", "dmic disable", "Mono ADC"},
+	{"Digital Mic Mux", "dmic data at high level", "DMIC"},
+	{"Digital Mic Mux", "dmic data at low level", "DMIC"},
+
+	{"I2S OUT", NULL, "Digital Mic Mux"},
+	/*
+	 * playback route map
+	 */
+	{"DAC SRC Mux", "LDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
+	{"DAC SRC Mux", "LDATA TO LDAC, LDATA TO RDAC", "I2S IN"},
+	{"DAC SRC Mux", "RDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
+	{"DAC SRC Mux", "RDATA TO LDAC, LDATA TO RDAC", "I2S IN"},
+
+	{"Left DAC", NULL, "DAC SRC Mux"},
+	{"Right DAC", NULL, "DAC SRC Mux"},
+
+	{"Left Hp mux", "lin1-rin1", "MIC1"},
+	{"Left Hp mux", "lin2-rin2", "MIC2"},
+	{"Left Hp mux", "lin-rin with Boost", "Differential Mux"},
+	{"Left Hp mux", "lin-rin with Boost and PGA", "Line input PGA"},
+
+	{"Right Hp mux", "lin1-rin1", "MIC1"},
+	{"Right Hp mux", "lin2-rin2", "MIC2"},
+	{"Right Hp mux", "lin-rin with Boost", "Differential Mux"},
+	{"Right Hp mux", "lin-rin with Boost and PGA", "Line input PGA"},
+
+	{"Left Hp mixer", "LLIN Switch", "Left Hp mux"},
+	{"Left Hp mixer", "Left DAC Switch", "Left DAC"},
+
+	{"Right Hp mixer", "RLIN Switch", "Right Hp mux"},
+	{"Right Hp mixer", "Right DAC Switch", "Right DAC"},
+
+	{"HPCP L", NULL, "Left Hp mixer"},
+	{"HPCP R", NULL, "Right Hp mixer"},
+
+	{"HPVOL L", NULL, "HPCP L"},
+	{"HPVOL R", NULL, "HPCP R"},
+
+	{"HPOL", NULL, "HPVOL L"},
+	{"HPOR", NULL, "HPVOL R"},
+};
+
+
+/* The set of rates we can generate from the above for each SYSCLK */
+
+static unsigned int rates_12288[] = {
+	8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_12288 = {
+	.count	= ARRAY_SIZE(rates_12288),
+	.list	= rates_12288,
+};
+
+static unsigned int rates_112896[] = {
+	8000, 11025, 22050, 44100,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_112896 = {
+	.count	= ARRAY_SIZE(rates_112896),
+	.list	= rates_112896,
+};
+
+static unsigned int rates_12[] = {
+	8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
+	48000, 88235, 96000,
+};
+
+static struct snd_pcm_hw_constraint_list constraints_12 = {
+	.count	= ARRAY_SIZE(rates_12),
+	.list	= rates_12,
+};
+
+/*
+ * Note that this should be called from init rather than from hw_params.
+ */
+static int es8336_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+				 int clk_id, unsigned int freq, int dir)
+{
+	struct snd_soc_component *component = codec_dai->component;
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+
+	switch (freq) {
+	case 11289600:
+	case 18432000:
+	case 22579200:
+	case 36864000:
+		es8336->sysclk_constraints = &constraints_112896;
+		es8336->sysclk = freq;
+		return 0;
+	case 12288000:
+	case 19200000:
+	case 16934400:
+	case 24576000:
+	case 33868800:
+		es8336->sysclk_constraints = &constraints_12288;
+		es8336->sysclk = freq;
+		return 0;
+	case 12000000:
+	case 24000000:
+		es8336->sysclk_constraints = &constraints_12;
+		es8336->sysclk = freq;
+		return 0;
+	}
+
+	return 0;
+}
+
+static int es8336_set_dai_fmt(struct snd_soc_dai *codec_dai,
+			      unsigned int fmt)
+{
+	struct snd_soc_component *component = codec_dai->component;
+	u8 iface = 0;
+	u8 adciface = 0;
+	u8 daciface = 0;
+
+	iface    = snd_soc_component_read(component, ES8336_IFACE);
+	adciface = snd_soc_component_read(component, ES8336_ADC_IFACE);
+	daciface = snd_soc_component_read(component, ES8336_DAC_IFACE);
+
+	/* set master/slave audio interface */
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		iface |= 0x80;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		iface &= 0x7F;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* interface format */
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		adciface &= 0xFC;
+		daciface &= 0xFC;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		return -EINVAL;
+	case SND_SOC_DAIFMT_LEFT_J:
+		adciface &= 0xFC;
+		daciface &= 0xFC;
+		adciface |= 0x01;
+		daciface |= 0x01;
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		adciface &= 0xDC;
+		daciface &= 0xDC;
+		adciface |= 0x03;
+		daciface |= 0x03;
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		adciface &= 0xDC;
+		daciface &= 0xDC;
+		adciface |= 0x23;
+		daciface |= 0x23;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* clock inversion */
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		iface    &= 0xDF;
+		adciface &= 0xDF;
+		daciface &= 0xDF;
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		iface    |= 0x20;
+		adciface |= 0x20;
+		daciface |= 0x20;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		iface    |= 0x20;
+		adciface &= 0xDF;
+		daciface &= 0xDF;
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		iface    &= 0xDF;
+		adciface |= 0x20;
+		daciface |= 0x20;
+		break;
+	default:
+		return -EINVAL;
+	}
+	snd_soc_component_write(component, ES8336_IFACE, iface);
+	snd_soc_component_write(component, ES8336_ADC_IFACE, adciface);
+	snd_soc_component_write(component, ES8336_DAC_IFACE, daciface);
+	return 0;
+}
+
+static int es8336_pcm_startup(struct snd_pcm_substream *substream,
+			      struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *component = dai->component;
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+	bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+
+	snd_soc_component_write(component, ES8336_RESET_REG00, 0xC0);
+	snd_soc_component_write(component, ES8336_SYS_PDN_REG0D, 0x00);
+	/* es8336: both playback and capture need dac mclk */
+	snd_soc_component_update_bits(component, ES8336_CLKMGR_CLKSW_REG01,
+			    ES8336_CLKMGR_MCLK_DIV_MASK |
+			    ES8336_CLKMGR_DAC_MCLK_MASK,
+			    ES8336_CLKMGR_MCLK_DIV_NML |
+			    ES8336_CLKMGR_DAC_MCLK_EN);
+	es8336->pwr_count++;
+
+	if (playback) {
+		snd_soc_component_write(component, ES8336_SYS_LP1_REG0E, 0x3F);
+		snd_soc_component_write(component, ES8336_SYS_LP2_REG0F, 0x1F);
+		snd_soc_component_write(component, ES8336_HPMIX_SWITCH_REG14, 0x88);
+		snd_soc_component_write(component, ES8336_HPMIX_PDN_REG15, 0x00);
+		snd_soc_component_write(component, ES8336_HPMIX_VOL_REG16, 0xBB);
+		snd_soc_component_write(component, ES8336_CPHP_PDN2_REG1A, 0x10);
+		snd_soc_component_write(component, ES8336_CPHP_LDOCTL_REG1B, 0x30);
+		snd_soc_component_write(component, ES8336_CPHP_PDN1_REG19, 0x02);
+		snd_soc_component_write(component, ES8336_DAC_PDN_REG2F, 0x00);
+		snd_soc_component_write(component, ES8336_CPHP_OUTEN_REG17, 0x66);
+		snd_soc_component_update_bits(component, ES8336_CLKMGR_CLKSW_REG01,
+				    ES8336_CLKMGR_DAC_MCLK_MASK |
+				    ES8336_CLKMGR_DAC_ANALOG_MASK,
+				    ES8336_CLKMGR_DAC_MCLK_EN |
+				    ES8336_CLKMGR_DAC_ANALOG_EN);
+		msleep(50);
+	} else {
+		snd_soc_component_update_bits(component, ES8336_ADC_PDN_LINSEL_REG22, 0xC0, 0x00);
+		snd_soc_component_update_bits(component, ES8336_CLKMGR_CLKSW_REG01,
+				    ES8336_CLKMGR_ADC_MCLK_MASK |
+				    ES8336_CLKMGR_ADC_ANALOG_MASK,
+				    ES8336_CLKMGR_ADC_MCLK_EN |
+				    ES8336_CLKMGR_ADC_ANALOG_EN);
+	}
+
+	return 0;
+}
+
+static void es8336_pcm_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *component = dai->component;
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+	bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+
+	if (playback) {
+		snd_soc_component_write(component, ES8336_CPHP_OUTEN_REG17, 0x00);
+		snd_soc_component_write(component, ES8336_DAC_PDN_REG2F, 0x11);
+		snd_soc_component_write(component, ES8336_CPHP_LDOCTL_REG1B, 0x03);
+		snd_soc_component_write(component, ES8336_CPHP_PDN2_REG1A, 0x22);
+		snd_soc_component_write(component, ES8336_CPHP_PDN1_REG19, 0x06);
+		snd_soc_component_write(component, ES8336_HPMIX_SWITCH_REG14, 0x00);
+		snd_soc_component_write(component, ES8336_HPMIX_PDN_REG15, 0x33);
+		snd_soc_component_write(component, ES8336_HPMIX_VOL_REG16, 0x00);
+		snd_soc_component_write(component, ES8336_SYS_PDN_REG0D, 0x00);
+		snd_soc_component_write(component, ES8336_SYS_LP1_REG0E, 0xFF);
+		snd_soc_component_write(component, ES8336_SYS_LP2_REG0F, 0xFF);
+		snd_soc_component_update_bits(component, ES8336_CLKMGR_CLKSW_REG01,
+				    ES8336_CLKMGR_DAC_ANALOG_MASK,
+				    ES8336_CLKMGR_DAC_ANALOG_DIS);
+	} else {
+		snd_soc_component_update_bits(component, ES8336_ADC_PDN_LINSEL_REG22, 0xC0, 0xc0);
+		snd_soc_component_update_bits(component, ES8336_CLKMGR_CLKSW_REG01,
+				    ES8336_CLKMGR_ADC_MCLK_MASK |
+				    ES8336_CLKMGR_ADC_ANALOG_MASK,
+				    ES8336_CLKMGR_ADC_MCLK_DIS |
+				    ES8336_CLKMGR_ADC_ANALOG_DIS);
+	}
+
+	if (--es8336->pwr_count == 0) {
+		if (!es8336->hp_inserted)
+			snd_soc_component_write(component, ES8336_SYS_PDN_REG0D, 0x3F);
+		snd_soc_component_write(component, ES8336_CLKMGR_CLKSW_REG01, 0xF3);
+	}
+}
+
+
+static int es8336_pcm_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *component = dai->component;
+	int val = 0;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		val = ES8336_DACWL_16;
+		break;
+	case SNDRV_PCM_FORMAT_S20_3LE:
+		val = ES8336_DACWL_20;
+		break;
+	case SNDRV_PCM_FORMAT_S24_LE:
+		val = ES8336_DACWL_24;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		val = ES8336_DACWL_32;
+		break;
+	default:
+		val = ES8336_DACWL_16;
+		break;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		snd_soc_component_update_bits(component, ES8336_SDP_DACFMT_REG0B,
+				    ES8336_DACWL_MASK, val);
+	else
+		snd_soc_component_update_bits(component, ES8336_SDP_ADCFMT_REG0A,
+				    ES8336_ADCWL_MASK, val);
+
+	return 0;
+}
+
+static int es8336_mute(struct snd_soc_dai *dai, int mute, int direction)
+{
+	struct snd_soc_component *component = dai->component;
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+
+	es8336->muted = mute;
+
+	if (mute) {
+		es8336_enable_spk(es8336, false);
+		msleep(100);
+		snd_soc_component_write(component, ES8336_DAC_SET1_REG30, 0x20);
+	}
+
+	snd_soc_component_write(component, ES8336_DAC_SET1_REG30, 0x00);
+	msleep(130);
+
+	if (!es8336->hp_inserted)
+		es8336_enable_spk(es8336, true);
+
+	return 0;
+}
+
+static int es8336_set_bias_level(struct snd_soc_component *component,
+				 enum snd_soc_bias_level level)
+{
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		break;
+
+	case SND_SOC_BIAS_PREPARE:
+		break;
+
+	case SND_SOC_BIAS_STANDBY:
+		break;
+
+	case SND_SOC_BIAS_OFF:
+		snd_soc_component_write(component, ES8336_CPHP_OUTEN_REG17, 0x00);
+		snd_soc_component_write(component, ES8336_DAC_PDN_REG2F, 0x11);
+		snd_soc_component_write(component, ES8336_CPHP_LDOCTL_REG1B, 0x03);
+		snd_soc_component_write(component, ES8336_CPHP_PDN2_REG1A, 0x22);
+		snd_soc_component_write(component, ES8336_CPHP_PDN1_REG19, 0x06);
+		snd_soc_component_write(component, ES8336_HPMIX_SWITCH_REG14, 0x00);
+		snd_soc_component_write(component, ES8336_HPMIX_PDN_REG15, 0x33);
+		snd_soc_component_write(component, ES8336_HPMIX_VOL_REG16, 0x00);
+		snd_soc_component_update_bits(component, ES8336_ADC_PDN_LINSEL_REG22, 0xC0, 0xC0);
+		if (!es8336->hp_inserted)
+			snd_soc_component_write(component, ES8336_SYS_PDN_REG0D, 0x3F);
+		snd_soc_component_write(component, ES8336_SYS_LP1_REG0E, 0x3F);
+		snd_soc_component_write(component, ES8336_SYS_LP2_REG0F, 0x1F);
+		snd_soc_component_write(component, ES8336_RESET_REG00, 0x00);
+		break;
+	}
+
+	return 0;
+}
+
+#define es8336_RATES SNDRV_PCM_RATE_8000_96000
+
+#define es8336_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+	SNDRV_PCM_FMTBIT_S24_LE)
+
+static const struct snd_soc_dai_ops es8336_ops = {
+	.startup = es8336_pcm_startup,
+	.hw_params = es8336_pcm_hw_params,
+	.set_fmt = es8336_set_dai_fmt,
+	.set_sysclk = es8336_set_dai_sysclk,
+	.mute_stream = es8336_mute,
+	.shutdown = es8336_pcm_shutdown,
+};
+
+static struct snd_soc_dai_driver es8336_dai = {
+	.name = "es8336-hifi",
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = es8336_RATES,
+		.formats = es8336_FORMATS,
+	},
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = es8336_RATES,
+		.formats = es8336_FORMATS,
+	},
+	.ops = &es8336_ops,
+	.symmetric_rates = 1,
+};
+
+static int es8336_init_regs(struct snd_soc_component *component)
+{
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+	snd_soc_component_write(component, ES8336_RESET_REG00, 0x3f);
+	usleep_range(5000, 5500);
+	snd_soc_component_write(component, ES8336_RESET_REG00, 0x00);
+	snd_soc_component_write(component, ES8336_SYS_VMIDSEL_REG0C, 0xFF);
+	msleep(30);
+	snd_soc_component_write(component, ES8336_CLKMGR_CLKSEL_REG02, 0x08);
+	snd_soc_component_write(component, ES8336_CLKMGR_ADCOSR_REG03, 0x20);
+	snd_soc_component_write(component, ES8336_CLKMGR_ADCDIV1_REG04, 0x11);
+	snd_soc_component_write(component, ES8336_CLKMGR_ADCDIV2_REG05, 0x00);
+	snd_soc_component_write(component, ES8336_CLKMGR_DACDIV1_REG06, 0x11);
+	snd_soc_component_write(component, ES8336_CLKMGR_DACDIV2_REG07, 0x00);
+	snd_soc_component_write(component, ES8336_CLKMGR_CPDIV_REG08, 0x00);
+	snd_soc_component_write(component, ES8336_SDP_MS_BCKDIV_REG09, 0x04);
+	snd_soc_component_write(component, ES8336_CLKMGR_CLKSW_REG01, 0x7F);
+	snd_soc_component_write(component, ES8336_CAL_TYPE_REG1C, 0x0F);
+	snd_soc_component_write(component, ES8336_CAL_HPLIV_REG1E, 0x90);
+	snd_soc_component_write(component, ES8336_CAL_HPRIV_REG1F, 0x90);
+	snd_soc_component_write(component, ES8336_ADC_VOLUME_REG27, 0x00);
+	snd_soc_component_write(component, ES8336_ADC_PDN_LINSEL_REG22, es8336->mic_src);
+	snd_soc_component_write(component, ES8336_ADC_D2SEPGA_REG24, 0x00);
+	snd_soc_component_write(component, ES8336_ADC_DMIC_REG25, 0x08);
+	snd_soc_component_write(component, ES8336_DAC_SET2_REG31, 0x20);
+	snd_soc_component_write(component, ES8336_DAC_SET3_REG32, 0x00);
+	snd_soc_component_write(component, ES8336_DAC_VOLL_REG33, 0x00);
+	snd_soc_component_write(component, ES8336_DAC_VOLR_REG34, 0x00);
+	snd_soc_component_write(component, ES8336_SDP_ADCFMT_REG0A, 0x00);
+	snd_soc_component_write(component, ES8336_SDP_DACFMT_REG0B, 0x00);
+	snd_soc_component_write(component, ES8336_SYS_VMIDLOW_REG10, 0x11);
+	snd_soc_component_write(component, ES8336_SYS_VSEL_REG11, 0xFC);
+	snd_soc_component_write(component, ES8336_SYS_REF_REG12, 0x28);
+	snd_soc_component_write(component, ES8336_SYS_LP1_REG0E, 0x04);
+	snd_soc_component_write(component, ES8336_SYS_LP2_REG0F, 0x0C);
+	snd_soc_component_write(component, ES8336_DAC_PDN_REG2F, 0x11);
+	snd_soc_component_write(component, ES8336_HPMIX_SEL_REG13, 0x00);
+	snd_soc_component_write(component, ES8336_HPMIX_SWITCH_REG14, 0x88);
+	snd_soc_component_write(component, ES8336_HPMIX_PDN_REG15, 0x00);
+	snd_soc_component_write(component, ES8336_HPMIX_VOL_REG16, 0xBB);
+	snd_soc_component_write(component, ES8336_CPHP_PDN2_REG1A, 0x10);
+	snd_soc_component_write(component, ES8336_CPHP_LDOCTL_REG1B, 0x30);
+	snd_soc_component_write(component, ES8336_CPHP_PDN1_REG19, 0x02);
+	snd_soc_component_write(component, ES8336_CPHP_ICAL_VOL_REG18, 0x00);
+	snd_soc_component_write(component, ES8336_GPIO_SEL_REG4D, 0x02);
+	snd_soc_component_write(component, ES8336_GPIO_DEBUNCE_INT_REG4E, 0x02);
+	snd_soc_component_write(component, ES8336_TESTMODE_REG50, 0xA0);
+	snd_soc_component_write(component, ES8336_TEST1_REG51, 0x00);
+	snd_soc_component_write(component, ES8336_TEST2_REG52, 0x00);
+	snd_soc_component_write(component, ES8336_SYS_PDN_REG0D, 0x00);
+	snd_soc_component_write(component, ES8336_RESET_REG00, 0xC0);
+	msleep(50);
+	snd_soc_component_write(component, ES8336_ADC_PGAGAIN_REG23, 0x60);
+	snd_soc_component_write(component, ES8336_ADC_D2SEPGA_REG24, 0x01);
+	/* adc ds mode, HPF enable */
+	snd_soc_component_write(component, ES8336_ADC_DMIC_REG25, 0x08);
+	snd_soc_component_write(component, ES8336_ADC_ALC1_REG29, 0xcd);
+	snd_soc_component_write(component, ES8336_ADC_ALC2_REG2A, 0x08);
+	snd_soc_component_write(component, ES8336_ADC_ALC3_REG2B, 0xa0);
+	snd_soc_component_write(component, ES8336_ADC_ALC4_REG2C, 0x05);
+	snd_soc_component_write(component, ES8336_ADC_ALC5_REG2D, 0x06);
+	snd_soc_component_write(component, ES8336_ADC_ALC6_REG2E, 0x61);
+	return 0;
+}
+
+static int es8336_suspend(struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static int es8336_resume(struct snd_soc_component *component)
+{
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+	int ret;
+
+	es8336_reset(component); /* UPDATED BY DAVID,15-3-5 */
+	ret = snd_soc_component_read(component, ES8336_CLKMGR_ADCDIV2_REG05);
+	if (!ret) {
+		es8336_init_regs(component);
+		snd_soc_component_write(component, ES8336_GPIO_SEL_REG4D, 0x02);
+		/* max debance time, enable interrupt, low active */
+		snd_soc_component_write(component, ES8336_GPIO_DEBUNCE_INT_REG4E, 0xf3);
+		/* es8336_set_bias_level(component, SND_SOC_BIAS_OFF); */
+		snd_soc_component_write(component, ES8336_CPHP_OUTEN_REG17, 0x00);
+		snd_soc_component_write(component, ES8336_DAC_PDN_REG2F, 0x11);
+		snd_soc_component_write(component, ES8336_CPHP_LDOCTL_REG1B, 0x03);
+		snd_soc_component_write(component, ES8336_CPHP_PDN2_REG1A, 0x22);
+		snd_soc_component_write(component, ES8336_CPHP_PDN1_REG19, 0x06);
+		snd_soc_component_write(component, ES8336_HPMIX_SWITCH_REG14, 0x00);
+		snd_soc_component_write(component, ES8336_HPMIX_PDN_REG15, 0x33);
+		snd_soc_component_write(component, ES8336_HPMIX_VOL_REG16, 0x00);
+		if (!es8336->hp_inserted)
+			snd_soc_component_write(component, ES8336_SYS_PDN_REG0D, 0x3F);
+		snd_soc_component_write(component, ES8336_SYS_LP1_REG0E, 0xFF);
+		snd_soc_component_write(component, ES8336_SYS_LP2_REG0F, 0xFF);
+		snd_soc_component_write(component, ES8336_CLKMGR_CLKSW_REG01, 0xF3);
+		snd_soc_component_update_bits(component, ES8336_ADC_PDN_LINSEL_REG22, 0xC0, 0xC0);
+	}
+	return 0;
+}
+
+static irqreturn_t es8336_irq_handler(int irq, void *data)
+{
+	struct es8336_priv *es8336 = data;
+
+	queue_delayed_work(system_power_efficient_wq, &es8336->work,
+			   msecs_to_jiffies(es8336->debounce_time));
+
+	return IRQ_HANDLED;
+}
+
+static void hp_work(struct work_struct *work)
+{
+	struct es8336_priv *es8336;
+
+	es8336 = container_of(work, struct es8336_priv, work.work);
+
+	es8336->hp_inserted = gpiod_get_value(es8336->hp_det_gpio);
+	if (!es8336->muted) {
+		if (es8336->hp_inserted)
+			es8336_enable_spk(es8336, false);
+		else
+			es8336_enable_spk(es8336, true);
+	}
+}
+
+static int es8336_probe(struct snd_soc_component *component)
+{
+	struct es8336_priv *es8336 = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+
+	es8336_component = component;
+	ret = snd_soc_component_read(component, ES8336_CLKMGR_ADCDIV2_REG05);
+	if (!ret) {
+		es8336_reset(component); /* UPDATED BY DAVID,15-3-5 */
+		ret = snd_soc_component_read(component, ES8336_CLKMGR_ADCDIV2_REG05);
+		if (!ret) {
+			es8336_init_regs(component);
+			snd_soc_component_write(component, ES8336_GPIO_SEL_REG4D, 0x02);
+			/* max debance time, enable interrupt, low active */
+			snd_soc_component_write(component,
+				      ES8336_GPIO_DEBUNCE_INT_REG4E, 0xf3);
+
+			/* es8336_set_bias_level(codec, SND_SOC_BIAS_OFF); */
+			snd_soc_component_write(component, ES8336_CPHP_OUTEN_REG17, 0x00);
+			snd_soc_component_write(component, ES8336_DAC_PDN_REG2F, 0x11);
+			snd_soc_component_write(component, ES8336_CPHP_LDOCTL_REG1B, 0x03);
+			snd_soc_component_write(component, ES8336_CPHP_PDN2_REG1A, 0x22);
+			snd_soc_component_write(component, ES8336_CPHP_PDN1_REG19, 0x06);
+			snd_soc_component_write(component, ES8336_HPMIX_SWITCH_REG14, 0x00);
+			snd_soc_component_write(component, ES8336_HPMIX_PDN_REG15, 0x33);
+			snd_soc_component_write(component, ES8336_HPMIX_VOL_REG16, 0x00);
+			if (!es8336->hp_inserted)
+				snd_soc_component_write(component, ES8336_SYS_PDN_REG0D,
+					      0x3F);
+			snd_soc_component_write(component, ES8336_SYS_LP1_REG0E, 0xFF);
+			snd_soc_component_write(component, ES8336_SYS_LP2_REG0F, 0xFF);
+			snd_soc_component_write(component, ES8336_CLKMGR_CLKSW_REG01, 0xF3);
+			snd_soc_component_update_bits(component, ES8336_ADC_PDN_LINSEL_REG22, 0xC0, 0xC0);
+		}
+	}
+
+	return ret;
+}
+
+static void es8336_remove(struct snd_soc_component *component)
+{
+	es8336_set_bias_level(component, SND_SOC_BIAS_OFF);
+}
+
+const struct regmap_config es8336_regmap_config = {
+	.reg_bits	= 8,
+	.val_bits	= 8,
+	.max_register	= ES8336_TEST3_REG53,
+	.cache_type	= REGCACHE_RBTREE,
+	.reg_defaults = es8336_reg_defaults,
+	.num_reg_defaults = ARRAY_SIZE(es8336_reg_defaults),
+};
+
+static const struct snd_soc_component_driver soc_component_dev_es8336 = {
+	.probe =	es8336_probe,
+	.remove =	es8336_remove,
+	.suspend =	es8336_suspend,
+	.resume =	es8336_resume,
+	.set_bias_level = es8336_set_bias_level,
+
+	.controls = es8336_snd_controls,
+	.num_controls = ARRAY_SIZE(es8336_snd_controls),
+	.dapm_widgets = es8336_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(es8336_dapm_widgets),
+	.dapm_routes = es8336_dapm_routes,
+	.num_dapm_routes = ARRAY_SIZE(es8336_dapm_routes),
+};
+
+static int es8336_i2c_probe(struct i2c_client *i2c,
+			    const struct i2c_device_id *id)
+{
+	struct es8336_priv *es8336;
+	int ret = -1;
+	int hp_irq;
+
+	es8336 = devm_kzalloc(&i2c->dev, sizeof(*es8336), GFP_KERNEL);
+	if (!es8336)
+		return -ENOMEM;
+
+	es8336->debounce_time = 200;
+	es8336->pwr_count = 0;
+	es8336->hp_inserted = false;
+	es8336->muted = true;
+
+	es8336->regmap = devm_regmap_init_i2c(i2c, &es8336_regmap_config);
+	if (IS_ERR(es8336->regmap)) {
+		ret = PTR_ERR(es8336->regmap);
+		dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
+		return ret;
+	}
+
+	i2c_set_clientdata(i2c, es8336);
+
+	es8336->spk_ctl_gpio = devm_gpiod_get_index_optional(&i2c->dev, "sel", 0,
+							GPIOD_OUT_HIGH);
+	ret = of_property_read_u8(i2c->dev.of_node, "mic-src", &es8336->mic_src);
+	if (ret != 0) {
+		dev_dbg(&i2c->dev, "mic1-src return %d", ret);
+		es8336->mic_src = 0x20;
+	}
+	dev_dbg(&i2c->dev, "mic1-src %x", es8336->mic_src);
+
+	if (IS_ERR_OR_NULL(es8336->spk_ctl_gpio))
+		dev_info(&i2c->dev, "Can not get spk_ctl_gpio\n");
+	else
+		es8336_enable_spk(es8336, false);
+
+	es8336->hp_det_gpio = devm_gpiod_get_index_optional(&i2c->dev, "det", 0,
+							GPIOD_IN);
+
+	if (IS_ERR_OR_NULL(es8336->hp_det_gpio)) {
+		dev_info(&i2c->dev, "Can not get hp_det_gpio\n");
+	} else {
+		INIT_DELAYED_WORK(&es8336->work, hp_work);
+		hp_irq = gpiod_to_irq(es8336->hp_det_gpio);
+		ret = devm_request_threaded_irq(&i2c->dev, hp_irq, NULL,
+						es8336_irq_handler,
+						IRQF_TRIGGER_FALLING |
+						IRQF_TRIGGER_RISING |
+						IRQF_ONESHOT,
+						"es8336_interrupt", es8336);
+		if (ret < 0) {
+			dev_err(&i2c->dev, "request_irq failed: %d\n", ret);
+			return ret;
+		}
+
+		schedule_delayed_work(&es8336->work,
+				      msecs_to_jiffies(es8336->debounce_time));
+	}
+
+	ret = snd_soc_register_component(&i2c->dev,
+				     &soc_component_dev_es8336,
+				     &es8336_dai, 1);
+
+	return ret;
+}
+
+static  int es8336_i2c_remove(struct i2c_client *client)
+{
+	kfree(i2c_get_clientdata(client));
+	return 0;
+}
+
+static void es8336_i2c_shutdown(struct i2c_client *client)
+{
+	struct es8336_priv *es8336 = i2c_get_clientdata(client);
+
+	if (es8336_component != NULL) {
+		es8336_enable_spk(es8336, false);
+		msleep(20);
+		es8336_set_bias_level(es8336_component, SND_SOC_BIAS_OFF);
+	}
+}
+
+static const struct i2c_device_id es8336_i2c_id[] = {
+	{"es8336", 0},
+	{"10ES8336:00", 0},
+	{"10ES8336", 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, es8336_i2c_id);
+
+static const struct of_device_id es8336_of_match[] = {
+	{ .compatible = "everest,es8336", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, es8336_of_match);
+
+static const struct acpi_device_id es8336_acpi_match[] = {
+	{ "ESSX8336", 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, es8336_acpi_match);
+
+static struct i2c_driver es8336_i2c_driver = {
+	.driver = {
+		.name		= "es8336",
+		.of_match_table = es8336_of_match,
+		.acpi_match_table = es8336_acpi_match,
+	},
+	.probe    = es8336_i2c_probe,
+	.remove	= es8336_i2c_remove,
+	.shutdown = es8336_i2c_shutdown,
+	.id_table = es8336_i2c_id,
+};
+
+module_i2c_driver(es8336_i2c_driver);
+MODULE_DESCRIPTION("ASoC es8336 driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/sound/soc/codecs/es8336.h b/target/linux/phytium/files-5.10/sound/soc/codecs/es8336.h
new file mode 100644
index 00000000000000..d2c74c11ffd1e3
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/codecs/es8336.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright Everest Semiconductor Co.,Ltd
+ *           Phytium Information Technology Co.,Ltd
+ *
+ * Author: David Yang <yangxiaohua@everest-semi.com>
+ *         Yiqun Zhang <zhangyiqun@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ES8336_H
+#define _ES8336_H
+
+/* ES8336 register space */
+/*
+ * RESET Control
+ */
+#define ES8336_RESET_REG00             0x00
+/*
+ * Clock Managerment
+ */
+#define ES8336_CLKMGR_CLKSW_REG01      0x01
+#define ES8336_CLKMGR_CLKSEL_REG02     0x02
+#define ES8336_CLKMGR_ADCOSR_REG03     0x03
+#define ES8336_CLKMGR_ADCDIV1_REG04    0x04
+#define ES8336_CLKMGR_ADCDIV2_REG05    0x05
+#define ES8336_CLKMGR_DACDIV1_REG06    0x06
+#define ES8336_CLKMGR_DACDIV2_REG07    0x07
+#define ES8336_CLKMGR_CPDIV_REG08      0x08
+/*
+ * SDP Control
+ */
+#define ES8336_SDP_MS_BCKDIV_REG09     0x09
+#define ES8336_SDP_ADCFMT_REG0A        0x0a
+#define ES8336_SDP_DACFMT_REG0B        0x0b
+/*
+ * System Control
+ */
+#define ES8336_SYS_VMIDSEL_REG0C       0x0c
+#define ES8336_SYS_PDN_REG0D           0x0d
+#define ES8336_SYS_LP1_REG0E           0x0e
+#define ES8336_SYS_LP2_REG0F           0x0f
+#define ES8336_SYS_VMIDLOW_REG10       0x10
+#define ES8336_SYS_VSEL_REG11          0x11
+#define ES8336_SYS_REF_REG12           0x12
+/*
+ * HP Mixer
+ */
+#define ES8336_HPMIX_SEL_REG13         0x13
+#define ES8336_HPMIX_SWITCH_REG14      0x14
+#define ES8336_HPMIX_PDN_REG15         0x15
+#define ES8336_HPMIX_VOL_REG16         0x16
+/*
+ * Charge Pump Headphone driver
+ */
+#define ES8336_CPHP_OUTEN_REG17        0x17
+#define ES8336_CPHP_ICAL_VOL_REG18     0x18
+#define ES8336_CPHP_PDN1_REG19         0x19
+#define ES8336_CPHP_PDN2_REG1A         0x1a
+#define ES8336_CPHP_LDOCTL_REG1B       0x1b
+/*
+ * Calibration
+ */
+#define ES8336_CAL_TYPE_REG1C         0x1c
+#define ES8336_CAL_SET_REG1D          0x1d
+#define ES8336_CAL_HPLIV_REG1E        0x1e
+#define ES8336_CAL_HPRIV_REG1F        0x1f
+#define ES8336_CAL_HPLMV_REG20        0x20
+#define ES8336_CAL_HPRMV_REG21        0x21
+/*
+ * ADC Control
+ */
+#define ES8336_ADC_PDN_LINSEL_REG22   0x22
+#define ES8336_ADC_PGAGAIN_REG23      0x23
+#define ES8336_ADC_D2SEPGA_REG24      0x24
+#define ES8336_ADC_DMIC_REG25         0x25
+#define ES8336_ADC_MUTE_REG26         0x26
+#define ES8336_ADC_VOLUME_REG27       0x27
+#define ES8336_ADC_ALC1_REG29         0x29
+#define ES8336_ADC_ALC2_REG2A         0x2a
+#define ES8336_ADC_ALC3_REG2B         0x2b
+#define ES8336_ADC_ALC4_REG2C         0x2c
+#define ES8336_ADC_ALC5_REG2D         0x2d
+#define ES8336_ADC_ALC6_REG2E         0x2e
+/*
+ * DAC Control
+ */
+#define ES8336_DAC_PDN_REG2F          0x2f
+#define ES8336_DAC_SET1_REG30         0x30
+#define ES8336_DAC_SET2_REG31         0x31
+#define ES8336_DAC_SET3_REG32         0x32
+#define ES8336_DAC_VOLL_REG33         0x33
+#define ES8336_DAC_VOLR_REG34         0x34
+/*
+ * GPIO
+ */
+#define ES8336_GPIO_SEL_REG4D         0x4D
+#define ES8336_GPIO_DEBUNCE_INT_REG4E 0x4E
+#define ES8336_GPIO_FLAG              0x4F
+/*
+ * TEST MODE
+ */
+#define ES8336_TESTMODE_REG50         0x50
+#define ES8336_TEST1_REG51            0x51
+#define ES8336_TEST2_REG52            0x52
+#define ES8336_TEST3_REG53            0x53
+
+#define ES8336_IFACE            ES8336_SDP_MS_BCKDIV_REG09
+#define ES8336_ADC_IFACE        ES8336_SDP_ADCFMT_REG0A
+#define ES8336_DAC_IFACE        ES8336_SDP_DACFMT_REG0B
+
+#define ES8336_REGNUM      84
+
+/* REGISTER 0X01 CLOCK MANAGER */
+#define ES8336_CLKMGR_MCLK_DIV_MASK	(0X1<<7)
+#define ES8336_CLKMGR_MCLK_DIV_NML	(0X0<<7)
+#define ES8336_CLKMGR_MCLK_DIV_1	(0X1<<7)
+#define ES8336_CLKMGR_ADC_MCLK_MASK	(0X1<<3)
+#define ES8336_CLKMGR_ADC_MCLK_EN	(0X1<<3)
+#define ES8336_CLKMGR_ADC_MCLK_DIS	(0X0<<3)
+#define ES8336_CLKMGR_DAC_MCLK_MASK	(0X1<<2)
+#define ES8336_CLKMGR_DAC_MCLK_EN	(0X1<<2)
+#define ES8336_CLKMGR_DAC_MCLK_DIS	(0X0<<2)
+#define ES8336_CLKMGR_ADC_ANALOG_MASK	(0X1<<1)
+#define ES8336_CLKMGR_ADC_ANALOG_EN	(0X1<<1)
+#define ES8336_CLKMGR_ADC_ANALOG_DIS	(0X0<<1)
+#define ES8336_CLKMGR_DAC_ANALOG_MASK	(0X1<<0)
+#define ES8336_CLKMGR_DAC_ANALOG_EN	(0X1<<0)
+#define ES8336_CLKMGR_DAC_ANALOG_DIS	(0X0<<0)
+
+/* REGISTER 0X0A */
+#define ES8336_ADCWL_MASK	(0x7 << 2)
+#define ES8336_ADCWL_32		(0x4 << 2)
+#define ES8336_ADCWL_24		(0x0 << 2)
+#define ES8336_ADCWL_20		(0x1 << 2)
+#define ES8336_ADCWL_18		(0x2 << 2)
+#define ES8336_ADCWL_16		(0x3 << 2)
+#define ES8336_ADCFMT_MASK	(0x3 << 0)
+#define ES8336_ADCFMT_I2S	(0x0 << 0)
+#define ES8336_ADCWL_LEFT	(0x1 << 0)
+#define ES8336_ADCWL_RIGHT	(0x2 << 0)
+#define ES8336_ADCWL_PCM	(0x3 << 0)
+
+/* REGISTER 0X0B */
+#define ES8336_DACWL_MASK	(0x7 << 2)
+#define ES8336_DACWL_32		(0x4 << 2)
+#define ES8336_DACWL_24		(0x0 << 2)
+#define ES8336_DACWL_20		(0x1 << 2)
+#define ES8336_DACWL_18		(0x2 << 2)
+#define ES8336_DACWL_16		(0x3 << 2)
+#define ES8336_DACFMT_MASK	(0x3 << 0)
+#define ES8336_DACFMT_I2S	(0x0 << 0)
+#define ES8336_DACWL_LEFT	(0x1 << 0)
+#define ES8336_DACWL_RIGHT	(0x2 << 0)
+#define ES8336_DACWL_PCM	(0x3 << 0)
+
+#endif
diff --git a/target/linux/phytium/files-5.10/sound/soc/codecs/es8388.c b/target/linux/phytium/files-5.10/sound/soc/codecs/es8388.c
new file mode 100644
index 00000000000000..2824b630668664
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/codecs/es8388.c
@@ -0,0 +1,820 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * es8388.c  --  ES8388 ALSA SoC Audio driver
+ *
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ * Author: Yiqun Zhang <zhangyiqun@phytium.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include "es8388.h"
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+
+static const unsigned int rates_12288[] = {
+	8000, 12000, 16000, 24000, 32000, 48000, 96000,
+};
+
+static const int ratios_12288[] = {
+	10, 7, 6, 4, 3, 2, 0,
+};
+
+static const struct snd_pcm_hw_constraint_list constraints_12288 = {
+	.count	= ARRAY_SIZE(rates_12288),
+	.list	= rates_12288,
+};
+
+static const unsigned int rates_11289[] = {
+	8018, 11025, 22050, 44100, 88200,
+};
+
+static const int ratios_11289[] = {
+	9, 7, 4, 2, 0,
+};
+
+static const struct snd_pcm_hw_constraint_list constraints_11289 = {
+	.count	= ARRAY_SIZE(rates_11289),
+	.list	= rates_11289,
+};
+
+#define ES8388_RATES (SNDRV_PCM_RATE_192000 | \
+		SNDRV_PCM_RATE_96000 | \
+		SNDRV_PCM_RATE_88200 | \
+		SNDRV_PCM_RATE_8000_48000)
+#define ES8388_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+		SNDRV_PCM_FMTBIT_S18_3LE | \
+		SNDRV_PCM_FMTBIT_S20_3LE | \
+		SNDRV_PCM_FMTBIT_S24_LE | \
+		SNDRV_PCM_FMTBIT_S32_LE)
+
+struct es8388_priv {
+	struct regmap *regmap;
+	struct clk *clk;
+	int playback_fs;
+	bool deemph;
+	int mclkdiv2;
+	const struct snd_pcm_hw_constraint_list *sysclk_constraints;
+	const int *mclk_ratios;
+	bool master;
+};
+
+/*
+ * ES8388 Controls
+ */
+static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
+					  "L + R Invert"};
+static SOC_ENUM_SINGLE_DECL(adcpol,
+			    ES8388_ADCCONTROL6, 6, adcpol_txt);
+
+static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
+static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
+static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
+static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
+static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
+
+static const struct {
+	int rate;
+	unsigned int val;
+} deemph_settings[] = {
+	{ 0,     ES8388_DACCONTROL6_DEEMPH_OFF },
+	{ 32000, ES8388_DACCONTROL6_DEEMPH_32k },
+	{ 44100, ES8388_DACCONTROL6_DEEMPH_44_1k },
+	{ 48000, ES8388_DACCONTROL6_DEEMPH_48k },
+};
+
+static int es8388_set_deemph(struct snd_soc_component *component)
+{
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+	int val, i, best;
+
+	/*
+	 * If we're using deemphasis select the nearest available sample
+	 * rate.
+	 */
+	if (es8388->deemph) {
+		best = 0;
+		for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
+			if (abs(deemph_settings[i].rate - es8388->playback_fs) <
+			    abs(deemph_settings[best].rate - es8388->playback_fs))
+				best = i;
+		}
+
+		val = deemph_settings[best].val;
+	} else {
+		val = ES8388_DACCONTROL6_DEEMPH_OFF;
+	}
+
+	dev_dbg(component->dev, "Set deemphasis %d\n", val);
+
+	return snd_soc_component_update_bits(component, ES8388_DACCONTROL6,
+			ES8388_DACCONTROL6_DEEMPH_MASK, val);
+}
+
+static int es8388_get_deemph(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = es8388->deemph;
+	return 0;
+}
+
+static int es8388_put_deemph(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+	unsigned int deemph = ucontrol->value.integer.value[0];
+	int ret;
+
+	if (deemph > 1)
+		return -EINVAL;
+
+	ret = es8388_set_deemph(component);
+	if (ret < 0)
+		return ret;
+
+	es8388->deemph = deemph;
+
+	return 0;
+}
+
+static const struct snd_kcontrol_new es8388_snd_controls[] = {
+	SOC_DOUBLE_R_TLV("Capture Digital Volume",
+		ES8388_ADCCONTROL8, ES8388_ADCCONTROL9,
+		 0, 0xc0, 1, dac_adc_tlv),
+
+	SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
+		    es8388_get_deemph, es8388_put_deemph),
+
+	SOC_ENUM("Capture Polarity", adcpol),
+
+	SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
+			ES8388_DACCONTROL17, 3, 7, 1, bypass_tlv),
+	SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
+			ES8388_DACCONTROL19, 3, 7, 1, bypass_tlv),
+	SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
+			ES8388_DACCONTROL18, 3, 7, 1, bypass_tlv),
+	SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
+			ES8388_DACCONTROL20, 3, 7, 1, bypass_tlv),
+
+	SOC_DOUBLE_R_TLV("PCM Volume",
+			ES8388_LDACVOL, ES8388_RDACVOL,
+			0, ES8388_DACVOL_MAX, 1, dac_adc_tlv),
+
+	SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
+			ES8388_LOUT1VOL, ES8388_ROUT1VOL,
+			0, ES8388_OUT1VOL_MAX, 0, play_tlv),
+
+	SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
+			ES8388_LOUT2VOL, ES8388_ROUT2VOL,
+			0, ES8388_OUT2VOL_MAX, 0, play_tlv),
+
+	SOC_DOUBLE_TLV("Mic PGA Volume", ES8388_ADCCONTROL1,
+			4, 0, 8, 0, mic_tlv),
+};
+
+/*
+ * DAPM Controls
+ */
+static const char * const es8388_line_texts[] = {
+	"Line 1", "Line 2", "PGA", "Differential"};
+
+static const struct soc_enum es8388_lline_enum =
+	SOC_ENUM_SINGLE(ES8388_DACCONTROL16, 3,
+			      ARRAY_SIZE(es8388_line_texts),
+			      es8388_line_texts);
+static const struct snd_kcontrol_new es8388_left_line_controls =
+	SOC_DAPM_ENUM("Route", es8388_lline_enum);
+
+static const struct soc_enum es8388_rline_enum =
+	SOC_ENUM_SINGLE(ES8388_DACCONTROL16, 0,
+			      ARRAY_SIZE(es8388_line_texts),
+			      es8388_line_texts);
+static const struct snd_kcontrol_new es8388_right_line_controls =
+	SOC_DAPM_ENUM("Route", es8388_lline_enum);
+
+/* Left Mixer */
+static const struct snd_kcontrol_new es8388_left_mixer_controls[] = {
+	SOC_DAPM_SINGLE("Playback Switch", ES8388_DACCONTROL17, 7, 1, 0),
+	SOC_DAPM_SINGLE("Left Bypass Switch", ES8388_DACCONTROL17, 6, 1, 0),
+	SOC_DAPM_SINGLE("Right Playback Switch", ES8388_DACCONTROL18, 7, 1, 0),
+	SOC_DAPM_SINGLE("Right Bypass Switch", ES8388_DACCONTROL18, 6, 1, 0),
+};
+
+/* Right Mixer */
+static const struct snd_kcontrol_new es8388_right_mixer_controls[] = {
+	SOC_DAPM_SINGLE("Left Playback Switch", ES8388_DACCONTROL19, 7, 1, 0),
+	SOC_DAPM_SINGLE("Left Bypass Switch", ES8388_DACCONTROL19, 6, 1, 0),
+	SOC_DAPM_SINGLE("Playback Switch", ES8388_DACCONTROL20, 7, 1, 0),
+	SOC_DAPM_SINGLE("Right Bypass Switch", ES8388_DACCONTROL20, 6, 1, 0),
+};
+
+static const char * const es8388_pga_sel[] = {
+	"Line 1", "Line 2", "Line 3", "Differential"};
+
+/* Left PGA Mux */
+static const struct soc_enum es8388_lpga_enum =
+	SOC_ENUM_SINGLE(ES8388_ADCCONTROL2, 6,
+			      ARRAY_SIZE(es8388_pga_sel),
+			      es8388_pga_sel);
+static const struct snd_kcontrol_new es8388_left_pga_controls =
+	SOC_DAPM_ENUM("Route", es8388_lpga_enum);
+
+/* Right PGA Mux */
+static const struct soc_enum es8388_rpga_enum =
+	SOC_ENUM_SINGLE(ES8388_ADCCONTROL2, 4,
+			      ARRAY_SIZE(es8388_pga_sel),
+			      es8388_pga_sel);
+static const struct snd_kcontrol_new es8388_right_pga_controls =
+	SOC_DAPM_ENUM("Route", es8388_rpga_enum);
+
+/* Differential Mux */
+static const char * const es8388_diff_sel[] = {"Line 1", "Line 2"};
+static SOC_ENUM_SINGLE_DECL(diffmux,
+			    ES8388_ADCCONTROL3, 7, es8388_diff_sel);
+static const struct snd_kcontrol_new es8388_diffmux_controls =
+	SOC_DAPM_ENUM("Route", diffmux);
+
+/* Mono ADC Mux */
+static const char * const es8388_mono_mux[] = {"Stereo", "Mono (Left)",
+	"Mono (Right)", "Digital Mono"};
+static SOC_ENUM_SINGLE_DECL(monomux,
+			    ES8388_ADCCONTROL3, 3, es8388_mono_mux);
+static const struct snd_kcontrol_new es8388_monomux_controls =
+	SOC_DAPM_ENUM("Route", monomux);
+
+static const struct snd_soc_dapm_widget es8388_dapm_widgets[] = {
+	SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
+		&es8388_diffmux_controls),
+	SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
+		&es8388_monomux_controls),
+	SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
+		&es8388_monomux_controls),
+
+	SND_SOC_DAPM_MUX("Left PGA Mux", ES8388_ADCPOWER,
+			ES8388_ADCPOWER_AINL_OFF, 1,
+			&es8388_left_pga_controls),
+	SND_SOC_DAPM_MUX("Right PGA Mux", ES8388_ADCPOWER,
+			ES8388_ADCPOWER_AINR_OFF, 1,
+			&es8388_right_pga_controls),
+
+	SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
+		&es8388_left_line_controls),
+	SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
+		&es8388_right_line_controls),
+
+	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8388_ADCPOWER,
+			ES8388_ADCPOWER_ADCR_OFF, 1),
+	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8388_ADCPOWER,
+			ES8388_ADCPOWER_ADCL_OFF, 1),
+
+	SND_SOC_DAPM_SUPPLY("DAC STM", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC STM", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
+
+	SND_SOC_DAPM_SUPPLY("DAC DIG", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC DIG", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
+
+	SND_SOC_DAPM_SUPPLY("DAC DLL", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC DLL", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
+
+	SND_SOC_DAPM_SUPPLY("ADC Vref", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC Vref", ES8388_CHIPPOWER,
+			ES8388_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
+
+	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8388_DACPOWER,
+			ES8388_DACPOWER_RDAC_OFF, 1),
+	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8388_DACPOWER,
+			ES8388_DACPOWER_LDAC_OFF, 1),
+
+	SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
+		&es8388_left_mixer_controls[0],
+		ARRAY_SIZE(es8388_left_mixer_controls)),
+	SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
+		&es8388_right_mixer_controls[0],
+		ARRAY_SIZE(es8388_right_mixer_controls)),
+
+	SND_SOC_DAPM_PGA("Right Out 2", ES8388_DACPOWER,
+			ES8388_DACPOWER_ROUT2_ON, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("Left Out 2", ES8388_DACPOWER,
+			ES8388_DACPOWER_LOUT2_ON, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("Right Out 1", ES8388_DACPOWER,
+			ES8388_DACPOWER_ROUT1_ON, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("Left Out 1", ES8388_DACPOWER,
+			ES8388_DACPOWER_LOUT1_ON, 0, NULL, 0),
+
+	SND_SOC_DAPM_OUTPUT("LOUT1"),
+	SND_SOC_DAPM_OUTPUT("ROUT1"),
+	SND_SOC_DAPM_OUTPUT("LOUT2"),
+	SND_SOC_DAPM_OUTPUT("ROUT2"),
+
+	SND_SOC_DAPM_INPUT("LINPUT1"),
+	SND_SOC_DAPM_INPUT("LINPUT2"),
+	SND_SOC_DAPM_INPUT("RINPUT1"),
+	SND_SOC_DAPM_INPUT("RINPUT2"),
+};
+
+static const struct snd_soc_dapm_route es8388_dapm_routes[] = {
+	{ "Left Line Mux", "Line 1", "LINPUT1" },
+	{ "Left Line Mux", "Line 2", "LINPUT2" },
+	{ "Left Line Mux", "PGA", "Left PGA Mux" },
+	{ "Left Line Mux", "Differential", "Differential Mux" },
+
+	{ "Right Line Mux", "Line 1", "RINPUT1" },
+	{ "Right Line Mux", "Line 2", "RINPUT2" },
+	{ "Right Line Mux", "PGA", "Right PGA Mux" },
+	{ "Right Line Mux", "Differential", "Differential Mux" },
+
+	{ "Left PGA Mux", "Line 1", "LINPUT1" },
+	{ "Left PGA Mux", "Line 2", "LINPUT2" },
+	{ "Left PGA Mux", "Differential", "Differential Mux" },
+
+	{ "Right PGA Mux", "Line 1", "RINPUT1" },
+	{ "Right PGA Mux", "Line 2", "RINPUT2" },
+	{ "Right PGA Mux", "Differential", "Differential Mux" },
+
+	{ "Differential Mux", "Line 1", "LINPUT1" },
+	{ "Differential Mux", "Line 1", "RINPUT1" },
+	{ "Differential Mux", "Line 2", "LINPUT2" },
+	{ "Differential Mux", "Line 2", "RINPUT2" },
+
+	{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
+	{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
+	{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
+
+	{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
+	{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
+	{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
+
+	{ "Left ADC", NULL, "Left ADC Mux" },
+	{ "Right ADC", NULL, "Right ADC Mux" },
+
+	{ "ADC DIG", NULL, "ADC STM" },
+	{ "ADC DIG", NULL, "ADC Vref" },
+	{ "ADC DIG", NULL, "ADC DLL" },
+
+	{ "Left ADC", NULL, "ADC DIG" },
+	{ "Right ADC", NULL, "ADC DIG" },
+
+	{ "Left Line Mux", "Line 1", "LINPUT1" },
+	{ "Left Line Mux", "Line 2", "LINPUT2" },
+	{ "Left Line Mux", "PGA", "Left PGA Mux" },
+	{ "Left Line Mux", "Differential", "Differential Mux" },
+
+	{ "Right Line Mux", "Line 1", "RINPUT1" },
+	{ "Right Line Mux", "Line 2", "RINPUT2" },
+	{ "Right Line Mux", "PGA", "Right PGA Mux" },
+	{ "Right Line Mux", "Differential", "Differential Mux" },
+
+	{ "Left Out 1", NULL, "Left DAC" },
+	{ "Right Out 1", NULL, "Right DAC" },
+	{ "Left Out 2", NULL, "Left DAC" },
+	{ "Right Out 2", NULL, "Right DAC" },
+
+	{ "Left Mixer", "Playback Switch", "Left DAC" },
+	{ "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
+	{ "Left Mixer", "Right Playback Switch", "Right DAC" },
+	{ "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
+
+	{ "Right Mixer", "Left Playback Switch", "Left DAC" },
+	{ "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
+	{ "Right Mixer", "Playback Switch", "Right DAC" },
+	{ "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
+
+	{ "DAC DIG", NULL, "DAC STM" },
+	{ "DAC DIG", NULL, "DAC Vref" },
+	{ "DAC DIG", NULL, "DAC DLL" },
+
+	{ "Left DAC", NULL, "DAC DIG" },
+	{ "Right DAC", NULL, "DAC DIG" },
+
+	{ "Left Out 1", NULL, "Left Mixer" },
+	{ "LOUT1", NULL, "Left Out 1" },
+	{ "Right Out 1", NULL, "Right Mixer" },
+	{ "ROUT1", NULL, "Right Out 1" },
+
+	{ "Left Out 2", NULL, "Left Mixer" },
+	{ "LOUT2", NULL, "Left Out 2" },
+	{ "Right Out 2", NULL, "Right Mixer" },
+	{ "ROUT2", NULL, "Right Out 2" },
+};
+
+static int es8388_mute(struct snd_soc_dai *dai, int mute, int direction)
+{
+	return snd_soc_component_update_bits(dai->component, ES8388_DACCONTROL3,
+			ES8388_DACCONTROL3_DACMUTE,
+			mute ? ES8388_DACCONTROL3_DACMUTE : 0);
+}
+
+static int es8388_startup(struct snd_pcm_substream *substream,
+			  struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *component = dai->component;
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+
+	if (es8388->master && es8388->sysclk_constraints)
+		snd_pcm_hw_constraint_list(substream->runtime, 0,
+				SNDRV_PCM_HW_PARAM_RATE,
+				es8388->sysclk_constraints);
+
+	return 0;
+}
+
+static int es8388_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params,
+	struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *component = dai->component;
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+	int i;
+	int reg;
+	int wl;
+	int ratio;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		reg = ES8388_DACCONTROL2;
+	else
+		reg = ES8388_ADCCONTROL5;
+
+	if (es8388->master) {
+		if (!es8388->sysclk_constraints) {
+			dev_err(component->dev, "No MCLK configured\n");
+			return -EINVAL;
+		}
+
+		for (i = 0; i < es8388->sysclk_constraints->count; i++)
+			if (es8388->sysclk_constraints->list[i] ==
+			    params_rate(params))
+				break;
+
+		if (i == es8388->sysclk_constraints->count) {
+			dev_err(component->dev,
+				"LRCLK %d unsupported with current clock\n",
+				params_rate(params));
+			return -EINVAL;
+		}
+		ratio = es8388->mclk_ratios[i];
+	} else {
+		ratio = 0;
+		es8388->mclkdiv2 = 0;
+	}
+
+	snd_soc_component_update_bits(component, ES8388_MASTERMODE,
+			ES8388_MASTERMODE_MCLKDIV2,
+			es8388->mclkdiv2 ? ES8388_MASTERMODE_MCLKDIV2 : 0);
+
+	switch (params_width(params)) {
+	case 16:
+		wl = 3;
+		break;
+	case 18:
+		wl = 2;
+		break;
+	case 20:
+		wl = 1;
+		break;
+	case 24:
+		wl = 0;
+		break;
+	case 32:
+		wl = 4;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		snd_soc_component_update_bits(component, ES8388_DACCONTROL1,
+				ES8388_DACCONTROL1_DACWL_MASK,
+				wl << ES8388_DACCONTROL1_DACWL_SHIFT);
+
+		es8388->playback_fs = params_rate(params);
+		es8388_set_deemph(component);
+	} else
+		snd_soc_component_update_bits(component, ES8388_ADCCONTROL4,
+				ES8388_ADCCONTROL4_ADCWL_MASK,
+				wl << ES8388_ADCCONTROL4_ADCWL_SHIFT);
+
+	return snd_soc_component_update_bits(component, reg, ES8388_RATEMASK, ratio);
+}
+
+static int es8388_set_sysclk(struct snd_soc_dai *codec_dai,
+		int clk_id, unsigned int freq, int dir)
+{
+	struct snd_soc_component *component = codec_dai->component;
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+	int mclkdiv2 = 0;
+
+	switch (freq) {
+	case 0:
+		es8388->sysclk_constraints = NULL;
+		es8388->mclk_ratios = NULL;
+		break;
+	case 22579200:
+		mclkdiv2 = 1;
+		/* fallthru */
+	case 11289600:
+		es8388->sysclk_constraints = &constraints_11289;
+		es8388->mclk_ratios = ratios_11289;
+		break;
+	case 24576000:
+		mclkdiv2 = 1;
+		/* fallthru */
+	case 12288000:
+		es8388->sysclk_constraints = &constraints_12288;
+		es8388->mclk_ratios = ratios_12288;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	es8388->mclkdiv2 = mclkdiv2;
+	return 0;
+}
+
+static int es8388_set_dai_fmt(struct snd_soc_dai *codec_dai,
+		unsigned int fmt)
+{
+	struct snd_soc_component *component = codec_dai->component;
+	struct es8388_priv *es8388 = snd_soc_component_get_drvdata(component);
+	u8 dac_mode = 0;
+	u8 adc_mode = 0;
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		/* Master serial port mode, with BCLK generated automatically */
+		snd_soc_component_update_bits(component, ES8388_MASTERMODE,
+				    ES8388_MASTERMODE_MSC,
+				    ES8388_MASTERMODE_MSC);
+		es8388->master = true;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		/* Slave serial port mode */
+		snd_soc_component_update_bits(component, ES8388_MASTERMODE,
+				    ES8388_MASTERMODE_MSC, 0);
+		es8388->master = false;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* interface format */
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		dac_mode |= ES8388_DACCONTROL1_DACFORMAT_I2S;
+		adc_mode |= ES8388_ADCCONTROL4_ADCFORMAT_I2S;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		dac_mode |= ES8388_DACCONTROL1_DACFORMAT_RJUST;
+		adc_mode |= ES8388_ADCCONTROL4_ADCFORMAT_RJUST;
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		dac_mode |= ES8388_DACCONTROL1_DACFORMAT_LJUST;
+		adc_mode |= ES8388_ADCCONTROL4_ADCFORMAT_LJUST;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* clock inversion */
+	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
+		return -EINVAL;
+
+	snd_soc_component_update_bits(component, ES8388_DACCONTROL1,
+			ES8388_DACCONTROL1_DACFORMAT_MASK, dac_mode);
+	snd_soc_component_update_bits(component, ES8388_ADCCONTROL4,
+			ES8388_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
+
+	return 0;
+}
+
+static int es8388_set_bias_level(struct snd_soc_component *component,
+				 enum snd_soc_bias_level level)
+{
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		break;
+
+	case SND_SOC_BIAS_PREPARE:
+		/* VREF, VMID=2x50k, digital enabled */
+		snd_soc_component_write(component, ES8388_CHIPPOWER, 0);
+		snd_soc_component_update_bits(component, ES8388_CONTROL1,
+				ES8388_CONTROL1_VMIDSEL_MASK |
+				ES8388_CONTROL1_ENREF,
+				ES8388_CONTROL1_VMIDSEL_50k |
+				ES8388_CONTROL1_ENREF);
+		break;
+
+	case SND_SOC_BIAS_STANDBY:
+		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
+			snd_soc_component_update_bits(component, ES8388_CONTROL1,
+					ES8388_CONTROL1_VMIDSEL_MASK |
+					ES8388_CONTROL1_ENREF,
+					ES8388_CONTROL1_VMIDSEL_5k |
+					ES8388_CONTROL1_ENREF);
+
+			/* Charge caps */
+			msleep(100);
+		}
+
+		snd_soc_component_write(component, ES8388_CONTROL2,
+				ES8388_CONTROL2_OVERCURRENT_ON |
+				ES8388_CONTROL2_THERMAL_SHUTDOWN_ON);
+
+		/* VREF, VMID=2*500k, digital stopped */
+		snd_soc_component_update_bits(component, ES8388_CONTROL1,
+				ES8388_CONTROL1_VMIDSEL_MASK |
+				ES8388_CONTROL1_ENREF,
+				ES8388_CONTROL1_VMIDSEL_500k |
+				ES8388_CONTROL1_ENREF);
+		break;
+
+	case SND_SOC_BIAS_OFF:
+		snd_soc_component_update_bits(component, ES8388_CONTROL1,
+				ES8388_CONTROL1_VMIDSEL_MASK |
+				ES8388_CONTROL1_ENREF,
+				0);
+		break;
+	}
+	return 0;
+}
+
+static const struct snd_soc_dai_ops es8388_dai_ops = {
+	.startup	= es8388_startup,
+	.hw_params	= es8388_hw_params,
+	.mute_stream = es8388_mute,
+	.set_sysclk	= es8388_set_sysclk,
+	.set_fmt	= es8388_set_dai_fmt,
+};
+
+static struct snd_soc_dai_driver es8388_dai = {
+	.name = "es8388-hifi",
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = ES8388_RATES,
+		.formats = ES8388_FORMATS,
+	},
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = ES8388_RATES,
+		.formats = ES8388_FORMATS,
+	},
+	.ops = &es8388_dai_ops,
+	.symmetric_rates = 1,
+};
+
+static int es8388_suspend(struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static int es8388_resume(struct snd_soc_component *component)
+{
+	struct regmap *regmap = dev_get_regmap(component->dev, NULL);
+	struct es8388_priv *es8388;
+	int ret;
+
+	es8388 = snd_soc_component_get_drvdata(component);
+
+	regcache_mark_dirty(regmap);
+	ret = regcache_sync(regmap);
+	if (ret) {
+		dev_err(component->dev, "unable to sync regcache\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int es8388_component_probe(struct snd_soc_component *component)
+{
+	snd_soc_component_write(component, ES8388_ADCPOWER, 0xf0);
+	snd_soc_component_write(component, ES8388_CONTROL1, 0x30);
+	snd_soc_component_write(component, ES8388_DACCONTROL21, 0x80);
+	snd_soc_component_write(component, ES8388_ADCCONTROL10, 0xda);
+
+	return 0;
+}
+
+static void es8388_remove(struct snd_soc_component *component)
+{
+}
+
+const struct regmap_config es8388_regmap_config = {
+	.reg_bits	= 8,
+	.val_bits	= 8,
+	.max_register	= ES8388_REG_MAX,
+	.cache_type	= REGCACHE_RBTREE,
+	.use_single_read = true,
+	.use_single_write = true,
+};
+EXPORT_SYMBOL_GPL(es8388_regmap_config);
+
+static const struct snd_soc_component_driver es8388_component_driver = {
+	.probe			= es8388_component_probe,
+	.remove			= es8388_remove,
+	.suspend		= es8388_suspend,
+	.resume			= es8388_resume,
+	.set_bias_level		= es8388_set_bias_level,
+	.controls		= es8388_snd_controls,
+	.num_controls		= ARRAY_SIZE(es8388_snd_controls),
+	.dapm_widgets		= es8388_dapm_widgets,
+	.num_dapm_widgets	= ARRAY_SIZE(es8388_dapm_widgets),
+	.dapm_routes		= es8388_dapm_routes,
+	.num_dapm_routes	= ARRAY_SIZE(es8388_dapm_routes),
+	.suspend_bias_off	= 1,
+	.idle_bias_on		= 1,
+	.use_pmdown_time	= 1,
+	.endianness		= 1,
+	.non_legacy_dai_naming	= 1,
+};
+
+int es8388_probe(struct device *dev, struct regmap *regmap)
+{
+	struct es8388_priv *es8388;
+
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	es8388 = devm_kzalloc(dev, sizeof(*es8388), GFP_KERNEL);
+	if (es8388 == NULL)
+		return -ENOMEM;
+
+	es8388->regmap = regmap;
+
+	dev_set_drvdata(dev, es8388);
+
+	return devm_snd_soc_register_component(dev,
+			&es8388_component_driver, &es8388_dai, 1);
+}
+EXPORT_SYMBOL_GPL(es8388_probe);
+
+static const struct i2c_device_id es8388_id[] = {
+	{ "es8388", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, es8388_id);
+
+static const struct of_device_id es8388_of_match[] = {
+	{ .compatible = "everest,es8388", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, es8388_of_match);
+
+static struct acpi_device_id es8388_acpi_match[] = {
+	{"ESSX8388", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(acpi, es8388_acpi_match);
+
+static int es8388_i2c_probe(struct i2c_client *i2c,
+			    const struct i2c_device_id *id)
+{
+	return es8388_probe(&i2c->dev,
+			devm_regmap_init_i2c(i2c, &es8388_regmap_config));
+}
+
+static struct i2c_driver es8388_i2c_driver = {
+	.driver = {
+		.name		= "es8388",
+		.of_match_table = es8388_of_match,
+		.acpi_match_table = es8388_acpi_match,
+	},
+	.probe    = es8388_i2c_probe,
+	.id_table = es8388_id,
+};
+
+module_i2c_driver(es8388_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC ES8388 driver");
+MODULE_AUTHOR("Yiqun Zhang <zhangyiqun@phytium.com.cn>");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/sound/soc/codecs/es8388.h b/target/linux/phytium/files-5.10/sound/soc/codecs/es8388.h
new file mode 100644
index 00000000000000..5858a71261fba6
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/codecs/es8388.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * es8388.h  --  ES8388 ALSA SoC Audio driver
+ */
+
+#ifndef _ES8388_H
+#define _ES8388_H
+
+#include <linux/regmap.h>
+
+struct device;
+
+extern const struct regmap_config es8388_regmap_config;
+int es8388_probe(struct device *dev, struct regmap *regmap);
+
+#define ES8388_DACLVOL 46
+#define ES8388_DACRVOL 47
+#define ES8388_DACCTL 28
+#define ES8388_RATEMASK (0x1f << 0)
+
+#define ES8388_CONTROL1		0x00
+#define ES8388_CONTROL1_VMIDSEL_OFF (0 << 0)
+#define ES8388_CONTROL1_VMIDSEL_50k (1 << 0)
+#define ES8388_CONTROL1_VMIDSEL_500k (2 << 0)
+#define ES8388_CONTROL1_VMIDSEL_5k (3 << 0)
+#define ES8388_CONTROL1_VMIDSEL_MASK (3 << 0)
+#define ES8388_CONTROL1_ENREF (1 << 2)
+#define ES8388_CONTROL1_SEQEN (1 << 3)
+#define ES8388_CONTROL1_SAMEFS (1 << 4)
+#define ES8388_CONTROL1_DACMCLK_ADC (0 << 5)
+#define ES8388_CONTROL1_DACMCLK_DAC (1 << 5)
+#define ES8388_CONTROL1_LRCM (1 << 6)
+#define ES8388_CONTROL1_SCP_RESET (1 << 7)
+
+#define ES8388_CONTROL2		0x01
+#define ES8388_CONTROL2_VREF_BUF_OFF (1 << 0)
+#define ES8388_CONTROL2_VREF_LOWPOWER (1 << 1)
+#define ES8388_CONTROL2_IBIASGEN_OFF (1 << 2)
+#define ES8388_CONTROL2_ANALOG_OFF (1 << 3)
+#define ES8388_CONTROL2_VREF_BUF_LOWPOWER (1 << 4)
+#define ES8388_CONTROL2_VCM_MOD_LOWPOWER (1 << 5)
+#define ES8388_CONTROL2_OVERCURRENT_ON (1 << 6)
+#define ES8388_CONTROL2_THERMAL_SHUTDOWN_ON (1 << 7)
+
+#define ES8388_CHIPPOWER	0x02
+#define ES8388_CHIPPOWER_DACVREF_OFF 0
+#define ES8388_CHIPPOWER_ADCVREF_OFF 1
+#define ES8388_CHIPPOWER_DACDLL_OFF 2
+#define ES8388_CHIPPOWER_ADCDLL_OFF 3
+#define ES8388_CHIPPOWER_DACSTM_RESET 4
+#define ES8388_CHIPPOWER_ADCSTM_RESET 5
+#define ES8388_CHIPPOWER_DACDIG_OFF 6
+#define ES8388_CHIPPOWER_ADCDIG_OFF 7
+
+#define ES8388_ADCPOWER		0x03
+#define ES8388_ADCPOWER_INT1_LOWPOWER 0
+#define ES8388_ADCPOWER_FLASH_ADC_LOWPOWER 1
+#define ES8388_ADCPOWER_ADC_BIAS_GEN_OFF 2
+#define ES8388_ADCPOWER_MIC_BIAS_OFF 3
+#define ES8388_ADCPOWER_ADCR_OFF 4
+#define ES8388_ADCPOWER_ADCL_OFF 5
+#define ES8388_ADCPOWER_AINR_OFF 6
+#define ES8388_ADCPOWER_AINL_OFF 7
+
+#define ES8388_DACPOWER		0x04
+#define ES8388_DACPOWER_OUT3_ON 0
+#define ES8388_DACPOWER_MONO_ON 1
+#define ES8388_DACPOWER_ROUT2_ON 2
+#define ES8388_DACPOWER_LOUT2_ON 3
+#define ES8388_DACPOWER_ROUT1_ON 4
+#define ES8388_DACPOWER_LOUT1_ON 5
+#define ES8388_DACPOWER_RDAC_OFF 6
+#define ES8388_DACPOWER_LDAC_OFF 7
+
+#define ES8388_CHIPLOPOW1	0x05
+#define ES8388_CHIPLOPOW2	0x06
+#define ES8388_ANAVOLMANAG	0x07
+
+#define ES8388_MASTERMODE	0x08
+#define ES8388_MASTERMODE_BCLKDIV (0 << 0)
+#define ES8388_MASTERMODE_BCLK_INV (1 << 5)
+#define ES8388_MASTERMODE_MCLKDIV2 (1 << 6)
+#define ES8388_MASTERMODE_MSC (1 << 7)
+
+#define ES8388_ADCCONTROL1	0x09
+#define ES8388_ADCCONTROL2	0x0a
+#define ES8388_ADCCONTROL3	0x0b
+
+#define ES8388_ADCCONTROL4	0x0c
+#define ES8388_ADCCONTROL4_ADCFORMAT_MASK (3 << 0)
+#define ES8388_ADCCONTROL4_ADCFORMAT_I2S (0 << 0)
+#define ES8388_ADCCONTROL4_ADCFORMAT_LJUST (1 << 0)
+#define ES8388_ADCCONTROL4_ADCFORMAT_RJUST (2 << 0)
+#define ES8388_ADCCONTROL4_ADCFORMAT_PCM (3 << 0)
+#define ES8388_ADCCONTROL4_ADCWL_SHIFT 2
+#define ES8388_ADCCONTROL4_ADCWL_MASK (7 << 2)
+#define ES8388_ADCCONTROL4_ADCLRP_I2S_POL_NORMAL (0 << 5)
+#define ES8388_ADCCONTROL4_ADCLRP_I2S_POL_INV (1 << 5)
+#define ES8388_ADCCONTROL4_ADCLRP_PCM_MSB_CLK2 (0 << 5)
+#define ES8388_ADCCONTROL4_ADCLRP_PCM_MSB_CLK1 (1 << 5)
+
+#define ES8388_ADCCONTROL5	0x0d
+#define ES8388_ADCCONTROL5_RATEMASK (0x1f << 0)
+
+#define ES8388_ADCCONTROL6	0x0e
+
+#define ES8388_ADCCONTROL7	0x0f
+#define ES8388_ADCCONTROL7_ADC_MUTE (1 << 2)
+#define ES8388_ADCCONTROL7_ADC_LER (1 << 3)
+#define ES8388_ADCCONTROL7_ADC_ZERO_CROSS (1 << 4)
+#define ES8388_ADCCONTROL7_ADC_SOFT_RAMP (1 << 5)
+#define ES8388_ADCCONTROL7_ADC_RAMP_RATE_4 (0 << 6)
+#define ES8388_ADCCONTROL7_ADC_RAMP_RATE_8 (1 << 6)
+#define ES8388_ADCCONTROL7_ADC_RAMP_RATE_16 (2 << 6)
+#define ES8388_ADCCONTROL7_ADC_RAMP_RATE_32 (3 << 6)
+
+#define ES8388_ADCCONTROL8	0x10
+#define ES8388_ADCCONTROL9	0x11
+#define ES8388_ADCCONTROL10	0x12
+#define ES8388_ADCCONTROL11	0x13
+#define ES8388_ADCCONTROL12	0x14
+#define ES8388_ADCCONTROL13	0x15
+#define ES8388_ADCCONTROL14	0x16
+
+#define ES8388_DACCONTROL1	0x17
+#define ES8388_DACCONTROL1_DACFORMAT_MASK (3 << 1)
+#define ES8388_DACCONTROL1_DACFORMAT_I2S (0 << 1)
+#define ES8388_DACCONTROL1_DACFORMAT_LJUST (1 << 1)
+#define ES8388_DACCONTROL1_DACFORMAT_RJUST (2 << 1)
+#define ES8388_DACCONTROL1_DACFORMAT_PCM (3 << 1)
+#define ES8388_DACCONTROL1_DACWL_SHIFT 3
+#define ES8388_DACCONTROL1_DACWL_MASK (7 << 3)
+#define ES8388_DACCONTROL1_DACLRP_I2S_POL_NORMAL (0 << 6)
+#define ES8388_DACCONTROL1_DACLRP_I2S_POL_INV (1 << 6)
+#define ES8388_DACCONTROL1_DACLRP_PCM_MSB_CLK2 (0 << 6)
+#define ES8388_DACCONTROL1_DACLRP_PCM_MSB_CLK1 (1 << 6)
+#define ES8388_DACCONTROL1_LRSWAP (1 << 7)
+
+#define ES8388_DACCONTROL2	0x18
+#define ES8388_DACCONTROL2_RATEMASK (0x1f << 0)
+#define ES8388_DACCONTROL2_DOUBLESPEED (1 << 5)
+
+#define ES8388_DACCONTROL3	0x19
+#define ES8388_DACCONTROL3_AUTOMUTE (1 << 2)
+#define ES8388_DACCONTROL3_DACMUTE (1 << 2)
+#define ES8388_DACCONTROL3_LEFTGAINVOL (1 << 3)
+#define ES8388_DACCONTROL3_DACZEROCROSS (1 << 4)
+#define ES8388_DACCONTROL3_DACSOFTRAMP (1 << 5)
+#define ES8388_DACCONTROL3_DACRAMPRATE (3 << 6)
+
+#define ES8388_LDACVOL 0x1a
+#define ES8388_LDACVOL_MASK (0 << 0)
+#define ES8388_LDACVOL_MAX (0xc0)
+
+#define ES8388_RDACVOL 0x1b
+#define ES8388_RDACVOL_MASK (0 << 0)
+#define ES8388_RDACVOL_MAX (0xc0)
+
+#define ES8388_DACVOL_MAX (0xc0)
+
+#define ES8388_DACCONTROL4	0x1a
+#define ES8388_DACCONTROL5	0x1b
+
+#define ES8388_DACCONTROL6	0x1c
+#define ES8388_DACCONTROL6_CLICKFREE (1 << 3)
+#define ES8388_DACCONTROL6_DAC_INVR (1 << 4)
+#define ES8388_DACCONTROL6_DAC_INVL (1 << 5)
+#define ES8388_DACCONTROL6_DEEMPH_MASK (3 << 6)
+#define ES8388_DACCONTROL6_DEEMPH_OFF (0 << 6)
+#define ES8388_DACCONTROL6_DEEMPH_32k (1 << 6)
+#define ES8388_DACCONTROL6_DEEMPH_44_1k (2 << 6)
+#define ES8388_DACCONTROL6_DEEMPH_48k (3 << 6)
+
+#define ES8388_DACCONTROL7	0x1d
+#define ES8388_DACCONTROL7_VPP_SCALE_3p5	(0 << 0)
+#define ES8388_DACCONTROL7_VPP_SCALE_4p0	(1 << 0)
+#define ES8388_DACCONTROL7_VPP_SCALE_3p0	(2 << 0)
+#define ES8388_DACCONTROL7_VPP_SCALE_2p5	(3 << 0)
+#define ES8388_DACCONTROL7_SHELVING_STRENGTH (1 << 2) /* In eights */
+#define ES8388_DACCONTROL7_MONO		(1 << 5)
+#define ES8388_DACCONTROL7_ZEROR	(1 << 6)
+#define ES8388_DACCONTROL7_ZEROL	(1 << 7)
+
+/* Shelving filter */
+#define ES8388_DACCONTROL8	0x1e
+#define ES8388_DACCONTROL9	0x1f
+#define ES8388_DACCONTROL10	0x20
+#define ES8388_DACCONTROL11	0x21
+#define ES8388_DACCONTROL12	0x22
+#define ES8388_DACCONTROL13	0x23
+#define ES8388_DACCONTROL14	0x24
+#define ES8388_DACCONTROL15	0x25
+
+#define ES8388_DACCONTROL16	0x26
+#define ES8388_DACCONTROL16_RMIXSEL_RIN1 (0 << 0)
+#define ES8388_DACCONTROL16_RMIXSEL_RIN2 (1 << 0)
+#define ES8388_DACCONTROL16_RMIXSEL_RIN3 (2 << 0)
+#define ES8388_DACCONTROL16_RMIXSEL_RADC (3 << 0)
+#define ES8388_DACCONTROL16_LMIXSEL_LIN1 (0 << 3)
+#define ES8388_DACCONTROL16_LMIXSEL_LIN2 (1 << 3)
+#define ES8388_DACCONTROL16_LMIXSEL_LIN3 (2 << 3)
+#define ES8388_DACCONTROL16_LMIXSEL_LADC (3 << 3)
+
+#define ES8388_DACCONTROL17	0x27
+#define ES8388_DACCONTROL17_LI2LOVOL (7 << 3)
+#define ES8388_DACCONTROL17_LI2LO (1 << 6)
+#define ES8388_DACCONTROL17_LD2LO (1 << 7)
+
+#define ES8388_DACCONTROL18	0x28
+#define ES8388_DACCONTROL18_RI2LOVOL (7 << 3)
+#define ES8388_DACCONTROL18_RI2LO (1 << 6)
+#define ES8388_DACCONTROL18_RD2LO (1 << 7)
+
+#define ES8388_DACCONTROL19	0x29
+#define ES8388_DACCONTROL19_LI2ROVOL (7 << 3)
+#define ES8388_DACCONTROL19_LI2RO (1 << 6)
+#define ES8388_DACCONTROL19_LD2RO (1 << 7)
+
+#define ES8388_DACCONTROL20	0x2a
+#define ES8388_DACCONTROL20_RI2ROVOL (7 << 3)
+#define ES8388_DACCONTROL20_RI2RO (1 << 6)
+#define ES8388_DACCONTROL20_RD2RO (1 << 7)
+
+#define ES8388_DACCONTROL21	0x2b
+#define ES8388_DACCONTROL21_LI2MOVOL (7 << 3)
+#define ES8388_DACCONTROL21_LI2MO (1 << 6)
+#define ES8388_DACCONTROL21_LD2MO (1 << 7)
+
+#define ES8388_DACCONTROL22	0x2c
+#define ES8388_DACCONTROL22_RI2MOVOL (7 << 3)
+#define ES8388_DACCONTROL22_RI2MO (1 << 6)
+#define ES8388_DACCONTROL22_RD2MO (1 << 7)
+
+#define ES8388_DACCONTROL23	0x2d
+#define ES8388_DACCONTROL23_MOUTINV		(1 << 1)
+#define ES8388_DACCONTROL23_HPSWPOL		(1 << 2)
+#define ES8388_DACCONTROL23_HPSWEN		(1 << 3)
+#define ES8388_DACCONTROL23_VROI_1p5k		(0 << 4)
+#define ES8388_DACCONTROL23_VROI_40k		(1 << 4)
+#define ES8388_DACCONTROL23_OUT3_VREF		(0 << 5)
+#define ES8388_DACCONTROL23_OUT3_ROUT1		(1 << 5)
+#define ES8388_DACCONTROL23_OUT3_MONOOUT	(2 << 5)
+#define ES8388_DACCONTROL23_OUT3_RIGHT_MIXER	(3 << 5)
+#define ES8388_DACCONTROL23_ROUT2INV		(1 << 7)
+
+/* LOUT1 Amplifier */
+#define ES8388_LOUT1VOL 0x2e
+#define ES8388_LOUT1VOL_MASK (0 << 5)
+#define ES8388_LOUT1VOL_MAX (0x24)
+
+/* ROUT1 Amplifier */
+#define ES8388_ROUT1VOL 0x2f
+#define ES8388_ROUT1VOL_MASK (0 << 5)
+#define ES8388_ROUT1VOL_MAX (0x24)
+
+#define ES8388_OUT1VOL_MAX (0x24)
+
+/* LOUT2 Amplifier */
+#define ES8388_LOUT2VOL 0x30
+#define ES8388_LOUT2VOL_MASK (0 << 5)
+#define ES8388_LOUT2VOL_MAX (0x24)
+
+/* ROUT2 Amplifier */
+#define ES8388_ROUT2VOL 0x31
+#define ES8388_ROUT2VOL_MASK (0 << 5)
+#define ES8388_ROUT2VOL_MAX (0x24)
+
+#define ES8388_OUT2VOL_MAX (0x24)
+
+/* Mono Out Amplifier */
+#define ES8388_MONOOUTVOL 0x32
+#define ES8388_MONOOUTVOL_MASK (0 << 5)
+#define ES8388_MONOOUTVOL_MAX (0x24)
+
+#define ES8388_DACCONTROL29	0x33
+#define ES8388_DACCONTROL30	0x34
+
+#define ES8388_SYSCLK		0
+
+#define ES8388_REG_MAX		0x35
+
+#define ES8388_1536FS		1536
+#define ES8388_1024FS		1024
+#define ES8388_768FS		768
+#define ES8388_512FS		512
+#define ES8388_384FS		384
+#define ES8388_256FS		256
+#define ES8388_128FS		128
+
+#endif
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/Kconfig b/target/linux/phytium/files-5.10/sound/soc/phytium/Kconfig
new file mode 100755
index 00000000000000..8769ed7ccf92dd
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/Kconfig
@@ -0,0 +1,30 @@
+config SND_SOC_PHYTIUM_I2S
+	tristate "Phytium I2S Device Driver"
+	help
+	 Say Y or M if you want to add support for I2S driver for
+	 Phytium I2S device . The device supports 2 channels each
+	 for play and record.
+
+config SND_PMDK_ES8388
+	tristate "Phytium machine support with ES8388"
+	depends on I2C && SND_SOC_PHYTIUM_I2S
+	select SND_SOC_ES8388
+	help
+	 Say Y if you want to add Phytium machine support for
+	 ES8388 codecs.
+
+config SND_PMDK_ES8336
+	tristate "Phytium machine support with ES8336"
+	depends on I2C && SND_SOC_PHYTIUM_I2S
+	select SND_SOC_ES8336
+	help
+	 Say Y if you want to add Phytium machine support for
+	 ES8336 codecs.
+
+config SND_PMDK_DP
+	tristate "Phytium machine support with DP"
+	depends on I2C && SND_SOC_PHYTIUM_I2S
+	select SND_SOC_HDMI_CODEC
+	help
+	 Say Y if you want to add Phytium machine support for
+	 Displayport.
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/Makefile b/target/linux/phytium/files-5.10/sound/soc/phytium/Makefile
new file mode 100644
index 00000000000000..db3c0659e84428
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/Makefile
@@ -0,0 +1,13 @@
+# PHYTIUM Platform Support
+
+snd-soc-phytium-i2s-objs :=phytium_i2s.o
+obj-$(CONFIG_SND_SOC_PHYTIUM_I2S) += snd-soc-phytium-i2s.o
+
+snd-soc-pmdk-es8388-objs :=pmdk_es8388.o
+obj-$(CONFIG_SND_PMDK_ES8388) += snd-soc-pmdk-es8388.o
+
+snd-soc-pmdk-es8336-objs :=pmdk_es8336.o
+obj-$(CONFIG_SND_PMDK_ES8336) += snd-soc-pmdk-es8336.o
+
+snd-soc-pmdk-dp-objs :=pmdk_dp.o
+obj-$(CONFIG_SND_PMDK_DP) += snd-soc-pmdk-dp.o
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/local.h b/target/linux/phytium/files-5.10/sound/soc/phytium/local.h
new file mode 100644
index 00000000000000..3076a9588c5c89
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/local.h
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PHYTIUM_I2S_LOCAL_H
+#define __PHYTIUM_I2S_LOCAL_H
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <sound/pcm.h>
+
+/* I2S clk setting*/
+#define CLK_CFG0	0xc00
+#define CLK_CFG1	0xc04
+
+/* common register for all channel */
+#define I2S_IER		0x000
+#define IRER		0x004
+#define ITER		0x008
+#define CER		0x00C
+
+#define RXFFR		0x014
+#define TXFFR		0x018
+
+/* Interrupt status register fields */
+#define ISR_TXFO	BIT(5)
+#define ISR_TXFE	BIT(4)
+#define ISR_RXFO	BIT(1)
+#define ISR_RXDA	BIT(0)
+
+/* I2STxRxRegisters for all channels */
+#define LRBR_LTHR(x)	(0x40 * x + 0x020)
+#define RRBR_RTHR(x)	(0x40 * x + 0x024)
+#define RER(x)		(0x40 * x + 0x028)
+
+#define RCR(x)		(0x40 * x + 0x030)
+
+#define ISR(x)		(0x40 * x + 0x038)
+#define IMR(x)		(0x40 * x + 0x03C)
+#define ROR(x)		(0x40 * x + 0x040)
+#define TOR(x)		(0x40 * x + 0x044)
+#define RFCR(x)		(0x40 * x + 0x048)
+#define TFCR(x)		(0x40 * x + 0x04C)
+#define RFF(x)		(0x40 * x + 0x050)
+#define TFF(x)		(0x40 * x + 0x054)
+
+/*enable txd and rxd block channel0~3 */
+#define TER(x)		(0x40 * x + 0x02C)
+#define CCR		0x010
+#define TCR(x)		(0x40 * x + 0x034)
+
+
+/* I2SCOMPRegisters */
+#define I2S_COMP_PARAM_2	0x01F0
+#define I2S_COMP_PARAM_1	0x01F4
+#define I2S_COMP_VERSION	0x01F8
+#define I2S_COMP_TYPE		0x01FC
+
+/***I2S AND DMA***/
+
+#define DMA_GCAP		0x0024
+
+#define DMA_CHAL_CONFG1		0x0028
+
+#define DMA_CHAL_CONFG0		0x0004
+#define DMA_MASK_INT		0x000c
+#define DMA_BDLPU(x)		(0x40 * x + 0x0040)
+#define DMA_BDLPL(x)		(0x40 * x + 0x0044)
+#define DMA_CHALX_DEV_ADDR(x)	(0x40 * x + 0x0048)
+#define DMA_CHALX_CBL(x)	(0x40 * x + 0x0054)
+#define DMA_CHALX_LVI(x)	(0x40 * x + 0x004c)
+
+#define DMA_CHALX_DSIZE(x)	(0x40 * x + 0x0064)
+#define DMA_CHALX_DLENTH(x)	(0x40 * x + 0x0068)
+#define DMA_CHALX_CTL(x)	(0x40 * x + 0x0058)
+
+
+#define DMA_CTL			0x0000
+
+#define DMA_LPIB(x)		(0x40 * x + 0x0050)
+
+#define DMA_STS			0x0008
+
+/****************/
+
+
+/* max number of fragments - we may use more if allocating more pages for BDL */
+#define BDL_SIZE		4096
+#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
+
+/*
+ * Component parameter register fields - define the I2S block's
+ * configuration.
+ */
+#define	COMP1_TX_WORDSIZE_3(r)	(((r) & GENMASK(27, 25)) >> 25)
+#define	COMP1_TX_WORDSIZE_2(r)	(((r) & GENMASK(24, 22)) >> 22)
+#define	COMP1_TX_WORDSIZE_1(r)	(((r) & GENMASK(21, 19)) >> 19)
+#define	COMP1_TX_WORDSIZE_0(r)	(((r) & GENMASK(18, 16)) >> 16)
+#define	COMP1_TX_CHANNELS(r)	(((r) & GENMASK(10, 9)) >> 9)
+#define	COMP1_RX_CHANNELS(r)	(((r) & GENMASK(8, 7)) >> 7)
+#define	COMP1_RX_ENABLED(r)	(((r) & BIT(6)) >> 6)
+#define	COMP1_TX_ENABLED(r)	(((r) & BIT(5)) >> 5)
+#define	COMP1_MODE_EN(r)	(((r) & BIT(4)) >> 4)
+#define	COMP1_FIFO_DEPTH_GLOBAL(r)	(((r) & GENMASK(3, 2)) >> 2)
+#define	COMP1_APB_DATA_WIDTH(r)	(((r) & GENMASK(1, 0)) >> 0)
+
+#define	COMP2_RX_WORDSIZE_3(r)	(((r) & GENMASK(12, 10)) >> 10)
+#define	COMP2_RX_WORDSIZE_2(r)	(((r) & GENMASK(9, 7)) >> 7)
+#define	COMP2_RX_WORDSIZE_1(r)	(((r) & GENMASK(5, 3)) >> 3)
+#define	COMP2_RX_WORDSIZE_0(r)	(((r) & GENMASK(2, 0)) >> 0)
+
+/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
+#define	COMP_MAX_WORDSIZE	(1 << 3)
+#define	COMP_MAX_DATA_WIDTH	(1 << 2)
+
+#define MAX_CHANNEL_NUM		8
+#define MIN_CHANNEL_NUM		2
+
+#define azx_bus(chip)	(&(chip)->bus.core)
+#define bus_to_azx(_bus)	container_of(_bus, struct azx, bus.core)
+
+#define I2S_UNSOL_QUEUE_SIZE	64
+#define I2S_MAX_CODECS		8	/* limit by controller side */
+
+
+#define azx_stream(dev)		(&(dev)->core)
+
+struct i2s_clk_config_data {
+	int chan_nr;
+	u32 data_width;
+	u32 sample_rate;
+};
+
+struct i2sc_bus {
+	struct device *dev;
+	const struct i2s_bus_ops *ops;
+	const struct i2s_io_ops *io_ops;
+	const struct i2s_ext_bus_ops *ext_ops;
+
+	/* h/w resources */
+	unsigned long addr;
+	void __iomem *remap_addr;
+	int irq;
+
+	/* codec linked list */
+	struct list_head codec_list;
+	unsigned int num_codecs;
+
+	unsigned int unsol_rp, unsol_wp;
+	struct work_struct unsol_work;
+
+	struct snd_dma_buffer bdl0;
+	struct snd_dma_buffer bdl1;
+
+	/* i2s_stream linked list */
+	struct list_head stream_list;
+
+	bool reverse_assign;		/* assign devices in reverse order */
+
+	int bdl_pos_adj;		/* BDL position adjustment */
+
+	/* locks */
+	spinlock_t reg_lock;
+};
+
+struct i2s_bus {
+	struct i2sc_bus core;
+
+	struct snd_card *card;
+
+	struct pci_dev *pci;
+
+	struct mutex prepare_mutex;
+};
+
+
+/*
+ * i2s stream
+ */
+struct i2s_stream {
+	struct i2sc_bus *bus;
+	struct snd_dma_buffer bdl; /* BDL buffer */
+	__le32 *posbuf;		/* position buffer pointer */
+	int direction;		/* playback / capture (SNDRV_PCM_STREAM_*) */
+
+	unsigned int bufsize;	/* size of the play buffer in bytes */
+	unsigned int period_bytes; /* size of the period in bytes */
+	unsigned int frags;	/* number for period in the play buffer */
+	unsigned int fifo_size;	/* FIFO size */
+
+	void __iomem *sd_addr;	/* stream descriptor pointer */
+
+	u32 sd_int_sta_mask;	/* stream int status mask */
+
+	/* pcm support */
+	struct snd_pcm_substream *substream;	/* assigned substream,
+						 * set in PCM open
+						 */
+	unsigned int format_val;	/* format value to be set in the
+					 * controller and the codec
+					 */
+	unsigned char stream_tag;	/* assigned stream */
+	unsigned char index;		/* stream index */
+	int assigned_key;		/* last device# key assigned to */
+
+	bool opened;
+	bool running;
+	bool prepared;
+	bool no_period_wakeup;
+
+	int delay_negative_threshold;
+
+	struct list_head list;
+
+};
+
+
+struct azx_dev {
+	struct i2s_stream core;
+	unsigned int irq_pending:1;
+};
+
+
+
+/* PCM setup */
+static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
+{
+	return substream->runtime->private_data;
+}
+
+
+#define AZX_MAX_CODECS		HDA_MAX_CODECS
+#define AZX_DEFAULT_CODECS	4
+
+#define stream_to_azx_dev(s)	container_of(s, struct azx_dev, core)
+
+struct azx;
+
+struct i2s_controller_ops {
+	int (*substream_alloc_pages)(struct azx *chip,
+				     struct snd_pcm_substream *substream,
+				     size_t size);
+	int (*substream_free_pages)(struct azx *chip,
+				    struct snd_pcm_substream *substream);
+	int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
+};
+
+struct i2s_io_ops {
+	int (*dma_alloc_pages)(struct i2sc_bus *bus, int type, size_t size,
+			       struct snd_dma_buffer *buf);
+	void (*dma_free_pages)(struct i2sc_bus *bus,
+			       struct snd_dma_buffer *buf);
+};
+
+struct azx {
+	struct i2s_bus bus;
+
+	struct snd_card *card;
+	struct pci_dev *pci;
+	int dev_index;
+
+	int playback_streams;
+	int playback_index_offset;
+	int capture_streams;
+	int capture_index_offset;
+	int num_streams;
+
+	/* Register interaction. */
+	const struct i2s_controller_ops *ops;
+
+	/* locks */
+	struct mutex open_mutex; /* Prevents concurrent open/close operations */
+
+	/* PCM */
+	struct list_head pcm_list; /* azx_pcm list */
+
+	/* flags */
+	int bdl_pos_adj;
+	unsigned int running:1;
+	unsigned int region_requested:1;
+	unsigned int disabled:1;
+};
+struct i2s_phytium {
+	struct azx chip;
+	struct snd_pcm_substream *substream;
+	struct device *dev;
+	struct device *pdev;
+	u32 paddr;
+	void __iomem *regs;
+	void __iomem *regs_db;
+	int irq_id;
+
+	/* for pending irqs */
+	struct work_struct irq_pending_work;
+
+	/* sync probing */
+	struct completion probe_wait;
+	struct work_struct probe_work;
+
+	/* extra flags */
+	unsigned int pcie:1;
+	unsigned int irq_pending_warned:1;
+	unsigned int probe_continued:1;
+	unsigned int i2s_dp:1;
+
+	unsigned int i2s_reg_comp1;
+	unsigned int i2s_reg_comp2;
+	struct clk *clk;
+	unsigned int capability;
+	unsigned int quirks;
+	u32 fifo_th;
+	int active;
+	u32 xfer_resolution;
+	u32 ccr;
+	u32 clk_base;
+
+	struct i2s_clk_config_data config;
+
+	  /*azx_dev*/
+	struct i2s_stream core;
+};
+
+#define azx_alloc_stream_pages(chip) \
+	snd_i2s_bus_alloc_stream_pages(azx_bus(chip))
+
+#endif
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/phytium_i2s.c b/target/linux/phytium/files-5.10/sound/soc/phytium/phytium_i2s.c
new file mode 100755
index 00000000000000..2d028d36b5eb86
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/phytium_i2s.c
@@ -0,0 +1,1424 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium I2S ASoC driver
+ *
+ * Copyright (c) 2020-2023 Phytium Technology Co., Ltd.
+ *
+ * Derived from sound/soc/dwc/dwc-i2s.c
+ *    Copyright (C) 2010 ST Microelectronics
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+#include <linux/clocksource.h>
+#include <linux/random.h>
+#include <linux/timecounter.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <linux/pci.h>
+#include <linux/acpi.h>
+#include "local.h"
+
+#define NUM_CAPTURE	1
+#define NUM_PLAYBACK	1
+
+#define PHYTIUM_I2S_PLAY	(1 << 0)
+#define PHYTIUM_I2S_RECORD	(1 << 1)
+#define PHYTIUM_I2S_SLAVE	(1 << 2)
+#define PHYTIUM_I2S_MASTER	(1 << 3)
+
+#define PHYTIUM_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
+
+#define TWO_CHANNEL_SUPPORT	2	/* up to 2.0 */
+#define FOUR_CHANNEL_SUPPORT	4	/* up to 3.1 */
+#define SIX_CHANNEL_SUPPORT	6	/* up to 5.1 */
+#define EIGHT_CHANNEL_SUPPORT	8	/* up to 7.1 */
+
+struct pdata_px210_mfd {
+	struct device		*dev;
+	char *name;
+	int clk_base;
+};
+
+static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
+{
+	writel(val, io_base + reg);
+}
+
+static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
+{
+	return readl(io_base + reg);
+}
+
+static inline void i2s_disable_channels(struct i2s_phytium *dev, u32 stream)
+{
+	u32 i = 0;
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		for (i = 0; i < 4; i++)
+			i2s_write_reg(dev->regs, TER(i), 0);
+	} else {
+		for (i = 0; i < 4; i++)
+			i2s_write_reg(dev->regs, RER(i), 0);
+	}
+}
+
+static int substream_free_pages(struct azx *chip,
+				struct snd_pcm_substream *substream)
+{
+	return snd_pcm_lib_free_pages(substream);
+}
+
+static void stream_update(struct i2sc_bus *bus, struct i2s_stream *s)
+{
+	struct azx *chip = bus_to_azx(bus);
+
+	struct azx_dev *azx_dev = stream_to_azx_dev(s);
+
+	/* check whether this IRQ is really acceptable */
+	if (!chip->ops->position_check ||
+	    chip->ops->position_check(chip, azx_dev)) {
+		spin_unlock(&bus->reg_lock);
+		snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
+		spin_lock(&bus->reg_lock);
+	}
+
+}
+
+int snd_i2s_bus_handle_stream_irq(struct i2sc_bus *bus, unsigned int status,
+				    void (*ack)(struct i2sc_bus *,
+						struct i2s_stream *))
+{
+	struct i2s_stream *azx_dev;
+	u32 sd_status, qc_sd_status;
+	int handled = 0;
+
+	list_for_each_entry(azx_dev, &bus->stream_list, list) {
+
+		if (status & azx_dev->sd_int_sta_mask) {
+			sd_status = i2s_read_reg(azx_dev->sd_addr, DMA_STS);
+			i2s_write_reg(azx_dev->sd_addr, DMA_STS, azx_dev->sd_int_sta_mask);
+			qc_sd_status = i2s_read_reg(azx_dev->sd_addr, DMA_STS);
+			handled |= 1 << azx_dev->index;
+			azx_dev->running = 1;
+			if (!azx_dev->substream || !azx_dev->running ||
+			    !(sd_status & 0xffffffff)) {
+				continue;
+			}
+			if (ack)
+				ack(bus, azx_dev);
+		}
+	}
+	return handled;
+}
+
+irqreturn_t azx_i2s_interrupt(int irq, void *dev_id)
+{
+	struct azx *chip = dev_id;
+	struct i2sc_bus *bus = azx_bus(chip);
+	u32 status;
+	bool active, handled = false;
+	int repeat = 0; /* count for avoiding endless loop */
+
+	spin_lock(&bus->reg_lock);
+
+	if (chip->disabled)
+		goto unlock;
+
+	do {
+
+		status = i2s_read_reg(bus->remap_addr, DMA_STS);
+
+		if (status == 0)
+			break;
+
+		handled = true;
+		active = false;
+		if (snd_i2s_bus_handle_stream_irq(bus, status, stream_update))
+			active = true;
+
+
+	} while (active && ++repeat < 1);
+
+ unlock:
+	spin_unlock(&bus->reg_lock);
+
+	return IRQ_RETVAL(handled);
+}
+
+static int azx_acquire_irq(struct azx *chip, int do_disconnect)
+{
+	struct i2sc_bus *bus = azx_bus(chip);
+	struct i2s_phytium *i2s = container_of(chip, struct i2s_phytium, chip);
+	int err;
+
+	err = devm_request_irq(i2s->dev, i2s->irq_id, azx_i2s_interrupt, IRQF_SHARED,
+				"phytium i2s", chip);
+
+	if (err < 0) {
+		dev_err(i2s->dev, "failed to request irq\n");
+		return err;
+	}
+
+	bus->irq = i2s->irq_id;
+
+	return 0;
+}
+
+static void i2s_start(struct i2s_phytium *dev,
+		      struct snd_pcm_substream *substream)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->regs, ITER, 1);
+	else
+		i2s_write_reg(dev->regs, IRER, 1);
+
+	/*enable the clock*/
+	i2s_write_reg(dev->regs, CER, 1);
+
+	/*enable the i2s*/
+	i2s_write_reg(dev->regs, I2S_IER, 1);
+}
+
+static void i2s_stop(struct i2s_phytium *dev,
+		struct snd_pcm_substream *substream)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->regs, ITER, 0);
+	else
+		i2s_write_reg(dev->regs, IRER, 0);
+
+	if (!dev->active) {
+		i2s_write_reg(dev->regs, CER, 0);
+		i2s_write_reg(dev->regs, I2S_IER, 0);
+	}
+}
+
+static void phytium_i2s_config(struct i2s_phytium *dev, int stream)
+{
+	i2s_disable_channels(dev, stream);
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		i2s_write_reg(dev->regs, TCR(0), dev->xfer_resolution);
+		i2s_write_reg(dev->regs, TER(0), 1);
+	} else {
+		i2s_write_reg(dev->regs, RCR(0), dev->xfer_resolution);
+		i2s_write_reg(dev->regs, RER(0), 1);
+	}
+}
+
+static int phytium_i2s_hw_params(struct snd_pcm_substream *substream,
+		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(dai);
+	struct i2s_clk_config_data *config = &dev->config;
+	u64 fix, point;
+	u32 cfg = 0;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		config->data_width = 16;
+		dev->ccr = 0x00;
+		dev->xfer_resolution = 0x02;
+		break;
+
+	case SNDRV_PCM_FORMAT_S24_LE:
+		config->data_width = 24;
+		dev->ccr = 0x08;
+		dev->xfer_resolution = 0x04;
+		break;
+
+	case SNDRV_PCM_FORMAT_S32_LE:
+		config->data_width = 32;
+		dev->ccr = 0x10;
+		dev->xfer_resolution = 0x05;
+		break;
+
+	default:
+		dev_err(dev->dev, "phytium-i2s: unsupported PCM fmt");
+		return -EINVAL;
+	}
+
+	config->chan_nr = params_channels(params);
+
+	switch (config->chan_nr) {
+	case EIGHT_CHANNEL_SUPPORT:
+	case SIX_CHANNEL_SUPPORT:
+	case FOUR_CHANNEL_SUPPORT:
+	case TWO_CHANNEL_SUPPORT:
+		break;
+	default:
+		dev_err(dev->dev, "channel not supported\n");
+		return -EINVAL;
+	}
+
+	phytium_i2s_config(dev, substream->stream);
+
+	i2s_write_reg(dev->regs, CCR, dev->ccr);
+
+	config->sample_rate = params_rate(params);
+	if (dev->capability & PHYTIUM_I2S_MASTER) {
+		fix = dev->clk_base / config->sample_rate / config->data_width / 32;
+		point = ((dev->clk_base / config->sample_rate) << 10) / config->data_width / 32;
+		point = (point - (fix << 10)) * 10;
+		cfg = ((u16) fix << 16) | (u16) point;
+		i2s_write_reg(dev->regs, CLK_CFG0, cfg);
+		i2s_write_reg(dev->regs, CLK_CFG1, 0xf);
+	}
+	return 0;
+}
+
+static int phytium_i2s_prepare(struct snd_pcm_substream *substream,
+			  struct snd_soc_dai *dai)
+{
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(dai);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->regs, TXFFR, 1);
+	else
+		i2s_write_reg(dev->regs, RXFFR, 1);
+
+	return 0;
+}
+
+static int phytium_i2s_trigger(struct snd_pcm_substream *substream,
+		int cmd, struct snd_soc_dai *dai)
+{
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(dai);
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		dev->active++;
+		i2s_start(dev, substream);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		dev->active--;
+		i2s_stop(dev, substream);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int phytium_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(cpu_dai);
+	int ret = 0;
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		if (dev->capability & PHYTIUM_I2S_SLAVE)
+			ret = 0;
+		else
+			ret = -EINVAL;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		if (dev->capability & PHYTIUM_I2S_MASTER)
+			ret = 0;
+		else
+			ret = -EINVAL;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFS:
+	case SND_SOC_DAIFMT_CBS_CFM:
+		ret = -EINVAL;
+		break;
+	default:
+		dev_dbg(dev->dev, "phytium/i2s: Invalid master/slave format\n");
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static const struct snd_soc_dai_ops phytium_i2s_dai_ops = {
+	.hw_params	= phytium_i2s_hw_params,
+	.prepare	= phytium_i2s_prepare,
+	.trigger	= phytium_i2s_trigger,
+	.set_fmt	= phytium_i2s_set_fmt,
+};
+
+#ifdef CONFIG_PM
+
+static int phytium_i2s_suspend(struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static int phytium_i2s_resume(struct snd_soc_component *component)
+{
+	struct i2s_phytium *dev = snd_soc_component_get_drvdata(component);
+	struct snd_soc_dai *dai;
+
+	for_each_component_dais(component, dai) {
+		if (snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK))
+			phytium_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK);
+		if (snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE))
+			phytium_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE);
+	}
+
+	return 0;
+}
+
+#else
+#define phytium_i2s_suspend NULL
+#define phytium_i2s_resume  NULL
+#endif
+
+static struct snd_soc_dai_driver phytium_i2s_dai = {
+	.playback = {
+		.stream_name = "i2s-Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_8000_192000,
+		.formats = SNDRV_PCM_FMTBIT_S8 |
+			   SNDRV_PCM_FMTBIT_S16_LE |
+			   SNDRV_PCM_FMTBIT_S20_LE |
+			   SNDRV_PCM_FMTBIT_S24_LE |
+			   SNDRV_PCM_FMTBIT_S32_LE,
+	},
+	.capture = {
+		.stream_name = "i2s-Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_8000_192000,
+		.formats = SNDRV_PCM_FMTBIT_S8 |
+			   SNDRV_PCM_FMTBIT_S16_LE |
+			   SNDRV_PCM_FMTBIT_S20_LE |
+			   SNDRV_PCM_FMTBIT_S24_LE |
+			   SNDRV_PCM_FMTBIT_S32_LE,
+	},
+	.ops     = &phytium_i2s_dai_ops,
+	.symmetric_rates = 1,
+};
+
+static const struct snd_pcm_hardware phytium_pcm_hardware = {
+	.info = SNDRV_PCM_INFO_INTERLEAVED |
+		SNDRV_PCM_INFO_MMAP |
+		SNDRV_PCM_INFO_MMAP_VALID |
+		SNDRV_PCM_INFO_BLOCK_TRANSFER,
+	.rates = SNDRV_PCM_RATE_8000 |
+		SNDRV_PCM_RATE_32000 |
+		SNDRV_PCM_RATE_44100 |
+		SNDRV_PCM_RATE_48000,
+	.rate_min = 8000,
+	.rate_max = 48000,
+	.formats = (SNDRV_PCM_FMTBIT_S8 |
+		SNDRV_PCM_FMTBIT_S16_LE |
+		SNDRV_PCM_FMTBIT_S20_LE |
+		SNDRV_PCM_FMTBIT_S24_LE |
+		SNDRV_PCM_FMTBIT_S32_LE),
+	.channels_min = 2,
+	.channels_max = 2,
+	.buffer_bytes_max = 4096*16,
+	.period_bytes_min = 1024,
+	.period_bytes_max = 4096*4,
+	.periods_min = 2,
+	.periods_max = 16,
+	.fifo_size = 16,
+};
+
+struct i2s_stream *snd_i2s_stream_assign(struct i2sc_bus *bus,
+					   struct snd_pcm_substream *substream)
+{
+	struct i2s_stream *azx_dev;
+	struct i2s_stream *res = NULL;
+
+	/* make a non-zero unique key for the substream */
+	int key = (substream->pcm->device << 16) | (substream->number << 2) |
+		(substream->stream + 1);
+
+	list_for_each_entry(azx_dev, &bus->stream_list, list) {
+		if (azx_dev->direction != substream->stream)
+			continue;
+
+		azx_dev->opened = 0;
+
+		if (azx_dev->assigned_key == key) {
+			res = azx_dev;
+			break;
+		}
+
+		if (!res || bus->reverse_assign)
+			res = azx_dev;
+	}
+
+	if (res) {
+		spin_lock_irq(&bus->reg_lock);
+		res->opened = 1;
+		res->running = 0;
+		res->assigned_key = key;
+		res->substream = substream;
+		spin_unlock_irq(&bus->reg_lock);
+	}
+
+	return res;
+}
+
+/* assign a stream for the PCM */
+static inline struct azx_dev *
+azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
+{
+	struct i2s_stream *s;
+
+	s = snd_i2s_stream_assign(azx_bus(chip), substream);
+	if (!s)
+		return NULL;
+	return stream_to_azx_dev(s);
+}
+
+static int phytium_pcm_open(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+	struct azx *chip = &dev->chip;
+	struct azx_dev *azx_dev;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	azx_dev = azx_assign_device(chip, substream);
+	if (azx_dev == NULL)
+		return -EBUSY;
+
+	snd_soc_set_runtime_hwparams(substream, &phytium_pcm_hardware);
+	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 128);
+	runtime->private_data = azx_dev;
+
+	return 0;
+}
+
+static int phytium_pcm_close(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+	struct azx *chip = &dev->chip;
+	struct azx_dev *azx_dev = get_azx_dev(substream);
+
+	mutex_lock(&chip->open_mutex);
+	azx_stream(azx_dev)->opened = 0;
+	azx_stream(azx_dev)->running = 0;
+	azx_stream(azx_dev)->substream = NULL;
+
+	mutex_unlock(&chip->open_mutex);
+	return 0;
+}
+
+static int phytium_pcm_new(struct snd_soc_component *component,
+				struct snd_soc_pcm_runtime *rtd)
+{
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+	size_t size = phytium_pcm_hardware.buffer_bytes_max;
+
+	snd_pcm_set_managed_buffer_all(rtd->pcm,
+				      SNDRV_DMA_TYPE_DEV,
+				      dev->pdev, size, size);
+
+	return 0;
+}
+
+static const struct i2s_io_ops axi_i2s_io_ops;
+static const struct i2s_controller_ops axi_i2s_ops;
+
+static int phytium_pcm_hw_params(struct snd_soc_component *component,
+					struct snd_pcm_substream *substream,
+					struct snd_pcm_hw_params *hw_params)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	struct azx *chip = &dev->chip;
+	struct azx_dev *azx_dev = get_azx_dev(substream);
+	int ret;
+
+	azx_dev->core.bufsize = 0;
+	azx_dev->core.period_bytes = 0;
+	azx_dev->core.format_val = 0;
+
+	ret = chip->ops->substream_alloc_pages(chip, substream,
+					  params_buffer_bytes(hw_params));
+
+	return ret;
+}
+/*
+ * set up a BDL entry
+ */
+static int setup_bdle(struct i2sc_bus *bus,
+		      struct snd_dma_buffer *dmab,
+		      struct i2s_stream *azx_dev, __le32 **bdlp,
+		      int ofs, int size, int with_ioc)
+{
+	struct snd_pcm_substream *substream = azx_dev->substream;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	__le32 *bdl = *bdlp;
+
+	dmab->addr = runtime->dma_addr;
+	while (size > 0) {
+		dma_addr_t addr;
+		int chunk;
+
+		if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
+			return -EINVAL;
+
+		addr = snd_sgbuf_get_addr(dmab, ofs);
+
+		/* program the address field of the BDL entry */
+		bdl[0] = cpu_to_le32((u32)addr);
+
+		bdl[1] = cpu_to_le32(upper_32_bits(addr));
+
+		/* program the size field of the BDL entry */
+		chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
+
+		bdl[2] = cpu_to_le32(chunk);
+
+		/* program the IOC to enable interrupt
+		 * only when the whole fragment is processed
+		 */
+		size -= chunk;
+		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
+
+		bdl += 4;
+		azx_dev->frags++;
+		ofs += chunk;
+	}
+	*bdlp = bdl;
+	return ofs;
+}
+
+int snd_i2s_stream_setup_periods(struct i2s_stream *azx_dev)
+{
+	struct i2sc_bus *bus = azx_dev->bus;
+	struct snd_pcm_substream *substream = azx_dev->substream;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	__le32 *bdl;
+	int i, ofs, periods, period_bytes;
+	int pos_adj, pos_align;
+
+	period_bytes = azx_dev->period_bytes;
+	periods = azx_dev->bufsize / period_bytes;
+
+	/* program the initial BDL entries */
+	bdl = (__le32 *)azx_dev->bdl.area;
+
+	ofs = 0;
+	azx_dev->frags = 0;
+
+	pos_adj = bus->bdl_pos_adj;
+
+	if (!azx_dev->no_period_wakeup && pos_adj > 0) {
+
+		pos_align = pos_adj;
+		pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
+		if (!pos_adj)
+			pos_adj = pos_align;
+		else
+			pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
+				pos_align;
+		pos_adj = frames_to_bytes(runtime, pos_adj);
+		if (pos_adj >= period_bytes) {
+			dev_warn(bus->dev, "Too big adjustment %d\n",
+				 pos_adj);
+			pos_adj = 0;
+		} else {
+
+			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
+					 azx_dev,
+					 &bdl, ofs, pos_adj, true);
+			if (ofs < 0)
+				goto error;
+		}
+	} else
+		pos_adj = 0;
+
+	for (i = 0; i < periods; i++) {
+		if (i == periods - 1 && pos_adj)
+			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
+					 azx_dev, &bdl, ofs,
+					 period_bytes - pos_adj, 0);
+		else
+			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
+					 azx_dev, &bdl, ofs,
+					 period_bytes,
+					 !azx_dev->no_period_wakeup);
+		if (ofs < 0)
+			goto error;
+	}
+	return 0;
+
+ error:
+	dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
+		azx_dev->bufsize, period_bytes);
+	return -EINVAL;
+}
+
+int snd_i2s_stream_set_params(struct i2s_stream *azx_dev,
+				 unsigned int format_val)
+{
+	unsigned int bufsize, period_bytes;
+	struct snd_pcm_substream *substream = azx_dev->substream;
+	struct snd_pcm_runtime *runtime;
+	int err;
+
+	if (!substream)
+		return -EINVAL;
+
+	runtime = substream->runtime;
+	bufsize = snd_pcm_lib_buffer_bytes(substream);
+	period_bytes = snd_pcm_lib_period_bytes(substream);
+	if (bufsize != azx_dev->bufsize ||
+	    period_bytes != azx_dev->period_bytes ||
+	    format_val != azx_dev->format_val ||
+	    runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
+
+		azx_dev->bufsize = bufsize;
+		azx_dev->period_bytes = period_bytes;
+		azx_dev->format_val = format_val;
+		azx_dev->no_period_wakeup = runtime->no_period_wakeup;
+		err = snd_i2s_stream_setup_periods(azx_dev);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+
+int snd_i2s_stream_setup(struct i2s_stream *azx_dev, int pcie, u32 paddr)
+{
+	struct snd_pcm_runtime *runtime;
+
+	if (azx_dev->substream)
+		runtime = azx_dev->substream->runtime;
+	else
+		runtime = NULL;
+
+	i2s_write_reg(azx_dev->sd_addr, DMA_CHAL_CONFG0, 0x8180);
+	i2s_write_reg(azx_dev->sd_addr, DMA_MASK_INT, 0x80000003);
+
+	if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK) {
+		i2s_write_reg(azx_dev->sd_addr, DMA_BDLPL(0), (u32)azx_dev->bdl.addr);
+		i2s_write_reg(azx_dev->sd_addr, DMA_BDLPU(0), upper_32_bits(azx_dev->bdl.addr));
+		if (pcie)
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DEV_ADDR(0), 0x1c8);
+		else
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DEV_ADDR(0), paddr + 0x1c8);
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CBL(0), azx_dev->bufsize);
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_LVI(0), azx_dev->frags - 1);
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DSIZE(0), 0x2);//0x2
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DLENTH(0), 0x0);//0x0
+	} else {
+		i2s_write_reg(azx_dev->sd_addr, DMA_BDLPL(1), (u32)azx_dev->bdl.addr);
+		i2s_write_reg(azx_dev->sd_addr, DMA_BDLPU(1), upper_32_bits(azx_dev->bdl.addr));
+		if (pcie)
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DEV_ADDR(1), 0x1c0);
+		else
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DEV_ADDR(1), paddr + 0x1c0);
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CBL(1), azx_dev->bufsize);
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_LVI(1), azx_dev->frags - 1);
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DSIZE(1), 0x8);//0x8
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_DLENTH(1), 0x0);
+	}
+
+	if (runtime && runtime->period_size > 64)
+		azx_dev->delay_negative_threshold =
+			-frames_to_bytes(runtime, 64);
+	else
+		azx_dev->delay_negative_threshold = 0;
+
+	return 0;
+}
+
+static int phytium_pcm_prepare(struct snd_soc_component *component,
+			      struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	struct azx *chip = &dev->chip;
+	struct azx_dev *azx_dev = get_azx_dev(substream);
+	struct i2sc_bus *bus = azx_bus(chip);
+	struct i2s_stream *hstr_p;
+	int err;
+
+	dev->substream = substream;
+	azx_dev->core.substream = substream;
+	azx_dev->core.sd_addr = dev->regs_db;
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		azx_dev->core.bdl.area = bus->bdl0.area;
+		azx_dev->core.bdl.addr = bus->bdl0.addr;
+	} else {
+		azx_dev->core.bdl.area = bus->bdl1.area;
+		azx_dev->core.bdl.addr = bus->bdl1.addr;
+	}
+
+	if (!substream)
+		return -EINVAL;
+
+	hstr_p = azx_stream(azx_dev);
+	hstr_p->direction = substream->stream;
+
+	err = snd_i2s_stream_set_params(azx_stream(azx_dev), 0);
+	if (err < 0)
+		goto unlock;
+
+	snd_i2s_stream_setup(azx_stream(azx_dev), dev->pcie, dev->paddr);
+
+ unlock:
+	if (!err)
+		azx_stream(azx_dev)->prepared = 1;
+
+	return err;
+}
+
+void snd_i2s_stream_clear(struct i2s_stream *azx_dev)
+{
+	if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(0), 0x0);
+	else
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(1), 0x0);
+
+	azx_dev->running = false;
+}
+
+void snd_i2s_stream_stop(struct i2s_stream *azx_dev)
+{
+	snd_i2s_stream_clear(azx_dev);
+}
+
+void snd_i2s_stream_start(struct i2s_stream *azx_dev, bool fresh_start)
+{
+	if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(0), 0x1);
+	else
+		i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(1), 0x5);
+
+	azx_dev->running = true;
+}
+
+static int phytium_pcm_trigger(struct snd_soc_component *component,
+			       struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	struct azx *chip = &dev->chip;
+	struct i2sc_bus *bus = azx_bus(chip);
+	struct azx_dev *azx_dev = get_azx_dev(substream);
+	struct snd_pcm_substream *s;
+	struct i2s_stream *hstr;
+	bool start;
+	int sbits = 0;
+
+	hstr = azx_stream(azx_dev);
+	hstr->direction = substream->stream;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+	case SNDRV_PCM_TRIGGER_RESUME:
+		start = true;
+		break;
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_STOP:
+		start = false;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	snd_pcm_group_for_each_entry(s, substream) {
+		if (s->pcm->card != substream->pcm->card)
+			continue;
+		azx_dev = get_azx_dev(s);
+		sbits |= 1 << azx_dev->core.index;
+		snd_pcm_trigger_done(s, substream);
+	}
+
+	spin_lock(&bus->reg_lock);
+
+	snd_pcm_group_for_each_entry(s, substream) {
+		if (s->pcm->card != substream->pcm->card)
+			continue;
+		azx_dev = get_azx_dev(s);
+		if (start)
+			snd_i2s_stream_start(azx_stream(azx_dev), true);
+		else
+			snd_i2s_stream_stop(azx_stream(azx_dev));
+	}
+
+	i2s_write_reg(dev->regs_db, DMA_CTL, 0x1);
+	spin_unlock(&bus->reg_lock);
+
+	return 0;
+}
+
+void snd_i2s_stream_cleanup(struct i2s_stream *azx_dev)
+{
+	int cnt = 10;
+	u32 mask;
+
+	if (azx_dev->sd_addr) {
+		if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK) {
+			mask = i2s_read_reg(azx_dev->sd_addr, DMA_MASK_INT);
+			mask &= ~BIT(0);
+			i2s_write_reg(azx_dev->sd_addr, DMA_MASK_INT, mask);
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(0), 0);
+			while (cnt--) {
+				if (i2s_read_reg(azx_dev->sd_addr, DMA_CHALX_CTL(0)) == 0)
+					break;
+			}
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(0), 2);
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(0), 0);
+			i2s_write_reg(azx_dev->sd_addr, DMA_BDLPL(0), 0);
+			i2s_write_reg(azx_dev->sd_addr, DMA_BDLPU(0), 0);
+		} else {
+			mask = i2s_read_reg(azx_dev->sd_addr, DMA_MASK_INT);
+			mask &= ~BIT(1);
+			i2s_write_reg(azx_dev->sd_addr, DMA_MASK_INT, mask);
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(1), 0);
+			while (cnt--) {
+				if (i2s_read_reg(azx_dev->sd_addr, DMA_CHALX_CTL(1)) == 0)
+					break;
+			}
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(1), 2);
+			i2s_write_reg(azx_dev->sd_addr, DMA_CHALX_CTL(1), 0);
+			i2s_write_reg(azx_dev->sd_addr, DMA_BDLPL(1), 0);
+			i2s_write_reg(azx_dev->sd_addr, DMA_BDLPU(1), 0);
+		}
+	}
+}
+
+static int phytium_pcm_hw_free(struct snd_soc_component *component,
+			       struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	struct azx *chip = &dev->chip;
+	struct i2s_stream *hstr_p;
+	struct azx_dev *azx_dev = get_azx_dev(substream);
+	int err;
+
+	hstr_p = azx_stream(azx_dev);
+	hstr_p->direction = substream->stream;
+	snd_i2s_stream_cleanup(azx_stream(azx_dev));
+
+	err = chip->ops->substream_free_pages(chip, substream);
+	azx_stream(azx_dev)->prepared = 0;
+
+	return err;
+}
+
+static snd_pcm_uframes_t phytium_pcm_pointer(struct snd_soc_component *component,
+					     struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2s_phytium *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	int stream = substream->stream;
+
+	u32 pos = i2s_read_reg(dev->regs_db, DMA_LPIB(stream));
+
+	return bytes_to_frames(substream->runtime, pos);
+}
+
+static const struct snd_soc_component_driver phytium_i2s_component = {
+	.name		= "phytium-i2s",
+	.pcm_construct  = phytium_pcm_new,
+	.suspend = phytium_i2s_suspend,
+	.resume  = phytium_i2s_resume,
+
+	.open = phytium_pcm_open,
+	.close = phytium_pcm_close,
+	.hw_params = phytium_pcm_hw_params,
+	.prepare = phytium_pcm_prepare,
+	.hw_free = phytium_pcm_hw_free,
+	.trigger = phytium_pcm_trigger,
+	.pointer = phytium_pcm_pointer,
+};
+
+/* Maximum bit resolution of a channel - not uniformly spaced */
+static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
+	12, 16, 20, 24, 32, 0, 0, 0
+};
+
+/* Width of (DMA) bus */
+static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
+	DMA_SLAVE_BUSWIDTH_1_BYTE,
+	DMA_SLAVE_BUSWIDTH_2_BYTES,
+	DMA_SLAVE_BUSWIDTH_4_BYTES,
+	DMA_SLAVE_BUSWIDTH_UNDEFINED
+};
+
+/* PCM format to support channel resolution */
+static const u32 formats[COMP_MAX_WORDSIZE] = {
+	SNDRV_PCM_FMTBIT_S16_LE,
+	SNDRV_PCM_FMTBIT_S16_LE,
+	SNDRV_PCM_FMTBIT_S24_LE,
+	SNDRV_PCM_FMTBIT_S24_LE,
+	SNDRV_PCM_FMTBIT_S32_LE,
+	0,
+	0,
+	0
+};
+
+static int phytium_configure_dai(struct i2s_phytium *dev)
+{
+	u32 comp1 = i2s_read_reg(dev->regs, dev->i2s_reg_comp1);
+	u32 comp2 = i2s_read_reg(dev->regs, dev->i2s_reg_comp2);
+	u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
+	u32 idx;
+
+	if (COMP1_TX_ENABLED(comp1)) {
+		dev_dbg(dev->dev, " phytium: play supported\n");
+		idx = COMP1_TX_WORDSIZE_0(comp1);
+		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
+			return -EINVAL;
+	}
+
+	if (COMP1_RX_ENABLED(comp1)) {
+		dev_dbg(dev->dev, "phytium: record supported\n");
+		idx = COMP2_RX_WORDSIZE_0(comp2);
+		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
+			return -EINVAL;
+		if (dev->quirks & PHYTIUM_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+			idx = 1;
+	}
+
+	if (COMP1_MODE_EN(comp1)) {
+		dev_dbg(dev->dev, "phytium: i2s master mode supported\n");
+		dev->capability |= PHYTIUM_I2S_MASTER;
+	} else {
+		dev_dbg(dev->dev, "phytium: i2s slave mode supported\n");
+		dev->capability |= PHYTIUM_I2S_SLAVE;
+	}
+
+	dev->fifo_th = fifo_depth / 2;
+	return 0;
+}
+
+static int phytium_configure_dai_by_dt(struct i2s_phytium *dev)
+{
+	u32 comp1 = i2s_read_reg(dev->regs, I2S_COMP_PARAM_1);
+	u32 comp2 = i2s_read_reg(dev->regs, I2S_COMP_PARAM_2);
+	u32 idx = COMP1_APB_DATA_WIDTH(comp1);
+	u32 idx2;
+	int ret;
+
+	if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
+		return -EINVAL;
+
+	ret = phytium_configure_dai(dev);
+	if (ret < 0)
+		return ret;
+
+	if (COMP1_TX_ENABLED(comp1)) {
+		idx2 = COMP1_TX_WORDSIZE_0(comp1);
+		dev->capability |= PHYTIUM_I2S_PLAY;
+	}
+	if (COMP1_RX_ENABLED(comp1)) {
+		idx2 = COMP2_RX_WORDSIZE_0(comp2);
+		dev->capability |= PHYTIUM_I2S_RECORD;
+	}
+
+	return 0;
+}
+
+static int phytium_dma_alloc_pages(struct i2sc_bus *bus, int type, size_t size,
+			       struct snd_dma_buffer *buf)
+{
+	int err;
+
+	err = snd_dma_alloc_pages(type, bus->dev, size, buf);
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+int snd_i2s_bus_alloc_stream_pages(struct i2sc_bus *bus)
+{
+	struct i2s_stream *s;
+	int num_streams = 0;
+	int err;
+
+	list_for_each_entry(s, &bus->stream_list, list) {
+
+		/* allocate memory for the BDL for each stream */
+		err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
+						   BDL_SIZE, &s->bdl);
+		if (num_streams == 0) {
+			bus->bdl0.addr = s->bdl.addr;
+			bus->bdl0.area = s->bdl.area;
+		} else {
+			bus->bdl1.addr = s->bdl.addr;
+			bus->bdl1.area = s->bdl.area;
+		}
+		num_streams++;
+		if (err < 0)
+			return -ENOMEM;
+	}
+
+	if (WARN_ON(!num_streams))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int stream_direction(struct azx *chip, unsigned char index)
+{
+	if (index >= chip->playback_index_offset &&
+	    index < chip->playback_index_offset + chip->playback_streams)
+		return SNDRV_PCM_STREAM_PLAYBACK;
+	return SNDRV_PCM_STREAM_CAPTURE;
+
+}
+
+void snd_i2s_stream_init(struct i2sc_bus *bus, struct i2s_stream *azx_dev,
+			  int idx, int direction, int tag)
+{
+	azx_dev->bus = bus;
+	azx_dev->sd_addr = bus->remap_addr;
+
+	if (idx == 0)
+		azx_dev->sd_int_sta_mask = 1 << idx;
+	else
+		azx_dev->sd_int_sta_mask = 1 << 8;
+
+	azx_dev->index = idx;
+	azx_dev->direction = direction;
+	azx_dev->stream_tag = tag;
+
+	list_add_tail(&azx_dev->list, &bus->stream_list);
+
+}
+
+int azx_i2s_init_streams(struct azx *chip)
+{
+	int i;
+
+	for (i = 0; i < chip->num_streams; i++) {
+		struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
+		int dir, tag;
+
+		if (!azx_dev)
+			return -ENOMEM;
+
+		dir = stream_direction(chip, i);
+
+		tag = i + 1;
+
+		snd_i2s_stream_init(azx_bus(chip), azx_stream(azx_dev),
+				     i, dir, tag);
+	}
+
+	return 0;
+}
+
+static int azx_first_init(struct azx *chip)
+{
+	struct i2s_phytium *i2s = container_of(chip, struct i2s_phytium, chip);
+	struct platform_device *pdev = to_platform_device(i2s->dev);
+	struct device *i2sdev = i2s->dev;
+	struct i2sc_bus *bus = azx_bus(chip);
+	struct resource *res;
+	int err;
+	unsigned int dma_bits = 64;
+
+	chip->region_requested = 1;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	bus->addr = res->start;
+	bus->remap_addr = i2s->regs_db;
+	bus->dev = i2s->pdev;
+
+	if (bus->remap_addr == NULL) {
+		dev_err(i2sdev, "ioremap error\n");
+		return -ENXIO;
+	}
+
+	if (azx_acquire_irq(chip, 0) < 0)
+		return -EBUSY;
+
+	synchronize_irq(bus->irq);
+
+	spin_lock_init(&bus->reg_lock);
+
+	if (!dma_set_mask(i2sdev, DMA_BIT_MASK(dma_bits))) {
+		err = dma_set_coherent_mask(i2sdev, DMA_BIT_MASK(dma_bits));
+	} else {
+		err = dma_set_mask(i2sdev, DMA_BIT_MASK(32));
+		err = dma_set_coherent_mask(i2sdev, DMA_BIT_MASK(32));
+	}
+
+	chip->playback_streams = NUM_PLAYBACK;
+	chip->capture_streams  = NUM_CAPTURE;
+
+	chip->playback_index_offset = 0;
+	chip->capture_index_offset = chip->playback_streams;
+	chip->num_streams = chip->playback_streams + chip->capture_streams;
+
+	err = azx_i2s_init_streams(chip);
+	if (err < 0)
+		return err;
+
+	err = azx_alloc_stream_pages(chip);
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+static int azx_probe_continue(struct azx *chip)
+{
+	struct i2s_phytium *i2s = container_of(chip, struct i2s_phytium, chip);
+	int err;
+
+	i2s->probe_continued = 1;
+
+	err = azx_first_init(chip);
+	if (err < 0)
+		goto out_free;
+
+	chip->running = 1;
+
+out_free:
+	return err;
+}
+
+static void azx_probe_work(struct work_struct *work)
+{
+	struct i2s_phytium *i2s = container_of(work, struct i2s_phytium, probe_work);
+
+	azx_probe_continue(&i2s->chip);
+}
+
+int azx_i2s_bus_init(struct azx *chip,
+		 const struct i2s_io_ops *io_ops)
+{
+	struct i2s_bus *bus = &chip->bus;
+
+	bus->core.io_ops = io_ops;
+
+	INIT_LIST_HEAD(&bus->core.stream_list);
+	bus->card = chip->card;
+	mutex_init(&bus->prepare_mutex);
+	bus->pci = chip->pci;
+
+	bus->core.bdl_pos_adj = chip->bdl_pos_adj;
+	return 0;
+}
+
+static int i2s_phytium_create(struct platform_device *pdev,
+			int dev, struct azx **rchip, struct i2s_phytium *i2s)
+{
+	struct azx *chip;
+	int err;
+
+	*rchip = NULL;
+
+	if (!i2s)
+		return -ENOMEM;
+	chip = &i2s->chip;
+
+	mutex_init(&chip->open_mutex);
+
+	chip->ops = &axi_i2s_ops;
+	chip->dev_index = dev;
+
+	INIT_LIST_HEAD(&chip->pcm_list);
+	init_completion(&i2s->probe_wait);
+
+	chip->bdl_pos_adj = 32;
+	err = azx_i2s_bus_init(chip, &axi_i2s_io_ops);
+	if (err < 0) {
+		kfree(i2s);
+		return err;
+	}
+
+	INIT_WORK(&i2s->probe_work, azx_probe_work);
+	*rchip = chip;
+	return 0;
+}
+
+static int substream_alloc_pages(struct azx *chip,
+				 struct snd_pcm_substream *substream,
+				 size_t size)
+{
+	int ret;
+
+	ret = snd_pcm_lib_malloc_pages(substream, size);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static void phytium_dma_free_pages(struct i2sc_bus *bus,
+			       struct snd_dma_buffer *buf)
+{
+	snd_dma_free_pages(buf);
+}
+
+static const struct i2s_io_ops axi_i2s_io_ops = {
+	.dma_alloc_pages = phytium_dma_alloc_pages,
+	.dma_free_pages = phytium_dma_free_pages,
+};
+
+static const struct i2s_controller_ops axi_i2s_ops = {
+	.substream_alloc_pages = substream_alloc_pages,
+	.substream_free_pages = substream_free_pages,
+};
+
+
+static int phytium_i2s_probe(struct platform_device *pdev)
+{
+	struct i2s_phytium *i2s;
+	struct azx *chip;
+	struct resource *res;
+	struct pdata_px210_mfd *pdata;
+	struct snd_soc_dai_driver *dai_drv;
+	struct clk *clk;
+	int err, ret;
+	int card_num = 1;
+	bool schedule_probe;
+	struct fwnode_handle *np;
+
+	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
+	if (!i2s)
+		return -ENOMEM;
+
+	dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
+	if (!dai_drv)
+		return -ENOMEM;
+	memcpy(dai_drv, &phytium_i2s_dai, sizeof(phytium_i2s_dai));
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	i2s->paddr = res->start;
+	i2s->regs = devm_ioremap_resource(&pdev->dev, res);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	i2s->regs_db = devm_ioremap_resource(&pdev->dev, res);
+
+	if (IS_ERR(i2s->regs))
+		return PTR_ERR(i2s->regs);
+
+	i2s->irq_id = platform_get_irq(pdev, 0);
+
+	if (i2s->irq_id < 0)
+		return i2s->irq_id;
+
+	i2s->i2s_reg_comp1 = I2S_COMP_PARAM_1;
+	i2s->i2s_reg_comp2 = I2S_COMP_PARAM_2;
+
+	ret = phytium_configure_dai_by_dt(i2s);
+	if (ret < 0)
+		return ret;
+
+	err = i2s_phytium_create(pdev, card_num, &chip, i2s);
+	if (err < 0)
+		return err;
+	i2s = container_of(chip, struct i2s_phytium, chip);
+	schedule_probe = !chip->disabled;
+
+	dev_set_drvdata(&pdev->dev, i2s);
+
+	pdata = dev_get_platdata(&pdev->dev);
+	i2s->dev = &pdev->dev;
+	if (pdata) {
+		dai_drv->name = pdata->name;
+		i2s->pdev = pdata->dev;
+		i2s->clk_base = pdata->clk_base;
+		i2s->pcie = 1;
+	} else if (pdev->dev.of_node) {
+		device_property_read_string(&pdev->dev, "dai-name", &dai_drv->name);
+		i2s->pdev = &pdev->dev;
+		clk = devm_clk_get(&pdev->dev, NULL);
+		i2s->clk_base = clk_get_rate(clk);
+	} else if (has_acpi_companion(&pdev->dev)) {
+		np = dev_fwnode(&(pdev->dev));
+		ret = fwnode_property_read_string(np, "dai-name", &dai_drv->name);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing dai-name property from acpi\n");
+			goto failed_get_dai_name;
+		}
+		i2s->pdev = &pdev->dev;
+		ret = fwnode_property_read_u32(np, "i2s_clk", &i2s->clk_base);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing i2s_clk property from acpi\n");
+			goto failed_get_dai_name;
+		}
+	}
+	ret = devm_snd_soc_register_component(&pdev->dev, &phytium_i2s_component,
+						 dai_drv, 1);
+	if (ret != 0)
+		dev_err(&pdev->dev, "not able to register dai\n");
+
+	if (schedule_probe)
+		schedule_work(&i2s->probe_work);
+
+	if (chip->disabled)
+		complete_all(&i2s->probe_wait);
+
+	return 0;
+failed_get_dai_name:
+	return ret;
+}
+
+static int phytium_i2s_remove(struct platform_device *pdev)
+{
+	pm_runtime_disable(&pdev->dev);
+	return 0;
+}
+
+static const struct of_device_id phytium_i2s_of_match[] = {
+	{ .compatible = "phytium,i2s", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, phytium_i2s_of_match);
+
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id phytium_i2s_acpi_match[] = {
+	{ "PHYT0016", 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, phytium_i2s_acpi_match);
+#else
+#define phytium_i2s_acpi_match NULL
+#endif
+
+static struct platform_driver phytium_i2s_driver = {
+	.probe	= phytium_i2s_probe,
+	.remove	= phytium_i2s_remove,
+	.driver	= {
+		.name = "phytium-i2s",
+		.of_match_table = of_match_ptr(phytium_i2s_of_match),
+		.acpi_match_table = phytium_i2s_acpi_match,
+	},
+};
+
+module_platform_driver(phytium_i2s_driver);
+
+MODULE_DESCRIPTION("Phytium I2S Driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Zhang Yiqun <zhangyiqun@phytium.com.cn>");
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_dp.c b/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_dp.c
new file mode 100755
index 00000000000000..ec045e9a4dc1b1
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_dp.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <sound/soc.h>
+#include <sound/pcm_params.h>
+#include <sound/jack.h>
+
+#define DAI_CNT(pmdk_dai_) sizeof(pmdk_dai_)/sizeof(struct snd_soc_dai_link)
+
+struct pmdk_dp_private {
+	struct snd_soc_jack jack0;
+	struct snd_soc_jack jack1;
+	struct snd_soc_jack jack2;
+};
+
+/* PMDK widgets */
+static const struct snd_soc_dapm_widget pmdk_dp_dapm_widgets[] = {
+	SND_SOC_DAPM_LINE("DP", NULL),
+};
+
+/* PMDK control */
+static const struct snd_kcontrol_new pmdk_controls[] = {
+	SOC_DAPM_PIN_SWITCH("DP"),
+};
+
+/* PMDK connections */
+static const struct snd_soc_dapm_route pmdk_dp_audio_map[] = {
+	{"DP", NULL, "TX"},
+};
+
+static struct snd_soc_jack_pin dp0_pins[] = {
+	{
+		.pin	= "HDMI/DP,pcm=0",
+		.mask	= SND_JACK_LINEOUT,
+	},
+};
+
+static struct snd_soc_jack_pin dp1_pins[] = {
+	{
+		.pin	= "HDMI/DP,pcm=1",
+		.mask	= SND_JACK_LINEOUT,
+	},
+};
+
+static struct snd_soc_jack_pin dp2_pins[] = {
+	{
+		.pin	= "HDMI/DP,pcm=2",
+		.mask	= SND_JACK_LINEOUT,
+	},
+};
+
+#define SMDK_DAI_FMT (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | \
+	SND_SOC_DAIFMT_CBS_CFS)
+
+static int pmdk_dp0_init(struct snd_soc_pcm_runtime *runtime)
+{
+	struct snd_soc_card *card = runtime->card;
+	struct pmdk_dp_private *priv = snd_soc_card_get_drvdata(card);
+	struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
+	int ret;
+
+	ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=0",
+				    SND_JACK_LINEOUT,
+				    &priv->jack0, dp0_pins,
+				    ARRAY_SIZE(dp0_pins));
+	if (ret) {
+		dev_err(card->dev, "Jack creation failed %d\n", ret);
+		return ret;
+	}
+	snd_soc_component_set_jack(component, &priv->jack0, NULL);
+	return ret;
+}
+
+static int pmdk_dp1_init(struct snd_soc_pcm_runtime *runtime)
+{
+	struct snd_soc_card *card = runtime->card;
+	struct pmdk_dp_private *priv = snd_soc_card_get_drvdata(card);
+	struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
+	int ret;
+
+	ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=1",
+				    SND_JACK_LINEOUT,
+				    &priv->jack1, dp1_pins,
+				    ARRAY_SIZE(dp1_pins));
+
+	if (ret) {
+		dev_err(card->dev, "Jack creation failed %d\n", ret);
+		return ret;
+	}
+	snd_soc_component_set_jack(component, &priv->jack1, NULL);
+	return ret;
+}
+
+static int pmdk_dp2_init(struct snd_soc_pcm_runtime *runtime)
+{
+	struct snd_soc_card *card = runtime->card;
+	struct pmdk_dp_private *priv = snd_soc_card_get_drvdata(card);
+	struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
+	int ret;
+
+	ret = snd_soc_card_jack_new(card, "HDMI/DP,pcm=2",
+				    SND_JACK_LINEOUT,
+				    &priv->jack2, dp2_pins,
+				    ARRAY_SIZE(dp2_pins));
+	if (ret) {
+		dev_err(card->dev, "Jack creation failed %d\n", ret);
+		return ret;
+	}
+	snd_soc_component_set_jack(component, &priv->jack2, NULL);
+	return ret;
+}
+
+SND_SOC_DAILINK_DEFS(pmdk_dp0_dai,
+	DAILINK_COMP_ARRAY(COMP_CPU("phytium-i2s-dp0")),
+	DAILINK_COMP_ARRAY(COMP_CODEC("hdmi-audio-codec.1346918656", "i2s-hifi")),
+	DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
+
+SND_SOC_DAILINK_DEFS(pmdk_dp1_dai,
+	DAILINK_COMP_ARRAY(COMP_CPU("phytium-i2s-dp1")),
+	DAILINK_COMP_ARRAY(COMP_CODEC("hdmi-audio-codec.1346918657", "i2s-hifi")),
+	DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
+
+SND_SOC_DAILINK_DEFS(pmdk_dp2_dai,
+	DAILINK_COMP_ARRAY(COMP_CPU("phytium-i2s-dp2")),
+	DAILINK_COMP_ARRAY(COMP_CODEC("hdmi-audio-codec.1346918658", "i2s-hifi")),
+	DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
+
+static struct snd_soc_dai_link pmdk_dai_local[] = {
+{
+	.name = "Phytium dp0-audio",
+	.stream_name = "Playback",
+	.dai_fmt = SMDK_DAI_FMT,
+	.init = pmdk_dp0_init,
+	SND_SOC_DAILINK_REG(pmdk_dp0_dai),
+},{
+	.name = "Phytium dp1-audio",
+	.stream_name = "Playback",
+	.dai_fmt = SMDK_DAI_FMT,
+	.init = pmdk_dp1_init,
+	SND_SOC_DAILINK_REG(pmdk_dp1_dai),
+},
+{
+	.name = "Phytium dp2-audio",
+	.stream_name = "Playback",
+	.dai_fmt = SMDK_DAI_FMT,
+	.init = pmdk_dp2_init,
+	SND_SOC_DAILINK_REG(pmdk_dp2_dai),
+},
+};
+
+static struct snd_soc_card pmdk = {
+	.name = "PMDK-I2S",
+	.owner = THIS_MODULE,
+
+	.dapm_widgets = pmdk_dp_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(pmdk_dp_dapm_widgets),
+	.controls = pmdk_controls,
+	.num_controls = ARRAY_SIZE(pmdk_controls),
+	.dapm_routes = pmdk_dp_audio_map,
+	.num_dapm_routes = ARRAY_SIZE(pmdk_dp_audio_map),
+};
+
+static int pmdk_sound_probe(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = &pmdk;
+	struct pmdk_dp_private *priv;
+	struct snd_soc_dai_link *pmdk_dai;
+	int num_dp = 2;
+	char dp_mask = 0x7;
+	int i,j = 0;
+	card->dev = &pdev->dev;
+
+	device_property_read_u32(&pdev->dev, "num-dp", &num_dp);
+	device_property_read_u8(&pdev->dev, "dp-mask", &dp_mask);
+	pmdk_dai = devm_kzalloc(&pdev->dev, num_dp * sizeof(*pmdk_dai), GFP_KERNEL);
+	if (!pmdk_dai)
+		return -ENOMEM;
+
+	if (!num_dp || num_dp > DAI_CNT(pmdk_dai_local))
+		return -EINVAL;
+
+	for(i = 0; i < num_dp; i++) {
+		for (; j < DAI_CNT(pmdk_dai_local); j++) {
+			if (BIT(j) & dp_mask) {
+				pmdk_dai[i] = pmdk_dai_local[j];
+				j++;
+				break;
+			}
+		}
+	}
+
+	card->dai_link = pmdk_dai;
+	card->num_links = num_dp;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	snd_soc_card_set_drvdata(card, priv);
+
+	return devm_snd_soc_register_card(&pdev->dev, card);
+}
+
+static const struct of_device_id pmdk_sound_of_match[] = {
+	{ .compatible = "phytium,pmdk-dp",},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, pmdk_sound_of_match);
+
+static const struct acpi_device_id pmdk_sound_acpi_match[] = {
+	{ "PHYT8006", 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, pmdk_sound_acpi_match);
+
+static struct platform_driver pmdk_sound_driver = {
+	.probe = pmdk_sound_probe,
+	.driver = {
+		.name = "pmdk_dp",
+		.acpi_match_table = pmdk_sound_acpi_match,
+		.of_match_table = pmdk_sound_of_match,
+#ifdef CONFIG_PM
+		.pm = &snd_soc_pm_ops,
+#endif
+	},
+};
+
+module_platform_driver(pmdk_sound_driver);
+
+MODULE_AUTHOR("Zhang Yiqun<zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("ALSA SoC PMDK DP");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_es8336.c b/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_es8336.c
new file mode 100644
index 00000000000000..f27404373a266b
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_es8336.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <sound/soc.h>
+#include <sound/pcm_params.h>
+
+/* PMDK widgets */
+static const struct snd_soc_dapm_widget pmdk_es8336_dapm_widgets[] = {
+	SND_SOC_DAPM_HP("HP", NULL),
+	SND_SOC_DAPM_MIC("Int Mic", NULL),
+	SND_SOC_DAPM_MIC("Mic In", NULL),
+};
+
+/* PMDK control */
+static const struct snd_kcontrol_new pmdk_controls[] = {
+	SOC_DAPM_PIN_SWITCH("HP"),
+	SOC_DAPM_PIN_SWITCH("Int Mic"),
+	SOC_DAPM_PIN_SWITCH("Mic In"),
+};
+
+/* PMDK connections */
+static const struct snd_soc_dapm_route pmdk_es8336_audio_map[] = {
+	{"DMIC", NULL, "Int Mic"},
+	{"MIC1", NULL, "Mic In"},
+	{"MIC2", NULL, "Mic In"},
+
+	{"HP", NULL, "HPOL"},
+	{"HP", NULL, "HPOR"},
+};
+
+#define PMDK_DAI_FMT (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | \
+	SND_SOC_DAIFMT_CBS_CFS)
+
+SND_SOC_DAILINK_DEFS(pmdk_es8366,
+	DAILINK_COMP_ARRAY(COMP_CPU("phytium-i2s-lsd")),
+	DAILINK_COMP_ARRAY(COMP_CODEC("i2c-ESSX8336:00", "es8336-hifi")),
+	DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
+
+static struct snd_soc_dai_link pmdk_dai[] = {
+	{
+		.name = "ES8336 HIFI",
+		.stream_name = "ES8336 HIFI",
+		.dai_fmt = PMDK_DAI_FMT,
+		SND_SOC_DAILINK_REG(pmdk_es8366),
+	},
+};
+
+static struct snd_soc_card pmdk = {
+	.name = "PMDK-I2S",
+	.owner = THIS_MODULE,
+	.dai_link = pmdk_dai,
+	.num_links = ARRAY_SIZE(pmdk_dai),
+
+	.dapm_widgets = pmdk_es8336_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(pmdk_es8336_dapm_widgets),
+	.controls = pmdk_controls,
+	.num_controls = ARRAY_SIZE(pmdk_controls),
+	.dapm_routes = pmdk_es8336_audio_map,
+	.num_dapm_routes = ARRAY_SIZE(pmdk_es8336_audio_map),
+};
+
+static int pmdk_sound_probe(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = &pmdk;
+	struct device *dev = &pdev->dev;
+
+	card->dev = dev;
+
+	return devm_snd_soc_register_card(&pdev->dev, card);
+}
+
+static const struct acpi_device_id pmdk_sound_acpi_match[] = {
+	{ "PHYT8005", 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, pmdk_sound_acpi_match);
+
+static struct platform_driver pmdk_sound_driver = {
+	.probe = pmdk_sound_probe,
+	.driver = {
+		.name = "pmdk_es8336",
+		.acpi_match_table = pmdk_sound_acpi_match,
+#ifdef CONFIG_PM
+		.pm = &snd_soc_pm_ops,
+#endif
+	},
+};
+
+module_platform_driver(pmdk_sound_driver);
+MODULE_AUTHOR("Zhang Yiqun <zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("ALSA SoC PMDK ES8336");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_es8388.c b/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_es8388.c
new file mode 100644
index 00000000000000..81b61c1323d8d8
--- /dev/null
+++ b/target/linux/phytium/files-5.10/sound/soc/phytium/pmdk_es8388.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2023 Phytium Technology Co., Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <sound/soc.h>
+#include <sound/pcm_params.h>
+#include <sound/jack.h>
+
+static struct snd_soc_jack hs_jack;
+
+/* Headset jack detection DAPM pins */
+static struct snd_soc_jack_pin hs_jack_pins[] = {
+	{
+		.pin	= "FrontIn",
+		.mask	= SND_JACK_MICROPHONE,
+	},
+	{
+		.pin	= "RearIn",
+		.mask	= SND_JACK_MICROPHONE,
+		.invert = 1
+	},
+	{
+		.pin	= "Front",
+		.mask	= SND_JACK_HEADPHONE,
+	},
+	{
+		.pin    = "Rear",
+		.mask   = SND_JACK_HEADPHONE,
+		.invert = 1
+	},
+};
+
+/* Headset jack detection gpios */
+static struct snd_soc_jack_gpio hs_jack_gpios[] = {
+	{
+		.name		= "det",
+		.report		= SND_JACK_HEADSET,
+		.debounce_time	= 200,
+		.invert		= 1,
+	},
+};
+
+/* PMDK widgets */
+static const struct snd_soc_dapm_widget pmdk_es8388_dapm_widgets[] = {
+	SND_SOC_DAPM_HP("Front", NULL),
+	SND_SOC_DAPM_HP("Rear", NULL),
+
+	SND_SOC_DAPM_MIC("FrontIn", NULL),
+	SND_SOC_DAPM_MIC("RearIn", NULL),
+};
+
+/* PMDK control */
+static const struct snd_kcontrol_new pmdk_controls[] = {
+	SOC_DAPM_PIN_SWITCH("Front"),
+	SOC_DAPM_PIN_SWITCH("Rear"),
+	SOC_DAPM_PIN_SWITCH("FrontIn"),
+	SOC_DAPM_PIN_SWITCH("RearIn"),
+};
+
+/* PMDK connections */
+static const struct snd_soc_dapm_route pmdk_es8388_audio_map[] = {
+	{"LINPUT1", NULL, "FrontIn"},
+	{"RINPUT1", NULL, "FrontIn"},
+
+	{"LINPUT2", NULL, "RearIn"},
+	{"RINPUT2", NULL, "RearIn"},
+
+	{"Front", NULL, "LOUT1"},
+	{"Front", NULL, "ROUT1"},
+
+	{"Rear", NULL, "LOUT2"},
+	{"Rear", NULL, "ROUT2"},
+};
+
+static int pmdk_es8388_init(struct snd_soc_pcm_runtime *rtd)
+{
+	int ret;
+
+	/* Jack detection API stuff */
+	ret = snd_soc_card_jack_new(rtd->card, "Headset Jack", SND_JACK_HEADSET,
+			    &hs_jack, hs_jack_pins,
+			    ARRAY_SIZE(hs_jack_pins));
+	if (ret)
+		goto err;
+
+	ret = snd_soc_jack_add_gpios(&hs_jack, ARRAY_SIZE(hs_jack_gpios),
+				hs_jack_gpios);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	return ret;
+}
+
+#define PMDK_DAI_FMT (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | \
+	SND_SOC_DAIFMT_CBS_CFS)
+
+SND_SOC_DAILINK_DEFS(pmdk_es8388,
+	DAILINK_COMP_ARRAY(COMP_CPU("phytium-i2s-lsd")),
+	DAILINK_COMP_ARRAY(COMP_CODEC("i2c-ESSX8388:00", "es8388-hifi")),
+	DAILINK_COMP_ARRAY(COMP_PLATFORM("snd-soc-dummy")));
+
+static struct snd_soc_dai_link pmdk_dai[] = {
+	{
+		.name = "ES8388 HIFI",
+		.stream_name = "ES8388 HIFI",
+		.dai_fmt = PMDK_DAI_FMT,
+		.init = pmdk_es8388_init,
+		SND_SOC_DAILINK_REG(pmdk_es8388),
+	},
+};
+
+static struct snd_soc_card pmdk = {
+	.name = "PMDK-I2S",
+	.owner = THIS_MODULE,
+	.dai_link = pmdk_dai,
+	.num_links = ARRAY_SIZE(pmdk_dai),
+
+	.dapm_widgets = pmdk_es8388_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(pmdk_es8388_dapm_widgets),
+	.controls = pmdk_controls,
+	.num_controls = ARRAY_SIZE(pmdk_controls),
+	.dapm_routes = pmdk_es8388_audio_map,
+	.num_dapm_routes = ARRAY_SIZE(pmdk_es8388_audio_map),
+};
+
+static int pmdk_sound_probe(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = &pmdk;
+	struct device *dev = &pdev->dev;
+	int n;
+
+	card->dev = dev;
+	hs_jack_gpios[0].gpiod_dev = dev;
+	n = gpiod_count(dev, "det");
+
+	if (n < 0)
+		pmdk_dai[0].init = NULL;
+
+	return devm_snd_soc_register_card(&pdev->dev, card);
+}
+
+static const struct acpi_device_id pmdk_sound_acpi_match[] = {
+	{ "PHYT8004", 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, pmdk_sound_acpi_match);
+
+static struct platform_driver pmdk_sound_driver = {
+	.probe = pmdk_sound_probe,
+	.driver = {
+		.name = "pmdk_es8388",
+		.acpi_match_table = pmdk_sound_acpi_match,
+#ifdef CONFIG_PM
+		.pm = &snd_soc_pm_ops,
+#endif
+	},
+};
+
+module_platform_driver(pmdk_sound_driver);
+
+MODULE_AUTHOR("Zhang Yiqun<zhangyiqun@phytium.com.cn>");
+MODULE_DESCRIPTION("ALSA SoC PMDK ES8388");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/phytium/image/Makefile b/target/linux/phytium/image/Makefile
new file mode 100644
index 00000000000000..f0459fc7697d0d
--- /dev/null
+++ b/target/linux/phytium/image/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2016-2017 Yousong Zhou <yszhou4tech@gmail.com>
+# Copyright (c) 2023 Phytium Technology Co., Ltd.
+# Copyright (C) 2023-2024 Ailick <277498654@qq.com>
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+define Build/Compile
+	$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux
+endef
+
+include $(SUBTARGET).mk
+
+$(eval $(call BuildImage))
diff --git a/target/linux/phytium/image/armv8.mk b/target/linux/phytium/image/armv8.mk
new file mode 100644
index 00000000000000..b3db8cc2b0df92
--- /dev/null
+++ b/target/linux/phytium/image/armv8.mk
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2023-2024 Ailick <277498654@qq.com>
+
+GRUB2_VARIANT =
+GRUB_TERMINALS =
+GRUB_SERIAL_CONFIG =
+GRUB_TERMINAL_CONFIG =
+GRUB_CONSOLE_CMDLINE = earlycon
+
+ifneq ($(CONFIG_GRUB_CONSOLE),)
+  GRUB_TERMINALS += console
+endif
+
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_GRUB_SERIAL))
+
+GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1 --rtscts=$(if $(CONFIG_GRUB_FLOWCONTROL),on,off)
+GRUB_TERMINALS += serial
+
+GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS)
+
+ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+ROOTPART:=$(if $(ROOTPART),$(ROOTPART),PARTUUID=$(IMG_PART_SIGNATURE)-02)
+GPT_ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+GPT_ROOTPART:=$(if $(GPT_ROOTPART),$(GPT_ROOTPART),PARTUUID=$(shell echo $(IMG_PART_DISKGUID) | sed 's/00$$/02/'))
+
+GRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT))
+GRUB_TITLE:=$(call qstrip,$(CONFIG_GRUB_TITLE))
+
+BOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS))
+
+define Build/combined
+  $(INSTALL_DIR) $@.boot/
+	$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/efi/openwrt/
+	-$(CP) $(STAGING_DIR_ROOT)/boot/. $@.boot/boot/
+	$(if $(filter $(1),efi),
+		$(INSTALL_DIR) $@.boot/efi/boot
+		$(CP) $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_aarch64),aa64,arm).efi $@.boot/efi/openwrt/
+		$(CP) $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_aarch64),aa64,arm).efi $@.boot/efi/boot/
+	)
+	KERNELPARTTYPE=ef FAT_TYPE="32" PADDING="1" SIGNATURE="$(IMG_PART_SIGNATURE)" \
+		$(if $(filter $(1),efi),GUID="$(IMG_PART_DISKGUID)") $(SCRIPT_DIR)/gen_image_generic.sh \
+		$@ \
+		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+		256
+endef
+
+define Build/grub-config
+	rm -fR $@.boot
+	$(INSTALL_DIR) $@.boot/efi/openwrt/
+	sed \
+		-e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \
+		-e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \
+		-e 's#@ROOTPART@#root=$(ROOTPART) rootwait#g' \
+		-e 's#@GPT_ROOTPART@#root=$(GPT_ROOTPART) rootwait#g' \
+		-e 's#@CMDLINE@#$(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE)#g' \
+		-e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \
+		-e 's#@TITLE@#$(GRUB_TITLE)#g' \
+		-e 's#@KERNEL_NAME@#$(KERNEL_NAME)#g' \
+		./grub-$(1).cfg > $@.boot/efi/openwrt/grub.cfg
+endef
+
+define Build/grub-install
+	rm -fR $@.grub2
+	$(INSTALL_DIR) $@.grub2
+endef
+
+DEVICE_VARS += GRUB2_VARIANT UBOOT
+define Device/efi-default
+  IMAGE/rootfs.img := append-rootfs | pad-to $(ROOTFS_PARTSIZE)
+  IMAGE/rootfs.img.gz := append-rootfs | pad-to $(ROOTFS_PARTSIZE) | gzip
+  IMAGE/combined.img := grub-config efi | combined efi | grub-install efi | append-metadata
+  IMAGE/combined.img.gz := grub-config efi | combined efi | grub-install efi | gzip | append-metadata
+  IMAGE/combined.vmdk := grub-config efi | combined efi | grub-install efi | qemu-image vmdk
+ ifeq ($(CONFIG_TARGET_IMAGES_GZIP),y)
+    IMAGES-y := rootfs.img.gz
+    IMAGES-y += combined.img.gz
+  else
+    IMAGES-y := rootfs.img
+    IMAGES-y += combined.img
+  endif
+  ifeq ($(CONFIG_VMDK_IMAGES),y)
+    IMAGES-y += combined.vmdk
+  endif
+  KERNEL := kernel-bin
+  KERNEL_INSTALL := 1
+  IMAGES := $$(IMAGES-y)
+  ARTIFACTS := $$(ARTIFACTS-y)
+  SUPPORTED_DEVICES :=
+ ifeq ($(CONFIG_arm),y)
+  KERNEL_NAME = zImage
+ endif
+endef
+
+define Device/generic
+  $(call Device/efi-default)
+  DEVICE_TITLE := Generic EFI Boot
+  GRUB2_VARIANT := generic
+  FILESYSTEMS := ext4 squashfs
+  UBOOT := $(if $(CONFIG_aarch64),qemu_armv8,qemu_armv7)
+  DEVICE_PACKAGES += kmod-amazon-ena kmod-e1000e kmod-vmxnet3 kmod-rtc-rx8025 \
+	kmod-i2c-mux-pca954x kmod-gpio-pca953x partx-utils kmod-wdt-sp805 \
+	kmod-mvneta kmod-mvpp2 kmod-fsl-dpaa1-net kmod-fsl-dpaa2-net \
+	kmod-fsl-enetc-net kmod-dwmac-imx kmod-fsl-fec kmod-thunderx-net \
+	kmod-dwmac-rockchip kmod-dwmac-sun8i kmod-phy-aquantia kmod-phy-broadcom \
+	kmod-phy-marvell kmod-phy-marvell-10g kmod-sfp kmod-atlantic \
+	kmod-bcmgenet kmod-octeontx2-net
+endef
+TARGET_DEVICES += generic
+
diff --git a/target/linux/phytium/image/bin/e2000_miniitx_uboot.bin b/target/linux/phytium/image/bin/e2000_miniitx_uboot.bin
new file mode 100644
index 00000000000000..6966cfa7118270
Binary files /dev/null and b/target/linux/phytium/image/bin/e2000_miniitx_uboot.bin differ
diff --git a/target/linux/phytium/image/bin/e2000d_demo_uboot.bin b/target/linux/phytium/image/bin/e2000d_demo_uboot.bin
new file mode 100644
index 00000000000000..43a8615afdfd71
Binary files /dev/null and b/target/linux/phytium/image/bin/e2000d_demo_uboot.bin differ
diff --git a/target/linux/phytium/image/bin/e2000q_demo_uboot.bin b/target/linux/phytium/image/bin/e2000q_demo_uboot.bin
new file mode 100644
index 00000000000000..94fc91e5d49eb0
Binary files /dev/null and b/target/linux/phytium/image/bin/e2000q_demo_uboot.bin differ
diff --git a/target/linux/phytium/image/bin/fip-all-2GB.bin b/target/linux/phytium/image/bin/fip-all-2GB.bin
new file mode 100644
index 00000000000000..d6d181cdc2cde1
Binary files /dev/null and b/target/linux/phytium/image/bin/fip-all-2GB.bin differ
diff --git a/target/linux/phytium/image/bin/fip-all-4GB.bin b/target/linux/phytium/image/bin/fip-all-4GB.bin
new file mode 100644
index 00000000000000..0243418107707f
Binary files /dev/null and b/target/linux/phytium/image/bin/fip-all-4GB.bin differ
diff --git a/target/linux/phytium/image/bin/uboot-env.txt b/target/linux/phytium/image/bin/uboot-env.txt
new file mode 100644
index 00000000000000..241154affd574b
--- /dev/null
+++ b/target/linux/phytium/image/bin/uboot-env.txt
@@ -0,0 +1,12 @@
+arch=arm
+cpu=armv8
+vendor=phytium
+baudrate=115200
+board=e2000
+board_name=e2000
+bootargs=console=ttyAMA1,115200 audit=0 earlycon=pl011,0x2800d000 root=/dev/mtdblock3 rw rootfstype=squashfs mtdparts=spi1.0:3M(uboot),64k(dtb),6M(kernel),-(rootfs)
+bootcmd=run load_kernel; run load_fdt; run boot_os;
+bootdelay=2
+load_fdt=cp.b 0x300000 0x90000000 0x10000
+load_kernel=cp.b 0x310000 0x90100000 0x600000
+boot_os=bootm 0x90100000 - 0x90000000
diff --git a/target/linux/phytium/image/dts_common.mk b/target/linux/phytium/image/dts_common.mk
new file mode 100644
index 00000000000000..1e616e74f00806
--- /dev/null
+++ b/target/linux/phytium/image/dts_common.mk
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2023-2024 Ailick <277498654@qq.com>
+
+### Image scripts ###
+# This function can be used to change the uboot environment variables.
+# In e2000.mk, use this function like this:
+# IMAGE/factory.bin := change-uboot-env $(1) $$(UBOOT_PATH) | append-uboot | xxx
+define Build/change-uboot-env
+	$(if $(findstring demo,$(word 1,$(1))), sed -i 's/spi0.0/spi1.0/g' ./bin/uboot-env.txt)
+	$(if $(findstring miniitx,$(word 1,$(1))), sed -i 's/spi1.0/spi0.0/g' ./bin/uboot-env.txt)
+	mkenvimage -s 0x1000 -o uboot-env.bin ./bin/uboot-env.txt
+	dd if=uboot-env.bin of=$(word 2,$(1)) bs=1k seek=1472 conv=notrunc
+	rm -f uboot-env.bin
+endef
+
+### Devices ###
+define Device/Default
+  PROFILES := Default
+  KERNEL_NAME := Image
+  KERNEL_LOADADDR := 0x80080000
+  KERNEL := kernel-bin | gzip | uImage gzip
+  DEVICE_DTS_DIR := $(DTS_DIR)/phytium
+  DEVICE_DTS = $(1)
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-dtb | pad-to 64k | append-kernel \
+	  | pad-to 6208k | append-rootfs | pad-rootfs | append-metadata
+  DEVICE_PACKAGES := uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug
+endef
diff --git a/target/linux/phytium/image/e2000.mk b/target/linux/phytium/image/e2000.mk
new file mode 100644
index 00000000000000..ee8ffd89b72daf
--- /dev/null
+++ b/target/linux/phytium/image/e2000.mk
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Phytium Technology Co., Ltd.
+
+include dts_common.mk
+
+define Device/e2000q-demo-board
+  DEVICE_VENDOR := Phytium
+  DEVICE_MODEL := E2000Q Demo
+  SOC := e2000
+  UBOOT_PATH := ./bin/e2000q_demo_uboot.bin
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-uboot | pad-to 3072k | append-dtb |\
+	  pad-to 3136k | append-kernel | pad-to 9280k |\
+	  append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += e2000q-demo-board
+
+define Device/e2000d-demo-board
+  DEVICE_VENDOR := Phytium
+  DEVICE_MODEL := E2000D Demo
+  SOC := e2000
+  UBOOT_PATH := ./bin/e2000d_demo_uboot.bin
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-uboot | pad-to 3072k | append-dtb |\
+	  pad-to 3136k | append-kernel | pad-to 9280k |\
+	  append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += e2000d-demo-board
+
+define Device/e2000q-miniitx-board
+  DEVICE_VENDOR := EmbedWay
+  DEVICE_MODEL := E2000Q MiniITX
+  SOC := e2000
+  UBOOT_PATH := ./bin/e2000_miniitx_uboot.bin
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-uboot | pad-to 3072k | append-dtb |\
+	  pad-to 3136k | append-kernel | pad-to 9280k |\
+	  append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += e2000q-miniitx-board
+
+define Device/e2000d-miniitx-board
+  DEVICE_VENDOR := EmbedWay
+  DEVICE_MODEL := E2000D MiniITX
+  SOC := e2000
+  UBOOT_PATH := ./bin/e2000_miniitx_uboot.bin
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-uboot | pad-to 3072k | append-dtb |\
+	  pad-to 3136k | append-kernel | pad-to 9280k |\
+	  append-rootfs | pad-rootfs | append-metadata
+endef
+TARGET_DEVICES += e2000d-miniitx-board
diff --git a/target/linux/phytium/image/grub-efi.cfg b/target/linux/phytium/image/grub-efi.cfg
new file mode 100644
index 00000000000000..03ca275bc86050
--- /dev/null
+++ b/target/linux/phytium/image/grub-efi.cfg
@@ -0,0 +1,14 @@
+@SERIAL_CONFIG@
+@TERMINAL_CONFIG@
+
+set default="0"
+set timeout="@TIMEOUT@"
+
+menuentry "@TITLE@" {
+	search --set=root --label kernel
+	linux /efi/openwrt/@KERNEL_NAME@ @GPT_ROOTPART@ @CMDLINE@ noinitrd ima_appraise=off
+}
+menuentry "@TITLE@ (failsafe)" {
+	search --set=root --label kernel
+	linux /efi/openwrt/@KERNEL_NAME@ failsafe=true @GPT_ROOTPART@ @CMDLINE@ noinitrd ima_appraise=off
+}
diff --git a/target/linux/phytium/image/phytiumpi.mk b/target/linux/phytium/image/phytiumpi.mk
new file mode 100644
index 00000000000000..a7d0e4efe21e6b
--- /dev/null
+++ b/target/linux/phytium/image/phytiumpi.mk
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Phytium Technology Co., Ltd.
+
+include dts_common.mk
+
+define Device/phytiumpi_firefly_4GB
+  DEVICE_VENDOR := FireFly
+  DEVICE_MODEL := PhytiumPi 4GB
+  SOC := phytiumpi
+  DEVICE_DTS := phytiumpi_firefly
+  KERNEL_SUFFIX := -fit-uImage.itb
+  DEVICE_DTS_CONFIG := phytium
+  KERNEL := kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb
+  UBOOT_PATH := ./bin/fip-all-4GB.bin
+  FILESYSTEMS := ext4
+  IMAGES += factory.bin
+  SUPPORTED_DEVICES := phytiumpi_firefly
+  IMAGE/factory.bin := append-uboot | pad-to 4096k | append-kernel | pad-to 10240k |\
+	  append-rootfs | pad-rootfs | append-metadata
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += phytiumpi_firefly_4GB
+
+define Device/phytiumpi_firefly_2GB
+  DEVICE_VENDOR := FireFly
+  DEVICE_MODEL := PhytiumPi 2GB
+  SOC := phytiumpi
+  DEVICE_DTS := phytiumpi_firefly
+  KERNEL_SUFFIX := -fit-uImage.itb
+  DEVICE_DTS_CONFIG := phytium
+  KERNEL := kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb
+  UBOOT_PATH := ./bin/fip-all-2GB.bin
+  FILESYSTEMS := ext4
+  IMAGES += factory.bin
+  SUPPORTED_DEVICES := phytiumpi_firefly
+  IMAGE/factory.bin := append-uboot | pad-to 4096k | append-kernel | pad-to 10240k |\
+	  append-rootfs | pad-rootfs | append-metadata
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += phytiumpi_firefly_2GB
diff --git a/target/linux/phytium/modules.mk b/target/linux/phytium/modules.mk
new file mode 100644
index 00000000000000..2ed807460e5b38
--- /dev/null
+++ b/target/linux/phytium/modules.mk
@@ -0,0 +1,30 @@
+define KernelPackage/hwmon-phytium
+  SUBMENU:=$(HWMON_MENU)
+  TITLE:=Phytium monitoring support
+  KCONFIG:=CONFIG_SENSORS_PHYTIUM
+  FILES:=$(LINUX_DIR)/drivers/hwmon/tacho-phytium.ko
+  AUTOLOAD:=$(call AutoLoad,50,tacho-phytium)
+  $(call AddDepends/hwmon,@TARGET_phytium)
+endef
+
+define KernelPackage/hwmon-phytium/description
+  Hwmon driver for Phytium tachometer.
+endef
+
+$(eval $(call KernelPackage,hwmon-phytium))
+
+define KernelPackage/drm-phytium
+  SUBMENU:=$(VIDEO_MENU)
+  TITLE:=DRM Support for Phytium Graphics Card
+  DEPENDS:=@TARGET_phytium @DISPLAY_SUPPORT +kmod-drm +kmod-drm-kms-helper \
+	+(LINUX_5_10||LINUX_6_1||LINUX_6_3||LINUX_6_4||LINUX_6_5||LINUX_6_6):kmod-acpi-video
+  KCONFIG:=CONFIG_DRM_PHYTIUM
+  FILES:=$(LINUX_DIR)/drivers/gpu/drm/phytium/phytium-dc-drm.ko
+  AUTOLOAD:=$(call AutoProbe,phytium-dc-drm)
+endef
+
+define KernelPackage/drm-phytium/description
+  Direct Rendering Manager (DRM) support for Phytium Graphics Card
+endef
+
+$(eval $(call KernelPackage,drm-phytium))
diff --git a/target/linux/phytium/patches-5.10/001-add-phytium-support.patch b/target/linux/phytium/patches-5.10/001-add-phytium-support.patch
new file mode 100644
index 00000000000000..4bbb851d4db6b3
--- /dev/null
+++ b/target/linux/phytium/patches-5.10/001-add-phytium-support.patch
@@ -0,0 +1,5102 @@
+--- a/Documentation/admin-guide/kernel-parameters.txt
++++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -3898,6 +3898,10 @@
+ 		force	Enable ASPM even on devices that claim not to support it.
+ 			WARNING: Forcing ASPM on may cause system lockups.
+ 
++	pcie_hp=	[PCIE] PCI Express Hotplug driver options:
++		nomsi	Do not use MSI for PCI Express Native Hotplug (this
++			makes all PCIe ports use INTx for hotplug services).
++
+ 	pcie_ports=	[PCIE] PCIe port services handling:
+ 		native	Use native PCIe services (PME, AER, DPC, PCIe hotplug)
+ 			even if the platform doesn't give the OS permission to
+--- a/Documentation/devicetree/bindings/arm/cpus.yaml
++++ b/Documentation/devicetree/bindings/arm/cpus.yaml
+@@ -162,6 +162,10 @@ properties:
+       - nvidia,tegra132-denver
+       - nvidia,tegra186-denver
+       - nvidia,tegra194-carmel
++      - phytium,ftc660
++      - phytium,ftc661
++      - phytium,ftc662
++      - phytium,ftc663
+       - qcom,krait
+       - qcom,kryo
+       - qcom,kryo260
+--- a/Documentation/devicetree/bindings/net/macb.txt
++++ b/Documentation/devicetree/bindings/net/macb.txt
+@@ -16,6 +16,8 @@ Required properties:
+   Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
+   Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
+   Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
++  Use "cdns,phytium-gem-1.0" for GEM version 1.0 on Phytium SoCs
++  Use "cdns,phytium-gem-2.0" for GEM version 2.0 on Phytium SoCs
+   Or the generic form: "cdns,emac".
+ - reg: Address and length of the register set for the device
+ 	For "sifive,fu540-c000-gem", second range is required to specify the
+--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+@@ -56,6 +56,7 @@ properties:
+         - amlogic,meson8m2-dwmac
+         - amlogic,meson-gxbb-dwmac
+         - amlogic,meson-axg-dwmac
++        - phytium,gmac
+         - snps,dwmac
+         - snps,dwmac-3.50a
+         - snps,dwmac-3.610
+--- a/arch/arm/include/asm/arch_timer.h
++++ b/arch/arm/include/asm/arch_timer.h
+@@ -7,6 +7,7 @@
+ #include <asm/hwcap.h>
+ #include <linux/clocksource.h>
+ #include <linux/init.h>
++#include <linux/io-64-nonatomic-lo-hi.h>
+ #include <linux/types.h>
+ 
+ #include <clocksource/arm_arch_timer.h>
+@@ -24,29 +25,35 @@ int arch_timer_arch_init(void);
+  * the code. At least it does so with a recent GCC (4.6.3).
+  */
+ static __always_inline
+-void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
++void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
+ {
+ 	if (access == ARCH_TIMER_PHYS_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+-			asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
++			asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
++			isb();
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
++		case ARCH_TIMER_REG_CVAL:
++			asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
+ 			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+-			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
++			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
++			isb();
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
++		case ARCH_TIMER_REG_CVAL:
++			asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val));
+ 			break;
++		default:
++			BUILD_BUG();
+ 		}
++	} else {
++		BUILD_BUG();
+ 	}
+-
+-	isb();
+ }
+ 
+ static __always_inline
+@@ -59,19 +66,19 @@ u32 arch_timer_reg_read_cp15(int access,
+ 		case ARCH_TIMER_REG_CTRL:
+ 			asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+-			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+ 			asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+-			break;
++		default:
++			BUILD_BUG();
+ 		}
++	} else {
++		BUILD_BUG();
+ 	}
+ 
+ 	return val;
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -327,4 +327,9 @@ config ARCH_ZYNQMP
+ 	help
+ 	  This enables support for Xilinx ZynqMP Family
+ 
++config ARCH_PHYTIUM
++    bool "Phytium SoC Family"
++    help
++      This enables support for Phytium ARMv8 SoC family.
++
+ endmenu
+--- a/arch/arm64/boot/dts/Makefile
++++ b/arch/arm64/boot/dts/Makefile
+@@ -30,3 +30,4 @@ subdir-y += ti
+ subdir-y += toshiba
+ subdir-y += xilinx
+ subdir-y += zte
++subdir-y += phytium
+--- a/arch/arm64/include/asm/arch_timer.h
++++ b/arch/arm64/include/asm/arch_timer.h
+@@ -32,7 +32,7 @@
+ 	({								\
+ 		const struct arch_timer_erratum_workaround *__wa;	\
+ 		__wa = __this_cpu_read(timer_unstable_counter_workaround); \
+-		(__wa && __wa->h) ? __wa->h : arch_timer_##h;		\
++		(__wa && __wa->h) ? ({ isb(); __wa->h;}) : arch_timer_##h; \
+ 	})
+ 
+ #else
+@@ -52,8 +52,6 @@ struct arch_timer_erratum_workaround {
+ 	enum arch_timer_erratum_match_type match_type;
+ 	const void *id;
+ 	const char *desc;
+-	u32 (*read_cntp_tval_el0)(void);
+-	u32 (*read_cntv_tval_el0)(void);
+ 	u64 (*read_cntpct_el0)(void);
+ 	u64 (*read_cntvct_el0)(void);
+ 	int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
+@@ -64,25 +62,28 @@ struct arch_timer_erratum_workaround {
+ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
+ 		timer_unstable_counter_workaround);
+ 
+-/* inline sysreg accessors that make erratum_handler() work */
+-static inline notrace u32 arch_timer_read_cntp_tval_el0(void)
++static inline notrace u64 arch_timer_read_cntpct_el0(void)
+ {
+-	return read_sysreg(cntp_tval_el0);
+-}
++	u64 cnt;
+ 
+-static inline notrace u32 arch_timer_read_cntv_tval_el0(void)
+-{
+-	return read_sysreg(cntv_tval_el0);
+-}
++	asm volatile(ALTERNATIVE("isb\n mrs %0, cntpct_el0",
++				 "nop\n" __mrs_s("%0", SYS_CNTPCTSS_EL0),
++				 ARM64_HAS_ECV)
++		     : "=r" (cnt));
+ 
+-static inline notrace u64 arch_timer_read_cntpct_el0(void)
+-{
+-	return read_sysreg(cntpct_el0);
++	return cnt;
+ }
+ 
+ static inline notrace u64 arch_timer_read_cntvct_el0(void)
+ {
+-	return read_sysreg(cntvct_el0);
++	u64 cnt;
++
++	asm volatile(ALTERNATIVE("isb\n mrs %0, cntvct_el0",
++				 "nop\n" __mrs_s("%0", SYS_CNTVCTSS_EL0),
++				 ARM64_HAS_ECV)
++		     : "=r" (cnt));
++
++	return cnt;
+ }
+ 
+ #define arch_timer_reg_read_stable(reg)					\
+@@ -102,51 +103,58 @@ static inline notrace u64 arch_timer_rea
+  * the code.
+  */
+ static __always_inline
+-void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
++void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
+ {
+ 	if (access == ARCH_TIMER_PHYS_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+ 			write_sysreg(val, cntp_ctl_el0);
++			isb();
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			write_sysreg(val, cntp_tval_el0);
++		case ARCH_TIMER_REG_CVAL:
++			write_sysreg(val, cntp_cval_el0);
+ 			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+ 			write_sysreg(val, cntv_ctl_el0);
++			isb();
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			write_sysreg(val, cntv_tval_el0);
++		case ARCH_TIMER_REG_CVAL:
++			write_sysreg(val, cntv_cval_el0);
+ 			break;
++		default:
++			BUILD_BUG();
+ 		}
++	} else {
++		BUILD_BUG();
+ 	}
+-
+-	isb();
+ }
+ 
+ static __always_inline
+-u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
++u64 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
+ {
+ 	if (access == ARCH_TIMER_PHYS_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+ 			return read_sysreg(cntp_ctl_el0);
+-		case ARCH_TIMER_REG_TVAL:
+-			return arch_timer_reg_read_stable(cntp_tval_el0);
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+ 			return read_sysreg(cntv_ctl_el0);
+-		case ARCH_TIMER_REG_TVAL:
+-			return arch_timer_reg_read_stable(cntv_tval_el0);
++		default:
++			BUILD_BUG();
+ 		}
+ 	}
+ 
+-	BUG();
++	BUILD_BUG();
++	unreachable();
+ }
+ 
+ static inline u32 arch_timer_get_cntfrq(void)
+@@ -169,7 +177,6 @@ static __always_inline u64 __arch_counte
+ {
+ 	u64 cnt;
+ 
+-	isb();
+ 	cnt = arch_timer_reg_read_stable(cntpct_el0);
+ 	arch_counter_enforce_ordering(cnt);
+ 	return cnt;
+@@ -179,8 +186,10 @@ static __always_inline u64 __arch_counte
+ {
+ 	u64 cnt;
+ 
+-	isb();
+-	cnt = read_sysreg(cntpct_el0);
++	asm volatile(ALTERNATIVE("isb\n mrs %0, cntpct_el0",
++				 "nop\n" __mrs_s("%0", SYS_CNTPCTSS_EL0),
++				 ARM64_HAS_ECV)
++		     : "=r" (cnt));
+ 	arch_counter_enforce_ordering(cnt);
+ 	return cnt;
+ }
+@@ -189,7 +198,6 @@ static __always_inline u64 __arch_counte
+ {
+ 	u64 cnt;
+ 
+-	isb();
+ 	cnt = arch_timer_reg_read_stable(cntvct_el0);
+ 	arch_counter_enforce_ordering(cnt);
+ 	return cnt;
+@@ -199,8 +207,10 @@ static __always_inline u64 __arch_counte
+ {
+ 	u64 cnt;
+ 
+-	isb();
+-	cnt = read_sysreg(cntvct_el0);
++	asm volatile(ALTERNATIVE("isb\n mrs %0, cntvct_el0",
++				 "nop\n" __mrs_s("%0", SYS_CNTVCTSS_EL0),
++				 ARM64_HAS_ECV)
++		     : "=r" (cnt));
+ 	arch_counter_enforce_ordering(cnt);
+ 	return cnt;
+ }
+--- a/arch/arm64/include/asm/cpucaps.h
++++ b/arch/arm64/include/asm/cpucaps.h
+@@ -69,7 +69,7 @@
+ #define ARM64_SPECTRE_BHB			59
+ #define ARM64_WORKAROUND_2457168		60
+ #define ARM64_WORKAROUND_1742098		61
+-
+-#define ARM64_NCAPS				62
++#define ARM64_HAS_ECV				62
++#define ARM64_NCAPS				63
+ 
+ #endif /* __ASM_CPUCAPS_H */
+--- a/arch/arm64/include/asm/esr.h
++++ b/arch/arm64/include/asm/esr.h
+@@ -227,6 +227,9 @@
+ #define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
+ 					 ESR_ELx_SYS64_ISS_DIR_READ)
+ 
++#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
++					 ESR_ELx_SYS64_ISS_DIR_READ)
++
+ #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
+ 					 ESR_ELx_SYS64_ISS_DIR_READ)
+ 
+@@ -317,6 +320,9 @@
+ #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
+ 					 ESR_ELx_CP15_64_ISS_DIR_READ)
+ 
++#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
++					 ESR_ELx_CP15_64_ISS_DIR_READ)
++
+ #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
+ 					 ESR_ELx_CP15_32_ISS_DIR_READ)
+ 
+--- a/arch/arm64/include/asm/sysreg.h
++++ b/arch/arm64/include/asm/sysreg.h
+@@ -453,6 +453,9 @@
+ 
+ #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
+ 
++#define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
++#define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
++
+ #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
+ #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
+ #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
+--- a/arch/arm64/kernel/cpufeature.c
++++ b/arch/arm64/kernel/cpufeature.c
+@@ -1769,6 +1769,16 @@ static const struct arm64_cpu_capabiliti
+ 		.sign = FTR_UNSIGNED,
+ 		.min_field_value = 1,
+ 	},
++	{
++		.desc = "Enhanced Counter Virtualization",
++		.capability = ARM64_HAS_ECV,
++		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
++		.matches = has_cpuid_feature,
++		.sys_reg = SYS_ID_AA64MMFR0_EL1,
++		.field_pos = ID_AA64MMFR0_ECV_SHIFT,
++		.sign = FTR_UNSIGNED,
++		.min_field_value = 1,
++	},
+ #ifdef CONFIG_ARM64_PAN
+ 	{
+ 		.desc = "Privileged Access Never",
+--- a/arch/arm64/kernel/traps.c
++++ b/arch/arm64/kernel/traps.c
+@@ -553,6 +553,12 @@ static const struct sys64_hook sys64_hoo
+ 		.handler = cntvct_read_handler,
+ 	},
+ 	{
++		/* Trap read access to CNTVCTSS_EL0 */
++		.esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
++		.esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS,
++		.handler = cntvct_read_handler,
++	},
++	{
+ 		/* Trap read access to CNTFRQ_EL0 */
+ 		.esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
+ 		.esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
+@@ -628,6 +634,11 @@ static const struct sys64_hook cp15_64_h
+ 		.esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
+ 		.handler = compat_cntvct_read_handler,
+ 	},
++	{
++		.esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
++		.esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS,
++		.handler = compat_cntvct_read_handler,
++	},
+ 	{},
+ };
+ 
+--- a/arch/arm64/mm/flush.c
++++ b/arch/arm64/mm/flush.c
+@@ -78,6 +78,8 @@ EXPORT_SYMBOL(flush_dcache_page);
+  * Additional functions defined in assembly.
+  */
+ EXPORT_SYMBOL(__flush_icache_range);
++EXPORT_SYMBOL(__flush_dcache_area);
++EXPORT_SYMBOL(__inval_dcache_area);
+ 
+ #ifdef CONFIG_ARCH_HAS_PMEM_API
+ void arch_wb_cache_pmem(void *addr, size_t size)
+--- a/drivers/acpi/acpi_apd.c
++++ b/drivers/acpi/acpi_apd.c
+@@ -158,6 +158,16 @@ static const struct apd_device_desc hip0
+ 	.fixed_clk_rate = 125000000,
+ };
+ 
++static const struct apd_device_desc phytium_i2c_desc = {
++	.setup = acpi_apd_setup,
++	.fixed_clk_rate = 200000000,
++};
++
++static const struct apd_device_desc phytium_pe220x_i2c_desc = {
++	.setup = acpi_apd_setup,
++	.fixed_clk_rate = 50000000,
++};
++
+ static const struct apd_device_desc thunderx2_i2c_desc = {
+ 	.setup = acpi_apd_setup,
+ 	.fixed_clk_rate = 125000000,
+@@ -240,6 +250,8 @@ static const struct acpi_device_id acpi_
+ 	{ "HISI02A2", APD_ADDR(hip08_i2c_desc) },
+ 	{ "HISI02A3", APD_ADDR(hip08_lite_i2c_desc) },
+ 	{ "HISI0173", APD_ADDR(hip08_spi_desc) },
++	{ "PHYT0003", APD_ADDR(phytium_i2c_desc) },
++	{ "PHYT0038", APD_ADDR(phytium_pe220x_i2c_desc) },
+ 	{ "NXP0001", APD_ADDR(nxp_i2c_desc) },
+ #endif
+ 	{ }
+--- a/drivers/acpi/internal.h
++++ b/drivers/acpi/internal.h
+@@ -90,6 +90,18 @@ bool acpi_scan_is_offline(struct acpi_de
+ acpi_status acpi_sysfs_table_handler(u32 event, void *table, void *context);
+ void acpi_scan_table_handler(u32 event, void *table, void *context);
+ 
++#ifdef CONFIG_ACPI_GENERIC_GSI
++int acpi_register_irq(struct device *dev, u32 hwirq, int trigger,
++		      int polarity, struct fwnode_handle *fwnode);
++#else
++static inline
++int acpi_register_irq(struct device *dev, u32 hwirq, int trigger,
++		      int polarity, struct fwnode_handle *fwnode)
++{
++	return acpi_register_gsi(dev, hwirq, trigger, polarity);
++}
++#endif
++
+ /* --------------------------------------------------------------------------
+                      Device Node Initialization / Removal
+    -------------------------------------------------------------------------- */
+--- a/drivers/acpi/irq.c
++++ b/drivers/acpi/irq.c
+@@ -10,6 +10,8 @@
+ #include <linux/irqdomain.h>
+ #include <linux/of.h>
+ 
++#include "internal.h"
++
+ enum acpi_irq_model_id acpi_irq_model;
+ 
+ static struct fwnode_handle *acpi_gsi_domain_id;
+@@ -38,29 +40,19 @@ int acpi_gsi_to_irq(u32 gsi, unsigned in
+ }
+ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
+ 
+-/**
+- * acpi_register_gsi() - Map a GSI to a linux IRQ number
+- * @dev: device for which IRQ has to be mapped
+- * @gsi: GSI IRQ number
+- * @trigger: trigger type of the GSI number to be mapped
+- * @polarity: polarity of the GSI to be mapped
+- *
+- * Returns: a valid linux IRQ number on success
+- *          -EINVAL on failure
+- */
+-int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
+-		      int polarity)
++int acpi_register_irq(struct device *dev, u32 hwirq, int trigger,
++		      int polarity, struct fwnode_handle *fwnode)
+ {
+ 	struct irq_fwspec fwspec;
+ 	unsigned int irq;
+ 
+-	if (WARN_ON(!acpi_gsi_domain_id)) {
+-		pr_warn("GSI: No registered irqchip, giving up\n");
++	if (!fwnode) {
++		dev_warn(dev, "No registered irqchip for hwirq %d\n", hwirq);
+ 		return -EINVAL;
+ 	}
+ 
+-	fwspec.fwnode = acpi_gsi_domain_id;
+-	fwspec.param[0] = gsi;
++	fwspec.fwnode = fwnode;
++	fwspec.param[0] = hwirq;
+ 	fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
+ 	fwspec.param_count = 2;
+ 
+@@ -70,6 +62,22 @@ int acpi_register_gsi(struct device *dev
+ 
+ 	return irq;
+ }
++
++/**
++ * acpi_register_gsi() - Map a GSI to a linux IRQ number
++ * @dev: device for which IRQ has to be mapped
++ * @gsi: GSI IRQ number
++ * @trigger: trigger type of the GSI number to be mapped
++ * @polarity: polarity of the GSI to be mapped
++ *
++ * Returns: a valid linux IRQ number on success
++ *          -EINVAL on failure
++ */
++int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
++		      int polarity)
++{
++	return acpi_register_irq(dev, gsi, trigger, polarity, acpi_gsi_domain_id);
++}
+ EXPORT_SYMBOL_GPL(acpi_register_gsi);
+ 
+ /**
+@@ -97,7 +105,7 @@ EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
+  * Return:
+  * The referenced device fwhandle or NULL on failure
+  */
+-static struct fwnode_handle *
++struct fwnode_handle *
+ acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
+ {
+ 	struct fwnode_handle *result;
+--- a/drivers/acpi/pci_irq.c
++++ b/drivers/acpi/pci_irq.c
+@@ -22,6 +22,8 @@
+ #include <linux/slab.h>
+ #include <linux/interrupt.h>
+ 
++#include "internal.h"
++
+ #define PREFIX "ACPI: "
+ 
+ #define _COMPONENT		ACPI_PCI_COMPONENT
+@@ -410,6 +412,7 @@ int acpi_pci_irq_enable(struct pci_dev *
+ 	char *link = NULL;
+ 	char link_desc[16];
+ 	int rc;
++	struct fwnode_handle *rs_fwnode;
+ 
+ 	pin = dev->pin;
+ 	if (!pin) {
+@@ -438,7 +441,8 @@ int acpi_pci_irq_enable(struct pci_dev *
+ 			gsi = acpi_pci_link_allocate_irq(entry->link,
+ 							 entry->index,
+ 							 &triggering, &polarity,
+-							 &link);
++							 &link,
++							 &rs_fwnode);
+ 		else
+ 			gsi = entry->index;
+ 	} else
+@@ -462,7 +466,7 @@ int acpi_pci_irq_enable(struct pci_dev *
+ 		return 0;
+ 	}
+ 
+-	rc = acpi_register_gsi(&dev->dev, gsi, triggering, polarity);
++	rc = acpi_register_irq(&dev->dev, gsi, triggering, polarity, rs_fwnode);
+ 	if (rc < 0) {
+ 		dev_warn(&dev->dev, "PCI INT %c: failed to register GSI\n",
+ 			 pin_name(pin));
+--- a/drivers/acpi/pci_link.c
++++ b/drivers/acpi/pci_link.c
+@@ -59,6 +59,7 @@ struct acpi_pci_link_irq {
+ 	u8 resource_type;
+ 	u8 possible_count;
+ 	u32 possible[ACPI_PCI_LINK_MAX_POSSIBLE];
++	struct acpi_resource_source resource_source;
+ 	u8 initialized:1;
+ 	u8 reserved:7;
+ };
+@@ -120,6 +121,8 @@ static acpi_status acpi_pci_link_check_p
+ 		{
+ 			struct acpi_resource_extended_irq *p =
+ 			    &resource->data.extended_irq;
++			struct acpi_resource_source *rs =
++			    &link->irq.resource_source;
+ 			if (!p || !p->interrupt_count) {
+ 				printk(KERN_WARNING PREFIX
+ 					      "Blank _PRS EXT IRQ resource\n");
+@@ -140,6 +143,12 @@ static acpi_status acpi_pci_link_check_p
+ 			link->irq.triggering = p->triggering;
+ 			link->irq.polarity = p->polarity;
+ 			link->irq.resource_type = ACPI_RESOURCE_TYPE_EXTENDED_IRQ;
++			if (p->resource_source.string_length) {
++				rs->index = p->resource_source.index;
++				rs->string_length = p->resource_source.string_length;
++				rs->string_ptr = kstrdup(p->resource_source.string_ptr,
++							 GFP_KERNEL);
++			}
+ 			break;
+ 		}
+ 	default:
+@@ -326,7 +335,8 @@ static int acpi_pci_link_set(struct acpi
+ 			resource->res.data.extended_irq.shareable = ACPI_SHARED;
+ 		resource->res.data.extended_irq.interrupt_count = 1;
+ 		resource->res.data.extended_irq.interrupts[0] = irq;
+-		/* ignore resource_source, it's optional */
++		resource->res.data.extended_irq.resource_source =
++			link->irq.resource_source;
+ 		break;
+ 	default:
+ 		printk(KERN_ERR PREFIX "Invalid Resource_type %d\n", link->irq.resource_type);
+@@ -612,7 +622,7 @@ static int acpi_pci_link_allocate(struct
+  * failure: return -1
+  */
+ int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
+-			       int *polarity, char **name)
++			       int *polarity, char **name, struct fwnode_handle **rs_fwnode)
+ {
+ 	int result;
+ 	struct acpi_device *device;
+@@ -656,6 +666,8 @@ int acpi_pci_link_allocate_irq(acpi_hand
+ 		*polarity = link->irq.polarity;
+ 	if (name)
+ 		*name = acpi_device_bid(link->device);
++	if (rs_fwnode)
++		*rs_fwnode = acpi_get_irq_source_fwhandle(&link->irq.resource_source);
+ 	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+ 			  "Link %s is referenced\n",
+ 			  acpi_device_bid(link->device)));
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -536,6 +536,18 @@ config HW_RANDOM_XIPHERA
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called xiphera-trng.
+ 
++config HW_RANDOM_PHYTIUM
++	tristate "Phytium Random Number Generator support"
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++	help
++	  This driver provides kernel-side support for the Random Number
++	  Generator hardware found on Phytium SoCs.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called phytium-rng.
++
++	  If unsure, say Y.
++
+ endif # HW_RANDOM
+ 
+ config UML_RANDOM
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -46,3 +46,5 @@ obj-$(CONFIG_HW_RANDOM_OPTEE) += optee-r
+ obj-$(CONFIG_HW_RANDOM_NPCM) += npcm-rng.o
+ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
+ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
++
++obj-$(CONFIG_HW_RANDOM_PHYTIUM) += phytium-rng.o
+\ No newline at end of file
+--- a/drivers/char/ipmi/Kconfig
++++ b/drivers/char/ipmi/Kconfig
+@@ -109,6 +109,27 @@ config ASPEED_KCS_IPMI_BMC
+ 	  The driver implements the BMC side of the KCS contorller, it
+ 	  provides the access of KCS IO space for BMC side.
+ 
++config PHYTIUM_KCS_IPMI_BMC
++	depends on ARCH_PHYTIUM
++	select IPMI_KCS_BMC
++	select REGMAP_MMIO
++	tristate "PHYTIUM KCS IPMI BMC driver"
++	help
++	  Provides a driver for the KCS (Kerboard Controller Style) IPMI
++	  interface found on Phytium SOCs.
++
++	  The driver implements the BMC side of the KCS controller, it
++	  provides the access of KCS IO space for BMC side.
++
++config PHYTIUM_BT_IPMI_BMC
++	depends on ARCH_PHYTIUM
++	depends on REGMAP && REGMAP_MMIO && MFD_SYSCON
++	tristate "PHYTIUM BT BMC driver"
++	help
++	  Provides a driver for the BT (Block Transfer) IPMI interface
++	  found on Phytium SOCs. The driver implements the BMC
++	  side of the BT interface.
++
+ config NPCM7XX_KCS_IPMI_BMC
+ 	depends on ARCH_NPCM7XX || COMPILE_TEST
+ 	select IPMI_KCS_BMC
+--- a/drivers/char/ipmi/Makefile
++++ b/drivers/char/ipmi/Makefile
+@@ -27,3 +27,5 @@ obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-b
+ obj-$(CONFIG_ASPEED_KCS_IPMI_BMC) += kcs_bmc_aspeed.o
+ obj-$(CONFIG_NPCM7XX_KCS_IPMI_BMC) += kcs_bmc_npcm7xx.o
+ obj-$(CONFIG_IPMB_DEVICE_INTERFACE) += ipmb_dev_int.o
++obj-$(CONFIG_PHYTIUM_KCS_IPMI_BMC) += kcs_bmc_phytium.o
++obj-$(CONFIG_PHYTIUM_BT_IPMI_BMC) += bt_bmc_phytium.o
+\ No newline at end of file
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -41,23 +41,29 @@
+ #define CNTACR_RWVT	BIT(4)
+ #define CNTACR_RWPT	BIT(5)
+ 
+-#define CNTVCT_LO	0x08
+-#define CNTVCT_HI	0x0c
++#define CNTVCT_LO	0x00
++#define CNTPCT_LO	0x08
+ #define CNTFRQ		0x10
+-#define CNTP_TVAL	0x28
++#define CNTP_CVAL_LO	0x20
+ #define CNTP_CTL	0x2c
+-#define CNTV_TVAL	0x38
++#define CNTV_CVAL_LO	0x30
+ #define CNTV_CTL	0x3c
+ 
+-static unsigned arch_timers_present __initdata;
++/*
++ * The minimum amount of time a generic counter is guaranteed to not roll over
++ * (40 years)
++ */
++#define MIN_ROLLOVER_SECS	(40ULL * 365 * 24 * 3600)
+ 
+-static void __iomem *arch_counter_base;
++static unsigned arch_timers_present __initdata;
+ 
+ struct arch_timer {
+ 	void __iomem *base;
+ 	struct clock_event_device evt;
+ };
+ 
++static struct arch_timer *arch_timer_mem __ro_after_init;
++
+ #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
+ 
+ static u32 arch_timer_rate;
+@@ -85,32 +91,57 @@ static int __init early_evtstrm_cfg(char
+ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
+ 
+ /*
++ * Makes an educated guess at a valid counter width based on the Generic Timer
++ * specification. Of note:
++ *   1) the system counter is at least 56 bits wide
++ *   2) a roll-over time of not less than 40 years
++ *
++ * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
++ */
++static int arch_counter_get_width(void)
++{
++	u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_rate;
++
++	/* guarantee the returned width is within the valid range */
++	return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);
++}
++
++/*
+  * Architected system timer support.
+  */
+ 
+ static __always_inline
+-void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
++void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
+ 			  struct clock_event_device *clk)
+ {
+ 	if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
+ 		struct arch_timer *timer = to_arch_timer(clk);
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+-			writel_relaxed(val, timer->base + CNTP_CTL);
++			writel_relaxed((u32)val, timer->base + CNTP_CTL);
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			writel_relaxed(val, timer->base + CNTP_TVAL);
++		case ARCH_TIMER_REG_CVAL:
++			/*
++			 * Not guaranteed to be atomic, so the timer
++			 * must be disabled at this point.
++			 */
++			writeq_relaxed(val, timer->base + CNTP_CVAL_LO);
+ 			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
+ 		struct arch_timer *timer = to_arch_timer(clk);
+ 		switch (reg) {
+ 		case ARCH_TIMER_REG_CTRL:
+-			writel_relaxed(val, timer->base + CNTV_CTL);
++			writel_relaxed((u32)val, timer->base + CNTV_CTL);
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			writel_relaxed(val, timer->base + CNTV_TVAL);
++		case ARCH_TIMER_REG_CVAL:
++			/* Same restriction as above */
++			writeq_relaxed(val, timer->base + CNTV_CVAL_LO);
+ 			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else {
+ 		arch_timer_reg_write_cp15(access, reg, val);
+@@ -129,9 +160,8 @@ u32 arch_timer_reg_read(int access, enum
+ 		case ARCH_TIMER_REG_CTRL:
+ 			val = readl_relaxed(timer->base + CNTP_CTL);
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			val = readl_relaxed(timer->base + CNTP_TVAL);
+-			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
+ 		struct arch_timer *timer = to_arch_timer(clk);
+@@ -139,9 +169,8 @@ u32 arch_timer_reg_read(int access, enum
+ 		case ARCH_TIMER_REG_CTRL:
+ 			val = readl_relaxed(timer->base + CNTV_CTL);
+ 			break;
+-		case ARCH_TIMER_REG_TVAL:
+-			val = readl_relaxed(timer->base + CNTV_TVAL);
+-			break;
++		default:
++			BUILD_BUG();
+ 		}
+ 	} else {
+ 		val = arch_timer_reg_read_cp15(access, reg);
+@@ -193,13 +222,11 @@ static struct clocksource clocksource_co
+ 	.name	= "arch_sys_counter",
+ 	.rating	= 400,
+ 	.read	= arch_counter_read,
+-	.mask	= CLOCKSOURCE_MASK(56),
+ 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+ };
+ 
+ static struct cyclecounter cyclecounter __ro_after_init = {
+ 	.read	= arch_counter_read_cc,
+-	.mask	= CLOCKSOURCE_MASK(56),
+ };
+ 
+ struct ate_acpi_oem_info {
+@@ -227,16 +254,6 @@ struct ate_acpi_oem_info {
+ 	_new;						\
+ })
+ 
+-static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
+-{
+-	return __fsl_a008585_read_reg(cntp_tval_el0);
+-}
+-
+-static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
+-{
+-	return __fsl_a008585_read_reg(cntv_tval_el0);
+-}
+-
+ static u64 notrace fsl_a008585_read_cntpct_el0(void)
+ {
+ 	return __fsl_a008585_read_reg(cntpct_el0);
+@@ -273,16 +290,6 @@ static u64 notrace fsl_a008585_read_cntv
+ 	_new;							\
+ })
+ 
+-static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
+-{
+-	return __hisi_161010101_read_reg(cntp_tval_el0);
+-}
+-
+-static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
+-{
+-	return __hisi_161010101_read_reg(cntv_tval_el0);
+-}
+-
+ static u64 notrace hisi_161010101_read_cntpct_el0(void)
+ {
+ 	return __hisi_161010101_read_reg(cntpct_el0);
+@@ -367,16 +374,6 @@ static u64 notrace sun50i_a64_read_cntvc
+ {
+ 	return __sun50i_a64_read_reg(cntvct_el0);
+ }
+-
+-static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
+-{
+-	return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
+-}
+-
+-static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
+-{
+-	return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
+-}
+ #endif
+ 
+ #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
+@@ -385,7 +382,7 @@ EXPORT_SYMBOL_GPL(timer_unstable_counter
+ 
+ static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
+ 
+-static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
++static void erratum_set_next_event_generic(const int access, unsigned long evt,
+ 						struct clock_event_device *clk)
+ {
+ 	unsigned long ctrl;
+@@ -406,17 +403,17 @@ static void erratum_set_next_event_tval_
+ 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
+ }
+ 
+-static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
++static __maybe_unused int erratum_set_next_event_virt(unsigned long evt,
+ 					    struct clock_event_device *clk)
+ {
+-	erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
++	erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+ 	return 0;
+ }
+ 
+-static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
++static __maybe_unused int erratum_set_next_event_phys(unsigned long evt,
+ 					    struct clock_event_device *clk)
+ {
+-	erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
++	erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+ 	return 0;
+ }
+ 
+@@ -426,12 +423,10 @@ static const struct arch_timer_erratum_w
+ 		.match_type = ate_match_dt,
+ 		.id = "fsl,erratum-a008585",
+ 		.desc = "Freescale erratum a005858",
+-		.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
+-		.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
+ 		.read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
+ 		.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
+-		.set_next_event_phys = erratum_set_next_event_tval_phys,
+-		.set_next_event_virt = erratum_set_next_event_tval_virt,
++		.set_next_event_phys = erratum_set_next_event_phys,
++		.set_next_event_virt = erratum_set_next_event_virt,
+ 	},
+ #endif
+ #ifdef CONFIG_HISILICON_ERRATUM_161010101
+@@ -439,23 +434,19 @@ static const struct arch_timer_erratum_w
+ 		.match_type = ate_match_dt,
+ 		.id = "hisilicon,erratum-161010101",
+ 		.desc = "HiSilicon erratum 161010101",
+-		.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
+-		.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
+ 		.read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
+ 		.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
+-		.set_next_event_phys = erratum_set_next_event_tval_phys,
+-		.set_next_event_virt = erratum_set_next_event_tval_virt,
++		.set_next_event_phys = erratum_set_next_event_phys,
++		.set_next_event_virt = erratum_set_next_event_virt,
+ 	},
+ 	{
+ 		.match_type = ate_match_acpi_oem_info,
+ 		.id = hisi_161010101_oem_info,
+ 		.desc = "HiSilicon erratum 161010101",
+-		.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
+-		.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
+ 		.read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
+ 		.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
+-		.set_next_event_phys = erratum_set_next_event_tval_phys,
+-		.set_next_event_virt = erratum_set_next_event_tval_virt,
++		.set_next_event_phys = erratum_set_next_event_phys,
++		.set_next_event_virt = erratum_set_next_event_virt,
+ 	},
+ #endif
+ #ifdef CONFIG_ARM64_ERRATUM_858921
+@@ -472,12 +463,10 @@ static const struct arch_timer_erratum_w
+ 		.match_type = ate_match_dt,
+ 		.id = "allwinner,erratum-unknown1",
+ 		.desc = "Allwinner erratum UNKNOWN1",
+-		.read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
+-		.read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
+ 		.read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
+ 		.read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
+-		.set_next_event_phys = erratum_set_next_event_tval_phys,
+-		.set_next_event_virt = erratum_set_next_event_tval_virt,
++		.set_next_event_phys = erratum_set_next_event_phys,
++		.set_next_event_virt = erratum_set_next_event_virt,
+ 	},
+ #endif
+ #ifdef CONFIG_ARM64_ERRATUM_1418040
+@@ -715,10 +704,18 @@ static __always_inline void set_next_eve
+ 					   struct clock_event_device *clk)
+ {
+ 	unsigned long ctrl;
++	u64 cnt;
++
+ 	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
+ 	ctrl |= ARCH_TIMER_CTRL_ENABLE;
+ 	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+-	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
++
++	if (access == ARCH_TIMER_PHYS_ACCESS)
++		cnt = __arch_counter_get_cntpct();
++	else
++		cnt = __arch_counter_get_cntvct();
++
++	arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
+ 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
+ }
+ 
+@@ -736,23 +733,79 @@ static int arch_timer_set_next_event_phy
+ 	return 0;
+ }
+ 
++static u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo)
++{
++	u32 cnt_lo, cnt_hi, tmp_hi;
++
++	do {
++		cnt_hi = readl_relaxed(t->base + offset_lo + 4);
++		cnt_lo = readl_relaxed(t->base + offset_lo);
++		tmp_hi = readl_relaxed(t->base + offset_lo + 4);
++	} while (cnt_hi != tmp_hi);
++
++	return ((u64) cnt_hi << 32) | cnt_lo;
++}
++
++static __always_inline void set_next_event_mem(const int access, unsigned long evt,
++					   struct clock_event_device *clk)
++{
++	struct arch_timer *timer = to_arch_timer(clk);
++	unsigned long ctrl;
++	u64 cnt;
++
++	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
++	ctrl |= ARCH_TIMER_CTRL_ENABLE;
++	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
++
++	if (access ==  ARCH_TIMER_MEM_VIRT_ACCESS)
++		cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO);
++	else
++		cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO);
++
++	arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
++	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
++}
++
+ static int arch_timer_set_next_event_virt_mem(unsigned long evt,
+ 					      struct clock_event_device *clk)
+ {
+-	set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
++	set_next_event_mem(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
+ 	return 0;
+ }
+ 
+ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
+ 					      struct clock_event_device *clk)
+ {
+-	set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
++	set_next_event_mem(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
+ 	return 0;
+ }
+ 
++static u64 __arch_timer_check_delta(void)
++{
++#ifdef CONFIG_ARM64
++	const struct midr_range broken_cval_midrs[] = {
++		/*
++		 * XGene-1 implements CVAL in terms of TVAL, meaning
++		 * that the maximum timer range is 32bit. Shame on them.
++		 */
++		MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
++						 APM_CPU_PART_POTENZA)),
++		{},
++	};
++
++	if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
++		pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 32bits");
++		return CLOCKSOURCE_MASK(32);
++	}
++#endif
++	return CLOCKSOURCE_MASK(arch_counter_get_width());
++}
++
+ static void __arch_timer_setup(unsigned type,
+ 			       struct clock_event_device *clk)
+ {
++	u64 max_delta;
++
+ 	clk->features = CLOCK_EVT_FEAT_ONESHOT;
+ 
+ 	if (type == ARCH_TIMER_TYPE_CP15) {
+@@ -784,6 +837,7 @@ static void __arch_timer_setup(unsigned
+ 		}
+ 
+ 		clk->set_next_event = sne;
++		max_delta = __arch_timer_check_delta();
+ 	} else {
+ 		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
+ 		clk->name = "arch_mem_timer";
+@@ -800,11 +854,13 @@ static void __arch_timer_setup(unsigned
+ 			clk->set_next_event =
+ 				arch_timer_set_next_event_phys_mem;
+ 		}
++
++		max_delta = CLOCKSOURCE_MASK(56);
+ 	}
+ 
+ 	clk->set_state_shutdown(clk);
+ 
+-	clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
++	clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
+ }
+ 
+ static void arch_timer_evtstrm_enable(int divider)
+@@ -974,15 +1030,7 @@ bool arch_timer_evtstrm_available(void)
+ 
+ static u64 arch_counter_get_cntvct_mem(void)
+ {
+-	u32 vct_lo, vct_hi, tmp_hi;
+-
+-	do {
+-		vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
+-		vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
+-		tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
+-	} while (vct_hi != tmp_hi);
+-
+-	return ((u64) vct_hi << 32) | vct_lo;
++	return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO);
+ }
+ 
+ static struct arch_timer_kvm_info arch_timer_kvm_info;
+@@ -995,6 +1043,7 @@ struct arch_timer_kvm_info *arch_timer_g
+ static void __init arch_counter_register(unsigned type)
+ {
+ 	u64 start_count;
++	int width;
+ 
+ 	/* Register the CP15 based counter if we have one */
+ 	if (type & ARCH_TIMER_TYPE_CP15) {
+@@ -1019,6 +1068,10 @@ static void __init arch_counter_register
+ 		arch_timer_read_counter = arch_counter_get_cntvct_mem;
+ 	}
+ 
++	width = arch_counter_get_width();
++	clocksource_counter.mask = CLOCKSOURCE_MASK(width);
++	cyclecounter.mask = CLOCKSOURCE_MASK(width);
++
+ 	if (!arch_counter_suspend_stop)
+ 		clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
+ 	start_count = arch_timer_read_counter();
+@@ -1028,8 +1081,7 @@ static void __init arch_counter_register
+ 	timecounter_init(&arch_timer_kvm_info.timecounter,
+ 			 &cyclecounter, start_count);
+ 
+-	/* 56 bits minimum, so we assume worst case rollover */
+-	sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
++	sched_clock_register(arch_timer_read_counter, width, arch_timer_rate);
+ }
+ 
+ static void arch_timer_stop(struct clock_event_device *clk)
+@@ -1170,25 +1222,25 @@ static int __init arch_timer_mem_registe
+ {
+ 	int ret;
+ 	irq_handler_t func;
+-	struct arch_timer *t;
+ 
+-	t = kzalloc(sizeof(*t), GFP_KERNEL);
+-	if (!t)
++	arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL);
++	if (!arch_timer_mem)
+ 		return -ENOMEM;
+ 
+-	t->base = base;
+-	t->evt.irq = irq;
+-	__arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
++	arch_timer_mem->base = base;
++	arch_timer_mem->evt.irq = irq;
++	__arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt);
+ 
+ 	if (arch_timer_mem_use_virtual)
+ 		func = arch_timer_handler_virt_mem;
+ 	else
+ 		func = arch_timer_handler_phys_mem;
+ 
+-	ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
++	ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt);
+ 	if (ret) {
+ 		pr_err("Failed to request mem timer irq\n");
+-		kfree(t);
++		kfree(arch_timer_mem);
++		arch_timer_mem = NULL;
+ 	}
+ 
+ 	return ret;
+@@ -1436,7 +1488,6 @@ arch_timer_mem_frame_register(struct arc
+ 		return ret;
+ 	}
+ 
+-	arch_counter_base = base;
+ 	arch_timers_present |= ARCH_TIMER_TYPE_MEM;
+ 
+ 	return 0;
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -21,7 +21,7 @@ config CRYPTO_DEV_PADLOCK
+ 	  (so called VIA PadLock ACE, Advanced Cryptography Engine)
+ 	  that provides instructions for very fast cryptographic
+ 	  operations with supported algorithms.
+-	  
++
+ 	  The instructions are used only when the CPU supports them.
+ 	  Otherwise software encryption is used.
+ 
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -712,6 +712,13 @@ config ZX_DMA
+ 	help
+ 	  Support the DMA engine for ZTE ZX family platform devices.
+ 
++config PHYTIUM_DDMA
++	bool "Phytium PE220x DDMA support"
++	depends on (ARCH_PHYTIUM || COMPILE_TEST)
++	select DMA_ENGINE
++	select DMA_VIRTUAL_CHANNELS
++	help
++	  Enable support for Phytium PE220x DDMA controller.
+ 
+ # driver files
+ source "drivers/dma/bestcomm/Kconfig"
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -87,3 +87,4 @@ obj-y += mediatek/
+ obj-y += qcom/
+ obj-y += ti/
+ obj-y += xilinx/
++obj-y += phytium/
+--- a/drivers/edac/Kconfig
++++ b/drivers/edac/Kconfig
+@@ -537,4 +537,11 @@ config EDAC_DMC520
+ 	  Support for error detection and correction on the
+ 	  SoCs with ARM DMC-520 DRAM controller.
+ 
++config EDAC_PHYTIUM
++	tristate "Phytium Pe220x SoC"
++	depends on (ARM64)
++	help
++	  Support for error detection and correction on the
++	  Phytium Pe220x family of SOCs.
++
+ endif # EDAC
+--- a/drivers/edac/Makefile
++++ b/drivers/edac/Makefile
+@@ -89,3 +89,4 @@ obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
+ obj-$(CONFIG_EDAC_ASPEED)		+= aspeed_edac.o
+ obj-$(CONFIG_EDAC_BLUEFIELD)		+= bluefield_edac.o
+ obj-$(CONFIG_EDAC_DMC520)		+= dmc520_edac.o
++obj-$(CONFIG_EDAC_PHYTIUM)		+= phytium_edac.o
+--- a/drivers/firmware/Kconfig
++++ b/drivers/firmware/Kconfig
+@@ -27,6 +27,18 @@ config ARM_SCMI_PROTOCOL
+ 	  This protocol library provides interface for all the client drivers
+ 	  making use of the features offered by the SCMI.
+ 
++if ARM_SCMI_PROTOCOL
++config ARM_SCMI_TRANSPORT_FORCE_POLLING
++	bool "Support force polling mode for SCMI Mailbox"
++	help
++	  Support force polling mode for SCMI Mailbox transports.
++
++	  If you want to configure SCMI Mailbox transport to use polling mode
++	  on the TX path and do not use any completion IRQ facility even when
++	  available through kernel parameter, answer Y. If unsure, say N.
++
++endif #ARM_SCMI_PROTOCOL
++
+ config ARM_SCMI_POWER_DOMAIN
+ 	tristate "SCMI power domain driver"
+ 	depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST && OF)
+--- a/drivers/firmware/arm_scmi/driver.c
++++ b/drivers/firmware/arm_scmi/driver.c
+@@ -98,6 +98,10 @@ struct scmi_info {
+ 	int users;
+ };
+ 
++#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING
++static bool scmi_force_polling;
++#endif
++
+ #define handle_to_scmi_info(h)	container_of(h, struct scmi_info, handle)
+ 
+ static const int scmi_linux_errmap[] = {
+@@ -344,6 +348,15 @@ static bool scmi_xfer_done_no_timeout(st
+ 	       ktime_after(ktime_get(), stop);
+ }
+ 
++
++#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING
++static int __init scmi_set_force_polling(char *str)
++{
++	return kstrtobool(str, &scmi_force_polling);
++}
++early_param("scmi.force_polling", scmi_set_force_polling);
++#endif
++
+ /**
+  * scmi_do_xfer() - Do one transfer
+  *
+@@ -366,6 +379,11 @@ int scmi_do_xfer(const struct scmi_handl
+ 	if (unlikely(!cinfo))
+ 		return -EINVAL;
+ 
++#ifdef CONFIG_ARM_SCMI_TRANSPORT_FORCE_POLLING
++	if (scmi_force_polling)
++		xfer->hdr.poll_completion = true;
++#endif
++
+ 	trace_scmi_xfer_begin(xfer->transfer_id, xfer->hdr.id,
+ 			      xfer->hdr.protocol_id, xfer->hdr.seq,
+ 			      xfer->hdr.poll_completion);
+--- a/drivers/firmware/arm_scmi/shmem.c
++++ b/drivers/firmware/arm_scmi/shmem.c
+@@ -32,6 +32,14 @@ struct scmi_shared_mem {
+ void shmem_tx_prepare(struct scmi_shared_mem __iomem *shmem,
+ 		      struct scmi_xfer *xfer)
+ {
++#ifdef CONFIG_ARCH_PHYTIUM
++	/* callee not set cahnnel free when init, caller set it */
++	static int is_init = 0;
++	if(unlikely(is_init == 0)) {
++		iowrite32(0x1, &shmem->channel_status);
++		is_init = 1;
++	}
++#endif
+ 	/*
+ 	 * Ideally channel must be free by now unless OS timeout last
+ 	 * request and platform continued to process the same, wait
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -108,6 +108,10 @@ config GPIO_REGMAP
+ config GPIO_MAX730X
+ 	tristate
+ 
++# This symbol is selected by both MMIO and PCI expanders
++config GPIO_PHYTIUM_CORE
++	tristate
++
+ menu "Memory mapped GPIO drivers"
+ 	depends on HAS_IOMEM
+ 
+@@ -739,6 +743,27 @@ config GPIO_AMD_FCH
+ 	  Note: This driver doesn't registers itself automatically, as it
+ 	  needs to be provided with platform specific configuration.
+ 	  (See eg. CONFIG_PCENGINES_APU2.)
++
++config GPIO_PHYTIUM_PLAT
++	tristate "Phytium GPIO Platform support"
++	default y if ARCH_PHYTIUM
++	depends on ARM64
++	select GPIO_PHYTIUM_CORE
++	select IRQ_DOMAIN
++	select GENERIC_IRQ_CHIP
++	select GPIOLIB_IRQCHIP
++	help
++	  Say yes here to enable GPIO support for Phytium SoCs.
++
++config GPIO_PHYTIUM_SGPIO
++	tristate "Phytium SGPIO support"
++	default y if ARCH_PHYTIUM
++	depends on ARM64
++	select IRQ_DOMAIN
++	select GENERIC_IRQ_CHIP
++	help
++	  Say yes here to enable SGPIO support for Phytium SoCs.
++
+ endmenu
+ 
+ menu "Port-mapped I/O GPIO drivers"
+@@ -1520,6 +1545,20 @@ config GPIO_SODAVILLE
+ 	help
+ 	  Say Y here to support Intel Sodaville GPIO.
+ 
++
++config GPIO_PHYTIUM_PCI
++	tristate "Phytium GPIO PCI support"
++	select GPIO_PHYTIUM_CORE
++	select IRQ_DOMAIN
++	select GENERIC_IRQ_CHIP
++	select GPIOLIB_IRQCHIP
++	help
++	  Say Y here to support Phytium PCI GPIO controller on px210 chipset.
++	  An interrupt is generated when any of the inputs change state
++	  (low to high or high to low).
++
++	  This driver can be used for Phytium px210.
++
+ endmenu
+ 
+ menu "SPI GPIO expanders"
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -180,3 +180,8 @@ obj-$(CONFIG_GPIO_XTENSA)		+= gpio-xtens
+ obj-$(CONFIG_GPIO_ZEVIO)		+= gpio-zevio.o
+ obj-$(CONFIG_GPIO_ZX)			+= gpio-zx.o
+ obj-$(CONFIG_GPIO_ZYNQ)			+= gpio-zynq.o
++
++obj-$(CONFIG_GPIO_PHYTIUM_CORE)		+= gpio-phytium-core.o
++obj-$(CONFIG_GPIO_PHYTIUM_PCI)		+= gpio-phytium-pci.o
++obj-$(CONFIG_GPIO_PHYTIUM_PLAT)		+= gpio-phytium-platform.o
++obj-$(CONFIG_GPIO_PHYTIUM_SGPIO)	+= gpio-phytium-sgpio.o
+--- a/drivers/gpu/drm/Kconfig
++++ b/drivers/gpu/drm/Kconfig
+@@ -393,6 +393,8 @@ source "drivers/gpu/drm/tidss/Kconfig"
+ 
+ source "drivers/gpu/drm/xlnx/Kconfig"
+ 
++source "drivers/gpu/drm/phytium/Kconfig"
++
+ # Keep legacy drivers last
+ 
+ menuconfig DRM_LEGACY
+--- a/drivers/gpu/drm/Makefile
++++ b/drivers/gpu/drm/Makefile
+@@ -124,3 +124,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/
+ obj-$(CONFIG_DRM_MCDE) += mcde/
+ obj-$(CONFIG_DRM_TIDSS) += tidss/
+ obj-y			+= xlnx/
++obj-$(CONFIG_DRM_PHYTIUM) += phytium/
+--- a/drivers/hwmon/Kconfig
++++ b/drivers/hwmon/Kconfig
+@@ -2096,6 +2096,16 @@ config SENSORS_INTEL_M10_BMC_HWMON
+ 	  sensors monitor various telemetry data of different components on the
+ 	  card, e.g. board temperature, FPGA core temperature/voltage/current.
+ 
++
++config SENSORS_PHYTIUM
++	tristate "Phytium Fan tach and capture counter driver"
++	help
++	  This driver provides support for Phytium Fan Tacho and capture
++	  counter controllers.
++
++	  This driver can also be built as a module. If so, the module
++	  will be called tacho-phytium.
++
+ if ACPI
+ 
+ comment "ACPI drivers"
+--- a/drivers/hwmon/Makefile
++++ b/drivers/hwmon/Makefile
+@@ -194,6 +194,8 @@ obj-$(CONFIG_SENSORS_WM831X)	+= wm831x-h
+ obj-$(CONFIG_SENSORS_WM8350)	+= wm8350-hwmon.o
+ obj-$(CONFIG_SENSORS_XGENE)	+= xgene-hwmon.o
+ 
++obj-$(CONFIG_SENSORS_PHYTIUM)	+= tacho-phytium.o
++
+ obj-$(CONFIG_SENSORS_OCC)	+= occ/
+ obj-$(CONFIG_PMBUS)		+= pmbus/
+ 
+--- a/drivers/hwspinlock/Kconfig
++++ b/drivers/hwspinlock/Kconfig
+@@ -65,4 +65,13 @@ config HSEM_U8500
+ 
+ 	  If unsure, say N.
+ 
++config HWSPINLOCK_PHYTIUM
++	tristate "Phytium Hardware Spinlock device"
++	depends on HWSPINLOCK
++	depends on ARCH_PHYTIUM
++	help
++	  Say y here to support the Phytium Hardware Spinlock device.
++
++	  If unsure, say N.
++
+ endif # HWSPINLOCK
+--- a/drivers/hwspinlock/Makefile
++++ b/drivers/hwspinlock/Makefile
+@@ -10,3 +10,5 @@ obj-$(CONFIG_HWSPINLOCK_SIRF)		+= sirf_h
+ obj-$(CONFIG_HWSPINLOCK_SPRD)		+= sprd_hwspinlock.o
+ obj-$(CONFIG_HWSPINLOCK_STM32)		+= stm32_hwspinlock.o
+ obj-$(CONFIG_HSEM_U8500)		+= u8500_hsem.o
++
++obj-$(CONFIG_HWSPINLOCK_PHYTIUM)	+= phytium_hwspinlock.o
+\ No newline at end of file
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -1206,6 +1206,34 @@ config I2C_RCAR
+ 	  This driver can also be built as a module.  If so, the module
+ 	  will be called i2c-rcar.
+ 
++config I2C_PHYTIUM_CORE
++	tristate
++
++config I2C_PHYTIUM_PCI
++	tristate "Phytium I2C PCI"
++	depends on PCI && ARCH_PHYTIUM
++	select I2C_PHYTIUM_CORE
++	select I2C_SMBUS
++	help
++	  If you say yes to this option, support will be included for the
++	  Phytium I2C adapter. Only master mode is supported.
++
++	  This driver can also be built as a module.  If so, the module
++	  will be called i2c-phytium-pci.
++
++config I2C_PHYTIUM_PLATFORM
++	tristate "Phytium I2C Platform"
++	depends on (ACPI && COMMON_CLK) || !ACPI
++	select I2C_SLAVE
++	select I2C_PHYTIUM_CORE
++	select I2C_SMBUS
++	help
++	  If you say yes to this option, support will be included for the
++	  Phytium I2C adapter. Only master mode is supported.
++
++	  This driver can also be built as a module.  If so, the module
++	  will be called i2c-phytium-platform.
++
+ comment "External I2C/SMBus adapter drivers"
+ 
+ config I2C_DIOLAN_U2C
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -123,6 +123,10 @@ obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o
+ obj-$(CONFIG_I2C_XLP9XX)	+= i2c-xlp9xx.o
+ obj-$(CONFIG_I2C_RCAR)		+= i2c-rcar.o
+ obj-$(CONFIG_I2C_ZX2967)	+= i2c-zx2967.o
++obj-$(CONFIG_I2C_PHYTIUM_CORE)      += i2c-phytium-core.o
++i2c-phytium-core-objs := i2c-phytium-common.o i2c-phytium-master.o i2c-phytium-slave.o
++obj-$(CONFIG_I2C_PHYTIUM_PCI)       += i2c-phytium-pci.o
++obj-$(CONFIG_I2C_PHYTIUM_PLATFORM)  += i2c-phytium-platform.o
+ 
+ # External I2C/SMBus adapter drivers
+ obj-$(CONFIG_I2C_DIOLAN_U2C)	+= i2c-diolan-u2c.o
+--- a/drivers/iio/adc/Kconfig
++++ b/drivers/iio/adc/Kconfig
+@@ -1226,4 +1226,16 @@ config XILINX_XADC
+ 	  The driver can also be build as a module. If so, the module will be called
+ 	  xilinx-xadc.
+ 
++config PHYTIUM_ADC
++	tristate "Phytium ADC driver"
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++	select IIO_BUFFER
++	select IIO_TRIGGERED_BUFFER
++	help
++	  Say yes here to build support for Phytium analog to digital
++	  converters (ADC).
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called phytium-adc.
++
+ endmenu
+--- a/drivers/iio/adc/Makefile
++++ b/drivers/iio/adc/Makefile
+@@ -111,3 +111,4 @@ obj-$(CONFIG_VIPERBOARD_ADC) += viperboa
+ xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
+ obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
+ obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
++obj-$(CONFIG_PHYTIUM_ADC) += phytium-adc.o
+\ No newline at end of file
+--- a/drivers/input/keyboard/Kconfig
++++ b/drivers/input/keyboard/Kconfig
+@@ -788,4 +788,15 @@ config KEYBOARD_MTK_PMIC
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called pmic-keys.
+ 
++config KEYBOARD_PHYTIUM
++	tristate "Phytium keypad support"
++	depends on ARCH_PHYTIUM
++	select INPUT_MATRIXKMAP
++	help
++	  Say Y here if you want to enable support for Phytium keypad
++	  port.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called phytium_keypad.
++
+ endif
+--- a/drivers/input/keyboard/Makefile
++++ b/drivers/input/keyboard/Makefile
+@@ -70,3 +70,4 @@ obj-$(CONFIG_KEYBOARD_TEGRA)		+= tegra-k
+ obj-$(CONFIG_KEYBOARD_TM2_TOUCHKEY)	+= tm2-touchkey.o
+ obj-$(CONFIG_KEYBOARD_TWL4030)		+= twl4030_keypad.o
+ obj-$(CONFIG_KEYBOARD_XTKBD)		+= xtkbd.o
++obj-$(CONFIG_KEYBOARD_PHYTIUM)		+= phytium-keypad.o
+--- a/drivers/input/serio/Kconfig
++++ b/drivers/input/serio/Kconfig
+@@ -40,6 +40,18 @@ config SERIO_I8042
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called i8042.
+ 
++config SERIO_PHYTIUM_PS2
++	depends on SERIO
++	tristate "PHYTIUM PS/2 (keyboard and mouse)"
++	default y if ARCH_PHYTIUM
++	depends on PCI
++	help
++	  This selects support for the PS/2 Host Controller on
++	  Phytium SoCs.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called phytium-ps2.
++
+ config SERIO_SERPORT
+ 	tristate "Serial port line discipline"
+ 	default y
+--- a/drivers/input/serio/Makefile
++++ b/drivers/input/serio/Makefile
+@@ -7,6 +7,7 @@
+ 
+ obj-$(CONFIG_SERIO)		+= serio.o
+ obj-$(CONFIG_SERIO_I8042)	+= i8042.o
++obj-$(CONFIG_SERIO_PHYTIUM_PS2)	+= phytium-ps2.o
+ obj-$(CONFIG_SERIO_PARKBD)	+= parkbd.o
+ obj-$(CONFIG_SERIO_SERPORT)	+= serport.o
+ obj-$(CONFIG_SERIO_CT82C710)	+= ct82c710.o
+--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+@@ -2873,6 +2873,13 @@ static void arm_smmu_write_msi_msg(struc
+ 	doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
+ 	doorbell &= MSI_CFG0_ADDR_MASK;
+ 
++#ifdef CONFIG_PM_SLEEP
++	/* Saves the msg (base addr of msi irq) and restores it during resume */
++	desc->msg.address_lo = msg->address_lo;
++	desc->msg.address_hi = msg->address_hi;
++	desc->msg.data = msg->data;
++#endif
++
+ 	writeq_relaxed(doorbell, smmu->base + cfg[0]);
+ 	writel_relaxed(msg->data, smmu->base + cfg[1]);
+ 	writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
+@@ -2928,11 +2935,51 @@ static void arm_smmu_setup_msis(struct a
+ 	devm_add_action(dev, arm_smmu_free_msis, dev);
+ }
+ 
+-static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
++#ifdef CONFIG_PM_SLEEP
++static void arm_smmu_resume_msis(struct arm_smmu_device *smmu)
++{
++       struct msi_desc *desc;
++       struct device *dev = smmu->dev;
++
++       for_each_msi_entry(desc, dev) {
++               switch (desc->platform.msi_index) {
++               case EVTQ_MSI_INDEX:
++               case GERROR_MSI_INDEX:
++               case PRIQ_MSI_INDEX: {
++                       phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];
++                       struct msi_msg *msg = &desc->msg;
++                       phys_addr_t doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
++
++                       doorbell &= MSI_CFG0_ADDR_MASK;
++                       writeq_relaxed(doorbell, smmu->base + cfg[0]);
++                       writel_relaxed(msg->data, smmu->base + cfg[1]);
++                       writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE,
++                                       smmu->base + cfg[2]);
++                       break;
++               }
++               default:
++                       continue;
++
++               }
++       }
++}
++#else
++static void arm_smmu_resume_msis(struct arm_smmu_device *smmu)
++{
++}
++#endif
++
++static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu, bool resume)
+ {
+ 	int irq, ret;
+ 
+-	arm_smmu_setup_msis(smmu);
++	if (!resume)
++		arm_smmu_setup_msis(smmu);
++	else {
++		/* The irq doesn't need to be re-requested during resume */
++		arm_smmu_resume_msis(smmu);
++		return;
++	}
+ 
+ 	/* Request interrupt lines */
+ 	irq = smmu->evtq.q.irq;
+@@ -2974,7 +3021,7 @@ static void arm_smmu_setup_unique_irqs(s
+ 	}
+ }
+ 
+-static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
++static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume)
+ {
+ 	int ret, irq;
+ 	u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
+@@ -3001,7 +3048,7 @@ static int arm_smmu_setup_irqs(struct ar
+ 		if (ret < 0)
+ 			dev_warn(smmu->dev, "failed to enable combined irq\n");
+ 	} else
+-		arm_smmu_setup_unique_irqs(smmu);
++		arm_smmu_setup_unique_irqs(smmu, resume);
+ 
+ 	if (smmu->features & ARM_SMMU_FEAT_PRI)
+ 		irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
+@@ -3026,7 +3073,7 @@ static int arm_smmu_device_disable(struc
+ 	return ret;
+ }
+ 
+-static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
++static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume)
+ {
+ 	int ret;
+ 	u32 reg, enables;
+@@ -3134,7 +3181,7 @@ static int arm_smmu_device_reset(struct
+ 		}
+ 	}
+ 
+-	ret = arm_smmu_setup_irqs(smmu);
++	ret = arm_smmu_setup_irqs(smmu, resume);
+ 	if (ret) {
+ 		dev_err(smmu->dev, "failed to setup irqs\n");
+ 		return ret;
+@@ -3144,7 +3191,7 @@ static int arm_smmu_device_reset(struct
+ 		enables &= ~(CR0_EVTQEN | CR0_PRIQEN);
+ 
+ 	/* Enable the SMMU interface, or ensure bypass */
+-	if (!bypass || disable_bypass) {
++	if (!smmu->bypass || disable_bypass) {
+ 		enables |= CR0_SMMUEN;
+ 	} else {
+ 		ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT);
+@@ -3492,6 +3539,26 @@ static void __iomem *arm_smmu_ioremap(st
+ 	return devm_ioremap_resource(dev, &res);
+ }
+ 
++#ifdef CONFIG_PM_SLEEP
++static int arm_smmu_suspend(struct device *dev)
++{
++	/*
++	 * The smmu is powered off and related registers are automatically
++	 * cleared when suspend. No need to do anything.
++	 */
++	return 0;
++}
++
++static int arm_smmu_resume(struct device *dev)
++{
++	struct arm_smmu_device *smmu = dev_get_drvdata(dev);
++
++	arm_smmu_device_reset(smmu, true);
++
++	return 0;
++}
++#endif
++
+ static int arm_smmu_device_probe(struct platform_device *pdev)
+ {
+ 	int irq, ret;
+@@ -3499,7 +3566,6 @@ static int arm_smmu_device_probe(struct
+ 	resource_size_t ioaddr;
+ 	struct arm_smmu_device *smmu;
+ 	struct device *dev = &pdev->dev;
+-	bool bypass;
+ 
+ 	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
+ 	if (!smmu) {
+@@ -3517,7 +3583,7 @@ static int arm_smmu_device_probe(struct
+ 	}
+ 
+ 	/* Set bypass mode according to firmware probing result */
+-	bypass = !!ret;
++	smmu->bypass = !!ret;
+ 
+ 	/* Base address */
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -3578,7 +3644,7 @@ static int arm_smmu_device_probe(struct
+ 	platform_set_drvdata(pdev, smmu);
+ 
+ 	/* Reset the device */
+-	ret = arm_smmu_device_reset(smmu, bypass);
++	ret = arm_smmu_device_reset(smmu, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -3623,10 +3689,21 @@ static const struct of_device_id arm_smm
+ };
+ MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
+ 
++#ifdef CONFIG_PM_SLEEP
++static const struct dev_pm_ops arm_smmu_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(arm_smmu_suspend,
++	arm_smmu_resume)
++};
++#define ARM_SMMU_PM_OPS                (&arm_smmu_pm_ops)
++#else
++#define ARM_SMMU_PM_OPS                NULL
++#endif
++
+ static struct platform_driver arm_smmu_driver = {
+ 	.driver	= {
+ 		.name			= "arm-smmu-v3",
+ 		.of_match_table		= arm_smmu_of_match,
++		.pm			= ARM_SMMU_PM_OPS,
+ 		.suppress_bind_attrs	= true,
+ 	},
+ 	.probe	= arm_smmu_device_probe,
+--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+@@ -636,6 +636,7 @@ struct arm_smmu_device {
+ 
+ 	/* IOMMU core code handle */
+ 	struct iommu_device		iommu;
++	bool                            bypass;
+ };
+ 
+ /* SMMU private data for each master */
+--- a/drivers/irqchip/Kconfig
++++ b/drivers/irqchip/Kconfig
+@@ -599,4 +599,12 @@ config MST_IRQ
+ 	help
+ 	  Support MStar Interrupt Controller.
+ 
++config PHYTIUM_IXIC
++	bool "Phytium SoC PCI Legacy Interrupt Controller"
++	depends on ARCH_PHYTIUM
++	select IRQ_DOMAIN
++	select IRQ_DOMAIN_HIERARCHY
++	help
++	  This enables support PCI Legacy Interrupt on Phytium SoC.
++
+ endmenu
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -114,3 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-l
+ obj-$(CONFIG_LOONGSON_PCH_MSI)		+= irq-loongson-pch-msi.o
+ obj-$(CONFIG_MST_IRQ)			+= irq-mst-intc.o
+ obj-$(CONFIG_SL28CPLD_INTC)		+= irq-sl28cpld.o
++obj-$(CONFIG_PHYTIUM_IXIC)		+= irq-phytium-ixic.o
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -4788,6 +4788,7 @@ static void its_restore_enable(void)
+ {
+ 	struct its_node *its;
+ 	int ret;
++	int cpu;
+ 
+ 	raw_spin_lock(&its_lock);
+ 	list_for_each_entry(its, &its_nodes, entry) {
+@@ -4841,6 +4842,23 @@ static void its_restore_enable(void)
+ 		    GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
+ 			its_cpu_init_collection(its);
+ 	}
++
++    /*
++     * Enable LPIs:firmware just restore GICR_CTLR_ENABLE_LPIs of boot
++     * CPU, the other CPUs also should be restored.
++     */
++    for_each_possible_cpu(cpu) {
++        void __iomem *rbase = gic_data_rdist_cpu(cpu)->rd_base;
++        u32 val;
++
++        /*Enable LPIs*/
++        val = readl_relaxed(rbase + GICR_CTLR);
++        if (val & GICR_CTLR_ENABLE_LPIS)
++            continue;
++
++        val |= GICR_CTLR_ENABLE_LPIS;
++        writel_relaxed(val, rbase + GICR_CTLR);
++    }
+ 	raw_spin_unlock(&its_lock);
+ }
+ 
+--- a/drivers/mailbox/Kconfig
++++ b/drivers/mailbox/Kconfig
+@@ -254,4 +254,13 @@ config QCOM_IPCC
+ 	  acts as an interrupt controller for receiving interrupts from clients.
+ 	  Say Y here if you want to build this driver.
+ 
++config PHYTIUM_MBOX
++	tristate "Phytium SoC Mailbox Support"
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++	help
++	  Mailbox driver implementation for the Phytium platform. It is used
++	  to send message between application processors and on-chip management
++	  firmware. Say Y here if you want to build this mailbox controller
++	  driver.
++
+ endif
+--- a/drivers/mailbox/Makefile
++++ b/drivers/mailbox/Makefile
+@@ -54,3 +54,5 @@ obj-$(CONFIG_SUN6I_MSGBOX)	+= sun6i-msgb
+ obj-$(CONFIG_SPRD_MBOX)		+= sprd-mailbox.o
+ 
+ obj-$(CONFIG_QCOM_IPCC)		+= qcom-ipcc.o
++
++obj-$(CONFIG_PHYTIUM_MBOX)	+= phytium-mailbox.o
+--- a/drivers/media/platform/Kconfig
++++ b/drivers/media/platform/Kconfig
+@@ -168,6 +168,15 @@ config VIDEO_TI_CAL
+ 	  In TI Technical Reference Manual this module is referred as
+ 	  Camera Interface Subsystem (CAMSS).
+ 
++config VIDEO_PHYTIUM_JPEG
++        tristate "Phytium JPEG Encoder driver"
++        depends on VIDEO_V4L2
++        select VIDEOBUF2_DMA_CONTIG
++	help
++          Support for the Phytium JPEG Encoder Engine embedded
++          in the Phytium SOCs. The engine can capture and
++          compress video data from digital or analog sources.
++
+ endif # V4L_PLATFORM_DRIVERS
+ 
+ menuconfig V4L_MEM2MEM_DRIVERS
+--- a/drivers/media/platform/Makefile
++++ b/drivers/media/platform/Makefile
+@@ -80,3 +80,4 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS)		+= qcom/
+ obj-$(CONFIG_VIDEO_QCOM_VENUS)		+= qcom/venus/
+ 
+ obj-y					+= sunxi/
++obj-$(CONFIG_VIDEO_PHYTIUM_JPEG)	+= phytium-jpeg/
+\ No newline at end of file
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -1035,6 +1035,21 @@ config UCB1400_CORE
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called ucb1400_core.
+ 
++config MFD_PHYTIUM_I2S_LSD
++	tristate "PHYTIUM px210 I2S LSD MFD driver"
++	depends on (PCI && ARCH_PHYTIUM)
++	select MFD_CORE
++	help
++	  This enables support for the Phytium px210 LSD I2S controller.
++
++config MFD_PHYTIUM_I2S_MMD
++	tristate "PHYTIUM px210 I2S MMD MFD driver"
++	depends on (PCI && ARCH_PHYTIUM)
++	select MFD_CORE
++	help
++	  This enables support for the Phytium px210 MMD I2S controllers
++	  for Display Port.
++
+ config MFD_PM8XXX
+ 	tristate "Qualcomm PM8xxx PMIC chips driver"
+ 	depends on (ARM || HEXAGON || COMPILE_TEST)
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -267,3 +267,6 @@ obj-$(CONFIG_MFD_KHADAS_MCU) 	+= khadas-
+ obj-$(CONFIG_SGI_MFD_IOC3)	+= ioc3.o
+ obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)	+= simple-mfd-i2c.o
+ obj-$(CONFIG_MFD_INTEL_M10_BMC)   += intel-m10-bmc.o
++
++obj-$(CONFIG_MFD_PHYTIUM_I2S_LSD) += phytium_px210_i2s_lsd.o
++obj-$(CONFIG_MFD_PHYTIUM_I2S_MMD) += phytium_px210_i2s_mmd.o
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -1105,3 +1105,37 @@ config MMC_OWL
+ 
+ config MMC_SDHCI_EXTERNAL_DMA
+ 	bool
++
++config MMC_PHYTIUM_SDCI
++	tristate "Phytium SD Host Controller support"
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++	default y if ARCH_PHYTIUM
++	help
++	  This selects support for the SD/MMC Host Controller on
++	  Phytium SoC family.
++
++	  If you have a controller with this interface, say Y or M here.
++
++	  If unsure, say N.
++
++config MMC_PHYTIUM_MCI_PCI
++	tristate "Phytium octopus PCI MultiMedia Card Interface support"
++	depends on ARCH_PHYTIUM
++	default y if ARCH_PHYTIUM
++	help
++	  This selects support for the PCI MultiMedia Card Interface on Phytium
++	  px210 chipset.
++
++	  If you have a controller with this interface, say Y or M here.
++
++	  If unsure, say N.
++
++config MMC_PHYTIUM_MCI_PLTFM
++	tristate "Phytium MultiMedia Card Interface support"
++	depends on ARCH_PHYTIUM && OF
++	default y if ARCH_PHYTIUM
++        help
++          This selects support for the MultiMedia Card Interface on Phytium SoCs.
++	  If you have a controller with this interface, say Y or M here.
++
++	  If unsure, say N.
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -77,6 +77,7 @@ obj-$(CONFIG_MMC_USDHI6ROL0)	+= usdhi6ro
+ obj-$(CONFIG_MMC_TOSHIBA_PCI)	+= toshsd.o
+ obj-$(CONFIG_MMC_BCM2835)	+= bcm2835.o
+ obj-$(CONFIG_MMC_OWL)		+= owl-mmc.o
++obj-$(CONFIG_MMC_PHYTIUM_SDCI)	+= phytium-sdci.o
+ 
+ obj-$(CONFIG_MMC_REALTEK_PCI)	+= rtsx_pci_sdmmc.o
+ obj-$(CONFIG_MMC_REALTEK_USB)	+= rtsx_usb_sdmmc.o
+@@ -112,3 +113,6 @@ endif
+ 
+ obj-$(CONFIG_MMC_SDHCI_XENON)	+= sdhci-xenon-driver.o
+ sdhci-xenon-driver-y		+= sdhci-xenon.o sdhci-xenon-phy.o
++
++obj-$(CONFIG_MMC_PHYTIUM_MCI_PCI)	+= phytium-mci-pci.o phytium-mci.o
++obj-$(CONFIG_MMC_PHYTIUM_MCI_PLTFM)	+= phytium-mci-plat.o phytium-mci.o
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -486,6 +486,25 @@ config MTD_NAND_RICOH
+ 	  expermental, readwrite
+ 	  'SmartMedia/xD new translation layer'
+ 
++config MTD_NAND_PHYTIUM
++	tristate
++
++config MTD_NAND_PHYTIUM_PCI
++	tristate "Support Phytium NAND controller as a PCI device"
++	select MTD_NAND_PHYTIUM
++	depends on PCI
++	help
++	  Enable the driver for NAND flash controller of Phytium Px210 chipset,
++	  using the Phytium NAND controller core.
++
++config MTD_NAND_PHYTIUM_PLAT
++	tristate "Support Phytium NAND controller as a platform device"
++	select MTD_NAND_PHYTIUM
++	depends on ARCH_PHYTIUM
++	help
++	  Enable the driver for NAND flash controller of Phytium CPU chipset,
++	  using the Phytium NAND controller core.
++
+ config MTD_NAND_DISKONCHIP
+ 	tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation)"
+ 	depends on HAS_IOMEM
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -59,6 +59,10 @@ obj-$(CONFIG_MTD_NAND_MESON)		+= meson_n
+ obj-$(CONFIG_MTD_NAND_CADENCE)		+= cadence-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_ARASAN)		+= arasan-nand-controller.o
+ 
++obj-$(CONFIG_MTD_NAND_PHYTIUM)		+= phytium_nand.o
++obj-$(CONFIG_MTD_NAND_PHYTIUM_PCI)	+= phytium_nand_pci.o
++obj-$(CONFIG_MTD_NAND_PHYTIUM_PLAT)	+= phytium_nand_plat.o
++
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
+ nand-objs += nand_jedec.o
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -17,6 +17,7 @@ spi-nor-objs			+= sst.o
+ spi-nor-objs			+= winbond.o
+ spi-nor-objs			+= xilinx.o
+ spi-nor-objs			+= xmc.o
++spi-nor-objs			+= boya.o
+ spi-nor-objs			+= xtx.o
+ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
+ 
+--- a/drivers/mtd/spi-nor/controllers/Kconfig
++++ b/drivers/mtd/spi-nor/controllers/Kconfig
+@@ -62,3 +62,12 @@ config SPI_INTEL_SPI_PLATFORM
+ 
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called intel-spi-platform.
++
++config SPI_PHYTIUM_QUADSPI
++    tristate "Phytium Quad SPI Controller"
++    depends on ARCH_PHYTIUM || ARM
++    depends on OF && HAS_IOMEM
++    help
++      This enables support for the Quad SPI controller in master mode.
++      This driver does not support generic SPI. The implementation only
++      supports SPI NOR.
+--- a/drivers/mtd/spi-nor/controllers/Makefile
++++ b/drivers/mtd/spi-nor/controllers/Makefile
+@@ -5,3 +5,4 @@ obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi
+ obj-$(CONFIG_SPI_INTEL_SPI)	+= intel-spi.o
+ obj-$(CONFIG_SPI_INTEL_SPI_PCI)	+= intel-spi-pci.o
+ obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM)	+= intel-spi-platform.o
++obj-$(CONFIG_SPI_PHYTIUM_QUADSPI)   += phytium-quadspi.o
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -2038,6 +2038,7 @@ static const struct spi_nor_manufacturer
+ 	&spi_nor_winbond,
+ 	&spi_nor_xilinx,
+ 	&spi_nor_xmc,
++	&spi_nor_boya,
+ 	&spi_nor_xtx,
+ };
+ 
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -398,6 +398,7 @@ extern const struct spi_nor_manufacturer
+ extern const struct spi_nor_manufacturer spi_nor_winbond;
+ extern const struct spi_nor_manufacturer spi_nor_xilinx;
+ extern const struct spi_nor_manufacturer spi_nor_xmc;
++extern const struct spi_nor_manufacturer spi_nor_boya;
+ extern const struct spi_nor_manufacturer spi_nor_xtx;
+ 
+ int spi_nor_write_enable(struct spi_nor *nor);
+--- a/drivers/net/can/Kconfig
++++ b/drivers/net/can/Kconfig
+@@ -179,6 +179,8 @@ source "drivers/net/can/softing/Kconfig"
+ source "drivers/net/can/spi/Kconfig"
+ source "drivers/net/can/usb/Kconfig"
+ 
++source "drivers/net/can/phytium/Kconfig"
++
+ endif
+ 
+ config CAN_DEBUG_DEVICES
+--- a/drivers/net/can/Makefile
++++ b/drivers/net/can/Makefile
+@@ -29,5 +29,6 @@ obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
+ obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
+ obj-$(CONFIG_CAN_XILINXCAN)	+= xilinx_can.o
+ obj-$(CONFIG_PCH_CAN)		+= pch_can.o
++obj-$(CONFIG_CAN_PHYTIUM)	+= phytium/
+ 
+ subdir-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) += -DDEBUG
+--- a/drivers/net/ethernet/cadence/macb.h
++++ b/drivers/net/ethernet/cadence/macb.h
+@@ -9,6 +9,7 @@
+ 
+ #include <linux/clk.h>
+ #include <linux/phylink.h>
++#include <linux/phy.h>
+ #include <linux/ptp_clock_kernel.h>
+ #include <linux/net_tstamp.h>
+ #include <linux/interrupt.h>
+@@ -17,6 +18,12 @@
+ #define MACB_EXT_DESC
+ #endif
+ 
++enum irq_type {
++	IRQ_TYPE_INTX = 1,
++	IRQ_TYPE_MSI = 2,
++	IRQ_TYPE_MAX = 3,
++};
++
+ #define MACB_GREGS_NBR 16
+ #define MACB_GREGS_VERSION 2
+ #define MACB_MAX_QUEUES 8
+@@ -77,10 +84,13 @@
+ #define MACB_RBQPH		0x04D4
+ 
+ /* GEM register offsets. */
++#define GEM_NCR			0x0000 /* Network Control */
+ #define GEM_NCFGR		0x0004 /* Network Config */
+ #define GEM_USRIO		0x000c /* User IO */
+ #define GEM_DMACFG		0x0010 /* DMA Configuration */
+ #define GEM_JML			0x0048 /* Jumbo Max Length */
++#define GEM_HS_MAC_CONFIG	0x0050 /* GEM high speed config */
++#define GEM_AXI_PIPE	0x0054 /* Axi max pipeline register*/
+ #define GEM_HRB			0x0080 /* Hash Bottom */
+ #define GEM_HRT			0x0084 /* Hash Top */
+ #define GEM_SA1B		0x0088 /* Specific1 Bottom */
+@@ -157,6 +167,7 @@
+ #define GEM_PEFTN		0x01f4 /* PTP Peer Event Frame Tx Ns */
+ #define GEM_PEFRSL		0x01f8 /* PTP Peer Event Frame Rx Sec Low */
+ #define GEM_PEFRN		0x01fc /* PTP Peer Event Frame Rx Ns */
++#define GEM_PCSCNTRL		0x0200 /* PCS Control */
+ #define GEM_DCFG1		0x0280 /* Design Config 1 */
+ #define GEM_DCFG2		0x0284 /* Design Config 2 */
+ #define GEM_DCFG3		0x0288 /* Design Config 3 */
+@@ -166,6 +177,10 @@
+ #define GEM_DCFG7		0x0298 /* Design Config 7 */
+ #define GEM_DCFG8		0x029C /* Design Config 8 */
+ #define GEM_DCFG10		0x02A4 /* Design Config 10 */
++#define GEM_DCFG12		0x02AC /* Design Config 12 */
++#define GEM_USX_CONTROL		0x0A80 /* High speed PCS control register */
++#define GEM_USX_STATUS		0x0A88 /* High speed PCS status register */
++#define GEM_TAIL_ENABLE		0x0E7C /* Phytium: Enable tail */
+ 
+ #define GEM_TXBDCTRL	0x04cc /* TX Buffer Descriptor control register */
+ #define GEM_RXBDCTRL	0x04d0 /* RX Buffer Descriptor control register */
+@@ -200,6 +215,37 @@
+ #define GEM_IER(hw_q)		(0x0600 + ((hw_q) << 2))
+ #define GEM_IDR(hw_q)		(0x0620 + ((hw_q) << 2))
+ #define GEM_IMR(hw_q)		(0x0640 + ((hw_q) << 2))
++#define GEM_TAIL(hw_q)		(0x0e80 + ((hw_q) << 2)) /* Phytium: tail register */
++#define GEM_SRC_SEL_LN          0x1C04
++#define GEM_DIV_SEL0_LN         0x1C08
++#define GEM_DIV_SEL1_LN         0x1C0C
++#define GEM_PMA_XCVR_POWER_STATE  0x1C10
++#define GEM_SPEED_MODE          0x1C14
++#define GEM_MII_SELECT          0x1C18
++#define GEM_SEL_MII_ON_RGMII    0x1C1C
++#define GEM_TX_CLK_SEL0         0x1C20
++#define GEM_TX_CLK_SEL1         0x1C24
++#define GEM_TX_CLK_SEL2         0x1C28
++#define GEM_TX_CLK_SEL3         0x1C2C
++#define GEM_RX_CLK_SEL0         0x1C30
++#define GEM_RX_CLK_SEL1         0x1C34
++#define GEM_CLK_250M_DIV10_DIV100_SEL 0x1C38
++#define GEM_TX_CLK_SEL5         0x1C3C
++#define GEM_TX_CLK_SEL6         0x1C40
++#define GEM_RX_CLK_SEL4         0x1C44
++#define GEM_RX_CLK_SEL5         0x1C48
++#define GEM_TX_CLK_SEL3_0       0x1C70
++#define GEM_TX_CLK_SEL4_0         0x1C74
++#define GEM_RX_CLK_SEL3_0         0x1C78
++#define GEM_RX_CLK_SEL4_0         0x1C7C
++#define GEM_RGMII_TX_CLK_SEL0     0x1C80
++#define GEM_RGMII_TX_CLK_SEL1     0x1C84
++
++#define GEM_PHY_INT_ENABLE        0x1C88
++#define GEM_PHY_INT_CLEAR         0x1C8C
++#define GEM_PHY_INT_STATE         0x1C90
++
++#define GEM_INTX_IRQ_MASK		  0x1C7C /* Phytium: irq mask */
+ 
+ /* Bitfields in NCR */
+ #define MACB_LB_OFFSET		0 /* reserved */
+@@ -231,6 +277,8 @@
+ #define MACB_SRTSM_OFFSET	15
+ #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
+ #define MACB_OSSMODE_SIZE	1
++#define MACB_2PT5G_OFFSET	29 /* 2.5G operation selected */
++#define MACB_2PT5G_SIZE		1
+ 
+ /* Bitfields in NCFGR */
+ #define MACB_SPD_OFFSET		0 /* Speed */
+@@ -272,11 +320,19 @@
+ #define MACB_IRXFCS_OFFSET	19
+ #define MACB_IRXFCS_SIZE	1
+ 
++/* GEM specific NCR bitfields. */
++#define GEM_ENABLE_HS_MAC_OFFSET	31
++#define GEM_ENABLE_HS_MAC_SIZE		1
++
+ /* GEM specific NCFGR bitfields. */
++#define GEM_FD_OFFSET		1 /* Full duplex */
++#define GEM_FD_SIZE		1
+ #define GEM_GBE_OFFSET		10 /* Gigabit mode enable */
+ #define GEM_GBE_SIZE		1
+ #define GEM_PCSSEL_OFFSET	11
+ #define GEM_PCSSEL_SIZE		1
++#define GEM_PAE_OFFSET		13 /* Pause enable */
++#define GEM_PAE_SIZE		1
+ #define GEM_CLK_OFFSET		18 /* MDC clock division */
+ #define GEM_CLK_SIZE		3
+ #define GEM_DBW_OFFSET		21 /* Data bus width */
+@@ -461,11 +517,21 @@
+ #define MACB_REV_OFFSET				0
+ #define MACB_REV_SIZE				16
+ 
++/* Bitfield in HS_MAC_CONFIG */
++#define GEM_HS_MAC_SPEED_OFFSET			0
++#define GEM_HS_MAC_SPEED_SIZE			3
++
++/* Bitfields in PCSCNTRL */
++#define GEM_PCSAUTONEG_OFFSET			12
++#define GEM_PCSAUTONEG_SIZE			1
++
+ /* Bitfields in DCFG1. */
+ #define GEM_IRQCOR_OFFSET			23
+ #define GEM_IRQCOR_SIZE				1
+ #define GEM_DBWDEF_OFFSET			25
+ #define GEM_DBWDEF_SIZE				3
++#define GEM_NO_PCS_OFFSET			0
++#define GEM_NO_PCS_SIZE				1
+ 
+ /* Bitfields in DCFG2. */
+ #define GEM_RX_PKT_BUFF_OFFSET			20
+@@ -500,6 +566,30 @@
+ #define GEM_RXBD_RDBUFF_OFFSET			8
+ #define GEM_RXBD_RDBUFF_SIZE			4
+ 
++/* Bitfields in DCFG12. */
++#define GEM_HIGH_SPEED_OFFSET			26
++#define GEM_HIGH_SPEED_SIZE			1
++
++/* Bitfields in USX_CONTROL. */
++#define GEM_USX_CTRL_SPEED_OFFSET		14
++#define GEM_USX_CTRL_SPEED_SIZE			3
++#define GEM_SERDES_RATE_OFFSET			12
++#define GEM_SERDES_RATE_SIZE			2
++#define GEM_RX_SCR_BYPASS_OFFSET		9
++#define GEM_RX_SCR_BYPASS_SIZE			1
++#define GEM_TX_SCR_BYPASS_OFFSET		8
++#define GEM_TX_SCR_BYPASS_SIZE			1
++#define GEM_RX_SYNC_RESET_OFFSET		2
++#define GEM_RX_SYNC_RESET_SIZE			1
++#define GEM_TX_EN_OFFSET			1
++#define GEM_TX_EN_SIZE				1
++#define GEM_SIGNAL_OK_OFFSET			0
++#define GEM_SIGNAL_OK_SIZE			1
++
++/* Bitfields in USX_STATUS. */
++#define GEM_USX_BLOCK_LOCK_OFFSET		0
++#define GEM_USX_BLOCK_LOCK_SIZE			1
++
+ /* Bitfields in TISUBN */
+ #define GEM_SUBNSINCR_OFFSET			0
+ #define GEM_SUBNSINCRL_OFFSET			24
+@@ -658,11 +748,16 @@
+ #define MACB_CAPS_GEM_HAS_PTP			0x00000040
+ #define MACB_CAPS_BD_RD_PREFETCH		0x00000080
+ #define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
++#define MACB_CAPS_SEL_CLK			0x00000200
++#define MACB_CAPS_TAILPTR		0x00001000 /* Phytium: tail register */
++#define MACB_CAPS_CLK_HW_CHG			0x04000000
+ #define MACB_CAPS_MACB_IS_EMAC			0x08000000
+ #define MACB_CAPS_FIFO_MODE			0x10000000
+ #define MACB_CAPS_GIGABIT_MODE_AVAILABLE	0x20000000
+ #define MACB_CAPS_SG_DISABLED			0x40000000
+ #define MACB_CAPS_MACB_IS_GEM			0x80000000
++#define MACB_CAPS_PCS				0x01000000
++#define MACB_CAPS_HIGH_SPEED			0x02000000
+ 
+ /* LSO settings */
+ #define MACB_LSO_UFO_ENABLE			0x01
+@@ -1112,6 +1207,7 @@ struct macb_config {
+ 			    struct clk **rx_clk, struct clk **tsu_clk);
+ 	int	(*init)(struct platform_device *pdev);
+ 	int	jumbo_max_len;
++	void (*sel_clk_hw)(struct macb *bp, int speed);
+ };
+ 
+ struct tsu_incr {
+@@ -1132,6 +1228,7 @@ struct macb_queue {
+ 	unsigned int		RBQS;
+ 	unsigned int		RBQP;
+ 	unsigned int		RBQPH;
++	unsigned int		TAILADDR;
+ 
+ 	unsigned int		tx_head, tx_tail;
+ 	struct macb_dma_desc	*tx_ring;
+@@ -1191,6 +1288,7 @@ struct macb {
+ 	struct clk		*rx_clk;
+ 	struct clk		*tsu_clk;
+ 	struct net_device	*dev;
++	struct ncsi_dev		*ndev;
+ 	union {
+ 		struct macb_stats	macb;
+ 		struct gem_stats	gem;
+@@ -1201,7 +1299,13 @@ struct macb {
+ 	struct mii_bus		*mii_bus;
+ 	struct phylink		*phylink;
+ 	struct phylink_config	phylink_config;
++	struct phylink_pcs	phylink_pcs;
++	int			link;
++	int			speed;
++	int			duplex;
++	int			use_ncsi;
+ 
++	int 		force_phy_mode;
+ 	u32			caps;
+ 	unsigned int		dma_burst_length;
+ 
+@@ -1244,6 +1348,8 @@ struct macb {
+ 	u32	rx_intr_mask;
+ 
+ 	struct macb_pm_data pm_data;
++
++	void (*sel_clk_hw)(struct macb *bp, int speed);
+ };
+ 
+ #ifdef CONFIG_MACB_USE_HWSTAMP
+@@ -1301,6 +1407,24 @@ static inline bool gem_has_ptp(struct ma
+ 	return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
+ }
+ 
++enum phytium_type {
++	PHYTIUM_DEV_1P0 = 1,
++	PHYTIUM_DEV_2P0,
++	PHYTIUM_DEV_3P0,
++};
++
++struct phytium_platform_pdata {
++	int			phytium_dev_type;
++	struct clk		*txclk;
++	struct clk		*rxclk;
++	struct clk		*tsu_clk;
++	u32			caps;
++	int			irq_type;
++	int			irq[4];
++	phy_interface_t		phy_interface;
++	const struct property_entry *properties;
++};
++
+ /**
+  * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
+  * @pclk:		platform clock
+@@ -1309,6 +1433,7 @@ static inline bool gem_has_ptp(struct ma
+ struct macb_platform_data {
+ 	struct clk	*pclk;
+ 	struct clk	*hclk;
++	struct phytium_platform_pdata phytium_macb_pdata;
+ };
+ 
+ #endif /* _MACB_H */
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -35,6 +35,8 @@
+ #include <linux/tcp.h>
+ #include <linux/iopoll.h>
+ #include <linux/pm_runtime.h>
++#include <linux/acpi.h>
++#include <net/ncsi.h>
+ #include "macb.h"
+ 
+ /* This structure is only used for MACB on SiFive FU540 devices */
+@@ -84,6 +86,14 @@ struct sifive_fu540_macb_mgmt {
+ #define MACB_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
+ #define MACB_WOL_ENABLED		(0x1 << 1)
+ 
++#define HS_SPEED_100M			0
++#define HS_SPEED_1000M			1
++#define HS_SPEED_2500M			2
++#define HS_SPEED_5000M			3
++#define HS_SPEED_10000M			4
++#define MACB_SERDES_RATE_5G		0
++#define MACB_SERDES_RATE_10G	1
++
+ /* Graceful stop timeouts in us. We should allow up to
+  * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
+  */
+@@ -513,6 +523,10 @@ static void macb_validate(struct phylink
+ 	    state->interface != PHY_INTERFACE_MODE_RMII &&
+ 	    state->interface != PHY_INTERFACE_MODE_GMII &&
+ 	    state->interface != PHY_INTERFACE_MODE_SGMII &&
++		state->interface != PHY_INTERFACE_MODE_2500BASEX &&
++	    state->interface != PHY_INTERFACE_MODE_5GBASER &&
++	    state->interface != PHY_INTERFACE_MODE_10GBASER &&
++		state->interface != PHY_INTERFACE_MODE_USXGMII &&
+ 	    !phy_interface_mode_is_rgmii(state->interface)) {
+ 		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
+ 		return;
+@@ -525,10 +539,47 @@ static void macb_validate(struct phylink
+ 		return;
+ 	}
+ 
++	if ((state->interface == PHY_INTERFACE_MODE_10GBASER ||
++	     state->interface == PHY_INTERFACE_MODE_USXGMII ||
++	     state->interface == PHY_INTERFACE_MODE_5GBASER) &&
++	    !(bp->caps & MACB_CAPS_HIGH_SPEED &&
++	      bp->caps & MACB_CAPS_PCS)) {
++		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
++		return;
++	}
++
+ 	phylink_set_port_modes(mask);
+ 	phylink_set(mask, Autoneg);
+ 	phylink_set(mask, Asym_Pause);
+ 
++	if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
++	    (state->interface == PHY_INTERFACE_MODE_NA ||
++	     state->interface == PHY_INTERFACE_MODE_10GBASER ||
++	     state->interface == PHY_INTERFACE_MODE_USXGMII)) {
++		bp->speed = state->speed;
++		bp->link = 1;
++		bp->duplex = state->duplex;
++		if (bp->speed == SPEED_5000) {
++			phylink_set(mask, 5000baseT_Full);
++		} else {
++			phylink_set(mask, 10000baseCR_Full);
++			phylink_set(mask, 10000baseER_Full);
++			phylink_set(mask, 10000baseKR_Full);
++			phylink_set(mask, 10000baseLR_Full);
++			phylink_set(mask, 10000baseLRM_Full);
++			phylink_set(mask, 10000baseSR_Full);
++			phylink_set(mask, 10000baseT_Full);
++		}
++		if (state->interface != PHY_INTERFACE_MODE_NA)
++			goto out;
++	}
++
++	if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
++		phylink_set(mask, 2500baseX_Full);
++
++	if (state->interface == PHY_INTERFACE_MODE_5GBASER)
++		phylink_set(mask, 5000baseT_Full);
++
+ 	phylink_set(mask, 10baseT_Half);
+ 	phylink_set(mask, 10baseT_Full);
+ 	phylink_set(mask, 100baseT_Half);
+@@ -545,23 +596,110 @@ static void macb_validate(struct phylink
+ 		if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
+ 			phylink_set(mask, 1000baseT_Half);
+ 	}
+-
++out:
+ 	bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
+ 	bitmap_and(state->advertising, state->advertising, mask,
+ 		   __ETHTOOL_LINK_MODE_MASK_NBITS);
+ }
+ 
+-static void macb_mac_pcs_get_state(struct phylink_config *config,
++static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++				 phy_interface_t interface, int speed,
++				 int duplex)
++{
++	struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
++	u32 config;
++
++	config = gem_readl(bp, USX_CONTROL);
++	if (speed == SPEED_10000) {
++		config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
++		config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
++	} else if (speed == SPEED_5000) {
++		config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_5G, config);
++		config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_5000M, config);
++	}
++
++	config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
++	/* reset */
++	config &= ~(GEM_BIT(SIGNAL_OK) | GEM_BIT(TX_EN));
++	config |= GEM_BIT(RX_SYNC_RESET);
++
++	gem_writel(bp, USX_CONTROL, config);
++
++	/* enable rx and tx */
++	config &= ~(GEM_BIT(RX_SYNC_RESET));
++	config |= GEM_BIT(SIGNAL_OK) | GEM_BIT(TX_EN);
++
++	gem_writel(bp, USX_CONTROL, config);
++}
++
++static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
+ 				   struct phylink_link_state *state)
+ {
++	struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
++	u32 val;
++
++	if (state->interface == PHY_INTERFACE_MODE_5GBASER)
++		state->speed = SPEED_5000;
++	else if (state->interface == PHY_INTERFACE_MODE_10GBASER ||
++		 state->interface == PHY_INTERFACE_MODE_USXGMII)
++		state->speed = bp->speed;
++
++	state->duplex = 1;
++	state->an_complete = 1;
++
++	val = gem_readl(bp, USX_STATUS);
++	state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
++	val = gem_readl(bp, NCFGR);
++	if (val & GEM_BIT(PAE))
++		state->pause = MLO_PAUSE_RX;
++}
++
++static int macb_usx_pcs_config(struct phylink_pcs *pcs,
++			       unsigned int mode,
++			       phy_interface_t interface,
++			       const unsigned long *advertising,
++			       bool permit_pause_to_mac)
++{
++	struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
++
++	gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
++		   GEM_BIT(SIGNAL_OK));
++
++	return 0;
++}
++
++static void macb_pcs_get_state(struct phylink_pcs *pcs,
++			       struct phylink_link_state *state)
++{
+ 	state->link = 0;
+ }
+ 
+-static void macb_mac_an_restart(struct phylink_config *config)
++static void macb_pcs_an_restart(struct phylink_pcs *pcs)
+ {
+ 	/* Not supported */
+ }
+ 
++static int macb_pcs_config(struct phylink_pcs *pcs,
++			   unsigned int mode,
++			   phy_interface_t interface,
++			   const unsigned long *advertising,
++			   bool permit_pause_to_mac)
++{
++	return 0;
++}
++
++static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
++	.pcs_get_state = macb_usx_pcs_get_state,
++	.pcs_config = macb_usx_pcs_config,
++	.pcs_link_up = macb_usx_pcs_link_up,
++};
++
++static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
++	.pcs_get_state = macb_pcs_get_state,
++	.pcs_an_restart = macb_pcs_an_restart,
++	.pcs_config = macb_pcs_config,
++};
++
+ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
+ 			    const struct phylink_link_state *state)
+ {
+@@ -569,25 +707,57 @@ static void macb_mac_config(struct phyli
+ 	struct macb *bp = netdev_priv(ndev);
+ 	unsigned long flags;
+ 	u32 old_ctrl, ctrl;
++	u32 old_ncr, ncr;
+ 
+ 	spin_lock_irqsave(&bp->lock, flags);
+ 
+-	old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
++	ctrl = macb_or_gem_readl(bp, NCFGR);
++	old_ctrl = ctrl;
++	ncr = macb_or_gem_readl(bp, NCR);
++	old_ncr = ncr;
+ 
+ 	if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
+ 		if (state->interface == PHY_INTERFACE_MODE_RMII)
+ 			ctrl |= MACB_BIT(RM9200_RMII);
+ 	} else if (macb_is_gem(bp)) {
+ 		ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
++		ncr &= ~GEM_BIT(ENABLE_HS_MAC);
+ 
+-		if (state->interface == PHY_INTERFACE_MODE_SGMII)
++		if (state->interface == PHY_INTERFACE_MODE_SGMII ||
++		    state->interface == PHY_INTERFACE_MODE_2500BASEX) {
+ 			ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
++		} else if (state->interface == PHY_INTERFACE_MODE_10GBASER ||
++			   state->interface == PHY_INTERFACE_MODE_USXGMII ||
++			   state->interface == PHY_INTERFACE_MODE_5GBASER) {
++			ctrl |= GEM_BIT(PCSSEL);
++			ncr |= GEM_BIT(ENABLE_HS_MAC);
++		}
+ 	}
+ 
+ 	/* Apply the new configuration, if any */
+ 	if (old_ctrl ^ ctrl)
+ 		macb_or_gem_writel(bp, NCFGR, ctrl);
+ 
++	if (old_ncr ^ ncr)
++		macb_or_gem_writel(bp, NCR, ncr);
++
++	/* Disable AN for SGMII fixed link configuration, enable otherwise.
++	 * Must be written after PCSSEL is set in NCFGR,
++	 * otherwise writes will not take effect.
++	 */
++	if (macb_is_gem(bp) && (state->interface == PHY_INTERFACE_MODE_SGMII ||
++				PHY_INTERFACE_MODE_2500BASEX)) {
++		u32 pcsctrl, old_pcsctrl;
++
++		old_pcsctrl = gem_readl(bp, PCSCNTRL);
++		if (mode == MLO_AN_FIXED)
++			pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
++		else
++			pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
++		if (old_pcsctrl != pcsctrl)
++			gem_writel(bp, PCSCNTRL, pcsctrl);
++	}
++
+ 	spin_unlock_irqrestore(&bp->lock, flags);
+ }
+ 
+@@ -600,18 +770,184 @@ static void macb_mac_link_down(struct ph
+ 	unsigned int q;
+ 	u32 ctrl;
+ 
++	if (bp->use_ncsi)
++		ncsi_stop_dev(bp->ndev);
++
+ 	if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
+ 		for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
+ 			queue_writel(queue, IDR,
+ 				     bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
+ 
+ 	/* Disable Rx and Tx */
+-	ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
++	ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE)) & ~(MACB_BIT(2PT5G));
+ 	macb_writel(bp, NCR, ctrl);
+ 
+ 	netif_tx_stop_all_queues(ndev);
+ }
+ 
++static void phytium_gem1p0_sel_clk(struct macb *bp, int speed)
++{
++	if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
++	    bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
++		gem_writel(bp, SRC_SEL_LN, 0x1); /*0x1c04*/
++		if (speed == SPEED_5000) {
++			gem_writel(bp, DIV_SEL0_LN, 0x8); /*0x1c08*/
++			gem_writel(bp, DIV_SEL0_LN, 0x8); /*0x1c08*/
++			gem_writel(bp, DIV_SEL1_LN, 0x2); /*0x1c0c*/
++			gem_writel(bp, PMA_XCVR_POWER_STATE, 0x0); /*0x1c10*/
++		} else {
++			gem_writel(bp, DIV_SEL0_LN, 0x4); /*0x1c08*/
++			gem_writel(bp, DIV_SEL1_LN, 0x1); /*0x1c0c*/
++			gem_writel(bp, PMA_XCVR_POWER_STATE, 0x1); /*0x1c10*/
++		}
++	} else if (bp->phy_interface ==  PHY_INTERFACE_MODE_5GBASER) {
++		gem_writel(bp, SRC_SEL_LN, 0x1); /*0x1c04*/
++		gem_writel(bp, DIV_SEL0_LN, 0x8); /*0x1c08*/
++		gem_writel(bp, DIV_SEL1_LN, 0x2); /*0x1c0c*/
++		gem_writel(bp, PMA_XCVR_POWER_STATE, 0x0); /*0x1c10*/
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
++		gem_writel(bp, SRC_SEL_LN, 0x1); /*0x1c04*/
++		gem_writel(bp, DIV_SEL0_LN, 0x1); /*0x1c08*/
++		gem_writel(bp, DIV_SEL1_LN, 0x2); /*0x1c0c*/
++		gem_writel(bp, PMA_XCVR_POWER_STATE, 0x1); /*0x1c10*/
++		gem_writel(bp, TX_CLK_SEL0, 0x0); /*0x1c20*/
++		gem_writel(bp, TX_CLK_SEL1, 0x1); /*0x1c24*/
++		gem_writel(bp, TX_CLK_SEL2, 0x1); /*0x1c28*/
++		gem_writel(bp, TX_CLK_SEL3, 0x1); /*0x1c2c*/
++		gem_writel(bp, RX_CLK_SEL0, 0x1); /*0x1c30*/
++		gem_writel(bp, RX_CLK_SEL1, 0x0); /*0x1c34*/
++		gem_writel(bp, TX_CLK_SEL3_0, 0x0); /*0x1c70*/
++		gem_writel(bp, TX_CLK_SEL4_0, 0x0); /*0x1c74*/
++		gem_writel(bp, RX_CLK_SEL3_0, 0x0); /*0x1c78*/
++		gem_writel(bp, RX_CLK_SEL4_0, 0x0); /*0x1c7c*/
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
++		if (speed == SPEED_1000) {
++			gem_writel(bp, SRC_SEL_LN, 0x1); /*0x1c04*/
++			gem_writel(bp, DIV_SEL0_LN, 0x4); /*0x1c08*/
++			gem_writel(bp, DIV_SEL1_LN, 0x8); /*0x1c0c*/
++			gem_writel(bp, PMA_XCVR_POWER_STATE, 0x1); /*0x1c10*/
++			gem_writel(bp, TX_CLK_SEL0, 0x0); /*0x1c20*/
++			gem_writel(bp, TX_CLK_SEL1, 0x0); /*0x1c24*/
++			gem_writel(bp, TX_CLK_SEL2, 0x0); /*0x1c28*/
++			gem_writel(bp, TX_CLK_SEL3, 0x1); /*0x1c2c*/
++			gem_writel(bp, RX_CLK_SEL0, 0x1); /*0x1c30*/
++			gem_writel(bp, RX_CLK_SEL1, 0x0); /*0x1c34*/
++			gem_writel(bp, TX_CLK_SEL3_0, 0x0); /*0x1c70*/
++			gem_writel(bp, TX_CLK_SEL4_0, 0x0); /*0x1c74*/
++			gem_writel(bp, RX_CLK_SEL3_0, 0x0); /*0x1c78*/
++			gem_writel(bp, RX_CLK_SEL4_0, 0x0); /*0x1c7c*/
++		} else if (speed == SPEED_100  || speed == SPEED_10) {
++			gem_writel(bp, SRC_SEL_LN, 0x1); /*0x1c04*/
++			gem_writel(bp, DIV_SEL0_LN, 0x4); /*0x1c08*/
++			gem_writel(bp, DIV_SEL1_LN, 0x8); /*0x1c0c*/
++			gem_writel(bp, PMA_XCVR_POWER_STATE, 0x1); /*0x1c10*/
++			gem_writel(bp, TX_CLK_SEL0, 0x0); /*0x1c20*/
++			gem_writel(bp, TX_CLK_SEL1, 0x0); /*0x1c24*/
++			gem_writel(bp, TX_CLK_SEL2, 0x1); /*0x1c28*/
++			gem_writel(bp, TX_CLK_SEL3, 0x1); /*0x1c2c*/
++			gem_writel(bp, RX_CLK_SEL0, 0x1); /*0x1c30*/
++			gem_writel(bp, RX_CLK_SEL1, 0x0); /*0x1c34*/
++			gem_writel(bp, TX_CLK_SEL3_0, 0x1); /*0x1c70*/
++			gem_writel(bp, TX_CLK_SEL4_0, 0x0); /*0x1c74*/
++			gem_writel(bp, RX_CLK_SEL3_0, 0x0); /*0x1c78*/
++			gem_writel(bp, RX_CLK_SEL4_0, 0x1); /*0x1c7c*/
++		}
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII ||
++		   bp->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) {
++		if (speed == SPEED_1000) {
++			gem_writel(bp, MII_SELECT, 0x1); /*0x1c18*/
++			gem_writel(bp, SEL_MII_ON_RGMII, 0x0); /*0x1c1c*/
++			gem_writel(bp, TX_CLK_SEL0, 0x0); /*0x1c20*/
++			gem_writel(bp, TX_CLK_SEL1, 0x1); /*0x1c24*/
++			gem_writel(bp, TX_CLK_SEL2, 0x0); /*0x1c28*/
++			gem_writel(bp, TX_CLK_SEL3, 0x0); /*0x1c2c*/
++			gem_writel(bp, RX_CLK_SEL0, 0x0); /*0x1c30*/
++			gem_writel(bp, RX_CLK_SEL1, 0x1); /*0x1c34*/
++			gem_writel(bp, CLK_250M_DIV10_DIV100_SEL, 0x0); /*0x1c38*/
++			gem_writel(bp, RX_CLK_SEL5, 0x1); /*0x1c48*/
++			gem_writel(bp, RGMII_TX_CLK_SEL0, 0x1); /*0x1c80*/
++			gem_writel(bp, RGMII_TX_CLK_SEL1, 0x0); /*0x1c84*/
++		} else if (speed == SPEED_100) {
++			gem_writel(bp, MII_SELECT, 0x1); /*0x1c18*/
++			gem_writel(bp, SEL_MII_ON_RGMII, 0x0); /*0x1c1c*/
++			gem_writel(bp, TX_CLK_SEL0, 0x0); /*0x1c20*/
++			gem_writel(bp, TX_CLK_SEL1, 0x1); /*0x1c24*/
++			gem_writel(bp, TX_CLK_SEL2, 0x0); /*0x1c28*/
++			gem_writel(bp, TX_CLK_SEL3, 0x0); /*0x1c2c*/
++			gem_writel(bp, RX_CLK_SEL0, 0x0); /*0x1c30*/
++			gem_writel(bp, RX_CLK_SEL1, 0x1); /*0x1c34*/
++			gem_writel(bp, CLK_250M_DIV10_DIV100_SEL, 0x0); /*0x1c38*/
++			gem_writel(bp, RX_CLK_SEL5, 0x1); /*0x1c48*/
++			gem_writel(bp, RGMII_TX_CLK_SEL0, 0x0); /*0x1c80*/
++			gem_writel(bp, RGMII_TX_CLK_SEL1, 0x0); /*0x1c84*/
++		} else {
++			gem_writel(bp, MII_SELECT, 0x1); /*0x1c18*/
++			gem_writel(bp, SEL_MII_ON_RGMII, 0x0); /*0x1c1c*/
++			gem_writel(bp, TX_CLK_SEL0, 0x0); /*0x1c20*/
++			gem_writel(bp, TX_CLK_SEL1, 0x1); /*0x1c24*/
++			gem_writel(bp, TX_CLK_SEL2, 0x0); /*0x1c28*/
++			gem_writel(bp, TX_CLK_SEL3, 0x0); /*0x1c2c*/
++			gem_writel(bp, RX_CLK_SEL0, 0x0); /*0x1c30*/
++			gem_writel(bp, RX_CLK_SEL1, 0x1); /*0x1c34*/
++			gem_writel(bp, CLK_250M_DIV10_DIV100_SEL, 0x1); /*0x1c38*/
++			gem_writel(bp, RX_CLK_SEL5, 0x1); /*0x1c48*/
++			gem_writel(bp, RGMII_TX_CLK_SEL0, 0x0); /*0x1c80*/
++			gem_writel(bp, RGMII_TX_CLK_SEL1, 0x0); /*0x1c84*/
++		}
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) {
++		gem_writel(bp, RX_CLK_SEL5, 0x1); /*0x1c48*/
++	}
++
++	if (speed == SPEED_100)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_100M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_1000)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_1000M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_2500)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_2500M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_5000)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_5000M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_10000)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++}
++
++static void phytium_gem2p0_sel_clk(struct macb *bp, int speed)
++{
++	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
++		if (speed == SPEED_100 || speed == SPEED_10) {
++			gem_writel(bp, SRC_SEL_LN, 0x1); /*0x1c04*/
++			gem_writel(bp, DIV_SEL1_LN, 0x1); /*0x1c0c*/
++		}
++	}
++
++	if (speed == SPEED_100 || speed == SPEED_10)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_100M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_1000)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_1000M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_2500)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_2500M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++}
++
++static void phytium_gem3p0_sel_clk(struct macb *bp, int speed)
++{
++	if (speed == SPEED_100 || speed == SPEED_10)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_100M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_1000)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_1000M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++	else if (speed == SPEED_2500)
++		gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_2500M,
++							gem_readl(bp, HS_MAC_CONFIG)));
++}
++
+ static void macb_mac_link_up(struct phylink_config *config,
+ 			     struct phy_device *phy,
+ 			     unsigned int mode, phy_interface_t interface,
+@@ -624,9 +960,13 @@ static void macb_mac_link_up(struct phyl
+ 	unsigned long flags;
+ 	unsigned int q;
+ 	u32 ctrl;
++	int err;
+ 
+ 	spin_lock_irqsave(&bp->lock, flags);
+ 
++	if (bp->caps & MACB_CAPS_SEL_CLK)
++		bp->sel_clk_hw(bp, speed);
++
+ 	ctrl = macb_or_gem_readl(bp, NCFGR);
+ 
+ 	ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
+@@ -642,7 +982,7 @@ static void macb_mac_link_up(struct phyl
+ 		if (macb_is_gem(bp)) {
+ 			ctrl &= ~GEM_BIT(GBE);
+ 
+-			if (speed == SPEED_1000)
++			if (speed == SPEED_1000 || speed == SPEED_2500)
+ 				ctrl |= GEM_BIT(GBE);
+ 		}
+ 
+@@ -664,18 +1004,71 @@ static void macb_mac_link_up(struct phyl
+ 
+ 	macb_or_gem_writel(bp, NCFGR, ctrl);
+ 
++	if (speed == SPEED_2500) {
++		u32 network_ctrl;
++
++		network_ctrl = macb_readl(bp, NCR);
++		network_ctrl |= MACB_BIT(2PT5G);
++		macb_writel(bp, NCR, network_ctrl);
++	}
++
++	if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
++	    bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
++		if (speed == SPEED_5000)
++			gem_writel(bp, HS_MAC_CONFIG,
++				   GEM_BFINS(HS_MAC_SPEED, HS_SPEED_5000M,
++					     gem_readl(bp, HS_MAC_CONFIG)));
++		else
++			gem_writel(bp, HS_MAC_CONFIG,
++				   GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
++					     gem_readl(bp, HS_MAC_CONFIG)));
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_5GBASER)
++		gem_writel(bp, HS_MAC_CONFIG,
++			   GEM_BFINS(HS_MAC_SPEED, HS_SPEED_5000M,
++				     gem_readl(bp, HS_MAC_CONFIG)));
++
+ 	spin_unlock_irqrestore(&bp->lock, flags);
+ 
+ 	/* Enable Rx and Tx */
+ 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
+ 
++	if (bp->use_ncsi) {
++		/* Start the NCSI device */
++		err = ncsi_start_dev(bp->ndev);
++		if (err) {
++			netdev_err(bp->dev, "Ncsi start dev failed (error %d)\n", err);
++			return;
++		}
++	}
++
+ 	netif_tx_wake_all_queues(ndev);
+ }
+ 
++static int macb_mac_prepare(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct net_device *ndev = to_net_dev(config->dev);
++	struct macb *bp = netdev_priv(ndev);
++
++	if (interface == PHY_INTERFACE_MODE_10GBASER ||
++	    interface == PHY_INTERFACE_MODE_5GBASER ||
++	    interface == PHY_INTERFACE_MODE_USXGMII)
++		bp->phylink_pcs.ops = &macb_phylink_usx_pcs_ops;
++	else if (interface == PHY_INTERFACE_MODE_SGMII ||
++		 interface == PHY_INTERFACE_MODE_2500BASEX)
++		bp->phylink_pcs.ops = &macb_phylink_pcs_ops;
++	else
++		bp->phylink_pcs.ops = NULL;
++
++	if (bp->phylink_pcs.ops)
++		phylink_set_pcs(bp->phylink, &bp->phylink_pcs);
++
++	return 0;
++}
++
+ static const struct phylink_mac_ops macb_phylink_ops = {
+ 	.validate = macb_validate,
+-	.mac_pcs_get_state = macb_mac_pcs_get_state,
+-	.mac_an_restart = macb_mac_an_restart,
++	.mac_prepare = macb_mac_prepare,
+ 	.mac_config = macb_mac_config,
+ 	.mac_link_down = macb_mac_link_down,
+ 	.mac_link_up = macb_mac_link_up,
+@@ -693,8 +1086,14 @@ static int macb_phylink_connect(struct m
+ 	struct device_node *dn = bp->pdev->dev.of_node;
+ 	struct net_device *dev = bp->dev;
+ 	struct phy_device *phydev;
++	struct macb_platform_data *pdata = dev_get_platdata(&bp->pdev->dev);
+ 	int ret;
+ 
++	if (pdata && pdata->phytium_macb_pdata.properties) {
++		phylink_start(bp->phylink);
++		return 0;
++	}
++
+ 	if (dn)
+ 		ret = phylink_of_phy_connect(bp->phylink, dn, 0);
+ 
+@@ -704,6 +1103,7 @@ static int macb_phylink_connect(struct m
+ 			netdev_err(dev, "no PHY found\n");
+ 			return -ENXIO;
+ 		}
++		phydev->force_mode = bp->force_phy_mode;
+ 
+ 		/* attach the mac to the phy */
+ 		ret = phylink_connect_phy(bp->phylink, phydev);
+@@ -719,6 +1119,29 @@ static int macb_phylink_connect(struct m
+ 	return 0;
+ }
+ 
++static void macb_get_pcs_fixed_state(struct phylink_config *config,
++				     struct phylink_link_state *state)
++{
++	struct net_device *ndev = to_net_dev(config->dev);
++	struct macb *bp = netdev_priv(ndev);
++
++	state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
++}
++
++static void macb_get_usx_pcs_fixed_state(struct phylink_config *config,
++					 struct phylink_link_state *state)
++{
++	u32 val;
++	struct net_device *ndev = to_net_dev(config->dev);
++	struct macb *bp = netdev_priv(ndev);
++
++	val = gem_readl(bp, USX_STATUS);
++	state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
++	val = gem_readl(bp, NCFGR);
++	if (val & GEM_BIT(PAE))
++		state->pause = MLO_PAUSE_RX;
++}
++
+ /* based on au1000_eth. c*/
+ static int macb_mii_probe(struct net_device *dev)
+ {
+@@ -727,8 +1150,19 @@ static int macb_mii_probe(struct net_dev
+ 	bp->phylink_config.dev = &dev->dev;
+ 	bp->phylink_config.type = PHYLINK_NETDEV;
+ 
++	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
++		bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
++		bp->phylink_config.poll_fixed_state = true;
++		bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
++			bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
++		bp->phylink_config.poll_fixed_state = true;
++		bp->phylink_config.get_fixed_state = macb_get_usx_pcs_fixed_state;
++	}
++
+ 	bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
+ 				     bp->phy_interface, &macb_phylink_ops);
++
+ 	if (IS_ERR(bp->phylink)) {
+ 		netdev_err(dev, "Could not create a phylink instance (%ld)\n",
+ 			   PTR_ERR(bp->phylink));
+@@ -2097,6 +2531,8 @@ static netdev_tx_t macb_start_xmit(struc
+ 	wmb();
+ 	skb_tx_timestamp(skb);
+ 
++	if (bp->caps & MACB_CAPS_TAILPTR)
++		queue_writel(queue, TAILADDR, BIT(31) | macb_tx_ring_wrap(bp, queue->tx_head));
+ 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
+ 
+ 	if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
+@@ -2294,6 +2730,9 @@ static void gem_init_rings(struct macb *
+ 		queue->tx_head = 0;
+ 		queue->tx_tail = 0;
+ 
++		if (bp->caps & MACB_CAPS_TAILPTR)
++			queue_writel(queue, TAILADDR, BIT(31) | queue->tx_head);
++
+ 		queue->rx_tail = 0;
+ 		queue->rx_prepared_head = 0;
+ 
+@@ -2463,6 +2902,45 @@ static void macb_configure_dma(struct ma
+ 	}
+ }
+ 
++static int phytium_mac_config(struct macb *bp)
++{
++	u32 old_ctrl, ctrl;
++	u32 old_ncr, ncr;
++
++	netdev_dbg(bp->dev, "phytium mac config");
++
++	ncr = macb_readl(bp, NCR);
++	old_ncr = ncr;
++	ctrl = macb_or_gem_readl(bp, NCFGR);
++	old_ctrl = ctrl;
++
++	ncr &= ~(GEM_BIT(ENABLE_HS_MAC) | MACB_BIT(2PT5G));
++	ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL) | MACB_BIT(SPD) | MACB_BIT(FD));
++	if (macb_is_gem(bp))
++		ctrl &= ~GEM_BIT(GBE);
++
++	if (bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
++		ctrl |= GEM_BIT(PCSSEL) | GEM_BIT(SGMIIEN);
++		ncr |= MACB_BIT(2PT5G);
++	} else if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
++		bp->phy_interface == PHY_INTERFACE_MODE_5GBASER) {
++		ctrl |= GEM_BIT(PCSSEL);
++		ncr |= GEM_BIT(ENABLE_HS_MAC);
++	}
++
++	if (bp->duplex)
++		ctrl |= MACB_BIT(FD);
++
++	/* Apply the new configuration, if any */
++	if (old_ctrl ^ ctrl)
++		macb_or_gem_writel(bp, NCFGR, ctrl);
++
++	if (old_ncr ^ ncr)
++		macb_or_gem_writel(bp, NCR, ncr);
++
++	return 0;
++}
++
+ static void macb_init_hw(struct macb *bp)
+ {
+ 	u32 config;
+@@ -2491,6 +2969,25 @@ static void macb_init_hw(struct macb *bp
+ 	if (bp->caps & MACB_CAPS_JUMBO)
+ 		bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
+ 
++	gem_writel(bp, AXI_PIPE, 0x1010);
++	if (bp->caps & MACB_CAPS_TAILPTR)
++		gem_writel(bp, TAIL_ENABLE, 0x80000001);
++
++	if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
++	    bp->phy_interface == PHY_INTERFACE_MODE_5GBASER ||
++	    bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
++		/* phytium need hwclock */
++		if (bp->caps & MACB_CAPS_SEL_CLK)
++			bp->sel_clk_hw(bp, bp->speed);
++		phytium_mac_config(bp);
++		if (bp->link)
++			macb_usx_pcs_link_up(&bp->phylink_pcs, 0,
++					     bp->phy_interface, bp->speed, bp->duplex);
++	} else {
++		bp->speed = SPEED_10;
++		bp->duplex = DUPLEX_HALF;
++	}
++
+ 	macb_configure_dma(bp);
+ }
+ 
+@@ -2615,7 +3112,10 @@ static void macb_set_rx_mode(struct net_
+ 
+ static int macb_open(struct net_device *dev)
+ {
+-	size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
++	/* adjust bufsz to be at least the size of a standard frame,
++	 * to fix rx error when set small size mtu.
++	 */
++	size_t bufsz = (dev->mtu < ETH_DATA_LEN ? ETH_DATA_LEN : dev->mtu) + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
+ 	struct macb *bp = netdev_priv(dev);
+ 	struct macb_queue *queue;
+ 	unsigned int q;
+@@ -3543,6 +4043,8 @@ static const struct net_device_ops macb_
+ #endif
+ 	.ndo_set_features	= macb_set_features,
+ 	.ndo_features_check	= macb_features_check,
++	.ndo_vlan_rx_add_vid	= ncsi_vlan_rx_add_vid,
++	.ndo_vlan_rx_kill_vid	= ncsi_vlan_rx_kill_vid,
+ };
+ 
+ /* Configure peripheral capabilities according to device tree
+@@ -3552,16 +4054,26 @@ static void macb_configure_caps(struct m
+ 				const struct macb_config *dt_conf)
+ {
+ 	u32 dcfg;
++	struct macb_platform_data *pdata;
+ 
+ 	if (dt_conf)
+ 		bp->caps = dt_conf->caps;
+ 
++	pdata = dev_get_platdata(&bp->pdev->dev);
++	if (pdata && pdata->phytium_macb_pdata.phytium_dev_type == PHYTIUM_DEV_3P0)
++		bp->caps |= pdata->phytium_macb_pdata.caps;
++
+ 	if (hw_is_gem(bp->regs, bp->native_io)) {
+ 		bp->caps |= MACB_CAPS_MACB_IS_GEM;
+ 
+ 		dcfg = gem_readl(bp, DCFG1);
+ 		if (GEM_BFEXT(IRQCOR, dcfg) == 0)
+ 			bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
++		if (GEM_BFEXT(NO_PCS, dcfg) == 0)
++			bp->caps |= MACB_CAPS_PCS;
++		dcfg = gem_readl(bp, DCFG12);
++		if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
++			bp->caps |= MACB_CAPS_HIGH_SPEED;
+ 		dcfg = gem_readl(bp, DCFG2);
+ 		if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
+ 			bp->caps |= MACB_CAPS_FIFO_MODE;
+@@ -3603,6 +4115,165 @@ static void macb_probe_queues(void __iom
+ 	*num_queues = hweight32(*queue_mask);
+ }
+ 
++#ifdef CONFIG_ACPI
++static int phytium_clk_acpi_init(struct platform_device *pdev, struct clk **pclk,
++				 struct clk **hclk, struct clk **tx_clk,
++				 struct clk **rx_clk, struct clk **tsu_clk)
++{
++	struct macb_platform_data *pdata;
++	int err;
++
++	pdata = dev_get_platdata(&pdev->dev);
++	if (pdata) {
++		*pclk = pdata->pclk;
++		*hclk = pdata->hclk;
++		*tx_clk = pdata->phytium_macb_pdata.txclk;
++		*rx_clk = pdata->phytium_macb_pdata.rxclk;
++		*tsu_clk = pdata->phytium_macb_pdata.tsu_clk;
++	} else {
++		*pclk = NULL;
++		*hclk = NULL;
++		*tx_clk = NULL;
++		*rx_clk = NULL;
++		*tsu_clk = NULL;
++	}
++
++	err = clk_prepare_enable(*pclk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
++		return err;
++	}
++
++	err = clk_prepare_enable(*hclk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
++		goto err_disable_pclk;
++	}
++
++	err = clk_prepare_enable(*tx_clk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
++		goto err_disable_hclk;
++	}
++
++	err = clk_prepare_enable(*rx_clk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
++		goto err_disable_txclk;
++	}
++
++	err = clk_prepare_enable(*tsu_clk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
++		goto err_disable_rxclk;
++	}
++
++	return 0;
++
++err_disable_rxclk:
++	clk_disable_unprepare(*rx_clk);
++
++err_disable_txclk:
++	clk_disable_unprepare(*tx_clk);
++
++err_disable_hclk:
++	clk_disable_unprepare(*hclk);
++
++err_disable_pclk:
++	clk_disable_unprepare(*pclk);
++
++	return err;
++}
++#endif
++
++static int phytium_clk_init(struct platform_device *pdev, struct clk **pclk,
++			    struct clk **hclk, struct clk **tx_clk,
++			    struct clk **rx_clk, struct clk **tsu_clk)
++{
++	struct macb_platform_data *pdata;
++	int err;
++
++	pdata = dev_get_platdata(&pdev->dev);
++	if (pdata) {
++		*pclk = pdata->pclk;
++		*hclk = pdata->hclk;
++		*tx_clk = pdata->phytium_macb_pdata.txclk;
++		*rx_clk = pdata->phytium_macb_pdata.rxclk;
++		*tsu_clk = pdata->phytium_macb_pdata.tsu_clk;
++	} else {
++		*pclk = devm_clk_get(&pdev->dev, "pclk");
++		*hclk = devm_clk_get(&pdev->dev, "hclk");
++		*tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
++		*rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
++		*tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
++	}
++
++	if (IS_ERR_OR_NULL(*pclk))
++		return dev_err_probe(&pdev->dev,
++				     IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
++				     "failed to get pclk\n");
++
++	if (IS_ERR_OR_NULL(*hclk))
++		return dev_err_probe(&pdev->dev,
++				     IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
++				     "failed to get hclk\n");
++
++	if (IS_ERR(*tx_clk))
++		return PTR_ERR(*tx_clk);
++
++	if (IS_ERR(*rx_clk))
++		return PTR_ERR(*rx_clk);
++
++	if (IS_ERR(*tsu_clk))
++		return PTR_ERR(*tsu_clk);
++
++	err = clk_prepare_enable(*pclk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
++		return err;
++	}
++
++	err = clk_prepare_enable(*hclk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
++		goto err_disable_pclk;
++	}
++
++	err = clk_prepare_enable(*tx_clk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
++		goto err_disable_hclk;
++	}
++
++	err = clk_prepare_enable(*rx_clk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
++		goto err_disable_txclk;
++	}
++
++	err = clk_prepare_enable(*tsu_clk);
++	if (err) {
++		dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
++		goto err_disable_rxclk;
++	}
++
++	return 0;
++
++err_disable_rxclk:
++	clk_disable_unprepare(*rx_clk);
++
++err_disable_txclk:
++	clk_disable_unprepare(*tx_clk);
++
++err_disable_hclk:
++	clk_disable_unprepare(*hclk);
++
++err_disable_pclk:
++	clk_disable_unprepare(*pclk);
++
++	return err;
++}
++
+ static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
+ 			 struct clk **hclk, struct clk **tx_clk,
+ 			 struct clk **rx_clk, struct clk **tsu_clk)
+@@ -3696,6 +4367,225 @@ err_disable_pclk:
+ 	return err;
+ }
+ 
++static irqreturn_t phytium_macb_interrupt_intx(int irq, void *dev_id)
++{
++	struct macb *bp = dev_id;
++	u32 irq_mask;
++	int i;
++
++	irq_mask = gem_readl(bp, INTX_IRQ_MASK);
++	if (unlikely(!irq_mask))
++		return IRQ_NONE;
++
++	gem_writel(bp, INTX_IRQ_MASK, irq_mask);
++
++	for (i = 0; i < bp->num_queues; i++) {
++		if ((irq_mask & bp->queue_mask) & BIT(i))
++			macb_interrupt(irq, &bp->queues[i]);
++	}
++	return IRQ_HANDLED;
++}
++
++static int phytium_queue_request_irq(struct platform_device *pdev, unsigned int q)
++{
++	int err;
++	struct macb_queue *queue;
++	struct macb_platform_data *pdata = dev_get_platdata(&pdev->dev);
++	struct net_device *dev = platform_get_drvdata(pdev);
++	struct macb *bp = netdev_priv(dev);
++
++	queue = &bp->queues[q];
++	if (q == 0 && pdata->phytium_macb_pdata.irq_type == IRQ_TYPE_INTX) {
++		dev->irq = pdata->phytium_macb_pdata.irq[q];
++		err = devm_request_irq(&pdev->dev, dev->irq, phytium_macb_interrupt_intx,
++				       IRQF_SHARED, dev->name, bp);
++		if (err) {
++			dev_err(&pdev->dev,
++				"Unable to request dev %d (error %d)\n",
++				dev->irq, err);
++		}
++	}
++
++	if (pdata->phytium_macb_pdata.irq_type == IRQ_TYPE_MSI) {
++		queue->irq = pdata->phytium_macb_pdata.irq[q];
++		err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
++				       0, dev->name, queue);
++		if (err) {
++			dev_err(&pdev->dev,
++				"Unable to request IRQ %d (error %d)\n",
++				queue->irq, err);
++		}
++	}
++
++	return err;
++}
++
++static int phytium_init(struct platform_device *pdev)
++{
++	struct net_device *dev = platform_get_drvdata(pdev);
++	unsigned int hw_q, q;
++	struct macb *bp = netdev_priv(dev);
++	struct macb_queue *queue;
++	int err;
++	u32 val, reg;
++	struct macb_platform_data *pdata;
++
++	bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
++	bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
++
++	pdata = dev_get_platdata(&pdev->dev);
++
++	/* set the queue register mapping once for all: queue0 has a special
++	 * register mapping but we don't want to test the queue index then
++	 * compute the corresponding register offset at run time.
++	 */
++	for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
++		if (!(bp->queue_mask & (1 << hw_q)))
++			continue;
++
++		queue = &bp->queues[q];
++		queue->bp = bp;
++		netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
++		if (hw_q) {
++			queue->ISR  = GEM_ISR(hw_q - 1);
++			queue->IER  = GEM_IER(hw_q - 1);
++			queue->IDR  = GEM_IDR(hw_q - 1);
++			queue->IMR  = GEM_IMR(hw_q - 1);
++			queue->TBQP = GEM_TBQP(hw_q - 1);
++			queue->RBQP = GEM_RBQP(hw_q - 1);
++			queue->RBQS = GEM_RBQS(hw_q - 1);
++#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
++			if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
++				queue->TBQPH = GEM_TBQPH(hw_q - 1);
++				queue->RBQPH = GEM_RBQPH(hw_q - 1);
++			}
++#endif
++		} else {
++			/* queue0 uses legacy registers */
++			queue->ISR  = MACB_ISR;
++			queue->IER  = MACB_IER;
++			queue->IDR  = MACB_IDR;
++			queue->IMR  = MACB_IMR;
++			queue->TBQP = MACB_TBQP;
++			queue->RBQP = MACB_RBQP;
++#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
++			if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
++				queue->TBQPH = MACB_TBQPH;
++				queue->RBQPH = MACB_RBQPH;
++			}
++#endif
++		}
++
++		if (bp->caps & MACB_CAPS_TAILPTR)
++			queue->TAILADDR = GEM_TAIL(hw_q);
++		/* get irq: here we use the linux queue index, not the hardware
++		 * queue index. the queue irq definitions in the device tree
++		 * must remove the optional gaps that could exist in the
++		 * hardware queue mask.
++		 */
++		if (pdata && pdata->phytium_macb_pdata.phytium_dev_type == PHYTIUM_DEV_3P0) {
++			err = phytium_queue_request_irq(pdev, q);
++		} else {
++			queue->irq = platform_get_irq(pdev, q);
++			err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
++					       IRQF_SHARED, dev->name, queue);
++			if (err) {
++				dev_err(&pdev->dev,
++					"Unable to request IRQ %d (error %d)\n",
++					queue->irq, err);
++				return err;
++			}
++		}
++
++		INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
++		q++;
++	}
++
++	dev->netdev_ops = &macb_netdev_ops;
++
++	/* setup appropriated routines according to adapter type */
++	if (macb_is_gem(bp)) {
++		bp->max_tx_length = GEM_MAX_TX_LEN;
++		bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
++		bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
++		bp->macbgem_ops.mog_init_rings = gem_init_rings;
++		bp->macbgem_ops.mog_rx = gem_rx;
++		dev->ethtool_ops = &gem_ethtool_ops;
++	} else {
++		bp->max_tx_length = MACB_MAX_TX_LEN;
++		bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
++		bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
++		bp->macbgem_ops.mog_init_rings = macb_init_rings;
++		bp->macbgem_ops.mog_rx = macb_rx;
++		dev->ethtool_ops = &macb_ethtool_ops;
++	}
++
++	/* Set features */
++	dev->hw_features = NETIF_F_SG;
++
++	/* Check LSO capability */
++	if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
++		dev->hw_features |= MACB_NETIF_LSO;
++
++	/* Checksum offload is only available on gem with packet buffer */
++	if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
++		dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
++	if (bp->caps & MACB_CAPS_SG_DISABLED)
++		dev->hw_features &= ~NETIF_F_SG;
++	dev->features = dev->hw_features;
++
++	/* Check RX Flow Filters support.
++	 * Max Rx flows set by availability of screeners & compare regs:
++	 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
++	 */
++	reg = gem_readl(bp, DCFG8);
++	bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
++			     GEM_BFEXT(T2SCR, reg));
++	INIT_LIST_HEAD(&bp->rx_fs_list.list);
++	if (bp->max_tuples > 0) {
++		/* also needs one ethtype match to check IPv4 */
++		if (GEM_BFEXT(SCR2ETH, reg) > 0) {
++			/* program this reg now */
++			reg = 0;
++			reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
++			gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
++			/* Filtering is supported in hw but don't enable it in kernel now */
++			dev->hw_features |= NETIF_F_NTUPLE;
++			/* init Rx flow definitions */
++			bp->rx_fs_list.count = 0;
++			spin_lock_init(&bp->rx_fs_lock);
++		} else {
++			bp->max_tuples = 0;
++		}
++	}
++
++	if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
++		val = 0;
++		if (phy_interface_mode_is_rgmii(bp->phy_interface))
++			val = GEM_BIT(RGMII);
++		else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
++			 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
++			val = MACB_BIT(RMII);
++		else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
++			val = MACB_BIT(MII);
++
++		if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
++			val |= MACB_BIT(CLKEN);
++
++		macb_or_gem_writel(bp, USRIO, val);
++	}
++
++	/* Set MII management clock divider */
++	val = macb_mdc_clk_div(bp);
++	val |= macb_dbw(bp);
++	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII ||
++	    bp->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
++		val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
++	macb_writel(bp, NCFGR, val);
++
++	return 0;
++}
++
+ static int macb_init(struct platform_device *pdev)
+ {
+ 	struct net_device *dev = platform_get_drvdata(pdev);
+@@ -4436,6 +5326,75 @@ static const struct macb_config zynq_con
+ 	.init = macb_init,
+ };
+ 
++static const struct macb_config phytium_gem1p0_config = {
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_SEL_CLK,
++	.dma_burst_length = 16,
++	.clk_init = phytium_clk_init,
++	.init = phytium_init,
++	.jumbo_max_len = 16360,
++	.sel_clk_hw = phytium_gem1p0_sel_clk,
++};
++
++static const struct macb_config phytium_gem2p0_config = {
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_SEL_CLK,
++	.dma_burst_length = 16,
++	.clk_init = macb_clk_init,
++	.init = macb_init,
++	.jumbo_max_len = 10240,
++	.sel_clk_hw = phytium_gem2p0_sel_clk,
++};
++
++static const struct macb_config phytium_gem3p0_config = {
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_SEL_CLK |
++			MACB_CAPS_TAILPTR,
++	.dma_burst_length = 16,
++	.clk_init = phytium_clk_init,
++	.init = phytium_init,
++	.jumbo_max_len = 10240,
++	.sel_clk_hw = phytium_gem3p0_sel_clk,
++};
++
++#ifdef CONFIG_ACPI
++static const struct macb_config phytium_gem1p0_acpi_config = {
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_SEL_CLK,
++	.dma_burst_length = 16,
++	.clk_init = phytium_clk_acpi_init,
++	.init = phytium_init,
++	.jumbo_max_len = 10240,
++	.sel_clk_hw = phytium_gem1p0_sel_clk,
++};
++
++static const struct macb_config phytium_gem3p0_acpi_config = {
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_SEL_CLK |
++			MACB_CAPS_TAILPTR,
++	.dma_burst_length = 16,
++	.clk_init = phytium_clk_acpi_init,
++	.init = phytium_init,
++	.jumbo_max_len = 10240,
++	.sel_clk_hw = phytium_gem3p0_sel_clk,
++};
++#endif
++
+ static const struct of_device_id macb_dt_ids[] = {
+ 	{ .compatible = "cdns,at32ap7000-macb" },
+ 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
+@@ -4453,11 +5412,26 @@ static const struct of_device_id macb_dt
+ 	{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
+ 	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
+ 	{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
++	{ .compatible = "cdns,phytium-gem-1.0", .data = &phytium_gem1p0_config },
++	{ .compatible = "cdns,phytium-gem-2.0", .data = &phytium_gem2p0_config },
++	{ .compatible = "cdns,phytium-gem-3.0", .data = &phytium_gem3p0_config },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, macb_dt_ids);
+ #endif /* CONFIG_OF */
+ 
++#ifdef CONFIG_ACPI
++static const struct acpi_device_id macb_acpi_ids[] = {
++	{ .id = "PHYT0036", .driver_data = (kernel_ulong_t)&phytium_gem1p0_acpi_config },
++	{ .id = "PHYT0046", .driver_data = (kernel_ulong_t)&phytium_gem3p0_acpi_config },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(acpi, macb_acpi_ids);
++#else
++#define macb_acpi_ids NULL
++#endif
++
+ static const struct macb_config default_gem_config = {
+ 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
+ 			MACB_CAPS_JUMBO |
+@@ -4468,6 +5442,32 @@ static const struct macb_config default_
+ 	.jumbo_max_len = 10240,
+ };
+ 
++static void gem_ncsi_handler(struct ncsi_dev *nd)
++{
++	if (unlikely(nd->state != ncsi_dev_state_functional))
++		return;
++
++	netdev_dbg(nd->dev, "NCSI interface %s\n",
++		   nd->link_up ? "up" : "down");
++}
++
++static int macb_get_phy_mode(struct platform_device *pdev)
++{
++	const char *pm;
++	int err, i;
++
++	err = device_property_read_string(&pdev->dev, "phy-mode", &pm);
++	if (err < 0)
++		return err;
++
++	for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) {
++		if (!strcasecmp(pm, phy_modes(i)))
++			return i;
++	}
++
++	return -ENODEV;
++}
++
+ static int macb_probe(struct platform_device *pdev)
+ {
+ 	const struct macb_config *macb_config = &default_gem_config;
+@@ -4476,17 +5476,26 @@ static int macb_probe(struct platform_de
+ 			struct clk **) = macb_config->clk_init;
+ 	int (*init)(struct platform_device *) = macb_config->init;
+ 	struct device_node *np = pdev->dev.of_node;
+-	struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
++	struct clk *pclk = NULL, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
+ 	struct clk *tsu_clk = NULL;
+ 	unsigned int queue_mask, num_queues;
++	struct macb_platform_data *pdata;
+ 	bool native_io;
+-	phy_interface_t interface;
+ 	struct net_device *dev;
+ 	struct resource *regs;
+ 	void __iomem *mem;
+ 	struct macb *bp;
+ 	int err, val;
+ 
++	pdata = dev_get_platdata(&pdev->dev);
++	if (pdata) {
++		if (pdata->phytium_macb_pdata.phytium_dev_type == PHYTIUM_DEV_3P0) {
++			macb_config = &phytium_gem3p0_config;
++			clk_init = macb_config->clk_init;
++			init = macb_config->init;
++		}
++	}
++
+ 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	mem = devm_ioremap_resource(&pdev->dev, regs);
+ 	if (IS_ERR(mem))
+@@ -4501,6 +5510,15 @@ static int macb_probe(struct platform_de
+ 			clk_init = macb_config->clk_init;
+ 			init = macb_config->init;
+ 		}
++	} else if (has_acpi_companion(&pdev->dev)) {
++		const struct acpi_device_id *match;
++
++		match = acpi_match_device(macb_acpi_ids, &pdev->dev);
++		if (match && match->driver_data) {
++			macb_config = (void *)match->driver_data;
++			clk_init = macb_config->clk_init;
++			init = macb_config->init;
++		}
+ 	}
+ 
+ 	err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
+@@ -4549,8 +5567,11 @@ static int macb_probe(struct platform_de
+ 	if (macb_config)
+ 		bp->jumbo_max_len = macb_config->jumbo_max_len;
+ 
++	if (macb_config)
++		bp->sel_clk_hw = macb_config->sel_clk_hw;
++
+ 	bp->wol = 0;
+-	if (of_get_property(np, "magic-packet", NULL))
++	if (device_property_read_bool(&pdev->dev, "magic-packet"))
+ 		bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
+ 	device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
+ 
+@@ -4602,22 +5623,47 @@ static int macb_probe(struct platform_de
+ 	else if (err)
+ 		macb_get_hwaddr(bp);
+ 
+-	err = of_get_phy_mode(np, &interface);
+-	if (err)
+-		/* not found in DT, MII by default */
+-		bp->phy_interface = PHY_INTERFACE_MODE_MII;
+-	else
+-		bp->phy_interface = interface;
++	err = macb_get_phy_mode(pdev);
++	if (err < 0) {
++		if (pdata && pdata->phytium_macb_pdata.phytium_dev_type == PHYTIUM_DEV_3P0)
++			bp->phy_interface = pdata->phytium_macb_pdata.phy_interface;
++		else
++			bp->phy_interface = PHY_INTERFACE_MODE_MII;
++	} else {
++		bp->phy_interface = err;
++	}
++
++	bp->link = 0;
++	bp->duplex = DUPLEX_UNKNOWN;
++	bp->speed = SPEED_UNKNOWN;
+ 
+ 	/* IP specific init */
+ 	err = init(pdev);
+ 	if (err)
+ 		goto err_out_free_netdev;
+ 
++	if (device_property_read_bool(&pdev->dev, "force-phy-mode")) {
++		bp->force_phy_mode = 1;
++	}
++
+ 	err = macb_mii_init(bp);
+ 	if (err)
+ 		goto err_out_free_netdev;
+ 
++	if (device_property_read_bool(&pdev->dev, "use-ncsi")) {
++		if (!IS_ENABLED(CONFIG_NET_NCSI)) {
++			dev_err(&pdev->dev, "NCSI stack not enabled\n");
++			goto err_out_free_netdev;
++		}
++		dev_notice(&pdev->dev, "Using NCSI interface\n");
++		bp->use_ncsi = 1;
++		bp->ndev = ncsi_register_dev(dev, gem_ncsi_handler);
++		if (!bp->ndev)
++			goto err_out_free_netdev;
++	} else {
++		bp->use_ncsi = 0;
++	}
++
+ 	netif_carrier_off(dev);
+ 
+ 	err = register_netdev(dev);
+@@ -4661,6 +5707,7 @@ static int macb_remove(struct platform_d
+ {
+ 	struct net_device *dev;
+ 	struct macb *bp;
++	struct macb_platform_data *pdata = dev_get_platdata(&pdev->dev);
+ 
+ 	dev = platform_get_drvdata(pdev);
+ 
+@@ -4669,16 +5716,21 @@ static int macb_remove(struct platform_d
+ 		mdiobus_unregister(bp->mii_bus);
+ 		mdiobus_free(bp->mii_bus);
+ 
++		if (bp->ndev)
++			ncsi_unregister_dev(bp->ndev);
+ 		unregister_netdev(dev);
+ 		tasklet_kill(&bp->hresp_err_tasklet);
+ 		pm_runtime_disable(&pdev->dev);
+ 		pm_runtime_dont_use_autosuspend(&pdev->dev);
+ 		if (!pm_runtime_suspended(&pdev->dev)) {
+-			clk_disable_unprepare(bp->tx_clk);
+-			clk_disable_unprepare(bp->hclk);
+-			clk_disable_unprepare(bp->pclk);
+-			clk_disable_unprepare(bp->rx_clk);
+-			clk_disable_unprepare(bp->tsu_clk);
++			if (!pdata) {
++				clk_disable_unprepare(bp->tx_clk);
++				clk_disable_unprepare(bp->hclk);
++				clk_disable_unprepare(bp->pclk);
++				clk_disable_unprepare(bp->rx_clk);
++				clk_disable_unprepare(bp->tsu_clk);
++			}
++
+ 			pm_runtime_set_suspended(&pdev->dev);
+ 		}
+ 		phylink_destroy(bp->phylink);
+@@ -4895,6 +5947,7 @@ static struct platform_driver macb_drive
+ 	.driver		= {
+ 		.name		= "macb",
+ 		.of_match_table	= of_match_ptr(macb_dt_ids),
++		.acpi_match_table = ACPI_PTR(macb_acpi_ids),
+ 		.pm	= &macb_pm_ops,
+ 	},
+ };
+--- a/drivers/net/ethernet/cadence/macb_pci.c
++++ b/drivers/net/ethernet/cadence/macb_pci.c
+@@ -21,17 +21,166 @@
+ 
+ #define CDNS_VENDOR_ID 0x17cd
+ #define CDNS_DEVICE_ID 0xe007
++#define PCI_DEVICE_ID_GMAC_3P0 0xdc3b
++#define PCI_SUBDEVICE_ID_SGMII				0x1000
++#define PCI_SUBDEVICE_ID_1000BASEX			0x1001
++#define PCI_SUBDEVICE_ID_USXGMII			0x1004
++#define PCI_SUBDEVICE_ID_10GBASER			0x1005
+ 
+ #define GEM_PCLK_RATE 50000000
+ #define GEM_HCLK_RATE 50000000
++#define GEM_TXCLK_RATE 25000000
++#define GEM_RXCLK_RATE 25000000
++#define GEM_TSUCLK_RATE 300000000
++
++static const u32 fixedlink[][5] = {
++	{0, 1, 1000, 1, 0},
++	{0, 1, 2500, 1, 0},
++	{0, 1, 5000, 1, 0},
++	{0, 1, 10000, 1, 0},
++};
++
++static const struct property_entry fl_properties[][2] = {
++	{PROPERTY_ENTRY_U32_ARRAY("fixed-link", fixedlink[0]), {}},
++	{PROPERTY_ENTRY_U32_ARRAY("fixed-link", fixedlink[1]), {}},
++	{PROPERTY_ENTRY_U32_ARRAY("fixed-link", fixedlink[2]), {}},
++	{PROPERTY_ENTRY_U32_ARRAY("fixed-link", fixedlink[3]), {}},
++};
++
++static const struct phytium_platform_pdata phytium_sgmii_pdata = {
++	.phytium_dev_type = PHYTIUM_DEV_3P0,
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_USRIO_DISABLED |
++			MACB_CAPS_TAILPTR,
++	.phy_interface = PHY_INTERFACE_MODE_SGMII,
++};
++
++static const struct phytium_platform_pdata phytium_1000basex_pdata = {
++	.phytium_dev_type = PHYTIUM_DEV_3P0,
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_USRIO_DISABLED |
++			MACB_CAPS_TAILPTR,
++	.phy_interface = PHY_INTERFACE_MODE_SGMII,
++	.properties = fl_properties[0],
++};
++
++static const struct phytium_platform_pdata phytium_usxgmii_pdata = {
++	.phytium_dev_type = PHYTIUM_DEV_3P0,
++	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
++			MACB_CAPS_JUMBO |
++			MACB_CAPS_GEM_HAS_PTP |
++			MACB_CAPS_BD_RD_PREFETCH |
++			MACB_CAPS_USRIO_DISABLED |
++			MACB_CAPS_TAILPTR,
++	.phy_interface = PHY_INTERFACE_MODE_USXGMII,
++	.properties = fl_properties[3],
++};
++
++static int phytium_macb_pci_init(struct pci_dev *pdev, struct macb_platform_data *plat_data,
++				 struct platform_device_info *plat_info,
++				 struct phytium_platform_pdata *phytium_data)
++{
++	int i;
++	int err;
++	char clkname[20];
++
++	err = pci_alloc_irq_vectors(pdev, 4, 4, PCI_IRQ_MSI);
++	if (err < 0) {
++		dev_err(&pdev->dev, "err=%d, fialed to allocate MSI entry", err);
++		plat_data->phytium_macb_pdata.irq_type = IRQ_TYPE_INTX;
++		plat_data->phytium_macb_pdata.irq[0] = pdev->irq;
++
++	} else {
++		plat_data->phytium_macb_pdata.irq_type = IRQ_TYPE_MSI;
++		for (i = 0; i < 4; i++)
++			plat_data->phytium_macb_pdata.irq[i] = pci_irq_vector(pdev, i);
++	}
++
++	plat_data->phytium_macb_pdata.phytium_dev_type = phytium_data->phytium_dev_type;
++	plat_data->phytium_macb_pdata.caps = phytium_data->caps;
++	plat_data->phytium_macb_pdata.phy_interface = phytium_data->phy_interface;
++	if (phytium_data && phytium_data->properties) {
++		plat_info->fwnode = NULL;
++		plat_info->properties = phytium_data->properties;
++		plat_data->phytium_macb_pdata.properties = phytium_data->properties;
++	}
++
++	snprintf(clkname, 20, "txclk:%02x", plat_info->id);
++	plat_data->phytium_macb_pdata.txclk =
++		clk_register_fixed_rate(&pdev->dev, clkname, NULL, 0, GEM_TXCLK_RATE);
++	if (IS_ERR(plat_data->phytium_macb_pdata.txclk)) {
++		err = PTR_ERR(plat_data->phytium_macb_pdata.txclk);
++		goto err_txclk_register;
++	}
++
++	snprintf(clkname, 20, "rxclk:%02x", plat_info->id);
++	plat_data->phytium_macb_pdata.rxclk =
++		clk_register_fixed_rate(&pdev->dev, clkname, NULL, 0, GEM_RXCLK_RATE);
++	if (IS_ERR(plat_data->phytium_macb_pdata.rxclk)) {
++		err = PTR_ERR(plat_data->phytium_macb_pdata.rxclk);
++		goto err_rxclk_register;
++	}
++
++	snprintf(clkname, 20, "tsuclk:%02x", plat_info->id);
++	plat_data->phytium_macb_pdata.tsu_clk =
++		clk_register_fixed_rate(&pdev->dev, clkname, NULL, 0, GEM_TSUCLK_RATE);
++	if (IS_ERR(plat_data->phytium_macb_pdata.tsu_clk)) {
++		err = PTR_ERR(plat_data->phytium_macb_pdata.tsu_clk);
++		goto err_tsuclk_register;
++	}
++
++	return 0;
++
++err_tsuclk_register:
++	clk_unregister(plat_data->phytium_macb_pdata.rxclk);
++
++err_rxclk_register:
++	clk_unregister(plat_data->phytium_macb_pdata.txclk);
++
++err_txclk_register:
++
++	return err;
++}
++
++static void phytium_macb_pci_uninit(struct pci_dev *pdev)
++{
++	struct platform_device *plat_dev = pci_get_drvdata(pdev);
++	struct macb_platform_data *plat_data = dev_get_platdata(&plat_dev->dev);
++
++	plat_dev->dev.dma_ops = NULL;
++	plat_dev->dev.iommu = NULL;
++	plat_dev->dev.iommu_group = NULL;
++	plat_dev->dev.dma_range_map = NULL;
++
++	clk_unregister(plat_data->phytium_macb_pdata.txclk);
++	clk_unregister(plat_data->phytium_macb_pdata.rxclk);
++	clk_unregister(plat_data->phytium_macb_pdata.tsu_clk);
++
++	if (plat_data->phytium_macb_pdata.properties) {
++		struct fwnode_handle *fw_node = dev_fwnode(&plat_dev->dev);
++
++		if (fw_node)
++			fwnode_remove_software_node(fw_node);
++		fw_node = NULL;
++	}
++}
+ 
+ static int macb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+ {
+ 	int err;
+ 	struct platform_device *plat_dev;
+ 	struct platform_device_info plat_info;
++	struct phytium_platform_pdata *phytium_data = NULL;
+ 	struct macb_platform_data plat_data;
+ 	struct resource res[2];
++	char pclk_name[20] = "pclk";
++	char hclk_name[20] = "hclk";
+ 
+ 	/* enable pci device */
+ 	err = pcim_enable_device(pdev);
+@@ -48,9 +197,6 @@ static int macb_probe(struct pci_dev *pd
+ 	res[0].end = pci_resource_end(pdev, 0);
+ 	res[0].name = PCI_DRIVER_NAME;
+ 	res[0].flags = IORESOURCE_MEM;
+-	res[1].start = pci_irq_vector(pdev, 0);
+-	res[1].name = PCI_DRIVER_NAME;
+-	res[1].flags = IORESOURCE_IRQ;
+ 
+ 	dev_info(&pdev->dev, "EMAC physical base addr: %pa\n",
+ 		 &res[0].start);
+@@ -58,32 +204,48 @@ static int macb_probe(struct pci_dev *pd
+ 	/* set up macb platform data */
+ 	memset(&plat_data, 0, sizeof(plat_data));
+ 
++	/* set up platform device info */
++	memset(&plat_info, 0, sizeof(plat_info));
++	plat_info.parent = &pdev->dev;
++	plat_info.fwnode = pdev->dev.fwnode;
++	plat_info.name = PLAT_DRIVER_NAME;
++	plat_info.id = pdev->devfn;
++	plat_info.res = res;
++	plat_info.num_res = ARRAY_SIZE(res);
++	plat_info.data = &plat_data;
++	plat_info.size_data = sizeof(plat_data);
++	plat_info.dma_mask = pdev->dma_mask;
++	if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM)
++		phytium_data = (struct phytium_platform_pdata *)id->driver_data;
++
+ 	/* initialize clocks */
+-	plat_data.pclk = clk_register_fixed_rate(&pdev->dev, "pclk", NULL, 0,
++	if (pdev->device == PCI_DEVICE_ID_GMAC_3P0) {
++		plat_info.id = (pdev->bus->number << 8) | pdev->devfn;
++		snprintf(pclk_name, 20, "pclk:%02x", plat_info.id);
++		snprintf(hclk_name, 20, "hclk:%02x", plat_info.id);
++	}
++	plat_data.pclk = clk_register_fixed_rate(&pdev->dev, pclk_name, NULL, 0,
+ 						 GEM_PCLK_RATE);
+ 	if (IS_ERR(plat_data.pclk)) {
+ 		err = PTR_ERR(plat_data.pclk);
+ 		goto err_pclk_register;
+ 	}
+ 
+-	plat_data.hclk = clk_register_fixed_rate(&pdev->dev, "hclk", NULL, 0,
++	plat_data.hclk = clk_register_fixed_rate(&pdev->dev, hclk_name, NULL, 0,
+ 						 GEM_HCLK_RATE);
+ 	if (IS_ERR(plat_data.hclk)) {
+ 		err = PTR_ERR(plat_data.hclk);
+ 		goto err_hclk_register;
+ 	}
+ 
+-	/* set up platform device info */
+-	memset(&plat_info, 0, sizeof(plat_info));
+-	plat_info.parent = &pdev->dev;
+-	plat_info.fwnode = pdev->dev.fwnode;
+-	plat_info.name = PLAT_DRIVER_NAME;
+-	plat_info.id = pdev->devfn;
+-	plat_info.res = res;
+-	plat_info.num_res = ARRAY_SIZE(res);
+-	plat_info.data = &plat_data;
+-	plat_info.size_data = sizeof(plat_data);
+-	plat_info.dma_mask = pdev->dma_mask;
++	if (pdev->device == PCI_DEVICE_ID_GMAC_3P0) {
++		if (phytium_macb_pci_init(pdev, &plat_data, &plat_info, phytium_data))
++			goto err_phytium_clk_register;
++	}
++
++	res[1].start = pci_irq_vector(pdev, 0);
++	res[1].name = PCI_DRIVER_NAME;
++	res[1].flags = IORESOURCE_IRQ;
+ 
+ 	/* register platform device */
+ 	plat_dev = platform_device_register_full(&plat_info);
+@@ -92,11 +254,21 @@ static int macb_probe(struct pci_dev *pd
+ 		goto err_plat_dev_register;
+ 	}
+ 
++	if (pdev->device == PCI_DEVICE_ID_GMAC_3P0) {
++		plat_dev->dev.dma_ops = (&pdev->dev)->dma_ops;
++		plat_dev->dev.iommu = (&pdev->dev)->iommu;
++		plat_dev->dev.iommu_group = (&pdev->dev)->iommu_group;
++		plat_dev->dev.dma_range_map = (&pdev->dev)->dma_range_map;
++	}
+ 	pci_set_drvdata(pdev, plat_dev);
+ 
+ 	return 0;
+ 
+ err_plat_dev_register:
++	if (pdev->device == PCI_DEVICE_ID_GMAC_3P0)
++		clk_unregister(plat_data.phytium_macb_pdata.tsu_clk);
++
++err_phytium_clk_register:
+ 	clk_unregister(plat_data.hclk);
+ 
+ err_hclk_register:
+@@ -113,11 +285,26 @@ static void macb_remove(struct pci_dev *
+ 
+ 	clk_unregister(plat_data->pclk);
+ 	clk_unregister(plat_data->hclk);
++
++	if (pdev->device == PCI_DEVICE_ID_GMAC_3P0)
++		phytium_macb_pci_uninit(pdev);
+ 	platform_device_unregister(plat_dev);
++
++	if (pdev->device == PCI_DEVICE_ID_GMAC_3P0)
++		pci_free_irq_vectors(pdev);
+ }
+ 
+ static const struct pci_device_id dev_id_table[] = {
+ 	{ PCI_DEVICE(CDNS_VENDOR_ID, CDNS_DEVICE_ID), },
++	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_PHYTIUM, PCI_DEVICE_ID_GMAC_3P0,
++				PCI_VENDOR_ID_PHYTIUM, PCI_SUBDEVICE_ID_SGMII),
++		.driver_data = (kernel_ulong_t)&phytium_sgmii_pdata},
++	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_PHYTIUM, PCI_DEVICE_ID_GMAC_3P0,
++				PCI_VENDOR_ID_PHYTIUM, PCI_SUBDEVICE_ID_1000BASEX),
++		.driver_data = (kernel_ulong_t)&phytium_1000basex_pdata},
++	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_PHYTIUM, PCI_DEVICE_ID_GMAC_3P0,
++				PCI_VENDOR_ID_PHYTIUM, PCI_SUBDEVICE_ID_USXGMII),
++		.driver_data = (kernel_ulong_t)&phytium_usxgmii_pdata},
+ 	{ 0, }
+ };
+ 
+--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
+@@ -117,6 +117,16 @@ config DWMAC_OXNAS
+ 	  This selects the Oxford Semiconductor OXNASSoC glue layer support for
+ 	  the stmmac device driver. This driver is used for OX820.
+ 
++config DWMAC_PHYTIUM
++	tristate "Phytium dwmac support"
++	default ARCH_PHYTIUM
++	depends on (OF || ACPI) && (ARCH_PHYTIUM || COMPILE_TEST)
++	help
++	  Support for GMAC controller on Phytium SoCs.
++
++	  This selects the Phytium GMAC glue layer support for the
++	  stmmac device driver.
++
+ config DWMAC_QCOM_ETHQOS
+ 	tristate "Qualcomm ETHQOS support"
+ 	default ARCH_QCOM
+--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_DWMAC_LPC18XX)	+= dwmac-lpc
+ obj-$(CONFIG_DWMAC_MEDIATEK)	+= dwmac-mediatek.o
+ obj-$(CONFIG_DWMAC_MESON)	+= dwmac-meson.o dwmac-meson8b.o
+ obj-$(CONFIG_DWMAC_OXNAS)	+= dwmac-oxnas.o
++obj-$(CONFIG_DWMAC_PHYTIUM)	+= dwmac-phytium.o
+ obj-$(CONFIG_DWMAC_QCOM_ETHQOS)	+= dwmac-qcom-ethqos.o
+ obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rk.o
+ obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -394,6 +394,12 @@ config XILINX_GMII2RGMII
+ 	  the Reduced Gigabit Media Independent Interface(RGMII) between
+ 	  Ethernet physical media devices and the Gigabit Ethernet controller.
+ 
++config MOTORCOMM_PHY
++	tristate "Motorcomm PHYs"
++	help
++		Enables support for Motorcomm network PHYs.
++		Currently supports the YT8511 gigabit PHY.
++
+ endif # PHYLIB
+ 
+ config MICREL_KS8995MA
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -96,3 +96,5 @@ obj-$(CONFIG_STE10XP)		+= ste10Xp.o
+ obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o
+ obj-$(CONFIG_VITESSE_PHY)	+= vitesse.o
+ obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
++
++obj-$(CONFIG_MOTORCOMM_PHY)    += motorcomm.o
+--- a/drivers/net/phy/at803x.c
++++ b/drivers/net/phy/at803x.c
+@@ -103,6 +103,10 @@
+ #define AT803X_DEBUG_REG_GREEN			0x3D
+ #define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
+ 
++#define AT803X_DEBUG_REG_B			0x0B
++#define AT803X_DEBUG_REG_B_HIBERNATION_ENABLE	0x1
++#define AT803X_DEBUG_REG_B_HIBERNATION_OFFSET	15
++
+ #define AT803X_DEBUG_REG_1F			0x1F
+ #define AT803X_DEBUG_PLL_ON			BIT(2)
+ #define AT803X_DEBUG_RGMII_1V8			BIT(3)
+@@ -284,6 +288,20 @@ static int at803x_enable_tx_delay(struct
+ 				     AT803X_DEBUG_TX_CLK_DLY_EN);
+ }
+ 
++static inline int at803x_disable_hibernate(struct phy_device *phydev)
++{
++	int ret = 0;
++	u16 val = 0;
++
++	ret = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_B);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
++	val &= (~(AT803X_DEBUG_REG_B_HIBERNATION_ENABLE << AT803X_DEBUG_REG_B_HIBERNATION_OFFSET));
++	return phy_write(phydev, AT803X_DEBUG_DATA, val);
++}
++
+ static int at803x_disable_rx_delay(struct phy_device *phydev)
+ {
+ 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+@@ -717,6 +735,10 @@ static int at803x_config_init(struct phy
+ {
+ 	int ret;
+ 
++	ret = at803x_disable_hibernate(phydev);
++	if (ret < 0)
++		return ret;
++
+ 	/* The RX and TX delay default is:
+ 	 *   after HW reset: RX delay enabled and TX delay disabled
+ 	 *   after SW reset: RX delay enabled, while TX delay retains the
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -306,6 +306,9 @@ static int phylink_parse_mode(struct phy
+ 			phylink_set(pl->supported, 2500baseX_Full);
+ 			break;
+ 
++		case PHY_INTERFACE_MODE_5GBASER:
++			phylink_set(pl->supported, 5000baseT_Full);
++			break;
+ 		case PHY_INTERFACE_MODE_USXGMII:
+ 		case PHY_INTERFACE_MODE_10GKR:
+ 		case PHY_INTERFACE_MODE_10GBASER:
+--- a/drivers/pci/hotplug/pciehp.h
++++ b/drivers/pci/hotplug/pciehp.h
+@@ -109,6 +109,11 @@ struct controller {
+ 	unsigned int ist_running;
+ 	int request_result;
+ 	wait_queue_head_t requester;
++
++#ifdef CONFIG_ARCH_PHYTIUM
++	u32 buses;
++	u16 slot_ctrl_t;
++#endif
+ };
+ 
+ /**
+--- a/drivers/pci/hotplug/pciehp_ctrl.c
++++ b/drivers/pci/hotplug/pciehp_ctrl.c
+@@ -226,6 +226,11 @@ void pciehp_handle_presence_or_link_chan
+ {
+ 	int present, link_active;
+ 
++#ifdef CONFIG_ARCH_PHYTIUM
++	struct pci_dev *pdev = ctrl->pcie->port;
++	u16 slot_ctrl_val;
++#endif
++
+ 	/*
+ 	 * If the slot is on and presence or link has changed, turn it off.
+ 	 * Even if it's occupied again, we cannot assume the card is the same.
+@@ -244,6 +249,21 @@ void pciehp_handle_presence_or_link_chan
+ 		if (events & PCI_EXP_SLTSTA_PDC)
+ 			ctrl_info(ctrl, "Slot(%s): Card not present\n",
+ 				  slot_name(ctrl));
++#ifdef CONFIG_ARCH_PHYTIUM
++		if ((ctrl->buses > 0) && (ctrl->slot_ctrl > 0)) {
++			pci_write_config_dword(pdev, PCI_PRIMARY_BUS, ctrl->buses);
++			slot_ctrl_val = ctrl->slot_ctrl_t | PCI_EXP_SLTCTL_ABPE |
++					PCI_EXP_SLTCTL_PFDE | PCI_EXP_SLTCTL_MRLSCE |
++					PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_CCIE |
++					PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_ATTN_IND_BLINK |
++					PCI_EXP_SLTCTL_PWR_IND_ON |
++					PCI_EXP_SLTCTL_DLLSCE;
++			slot_ctrl_val &= ~PCI_EXP_SLTCTL_PWR_OFF;
++			pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl_val);
++			ctrl_info(ctrl, "Ctrl buses=0x%x, slot_ctrl=0x%x\n",
++				  ctrl->buses, slot_ctrl_val);
++		}
++#endif
+ 		pciehp_disable_slot(ctrl, SURPRISE_REMOVAL);
+ 		break;
+ 	default:
+--- a/drivers/pci/hotplug/pciehp_hpc.c
++++ b/drivers/pci/hotplug/pciehp_hpc.c
+@@ -597,7 +597,7 @@ static irqreturn_t pciehp_isr(int irq, v
+ 	 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
+ 	 */
+ 	if (pdev->current_state == PCI_D3cold ||
+-	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
++			(!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
+ 		return IRQ_NONE;
+ 
+ 	/*
+@@ -695,7 +695,13 @@ static irqreturn_t pciehp_ist(int irq, v
+ 	struct controller *ctrl = (struct controller *)dev_id;
+ 	struct pci_dev *pdev = ctrl_dev(ctrl);
+ 	irqreturn_t ret;
++#ifdef CONFIG_ARCH_PHYTIUM
++	u32 events, buses;
++	u16 slot_ctrl;
++	bool link_active;
++#else
+ 	u32 events;
++#endif
+ 
+ 	ctrl->ist_running = true;
+ 	pci_config_pm_runtime_get(pdev);
+@@ -715,6 +721,23 @@ static irqreturn_t pciehp_ist(int irq, v
+ 		goto out;
+ 	}
+ 
++#ifdef CONFIG_ARCH_PHYTIUM
++	if(ctrl->state == ON_STATE) {
++		pci_read_config_dword(pdev, PCI_PRIMARY_BUS, &buses);
++		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
++		ctrl->buses = buses;
++		ctrl->slot_ctrl_t = slot_ctrl;
++                ctrl_dbg(ctrl, "Ctrl buses=0x%x, slot_ctrl=0x%x\n",
++				ctrl->buses, ctrl->slot_ctrl_t);
++        }
++
++	mdelay(1000);
++
++	link_active = pciehp_check_link_active(ctrl);
++	if((ctrl->state == ON_STATE) && (link_active == false))
++		events |= PCI_EXP_SLTSTA_DLLSC;
++#endif
++
+ 	/* Check Attention Button Pressed */
+ 	if (events & PCI_EXP_SLTSTA_ABP) {
+ 		ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
+@@ -749,7 +772,6 @@ static irqreturn_t pciehp_ist(int irq, v
+ 	else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
+ 		pciehp_handle_presence_or_link_change(ctrl, events);
+ 	up_read(&ctrl->reset_lock);
+-
+ 	ret = IRQ_HANDLED;
+ out:
+ 	pci_config_pm_runtime_put(pdev);
+--- a/drivers/pci/pcie/portdrv.h
++++ b/drivers/pci/pcie/portdrv.h
+@@ -123,6 +123,19 @@ void pcie_port_bus_unregister(void);
+ 
+ struct pci_dev;
+ 
++#ifdef CONFIG_HOTPLUG_PCI_PCIE
++extern bool pciehp_msi_disabled;
++
++static inline bool pciehp_no_msi(void)
++{
++	return pciehp_msi_disabled;
++}
++
++#else  /* !CONFIG_HOTPLUG_PCI_PCIE */
++static inline bool pciehp_no_msi(void) { return false; }
++#endif /* !CONFIG_HOTPLUG_PCI_PCIE */
++
++
+ #ifdef CONFIG_PCIE_PME
+ extern bool pcie_pme_msi_disabled;
+ 
+--- a/drivers/pci/pcie/portdrv_core.c
++++ b/drivers/pci/pcie/portdrv_core.c
+@@ -25,6 +25,17 @@ struct portdrv_service_data {
+ 	u32 service;
+ };
+ 
++bool pciehp_msi_disabled;
++
++static int __init pciehp_setup(char *str)
++{
++	if (!strncmp(str, "nomsi", 5))
++		pciehp_msi_disabled = true;
++
++	return 1;
++}
++__setup("pcie_hp=", pciehp_setup);
++
+ /**
+  * release_pcie_device - free PCI Express port service device structure
+  * @dev: Port service device to release
+@@ -177,6 +188,9 @@ static int pcie_init_service_irqs(struct
+ 	if ((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi())
+ 		goto legacy_irq;
+ 
++	if ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())
++		goto legacy_irq;
++
+ 	/* Try to use MSI-X or MSI if supported */
+ 	if (pcie_port_enable_irq_vec(dev, irqs, mask) == 0)
+ 		return 0;
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -30,6 +30,7 @@
+ #include <linux/suspend.h>
+ #include <linux/switchtec.h>
+ #include <asm/dma.h>	/* isa_dma_bridge_buggy */
++#include <linux/crash_dump.h>
+ #include "pci.h"
+ 
+ static ktime_t fixup_debug_start(struct pci_dev *dev,
+@@ -3885,12 +3886,12 @@ static int nvme_disable_and_flr(struct p
+ 	void __iomem *bar;
+ 	u16 cmd;
+ 	u32 cfg;
+-
++	printk("%s began\n", __func__);
+ 	if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
+ 	    !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
+ 		return -ENOTTY;
+ 
+-	if (probe)
++	if (probe & !is_kdump_kernel())
+ 		return 0;
+ 
+ 	bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
+@@ -3944,7 +3945,7 @@ static int nvme_disable_and_flr(struct p
+ 	pci_iounmap(dev, bar);
+ 
+ 	pcie_flr(dev);
+-
++	printk("%s finished\n", __func__);
+ 	return 0;
+ }
+ 
+@@ -4040,6 +4041,7 @@ static const struct pci_dev_reset_method
+ 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
+ 		reset_ivb_igd },
+ 	{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
++	{ PCI_VENDOR_ID_SAMSUNG, 0xa809, nvme_disable_and_flr },
+ 	{ PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
+ 	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
+ 		reset_chelsio_generic_dev },
+@@ -4979,6 +4981,10 @@ static const struct pci_dev_acs_enabled
+ 	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
+ 	/* Wangxun nics */
+ 	{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
++	/* Phytium Technology */
++	{ 0x10b5, PCI_ANY_ID, pci_quirk_xgene_acs },
++	{ 0x17cd, PCI_ANY_ID, pci_quirk_xgene_acs },
++	{ 0x1db7, PCI_ANY_ID, pci_quirk_xgene_acs },
+ 	{ 0 }
+ };
+ 
+@@ -5362,6 +5368,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SE
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PHYTIUM, 0xdc3a, quirk_no_ext_tags);
+ 
+ #ifdef CONFIG_PCI_ATS
+ static void quirk_no_ats(struct pci_dev *pdev)
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -570,4 +570,14 @@ config PWM_ZX
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-zx.
+ 
++config PWM_PHYTIUM
++	tristate "Phytium PWM support"
++	depends on ARCH_PHYTIUM
++	help
++	  Generic PWM framework driver for the PWM controller found on
++	  Phytium SoCs.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called pwm-phytium.
++
+ endif
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -55,3 +55,5 @@ obj-$(CONFIG_PWM_TWL)		+= pwm-twl.o
+ obj-$(CONFIG_PWM_TWL_LED)	+= pwm-twl-led.o
+ obj-$(CONFIG_PWM_VT8500)	+= pwm-vt8500.o
+ obj-$(CONFIG_PWM_ZX)		+= pwm-zx.o
++
++obj-$(CONFIG_PWM_PHYTIUM)       += pwm-phytium.o
+--- a/drivers/pwm/sysfs.c
++++ b/drivers/pwm/sysfs.c
+@@ -260,7 +260,7 @@ static int pwm_export_child(struct devic
+ 	export->child.parent = parent;
+ 	export->child.devt = MKDEV(0, 0);
+ 	export->child.groups = pwm_groups;
+-	dev_set_name(&export->child, "pwm%u", pwm->hwpwm);
++	dev_set_name(&export->child, "pwm%u", pwm->pwm);
+ 
+ 	ret = device_register(&export->child);
+ 	if (ret) {
+--- a/drivers/remoteproc/Kconfig
++++ b/drivers/remoteproc/Kconfig
+@@ -288,6 +288,12 @@ config TI_K3_R5_REMOTEPROC
+ 	  It's safe to say N here if you're not interested in utilizing
+ 	  a slave processor.
+ 
++config HOMO_REMOTEPROC
++	bool "homogeneous remoteproc support"
++	select RPMSG_VIRTIO
++	help
++	  Say y here to support homogeneous processors via the remote processor framework.
++
+ endif # REMOTEPROC
+ 
+ endmenu
+--- a/drivers/remoteproc/Makefile
++++ b/drivers/remoteproc/Makefile
+@@ -34,3 +34,4 @@ obj-$(CONFIG_ST_SLIM_REMOTEPROC)	+= st_s
+ obj-$(CONFIG_STM32_RPROC)		+= stm32_rproc.o
+ obj-$(CONFIG_TI_K3_DSP_REMOTEPROC)	+= ti_k3_dsp_remoteproc.o
+ obj-$(CONFIG_TI_K3_R5_REMOTEPROC)	+= ti_k3_r5_remoteproc.o
++obj-$(CONFIG_HOMO_REMOTEPROC)  += homo_remoteproc.o
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -701,6 +701,16 @@ config RTC_DRV_S5M
+ 	  This driver can also be built as a module. If so, the module
+ 	  will be called rtc-s5m.
+ 
++config RTC_DRV_SD3068
++	tristate "ZXW Shenzhen whwave SD3068"
++        select REGMAP_I2C
++        help
++          If you say yes here you get support for the ZXW Shenzhen whwave
++          SD3068 RTC chips.
++
++          This driver can also be built as a module. If so, the module
++          will be called rtc-sd3068
++
+ config RTC_DRV_SD3078
+ 	tristate "ZXW Shenzhen whwave SD3078"
+ 	select REGMAP_I2C
+--- a/drivers/rtc/Makefile
++++ b/drivers/rtc/Makefile
+@@ -153,6 +153,7 @@ obj-$(CONFIG_RTC_DRV_S3C)	+= rtc-s3c.o
+ obj-$(CONFIG_RTC_DRV_S5M)	+= rtc-s5m.o
+ obj-$(CONFIG_RTC_DRV_SA1100)	+= rtc-sa1100.o
+ obj-$(CONFIG_RTC_DRV_SC27XX)	+= rtc-sc27xx.o
++obj-$(CONFIG_RTC_DRV_SD3068)   += rtc-sd3068.o
+ obj-$(CONFIG_RTC_DRV_SD3078)   += rtc-sd3078.o
+ obj-$(CONFIG_RTC_DRV_SH)	+= rtc-sh.o
+ obj-$(CONFIG_RTC_DRV_SIRFSOC)	+= rtc-sirfsoc.o
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -585,6 +585,44 @@ config SPI_ORION
+ 	  This enables using the SPI master controller on the Orion
+ 	  and MVEBU chips.
+ 
++config SPI_PHYTIUM
++	tristate
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++
++config SPI_PHYTIUM_PLAT
++	tristate "Phytium SPI controller platform support"
++	select SPI_PHYTIUM
++	help
++	  This selects a platform driver for Phytium SPI controller.
++
++	  If you say yes to this option, support will be included for
++	  Pd1904 and pd2008 families of SPI controller.
++
++config SPI_PHYTIUM_PCI
++	tristate "Phytium SPI controller PCI support"
++	depends on PCI
++	select SPI_PHYTIUM
++	help
++	  This selects a PCI driver for Phytium SPI controller.
++
++	  If you say yes to this option, support will be included for
++	  Phytium px210 chipset of SPI controller.
++
++	  If unsure, say N.
++
++config SPI_PHYTIUM_QSPI
++	tristate "Phytium Quad SPI controller"
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++	depends on OF
++	depends on SPI_MEM
++	help
++	  This enables support for Phytium Quad SPI flash controller.
++
++	  This driver does not support generic SPI. The implementation only
++	  supports spi-mem interface.
++
++	  If unsure, say N.
++
+ config SPI_PIC32
+ 	tristate "Microchip PIC32 series SPI"
+ 	depends on MACH_PIC32 || COMPILE_TEST
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -82,6 +82,11 @@ obj-$(CONFIG_SPI_OMAP_100K)		+= spi-omap
+ obj-$(CONFIG_SPI_OMAP24XX)		+= spi-omap2-mcspi.o
+ obj-$(CONFIG_SPI_TI_QSPI)		+= spi-ti-qspi.o
+ obj-$(CONFIG_SPI_ORION)			+= spi-orion.o
++obj-$(CONFIG_SPI_PHYTIUM)		+= spi-phytium.o
++obj-$(CONFIG_SPI_PHYTIUM_PLAT)		+= spi-phytium-plat.o
++obj-$(CONFIG_SPI_PHYTIUM_PCI)		+= spi-phytium-pci.o
++obj-$(CONFIG_SPI_PHYTIUM_QSPI)		+= spi-phytium-qspi.o
++obj-$(CONFIG_SPI_PHYTIUM)       += spi-phytium-dma.o
+ obj-$(CONFIG_SPI_PIC32)			+= spi-pic32.o
+ obj-$(CONFIG_SPI_PIC32_SQI)		+= spi-pic32-sqi.o
+ obj-$(CONFIG_SPI_PL022)			+= spi-pl022.o
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -5,6 +5,7 @@
+ 
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+ 
++#include <linux/acpi.h>
+ #include <linux/arm-smccc.h>
+ #include <linux/crash_dump.h>
+ #include <linux/errno.h>
+@@ -776,6 +777,14 @@ static const struct of_device_id optee_d
+ };
+ MODULE_DEVICE_TABLE(of, optee_dt_match);
+ 
++#ifdef CONFIG_ACPI
++static const struct acpi_device_id optee_acpi_match[] = {
++	{ "PHYT8003" },
++	{ }
++};
++MODULE_DEVICE_TABLE(acpi, optee_acpi_match);
++#endif
++
+ static struct platform_driver optee_driver = {
+ 	.probe  = optee_probe,
+ 	.remove = optee_remove,
+@@ -783,6 +792,7 @@ static struct platform_driver optee_driv
+ 	.driver = {
+ 		.name = "optee",
+ 		.of_match_table = optee_dt_match,
++		.acpi_match_table = ACPI_PTR(optee_acpi_match),
+ 	},
+ };
+ module_platform_driver(optee_driver);
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -73,6 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE
+ 	  your boot loader (lilo or loadlin) about how to pass options to the
+ 	  kernel at boot time.)
+ 
++config SERIAL_PHYTIUM_PCI
++	tristate "Phytium PCI serial port support"
++	depends on PCI
++	select SERIAL_CORE
++	help
++	  This driver supports the Phytium UART controller on PCI/PCIe adapters.
++	  If you want to compile this driver into the kernel, say Y here.  To
++	  compile this driver as a module, choose M here.
++
++	  If unsure, say N.
++
+ config SERIAL_EARLYCON_ARM_SEMIHOST
+ 	bool "Early console using ARM semihosting"
+ 	depends on ARM64 || ARM
+--- a/drivers/tty/serial/Makefile
++++ b/drivers/tty/serial/Makefile
+@@ -91,6 +91,8 @@ obj-$(CONFIG_SERIAL_RDA)	+= rda-uart.o
+ obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
+ obj-$(CONFIG_SERIAL_SIFIVE)	+= sifive.o
+ 
++obj-$(CONFIG_SERIAL_PHYTIUM_PCI) += phytium-uart.o
++
+ # GPIOLIB helpers for modem control lines
+ obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
+ 
+--- a/drivers/usb/Kconfig
++++ b/drivers/usb/Kconfig
+@@ -125,6 +125,8 @@ source "drivers/usb/chipidea/Kconfig"
+ 
+ source "drivers/usb/isp1760/Kconfig"
+ 
++source "drivers/usb/phytium/Kconfig"
++
+ comment "USB port drivers"
+ 
+ if USB
+--- a/drivers/usb/Makefile
++++ b/drivers/usb/Makefile
+@@ -66,3 +66,5 @@ obj-$(CONFIG_USBIP_CORE)	+= usbip/
+ obj-$(CONFIG_TYPEC)		+= typec/
+ 
+ obj-$(CONFIG_USB_ROLE_SWITCH)	+= roles/
++
++obj-$(CONFIG_USB_PHYTIUM)   += phytium/
+--- a/drivers/usb/host/xhci-pci.c
++++ b/drivers/usb/host/xhci-pci.c
+@@ -72,6 +72,8 @@
+ #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI			0x2142
+ #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI			0x3242
+ 
++#define PCI_DEVICE_ID_PHYTIUM_XHCI				0xdc27
++
+ static const char hcd_name[] = "xhci_hcd";
+ 
+ static struct hc_driver __read_mostly xhci_pci_hc_driver;
+@@ -283,6 +285,9 @@ static void xhci_pci_quirks(struct devic
+ 	if (pdev->vendor == PCI_VENDOR_ID_VIA)
+ 		xhci->quirks |= XHCI_RESET_ON_RESUME;
+ 
++	if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM ||
++	    pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI)
++		xhci->quirks |= XHCI_RESET_ON_RESUME;
+ 	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
+ 	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
+ 			pdev->device == 0x3432)
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -137,6 +137,10 @@ static const struct xhci_plat_priv xhci_
+ 	.quirks = XHCI_RESET_ON_RESUME | XHCI_SUSPEND_RESUME_CLKS,
+ };
+ 
++static const struct xhci_plat_priv xhci_plat_phytium_pe220x = {
++	.quirks = XHCI_RESET_ON_RESUME,
++};
++
+ static const struct of_device_id usb_xhci_of_match[] = {
+ 	{
+ 		.compatible = "generic-xhci",
+@@ -178,6 +182,9 @@ static const struct of_device_id usb_xhc
+ 	}, {
+ 		.compatible = "brcm,bcm7445-xhci",
+ 		.data = &xhci_plat_brcm,
++	}, {
++		.compatible = "phytium,pe220x-xhci",
++		.data = &xhci_plat_phytium_pe220x,
+ 	},
+ 	{},
+ };
+@@ -289,6 +296,8 @@ static int xhci_plat_probe(struct platfo
+ 
+ 	if (pdev->dev.of_node)
+ 		priv_match = of_device_get_match_data(&pdev->dev);
++	else if (has_acpi_companion(&pdev->dev))
++		priv_match = acpi_device_get_match_data(&pdev->dev);
+ 	else
+ 		priv_match = dev_get_platdata(&pdev->dev);
+ 
+@@ -533,6 +542,7 @@ static const struct dev_pm_ops xhci_plat
+ static const struct acpi_device_id usb_xhci_acpi_match[] = {
+ 	/* XHCI-compliant USB Controller */
+ 	{ "PNP0D10", },
++	{ "PHYT0039", (kernel_ulong_t)&xhci_plat_phytium_pe220x },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(acpi, usb_xhci_acpi_match);
+--- a/drivers/w1/masters/Kconfig
++++ b/drivers/w1/masters/Kconfig
+@@ -74,5 +74,15 @@ config W1_MASTER_SGI
+ 	  This support is also available as a module.  If so, the module
+ 	  will be called sgi_w1.
+ 
++config W1_MASTER_PHYTIUM
++	tristate "Phytium 1-wire driver"
++	depends on ARCH_PHYTIUM || COMPILE_TEST
++	help
++	  Say Y here if you want to get support for the 1-wire interface
++	  on an Phytium SoC.
++
++	  This driver can also be built as a module.  If so, the module
++	  will be called phytium-w1.
++
+ endmenu
+ 
+--- a/drivers/w1/masters/Makefile
++++ b/drivers/w1/masters/Makefile
+@@ -12,3 +12,5 @@ obj-$(CONFIG_W1_MASTER_DS1WM)		+= ds1wm.
+ obj-$(CONFIG_W1_MASTER_GPIO)		+= w1-gpio.o
+ obj-$(CONFIG_HDQ_MASTER_OMAP)		+= omap_hdq.o
+ obj-$(CONFIG_W1_MASTER_SGI)		+= sgi_w1.o
++
++obj-$(CONFIG_W1_MASTER_PHYTIUM)		+= phytium_w1.o
+\ No newline at end of file
+--- a/include/acpi/acpi_drivers.h
++++ b/include/acpi/acpi_drivers.h
+@@ -68,7 +68,7 @@
+ 
+ int acpi_irq_penalty_init(void);
+ int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
+-			       int *polarity, char **name);
++			       int *polarity, char **name, struct fwnode_handle **rs_fwnode);
+ int acpi_pci_link_free_irq(acpi_handle handle);
+ 
+ /* ACPI PCI Device Binding (pci_bind.c) */
+--- a/include/clocksource/arm_arch_timer.h
++++ b/include/clocksource/arm_arch_timer.h
+@@ -24,7 +24,7 @@
+ 
+ enum arch_timer_reg {
+ 	ARCH_TIMER_REG_CTRL,
+-	ARCH_TIMER_REG_TVAL,
++	ARCH_TIMER_REG_CVAL,
+ };
+ 
+ enum arch_timer_ppi_nr {
+--- a/include/linux/acpi.h
++++ b/include/linux/acpi.h
+@@ -340,6 +340,16 @@ struct irq_domain *acpi_irq_create_hiera
+ 					     const struct irq_domain_ops *ops,
+ 					     void *host_data);
+ 
++#ifdef CONFIG_ACPI_GENERIC_GSI
++struct fwnode_handle *acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source);
++#else
++static inline
++struct fwnode_handle *acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
++{
++	return NULL;
++}
++#endif
++
+ #ifdef CONFIG_X86_IO_APIC
+ extern int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
+ #else
+--- a/include/linux/cpuhotplug.h
++++ b/include/linux/cpuhotplug.h
+@@ -196,6 +196,7 @@ enum cpuhp_state {
+ 	CPUHP_AP_ONLINE_DYN_END		= CPUHP_AP_ONLINE_DYN + 30,
+ 	CPUHP_AP_X86_HPET_ONLINE,
+ 	CPUHP_AP_X86_KVM_CLK_ONLINE,
++	CPUHP_AP_HOMO_RPROC_STARTING,
+ 	CPUHP_AP_ACTIVE,
+ 	CPUHP_ONLINE,
+ };
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -3141,4 +3141,6 @@
+ 
+ #define PCI_VENDOR_ID_NCUBE		0x10ff
+ 
++#define PCI_VENDOR_ID_PHYTIUM		0x1db7
++
+ #endif /* _LINUX_PCI_IDS_H */
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -107,6 +107,7 @@ extern const int phy_10gbit_features_arr
+  * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
+  * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX
+  * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX
++ * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR
+  * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI
+  * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface
+  * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR
+@@ -139,6 +140,7 @@ typedef enum {
+ 	PHY_INTERFACE_MODE_100BASEX,
+ 	PHY_INTERFACE_MODE_1000BASEX,
+ 	PHY_INTERFACE_MODE_2500BASEX,
++	PHY_INTERFACE_MODE_5GBASER,
+ 	PHY_INTERFACE_MODE_RXAUI,
+ 	PHY_INTERFACE_MODE_XAUI,
+ 	/* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
+@@ -209,6 +211,8 @@ static inline const char *phy_modes(phy_
+ 		return "1000base-x";
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+ 		return "2500base-x";
++	case PHY_INTERFACE_MODE_5GBASER:
++		return "5gbase-r";
+ 	case PHY_INTERFACE_MODE_RXAUI:
+ 		return "rxaui";
+ 	case PHY_INTERFACE_MODE_XAUI:
+@@ -549,7 +553,7 @@ struct phy_device {
+ 	struct phy_driver *drv;
+ 
+ 	u32 phy_id;
+-
++	u32 force_mode;
+ 	struct phy_c45_device_ids c45_ids;
+ 	unsigned is_c45:1;
+ 	unsigned is_internal:1;
+--- a/include/sound/hdaudio.h
++++ b/include/sound/hdaudio.h
+@@ -340,6 +340,7 @@ struct hdac_bus {
+ 	bool align_bdle_4k:1;		/* BDLE align 4K boundary */
+ 	bool reverse_assign:1;		/* assign devices in reverse order */
+ 	bool corbrp_self_clear:1;	/* CORBRP clears itself after reset */
++	bool cmd_resend:1;		/* command resend */
+ 	bool polling_mode:1;
+ 	bool needs_damn_long_delay:1;
+ 
+--- a/include/uapi/linux/serial_core.h
++++ b/include/uapi/linux/serial_core.h
+@@ -279,4 +279,11 @@
+ /* Freescale LINFlexD UART */
+ #define PORT_LINFLEXUART	122
+ 
++
++/* Phytium PCI UART
++ * use bigger value to aviod code confilct
++ * when update in the future.
++ */
++#define PORT_PHYTIUM   200
++
+ #endif /* _UAPILINUX_SERIAL_CORE_H */
+--- a/sound/hda/hdac_controller.c
++++ b/sound/hda/hdac_controller.c
+@@ -143,6 +143,9 @@ int snd_hdac_bus_send_cmd(struct hdac_bu
+ {
+ 	unsigned int addr = azx_command_addr(val);
+ 	unsigned int wp, rp;
++	unsigned long timeout;
++	unsigned int rirb_wp;
++	int i = 0;
+ 
+ 	spin_lock_irq(&bus->reg_lock);
+ 
+@@ -169,6 +172,42 @@ int snd_hdac_bus_send_cmd(struct hdac_bu
+ 	bus->corb.buf[wp] = cpu_to_le32(val);
+ 	snd_hdac_chip_writew(bus, CORBWP, wp);
+ 
++	if (bus->cmd_resend) {
++		timeout = jiffies + msecs_to_jiffies(1000);
++		udelay(80);
++		rirb_wp = snd_hdac_chip_readw(bus, RIRBWP);
++		while (rirb_wp == bus->rirb.wp) {
++			udelay(80);
++			rirb_wp = snd_hdac_chip_readw(bus, RIRBWP);
++			if (rirb_wp != bus->rirb.wp)
++				break;
++			if (i > 5)
++				break;
++			if (time_after(jiffies, timeout))
++				break;
++
++			/* add command to corb */
++			wp = snd_hdac_chip_readw(bus, CORBWP);
++			if (wp == 0xffff) {
++				/* something wrong, controller likely turned to D3 */
++				spin_unlock_irq(&bus->reg_lock);
++				return -EIO;
++			}
++			wp++;
++			wp %= AZX_MAX_CORB_ENTRIES;
++
++			rp = snd_hdac_chip_readw(bus, CORBRP);
++			if (wp == rp) {
++				/* oops, it's full */
++				spin_unlock_irq(&bus->reg_lock);
++				return -EAGAIN;
++			}
++			bus->corb.buf[wp] = cpu_to_le32(val);
++			snd_hdac_chip_writew(bus, CORBWP, wp);
++			i++;
++		}
++	}
++
+ 	spin_unlock_irq(&bus->reg_lock);
+ 
+ 	return 0;
+--- a/sound/hda/hdac_stream.c
++++ b/sound/hda/hdac_stream.c
+@@ -87,7 +87,11 @@ void snd_hdac_stream_start(struct hdac_s
+ 
+ 	trace_snd_hdac_stream_start(bus, azx_dev);
+ 
++#ifdef CONFIG_SND_HDA_PHYTIUM
++	azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK) / 15;
++#else
+ 	azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
++#endif
+ 	if (!fresh_start)
+ 		azx_dev->start_wallclk -= azx_dev->period_wallclk;
+ 
+@@ -550,7 +554,11 @@ static u64 azx_cc_read(const struct cycl
+ {
+ 	struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
+ 
++#ifdef CONFIG_SND_HDA_PHYTIUM
++	return snd_hdac_chip_readl(azx_dev->bus, WALLCLK) / 25;
++#else
+ 	return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
++#endif
+ }
+ 
+ static void azx_timecounter_init(struct hdac_stream *azx_dev,
+--- a/sound/pci/hda/Kconfig
++++ b/sound/pci/hda/Kconfig
+@@ -26,6 +26,22 @@ config SND_HDA_INTEL
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called snd-hda-intel.
+ 
++config SND_HDA_PHYTIUM
++	tristate "PHYTIUM HD Audio"
++	depends on SOUND
++	select SND_HDA
++	select SND_HDA_ALIGNED_MMIO
++	help
++	  Say Y here to support the HDA controller present in PHYTIUM
++	  SoCs
++
++	  This options enables support for the HD Audio controller
++	  present in some PHYTIUM SoCs, used to communicate audio
++	  to the "High Definition Audio" codec.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called snd-hda-phytium.
++
+ config SND_HDA_TEGRA
+ 	tristate "NVIDIA Tegra HD Audio"
+ 	depends on ARCH_TEGRA
+--- a/sound/pci/hda/Makefile
++++ b/sound/pci/hda/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ snd-hda-intel-objs := hda_intel.o
+ snd-hda-tegra-objs := hda_tegra.o
++snd-hda-phytium-objs := hda_phytium.o
+ 
+ snd-hda-codec-y := hda_bind.o hda_codec.o hda_jack.o hda_auto_parser.o hda_sysfs.o
+ snd-hda-codec-y += hda_controller.o
+@@ -48,3 +49,4 @@ obj-$(CONFIG_SND_HDA_CODEC_HDMI) += snd-
+ # when built in kernel
+ obj-$(CONFIG_SND_HDA_INTEL) += snd-hda-intel.o
+ obj-$(CONFIG_SND_HDA_TEGRA) += snd-hda-tegra.o
++obj-$(CONFIG_SND_HDA_PHYTIUM) += snd-hda-phytium.o
+--- a/sound/pci/hda/hda_controller.c
++++ b/sound/pci/hda/hda_controller.c
+@@ -17,6 +17,8 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/slab.h>
+ 
++#include "hda_phytium.h"
++
+ #ifdef CONFIG_X86
+ /* for art-tsc conversion */
+ #include <asm/tsc.h>
+@@ -157,6 +159,10 @@ static int azx_pcm_prepare(struct snd_pc
+ 		snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
+ 	unsigned short ctls = spdif ? spdif->ctls : 0;
+ 
++	struct hda_ft *hda;
++	hda = container_of(chip, struct hda_ft, chip);
++	hda->substream = substream;
++
+ 	trace_azx_pcm_prepare(chip, azx_dev);
+ 	dsp_lock(azx_dev);
+ 	if (dsp_is_locked(azx_dev)) {
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -77,6 +77,7 @@ source "sound/soc/ux500/Kconfig"
+ source "sound/soc/xilinx/Kconfig"
+ source "sound/soc/xtensa/Kconfig"
+ source "sound/soc/zte/Kconfig"
++source "sound/soc/phytium/Kconfig"
+ 
+ # Supported codecs
+ source "sound/soc/codecs/Kconfig"
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -60,3 +60,4 @@ obj-$(CONFIG_SND_SOC)	+= ux500/
+ obj-$(CONFIG_SND_SOC)	+= xilinx/
+ obj-$(CONFIG_SND_SOC)	+= xtensa/
+ obj-$(CONFIG_SND_SOC)	+= zte/
++obj-$(CONFIG_SND_SOC)	+= phytium/
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -795,6 +795,15 @@ config SND_SOC_ES8328_SPI
+ 	depends on SPI_MASTER
+ 	select SND_SOC_ES8328
+ 
++config SND_SOC_ES8336
++	tristate "Everest Semi ES8336 CODEC"
++	depends on I2C
++	select GPIO_PHYTIUM_PCI
++
++config SND_SOC_ES8388
++	tristate "Everest Semi ES8388 CODEC"
++	depends on I2C
++
+ config SND_SOC_GTM601
+ 	tristate 'GTM601 UMTS modem audio codec'
+ 
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -90,6 +90,8 @@ snd-soc-es8316-objs := es8316.o
+ snd-soc-es8328-objs := es8328.o
+ snd-soc-es8328-i2c-objs := es8328-i2c.o
+ snd-soc-es8328-spi-objs := es8328-spi.o
++snd-soc-es8336-objs := es8336.o
++snd-soc-es8388-objs := es8388.o
+ snd-soc-gtm601-objs := gtm601.o
+ snd-soc-hdac-hdmi-objs := hdac_hdmi.o
+ snd-soc-hdac-hda-objs := hdac_hda.o
+@@ -399,6 +401,8 @@ obj-$(CONFIG_SND_SOC_ES8316)    += snd-s
+ obj-$(CONFIG_SND_SOC_ES8328)	+= snd-soc-es8328.o
+ obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
+ obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
++obj-$(CONFIG_SND_SOC_ES8336)	+= snd-soc-es8336.o
++obj-$(CONFIG_SND_SOC_ES8388)	+= snd-soc-es8388.o
+ obj-$(CONFIG_SND_SOC_GTM601)    += snd-soc-gtm601.o
+ obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
+ obj-$(CONFIG_SND_SOC_HDAC_HDA) += snd-soc-hdac-hda.o
diff --git a/target/linux/phytium/patches-5.10/002-fix-build-fail.patch b/target/linux/phytium/patches-5.10/002-fix-build-fail.patch
new file mode 100644
index 00000000000000..d94ddc879ab50c
--- /dev/null
+++ b/target/linux/phytium/patches-5.10/002-fix-build-fail.patch
@@ -0,0 +1,11 @@
+--- a/scripts/Makefile
++++ b/scripts/Makefile
+@@ -21,7 +21,7 @@ HOSTCFLAGS_asn1_compiler.o = -I$(srctree
+ HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS)
+ HOSTLDLIBS_sign-file = $(CRYPTO_LIBS)
+ HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS)
+-HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS)
++HOSTLDLIBS_extract-cert = -lcrypto -lpthread
+ 
+ ifdef CONFIG_UNWINDER_ORC
+ ifeq ($(ARCH),x86_64)
diff --git a/target/linux/phytium/phytiumpi/base-files/etc/inittab b/target/linux/phytium/phytiumpi/base-files/etc/inittab
new file mode 100644
index 00000000000000..b944a93ada4b5a
--- /dev/null
+++ b/target/linux/phytium/phytiumpi/base-files/etc/inittab
@@ -0,0 +1,4 @@
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+::askconsole:/usr/libexec/login.sh
+tty1::askfirst:/usr/libexec/login.sh
diff --git a/target/linux/phytium/phytiumpi/base-files/lib/upgrade/platform.sh b/target/linux/phytium/phytiumpi/base-files/lib/upgrade/platform.sh
new file mode 100755
index 00000000000000..e9bcfea7dc3ede
--- /dev/null
+++ b/target/linux/phytium/phytiumpi/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,47 @@
+REQUIRE_IMAGE_METADATA=1
+
+platform_do_upgrade() {
+	local board=$(board_name)
+	case "$board" in
+	phytiumpi_firefly)
+		export_bootdevice
+		export_partdevice rootdev 0
+		case "$rootdev" in
+		mmc*)
+			CI_ROOTDEV="$rootdev"
+			CI_KERNPART="kernel"
+			CI_ROOTPART="rootfs"
+			emmc_do_upgrade "$1"
+			;;
+		esac
+		;;
+	esac
+}
+
+platform_check_image() {
+	local board=$(board_name)
+	local magic="$(get_magic_long "$1")"
+	case "$board" in
+	phytiumpi_firefly)
+		[ "$magic" != "73797375" ] && {
+			echo "Invalid image type."
+			return 1
+		}
+		return 0
+		;;
+	esac
+
+	return 0
+}
+
+platform_copy_config() {
+	case "$(board_name)" in
+	phytiumpi_firefly)
+		export_bootdevice
+		export_partdevice rootdev 0
+		if echo $rootdev | grep -q mmc; then
+			emmc_copy_config
+		fi
+		;;
+	esac
+}
diff --git a/target/linux/phytium/phytiumpi/config-5.10 b/target/linux/phytium/phytiumpi/config-5.10
new file mode 100644
index 00000000000000..2839a05eab0b8d
--- /dev/null
+++ b/target/linux/phytium/phytiumpi/config-5.10
@@ -0,0 +1,682 @@
+CONFIG_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PHYTIUM=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_MODULE_PLTS=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SVE=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_UAO=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_VHE=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_CRDA_SUPPORT=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=5
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_SCMI is not set
+CONFIG_COMPAT=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTIG_ALLOC=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_BLAKE2S=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PHYTIUM=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_PHYTIUM_CORE=y
+# CONFIG_GPIO_PHYTIUM_PCI is not set
+CONFIG_GPIO_PHYTIUM_PLAT=y
+# CONFIG_GPIO_PHYTIUM_SGPIO is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+# CONFIG_HARDENED_USERCOPY is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HOLES_IN_ZONE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KEYS=y
+CONFIG_KSM=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_PHYTIUM_MCI_PLTFM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_FLOW_LIMIT=y
+# CONFIG_NL80211_TESTMODE is not set
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OID_REGISTRY=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_XPCS=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHYTIUM_MBOX=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RTL8723BS is not set
+CONFIG_RTL8821CS=m
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_HOST=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SG_POOL=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_PHYTIUM=y
+# CONFIG_SPI_PHYTIUM_PCI is not set
+CONFIG_SPI_PHYTIUM_PLAT=y
+CONFIG_SPI_PHYTIUM_QSPI=y
+CONFIG_SPI_PHYTIUM_QUADSPI=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_DP_ALTMODE is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_UACCE is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_PHYTIUM=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VIRT_WIFI is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WFX is not set
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/phytium/phytiumpi/target.mk b/target/linux/phytium/phytiumpi/target.mk
new file mode 100644
index 00000000000000..b28d84ef0dcc1b
--- /dev/null
+++ b/target/linux/phytium/phytiumpi/target.mk
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Phytium Technology Co., Ltd.
+
+ARCH:=aarch64
+SUBTARGET:=phytiumpi
+BOARDNAME:=PhytiumPi
+FEATURES+=emmc nand display
+
+DEFAULT_PACKAGES += hostapd hostapd-utils kmod-rtl8821cs kmod-cfg80211
+
+define Target/Description
+	Build firmware image for Phytium PhytiumPi devices.
+endef
diff --git a/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
index 746a3ac70a5c13..7dad27e7e20def 100644
--- a/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ b/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -25,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/mmc/host/Kconfig
 +++ b/drivers/mmc/host/Kconfig
-@@ -1103,3 +1103,5 @@ config MMC_OWL
+@@ -1105,3 +1105,5 @@ config MMC_OWL
  
  config MMC_SDHCI_EXTERNAL_DMA
  	bool
diff --git a/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
index 2896002ed1aaee..9a0dbd7bb85c9a 100644
--- a/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ b/target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -25,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/mmc/host/Kconfig
 +++ b/drivers/mmc/host/Kconfig
-@@ -1093,3 +1093,5 @@ config MMC_OWL
+@@ -1095,3 +1095,5 @@ config MMC_OWL
  
  config MMC_SDHCI_EXTERNAL_DMA
  	bool
diff --git a/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
index add9adc3b8e52e..fbc311d39c7e30 100644
--- a/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ b/target/linux/ramips/patches-5.4/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -25,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/mmc/host/Kconfig
 +++ b/drivers/mmc/host/Kconfig
-@@ -1020,3 +1020,5 @@ config MMC_SDHCI_AM654
+@@ -1021,3 +1021,5 @@ config MMC_SDHCI_AM654
  	  If you have a controller with this interface, say Y or M here.
  
  	  If unsure, say N.
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index 7de86c84cf625a..820d155e2e4cea 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -8,7 +8,7 @@ define Device/ariaboard_photonicat
   SOC := rk3568
   UBOOT_DEVICE_NAME := photonicat-rk3568
   IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
-  DEVICE_PACKAGES := ath10k-firmware-qca9377-sdio kmod-ath10k kmod-ath10k-sdio pcat-manager wpad
+  DEVICE_PACKAGES := photonicat-firmware  kmod-ath10k kmod-ath10k-sdio pcat-manager wpad
 endef
 TARGET_DEVICES += ariaboard_photonicat
 
diff --git a/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch b/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch
index ce479f9734691a..0dcbc9bf5bcb98 100644
--- a/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch
+++ b/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch
@@ -38,7 +38,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		if (!buf->sec_page)
  			return -ENOMEM;
  
-@@ -4631,6 +4635,10 @@ static inline void stmmac_rx_refill(stru
+@@ -4632,6 +4636,10 @@ static inline void stmmac_rx_refill(stru
  	struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int entry = rx_q->dirty_rx;
@@ -49,7 +49,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	while (dirty-- > 0) {
  		struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
-@@ -4643,13 +4651,13 @@ static inline void stmmac_rx_refill(stru
+@@ -4644,13 +4652,13 @@ static inline void stmmac_rx_refill(stru
  			p = rx_q->dma_rx + entry;
  
  		if (!buf->page) {
diff --git a/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch b/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch
index 2c6cbb16fa3752..66b9a33e14aab9 100644
--- a/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch
+++ b/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch
@@ -22,7 +22,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -1127,6 +1127,11 @@ static int dwc3_core_init(struct dwc3 *d
+@@ -1090,6 +1090,11 @@ static int dwc3_core_init(struct dwc3 *d
  		if (dwc->parkmode_disable_ss_quirk)
  			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
  
diff --git a/target/linux/rockchip/patches-5.15/114-rfkill-gpio-add-of_match_table-support.patch b/target/linux/rockchip/patches-5.15/114-rfkill-gpio-add-of_match_table-support.patch
index 0be77c07e3b747..7b8a50ff461b1f 100644
--- a/target/linux/rockchip/patches-5.15/114-rfkill-gpio-add-of_match_table-support.patch
+++ b/target/linux/rockchip/patches-5.15/114-rfkill-gpio-add-of_match_table-support.patch
@@ -10,7 +10,7 @@ Signed-off-by: jensen <jensenhuang@friendlyarm.com>
 
 --- a/net/rfkill/rfkill-gpio.c
 +++ b/net/rfkill/rfkill-gpio.c
-@@ -156,6 +156,13 @@ static const struct acpi_device_id rfkil
+@@ -164,6 +164,13 @@ static const struct acpi_device_id rfkil
  };
  MODULE_DEVICE_TABLE(acpi, rfkill_acpi_match);
  #endif
@@ -24,7 +24,7 @@ Signed-off-by: jensen <jensenhuang@friendlyarm.com>
  
  static struct platform_driver rfkill_gpio_driver = {
  	.probe = rfkill_gpio_probe,
-@@ -163,6 +170,7 @@ static struct platform_driver rfkill_gpi
+@@ -171,6 +178,7 @@ static struct platform_driver rfkill_gpi
  	.driver = {
  		.name = "rfkill_gpio",
  		.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
diff --git a/target/linux/rockchip/patches-6.1/011-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch b/target/linux/rockchip/patches-6.1/011-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch
index 359ef82281ac95..daec674d051034 100644
--- a/target/linux/rockchip/patches-6.1/011-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch
+++ b/target/linux/rockchip/patches-6.1/011-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch
@@ -21,7 +21,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -13959,6 +13959,7 @@ F:	include/uapi/linux/meye.h
+@@ -13964,6 +13964,7 @@ F:	include/uapi/linux/meye.h
  
  MOTORCOMM PHY DRIVER
  M:	Peter Geis <pgwipeout@gmail.com>
diff --git a/target/linux/rockchip/patches-6.1/114-rfkill-gpio-add-of_match_table-support.patch b/target/linux/rockchip/patches-6.1/114-rfkill-gpio-add-of_match_table-support.patch
index 0be77c07e3b747..7b8a50ff461b1f 100644
--- a/target/linux/rockchip/patches-6.1/114-rfkill-gpio-add-of_match_table-support.patch
+++ b/target/linux/rockchip/patches-6.1/114-rfkill-gpio-add-of_match_table-support.patch
@@ -10,7 +10,7 @@ Signed-off-by: jensen <jensenhuang@friendlyarm.com>
 
 --- a/net/rfkill/rfkill-gpio.c
 +++ b/net/rfkill/rfkill-gpio.c
-@@ -156,6 +156,13 @@ static const struct acpi_device_id rfkil
+@@ -164,6 +164,13 @@ static const struct acpi_device_id rfkil
  };
  MODULE_DEVICE_TABLE(acpi, rfkill_acpi_match);
  #endif
@@ -24,7 +24,7 @@ Signed-off-by: jensen <jensenhuang@friendlyarm.com>
  
  static struct platform_driver rfkill_gpio_driver = {
  	.probe = rfkill_gpio_probe,
-@@ -163,6 +170,7 @@ static struct platform_driver rfkill_gpi
+@@ -171,6 +178,7 @@ static struct platform_driver rfkill_gpi
  	.driver = {
  		.name = "rfkill_gpio",
  		.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
diff --git a/target/linux/x86/64/config-6.6 b/target/linux/x86/64/config-6.6
new file mode 100644
index 00000000000000..5de48cc8af6bfd
--- /dev/null
+++ b/target/linux/x86/64/config-6.6
@@ -0,0 +1,532 @@
+CONFIG_64BIT=y
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+# CONFIG_ACPI_BGRT is not set
+CONFIG_ACPI_BUTTON=y
+# CONFIG_ACPI_CMPC is not set
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPPC_LIB=y
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_DPTF is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_FPDT is not set
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_I2C_OPREGION is not set
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ACPI_LPIT=y
+# CONFIG_ACPI_PCC is not set
+# CONFIG_ACPI_PCI_SLOT is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PRMT=y
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+# CONFIG_ACPI_WMI is not set
+# CONFIG_ACRN_GUEST is not set
+CONFIG_AGP=y
+# CONFIG_AGP_AMD64 is not set
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_AMD_HSMP is not set
+# CONFIG_AMD_PMC is not set
+# CONFIG_AMD_PTDMA is not set
+# CONFIG_AMD_SFH_HID is not set
+CONFIG_ARCH_CPUIDLE_HALTPOLL=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ARCH_MMAP_RND_BITS=28
+CONFIG_ARCH_MMAP_RND_BITS_MAX=32
+CONFIG_ARCH_MMAP_RND_BITS_MIN=28
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+# CONFIG_ASUS_TF103C_DOCK is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BALLOON_COMPACTION=y
+# CONFIG_BARCO_P50_GPIO is not set
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_COMPAT=y
+# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
+CONFIG_BTT=y
+CONFIG_CDROM=y
+CONFIG_COMPAT=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_CONNECTOR=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
+CONFIG_CPU_RMAP=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_AES_NI_INTEL=y
+# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set
+# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
+# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
+# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
+# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
+# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
+CONFIG_CRYPTO_LRW=y
+# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set
+# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set
+# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
+# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
+# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
+# CONFIG_CRYPTO_SHA1_SSSE3 is not set
+# CONFIG_CRYPTO_SHA512_SSSE3 is not set
+CONFIG_CRYPTO_SIMD=y
+# CONFIG_CRYPTO_SM3_AVX_X86_64 is not set
+# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set
+# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set
+# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set
+# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
+# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_XTS_AES_SYNC=y
+# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_BOCHS=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=y
+CONFIG_DRM_DP_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+# CONFIG_DRM_HYPERV is not set
+CONFIG_DRM_I915_FORCE_PROBE=""
+CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
+CONFIG_DRM_I915_FENCE_TIMEOUT=10000
+CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
+CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
+CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
+CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
+CONFIG_DRM_I915_STOP_TIMEOUT=100
+CONFIG_DRM_I915_TIMESLICE_DURATION=1
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_DRM_SSD130X is not set
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_VRAM_HELPER=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+# CONFIG_EFI_FAKE_MEMMAP is not set
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+# CONFIG_EFI_MIXED is not set
+# CONFIG_EFI_PGT_DUMP is not set
+# CONFIG_EFI_RCI2_TABLE is not set
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_FAILOVER=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_EFI=y
+CONFIG_FB_HYPERV=y
+# CONFIG_FB_INTEL is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_TILEBLITTING=y
+# CONFIG_FB_VESA is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FREEZER=y
+CONFIG_FUSION_SAS=y
+CONFIG_FW_CACHE=y
+CONFIG_GART_IOMMU=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CPU=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ACPI=y
+# CONFIG_GPIO_CASCADE is not set
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_ICH=y
+CONFIG_GPIO_SCH=y
+# CONFIG_GPIO_SIM is not set
+# CONFIG_GPIO_VIRTIO is not set
+CONFIG_GUEST_PERF_EVENTS=y
+CONFIG_HALTPOLL_CPUIDLE=y
+CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
+CONFIG_HDMI=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_HYPERV_MOUSE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HOTPLUG_SMT=y
+CONFIG_HPET=y
+CONFIG_HPET_MMAP=y
+# CONFIG_HP_ACCEL is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+CONFIG_HW_RANDOM_AMD=y
+CONFIG_HW_RANDOM_INTEL=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HYPERV=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_HYPERV_BALLOON=y
+CONFIG_HYPERV_KEYBOARD=y
+CONFIG_HYPERV_NET=y
+CONFIG_HYPERV_STORAGE=y
+# CONFIG_HYPERV_TESTING is not set
+CONFIG_HYPERV_TIMER=y
+CONFIG_HYPERV_UTILS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+# CONFIG_HYPERV_VSOCKETS is not set
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HID_ACPI is not set
+# CONFIG_IA32_EMULATION is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INTEL_GTT=y
+# CONFIG_INTEL_IDXD_COMPAT is not set
+# CONFIG_INTEL_IPS is not set
+# CONFIG_INTEL_MEI_HDCP is not set
+# CONFIG_INTEL_MEI_PXP is not set
+# CONFIG_INTEL_MENLOW is not set
+CONFIG_INTEL_PCH_THERMAL=y
+# CONFIG_INTEL_SAR_INT1092 is not set
+# CONFIG_INTEL_SCU_PLATFORM is not set
+CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
+CONFIG_INTEL_SOC_DTS_THERMAL=y
+# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set
+# CONFIG_INTEL_TURBO_MAX_3 is not set
+# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set
+CONFIG_INTERVAL_TREE=y
+# CONFIG_IOMMU_DEBUG is not set
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOSF_MBI=y
+# CONFIG_IOSF_MBI_DEBUG is not set
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_ISO9660_FS=y
+CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
+CONFIG_KCMP=y
+CONFIG_KVM_GUEST=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEGACY_VSYSCALL_EMULATE is not set
+CONFIG_LEGACY_VSYSCALL_NONE=y
+# CONFIG_LEGACY_VSYSCALL_XONLY is not set
+CONFIG_LIBNVDIMM=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LPC_ICH=y
+CONFIG_LPC_SCH=y
+CONFIG_MAILBOX=y
+# CONFIG_MAXSMP is not set
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMREGION=y
+# CONFIG_MERAKI_MX100 is not set
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_INTEL_LPSS_ACPI is not set
+# CONFIG_MFD_INTEL_PMC_BXT is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MMC_WBSD is not set
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MPSC is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_ND_CLAIM=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+# CONFIG_NITRO_ENCLAVES is not set
+CONFIG_NR_CPUS=512
+CONFIG_NR_CPUS_DEFAULT=64
+CONFIG_NR_CPUS_RANGE_BEGIN=2
+CONFIG_NR_CPUS_RANGE_END=512
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_HWMON is not set
+CONFIG_NVME_MULTIPATH=y
+# CONFIG_NVME_VERBOSE_ERRORS is not set
+CONFIG_OUTPUT_FORMAT="elf64-x86-64"
+CONFIG_PADATA=y
+CONFIG_PAGE_REPORTING=y
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_PAGE_TABLE_ISOLATION=y
+CONFIG_PARAVIRT=y
+CONFIG_PARAVIRT_CLOCK=y
+# CONFIG_PARAVIRT_DEBUG is not set
+CONFIG_PARAVIRT_SPINLOCKS=y
+CONFIG_PARAVIRT_XXL=y
+CONFIG_PATA_AMD=y
+CONFIG_PATA_ATIIXP=y
+CONFIG_PATA_MPIIX=y
+CONFIG_PATA_OLDPIIX=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PATA_VIA=y
+CONFIG_PCC=y
+# CONFIG_PCENGINES_APU2 is not set
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_HYPERV=y
+CONFIG_PCI_HYPERV_INTERFACE=y
+# CONFIG_PCI_MMCONFIG is not set
+CONFIG_PCI_XEN=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_ALDERLAKE is not set
+# CONFIG_PINCTRL_BAYTRAIL is not set
+# CONFIG_PINCTRL_BROXTON is not set
+# CONFIG_PINCTRL_CANNONLAKE is not set
+# CONFIG_PINCTRL_CHERRYVIEW is not set
+# CONFIG_PINCTRL_DENVERTON is not set
+# CONFIG_PINCTRL_ELKHARTLAKE is not set
+# CONFIG_PINCTRL_EMMITSBURG is not set
+# CONFIG_PINCTRL_GEMINILAKE is not set
+# CONFIG_PINCTRL_JASPERLAKE is not set
+# CONFIG_PINCTRL_LAKEFIELD is not set
+# CONFIG_PINCTRL_LEWISBURG is not set
+# CONFIG_PINCTRL_LYNXPOINT is not set
+# CONFIG_PINCTRL_SUNRISEPOINT is not set
+# CONFIG_PINCTRL_TIGERLAKE is not set
+CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PVH=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RAS=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SAMSUNG_Q10 is not set
+CONFIG_SATA_AHCI=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_MC_PRIO=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_VIRTIO=y
+# CONFIG_SENSORS_ASUS_EC is not set
+CONFIG_SENSORS_CORETEMP=y
+CONFIG_SENSORS_FAM15H_POWER=y
+CONFIG_SENSORS_I5500=y
+CONFIG_SENSORS_K10TEMP=y
+CONFIG_SENSORS_K8TEMP=y
+# CONFIG_SENSORS_SY7636A is not set
+# CONFIG_SENSORS_TMP464 is not set
+CONFIG_SENSORS_VIA_CPUTEMP=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+# CONFIG_SPARSEMEM_VMEMMAP is not set
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_STACK_VALIDATION=y
+CONFIG_SWIOTLB=y
+CONFIG_SWIOTLB_XEN=y
+CONFIG_SYNC_FILE=y
+# CONFIG_SYSTEM76_ACPI is not set
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+# CONFIG_UACCE is not set
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UCS2_STRING=y
+# CONFIG_UNWINDER_ORC is not set
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_XEN_HCD is not set
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+# CONFIG_VIRTIO_PMEM is not set
+# CONFIG_VIRTIO_VSOCKETS is not set
+CONFIG_VIRTIO_VSOCKETS_COMMON=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VMAP_PFN=y
+CONFIG_VMAP_STACK=y
+# CONFIG_VMD is not set
+CONFIG_VMGENID=y
+CONFIG_VMWARE_BALLOON=y
+CONFIG_VMWARE_PVSCSI=y
+CONFIG_VMWARE_VMCI=y
+CONFIG_VMWARE_VMCI_VSOCKETS=y
+CONFIG_VMXNET3=y
+CONFIG_VSOCKETS=y
+CONFIG_VSOCKETS_LOOPBACK=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WIRELESS_HOTKEY is not set
+# CONFIG_X86_5LEVEL is not set
+CONFIG_X86_64=y
+CONFIG_X86_64_SMP=y
+CONFIG_X86_ACPI_CPUFREQ=y
+# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
+CONFIG_X86_AMD_FREQ_SENSITIVITY=y
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+CONFIG_X86_AMD_PSTATE=y
+CONFIG_X86_CPUID=y
+CONFIG_X86_DIRECT_GBPAGES=y
+CONFIG_X86_HV_CALLBACK_VECTOR=y
+CONFIG_X86_INTEL_LPSS=y
+# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
+CONFIG_X86_INTEL_PSTATE=y
+# CONFIG_X86_KERNEL_IBT is not set
+CONFIG_X86_MINIMUM_CPU_FAMILY=64
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PKG_TEMP_THERMAL=y
+# CONFIG_X86_PMEM_LEGACY is not set
+CONFIG_X86_PM_TIMER=y
+# CONFIG_X86_POWERNOW_K8 is not set
+CONFIG_X86_SGX=y
+# CONFIG_X86_VSYSCALL_EMULATION is not set
+CONFIG_X86_X2APIC=y
+CONFIG_X86_X32_ABI=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XEN=y
+CONFIG_XENFS=y
+CONFIG_XEN_512GB=y
+CONFIG_XEN_ACPI=y
+CONFIG_XEN_ACPI_PROCESSOR=y
+CONFIG_XEN_AUTO_XLATE=y
+# CONFIG_XEN_BACKEND is not set
+CONFIG_XEN_BALLOON=y
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_DEBUG_FS=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN_EFI=y
+CONFIG_XEN_FBDEV_FRONTEND=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_XEN_HAVE_PVMMU=y
+CONFIG_XEN_HAVE_VPMU=y
+# CONFIG_XEN_MCE_LOG is not set
+CONFIG_XEN_NETDEV_FRONTEND=y
+CONFIG_XEN_PCIDEV_FRONTEND=y
+CONFIG_XEN_PRIVCMD=y
+CONFIG_XEN_PV=y
+CONFIG_XEN_PVH=y
+CONFIG_XEN_PVHVM=y
+CONFIG_XEN_PVHVM_GUEST=y
+CONFIG_XEN_PVHVM_SMP=y
+CONFIG_XEN_PV_DOM0=y
+CONFIG_XEN_PV_SMP=y
+CONFIG_XEN_SAVE_RESTORE=y
+CONFIG_XEN_SCSI_FRONTEND=y
+CONFIG_XEN_SYMS=y
+CONFIG_XEN_SYS_HYPERVISOR=y
+CONFIG_XEN_WDT=y
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XPS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/x86/Makefile b/target/linux/x86/Makefile
index 9a0fe21530a6ac..f18c6e1e40520e 100644
--- a/target/linux/x86/Makefile
+++ b/target/linux/x86/Makefile
@@ -11,18 +11,17 @@ FEATURES:=squashfs vdi vmdk vhdx pcmcia fpu boot-part rootfs-part
 SUBTARGETS:=64 generic legacy geode 
 
 KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.6
 
 KERNELNAME:=bzImage
 
 include $(INCLUDE_DIR)/target.mk
 
 DEFAULT_PACKAGES += partx-utils mkf2fs e2fsprogs kmod-button-hotplug kmod-usb-hid kmod-mmc kmod-sdhci kmod-fs-f2fs cfdisk usbutils pciutils \
-kmod-alx kmod-e1000e kmod-igb kmod-igc kmod-igbvf kmod-iavf kmod-bnx2x kmod-pcnet32 kmod-tulip kmod-via-velocity kmod-vmxnet3 kmod-i40e kmod-i40evf kmod-r8125 kmod-8139cp kmod-8139too kmod-tg3 \
-htop lm-sensors iperf3 autocore-x86 automount autosamba luci-app-adbyby-plus luci-app-ipsec-vpnd luci-proto-bonding luci-app-diskman \
-luci-app-unblockmusic luci-app-zerotier luci-app-xlnetacc ddns-scripts_aliyun ddns-scripts_dnspod ca-bundle luci-app-wireguard luci-app-ttyd \
-kmod-sound-hda-core kmod-sound-hda-codec-realtek kmod-sound-hda-codec-via kmod-sound-via82xx kmod-sound-hda-intel kmod-sound-hda-codec-hdmi kmod-sound-i8x0 kmod-usb-audio \
-kmod-usb-net kmod-usb-net-asix-ax88179 kmod-usb-net-rtl8150 kmod-usb-net-rtl8152-vendor kmod-usb-net-aqc111 kmod-mlx4-core kmod-mlx5-core kmod-drm-i915 kmod-drm-amdgpu
+kmod-alx kmod-e1000e kmod-igb kmod-igc kmod-igbvf kmod-iavf kmod-bnx2x kmod-pcnet32 kmod-tulip kmod-via-velocity kmod-vmxnet3 kmod-i40e kmod-i40evf \
+kmod-sound-hda-core kmod-sound-hda-codec-realtek kmod-sound-hda-codec-via kmod-sound-via82xx kmod-sound-hda-intel kmod-sound-hda-codec-hdmi kmod-sound-i8x0 \
+kmod-usb-net kmod-usb-net-asix-ax88179 kmod-usb-net-rtl8150 kmod-usb-net-aqc111 kmod-mlx4-core kmod-mlx5-core kmod-drm-i915 kmod-drm-amdgpu kmod-usb-audio \
+kmod-usb-net-rtl8152-vendor kmod-r8125 kmod-r8168 kmod-8139cp kmod-8139too kmod-tg3 htop lm-sensors iperf3-ssl autocore-x86 automount autosamba ca-bundle
 
 $(eval $(call BuildTarget))
 
diff --git a/target/linux/x86/config-6.6 b/target/linux/x86/config-6.6
new file mode 100644
index 00000000000000..b52a35aca208ab
--- /dev/null
+++ b/target/linux/x86/config-6.6
@@ -0,0 +1,570 @@
+# CONFIG_60XX_WDT is not set
+# CONFIG_64BIT is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+# CONFIG_ACPI_CMPC is not set
+# CONFIG_ACPI_CONTAINER is not set
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_DPTF is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_TINY_POWER_BUTTON is not set
+# CONFIG_ACPI_WMI is not set
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_ALIM1535_WDT is not set
+# CONFIG_ALIX is not set
+CONFIG_AMD_NB=y
+# CONFIG_AMD_PMC is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_NR_GPIO=512
+CONFIG_ARCH_RANDOM=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPLIT_ARG64=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USES_PG_UNCACHED=y
+CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ATA=y
+CONFIG_ATA_GENERIC=y
+CONFIG_ATA_PIIX=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKSRC_I8253=y
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPAT_32=y
+CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_COMPAT_VDSO is not set
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_CPU5_WDT is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_CENTAUR=y
+CONFIG_CPU_SUP_CYRIX_32=y
+CONFIG_CPU_SUP_HYGON=y
+CONFIG_CPU_SUP_INTEL=y
+CONFIG_CPU_SUP_TRANSMETA_32=y
+CONFIG_CPU_SUP_UMC_32=y
+CONFIG_CPU_SUP_VORTEX_32=y
+CONFIG_CPU_SUP_ZHAOXIN=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32_PCLMUL is not set
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
+# CONFIG_CX_ECAT is not set
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_DEBUG_BOOT_PARAMS is not set
+# CONFIG_DEBUG_ENTRY is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MISC=y
+# CONFIG_DEBUG_NMI_SELFTEST is not set
+# CONFIG_DEBUG_TLBFLUSH is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DYNAMIC_SIGFRAME=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EARLY_PRINTK_DBGP is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDD is not set
+# CONFIG_EISA is not set
+# CONFIG_EUROTECH_WDT is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+# CONFIG_F71808E_WDT is not set
+CONFIG_FB_CMDLINE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUSION=y
+# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION_LOGGING is not set
+CONFIG_FUSION_MAX_SGE=128
+CONFIG_FUSION_SPI=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC12_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+# CONFIG_GEOS is not set
+CONFIG_GLOB=y
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHMEM4G=y
+# CONFIG_HIGHMEM64G is not set
+# CONFIG_HIGHPTE is not set
+# CONFIG_HPET is not set
+CONFIG_HPET_EMULATE_RTC=y
+CONFIG_HPET_TIMER=y
+# CONFIG_HP_ACCEL is not set
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIA=y
+# CONFIG_HYPERVISOR_GUEST is not set
+CONFIG_HZ_PERIODIC=y
+CONFIG_HYPERV=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_HYPERV_BALLOON=y
+CONFIG_HYPERV_KEYBOARD=y
+CONFIG_HYPERV_NET=y
+CONFIG_HYPERV_STORAGE=y
+# CONFIG_HYPERV_TESTING is not set
+CONFIG_HYPERV_TIMER=y
+CONFIG_HYPERV_UTILS=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_HYPERV_VSOCKETS is not set
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HID_ACPI is not set
+CONFIG_I8253_LOCK=y
+CONFIG_IA32_FEAT_CTL=y
+# CONFIG_IB700_WDT is not set
+# CONFIG_IBMASR is not set
+# CONFIG_IBM_RTL is not set
+# CONFIG_IE6XX_WDT is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INSTRUCTION_DECODER=y
+# CONFIG_INTEL_HFI_THERMAL is not set
+# CONFIG_INTEL_IPS is not set
+# CONFIG_INTEL_LDMA is not set
+# CONFIG_INTEL_MENLOW is not set
+# CONFIG_INTEL_PCH_THERMAL is not set
+# CONFIG_INTEL_POWERCLAMP is not set
+# CONFIG_INTEL_SAR_INT1092 is not set
+# CONFIG_INTEL_SCU_PCI is not set
+# CONFIG_INTEL_SCU_PLATFORM is not set
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+# CONFIG_INTEL_VSEC is not set
+# CONFIG_IOSF_MBI is not set
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_NONE is not set
+# CONFIG_IO_DELAY_UDELAY is not set
+CONFIG_IO_URING=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISA is not set
+CONFIG_ISA_DMA_API=y
+# CONFIG_ISCSI_IBFT is not set
+# CONFIG_IT8712F_WDT is not set
+# CONFIG_IT87_WDT is not set
+# CONFIG_ITCO_WDT is not set
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KMAP_LOCAL=y
+# CONFIG_LEDS_CLEVO_MAIL is not set
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_M486 is not set
+# CONFIG_M486SX is not set
+# CONFIG_M586 is not set
+# CONFIG_M586MMX is not set
+# CONFIG_M586TSC is not set
+CONFIG_M686=y
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_MATOM is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MCRUSOE is not set
+# CONFIG_MCYRIXIII is not set
+# CONFIG_MEFFICEON is not set
+# CONFIG_MELAN is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_INTEL_LPSS_ACPI is not set
+# CONFIG_MFD_INTEL_LPSS_PCI is not set
+# CONFIG_MFD_INTEL_PMC_BXT is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+# CONFIG_MGEODEGX1 is not set
+# CONFIG_MGEODE_LX is not set
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_AMD=y
+CONFIG_MICROCODE_INTEL=y
+# CONFIG_MICROCODE_LATE_LOADING is not set
+CONFIG_MIGRATION=y
+# CONFIG_MK6 is not set
+# CONFIG_MK7 is not set
+# CONFIG_MK8 is not set
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+# CONFIG_MODIFY_LDT_SYSCALL is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MPENTIUM4 is not set
+# CONFIG_MPENTIUMII is not set
+# CONFIG_MPENTIUMIII is not set
+# CONFIG_MPENTIUMM is not set
+# CONFIG_MTD is not set
+CONFIG_MTRR=y
+# CONFIG_MTRR_SANITIZER is not set
+# CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
+# CONFIG_MWINCHIP3D is not set
+# CONFIG_MWINCHIPC6 is not set
+CONFIG_NAMESPACES=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+# CONFIG_NET5501 is not set
+# CONFIG_NET_NS is not set
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_NLS=y
+# CONFIG_NOHIGHMEM is not set
+CONFIG_NR_CPUS=1
+CONFIG_NR_CPUS_DEFAULT=1
+CONFIG_NR_CPUS_RANGE_BEGIN=1
+CONFIG_NR_CPUS_RANGE_END=1
+# CONFIG_NSC_GPIO is not set
+CONFIG_NVRAM=y
+# CONFIG_OF is not set
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_OLPC is not set
+CONFIG_OUTPUT_FORMAT="elf32-i386"
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_VERSION=0
+CONFIG_PC104=y
+# CONFIG_PC8736x_GPIO is not set
+# CONFIG_PC87413_WDT is not set
+CONFIG_PCI=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_BIOS=y
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_GOANY=y
+# CONFIG_PCI_GOBIOS is not set
+# CONFIG_PCI_GODIRECT is not set
+# CONFIG_PCI_GOMMCONFIG is not set
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOCKLESS_CONFIG=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_EVENTS_AMD_BRS=y
+CONFIG_PERF_EVENTS_AMD_POWER=y
+CONFIG_PERF_EVENTS_AMD_UNCORE=y
+CONFIG_PERF_EVENTS_INTEL_CSTATE=y
+CONFIG_PERF_EVENTS_INTEL_RAPL=y
+CONFIG_PERF_EVENTS_INTEL_UNCORE=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYSICAL_ALIGN=0x200000
+CONFIG_PHYSICAL_START=0x1000000
+# CONFIG_PHY_INTEL_LGM_EMMC is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_ALDERLAKE is not set
+# CONFIG_PINCTRL_BAYTRAIL is not set
+# CONFIG_PINCTRL_BROXTON is not set
+# CONFIG_PINCTRL_CANNONLAKE is not set
+# CONFIG_PINCTRL_CHERRYVIEW is not set
+# CONFIG_PINCTRL_DENVERTON is not set
+# CONFIG_PINCTRL_ELKHARTLAKE is not set
+# CONFIG_PINCTRL_EMMITSBURG is not set
+# CONFIG_PINCTRL_GEMINILAKE is not set
+# CONFIG_PINCTRL_JASPERLAKE is not set
+# CONFIG_PINCTRL_LAKEFIELD is not set
+# CONFIG_PINCTRL_LEWISBURG is not set
+# CONFIG_PINCTRL_LYNXPOINT is not set
+# CONFIG_PINCTRL_SUNRISEPOINT is not set
+# CONFIG_PINCTRL_TIGERLAKE is not set
+CONFIG_PMC_ATOM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPT_RCU=y
+# CONFIG_PROCESSOR_SELECT is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_ARCH_STATUS=y
+# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
+# CONFIG_PUNIT_ATOM_DEBUG is not set
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+# CONFIG_RETHUNK is not set
+CONFIG_RETPOLINE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTS5139=y
+# CONFIG_RTS5139_DEBUG is not set
+# CONFIG_SAMSUNG_Q10 is not set
+CONFIG_SATA_HOST=y
+# CONFIG_SBC7240_WDT is not set
+# CONFIG_SBC8360_WDT is not set
+# CONFIG_SBC_EPX_C3_WATCHDOG is not set
+# CONFIG_SC1200_WDT is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCx200 is not set
+# CONFIG_SENSORS_ASUS_EC is not set
+CONFIG_SENSORS_FAM15H_POWER=y
+CONFIG_SENSORS_K10TEMP=y
+# CONFIG_SENSORS_SY7636A is not set
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PNP=y
+# CONFIG_SERIAL_LANTIQ is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+# CONFIG_SHORTCUT_FE is not set
+# CONFIG_SIEMENS_SIMATIC_IPC is not set
+# CONFIG_SMSC37B787_WDT is not set
+# CONFIG_SMSC_SCH311X_WDT is not set
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPECULATION_MITIGATIONS=y
+CONFIG_SRCU=y
+# CONFIG_STATIC_CALL_SELFTEST is not set
+# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+# CONFIG_SYSTEM76_ACPI is not set
+# CONFIG_TELCLOCK is not set
+# CONFIG_TEST_FPU is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_TOSHIBA is not set
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+# CONFIG_TQMX86_WDT is not set
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNWINDER_FRAME_POINTER=y
+# CONFIG_UNWINDER_GUESS is not set
+CONFIG_UP_LATE_INIT=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+# CONFIG_USER_NS is not set
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VIA_WDT is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WAFER_WDT is not set
+# CONFIG_WINMATE_FM07_KEYS is not set
+# CONFIG_WIRELESS_HOTKEY is not set
+CONFIG_X86=y
+CONFIG_X86_32=y
+# CONFIG_X86_32_IRIS is not set
+CONFIG_X86_ACPI_CPUFREQ=y
+CONFIG_X86_ACPI_CPUFREQ_CPB=y
+CONFIG_X86_AMD_FREQ_SENSITIVITY=y
+CONFIG_X86_AMD_PLATFORM_DEVICE=y
+CONFIG_X86_AMD_PSTATE=y
+# CONFIG_X86_ANCIENT_MCE is not set
+# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
+CONFIG_X86_CMOV=y
+CONFIG_X86_CMPXCHG64=y
+# CONFIG_X86_CPA_STATISTICS is not set
+# CONFIG_X86_CPUFREQ_NFORCE2 is not set
+# CONFIG_X86_CPUID is not set
+# CONFIG_X86_CPU_RESCTRL is not set
+CONFIG_X86_DEBUGCTLMSR=y
+# CONFIG_X86_DEBUG_FPU is not set
+# CONFIG_X86_DECODER_SELFTEST is not set
+# CONFIG_X86_EXTENDED_PLATFORM is not set
+# CONFIG_X86_E_POWERSAVER is not set
+CONFIG_X86_FEATURE_NAMES=y
+# CONFIG_X86_GENERIC is not set
+# CONFIG_X86_GX_SUSPMOD is not set
+# CONFIG_X86_INTEL_LPSS is not set
+# CONFIG_X86_INTEL_PSTATE is not set
+# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
+CONFIG_X86_INTEL_TSX_MODE_OFF=y
+# CONFIG_X86_INTEL_TSX_MODE_ON is not set
+CONFIG_X86_INTERNODE_CACHE_SHIFT=5
+CONFIG_X86_IOPL_IOPERM=y
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_L1_CACHE_SHIFT=5
+# CONFIG_X86_LEGACY_VM86 is not set
+CONFIG_X86_LOCAL_APIC=y
+# CONFIG_X86_LONGHAUL is not set
+# CONFIG_X86_LONGRUN is not set
+CONFIG_X86_MCE=y
+# CONFIG_X86_MCELOG_LEGACY is not set
+CONFIG_X86_MCE_AMD=y
+# CONFIG_X86_MCE_INJECT is not set
+CONFIG_X86_MCE_INTEL=y
+CONFIG_X86_MCE_THRESHOLD=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=6
+CONFIG_X86_MPPARSE=y
+CONFIG_X86_MSR=y
+# CONFIG_X86_P4_CLOCKMOD is not set
+CONFIG_X86_PAT=y
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PLATFORM_DEVICES=y
+# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
+CONFIG_X86_PM_TIMER=y
+# CONFIG_X86_POWERNOW_K6 is not set
+# CONFIG_X86_POWERNOW_K7 is not set
+# CONFIG_X86_POWERNOW_K8 is not set
+# CONFIG_X86_REBOOTFIXUPS is not set
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
+# CONFIG_X86_SPEEDSTEP_ICH is not set
+# CONFIG_X86_SPEEDSTEP_SMI is not set
+CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_X86_THERMAL_VECTOR=y
+CONFIG_X86_TSC=y
+CONFIG_X86_UMIP=y
+CONFIG_X86_UP_APIC=y
+# CONFIG_X86_UP_IOAPIC is not set
+CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_VERBOSE_BOOTUP=y
+CONFIG_X86_VMX_FEATURE_NAMES=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/x86/generic/config-6.6 b/target/linux/x86/generic/config-6.6
new file mode 100644
index 00000000000000..e46fc01eea568f
--- /dev/null
+++ b/target/linux/x86/generic/config-6.6
@@ -0,0 +1,476 @@
+# CONFIG_3C515 is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+# CONFIG_ACPI_BGRT is not set
+CONFIG_ACPI_BUTTON=y
+# CONFIG_ACPI_CMPC is not set
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_DPTF is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+# CONFIG_ACPI_FAN is not set
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_I2C_OPREGION is not set
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TAD=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+# CONFIG_ACPI_WMI is not set
+CONFIG_AGP=y
+# CONFIG_AGP_ALI is not set
+# CONFIG_AGP_AMD is not set
+# CONFIG_AGP_AMD64 is not set
+# CONFIG_AGP_ATI is not set
+# CONFIG_AGP_EFFICEON is not set
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_NVIDIA is not set
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_SWORKS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_AMD_PMC is not set
+# CONFIG_APM is not set
+CONFIG_ARCH_CPUIDLE_HALTPOLL=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+# CONFIG_ASUS_TF103C_DOCK is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BALLOON_COMPACTION=y
+# CONFIG_BARCO_P50_GPIO is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
+CONFIG_BTT=y
+CONFIG_CDROM=y
+CONFIG_CONNECTOR=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_RMAP=y
+# CONFIG_CS89x0_ISA is not set
+# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_BOCHS=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=y
+CONFIG_DRM_DP_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+# CONFIG_DRM_HYPERV is not set
+CONFIG_DRM_I915=y
+CONFIG_DRM_I915_CAPTURE_ERROR=y
+CONFIG_DRM_I915_COMPRESS_ERROR=y
+# CONFIG_DRM_I915_DEBUG is not set
+# CONFIG_DRM_I915_DEBUG_GUC is not set
+# CONFIG_DRM_I915_DEBUG_MMIO is not set
+# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
+# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
+CONFIG_DRM_I915_FENCE_TIMEOUT=10000
+CONFIG_DRM_I915_FORCE_PROBE=""
+CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
+# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
+CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
+CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
+CONFIG_DRM_I915_PXP=y
+# CONFIG_DRM_I915_SELFTEST is not set
+CONFIG_DRM_I915_STOP_TIMEOUT=100
+# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
+# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
+CONFIG_DRM_I915_TIMESLICE_DURATION=1
+CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
+CONFIG_DRM_I915_USERPTR=y
+# CONFIG_DRM_I915_WERROR is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_DRM_SSD130X is not set
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_VRAM_HELPER=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set
+# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+# CONFIG_EFI_FAKE_MEMMAP is not set
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+# CONFIG_EFI_PGT_DUMP is not set
+# CONFIG_EFI_RCI2_TABLE is not set
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_EL3 is not set
+CONFIG_FAILOVER=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_EFI=y
+CONFIG_FB_HYPERV=y
+# CONFIG_FB_I810 is not set
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_VESA is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FREEZER=y
+CONFIG_FW_CACHE=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_CASCADE=y
+CONFIG_GPIO_CDEV=y
+# CONFIG_GPIO_SIM is not set
+CONFIG_GPIO_VIRTIO=y
+CONFIG_GUEST_PERF_EVENTS=y
+CONFIG_GUP_GET_PTE_LOW_HIGH=y
+CONFIG_HALTPOLL_CPUIDLE=y
+CONFIG_HDMI=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_HYPERV_MOUSE=y
+# CONFIG_HIGHMEM4G is not set
+CONFIG_HIGHMEM64G=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_COMPAQ is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_IBM is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HOTPLUG_SMT=y
+CONFIG_HPET=y
+CONFIG_HPET_MMAP=y
+# CONFIG_HP_ACCEL is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HYPERV=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_HYPERV_BALLOON=y
+CONFIG_HYPERV_KEYBOARD=y
+CONFIG_HYPERV_NET=y
+CONFIG_HYPERV_STORAGE=y
+# CONFIG_HYPERV_TESTING is not set
+CONFIG_HYPERV_TIMER=y
+CONFIG_HYPERV_UTILS=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HID_ACPI is not set
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INTEL_GTT=y
+CONFIG_INTEL_IDLE=y
+# CONFIG_INTEL_IPS is not set
+CONFIG_INTEL_MEI=y
+# CONFIG_INTEL_MEI_HDCP is not set
+CONFIG_INTEL_MEI_ME=y
+CONFIG_INTEL_MEI_PXP=y
+# CONFIG_INTEL_MEI_WDT is not set
+# CONFIG_INTEL_MENLOW is not set
+CONFIG_INTEL_PCH_THERMAL=y
+# CONFIG_INTEL_SAR_INT1092 is not set
+# CONFIG_INTEL_SCU_PLATFORM is not set
+CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
+CONFIG_INTEL_SOC_DTS_THERMAL=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_IOSF_MBI=y
+# CONFIG_IOSF_MBI_DEBUG is not set
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_ISA=y
+CONFIG_ISAPNP=y
+CONFIG_ISA_BUS_API=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+CONFIG_KCMP=y
+CONFIG_KVM=y
+CONFIG_KVM_AMD=y
+CONFIG_KVM_ASYNC_PF=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_GUEST=y
+CONFIG_KVM_INTEL=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+# CONFIG_KVM_XEN is not set
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+# CONFIG_LANCE is not set
+CONFIG_LIBNVDIMM=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+# CONFIG_M686 is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMREGION=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_INTEL_LPSS=y
+CONFIG_MFD_INTEL_LPSS_ACPI=y
+# CONFIG_MFD_INTEL_PMC_BXT is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+# CONFIG_MIXCOMWD is not set
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MMC_WBSD is not set
+CONFIG_MMU_NOTIFIER=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+# CONFIG_MOUSE_PS2_BYD is not set
+# CONFIG_MOUSE_PS2_CYPRESS is not set
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_VMMOUSE is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MPENTIUM4=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_MUX_ADG792A is not set
+# CONFIG_MUX_GPIO is not set
+CONFIG_ND_CLAIM=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NO_HZ=y
+CONFIG_NR_CPUS=4
+CONFIG_NR_CPUS_DEFAULT=8
+CONFIG_NR_CPUS_RANGE_BEGIN=2
+CONFIG_NR_CPUS_RANGE_END=8
+CONFIG_PADATA=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_TABLE_ISOLATION=y
+CONFIG_PARAVIRT=y
+CONFIG_PARAVIRT_CLOCK=y
+# CONFIG_PARAVIRT_DEBUG is not set
+CONFIG_PARAVIRT_SPINLOCKS=y
+CONFIG_PATA_AMD=y
+CONFIG_PATA_ATIIXP=y
+CONFIG_PATA_MPIIX=y
+CONFIG_PATA_OLDPIIX=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_SC1200=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PATA_VIA=y
+# CONFIG_PCENGINES_APU2 is not set
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_XEN=y
+# CONFIG_PCWATCHDOG is not set
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_ALDERLAKE is not set
+CONFIG_PINCTRL_BAYTRAIL=y
+CONFIG_PINCTRL_BROXTON=y
+CONFIG_PINCTRL_CANNONLAKE=y
+CONFIG_PINCTRL_CHERRYVIEW=y
+CONFIG_PINCTRL_DENVERTON=y
+# CONFIG_PINCTRL_ELKHARTLAKE is not set
+# CONFIG_PINCTRL_EMMITSBURG is not set
+CONFIG_PINCTRL_GEMINILAKE=y
+CONFIG_PINCTRL_INTEL=y
+# CONFIG_PINCTRL_JASPERLAKE is not set
+# CONFIG_PINCTRL_LAKEFIELD is not set
+# CONFIG_PINCTRL_LEWISBURG is not set
+# CONFIG_PINCTRL_LYNXPOINT is not set
+CONFIG_PINCTRL_SUNRISEPOINT=y
+# CONFIG_PINCTRL_TIGERLAKE is not set
+CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+# CONFIG_PNPBIOS is not set
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PVH=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RAS=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SAMSUNG_Q10 is not set
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_VIA=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_SMT=y
+# CONFIG_SCSI_FDOMAIN_ISA is not set
+CONFIG_SCSI_VIRTIO=y
+# CONFIG_SENSORS_ASUS_EC is not set
+CONFIG_SENSORS_CORETEMP=y
+CONFIG_SENSORS_FAM15H_POWER=y
+CONFIG_SENSORS_I5500=y
+CONFIG_SENSORS_K10TEMP=y
+CONFIG_SENSORS_K8TEMP=y
+# CONFIG_SENSORS_SY7636A is not set
+# CONFIG_SENSORS_TMP464 is not set
+CONFIG_SENSORS_VIA_CPUTEMP=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SWIOTLB=y
+CONFIG_SYNC_FILE=y
+# CONFIG_SYSTEM76_ACPI is not set
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UCS2_STRING=y
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_XEN_HCD is not set
+CONFIG_USER_RETURN_NOTIFIER=y
+CONFIG_VHOST=y
+CONFIG_VHOST_IOTLB=y
+CONFIG_VHOST_NET=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+# CONFIG_VIRTIO_PMEM is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_VMAP_PFN=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WDT is not set
+# CONFIG_WIRELESS_HOTKEY is not set
+CONFIG_X86_32_SMP=y
+CONFIG_X86_ACPI_CPUFREQ=y
+# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
+CONFIG_X86_AMD_FREQ_SENSITIVITY=y
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+CONFIG_X86_AMD_PSTATE=y
+# CONFIG_X86_BIGSMP is not set
+CONFIG_X86_CPUID=y
+# CONFIG_X86_E_POWERSAVER is not set
+CONFIG_X86_HV_CALLBACK_VECTOR=y
+CONFIG_X86_INTEL_LPSS=y
+CONFIG_X86_INTEL_PSTATE=y
+CONFIG_X86_INTERNODE_CACHE_SHIFT=7
+CONFIG_X86_L1_CACHE_SHIFT=7
+# CONFIG_X86_LONGHAUL is not set
+CONFIG_X86_NEED_RELOCS=y
+CONFIG_X86_PAE=y
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PKG_TEMP_THERMAL=y
+# CONFIG_X86_PMEM_LEGACY is not set
+CONFIG_X86_PM_TIMER=y
+# CONFIG_X86_POWERNOW_K8 is not set
+CONFIG_XEN=y
+CONFIG_XENFS=y
+CONFIG_XEN_ACPI=y
+CONFIG_XEN_AUTO_XLATE=y
+# CONFIG_XEN_BACKEND is not set
+CONFIG_XEN_BALLOON=y
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_DEBUG_FS=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_FBDEV_FRONTEND=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_XEN_NETDEV_FRONTEND=y
+CONFIG_XEN_PRIVCMD=y
+CONFIG_XEN_PVH=y
+CONFIG_XEN_PVHVM=y
+CONFIG_XEN_PVHVM_GUEST=y
+CONFIG_XEN_PVHVM_SMP=y
+CONFIG_XEN_SAVE_RESTORE=y
+CONFIG_XEN_SCSI_FRONTEND=y
+CONFIG_XEN_SYS_HYPERVISOR=y
+CONFIG_XEN_WDT=y
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XPS=y
+CONFIG_ZLIB_DEFLATE=y
diff --git a/target/linux/x86/geode/config-6.6 b/target/linux/x86/geode/config-6.6
new file mode 100644
index 00000000000000..465fd617d88fcb
--- /dev/null
+++ b/target/linux/x86/geode/config-6.6
@@ -0,0 +1,150 @@
+# CONFIG_3C515 is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+CONFIG_8139TOO_8129=y
+CONFIG_8139TOO_PIO=y
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+# CONFIG_ACPI_BATTERY is not set
+# CONFIG_ACPI_CMPC is not set
+# CONFIG_ACPI_CONTAINER is not set
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_DPTF is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_TINY_POWER_BUTTON is not set
+# CONFIG_ACPI_WMI is not set
+CONFIG_ALIX=y
+# CONFIG_AMD_PMC is not set
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+# CONFIG_ASUS_TF103C_DOCK is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_BARCO_P50_GPIO is not set
+CONFIG_CS5535_CLOCK_EVENT_SRC=y
+CONFIG_CS5535_MFGPT=y
+CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
+# CONFIG_CS89x0_ISA is not set
+CONFIG_DMA_ACPI=y
+# CONFIG_EL3 is not set
+CONFIG_GEODE_WDT=y
+CONFIG_GEOS=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_ACPI=y
+# CONFIG_GPIO_CASCADE is not set
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CS5535=y
+# CONFIG_GPIO_SIM is not set
+# CONFIG_HPET is not set
+# CONFIG_HP_ACCEL is not set
+CONFIG_HWMON=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALGOPCA=y
+CONFIG_I2C_ALGOPCF=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HID_ACPI is not set
+# CONFIG_INTEL_IPS is not set
+# CONFIG_INTEL_MENLOW is not set
+# CONFIG_INTEL_SAR_INT1092 is not set
+# CONFIG_INTEL_SCU_PLATFORM is not set
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+CONFIG_IOSF_MBI=y
+# CONFIG_IOSF_MBI_DEBUG is not set
+CONFIG_ISA=y
+# CONFIG_ISAPNP is not set
+CONFIG_ISA_BUS_API=y
+# CONFIG_ISCSI_IBFT is not set
+# CONFIG_LANCE is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_M686 is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CS5535=y
+# CONFIG_MFD_INTEL_LPSS_ACPI is not set
+# CONFIG_MFD_INTEL_PMC_BXT is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+CONFIG_MGEODEGX1=y
+# CONFIG_MIXCOMWD is not set
+CONFIG_NATSEMI=y
+CONFIG_NET5501=y
+CONFIG_NSC_GPIO=y
+CONFIG_PATA_CS5520=y
+CONFIG_PATA_CS5530=y
+CONFIG_PATA_CS5535=y
+CONFIG_PATA_CS5536=y
+CONFIG_PATA_SC1200=y
+CONFIG_PC8736x_GPIO=y
+# CONFIG_PCENGINES_APU2 is not set
+CONFIG_PCI_MMCONFIG=y
+# CONFIG_PCWATCHDOG is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_ALDERLAKE is not set
+# CONFIG_PINCTRL_BAYTRAIL is not set
+# CONFIG_PINCTRL_BROXTON is not set
+# CONFIG_PINCTRL_CANNONLAKE is not set
+# CONFIG_PINCTRL_CHERRYVIEW is not set
+# CONFIG_PINCTRL_DENVERTON is not set
+# CONFIG_PINCTRL_ELKHARTLAKE is not set
+# CONFIG_PINCTRL_EMMITSBURG is not set
+# CONFIG_PINCTRL_GEMINILAKE is not set
+# CONFIG_PINCTRL_JASPERLAKE is not set
+# CONFIG_PINCTRL_LAKEFIELD is not set
+# CONFIG_PINCTRL_LEWISBURG is not set
+# CONFIG_PINCTRL_LYNXPOINT is not set
+# CONFIG_PINCTRL_SUNRISEPOINT is not set
+# CONFIG_PINCTRL_TIGERLAKE is not set
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+# CONFIG_PNPBIOS is not set
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_SAMSUNG_Q10 is not set
+CONFIG_SC1200_WDT=y
+# CONFIG_SCSI_FDOMAIN_ISA is not set
+CONFIG_SCx200_ACB=y
+CONFIG_SCx200_WDT=y
+# CONFIG_SENSORS_ASUS_EC is not set
+CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_SY7636A is not set
+# CONFIG_SENSORS_TMP464 is not set
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_VIA_RHINE=y
+CONFIG_VIA_RHINE_MMIO=y
+# CONFIG_WDT is not set
+# CONFIG_WIRELESS_HOTKEY is not set
+# CONFIG_X86_ACPI_CPUFREQ is not set
+CONFIG_X86_ALIGNMENT_16=y
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+CONFIG_X86_AMD_PSTATE=y
+CONFIG_X86_CPUID=y
+# CONFIG_X86_E_POWERSAVER is not set
+CONFIG_X86_INTEL_LPSS=y
+# CONFIG_X86_LONGHAUL is not set
+# CONFIG_X86_MCE is not set
+CONFIG_X86_MINIMUM_CPU_FAMILY=5
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PM_TIMER=y
+CONFIG_X86_REBOOTFIXUPS=y
diff --git a/target/linux/x86/image/64.mk b/target/linux/x86/image/64.mk
index 75969666f3c8c9..25090ea15059a4 100644
--- a/target/linux/x86/image/64.mk
+++ b/target/linux/x86/image/64.mk
@@ -1,8 +1,9 @@
 define Device/generic
   DEVICE_VENDOR := Generic
   DEVICE_MODEL := x86/64
-  DEVICE_PACKAGES += kmod-amazon-ena kmod-bnx2 kmod-e1000e kmod-e1000 \
-	kmod-forcedeth kmod-ixgbe kmod-amd-xgbe kmod-r8168 kmod-fs-vfat
+  DEVICE_PACKAGES += kmod-amazon-ena kmod-amd-xgbe kmod-bnx2 \
+	kmod-e1000e kmod-e1000 kmod-forcedeth kmod-fs-vfat \
+	kmod-igb kmod-igc kmod-ixgbe kmod-r8168 kmod-tg3
   GRUB2_VARIANT := generic
 endef
 TARGET_DEVICES += generic
diff --git a/target/linux/x86/legacy/config-6.6 b/target/linux/x86/legacy/config-6.6
new file mode 100644
index 00000000000000..f159d79c4c8060
--- /dev/null
+++ b/target/linux/x86/legacy/config-6.6
@@ -0,0 +1,230 @@
+# CONFIG_3C515 is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+# CONFIG_ACPI_CMPC is not set
+# CONFIG_ACPI_CONTAINER is not set
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_DPTF is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+# CONFIG_ACPI_FAN is not set
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_I2C_OPREGION is not set
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_SBS is not set
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+# CONFIG_ACPI_WMI is not set
+CONFIG_AGP=y
+# CONFIG_AGP_ALI is not set
+# CONFIG_AGP_AMD is not set
+# CONFIG_AGP_AMD64 is not set
+# CONFIG_AGP_ATI is not set
+# CONFIG_AGP_EFFICEON is not set
+CONFIG_AGP_INTEL=y
+# CONFIG_AGP_NVIDIA is not set
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_SWORKS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_AMD_PMC is not set
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CDROM=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CS89x0_ISA is not set
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_AMDGPU=y
+# CONFIG_DRM_AMD_DC is not set
+CONFIG_DRM_BOCHS=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=y
+CONFIG_DRM_DP_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_I915=y
+CONFIG_DRM_I915_CAPTURE_ERROR=y
+CONFIG_DRM_I915_COMPRESS_ERROR=y
+# CONFIG_DRM_I915_DEBUG is not set
+# CONFIG_DRM_I915_DEBUG_GUC is not set
+# CONFIG_DRM_I915_DEBUG_MMIO is not set
+# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
+# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
+CONFIG_DRM_I915_FENCE_TIMEOUT=10000
+CONFIG_DRM_I915_FORCE_PROBE=""
+CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
+# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
+CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
+CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
+# CONFIG_DRM_I915_SELFTEST is not set
+CONFIG_DRM_I915_STOP_TIMEOUT=100
+# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
+# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
+CONFIG_DRM_I915_TIMESLICE_DURATION=1
+CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
+CONFIG_DRM_I915_USERPTR=y
+# CONFIG_DRM_I915_WERROR is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_RADEON=y
+CONFIG_DRM_SCHED=y
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_DRM_SSD130X is not set
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+CONFIG_DRM_VRAM_HELPER=y
+# CONFIG_EL3 is not set
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_I810 is not set
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_VESA is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_HDMI=y
+CONFIG_HID_BATTERY_STRENGTH=y
+# CONFIG_HIGHMEM4G is not set
+CONFIG_HPET=y
+CONFIG_HPET_MMAP=y
+# CONFIG_HP_ACCEL is not set
+CONFIG_HWMON=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HID_ACPI is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INTEL_GTT=y
+CONFIG_INTEL_IDLE=y
+# CONFIG_INTEL_IPS is not set
+# CONFIG_INTEL_MEI_HDCP is not set
+# CONFIG_INTEL_MEI_PXP is not set
+# CONFIG_INTEL_MENLOW is not set
+# CONFIG_INTEL_SAR_INT1092 is not set
+# CONFIG_INTEL_SCU_PLATFORM is not set
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+CONFIG_INTERVAL_TREE=y
+CONFIG_IOSF_MBI=y
+# CONFIG_IOSF_MBI_DEBUG is not set
+CONFIG_ISA=y
+CONFIG_ISAPNP=y
+CONFIG_ISA_BUS_API=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+CONFIG_KCMP=y
+# CONFIG_LANCE is not set
+CONFIG_M586MMX=y
+# CONFIG_M686 is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_INTEL_LPSS=y
+CONFIG_MFD_INTEL_LPSS_ACPI=y
+# CONFIG_MFD_INTEL_PMC_BXT is not set
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+# CONFIG_MIXCOMWD is not set
+CONFIG_MMU_NOTIFIER=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+# CONFIG_MOUSE_PS2_BYD is not set
+# CONFIG_MOUSE_PS2_CYPRESS is not set
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_NOHIGHMEM=y
+CONFIG_NO_HZ=y
+CONFIG_PATA_AMD=y
+CONFIG_PATA_ATIIXP=y
+CONFIG_PATA_LEGACY=y
+CONFIG_PATA_MPIIX=y
+CONFIG_PATA_OLDPIIX=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_SC1200=y
+CONFIG_PATA_SIS=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PATA_VIA=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_MMCONFIG=y
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+# CONFIG_PNPBIOS is not set
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_RAS=y
+CONFIG_RELAY=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_SAMSUNG_Q10 is not set
+CONFIG_SATA_AHCI=y
+# CONFIG_SCSI_FDOMAIN_ISA is not set
+# CONFIG_SENSORS_ASUS_EC is not set
+# CONFIG_SENSORS_SY7636A is not set
+# CONFIG_SENSORS_TMP464 is not set
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SYNC_FILE=y
+# CONFIG_SYSTEM76_ACPI is not set
+# CONFIG_TOSHIBA_BT_RFKILL is not set
+CONFIG_USB_STORAGE=y
+CONFIG_VMAP_PFN=y
+# CONFIG_WDT is not set
+# CONFIG_WIRELESS_HOTKEY is not set
+CONFIG_X86_ACPI_CPUFREQ=y
+# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
+CONFIG_X86_ALIGNMENT_16=y
+# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+CONFIG_X86_AMD_PSTATE=y
+# CONFIG_X86_E_POWERSAVER is not set
+CONFIG_X86_F00F_BUG=y
+# CONFIG_X86_INTEL_LPSS is not set
+# CONFIG_X86_LONGHAUL is not set
+CONFIG_X86_MINIMUM_CPU_FAMILY=5
+# CONFIG_X86_PAE is not set
+# CONFIG_X86_PCC_CPUFREQ is not set
+CONFIG_X86_PM_TIMER=y
+# CONFIG_X86_POWERNOW_K8 is not set
+CONFIG_ZLIB_DEFLATE=y
diff --git a/target/linux/x86/modules.mk b/target/linux/x86/modules.mk
index 7921726765a8dc..7e5a692a03a81f 100644
--- a/target/linux/x86/modules.mk
+++ b/target/linux/x86/modules.mk
@@ -6,7 +6,7 @@ define KernelPackage/amd-xgbe
   SUBMENU:=$(NETWORK_DEVICES_MENU)
   TITLE:=AMD Ethernet on SoC support
   DEPENDS:=@PCI_SUPPORT @TARGET_x86_64 +kmod-lib-crc32c +kmod-ptp +kmod-libphy \
-	+(LINUX_5_10||LINUX_5_15||LINUX_6_1):kmod-mdio-devres
+	+(LINUX_5_10||LINUX_5_15||LINUX_6_1||LINUX_6_6):kmod-mdio-devres
   KCONFIG:=CONFIG_AMD_XGBE
   FILES:=$(LINUX_DIR)/drivers/net/ethernet/amd/xgbe/amd-xgbe.ko
   AUTOLOAD:=$(call AutoLoad,35,amd-xgbe)
diff --git a/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch b/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch
index 0ab685a8f3cb51..562a61b452a5bb 100644
--- a/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch
+++ b/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch
@@ -140,7 +140,7 @@ and performance for all other cases.
  	 * and hopefully then we'll have sufficient space.
 --- a/net/ipv4/tcp_ipv4.c
 +++ b/net/ipv4/tcp_ipv4.c
-@@ -3224,6 +3224,8 @@ static int __net_init tcp_sk_init(struct
+@@ -3225,6 +3225,8 @@ static int __net_init tcp_sk_init(struct
  
  	net->ipv4.sysctl_tcp_shrink_window = 0;
  
diff --git a/target/linux/x86/patches-6.6/100-fix_cs5535_clockevt.patch b/target/linux/x86/patches-6.6/100-fix_cs5535_clockevt.patch
new file mode 100644
index 00000000000000..d4de2027bafe15
--- /dev/null
+++ b/target/linux/x86/patches-6.6/100-fix_cs5535_clockevt.patch
@@ -0,0 +1,13 @@
+--- a/drivers/clocksource/timer-cs5535.c
++++ b/drivers/clocksource/timer-cs5535.c
+@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v
+ 		cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
+ 				MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
+ 
+-	cs5535_clockevent.event_handler(&cs5535_clockevent);
++	if (cs5535_clockevent.event_handler)
++		cs5535_clockevent.event_handler(&cs5535_clockevent);
++
+ 	return IRQ_HANDLED;
+ }
+ 
diff --git a/target/linux/x86/patches-6.6/992-enable-intel-guc.patch b/target/linux/x86/patches-6.6/992-enable-intel-guc.patch
new file mode 100644
index 00000000000000..f7e3bfd8f74dac
--- /dev/null
+++ b/target/linux/x86/patches-6.6/992-enable-intel-guc.patch
@@ -0,0 +1,18 @@
+--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
++++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+@@ -31,10 +31,14 @@ static void uc_expand_default_options(st
+ 		return;
+ 
+ 	/* Don't enable GuC/HuC on pre-Gen12 */
+-	if (GRAPHICS_VER(i915) < 12) {
++	if (GRAPHICS_VER(i915) < 9) {
+ 		i915->params.enable_guc = 0;
+ 		return;
+ 	}
++	if(GRAPHICS_VER(i915) < 11){
++		i915->params.enable_guc = 2;
++		return;
++	}
+ 
+ 	/* Don't enable GuC/HuC on older Gen12 platforms */
+ 	if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
diff --git a/target/linux/x86/patches-6.6/993-bnx2x_warpcore_8727_2_5g_sgmii_txfault.patch b/target/linux/x86/patches-6.6/993-bnx2x_warpcore_8727_2_5g_sgmii_txfault.patch
new file mode 100644
index 00000000000000..96f6b11f967d4b
--- /dev/null
+++ b/target/linux/x86/patches-6.6/993-bnx2x_warpcore_8727_2_5g_sgmii_txfault.patch
@@ -0,0 +1,216 @@
+--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+@@ -1593,6 +1593,7 @@ struct bnx2x {
+ 	uint			num_ethernet_queues;
+ 	uint			num_cnic_queues;
+ 	int			disable_tpa;
++	int			mask_tx_fault;
+ 
+ 	u32			rx_mode;
+ #define BNX2X_RX_MODE_NONE		0
+--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+@@ -151,6 +151,7 @@ typedef int (*read_sfp_module_eeprom_fun
+ 
+ #define SFP_EEPROM_CON_TYPE_ADDR		0x2
+ 	#define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN	0x0
++	#define SFP_EEPROM_CON_TYPE_VAL_SC	0x1
+ 	#define SFP_EEPROM_CON_TYPE_VAL_LC	0x7
+ 	#define SFP_EEPROM_CON_TYPE_VAL_COPPER	0x21
+ 	#define SFP_EEPROM_CON_TYPE_VAL_RJ45	0x22
+@@ -4210,6 +4211,16 @@ static void bnx2x_warpcore_set_sgmii_spe
+ 					 0x1000);
+ 		DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
+ 	} else {
++		/* Note that 2.5G works only when used with 1G advertisment */
++		if (fiber_mode && (phy->req_line_speed == SPEED_2500) &&
++			(phy->speed_cap_mask &
++			 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
++			  PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) {
++			bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
++				MDIO_WC_REG_SERDESDIGITAL_MISC1,
++					0x6010);
++		}
++
+ 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
+ 				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
+ 		val16 &= 0xcebf;
+@@ -4220,6 +4231,7 @@ static void bnx2x_warpcore_set_sgmii_spe
+ 			val16 |= 0x2000;
+ 			break;
+ 		case SPEED_1000:
++		case SPEED_2500:
+ 			val16 |= 0x0040;
+ 			break;
+ 		default:
+@@ -8174,6 +8186,7 @@ static int bnx2x_get_edc_mode(struct bnx
+ 		break;
+ 	}
+ 	case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
++	case SFP_EEPROM_CON_TYPE_VAL_SC:
+ 	case SFP_EEPROM_CON_TYPE_VAL_LC:
+ 	case SFP_EEPROM_CON_TYPE_VAL_RJ45:
+ 		check_limiting_mode = 1;
+@@ -8184,7 +8197,8 @@ static int bnx2x_get_edc_mode(struct bnx
+ 		    (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
+ 			DP(NETIF_MSG_LINK, "1G SFP module detected\n");
+ 			phy->media_type = ETH_PHY_SFP_1G_FIBER;
+-			if (phy->req_line_speed != SPEED_1000) {
++			if ((phy->req_line_speed != SPEED_1000) &&
++				(phy->req_line_speed != SPEED_2500)) {
+ 				u8 gport = params->port;
+ 				phy->req_line_speed = SPEED_1000;
+ 				if (!CHIP_IS_E1x(bp)) {
+@@ -8344,7 +8358,7 @@ static int bnx2x_wait_for_sfp_module_ini
+ 	 * some phys type ( e.g. JDSU )
+ 	 */
+ 
+-	for (timeout = 0; timeout < 60; timeout++) {
++	for (timeout = 0; timeout < 1800; timeout++) {
+ 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
+ 			rc = bnx2x_warpcore_read_sfp_module_eeprom(
+ 				phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
+@@ -9238,6 +9252,7 @@ static void bnx2x_8727_config_speed(stru
+ 	u16 tmp1, val;
+ 	/* Set option 1G speed */
+ 	if ((phy->req_line_speed == SPEED_1000) ||
++		(phy->req_line_speed == SPEED_2500) ||
+ 	    (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
+ 		DP(NETIF_MSG_LINK, "Setting 1G force\n");
+ 		bnx2x_cl45_write(bp, phy,
+@@ -9247,6 +9262,22 @@ static void bnx2x_8727_config_speed(stru
+ 		bnx2x_cl45_read(bp, phy,
+ 				MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
+ 		DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
++		if ((phy->req_line_speed == SPEED_2500) &&
++			(phy->speed_cap_mask &
++			(PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
++			 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) {
++			bnx2x_cl45_read_and_write(bp, phy,
++					MDIO_AN_DEVAD,
++					MDIO_AN_REG_8727_MISC_CTRL2,
++					~(1<<5));
++			bnx2x_cl45_write(bp, phy,
++					MDIO_AN_DEVAD,
++					MDIO_AN_REG_8727_MISC_CTRL1, 0x0010);
++		} else {
++			bnx2x_cl45_write(bp, phy,
++					MDIO_AN_DEVAD,
++					MDIO_AN_REG_8727_MISC_CTRL1, 0x001C);
++		}
+ 		/* Power down the XAUI until link is up in case of dual-media
+ 		 * and 1G
+ 		 */
+@@ -9268,7 +9299,7 @@ static void bnx2x_8727_config_speed(stru
+ 
+ 		DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
+ 		bnx2x_cl45_write(bp, phy,
+-				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
++				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2, 0);
+ 		bnx2x_cl45_write(bp, phy,
+ 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
+ 	} else {
+@@ -9276,9 +9307,12 @@ static void bnx2x_8727_config_speed(stru
+ 		 * registers although it is default
+ 		 */
+ 		bnx2x_cl45_write(bp, phy,
+-				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
++				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2,
+ 				 0x0020);
+ 		bnx2x_cl45_write(bp, phy,
++				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL1,
++				 0x001C);
++		bnx2x_cl45_write(bp, phy,
+ 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
+ 		bnx2x_cl45_write(bp, phy,
+ 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
+@@ -9567,6 +9601,11 @@ static u8 bnx2x_8727_read_status(struct
+ 		vars->line_speed = SPEED_10000;
+ 		DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
+ 			   params->port);
++	} else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
++		link_up = 1;
++		vars->line_speed = SPEED_2500;
++		DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
++			   params->port);
+ 	} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
+ 		link_up = 1;
+ 		vars->line_speed = SPEED_1000;
+@@ -9598,7 +9637,8 @@ static u8 bnx2x_8727_read_status(struct
+ 	}
+ 
+ 	if ((DUAL_MEDIA(params)) &&
+-	    (phy->req_line_speed == SPEED_1000)) {
++	    ((phy->req_line_speed == SPEED_1000) ||
++	     (phy->req_line_speed == SPEED_2500))) {
+ 		bnx2x_cl45_read(bp, phy,
+ 				MDIO_PMA_DEVAD,
+ 				MDIO_PMA_REG_8727_PCS_GP, &val1);
+@@ -11722,6 +11762,7 @@ static const struct bnx2x_phy phy_warpco
+ 			   SUPPORTED_100baseT_Full |
+ 			   SUPPORTED_1000baseT_Full |
+ 			   SUPPORTED_1000baseKX_Full |
++			   SUPPORTED_2500baseX_Full |
+ 			   SUPPORTED_10000baseT_Full |
+ 			   SUPPORTED_10000baseKR_Full |
+ 			   SUPPORTED_20000baseKR2_Full |
+@@ -11908,6 +11949,7 @@ static const struct bnx2x_phy phy_8727 =
+ 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
+ 	.mdio_ctrl	= 0,
+ 	.supported	= (SUPPORTED_10000baseT_Full |
++			   SUPPORTED_2500baseX_Full |
+ 			   SUPPORTED_1000baseT_Full |
+ 			   SUPPORTED_FIBRE |
+ 			   SUPPORTED_Pause |
+@@ -12255,6 +12297,7 @@ static int bnx2x_populate_int_phy(struct
+ 			break;
+ 		case PORT_HW_CFG_NET_SERDES_IF_SFI:
+ 			phy->supported &= (SUPPORTED_1000baseT_Full |
++					   SUPPORTED_2500baseX_Full |
+ 					   SUPPORTED_10000baseT_Full |
+ 					   SUPPORTED_FIBRE |
+ 					   SUPPORTED_Pause |
+@@ -13939,7 +13982,8 @@ void bnx2x_period_func(struct link_param
+ 		    & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
+ 		    PORT_HW_CFG_NET_SERDES_IF_SFI) {
+ 			if (bnx2x_is_sfp_module_plugged(phy, params)) {
+-				bnx2x_sfp_tx_fault_detection(phy, params, vars);
++				if(!((params->port + 1) & bp->mask_tx_fault))
++					bnx2x_sfp_tx_fault_detection(phy, params, vars);
+ 			} else if (vars->link_status &
+ 				LINK_STATUS_SFP_TX_FAULT) {
+ 				/* Clean trail, interrupt corrects the leds */
+--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+@@ -112,6 +112,10 @@ static int disable_tpa;
+ module_param(disable_tpa, int, 0444);
+ MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
+ 
++static int mask_tx_fault;
++module_param(mask_tx_fault, int, 0444);
++MODULE_PARM_DESC(mask_tx_fault, " Mask SFP TX fault detection");
++
+ static int int_mode;
+ module_param(int_mode, int, 0444);
+ MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
+@@ -12344,6 +12348,8 @@ static int bnx2x_init_bp(struct bnx2x *b
+ 	if (BP_NOMCP(bp) && (func == 0))
+ 		dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
+ 
++	bp->mask_tx_fault = mask_tx_fault;
++
+ 	bp->disable_tpa = disable_tpa;
+ 	bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
+ 	/* Reduce memory usage in kdump environment by disabling TPA */
+--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+@@ -7169,7 +7169,8 @@ Theotherbitsarereservedandshouldbezero*/
+ #define MDIO_PMA_REG_8727_PCS_GP		0xc842
+ #define MDIO_PMA_REG_8727_OPT_CFG_REG		0xc8e4
+ 
+-#define MDIO_AN_REG_8727_MISC_CTRL		0x8309
++#define MDIO_AN_REG_8727_MISC_CTRL1		0x8308
++#define MDIO_AN_REG_8727_MISC_CTRL2		0x8309
+ 
+ #define MDIO_PMA_REG_8073_CHIP_REV			0xc801
+ #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS		0xc820
diff --git a/target/linux/x86/patches-6.6/996-intel-igc-i225-i226-disable-eee.patch b/target/linux/x86/patches-6.6/996-intel-igc-i225-i226-disable-eee.patch
new file mode 100644
index 00000000000000..3f95aee0fed121
--- /dev/null
+++ b/target/linux/x86/patches-6.6/996-intel-igc-i225-i226-disable-eee.patch
@@ -0,0 +1,11 @@
+--- a/drivers/net/ethernet/intel/igc/igc_main.c
++++ b/drivers/net/ethernet/intel/igc/igc_main.c
+@@ -108,7 +108,7 @@ void igc_reset(struct igc_adapter *adapt
+ 		netdev_err(dev, "Error on hardware initialization\n");
+ 
+ 	/* Re-establish EEE setting */
+-	igc_set_eee_i225(hw, true, true, true);
++	igc_set_eee_i225(hw, false, false, false);
+ 
+ 	if (!netif_running(adapter->netdev))
+ 		igc_power_down_phy_copper_base(&adapter->hw);
diff --git a/target/linux/x86/patches-6.6/999-Add-xtsproxy-Crypto-API-module.patch b/target/linux/x86/patches-6.6/999-Add-xtsproxy-Crypto-API-module.patch
new file mode 100644
index 00000000000000..d75818164585fe
--- /dev/null
+++ b/target/linux/x86/patches-6.6/999-Add-xtsproxy-Crypto-API-module.patch
@@ -0,0 +1,178 @@
+From 354d7a8febaa440dd3244466670315ed2805764e Mon Sep 17 00:00:00 2001
+From: Ignat Korchagin <ignat@cloudflare.com>
+Date: Wed, 4 Dec 2019 16:53:46 +0000
+Subject: [PATCH] Add xtsproxy Crypto API module
+
+This module implements a Crypto API AES-XTS synchronous driver, which uses
+AES NI implementation as a backend and falls back to generic AES implementation,
+when FPU is not usable.
+---
+ crypto/Kconfig    |  10 ++++
+ crypto/Makefile   |   1 +
+ crypto/xtsproxy.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 142 insertions(+)
+ create mode 100644 crypto/xtsproxy.c
+
+--- a/crypto/Kconfig
++++ b/crypto/Kconfig
+@@ -709,6 +709,16 @@ config CRYPTO_HCTR2
+ 
+ 	  See https://eprint.iacr.org/2021/1441
+ 
++config CRYPTO_XTS_AES_SYNC
++	tristate "XTS AES synchronous implementation"
++	depends on X86 && 64BIT
++	select CRYPTO_AES
++	select CRYPTO_AES_NI_INTEL
++	help
++	  A synchronous AES-XTS implementaion, which uses AES NI as a
++	  backend implementation and falls back to generic implementation,
++	  when FPU is not usable.
++
+ config CRYPTO_KEYWRAP
+ 	tristate "KW (AES Key Wrap)"
+ 	select CRYPTO_SKCIPHER
+--- a/crypto/Makefile
++++ b/crypto/Makefile
+@@ -93,6 +93,7 @@ obj-$(CONFIG_CRYPTO_PCBC) += pcbc.o
+ obj-$(CONFIG_CRYPTO_CTS) += cts.o
+ obj-$(CONFIG_CRYPTO_LRW) += lrw.o
+ obj-$(CONFIG_CRYPTO_XTS) += xts.o
++obj-$(CONFIG_CRYPTO_XTS_AES_SYNC) += xtsproxy.o
+ obj-$(CONFIG_CRYPTO_CTR) += ctr.o
+ obj-$(CONFIG_CRYPTO_XCTR) += xctr.o
+ obj-$(CONFIG_CRYPTO_HCTR2) += hctr2.o
+--- /dev/null
++++ b/crypto/xtsproxy.c
+@@ -0,0 +1,131 @@
++#include <linux/module.h>
++#include <linux/crypto.h>
++#include <linux/err.h>
++#include <crypto/internal/skcipher.h>
++#include <crypto/aes.h>
++#include <asm/fpu/api.h>
++
++struct xtsproxy_ctx {
++	struct crypto_skcipher *xts_aesni;
++	struct crypto_skcipher *xts_generic;
++};
++
++static int xtsproxy_skcipher_init(struct crypto_skcipher *tfm)
++{
++	struct xtsproxy_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	/* AESNI based XTS implementation, requires FPU to be available */
++	ctx->xts_aesni = crypto_alloc_skcipher("__xts-aes-aesni", CRYPTO_ALG_INTERNAL, 0);
++	if (IS_ERR(ctx->xts_aesni))
++		return PTR_ERR(ctx->xts_aesni);
++
++	/* generic XTS implementation based on generic FPU-less AES */
++	/* there is also aes-aesni implementation, which falls back to aes-generic */
++	/* but we're doing FPU checks in our code, so no need to repeat those */
++	/* as we will always fallback to aes-generic in this case */
++	ctx->xts_generic = crypto_alloc_skcipher("xts(ecb(aes-generic))", 0, 0);
++	if (IS_ERR(ctx->xts_generic))
++		return PTR_ERR(ctx->xts_generic);
++
++	/* make sure we allocate enough request memory for both implementations */
++	crypto_skcipher_set_reqsize(tfm, max(crypto_skcipher_reqsize(ctx->xts_aesni), crypto_skcipher_reqsize(ctx->xts_generic)));
++
++	return 0;
++}
++
++static void xtsproxy_skcipher_exit(struct crypto_skcipher *tfm)
++{
++	struct xtsproxy_ctx *ctx = crypto_skcipher_ctx(tfm);
++
++	if (!IS_ERR_OR_NULL(ctx->xts_generic)) {
++		crypto_free_skcipher(ctx->xts_generic);
++		ctx->xts_generic = NULL;
++	}
++
++	if (!IS_ERR_OR_NULL(ctx->xts_aesni)) {
++		crypto_free_skcipher(ctx->xts_aesni);
++		ctx->xts_aesni = NULL;
++	}
++}
++
++static int xtsproxy_setkey(struct crypto_skcipher *tfm, const u8 *key,
++			    unsigned int keylen)
++{
++	struct xtsproxy_ctx *ctx = crypto_skcipher_ctx(tfm);
++	int err;
++
++	err = crypto_skcipher_setkey(ctx->xts_aesni, key, keylen);
++	if (err)
++		return err;
++
++	return crypto_skcipher_setkey(ctx->xts_generic, key, keylen);
++}
++
++static int xtsproxy_encrypt(struct skcipher_request *req)
++{
++	struct xtsproxy_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
++
++	if (irq_fpu_usable())
++		skcipher_request_set_tfm(req, ctx->xts_aesni);
++	else
++		skcipher_request_set_tfm(req, ctx->xts_generic);
++
++	/* underlying implementations should not try to sleep */
++	req->base.flags &= ~(CRYPTO_TFM_REQ_MAY_SLEEP | CRYPTO_TFM_REQ_MAY_BACKLOG);
++
++	return crypto_skcipher_encrypt(req);
++}
++
++static int xtsproxy_decrypt(struct skcipher_request *req)
++{
++	struct xtsproxy_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
++
++	if (irq_fpu_usable())
++		skcipher_request_set_tfm(req, ctx->xts_aesni);
++	else
++		skcipher_request_set_tfm(req, ctx->xts_generic);
++
++	/* underlying implementations should not try to sleep */
++	req->base.flags &= ~(CRYPTO_TFM_REQ_MAY_SLEEP | CRYPTO_TFM_REQ_MAY_BACKLOG);
++
++	return crypto_skcipher_decrypt(req);
++}
++
++static struct skcipher_alg xtsproxy_skcipher = {
++	.base = {
++		.cra_name			= "xts(aes)",
++		.cra_driver_name	= "xts-aes-xtsproxy",
++		/* make sure we don't use it unless requested explicitly */
++		.cra_priority		= 0,
++		/* .cra_flags			= CRYPTO_ALG_INTERNAL, */
++		.cra_blocksize		= AES_BLOCK_SIZE,
++		.cra_ctxsize		= sizeof(struct xtsproxy_ctx),
++		.cra_module			= THIS_MODULE,
++	},
++	.min_keysize	= 2 * AES_MIN_KEY_SIZE,
++	.max_keysize	= 2 * AES_MAX_KEY_SIZE,
++	.ivsize			= AES_BLOCK_SIZE,
++	.init 			= xtsproxy_skcipher_init,
++	.exit 			= xtsproxy_skcipher_exit,
++	.setkey			= xtsproxy_setkey,
++	.encrypt		= xtsproxy_encrypt,
++	.decrypt		= xtsproxy_decrypt,
++};
++
++static int __init xtsproxy_init(void)
++{
++	return crypto_register_skcipher(&xtsproxy_skcipher);
++}
++
++static void __exit xtsproxy_fini(void)
++{
++	crypto_unregister_skcipher(&xtsproxy_skcipher);
++}
++
++module_init(xtsproxy_init);
++module_exit(xtsproxy_fini);
++
++MODULE_DESCRIPTION("XTS-AES using AESNI implementation with generic AES fallback");
++MODULE_AUTHOR("Ignat Korchagin <ignat@cloudflare.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_CRYPTO("xts(aes)");
diff --git a/toolchain/binutils/Config.in b/toolchain/binutils/Config.in
index 4fc48d77fc7d6f..3ec4fe47a8f3a9 100644
--- a/toolchain/binutils/Config.in
+++ b/toolchain/binutils/Config.in
@@ -2,7 +2,7 @@
 
 choice
 	prompt "Binutils Version" if TOOLCHAINOPTS
-	default BINUTILS_USE_VERSION_2_37
+	default BINUTILS_USE_VERSION_2_40
 	help
 	  Select the version of binutils you wish to use.
 
@@ -21,6 +21,10 @@ choice
 	config BINUTILS_USE_VERSION_2_40
 		bool "Binutils 2.40"
 		select BINUTILS_VERSION_2_40
+
+	config BINUTILS_USE_VERSION_2_41
+		bool "Binutils 2.41"
+		select BINUTILS_VERSION_2_41
 endchoice
 
 config EXTRA_BINUTILS_CONFIG_OPTIONS
diff --git a/toolchain/binutils/Config.version b/toolchain/binutils/Config.version
index 045007166e94f8..acb764bb6a741b 100644
--- a/toolchain/binutils/Config.version
+++ b/toolchain/binutils/Config.version
@@ -1,6 +1,5 @@
 
 config BINUTILS_VERSION_2_37
-	default y if !TOOLCHAINOPTS
 	bool
 
 config BINUTILS_VERSION_2_38
@@ -10,6 +9,10 @@ config BINUTILS_VERSION_2_39
 	bool
 
 config BINUTILS_VERSION_2_40
+	default y if !TOOLCHAINOPTS
+	bool
+
+config BINUTILS_VERSION_2_41
 	bool
 
 config BINUTILS_VERSION
@@ -18,3 +21,4 @@ config BINUTILS_VERSION
 	default "2.38"			if BINUTILS_VERSION_2_38
 	default "2.39"			if BINUTILS_VERSION_2_39
 	default "2.40"			if BINUTILS_VERSION_2_40
+	default "2.41"			if BINUTILS_VERSION_2_41
diff --git a/toolchain/binutils/Makefile b/toolchain/binutils/Makefile
index cf65e83e6fdabe..b2831f8c2b2668 100644
--- a/toolchain/binutils/Makefile
+++ b/toolchain/binutils/Makefile
@@ -12,6 +12,7 @@ BIN_VERSION:=$(PKG_VERSION)
 
 PKG_SOURCE_URL:=@GNU/binutils/
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
+PKG_CPE_ID:=cpe:/a:gnu:binutils
 
 TAR_OPTIONS += --exclude='*.rej'
 
@@ -31,20 +32,34 @@ ifeq ($(PKG_VERSION),2.40)
   PKG_HASH:=0f8a4c272d7f17f369ded10a4aca28b8e304828e95526da482b0ccc4dfc9d8e1
 endif
 
+ifeq ($(PKG_VERSION),2.41)
+  PKG_HASH:=ae9a5789e23459e59606e6714723f2d3ffc31c03174191ef0d015bdf06007450
+endif
+
 HOST_BUILD_PARALLEL:=1
 
 PATCH_DIR:=./patches/$(PKG_VERSION)
 
 include $(INCLUDE_DIR)/toolchain-build.mk
 
+ifdef CONFIG_GCC_USE_GRAPHITE
+  GRAPHITE_CONFIGURE:= --with-isl=$(STAGING_DIR_HOST)
+else
+  GRAPHITE_CONFIGURE:= --without-isl --without-cloog
+endif
+
 HOST_CONFIGURE_ARGS = \
 	--prefix=$(TOOLCHAIN_DIR) \
 	--build=$(GNU_HOST_NAME) \
 	--host=$(GNU_HOST_NAME) \
 	--target=$(REAL_GNU_TARGET_NAME) \
 	--with-sysroot=$(TOOLCHAIN_DIR) \
+	--with-system-zlib \
+	--without-zstd \
 	--enable-deterministic-archives \
 	--enable-plugins \
+	--enable-lto \
+	--disable-gprofng \
 	--disable-multilib \
 	--disable-werror \
 	--disable-nls \
@@ -74,7 +89,6 @@ define Host/Prepare
 	$(call Host/Prepare/Default)
 	ln -snf $(notdir $(HOST_BUILD_DIR)) $(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)
 	$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(HOST_BUILD_DIR)/
-	$(SED) 's, " Linaro.*,,' $(HOST_BUILD_DIR)/bfd/version.h
 endef
 
 define Host/Compile
@@ -82,22 +96,10 @@ define Host/Compile
 endef
 
 define Host/Install
-	mkdir -p $(TOOLCHAIN_DIR)/initial
-	$(MAKE) -C $(HOST_BUILD_DIR) \
-		prefix=$(TOOLCHAIN_DIR)/initial \
-		install
 	$(MAKE) -C $(HOST_BUILD_DIR) \
-		prefix=$(TOOLCHAIN_DIR) \
 		install
-	$(call FixupLibdir,$(TOOLCHAIN_DIR)/initial)
-	$(RM) $(TOOLCHAIN_DIR)/initial/lib/libiberty.a
+	$(call FixupLibdir,$(TOOLCHAIN_DIR))
 	$(CP) $(TOOLCHAIN_DIR)/bin/$(REAL_GNU_TARGET_NAME)-readelf $(HOST_BUILD_PREFIX)/bin/readelf
-	# ARC gcc requires extlib.
-	# If extlib is not available in "initial" folder
-	# initial gcc will fail to build libc.
-	if [ -d $(TOOLCHAIN_DIR)/extlib ]; then \
-		$(CP) -r $(TOOLCHAIN_DIR)/extlib $(TOOLCHAIN_DIR)/initial/; \
-	fi
 endef
 
 define Host/Clean
diff --git a/toolchain/binutils/patches/2.40/005-libctf-update-regexp-to-allow-makeinfo-to-build-docu.patch b/toolchain/binutils/patches/2.40/005-libctf-update-regexp-to-allow-makeinfo-to-build-docu.patch
new file mode 100644
index 00000000000000..19af34091c862c
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/005-libctf-update-regexp-to-allow-makeinfo-to-build-docu.patch
@@ -0,0 +1,70 @@
+From f7c5db99b76e8dde89335d794c82fcbfbf53c612 Mon Sep 17 00:00:00 2001
+From: Enze Li <enze.li@hotmail.com>
+Date: Sat, 14 Jan 2023 11:33:48 +0800
+Subject: [PATCH 05/50] libctf: update regexp to allow makeinfo to build
+ document
+
+While trying to build gdb on latest openSUSE Tumbleweed, I noticed the
+following warning,
+
+ checking for makeinfo... makeinfo --split-size=5000000
+ configure: WARNING:
+ *** Makeinfo is too old. Info documentation will not be built.
+
+then I checked the version of makeinfo, it said,
+======
+$ makeinfo --version
+texi2any (GNU texinfo) 7.0.1
+
+Copyright (C) 2022 Free Software Foundation, Inc.
+License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+This is free software: you are free to change and redistribute it.
+There is NO WARRANTY, to the extent permitted by law.
+======
+
+After digging a little bit, it became quite obvious that a dot is
+missing in regexp that makes it impossible to match versions higher than
+7.0, and here's the solution:
+
+-       | egrep 'texinfo[^0-9]*(6\.[3-9]|[7-9][0-9])' >/dev/null 2>&1; then
++       | egrep 'texinfo[^0-9]*(6\.[3-9]|[7-9]\.[0-9])' >/dev/null 2>&1; then
+
+However, Eli pointed out that the solution above has another problem: it
+will stop working when Texinfo 10.1 will be released.  Meanwhile, he
+suggested to solve this problem permanently.  That is, we don't care
+about the minor version for Texinfo > 6.9, we only care about the major
+version.
+
+In this way, the problem will be resolved permanently, thanks to Eli.
+
+libctf/ChangeLog:
+
+	* configure: Regenerated.
+	* configure.ac: Update regexp to match versions higher than 7.0.
+---
+ libctf/configure    | 2 +-
+ libctf/configure.ac | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/libctf/configure
++++ b/libctf/configure
+@@ -14865,7 +14865,7 @@ esac
+     # We require texinfo to be 6.3 or later, for a working synindex
+     # and validatemenus: otherwise we fall back to /bin/true.
+     if ${MAKEINFO} --version \
+-       | egrep 'texinfo[^0-9]*(6\.[3-9]|[7-9][0-9])' >/dev/null 2>&1; then
++       | egrep 'texinfo[^0-9]*(6\.[3-9]|[7-9]|[1-6][0-9])' >/dev/null 2>&1; then
+       build_info=yes
+     else
+         build_info=
+--- a/libctf/configure.ac
++++ b/libctf/configure.ac
+@@ -184,7 +184,7 @@ changequote(,)
+     # We require texinfo to be 6.3 or later, for a working synindex
+     # and validatemenus: otherwise we fall back to /bin/true.
+     if ${MAKEINFO} --version \
+-       | egrep 'texinfo[^0-9]*(6\.[3-9]|[7-9][0-9])' >/dev/null 2>&1; then
++       | egrep 'texinfo[^0-9]*(6\.[3-9]|[7-9]|[1-6][0-9])' >/dev/null 2>&1; then
+       build_info=yes
+     else
+         build_info=
diff --git a/toolchain/binutils/patches/2.40/007-Fix-version-number-snafu-in-some-configuration-files.patch b/toolchain/binutils/patches/2.40/007-Fix-version-number-snafu-in-some-configuration-files.patch
new file mode 100644
index 00000000000000..0676240442facf
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/007-Fix-version-number-snafu-in-some-configuration-files.patch
@@ -0,0 +1,444 @@
+From 59706683feafb6252d0ad369cf8759f75fd147be Mon Sep 17 00:00:00 2001
+From: Nick Clifton <nickc@redhat.com>
+Date: Tue, 17 Jan 2023 12:02:56 +0000
+Subject: [PATCH 07/50] Fix version number snafu in some configuration files:
+ 2.40.00 should be 2.40
+
+---
+ binutils/configure             | 20 ++++++++++----------
+ gprof/configure                | 20 ++++++++++----------
+ gprofng/configure              | 20 ++++++++++----------
+ gprofng/doc/version.texi       |  4 ++--
+ gprofng/libcollector/configure | 20 ++++++++++----------
+ ld/configure                   | 20 ++++++++++----------
+ 6 files changed, 52 insertions(+), 52 deletions(-)
+
+--- a/binutils/configure
++++ b/binutils/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for binutils 2.40.00.
++# Generated by GNU Autoconf 2.69 for binutils 2.40.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='binutils'
+ PACKAGE_TARNAME='binutils'
+-PACKAGE_VERSION='2.40.00'
+-PACKAGE_STRING='binutils 2.40.00'
++PACKAGE_VERSION='2.40'
++PACKAGE_STRING='binutils 2.40'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1401,7 +1401,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures binutils 2.40.00 to adapt to many kinds of systems.
++\`configure' configures binutils 2.40 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1472,7 +1472,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of binutils 2.40.00:";;
++     short | recursive ) echo "Configuration of binutils 2.40:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1631,7 +1631,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-binutils configure 2.40.00
++binutils configure 2.40
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2099,7 +2099,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by binutils $as_me 2.40.00, which was
++It was created by binutils $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3081,7 +3081,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='binutils'
+- VERSION='2.40.00'
++ VERSION='2.40'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -15326,7 +15326,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by binutils $as_me 2.40.00, which was
++This file was extended by binutils $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -15392,7 +15392,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-binutils config.status 2.40.00
++binutils config.status 2.40
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gprof/configure
++++ b/gprof/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gprof 2.40.00.
++# Generated by GNU Autoconf 2.69 for gprof 2.40.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gprof'
+ PACKAGE_TARNAME='gprof'
+-PACKAGE_VERSION='2.40.00'
+-PACKAGE_STRING='gprof 2.40.00'
++PACKAGE_VERSION='2.40'
++PACKAGE_STRING='gprof 2.40'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1338,7 +1338,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gprof 2.40.00 to adapt to many kinds of systems.
++\`configure' configures gprof 2.40 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1409,7 +1409,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gprof 2.40.00:";;
++     short | recursive ) echo "Configuration of gprof 2.40:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1520,7 +1520,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gprof configure 2.40.00
++gprof configure 2.40
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -1885,7 +1885,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gprof $as_me 2.40.00, which was
++It was created by gprof $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -2864,7 +2864,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gprof'
+- VERSION='2.40.00'
++ VERSION='2.40'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -12572,7 +12572,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gprof $as_me 2.40.00, which was
++This file was extended by gprof $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -12638,7 +12638,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gprof config.status 2.40.00
++gprof config.status 2.40
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gprofng/configure
++++ b/gprofng/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gprofng 2.40.00.
++# Generated by GNU Autoconf 2.69 for gprofng 2.40.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gprofng'
+ PACKAGE_TARNAME='gprofng'
+-PACKAGE_VERSION='2.40.00'
+-PACKAGE_STRING='gprofng 2.40.00'
++PACKAGE_VERSION='2.40'
++PACKAGE_STRING='gprofng 2.40'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1362,7 +1362,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gprofng 2.40.00 to adapt to many kinds of systems.
++\`configure' configures gprofng 2.40 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1433,7 +1433,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gprofng 2.40.00:";;
++     short | recursive ) echo "Configuration of gprofng 2.40:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1547,7 +1547,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gprofng configure 2.40.00
++gprofng configure 2.40
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2079,7 +2079,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gprofng $as_me 2.40.00, which was
++It was created by gprofng $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3052,7 +3052,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gprofng'
+- VERSION='2.40.00'
++ VERSION='2.40'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -17467,7 +17467,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gprofng $as_me 2.40.00, which was
++This file was extended by gprofng $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -17533,7 +17533,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gprofng config.status 2.40.00
++gprofng config.status 2.40
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gprofng/doc/version.texi
++++ b/gprofng/doc/version.texi
+@@ -1,4 +1,4 @@
+ @set UPDATED 5 January 2023
+ @set UPDATED-MONTH January 2023
+-@set EDITION 2.40.00
+-@set VERSION 2.40.00
++@set EDITION 2.40
++@set VERSION 2.40
+--- a/gprofng/libcollector/configure
++++ b/gprofng/libcollector/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gprofng 2.40.00.
++# Generated by GNU Autoconf 2.69 for gprofng 2.40.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gprofng'
+ PACKAGE_TARNAME='gprofng'
+-PACKAGE_VERSION='2.40.00'
+-PACKAGE_STRING='gprofng 2.40.00'
++PACKAGE_VERSION='2.40'
++PACKAGE_STRING='gprofng 2.40'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1325,7 +1325,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gprofng 2.40.00 to adapt to many kinds of systems.
++\`configure' configures gprofng 2.40 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1396,7 +1396,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gprofng 2.40.00:";;
++     short | recursive ) echo "Configuration of gprofng 2.40:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1505,7 +1505,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gprofng configure 2.40.00
++gprofng configure 2.40
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -1991,7 +1991,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gprofng $as_me 2.40.00, which was
++It was created by gprofng $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -2968,7 +2968,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gprofng'
+- VERSION='2.40.00'
++ VERSION='2.40'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -16098,7 +16098,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gprofng $as_me 2.40.00, which was
++This file was extended by gprofng $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -16164,7 +16164,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gprofng config.status 2.40.00
++gprofng config.status 2.40
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/ld/configure
++++ b/ld/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for ld 2.40.00.
++# Generated by GNU Autoconf 2.69 for ld 2.40.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='ld'
+ PACKAGE_TARNAME='ld'
+-PACKAGE_VERSION='2.40.00'
+-PACKAGE_STRING='ld 2.40.00'
++PACKAGE_VERSION='2.40'
++PACKAGE_STRING='ld 2.40'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1423,7 +1423,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures ld 2.40.00 to adapt to many kinds of systems.
++\`configure' configures ld 2.40 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1494,7 +1494,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of ld 2.40.00:";;
++     short | recursive ) echo "Configuration of ld 2.40:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1661,7 +1661,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-ld configure 2.40.00
++ld configure 2.40
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2376,7 +2376,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by ld $as_me 2.40.00, which was
++It was created by ld $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3359,7 +3359,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='ld'
+- VERSION='2.40.00'
++ VERSION='2.40'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -18083,7 +18083,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by ld $as_me 2.40.00, which was
++This file was extended by ld $as_me 2.40, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -18149,7 +18149,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-ld config.status 2.40.00
++ld config.status 2.40
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
diff --git a/toolchain/binutils/patches/2.40/010-toplevel-Makefile.def-add-install-strip-dependency-o.patch b/toolchain/binutils/patches/2.40/010-toplevel-Makefile.def-add-install-strip-dependency-o.patch
new file mode 100644
index 00000000000000..bef40f546fa232
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/010-toplevel-Makefile.def-add-install-strip-dependency-o.patch
@@ -0,0 +1,60 @@
+From bcea253f5fa194e57f9564e8461c718e228bd26e Mon Sep 17 00:00:00 2001
+From: Indu Bhagat <indu.bhagat@oracle.com>
+Date: Wed, 18 Jan 2023 23:17:49 -0800
+Subject: [PATCH 10/50] toplevel: Makefile.def: add install-strip dependency on
+ libsframe
+
+As noted in PR libsframe/30014 - FTBFS: install-strip fails because
+bfdlib relinks and fails to find libsframe, the install time
+dependencies of libbfd need to be updated.
+
+	PR libsframe/30014
+	* Makefile.def: Reflect that libsframe needs to installed before
+	libbfd.  Reorder a bit to better track libsframe dependencies.
+	* Makefile.in: Regenerate.
+
+(cherry picked from commit b8d21eb0cd10d6127e77cc437d82e949adb0c454)
+---
+ Makefile.def | 5 ++++-
+ Makefile.in  | 3 ++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/Makefile.def
++++ b/Makefile.def
+@@ -493,7 +493,6 @@ dependencies = { module=install-binutils
+ dependencies = { module=install-strip-binutils; on=install-strip-opcodes; };
+ 
+ // Likewise for ld, libctf, and bfd.
+-dependencies = { module=install-bfd; on=install-libsframe; };
+ dependencies = { module=install-libctf; on=install-bfd; };
+ dependencies = { module=install-ld; on=install-bfd; };
+ dependencies = { module=install-ld; on=install-libctf; };
+@@ -501,6 +500,10 @@ dependencies = { module=install-strip-li
+ dependencies = { module=install-strip-ld; on=install-strip-bfd; };
+ dependencies = { module=install-strip-ld; on=install-strip-libctf; };
+ 
++// libbfd depends on libsframe
++dependencies = { module=install-bfd; on=install-libsframe; };
++dependencies = { module=install-strip-bfd; on=install-strip-libsframe; };
++
+ // libopcodes depends on libbfd
+ dependencies = { module=configure-opcodes; on=configure-bfd; hard=true; };
+ dependencies = { module=install-opcodes; on=install-bfd; };
+--- a/Makefile.in
++++ b/Makefile.in
+@@ -64549,13 +64549,14 @@ all-stageautoprofile-binutils: maybe-all
+ all-stageautofeedback-binutils: maybe-all-stageautofeedback-libsframe
+ install-binutils: maybe-install-opcodes
+ install-strip-binutils: maybe-install-strip-opcodes
+-install-bfd: maybe-install-libsframe
+ install-libctf: maybe-install-bfd
+ install-ld: maybe-install-bfd
+ install-ld: maybe-install-libctf
+ install-strip-libctf: maybe-install-strip-bfd
+ install-strip-ld: maybe-install-strip-bfd
+ install-strip-ld: maybe-install-strip-libctf
++install-bfd: maybe-install-libsframe
++install-strip-bfd: maybe-install-strip-libsframe
+ configure-opcodes: configure-bfd
+ configure-stage1-opcodes: configure-stage1-bfd
+ configure-stage2-opcodes: configure-stage2-bfd
diff --git a/toolchain/binutils/patches/2.40/018-gprofng-PR29521-docs-man-pages-are-not-in-the-releas.patch b/toolchain/binutils/patches/2.40/018-gprofng-PR29521-docs-man-pages-are-not-in-the-releas.patch
new file mode 100644
index 00000000000000..ae557645c0f02b
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/018-gprofng-PR29521-docs-man-pages-are-not-in-the-releas.patch
@@ -0,0 +1,703 @@
+From c6e269febbc946a54ed9dbbb2dc70feba6017607 Mon Sep 17 00:00:00 2001
+From: Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
+Date: Fri, 20 Jan 2023 15:39:55 -0800
+Subject: [PATCH 18/50] gprofng: PR29521 [docs] man pages are not in the
+ release tarball
+
+gprofng/ChangeLog
+2023-01-20  Vladimir Mezentsev  <vladimir.mezentsev@oracle.com>
+
+	PR gprofng/29521
+	* configure.ac: Check if $MAKEINFO and $HELP2MAN are missing.
+	* Makefile.am: Build doc if $MAKEINFO exists.
+	* doc/gprofng.texi: Update documentation for gprofng.
+	* doc/Makefile.am: Build gprofng.1.
+	* src/Makefile.am: Move the build of gprofng.1 to doc/Makefile.am.
+	* configure: Rebuild.
+	* Makefile.in: Rebuild.
+	* doc/Makefile.in: Rebuild.
+	* src/Makefile.in: Rebuild.
+---
+ gprofng/Makefile.am      |   2 +-
+ gprofng/Makefile.in      |   2 +-
+ gprofng/configure        |  79 +++++++++++++++---
+ gprofng/configure.ac     |  21 +++--
+ gprofng/doc/Makefile.am  |  24 +++++-
+ gprofng/doc/Makefile.in  |  93 ++++++++++++++++++---
+ gprofng/doc/gprofng.texi | 169 +++++++++++++++++++++++++++++++++++++++
+ gprofng/src/Makefile.am  |   8 +-
+ gprofng/src/Makefile.in  |   8 +-
+ 9 files changed, 364 insertions(+), 42 deletions(-)
+
+--- a/gprofng/Makefile.am
++++ b/gprofng/Makefile.am
+@@ -23,7 +23,7 @@ AUTOMAKE_OPTIONS = dejagnu foreign
+ if BUILD_COLLECTOR
+     COLLECTOR_SUBDIRS = libcollector
+ endif
+-if BUILD_MAN
++if BUILD_DOC
+     DOC_SUBDIR = doc
+ endif
+ if BUILD_SRC
+--- a/gprofng/Makefile.in
++++ b/gprofng/Makefile.in
+@@ -381,7 +381,7 @@ zlibinc = @zlibinc@
+ ACLOCAL_AMFLAGS = -I . -I .. 
+ AUTOMAKE_OPTIONS = dejagnu foreign
+ @BUILD_COLLECTOR_TRUE@COLLECTOR_SUBDIRS = libcollector
+-@BUILD_MAN_TRUE@DOC_SUBDIR = doc
++@BUILD_DOC_TRUE@DOC_SUBDIR = doc
+ @BUILD_SRC_TRUE@SRC_SUBDIRS = src gp-display-html $(DOC_SUBDIR)
+ SUBDIRS = $(COLLECTOR_SUBDIRS) $(SRC_SUBDIRS)
+ DIST_SUBDIRS = libcollector src gp-display-html $(DOC_SUBDIR)
+--- a/gprofng/configure
++++ b/gprofng/configure
+@@ -639,6 +639,8 @@ GPROFNG_CPPFLAGS
+ GPROFNG_NO_FORMAT_TRUNCATION_CFLAGS
+ GPROFNG_CFLAGS
+ LD_NO_AS_NEEDED
++BUILD_DOC_FALSE
++BUILD_DOC_TRUE
+ BUILD_MAN_FALSE
+ BUILD_MAN_TRUE
+ HELP2MAN
+@@ -12221,7 +12223,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 12224 "configure"
++#line 12226 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -12327,7 +12329,7 @@ else
+   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+   lt_status=$lt_dlunknown
+   cat > conftest.$ac_ext <<_LT_EOF
+-#line 12330 "configure"
++#line 12332 "configure"
+ #include "confdefs.h"
+ 
+ #if HAVE_DLFCN_H
+@@ -16737,9 +16739,58 @@ fi
+ 
+ # Generate manpages, if possible.
+ build_man=false
++build_doc=false
+ if test $cross_compiling = no; then
++  for ac_prog in help2man
++do
++  # Extract the first word of "$ac_prog", so it can be a program name with args.
++set dummy $ac_prog; ac_word=$2
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
++$as_echo_n "checking for $ac_word... " >&6; }
++if ${ac_cv_prog_HELP2MAN+:} false; then :
++  $as_echo_n "(cached) " >&6
++else
++  if test -n "$HELP2MAN"; then
++  ac_cv_prog_HELP2MAN="$HELP2MAN" # Let the user override the test.
++else
++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
++for as_dir in $PATH
++do
++  IFS=$as_save_IFS
++  test -z "$as_dir" && as_dir=.
++    for ac_exec_ext in '' $ac_executable_extensions; do
++  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
++    ac_cv_prog_HELP2MAN="$ac_prog"
++    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
++    break 2
++  fi
++done
++  done
++IFS=$as_save_IFS
++
++fi
++fi
++HELP2MAN=$ac_cv_prog_HELP2MAN
++if test -n "$HELP2MAN"; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $HELP2MAN" >&5
++$as_echo "$HELP2MAN" >&6; }
++else
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
++$as_echo "no" >&6; }
++fi
+ 
+-HELP2MAN=${HELP2MAN-"${am_missing_run}help2man"}
++
++  test -n "$HELP2MAN" && break
++done
++test -n "$HELP2MAN" || HELP2MAN="$MISSING help2man"
++
++  case "x$HELP2MAN" in
++    x | */missing\ help2man* )
++      { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: gprofng: help2man is missing. Man pages will not be built." >&5
++$as_echo "$as_me: WARNING: gprofng: help2man is missing. Man pages will not be built." >&2;}
++      ;;
++    * ) build_man=true ;;
++    esac
+ 
+   for ac_prog in makeinfo
+ do
+@@ -16782,10 +16833,10 @@ fi
+ 
+   test -n "$MAKEINFO" && break
+ done
+-test -n "$MAKEINFO" || MAKEINFO=""@echo makeinfo missing; true""
++test -n "$MAKEINFO" || MAKEINFO="$MISSING makeinfo"
+ 
+-  case "$MAKEINFO" in
+-    *true)
++  case "x$MAKEINFO" in
++    x | */missing\ makeinfo*)
+       { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: gprofng: makeinfo is missing. Info documentation will not be built." >&5
+ $as_echo "$as_me: WARNING: gprofng: makeinfo is missing. Info documentation will not be built." >&2;}
+       ;;
+@@ -16796,9 +16847,7 @@ $as_echo "$as_me: WARNING: gprofng: make
+ $as_echo "$as_me: WARNING: gprofng: $MAKEINFO is too old. Info documentation will not be built." >&2;}
+ 	  MAKEINFO="@echo $MAKEINFO is too old, 6.5 or newer required; true"
+ 	  ;;
+-	x* )
+-	  build_man=true
+-	  ;;
++	x* ) build_doc=true ;;
+ 	esac
+       ;;
+     esac
+@@ -16812,6 +16861,14 @@ else
+   BUILD_MAN_FALSE=
+ fi
+ 
++ if test x$build_doc = xtrue; then
++  BUILD_DOC_TRUE=
++  BUILD_DOC_FALSE='#'
++else
++  BUILD_DOC_TRUE='#'
++  BUILD_DOC_FALSE=
++fi
++
+ 
+ LD_NO_AS_NEEDED=${no_as_needed}
+ 
+@@ -17070,6 +17127,10 @@ if test -z "${BUILD_MAN_TRUE}" && test -
+   as_fn_error $? "conditional \"BUILD_MAN\" was never defined.
+ Usually this means the macro was only invoked conditionally." "$LINENO" 5
+ fi
++if test -z "${BUILD_DOC_TRUE}" && test -z "${BUILD_DOC_FALSE}"; then
++  as_fn_error $? "conditional \"BUILD_DOC\" was never defined.
++Usually this means the macro was only invoked conditionally." "$LINENO" 5
++fi
+ 
+ : "${CONFIG_STATUS=./config.status}"
+ ac_write_fail=0
+--- a/gprofng/configure.ac
++++ b/gprofng/configure.ac
+@@ -210,11 +210,19 @@ AM_ZLIB
+ 
+ # Generate manpages, if possible.
+ build_man=false
++build_doc=false
+ if test $cross_compiling = no; then
+-  AM_MISSING_PROG(HELP2MAN, help2man)
+-  AC_CHECK_PROGS([MAKEINFO], makeinfo, ["@echo makeinfo missing; true"])
+-  case "$MAKEINFO" in
+-    *true)
++  AC_CHECK_PROGS([HELP2MAN], help2man, [$MISSING help2man])
++  case "x$HELP2MAN" in
++    x | */missing\ help2man* )
++      AC_MSG_WARN([gprofng: help2man is missing. Man pages will not be built.])
++      ;;
++    * ) build_man=true ;;
++    esac
++
++  AC_CHECK_PROGS([MAKEINFO], makeinfo, [$MISSING makeinfo])
++  case "x$MAKEINFO" in
++    x | */missing\ makeinfo*)
+       AC_MSG_WARN([gprofng: makeinfo is missing. Info documentation will not be built.])
+       ;;
+     *)
+@@ -223,15 +231,14 @@ if test $cross_compiling = no; then
+ 	  AC_MSG_WARN([gprofng: $MAKEINFO is too old. Info documentation will not be built.])
+ 	  MAKEINFO="@echo $MAKEINFO is too old, 6.5 or newer required; true"
+ 	  ;;
+-	x* )
+-	  build_man=true
+-	  ;;
++	x* ) build_doc=true ;;
+ 	esac
+       ;;
+     esac
+   AC_SUBST(MAKEINFO)
+ fi
+ AM_CONDITIONAL([BUILD_MAN], [test x$build_man = xtrue])
++AM_CONDITIONAL([BUILD_DOC], [test x$build_doc = xtrue])
+ 
+ AC_SUBST(LD_NO_AS_NEEDED, [${no_as_needed}])
+ AC_SUBST(GPROFNG_CFLAGS, [${gprofng_cflags}])
+--- a/gprofng/doc/Makefile.am
++++ b/gprofng/doc/Makefile.am
+@@ -19,9 +19,31 @@
+ 
+ AUTOMAKE_OPTIONS = info-in-builddir foreign no-texinfo.tex
+ 
++# Options to extract the man page
++MANCONF = -Dman
++
++TEXI2POD = perl $(srcdir)/../../etc/texi2pod.pl $(AM_MAKEINFOFLAGS)
++POD2MAN = pod2man --center="User Commands" \
++	--release="binutils-$(VERSION)" --section=1
++
+ info_TEXINFOS       = gprofng.texi
+ gprofng_TEXINFOS    = fdl.texi
+ TEXINFO_TEX         = .
+ MAKEINFOHTML        = $(MAKEINFO) --html --no-split
+ 
+-MAINTAINERCLEANFILES = gprofng.info
++man_MANS = gprofng.1
++
++# Build the man page from the texinfo file
++# The sed command removes the no-adjust Nroff command so that
++# the man output looks standard.
++gprofng.1: $(srcdir)/gprofng.texi
++	$(AM_V_GEN)touch $@
++	$(AM_V_at)-$(TEXI2POD) $(MANCONF) < $(srcdir)/gprofng.texi > gprofng.pod
++	$(AM_V_at)-($(POD2MAN) gprofng.pod | \
++	  sed -e '/^.if n .na/d' > $@.tmp && \
++	  mv -f $@.tmp $@) || (rm -f $@.tmp && exit 1)
++	$(AM_V_at)rm -f gprofng.pod
++
++MAINTAINERCLEANFILES = gprofng.info $(man_MANS)
++
++info: $(man_MANS)
+--- a/gprofng/doc/Makefile.in
++++ b/gprofng/doc/Makefile.in
+@@ -182,7 +182,7 @@ am__can_run_installinfo = \
+     n|no|NO) false;; \
+     *) (install-info --version) >/dev/null 2>&1;; \
+   esac
+-am__installdirs = "$(DESTDIR)$(infodir)"
++am__installdirs = "$(DESTDIR)$(infodir)" "$(DESTDIR)$(man1dir)"
+ am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+ am__vpath_adj = case $$p in \
+     $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+@@ -210,6 +210,9 @@ am__uninstall_files_from_dir = { \
+     || { echo " ( cd '$$dir' && rm -f" $$files ")"; \
+          $(am__cd) "$$dir" && rm -f $$files; }; \
+   }
++man1dir = $(mandir)/man1
++NROFF = nroff
++MANS = $(man_MANS)
+ am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP)
+ am__DIST_COMMON = $(gprofng_TEXINFOS) $(srcdir)/Makefile.in \
+ 	$(top_srcdir)/../mkinstalldirs mdate-sh texinfo.tex
+@@ -361,11 +364,19 @@ top_srcdir = @top_srcdir@
+ zlibdir = @zlibdir@
+ zlibinc = @zlibinc@
+ AUTOMAKE_OPTIONS = info-in-builddir foreign no-texinfo.tex
++
++# Options to extract the man page
++MANCONF = -Dman
++TEXI2POD = perl $(srcdir)/../../etc/texi2pod.pl $(AM_MAKEINFOFLAGS)
++POD2MAN = pod2man --center="User Commands" \
++	--release="binutils-$(VERSION)" --section=1
++
+ info_TEXINFOS = gprofng.texi
+ gprofng_TEXINFOS = fdl.texi
+ TEXINFO_TEX = .
+ MAKEINFOHTML = $(MAKEINFO) --html --no-split
+-MAINTAINERCLEANFILES = gprofng.info
++man_MANS = gprofng.1
++MAINTAINERCLEANFILES = gprofng.info $(man_MANS)
+ all: all-am
+ 
+ .SUFFIXES:
+@@ -558,6 +569,49 @@ maintainer-clean-aminfo:
+ 	  echo " rm -f $$i $$i-[0-9] $$i-[0-9][0-9] $$i_i[0-9] $$i_i[0-9][0-9]"; \
+ 	  rm -f $$i $$i-[0-9] $$i-[0-9][0-9] $$i_i[0-9] $$i_i[0-9][0-9]; \
+ 	done
++install-man1: $(man_MANS)
++	@$(NORMAL_INSTALL)
++	@list1=''; \
++	list2='$(man_MANS)'; \
++	test -n "$(man1dir)" \
++	  && test -n "`echo $$list1$$list2`" \
++	  || exit 0; \
++	echo " $(MKDIR_P) '$(DESTDIR)$(man1dir)'"; \
++	$(MKDIR_P) "$(DESTDIR)$(man1dir)" || exit 1; \
++	{ for i in $$list1; do echo "$$i"; done;  \
++	if test -n "$$list2"; then \
++	  for i in $$list2; do echo "$$i"; done \
++	    | sed -n '/\.1[a-z]*$$/p'; \
++	fi; \
++	} | while read p; do \
++	  if test -f $$p; then d=; else d="$(srcdir)/"; fi; \
++	  echo "$$d$$p"; echo "$$p"; \
++	done | \
++	sed -e 'n;s,.*/,,;p;h;s,.*\.,,;s,^[^1][0-9a-z]*$$,1,;x' \
++	      -e 's,\.[0-9a-z]*$$,,;$(transform);G;s,\n,.,' | \
++	sed 'N;N;s,\n, ,g' | { \
++	list=; while read file base inst; do \
++	  if test "$$base" = "$$inst"; then list="$$list $$file"; else \
++	    echo " $(INSTALL_DATA) '$$file' '$(DESTDIR)$(man1dir)/$$inst'"; \
++	    $(INSTALL_DATA) "$$file" "$(DESTDIR)$(man1dir)/$$inst" || exit $$?; \
++	  fi; \
++	done; \
++	for i in $$list; do echo "$$i"; done | $(am__base_list) | \
++	while read files; do \
++	  test -z "$$files" || { \
++	    echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(man1dir)'"; \
++	    $(INSTALL_DATA) $$files "$(DESTDIR)$(man1dir)" || exit $$?; }; \
++	done; }
++
++uninstall-man1:
++	@$(NORMAL_UNINSTALL)
++	@list=''; test -n "$(man1dir)" || exit 0; \
++	files=`{ for i in $$list; do echo "$$i"; done; \
++	l2='$(man_MANS)'; for i in $$l2; do echo "$$i"; done | \
++	  sed -n '/\.1[a-z]*$$/p'; \
++	} | sed -e 's,.*/,,;h;s,.*\.,,;s,^[^1][0-9a-z]*$$,1,;x' \
++	      -e 's,\.[0-9a-z]*$$,,;$(transform);G;s,\n,.,'`; \
++	dir='$(DESTDIR)$(man1dir)'; $(am__uninstall_files_from_dir)
+ tags TAGS:
+ 
+ ctags CTAGS:
+@@ -600,9 +654,9 @@ distdir: $(DISTFILES)
+ 	  dist-info
+ check-am: all-am
+ check: check-am
+-all-am: Makefile $(INFO_DEPS)
++all-am: Makefile $(INFO_DEPS) $(MANS)
+ installdirs:
+-	for dir in "$(DESTDIR)$(infodir)"; do \
++	for dir in "$(DESTDIR)$(infodir)" "$(DESTDIR)$(man1dir)"; do \
+ 	  test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ 	done
+ install: install-am
+@@ -652,11 +706,9 @@ html: html-am
+ 
+ html-am: $(HTMLS)
+ 
+-info: info-am
+-
+ info-am: $(INFO_DEPS)
+ 
+-install-data-am: install-info-am
++install-data-am: install-info-am install-man
+ 
+ install-dvi: install-dvi-am
+ 
+@@ -739,7 +791,7 @@ install-info-am: $(INFO_DEPS)
+ 	    install-info --info-dir="$(DESTDIR)$(infodir)" "$(DESTDIR)$(infodir)/$$relfile" || :;\
+ 	  done; \
+ 	else : ; fi
+-install-man:
++install-man: install-man1
+ 
+ install-pdf: install-pdf-am
+ 
+@@ -794,7 +846,9 @@ ps: ps-am
+ ps-am: $(PSS)
+ 
+ uninstall-am: uninstall-dvi-am uninstall-html-am uninstall-info-am \
+-	uninstall-pdf-am uninstall-ps-am
++	uninstall-man uninstall-pdf-am uninstall-ps-am
++
++uninstall-man: uninstall-man1
+ 
+ .MAKE: install-am install-strip
+ 
+@@ -804,19 +858,32 @@ uninstall-am: uninstall-dvi-am uninstall
+ 	html-am info info-am install install-am install-data \
+ 	install-data-am install-dvi install-dvi-am install-exec \
+ 	install-exec-am install-html install-html-am install-info \
+-	install-info-am install-man install-pdf install-pdf-am \
+-	install-ps install-ps-am install-strip installcheck \
+-	installcheck-am installdirs maintainer-clean \
++	install-info-am install-man install-man1 install-pdf \
++	install-pdf-am install-ps install-ps-am install-strip \
++	installcheck installcheck-am installdirs maintainer-clean \
+ 	maintainer-clean-aminfo maintainer-clean-generic \
+ 	maintainer-clean-vti mostlyclean mostlyclean-aminfo \
+ 	mostlyclean-generic mostlyclean-libtool mostlyclean-vti pdf \
+ 	pdf-am ps ps-am tags-am uninstall uninstall-am \
+ 	uninstall-dvi-am uninstall-html-am uninstall-info-am \
+-	uninstall-pdf-am uninstall-ps-am
++	uninstall-man uninstall-man1 uninstall-pdf-am uninstall-ps-am
+ 
+ .PRECIOUS: Makefile
+ 
+ 
++# Build the man page from the texinfo file
++# The sed command removes the no-adjust Nroff command so that
++# the man output looks standard.
++gprofng.1: $(srcdir)/gprofng.texi
++	$(AM_V_GEN)touch $@
++	$(AM_V_at)-$(TEXI2POD) $(MANCONF) < $(srcdir)/gprofng.texi > gprofng.pod
++	$(AM_V_at)-($(POD2MAN) gprofng.pod | \
++	  sed -e '/^.if n .na/d' > $@.tmp && \
++	  mv -f $@.tmp $@) || (rm -f $@.tmp && exit 1)
++	$(AM_V_at)rm -f gprofng.pod
++
++info: $(man_MANS)
++
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
+ .NOEXPORT:
+--- a/gprofng/doc/gprofng.texi
++++ b/gprofng/doc/gprofng.texi
+@@ -1,5 +1,8 @@
+ \input texinfo @c -*-texinfo-*-
+ 
++@c for $sect (qw(NAME SYNOPSIS TARGET DESCRIPTION OPTIONS ENVIRONMENT FILES
++@c               BUGS NOTES FOOTNOTES SEEALSO AUTHOR COPYRIGHT)) {
++
+ @c ----------------------------------------------------------------------------
+ @c This is the Texinfo source file for the GPROFNG manual.
+ @c
+@@ -59,6 +62,10 @@ gprofng
+ @cindex \label\, \string\
+ @end macro
+ 
++@macro gcctabopt{body}
++@code{\body\}
++@end macro
++
+ @c -- Get the version information ---------------------------------------------
+ @include version.texi
+ 
+@@ -99,6 +106,20 @@ section entitled ``GNU Free Documentatio
+ @page
+ @vskip 0pt plus 1filll
+ @insertcopying
++
++@c man begin COPYRIGHT
++
++Copyright @copyright{} 2022-2023 Free Software Foundation, Inc.
++
++Permission is granted to copy, distribute and/or modify this document
++under the terms of the GNU Free Documentation License, Version 1.3
++or any later version published by the Free Software Foundation;
++with no Invariant Sections, with no Front-Cover Texts, and with no
++Back-Cover Texts.  A copy of the license is included in the
++section entitled ``GNU Free Documentation License''.
++
++@c man end
++
+ @end titlepage
+ 
+ @c -- Generate the Table of Contents ------------------------------------------
+@@ -163,6 +184,154 @@ Terminology
+ @end menu
+ @end ifinfo
+ 
++@ifset man
++
++@c man title gprofng the driver for the gprofng tool suite
++
++@c man begin SYNOPSIS
++gprofng [OPTION(S)] ACTION [@b{QUALIFIER}] [ARGUMENTS] TARGET
++@c man end
++
++@c man begin DESCRIPTION
++This is the driver for the GPROFNG tools suite to gather and analyze performance data.
++
++The driver executes the action specified. An example of an action is @code{collect}
++to collect performance data. Depending on the action, a qualifier may be needed to
++define the command. Several qualifiers support options. The last item on the command
++is the target the command applies to.
++
++For example, to collect performance data for an application called @code{a.out} and
++store the results in experiment directory @code{mydata.er}, the following command may
++be used:
++
++@smallexample
++$ gprofng collect app -o mydata.er a.out
++@end smallexample
++
++In this example, the action is @code{collect}, the qualifier is @code{app}, the single
++argument is @code{-o mydata.er} and the target is @code{a.out}.
++
++If gprofng is executed without any additional option, action, or target, a usage
++overview is printed.
++
++@c man end
++
++@c man begin OPTIONS
++
++@table @gcctabopt
++
++@item @var{--version}
++print the version number and exit.
++
++@item @var{--help}
++print usage information and exit.
++
++@end table
++
++@c man end
++
++@c man begin NOTES
++
++The gprofng driver supports the following commands.
++
++@c The man pages for the commands below can be viewed using the command name with "gprofng" replaced by "gp" and the spaces replaced by a dash ("-"). For example the man page
++@c        name for "gprofng collect app" is "gp-collect-app".
++
++Collect performance data:
++
++@table @code
++
++@item gprofng collect app
++collect application performance data.
++
++@end table
++
++Display the performance results:
++
++@table @code
++
++@item gprofng display text
++display the performance data in ASCII format.
++
++@item gprofng display html
++generate an HTML file from one or more experiments.
++
++@end table
++
++Miscellaneous commands:
++
++@table @code
++
++@item gprofng display src
++display source or disassembly with compiler annotations.
++
++@item gprofng archive
++include binaries and source code in an experiment directory.
++
++@end table
++
++It is also possible to invoke the lower level commands directly, but since
++these are subject to change, in particular the options, we recommend to
++use the driver.
++
++@c man end
++
++@c man begin ENVIRONMENT
++The following environment variables are supported:
++
++@table @code
++
++@item @env{GPROFNG_MAX_CALL_STACK_DEPTH}
++set the depth of the call stack (default is 256).
++
++@item @env{GPROFNG_USE_JAVA_OPTIONS}
++may be set when profiling a C/C++ application that uses dlopen() to execute Java code.
++
++@item @env{GPROFNG_SSH_REMOTE_DISPLAY}
++use this variable to define the ssh command executed by the remote display tool.
++
++@item @env{GPROFNG_SKIP_VALIDATION}
++set this variable to disable checking hardware, system, and Java versions.
++
++@item @env{GPROFNG_ALLOW_CORE_DUMP}
++set this variable to allow a core file to be generated; otherwise an error report is created on /tmp.
++
++@item @env{GPROFNG_ARCHIVE}
++use this variable to define the settings for automatic archiving upon experiment recording completion.
++
++@item @env{GPROFNG_ARCHIVE_COMMON_DIR}
++set this variable to the location of the common archive.
++
++@item @env{GPROFNG_JAVA_MAX_CALL_STACK_DEPTH}
++set the depth of the Java call stack; the default is 256; set to 0 to disable capturing of call stacks.
++
++@item @env{GPROFNG_JAVA_NATIVE_MAX_CALL_STACK_DEPTH}
++set the depth of the Java native call stack; the default is 256; set to 0 to disable capturing of call stacks (JNI and assembly call stacks are not captured).
++
++@end table
++
++@c man end
++
++@c man begin SEEALSO
++The man pages for the various gprofng commands are not available yet, but
++the @option{--help} option supported on each of the commands lists the options
++and provides more information.
++
++For example this displays the options supported on the @command{gprofng collect app}
++command:
++
++@smallexample
++$ gprofng collect app --help
++@end smallexample
++
++The user guide is available as an Info entry for @file{gprofng}.
++@c man end
++
++@end ifset
++
++@c man begin DESCRIPTION
++@c man end
++
+ @c -- A new node --------------------------------------------------------------
+ @node    Introduction
+ @chapter Introduction
+--- a/gprofng/src/Makefile.am
++++ b/gprofng/src/Makefile.am
+@@ -160,7 +160,7 @@ gp_display_text_LDADD = $(LIBGPROFNG) $(
+ 
+ if BUILD_MAN
+ 
+-man_MANS = gprofng.1 \
++man_MANS = \
+ 	gp-archive.1 \
+ 	gp-collect-app.1 \
+ 	gp-display-src.1 \
+@@ -191,10 +191,6 @@ H2M_FILTER = | sed 's/\.TP/\.TP\n.B/' |
+   | sed 's/See also:/\.SH SEE ALSO/' | sed 's/Documentation:/.SH DOCUMENTATION/' \
+   | sed 's/Limitations:/.SH LIMITATIONS/'
+ 
+-gprofng.1: $(srcdir)/gprofng.cc $(common_mandeps) | ./gprofng$(EXEEXT)
+-	$(AM_V_GEN)_BUILDING_MANPAGE=1 $(HELP2MAN) $(HELP2MAN_OPT) \
+-	  --name=$(TEXT_GPROFNG) ./gprofng$(EXEEXT) $(H2M_FILTER) > $@
+-
+ gp-archive.1: $(srcdir)/gp-archive.cc $(common_mandeps) | ./gp-archive$(EXEEXT)
+ 	$(AM_V_GEN)_BUILDING_MANPAGE=1 $(HELP2MAN) $(HELP2MAN_OPT) \
+ 	  --name=$(TEXT_GP_ARCHIVE) ./gp-archive$(EXEEXT) $(H2M_FILTER) > $@
+@@ -223,3 +219,5 @@ dist-hook: $(LIBGPROFNG)
+ 
+ install-data-local: install-pkglibLTLIBRARIES
+ 	rm -f $(DESTDIR)/$(pkglibdir)/*.la $(DESTDIR)/$(pkglibdir)/*.a
++
++$(srcdir)/DbeSession.cc: QLParser.tab.hh
+--- a/gprofng/src/Makefile.in
++++ b/gprofng/src/Makefile.in
+@@ -572,7 +572,7 @@ gp_display_src_SOURCES = gp-display-src.
+ gp_display_src_LDADD = $(LIBGPROFNG) $(CLOCK_GETTIME_LINK) $(ZLIB)
+ gp_display_text_SOURCES = gp-display-text.cc ipc.cc ipcio.cc
+ gp_display_text_LDADD = $(LIBGPROFNG) $(CLOCK_GETTIME_LINK) $(ZLIB)
+-@BUILD_MAN_TRUE@man_MANS = gprofng.1 \
++@BUILD_MAN_TRUE@man_MANS = \
+ @BUILD_MAN_TRUE@	gp-archive.1 \
+ @BUILD_MAN_TRUE@	gp-collect-app.1 \
+ @BUILD_MAN_TRUE@	gp-display-src.1 \
+@@ -1176,10 +1176,6 @@ uninstall-man: uninstall-man1
+ QLParser.tab.cc QLParser.tab.hh: QLParser.yy
+ 	$(BISON) $^
+ 
+-@BUILD_MAN_TRUE@gprofng.1: $(srcdir)/gprofng.cc $(common_mandeps) | ./gprofng$(EXEEXT)
+-@BUILD_MAN_TRUE@	$(AM_V_GEN)_BUILDING_MANPAGE=1 $(HELP2MAN) $(HELP2MAN_OPT) \
+-@BUILD_MAN_TRUE@	  --name=$(TEXT_GPROFNG) ./gprofng$(EXEEXT) $(H2M_FILTER) > $@
+-
+ @BUILD_MAN_TRUE@gp-archive.1: $(srcdir)/gp-archive.cc $(common_mandeps) | ./gp-archive$(EXEEXT)
+ @BUILD_MAN_TRUE@	$(AM_V_GEN)_BUILDING_MANPAGE=1 $(HELP2MAN) $(HELP2MAN_OPT) \
+ @BUILD_MAN_TRUE@	  --name=$(TEXT_GP_ARCHIVE) ./gp-archive$(EXEEXT) $(H2M_FILTER) > $@
+@@ -1207,6 +1203,8 @@ dist-hook: $(LIBGPROFNG)
+ install-data-local: install-pkglibLTLIBRARIES
+ 	rm -f $(DESTDIR)/$(pkglibdir)/*.la $(DESTDIR)/$(pkglibdir)/*.a
+ 
++$(srcdir)/DbeSession.cc: QLParser.tab.hh
++
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
+ # Otherwise a system limit (for SysV at least) may be exceeded.
+ .NOEXPORT:
diff --git a/toolchain/binutils/patches/2.40/020-gprofng-PR30043-libgprofng.so.-are-installed-to-a-wr.patch b/toolchain/binutils/patches/2.40/020-gprofng-PR30043-libgprofng.so.-are-installed-to-a-wr.patch
new file mode 100644
index 00000000000000..d8d76a2961bf8c
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/020-gprofng-PR30043-libgprofng.so.-are-installed-to-a-wr.patch
@@ -0,0 +1,212 @@
+From edd36b26f3506eeb259534ba2493e15c728cd280 Mon Sep 17 00:00:00 2001
+From: Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
+Date: Wed, 25 Jan 2023 19:21:38 -0800
+Subject: [PATCH 20/50] gprofng: PR30043 libgprofng.so.* are installed to a
+ wrong location
+
+gprofng/ChangeLog
+2023-01-25  Vladimir Mezentsev  <vladimir.mezentsev@oracle.com>
+
+	PR gprofng/30043
+	PR gprofng/28972
+	* src/Makefile.am: Use lib_LTLIBRARIES instead of pkglib_LTLIBRARIES.
+	* src/Makefile.in: Rebuild.
+---
+ gprofng/src/Makefile.am |  7 +---
+ gprofng/src/Makefile.in | 76 +++++++++++++++++++----------------------
+ 2 files changed, 37 insertions(+), 46 deletions(-)
+
+--- a/gprofng/src/Makefile.am
++++ b/gprofng/src/Makefile.am
+@@ -124,7 +124,7 @@ BUILT_SOURCES = QLParser.tab.hh
+ EXTRA_DIST = QLParser.yy $(man_MANS)
+ 
+ 
+-pkglib_LTLIBRARIES = $(LIBGPROFNG)
++lib_LTLIBRARIES = $(LIBGPROFNG)
+ libgprofng_la_SOURCES = $(CCSOURCES) $(CSOURCES)
+ libgprofng_la_LDFLAGS = -version-info 0:0:0
+ 
+@@ -215,9 +215,4 @@ endif
+ # so ensure that the necessary libraries are built at dist time.
+ dist-hook: $(LIBGPROFNG)
+ 
+-.PHONY: install-data-local
+-
+-install-data-local: install-pkglibLTLIBRARIES
+-	rm -f $(DESTDIR)/$(pkglibdir)/*.la $(DESTDIR)/$(pkglibdir)/*.a
+-
+ $(srcdir)/DbeSession.cc: QLParser.tab.hh
+--- a/gprofng/src/Makefile.in
++++ b/gprofng/src/Makefile.in
+@@ -155,9 +155,9 @@ am__uninstall_files_from_dir = { \
+     || { echo " ( cd '$$dir' && rm -f" $$files ")"; \
+          $(am__cd) "$$dir" && rm -f $$files; }; \
+   }
+-am__installdirs = "$(DESTDIR)$(pkglibdir)" "$(DESTDIR)$(bindir)" \
++am__installdirs = "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" \
+ 	"$(DESTDIR)$(man1dir)" "$(DESTDIR)$(dbedir)"
+-LTLIBRARIES = $(pkglib_LTLIBRARIES)
++LTLIBRARIES = $(lib_LTLIBRARIES)
+ am__DEPENDENCIES_1 =
+ libgprofng_la_DEPENDENCIES = $(top_builddir)/../opcodes/libopcodes.la \
+ 	$(top_builddir)/../bfd/libbfd.la $(am__DEPENDENCIES_1)
+@@ -548,7 +548,7 @@ AM_CFLAGS = $(GPROFNG_CFLAGS) $(PTHREAD_
+ AM_CXXFLAGS = $(AM_CFLAGS)
+ BUILT_SOURCES = QLParser.tab.hh
+ EXTRA_DIST = QLParser.yy $(man_MANS)
+-pkglib_LTLIBRARIES = $(LIBGPROFNG)
++lib_LTLIBRARIES = $(LIBGPROFNG)
+ libgprofng_la_SOURCES = $(CCSOURCES) $(CSOURCES)
+ libgprofng_la_LDFLAGS = -version-info 0:0:0
+ 
+@@ -636,33 +636,33 @@ $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(
+ 	cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+ $(am__aclocal_m4_deps):
+ 
+-install-pkglibLTLIBRARIES: $(pkglib_LTLIBRARIES)
++install-libLTLIBRARIES: $(lib_LTLIBRARIES)
+ 	@$(NORMAL_INSTALL)
+-	@list='$(pkglib_LTLIBRARIES)'; test -n "$(pkglibdir)" || list=; \
++	@list='$(lib_LTLIBRARIES)'; test -n "$(libdir)" || list=; \
+ 	list2=; for p in $$list; do \
+ 	  if test -f $$p; then \
+ 	    list2="$$list2 $$p"; \
+ 	  else :; fi; \
+ 	done; \
+ 	test -z "$$list2" || { \
+-	  echo " $(MKDIR_P) '$(DESTDIR)$(pkglibdir)'"; \
+-	  $(MKDIR_P) "$(DESTDIR)$(pkglibdir)" || exit 1; \
+-	  echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 '$(DESTDIR)$(pkglibdir)'"; \
+-	  $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 "$(DESTDIR)$(pkglibdir)"; \
++	  echo " $(MKDIR_P) '$(DESTDIR)$(libdir)'"; \
++	  $(MKDIR_P) "$(DESTDIR)$(libdir)" || exit 1; \
++	  echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 '$(DESTDIR)$(libdir)'"; \
++	  $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 "$(DESTDIR)$(libdir)"; \
+ 	}
+ 
+-uninstall-pkglibLTLIBRARIES:
++uninstall-libLTLIBRARIES:
+ 	@$(NORMAL_UNINSTALL)
+-	@list='$(pkglib_LTLIBRARIES)'; test -n "$(pkglibdir)" || list=; \
++	@list='$(lib_LTLIBRARIES)'; test -n "$(libdir)" || list=; \
+ 	for p in $$list; do \
+ 	  $(am__strip_dir) \
+-	  echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(pkglibdir)/$$f'"; \
+-	  $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(pkglibdir)/$$f"; \
++	  echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(libdir)/$$f'"; \
++	  $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(libdir)/$$f"; \
+ 	done
+ 
+-clean-pkglibLTLIBRARIES:
+-	-test -z "$(pkglib_LTLIBRARIES)" || rm -f $(pkglib_LTLIBRARIES)
+-	@list='$(pkglib_LTLIBRARIES)'; \
++clean-libLTLIBRARIES:
++	-test -z "$(lib_LTLIBRARIES)" || rm -f $(lib_LTLIBRARIES)
++	@list='$(lib_LTLIBRARIES)'; \
+ 	locs=`for p in $$list; do echo $$p; done | \
+ 	      sed 's|^[^/]*$$|.|; s|/[^/]*$$||; s|$$|/so_locations|' | \
+ 	      sort -u`; \
+@@ -672,7 +672,7 @@ clean-pkglibLTLIBRARIES:
+ 	}
+ 
+ libgprofng.la: $(libgprofng_la_OBJECTS) $(libgprofng_la_DEPENDENCIES) $(EXTRA_libgprofng_la_DEPENDENCIES) 
+-	$(AM_V_CXXLD)$(libgprofng_la_LINK) -rpath $(pkglibdir) $(libgprofng_la_OBJECTS) $(libgprofng_la_LIBADD) $(LIBS)
++	$(AM_V_CXXLD)$(libgprofng_la_LINK) -rpath $(libdir) $(libgprofng_la_OBJECTS) $(libgprofng_la_LIBADD) $(LIBS)
+ install-binPROGRAMS: $(bin_PROGRAMS)
+ 	@$(NORMAL_INSTALL)
+ 	@list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+@@ -1039,8 +1039,10 @@ check-am: all-am
+ check: $(BUILT_SOURCES)
+ 	$(MAKE) $(AM_MAKEFLAGS) check-am
+ all-am: Makefile $(LTLIBRARIES) $(PROGRAMS) $(MANS) $(DATA)
++install-binPROGRAMS: install-libLTLIBRARIES
++
+ installdirs:
+-	for dir in "$(DESTDIR)$(pkglibdir)" "$(DESTDIR)$(bindir)" "$(DESTDIR)$(man1dir)" "$(DESTDIR)$(dbedir)"; do \
++	for dir in "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" "$(DESTDIR)$(man1dir)" "$(DESTDIR)$(dbedir)"; do \
+ 	  test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ 	done
+ install: $(BUILT_SOURCES)
+@@ -1078,8 +1080,8 @@ maintainer-clean-generic:
+ 	-test -z "$(MAINTAINERCLEANFILES)" || rm -f $(MAINTAINERCLEANFILES)
+ clean: clean-am
+ 
+-clean-am: clean-binPROGRAMS clean-generic clean-libtool \
+-	clean-pkglibLTLIBRARIES mostlyclean-am
++clean-am: clean-binPROGRAMS clean-generic clean-libLTLIBRARIES \
++	clean-libtool mostlyclean-am
+ 
+ distclean: distclean-am
+ 	-rm -rf ./$(DEPDIR)
+@@ -1099,13 +1101,13 @@ info: info-am
+ 
+ info-am:
+ 
+-install-data-am: install-data-local install-dbeDATA install-man
++install-data-am: install-dbeDATA install-man
+ 
+ install-dvi: install-dvi-am
+ 
+ install-dvi-am:
+ 
+-install-exec-am: install-binPROGRAMS install-pkglibLTLIBRARIES
++install-exec-am: install-binPROGRAMS install-libLTLIBRARIES
+ 
+ install-html: install-html-am
+ 
+@@ -1145,30 +1147,29 @@ ps: ps-am
+ 
+ ps-am:
+ 
+-uninstall-am: uninstall-binPROGRAMS uninstall-dbeDATA uninstall-man \
+-	uninstall-pkglibLTLIBRARIES
++uninstall-am: uninstall-binPROGRAMS uninstall-dbeDATA \
++	uninstall-libLTLIBRARIES uninstall-man
+ 
+ uninstall-man: uninstall-man1
+ 
+ .MAKE: all check install install-am install-strip
+ 
+ .PHONY: CTAGS GTAGS TAGS all all-am check check-am clean \
+-	clean-binPROGRAMS clean-generic clean-libtool \
+-	clean-pkglibLTLIBRARIES cscopelist-am ctags ctags-am dist-hook \
+-	distclean distclean-compile distclean-generic \
+-	distclean-libtool distclean-tags distdir dvi dvi-am html \
+-	html-am info info-am install install-am install-binPROGRAMS \
+-	install-data install-data-am install-data-local \
+-	install-dbeDATA install-dvi install-dvi-am install-exec \
+-	install-exec-am install-html install-html-am install-info \
+-	install-info-am install-man install-man1 install-pdf \
+-	install-pdf-am install-pkglibLTLIBRARIES install-ps \
++	clean-binPROGRAMS clean-generic clean-libLTLIBRARIES \
++	clean-libtool cscopelist-am ctags ctags-am dist-hook distclean \
++	distclean-compile distclean-generic distclean-libtool \
++	distclean-tags distdir dvi dvi-am html html-am info info-am \
++	install install-am install-binPROGRAMS install-data \
++	install-data-am install-dbeDATA install-dvi install-dvi-am \
++	install-exec install-exec-am install-html install-html-am \
++	install-info install-info-am install-libLTLIBRARIES \
++	install-man install-man1 install-pdf install-pdf-am install-ps \
+ 	install-ps-am install-strip installcheck installcheck-am \
+ 	installdirs maintainer-clean maintainer-clean-generic \
+ 	mostlyclean mostlyclean-compile mostlyclean-generic \
+ 	mostlyclean-libtool pdf pdf-am ps ps-am tags tags-am uninstall \
+ 	uninstall-am uninstall-binPROGRAMS uninstall-dbeDATA \
+-	uninstall-man uninstall-man1 uninstall-pkglibLTLIBRARIES
++	uninstall-libLTLIBRARIES uninstall-man uninstall-man1
+ 
+ .PRECIOUS: Makefile
+ 
+@@ -1198,11 +1199,6 @@ QLParser.tab.cc QLParser.tab.hh: QLParse
+ # so ensure that the necessary libraries are built at dist time.
+ dist-hook: $(LIBGPROFNG)
+ 
+-.PHONY: install-data-local
+-
+-install-data-local: install-pkglibLTLIBRARIES
+-	rm -f $(DESTDIR)/$(pkglibdir)/*.la $(DESTDIR)/$(pkglibdir)/*.a
+-
+ $(srcdir)/DbeSession.cc: QLParser.tab.hh
+ 
+ # Tell versions [3.59,3.63) of GNU make to not export all variables.
diff --git a/toolchain/binutils/patches/2.40/026-RISC-V-make-C-extension-JAL-available-again-for-32-b.patch b/toolchain/binutils/patches/2.40/026-RISC-V-make-C-extension-JAL-available-again-for-32-b.patch
new file mode 100644
index 00000000000000..4129a22906da48
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/026-RISC-V-make-C-extension-JAL-available-again-for-32-b.patch
@@ -0,0 +1,115 @@
+From 27f59ec47a18277b6ea3548f405263ef558f5217 Mon Sep 17 00:00:00 2001
+From: Jan Beulich <jbeulich@suse.com>
+Date: Tue, 31 Jan 2023 09:47:22 +0100
+Subject: [PATCH 26/50] RISC-V: make C-extension JAL available again for
+ (32-bit) assembly
+
+Along with the normal JAL alias, the C-extension one should have been
+moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for
+consistent alias handling"), for the assembler to actually be able to
+use it where/when possible.
+
+Since neither this nor any other compressed branch insn was being tested
+so far, take the opportunity and introduce a new testcase covering those.
+---
+ gas/config/tc-riscv.c                 |  3 +++
+ gas/testsuite/gas/riscv/c-branch-na.d | 20 ++++++++++++++++++++
+ gas/testsuite/gas/riscv/c-branch.d    | 19 +++++++++++++++++++
+ gas/testsuite/gas/riscv/c-branch.s    | 11 +++++++++++
+ opcodes/riscv-opc.c                   |  2 +-
+ 5 files changed, 54 insertions(+), 1 deletion(-)
+ create mode 100644 gas/testsuite/gas/riscv/c-branch-na.d
+ create mode 100644 gas/testsuite/gas/riscv/c-branch.d
+ create mode 100644 gas/testsuite/gas/riscv/c-branch.s
+
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -2762,6 +2762,8 @@ riscv_ip (char *str, struct riscv_cl_ins
+ 		case 'p':
+ 		  goto branch;
+ 		case 'a':
++		  if (oparg == insn->args + 1)
++		    goto jump_check_gpr;
+ 		  goto jump;
+ 		case 'S': /* Floating-point RS1 x8-x15.  */
+ 		  if (!reg_lookup (&asarg, RCLASS_FPR, &regno)
+@@ -3271,6 +3273,7 @@ riscv_ip (char *str, struct riscv_cl_ins
+ 		 but the 2nd (with 2 operands) might.  */
+ 	      if (oparg == insn->args)
+ 		{
++	    jump_check_gpr:
+ 		  asargStart = asarg;
+ 		  if (reg_lookup (&asarg, RCLASS_GPR, NULL)
+ 		      && (*asarg == ',' || (ISSPACE (*asarg) && asarg[1] == ',')))
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/c-branch-na.d
+@@ -0,0 +1,20 @@
++#as: -march=rv32ic
++#source: c-branch.s
++#objdump: -drw -Mno-aliases
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+ <target>:
++[ 	]+[0-9a-f]+:[ 	]+c001[ 	]+c\.beqz[ 	]+s0,0 <target>[ 	]+0: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+dcfd[ 	]+c\.beqz[ 	]+s1,0 <target>[ 	]+2: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+fc75[ 	]+c\.bnez[ 	]+s0,0 <target>[ 	]+4: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+fced[ 	]+c\.bnez[ 	]+s1,0 <target>[ 	]+6: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+bfe5[ 	]+c\.j[ 	]+0 <target>[ 	]+8: R_RISCV_RVC_JUMP	.*
++[ 	]+[0-9a-f]+:[ 	]+3fdd[ 	]+c\.jal[ 	]+0 <target>[ 	]+a: R_RISCV_RVC_JUMP	.*
++[ 	]+[0-9a-f]+:[ 	]+9302[ 	]+c\.jalr[ 	]+t1
++[ 	]+[0-9a-f]+:[ 	]+8382[ 	]+c\.jr[ 	]+t2
++[ 	]+[0-9a-f]+:[ 	]+8082[ 	]+c\.jr[ 	]+ra
++#...
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/c-branch.d
+@@ -0,0 +1,19 @@
++#as: -march=rv64ic
++#objdump: -drw
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+ <target>:
++[ 	]+[0-9a-f]+:[ 	]+c001[ 	]+beqz[ 	]+s0,0 <target>[ 	]+0: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+dcfd[ 	]+beqz[ 	]+s1,0 <target>[ 	]+2: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+fc75[ 	]+bnez[ 	]+s0,0 <target>[ 	]+4: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+fced[ 	]+bnez[ 	]+s1,0 <target>[ 	]+6: R_RISCV_RVC_BRANCH	.*
++[ 	]+[0-9a-f]+:[ 	]+bfe5[ 	]+j[ 	]+0 <target>[ 	]+8: R_RISCV_RVC_JUMP	.*
++[ 	]+[0-9a-f]+:[ 	]+ff7ff0ef[ 	]+jal[ 	]+0 <target>[ 	]+a: R_RISCV_JAL	.*
++[ 	]+[0-9a-f]+:[ 	]+9302[ 	]+jalr[ 	]+t1
++[ 	]+[0-9a-f]+:[ 	]+8382[ 	]+jr[ 	]+t2
++[ 	]+[0-9a-f]+:[ 	]+8082[ 	]+ret
++#...
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/c-branch.s
+@@ -0,0 +1,11 @@
++	.text
++target:
++	beq	x8, x0, target
++	beqz	x9, target
++	bne	x8, x0, target
++	bnez	x9, target
++	j	target
++	jal	target
++	jalr	x6
++	jr	x7
++	ret
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -340,9 +340,9 @@ const struct riscv_opcode riscv_opcodes[
+ {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
+ {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
+ {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
++{"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
+ {"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
+ {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
+-{"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
+ {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
+ {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
+ {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
diff --git a/toolchain/binutils/patches/2.40/034-bpf-fix-error-conversion-from-long-unsigned-int-to-u.patch b/toolchain/binutils/patches/2.40/034-bpf-fix-error-conversion-from-long-unsigned-int-to-u.patch
new file mode 100644
index 00000000000000..d4317cdb0fbda5
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/034-bpf-fix-error-conversion-from-long-unsigned-int-to-u.patch
@@ -0,0 +1,209 @@
+From 3e888977f165594cf44dbe8f67e3a4960b22c11f Mon Sep 17 00:00:00 2001
+From: "Guillermo E. Martinez" <guillermo.e.martinez@oracle.com>
+Date: Fri, 3 Feb 2023 11:17:49 -0600
+Subject: [PATCH 34/50] bpf: fix error conversion from long unsigned int to
+ unsigned int [-Werror=overflow]
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Regenerating BPF target using the maintainer mode emits:
+.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
+  57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+
+The use of a narrow size to handle the mask CGEN in instruction format
+is causing this error.  Additionally eBPF `call' instructions
+constructed by expressions using symbols (BPF_PSEUDO_CALL) emits
+annotations in `src' field of the instruction, used to identify BPF
+target endianness.
+
+cpu/
+	* bpf.cpu (define-call-insn): Remove `src' field from
+	instruction mask.
+
+include/
+	*opcode/cge.h (CGEN_IFMT): Adjust mask bit width.
+
+opcodes/
+	* bpf-opc.c: Regenerate.
+
+(cherry picked from commit 7f6ebecd56e690012b05af0a492280765b17f186)
+---
+ cpu/bpf.cpu           |  2 +-
+ include/opcode/cgen.h |  2 +-
+ opcodes/bpf-opc.c     | 54 +++++++++++++++++++++++--------------------
+ opcodes/cgen-dis.c    |  2 +-
+ 4 files changed, 32 insertions(+), 28 deletions(-)
+
+--- a/cpu/bpf.cpu
++++ b/cpu/bpf.cpu
+@@ -768,7 +768,7 @@
+        "call"
+        (endian-isas x-endian)
+        "call $disp32"
+-       (+ disp32 (f-offset16 0) (f-regs 0)
++       (+ disp32 (f-offset16 0) (.sym src x-endian) ((.sym f-dst x-endian) 0)
+           OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
+        (c-call VOID
+                "bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
+--- a/include/opcode/cgen.h
++++ b/include/opcode/cgen.h
+@@ -914,7 +914,7 @@ typedef struct
+      Each insn's value is stored with the insn.
+      The first step in recognizing an insn for disassembly is
+      (opcode & mask) == value.  */
+-  CGEN_INSN_INT mask;
++  CGEN_INSN_LGUINT mask;
+ #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
+ 
+   /* Instruction fields.
+--- a/opcodes/bpf-opc.c
++++ b/opcodes/bpf-opc.c
+@@ -50,99 +50,103 @@ static const CGEN_IFMT ifmt_empty ATTRIB
+ };
+ 
+ static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
+-  64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
+-  64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++};
++
++static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = {
++  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
+-  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
++  64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
+ };
+ 
+ #undef F
+@@ -1646,7 +1650,7 @@ static const CGEN_OPCODE bpf_cgen_insn_o
+   {
+     { 0, 0, 0, 0 },
+     { { MNEM, ' ', OP (DISP32), 0 } },
+-    & ifmt_callle, { 0x85 }
++    & ifmt_callbe, { 0x85 }
+   },
+ /* call $dstle */
+   {
+--- a/opcodes/cgen-dis.c
++++ b/opcodes/cgen-dis.c
+@@ -39,7 +39,7 @@ static void		 add_insn_to_hash_chain (CG
+ static int
+ count_decodable_bits (const CGEN_INSN *insn)
+ {
+-  unsigned mask = CGEN_INSN_BASE_MASK (insn);
++  CGEN_INSN_LGUINT mask = CGEN_INSN_BASE_MASK (insn);
+ #if GCC_VERSION >= 3004
+   return __builtin_popcount (mask);
+ #else
diff --git a/toolchain/binutils/patches/2.40/035-Pass-JANSSON_LIBS-and-ZSTD_LIBS-to-ld-bootstrap-boot.patch b/toolchain/binutils/patches/2.40/035-Pass-JANSSON_LIBS-and-ZSTD_LIBS-to-ld-bootstrap-boot.patch
new file mode 100644
index 00000000000000..3741c08a0c9969
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/035-Pass-JANSSON_LIBS-and-ZSTD_LIBS-to-ld-bootstrap-boot.patch
@@ -0,0 +1,50 @@
+From e1815414077347097e5bf0d75162add955e241d9 Mon Sep 17 00:00:00 2001
+From: Romain Geissler <romain.geissler@amadeus.com>
+Date: Sun, 5 Feb 2023 13:56:34 +0000
+Subject: [PATCH 35/50] Pass $JANSSON_LIBS and $ZSTD_LIBS to
+ ld-bootstrap/bootrap.exp
+
+---
+ ld/Makefile.am                          | 1 +
+ ld/Makefile.in                          | 1 +
+ ld/testsuite/ld-bootstrap/bootstrap.exp | 4 ++--
+ 3 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/ld/Makefile.am
++++ b/ld/Makefile.am
+@@ -992,6 +992,7 @@ check-DEJAGNU: site.exp
+ 		CXXFLAGS_FOR_TARGET="$(CXXFLAGS_FOR_TARGET)" \
+ 		OFILES="$(OFILES)" BFDLIB="$(TESTBFDLIB)" CTFLIB="$(TESTCTFLIB) $(ZLIB)" \
+ 		SFRAMELIB="$(TESTSFRAMELIB)" \
++		JANSSON_LIBS="$(JANSSON_LIBS)" ZSTD_LIBS="$(ZSTD_LIBS)" \
+ 		LIBIBERTY="$(LIBIBERTY) $(LIBINTL)" LIBS="$(LIBS)" \
+ 		DO_COMPARE="`echo '$(do_compare)' | sed -e 's,\\$$,,g'`" \
+ 		$(RUNTESTFLAGS); \
+--- a/ld/Makefile.in
++++ b/ld/Makefile.in
+@@ -2645,6 +2645,7 @@ check-DEJAGNU: site.exp
+ 		CXXFLAGS_FOR_TARGET="$(CXXFLAGS_FOR_TARGET)" \
+ 		OFILES="$(OFILES)" BFDLIB="$(TESTBFDLIB)" CTFLIB="$(TESTCTFLIB) $(ZLIB)" \
+ 		SFRAMELIB="$(TESTSFRAMELIB)" \
++		JANSSON_LIBS="$(JANSSON_LIBS)" ZSTD_LIBS="$(ZSTD_LIBS)" \
+ 		LIBIBERTY="$(LIBIBERTY) $(LIBINTL)" LIBS="$(LIBS)" \
+ 		DO_COMPARE="`echo '$(do_compare)' | sed -e 's,\\$$,,g'`" \
+ 		$(RUNTESTFLAGS); \
+--- a/ld/testsuite/ld-bootstrap/bootstrap.exp
++++ b/ld/testsuite/ld-bootstrap/bootstrap.exp
+@@ -162,13 +162,13 @@ foreach flags $test_flags {
+     }
+ 
+     if { [lindex [remote_exec build grep "-q \"HAVE_ZSTD 1\" config.h" ] 0] == 0 } then {
+-	set extralibs "$extralibs -lzstd"
++	set extralibs "$extralibs $ZSTD_LIBS"
+     }
+ 
+     # Check if the system's jansson library is used. If so, the object files will
+     # be using symbols from it, so link to it.
+     if { [lindex [remote_exec build grep "-q \"HAVE_JANSSON 1\" config.h" ] 0] == 0 } then {
+-	set extralibs "$extralibs -ljansson"
++	set extralibs "$extralibs $JANSSON_LIBS"
+     }
+ 
+     # Plugin support requires linking with libdl.
diff --git a/toolchain/binutils/patches/2.40/036-Regen-config-files.patch b/toolchain/binutils/patches/2.40/036-Regen-config-files.patch
new file mode 100644
index 00000000000000..1c80dde3102fbf
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/036-Regen-config-files.patch
@@ -0,0 +1,714 @@
+From 1fc096a4c590f28e0efb1823cdca653f2db9de74 Mon Sep 17 00:00:00 2001
+From: Alan Modra <amodra@gmail.com>
+Date: Mon, 6 Feb 2023 10:48:59 +1030
+Subject: [PATCH 36/50] Regen config files
+
+For the version update to 2.40.0
+---
+ bfd/configure                  | 20 ++++++++++----------
+ binutils/configure             | 20 ++++++++++----------
+ gas/configure                  | 20 ++++++++++----------
+ gprof/configure                | 20 ++++++++++----------
+ gprofng/configure              | 20 ++++++++++----------
+ gprofng/doc/version.texi       |  8 ++++----
+ gprofng/libcollector/configure | 20 ++++++++++----------
+ intl/configure                 |  3 +++
+ ld/configure                   | 20 ++++++++++----------
+ opcodes/configure              | 20 ++++++++++----------
+ 10 files changed, 87 insertions(+), 84 deletions(-)
+
+--- a/bfd/configure
++++ b/bfd/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for bfd 2.40.
++# Generated by GNU Autoconf 2.69 for bfd 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='bfd'
+ PACKAGE_TARNAME='bfd'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='bfd 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='bfd 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1400,7 +1400,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures bfd 2.40 to adapt to many kinds of systems.
++\`configure' configures bfd 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1471,7 +1471,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of bfd 2.40:";;
++     short | recursive ) echo "Configuration of bfd 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1608,7 +1608,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-bfd configure 2.40
++bfd configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2202,7 +2202,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by bfd $as_me 2.40, which was
++It was created by bfd $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3184,7 +3184,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='bfd'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -15906,7 +15906,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by bfd $as_me 2.40, which was
++This file was extended by bfd $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -15972,7 +15972,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-bfd config.status 2.40
++bfd config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/binutils/configure
++++ b/binutils/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for binutils 2.40.
++# Generated by GNU Autoconf 2.69 for binutils 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='binutils'
+ PACKAGE_TARNAME='binutils'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='binutils 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='binutils 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1401,7 +1401,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures binutils 2.40 to adapt to many kinds of systems.
++\`configure' configures binutils 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1472,7 +1472,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of binutils 2.40:";;
++     short | recursive ) echo "Configuration of binutils 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1631,7 +1631,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-binutils configure 2.40
++binutils configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2099,7 +2099,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by binutils $as_me 2.40, which was
++It was created by binutils $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3081,7 +3081,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='binutils'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -15326,7 +15326,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by binutils $as_me 2.40, which was
++This file was extended by binutils $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -15392,7 +15392,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-binutils config.status 2.40
++binutils config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gas/configure
++++ b/gas/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gas 2.40.
++# Generated by GNU Autoconf 2.69 for gas 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gas'
+ PACKAGE_TARNAME='gas'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='gas 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='gas 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1381,7 +1381,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gas 2.40 to adapt to many kinds of systems.
++\`configure' configures gas 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1452,7 +1452,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gas 2.40:";;
++     short | recursive ) echo "Configuration of gas 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1600,7 +1600,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gas configure 2.40
++gas configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2011,7 +2011,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gas $as_me 2.40, which was
++It was created by gas $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -2990,7 +2990,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gas'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -14910,7 +14910,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gas $as_me 2.40, which was
++This file was extended by gas $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -14976,7 +14976,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gas config.status 2.40
++gas config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gprof/configure
++++ b/gprof/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gprof 2.40.
++# Generated by GNU Autoconf 2.69 for gprof 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gprof'
+ PACKAGE_TARNAME='gprof'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='gprof 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='gprof 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1338,7 +1338,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gprof 2.40 to adapt to many kinds of systems.
++\`configure' configures gprof 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1409,7 +1409,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gprof 2.40:";;
++     short | recursive ) echo "Configuration of gprof 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1520,7 +1520,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gprof configure 2.40
++gprof configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -1885,7 +1885,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gprof $as_me 2.40, which was
++It was created by gprof $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -2864,7 +2864,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gprof'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -12572,7 +12572,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gprof $as_me 2.40, which was
++This file was extended by gprof $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -12638,7 +12638,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gprof config.status 2.40
++gprof config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gprofng/configure
++++ b/gprofng/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gprofng 2.40.
++# Generated by GNU Autoconf 2.69 for gprofng 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gprofng'
+ PACKAGE_TARNAME='gprofng'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='gprofng 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='gprofng 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1364,7 +1364,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gprofng 2.40 to adapt to many kinds of systems.
++\`configure' configures gprofng 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1435,7 +1435,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gprofng 2.40:";;
++     short | recursive ) echo "Configuration of gprofng 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1549,7 +1549,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gprofng configure 2.40
++gprofng configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2081,7 +2081,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gprofng $as_me 2.40, which was
++It was created by gprofng $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3054,7 +3054,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gprofng'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -17528,7 +17528,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gprofng $as_me 2.40, which was
++This file was extended by gprofng $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -17594,7 +17594,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gprofng config.status 2.40
++gprofng config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/gprofng/doc/version.texi
++++ b/gprofng/doc/version.texi
+@@ -1,4 +1,4 @@
+-@set UPDATED 5 January 2023
+-@set UPDATED-MONTH January 2023
+-@set EDITION 2.40
+-@set VERSION 2.40
++@set UPDATED 1 February 2023
++@set UPDATED-MONTH February 2023
++@set EDITION 2.40.0
++@set VERSION 2.40.0
+--- a/gprofng/libcollector/configure
++++ b/gprofng/libcollector/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for gprofng 2.40.
++# Generated by GNU Autoconf 2.69 for gprofng 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='gprofng'
+ PACKAGE_TARNAME='gprofng'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='gprofng 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='gprofng 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1325,7 +1325,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures gprofng 2.40 to adapt to many kinds of systems.
++\`configure' configures gprofng 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1396,7 +1396,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of gprofng 2.40:";;
++     short | recursive ) echo "Configuration of gprofng 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1505,7 +1505,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-gprofng configure 2.40
++gprofng configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -1991,7 +1991,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by gprofng $as_me 2.40, which was
++It was created by gprofng $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -2968,7 +2968,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='gprofng'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -16098,7 +16098,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by gprofng $as_me 2.40, which was
++This file was extended by gprofng $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -16164,7 +16164,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-gprofng config.status 2.40
++gprofng config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/intl/configure
++++ b/intl/configure
+@@ -6857,6 +6857,9 @@ case "${host}" in
+ 	# sets the default TLS model and affects inlining.
+ 	PICFLAG=-fPIC
+ 	;;
++    loongarch*-*-*)
++	PICFLAG=-fpic
++	;;
+     mips-sgi-irix6*)
+ 	# PIC is the default.
+ 	;;
+--- a/ld/configure
++++ b/ld/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for ld 2.40.
++# Generated by GNU Autoconf 2.69 for ld 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='ld'
+ PACKAGE_TARNAME='ld'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='ld 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='ld 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1423,7 +1423,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures ld 2.40 to adapt to many kinds of systems.
++\`configure' configures ld 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1494,7 +1494,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of ld 2.40:";;
++     short | recursive ) echo "Configuration of ld 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1661,7 +1661,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-ld configure 2.40
++ld configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2376,7 +2376,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by ld $as_me 2.40, which was
++It was created by ld $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3359,7 +3359,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='ld'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -18083,7 +18083,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by ld $as_me 2.40, which was
++This file was extended by ld $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -18149,7 +18149,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-ld config.status 2.40
++ld config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
+--- a/opcodes/configure
++++ b/opcodes/configure
+@@ -1,6 +1,6 @@
+ #! /bin/sh
+ # Guess values for system-dependent variables and create Makefiles.
+-# Generated by GNU Autoconf 2.69 for opcodes 2.40.
++# Generated by GNU Autoconf 2.69 for opcodes 2.40.0.
+ #
+ #
+ # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+@@ -587,8 +587,8 @@ MAKEFLAGS=
+ # Identity of this package.
+ PACKAGE_NAME='opcodes'
+ PACKAGE_TARNAME='opcodes'
+-PACKAGE_VERSION='2.40'
+-PACKAGE_STRING='opcodes 2.40'
++PACKAGE_VERSION='2.40.0'
++PACKAGE_STRING='opcodes 2.40.0'
+ PACKAGE_BUGREPORT=''
+ PACKAGE_URL=''
+ 
+@@ -1360,7 +1360,7 @@ if test "$ac_init_help" = "long"; then
+   # Omit some internal or obsolete options to make the list less imposing.
+   # This message is too long to be a string in the A/UX 3.1 sh.
+   cat <<_ACEOF
+-\`configure' configures opcodes 2.40 to adapt to many kinds of systems.
++\`configure' configures opcodes 2.40.0 to adapt to many kinds of systems.
+ 
+ Usage: $0 [OPTION]... [VAR=VALUE]...
+ 
+@@ -1431,7 +1431,7 @@ fi
+ 
+ if test -n "$ac_init_help"; then
+   case $ac_init_help in
+-     short | recursive ) echo "Configuration of opcodes 2.40:";;
++     short | recursive ) echo "Configuration of opcodes 2.40.0:";;
+    esac
+   cat <<\_ACEOF
+ 
+@@ -1545,7 +1545,7 @@ fi
+ test -n "$ac_init_help" && exit $ac_status
+ if $ac_init_version; then
+   cat <<\_ACEOF
+-opcodes configure 2.40
++opcodes configure 2.40.0
+ generated by GNU Autoconf 2.69
+ 
+ Copyright (C) 2012 Free Software Foundation, Inc.
+@@ -2139,7 +2139,7 @@ cat >config.log <<_ACEOF
+ This file contains any messages produced by compilers while
+ running configure, to aid debugging if configure makes a mistake.
+ 
+-It was created by opcodes $as_me 2.40, which was
++It was created by opcodes $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   $ $0 $@
+@@ -3118,7 +3118,7 @@ fi
+ 
+ # Define the identity of the package.
+  PACKAGE='opcodes'
+- VERSION='2.40'
++ VERSION='2.40.0'
+ 
+ 
+ cat >>confdefs.h <<_ACEOF
+@@ -13191,7 +13191,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_wri
+ # report actual input values of CONFIG_FILES etc. instead of their
+ # values after options handling.
+ ac_log="
+-This file was extended by opcodes $as_me 2.40, which was
++This file was extended by opcodes $as_me 2.40.0, which was
+ generated by GNU Autoconf 2.69.  Invocation command line was
+ 
+   CONFIG_FILES    = $CONFIG_FILES
+@@ -13257,7 +13257,7 @@ _ACEOF
+ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ ac_cs_version="\\
+-opcodes config.status 2.40
++opcodes config.status 2.40.0
+ configured by $0, generated by GNU Autoconf 2.69,
+   with options \\"\$ac_cs_config\\"
+ 
diff --git a/toolchain/binutils/patches/2.40/040-configure-remove-dependencies-on-gmp-and-mpfr-when-g.patch b/toolchain/binutils/patches/2.40/040-configure-remove-dependencies-on-gmp-and-mpfr-when-g.patch
new file mode 100644
index 00000000000000..261acb549e6143
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/040-configure-remove-dependencies-on-gmp-and-mpfr-when-g.patch
@@ -0,0 +1,51 @@
+From 17294931e3e361bee6810b1a39493e214b38c5e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= <chigot@adacore.com>
+Date: Tue, 3 Jan 2023 14:24:43 +0100
+Subject: [PATCH 40/50] configure: remove dependencies on gmp and mpfr when gdb
+ is disabled
+
+Since 991180627851801f1999d1ebbc0e569a17e47c74, the configure checks
+about GMP and MPFR for gdb builds have been moved to the toplevel
+configure.
+However, it doesn't take into account the --disable-gdb option. Meaning
+that a build without gdb will require these libraries even if not
+needed.
+
+ChangeLog:
+
+	* configure.ac: Skip GMP and MPFR when --disable-gdb is
+	provided.
+	* configure: Regenerate.
+
+(cherry picked from commit 5fb0e308577143ceb313fde5538dc9ecb038f29f)
+---
+ configure    | 4 +++-
+ configure.ac | 4 +++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/configure
++++ b/configure
+@@ -8032,7 +8032,9 @@ if test -d ${srcdir}/gcc ; then
+   require_mpc=yes
+ fi
+ if test -d ${srcdir}/gdb ; then
+-  require_gmp=yes
++  if test "x$enable_gdb" != xno; then
++   require_gmp=yes
++  fi
+ fi
+ 
+ gmplibs="-lmpfr -lgmp"
+--- a/configure.ac
++++ b/configure.ac
+@@ -1585,7 +1585,9 @@ if test -d ${srcdir}/gcc ; then
+   require_mpc=yes
+ fi
+ if test -d ${srcdir}/gdb ; then
+-  require_gmp=yes
++  if test "x$enable_gdb" != xno; then
++   require_gmp=yes
++  fi
+ fi
+ 
+ gmplibs="-lmpfr -lgmp"
diff --git a/toolchain/binutils/patches/2.40/046-gas-correct-symbol-name-comparison-in-.startof.-.siz.patch b/toolchain/binutils/patches/2.40/046-gas-correct-symbol-name-comparison-in-.startof.-.siz.patch
new file mode 100644
index 00000000000000..4e31bb43edb152
--- /dev/null
+++ b/toolchain/binutils/patches/2.40/046-gas-correct-symbol-name-comparison-in-.startof.-.siz.patch
@@ -0,0 +1,46 @@
+From b2bc62b7b4e7638c3a249d2d2728ceb4d5f2b22c Mon Sep 17 00:00:00 2001
+From: Jan Beulich <jbeulich@suse.com>
+Date: Tue, 14 Feb 2023 08:35:02 +0100
+Subject: [PATCH 46/50] gas: correct symbol name comparison in
+ .startof./.sizeof. handling
+
+In 162c6aef1f3a ("gas: fold symbol table entries generated for
+.startof.() / .sizeof.()") I screwed up quite badly, inverting the case
+sensitive and case insensitive comparison functions.
+---
+ gas/expr.c                      | 4 ++--
+ gas/testsuite/gas/elf/startof.d | 2 ++
+ gas/testsuite/gas/elf/startof.s | 3 +++
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+--- a/gas/expr.c
++++ b/gas/expr.c
+@@ -149,8 +149,8 @@ symbol_lookup_or_make (const char *name,
+ 
+     name = S_GET_NAME (symbolP);
+     if ((symbols_case_sensitive
+-	 ? strcasecmp (buf, name)
+-	 : strcmp (buf, name)) == 0)
++	 ? strcmp (buf, name)
++	 : strcasecmp (buf, name)) == 0)
+       {
+ 	free (buf);
+ 	return symbolP;
+--- a/gas/testsuite/gas/elf/startof.d
++++ b/gas/testsuite/gas/elf/startof.d
+@@ -7,4 +7,6 @@ Symbol table .*
+ #...
+      [1-8]: 0+ .* UND \.startof\.\.text
+      [2-9]: 0+ .* UND \.sizeof\.\.text
++ +[1-9][0-9]*: 0+ .* UND \.startof\.\.Text
++ +[1-9][0-9]*: 0+ .* UND \.sizeof\.\.TEXT
+ #pass
+--- a/gas/testsuite/gas/elf/startof.s
++++ b/gas/testsuite/gas/elf/startof.s
+@@ -4,3 +4,6 @@
+ 	.dc.a	0
+ 	.dc.a	.sizeof.(.text)
+ 	.dc.a	.startof.(.text)
++	.dc.a	0
++	.dc.a	.startof.(.Text)
++	.dc.a	.sizeof.(.TEXT)
diff --git a/toolchain/binutils/patches/2.41/300-001_ld_makefile_patch.patch b/toolchain/binutils/patches/2.41/300-001_ld_makefile_patch.patch
new file mode 100644
index 00000000000000..2dafd92a01d35b
--- /dev/null
+++ b/toolchain/binutils/patches/2.41/300-001_ld_makefile_patch.patch
@@ -0,0 +1,22 @@
+--- a/ld/Makefile.am
++++ b/ld/Makefile.am
+@@ -50,7 +50,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
+ # We put the scripts in the directory $(scriptdir)/ldscripts.
+ # We can't put the scripts in $(datadir) because the SEARCH_DIR
+ # directives need to be different for native and cross linkers.
+-scriptdir = $(tooldir)/lib
++scriptdir = $(libdir)
+ 
+ EMUL = @EMUL@
+ EMULATION_OFILES = @EMULATION_OFILES@
+--- a/ld/Makefile.in
++++ b/ld/Makefile.in
+@@ -573,7 +573,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
+ # We put the scripts in the directory $(scriptdir)/ldscripts.
+ # We can't put the scripts in $(datadir) because the SEARCH_DIR
+ # directives need to be different for native and cross linkers.
+-scriptdir = $(tooldir)/lib
++scriptdir = $(libdir)
+ BASEDIR = $(srcdir)/..
+ BFDDIR = $(BASEDIR)/bfd
+ INCDIR = $(BASEDIR)/include
diff --git a/toolchain/binutils/patches/2.41/400-mips_no_dynamic_linking_sym.patch b/toolchain/binutils/patches/2.41/400-mips_no_dynamic_linking_sym.patch
new file mode 100644
index 00000000000000..c50a988da46051
--- /dev/null
+++ b/toolchain/binutils/patches/2.41/400-mips_no_dynamic_linking_sym.patch
@@ -0,0 +1,18 @@
+--- a/bfd/elfxx-mips.c
++++ b/bfd/elfxx-mips.c
+@@ -8144,6 +8144,7 @@ _bfd_mips_elf_create_dynamic_sections (b
+ 
+       name = SGI_COMPAT (abfd) ? "_DYNAMIC_LINK" : "_DYNAMIC_LINKING";
+       bh = NULL;
++      if (0) {
+       if (!(_bfd_generic_link_add_one_symbol
+ 	    (info, abfd, name, BSF_GLOBAL, bfd_abs_section_ptr, 0,
+ 	     NULL, false, get_elf_backend_data (abfd)->collect, &bh)))
+@@ -8156,6 +8157,7 @@ _bfd_mips_elf_create_dynamic_sections (b
+ 
+       if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ 	return false;
++      }
+ 
+       if (! mips_elf_hash_table (info)->use_rld_obj_head)
+ 	{
diff --git a/toolchain/binutils/patches/2.41/500-Change-default-emulation-for-mips64-linux.patch b/toolchain/binutils/patches/2.41/500-Change-default-emulation-for-mips64-linux.patch
new file mode 100644
index 00000000000000..60676bbe549651
--- /dev/null
+++ b/toolchain/binutils/patches/2.41/500-Change-default-emulation-for-mips64-linux.patch
@@ -0,0 +1,48 @@
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -947,8 +947,8 @@ case "${targ}" in
+     want64=true
+     ;;
+   mips64*el-*-linux*)
+-    targ_defvec=mips_elf32_ntrad_le_vec
+-    targ_selvecs="mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_le_vec mips_elf64_trad_be_vec"
++    targ_defvec=mips_elf64_trad_le_vec
++    targ_selvecs="mips_elf32_ntrad_le_vec mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_be_vec"
+     ;;
+   mips64*-*-linux*-gnuabi64)
+     targ_defvec=mips_elf64_trad_be_vec
+@@ -956,8 +956,8 @@ case "${targ}" in
+     want64=true
+     ;;
+   mips64*-*-linux*)
+-    targ_defvec=mips_elf32_ntrad_be_vec
+-    targ_selvecs="mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
++    targ_defvec=mips_elf64_trad_be_vec
++    targ_selvecs="mips_elf32_ntrad_be_vec mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_le_vec"
+     ;;
+   mips*el-*-linux*)
+     targ_defvec=mips_elf32_trad_le_vec
+--- a/ld/configure.tgt
++++ b/ld/configure.tgt
+@@ -585,8 +585,8 @@ mips64*el-*-linux-gnuabi64)
+ 			targ_extra_emuls="elf64btsmip elf32ltsmipn32 elf32btsmipn32 elf32ltsmip elf32btsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+-mips64*el-*-linux-*)	targ_emul=elf32ltsmipn32
+-			targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip"
++mips64*el-*-linux-*)	targ_emul=elf64ltsmip
++			targ_extra_emuls="elf32btsmipn32 elf32ltsmipn32 elf32ltsmip elf32btsmip elf64btsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+ mips64*-*-linux-gnuabi64)
+@@ -594,8 +594,8 @@ mips64*-*-linux-gnuabi64)
+ 			targ_extra_emuls="elf64ltsmip elf32btsmipn32 elf32ltsmipn32 elf32btsmip elf32ltsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+-mips64*-*-linux-*)	targ_emul=elf32btsmipn32
+-			targ_extra_emuls="elf32ltsmipn32 elf32btsmip elf32ltsmip elf64btsmip elf64ltsmip"
++mips64*-*-linux-*)	targ_emul=elf64btsmip
++			targ_extra_emuls="elf32btsmipn32 elf32ltsmipn32 elf32btsmip elf32ltsmip elf64ltsmip"
+ 			targ_extra_libpath=$targ_extra_emuls
+ 			;;
+ mips*el-*-linux-*)	targ_emul=elf32ltsmip
diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in
index 8a31bf0d2e5e9a..3e7a0e152f4cf3 100644
--- a/toolchain/gcc/Config.in
+++ b/toolchain/gcc/Config.in
@@ -3,6 +3,7 @@
 choice
 	prompt "GCC compiler Version" if TOOLCHAINOPTS
 	default GCC_USE_VERSION_8 if mips || mipsel || mips64 || mips64el
+	default GCC_USE_VERSION_13 if loongarch64
 	default GCC_USE_VERSION_11
 	help
 	  Select the version of gcc you wish to use.
@@ -15,6 +16,9 @@ choice
 
 	config GCC_USE_VERSION_12
 		bool "gcc 12.x"
+		
+	config GCC_USE_VERSION_13
+		bool "gcc 13.x"	
 endchoice
 
 config GCC_USE_GRAPHITE
diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version
index da915851a5fb69..8670f49b4cfbcb 100644
--- a/toolchain/gcc/Config.version
+++ b/toolchain/gcc/Config.version
@@ -7,8 +7,14 @@ config GCC_VERSION_12
 	default y if GCC_USE_VERSION_12
 	bool
 
+config GCC_VERSION_13
+	default y if GCC_USE_VERSION_13
+	default y if loongarch64
+	bool
+
 config GCC_VERSION
 	string
 	default "8.4.0"		if GCC_VERSION_8
 	default "12.2.0"	if GCC_VERSION_12
+	default "13.2.0"	if GCC_VERSION_13
 	default "11.3.0"
diff --git a/toolchain/gcc/common.mk b/toolchain/gcc/common.mk
index 8cb21b50d8b9de..a87cf8ccaf33f2 100644
--- a/toolchain/gcc/common.mk
+++ b/toolchain/gcc/common.mk
@@ -41,6 +41,10 @@ ifeq ($(PKG_VERSION),12.2.0)
   PKG_HASH:=e549cf9cf3594a00e27b6589d4322d70e0720cdd213f39beb4181e06926230ff
 endif
 
+ifeq ($(PKG_VERSION),13.2.0)
+  PKG_HASH:=e275e76442a6067341a27f04c5c6b83d8613144004c0413528863dc6b5c743da
+endif
+
 PATCH_DIR=../patches-$(GCC_MAJOR_VERSION).x
 
 BUGURL=http://bugs.openwrt.org/
@@ -181,9 +185,13 @@ define Host/SetToolchainInfo
 	$(SED) 's,GCC_VERSION=.*,GCC_VERSION=$(GCC_VERSION),' $(TOOLCHAIN_DIR)/info.mk
 endef
 
-ifeq ($(GCC_MAJOR_VERSION),12)
-	GCC_VERSION_FILE:=gcc/genversion.cc
+ifeq ($(GCC_MAJOR_VERSION),11)
+	GCC_VERSION_FILE:=gcc/version.c
 else
+	GCC_VERSION_FILE:=gcc/genversion.cc
+endif
+
+ifeq ($(GCC_MAJOR_VERSION),8)
 	GCC_VERSION_FILE:=gcc/version.c
 endif
 
diff --git a/toolchain/gcc/patches-13.x/002-case_insensitive.patch b/toolchain/gcc/patches-13.x/002-case_insensitive.patch
new file mode 100644
index 00000000000000..409497e5a3d866
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/002-case_insensitive.patch
@@ -0,0 +1,24 @@
+commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e
+Author: Felix Fietkau <nbd@openwrt.org>
+Date:   Sun Oct 19 21:45:51 2014 +0000
+
+    gcc: do not assume that the Mac OS X filesystem is case insensitive
+    
+    Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+    
+    SVN-Revision: 42973
+
+--- a/include/filenames.h
++++ b/include/filenames.h
+@@ -44,11 +44,6 @@ extern "C" {
+ #  define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)
+ #  define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)
+ #else /* not DOSish */
+-#  if defined(__APPLE__)
+-#    ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+-#      define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+-#    endif
+-#  endif /* __APPLE__ */
+ #  define HAS_DRIVE_SPEC(f) (0)
+ #  define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)
+ #  define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)
diff --git a/toolchain/gcc/patches-13.x/010-documentation.patch b/toolchain/gcc/patches-13.x/010-documentation.patch
new file mode 100644
index 00000000000000..9646568afebdeb
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/010-documentation.patch
@@ -0,0 +1,35 @@
+commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2
+Author: Luka Perkov <luka@openwrt.org>
+Date:   Tue Feb 26 16:16:33 2013 +0000
+
+    gcc: don't build documentation
+    
+    This closes #13039.
+    
+    Signed-off-by: Luka Perkov <luka@openwrt.org>
+    
+    SVN-Revision: 35807
+
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -3397,18 +3397,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)
+ doc/gccint.info: $(TEXI_GCCINT_FILES)
+ doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+ 
+-doc/%.info: %.texi
+-	if [ x$(BUILD_INFO) = xinfo ]; then \
+-		$(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+-			-I $(gcc_docdir)/include -o $@ $<; \
+-	fi
++doc/%.info:
+ 
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
+-	if [ x$(BUILD_INFO) = xinfo ]; then \
+-		$(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
+-			-I $(gcc_docdir)/include -o $@ $<; \
+-	fi
++doc/gccinstall.info:
+ 
+ doc/cpp.dvi: $(TEXI_CPP_FILES)
+ doc/gcc.dvi: $(TEXI_GCC_FILES)
diff --git a/toolchain/gcc/patches-13.x/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches-13.x/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 00000000000000..856fd6a46cef1a
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -3134,6 +3134,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+       emit_insn (gen_update_got_version ());
+     }
+ 
++  if (TARGET_MIPS16 && TARGET_USE_GOT)
++    {
++      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++    }
++
+   if (TARGET_MIPS16
+       && TARGET_EXPLICIT_RELOCS
+       && TARGET_CALL_CLOBBERED_GP)
diff --git a/toolchain/gcc/patches-13.x/230-musl_libssp.patch b/toolchain/gcc/patches-13.x/230-musl_libssp.patch
new file mode 100644
index 00000000000000..fee068e1d60ac8
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/230-musl_libssp.patch
@@ -0,0 +1,13 @@
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -972,7 +972,9 @@ proper position among the other output f
+ #endif
+ 
+ #ifndef LINK_SSP_SPEC
+-#ifdef TARGET_LIBC_PROVIDES_SSP
++#if DEFAULT_LIBC == LIBC_MUSL
++#define LINK_SSP_SPEC "-lssp_nonshared"
++#elif defined(TARGET_LIBC_PROVIDES_SSP)
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+ 		       "|fstack-protector-strong|fstack-protector-explicit:}"
+ #else
diff --git a/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch b/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch
new file mode 100644
index 00000000000000..ce21e0433d11cb
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/300-mips_Os_cpu_rtx_cost_model.patch
@@ -0,0 +1,21 @@
+commit ecf7671b769fe96f7b5134be442089f8bdba55d2
+Author: Felix Fietkau <nbd@nbd.name>
+Date:   Thu Aug 4 20:29:45 2016 +0200
+
+gcc: add a patch to generate better code with Os on mips
+
+Also happens to reduce compressed code size a bit
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -20213,7 +20213,7 @@ mips_option_override (void)
+     flag_pcc_struct_return = 0;
+ 
+   /* Decide which rtx_costs structure to use.  */
+-  if (optimize_size)
++  if (0 && optimize_size)
+     mips_cost = &mips_rtx_cost_optimize_size;
+   else
+     mips_cost = &mips_rtx_cost_data[mips_tune];
diff --git a/toolchain/gcc/patches-13.x/810-arm-softfloat-libgcc.patch b/toolchain/gcc/patches-13.x/810-arm-softfloat-libgcc.patch
new file mode 100644
index 00000000000000..5c9d86aead7325
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/810-arm-softfloat-libgcc.patch
@@ -0,0 +1,33 @@
+commit 8570c4be394cff7282f332f97da2ff569a927ddb
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date:   Wed Feb 2 20:06:12 2011 +0000
+
+    fixup arm soft-float symbols
+    
+    SVN-Revision: 25325
+
+--- a/libgcc/config/arm/t-linux
++++ b/libgcc/config/arm/t-linux
+@@ -1,6 +1,10 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
+-	_ctzsi2 _arm_addsubdf3 _arm_addsubsf3
++	_ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \
++	_arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
++	_arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \
++	_arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \
++	_arm_fixsfsi _arm_fixunssfsi
+ 
+ # Just for these, we omit the frame pointer since it makes such a big
+ # difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -58,8 +58,6 @@
+    %{shared:-lc} \
+    %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+ 
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+ 
+ #define LINUX_TARGET_LINK_SPEC  "%{h*} \
diff --git a/toolchain/gcc/patches-13.x/820-libgcc_pic.patch b/toolchain/gcc/patches-13.x/820-libgcc_pic.patch
new file mode 100644
index 00000000000000..7d102981904fcd
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/820-libgcc_pic.patch
@@ -0,0 +1,44 @@
+commit c96312958c0621e72c9b32da5bc224ffe2161384
+Author: Felix Fietkau <nbd@openwrt.org>
+Date:   Mon Oct 19 23:26:09 2009 +0000
+
+    gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)
+    
+    SVN-Revision: 18086
+
+--- a/libgcc/Makefile.in
++++ b/libgcc/Makefile.in
+@@ -933,11 +933,12 @@ $(libgcov-driver-objects): %$(objext): $
+ 
+ # Static libraries.
+ libgcc.a: $(libgcc-objects)
++libgcc_pic.a: $(libgcc-s-objects)
+ libgcov.a: $(libgcov-objects)
+ libunwind.a: $(libunwind-objects)
+ libgcc_eh.a: $(libgcc-eh-objects)
+ 
+-libgcc.a libgcov.a libunwind.a libgcc_eh.a:
++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:
+ 	-rm -f $@
+ 
+ 	objects="$(objects)";					\
+@@ -961,7 +962,7 @@ all: libunwind.a
+ endif
+ 
+ ifeq ($(enable_shared),yes)
+-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)
++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)
+ ifneq ($(LIBUNWIND),)
+ all: libunwind$(SHLIB_EXT)
+ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)
+@@ -1167,6 +1168,10 @@ install-shared:
+ 	chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+ 	$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+ 
++	$(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/
++	chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++	$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++
+ 	$(subst @multilib_dir@,$(MULTIDIR),$(subst \
+ 		@shlib_base_name@,libgcc_s,$(subst \
+ 		@shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))
diff --git a/toolchain/gcc/patches-13.x/840-armv4_pass_fix-v4bx_to_ld.patch b/toolchain/gcc/patches-13.x/840-armv4_pass_fix-v4bx_to_ld.patch
new file mode 100644
index 00000000000000..82935f3d1d0bfa
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/840-armv4_pass_fix-v4bx_to_ld.patch
@@ -0,0 +1,28 @@
+commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date:   Wed Feb 2 19:34:36 2011 +0000
+
+    add armv4 fixup patches
+    
+    SVN-Revision: 25322
+
+
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -88,10 +88,15 @@
+ #define MUSL_DYNAMIC_LINKER \
+   "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+ 
++/* For armv4 we pass --fix-v4bx to linker to support EABI */
++#undef TARGET_FIX_V4BX_SPEC
++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
++  "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to
+    use the GNU/Linux version, not the generic BPABI version.  */
+ #undef  LINK_SPEC
+-#define LINK_SPEC EABI_LINK_SPEC					\
++#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC			\
+   LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC,				\
+ 		       LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC)
+ 
diff --git a/toolchain/gcc/patches-13.x/850-use_shared_libgcc.patch b/toolchain/gcc/patches-13.x/850-use_shared_libgcc.patch
new file mode 100644
index 00000000000000..f4505ee70ffdc8
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/850-use_shared_libgcc.patch
@@ -0,0 +1,54 @@
+commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd
+Author: Felix Fietkau <nbd@openwrt.org>
+Date:   Sun Feb 12 20:25:47 2012 +0000
+
+    gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary
+    
+    SVN-Revision: 30486
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -129,10 +129,6 @@
+   "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} "	\
+   LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
+ 
+-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+-   do not use -lfloat.  */
+-#undef LIBGCC_SPEC
+-
+ /* Clear the instruction cache from `beg' to `end'.  This is
+    implemented in lib1funcs.S, so ensure an error if this definition
+    is used.  */
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -58,6 +58,10 @@ see the files COPYING3 and COPYING.RUNTI
+ 	builtin_assert ("system=posix");			\
+     } while (0)
+ 
++#ifndef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}"
++#endif
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+    uClibc or Bionic or musl is the default C library and whether
+    -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+--- a/libgcc/mkmap-symver.awk
++++ b/libgcc/mkmap-symver.awk
+@@ -136,5 +136,5 @@ function output(lib) {
+   else if (inherit[lib])
+     printf("} %s;\n", inherit[lib]);
+   else
+-    printf ("\n  local:\n\t*;\n};\n");
++    printf ("\n\t*;\n};\n");
+ }
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -67,6 +67,9 @@
+ #undef	CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+ 
++#undef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc"
++
+ #undef  LINK_SHLIB_SPEC
+ #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \
+   %{static-pie:-static -pie --no-dynamic-linker -z text}"
diff --git a/toolchain/gcc/patches-13.x/851-libgcc_no_compat.patch b/toolchain/gcc/patches-13.x/851-libgcc_no_compat.patch
new file mode 100644
index 00000000000000..d710e407174717
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/851-libgcc_no_compat.patch
@@ -0,0 +1,22 @@
+commit 64661de100da1ec1061ef3e5e400285dce115e6b
+Author: Felix Fietkau <nbd@openwrt.org>
+Date:   Sun May 10 13:16:35 2015 +0000
+
+    gcc: add some size optimization patches
+    
+    Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+    
+    SVN-Revision: 45664
+
+--- a/libgcc/config/t-libunwind
++++ b/libgcc/config/t-libunwind
+@@ -2,8 +2,7 @@
+ 
+ HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER
+ 
+-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \
+-  $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c
++LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+ LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+ 
+ # Override the default value from t-slibgcc-elf-ver and mention -lunwind
diff --git a/toolchain/gcc/patches-13.x/870-ppc_no_crtsavres.patch b/toolchain/gcc/patches-13.x/870-ppc_no_crtsavres.patch
new file mode 100644
index 00000000000000..0dca68899eb090
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/870-ppc_no_crtsavres.patch
@@ -0,0 +1,11 @@
+--- a/gcc/config/rs6000/rs6000-logue.cc
++++ b/gcc/config/rs6000/rs6000-logue.cc
+@@ -344,7 +344,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+   /* Define cutoff for using out-of-line functions to save registers.  */
+   if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
+     {
+-      if (!optimize_size)
++      if (1)
+ 	{
+ 	  strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
+ 	  strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
diff --git a/toolchain/gcc/patches-13.x/881-no_tm_section.patch b/toolchain/gcc/patches-13.x/881-no_tm_section.patch
new file mode 100644
index 00000000000000..2029910fd07926
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/881-no_tm_section.patch
@@ -0,0 +1,11 @@
+--- a/libgcc/crtstuff.c
++++ b/libgcc/crtstuff.c
+@@ -152,7 +152,7 @@ call_ ## FUNC (void)					\
+ #endif
+ 
+ #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)
+-# define USE_TM_CLONE_REGISTRY 1
++# define USE_TM_CLONE_REGISTRY 0
+ #elif !defined(USE_TM_CLONE_REGISTRY)
+ # define USE_TM_CLONE_REGISTRY 0
+ #endif
diff --git a/toolchain/gcc/patches-13.x/900-bad-mips16-crt.patch b/toolchain/gcc/patches-13.x/900-bad-mips16-crt.patch
new file mode 100644
index 00000000000000..dd6e9dc889ad07
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/900-bad-mips16-crt.patch
@@ -0,0 +1,9 @@
+--- a/libgcc/config/mips/t-mips16
++++ b/libgcc/config/mips/t-mips16
+@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16
+ 
+ # Version these symbols if building libgcc.so.
+ SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver
++
++CRTSTUFF_T_CFLAGS += -mno-mips16
++CRTSTUFF_T_CFLAGS_S += -mno-mips16
diff --git a/toolchain/gcc/patches-13.x/910-mbsd_multi.patch b/toolchain/gcc/patches-13.x/910-mbsd_multi.patch
new file mode 100644
index 00000000000000..4138e79bcc8381
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/910-mbsd_multi.patch
@@ -0,0 +1,146 @@
+commit 99368862e44740ff4fd33760893f04e14f9dbdf1
+Author: Felix Fietkau <nbd@openwrt.org>
+Date:   Tue Jul 31 00:52:27 2007 +0000
+
+    Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly
+    
+    SVN-Revision: 8256
+
+	This patch brings over a feature from MirBSD:
+	* -fhonour-copts
+	  If this option is not given, it's warned (depending
+	  on environment variables). This is to catch errors
+	  of misbuilt packages which override CFLAGS themselves.
+
+	This patch was authored by Thorsten Glaser <tg at mirbsd.de>
+	with copyright assignment to the FSF in effect.
+
+--- a/gcc/c-family/c-opts.cc
++++ b/gcc/c-family/c-opts.cc
+@@ -104,6 +104,9 @@ static size_t include_cursor;
+ /* Whether any standard preincluded header has been preincluded.  */
+ static bool done_preinclude;
+ 
++/* Check if a port honours COPTS.  */
++static int honour_copts = 0;
++
+ static void handle_OPT_d (const char *);
+ static void set_std_cxx98 (int);
+ static void set_std_cxx11 (int);
+@@ -475,6 +478,12 @@ c_common_handle_option (size_t scode, co
+       flag_no_builtin = !value;
+       break;
+ 
++    case OPT_fhonour_copts:
++      if (c_language == clk_c) {
++        honour_copts++;
++      }
++      break;
++
+     case OPT_fconstant_string_class_:
+       constant_string_class_name = arg;
+       break;
+@@ -1228,6 +1237,47 @@ c_common_init (void)
+       return false;
+     }
+ 
++  if (c_language == clk_c) {
++    char *ev = getenv ("GCC_HONOUR_COPTS");
++    int evv;
++    if (ev == NULL)
++      evv = -1;
++    else if ((*ev == '0') || (*ev == '\0'))
++      evv = 0;
++    else if (*ev == '1')
++      evv = 1;
++    else if (*ev == '2')
++      evv = 2;
++    else if (*ev == 's')
++      evv = -1;
++    else {
++      warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1");
++      evv = 1; /* maybe depend this on something like MIRBSD_NATIVE?  */
++    }
++    if (evv == 1) {
++      if (honour_copts == 0) {
++        error ("someone does not honour COPTS at all in lenient mode");
++        return false;
++      } else if (honour_copts != 1) {
++        warning (0, "someone does not honour COPTS correctly, passed %d times",
++         honour_copts);
++      }
++    } else if (evv == 2) {
++      if (honour_copts == 0) {
++        error ("someone does not honour COPTS at all in strict mode");
++        return false;
++      } else if (honour_copts != 1) {
++        error ("someone does not honour COPTS correctly, passed %d times",
++         honour_copts);
++        return false;
++      }
++    } else if (evv == 0) {
++      if (honour_copts != 1)
++        inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times",
++         honour_copts);
++    }
++  }
++
+   return true;
+ }
+ 
+--- a/gcc/c-family/c.opt
++++ b/gcc/c-family/c.opt
+@@ -1837,6 +1837,9 @@ C++ ObjC++ Optimization Alias(fexception
+ fhonor-std
+ C++ ObjC++ WarnRemoved
+ 
++fhonour-copts
++C ObjC C++ ObjC++ RejectNegative
++
+ fhosted
+ C ObjC
+ Assume normal C execution environment.
+--- a/gcc/common.opt
++++ b/gcc/common.opt
+@@ -1801,6 +1801,9 @@ fharden-conditional-branches
+ Common Var(flag_harden_conditional_branches) Optimization
+ Harden conditional branches by checking reversed conditions.
+ 
++fhonour-copts
++Common RejectNegative
++
+ ; Nonzero means ignore `#ident' directives.  0 means handle them.
+ ; Generate position-independent code for executables if possible
+ ; On SVR4 targets, it also controls whether or not to emit a
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -10065,6 +10065,17 @@ This option is only supported for C and
+ @option{-Wall} and by @option{-Wpedantic}, which can be disabled with
+ @option{-Wno-pointer-sign}.
+ 
++@item -fhonour-copts
++@opindex fhonour-copts
++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not
++given at least once, and warn if it is given more than once.
++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not
++given exactly once.
++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option
++is not given exactly once.
++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.
++This flag and environment variable only affect the C language.
++
+ @opindex Wstack-protector
+ @opindex Wno-stack-protector
+ @item -Wstack-protector
+--- a/gcc/opts.cc
++++ b/gcc/opts.cc
+@@ -2767,6 +2767,9 @@ common_handle_option (struct gcc_options
+       add_comma_separated_to_vector (&opts->x_flag_ignored_attributes, arg);
+       break;
+ 
++    case OPT_fhonour_copts:
++      break;
++
+     case OPT_Werror:
+       dc->warning_as_error_requested = value;
+       break;
diff --git a/toolchain/gcc/patches-13.x/920-specs_nonfatal_getenv.patch b/toolchain/gcc/patches-13.x/920-specs_nonfatal_getenv.patch
new file mode 100644
index 00000000000000..265ca22c0c3cdb
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/920-specs_nonfatal_getenv.patch
@@ -0,0 +1,22 @@
+Author: Jo-Philipp Wich <jow@openwrt.org>
+Date:   Sat Apr 21 03:02:39 2012 +0000
+
+    gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset
+    
+    SVN-Revision: 31390
+
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -10174,8 +10174,10 @@ getenv_spec_function (int argc, const ch
+     }
+ 
+   if (!value)
+-    fatal_error (input_location,
+-		 "environment variable %qs not defined", varname);
++    {
++      warning (input_location, "environment variable %qs not defined", varname);
++      value = "";
++    }
+ 
+   /* We have to escape every character of the environment variable so
+      they are not interpreted as active spec characters.  A
diff --git a/toolchain/gcc/patches-13.x/960-gotools-fix-compilation-when-making-cross-compiler.patch b/toolchain/gcc/patches-13.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
new file mode 100644
index 00000000000000..b1d7576328f51a
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/960-gotools-fix-compilation-when-making-cross-compiler.patch
@@ -0,0 +1,67 @@
+From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001
+From: Yousong Zhou <yszhou4tech@gmail.com>
+Date: Fri, 4 May 2018 18:20:53 +0800
+Subject: [PATCH] gotools: fix compilation when making cross compiler
+
+libgo is "the runtime support library for the Go programming language.
+This library is intended for use with the Go frontend."
+
+gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but
+the linker will complain that it cannot find it.  That's because shared libgcc
+is not present in the install directory yet.  libgo.so was made without problem
+because gcc will emit -lgcc_s when compiled with -shared option.  When gotools
+were being made, it was supplied with -static-libgcc thus no link option was
+provided.  Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec
+for linking with libgo.so
+
+- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation
+- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html
+
+When 3-pass GCC compilation is used, shared libgcc runtime libraries will be
+available after gcc pass2 completed and will meet the gotools link requirement
+at gcc pass3
+---
+ gotools/Makefile.am | 4 +++-
+ gotools/Makefile.in | 4 +++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/gotools/Makefile.am
++++ b/gotools/Makefile.am
+@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ 
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+ 
+ LIBGOTOOL = $(libgodir)/libgotool.a
+@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ 
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++	-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ 
+ libgosrcdir = $(srcdir)/../libgo/go
+--- a/gotools/Makefile.in
++++ b/gotools/Makefile.in
+@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+ LIBGOTOOL = $(libgodir)/libgotool.a
+ @NATIVE_FALSE@GOCOMPILER = $(GOC)
+@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a
+ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++	-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ libgosrcdir = $(srcdir)/../libgo/go
+ cmdsrcdir = $(libgosrcdir)/cmd
diff --git a/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch b/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch
new file mode 100644
index 00000000000000..7844268e7e2206
--- /dev/null
+++ b/toolchain/gcc/patches-13.x/970-macos_arm64-building-fix.patch
@@ -0,0 +1,45 @@
+commit 9c6e71079b46ad5433165feaa2001450f2017b56
+Author: Przemysław Buczkowski <prem@prem.moe>
+Date:   Mon Aug 16 13:16:21 2021 +0100
+
+    GCC: Patch for Apple Silicon compatibility
+    
+    This patch fixes a linker error occuring when compiling
+    the cross-compiler on macOS and ARM64 architecture.
+    
+    Adapted from:
+    https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404
+    
+    Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913
+    Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329
+    Reviewed-by: John Scipione <jscipione@gmail.com>
+    Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
+
+--- a/gcc/config/aarch64/aarch64.h
++++ b/gcc/config/aarch64/aarch64.h
+@@ -1185,7 +1185,7 @@ extern enum aarch64_code_model aarch64_c
+ 
+ /* Extra specs when building a native AArch64-hosted compiler.
+    Option rewriting rules based on host system.  */
+-#if defined(__aarch64__)
++#if defined(__aarch64__) && ! defined(__APPLE__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ #define HAVE_LOCAL_CPU_DETECT
+ # define EXTRA_SPEC_FUNCTIONS                                           \
+--- a/gcc/config/host-darwin.cc
++++ b/gcc/config/host-darwin.cc
+@@ -23,6 +23,8 @@
+ #include "options.h"
+ #include "diagnostic-core.h"
+ #include "config/host-darwin.h"
++#include "hosthooks.h"
++#include "hosthooks-def.h"
+ #include <errno.h>
+ 
+ /* For Darwin (macOS only) platforms, without ASLR (PIE) enabled on the
+@@ -181,3 +183,5 @@ darwin_gt_pch_use_address (void *&addr,
+ 
+   return 1;
+ }
++
++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
diff --git a/toolchain/gdb/Makefile b/toolchain/gdb/Makefile
index 70a4fa59026fc6..ecb31398e6edfd 100644
--- a/toolchain/gdb/Makefile
+++ b/toolchain/gdb/Makefile
@@ -7,12 +7,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=gdb
-PKG_VERSION:=12.1
+PKG_VERSION:=14.1
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@GNU/gdb
-PKG_HASH:=0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed
+PKG_HASH:=d66df51276143451fcbff464cc8723d68f1e9df45a6a2d5635a54e71643edb80
+PKG_CPE_ID:=cpe:/a:gnu:gdb
 GDB_DIR:=$(PKG_NAME)-$(PKG_VERSION)
 
 HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(GDB_DIR)
@@ -21,6 +22,9 @@ HOST_BUILD_PARALLEL:=1
 
 include $(INCLUDE_DIR)/toolchain-build.mk
 
+export ZSTD_CFLAGS=-I$(STAGING_DIR_HOST)/include -pthread
+export ZSTD_LIBS=-L$(STAGING_DIR_HOST)/lib -lzstd -lpthread
+
 HOST_CONFIGURE_VARS += \
 	acx_cv_cc_gcc_supports_ada=false \
 	gdb_cv_func_sigsetjmp=yes
diff --git a/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch b/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch
index 118bebe3c82bba..94305092788977 100644
--- a/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch
+++ b/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch
@@ -1,6 +1,6 @@
 --- a/gdbserver/configure
 +++ b/gdbserver/configure
-@@ -2664,7 +2664,7 @@ $as_echo "$as_me: error: \`$ac_var' was
+@@ -2674,7 +2674,7 @@ $as_echo "$as_me: error: \`$ac_var' was
        ac_cache_corrupted=: ;;
      ,);;
      *)
diff --git a/toolchain/glibc/common.mk b/toolchain/glibc/common.mk
index 314144eeab8fb6..e3b19a105b6062 100644
--- a/toolchain/glibc/common.mk
+++ b/toolchain/glibc/common.mk
@@ -7,15 +7,16 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=glibc
-PKG_VERSION:=2.36
+PKG_VERSION:=2.37
 PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=3aae843e9e9e6a2502e98ff44d2671b20a023f8e
-PKG_MIRROR_HASH:=29bdd6ca699f297de500ea457741d0706d57a69836fa7d45e6cc2cc20484cad4
+PKG_SOURCE_VERSION:=b4e23c75aea756b4bddc4abcf27a1c6dca8b6bd3
+PKG_MIRROR_HASH:=4d5b3de6ec7b47427700f74fdb529e32083b54a512f6ca86ec824a61092ecdd4
 PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz
+PKG_CPE_ID:=cpe:/a:gnu:glibc
 
 HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(PKG_SOURCE_SUBDIR)
 CUR_BUILD_DIR:=$(HOST_BUILD_DIR)-$(VARIANT)
diff --git a/toolchain/musl/Makefile b/toolchain/musl/Makefile
index 2b9312bcbf123c..d441e37684769a 100644
--- a/toolchain/musl/Makefile
+++ b/toolchain/musl/Makefile
@@ -9,7 +9,7 @@ HOST_BUILD_PARALLEL:=1
 
 MUSL_MAKEOPTS = -C $(HOST_BUILD_DIR) \
 	DESTDIR="$(TOOLCHAIN_DIR)/" \
-	LIBCC="$(subst libgcc.a,libgcc_initial.a,$(shell $(TARGET_CC) -print-libgcc-file-name))"
+	LIBCC="$(shell $(TARGET_CC) -print-libgcc-file-name)"
 
 define Host/SetToolchainInfo
 	$(SED) 's,^\(LIBC_TYPE\)=.*,\1=$(PKG_NAME),' $(TOOLCHAIN_DIR)/info.mk
diff --git a/toolchain/musl/common.mk b/toolchain/musl/common.mk
index 040127c3bccdb6..94444eaf75d25b 100644
--- a/toolchain/musl/common.mk
+++ b/toolchain/musl/common.mk
@@ -8,12 +8,13 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/target.mk
 
 PKG_NAME:=musl
-PKG_VERSION:=1.2.3
+PKG_VERSION:=1.2.4
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://musl.libc.org/releases/
-PKG_HASH:=7d5b0b6062521e4627e099e4c9dc8248d32a30285e959b7eecaa780cf8cfd4a4
+PKG_HASH:=7a35eae33d5372a7c0da1188de798726f68825513b7ae3ebe97aaaa52114f039
+PKG_CPE_ID:=cpe:/a:musl-libc:musl
 
 LIBC_SO_VERSION:=$(PKG_VERSION)
 PATCH_DIR:=$(PATH_PREFIX)/patches
diff --git a/toolchain/musl/patches/600-nftw-support-common-gnu-extension.patch b/toolchain/musl/patches/600-nftw-support-common-gnu-extension.patch
index 2a7436cf8489b4..7a1ab3f99a3619 100644
--- a/toolchain/musl/patches/600-nftw-support-common-gnu-extension.patch
+++ b/toolchain/musl/patches/600-nftw-support-common-gnu-extension.patch
@@ -33,7 +33,7 @@ Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
  #include <ftw.h>
  #include <dirent.h>
  #include <fcntl.h>
-@@ -72,8 +73,20 @@ static int do_nftw(char *path, int (*fn)
+@@ -74,8 +75,20 @@ static int do_nftw(char *path, int (*fn)
  		if (!fd_limit) close(dfd);
  	}
  
@@ -56,7 +56,7 @@ Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
  
  	for (; h; h = h->chain)
  		if (h->dev == st.st_dev && h->ino == st.st_ino)
-@@ -101,7 +114,10 @@ static int do_nftw(char *path, int (*fn)
+@@ -103,7 +116,10 @@ static int do_nftw(char *path, int (*fn)
  				strcpy(path+j+1, de->d_name);
  				if ((r=do_nftw(path, fn, fd_limit-1, flags, &new))) {
  					closedir(d);
@@ -68,7 +68,7 @@ Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
  				}
  			}
  			closedir(d);
-@@ -112,8 +128,16 @@ static int do_nftw(char *path, int (*fn)
+@@ -114,8 +130,16 @@ static int do_nftw(char *path, int (*fn)
  	}
  
  	path[l] = 0;
@@ -87,9 +87,9 @@ Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
  
  	return 0;
  }
-@@ -139,4 +163,5 @@ int nftw(const char *path, int (*fn)(con
+@@ -140,3 +164,5 @@ int nftw(const char *path, int (*fn)(con
+ 	pthread_setcancelstate(cs, 0);
  	return r;
  }
- 
++
 +#undef nftw64
- weak_alias(nftw, nftw64);
diff --git a/toolchain/musl/patches/800-mips_pie_debug.patch b/toolchain/musl/patches/800-mips_pie_debug.patch
deleted file mode 100644
index 80fe15e84188d1..00000000000000
--- a/toolchain/musl/patches/800-mips_pie_debug.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-Fix DT_DEBUG handling on MIPS in musl libc.
-With this change gdb will load the symbol files for shared libraries on MIPS too.
-
-This patch was taken from this thread: https://www.openwall.com/lists/musl/2022/01/09/4
-
---- a/arch/mips/reloc.h
-+++ b/arch/mips/reloc.h
-@@ -29,6 +29,7 @@
- 
- #define NEED_MIPS_GOT_RELOCS 1
- #define DT_DEBUG_INDIRECT DT_MIPS_RLD_MAP
-+#define DT_DEBUG_INDIRECT_REL DT_MIPS_RLD_MAP_REL
- #define ARCH_SYM_REJECT_UND(s) (!((s)->st_other & STO_MIPS_PLT))
- 
- #define CRTJMP(pc,sp) __asm__ __volatile__( \
---- a/arch/mips64/reloc.h
-+++ b/arch/mips64/reloc.h
-@@ -38,6 +38,7 @@
- 
- #define NEED_MIPS_GOT_RELOCS 1
- #define DT_DEBUG_INDIRECT DT_MIPS_RLD_MAP
-+#define DT_DEBUG_INDIRECT_REL DT_MIPS_RLD_MAP_REL
- #define ARCH_SYM_REJECT_UND(s) (!((s)->st_other & STO_MIPS_PLT))
- 
- #define CRTJMP(pc,sp) __asm__ __volatile__( \
---- a/arch/mipsn32/reloc.h
-+++ b/arch/mipsn32/reloc.h
-@@ -29,6 +29,7 @@
- 
- #define NEED_MIPS_GOT_RELOCS 1
- #define DT_DEBUG_INDIRECT DT_MIPS_RLD_MAP
-+#define DT_DEBUG_INDIRECT_REL DT_MIPS_RLD_MAP_REL
- #define ARCH_SYM_REJECT_UND(s) (!((s)->st_other & STO_MIPS_PLT))
- 
- #define CRTJMP(pc,sp) __asm__ __volatile__( \
---- a/ldso/dynlink.c
-+++ b/ldso/dynlink.c
-@@ -1923,6 +1923,10 @@ void __dls3(size_t *sp, size_t *auxv)
- 			size_t *ptr = (size_t *) app.dynv[i+1];
- 			*ptr = (size_t)&debug;
- 		}
-+		if (app.dynv[i]==DT_DEBUG_INDIRECT_REL) {
-+			size_t *ptr = (size_t *)((size_t)&app.dynv[i] + app.dynv[i+1]);
-+			*ptr = (size_t)&debug;
-+		}
- 	}
- 
- 	/* This must be done before final relocations, since it calls
---- a/src/internal/dynlink.h
-+++ b/src/internal/dynlink.h
-@@ -92,6 +92,10 @@ struct fdpic_dummy_loadmap {
- #define DT_DEBUG_INDIRECT 0
- #endif
- 
-+#ifndef DT_DEBUG_INDIRECT_REL
-+#define DT_DEBUG_INDIRECT_REL 0
-+#endif
-+
- #define AUX_CNT 32
- #define DYN_CNT 32
- 
diff --git a/toolchain/musl/patches/990-add_loongarch64_support.patch b/toolchain/musl/patches/990-add_loongarch64_support.patch
new file mode 100644
index 00000000000000..fc6fa6913f20ff
--- /dev/null
+++ b/toolchain/musl/patches/990-add_loongarch64_support.patch
@@ -0,0 +1,1404 @@
+>From 2d5f9717fda5c16f10d805ce8a26f1e78de440ea Mon Sep 17 00:00:00 2001
+From: wanghongliang <wanghongliang@loongson.cn>
+Date: Wed, 15 Nov 2023 01:31:51 +0800
+Subject: [PATCH] add loongarch64 port v9.
+
+Author: Xiaojuan Zhai <zhaixiaojuan@loongson.cn>
+Author: Meidan Li <limeidan@loongson.cn>
+Author: Guoqi Chen <chenguoqi@loongson.cn>
+Author: Xiaolin Zhao <zhaoxiaolin@loongson.cn>
+Author: Fan peng <fanpeng@loongson.cn>
+Author: Jiantao Shan <shanjiantao@loongson.cn>
+Author: Xuhui Qiang <qiangxuhui@loongson.cn>
+Author: Jingyun Hua <huajingyun@loongson.cn>
+Author: Liu xue <liuxue@loongson.cn>
+Author: Hongliang Wang <wanghongliang@loongson.cn>
+
+Signed-off-by: wanghongliang <wanghongliang@loongson.cn>
+---
+ arch/loongarch64/atomic_arch.h             |  53 ++++
+ arch/loongarch64/bits/alltypes.h.in        |  18 ++
+ arch/loongarch64/bits/fenv.h               |  20 ++
+ arch/loongarch64/bits/float.h              |  16 ++
+ arch/loongarch64/bits/posix.h              |   2 +
+ arch/loongarch64/bits/ptrace.h             |   4 +
+ arch/loongarch64/bits/reg.h                |   2 +
+ arch/loongarch64/bits/setjmp.h             |   1 +
+ arch/loongarch64/bits/signal.h             |  92 +++++++
+ arch/loongarch64/bits/stat.h               |  18 ++
+ arch/loongarch64/bits/stdint.h             |  20 ++
+ arch/loongarch64/bits/syscall.h.in         | 303 +++++++++++++++++++++
+ arch/loongarch64/bits/user.h               |   5 +
+ arch/loongarch64/crt_arch.h                |  13 +
+ arch/loongarch64/pthread_arch.h            |  11 +
+ arch/loongarch64/reloc.h                   |  29 ++
+ arch/loongarch64/syscall_arch.h            | 137 ++++++++++
+ configure                                  |  15 +
+ include/elf.h                              | 104 ++++++-
+ src/fenv/loongarch64/fenv.S                |  78 ++++++
+ src/ldso/loongarch64/dlsym.s               |   7 +
+ src/setjmp/loongarch64/longjmp.S           |  32 +++
+ src/setjmp/loongarch64/setjmp.S            |  34 +++
+ src/signal/loongarch64/restore.s           |  10 +
+ src/signal/loongarch64/sigsetjmp.s         |  25 ++
+ src/thread/loongarch64/__set_thread_area.s |   7 +
+ src/thread/loongarch64/__unmapself.s       |   7 +
+ src/thread/loongarch64/clone.s             |  28 ++
+ src/thread/loongarch64/syscall_cp.s        |  29 ++
+ 29 files changed, 1119 insertions(+), 1 deletion(-)
+ create mode 100644 arch/loongarch64/atomic_arch.h
+ create mode 100644 arch/loongarch64/bits/alltypes.h.in
+ create mode 100644 arch/loongarch64/bits/fenv.h
+ create mode 100644 arch/loongarch64/bits/float.h
+ create mode 100644 arch/loongarch64/bits/posix.h
+ create mode 100644 arch/loongarch64/bits/ptrace.h
+ create mode 100644 arch/loongarch64/bits/reg.h
+ create mode 100644 arch/loongarch64/bits/setjmp.h
+ create mode 100644 arch/loongarch64/bits/signal.h
+ create mode 100644 arch/loongarch64/bits/stat.h
+ create mode 100644 arch/loongarch64/bits/stdint.h
+ create mode 100644 arch/loongarch64/bits/syscall.h.in
+ create mode 100644 arch/loongarch64/bits/user.h
+ create mode 100644 arch/loongarch64/crt_arch.h
+ create mode 100644 arch/loongarch64/pthread_arch.h
+ create mode 100644 arch/loongarch64/reloc.h
+ create mode 100644 arch/loongarch64/syscall_arch.h
+ create mode 100644 src/fenv/loongarch64/fenv.S
+ create mode 100644 src/ldso/loongarch64/dlsym.s
+ create mode 100644 src/setjmp/loongarch64/longjmp.S
+ create mode 100644 src/setjmp/loongarch64/setjmp.S
+ create mode 100644 src/signal/loongarch64/restore.s
+ create mode 100644 src/signal/loongarch64/sigsetjmp.s
+ create mode 100644 src/thread/loongarch64/__set_thread_area.s
+ create mode 100644 src/thread/loongarch64/__unmapself.s
+ create mode 100644 src/thread/loongarch64/clone.s
+ create mode 100644 src/thread/loongarch64/syscall_cp.s
+
+diff --git a/arch/loongarch64/atomic_arch.h b/arch/loongarch64/atomic_arch.h
+new file mode 100644
+index 00000000..2225d027
+--- /dev/null
++++ b/arch/loongarch64/atomic_arch.h
+@@ -0,0 +1,53 @@
++#define a_ll a_ll
++static inline int a_ll(volatile int *p)
++{
++	int v;
++	__asm__ __volatile__ (
++		"ll.w %0, %1"
++		: "=r"(v)
++		: "ZC"(*p));
++	return v;
++}
++
++#define a_sc a_sc
++static inline int a_sc(volatile int *p, int v)
++{
++	int r;
++	__asm__ __volatile__ (
++		"sc.w %0, %1"
++		: "=r"(r), "=ZC"(*p)
++		: "0"(v) : "memory");
++	return r;
++}
++
++#define a_ll_p a_ll_p
++static inline void *a_ll_p(volatile void *p)
++{
++	void *v;
++	__asm__ __volatile__ (
++		"ll.d %0, %1"
++		: "=r"(v)
++		: "ZC"(*(void *volatile *)p));
++	return v;
++}
++
++#define a_sc_p a_sc_p
++static inline int a_sc_p(volatile void *p, void *v)
++{
++	long r;
++	__asm__ __volatile__ (
++		"sc.d %0, %1"
++		: "=r"(r), "=ZC"(*(void *volatile *)p)
++		: "0"(v)
++		: "memory");
++	return r;
++}
++
++#define a_barrier a_barrier
++static inline void a_barrier()
++{
++	__asm__ __volatile__ ("dbar 0" : : : "memory");
++}
++
++#define a_pre_llsc  a_barrier
++#define a_post_llsc a_barrier
+diff --git a/arch/loongarch64/bits/alltypes.h.in b/arch/loongarch64/bits/alltypes.h.in
+new file mode 100644
+index 00000000..06db4096
+--- /dev/null
++++ b/arch/loongarch64/bits/alltypes.h.in
+@@ -0,0 +1,18 @@
++#define _Addr  long
++#define _Int64 long
++#define _Reg   long
++
++#define __BYTE_ORDER  1234
++#define __LONG_MAX    0x7fffffffffffffffL
++
++#ifndef __cplusplus
++TYPEDEF int wchar_t;
++#endif
++
++TYPEDEF float  float_t;
++TYPEDEF double double_t;
++
++TYPEDEF struct { long long __ll; long double __ld; } max_align_t;
++
++TYPEDEF unsigned nlink_t;
++TYPEDEF int blksize_t;
+diff --git a/arch/loongarch64/bits/fenv.h b/arch/loongarch64/bits/fenv.h
+new file mode 100644
+index 00000000..99e916e1
+--- /dev/null
++++ b/arch/loongarch64/bits/fenv.h
+@@ -0,0 +1,20 @@
++#define FE_INEXACT    0x010000
++#define FE_UNDERFLOW  0x020000
++#define FE_OVERFLOW   0x040000
++#define FE_DIVBYZERO  0x080000
++#define FE_INVALID    0x100000
++
++#define FE_ALL_EXCEPT 0x1F0000
++
++#define FE_TONEAREST  0x000
++#define FE_TOWARDZERO 0x100
++#define FE_UPWARD     0x200
++#define FE_DOWNWARD   0x300
++
++typedef unsigned fexcept_t;
++
++typedef struct {
++	unsigned int __cw;
++} fenv_t;
++
++#define FE_DFL_ENV ((const fenv_t *) -1)
+diff --git a/arch/loongarch64/bits/float.h b/arch/loongarch64/bits/float.h
+new file mode 100644
+index 00000000..63e86d44
+--- /dev/null
++++ b/arch/loongarch64/bits/float.h
+@@ -0,0 +1,16 @@
++#define FLT_EVAL_METHOD 0
++
++#define LDBL_TRUE_MIN   6.47517511943802511092443895822764655e-4966L
++#define LDBL_MIN        3.36210314311209350626267781732175260e-4932L
++#define LDBL_MAX        1.18973149535723176508575932662800702e+4932L
++#define LDBL_EPSILON    1.92592994438723585305597794258492732e-34L
++
++#define LDBL_MANT_DIG   113
++#define LDBL_MIN_EXP    (-16381)
++#define LDBL_MAX_EXP    16384
++
++#define LDBL_DIG        33
++#define LDBL_MIN_10_EXP (-4931)
++#define LDBL_MAX_10_EXP 4932
++
++#define DECIMAL_DIG     36
+diff --git a/arch/loongarch64/bits/posix.h b/arch/loongarch64/bits/posix.h
+new file mode 100644
+index 00000000..c37b94c1
+--- /dev/null
++++ b/arch/loongarch64/bits/posix.h
+@@ -0,0 +1,2 @@
++#define _POSIX_V6_LP64_OFF64  1
++#define _POSIX_V7_LP64_OFF64  1
+diff --git a/arch/loongarch64/bits/ptrace.h b/arch/loongarch64/bits/ptrace.h
+new file mode 100644
+index 00000000..dce2fa51
+--- /dev/null
++++ b/arch/loongarch64/bits/ptrace.h
+@@ -0,0 +1,4 @@
++#define PTRACE_GET_THREAD_AREA  25
++#define PTRACE_SET_THREAD_AREA  26
++#define PTRACE_GET_WATCH_REGS   0xd0
++#define PTRACE_SET_WATCH_REGS   0xd1
+diff --git a/arch/loongarch64/bits/reg.h b/arch/loongarch64/bits/reg.h
+new file mode 100644
+index 00000000..2633f39d
+--- /dev/null
++++ b/arch/loongarch64/bits/reg.h
+@@ -0,0 +1,2 @@
++#undef __WORDSIZE
++#define __WORDSIZE 64
+diff --git a/arch/loongarch64/bits/setjmp.h b/arch/loongarch64/bits/setjmp.h
+new file mode 100644
+index 00000000..4bfa374d
+--- /dev/null
++++ b/arch/loongarch64/bits/setjmp.h
+@@ -0,0 +1 @@
++typedef unsigned long  __jmp_buf[23];
+diff --git a/arch/loongarch64/bits/signal.h b/arch/loongarch64/bits/signal.h
+new file mode 100644
+index 00000000..e1d256e7
+--- /dev/null
++++ b/arch/loongarch64/bits/signal.h
+@@ -0,0 +1,92 @@
++#if defined(_POSIX_SOURCE) || defined(_POSIX_C_SOURCE) \
++ || defined(_XOPEN_SOURCE) || defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
++
++#if defined(_XOPEN_SOURCE) || defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
++#define MINSIGSTKSZ 4096
++#define SIGSTKSZ    16384
++#endif
++
++#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
++typedef unsigned long greg_t, gregset_t[32];
++
++struct sigcontext {
++	unsigned long sc_pc;
++	unsigned long sc_regs[32];
++	unsigned int sc_flags;
++	unsigned long sc_extcontext[] __attribute__((__aligned__(16)));
++};
++
++typedef struct {
++	unsigned long __pc;
++	unsigned long __gregs[32];
++	unsigned int __flags;
++	unsigned long __extcontext[] __attribute__((__aligned__(16)));
++} mcontext_t;
++#else
++typedef struct {
++	unsigned long __space[34];
++} mcontext_t;
++#endif
++
++struct sigaltstack {
++	void   *ss_sp;
++	int    ss_flags;
++	size_t ss_size;
++};
++
++typedef struct __ucontext
++{
++	unsigned long      __uc_flags;
++	struct __ucontext  *uc_link;
++	stack_t            uc_stack;
++	sigset_t           uc_sigmask;
++	long               __uc_pad;
++	mcontext_t         uc_mcontext;
++} ucontext_t;
++
++#define SA_NOCLDSTOP     1
++#define SA_NOCLDWAIT     2
++#define SA_SIGINFO       4
++#define SA_ONSTACK       0x08000000
++#define SA_RESTART       0x10000000
++#define SA_NODEFER       0x40000000
++#define SA_RESETHAND     0x80000000
++#define SA_RESTORER      0x0
++
++#endif
++
++#define SIGHUP           1
++#define SIGINT           2
++#define SIGQUIT          3
++#define SIGILL           4
++#define SIGTRAP          5
++#define SIGABRT          6
++#define SIGIOT           SIGABRT
++#define SIGBUS           7
++#define SIGFPE           8
++#define SIGKILL          9
++#define SIGUSR1         10
++#define SIGSEGV         11
++#define SIGUSR2         12
++#define SIGPIPE         13
++#define SIGALRM         14
++#define SIGTERM         15
++#define SIGSTKFLT       16
++#define SIGCHLD         17
++#define SIGCONT         18
++#define SIGSTOP         19
++#define SIGTSTP         20
++#define SIGTTIN         21
++#define SIGTTOU         22
++#define SIGURG          23
++#define SIGXCPU         24
++#define SIGXFSZ         25
++#define SIGVTALRM       26
++#define SIGPROF         27
++#define SIGWINCH        28
++#define SIGIO           29
++#define SIGPOLL         SIGIO
++#define SIGPWR          30
++#define SIGSYS          31
++#define SIGUNUSED       SIGSYS
++#define _NSIG           65
+diff --git a/arch/loongarch64/bits/stat.h b/arch/loongarch64/bits/stat.h
+new file mode 100644
+index 00000000..b7f4221b
+--- /dev/null
++++ b/arch/loongarch64/bits/stat.h
+@@ -0,0 +1,18 @@
++struct stat {
++	dev_t st_dev;
++	ino_t st_ino;
++	mode_t st_mode;
++	nlink_t st_nlink;
++	uid_t st_uid;
++	gid_t st_gid;
++	dev_t st_rdev;
++	unsigned long __pad;
++	off_t st_size;
++	blksize_t st_blksize;
++	int __pad2;
++	blkcnt_t st_blocks;
++	struct timespec st_atim;
++	struct timespec st_mtim;
++	struct timespec st_ctim;
++	unsigned __unused[2];
++};
+diff --git a/arch/loongarch64/bits/stdint.h b/arch/loongarch64/bits/stdint.h
+new file mode 100644
+index 00000000..60c12499
+--- /dev/null
++++ b/arch/loongarch64/bits/stdint.h
+@@ -0,0 +1,20 @@
++typedef int32_t  int_fast16_t;
++typedef int32_t  int_fast32_t;
++typedef uint32_t uint_fast16_t;
++typedef uint32_t uint_fast32_t;
++
++#define INT_FAST16_MIN  INT32_MIN
++#define INT_FAST32_MIN  INT32_MIN
++
++#define INT_FAST16_MAX  INT32_MAX
++#define INT_FAST32_MAX  INT32_MAX
++
++#define UINT_FAST16_MAX UINT32_MAX
++#define UINT_FAST32_MAX UINT32_MAX
++
++#define INTPTR_MIN      INT64_MIN
++#define INTPTR_MAX      INT64_MAX
++#define UINTPTR_MAX     UINT64_MAX
++#define PTRDIFF_MIN     INT64_MIN
++#define PTRDIFF_MAX     INT64_MAX
++#define SIZE_MAX        UINT64_MAX
+diff --git a/arch/loongarch64/bits/syscall.h.in b/arch/loongarch64/bits/syscall.h.in
+new file mode 100644
+index 00000000..0980e533
+--- /dev/null
++++ b/arch/loongarch64/bits/syscall.h.in
+@@ -0,0 +1,303 @@
++#define __NR_io_setup                   0
++#define __NR_io_destroy                 1
++#define __NR_io_submit                  2
++#define __NR_io_cancel                  3
++#define __NR_io_getevents               4
++#define __NR_setxattr                   5
++#define __NR_lsetxattr                  6
++#define __NR_fsetxattr                  7
++#define __NR_getxattr                   8
++#define __NR_lgetxattr                  9
++#define __NR_fgetxattr                  10
++#define __NR_listxattr                  11
++#define __NR_llistxattr                 12
++#define __NR_flistxattr                 13
++#define __NR_removexattr                14
++#define __NR_lremovexattr               15
++#define __NR_fremovexattr               16
++#define __NR_getcwd                     17
++#define __NR_lookup_dcookie             18
++#define __NR_eventfd2                   19
++#define __NR_epoll_create1              20
++#define __NR_epoll_ctl                  21
++#define __NR_epoll_pwait                22
++#define __NR_dup                        23
++#define __NR_dup3                       24
++#define __NR3264_fcntl                  25
++#define __NR_inotify_init1              26
++#define __NR_inotify_add_watch          27
++#define __NR_inotify_rm_watch           28
++#define __NR_ioctl                      29
++#define __NR_ioprio_set                 30
++#define __NR_ioprio_get                 31
++#define __NR_flock                      32
++#define __NR_mknodat                    33
++#define __NR_mkdirat                    34
++#define __NR_unlinkat                   35
++#define __NR_symlinkat                  36
++#define __NR_linkat                     37
++#define __NR_umount2                    39
++#define __NR_mount                      40
++#define __NR_pivot_root                 41
++#define __NR_nfsservctl                 42
++#define __NR3264_statfs                 43
++#define __NR3264_fstatfs                44
++#define __NR3264_truncate               45
++#define __NR3264_ftruncate              46
++#define __NR_fallocate                  47
++#define __NR_faccessat                  48
++#define __NR_chdir                      49
++#define __NR_fchdir                     50
++#define __NR_chroot                     51
++#define __NR_fchmod                     52
++#define __NR_fchmodat                   53
++#define __NR_fchownat                   54
++#define __NR_fchown                     55
++#define __NR_openat                     56
++#define __NR_close                      57
++#define __NR_vhangup                    58
++#define __NR_pipe2                      59
++#define __NR_quotactl                   60
++#define __NR_getdents64                 61
++#define __NR3264_lseek                  62
++#define __NR_read                       63
++#define __NR_write                      64
++#define __NR_readv                      65
++#define __NR_writev                     66
++#define __NR_pread64                    67
++#define __NR_pwrite64                   68
++#define __NR_preadv                     69
++#define __NR_pwritev                    70
++#define __NR3264_sendfile               71
++#define __NR_pselect6                   72
++#define __NR_ppoll                      73
++#define __NR_signalfd4                  74
++#define __NR_vmsplice                   75
++#define __NR_splice                     76
++#define __NR_tee                        77
++#define __NR_readlinkat                 78
++#define __NR_sync                       81
++#define __NR_fsync                      82
++#define __NR_fdatasync                  83
++#define __NR_sync_file_range            84
++#define __NR_timerfd_create             85
++#define __NR_timerfd_settime            86
++#define __NR_timerfd_gettime            87
++#define __NR_utimensat                  88
++#define __NR_acct                       89
++#define __NR_capget                     90
++#define __NR_capset                     91
++#define __NR_personality                92
++#define __NR_exit                       93
++#define __NR_exit_group                 94
++#define __NR_waitid                     95
++#define __NR_set_tid_address            96
++#define __NR_unshare                    97
++#define __NR_futex                      98
++#define __NR_set_robust_list            99
++#define __NR_get_robust_list            100
++#define __NR_nanosleep                  101
++#define __NR_getitimer                  102
++#define __NR_setitimer                  103
++#define __NR_kexec_load                 104
++#define __NR_init_module                105
++#define __NR_delete_module              106
++#define __NR_timer_create               107
++#define __NR_timer_gettime              108
++#define __NR_timer_getoverrun           109
++#define __NR_timer_settime              110
++#define __NR_timer_delete               111
++#define __NR_clock_settime              112
++#define __NR_clock_gettime              113
++#define __NR_clock_getres               114
++#define __NR_clock_nanosleep            115
++#define __NR_syslog                     116
++#define __NR_ptrace                     117
++#define __NR_sched_setparam             118
++#define __NR_sched_setscheduler         119
++#define __NR_sched_getscheduler         120
++#define __NR_sched_getparam             121
++#define __NR_sched_setaffinity          122
++#define __NR_sched_getaffinity          123
++#define __NR_sched_yield                124
++#define __NR_sched_get_priority_max     125
++#define __NR_sched_get_priority_min     126
++#define __NR_sched_rr_get_interval      127
++#define __NR_restart_syscall            128
++#define __NR_kill                       129
++#define __NR_tkill                      130
++#define __NR_tgkill                     131
++#define __NR_sigaltstack                132
++#define __NR_rt_sigsuspend              133
++#define __NR_rt_sigaction               134
++#define __NR_rt_sigprocmask             135
++#define __NR_rt_sigpending              136
++#define __NR_rt_sigtimedwait            137
++#define __NR_rt_sigqueueinfo            138
++#define __NR_rt_sigreturn               139
++#define __NR_setpriority                140
++#define __NR_getpriority                141
++#define __NR_reboot                     142
++#define __NR_setregid                   143
++#define __NR_setgid                     144
++#define __NR_setreuid                   145
++#define __NR_setuid                     146
++#define __NR_setresuid                  147
++#define __NR_getresuid                  148
++#define __NR_setresgid                  149
++#define __NR_getresgid                  150
++#define __NR_setfsuid                   151
++#define __NR_setfsgid                   152
++#define __NR_times                      153
++#define __NR_setpgid                    154
++#define __NR_getpgid                    155
++#define __NR_getsid                     156
++#define __NR_setsid                     157
++#define __NR_getgroups                  158
++#define __NR_setgroups                  159
++#define __NR_uname                      160
++#define __NR_sethostname                161
++#define __NR_setdomainname              162
++#define __NR_getrlimit                  163
++#define __NR_setrlimit                  164
++#define __NR_getrusage                  165
++#define __NR_umask                      166
++#define __NR_prctl                      167
++#define __NR_getcpu                     168
++#define __NR_gettimeofday               169
++#define __NR_settimeofday               170
++#define __NR_adjtimex                   171
++#define __NR_getpid                     172
++#define __NR_getppid                    173
++#define __NR_getuid                     174
++#define __NR_geteuid                    175
++#define __NR_getgid                     176
++#define __NR_getegid                    177
++#define __NR_gettid                     178
++#define __NR_sysinfo                    179
++#define __NR_mq_open                    180
++#define __NR_mq_unlink                  181
++#define __NR_mq_timedsend               182
++#define __NR_mq_timedreceive            183
++#define __NR_mq_notify                  184
++#define __NR_mq_getsetattr              185
++#define __NR_msgget                     186
++#define __NR_msgctl                     187
++#define __NR_msgrcv                     188
++#define __NR_msgsnd                     189
++#define __NR_semget                     190
++#define __NR_semctl                     191
++#define __NR_semtimedop                 192
++#define __NR_semop                      193
++#define __NR_shmget                     194
++#define __NR_shmctl                     195
++#define __NR_shmat                      196
++#define __NR_shmdt                      197
++#define __NR_socket                     198
++#define __NR_socketpair                 199
++#define __NR_bind                       200
++#define __NR_listen                     201
++#define __NR_accept                     202
++#define __NR_connect                    203
++#define __NR_getsockname                204
++#define __NR_getpeername                205
++#define __NR_sendto                     206
++#define __NR_recvfrom                   207
++#define __NR_setsockopt                 208
++#define __NR_getsockopt                 209
++#define __NR_shutdown                   210
++#define __NR_sendmsg                    211
++#define __NR_recvmsg                    212
++#define __NR_readahead                  213
++#define __NR_brk                        214
++#define __NR_munmap                     215
++#define __NR_mremap                     216
++#define __NR_add_key                    217
++#define __NR_request_key                218
++#define __NR_keyctl                     219
++#define __NR_clone                      220
++#define __NR_execve                     221
++#define __NR3264_mmap                   222
++#define __NR3264_fadvise64              223
++#define __NR_swapon                     224
++#define __NR_swapoff                    225
++#define __NR_mprotect                   226
++#define __NR_msync                      227
++#define __NR_mlock                      228
++#define __NR_munlock                    229
++#define __NR_mlockall                   230
++#define __NR_munlockall                 231
++#define __NR_mincore                    232
++#define __NR_madvise                    233
++#define __NR_remap_file_pages           234
++#define __NR_mbind                      235
++#define __NR_get_mempolicy              236
++#define __NR_set_mempolicy              237
++#define __NR_migrate_pages              238
++#define __NR_move_pages                 239
++#define __NR_rt_tgsigqueueinfo          240
++#define __NR_perf_event_open            241
++#define __NR_accept4                    242
++#define __NR_recvmmsg                   243
++#define __NR_arch_specific_syscall      244
++#define __NR_wait4                      260
++#define __NR_prlimit64                  261
++#define __NR_fanotify_init              262
++#define __NR_fanotify_mark              263
++#define __NR_name_to_handle_at          264
++#define __NR_open_by_handle_at          265
++#define __NR_clock_adjtime              266
++#define __NR_syncfs                     267
++#define __NR_setns                      268
++#define __NR_sendmmsg                   269
++#define __NR_process_vm_readv           270
++#define __NR_process_vm_writev          271
++#define __NR_kcmp                       272
++#define __NR_finit_module               273
++#define __NR_sched_setattr              274
++#define __NR_sched_getattr              275
++#define __NR_renameat2                  276
++#define __NR_seccomp                    277
++#define __NR_getrandom                  278
++#define __NR_memfd_create               279
++#define __NR_bpf                        280
++#define __NR_execveat                   281
++#define __NR_userfaultfd                282
++#define __NR_membarrier                 283
++#define __NR_mlock2                     284
++#define __NR_copy_file_range            285
++#define __NR_preadv2                    286
++#define __NR_pwritev2                   287
++#define __NR_pkey_mprotect              288
++#define __NR_pkey_alloc                 289
++#define __NR_pkey_free                  290
++#define __NR_statx                      291
++#define __NR_io_pgetevents              292
++#define __NR_rseq                       293
++#define __NR_kexec_file_load            294
++#define __NR_pidfd_send_signal          424
++#define __NR_io_uring_setup             425
++#define __NR_io_uring_enter             426
++#define __NR_io_uring_register          427
++#define __NR_open_tree                  428
++#define __NR_move_mount                 429
++#define __NR_fsopen                     430
++#define __NR_fsconfig                   431
++#define __NR_fsmount                    432
++#define __NR_fspick                     433
++#define __NR_pidfd_open                 434
++#define __NR_clone3                     435
++#define __NR_close_range                436
++#define __NR_openat2                    437
++#define __NR_pidfd_getfd                438
++#define __NR_faccessat2                 439
++#define __NR_process_madvise            440
++#define __NR_fcntl                      __NR3264_fcntl
++#define __NR_statfs                     __NR3264_statfs
++#define __NR_fstatfs                    __NR3264_fstatfs
++#define __NR_truncate                   __NR3264_truncate
++#define __NR_ftruncate                  __NR3264_ftruncate
++#define __NR_lseek                      __NR3264_lseek
++#define __NR_sendfile                   __NR3264_sendfile
++#define __NR_mmap                       __NR3264_mmap
++#define __NR_fadvise64                  __NR3264_fadvise64
+diff --git a/arch/loongarch64/bits/user.h b/arch/loongarch64/bits/user.h
+new file mode 100644
+index 00000000..5a71d132
+--- /dev/null
++++ b/arch/loongarch64/bits/user.h
+@@ -0,0 +1,5 @@
++#define ELF_NGREG    45
++#define ELF_NFPREG   33
++
++typedef unsigned long elf_greg_t, elf_gregset_t[ELF_NGREG];
++typedef double elf_fpreg_t, elf_fpregset_t[ELF_NFPREG];
+diff --git a/arch/loongarch64/crt_arch.h b/arch/loongarch64/crt_arch.h
+new file mode 100644
+index 00000000..e0760d9e
+--- /dev/null
++++ b/arch/loongarch64/crt_arch.h
+@@ -0,0 +1,13 @@
++__asm__(
++".text \n"
++".global " START "\n"
++".type   " START ", @function\n"
++START ":\n"
++"	move $fp, $zero\n"
++"	move $a0, $sp\n"
++".weak _DYNAMIC\n"
++".hidden _DYNAMIC\n"
++"	la.local $a1, _DYNAMIC\n"
++"	bstrins.d $sp, $zero, 3, 0\n"
++"	b " START "_c\n"
++);
+diff --git a/arch/loongarch64/pthread_arch.h b/arch/loongarch64/pthread_arch.h
+new file mode 100644
+index 00000000..28fbfcd1
+--- /dev/null
++++ b/arch/loongarch64/pthread_arch.h
+@@ -0,0 +1,11 @@
++static inline uintptr_t __get_tp()
++{
++	uintptr_t tp;
++	__asm__ __volatile__("move %0, $tp" : "=r"(tp));
++	return tp;
++}
++
++#define TLS_ABOVE_TP
++#define GAP_ABOVE_TP   0
++#define DTP_OFFSET     0
++#define MC_PC          __pc
+diff --git a/arch/loongarch64/reloc.h b/arch/loongarch64/reloc.h
+new file mode 100644
+index 00000000..6907de8e
+--- /dev/null
++++ b/arch/loongarch64/reloc.h
+@@ -0,0 +1,29 @@
++#if defined __loongarch_double_float
++#define FP_SUFFIX "-lp64d"
++#elif defined __loongarch_single_float
++#define FP_SUFFIX "-lp64f"
++#elif defined __loongarch_soft_float
++#define FP_SUFFIX "-lp64s"
++#endif
++
++#define LDSO_ARCH "loongarch64"  FP_SUFFIX
++
++#define TPOFF_K         0
++
++#define REL_PLT         R_LARCH_JUMP_SLOT
++#define REL_COPY        R_LARCH_COPY
++#define REL_DTPMOD      R_LARCH_TLS_DTPMOD64
++#define REL_DTPOFF      R_LARCH_TLS_DTPREL64
++#define REL_TPOFF       R_LARCH_TLS_TPREL64
++#define REL_RELATIVE    R_LARCH_RELATIVE
++#define REL_SYMBOLIC    R_LARCH_64
++
++#define CRTJMP(pc,sp) __asm__ __volatile__( \
++	"move $sp, %1 ; jr %0" : : "r"(pc), "r"(sp) : "memory" )
++
++#define GETFUNCSYM(fp, sym, got) __asm__ ( \
++	".hidden " #sym "\n" \
++	".align 8 \n" \
++	"	la.local $t1, "#sym" \n" \
++	"	move %0, $t1 \n" \
++	: "=r"(*(fp)) : : "memory" )
+diff --git a/arch/loongarch64/syscall_arch.h b/arch/loongarch64/syscall_arch.h
+new file mode 100644
+index 00000000..4d5e1885
+--- /dev/null
++++ b/arch/loongarch64/syscall_arch.h
+@@ -0,0 +1,137 @@
++#define __SYSCALL_LL_E(x) (x)
++#define __SYSCALL_LL_O(x) (x)
++
++#define SYSCALL_CLOBBERLIST \
++	"$t0", "$t1", "$t2", "$t3", \
++	"$t4", "$t5", "$t6", "$t7", "$t8", "memory"
++
++static inline long __syscall0(long n)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0");
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "=r"(a0)
++		: "r"(a7)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall1(long n, long a)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++		: "r"(a7)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall2(long n, long a, long b)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++	register long a1 __asm__("$a1") = b;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++	        : "r"(a7), "r"(a1)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall3(long n, long a, long b, long c)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++	register long a1 __asm__("$a1") = b;
++	register long a2 __asm__("$a2") = c;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++	        : "r"(a7), "r"(a1), "r"(a2)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall4(long n, long a, long b, long c, long d)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++	register long a1 __asm__("$a1") = b;
++	register long a2 __asm__("$a2") = c;
++	register long a3 __asm__("$a3") = d;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++	        : "r"(a7), "r"(a1), "r"(a2), "r"(a3)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall5(long n, long a, long b, long c, long d, long e)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++	register long a1 __asm__("$a1") = b;
++	register long a2 __asm__("$a2") = c;
++	register long a3 __asm__("$a3") = d;
++	register long a4 __asm__("$a4") = e;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++	        : "r"(a7), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++	register long a1 __asm__("$a1") = b;
++	register long a2 __asm__("$a2") = c;
++	register long a3 __asm__("$a3") = d;
++	register long a4 __asm__("$a4") = e;
++	register long a5 __asm__("$a5") = f;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++	        : "r"(a7), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++static inline long __syscall7(long n, long a, long b, long c, long d, long e, long f, long g)
++{
++	register long a7 __asm__("$a7") = n;
++	register long a0 __asm__("$a0") = a;
++	register long a1 __asm__("$a1") = b;
++	register long a2 __asm__("$a2") = c;
++	register long a3 __asm__("$a3") = d;
++	register long a4 __asm__("$a4") = e;
++	register long a5 __asm__("$a5") = f;
++	register long a6 __asm__("$a6") = g;
++
++	__asm__ __volatile__ (
++		"syscall 0"
++		: "+r"(a0)
++	        : "r"(a7), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5), "r"(a6)
++		: SYSCALL_CLOBBERLIST);
++	return a0;
++}
++
++#define VDSO_USEFUL
++#define VDSO_CGT_SYM "__vdso_clock_gettime"
++#define VDSO_CGT_VER "LINUX_5.10"
++
++#define IPC_64  0
+diff --git a/configure b/configure
+index 0b966ede..93b06287 100755
+--- a/configure
++++ b/configure
+@@ -328,6 +328,7 @@ i?86*) ARCH=i386 ;;
+ x86_64-x32*|x32*|x86_64*x32) ARCH=x32 ;;
+ x86_64-nt64*) ARCH=nt64 ;;
+ x86_64*) ARCH=x86_64 ;;
++loongarch64*) ARCH=loongarch64 ;;
+ m68k*) ARCH=m68k ;;
+ mips64*|mipsisa64*) ARCH=mips64 ;;
+ mips*) ARCH=mips ;;
+@@ -671,6 +672,20 @@ if test "$ARCH" = "aarch64" ; then
+ trycppif __AARCH64EB__ "$t" && SUBARCH=${SUBARCH}_be
+ fi
+ 
++if test "$ARCH" = "loongarch64" ; then
++trycppif __loongarch_double_float "$t" && SUBARCH=${SUBARCH}-lp64d
++trycppif __loongarch_single_float "$t" && SUBARCH=${SUBARCH}-lp64f
++trycppif __loongarch_soft_float "$t" && SUBARCH=${SUBARCH}-lp64s
++printf "checking whether compiler support FCSRs... "
++echo "__asm__(\"movfcsr2gr \$t0,\$fcsr0\");" > "$tmpc"
++if $CC -c -o /dev/null "$tmpc" >/dev/null 2>&1 ; then
++printf "yes\n"
++else
++printf "no\n"
++CFLAGS_AUTO="$CFLAGS_AUTO -DBROKEN_LOONGARCH_FCSR_ASM"
++fi
++fi
++
+ if test "$ARCH" = "m68k" ; then
+ if trycppif "__HAVE_68881__" ; then : ;
+ elif trycppif "__mcffpu__" ; then SUBARCH="-fp64"
+diff --git a/include/elf.h b/include/elf.h
+index 23f2c4bc..7114f262 100644
+--- a/include/elf.h
++++ b/include/elf.h
+@@ -315,7 +315,8 @@ typedef struct {
+ #define EM_RISCV	243
+ #define EM_BPF		247
+ #define EM_CSKY		252
+-#define EM_NUM		253
++#define EM_LOONGARCH	258
++#define EM_NUM		259
+ 
+ #define EM_ALPHA	0x9026
+ 
+@@ -699,6 +700,11 @@ typedef struct {
+ #define NT_MIPS_FP_MODE	0x801
+ #define NT_MIPS_MSA	0x802
+ #define NT_VERSION	1
++#define NT_LOONGARCH_CPUCFG	0xa00
++#define NT_LOONGARCH_CSR	0xa01
++#define NT_LOONGARCH_LSX	0xa02
++#define NT_LOONGARCH_LASX	0xa03
++#define NT_LOONGARCH_LBT	0xa04
+ 
+ 
+ 
+@@ -3293,6 +3299,102 @@ enum
+ #define R_RISCV_SET32           56
+ #define R_RISCV_32_PCREL        57
+ 
++#define EF_LARCH_ABI_MODIFIER_MASK    0x07
++#define EF_LARCH_ABI_SOFT_FLOAT       0x01
++#define EF_LARCH_ABI_SINGLE_FLOAT     0x02
++#define EF_LARCH_ABI_DOUBLE_FLOAT     0x03
++#define EF_LARCH_OBJABI_V1            0x40
++
++#define R_LARCH_NONE                        0
++#define R_LARCH_32                          1
++#define R_LARCH_64                          2
++#define R_LARCH_RELATIVE                    3
++#define R_LARCH_COPY                        4
++#define R_LARCH_JUMP_SLOT                   5
++#define R_LARCH_TLS_DTPMOD32                6
++#define R_LARCH_TLS_DTPMOD64                7
++#define R_LARCH_TLS_DTPREL32                8
++#define R_LARCH_TLS_DTPREL64                9
++#define R_LARCH_TLS_TPREL32                 10
++#define R_LARCH_TLS_TPREL64                 11
++#define R_LARCH_IRELATIVE                   12
++#define R_LARCH_MARK_LA                     20
++#define R_LARCH_MARK_PCREL                  21
++#define R_LARCH_SOP_PUSH_PCREL              22
++#define R_LARCH_SOP_PUSH_ABSOLUTE           23
++#define R_LARCH_SOP_PUSH_DUP                24
++#define R_LARCH_SOP_PUSH_GPREL              25
++#define R_LARCH_SOP_PUSH_TLS_TPREL          26
++#define R_LARCH_SOP_PUSH_TLS_GOT            27
++#define R_LARCH_SOP_PUSH_TLS_GD             28
++#define R_LARCH_SOP_PUSH_PLT_PCREL          29
++#define R_LARCH_SOP_ASSERT                  30
++#define R_LARCH_SOP_NOT                     31
++#define R_LARCH_SOP_SUB                     32
++#define R_LARCH_SOP_SL                      33
++#define R_LARCH_SOP_SR                      34
++#define R_LARCH_SOP_ADD                     35
++#define R_LARCH_SOP_AND                     36
++#define R_LARCH_SOP_IF_ELSE                 37
++#define R_LARCH_SOP_POP_32_S_10_5           38
++#define R_LARCH_SOP_POP_32_U_10_12          39
++#define R_LARCH_SOP_POP_32_S_10_12          40
++#define R_LARCH_SOP_POP_32_S_10_16          41
++#define R_LARCH_SOP_POP_32_S_10_16_S2       42
++#define R_LARCH_SOP_POP_32_S_5_20           43
++#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2   44
++#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2  45
++#define R_LARCH_SOP_POP_32_U                46
++#define R_LARCH_ADD8                        47
++#define R_LARCH_ADD16                       48
++#define R_LARCH_ADD24                       49
++#define R_LARCH_ADD32                       50
++#define R_LARCH_ADD64                       51
++#define R_LARCH_SUB8                        52
++#define R_LARCH_SUB16                       53
++#define R_LARCH_SUB24                       54
++#define R_LARCH_SUB32                       55
++#define R_LARCH_SUB64                       56
++#define R_LARCH_GNU_VTINHERIT               57
++#define R_LARCH_GNU_VTENTRY                 58
++#define R_LARCH_B16                         64
++#define R_LARCH_B21                         65
++#define R_LARCH_B26                         66
++#define R_LARCH_ABS_HI20                    67
++#define R_LARCH_ABS_LO12                    68
++#define R_LARCH_ABS64_LO20                  69
++#define R_LARCH_ABS64_HI12                  70
++#define R_LARCH_PCALA_HI20                  71
++#define R_LARCH_PCALA_LO12                  72
++#define R_LARCH_PCALA64_LO20                73
++#define R_LARCH_PCALA64_HI12                74
++#define R_LARCH_GOT_PC_HI20                 75
++#define R_LARCH_GOT_PC_LO12                 76
++#define R_LARCH_GOT64_PC_LO20               77
++#define R_LARCH_GOT64_PC_HI12               78
++#define R_LARCH_GOT_HI20                    79
++#define R_LARCH_GOT_LO12                    80
++#define R_LARCH_GOT64_LO20                  81
++#define R_LARCH_GOT64_HI12                  82
++#define R_LARCH_TLS_LE_HI20                 83
++#define R_LARCH_TLS_LE_LO12                 84
++#define R_LARCH_TLS_LE64_LO20               85
++#define R_LARCH_TLS_LE64_HI12               86
++#define R_LARCH_TLS_IE_PC_HI20              87
++#define R_LARCH_TLS_IE_PC_LO12              88
++#define R_LARCH_TLS_IE64_PC_LO20            89
++#define R_LARCH_TLS_IE64_PC_HI12            90
++#define R_LARCH_TLS_IE_HI20                 91
++#define R_LARCH_TLS_IE_LO12                 92
++#define R_LARCH_TLS_IE64_LO20               93
++#define R_LARCH_TLS_IE64_HI12               94
++#define R_LARCH_TLS_LD_PC_HI20              95
++#define R_LARCH_TLS_LD_HI20                 96
++#define R_LARCH_TLS_GD_PC_HI20              97
++#define R_LARCH_TLS_GD_HI20                 98
++#define R_LARCH_32_PCREL                    99
++#define R_LARCH_RELAX                       100
++
+ #ifdef __cplusplus
+ }
+ #endif
+diff --git a/src/fenv/loongarch64/fenv.S b/src/fenv/loongarch64/fenv.S
+new file mode 100644
+index 00000000..54064e01
+--- /dev/null
++++ b/src/fenv/loongarch64/fenv.S
+@@ -0,0 +1,78 @@
++#ifndef __loongarch_soft_float
++
++#ifdef BROKEN_LOONGARCH_FCSR_ASM
++#define FCSR $r0
++#else
++#define FCSR $fcsr0
++#endif
++
++.global	feclearexcept
++.type   feclearexcept,@function
++feclearexcept:
++	li.w    $t0, 0x1f0000
++	and     $a0, $a0, $t0
++	movfcsr2gr $t1, FCSR
++	andn    $t1, $t1, $a0
++	movgr2fcsr FCSR, $t1
++	li.w    $a0, 0
++	jr      $ra
++
++.global	feraiseexcept
++.type   feraiseexcept,@function
++feraiseexcept:
++	li.w    $t0, 0x1f0000
++	and     $a0, $a0, $t0
++	movfcsr2gr $t1, FCSR
++	or      $t1, $t1, $a0
++	movgr2fcsr FCSR, $t1
++	li.w    $a0, 0
++	jr      $ra
++
++.global	fetestexcept
++.type   fetestexcept,@function
++fetestexcept:
++	li.w    $t0, 0x1f0000
++	and     $a0, $a0, $t0
++	movfcsr2gr $t1, FCSR
++	and     $a0, $t1, $a0
++	jr      $ra
++
++.global	fegetround
++.type   fegetround,@function
++fegetround:
++	movfcsr2gr $t0, FCSR
++	andi    $a0, $t0, 0x300
++	jr      $ra
++
++.global	__fesetround
++.hidden __fesetround
++.type   __fesetround,@function
++__fesetround:
++	li.w    $t0, 0x300
++	and     $a0, $a0, $t0
++	movfcsr2gr $t1, FCSR
++	andn    $t1, $t1, $t0
++	or      $t1, $t1, $a0
++	movgr2fcsr FCSR, $t1
++	li.w    $a0, 0
++	jr      $ra
++
++.global	fegetenv
++.type   fegetenv,@function
++fegetenv:
++	movfcsr2gr $t0, FCSR
++	st.w    $t0, $a0, 0
++	li.w    $a0, 0
++	jr      $ra
++
++.global	fesetenv
++.type   fesetenv,@function
++fesetenv:
++	addi.d  $t0, $a0, 1
++	beq     $t0, $r0, 1f
++	ld.w    $t0, $a0, 0
++1:	movgr2fcsr FCSR, $t0
++	li.w    $a0, 0
++	jr      $ra
++
++#endif
+diff --git a/src/ldso/loongarch64/dlsym.s b/src/ldso/loongarch64/dlsym.s
+new file mode 100644
+index 00000000..26fabcdb
+--- /dev/null
++++ b/src/ldso/loongarch64/dlsym.s
+@@ -0,0 +1,7 @@
++.global dlsym
++.hidden __dlsym
++.type   dlsym,@function
++dlsym:
++	move      $a2, $ra
++	la.global $t0, __dlsym
++	jr        $t0
+diff --git a/src/setjmp/loongarch64/longjmp.S b/src/setjmp/loongarch64/longjmp.S
+new file mode 100644
+index 00000000..896d2e26
+--- /dev/null
++++ b/src/setjmp/loongarch64/longjmp.S
+@@ -0,0 +1,32 @@
++.global _longjmp
++.global longjmp
++.type   _longjmp,@function
++.type   longjmp,@function
++_longjmp:
++longjmp:
++	ld.d    $ra, $a0, 0
++	ld.d    $sp, $a0, 8
++	ld.d    $r21,$a0, 16
++	ld.d    $fp, $a0, 24
++	ld.d    $s0, $a0, 32
++	ld.d    $s1, $a0, 40
++	ld.d    $s2, $a0, 48
++	ld.d    $s3, $a0, 56
++	ld.d    $s4, $a0, 64
++	ld.d    $s5, $a0, 72
++	ld.d    $s6, $a0, 80
++	ld.d    $s7, $a0, 88
++	ld.d    $s8, $a0, 96
++#ifndef __loongarch_soft_float
++	fld.d   $fs0, $a0, 104
++	fld.d   $fs1, $a0, 112
++	fld.d   $fs2, $a0, 120
++	fld.d   $fs3, $a0, 128
++	fld.d   $fs4, $a0, 136
++	fld.d   $fs5, $a0, 144
++	fld.d   $fs6, $a0, 152
++	fld.d   $fs7, $a0, 160
++#endif
++	sltui   $a0, $a1, 1
++	add.d   $a0, $a0, $a1
++	jr      $ra
+diff --git a/src/setjmp/loongarch64/setjmp.S b/src/setjmp/loongarch64/setjmp.S
+new file mode 100644
+index 00000000..d158a3d2
+--- /dev/null
++++ b/src/setjmp/loongarch64/setjmp.S
+@@ -0,0 +1,34 @@
++.global __setjmp
++.global _setjmp
++.global setjmp
++.type __setjmp,@function
++.type _setjmp,@function
++.type setjmp,@function
++__setjmp:
++_setjmp:
++setjmp:
++	st.d    $ra, $a0, 0
++	st.d    $sp, $a0, 8
++	st.d    $r21,$a0, 16
++	st.d    $fp, $a0, 24
++	st.d    $s0, $a0, 32
++	st.d    $s1, $a0, 40
++	st.d    $s2, $a0, 48
++	st.d    $s3, $a0, 56
++	st.d    $s4, $a0, 64
++	st.d    $s5, $a0, 72
++	st.d    $s6, $a0, 80
++	st.d    $s7, $a0, 88
++	st.d    $s8, $a0, 96
++#ifndef __loongarch_soft_float
++	fst.d   $fs0, $a0, 104
++	fst.d   $fs1, $a0, 112
++	fst.d   $fs2, $a0, 120
++	fst.d   $fs3, $a0, 128
++	fst.d   $fs4, $a0, 136
++	fst.d   $fs5, $a0, 144
++	fst.d   $fs6, $a0, 152
++	fst.d   $fs7, $a0, 160
++#endif
++	move    $a0, $zero
++	jr      $ra
+diff --git a/src/signal/loongarch64/restore.s b/src/signal/loongarch64/restore.s
+new file mode 100644
+index 00000000..f8e6daeb
+--- /dev/null
++++ b/src/signal/loongarch64/restore.s
+@@ -0,0 +1,10 @@
++.global	__restore_rt
++.global	__restore
++.hidden __restore_rt
++.hidden __restore
++.type   __restore_rt,@function
++.type   __restore,@function
++__restore_rt:
++__restore:
++	li.w    $a7, 139
++	syscall	0
+diff --git a/src/signal/loongarch64/sigsetjmp.s b/src/signal/loongarch64/sigsetjmp.s
+new file mode 100644
+index 00000000..992ab1a4
+--- /dev/null
++++ b/src/signal/loongarch64/sigsetjmp.s
+@@ -0,0 +1,25 @@
++.global sigsetjmp
++.global __sigsetjmp
++.type sigsetjmp,@function
++.type __sigsetjmp,@function
++sigsetjmp:
++__sigsetjmp:
++	beq     $a1, $zero, 1f
++	st.d    $ra, $a0, 168
++	st.d    $s0, $a0, 176
++	move    $s0, $a0
++
++	la.global  $t0, setjmp
++	jirl       $ra, $t0, 0
++
++	move    $a1, $a0        # Return from 'setjmp' or 'longjmp'
++	move    $a0, $s0
++	ld.d    $ra, $a0, 168
++	ld.d    $s0, $a0, 176
++
++.hidden __sigsetjmp_tail
++	la.global  $t0, __sigsetjmp_tail
++	jr         $t0
++1:
++	la.global  $t0, setjmp
++	jr         $t0
+diff --git a/src/thread/loongarch64/__set_thread_area.s b/src/thread/loongarch64/__set_thread_area.s
+new file mode 100644
+index 00000000..ffdd52f1
+--- /dev/null
++++ b/src/thread/loongarch64/__set_thread_area.s
+@@ -0,0 +1,7 @@
++.global	__set_thread_area
++.hidden __set_thread_area
++.type   __set_thread_area,@function
++__set_thread_area:
++	move $tp, $a0
++	move $a0, $zero
++	jr   $ra
+diff --git a/src/thread/loongarch64/__unmapself.s b/src/thread/loongarch64/__unmapself.s
+new file mode 100644
+index 00000000..1de334af
+--- /dev/null
++++ b/src/thread/loongarch64/__unmapself.s
+@@ -0,0 +1,7 @@
++.global	__unmapself
++.type   __unmapself, @function
++__unmapself:
++	li.d    $a7, 215   # call munmap
++	syscall	0
++	li.d    $a7, 93    # call exit
++	syscall	0
+diff --git a/src/thread/loongarch64/clone.s b/src/thread/loongarch64/clone.s
+new file mode 100644
+index 00000000..db9015e6
+--- /dev/null
++++ b/src/thread/loongarch64/clone.s
+@@ -0,0 +1,28 @@
++#__clone(func, stack, flags, arg, ptid, tls, ctid)
++#         a0,    a1,   a2,    a3,  a4,  a5,   a6
++# sys_clone(flags, stack, ptid, ctid, tls)
++#            a0,    a1,   a2,    a3,  a4
++
++.global	__clone
++.hidden __clone
++.type __clone,@function
++__clone:
++	# Save function pointer and argument pointer on new thread stack
++	addi.d  $a1, $a1, -16
++	st.d    $a0, $a1, 0     # save function pointer
++	st.d    $a3, $a1, 8     # save argument pointer
++	or      $a0, $a2, $zero
++	or      $a2, $a4, $zero
++	or      $a3, $a6, $zero
++	or      $a4, $a5, $zero
++	ori     $a7, $zero, 220
++	syscall 0               # call clone
++
++	beqz    $a0, 1f         # whether child process
++	jirl    $zero, $ra, 0   # parent process return
++1:
++	ld.d    $t8, $sp, 0     # function pointer
++	ld.d    $a0, $sp, 8     # argument pointer
++	jirl    $ra, $t8, 0     # call the user's function
++	ori     $a7, $zero, 93
++	syscall	0               # child process exit
+diff --git a/src/thread/loongarch64/syscall_cp.s b/src/thread/loongarch64/syscall_cp.s
+new file mode 100644
+index 00000000..0fbc7a47
+--- /dev/null
++++ b/src/thread/loongarch64/syscall_cp.s
+@@ -0,0 +1,29 @@
++.global	__cp_begin
++.hidden	__cp_begin
++.global	__cp_end
++.hidden	__cp_end
++.global	__cp_cancel
++.hidden	__cp_cancel
++.hidden	__cancel
++.global	__syscall_cp_asm
++.hidden	__syscall_cp_asm
++.type   __syscall_cp_asm,@function
++
++__syscall_cp_asm:
++__cp_begin:
++	ld.w $a0, $a0, 0
++	bnez $a0, __cp_cancel
++	move $t8, $a1    # reserve system call number
++	move $a0, $a2
++	move $a1, $a3
++	move $a2, $a4
++	move $a3, $a5
++	move $a4, $a6
++	move $a5, $a7
++	move $a7, $t8
++	syscall	0
++__cp_end:
++	jr $ra
++__cp_cancel:
++	la.local $t8, __cancel
++	jr $t8
+-- 
+2.37.1
+
diff --git a/tools/Makefile b/tools/Makefile
index 7b3a8eb1425cbc..dbb2f4407f9623 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -61,6 +61,7 @@ tools-y += pkgconf
 tools-y += quilt
 tools-y += squashfskit4
 tools-y += sstrip
+tools-y += util-linux
 tools-y += zip
 tools-y += zlib
 tools-y += zstd
@@ -118,6 +119,7 @@ $(curdir)/quilt/compile := $(curdir)/autoconf/compile $(curdir)/findutils/compil
 $(curdir)/sdcc/compile := $(curdir)/bison/compile
 $(curdir)/squashfs/compile := $(curdir)/lzma-old/compile
 $(curdir)/squashfskit4/compile := $(curdir)/xz/compile $(curdir)/zlib/compile
+$(curdir)/util-linux/compile := $(curdir)/meson/compile $(curdir)/bison/compile
 $(curdir)/zstd/compile := $(curdir)/meson/compile
 
 ifneq ($(HOST_OS),Linux)
diff --git a/tools/dwarves/Makefile b/tools/dwarves/Makefile
index 00833b95767c50..e037ce2e1e2190 100644
--- a/tools/dwarves/Makefile
+++ b/tools/dwarves/Makefile
@@ -3,12 +3,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=dwarves
-PKG_VERSION:=1.24
+PKG_VERSION:=1.25
 PKG_RELEASE:=$(AUTORELEASE)
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://fedorapeople.org/~acme/dwarves/
-PKG_HASH:=576bc112b95937dfbcd347c423696ee9e1992a338fdca1acacca736fd95f69c2
+PKG_HASH:=e7d45955f6f4eca25a4c8c3bd6611059b35dc217e45976681d7db170fccdec4a
 
 PKG_LICENSE:=GPL-2.0-only
 PKG_LICENSE_FILES:=COPYING
diff --git a/tools/include/elf.h b/tools/include/elf.h
index 036a176345eb6e..4bc0e4299c3a4c 100644
--- a/tools/include/elf.h
+++ b/tools/include/elf.h
@@ -1,5 +1,5 @@
 /* This file defines standard ELF types, structures, and macros.
-   Copyright (C) 1995-2012 Free Software Foundation, Inc.
+   Copyright (C) 1995-2023 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -14,7 +14,7 @@
 
    You should have received a copy of the GNU Lesser General Public
    License along with the GNU C Library; if not, see
-   <http://www.gnu.org/licenses/>.  */
+   <https://www.gnu.org/licenses/>.  */
 
 #ifndef _ELF_H
 #define	_ELF_H 1
@@ -168,86 +168,203 @@ typedef struct
 
 /* Legal values for e_machine (architecture).  */
 
-#define EM_NONE		 0		/* No machine */
-#define EM_M32		 1		/* AT&T WE 32100 */
-#define EM_SPARC	 2		/* SUN SPARC */
-#define EM_386		 3		/* Intel 80386 */
-#define EM_68K		 4		/* Motorola m68k family */
-#define EM_88K		 5		/* Motorola m88k family */
-#define EM_860		 7		/* Intel 80860 */
-#define EM_MIPS		 8		/* MIPS R3000 big-endian */
-#define EM_S370		 9		/* IBM System/370 */
-#define EM_MIPS_RS3_LE	10		/* MIPS R3000 little-endian */
-
-#define EM_PARISC	15		/* HPPA */
-#define EM_VPP500	17		/* Fujitsu VPP500 */
-#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
-#define EM_960		19		/* Intel 80960 */
-#define EM_PPC		20		/* PowerPC */
-#define EM_PPC64	21		/* PowerPC 64-bit */
-#define EM_S390		22		/* IBM S390 */
-
-#define EM_V800		36		/* NEC V800 series */
-#define EM_FR20		37		/* Fujitsu FR20 */
-#define EM_RH32		38		/* TRW RH-32 */
-#define EM_RCE		39		/* Motorola RCE */
-#define EM_ARM		40		/* ARM */
-#define EM_FAKE_ALPHA	41		/* Digital Alpha */
-#define EM_SH		42		/* Hitachi SH */
-#define EM_SPARCV9	43		/* SPARC v9 64-bit */
-#define EM_TRICORE	44		/* Siemens Tricore */
-#define EM_ARC		45		/* Argonaut RISC Core */
-#define EM_H8_300	46		/* Hitachi H8/300 */
-#define EM_H8_300H	47		/* Hitachi H8/300H */
-#define EM_H8S		48		/* Hitachi H8S */
-#define EM_H8_500	49		/* Hitachi H8/500 */
-#define EM_IA_64	50		/* Intel Merced */
-#define EM_MIPS_X	51		/* Stanford MIPS-X */
-#define EM_COLDFIRE	52		/* Motorola Coldfire */
-#define EM_68HC12	53		/* Motorola M68HC12 */
-#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
-#define EM_PCP		55		/* Siemens PCP */
-#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
-#define EM_NDR1		57		/* Denso NDR1 microprocessor */
-#define EM_STARCORE	58		/* Motorola Start*Core processor */
-#define EM_ME16		59		/* Toyota ME16 processor */
-#define EM_ST100	60		/* STMicroelectronic ST100 processor */
-#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
-#define EM_X86_64	62		/* AMD x86-64 architecture */
-#define EM_PDSP		63		/* Sony DSP Processor */
-
-#define EM_FX66		66		/* Siemens FX66 microcontroller */
-#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
-#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
-#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
-#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
-#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
-#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
-#define EM_SVX		73		/* Silicon Graphics SVx */
-#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
-#define EM_VAX		75		/* Digital VAX */
-#define EM_CRIS		76		/* Axis Communications 32-bit embedded processor */
-#define EM_JAVELIN	77		/* Infineon Technologies 32-bit embedded processor */
-#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
-#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
-#define EM_MMIX		80		/* Donald Knuth's educational 64-bit processor */
-#define EM_HUANY	81		/* Harvard University machine-independent object files */
-#define EM_PRISM	82		/* SiTera Prism */
-#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
-#define EM_FR30		84		/* Fujitsu FR30 */
-#define EM_D10V		85		/* Mitsubishi D10V */
-#define EM_D30V		86		/* Mitsubishi D30V */
-#define EM_V850		87		/* NEC v850 */
-#define EM_M32R		88		/* Mitsubishi M32R */
-#define EM_MN10300	89		/* Matsushita MN10300 */
-#define EM_MN10200	90		/* Matsushita MN10200 */
-#define EM_PJ		91		/* picoJava */
-#define EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
-#define EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
-#define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
-#define EM_TILEPRO	188		/* Tilera TILEPro */
-#define EM_TILEGX	191		/* Tilera TILE-Gx */
-#define EM_NUM		192
+#define EM_NONE		 0	/* No machine */
+#define EM_M32		 1	/* AT&T WE 32100 */
+#define EM_SPARC	 2	/* SUN SPARC */
+#define EM_386		 3	/* Intel 80386 */
+#define EM_68K		 4	/* Motorola m68k family */
+#define EM_88K		 5	/* Motorola m88k family */
+#define EM_IAMCU	 6	/* Intel MCU */
+#define EM_860		 7	/* Intel 80860 */
+#define EM_MIPS		 8	/* MIPS R3000 big-endian */
+#define EM_S370		 9	/* IBM System/370 */
+#define EM_MIPS_RS3_LE	10	/* MIPS R3000 little-endian */
+				/* reserved 11-14 */
+#define EM_PARISC	15	/* HPPA */
+				/* reserved 16 */
+#define EM_VPP500	17	/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18	/* Sun's "v8plus" */
+#define EM_960		19	/* Intel 80960 */
+#define EM_PPC		20	/* PowerPC */
+#define EM_PPC64	21	/* PowerPC 64-bit */
+#define EM_S390		22	/* IBM S390 */
+#define EM_SPU		23	/* IBM SPU/SPC */
+				/* reserved 24-35 */
+#define EM_V800		36	/* NEC V800 series */
+#define EM_FR20		37	/* Fujitsu FR20 */
+#define EM_RH32		38	/* TRW RH-32 */
+#define EM_RCE		39	/* Motorola RCE */
+#define EM_ARM		40	/* ARM */
+#define EM_FAKE_ALPHA	41	/* Digital Alpha */
+#define EM_SH		42	/* Hitachi SH */
+#define EM_SPARCV9	43	/* SPARC v9 64-bit */
+#define EM_TRICORE	44	/* Siemens Tricore */
+#define EM_ARC		45	/* Argonaut RISC Core */
+#define EM_H8_300	46	/* Hitachi H8/300 */
+#define EM_H8_300H	47	/* Hitachi H8/300H */
+#define EM_H8S		48	/* Hitachi H8S */
+#define EM_H8_500	49	/* Hitachi H8/500 */
+#define EM_IA_64	50	/* Intel Merced */
+#define EM_MIPS_X	51	/* Stanford MIPS-X */
+#define EM_COLDFIRE	52	/* Motorola Coldfire */
+#define EM_68HC12	53	/* Motorola M68HC12 */
+#define EM_MMA		54	/* Fujitsu MMA Multimedia Accelerator */
+#define EM_PCP		55	/* Siemens PCP */
+#define EM_NCPU		56	/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57	/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58	/* Motorola Start*Core processor */
+#define EM_ME16		59	/* Toyota ME16 processor */
+#define EM_ST100	60	/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61	/* Advanced Logic Corp. Tinyj emb.fam */
+#define EM_X86_64	62	/* AMD x86-64 architecture */
+#define EM_PDSP		63	/* Sony DSP Processor */
+#define EM_PDP10	64	/* Digital PDP-10 */
+#define EM_PDP11	65	/* Digital PDP-11 */
+#define EM_FX66		66	/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67	/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68	/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69	/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70	/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71	/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72	/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73	/* Silicon Graphics SVx */
+#define EM_ST19		74	/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75	/* Digital VAX */
+#define EM_CRIS		76	/* Axis Communications 32-bit emb.proc */
+#define EM_JAVELIN	77	/* Infineon Technologies 32-bit emb.proc */
+#define EM_FIREPATH	78	/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79	/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80	/* Donald Knuth's educational 64-bit proc */
+#define EM_HUANY	81	/* Harvard University machine-independent object files */
+#define EM_PRISM	82	/* SiTera Prism */
+#define EM_AVR		83	/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84	/* Fujitsu FR30 */
+#define EM_D10V		85	/* Mitsubishi D10V */
+#define EM_D30V		86	/* Mitsubishi D30V */
+#define EM_V850		87	/* NEC v850 */
+#define EM_M32R		88	/* Mitsubishi M32R */
+#define EM_MN10300	89	/* Matsushita MN10300 */
+#define EM_MN10200	90	/* Matsushita MN10200 */
+#define EM_PJ		91	/* picoJava */
+#define EM_OPENRISC	92	/* OpenRISC 32-bit embedded processor */
+#define EM_ARC_COMPACT	93	/* ARC International ARCompact */
+#define EM_XTENSA	94	/* Tensilica Xtensa Architecture */
+#define EM_VIDEOCORE	95	/* Alphamosaic VideoCore */
+#define EM_TMM_GPP	96	/* Thompson Multimedia General Purpose Proc */
+#define EM_NS32K	97	/* National Semi. 32000 */
+#define EM_TPC		98	/* Tenor Network TPC */
+#define EM_SNP1K	99	/* Trebia SNP 1000 */
+#define EM_ST200	100	/* STMicroelectronics ST200 */
+#define EM_IP2K		101	/* Ubicom IP2xxx */
+#define EM_MAX		102	/* MAX processor */
+#define EM_CR		103	/* National Semi. CompactRISC */
+#define EM_F2MC16	104	/* Fujitsu F2MC16 */
+#define EM_MSP430	105	/* Texas Instruments msp430 */
+#define EM_BLACKFIN	106	/* Analog Devices Blackfin DSP */
+#define EM_SE_C33	107	/* Seiko Epson S1C33 family */
+#define EM_SEP		108	/* Sharp embedded microprocessor */
+#define EM_ARCA		109	/* Arca RISC */
+#define EM_UNICORE	110	/* PKU-Unity & MPRC Peking Uni. mc series */
+#define EM_EXCESS	111	/* eXcess configurable cpu */
+#define EM_DXP		112	/* Icera Semi. Deep Execution Processor */
+#define EM_ALTERA_NIOS2 113	/* Altera Nios II */
+#define EM_CRX		114	/* National Semi. CompactRISC CRX */
+#define EM_XGATE	115	/* Motorola XGATE */
+#define EM_C166		116	/* Infineon C16x/XC16x */
+#define EM_M16C		117	/* Renesas M16C */
+#define EM_DSPIC30F	118	/* Microchip Technology dsPIC30F */
+#define EM_CE		119	/* Freescale Communication Engine RISC */
+#define EM_M32C		120	/* Renesas M32C */
+				/* reserved 121-130 */
+#define EM_TSK3000	131	/* Altium TSK3000 */
+#define EM_RS08		132	/* Freescale RS08 */
+#define EM_SHARC	133	/* Analog Devices SHARC family */
+#define EM_ECOG2	134	/* Cyan Technology eCOG2 */
+#define EM_SCORE7	135	/* Sunplus S+core7 RISC */
+#define EM_DSP24	136	/* New Japan Radio (NJR) 24-bit DSP */
+#define EM_VIDEOCORE3	137	/* Broadcom VideoCore III */
+#define EM_LATTICEMICO32 138	/* RISC for Lattice FPGA */
+#define EM_SE_C17	139	/* Seiko Epson C17 */
+#define EM_TI_C6000	140	/* Texas Instruments TMS320C6000 DSP */
+#define EM_TI_C2000	141	/* Texas Instruments TMS320C2000 DSP */
+#define EM_TI_C5500	142	/* Texas Instruments TMS320C55x DSP */
+#define EM_TI_ARP32	143	/* Texas Instruments App. Specific RISC */
+#define EM_TI_PRU	144	/* Texas Instruments Prog. Realtime Unit */
+				/* reserved 145-159 */
+#define EM_MMDSP_PLUS	160	/* STMicroelectronics 64bit VLIW DSP */
+#define EM_CYPRESS_M8C	161	/* Cypress M8C */
+#define EM_R32C		162	/* Renesas R32C */
+#define EM_TRIMEDIA	163	/* NXP Semi. TriMedia */
+#define EM_QDSP6	164	/* QUALCOMM DSP6 */
+#define EM_8051		165	/* Intel 8051 and variants */
+#define EM_STXP7X	166	/* STMicroelectronics STxP7x */
+#define EM_NDS32	167	/* Andes Tech. compact code emb. RISC */
+#define EM_ECOG1X	168	/* Cyan Technology eCOG1X */
+#define EM_MAXQ30	169	/* Dallas Semi. MAXQ30 mc */
+#define EM_XIMO16	170	/* New Japan Radio (NJR) 16-bit DSP */
+#define EM_MANIK	171	/* M2000 Reconfigurable RISC */
+#define EM_CRAYNV2	172	/* Cray NV2 vector architecture */
+#define EM_RX		173	/* Renesas RX */
+#define EM_METAG	174	/* Imagination Tech. META */
+#define EM_MCST_ELBRUS	175	/* MCST Elbrus */
+#define EM_ECOG16	176	/* Cyan Technology eCOG16 */
+#define EM_CR16		177	/* National Semi. CompactRISC CR16 */
+#define EM_ETPU		178	/* Freescale Extended Time Processing Unit */
+#define EM_SLE9X	179	/* Infineon Tech. SLE9X */
+#define EM_L10M		180	/* Intel L10M */
+#define EM_K10M		181	/* Intel K10M */
+				/* reserved 182 */
+#define EM_AARCH64	183	/* ARM AARCH64 */
+				/* reserved 184 */
+#define EM_AVR32	185	/* Amtel 32-bit microprocessor */
+#define EM_STM8		186	/* STMicroelectronics STM8 */
+#define EM_TILE64	187	/* Tilera TILE64 */
+#define EM_TILEPRO	188	/* Tilera TILEPro */
+#define EM_MICROBLAZE	189	/* Xilinx MicroBlaze */
+#define EM_CUDA		190	/* NVIDIA CUDA */
+#define EM_TILEGX	191	/* Tilera TILE-Gx */
+#define EM_CLOUDSHIELD	192	/* CloudShield */
+#define EM_COREA_1ST	193	/* KIPO-KAIST Core-A 1st gen. */
+#define EM_COREA_2ND	194	/* KIPO-KAIST Core-A 2nd gen. */
+#define EM_ARCV2	195	/* Synopsys ARCv2 ISA.  */
+#define EM_OPEN8	196	/* Open8 RISC */
+#define EM_RL78		197	/* Renesas RL78 */
+#define EM_VIDEOCORE5	198	/* Broadcom VideoCore V */
+#define EM_78KOR	199	/* Renesas 78KOR */
+#define EM_56800EX	200	/* Freescale 56800EX DSC */
+#define EM_BA1		201	/* Beyond BA1 */
+#define EM_BA2		202	/* Beyond BA2 */
+#define EM_XCORE	203	/* XMOS xCORE */
+#define EM_MCHP_PIC	204	/* Microchip 8-bit PIC(r) */
+#define EM_INTELGT	205	/* Intel Graphics Technology */
+				/* reserved 206-209 */
+#define EM_KM32		210	/* KM211 KM32 */
+#define EM_KMX32	211	/* KM211 KMX32 */
+#define EM_EMX16	212	/* KM211 KMX16 */
+#define EM_EMX8		213	/* KM211 KMX8 */
+#define EM_KVARC	214	/* KM211 KVARC */
+#define EM_CDP		215	/* Paneve CDP */
+#define EM_COGE		216	/* Cognitive Smart Memory Processor */
+#define EM_COOL		217	/* Bluechip CoolEngine */
+#define EM_NORC		218	/* Nanoradio Optimized RISC */
+#define EM_CSR_KALIMBA	219	/* CSR Kalimba */
+#define EM_Z80		220	/* Zilog Z80 */
+#define EM_VISIUM	221	/* Controls and Data Services VISIUMcore */
+#define EM_FT32		222	/* FTDI Chip FT32 */
+#define EM_MOXIE	223	/* Moxie processor */
+#define EM_AMDGPU	224	/* AMD GPU */
+				/* reserved 225-242 */
+#define EM_RISCV	243	/* RISC-V */
+
+#define EM_BPF		247	/* Linux BPF -- in-kernel virtual machine */
+#define EM_CSKY		252     /* C-SKY */
+#define EM_LOONGARCH	258	/* LoongArch */
+
+#define EM_NUM		259
+
+/* Old spellings/synonyms.  */
+
+#define EM_ARC_A5	EM_ARC_COMPACT
 
 /* If it is necessary to assign new unofficial EM_* values, please
    pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
@@ -326,8 +443,9 @@ typedef struct
 #define SHT_FINI_ARRAY	  15		/* Array of destructors */
 #define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
 #define SHT_GROUP	  17		/* Section group */
-#define SHT_SYMTAB_SHNDX  18		/* Extended section indeces */
-#define	SHT_NUM		  19		/* Number of defined types.  */
+#define SHT_SYMTAB_SHNDX  18		/* Extended section indices */
+#define SHT_RELR	  19            /* RELR relative relocations */
+#define	SHT_NUM		  20		/* Number of defined types.  */
 #define SHT_LOOS	  0x60000000	/* Start OS-specific.  */
 #define SHT_GNU_ATTRIBUTES 0x6ffffff5	/* Object attributes.  */
 #define SHT_GNU_HASH	  0x6ffffff6	/* GNU-style hash table.  */
@@ -360,13 +478,40 @@ typedef struct
 					   required */
 #define SHF_GROUP	     (1 << 9)	/* Section is member of a group.  */
 #define SHF_TLS		     (1 << 10)	/* Section hold thread-local data.  */
+#define SHF_COMPRESSED	     (1 << 11)	/* Section with compressed data. */
 #define SHF_MASKOS	     0x0ff00000	/* OS-specific.  */
 #define SHF_MASKPROC	     0xf0000000	/* Processor-specific */
+#define SHF_GNU_RETAIN	     (1 << 21)  /* Not to be GCed by linker.  */
 #define SHF_ORDERED	     (1 << 30)	/* Special ordering requirement
 					   (Solaris).  */
-#define SHF_EXCLUDE	     (1 << 31)	/* Section is excluded unless
+#define SHF_EXCLUDE	     (1U << 31)	/* Section is excluded unless
 					   referenced or allocated (Solaris).*/
 
+/* Section compression header.  Used when SHF_COMPRESSED is set.  */
+
+typedef struct
+{
+  Elf32_Word	ch_type;	/* Compression format.  */
+  Elf32_Word	ch_size;	/* Uncompressed data size.  */
+  Elf32_Word	ch_addralign;	/* Uncompressed data alignment.  */
+} Elf32_Chdr;
+
+typedef struct
+{
+  Elf64_Word	ch_type;	/* Compression format.  */
+  Elf64_Word	ch_reserved;
+  Elf64_Xword	ch_size;	/* Uncompressed data size.  */
+  Elf64_Xword	ch_addralign;	/* Uncompressed data alignment.  */
+} Elf64_Chdr;
+
+/* Legal values for ch_type (compression algorithm).  */
+#define ELFCOMPRESS_ZLIB	1	   /* ZLIB/DEFLATE algorithm.  */
+#define ELFCOMPRESS_ZSTD	2	   /* Zstandard algorithm.  */
+#define ELFCOMPRESS_LOOS	0x60000000 /* Start of OS-specific.  */
+#define ELFCOMPRESS_HIOS	0x6fffffff /* End of OS-specific.  */
+#define ELFCOMPRESS_LOPROC	0x70000000 /* Start of processor-specific.  */
+#define ELFCOMPRESS_HIPROC	0x7fffffff /* End of processor-specific.  */
+
 /* Section group handling.  */
 #define GRP_COMDAT	0x1		/* Mark group as COMDAT.  */
 
@@ -520,6 +665,11 @@ typedef struct
   Elf64_Sxword	r_addend;		/* Addend */
 } Elf64_Rela;
 
+/* RELR relocation table entry */
+
+typedef Elf32_Word	Elf32_Relr;
+typedef Elf64_Xword	Elf64_Relr;
+
 /* How to extract and insert information held in the r_info field.  */
 
 #define ELF32_R_SYM(val)		((val) >> 8)
@@ -577,6 +727,7 @@ typedef struct
 #define PT_GNU_EH_FRAME	0x6474e550	/* GCC .eh_frame_hdr segment */
 #define PT_GNU_STACK	0x6474e551	/* Indicates stack executability */
 #define PT_GNU_RELRO	0x6474e552	/* Read-only after relocation */
+#define PT_GNU_PROPERTY	0x6474e553	/* GNU property */
 #define PT_LOSUNW	0x6ffffffa
 #define PT_SUNWBSS	0x6ffffffa	/* Sun Specific segment */
 #define PT_SUNWSTACK	0x6ffffffb	/* Stack segment */
@@ -596,6 +747,8 @@ typedef struct
 /* Legal values for note segment descriptor types for core files. */
 
 #define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
+#define NT_PRFPREG	2		/* Contains copy of fpregset
+					   struct.  */
 #define NT_FPREGSET	2		/* Contains copy of fpregset struct */
 #define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
 #define NT_PRXREG	4		/* Contains copy of prxregset struct */
@@ -611,13 +764,82 @@ typedef struct
 #define NT_LWPSTATUS	16		/* Contains copy of lwpstatus struct */
 #define NT_LWPSINFO	17		/* Contains copy of lwpinfo struct */
 #define NT_PRFPXREG	20		/* Contains copy of fprxregset struct */
+#define NT_SIGINFO	0x53494749	/* Contains copy of siginfo_t,
+					   size might increase */
+#define NT_FILE		0x46494c45	/* Contains information about mapped
+					   files */
 #define NT_PRXFPREG	0x46e62b7f	/* Contains copy of user_fxsr_struct */
 #define NT_PPC_VMX	0x100		/* PowerPC Altivec/VMX registers */
 #define NT_PPC_SPE	0x101		/* PowerPC SPE/EVR registers */
 #define NT_PPC_VSX	0x102		/* PowerPC VSX registers */
+#define NT_PPC_TAR	0x103		/* Target Address Register */
+#define NT_PPC_PPR	0x104		/* Program Priority Register */
+#define NT_PPC_DSCR	0x105		/* Data Stream Control Register */
+#define NT_PPC_EBB	0x106		/* Event Based Branch Registers */
+#define NT_PPC_PMU	0x107		/* Performance Monitor Registers */
+#define NT_PPC_TM_CGPR	0x108		/* TM checkpointed GPR Registers */
+#define NT_PPC_TM_CFPR	0x109		/* TM checkpointed FPR Registers */
+#define NT_PPC_TM_CVMX	0x10a		/* TM checkpointed VMX Registers */
+#define NT_PPC_TM_CVSX	0x10b		/* TM checkpointed VSX Registers */
+#define NT_PPC_TM_SPR	0x10c		/* TM Special Purpose Registers */
+#define NT_PPC_TM_CTAR	0x10d		/* TM checkpointed Target Address
+					   Register */
+#define NT_PPC_TM_CPPR	0x10e		/* TM checkpointed Program Priority
+					   Register */
+#define NT_PPC_TM_CDSCR	0x10f		/* TM checkpointed Data Stream Control
+					   Register */
+#define NT_PPC_PKEY	0x110		/* Memory Protection Keys
+					   registers.  */
 #define NT_386_TLS	0x200		/* i386 TLS slots (struct user_desc) */
 #define NT_386_IOPERM	0x201		/* x86 io permission bitmap (1=deny) */
 #define NT_X86_XSTATE	0x202		/* x86 extended state using xsave */
+#define NT_S390_HIGH_GPRS	0x300	/* s390 upper register halves */
+#define NT_S390_TIMER	0x301		/* s390 timer register */
+#define NT_S390_TODCMP	0x302		/* s390 TOD clock comparator register */
+#define NT_S390_TODPREG	0x303		/* s390 TOD programmable register */
+#define NT_S390_CTRS	0x304		/* s390 control registers */
+#define NT_S390_PREFIX	0x305		/* s390 prefix register */
+#define NT_S390_LAST_BREAK	0x306	/* s390 breaking event address */
+#define NT_S390_SYSTEM_CALL	0x307	/* s390 system call restart data */
+#define NT_S390_TDB	0x308		/* s390 transaction diagnostic block */
+#define NT_S390_VXRS_LOW	0x309	/* s390 vector registers 0-15
+					   upper half.  */
+#define NT_S390_VXRS_HIGH	0x30a	/* s390 vector registers 16-31.  */
+#define NT_S390_GS_CB	0x30b		/* s390 guarded storage registers.  */
+#define NT_S390_GS_BC	0x30c		/* s390 guarded storage
+					   broadcast control block.  */
+#define NT_S390_RI_CB	0x30d		/* s390 runtime instrumentation.  */
+#define NT_S390_PV_CPU_DATA	0x30e	/* s390 protvirt cpu dump data.  */
+#define NT_ARM_VFP	0x400		/* ARM VFP/NEON registers */
+#define NT_ARM_TLS	0x401		/* ARM TLS register */
+#define NT_ARM_HW_BREAK	0x402		/* ARM hardware breakpoint registers */
+#define NT_ARM_HW_WATCH	0x403		/* ARM hardware watchpoint registers */
+#define NT_ARM_SYSTEM_CALL	0x404	/* ARM system call number */
+#define NT_ARM_SVE	0x405		/* ARM Scalable Vector Extension
+					   registers */
+#define NT_ARM_PAC_MASK	0x406		/* ARM pointer authentication
+					   code masks.  */
+#define NT_ARM_PACA_KEYS	0x407	/* ARM pointer authentication
+					   address keys.  */
+#define NT_ARM_PACG_KEYS	0x408	/* ARM pointer authentication
+					   generic key.  */
+#define NT_ARM_TAGGED_ADDR_CTRL	0x409	/* AArch64 tagged address
+					   control.  */
+#define NT_ARM_PAC_ENABLED_KEYS	0x40a	/* AArch64 pointer authentication
+					   enabled keys.  */
+#define NT_VMCOREDD	0x700		/* Vmcore Device Dump Note.  */
+#define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers.  */
+#define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode.  */
+#define NT_MIPS_MSA	0x802		/* MIPS SIMD registers.  */
+#define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers.  */
+#define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and
+					   status registers.  */
+#define NT_LOONGARCH_LSX	0xa02	/* LoongArch Loongson SIMD
+					   Extension registers.  */
+#define NT_LOONGARCH_LASX	0xa03	/* LoongArch Loongson Advanced
+					   SIMD Extension registers.  */
+#define NT_LOONGARCH_LBT	0xa04	/* LoongArch Loongson Binary
+					   Translation registers.  */
 
 /* Legal values for the note segment descriptor types for object files.  */
 
@@ -682,7 +904,11 @@ typedef struct
 #define DT_ENCODING	32		/* Start of encoded range */
 #define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
 #define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
-#define	DT_NUM		34		/* Number used */
+#define DT_SYMTAB_SHNDX	34		/* Address of SYMTAB_SHNDX section */
+#define DT_RELRSZ	35		/* Total size of RELR relative relocations */
+#define DT_RELR		36		/* Address of RELR relative relocations */
+#define DT_RELRENT	37		/* Size of one RELR relative relocaction */
+#define	DT_NUM		38		/* Number used */
 #define DT_LOOS		0x6000000d	/* Start of OS-specific */
 #define DT_HIOS		0x6ffff000	/* End of OS-specific */
 #define DT_LOPROC	0x70000000	/* Start of processor-specific */
@@ -781,6 +1007,20 @@ typedef struct
 #define DF_1_ENDFILTEE	0x00004000	/* Filtee terminates filters search. */
 #define	DF_1_DISPRELDNE	0x00008000	/* Disp reloc applied at build time. */
 #define	DF_1_DISPRELPND	0x00010000	/* Disp reloc applied at run-time.  */
+#define	DF_1_NODIRECT	0x00020000	/* Object has no-direct binding. */
+#define	DF_1_IGNMULDEF	0x00040000
+#define	DF_1_NOKSYMS	0x00080000
+#define	DF_1_NOHDR	0x00100000
+#define	DF_1_EDITED	0x00200000	/* Object is modified after built.  */
+#define	DF_1_NORELOC	0x00400000
+#define	DF_1_SYMINTPOSE	0x00800000	/* Object has individual interposers.  */
+#define	DF_1_GLOBAUDIT	0x01000000	/* Global auditing required.  */
+#define	DF_1_SINGLETON	0x02000000	/* Singleton symbols are used.  */
+#define	DF_1_STUB	0x04000000
+#define	DF_1_PIE	0x08000000
+#define	DF_1_KMOD       0x10000000
+#define	DF_1_WEAKFILTER 0x20000000
+#define	DF_1_NOCOMMON   0x40000000
 
 /* Flags for the feature selection in DT_FEATURE_1.  */
 #define DTF_1_PARINIT	0x00000001
@@ -825,7 +1065,8 @@ typedef struct
 
 /* Legal values for vd_flags (version information flags).  */
 #define VER_FLG_BASE	0x1		/* Version definition of file itself */
-#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier.  Also
+					   used by vna_flags below.  */
 
 /* Versym symbol index values.  */
 #define	VER_NDX_LOCAL		0	/* Symbol is local.  */
@@ -833,7 +1074,7 @@ typedef struct
 #define	VER_NDX_LORESERVE	0xff00	/* Beginning of reserved entries.  */
 #define	VER_NDX_ELIMINATE	0xff01	/* Symbol is to be eliminated.  */
 
-/* Auxialiary version information.  */
+/* Auxiliary version information.  */
 
 typedef struct
 {
@@ -903,10 +1144,6 @@ typedef struct
 } Elf64_Vernaux;
 
 
-/* Legal values for vna_flags.  */
-#define VER_FLG_WEAK	0x2		/* Weak version identifier */
-
-
 /* Auxiliary vector.  */
 
 /* This vector is normally only used by the program interpreter.  The
@@ -961,7 +1198,7 @@ typedef struct
 
 /* Some more special a_type values describing the hardware.  */
 #define AT_PLATFORM	15		/* String identifying platform.  */
-#define AT_HWCAP	16		/* Machine dependent hints about
+#define AT_HWCAP	16		/* Machine-dependent hints about
 					   processor capabilities.  */
 
 /* This entry gives some information about the FPU initialization
@@ -983,6 +1220,9 @@ typedef struct
 
 #define AT_RANDOM	25		/* Address of 16 random bytes.  */
 
+#define AT_HWCAP2	26		/* More machine-dependent hints about
+					   processor capabilities.  */
+
 #define AT_EXECFN	31		/* Filename of executable.  */
 
 /* Pointer to the global system page used for system calls and other
@@ -997,6 +1237,20 @@ typedef struct
 #define AT_L2_CACHESHAPE	36
 #define AT_L3_CACHESHAPE	37
 
+/* Shapes of the caches, with more room to describe them.
+   *GEOMETRY are comprised of cache line size in bytes in the bottom 16 bits
+   and the cache associativity in the next 16 bits.  */
+#define AT_L1I_CACHESIZE	40
+#define AT_L1I_CACHEGEOMETRY	41
+#define AT_L1D_CACHESIZE	42
+#define AT_L1D_CACHEGEOMETRY	43
+#define AT_L2_CACHESIZE		44
+#define AT_L2_CACHEGEOMETRY	45
+#define AT_L3_CACHESIZE		46
+#define AT_L3_CACHEGEOMETRY	47
+
+#define AT_MINSIGSTKSZ		51 /* Stack needed for signal delivery  */
+
 /* Note section contents.  Each entry in the note section begins with
    a header of a fixed form.  */
 
@@ -1022,6 +1276,8 @@ typedef struct
 /* Note entries for GNU systems have this name.  */
 #define ELF_NOTE_GNU		"GNU"
 
+/* Note entries for freedesktop.org have this name.  */
+#define ELF_NOTE_FDO		"FDO"
 
 /* Defined types of notes for Solaris.  */
 
@@ -1062,6 +1318,84 @@ typedef struct
 /* Version note generated by GNU gold containing a version string.  */
 #define NT_GNU_GOLD_VERSION	4
 
+/* Program property.  */
+#define NT_GNU_PROPERTY_TYPE_0 5
+
+/* Packaging metadata as defined on
+   https://systemd.io/COREDUMP_PACKAGE_METADATA/ */
+#define NT_FDO_PACKAGING_METADATA 0xcafe1a7e
+
+/* Note section name of program property.   */
+#define NOTE_GNU_PROPERTY_SECTION_NAME ".note.gnu.property"
+
+/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0).  */
+
+/* Stack size.  */
+#define GNU_PROPERTY_STACK_SIZE			1
+/* No copy relocation on protected data symbol.  */
+#define GNU_PROPERTY_NO_COPY_ON_PROTECTED	2
+
+/* A 4-byte unsigned integer property: A bit is set if it is set in all
+   relocatable inputs.  */
+#define GNU_PROPERTY_UINT32_AND_LO	0xb0000000
+#define GNU_PROPERTY_UINT32_AND_HI	0xb0007fff
+
+/* A 4-byte unsigned integer property: A bit is set if it is set in any
+   relocatable inputs.  */
+#define GNU_PROPERTY_UINT32_OR_LO	0xb0008000
+#define GNU_PROPERTY_UINT32_OR_HI	0xb000ffff
+
+/* The needed properties by the object file.  */
+#define GNU_PROPERTY_1_NEEDED		GNU_PROPERTY_UINT32_OR_LO
+
+/* Set if the object file requires canonical function pointers and
+   cannot be used with copy relocation.  */
+#define GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0)
+
+/* Processor-specific semantics, lo */
+#define GNU_PROPERTY_LOPROC			0xc0000000
+/* Processor-specific semantics, hi */
+#define GNU_PROPERTY_HIPROC			0xdfffffff
+/* Application-specific semantics, lo */
+#define GNU_PROPERTY_LOUSER			0xe0000000
+/* Application-specific semantics, hi */
+#define GNU_PROPERTY_HIUSER			0xffffffff
+
+/* AArch64 specific GNU properties.  */
+#define GNU_PROPERTY_AARCH64_FEATURE_1_AND	0xc0000000
+
+#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI	(1U << 0)
+#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC	(1U << 1)
+
+/* The x86 instruction sets indicated by the corresponding bits are
+   used in program.  Their support in the hardware is optional.  */
+#define GNU_PROPERTY_X86_ISA_1_USED		0xc0010002
+/* The x86 instruction sets indicated by the corresponding bits are
+   used in program and they must be supported by the hardware.   */
+#define GNU_PROPERTY_X86_ISA_1_NEEDED		0xc0008002
+/* X86 processor-specific features used in program.  */
+#define GNU_PROPERTY_X86_FEATURE_1_AND		0xc0000002
+
+/* GNU_PROPERTY_X86_ISA_1_BASELINE: CMOV, CX8 (cmpxchg8b), FPU (fld),
+   MMX, OSFXSR (fxsave), SCE (syscall), SSE and SSE2.  */
+#define GNU_PROPERTY_X86_ISA_1_BASELINE		(1U << 0)
+/* GNU_PROPERTY_X86_ISA_1_V2: GNU_PROPERTY_X86_ISA_1_BASELINE,
+   CMPXCHG16B (cmpxchg16b), LAHF-SAHF (lahf), POPCNT (popcnt), SSE3,
+   SSSE3, SSE4.1 and SSE4.2.  */
+#define GNU_PROPERTY_X86_ISA_1_V2		(1U << 1)
+/* GNU_PROPERTY_X86_ISA_1_V3: GNU_PROPERTY_X86_ISA_1_V2, AVX, AVX2, BMI1,
+   BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE.  */
+#define GNU_PROPERTY_X86_ISA_1_V3		(1U << 2)
+/* GNU_PROPERTY_X86_ISA_1_V4: GNU_PROPERTY_X86_ISA_1_V3, AVX512F,
+   AVX512BW, AVX512CD, AVX512DQ and AVX512VL.  */
+#define GNU_PROPERTY_X86_ISA_1_V4		(1U << 3)
+
+/* This indicates that all executable sections are compatible with
+   IBT.  */
+#define GNU_PROPERTY_X86_FEATURE_1_IBT		(1U << 0)
+/* This indicates that all executable sections are compatible with
+   SHSTK.  */
+#define GNU_PROPERTY_X86_FEATURE_1_SHSTK	(1U << 1)
 
 /* Move records.  */
 typedef struct
@@ -1198,7 +1532,7 @@ typedef struct
 #define R_386_TLS_DTPMOD32 35		/* ID of module containing symbol */
 #define R_386_TLS_DTPOFF32 36		/* Offset in TLS block */
 #define R_386_TLS_TPOFF32  37		/* Negated offset in static TLS block */
-/* 38? */
+#define R_386_SIZE32	   38 		/* 32-bit symbol size */
 #define R_386_TLS_GOTDESC  39		/* GOT offset for TLS descriptor.  */
 #define R_386_TLS_DESC_CALL 40		/* Marker of call through TLS
 					   descriptor for
@@ -1208,8 +1542,10 @@ typedef struct
 					   argument, returning the TLS
 					   offset for the symbol.  */
 #define R_386_IRELATIVE	   42		/* Adjust indirectly by program base */
+#define R_386_GOT32X	   43		/* Load from 32 bit GOT entry,
+					   relaxable. */
 /* Keep this the last entry.  */
-#define R_386_NUM	   43
+#define R_386_NUM	   44
 
 /* SUN SPARC specific definitions.  */
 
@@ -1334,102 +1670,107 @@ typedef struct
 
 /* For Sparc64, legal values for d_tag of Elf64_Dyn.  */
 
-#define DT_SPARC_REGISTER 0x70000001
-#define DT_SPARC_NUM	2
+#define DT_SPARC_REGISTER	0x70000001
+#define DT_SPARC_NUM		2
 
 /* MIPS R3000 specific definitions.  */
 
 /* Legal values for e_flags field of Elf32_Ehdr.  */
 
-#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
-#define EF_MIPS_PIC	    2		/* Contains PIC code */
-#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
-#define EF_MIPS_XGOT	    8
-#define EF_MIPS_64BIT_WHIRL 16
-#define EF_MIPS_ABI2	    32
-#define EF_MIPS_ABI_ON32    64
-#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
+#define EF_MIPS_NOREORDER	1     /* A .noreorder directive was used.  */
+#define EF_MIPS_PIC		2     /* Contains PIC code.  */
+#define EF_MIPS_CPIC		4     /* Uses PIC calling sequence.  */
+#define EF_MIPS_XGOT		8
+#define EF_MIPS_64BIT_WHIRL	16
+#define EF_MIPS_ABI2		32
+#define EF_MIPS_ABI_ON32	64
+#define EF_MIPS_FP64		512  /* Uses FP64 (12 callee-saved).  */
+#define EF_MIPS_NAN2008	1024  /* Uses IEEE 754-2008 NaN encoding.  */
+#define EF_MIPS_ARCH		0xf0000000 /* MIPS architecture level.  */
 
 /* Legal values for MIPS architecture level.  */
 
-#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
-#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
-#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
-#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
-#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
-#define EF_MIPS_ARCH_32	    0x60000000	/* MIPS32 code.  */
-#define EF_MIPS_ARCH_64	    0x70000000	/* MIPS64 code.  */
-
-/* The following are non-official names and should not be used.  */
-
-#define E_MIPS_ARCH_1	  0x00000000	/* -mips1 code.  */
-#define E_MIPS_ARCH_2	  0x10000000	/* -mips2 code.  */
-#define E_MIPS_ARCH_3	  0x20000000	/* -mips3 code.  */
-#define E_MIPS_ARCH_4	  0x30000000	/* -mips4 code.  */
-#define E_MIPS_ARCH_5	  0x40000000	/* -mips5 code.  */
-#define E_MIPS_ARCH_32	  0x60000000	/* MIPS32 code.  */
-#define E_MIPS_ARCH_64	  0x70000000	/* MIPS64 code.  */
+#define EF_MIPS_ARCH_1		0x00000000 /* -mips1 code.  */
+#define EF_MIPS_ARCH_2		0x10000000 /* -mips2 code.  */
+#define EF_MIPS_ARCH_3		0x20000000 /* -mips3 code.  */
+#define EF_MIPS_ARCH_4		0x30000000 /* -mips4 code.  */
+#define EF_MIPS_ARCH_5		0x40000000 /* -mips5 code.  */
+#define EF_MIPS_ARCH_32		0x50000000 /* MIPS32 code.  */
+#define EF_MIPS_ARCH_64		0x60000000 /* MIPS64 code.  */
+#define EF_MIPS_ARCH_32R2	0x70000000 /* MIPS32r2 code.  */
+#define EF_MIPS_ARCH_64R2	0x80000000 /* MIPS64r2 code.  */
+
+/* The following are unofficial names and should not be used.  */
+
+#define E_MIPS_ARCH_1		EF_MIPS_ARCH_1
+#define E_MIPS_ARCH_2		EF_MIPS_ARCH_2
+#define E_MIPS_ARCH_3		EF_MIPS_ARCH_3
+#define E_MIPS_ARCH_4		EF_MIPS_ARCH_4
+#define E_MIPS_ARCH_5		EF_MIPS_ARCH_5
+#define E_MIPS_ARCH_32		EF_MIPS_ARCH_32
+#define E_MIPS_ARCH_64		EF_MIPS_ARCH_64
 
 /* Special section indices.  */
 
-#define SHN_MIPS_ACOMMON    0xff00	/* Allocated common symbols */
-#define SHN_MIPS_TEXT	    0xff01	/* Allocated test symbols.  */
-#define SHN_MIPS_DATA	    0xff02	/* Allocated data symbols.  */
-#define SHN_MIPS_SCOMMON    0xff03	/* Small common symbols */
-#define SHN_MIPS_SUNDEFINED 0xff04	/* Small undefined symbols */
+#define SHN_MIPS_ACOMMON	0xff00	/* Allocated common symbols.  */
+#define SHN_MIPS_TEXT		0xff01	/* Allocated test symbols.  */
+#define SHN_MIPS_DATA		0xff02	/* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON 	0xff03	/* Small common symbols.  */
+#define SHN_MIPS_SUNDEFINED	0xff04	/* Small undefined symbols.  */
 
 /* Legal values for sh_type field of Elf32_Shdr.  */
 
-#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */
-#define SHT_MIPS_MSYM	       0x70000001
-#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */
-#define SHT_MIPS_GPTAB	       0x70000003 /* Global data area sizes */
-#define SHT_MIPS_UCODE	       0x70000004 /* Reserved for SGI/MIPS compilers */
-#define SHT_MIPS_DEBUG	       0x70000005 /* MIPS ECOFF debugging information*/
-#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */
-#define SHT_MIPS_PACKAGE       0x70000007
-#define SHT_MIPS_PACKSYM       0x70000008
-#define SHT_MIPS_RELD	       0x70000009
-#define SHT_MIPS_IFACE         0x7000000b
-#define SHT_MIPS_CONTENT       0x7000000c
-#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */
-#define SHT_MIPS_SHDR	       0x70000010
-#define SHT_MIPS_FDESC	       0x70000011
-#define SHT_MIPS_EXTSYM	       0x70000012
-#define SHT_MIPS_DENSE	       0x70000013
-#define SHT_MIPS_PDESC	       0x70000014
-#define SHT_MIPS_LOCSYM	       0x70000015
-#define SHT_MIPS_AUXSYM	       0x70000016
-#define SHT_MIPS_OPTSYM	       0x70000017
-#define SHT_MIPS_LOCSTR	       0x70000018
-#define SHT_MIPS_LINE	       0x70000019
-#define SHT_MIPS_RFDESC	       0x7000001a
-#define SHT_MIPS_DELTASYM      0x7000001b
-#define SHT_MIPS_DELTAINST     0x7000001c
-#define SHT_MIPS_DELTACLASS    0x7000001d
-#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */
-#define SHT_MIPS_DELTADECL     0x7000001f
-#define SHT_MIPS_SYMBOL_LIB    0x70000020
-#define SHT_MIPS_EVENTS	       0x70000021 /* Event section.  */
-#define SHT_MIPS_TRANSLATE     0x70000022
-#define SHT_MIPS_PIXIE	       0x70000023
-#define SHT_MIPS_XLATE	       0x70000024
-#define SHT_MIPS_XLATE_DEBUG   0x70000025
-#define SHT_MIPS_WHIRL	       0x70000026
-#define SHT_MIPS_EH_REGION     0x70000027
-#define SHT_MIPS_XLATE_OLD     0x70000028
-#define SHT_MIPS_PDR_EXCEPTION 0x70000029
+#define SHT_MIPS_LIBLIST	0x70000000 /* Shared objects used in link.  */
+#define SHT_MIPS_MSYM		0x70000001
+#define SHT_MIPS_CONFLICT	0x70000002 /* Conflicting symbols.  */
+#define SHT_MIPS_GPTAB		0x70000003 /* Global data area sizes.  */
+#define SHT_MIPS_UCODE		0x70000004 /* Reserved for SGI/MIPS compilers */
+#define SHT_MIPS_DEBUG		0x70000005 /* MIPS ECOFF debugging info.  */
+#define SHT_MIPS_REGINFO	0x70000006 /* Register usage information.  */
+#define SHT_MIPS_PACKAGE	0x70000007
+#define SHT_MIPS_PACKSYM	0x70000008
+#define SHT_MIPS_RELD		0x70000009
+#define SHT_MIPS_IFACE		0x7000000b
+#define SHT_MIPS_CONTENT	0x7000000c
+#define SHT_MIPS_OPTIONS	0x7000000d /* Miscellaneous options.  */
+#define SHT_MIPS_SHDR		0x70000010
+#define SHT_MIPS_FDESC		0x70000011
+#define SHT_MIPS_EXTSYM		0x70000012
+#define SHT_MIPS_DENSE		0x70000013
+#define SHT_MIPS_PDESC		0x70000014
+#define SHT_MIPS_LOCSYM		0x70000015
+#define SHT_MIPS_AUXSYM		0x70000016
+#define SHT_MIPS_OPTSYM		0x70000017
+#define SHT_MIPS_LOCSTR		0x70000018
+#define SHT_MIPS_LINE		0x70000019
+#define SHT_MIPS_RFDESC		0x7000001a
+#define SHT_MIPS_DELTASYM	0x7000001b
+#define SHT_MIPS_DELTAINST	0x7000001c
+#define SHT_MIPS_DELTACLASS	0x7000001d
+#define SHT_MIPS_DWARF		0x7000001e /* DWARF debugging information.  */
+#define SHT_MIPS_DELTADECL	0x7000001f
+#define SHT_MIPS_SYMBOL_LIB	0x70000020
+#define SHT_MIPS_EVENTS		0x70000021 /* Event section.  */
+#define SHT_MIPS_TRANSLATE	0x70000022
+#define SHT_MIPS_PIXIE		0x70000023
+#define SHT_MIPS_XLATE		0x70000024
+#define SHT_MIPS_XLATE_DEBUG	0x70000025
+#define SHT_MIPS_WHIRL		0x70000026
+#define SHT_MIPS_EH_REGION	0x70000027
+#define SHT_MIPS_XLATE_OLD	0x70000028
+#define SHT_MIPS_PDR_EXCEPTION	0x70000029
+#define SHT_MIPS_XHASH		0x7000002b
 
 /* Legal values for sh_flags field of Elf32_Shdr.  */
 
-#define SHF_MIPS_GPREL	 0x10000000	/* Must be part of global data area */
-#define SHF_MIPS_MERGE	 0x20000000
-#define SHF_MIPS_ADDR	 0x40000000
-#define SHF_MIPS_STRINGS 0x80000000
-#define SHF_MIPS_NOSTRIP 0x08000000
-#define SHF_MIPS_LOCAL	 0x04000000
-#define SHF_MIPS_NAMES	 0x02000000
-#define SHF_MIPS_NODUPE	 0x01000000
+#define SHF_MIPS_GPREL		0x10000000 /* Must be in global data area.  */
+#define SHF_MIPS_MERGE		0x20000000
+#define SHF_MIPS_ADDR		0x40000000
+#define SHF_MIPS_STRINGS	0x80000000
+#define SHF_MIPS_NOSTRIP	0x08000000
+#define SHF_MIPS_LOCAL		0x04000000
+#define SHF_MIPS_NAMES		0x02000000
+#define SHF_MIPS_NODUPE		0x01000000
 
 
 /* Symbol tables.  */
@@ -1451,23 +1792,23 @@ typedef union
 {
   struct
     {
-      Elf32_Word gt_current_g_value;	/* -G value used for compilation */
-      Elf32_Word gt_unused;		/* Not used */
-    } gt_header;			/* First entry in section */
+      Elf32_Word gt_current_g_value;	/* -G value used for compilation.  */
+      Elf32_Word gt_unused;		/* Not used.  */
+    } gt_header;			/* First entry in section.  */
   struct
     {
-      Elf32_Word gt_g_value;		/* If this value were used for -G */
-      Elf32_Word gt_bytes;		/* This many bytes would be used */
-    } gt_entry;				/* Subsequent entries in section */
+      Elf32_Word gt_g_value;		/* If this value were used for -G.  */
+      Elf32_Word gt_bytes;		/* This many bytes would be used.  */
+    } gt_entry;				/* Subsequent entries in section.  */
 } Elf32_gptab;
 
 /* Entry found in sections of type SHT_MIPS_REGINFO.  */
 
 typedef struct
 {
-  Elf32_Word	ri_gprmask;		/* General registers used */
-  Elf32_Word	ri_cprmask[4];		/* Coprocessor registers used */
-  Elf32_Sword	ri_gp_value;		/* $gp register value */
+  Elf32_Word ri_gprmask;		/* General registers used.  */
+  Elf32_Word ri_cprmask[4];		/* Coprocessor registers used.  */
+  Elf32_Sword ri_gp_value;		/* $gp register value.  */
 } Elf32_RegInfo;
 
 /* Entries found in sections of type SHT_MIPS_OPTIONS.  */
@@ -1593,9 +1934,10 @@ typedef struct
 
 /* Legal values for p_type field of Elf32_Phdr.  */
 
-#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
-#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
-#define PT_MIPS_OPTIONS 0x70000002
+#define PT_MIPS_REGINFO	  0x70000000	/* Register usage information. */
+#define PT_MIPS_RTPROC	  0x70000001	/* Runtime procedure table. */
+#define PT_MIPS_OPTIONS	  0x70000002
+#define PT_MIPS_ABIFLAGS  0x70000003	/* FP mode requirement. */
 
 /* Special program header types.  */
 
@@ -1661,7 +2003,13 @@ typedef struct
    PLT is writable.  For a non-writable PLT, this is omitted or has a zero
    value.  */
 #define DT_MIPS_RWPLT        0x70000034
-#define DT_MIPS_NUM	     0x35
+/* An alternative description of the classic MIPS RLD_MAP that is usable
+   in a PIE as it stores a relative offset from the address of the tag
+   rather than an absolute address.  */
+#define DT_MIPS_RLD_MAP_REL  0x70000035
+/* GNU-style hash table with xlat.  */
+#define DT_MIPS_XHASH	     0x70000036
+#define DT_MIPS_NUM	     0x37
 
 /* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */
 
@@ -1717,6 +2065,101 @@ typedef struct
 
 typedef Elf32_Addr Elf32_Conflict;
 
+typedef struct
+{
+  /* Version of flags structure.  */
+  Elf32_Half version;
+  /* The level of the ISA: 1-5, 32, 64.  */
+  unsigned char isa_level;
+  /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise.  */
+  unsigned char isa_rev;
+  /* The size of general purpose registers.  */
+  unsigned char gpr_size;
+  /* The size of co-processor 1 registers.  */
+  unsigned char cpr1_size;
+  /* The size of co-processor 2 registers.  */
+  unsigned char cpr2_size;
+  /* The floating-point ABI.  */
+  unsigned char fp_abi;
+  /* Processor-specific extension.  */
+  Elf32_Word isa_ext;
+  /* Mask of ASEs used.  */
+  Elf32_Word ases;
+  /* Mask of general flags.  */
+  Elf32_Word flags1;
+  Elf32_Word flags2;
+} Elf_MIPS_ABIFlags_v0;
+
+/* Values for the register size bytes of an abi flags structure.  */
+
+#define MIPS_AFL_REG_NONE	0x00	 /* No registers.  */
+#define MIPS_AFL_REG_32		0x01	 /* 32-bit registers.  */
+#define MIPS_AFL_REG_64		0x02	 /* 64-bit registers.  */
+#define MIPS_AFL_REG_128	0x03	 /* 128-bit registers.  */
+
+/* Masks for the ases word of an ABI flags structure.  */
+
+#define MIPS_AFL_ASE_DSP	0x00000001 /* DSP ASE.  */
+#define MIPS_AFL_ASE_DSPR2	0x00000002 /* DSP R2 ASE.  */
+#define MIPS_AFL_ASE_EVA	0x00000004 /* Enhanced VA Scheme.  */
+#define MIPS_AFL_ASE_MCU	0x00000008 /* MCU (MicroController) ASE.  */
+#define MIPS_AFL_ASE_MDMX	0x00000010 /* MDMX ASE.  */
+#define MIPS_AFL_ASE_MIPS3D	0x00000020 /* MIPS-3D ASE.  */
+#define MIPS_AFL_ASE_MT		0x00000040 /* MT ASE.  */
+#define MIPS_AFL_ASE_SMARTMIPS	0x00000080 /* SmartMIPS ASE.  */
+#define MIPS_AFL_ASE_VIRT	0x00000100 /* VZ ASE.  */
+#define MIPS_AFL_ASE_MSA	0x00000200 /* MSA ASE.  */
+#define MIPS_AFL_ASE_MIPS16	0x00000400 /* MIPS16 ASE.  */
+#define MIPS_AFL_ASE_MICROMIPS	0x00000800 /* MICROMIPS ASE.  */
+#define MIPS_AFL_ASE_XPA	0x00001000 /* XPA ASE.  */
+#define MIPS_AFL_ASE_MASK	0x00001fff /* All ASEs.  */
+
+/* Values for the isa_ext word of an ABI flags structure.  */
+
+#define MIPS_AFL_EXT_XLR	  1   /* RMI Xlr instruction.  */
+#define MIPS_AFL_EXT_OCTEON2	  2   /* Cavium Networks Octeon2.  */
+#define MIPS_AFL_EXT_OCTEONP	  3   /* Cavium Networks OcteonP.  */
+#define MIPS_AFL_EXT_LOONGSON_3A  4   /* Loongson 3A.  */
+#define MIPS_AFL_EXT_OCTEON	  5   /* Cavium Networks Octeon.  */
+#define MIPS_AFL_EXT_5900	  6   /* MIPS R5900 instruction.  */
+#define MIPS_AFL_EXT_4650	  7   /* MIPS R4650 instruction.  */
+#define MIPS_AFL_EXT_4010	  8   /* LSI R4010 instruction.  */
+#define MIPS_AFL_EXT_4100	  9   /* NEC VR4100 instruction.  */
+#define MIPS_AFL_EXT_3900	  10  /* Toshiba R3900 instruction.  */
+#define MIPS_AFL_EXT_10000	  11  /* MIPS R10000 instruction.  */
+#define MIPS_AFL_EXT_SB1	  12  /* Broadcom SB-1 instruction.  */
+#define MIPS_AFL_EXT_4111	  13  /* NEC VR4111/VR4181 instruction.  */
+#define MIPS_AFL_EXT_4120	  14  /* NEC VR4120 instruction.  */
+#define MIPS_AFL_EXT_5400	  15  /* NEC VR5400 instruction.  */
+#define MIPS_AFL_EXT_5500	  16  /* NEC VR5500 instruction.  */
+#define MIPS_AFL_EXT_LOONGSON_2E  17  /* ST Microelectronics Loongson 2E.  */
+#define MIPS_AFL_EXT_LOONGSON_2F  18  /* ST Microelectronics Loongson 2F.  */
+
+/* Masks for the flags1 word of an ABI flags structure.  */
+#define MIPS_AFL_FLAGS1_ODDSPREG  1  /* Uses odd single-precision registers.  */
+
+/* Object attribute values.  */
+enum
+{
+  /* Not tagged or not using any ABIs affected by the differences.  */
+  Val_GNU_MIPS_ABI_FP_ANY = 0,
+  /* Using hard-float -mdouble-float.  */
+  Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
+  /* Using hard-float -msingle-float.  */
+  Val_GNU_MIPS_ABI_FP_SINGLE = 2,
+  /* Using soft-float.  */
+  Val_GNU_MIPS_ABI_FP_SOFT = 3,
+  /* Using -mips32r2 -mfp64.  */
+  Val_GNU_MIPS_ABI_FP_OLD_64 = 4,
+  /* Using -mfpxx.  */
+  Val_GNU_MIPS_ABI_FP_XX = 5,
+  /* Using -mips32r2 -mfp64.  */
+  Val_GNU_MIPS_ABI_FP_64 = 6,
+  /* Using -mips32r2 -mfp64 -mno-odd-spreg.  */
+  Val_GNU_MIPS_ABI_FP_64A = 7,
+  /* Maximum allocated FP ABI value.  */
+  Val_GNU_MIPS_ABI_FP_MAX = 7
+};
 
 /* HPPA specific definitions.  */
 
@@ -1737,9 +2180,9 @@ typedef Elf32_Addr Elf32_Conflict;
 #define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
 #define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
 
-/* Additional section indeces.  */
+/* Additional section indices.  */
 
-#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
+#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tentatively declared
 					      symbols in ANSI C.  */
 #define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
 
@@ -2058,6 +2501,8 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got@dtprel@l */
 #define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got@dtprel@h */
 #define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got@dtprel@ha */
+#define R_PPC_TLSGD		95 /* none	(sym+add)@tlsgd */
+#define R_PPC_TLSLD		96 /* none	(sym+add)@tlsld */
 
 /* The remaining relocs are from the Embedded ELF ABI, and are not
    in the SVR4 ELF ABI.  */
@@ -2101,7 +2546,11 @@ typedef Elf32_Addr Elf32_Conflict;
 
 /* PowerPC specific values for the Dyn d_tag field.  */
 #define DT_PPC_GOT		(DT_LOPROC + 0)
-#define DT_PPC_NUM		1
+#define DT_PPC_OPT		(DT_LOPROC + 1)
+#define DT_PPC_NUM		2
+
+/* PowerPC specific values for the DT_PPC_OPT Dyn entry.  */
+#define PPC_OPT_TLS		1
 
 /* PowerPC64 relocations defined by the ABIs */
 #define R_PPC64_NONE		R_PPC_NONE
@@ -2214,6 +2663,17 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel@highera */
 #define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel@highest */
 #define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel@highesta */
+#define R_PPC64_TLSGD		107 /* none	(sym+add)@tlsgd */
+#define R_PPC64_TLSLD		108 /* none	(sym+add)@tlsld */
+#define R_PPC64_TOCSAVE		109 /* none */
+
+/* Added when HA and HI relocs were changed to report overflows.  */
+#define R_PPC64_ADDR16_HIGH	110
+#define R_PPC64_ADDR16_HIGHA	111
+#define R_PPC64_TPREL16_HIGH	112
+#define R_PPC64_TPREL16_HIGHA	113
+#define R_PPC64_DTPREL16_HIGH	114
+#define R_PPC64_DTPREL16_HIGHA	115
 
 /* GNU extension to support local ifunc.  */
 #define R_PPC64_JMP_IREL	247
@@ -2223,11 +2683,29 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_PPC64_REL16_HI	251	/* half16   (sym+add-.)@h */
 #define R_PPC64_REL16_HA	252	/* half16   (sym+add-.)@ha */
 
+/* e_flags bits specifying ABI.
+   1 for original function descriptor using ABI,
+   2 for revised ABI without function descriptors,
+   0 for unspecified or not using any features affected by the differences.  */
+#define EF_PPC64_ABI	3
+
 /* PowerPC64 specific values for the Dyn d_tag field.  */
 #define DT_PPC64_GLINK  (DT_LOPROC + 0)
 #define DT_PPC64_OPD	(DT_LOPROC + 1)
 #define DT_PPC64_OPDSZ	(DT_LOPROC + 2)
-#define DT_PPC64_NUM    3
+#define DT_PPC64_OPT	(DT_LOPROC + 3)
+#define DT_PPC64_NUM    4
+
+/* PowerPC64 specific bits in the DT_PPC64_OPT Dyn entry.  */
+#define PPC64_OPT_TLS		1
+#define PPC64_OPT_MULTI_TOC	2
+#define PPC64_OPT_LOCALENTRY	4
+
+/* PowerPC64 specific values for the Elf64_Sym st_other field.  */
+#define STO_PPC64_LOCAL_BIT	5
+#define STO_PPC64_LOCAL_MASK	(7 << STO_PPC64_LOCAL_BIT)
+#define PPC64_LOCAL_ENTRY_OFFSET(other)				\
+ (((1 << (((other) & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT)) >> 2) << 2)
 
 
 /* ARM specific declarations */
@@ -2246,6 +2724,9 @@ typedef Elf32_Addr Elf32_Conflict;
 #define EF_ARM_VFP_FLOAT	0x400
 #define EF_ARM_MAVERICK_FLOAT	0x800
 
+#define EF_ARM_ABI_FLOAT_SOFT	0x200   /* NB conflicts with EF_ARM_SOFT_FLOAT */
+#define EF_ARM_ABI_FLOAT_HARD	0x400   /* NB conflicts with EF_ARM_VFP_FLOAT */
+
 
 /* Other constants defined in the ARM ELF spec. version B-01.  */
 /* NB. These conflict with values defined above.  */
@@ -2290,26 +2771,180 @@ typedef Elf32_Addr Elf32_Conflict;
 #define SHT_ARM_ATTRIBUTES	(SHT_LOPROC + 3) /* ARM attributes section.  */
 
 
+/* AArch64 relocs.  */
+
+#define R_AARCH64_NONE            0	/* No relocation.  */
+
+/* ILP32 AArch64 relocs.  */
+#define R_AARCH64_P32_ABS32		  1	/* Direct 32 bit.  */
+#define R_AARCH64_P32_COPY		180	/* Copy symbol at runtime.  */
+#define R_AARCH64_P32_GLOB_DAT		181	/* Create GOT entry.  */
+#define R_AARCH64_P32_JUMP_SLOT		182	/* Create PLT entry.  */
+#define R_AARCH64_P32_RELATIVE		183	/* Adjust by program base.  */
+#define R_AARCH64_P32_TLS_DTPMOD	184	/* Module number, 32 bit.  */
+#define R_AARCH64_P32_TLS_DTPREL	185	/* Module-relative offset, 32 bit.  */
+#define R_AARCH64_P32_TLS_TPREL		186	/* TP-relative offset, 32 bit.  */
+#define R_AARCH64_P32_TLSDESC		187	/* TLS Descriptor.  */
+#define R_AARCH64_P32_IRELATIVE		188	/* STT_GNU_IFUNC relocation. */
+
+/* LP64 AArch64 relocs.  */
+#define R_AARCH64_ABS64         257	/* Direct 64 bit. */
+#define R_AARCH64_ABS32         258	/* Direct 32 bit.  */
+#define R_AARCH64_ABS16		259	/* Direct 16-bit.  */
+#define R_AARCH64_PREL64	260	/* PC-relative 64-bit.	*/
+#define R_AARCH64_PREL32	261	/* PC-relative 32-bit.	*/
+#define R_AARCH64_PREL16	262	/* PC-relative 16-bit.	*/
+#define R_AARCH64_MOVW_UABS_G0	263	/* Dir. MOVZ imm. from bits 15:0.  */
+#define R_AARCH64_MOVW_UABS_G0_NC 264	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_UABS_G1	265	/* Dir. MOVZ imm. from bits 31:16.  */
+#define R_AARCH64_MOVW_UABS_G1_NC 266	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_UABS_G2	267	/* Dir. MOVZ imm. from bits 47:32.  */
+#define R_AARCH64_MOVW_UABS_G2_NC 268	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_UABS_G3	269	/* Dir. MOV{K,Z} imm. from 63:48.  */
+#define R_AARCH64_MOVW_SABS_G0	270	/* Dir. MOV{N,Z} imm. from 15:0.  */
+#define R_AARCH64_MOVW_SABS_G1	271	/* Dir. MOV{N,Z} imm. from 31:16.  */
+#define R_AARCH64_MOVW_SABS_G2	272	/* Dir. MOV{N,Z} imm. from 47:32.  */
+#define R_AARCH64_LD_PREL_LO19	273	/* PC-rel. LD imm. from bits 20:2.  */
+#define R_AARCH64_ADR_PREL_LO21	274	/* PC-rel. ADR imm. from bits 20:0.  */
+#define R_AARCH64_ADR_PREL_PG_HI21 275	/* Page-rel. ADRP imm. from 32:12.  */
+#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 /* Likewise; no overflow check.  */
+#define R_AARCH64_ADD_ABS_LO12_NC 277	/* Dir. ADD imm. from bits 11:0.  */
+#define R_AARCH64_LDST8_ABS_LO12_NC 278	/* Likewise for LD/ST; no check. */
+#define R_AARCH64_TSTBR14	279	/* PC-rel. TBZ/TBNZ imm. from 15:2.  */
+#define R_AARCH64_CONDBR19	280	/* PC-rel. cond. br. imm. from 20:2. */
+#define R_AARCH64_JUMP26	282	/* PC-rel. B imm. from bits 27:2.  */
+#define R_AARCH64_CALL26	283	/* Likewise for CALL.  */
+#define R_AARCH64_LDST16_ABS_LO12_NC 284 /* Dir. ADD imm. from bits 11:1.  */
+#define R_AARCH64_LDST32_ABS_LO12_NC 285 /* Likewise for bits 11:2.  */
+#define R_AARCH64_LDST64_ABS_LO12_NC 286 /* Likewise for bits 11:3.  */
+#define R_AARCH64_MOVW_PREL_G0	287	/* PC-rel. MOV{N,Z} imm. from 15:0.  */
+#define R_AARCH64_MOVW_PREL_G0_NC 288	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_PREL_G1	289	/* PC-rel. MOV{N,Z} imm. from 31:16. */
+#define R_AARCH64_MOVW_PREL_G1_NC 290	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_PREL_G2	291	/* PC-rel. MOV{N,Z} imm. from 47:32. */
+#define R_AARCH64_MOVW_PREL_G2_NC 292	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_PREL_G3	293	/* PC-rel. MOV{N,Z} imm. from 63:48. */
+#define R_AARCH64_LDST128_ABS_LO12_NC 299 /* Dir. ADD imm. from bits 11:4.  */
+#define R_AARCH64_MOVW_GOTOFF_G0 300	/* GOT-rel. off. MOV{N,Z} imm. 15:0. */
+#define R_AARCH64_MOVW_GOTOFF_G0_NC 301	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_GOTOFF_G1 302	/* GOT-rel. o. MOV{N,Z} imm. 31:16.  */
+#define R_AARCH64_MOVW_GOTOFF_G1_NC 303	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_GOTOFF_G2 304	/* GOT-rel. o. MOV{N,Z} imm. 47:32.  */
+#define R_AARCH64_MOVW_GOTOFF_G2_NC 305	/* Likewise for MOVK; no check.  */
+#define R_AARCH64_MOVW_GOTOFF_G3 306	/* GOT-rel. o. MOV{N,Z} imm. 63:48.  */
+#define R_AARCH64_GOTREL64	307	/* GOT-relative 64-bit.  */
+#define R_AARCH64_GOTREL32	308	/* GOT-relative 32-bit.  */
+#define R_AARCH64_GOT_LD_PREL19	309	/* PC-rel. GOT off. load imm. 20:2.  */
+#define R_AARCH64_LD64_GOTOFF_LO15 310	/* GOT-rel. off. LD/ST imm. 14:3.  */
+#define R_AARCH64_ADR_GOT_PAGE	311	/* P-page-rel. GOT off. ADRP 32:12.  */
+#define R_AARCH64_LD64_GOT_LO12_NC 312	/* Dir. GOT off. LD/ST imm. 11:3.  */
+#define R_AARCH64_LD64_GOTPAGE_LO15 313	/* GOT-page-rel. GOT off. LD/ST 14:3 */
+#define R_AARCH64_TLSGD_ADR_PREL21 512	/* PC-relative ADR imm. 20:0.  */
+#define R_AARCH64_TLSGD_ADR_PAGE21 513	/* page-rel. ADRP imm. 32:12.  */
+#define R_AARCH64_TLSGD_ADD_LO12_NC 514	/* direct ADD imm. from 11:0.  */
+#define R_AARCH64_TLSGD_MOVW_G1	515	/* GOT-rel. MOV{N,Z} 31:16.  */
+#define R_AARCH64_TLSGD_MOVW_G0_NC 516	/* GOT-rel. MOVK imm. 15:0.  */
+#define R_AARCH64_TLSLD_ADR_PREL21 517	/* Like 512; local dynamic model.  */
+#define R_AARCH64_TLSLD_ADR_PAGE21 518	/* Like 513; local dynamic model.  */
+#define R_AARCH64_TLSLD_ADD_LO12_NC 519	/* Like 514; local dynamic model.  */
+#define R_AARCH64_TLSLD_MOVW_G1	520	/* Like 515; local dynamic model.  */
+#define R_AARCH64_TLSLD_MOVW_G0_NC 521	/* Like 516; local dynamic model.  */
+#define R_AARCH64_TLSLD_LD_PREL19 522	/* TLS PC-rel. load imm. 20:2.  */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 /* TLS DTP-rel. MOV{N,Z} 47:32.  */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 /* TLS DTP-rel. MOV{N,Z} 31:16.  */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 /* Likewise; MOVK; no check.  */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 /* TLS DTP-rel. MOV{N,Z} 15:0.  */
+#define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 /* Likewise; MOVK; no check.  */
+#define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 /* DTP-rel. ADD imm. from 23:12. */
+#define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 /* DTP-rel. ADD imm. from 11:0.  */
+#define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 /* Likewise; no ovfl. check.  */
+#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 /* DTP-rel. LD/ST imm. 11:0.  */
+#define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 /* Likewise; no check.  */
+#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 /* DTP-rel. LD/ST imm. 11:1.  */
+#define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 /* Likewise; no check.  */
+#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 /* DTP-rel. LD/ST imm. 11:2.  */
+#define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 /* Likewise; no check.  */
+#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 /* DTP-rel. LD/ST imm. 11:3.  */
+#define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 /* Likewise; no check.  */
+#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 /* GOT-rel. MOV{N,Z} 31:16.  */
+#define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 /* GOT-rel. MOVK 15:0.  */
+#define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 /* Page-rel. ADRP 32:12.  */
+#define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 /* Direct LD off. 11:3.  */
+#define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 /* PC-rel. load imm. 20:2.  */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 /* TLS TP-rel. MOV{N,Z} 47:32.  */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G1 545 /* TLS TP-rel. MOV{N,Z} 31:16.  */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 /* Likewise; MOVK; no check.  */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G0 547 /* TLS TP-rel. MOV{N,Z} 15:0.  */
+#define R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 /* Likewise; MOVK; no check.  */
+#define R_AARCH64_TLSLE_ADD_TPREL_HI12 549 /* TP-rel. ADD imm. 23:12.  */
+#define R_AARCH64_TLSLE_ADD_TPREL_LO12 550 /* TP-rel. ADD imm. 11:0.  */
+#define R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 /* Likewise; no ovfl. check.  */
+#define R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 /* TP-rel. LD/ST off. 11:0.  */
+#define R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 /* Likewise; no ovfl. check. */
+#define R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 /* TP-rel. LD/ST off. 11:1.  */
+#define R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 /* Likewise; no check.  */
+#define R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 /* TP-rel. LD/ST off. 11:2.  */
+#define R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 /* Likewise; no check.  */
+#define R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 /* TP-rel. LD/ST off. 11:3.  */
+#define R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 /* Likewise; no check.  */
+#define R_AARCH64_TLSDESC_LD_PREL19 560	/* PC-rel. load immediate 20:2.  */
+#define R_AARCH64_TLSDESC_ADR_PREL21 561 /* PC-rel. ADR immediate 20:0.  */
+#define R_AARCH64_TLSDESC_ADR_PAGE21 562 /* Page-rel. ADRP imm. 32:12.  */
+#define R_AARCH64_TLSDESC_LD64_LO12 563	/* Direct LD off. from 11:3.  */
+#define R_AARCH64_TLSDESC_ADD_LO12 564	/* Direct ADD imm. from 11:0.  */
+#define R_AARCH64_TLSDESC_OFF_G1 565	/* GOT-rel. MOV{N,Z} imm. 31:16.  */
+#define R_AARCH64_TLSDESC_OFF_G0_NC 566	/* GOT-rel. MOVK imm. 15:0; no ck.  */
+#define R_AARCH64_TLSDESC_LDR	567	/* Relax LDR.  */
+#define R_AARCH64_TLSDESC_ADD	568	/* Relax ADD.  */
+#define R_AARCH64_TLSDESC_CALL	569	/* Relax BLR.  */
+#define R_AARCH64_TLSLE_LDST128_TPREL_LO12 570 /* TP-rel. LD/ST off. 11:4.  */
+#define R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC 571 /* Likewise; no check.  */
+#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12 572 /* DTP-rel. LD/ST imm. 11:4. */
+#define R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC 573 /* Likewise; no check.  */
+#define R_AARCH64_COPY         1024	/* Copy symbol at runtime.  */
+#define R_AARCH64_GLOB_DAT     1025	/* Create GOT entry.  */
+#define R_AARCH64_JUMP_SLOT    1026	/* Create PLT entry.  */
+#define R_AARCH64_RELATIVE     1027	/* Adjust by program base.  */
+#define R_AARCH64_TLS_DTPMOD   1028	/* Module number, 64 bit.  */
+#define R_AARCH64_TLS_DTPREL   1029	/* Module-relative offset, 64 bit.  */
+#define R_AARCH64_TLS_TPREL    1030	/* TP-relative offset, 64 bit.  */
+#define R_AARCH64_TLSDESC      1031	/* TLS Descriptor.  */
+#define R_AARCH64_IRELATIVE	1032	/* STT_GNU_IFUNC relocation.  */
+
+/* MTE memory tag segment type.  */
+#define PT_AARCH64_MEMTAG_MTE	(PT_LOPROC + 2)
+
+/* AArch64 specific values for the Dyn d_tag field.  */
+#define DT_AARCH64_BTI_PLT	(DT_LOPROC + 1)
+#define DT_AARCH64_PAC_PLT	(DT_LOPROC + 3)
+#define DT_AARCH64_VARIANT_PCS	(DT_LOPROC + 5)
+#define DT_AARCH64_NUM		6
+
+/* AArch64 specific values for the st_other field.  */
+#define STO_AARCH64_VARIANT_PCS 0x80
+
 /* ARM relocs.  */
 
 #define R_ARM_NONE		0	/* No reloc */
-#define R_ARM_PC24		1	/* PC relative 26 bit branch */
+#define R_ARM_PC24		1	/* Deprecated PC relative 26
+					   bit branch.  */
 #define R_ARM_ABS32		2	/* Direct 32 bit  */
 #define R_ARM_REL32		3	/* PC relative 32 bit */
 #define R_ARM_PC13		4
 #define R_ARM_ABS16		5	/* Direct 16 bit */
 #define R_ARM_ABS12		6	/* Direct 12 bit */
-#define R_ARM_THM_ABS5		7
+#define R_ARM_THM_ABS5		7	/* Direct & 0x7C (LDR, STR).  */
 #define R_ARM_ABS8		8	/* Direct 8 bit */
 #define R_ARM_SBREL32		9
-#define R_ARM_THM_PC22		10
-#define R_ARM_THM_PC8		11
+#define R_ARM_THM_PC22		10	/* PC relative 24 bit (Thumb32 BL).  */
+#define R_ARM_THM_PC8		11	/* PC relative & 0x3FC
+					   (Thumb16 LDR, ADD, ADR).  */
 #define R_ARM_AMP_VCALL9	12
 #define R_ARM_SWI24		13	/* Obsolete static relocation.  */
 #define R_ARM_TLS_DESC		13      /* Dynamic relocation.  */
-#define R_ARM_THM_SWI8		14
-#define R_ARM_XPC25		15
-#define R_ARM_THM_XPC22		16
+#define R_ARM_THM_SWI8		14	/* Reserved.  */
+#define R_ARM_XPC25		15	/* Reserved.  */
+#define R_ARM_THM_XPC22		16	/* Reserved.  */
 #define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
 #define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
 #define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
@@ -2320,21 +2955,109 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_ARM_GOTOFF		24	/* 32 bit offset to GOT */
 #define R_ARM_GOTPC		25	/* 32 bit PC relative offset to GOT */
 #define R_ARM_GOT32		26	/* 32 bit GOT entry */
-#define R_ARM_PLT32		27	/* 32 bit PLT address */
-#define R_ARM_ALU_PCREL_7_0	32
-#define R_ARM_ALU_PCREL_15_8	33
-#define R_ARM_ALU_PCREL_23_15	34
-#define R_ARM_LDR_SBREL_11_0	35
-#define R_ARM_ALU_SBREL_19_12	36
-#define R_ARM_ALU_SBREL_27_20	37
+#define R_ARM_PLT32		27	/* Deprecated, 32 bit PLT address.  */
+#define R_ARM_CALL		28	/* PC relative 24 bit (BL, BLX).  */
+#define R_ARM_JUMP24		29	/* PC relative 24 bit
+					   (B, BL<cond>).  */
+#define R_ARM_THM_JUMP24	30	/* PC relative 24 bit (Thumb32 B.W).  */
+#define R_ARM_BASE_ABS		31	/* Adjust by program base.  */
+#define R_ARM_ALU_PCREL_7_0	32	/* Obsolete.  */
+#define R_ARM_ALU_PCREL_15_8	33	/* Obsolete.  */
+#define R_ARM_ALU_PCREL_23_15	34	/* Obsolete.  */
+#define R_ARM_LDR_SBREL_11_0	35	/* Deprecated, prog. base relative.  */
+#define R_ARM_ALU_SBREL_19_12	36	/* Deprecated, prog. base relative.  */
+#define R_ARM_ALU_SBREL_27_20	37	/* Deprecated, prog. base relative.  */
+#define R_ARM_TARGET1		38
+#define R_ARM_SBREL31		39	/* Program base relative.  */
+#define R_ARM_V4BX		40
+#define R_ARM_TARGET2		41
+#define R_ARM_PREL31		42	/* 32 bit PC relative.  */
+#define R_ARM_MOVW_ABS_NC	43	/* Direct 16-bit (MOVW).  */
+#define R_ARM_MOVT_ABS		44	/* Direct high 16-bit (MOVT).  */
+#define R_ARM_MOVW_PREL_NC	45	/* PC relative 16-bit (MOVW).  */
+#define R_ARM_MOVT_PREL		46	/* PC relative (MOVT).  */
+#define R_ARM_THM_MOVW_ABS_NC	47	/* Direct 16 bit (Thumb32 MOVW).  */
+#define R_ARM_THM_MOVT_ABS	48	/* Direct high 16 bit
+					   (Thumb32 MOVT).  */
+#define R_ARM_THM_MOVW_PREL_NC	49	/* PC relative 16 bit
+					   (Thumb32 MOVW).  */
+#define R_ARM_THM_MOVT_PREL	50	/* PC relative high 16 bit
+					   (Thumb32 MOVT).  */
+#define R_ARM_THM_JUMP19	51	/* PC relative 20 bit
+					   (Thumb32 B<cond>.W).  */
+#define R_ARM_THM_JUMP6		52	/* PC relative X & 0x7E
+					   (Thumb16 CBZ, CBNZ).  */
+#define R_ARM_THM_ALU_PREL_11_0	53	/* PC relative 12 bit
+					   (Thumb32 ADR.W).  */
+#define R_ARM_THM_PC12		54	/* PC relative 12 bit
+					   (Thumb32 LDR{D,SB,H,SH}).  */
+#define R_ARM_ABS32_NOI		55	/* Direct 32-bit.  */
+#define R_ARM_REL32_NOI		56	/* PC relative 32-bit.  */
+#define R_ARM_ALU_PC_G0_NC	57	/* PC relative (ADD, SUB).  */
+#define R_ARM_ALU_PC_G0		58	/* PC relative (ADD, SUB).  */
+#define R_ARM_ALU_PC_G1_NC	59	/* PC relative (ADD, SUB).  */
+#define R_ARM_ALU_PC_G1		60	/* PC relative (ADD, SUB).  */
+#define R_ARM_ALU_PC_G2		61	/* PC relative (ADD, SUB).  */
+#define R_ARM_LDR_PC_G1		62	/* PC relative (LDR,STR,LDRB,STRB).  */
+#define R_ARM_LDR_PC_G2		63	/* PC relative (LDR,STR,LDRB,STRB).  */
+#define R_ARM_LDRS_PC_G0	64	/* PC relative (STR{D,H},
+					   LDR{D,SB,H,SH}).  */
+#define R_ARM_LDRS_PC_G1	65	/* PC relative (STR{D,H},
+					   LDR{D,SB,H,SH}).  */
+#define R_ARM_LDRS_PC_G2	66	/* PC relative (STR{D,H},
+					   LDR{D,SB,H,SH}).  */
+#define R_ARM_LDC_PC_G0		67	/* PC relative (LDC, STC).  */
+#define R_ARM_LDC_PC_G1		68	/* PC relative (LDC, STC).  */
+#define R_ARM_LDC_PC_G2		69	/* PC relative (LDC, STC).  */
+#define R_ARM_ALU_SB_G0_NC	70	/* Program base relative (ADD,SUB).  */
+#define R_ARM_ALU_SB_G0		71	/* Program base relative (ADD,SUB).  */
+#define R_ARM_ALU_SB_G1_NC	72	/* Program base relative (ADD,SUB).  */
+#define R_ARM_ALU_SB_G1		73	/* Program base relative (ADD,SUB).  */
+#define R_ARM_ALU_SB_G2		74	/* Program base relative (ADD,SUB).  */
+#define R_ARM_LDR_SB_G0		75	/* Program base relative (LDR,
+					   STR, LDRB, STRB).  */
+#define R_ARM_LDR_SB_G1		76	/* Program base relative
+					   (LDR, STR, LDRB, STRB).  */
+#define R_ARM_LDR_SB_G2		77	/* Program base relative
+					   (LDR, STR, LDRB, STRB).  */
+#define R_ARM_LDRS_SB_G0	78	/* Program base relative
+					   (LDR, STR, LDRB, STRB).  */
+#define R_ARM_LDRS_SB_G1	79	/* Program base relative
+					   (LDR, STR, LDRB, STRB).  */
+#define R_ARM_LDRS_SB_G2	80	/* Program base relative
+					   (LDR, STR, LDRB, STRB).  */
+#define R_ARM_LDC_SB_G0		81	/* Program base relative (LDC,STC).  */
+#define R_ARM_LDC_SB_G1		82	/* Program base relative (LDC,STC).  */
+#define R_ARM_LDC_SB_G2		83	/* Program base relative (LDC,STC).  */
+#define R_ARM_MOVW_BREL_NC	84	/* Program base relative 16
+					   bit (MOVW).  */
+#define R_ARM_MOVT_BREL		85	/* Program base relative high
+					   16 bit (MOVT).  */
+#define R_ARM_MOVW_BREL		86	/* Program base relative 16
+					   bit (MOVW).  */
+#define R_ARM_THM_MOVW_BREL_NC	87	/* Program base relative 16
+					   bit (Thumb32 MOVW).  */
+#define R_ARM_THM_MOVT_BREL	88	/* Program base relative high
+					   16 bit (Thumb32 MOVT).  */
+#define R_ARM_THM_MOVW_BREL	89	/* Program base relative 16
+					   bit (Thumb32 MOVW).  */
 #define R_ARM_TLS_GOTDESC	90
 #define R_ARM_TLS_CALL		91
-#define R_ARM_TLS_DESCSEQ	92
+#define R_ARM_TLS_DESCSEQ	92	/* TLS relaxation.  */
 #define R_ARM_THM_TLS_CALL	93
+#define R_ARM_PLT32_ABS		94
+#define R_ARM_GOT_ABS		95	/* GOT entry.  */
+#define R_ARM_GOT_PREL		96	/* PC relative GOT entry.  */
+#define R_ARM_GOT_BREL12	97	/* GOT entry relative to GOT
+					   origin (LDR).  */
+#define R_ARM_GOTOFF12		98	/* 12 bit, GOT entry relative
+					   to GOT origin (LDR, STR).  */
+#define R_ARM_GOTRELAX		99
 #define R_ARM_GNU_VTENTRY	100
 #define R_ARM_GNU_VTINHERIT	101
-#define R_ARM_THM_PC11		102	/* thumb unconditional branch */
-#define R_ARM_THM_PC9		103	/* thumb conditional branch */
+#define R_ARM_THM_PC11		102	/* PC relative & 0xFFE (Thumb16 B).  */
+#define R_ARM_THM_PC9		103	/* PC relative & 0x1FE
+					   (Thumb16 B/B<cond>).  */
 #define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic
 					   thread local data */
 #define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic
@@ -2345,7 +3068,18 @@ typedef Elf32_Addr Elf32_Conflict;
 					   static TLS block offset */
 #define R_ARM_TLS_LE32		108	/* 32 bit offset relative to static
 					   TLS block */
-#define	R_ARM_THM_TLS_DESCSEQ	129
+#define R_ARM_TLS_LDO12		109	/* 12 bit relative to TLS
+					   block (LDR, STR).  */
+#define R_ARM_TLS_LE12		110	/* 12 bit relative to static
+					   TLS block (LDR, STR).  */
+#define R_ARM_TLS_IE12GP	111	/* 12 bit GOT entry relative
+					   to GOT origin (LDR).  */
+#define R_ARM_ME_TOO		128	/* Obsolete.  */
+#define R_ARM_THM_TLS_DESCSEQ	129
+#define R_ARM_THM_TLS_DESCSEQ16	129
+#define R_ARM_THM_TLS_DESCSEQ32	130
+#define R_ARM_THM_GOT_BREL12	131	/* GOT entry relative to GOT
+					   origin, 12 bit (Thumb32 LDR).  */
 #define R_ARM_IRELATIVE		160
 #define R_ARM_RXPC25		249
 #define R_ARM_RSBREL32		250
@@ -2357,6 +3091,81 @@ typedef Elf32_Addr Elf32_Conflict;
 /* Keep this the last entry.  */
 #define R_ARM_NUM		256
 
+/* C-SKY */
+#define R_CKCORE_NONE               0	/* no reloc */
+#define R_CKCORE_ADDR32             1	/* direct 32 bit (S + A) */
+#define R_CKCORE_PCRELIMM8BY4       2	/* disp ((S + A - P) >> 2) & 0xff   */
+#define R_CKCORE_PCRELIMM11BY2      3	/* disp ((S + A - P) >> 1) & 0x7ff  */
+#define R_CKCORE_PCREL32            5	/* 32-bit rel (S + A - P)           */
+#define R_CKCORE_PCRELJSR_IMM11BY2  6	/* disp ((S + A - P) >>1) & 0x7ff   */
+#define R_CKCORE_RELATIVE           9	/* 32 bit adjust program base(B + A)*/
+#define R_CKCORE_COPY               10	/* 32 bit adjust by program base    */
+#define R_CKCORE_GLOB_DAT           11	/* off between got and sym (S)      */
+#define R_CKCORE_JUMP_SLOT          12	/* PLT entry (S) */
+#define R_CKCORE_GOTOFF             13	/* offset to GOT (S + A - GOT)      */
+#define R_CKCORE_GOTPC              14	/* PC offset to GOT (GOT + A - P)   */
+#define R_CKCORE_GOT32              15	/* 32 bit GOT entry (G) */
+#define R_CKCORE_PLT32              16	/* 32 bit PLT entry (G) */
+#define R_CKCORE_ADDRGOT            17	/* GOT entry in GLOB_DAT (GOT + G)  */
+#define R_CKCORE_ADDRPLT            18	/* PLT entry in GLOB_DAT (GOT + G)  */
+#define R_CKCORE_PCREL_IMM26BY2     19	/* ((S + A - P) >> 1) & 0x3ffffff   */
+#define R_CKCORE_PCREL_IMM16BY2     20	/* disp ((S + A - P) >> 1) & 0xffff */
+#define R_CKCORE_PCREL_IMM16BY4     21	/* disp ((S + A - P) >> 2) & 0xffff */
+#define R_CKCORE_PCREL_IMM10BY2     22	/* disp ((S + A - P) >> 1) & 0x3ff  */
+#define R_CKCORE_PCREL_IMM10BY4     23	/* disp ((S + A - P) >> 2) & 0x3ff  */
+#define R_CKCORE_ADDR_HI16          24	/* high & low 16 bit ADDR */
+                                        /* ((S + A) >> 16) & 0xffff */
+#define R_CKCORE_ADDR_LO16          25	/* (S + A) & 0xffff */
+#define R_CKCORE_GOTPC_HI16         26	/* high & low 16 bit GOTPC */
+                                        /* ((GOT + A - P) >> 16) & 0xffff */
+#define R_CKCORE_GOTPC_LO16         27	/* (GOT + A - P) & 0xffff */
+#define R_CKCORE_GOTOFF_HI16        28	/* high & low 16 bit GOTOFF */
+                                        /* ((S + A - GOT) >> 16) & 0xffff */
+#define R_CKCORE_GOTOFF_LO16        29	/* (S + A - GOT) & 0xffff */
+#define R_CKCORE_GOT12              30	/* 12 bit disp GOT entry (G) */
+#define R_CKCORE_GOT_HI16           31	/* high & low 16 bit GOT */
+                                        /* (G >> 16) & 0xffff */
+#define R_CKCORE_GOT_LO16           32	/* (G & 0xffff) */
+#define R_CKCORE_PLT12              33	/* 12 bit disp PLT entry (G) */
+#define R_CKCORE_PLT_HI16           34	/* high & low 16 bit PLT */
+                                        /* (G >> 16) & 0xffff */
+#define R_CKCORE_PLT_LO16           35	/* G & 0xffff */
+#define R_CKCORE_ADDRGOT_HI16       36	/* high & low 16 bit ADDRGOT */
+                                        /* (GOT + G * 4) & 0xffff */
+#define R_CKCORE_ADDRGOT_LO16       37	/* (GOT + G * 4) & 0xffff */
+#define R_CKCORE_ADDRPLT_HI16       38	/* high & low 16 bit ADDRPLT */
+                                        /* ((GOT + G * 4) >> 16) & 0xFFFF */
+#define R_CKCORE_ADDRPLT_LO16       39	/* (GOT+G*4) & 0xffff */
+#define R_CKCORE_PCREL_JSR_IMM26BY2 40	/* disp ((S+A-P) >>1) & x3ffffff */
+#define R_CKCORE_TOFFSET_LO16       41	/* (S+A-BTEXT) & 0xffff */
+#define R_CKCORE_DOFFSET_LO16       42	/* (S+A-BTEXT) & 0xffff */
+#define R_CKCORE_PCREL_IMM18BY2     43	/* disp ((S+A-P) >>1) & 0x3ffff */
+#define R_CKCORE_DOFFSET_IMM18      44	/* disp (S+A-BDATA) & 0x3ffff */
+#define R_CKCORE_DOFFSET_IMM18BY2   45	/* disp ((S+A-BDATA)>>1) & 0x3ffff */
+#define R_CKCORE_DOFFSET_IMM18BY4   46	/* disp ((S+A-BDATA)>>2) & 0x3ffff */
+#define R_CKCORE_GOT_IMM18BY4       48	/* disp (G >> 2) */
+#define R_CKCORE_PLT_IMM18BY4       49	/* disp (G >> 2) */
+#define R_CKCORE_PCREL_IMM7BY4      50	/* disp ((S+A-P) >>2) & 0x7f */
+#define R_CKCORE_TLS_LE32           51	/* 32 bit offset to TLS block */
+#define R_CKCORE_TLS_IE32           52
+#define R_CKCORE_TLS_GD32           53
+#define R_CKCORE_TLS_LDM32          54
+#define R_CKCORE_TLS_LDO32          55
+#define R_CKCORE_TLS_DTPMOD32       56
+#define R_CKCORE_TLS_DTPOFF32       57
+#define R_CKCORE_TLS_TPOFF32        58
+
+/* C-SKY elf header definition.  */
+#define EF_CSKY_ABIMASK		    0XF0000000
+#define EF_CSKY_OTHER		    0X0FFF0000
+#define EF_CSKY_PROCESSOR	    0X0000FFFF
+
+#define EF_CSKY_ABIV1		    0X10000000
+#define EF_CSKY_ABIV2		    0X20000000
+
+/* C-SKY attributes section.  */
+#define SHT_CSKY_ATTRIBUTES	    (SHT_LOPROC + 1)
+
 /* IA-64 specific declarations.  */
 
 /* Processor specific flags for the Ehdr e_flags field.  */
@@ -2701,8 +3510,18 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_X86_64_TLSDESC        36	/* TLS descriptor.  */
 #define R_X86_64_IRELATIVE	37	/* Adjust indirectly by program base */
 #define R_X86_64_RELATIVE64	38	/* 64-bit adjust by program base */
+					/* 39 Reserved was R_X86_64_PC32_BND */
+					/* 40 Reserved was R_X86_64_PLT32_BND */
+#define R_X86_64_GOTPCRELX	41	/* Load from 32 bit signed pc relative
+					   offset to GOT entry without REX
+					   prefix, relaxable.  */
+#define R_X86_64_REX_GOTPCRELX	42	/* Load from 32 bit signed pc relative
+					   offset to GOT entry with REX prefix,
+					   relaxable.  */
+#define R_X86_64_NUM		43
 
-#define R_X86_64_NUM		39
+/* x86-64 sh_type values.  */
+#define SHT_X86_64_UNWIND	0x70000001 /* Unwind information.  */
 
 
 /* AM33 relocations.  */
@@ -2730,8 +3549,23 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_MN10300_GLOB_DAT	21	/* Create GOT entry.  */
 #define R_MN10300_JMP_SLOT	22	/* Create PLT entry.  */
 #define R_MN10300_RELATIVE	23	/* Adjust by program base.  */
-
-#define R_MN10300_NUM		24
+#define R_MN10300_TLS_GD	24	/* 32-bit offset for global dynamic.  */
+#define R_MN10300_TLS_LD	25	/* 32-bit offset for local dynamic.  */
+#define R_MN10300_TLS_LDO	26	/* Module-relative offset.  */
+#define R_MN10300_TLS_GOTIE	27	/* GOT offset for static TLS block
+					   offset.  */
+#define R_MN10300_TLS_IE	28	/* GOT address for static TLS block
+					   offset.  */
+#define R_MN10300_TLS_LE	29	/* Offset relative to static TLS
+					   block.  */
+#define R_MN10300_TLS_DTPMOD	30	/* ID of module containing symbol.  */
+#define R_MN10300_TLS_DTPOFF	31	/* Offset in module TLS block.  */
+#define R_MN10300_TLS_TPOFF	32	/* Offset in static TLS block.  */
+#define R_MN10300_SYM_DIFF	33	/* Adjustment for next reloc as needed
+					   by linker relaxation.  */
+#define R_MN10300_ALIGN		34	/* Alignment requirement for linker
+					   relaxation.  */
+#define R_MN10300_NUM		35
 
 
 /* M32R relocs.  */
@@ -2789,6 +3623,89 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
 #define R_M32R_NUM		256	/* Keep this the last entry. */
 
+/* MicroBlaze relocations */
+#define R_MICROBLAZE_NONE		0	/* No reloc. */
+#define R_MICROBLAZE_32 		1	/* Direct 32 bit. */
+#define R_MICROBLAZE_32_PCREL		2	/* PC relative 32 bit. */
+#define R_MICROBLAZE_64_PCREL		3	/* PC relative 64 bit. */
+#define R_MICROBLAZE_32_PCREL_LO	4	/* Low 16 bits of PCREL32. */
+#define R_MICROBLAZE_64 		5	/* Direct 64 bit. */
+#define R_MICROBLAZE_32_LO		6	/* Low 16 bit. */
+#define R_MICROBLAZE_SRO32		7	/* Read-only small data area. */
+#define R_MICROBLAZE_SRW32		8	/* Read-write small data area. */
+#define R_MICROBLAZE_64_NONE		9	/* No reloc. */
+#define R_MICROBLAZE_32_SYM_OP_SYM	10	/* Symbol Op Symbol relocation. */
+#define R_MICROBLAZE_GNU_VTINHERIT	11	/* GNU C++ vtable hierarchy. */
+#define R_MICROBLAZE_GNU_VTENTRY	12	/* GNU C++ vtable member usage. */
+#define R_MICROBLAZE_GOTPC_64		13	/* PC-relative GOT offset.  */
+#define R_MICROBLAZE_GOT_64		14	/* GOT entry offset.  */
+#define R_MICROBLAZE_PLT_64		15	/* PLT offset (PC-relative).  */
+#define R_MICROBLAZE_REL		16	/* Adjust by program base.  */
+#define R_MICROBLAZE_JUMP_SLOT		17	/* Create PLT entry.  */
+#define R_MICROBLAZE_GLOB_DAT		18	/* Create GOT entry.  */
+#define R_MICROBLAZE_GOTOFF_64		19	/* 64 bit offset to GOT. */
+#define R_MICROBLAZE_GOTOFF_32		20	/* 32 bit offset to GOT. */
+#define R_MICROBLAZE_COPY		21	/* Runtime copy.  */
+#define R_MICROBLAZE_TLS		22	/* TLS Reloc. */
+#define R_MICROBLAZE_TLSGD		23	/* TLS General Dynamic. */
+#define R_MICROBLAZE_TLSLD		24	/* TLS Local Dynamic. */
+#define R_MICROBLAZE_TLSDTPMOD32	25	/* TLS Module ID. */
+#define R_MICROBLAZE_TLSDTPREL32	26	/* TLS Offset Within TLS Block. */
+#define R_MICROBLAZE_TLSDTPREL64	27	/* TLS Offset Within TLS Block. */
+#define R_MICROBLAZE_TLSGOTTPREL32	28	/* TLS Offset From Thread Pointer. */
+#define R_MICROBLAZE_TLSTPREL32 	29	/* TLS Offset From Thread Pointer. */
+
+/* Legal values for d_tag (dynamic entry type).  */
+#define DT_NIOS2_GP             0x70000002 /* Address of _gp.  */
+
+/* Nios II relocations.  */
+#define R_NIOS2_NONE		0	/* No reloc.  */
+#define R_NIOS2_S16		1	/* Direct signed 16 bit.  */
+#define R_NIOS2_U16		2	/* Direct unsigned 16 bit.  */
+#define R_NIOS2_PCREL16		3	/* PC relative 16 bit.  */
+#define R_NIOS2_CALL26		4	/* Direct call.  */
+#define R_NIOS2_IMM5		5	/* 5 bit constant expression.  */
+#define R_NIOS2_CACHE_OPX	6	/* 5 bit expression, shift 22.  */
+#define R_NIOS2_IMM6		7	/* 6 bit constant expression.  */
+#define R_NIOS2_IMM8		8	/* 8 bit constant expression.  */
+#define R_NIOS2_HI16		9	/* High 16 bit.  */
+#define R_NIOS2_LO16		10	/* Low 16 bit.  */
+#define R_NIOS2_HIADJ16		11	/* High 16 bit, adjusted.  */
+#define R_NIOS2_BFD_RELOC_32	12	/* 32 bit symbol value + addend.  */
+#define R_NIOS2_BFD_RELOC_16	13	/* 16 bit symbol value + addend.  */
+#define R_NIOS2_BFD_RELOC_8	14	/* 8 bit symbol value + addend.  */
+#define R_NIOS2_GPREL		15	/* 16 bit GP pointer offset.  */
+#define R_NIOS2_GNU_VTINHERIT	16	/* GNU C++ vtable hierarchy.  */
+#define R_NIOS2_GNU_VTENTRY	17	/* GNU C++ vtable member usage.  */
+#define R_NIOS2_UJMP		18	/* Unconditional branch.  */
+#define R_NIOS2_CJMP		19	/* Conditional branch.  */
+#define R_NIOS2_CALLR		20	/* Indirect call through register.  */
+#define R_NIOS2_ALIGN		21	/* Alignment requirement for
+					   linker relaxation.  */
+#define R_NIOS2_GOT16		22	/* 16 bit GOT entry.  */
+#define R_NIOS2_CALL16		23	/* 16 bit GOT entry for function.  */
+#define R_NIOS2_GOTOFF_LO	24	/* %lo of offset to GOT pointer.  */
+#define R_NIOS2_GOTOFF_HA	25	/* %hiadj of offset to GOT pointer.  */
+#define R_NIOS2_PCREL_LO	26	/* %lo of PC relative offset.  */
+#define R_NIOS2_PCREL_HA	27	/* %hiadj of PC relative offset.  */
+#define R_NIOS2_TLS_GD16	28	/* 16 bit GOT offset for TLS GD.  */
+#define R_NIOS2_TLS_LDM16	29	/* 16 bit GOT offset for TLS LDM.  */
+#define R_NIOS2_TLS_LDO16	30	/* 16 bit module relative offset.  */
+#define R_NIOS2_TLS_IE16	31	/* 16 bit GOT offset for TLS IE.  */
+#define R_NIOS2_TLS_LE16	32	/* 16 bit LE TP-relative offset.  */
+#define R_NIOS2_TLS_DTPMOD	33	/* Module number.  */
+#define R_NIOS2_TLS_DTPREL	34	/* Module-relative offset.  */
+#define R_NIOS2_TLS_TPREL	35	/* TP-relative offset.  */
+#define R_NIOS2_COPY		36	/* Copy symbol at runtime.  */
+#define R_NIOS2_GLOB_DAT	37	/* Create GOT entry.  */
+#define R_NIOS2_JUMP_SLOT	38	/* Create PLT entry.  */
+#define R_NIOS2_RELATIVE	39	/* Adjust by program base.  */
+#define R_NIOS2_GOTOFF		40	/* 16 bit offset to GOT pointer.  */
+#define R_NIOS2_CALL26_NOAT	41	/* Direct call in .noat section.  */
+#define R_NIOS2_GOT_LO		42	/* %lo() of GOT entry.  */
+#define R_NIOS2_GOT_HA		43	/* %hiadj() of GOT entry.  */
+#define R_NIOS2_CALL_LO		44	/* %lo() of function GOT entry.  */
+#define R_NIOS2_CALL_HA		45	/* %hiadj() of function GOT entry.  */
 
 /* TILEPro relocations.  */
 #define R_TILEPRO_NONE		0	/* No reloc */
@@ -2955,12 +3872,18 @@ typedef Elf32_Addr Elf32_Conflict;
 #define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */
 #define R_TILEGX_IMM16_X0_HW0_GOT 64	/* X0 pipe hword 0 GOT offset */
 #define R_TILEGX_IMM16_X1_HW0_GOT 65	/* X1 pipe hword 0 GOT offset */
-/* Relocs 66-71 are currently not defined.  */
+#define R_TILEGX_IMM16_X0_HW0_PLT_PCREL 66 /* X0 pipe PC-rel PLT hword 0 */
+#define R_TILEGX_IMM16_X1_HW0_PLT_PCREL 67 /* X1 pipe PC-rel PLT hword 0 */
+#define R_TILEGX_IMM16_X0_HW1_PLT_PCREL 68 /* X0 pipe PC-rel PLT hword 1 */
+#define R_TILEGX_IMM16_X1_HW1_PLT_PCREL 69 /* X1 pipe PC-rel PLT hword 1 */
+#define R_TILEGX_IMM16_X0_HW2_PLT_PCREL 70 /* X0 pipe PC-rel PLT hword 2 */
+#define R_TILEGX_IMM16_X1_HW2_PLT_PCREL 71 /* X1 pipe PC-rel PLT hword 2 */
 #define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */
 #define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */
 #define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */
 #define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */
-/* Relocs 76-77 are currently not defined.  */
+#define R_TILEGX_IMM16_X0_HW3_PLT_PCREL 76 /* X0 pipe PC-rel PLT hword 3 */
+#define R_TILEGX_IMM16_X1_HW3_PLT_PCREL 77 /* X1 pipe PC-rel PLT hword 3 */
 #define R_TILEGX_IMM16_X0_HW0_TLS_GD 78	/* X0 pipe hword 0 TLS GD offset */
 #define R_TILEGX_IMM16_X1_HW0_TLS_GD 79	/* X1 pipe hword 0 TLS GD offset */
 #define R_TILEGX_IMM16_X0_HW0_TLS_LE 80	/* X0 pipe hword 0 TLS LE offset */
@@ -2976,7 +3899,12 @@ typedef Elf32_Addr Elf32_Conflict;
 /* Relocs 90-91 are currently not defined.  */
 #define R_TILEGX_IMM16_X0_HW0_TLS_IE 92	/* X0 pipe hword 0 TLS IE offset */
 #define R_TILEGX_IMM16_X1_HW0_TLS_IE 93	/* X1 pipe hword 0 TLS IE offset */
-/* Relocs 94-99 are currently not defined.  */
+#define R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 94 /* X0 pipe PC-rel PLT last hword 0 */
+#define R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 95 /* X1 pipe PC-rel PLT last hword 0 */
+#define R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 96 /* X0 pipe PC-rel PLT last hword 1 */
+#define R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 97 /* X1 pipe PC-rel PLT last hword 1 */
+#define R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 98 /* X0 pipe PC-rel PLT last hword 2 */
+#define R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 99 /* X1 pipe PC-rel PLT last hword 2 */
 #define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */
 #define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */
 #define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */
@@ -3004,4 +3932,396 @@ typedef Elf32_Addr Elf32_Conflict;
 
 #define R_TILEGX_NUM		130
 
+/* RISC-V ELF Flags */
+#define EF_RISCV_RVC 			0x0001
+#define EF_RISCV_FLOAT_ABI 		0x0006
+#define EF_RISCV_FLOAT_ABI_SOFT 	0x0000
+#define EF_RISCV_FLOAT_ABI_SINGLE 	0x0002
+#define EF_RISCV_FLOAT_ABI_DOUBLE 	0x0004
+#define EF_RISCV_FLOAT_ABI_QUAD 	0x0006
+#define EF_RISCV_RVE			0x0008
+#define EF_RISCV_TSO			0x0010
+
+/* RISC-V relocations.  */
+#define R_RISCV_NONE		 0
+#define R_RISCV_32		 1
+#define R_RISCV_64		 2
+#define R_RISCV_RELATIVE	 3
+#define R_RISCV_COPY		 4
+#define R_RISCV_JUMP_SLOT	 5
+#define R_RISCV_TLS_DTPMOD32	 6
+#define R_RISCV_TLS_DTPMOD64	 7
+#define R_RISCV_TLS_DTPREL32	 8
+#define R_RISCV_TLS_DTPREL64	 9
+#define R_RISCV_TLS_TPREL32	10
+#define R_RISCV_TLS_TPREL64	11
+#define R_RISCV_BRANCH		16
+#define R_RISCV_JAL		17
+#define R_RISCV_CALL		18
+#define R_RISCV_CALL_PLT	19
+#define R_RISCV_GOT_HI20	20
+#define R_RISCV_TLS_GOT_HI20	21
+#define R_RISCV_TLS_GD_HI20	22
+#define R_RISCV_PCREL_HI20	23
+#define R_RISCV_PCREL_LO12_I	24
+#define R_RISCV_PCREL_LO12_S	25
+#define R_RISCV_HI20		26
+#define R_RISCV_LO12_I		27
+#define R_RISCV_LO12_S		28
+#define R_RISCV_TPREL_HI20	29
+#define R_RISCV_TPREL_LO12_I	30
+#define R_RISCV_TPREL_LO12_S	31
+#define R_RISCV_TPREL_ADD	32
+#define R_RISCV_ADD8		33
+#define R_RISCV_ADD16		34
+#define R_RISCV_ADD32		35
+#define R_RISCV_ADD64		36
+#define R_RISCV_SUB8		37
+#define R_RISCV_SUB16		38
+#define R_RISCV_SUB32		39
+#define R_RISCV_SUB64		40
+#define R_RISCV_GNU_VTINHERIT	41
+#define R_RISCV_GNU_VTENTRY	42
+#define R_RISCV_ALIGN		43
+#define R_RISCV_RVC_BRANCH	44
+#define R_RISCV_RVC_JUMP	45
+#define R_RISCV_RVC_LUI		46
+#define R_RISCV_GPREL_I		47
+#define R_RISCV_GPREL_S		48
+#define R_RISCV_TPREL_I		49
+#define R_RISCV_TPREL_S		50
+#define R_RISCV_RELAX		51
+#define R_RISCV_SUB6		52
+#define R_RISCV_SET6		53
+#define R_RISCV_SET8		54
+#define R_RISCV_SET16		55
+#define R_RISCV_SET32		56
+#define R_RISCV_32_PCREL	57
+#define R_RISCV_IRELATIVE	58
+
+#define R_RISCV_NUM		59
+
+/* RISC-V specific values for the st_other field.  */
+#define STO_RISCV_VARIANT_CC	0x80	/* Function uses variant calling
+					   convention */
+
+/* RISC-V specific values for the sh_type field.  */
+#define SHT_RISCV_ATTRIBUTES	(SHT_LOPROC + 3)
+
+/* RISC-V specific values for the p_type field.  */
+#define PT_RISCV_ATTRIBUTES	(PT_LOPROC + 3)
+
+/* RISC-V specific values for the d_tag field.  */
+#define DT_RISCV_VARIANT_CC	(DT_LOPROC + 1)
+
+/* BPF specific declarations.  */
+
+#define R_BPF_NONE		0	/* No reloc */
+#define R_BPF_64_64		1
+#define R_BPF_64_32		10
+
+/* Imagination Meta specific relocations. */
+
+#define R_METAG_HIADDR16	0
+#define R_METAG_LOADDR16	1
+#define R_METAG_ADDR32		2	/* 32bit absolute address */
+#define R_METAG_NONE		3	/* No reloc */
+#define R_METAG_RELBRANCH	4
+#define R_METAG_GETSETOFF	5
+
+/* Backward compatibility */
+#define R_METAG_REG32OP1	6
+#define R_METAG_REG32OP2	7
+#define R_METAG_REG32OP3	8
+#define R_METAG_REG16OP1	9
+#define R_METAG_REG16OP2	10
+#define R_METAG_REG16OP3	11
+#define R_METAG_REG32OP4	12
+
+#define R_METAG_HIOG		13
+#define R_METAG_LOOG		14
+
+#define R_METAG_REL8		15
+#define R_METAG_REL16		16
+
+/* GNU */
+#define R_METAG_GNU_VTINHERIT	30
+#define R_METAG_GNU_VTENTRY	31
+
+/* PIC relocations */
+#define R_METAG_HI16_GOTOFF	32
+#define R_METAG_LO16_GOTOFF	33
+#define R_METAG_GETSET_GOTOFF	34
+#define R_METAG_GETSET_GOT	35
+#define R_METAG_HI16_GOTPC	36
+#define R_METAG_LO16_GOTPC	37
+#define R_METAG_HI16_PLT	38
+#define R_METAG_LO16_PLT	39
+#define R_METAG_RELBRANCH_PLT	40
+#define R_METAG_GOTOFF		41
+#define R_METAG_PLT		42
+#define R_METAG_COPY		43
+#define R_METAG_JMP_SLOT	44
+#define R_METAG_RELATIVE	45
+#define R_METAG_GLOB_DAT	46
+
+/* TLS relocations */
+#define R_METAG_TLS_GD		47
+#define R_METAG_TLS_LDM		48
+#define R_METAG_TLS_LDO_HI16	49
+#define R_METAG_TLS_LDO_LO16	50
+#define R_METAG_TLS_LDO		51
+#define R_METAG_TLS_IE		52
+#define R_METAG_TLS_IENONPIC	53
+#define R_METAG_TLS_IENONPIC_HI16 54
+#define R_METAG_TLS_IENONPIC_LO16 55
+#define R_METAG_TLS_TPOFF	56
+#define R_METAG_TLS_DTPMOD	57
+#define R_METAG_TLS_DTPOFF	58
+#define R_METAG_TLS_LE		59
+#define R_METAG_TLS_LE_HI16	60
+#define R_METAG_TLS_LE_LO16	61
+
+/* NDS32 relocations.  */
+#define R_NDS32_NONE		0
+#define R_NDS32_32_RELA 	20
+#define R_NDS32_COPY		39
+#define R_NDS32_GLOB_DAT	40
+#define R_NDS32_JMP_SLOT	41
+#define R_NDS32_RELATIVE	42
+#define R_NDS32_TLS_TPOFF	102
+#define R_NDS32_TLS_DESC	119
+
+/* LoongArch ELF Flags */
+#define EF_LARCH_ABI_MODIFIER_MASK  0x07
+#define EF_LARCH_ABI_SOFT_FLOAT     0x01
+#define EF_LARCH_ABI_SINGLE_FLOAT   0x02
+#define EF_LARCH_ABI_DOUBLE_FLOAT   0x03
+#define EF_LARCH_OBJABI_V1          0x40
+
+/* LoongArch specific dynamic relocations */
+#define R_LARCH_NONE		0
+#define R_LARCH_32		1
+#define R_LARCH_64		2
+#define R_LARCH_RELATIVE	3
+#define R_LARCH_COPY		4
+#define R_LARCH_JUMP_SLOT	5
+#define R_LARCH_TLS_DTPMOD32	6
+#define R_LARCH_TLS_DTPMOD64	7
+#define R_LARCH_TLS_DTPREL32	8
+#define R_LARCH_TLS_DTPREL64	9
+#define R_LARCH_TLS_TPREL32	10
+#define R_LARCH_TLS_TPREL64	11
+#define R_LARCH_IRELATIVE	12
+
+/* Reserved for future relocs that the dynamic linker must understand.  */
+
+/* used by the static linker for relocating .text.  */
+#define R_LARCH_MARK_LA  20
+#define R_LARCH_MARK_PCREL  21
+#define R_LARCH_SOP_PUSH_PCREL  22
+#define R_LARCH_SOP_PUSH_ABSOLUTE  23
+#define R_LARCH_SOP_PUSH_DUP  24
+#define R_LARCH_SOP_PUSH_GPREL  25
+#define R_LARCH_SOP_PUSH_TLS_TPREL  26
+#define R_LARCH_SOP_PUSH_TLS_GOT  27
+#define R_LARCH_SOP_PUSH_TLS_GD  28
+#define R_LARCH_SOP_PUSH_PLT_PCREL  29
+#define R_LARCH_SOP_ASSERT  30
+#define R_LARCH_SOP_NOT  31
+#define R_LARCH_SOP_SUB  32
+#define R_LARCH_SOP_SL  33
+#define R_LARCH_SOP_SR  34
+#define R_LARCH_SOP_ADD  35
+#define R_LARCH_SOP_AND  36
+#define R_LARCH_SOP_IF_ELSE  37
+#define R_LARCH_SOP_POP_32_S_10_5  38
+#define R_LARCH_SOP_POP_32_U_10_12  39
+#define R_LARCH_SOP_POP_32_S_10_12  40
+#define R_LARCH_SOP_POP_32_S_10_16  41
+#define R_LARCH_SOP_POP_32_S_10_16_S2  42
+#define R_LARCH_SOP_POP_32_S_5_20  43
+#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2  44
+#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2  45
+#define R_LARCH_SOP_POP_32_U  46
+
+/* used by the static linker for relocating non .text.  */
+#define R_LARCH_ADD8  47
+#define R_LARCH_ADD16  48
+#define R_LARCH_ADD24  49
+#define R_LARCH_ADD32  50
+#define R_LARCH_ADD64  51
+#define R_LARCH_SUB8  52
+#define R_LARCH_SUB16  53
+#define R_LARCH_SUB24  54
+#define R_LARCH_SUB32  55
+#define R_LARCH_SUB64  56
+#define R_LARCH_GNU_VTINHERIT  57
+#define R_LARCH_GNU_VTENTRY  58
+
+/* reserved 59-63 */
+
+#define R_LARCH_B16 64
+#define R_LARCH_B21 65
+#define R_LARCH_B26 66
+#define R_LARCH_ABS_HI20 67
+#define R_LARCH_ABS_LO12 68
+#define R_LARCH_ABS64_LO20 69
+#define R_LARCH_ABS64_HI12 70
+#define R_LARCH_PCALA_HI20 71
+#define R_LARCH_PCALA_LO12 72
+#define R_LARCH_PCALA64_LO20 73
+#define R_LARCH_PCALA64_HI12 74
+#define R_LARCH_GOT_PC_HI20 75
+#define R_LARCH_GOT_PC_LO12 76
+#define R_LARCH_GOT64_PC_LO20 77
+#define R_LARCH_GOT64_PC_HI12 78
+#define R_LARCH_GOT_HI20 79
+#define R_LARCH_GOT_LO12 80
+#define R_LARCH_GOT64_LO20 81
+#define R_LARCH_GOT64_HI12 82
+#define R_LARCH_TLS_LE_HI20 83
+#define R_LARCH_TLS_LE_LO12 84
+#define R_LARCH_TLS_LE64_LO20 85
+#define R_LARCH_TLS_LE64_HI12 86
+#define R_LARCH_TLS_IE_PC_HI20 87
+#define R_LARCH_TLS_IE_PC_LO12 88
+#define R_LARCH_TLS_IE64_PC_LO20 89
+#define R_LARCH_TLS_IE64_PC_HI12 90
+#define R_LARCH_TLS_IE_HI20 91
+#define R_LARCH_TLS_IE_LO12 92
+#define R_LARCH_TLS_IE64_LO20 93
+#define R_LARCH_TLS_IE64_HI12 94
+#define R_LARCH_TLS_LD_PC_HI20 95
+#define R_LARCH_TLS_LD_HI20 96
+#define R_LARCH_TLS_GD_PC_HI20 97
+#define R_LARCH_TLS_GD_HI20 98
+#define R_LARCH_32_PCREL 99
+#define R_LARCH_RELAX 100
+
+/* ARC specific declarations.  */
+
+/* Processor specific flags for the Ehdr e_flags field.  */
+#define EF_ARC_MACH_MSK	    0x000000ff
+#define EF_ARC_OSABI_MSK    0x00000f00
+#define EF_ARC_ALL_MSK	    (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK)
+
+/* Processor specific values for the Shdr sh_type field.  */
+#define SHT_ARC_ATTRIBUTES	(SHT_LOPROC + 1) /* ARC attributes section.  */
+
+/* ARCompact/ARCv2 specific relocs.  */
+#define R_ARC_NONE		0x0
+#define R_ARC_8			0x1
+#define R_ARC_16		0x2
+#define R_ARC_24		0x3
+#define R_ARC_32		0x4
+
+#define R_ARC_B22_PCREL		0x6
+#define R_ARC_H30		0x7
+#define R_ARC_N8		0x8
+#define R_ARC_N16		0x9
+#define R_ARC_N24		0xA
+#define R_ARC_N32		0xB
+#define R_ARC_SDA		0xC
+#define R_ARC_SECTOFF		0xD
+#define R_ARC_S21H_PCREL	0xE
+#define R_ARC_S21W_PCREL	0xF
+#define R_ARC_S25H_PCREL	0x10
+#define R_ARC_S25W_PCREL	0x11
+#define R_ARC_SDA32		0x12
+#define R_ARC_SDA_LDST		0x13
+#define R_ARC_SDA_LDST1		0x14
+#define R_ARC_SDA_LDST2		0x15
+#define R_ARC_SDA16_LD		0x16
+#define R_ARC_SDA16_LD1		0x17
+#define R_ARC_SDA16_LD2		0x18
+#define R_ARC_S13_PCREL		0x19
+#define R_ARC_W			0x1A
+#define R_ARC_32_ME		0x1B
+#define R_ARC_N32_ME		0x1C
+#define R_ARC_SECTOFF_ME	0x1D
+#define R_ARC_SDA32_ME		0x1E
+#define R_ARC_W_ME		0x1F
+#define R_ARC_H30_ME		0x20
+#define R_ARC_SECTOFF_U8	0x21
+#define R_ARC_SECTOFF_S9	0x22
+#define R_AC_SECTOFF_U8		0x23
+#define R_AC_SECTOFF_U8_1	0x24
+#define R_AC_SECTOFF_U8_2	0x25
+#define R_AC_SECTOFF_S9		0x26
+#define R_AC_SECTOFF_S9_1	0x27
+#define R_AC_SECTOFF_S9_2	0x28
+#define R_ARC_SECTOFF_ME_1	0x29
+#define R_ARC_SECTOFF_ME_2	0x2A
+#define R_ARC_SECTOFF_1		0x2B
+#define R_ARC_SECTOFF_2		0x2C
+#define R_ARC_SDA_12		0x2D
+#define R_ARC_SDA16_ST2		0x30
+#define R_ARC_32_PCREL		0x31
+#define R_ARC_PC32		0x32
+#define R_ARC_GOTPC32		0x33
+#define R_ARC_PLT32		0x34
+#define R_ARC_COPY		0x35
+#define R_ARC_GLOB_DAT		0x36
+#define R_ARC_JMP_SLOT		0x37
+#define R_ARC_RELATIVE		0x38
+#define R_ARC_GOTOFF		0x39
+#define R_ARC_GOTPC		0x3A
+#define R_ARC_GOT32		0x3B
+#define R_ARC_S21W_PCREL_PLT	0x3C
+#define R_ARC_S25H_PCREL_PLT	0x3D
+
+#define R_ARC_JLI_SECTOFF	0x3F
+
+#define R_ARC_TLS_DTPMOD	0x42
+#define R_ARC_TLS_DTPOFF	0x43
+#define R_ARC_TLS_TPOFF		0x44
+#define R_ARC_TLS_GD_GOT	0x45
+#define R_ARC_TLS_GD_LD	        0x46
+#define R_ARC_TLS_GD_CALL	0x47
+#define R_ARC_TLS_IE_GOT	0x48
+#define R_ARC_TLS_DTPOFF_S9	0x49
+#define R_ARC_TLS_LE_S9		0x4A
+#define R_ARC_TLS_LE_32		0x4B
+#define R_ARC_S25W_PCREL_PLT	0x4C
+#define R_ARC_S21H_PCREL_PLT	0x4D
+#define R_ARC_NPS_CMEM16	0x4E
+
+/* OpenRISC 1000 specific relocs.  */
+#define R_OR1K_NONE		0
+#define R_OR1K_32		1
+#define R_OR1K_16		2
+#define R_OR1K_8		3
+#define R_OR1K_LO_16_IN_INSN	4
+#define R_OR1K_HI_16_IN_INSN	5
+#define R_OR1K_INSN_REL_26	6
+#define R_OR1K_GNU_VTENTRY	7
+#define R_OR1K_GNU_VTINHERIT	8
+#define R_OR1K_32_PCREL		9
+#define R_OR1K_16_PCREL		10
+#define R_OR1K_8_PCREL		11
+#define R_OR1K_GOTPC_HI16	12
+#define R_OR1K_GOTPC_LO16	13
+#define R_OR1K_GOT16		14
+#define R_OR1K_PLT26		15
+#define R_OR1K_GOTOFF_HI16	16
+#define R_OR1K_GOTOFF_LO16	17
+#define R_OR1K_COPY		18
+#define R_OR1K_GLOB_DAT		19
+#define R_OR1K_JMP_SLOT		20
+#define R_OR1K_RELATIVE		21
+#define R_OR1K_TLS_GD_HI16	22
+#define R_OR1K_TLS_GD_LO16	23
+#define R_OR1K_TLS_LDM_HI16	24
+#define R_OR1K_TLS_LDM_LO16	25
+#define R_OR1K_TLS_LDO_HI16	26
+#define R_OR1K_TLS_LDO_LO16	27
+#define R_OR1K_TLS_IE_HI16	28
+#define R_OR1K_TLS_IE_LO16	29
+#define R_OR1K_TLS_LE_HI16	30
+#define R_OR1K_TLS_LE_LO16	31
+#define R_OR1K_TLS_TPOFF	32
+#define R_OR1K_TLS_DTPOFF	33
+#define R_OR1K_TLS_DTPMOD	34
+
 #endif	/* elf.h */
diff --git a/tools/util-linux/Makefile b/tools/util-linux/Makefile
new file mode 100644
index 00000000000000..acd819e38b78b2
--- /dev/null
+++ b/tools/util-linux/Makefile
@@ -0,0 +1,132 @@
+#
+# Copyright (C) 2006-2015 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=util-linux
+PKG_VERSION:=2.39.3
+
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
+PKG_SOURCE_URL:=@KERNEL/linux/utils/$(PKG_NAME)/v2.39
+PKG_HASH:=7b6605e48d1a49f43cc4b4cfc59f313d0dd5402fa40b96810bd572e167dfed0f
+PKG_CPE_ID:=cpe:/a:kernel:util-linux
+
+HOST_BUILD_PARALLEL:=1
+
+include $(INCLUDE_DIR)/host-build.mk
+
+HOST_CONFIGURE_ARGS += \
+	--disable-poman \
+	--disable-nls \
+	--disable-asciidoc \
+	--disable-poman \
+	--disable-libuuid \
+	--disable-libblkid \
+	--disable-libmount \
+	--disable-libsmartcols \
+	--disable-libfdisk \
+	--disable-fdisks \
+	--disable-mount \
+	--disable-losetup \
+	--disable-zramctl \
+	--disable-fsck \
+	--disable-partx \
+	--disable-uuidd \
+	--disable-uuidgen \
+	--disable-blkid \
+	--disable-wipefs \
+	--disable-mountpoint \
+	--disable-fallocate \
+	--disable-unshare \
+	--disable-nsenter \
+	--disable-setpriv \
+	--disable-hardlink \
+	--disable-eject \
+	--disable-agetty \
+	--disable-cramfs \
+	--disable-bfs \
+	--disable-minix \
+	--disable-hwclock \
+	--disable-mkfs \
+	--disable-fstrim \
+	--disable-swapon \
+	--disable-lscpu \
+	--disable-lsfd \
+	--disable-lslogins \
+	--disable-wdctl \
+	--disable-cal \
+	--disable-logger \
+	--disable-whereis \
+	--disable-pipesz \
+	--disable-waitpid \
+	--disable-switch_root \
+	--disable-pivot_root \
+	--disable-lsmem \
+	--disable-chmem \
+	--disable-ipcmk \
+	--disable-ipcrm \
+	--disable-ipcs \
+	--disable-irqtop \
+	--disable-lsirq \
+	--disable-lsns \
+	--disable-rfkill \
+	--disable-scriptutils \
+	--disable-tunelp \
+	--disable-kill \
+	--disable-last \
+	--disable-utmpdump \
+	--disable-line \
+	--disable-mesg \
+	--disable-raw \
+	--disable-rename \
+	--disable-vipw \
+	--disable-newgrp \
+	--disable-chfn-chsh \
+	--disable-login \
+	--disable-nologin \
+	--disable-sulogin \
+	--disable-su \
+	--disable-runuser \
+	--disable-ul \
+	--disable-more \
+	--disable-pg \
+	--disable-setterm \
+	--disable-schedutils \
+	--disable-wall \
+	--disable-write \
+	--disable-bash-completion \
+	--disable-pylibmount \
+	--disable-pg-bell \
+	--without-util \
+	--without-selinux \
+	--without-audit \
+	--without-udev \
+	--without-ncursesw \
+	--without-ncurses \
+	--without-slang \
+	--without-tinfo \
+	--without-readline \
+	--without-utempter \
+	--without-cap-ng \
+	--without-libz \
+	--without-libmagic \
+	--without-user \
+	--without-btrfs \
+	--without-systemd \
+	--without-smack \
+	--without-econf \
+	--without-python \
+	--without-cryptsetup
+
+define Host/Install
+	$(INSTALL_BIN) $(HOST_BUILD_DIR)/hexdump $(STAGING_DIR_HOST)/bin/
+endef
+
+define Host/Uninstall
+	rm -f $(STAGING_DIR_HOST)/bin/hexdump
+endef
+
+$(eval $(call HostBuild))
diff --git a/tools/zstd/Makefile b/tools/zstd/Makefile
index ea0f823e11da53..4d46a5f9505597 100644
--- a/tools/zstd/Makefile
+++ b/tools/zstd/Makefile
@@ -1,11 +1,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=zstd
-PKG_VERSION:=1.5.4
+PKG_VERSION:=1.5.5
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://github.com/facebook/zstd/releases/download/v$(PKG_VERSION)
-PKG_HASH:=0f470992aedad543126d06efab344dc5f3e171893810455787d38347343a4424
+PKG_HASH:=9c4396cc829cfae319a6e2615202e82aad41372073482fce286fac78646d3ee4
 
 PKG_LICENSE:=BSD-3-Clause
 PKG_LICENSE_FILES:=LICENSE