Mux or ProbeExpr of View doesn't work

[dtzSiFive]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Consider these tests (drop in DataView.scala test):

• Mux :

  it should "handle mux of bundle view" in {
    import SimpleBundleDataView._
    class MyModule extends Module {
      val cond = IO(Input(Bool()))
      val in1 = IO(Input(new BundleA(8)))
      val in2 = IO(Input(new BundleA(8)))
      val out = IO(Output(new BundleB(8)))

      out := Mux(cond, in1.viewAs[BundleB], in2.viewAs[BundleB])
    }
    val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
    chirrtl should include("asdf")
  }

  it should "handle view of mux of bundle" in {
    import SimpleBundleDataView._
    class MyModule extends Module {
      val cond = IO(Input(Bool()))
      val in1 = IO(Input(new BundleA(8)))
      val in2 = IO(Input(new BundleA(8)))
      val out = IO(Output(new BundleB(8)))

      out := Mux(cond, in1, in2).viewAs[BundleB]
    }
    val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
    chirrtl should include("asdf")
  }

• Probe:

  it should "handle Probe of view, member" in {
    import SimpleBundleDataView._
    class MyModule extends Module {
      val in = IO(Input(new BundleA(8)))
      val out_probe = IO(Output(Probe(UInt(8.W))))
      val view = in.viewAs[BundleB]
      define(out_probe, ProbeValue(view.bar))
    }
    val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
    chirrtl should include("define out_probe = probe(in.foo)")
    ChiselStage.emitSystemVerilog(new MyModule)
  }

  it should "handle Probe of view, bundle" in {
    import SimpleBundleDataView._
    class MyModule extends Module {
      val in = IO(Input(new BundleA(8)))
      val out_probe = IO(Output(Probe(new BundleB(8))))
      val view = in.viewAs[BundleB]
      define(out_probe, ProbeValue(view))
    }
    val chirrtl = ChiselStage.emitCHIRRTL(new MyModule)
    chirrtl should include("define out_probe = probe(in)")
  }

What is the current behavior?

Mux:
The latter works, but the former does not, producing an error instead.

Probe:
Former works (member of view), but latter does not.

What is the expected behavior?

Ability to use view refs in expressions.

Other Information

Mux Error:

[info] - should handle mux of bundle view *** FAILED ***
[info]   chisel3.package$ChiselException: Internal Error: In .ref for MyModule.in1: IO[BundleB] got 'Some(AggregateViewBinding(Map(MyModule.in1.foo: IO[UInt<8>] -> MyModule.in1.foo: IO[UInt<8>], MyModule.in1: IO[BundleB] -> MyModule.in1: IO[BundleA])))' and 'Some(MyModule.in1: IO[BundleA])'
[info]   at ... ()
[info]   at chiselTests.experimental.DataViewSpec$MyModule$41.$anonfun$new$187(DataView.scala:945)
[info]   at chisel3.Data.$anonfun$$colon$eq$1(Data.scala:736)
[info]   at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.scala:18)
[info]   at chisel3.experimental.prefix$.apply(prefix.scala:33)
[info]   at chisel3.Data.$colon$eq(Data.scala:736)
[info]   at chiselTests.experimental.DataViewSpec$MyModule$41.<init>(DataView.scala:945)
[info]   at chiselTests.experimental.DataViewSpec.$anonfun$new$188(DataView.scala:947)
[info]   at chisel3.Module$.evaluate(Module.scala:92)
[info]   at chisel3.Module$.do_apply(Module.scala:35)
[info]   at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:53)
[info]   at chisel3.internal.Builder$.$anonfun$buildImpl$1(Builder.scala:1025)
[info]   at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
[info]   at chisel3.internal.Builder$.buildImpl(Builder.scala:1019)
[info]   at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:1011)
[info]   at logger.Logger$.$anonfun$makeScope$4(Logger.scala:148)
[info]   at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
[info]   at logger.Logger$.makeScope(Logger.scala:146)
[info]   at logger.Logger$.makeScope(Logger.scala:133)
[info]   at ... ()
[info]   at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)

Probe test error:

[info] - should handle Probe of view, bundle *** FAILED ***
[info]   chisel3.package$ChiselException: Internal Error: In .ref for MyModule.in: IO[BundleB] got 'Some(AggregateViewBinding(Map(MyModule.in.foo: IO[UInt<8>] -> MyModule.in.foo: IO[UInt<8>], MyModule.in: IO[BundleB] -> MyModule.in: IO[BundleA])))' and 'Some(MyModule.in: IO[BundleA])'
[info]   at ... ()
[info]   at chiselTests.experimental.DataViewSpec$MyModule$39.<init>(DataView.scala:909)
[info]   at chiselTests.experimental.DataViewSpec.$anonfun$new$183(DataView.scala:911)
[info]   at chisel3.Module$.evaluate(Module.scala:92)
[info]   at chisel3.Module$.do_apply(Module.scala:35)
[info]   at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:53)
[info]   at chisel3.internal.Builder$.$anonfun$buildImpl$1(Builder.scala:1025)
[info]   at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
[info]   at chisel3.internal.Builder$.buildImpl(Builder.scala:1019)
[info]   at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:1011)
[info]   at logger.Logger$.$anonfun$makeScope$4(Logger.scala:148)
[info]   at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
[info]   at logger.Logger$.makeScope(Logger.scala:146)
[info]   at logger.Logger$.makeScope(Logger.scala:133)
[info]   at ... ()
[info]   at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)

What is the use case for changing the behavior?