From ade38c17b86d9723fad16216807f787b95a1632e Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Fri, 16 Feb 2024 13:20:52 -0800 Subject: [PATCH] Make `SRAMInterface` parameters publicly available (#3826) (cherry picked from commit 8f0196fa813464f9903d2f8f7ffea1982ef0ca54) --- src/main/scala/chisel3/util/SRAM.scala | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index edcfb679971..e8e4a291350 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -81,13 +81,18 @@ class MemoryReadWritePort[T <: Data] private[chisel3] (tpe: T, addrWidth: Int, m * @param numReadwritePorts The number of read/write ports */ class SRAMInterface[T <: Data]( - memSize: BigInt, - tpe: T, - numReadPorts: Int, - numWritePorts: Int, - numReadwritePorts: Int, - masked: Boolean = false) + val memSize: BigInt, + // tpe can't be directly made public as it will become a Bundle field + tpe: T, + val numReadPorts: Int, + val numWritePorts: Int, + val numReadwritePorts: Int, + val masked: Boolean = false) extends Bundle { + + /** Public accessor for data type of this interface. */ + def dataType: T = tpe + if (masked) { require( tpe.isInstanceOf[Vec[_]],