From 53efa00ac99d81336df227536bcf674252b17c8a Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Mon, 17 Aug 2020 16:44:47 -0700 Subject: [PATCH] Update to Chisel 3.4.0-RC1+ and FIRRTL 1.4.0-RC1+ Use sbt-sriracha for fully SBT-managed source dependencies. They are also toggleable via JVM System Properties: sbt.sourcemode and sbt.workspace Update Makefiles and build rocketchip fat jar --- .gitignore | 1 + .sbtopts | 2 + Makefrag | 53 ++++++++----------- build.sbt | 35 +++++++----- chisel3 | 2 +- emulator/Makefrag-verilator | 6 +-- firrtl | 2 +- project/build.properties | 2 +- project/plugins.sbt | 9 +++- .../stage/phases/GenerateFirrtlAnnos.scala | 20 +++---- vsim/Makefrag-verilog | 6 +-- wit-manifest.json | 4 +- 12 files changed, 73 insertions(+), 69 deletions(-) create mode 100644 .sbtopts diff --git a/.gitignore b/.gitignore index 9d6915d8a58..bf819ca2264 100644 --- a/.gitignore +++ b/.gitignore @@ -5,3 +5,4 @@ project/target .addons-dont-touch /lib/ /test_lib/ +rocketchip.jar diff --git a/.sbtopts b/.sbtopts new file mode 100644 index 00000000000..e6cc065089b --- /dev/null +++ b/.sbtopts @@ -0,0 +1,2 @@ +-Dsbt.sourcemode=true +-Dsbt.workspace=$PWD diff --git a/Makefrag b/Makefrag index f8fdc0bf381..8e4fd372f7c 100644 --- a/Makefrag +++ b/Makefrag @@ -25,46 +25,37 @@ EMPTY := SPACE := $(EMPTY) $(EMPTY) COMMA := , -SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -jar $(base_dir)/sbt-launch.jar +# Running with sbt-launch.jar doesn't read .sbtopts by default +# Set if the file exists (if it exists, we're building chisel3 and firrtl from source) +sbtopts_file := $(base_dir)/.sbtopts +ifneq (,$(wildcard $(sbtopts_file))) + SBT_OPTS ?= $(shell cat $(sbtopts_file)) +endif +SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -jar $(base_dir)/sbt-launch.jar SHELL := /bin/bash FIRRTL_TRANSFORMS := \ firrtl.passes.InlineInstances \ -ROCKET_CLASS_DIRS ?= \ - $(base_dir)/target/scala-2.12/classes \ - $(base_dir)/chisel3/target/scala-2.12/classes \ - $(base_dir)/chisel3/core/target/scala-2.12/classes \ - $(base_dir)/chisel3/macros/target/scala-2.12/classes - -ROCKET_CLASSES ?= $(subst $(SPACE),:,$(ROCKET_CLASS_DIRS)) -FIRRTL_JAR ?= $(base_dir)/firrtl/utils/bin/firrtl.jar FIRRTL_TEST_JAR ?= $(base_dir)/firrtl/utils/bin/firrtl-test.jar -FIRRTL ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -cp "$(FIRRTL_JAR)":"$(ROCKET_CLASSES)" firrtl.Driver - -# Build firrtl.jar and put it where chisel3 can find it. -$(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala") - $(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala - cd $(base_dir)/firrtl && $(SBT) "Test / assembly" - touch $(FIRRTL_JAR) - mkdir -p $(base_dir)/lib - cp -p $(FIRRTL_JAR) $(base_dir)/lib - - mkdir -p $(base_dir)/test_lib - cp -p $(FIRRTL_JAR) $(base_dir)/test_lib - cp -p $(FIRRTL_TEST_JAR) $(base_dir)/test_lib -# When chisel3 pr 448 is merged, the following extraneous copy may be removed. - mkdir -p $(base_dir)/chisel3/lib - cp -p $(FIRRTL_JAR) $(base_dir)/chisel3/lib - -src_path := src/main/scala + +JAVA ?= java -Xmx$(JVM_MEMORY) -Xss8M +FIRRTL ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) firrtl.stage.FirrtlMain +GENERATOR ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) $(PROJECT).Generator + +# Extracting this information from SBT would be more robust +# api-config-chipsalliance does not use standard SBT src/main/scala, but has no resources +scala_srcs := $(shell find $(base_dir) -name "*.scala" -o -name "*.sbt") +resources := $(shell find $(base_dir) -type f -path "*/src/main/resources/*") +all_srcs := $(scala_srcs) $(resources) + +ROCKET_CHIP_JAR := $(base_dir)/rocketchip.jar +$(ROCKET_CHIP_JAR): $(all_srcs) + cd $(base_dir) && $(SBT) $(SBT_OPTS) assembly + resources := $(base_dir)/src/main/resources csrc := $(resources)/csrc vsrc := $(resources)/vsrc -default_submodules := . hardfloat chisel3 -default_submodule_src_paths := $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(base_dir)/$(submodule)/$(src_path)) -other_src_paths := $(base_dir)/api-config-chipsalliance/design/craft/src -chisel_srcs := $(foreach path,$(default_submodule_src_paths) $(other_src_paths),$(shell find $(path) -name "*.scala")) disasm := 2> which_disasm := $(shell which spike-dasm 2> /dev/null) diff --git a/build.sbt b/build.sbt index 0b6a15d44d7..a4e3f169612 100644 --- a/build.sbt +++ b/build.sbt @@ -5,6 +5,9 @@ import scala.sys.process._ enablePlugins(PackPlugin) +// This needs to stay in sync with the chisel3 and firrtl git submodules +val chiselVersion = "3.4.0-RC1" + lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.2-SNAPSHOT", @@ -53,26 +56,26 @@ lazy val commonSettings = Seq( } ) -lazy val chisel = (project in file("chisel3")).settings(commonSettings) - -def dependOnChisel(prj: Project) = { - if (sys.props.contains("ROCKET_USE_MAVEN")) { - prj.settings( - libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.2-SNAPSHOT") - ) - } else { - prj.dependsOn(chisel) - } -} +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full lazy val `api-config-chipsalliance` = (project in file("api-config-chipsalliance/build-rules/sbt")) .settings(commonSettings) .settings(publishArtifact := false) -lazy val hardfloat = dependOnChisel(project).settings(commonSettings) +lazy val hardfloat = (project in file("hardfloat")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(commonSettings) .settings(publishArtifact := false) lazy val `rocket-macros` = (project in file("macros")).settings(commonSettings) .settings(publishArtifact := false) -lazy val rocketchip = dependOnChisel(project in file(".")) +lazy val rocketchip = (project in file(".")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings, chipSettings) .dependsOn(`api-config-chipsalliance` % "compile-internal;test-internal") .dependsOn(hardfloat % "compile-internal;test-internal") @@ -89,7 +92,11 @@ lazy val rocketchip = dependOnChisel(project in file(".")) exportJars := true, Test / unmanagedBase := baseDirectory.value / "test_lib" ) - + .settings( // Assembly settings + assembly / test := {}, + assembly / assemblyJarName := "rocketchip.jar", + assembly / assemblyOutputPath := baseDirectory.value / "rocketchip.jar" + ) lazy val addons = settingKey[Seq[String]]("list of addons used for this build") lazy val make = inputKey[Unit]("trigger backend-specific makefile command") diff --git a/chisel3 b/chisel3 index cc2971feb15..816b2f583b0 160000 --- a/chisel3 +++ b/chisel3 @@ -1 +1 @@ -Subproject commit cc2971feb15d4bc8cb4a8138b5a095ccbc92dcc3 +Subproject commit 816b2f583b0fc152c1c0f91f77c8b64c67328086 diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator index d1b05fe61ec..b80e90786fb 100644 --- a/emulator/Makefrag-verilator +++ b/emulator/Makefrag-verilator @@ -8,11 +8,11 @@ verilog = \ .SECONDARY: $(firrtl) $(verilog) -$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img) +$(generated_dir)/%.fir $(generated_dir)/%.d: $(ROCKET_CHIP_JAR) $(bootrom_img) mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG) $(CHISEL_OPTIONS)" + cd $(base_dir) && $(GENERATOR) -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG) $(CHISEL_OPTIONS) -%.v %.conf: %.fir $(FIRRTL_JAR) +%.v %.conf: %.fir $(ROCKET_CHIP_JAR) mkdir -p $(dir $@) $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) \ -o $*.v \ diff --git a/firrtl b/firrtl index c07da8a5817..c9a320b00ec 160000 --- a/firrtl +++ b/firrtl @@ -1 +1 @@ -Subproject commit c07da8a581789b88f7e6ffc98c8e810565034ad9 +Subproject commit c9a320b00ec31bc971cba0f09d1bbf3851733c46 diff --git a/project/build.properties b/project/build.properties index 5a9ed9251a0..0837f7a132d 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.4 +sbt.version=1.3.13 diff --git a/project/plugins.sbt b/project/plugins.sbt index f8d325ea9cc..0f4da37ba0d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -2,7 +2,7 @@ addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") -addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0") +addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0") addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") @@ -13,3 +13,10 @@ addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") + +addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") + +addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") + +// From FIRRTL for building from source +addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.19") diff --git a/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala b/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala index 28d90a303f8..7a73b9477ce 100644 --- a/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala +++ b/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala @@ -6,7 +6,7 @@ import chisel3.stage.phases.{Convert, Elaborate, MaybeAspectPhase} import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, DeletedAnnotation, JsonProtocol} import firrtl.options.Viewer.view -import firrtl.options.{Dependency, Phase, PreservesAll, StageOptions, TargetDirAnnotation, Unserializable} +import firrtl.options._ import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.util.HasRocketChipStageUtils @@ -19,18 +19,14 @@ class GenerateFirrtlAnnos extends Phase with PreservesAll[Phase] with HasRocketC val targetDir = view[StageOptions](annotations).targetDir val fileName = s"${view[RocketChipOptions](annotations).longName.get}.anno.json" - val annos = scala.collection.mutable.Buffer[Annotation]() - annotations.flatMap { - case a: Unserializable => - Some(a) - case a: TargetDirAnnotation => - /** Don't serialize, in case of downstream FIRRTL call */ - Some(a) - case a @ DeletedAnnotation(_, _: Unserializable) => - /** [[DeletedAnnotation]]s of unserializable annotations cannot be serialized */ - Some(a) + val annos = annotations.view.flatMap { + // Remove TargetDirAnnotation so that we can pass as argument to FIRRTL + // Remove CustomFileEmission, those are serialized automatically by Stages + case (_: Unserializable | _: TargetDirAnnotation | _: CustomFileEmission) => + None + case DeletedAnnotation(_, (_: Unserializable | _: CustomFileEmission)) => + None case a => - annos += a Some(a) } diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 13e35373d37..0ec2530ad6f 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -8,11 +8,11 @@ verilog = $(generated_dir)/$(long_name).v # files. .SECONDARY: $(firrtl) $(verilog) -$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img) +$(generated_dir)/%.fir $(generated_dir)/%.d: $(ROCKET_CHIP_JAR) $(bootrom_img) mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG)" + cd $(base_dir) && $(GENERATOR) -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG) -$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR) +$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(ROCKET_CHIP_JAR) mkdir -p $(dir $@) $(FIRRTL) -i $< \ -o $(generated_dir)/$*.v \ diff --git a/wit-manifest.json b/wit-manifest.json index 7e14634de68..e1695306e32 100644 --- a/wit-manifest.json +++ b/wit-manifest.json @@ -10,12 +10,12 @@ "source": "git@github.com:sifive/api-chisel3-sifive.git" }, { - "commit": "cc2971feb15d4bc8cb4a8138b5a095ccbc92dcc3", + "commit": "816b2f583b0fc152c1c0f91f77c8b64c67328086", "name": "chisel3", "source": "git@github.com:freechipsproject/chisel3.git" }, { - "commit": "c07da8a581789b88f7e6ffc98c8e810565034ad9", + "commit": "c9a320b00ec31bc971cba0f09d1bbf3851733c46", "name": "firrtl", "source": "git@github.com:freechipsproject/firrtl.git" },