From 691cc14883f2525cf640c2719fcf9078fe93dea1 Mon Sep 17 00:00:00 2001 From: YoungSeok Na Date: Mon, 7 Feb 2022 11:20:01 -0500 Subject: [PATCH 1/5] [API] Multiple report file parsing support --- python/heterocl/report.py | 123 +++++++++++++++++-------------- python/heterocl/report_config.py | 3 +- 2 files changed, 69 insertions(+), 57 deletions(-) diff --git a/python/heterocl/report.py b/python/heterocl/report.py index bab4a5e08..c6f0dd3df 100644 --- a/python/heterocl/report.py +++ b/python/heterocl/report.py @@ -456,64 +456,77 @@ def parse_js(path, print_flag=False): def parse_xml(path, xml_path, prod_name, print_flag=False): xml_file = os.path.join(path, xml_path) - if not os.path.isfile(xml_file): - raise RuntimeError("Cannot find {}, run csyn first".format(xml_file)) - json_file = os.path.join(path,"report.json") - outfile = open(json_file, "w") - with open(xml_file, "r") as xml: - profile = xmltodict.parse(xml.read())["profile"] - json.dump(profile, outfile, indent=2) - - config = RptSetup(profile, prod_name) - config.eval_members() - - res = {} - res["HLS Version"] = config.prod_name + " " + config.version - res["Product family"] = config.prod_family - res["Target device"] = config.target_device - res["Top Model Name"] = config.top_model_name - res["Target CP"] = config.target_cp + " " + config.assignment_unit - res["Estimated CP"] = config.estimated_cp + " " + config.assignment_unit - res["Latency (cycles)"] = "Min {:<6}; ".format(config.min_latency) + \ - "Max {:<6}".format(config.max_latency) - res["Interval (cycles)"] = "Min {:<6}; ".format(config.min_interval) + \ - "Max {:<6}".format(config.max_interval) - - est_resources = config.est_resources - avail_resources = config.avail_resources - key_avail = list(avail_resources.keys()) - - resources = {} - for name in key_avail: + p = xml_file.rsplit('/', 1)[0] + + other_xml_file = [xml_file] + for file in os.listdir(p): + if file.endswith("_csynth.xml") and file != "test_csynth.xml": + fpath = os.path.join(p, file) + other_xml_file.append(fpath) + + for xml_file in other_xml_file: + if not os.path.isfile(xml_file): + raise RuntimeError("Cannot find {}, run csyn first".format(xml_file)) + json_file = os.path.join(path,"report.json") + outfile = open(json_file, "w") + with open(xml_file, "r") as xml: + profile = xmltodict.parse(xml.read())["profile"] + json.dump(profile, outfile, indent=2) + + print(f"File: {xml_file}") + config = RptSetup(profile, prod_name) + config.eval_members() + res = {} + res["HLS Version"] = config.prod_name + " " + config.version + res["Product family"] = config.prod_family + res["Target device"] = config.target_device + res["Top Model Name"] = config.top_model_name + res["Target CP"] = config.target_cp + " " + config.assignment_unit + res["Estimated CP"] = config.estimated_cp + " " + config.assignment_unit + res["Latency (cycles)"] = "Min {:<6}; ".format(config.min_latency) + \ + "Max {:<6}".format(config.max_latency) + res["Interval (cycles)"] = "Min {:<6}; ".format(config.min_interval) + \ + "Max {:<6}".format(config.max_interval) + + est_resources = config.est_resources + avail_resources = config.avail_resources + key_avail = list(avail_resources.keys()) + + resources = {} + for name in key_avail: + try: + item = [est_resources[name], avail_resources[name]] + item.append("{}%".format(round(int(item[0])/int(item[1])*100))) + resources[name] = item.copy() + except ZeroDivisionError: + item.append("0%") + resources[name] = item.copy() + except: + pass + res["Resources"] = tabulate([[key] + resources[key] for key in resources.keys()], + headers=["Type", "Used", "Total", "Util"], + colalign=("left","right","right","right")) + lst = list(res.items()) + tablestr = tabulate(lst, tablefmt="psql").split("\n") + endash = tablestr[0].split("+") + splitline = "+" + endash[1] + "+" + endash[2] + "+" + tablestr.insert(5, splitline) + table = '\n'.join(tablestr) + + # Latency information extraction + clock_unit = config.performance_unit + summary = config.loop_latency + + info_table = Displayer(clock_unit) try: - item = [est_resources[name], avail_resources[name]] - item.append("{}%".format(round(int(item[0])/int(item[1])*100))) - resources[name] = item.copy() - except ZeroDivisionError: - item.append("0%") - resources[name] = item.copy() + info_table.init_table(summary) + info_table.collect_data(summary) + info_table.display() except: pass - res["Resources"] = tabulate([[key] + resources[key] for key in resources.keys()], - headers=["Type", "Used", "Total", "Util"], - colalign=("left","right","right","right")) - lst = list(res.items()) - tablestr = tabulate(lst, tablefmt="psql").split("\n") - endash = tablestr[0].split("+") - splitline = "+" + endash[1] + "+" + endash[2] + "+" - tablestr.insert(5, splitline) - table = '\n'.join(tablestr) - - # Latency information extraction - clock_unit = config.performance_unit - summary = config.loop_latency - - info_table = Displayer(clock_unit) - info_table.init_table(summary) - info_table.collect_data(summary) - - if print_flag: - print(table) + + if print_flag: + print(table) return info_table def report_stats(target, folder): diff --git a/python/heterocl/report_config.py b/python/heterocl/report_config.py index 42abeb971..7d7b8c3bb 100644 --- a/python/heterocl/report_config.py +++ b/python/heterocl/report_config.py @@ -82,8 +82,7 @@ def _lookup(self, keys): try: return reduce(operator.getitem, keys, self.profile) except KeyError: - print("Invalid key") - raise + pass def eval_members(self): """Initialize each attribute to appropriate values. From f6bb8ae97724f434bbf0e13e30b6da8c070a4865 Mon Sep 17 00:00:00 2001 From: YoungSeok Na Date: Mon, 21 Feb 2022 13:16:21 -0500 Subject: [PATCH 2/5] [API] Revised parsing support --- python/heterocl/report.py | 159 ++++++++++++++++++++++++-------------- 1 file changed, 102 insertions(+), 57 deletions(-) diff --git a/python/heterocl/report.py b/python/heterocl/report.py index c6f0dd3df..5e70f94d0 100644 --- a/python/heterocl/report.py +++ b/python/heterocl/report.py @@ -3,8 +3,6 @@ import time import xmltodict import pandas as pd -# Support for graphical display of the report -#import matplotlib.pyplot as plt from .report_config import RptSetup from tabulate import tabulate from .schedule import Stage @@ -57,6 +55,10 @@ class Displayer(object): get_max(col) Sort the latency in a decreasing order for specific latency category. + + add_fields(val) + Dictionary representation of the Displayer object's member of + report files. display(loops=None, level=None, cols=None) Display the report table with appropriate query arguments. @@ -373,6 +375,31 @@ def get_max(self, col): tup_lst = list(map(lambda x: (x[0], x[1], x[2].count('+')), tup_lst)) return list(reversed(sorted(tup_lst, key=lambda x: int(x[1])))) + def add_fields(self, val): + """Append additional data present in separate report files. + + Parameters + ---------- + val: dict + Dictionary representation of the Displayer object's member + of report files. + + Returns + ---------- + None + """ + self._category = val['_category'] + self._category_aux = val['_category_aux'] + self._loop_name += val['_loop_name'] + self._loop_name_aux += val['_loop_name_aux'] + self._max_level = val['_max_level'] if val['_max_level'] > self._max_level else self._max_level + + for key in self._category_aux: + try: + self._data[key] += val['_data'][key] + except: + self._data[key] = val['_data'][key] + def display(self, loops=None, level=None, cols=None): """Display the report file. @@ -431,7 +458,7 @@ def display(self, loops=None, level=None, cols=None): print('* Units in {}'.format(self.unit)) splt = df.loc[rows, cols].to_string().split("\n") pd.set_option('max_colwidth', len(splt[0]) * 100) - return df.loc[rows, cols].to_string() + return df.loc[rows, cols].to_string() def parse_js(path, print_flag=False): js_file = os.path.join(path, "kernel/reports/lib/report_data.js") @@ -456,78 +483,96 @@ def parse_js(path, print_flag=False): def parse_xml(path, xml_path, prod_name, print_flag=False): xml_file = os.path.join(path, xml_path) + # Collect files other than the main one. p = xml_file.rsplit('/', 1)[0] - - other_xml_file = [xml_file] + other_xml_file = [] for file in os.listdir(p): if file.endswith("_csynth.xml") and file != "test_csynth.xml": fpath = os.path.join(p, file) other_xml_file.append(fpath) - for xml_file in other_xml_file: - if not os.path.isfile(xml_file): - raise RuntimeError("Cannot find {}, run csyn first".format(xml_file)) - json_file = os.path.join(path,"report.json") - outfile = open(json_file, "w") - with open(xml_file, "r") as xml: + # Display the general information in `test_csynth.xml` + if not os.path.isfile(xml_file): + raise RuntimeError("Cannot find {}, run csyn first".format(xml_file)) + json_file = os.path.join(path,"report.json") + outfile = open(json_file, "w") + with open(xml_file, "r") as xml: + profile = xmltodict.parse(xml.read())["profile"] + json.dump(profile, outfile, indent=2) + + config = RptSetup(profile, prod_name) + config.eval_members() + res = {} + res["HLS Version"] = config.prod_name + " " + config.version + res["Product family"] = config.prod_family + res["Target device"] = config.target_device + res["Top Model Name"] = config.top_model_name + res["Target CP"] = config.target_cp + " " + config.assignment_unit + res["Estimated CP"] = config.estimated_cp + " " + config.assignment_unit + res["Latency (cycles)"] = "Min {:<6}; ".format(config.min_latency) + \ + "Max {:<6}".format(config.max_latency) + res["Interval (cycles)"] = "Min {:<6}; ".format(config.min_interval) + \ + "Max {:<6}".format(config.max_interval) + + est_resources = config.est_resources + avail_resources = config.avail_resources + key_avail = list(avail_resources.keys()) + + resources = {} + for name in key_avail: + try: + item = [est_resources[name], avail_resources[name]] + item.append("{}%".format(round(int(item[0])/int(item[1])*100))) + resources[name] = item.copy() + except ZeroDivisionError: + item.append("0%") + resources[name] = item.copy() + except: + pass + res["Resources"] = tabulate([[key] + resources[key] for key in resources.keys()], + headers=["Type", "Used", "Total", "Util"], + colalign=("left","right","right","right")) + lst = list(res.items()) + tablestr = tabulate(lst, tablefmt="psql").split("\n") + endash = tablestr[0].split("+") + splitline = "+" + endash[1] + "+" + endash[2] + "+" + tablestr.insert(5, splitline) + table = '\n'.join(tablestr) + + clock_unit = config.performance_unit + + # Parse latency information in the main report file (if it exists) + summary = config.loop_latency + out_info_table = Displayer(clock_unit) + try: + out_info_table.init_table(summary) + out_info_table.collect_data(summary) + except: + pass + + # Latency information extraction + for lat_xml_file in other_xml_file: + with open(lat_xml_file, "r") as xml: profile = xmltodict.parse(xml.read())["profile"] - json.dump(profile, outfile, indent=2) - print(f"File: {xml_file}") config = RptSetup(profile, prod_name) config.eval_members() - res = {} - res["HLS Version"] = config.prod_name + " " + config.version - res["Product family"] = config.prod_family - res["Target device"] = config.target_device - res["Top Model Name"] = config.top_model_name - res["Target CP"] = config.target_cp + " " + config.assignment_unit - res["Estimated CP"] = config.estimated_cp + " " + config.assignment_unit - res["Latency (cycles)"] = "Min {:<6}; ".format(config.min_latency) + \ - "Max {:<6}".format(config.max_latency) - res["Interval (cycles)"] = "Min {:<6}; ".format(config.min_interval) + \ - "Max {:<6}".format(config.max_interval) - - est_resources = config.est_resources - avail_resources = config.avail_resources - key_avail = list(avail_resources.keys()) - - resources = {} - for name in key_avail: - try: - item = [est_resources[name], avail_resources[name]] - item.append("{}%".format(round(int(item[0])/int(item[1])*100))) - resources[name] = item.copy() - except ZeroDivisionError: - item.append("0%") - resources[name] = item.copy() - except: - pass - res["Resources"] = tabulate([[key] + resources[key] for key in resources.keys()], - headers=["Type", "Used", "Total", "Util"], - colalign=("left","right","right","right")) - lst = list(res.items()) - tablestr = tabulate(lst, tablefmt="psql").split("\n") - endash = tablestr[0].split("+") - splitline = "+" + endash[1] + "+" + endash[2] + "+" - tablestr.insert(5, splitline) - table = '\n'.join(tablestr) - - # Latency information extraction - clock_unit = config.performance_unit + summary = config.loop_latency - info_table = Displayer(clock_unit) try: + info_table = Displayer(clock_unit) info_table.init_table(summary) info_table.collect_data(summary) - info_table.display() + res = vars(info_table) + out_info_table.add_fields(res) except: + print("Report for issue") pass - if print_flag: - print(table) - return info_table + if print_flag: + print(table) + return out_info_table def report_stats(target, folder): path = folder From d40485c15fb4b76c5ef9f968f3a449e9b05bf882 Mon Sep 17 00:00:00 2001 From: YoungSeok Na Date: Mon, 21 Feb 2022 14:34:22 -0500 Subject: [PATCH 3/5] [API] Static testset added --- tests/test_hls_report.py | 70 ++++ tests/test_report_data/expected.json | 11 + tests/test_report_data/multi_report.xml | 521 ++++++++++++++++++++++++ 3 files changed, 602 insertions(+) create mode 100644 tests/test_report_data/multi_report.xml diff --git a/tests/test_hls_report.py b/tests/test_hls_report.py index 485577a65..c5657b423 100644 --- a/tests/test_hls_report.py +++ b/tests/test_hls_report.py @@ -92,6 +92,33 @@ def spam_filter(): pass # END TODO +def stages(): + + A = hcl.placeholder((32, 32), "A") + C = hcl.placeholder((32, 32), "C") + def kernel(A, C): + B = hcl.compute(A.shape, lambda i, j : A[i, j] + 1, "B") + D = hcl.compute(A.shape, lambda i, j : B[i, j] + 1, "D") + E = hcl.compute(A.shape, lambda i, j : C[i, j] + 1, "E") + F = hcl.compute(A.shape, lambda i, j : D[i, j] + E[i, j], "F") + return F + + target = hcl.Platform.xilinx_zc706 + target.config(compiler="vivado_hls", mode="csyn", project="stages-tvm.prj") + s = hcl.create_schedule([A, C], kernel) + s.to(kernel.B, s[kernel.D]) + s.to(kernel.D, s[kernel.F]) + s.to(kernel.E, s[kernel.F]) + mod = hcl.build(s, target=target) + np_A = np.zeros((32, 32)) + np_C = np.zeros((32, 32)) + np_F = np.zeros((32, 32)) + hcl_A = hcl.asarray(np_A) + hcl_C = hcl.asarray(np_C) + hcl_F = hcl.asarray(np_F) + mod(hcl_A, hcl_C, hcl_F) + return mod.report() + def refine(res_tbl): lst = res_tbl.split("\n") pattern = re.compile(r'\s\s+') @@ -457,6 +484,48 @@ def test_spam_filter(vhls): } _test_rpt(config) +def test_multi_rpt(vhls): + config = { + 'vhls' : vhls, + 'has_algorithm' : 0, + 'algorithm' : { + 'report_path' : '/test_report_data/multi_report.xml', + 'name' : 'stages' + }, + 'get_max' : 'Latency', + 'col' : 'Category', + 'info' : 'NoQuery', + 'loop_query' : { + 'query' : ['B', 'F'], + 'name' : 'LoopQuery' + }, + 'column_query' : { + 'query' : ['Trip Count', 'Latency', 'Iteration Latency', + 'Pipeline II', 'Pipeline Depth'], + 'name' : 'ColumnQuery' + }, + 'level_query' : { + 'val' : 0, + 'name' : 'LevelQuery' + }, + 'level_out_of_bound' : { + 'val' : [5, -2], + 'name' : 'LevelQueryOOB' + }, + 'multi_query' : { + 'row_query' : ['D'], + 'level_query' : 1, + 'name' : 'MultiQuery' + }, + 'all_query' : { + 'row_query' : ['B', 'E'], + 'col_query' : ['Latency'], + 'level_query' : 0, + 'name' : 'AllQuery' + } + } + _test_rpt(config) + if __name__ == '__main__': test_knn_digitrec(False) test_kmeans(False) @@ -464,3 +533,4 @@ def test_spam_filter(vhls): test_sobel_partial(False) test_canny(False) test_spam_filter(False) + test_multi_rpt(False) diff --git a/tests/test_report_data/expected.json b/tests/test_report_data/expected.json index dc8edc594..5031b59d2 100644 --- a/tests/test_report_data/expected.json +++ b/tests/test_report_data/expected.json @@ -64,5 +64,16 @@ "LevelQueryOOB" : ["Trip Count, Latency Iteration Latency Pipeline II Pipeline Depth", "outer_loop_x_outer_loop_y, 22500, 92610000, 4116, N/A, N/A", "+ data_local_x_outer_data_local_x_inner, 1024, 1026, N/A, 1, 4", "+ dot_product_loop_x_outer1_dot_product_loop_x_inner1, 1024, 1027, N/A, 1, 5", "+ grad_x_outer2_grad_x_inner2, 1024, 1026, N/A, 1, 4", "+ update_param_loop_x_outer3_update_param_loop_x_inner3, 1024, 1026, N/A, 1, 4"], "MultiQuery" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "+ update_param_loop_x_outer3_update_param_loop_x_inner3, 1024, 1026, N/A, 1, 4"], "AllQuery" : ["Latency", "+ dot_product_loop_x_outer1_dot_product_loop_x_inner1, 1027"] + }, + "stages" : { + "GetMax" : {"E_i2": {"3136": 0}, "B_i": {"3136": 0}, "F_i3": {"2112": 0}, "D_i1": {"2112": 0}, "E_j2": {"96": 1}, "B_j": {"96": 1}, "F_j3": {"64": 1}, "D_j1": {"64": 1}}, + "Category" : "Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", + "NoQuery" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "B_i, 32, 3136, 98, N/A, N/A", "+ B_j, 32, 96, 3, N/A, N/A", "D_i1, 32, 2112, 66, N/A, N/A", "+ D_j1, 32, 64, 2, N/A, N/A", "E_i2, 32, 3136, 98, N/A, N/A", "+ E_j2, 32, 96, 3, N/A, N/A", "F_i3, 32, 2112, 66, N/A, N/A", "+ F_j3, 32, 64, 2, N/A, N/A"], + "LoopQuery" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "B_i, 32, 3136, 98, N/A, N/A", "+ B_j, 32, 96, 3, N/A, N/A", "F_i3, 32, 2112, 66, N/A, N/A", "+ F_j3, 32, 64, 2, N/A, N/A"], + "ColumnQuery" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "B_i, 32, 3136, 98, N/A, N/A", "+ B_j, 32, 96, 3, N/A, N/A", "D_i1, 32, 2112, 66, N/A, N/A", "+ D_j1, 32, 64, 2, N/A, N/A", "E_i2, 32, 3136, 98, N/A, N/A", "+ E_j2, 32, 96, 3, N/A, N/A", "F_i3, 32, 2112, 66, N/A, N/A", "+ F_j3, 32, 64, 2, N/A, N/A"], + "LevelQuery" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "B_i, 32, 3136, 98, N/A, N/A", "D_i1, 32, 2112, 66, N/A, N/A", "E_i2, 32, 3136, 98, N/A, N/A", "F_i3, 32, 2112, 66, N/A, N/A"], + "LevelQueryOOB" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "B_i, 32, 3136, 98, N/A, N/A", "+ B_j, 32, 96, 3, N/A, N/A", "D_i1, 32, 2112, 66, N/A, N/A", "+ D_j1, 32, 64, 2, N/A, N/A", "E_i2, 32, 3136, 98, N/A, N/A", "+ E_j2, 32, 96, 3, N/A, N/A", "F_i3, 32, 2112, 66, N/A, N/A", "+ F_j3, 32, 64, 2, N/A, N/A"], + "MultiQuery" : ["Trip Count Latency Iteration Latency Pipeline II Pipeline Depth", "D_i1, 32, 2112, 66, N/A, N/A", "+ D_j1, 32, 64, 2, N/A, N/A"], + "AllQuery" : ["Latency", "B_i, 3136", "E_i2, 3136"] } } diff --git a/tests/test_report_data/multi_report.xml b/tests/test_report_data/multi_report.xml new file mode 100644 index 000000000..537db4862 --- /dev/null +++ b/tests/test_report_data/multi_report.xml @@ -0,0 +1,521 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +test +10.00 +1.25 + + + +dataflow + +ns +6.186 + + +clock cycles +3137 +3137 +3137 +3138 +3138 +3138 + + + +32 +3136 +98 + +32 +96 +3 + + + +32 +2112 +66 + +32 +64 +2 + + + +32 +3136 +98 + +32 +96 +3 + + + +32 +2112 +66 + +32 +64 +2 + + + + + + + +0 +299 +912 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +A_address0 +A +array + +ap_memory + +out +10 +address +int + + +A_ce0 +A +array + +ap_memory + +out +1 +control +int + + +A_d0 +A +array + +ap_memory + +out +32 +data +int + + +A_q0 +A +array + +ap_memory + +in +32 +data +int + + +A_we0 +A +array + +ap_memory + +out +1 +control +int + + +A_address1 +A +array + +ap_memory + +out +10 +address +int + + +A_ce1 +A +array + +ap_memory + +out +1 +control +int + + +A_d1 +A +array + +ap_memory + +out +32 +data +int + + +A_q1 +A +array + +ap_memory + +in +32 +data +int + + +A_we1 +A +array + +ap_memory + +out +1 +control +int + + +C_address0 +C +array + +ap_memory + +out +10 +address +int + + +C_ce0 +C +array + +ap_memory + +out +1 +control +int + + +C_d0 +C +array + +ap_memory + +out +32 +data +int + + +C_q0 +C +array + +ap_memory + +in +32 +data +int + + +C_we0 +C +array + +ap_memory + +out +1 +control +int + + +C_address1 +C +array + +ap_memory + +out +10 +address +int + + +C_ce1 +C +array + +ap_memory + +out +1 +control +int + + +C_d1 +C +array + +ap_memory + +out +32 +data +int + + +C_q1 +C +array + +ap_memory + +in +32 +data +int + + +C_we1 +C +array + +ap_memory + +out +1 +control +int + + +F_address0 +F +array + +ap_memory + +out +10 +address +int + + +F_ce0 +F +array + +ap_memory + +out +1 +control +int + + +F_d0 +F +array + +ap_memory + +out +32 +data +int + + +F_q0 +F +array + +ap_memory + +in +32 +data +int + + +F_we0 +F +array + +ap_memory + +out +1 +control +int + + +F_address1 +F +array + +ap_memory + +out +10 +address +int + + +F_ce1 +F +array + +ap_memory + +out +1 +control +int + + +F_d1 +F +array + +ap_memory + +out +32 +data +int + + +F_q1 +F +array + +ap_memory + +in +32 +data +int + + +F_we1 +F +array + +ap_memory + +out +1 +control +int + + +ap_clk +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +test +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +test +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +test +return value + +ap_ctrl_hs + +out +1 +control + + + + From 9bcb770ddee67d2f9f6c59c4be7703909b0a8f35 Mon Sep 17 00:00:00 2001 From: YoungSeok Na Date: Mon, 21 Feb 2022 15:26:48 -0500 Subject: [PATCH 4/5] [API] get_rpt fix --- tests/test_hls_report.py | 42 +- .../stages_report/Loop_B_i_proc4_csynth.rpt | 157 ++++++ .../stages_report/Loop_B_i_proc4_csynth.xml | 240 +++++++++ .../stages_report/Loop_D_i1_proc5_csynth.rpt | 152 ++++++ .../stages_report/Loop_D_i1_proc5_csynth.xml | 207 ++++++++ .../stages_report/Loop_E_i2_proc6_csynth.rpt | 157 ++++++ .../stages_report/Loop_E_i2_proc6_csynth.xml | 240 +++++++++ .../stages_report/Loop_F_i3_proc7_csynth.rpt | 159 ++++++ .../stages_report/Loop_F_i3_proc7_csynth.xml | 251 +++++++++ .../test_report_data/stages_report/csynth.xml | 479 ++++++++++++++++++ .../stages_report/test_csynth.rpt | 190 +++++++ .../stages_report/test_csynth.xml | 479 ++++++++++++++++++ 12 files changed, 2748 insertions(+), 5 deletions(-) create mode 100644 tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt create mode 100644 tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.xml create mode 100644 tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt create mode 100644 tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.xml create mode 100644 tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt create mode 100644 tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.xml create mode 100644 tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt create mode 100644 tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.xml create mode 100644 tests/test_report_data/stages_report/csynth.xml create mode 100644 tests/test_report_data/stages_report/test_csynth.rpt create mode 100644 tests/test_report_data/stages_report/test_csynth.xml diff --git a/tests/test_hls_report.py b/tests/test_hls_report.py index c5657b423..508c70965 100644 --- a/tests/test_hls_report.py +++ b/tests/test_hls_report.py @@ -1,5 +1,6 @@ import heterocl as hcl import numpy as np +import os import re import json import xmltodict @@ -146,11 +147,33 @@ def get_rpt(config): with open(xml_file, "r") as xml: profile = xmltodict.parse(xml.read())["profile"] clock_unit = profile["PerformanceEstimates"]["SummaryOfOverallLatency"]["unit"] - summary = profile["PerformanceEstimates"]["SummaryOfLoopLatency"] - + rpt = hcl.report.Displayer(clock_unit) - rpt.init_table(summary) - rpt.collect_data(summary) + try: + summary = profile["PerformanceEstimates"]["SummaryOfLoopLatency"] + rpt.init_table(summary) + rpt.collect_data(summary) + except: + pass + + path = config['algorithm']['data_path'] + if path: + other_rpt = [] + path = str(pathlib.Path(__file__).parent.absolute()) + path + for file in os.listdir(path): + if file.endswith("_csynth.xml") and file != "test_csynth.xml": + fpath = os.path.join(path, file) + other_rpt.append(fpath) + + for files in other_rpt: + with open(files, "r") as xml: + profile = xmltodict.parse(xml.read())["profile"] + summary = profile["PerformanceEstimates"]["SummaryOfLoopLatency"] + rpt_inner = hcl.report.Displayer(clock_unit) + rpt_inner.init_table(summary) + rpt_inner.collect_data(summary) + res = vars(rpt_inner) + rpt.add_fields(res) return rpt def _test_rpt(config): @@ -239,6 +262,7 @@ def test_knn_digitrec(vhls): 'has_algorithm' : 1, 'algorithm' : { 'report_path' : '/test_report_data/digitrec_report.xml', + 'data_path' : '', 'name' : 'knn_digitrec' }, 'get_max' : 'Latency', @@ -280,6 +304,7 @@ def test_kmeans(vhls): 'has_algorithm' : 1, 'algorithm' : { 'report_path' : '/test_report_data/kmeans_report.xml', + 'data_path' : '', 'name' : 'kmeans' }, 'get_max' : 'Absolute Time Latency', @@ -321,6 +346,7 @@ def test_sobel(vhls): 'has_algorithm' : 0, 'algorithm' : { 'report_path' : '/test_report_data/sobel_report.xml', + 'data_path' : '', 'name' : 'sobel' }, 'get_max' : 'Latency', @@ -363,6 +389,7 @@ def test_sobel_partial(vhls): 'has_algorithm' : 0, 'algorithm' : { 'report_path' : '/test_report_data/sobel_report_partial.xml', + 'data_path' : '', 'name' : 'sobel_partial' }, 'get_max' : 'Latency', @@ -405,6 +432,7 @@ def test_canny(vhls): 'has_algorithm' : 0, 'algorithm' : { 'report_path' : '/test_report_data/canny_report.xml', + 'data_path' : '', 'name' : 'canny' }, 'get_max' : 'Max Latency', @@ -448,6 +476,7 @@ def test_spam_filter(vhls): 'has_algorithm' : 0, 'algorithm' : { 'report_path' : '/test_report_data/spam_filter_report.xml', + 'data_path' : '', 'name' : 'spam_filter' }, 'get_max' : 'Latency', @@ -485,11 +514,14 @@ def test_spam_filter(vhls): _test_rpt(config) def test_multi_rpt(vhls): + # `report_path` can also be switched into + # `/test_report_data/multi_report.xml` config = { 'vhls' : vhls, 'has_algorithm' : 0, 'algorithm' : { - 'report_path' : '/test_report_data/multi_report.xml', + 'report_path' : '/test_report_data/stages_report/test_csynth.xml', + 'data_path' : '/test_report_data/stages_report/', 'name' : 'stages' }, 'get_max' : 'Latency', diff --git a/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt b/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt new file mode 100644 index 000000000..12d914e5e --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt @@ -0,0 +1,157 @@ + + +================================================================ +== Vivado HLS Report for 'Loop_B_i_proc4' +================================================================ +* Date: Mon Feb 21 13:58:40 2022 + +* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) +* Project: out.prj +* Solution: solution1 +* Product family: zynq +* Target device: xc7z020-clg484-1 + + +================================================================ +== Performance Estimates +================================================================ ++ Timing (ns): + * Summary: + +--------+-------+----------+------------+ + | Clock | Target| Estimated| Uncertainty| + +--------+-------+----------+------------+ + |ap_clk | 10.00| 6.186| 1.25| + +--------+-------+----------+------------+ + ++ Latency (clock cycles): + * Summary: + +------+------+------+------+---------+ + | Latency | Interval | Pipeline| + | min | max | min | max | Type | + +------+------+------+------+---------+ + | 3137| 3137| 3137| 3137| none | + +------+------+------+------+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + +----------+------+------+----------+-----------+-----------+------+----------+ + | | Latency | Iteration| Initiation Interval | Trip | | + | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| + +----------+------+------+----------+-----------+-----------+------+----------+ + |- B_i | 3136| 3136| 98| -| -| 32| no | + | + B_j | 96| 96| 3| -| -| 32| no | + +----------+------+------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++-----------------+---------+-------+--------+-------+-----+ +| Name | BRAM_18K| DSP48E| FF | LUT | URAM| ++-----------------+---------+-------+--------+-------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 105| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| -| 78| -| +|Register | -| -| 69| -| -| ++-----------------+---------+-------+--------+-------+-----+ +|Total | 0| 0| 69| 183| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Available | 280| 220| 106400| 53200| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Utilization (%) | 0| 0| ~0 | ~0 | 0| ++-----------------+---------+-------+--------+-------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP48E: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------+----------+-------+---+----+------------+------------+ + | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------+----------+-------+---+----+------------+------------+ + |B_pipe_1_V_din | + | 0| 0| 39| 32| 1| + |add_ln20_fu_128_p2 | + | 0| 0| 12| 12| 12| + |i_fu_94_p2 | + | 0| 0| 15| 6| 1| + |j_fu_118_p2 | + | 0| 0| 15| 6| 1| + |icmp_ln17_fu_88_p2 | icmp | 0| 0| 11| 6| 7| + |icmp_ln18_fu_112_p2 | icmp | 0| 0| 11| 6| 7| + |ap_block_state1 | or | 0| 0| 2| 1| 1| + +---------------------+----------+-------+---+----+------------+------------+ + |Total | | 0| 0| 105| 69| 30| + +---------------------+----------+-------+---+----+------------+------------+ + + * Multiplexer: + +------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------+----+-----------+-----+-----------+ + |B_pipe_1_V_blk_n | 9| 2| 1| 2| + |ap_NS_fsm | 33| 6| 1| 6| + |ap_done | 9| 2| 1| 2| + |i_0_i_i_reg_66 | 9| 2| 6| 12| + |j_0_i_i_reg_77 | 9| 2| 6| 12| + |real_start | 9| 2| 1| 2| + +------------------+----+-----------+-----+-----------+ + |Total | 78| 16| 16| 36| + +------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +-------------------+----+----+-----+-----------+ + |A_load_reg_170 | 32| 0| 32| 0| + |ap_CS_fsm | 5| 0| 5| 0| + |ap_done_reg | 1| 0| 1| 0| + |i_0_i_i_reg_66 | 6| 0| 6| 0| + |i_reg_147 | 6| 0| 6| 0| + |j_0_i_i_reg_77 | 6| 0| 6| 0| + |j_reg_160 | 6| 0| 6| 0| + |start_once_reg | 1| 0| 1| 0| + |zext_ln18_reg_152 | 6| 0| 12| 6| + +-------------------+----+----+-----+-----------+ + |Total | 69| 0| 75| 6| + +-------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-------------------+-----+-----+------------+----------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-------------------+-----+-----+------------+----------------+--------------+ +|ap_clk | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|ap_rst | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|ap_start | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|start_full_n | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|ap_done | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|ap_continue | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|ap_idle | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|ap_ready | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|start_out | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|start_write | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | +|A_address0 | out | 10| ap_memory | A | array | +|A_ce0 | out | 1| ap_memory | A | array | +|A_q0 | in | 32| ap_memory | A | array | +|B_pipe_1_V_din | out | 32| ap_fifo | B_pipe_1_V | pointer | +|B_pipe_1_V_full_n | in | 1| ap_fifo | B_pipe_1_V | pointer | +|B_pipe_1_V_write | out | 1| ap_fifo | B_pipe_1_V | pointer | ++-------------------+-----+-----+------------+----------------+--------------+ + diff --git a/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.xml b/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.xml new file mode 100644 index 000000000..d65c11c7d --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.xml @@ -0,0 +1,240 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +Loop_B_i_proc4 +10.00 +1.25 + + + +none + +ns +6.186 + + +clock cycles +3137 +3137 +3137 +3137 +3137 + + + +32 +3136 +98 + +32 +96 +3 + + + + + + + +69 +183 +0 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +ap_clk +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +Loop_B_i_proc4 +return value + +ap_ctrl_hs + +out +1 +unknown + + +A_address0 +A +array + +ap_memory + +out +10 +address + + +A_ce0 +A +array + +ap_memory + +out +1 +control + + +A_q0 +A +array + +ap_memory + +in +32 +data + + +B_pipe_1_V_din +B_pipe_1_V +pointer + +ap_fifo + +out +32 +control + + +B_pipe_1_V_full_n +B_pipe_1_V +pointer + +ap_fifo + +in +1 +control + + +B_pipe_1_V_write +B_pipe_1_V +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt b/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt new file mode 100644 index 000000000..1eb03fa83 --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt @@ -0,0 +1,152 @@ + + +================================================================ +== Vivado HLS Report for 'Loop_D_i1_proc5' +================================================================ +* Date: Mon Feb 21 13:58:40 2022 + +* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) +* Project: out.prj +* Solution: solution1 +* Product family: zynq +* Target device: xc7z020-clg484-1 + + +================================================================ +== Performance Estimates +================================================================ ++ Timing (ns): + * Summary: + +--------+-------+----------+------------+ + | Clock | Target| Estimated| Uncertainty| + +--------+-------+----------+------------+ + |ap_clk | 10.00| 6.186| 1.25| + +--------+-------+----------+------------+ + ++ Latency (clock cycles): + * Summary: + +------+------+------+------+---------+ + | Latency | Interval | Pipeline| + | min | max | min | max | Type | + +------+------+------+------+---------+ + | 2113| 2113| 2113| 2113| none | + +------+------+------+------+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + +----------+------+------+----------+-----------+-----------+------+----------+ + | | Latency | Iteration| Initiation Interval | Trip | | + | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| + +----------+------+------+----------+-----------+-----------+------+----------+ + |- D_i1 | 2112| 2112| 66| -| -| 32| no | + | + D_j1 | 64| 64| 2| -| -| 32| no | + +----------+------+------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++-----------------+---------+-------+--------+-------+-----+ +| Name | BRAM_18K| DSP48E| FF | LUT | URAM| ++-----------------+---------+-------+--------+-------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 95| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| -| 72| -| +|Register | -| -| 61| -| -| ++-----------------+---------+-------+--------+-------+-----+ +|Total | 0| 0| 61| 167| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Available | 280| 220| 106400| 53200| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Utilization (%) | 0| 0| ~0 | ~0 | 0| ++-----------------+---------+-------+--------+-------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP48E: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +--------------------+----------+-------+---+----+------------+------------+ + | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| + +--------------------+----------+-------+---+----+------------+------------+ + |D_pipe_2_V_din | + | 0| 0| 39| 32| 1| + |i1_fu_83_p2 | + | 0| 0| 15| 6| 1| + |j1_fu_95_p2 | + | 0| 0| 15| 6| 1| + |ap_block_state3 | and | 0| 0| 2| 1| 1| + |icmp_ln27_fu_77_p2 | icmp | 0| 0| 11| 6| 7| + |icmp_ln28_fu_89_p2 | icmp | 0| 0| 11| 6| 7| + |ap_block_state1 | or | 0| 0| 2| 1| 1| + +--------------------+----------+-------+---+----+------------+------------+ + |Total | | 0| 0| 95| 58| 19| + +--------------------+----------+-------+---+----+------------+------------+ + + * Multiplexer: + +------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------+----+-----------+-----+-----------+ + |B_pipe_1_V_blk_n | 9| 2| 1| 2| + |D_pipe_2_V_blk_n | 9| 2| 1| 2| + |ap_NS_fsm | 27| 5| 1| 5| + |ap_done | 9| 2| 1| 2| + |i1_0_reg_55 | 9| 2| 6| 12| + |j1_0_reg_66 | 9| 2| 6| 12| + +------------------+----+-----------+-----+-----------+ + |Total | 72| 15| 16| 35| + +------------------+----+-----------+-----+-----------+ + + * Register: + +---------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +---------------+----+----+-----+-----------+ + |ap_CS_fsm | 4| 0| 4| 0| + |ap_done_reg | 1| 0| 1| 0| + |i1_0_reg_55 | 6| 0| 6| 0| + |i1_reg_110 | 6| 0| 6| 0| + |j1_0_reg_66 | 6| 0| 6| 0| + |j1_reg_118 | 6| 0| 6| 0| + |tmp_2_reg_123 | 32| 0| 32| 0| + +---------------+----+----+-----+-----------+ + |Total | 61| 0| 61| 0| + +---------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++--------------------+-----+-----+------------+-----------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++--------------------+-----+-----+------------+-----------------+--------------+ +|ap_clk | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|ap_rst | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|ap_start | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|ap_done | out | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|ap_continue | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|ap_idle | out | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|ap_ready | out | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | +|B_pipe_1_V_dout | in | 32| ap_fifo | B_pipe_1_V | pointer | +|B_pipe_1_V_empty_n | in | 1| ap_fifo | B_pipe_1_V | pointer | +|B_pipe_1_V_read | out | 1| ap_fifo | B_pipe_1_V | pointer | +|D_pipe_2_V_din | out | 32| ap_fifo | D_pipe_2_V | pointer | +|D_pipe_2_V_full_n | in | 1| ap_fifo | D_pipe_2_V | pointer | +|D_pipe_2_V_write | out | 1| ap_fifo | D_pipe_2_V | pointer | ++--------------------+-----+-----+------------+-----------------+--------------+ + diff --git a/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.xml b/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.xml new file mode 100644 index 000000000..f4bb9051e --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.xml @@ -0,0 +1,207 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +Loop_D_i1_proc5 +10.00 +1.25 + + + +none + +ns +6.186 + + +clock cycles +2113 +2113 +2113 +2113 +2113 + + + +32 +2112 +66 + +32 +64 +2 + + + + + + + +61 +167 +0 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +ap_clk +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +Loop_D_i1_proc5 +return value + +ap_ctrl_hs + +out +1 +control + + +B_pipe_1_V_dout +B_pipe_1_V +pointer + +ap_fifo + +in +32 +control + + +B_pipe_1_V_empty_n +B_pipe_1_V +pointer + +ap_fifo + +in +1 +control + + +B_pipe_1_V_read +B_pipe_1_V +pointer + +ap_fifo + +out +1 +control + + +D_pipe_2_V_din +D_pipe_2_V +pointer + +ap_fifo + +out +32 +control + + +D_pipe_2_V_full_n +D_pipe_2_V +pointer + +ap_fifo + +in +1 +control + + +D_pipe_2_V_write +D_pipe_2_V +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt b/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt new file mode 100644 index 000000000..5f0f14731 --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt @@ -0,0 +1,157 @@ + + +================================================================ +== Vivado HLS Report for 'Loop_E_i2_proc6' +================================================================ +* Date: Mon Feb 21 13:58:40 2022 + +* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) +* Project: out.prj +* Solution: solution1 +* Product family: zynq +* Target device: xc7z020-clg484-1 + + +================================================================ +== Performance Estimates +================================================================ ++ Timing (ns): + * Summary: + +--------+-------+----------+------------+ + | Clock | Target| Estimated| Uncertainty| + +--------+-------+----------+------------+ + |ap_clk | 10.00| 6.186| 1.25| + +--------+-------+----------+------------+ + ++ Latency (clock cycles): + * Summary: + +------+------+------+------+---------+ + | Latency | Interval | Pipeline| + | min | max | min | max | Type | + +------+------+------+------+---------+ + | 3137| 3137| 3137| 3137| none | + +------+------+------+------+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + +----------+------+------+----------+-----------+-----------+------+----------+ + | | Latency | Iteration| Initiation Interval | Trip | | + | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| + +----------+------+------+----------+-----------+-----------+------+----------+ + |- E_i2 | 3136| 3136| 98| -| -| 32| no | + | + E_j2 | 96| 96| 3| -| -| 32| no | + +----------+------+------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++-----------------+---------+-------+--------+-------+-----+ +| Name | BRAM_18K| DSP48E| FF | LUT | URAM| ++-----------------+---------+-------+--------+-------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 105| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| -| 78| -| +|Register | -| -| 69| -| -| ++-----------------+---------+-------+--------+-------+-----+ +|Total | 0| 0| 69| 183| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Available | 280| 220| 106400| 53200| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Utilization (%) | 0| 0| ~0 | ~0 | 0| ++-----------------+---------+-------+--------+-------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP48E: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +---------------------+----------+-------+---+----+------------+------------+ + | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| + +---------------------+----------+-------+---+----+------------+------------+ + |E_pipe_3_V_din | + | 0| 0| 39| 32| 1| + |add_ln42_fu_128_p2 | + | 0| 0| 12| 12| 12| + |i2_fu_94_p2 | + | 0| 0| 15| 6| 1| + |j2_fu_118_p2 | + | 0| 0| 15| 6| 1| + |icmp_ln39_fu_88_p2 | icmp | 0| 0| 11| 6| 7| + |icmp_ln40_fu_112_p2 | icmp | 0| 0| 11| 6| 7| + |ap_block_state1 | or | 0| 0| 2| 1| 1| + +---------------------+----------+-------+---+----+------------+------------+ + |Total | | 0| 0| 105| 69| 30| + +---------------------+----------+-------+---+----+------------+------------+ + + * Multiplexer: + +------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------+----+-----------+-----+-----------+ + |E_pipe_3_V_blk_n | 9| 2| 1| 2| + |ap_NS_fsm | 33| 6| 1| 6| + |ap_done | 9| 2| 1| 2| + |i2_0_reg_66 | 9| 2| 6| 12| + |j2_0_reg_77 | 9| 2| 6| 12| + |real_start | 9| 2| 1| 2| + +------------------+----+-----------+-----+-----------+ + |Total | 78| 16| 16| 36| + +------------------+----+-----------+-----+-----------+ + + * Register: + +-------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +-------------------+----+----+-----+-----------+ + |C_load_reg_170 | 32| 0| 32| 0| + |ap_CS_fsm | 5| 0| 5| 0| + |ap_done_reg | 1| 0| 1| 0| + |i2_0_reg_66 | 6| 0| 6| 0| + |i2_reg_147 | 6| 0| 6| 0| + |j2_0_reg_77 | 6| 0| 6| 0| + |j2_reg_160 | 6| 0| 6| 0| + |start_once_reg | 1| 0| 1| 0| + |zext_ln40_reg_152 | 6| 0| 12| 6| + +-------------------+----+----+-----+-----------+ + |Total | 69| 0| 75| 6| + +-------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++-------------------+-----+-----+------------+-----------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++-------------------+-----+-----+------------+-----------------+--------------+ +|ap_clk | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|ap_rst | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|ap_start | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|start_full_n | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|ap_done | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|ap_continue | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|ap_idle | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|ap_ready | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|start_out | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|start_write | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | +|C_address0 | out | 10| ap_memory | C | array | +|C_ce0 | out | 1| ap_memory | C | array | +|C_q0 | in | 32| ap_memory | C | array | +|E_pipe_3_V_din | out | 32| ap_fifo | E_pipe_3_V | pointer | +|E_pipe_3_V_full_n | in | 1| ap_fifo | E_pipe_3_V | pointer | +|E_pipe_3_V_write | out | 1| ap_fifo | E_pipe_3_V | pointer | ++-------------------+-----+-----+------------+-----------------+--------------+ + diff --git a/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.xml b/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.xml new file mode 100644 index 000000000..2a7fb6ac2 --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.xml @@ -0,0 +1,240 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +Loop_E_i2_proc6 +10.00 +1.25 + + + +none + +ns +6.186 + + +clock cycles +3137 +3137 +3137 +3137 +3137 + + + +32 +3136 +98 + +32 +96 +3 + + + + + + + +69 +183 +0 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +ap_clk +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +in +1 +control + + +start_full_n +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +in +1 +unknown + + +ap_done +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +out +1 +control + + +start_out +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +out +1 +unknown + + +start_write +Loop_E_i2_proc6 +return value + +ap_ctrl_hs + +out +1 +unknown + + +C_address0 +C +array + +ap_memory + +out +10 +address + + +C_ce0 +C +array + +ap_memory + +out +1 +control + + +C_q0 +C +array + +ap_memory + +in +32 +data + + +E_pipe_3_V_din +E_pipe_3_V +pointer + +ap_fifo + +out +32 +control + + +E_pipe_3_V_full_n +E_pipe_3_V +pointer + +ap_fifo + +in +1 +control + + +E_pipe_3_V_write +E_pipe_3_V +pointer + +ap_fifo + +out +1 +control + + + + diff --git a/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt b/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt new file mode 100644 index 000000000..bc75e2680 --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt @@ -0,0 +1,159 @@ + + +================================================================ +== Vivado HLS Report for 'Loop_F_i3_proc7' +================================================================ +* Date: Mon Feb 21 13:58:41 2022 + +* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) +* Project: out.prj +* Solution: solution1 +* Product family: zynq +* Target device: xc7z020-clg484-1 + + +================================================================ +== Performance Estimates +================================================================ ++ Timing (ns): + * Summary: + +--------+-------+----------+------------+ + | Clock | Target| Estimated| Uncertainty| + +--------+-------+----------+------------+ + |ap_clk | 10.00| 6.186| 1.25| + +--------+-------+----------+------------+ + ++ Latency (clock cycles): + * Summary: + +------+------+------+------+---------+ + | Latency | Interval | Pipeline| + | min | max | min | max | Type | + +------+------+------+------+---------+ + | 2113| 2113| 2113| 2113| none | + +------+------+------+------+---------+ + + + Detail: + * Instance: + N/A + + * Loop: + +----------+------+------+----------+-----------+-----------+------+----------+ + | | Latency | Iteration| Initiation Interval | Trip | | + | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| + +----------+------+------+----------+-----------+-----------+------+----------+ + |- F_i3 | 2112| 2112| 66| -| -| 32| no | + | + F_j3 | 64| 64| 2| -| -| 32| no | + +----------+------+------+----------+-----------+-----------+------+----------+ + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++-----------------+---------+-------+--------+-------+-----+ +| Name | BRAM_18K| DSP48E| FF | LUT | URAM| ++-----------------+---------+-------+--------+-------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 107| -| +|FIFO | -| -| -| -| -| +|Instance | -| -| -| -| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| -| 72| -| +|Register | -| -| 79| -| -| ++-----------------+---------+-------+--------+-------+-----+ +|Total | 0| 0| 79| 179| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Available | 280| 220| 106400| 53200| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Utilization (%) | 0| 0| ~0 | ~0 | 0| ++-----------------+---------+-------+--------+-------+-----+ + ++ Detail: + * Instance: + N/A + + * DSP48E: + N/A + + * Memory: + N/A + + * FIFO: + N/A + + * Expression: + +----------------------+----------+-------+---+----+------------+------------+ + | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| + +----------------------+----------+-------+---+----+------------+------------+ + |add_ln52_1_fu_139_p2 | + | 0| 0| 12| 12| 12| + |add_ln52_fu_129_p2 | + | 0| 0| 39| 32| 32| + |i3_fu_99_p2 | + | 0| 0| 15| 6| 1| + |j3_fu_123_p2 | + | 0| 0| 15| 6| 1| + |icmp_ln46_fu_93_p2 | icmp | 0| 0| 11| 6| 7| + |icmp_ln47_fu_117_p2 | icmp | 0| 0| 11| 6| 7| + |ap_block_state1 | or | 0| 0| 2| 1| 1| + |ap_block_state3 | or | 0| 0| 2| 1| 1| + +----------------------+----------+-------+---+----+------------+------------+ + |Total | | 0| 0| 107| 70| 62| + +----------------------+----------+-------+---+----+------------+------------+ + + * Multiplexer: + +------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +------------------+----+-----------+-----+-----------+ + |D_pipe_2_V_blk_n | 9| 2| 1| 2| + |E_pipe_3_V_blk_n | 9| 2| 1| 2| + |ap_NS_fsm | 27| 5| 1| 5| + |ap_done | 9| 2| 1| 2| + |i3_0_reg_71 | 9| 2| 6| 12| + |j3_0_reg_82 | 9| 2| 6| 12| + +------------------+----+-----------+-----+-----------+ + |Total | 72| 15| 16| 35| + +------------------+----+-----------+-----+-----------+ + + * Register: + +--------------------+----+----+-----+-----------+ + | Name | FF | LUT| Bits| Const Bits| + +--------------------+----+----+-----+-----------+ + |add_ln52_1_reg_174 | 12| 0| 12| 0| + |add_ln52_reg_169 | 32| 0| 32| 0| + |ap_CS_fsm | 4| 0| 4| 0| + |ap_done_reg | 1| 0| 1| 0| + |i3_0_reg_71 | 6| 0| 6| 0| + |i3_reg_151 | 6| 0| 6| 0| + |j3_0_reg_82 | 6| 0| 6| 0| + |j3_reg_164 | 6| 0| 6| 0| + |zext_ln47_reg_156 | 6| 0| 12| 6| + +--------------------+----+----+-----+-----------+ + |Total | 79| 0| 85| 6| + +--------------------+----+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++--------------------+-----+-----+------------+-----------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | ++--------------------+-----+-----+------------+-----------------+--------------+ +|ap_clk | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|ap_rst | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|ap_start | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|ap_done | out | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|ap_continue | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|ap_idle | out | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|ap_ready | out | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | +|D_pipe_2_V_dout | in | 32| ap_fifo | D_pipe_2_V | pointer | +|D_pipe_2_V_empty_n | in | 1| ap_fifo | D_pipe_2_V | pointer | +|D_pipe_2_V_read | out | 1| ap_fifo | D_pipe_2_V | pointer | +|E_pipe_3_V_dout | in | 32| ap_fifo | E_pipe_3_V | pointer | +|E_pipe_3_V_empty_n | in | 1| ap_fifo | E_pipe_3_V | pointer | +|E_pipe_3_V_read | out | 1| ap_fifo | E_pipe_3_V | pointer | +|F_address0 | out | 10| ap_memory | F | array | +|F_ce0 | out | 1| ap_memory | F | array | +|F_we0 | out | 1| ap_memory | F | array | +|F_d0 | out | 32| ap_memory | F | array | ++--------------------+-----+-----+------------+-----------------+--------------+ + diff --git a/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.xml b/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.xml new file mode 100644 index 000000000..d71b9bba5 --- /dev/null +++ b/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.xml @@ -0,0 +1,251 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +Loop_F_i3_proc7 +10.00 +1.25 + + + +none + +ns +6.186 + + +clock cycles +2113 +2113 +2113 +2113 +2113 + + + +32 +2112 +66 + +32 +64 +2 + + + + + + + +79 +179 +0 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +ap_clk +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_continue +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +in +1 +control + + +ap_idle +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +Loop_F_i3_proc7 +return value + +ap_ctrl_hs + +out +1 +control + + +D_pipe_2_V_dout +D_pipe_2_V +pointer + +ap_fifo + +in +32 +control + + +D_pipe_2_V_empty_n +D_pipe_2_V +pointer + +ap_fifo + +in +1 +control + + +D_pipe_2_V_read +D_pipe_2_V +pointer + +ap_fifo + +out +1 +control + + +E_pipe_3_V_dout +E_pipe_3_V +pointer + +ap_fifo + +in +32 +control + + +E_pipe_3_V_empty_n +E_pipe_3_V +pointer + +ap_fifo + +in +1 +control + + +E_pipe_3_V_read +E_pipe_3_V +pointer + +ap_fifo + +out +1 +control + + +F_address0 +F +array + +ap_memory + +out +10 +address + + +F_ce0 +F +array + +ap_memory + +out +1 +control + + +F_we0 +F +array + +ap_memory + +out +1 +control + + +F_d0 +F +array + +ap_memory + +out +32 +data + + + + diff --git a/tests/test_report_data/stages_report/csynth.xml b/tests/test_report_data/stages_report/csynth.xml new file mode 100644 index 000000000..77275fdcf --- /dev/null +++ b/tests/test_report_data/stages_report/csynth.xml @@ -0,0 +1,479 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +test +10.00 +1.25 + + + +dataflow + +ns +6.186 + + +clock cycles +3137 +3137 +3137 +3138 +3138 +3138 + + + + + +0 +299 +912 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +A_address0 +A +array + +ap_memory + +out +10 +address +int + + +A_ce0 +A +array + +ap_memory + +out +1 +control +int + + +A_d0 +A +array + +ap_memory + +out +32 +data +int + + +A_q0 +A +array + +ap_memory + +in +32 +data +int + + +A_we0 +A +array + +ap_memory + +out +1 +control +int + + +A_address1 +A +array + +ap_memory + +out +10 +address +int + + +A_ce1 +A +array + +ap_memory + +out +1 +control +int + + +A_d1 +A +array + +ap_memory + +out +32 +data +int + + +A_q1 +A +array + +ap_memory + +in +32 +data +int + + +A_we1 +A +array + +ap_memory + +out +1 +control +int + + +C_address0 +C +array + +ap_memory + +out +10 +address +int + + +C_ce0 +C +array + +ap_memory + +out +1 +control +int + + +C_d0 +C +array + +ap_memory + +out +32 +data +int + + +C_q0 +C +array + +ap_memory + +in +32 +data +int + + +C_we0 +C +array + +ap_memory + +out +1 +control +int + + +C_address1 +C +array + +ap_memory + +out +10 +address +int + + +C_ce1 +C +array + +ap_memory + +out +1 +control +int + + +C_d1 +C +array + +ap_memory + +out +32 +data +int + + +C_q1 +C +array + +ap_memory + +in +32 +data +int + + +C_we1 +C +array + +ap_memory + +out +1 +control +int + + +F_address0 +F +array + +ap_memory + +out +10 +address +int + + +F_ce0 +F +array + +ap_memory + +out +1 +control +int + + +F_d0 +F +array + +ap_memory + +out +32 +data +int + + +F_q0 +F +array + +ap_memory + +in +32 +data +int + + +F_we0 +F +array + +ap_memory + +out +1 +control +int + + +F_address1 +F +array + +ap_memory + +out +10 +address +int + + +F_ce1 +F +array + +ap_memory + +out +1 +control +int + + +F_d1 +F +array + +ap_memory + +out +32 +data +int + + +F_q1 +F +array + +ap_memory + +in +32 +data +int + + +F_we1 +F +array + +ap_memory + +out +1 +control +int + + +ap_clk +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +test +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +test +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +test +return value + +ap_ctrl_hs + +out +1 +control + + + + diff --git a/tests/test_report_data/stages_report/test_csynth.rpt b/tests/test_report_data/stages_report/test_csynth.rpt new file mode 100644 index 000000000..77e8a92d6 --- /dev/null +++ b/tests/test_report_data/stages_report/test_csynth.rpt @@ -0,0 +1,190 @@ + + +================================================================ +== Vivado HLS Report for 'test' +================================================================ +* Date: Mon Feb 21 13:58:41 2022 + +* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) +* Project: out.prj +* Solution: solution1 +* Product family: zynq +* Target device: xc7z020-clg484-1 + + +================================================================ +== Performance Estimates +================================================================ ++ Timing (ns): + * Summary: + +--------+-------+----------+------------+ + | Clock | Target| Estimated| Uncertainty| + +--------+-------+----------+------------+ + |ap_clk | 10.00| 6.186| 1.25| + +--------+-------+----------+------------+ + ++ Latency (clock cycles): + * Summary: + +------+------+------+------+----------+ + | Latency | Interval | Pipeline | + | min | max | min | max | Type | + +------+------+------+------+----------+ + | 3137| 3137| 3138| 3138| dataflow | + +------+------+------+------+----------+ + + + Detail: + * Instance: + +--------------------+-----------------+------+------+------+------+---------+ + | | | Latency | Interval | Pipeline| + | Instance | Module | min | max | min | max | Type | + +--------------------+-----------------+------+------+------+------+---------+ + |Loop_B_i_proc4_U0 |Loop_B_i_proc4 | 3137| 3137| 3137| 3137| none | + |Loop_E_i2_proc6_U0 |Loop_E_i2_proc6 | 3137| 3137| 3137| 3137| none | + |Loop_F_i3_proc7_U0 |Loop_F_i3_proc7 | 2113| 2113| 2113| 2113| none | + |Loop_D_i1_proc5_U0 |Loop_D_i1_proc5 | 2113| 2113| 2113| 2113| none | + +--------------------+-----------------+------+------+------+------+---------+ + + * Loop: + N/A + + + +================================================================ +== Utilization Estimates +================================================================ +* Summary: ++-----------------+---------+-------+--------+-------+-----+ +| Name | BRAM_18K| DSP48E| FF | LUT | URAM| ++-----------------+---------+-------+--------+-------+-----+ +|DSP | -| -| -| -| -| +|Expression | -| -| 0| 32| -| +|FIFO | 0| -| 15| 132| -| +|Instance | -| -| 278| 712| -| +|Memory | -| -| -| -| -| +|Multiplexer | -| -| -| 36| -| +|Register | -| -| 6| -| -| ++-----------------+---------+-------+--------+-------+-----+ +|Total | 0| 0| 299| 912| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Available | 280| 220| 106400| 53200| 0| ++-----------------+---------+-------+--------+-------+-----+ +|Utilization (%) | 0| 0| ~0 | 1| 0| ++-----------------+---------+-------+--------+-------+-----+ + ++ Detail: + * Instance: + +--------------------+-----------------+---------+-------+----+-----+-----+ + | Instance | Module | BRAM_18K| DSP48E| FF | LUT | URAM| + +--------------------+-----------------+---------+-------+----+-----+-----+ + |Loop_B_i_proc4_U0 |Loop_B_i_proc4 | 0| 0| 69| 183| 0| + |Loop_D_i1_proc5_U0 |Loop_D_i1_proc5 | 0| 0| 61| 167| 0| + |Loop_E_i2_proc6_U0 |Loop_E_i2_proc6 | 0| 0| 69| 183| 0| + |Loop_F_i3_proc7_U0 |Loop_F_i3_proc7 | 0| 0| 79| 179| 0| + +--------------------+-----------------+---------+-------+----+-----+-----+ + |Total | | 0| 0| 278| 712| 0| + +--------------------+-----------------+---------+-------+----+-----+-----+ + + * DSP48E: + N/A + + * Memory: + N/A + + * FIFO: + +--------------+---------+---+----+-----+------+-----+---------+ + | Name | BRAM_18K| FF| LUT| URAM| Depth| Bits| Size:D*B| + +--------------+---------+---+----+-----+------+-----+---------+ + |B_pipe_1_V_U | 0| 5| 0| -| 1| 32| 32| + |D_pipe_2_V_U | 0| 5| 0| -| 1| 32| 32| + |E_pipe_3_V_U | 0| 5| 0| -| 1| 32| 32| + +--------------+---------+---+----+-----+------+-----+---------+ + |Total | 0| 15| 0| 0| 3| 96| 96| + +--------------+---------+---+----+-----+------+-----+---------+ + + * Expression: + +-------------------------------------+----------+-------+---+----+------------+------------+ + | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| + +-------------------------------------+----------+-------+---+----+------------+------------+ + |Loop_B_i_proc4_U0_ap_ready_count | + | 0| 0| 10| 2| 1| + |Loop_E_i2_proc6_U0_ap_ready_count | + | 0| 0| 10| 2| 1| + |Loop_B_i_proc4_U0_ap_start | and | 0| 0| 2| 1| 1| + |Loop_E_i2_proc6_U0_ap_start | and | 0| 0| 2| 1| 1| + |ap_idle | and | 0| 0| 2| 1| 1| + |ap_sync_ready | and | 0| 0| 2| 1| 1| + |ap_sync_Loop_B_i_proc4_U0_ap_ready | or | 0| 0| 2| 1| 1| + |ap_sync_Loop_E_i2_proc6_U0_ap_ready | or | 0| 0| 2| 1| 1| + +-------------------------------------+----------+-------+---+----+------------+------------+ + |Total | | 0| 0| 32| 10| 8| + +-------------------------------------+----------+-------+---+----+------------+------------+ + + * Multiplexer: + +-----------------------------------------+----+-----------+-----+-----------+ + | Name | LUT| Input Size| Bits| Total Bits| + +-----------------------------------------+----+-----------+-----+-----------+ + |Loop_B_i_proc4_U0_ap_ready_count | 9| 2| 2| 4| + |Loop_E_i2_proc6_U0_ap_ready_count | 9| 2| 2| 4| + |ap_sync_reg_Loop_B_i_proc4_U0_ap_ready | 9| 2| 1| 2| + |ap_sync_reg_Loop_E_i2_proc6_U0_ap_ready | 9| 2| 1| 2| + +-----------------------------------------+----+-----------+-----+-----------+ + |Total | 36| 8| 6| 12| + +-----------------------------------------+----+-----------+-----+-----------+ + + * Register: + +-----------------------------------------+---+----+-----+-----------+ + | Name | FF| LUT| Bits| Const Bits| + +-----------------------------------------+---+----+-----+-----------+ + |Loop_B_i_proc4_U0_ap_ready_count | 2| 0| 2| 0| + |Loop_E_i2_proc6_U0_ap_ready_count | 2| 0| 2| 0| + |ap_sync_reg_Loop_B_i_proc4_U0_ap_ready | 1| 0| 1| 0| + |ap_sync_reg_Loop_E_i2_proc6_U0_ap_ready | 1| 0| 1| 0| + +-----------------------------------------+---+----+-----+-----------+ + |Total | 6| 0| 6| 0| + +-----------------------------------------+---+----+-----+-----------+ + + + +================================================================ +== Interface +================================================================ +* Summary: ++------------+-----+-----+------------+--------------+--------------+ +| RTL Ports | Dir | Bits| Protocol | Source Object| C Type | ++------------+-----+-----+------------+--------------+--------------+ +|A_address0 | out | 10| ap_memory | A | array | +|A_ce0 | out | 1| ap_memory | A | array | +|A_d0 | out | 32| ap_memory | A | array | +|A_q0 | in | 32| ap_memory | A | array | +|A_we0 | out | 1| ap_memory | A | array | +|A_address1 | out | 10| ap_memory | A | array | +|A_ce1 | out | 1| ap_memory | A | array | +|A_d1 | out | 32| ap_memory | A | array | +|A_q1 | in | 32| ap_memory | A | array | +|A_we1 | out | 1| ap_memory | A | array | +|C_address0 | out | 10| ap_memory | C | array | +|C_ce0 | out | 1| ap_memory | C | array | +|C_d0 | out | 32| ap_memory | C | array | +|C_q0 | in | 32| ap_memory | C | array | +|C_we0 | out | 1| ap_memory | C | array | +|C_address1 | out | 10| ap_memory | C | array | +|C_ce1 | out | 1| ap_memory | C | array | +|C_d1 | out | 32| ap_memory | C | array | +|C_q1 | in | 32| ap_memory | C | array | +|C_we1 | out | 1| ap_memory | C | array | +|F_address0 | out | 10| ap_memory | F | array | +|F_ce0 | out | 1| ap_memory | F | array | +|F_d0 | out | 32| ap_memory | F | array | +|F_q0 | in | 32| ap_memory | F | array | +|F_we0 | out | 1| ap_memory | F | array | +|F_address1 | out | 10| ap_memory | F | array | +|F_ce1 | out | 1| ap_memory | F | array | +|F_d1 | out | 32| ap_memory | F | array | +|F_q1 | in | 32| ap_memory | F | array | +|F_we1 | out | 1| ap_memory | F | array | +|ap_clk | in | 1| ap_ctrl_hs | test | return value | +|ap_rst | in | 1| ap_ctrl_hs | test | return value | +|ap_start | in | 1| ap_ctrl_hs | test | return value | +|ap_done | out | 1| ap_ctrl_hs | test | return value | +|ap_ready | out | 1| ap_ctrl_hs | test | return value | +|ap_idle | out | 1| ap_ctrl_hs | test | return value | ++------------+-----+-----+------------+--------------+--------------+ + diff --git a/tests/test_report_data/stages_report/test_csynth.xml b/tests/test_report_data/stages_report/test_csynth.xml new file mode 100644 index 000000000..77275fdcf --- /dev/null +++ b/tests/test_report_data/stages_report/test_csynth.xml @@ -0,0 +1,479 @@ + + + +2019.1.3 + + + +ns +zynq +xc7z020-clg484-1 +test +10.00 +1.25 + + + +dataflow + +ns +6.186 + + +clock cycles +3137 +3137 +3137 +3138 +3138 +3138 + + + + + +0 +299 +912 +0 +0 + + +280 +220 +106400 +53200 +0 + + + + + +A_address0 +A +array + +ap_memory + +out +10 +address +int + + +A_ce0 +A +array + +ap_memory + +out +1 +control +int + + +A_d0 +A +array + +ap_memory + +out +32 +data +int + + +A_q0 +A +array + +ap_memory + +in +32 +data +int + + +A_we0 +A +array + +ap_memory + +out +1 +control +int + + +A_address1 +A +array + +ap_memory + +out +10 +address +int + + +A_ce1 +A +array + +ap_memory + +out +1 +control +int + + +A_d1 +A +array + +ap_memory + +out +32 +data +int + + +A_q1 +A +array + +ap_memory + +in +32 +data +int + + +A_we1 +A +array + +ap_memory + +out +1 +control +int + + +C_address0 +C +array + +ap_memory + +out +10 +address +int + + +C_ce0 +C +array + +ap_memory + +out +1 +control +int + + +C_d0 +C +array + +ap_memory + +out +32 +data +int + + +C_q0 +C +array + +ap_memory + +in +32 +data +int + + +C_we0 +C +array + +ap_memory + +out +1 +control +int + + +C_address1 +C +array + +ap_memory + +out +10 +address +int + + +C_ce1 +C +array + +ap_memory + +out +1 +control +int + + +C_d1 +C +array + +ap_memory + +out +32 +data +int + + +C_q1 +C +array + +ap_memory + +in +32 +data +int + + +C_we1 +C +array + +ap_memory + +out +1 +control +int + + +F_address0 +F +array + +ap_memory + +out +10 +address +int + + +F_ce0 +F +array + +ap_memory + +out +1 +control +int + + +F_d0 +F +array + +ap_memory + +out +32 +data +int + + +F_q0 +F +array + +ap_memory + +in +32 +data +int + + +F_we0 +F +array + +ap_memory + +out +1 +control +int + + +F_address1 +F +array + +ap_memory + +out +10 +address +int + + +F_ce1 +F +array + +ap_memory + +out +1 +control +int + + +F_d1 +F +array + +ap_memory + +out +32 +data +int + + +F_q1 +F +array + +ap_memory + +in +32 +data +int + + +F_we1 +F +array + +ap_memory + +out +1 +control +int + + +ap_clk +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_rst +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_start +test +return value + +ap_ctrl_hs + +in +1 +control + + +ap_done +test +return value + +ap_ctrl_hs + +out +1 +control + + +ap_ready +test +return value + +ap_ctrl_hs + +out +1 +control + + +ap_idle +test +return value + +ap_ctrl_hs + +out +1 +control + + + + From a6f852cee1977588876a2bdbb7f395596dd4b9bd Mon Sep 17 00:00:00 2001 From: YoungSeok Na Date: Mon, 21 Feb 2022 16:27:03 -0500 Subject: [PATCH 5/5] [API] Remove unnecessary report files --- .../stages_report/Loop_B_i_proc4_csynth.rpt | 157 --------------- .../stages_report/Loop_D_i1_proc5_csynth.rpt | 152 -------------- .../stages_report/Loop_E_i2_proc6_csynth.rpt | 157 --------------- .../stages_report/Loop_F_i3_proc7_csynth.rpt | 159 --------------- .../stages_report/test_csynth.rpt | 190 ------------------ 5 files changed, 815 deletions(-) delete mode 100644 tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt delete mode 100644 tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt delete mode 100644 tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt delete mode 100644 tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt delete mode 100644 tests/test_report_data/stages_report/test_csynth.rpt diff --git a/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt b/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt deleted file mode 100644 index 12d914e5e..000000000 --- a/tests/test_report_data/stages_report/Loop_B_i_proc4_csynth.rpt +++ /dev/null @@ -1,157 +0,0 @@ - - -================================================================ -== Vivado HLS Report for 'Loop_B_i_proc4' -================================================================ -* Date: Mon Feb 21 13:58:40 2022 - -* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) -* Project: out.prj -* Solution: solution1 -* Product family: zynq -* Target device: xc7z020-clg484-1 - - -================================================================ -== Performance Estimates -================================================================ -+ Timing (ns): - * Summary: - +--------+-------+----------+------------+ - | Clock | Target| Estimated| Uncertainty| - +--------+-------+----------+------------+ - |ap_clk | 10.00| 6.186| 1.25| - +--------+-------+----------+------------+ - -+ Latency (clock cycles): - * Summary: - +------+------+------+------+---------+ - | Latency | Interval | Pipeline| - | min | max | min | max | Type | - +------+------+------+------+---------+ - | 3137| 3137| 3137| 3137| none | - +------+------+------+------+---------+ - - + Detail: - * Instance: - N/A - - * Loop: - +----------+------+------+----------+-----------+-----------+------+----------+ - | | Latency | Iteration| Initiation Interval | Trip | | - | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| - +----------+------+------+----------+-----------+-----------+------+----------+ - |- B_i | 3136| 3136| 98| -| -| 32| no | - | + B_j | 96| 96| 3| -| -| 32| no | - +----------+------+------+----------+-----------+-----------+------+----------+ - - - -================================================================ -== Utilization Estimates -================================================================ -* Summary: -+-----------------+---------+-------+--------+-------+-----+ -| Name | BRAM_18K| DSP48E| FF | LUT | URAM| -+-----------------+---------+-------+--------+-------+-----+ -|DSP | -| -| -| -| -| -|Expression | -| -| 0| 105| -| -|FIFO | -| -| -| -| -| -|Instance | -| -| -| -| -| -|Memory | -| -| -| -| -| -|Multiplexer | -| -| -| 78| -| -|Register | -| -| 69| -| -| -+-----------------+---------+-------+--------+-------+-----+ -|Total | 0| 0| 69| 183| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Available | 280| 220| 106400| 53200| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Utilization (%) | 0| 0| ~0 | ~0 | 0| -+-----------------+---------+-------+--------+-------+-----+ - -+ Detail: - * Instance: - N/A - - * DSP48E: - N/A - - * Memory: - N/A - - * FIFO: - N/A - - * Expression: - +---------------------+----------+-------+---+----+------------+------------+ - | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| - +---------------------+----------+-------+---+----+------------+------------+ - |B_pipe_1_V_din | + | 0| 0| 39| 32| 1| - |add_ln20_fu_128_p2 | + | 0| 0| 12| 12| 12| - |i_fu_94_p2 | + | 0| 0| 15| 6| 1| - |j_fu_118_p2 | + | 0| 0| 15| 6| 1| - |icmp_ln17_fu_88_p2 | icmp | 0| 0| 11| 6| 7| - |icmp_ln18_fu_112_p2 | icmp | 0| 0| 11| 6| 7| - |ap_block_state1 | or | 0| 0| 2| 1| 1| - +---------------------+----------+-------+---+----+------------+------------+ - |Total | | 0| 0| 105| 69| 30| - +---------------------+----------+-------+---+----+------------+------------+ - - * Multiplexer: - +------------------+----+-----------+-----+-----------+ - | Name | LUT| Input Size| Bits| Total Bits| - +------------------+----+-----------+-----+-----------+ - |B_pipe_1_V_blk_n | 9| 2| 1| 2| - |ap_NS_fsm | 33| 6| 1| 6| - |ap_done | 9| 2| 1| 2| - |i_0_i_i_reg_66 | 9| 2| 6| 12| - |j_0_i_i_reg_77 | 9| 2| 6| 12| - |real_start | 9| 2| 1| 2| - +------------------+----+-----------+-----+-----------+ - |Total | 78| 16| 16| 36| - +------------------+----+-----------+-----+-----------+ - - * Register: - +-------------------+----+----+-----+-----------+ - | Name | FF | LUT| Bits| Const Bits| - +-------------------+----+----+-----+-----------+ - |A_load_reg_170 | 32| 0| 32| 0| - |ap_CS_fsm | 5| 0| 5| 0| - |ap_done_reg | 1| 0| 1| 0| - |i_0_i_i_reg_66 | 6| 0| 6| 0| - |i_reg_147 | 6| 0| 6| 0| - |j_0_i_i_reg_77 | 6| 0| 6| 0| - |j_reg_160 | 6| 0| 6| 0| - |start_once_reg | 1| 0| 1| 0| - |zext_ln18_reg_152 | 6| 0| 12| 6| - +-------------------+----+----+-----+-----------+ - |Total | 69| 0| 75| 6| - +-------------------+----+----+-----+-----------+ - - - -================================================================ -== Interface -================================================================ -* Summary: -+-------------------+-----+-----+------------+----------------+--------------+ -| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | -+-------------------+-----+-----+------------+----------------+--------------+ -|ap_clk | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|ap_rst | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|ap_start | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|start_full_n | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|ap_done | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|ap_continue | in | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|ap_idle | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|ap_ready | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|start_out | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|start_write | out | 1| ap_ctrl_hs | Loop_B_i_proc4 | return value | -|A_address0 | out | 10| ap_memory | A | array | -|A_ce0 | out | 1| ap_memory | A | array | -|A_q0 | in | 32| ap_memory | A | array | -|B_pipe_1_V_din | out | 32| ap_fifo | B_pipe_1_V | pointer | -|B_pipe_1_V_full_n | in | 1| ap_fifo | B_pipe_1_V | pointer | -|B_pipe_1_V_write | out | 1| ap_fifo | B_pipe_1_V | pointer | -+-------------------+-----+-----+------------+----------------+--------------+ - diff --git a/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt b/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt deleted file mode 100644 index 1eb03fa83..000000000 --- a/tests/test_report_data/stages_report/Loop_D_i1_proc5_csynth.rpt +++ /dev/null @@ -1,152 +0,0 @@ - - -================================================================ -== Vivado HLS Report for 'Loop_D_i1_proc5' -================================================================ -* Date: Mon Feb 21 13:58:40 2022 - -* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) -* Project: out.prj -* Solution: solution1 -* Product family: zynq -* Target device: xc7z020-clg484-1 - - -================================================================ -== Performance Estimates -================================================================ -+ Timing (ns): - * Summary: - +--------+-------+----------+------------+ - | Clock | Target| Estimated| Uncertainty| - +--------+-------+----------+------------+ - |ap_clk | 10.00| 6.186| 1.25| - +--------+-------+----------+------------+ - -+ Latency (clock cycles): - * Summary: - +------+------+------+------+---------+ - | Latency | Interval | Pipeline| - | min | max | min | max | Type | - +------+------+------+------+---------+ - | 2113| 2113| 2113| 2113| none | - +------+------+------+------+---------+ - - + Detail: - * Instance: - N/A - - * Loop: - +----------+------+------+----------+-----------+-----------+------+----------+ - | | Latency | Iteration| Initiation Interval | Trip | | - | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| - +----------+------+------+----------+-----------+-----------+------+----------+ - |- D_i1 | 2112| 2112| 66| -| -| 32| no | - | + D_j1 | 64| 64| 2| -| -| 32| no | - +----------+------+------+----------+-----------+-----------+------+----------+ - - - -================================================================ -== Utilization Estimates -================================================================ -* Summary: -+-----------------+---------+-------+--------+-------+-----+ -| Name | BRAM_18K| DSP48E| FF | LUT | URAM| -+-----------------+---------+-------+--------+-------+-----+ -|DSP | -| -| -| -| -| -|Expression | -| -| 0| 95| -| -|FIFO | -| -| -| -| -| -|Instance | -| -| -| -| -| -|Memory | -| -| -| -| -| -|Multiplexer | -| -| -| 72| -| -|Register | -| -| 61| -| -| -+-----------------+---------+-------+--------+-------+-----+ -|Total | 0| 0| 61| 167| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Available | 280| 220| 106400| 53200| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Utilization (%) | 0| 0| ~0 | ~0 | 0| -+-----------------+---------+-------+--------+-------+-----+ - -+ Detail: - * Instance: - N/A - - * DSP48E: - N/A - - * Memory: - N/A - - * FIFO: - N/A - - * Expression: - +--------------------+----------+-------+---+----+------------+------------+ - | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| - +--------------------+----------+-------+---+----+------------+------------+ - |D_pipe_2_V_din | + | 0| 0| 39| 32| 1| - |i1_fu_83_p2 | + | 0| 0| 15| 6| 1| - |j1_fu_95_p2 | + | 0| 0| 15| 6| 1| - |ap_block_state3 | and | 0| 0| 2| 1| 1| - |icmp_ln27_fu_77_p2 | icmp | 0| 0| 11| 6| 7| - |icmp_ln28_fu_89_p2 | icmp | 0| 0| 11| 6| 7| - |ap_block_state1 | or | 0| 0| 2| 1| 1| - +--------------------+----------+-------+---+----+------------+------------+ - |Total | | 0| 0| 95| 58| 19| - +--------------------+----------+-------+---+----+------------+------------+ - - * Multiplexer: - +------------------+----+-----------+-----+-----------+ - | Name | LUT| Input Size| Bits| Total Bits| - +------------------+----+-----------+-----+-----------+ - |B_pipe_1_V_blk_n | 9| 2| 1| 2| - |D_pipe_2_V_blk_n | 9| 2| 1| 2| - |ap_NS_fsm | 27| 5| 1| 5| - |ap_done | 9| 2| 1| 2| - |i1_0_reg_55 | 9| 2| 6| 12| - |j1_0_reg_66 | 9| 2| 6| 12| - +------------------+----+-----------+-----+-----------+ - |Total | 72| 15| 16| 35| - +------------------+----+-----------+-----+-----------+ - - * Register: - +---------------+----+----+-----+-----------+ - | Name | FF | LUT| Bits| Const Bits| - +---------------+----+----+-----+-----------+ - |ap_CS_fsm | 4| 0| 4| 0| - |ap_done_reg | 1| 0| 1| 0| - |i1_0_reg_55 | 6| 0| 6| 0| - |i1_reg_110 | 6| 0| 6| 0| - |j1_0_reg_66 | 6| 0| 6| 0| - |j1_reg_118 | 6| 0| 6| 0| - |tmp_2_reg_123 | 32| 0| 32| 0| - +---------------+----+----+-----+-----------+ - |Total | 61| 0| 61| 0| - +---------------+----+----+-----+-----------+ - - - -================================================================ -== Interface -================================================================ -* Summary: -+--------------------+-----+-----+------------+-----------------+--------------+ -| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | -+--------------------+-----+-----+------------+-----------------+--------------+ -|ap_clk | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|ap_rst | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|ap_start | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|ap_done | out | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|ap_continue | in | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|ap_idle | out | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|ap_ready | out | 1| ap_ctrl_hs | Loop_D_i1_proc5 | return value | -|B_pipe_1_V_dout | in | 32| ap_fifo | B_pipe_1_V | pointer | -|B_pipe_1_V_empty_n | in | 1| ap_fifo | B_pipe_1_V | pointer | -|B_pipe_1_V_read | out | 1| ap_fifo | B_pipe_1_V | pointer | -|D_pipe_2_V_din | out | 32| ap_fifo | D_pipe_2_V | pointer | -|D_pipe_2_V_full_n | in | 1| ap_fifo | D_pipe_2_V | pointer | -|D_pipe_2_V_write | out | 1| ap_fifo | D_pipe_2_V | pointer | -+--------------------+-----+-----+------------+-----------------+--------------+ - diff --git a/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt b/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt deleted file mode 100644 index 5f0f14731..000000000 --- a/tests/test_report_data/stages_report/Loop_E_i2_proc6_csynth.rpt +++ /dev/null @@ -1,157 +0,0 @@ - - -================================================================ -== Vivado HLS Report for 'Loop_E_i2_proc6' -================================================================ -* Date: Mon Feb 21 13:58:40 2022 - -* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) -* Project: out.prj -* Solution: solution1 -* Product family: zynq -* Target device: xc7z020-clg484-1 - - -================================================================ -== Performance Estimates -================================================================ -+ Timing (ns): - * Summary: - +--------+-------+----------+------------+ - | Clock | Target| Estimated| Uncertainty| - +--------+-------+----------+------------+ - |ap_clk | 10.00| 6.186| 1.25| - +--------+-------+----------+------------+ - -+ Latency (clock cycles): - * Summary: - +------+------+------+------+---------+ - | Latency | Interval | Pipeline| - | min | max | min | max | Type | - +------+------+------+------+---------+ - | 3137| 3137| 3137| 3137| none | - +------+------+------+------+---------+ - - + Detail: - * Instance: - N/A - - * Loop: - +----------+------+------+----------+-----------+-----------+------+----------+ - | | Latency | Iteration| Initiation Interval | Trip | | - | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| - +----------+------+------+----------+-----------+-----------+------+----------+ - |- E_i2 | 3136| 3136| 98| -| -| 32| no | - | + E_j2 | 96| 96| 3| -| -| 32| no | - +----------+------+------+----------+-----------+-----------+------+----------+ - - - -================================================================ -== Utilization Estimates -================================================================ -* Summary: -+-----------------+---------+-------+--------+-------+-----+ -| Name | BRAM_18K| DSP48E| FF | LUT | URAM| -+-----------------+---------+-------+--------+-------+-----+ -|DSP | -| -| -| -| -| -|Expression | -| -| 0| 105| -| -|FIFO | -| -| -| -| -| -|Instance | -| -| -| -| -| -|Memory | -| -| -| -| -| -|Multiplexer | -| -| -| 78| -| -|Register | -| -| 69| -| -| -+-----------------+---------+-------+--------+-------+-----+ -|Total | 0| 0| 69| 183| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Available | 280| 220| 106400| 53200| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Utilization (%) | 0| 0| ~0 | ~0 | 0| -+-----------------+---------+-------+--------+-------+-----+ - -+ Detail: - * Instance: - N/A - - * DSP48E: - N/A - - * Memory: - N/A - - * FIFO: - N/A - - * Expression: - +---------------------+----------+-------+---+----+------------+------------+ - | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| - +---------------------+----------+-------+---+----+------------+------------+ - |E_pipe_3_V_din | + | 0| 0| 39| 32| 1| - |add_ln42_fu_128_p2 | + | 0| 0| 12| 12| 12| - |i2_fu_94_p2 | + | 0| 0| 15| 6| 1| - |j2_fu_118_p2 | + | 0| 0| 15| 6| 1| - |icmp_ln39_fu_88_p2 | icmp | 0| 0| 11| 6| 7| - |icmp_ln40_fu_112_p2 | icmp | 0| 0| 11| 6| 7| - |ap_block_state1 | or | 0| 0| 2| 1| 1| - +---------------------+----------+-------+---+----+------------+------------+ - |Total | | 0| 0| 105| 69| 30| - +---------------------+----------+-------+---+----+------------+------------+ - - * Multiplexer: - +------------------+----+-----------+-----+-----------+ - | Name | LUT| Input Size| Bits| Total Bits| - +------------------+----+-----------+-----+-----------+ - |E_pipe_3_V_blk_n | 9| 2| 1| 2| - |ap_NS_fsm | 33| 6| 1| 6| - |ap_done | 9| 2| 1| 2| - |i2_0_reg_66 | 9| 2| 6| 12| - |j2_0_reg_77 | 9| 2| 6| 12| - |real_start | 9| 2| 1| 2| - +------------------+----+-----------+-----+-----------+ - |Total | 78| 16| 16| 36| - +------------------+----+-----------+-----+-----------+ - - * Register: - +-------------------+----+----+-----+-----------+ - | Name | FF | LUT| Bits| Const Bits| - +-------------------+----+----+-----+-----------+ - |C_load_reg_170 | 32| 0| 32| 0| - |ap_CS_fsm | 5| 0| 5| 0| - |ap_done_reg | 1| 0| 1| 0| - |i2_0_reg_66 | 6| 0| 6| 0| - |i2_reg_147 | 6| 0| 6| 0| - |j2_0_reg_77 | 6| 0| 6| 0| - |j2_reg_160 | 6| 0| 6| 0| - |start_once_reg | 1| 0| 1| 0| - |zext_ln40_reg_152 | 6| 0| 12| 6| - +-------------------+----+----+-----+-----------+ - |Total | 69| 0| 75| 6| - +-------------------+----+----+-----+-----------+ - - - -================================================================ -== Interface -================================================================ -* Summary: -+-------------------+-----+-----+------------+-----------------+--------------+ -| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | -+-------------------+-----+-----+------------+-----------------+--------------+ -|ap_clk | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|ap_rst | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|ap_start | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|start_full_n | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|ap_done | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|ap_continue | in | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|ap_idle | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|ap_ready | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|start_out | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|start_write | out | 1| ap_ctrl_hs | Loop_E_i2_proc6 | return value | -|C_address0 | out | 10| ap_memory | C | array | -|C_ce0 | out | 1| ap_memory | C | array | -|C_q0 | in | 32| ap_memory | C | array | -|E_pipe_3_V_din | out | 32| ap_fifo | E_pipe_3_V | pointer | -|E_pipe_3_V_full_n | in | 1| ap_fifo | E_pipe_3_V | pointer | -|E_pipe_3_V_write | out | 1| ap_fifo | E_pipe_3_V | pointer | -+-------------------+-----+-----+------------+-----------------+--------------+ - diff --git a/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt b/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt deleted file mode 100644 index bc75e2680..000000000 --- a/tests/test_report_data/stages_report/Loop_F_i3_proc7_csynth.rpt +++ /dev/null @@ -1,159 +0,0 @@ - - -================================================================ -== Vivado HLS Report for 'Loop_F_i3_proc7' -================================================================ -* Date: Mon Feb 21 13:58:41 2022 - -* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) -* Project: out.prj -* Solution: solution1 -* Product family: zynq -* Target device: xc7z020-clg484-1 - - -================================================================ -== Performance Estimates -================================================================ -+ Timing (ns): - * Summary: - +--------+-------+----------+------------+ - | Clock | Target| Estimated| Uncertainty| - +--------+-------+----------+------------+ - |ap_clk | 10.00| 6.186| 1.25| - +--------+-------+----------+------------+ - -+ Latency (clock cycles): - * Summary: - +------+------+------+------+---------+ - | Latency | Interval | Pipeline| - | min | max | min | max | Type | - +------+------+------+------+---------+ - | 2113| 2113| 2113| 2113| none | - +------+------+------+------+---------+ - - + Detail: - * Instance: - N/A - - * Loop: - +----------+------+------+----------+-----------+-----------+------+----------+ - | | Latency | Iteration| Initiation Interval | Trip | | - | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| - +----------+------+------+----------+-----------+-----------+------+----------+ - |- F_i3 | 2112| 2112| 66| -| -| 32| no | - | + F_j3 | 64| 64| 2| -| -| 32| no | - +----------+------+------+----------+-----------+-----------+------+----------+ - - - -================================================================ -== Utilization Estimates -================================================================ -* Summary: -+-----------------+---------+-------+--------+-------+-----+ -| Name | BRAM_18K| DSP48E| FF | LUT | URAM| -+-----------------+---------+-------+--------+-------+-----+ -|DSP | -| -| -| -| -| -|Expression | -| -| 0| 107| -| -|FIFO | -| -| -| -| -| -|Instance | -| -| -| -| -| -|Memory | -| -| -| -| -| -|Multiplexer | -| -| -| 72| -| -|Register | -| -| 79| -| -| -+-----------------+---------+-------+--------+-------+-----+ -|Total | 0| 0| 79| 179| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Available | 280| 220| 106400| 53200| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Utilization (%) | 0| 0| ~0 | ~0 | 0| -+-----------------+---------+-------+--------+-------+-----+ - -+ Detail: - * Instance: - N/A - - * DSP48E: - N/A - - * Memory: - N/A - - * FIFO: - N/A - - * Expression: - +----------------------+----------+-------+---+----+------------+------------+ - | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| - +----------------------+----------+-------+---+----+------------+------------+ - |add_ln52_1_fu_139_p2 | + | 0| 0| 12| 12| 12| - |add_ln52_fu_129_p2 | + | 0| 0| 39| 32| 32| - |i3_fu_99_p2 | + | 0| 0| 15| 6| 1| - |j3_fu_123_p2 | + | 0| 0| 15| 6| 1| - |icmp_ln46_fu_93_p2 | icmp | 0| 0| 11| 6| 7| - |icmp_ln47_fu_117_p2 | icmp | 0| 0| 11| 6| 7| - |ap_block_state1 | or | 0| 0| 2| 1| 1| - |ap_block_state3 | or | 0| 0| 2| 1| 1| - +----------------------+----------+-------+---+----+------------+------------+ - |Total | | 0| 0| 107| 70| 62| - +----------------------+----------+-------+---+----+------------+------------+ - - * Multiplexer: - +------------------+----+-----------+-----+-----------+ - | Name | LUT| Input Size| Bits| Total Bits| - +------------------+----+-----------+-----+-----------+ - |D_pipe_2_V_blk_n | 9| 2| 1| 2| - |E_pipe_3_V_blk_n | 9| 2| 1| 2| - |ap_NS_fsm | 27| 5| 1| 5| - |ap_done | 9| 2| 1| 2| - |i3_0_reg_71 | 9| 2| 6| 12| - |j3_0_reg_82 | 9| 2| 6| 12| - +------------------+----+-----------+-----+-----------+ - |Total | 72| 15| 16| 35| - +------------------+----+-----------+-----+-----------+ - - * Register: - +--------------------+----+----+-----+-----------+ - | Name | FF | LUT| Bits| Const Bits| - +--------------------+----+----+-----+-----------+ - |add_ln52_1_reg_174 | 12| 0| 12| 0| - |add_ln52_reg_169 | 32| 0| 32| 0| - |ap_CS_fsm | 4| 0| 4| 0| - |ap_done_reg | 1| 0| 1| 0| - |i3_0_reg_71 | 6| 0| 6| 0| - |i3_reg_151 | 6| 0| 6| 0| - |j3_0_reg_82 | 6| 0| 6| 0| - |j3_reg_164 | 6| 0| 6| 0| - |zext_ln47_reg_156 | 6| 0| 12| 6| - +--------------------+----+----+-----+-----------+ - |Total | 79| 0| 85| 6| - +--------------------+----+----+-----+-----------+ - - - -================================================================ -== Interface -================================================================ -* Summary: -+--------------------+-----+-----+------------+-----------------+--------------+ -| RTL Ports | Dir | Bits| Protocol | Source Object | C Type | -+--------------------+-----+-----+------------+-----------------+--------------+ -|ap_clk | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|ap_rst | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|ap_start | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|ap_done | out | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|ap_continue | in | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|ap_idle | out | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|ap_ready | out | 1| ap_ctrl_hs | Loop_F_i3_proc7 | return value | -|D_pipe_2_V_dout | in | 32| ap_fifo | D_pipe_2_V | pointer | -|D_pipe_2_V_empty_n | in | 1| ap_fifo | D_pipe_2_V | pointer | -|D_pipe_2_V_read | out | 1| ap_fifo | D_pipe_2_V | pointer | -|E_pipe_3_V_dout | in | 32| ap_fifo | E_pipe_3_V | pointer | -|E_pipe_3_V_empty_n | in | 1| ap_fifo | E_pipe_3_V | pointer | -|E_pipe_3_V_read | out | 1| ap_fifo | E_pipe_3_V | pointer | -|F_address0 | out | 10| ap_memory | F | array | -|F_ce0 | out | 1| ap_memory | F | array | -|F_we0 | out | 1| ap_memory | F | array | -|F_d0 | out | 32| ap_memory | F | array | -+--------------------+-----+-----+------------+-----------------+--------------+ - diff --git a/tests/test_report_data/stages_report/test_csynth.rpt b/tests/test_report_data/stages_report/test_csynth.rpt deleted file mode 100644 index 77e8a92d6..000000000 --- a/tests/test_report_data/stages_report/test_csynth.rpt +++ /dev/null @@ -1,190 +0,0 @@ - - -================================================================ -== Vivado HLS Report for 'test' -================================================================ -* Date: Mon Feb 21 13:58:41 2022 - -* Version: 2019.1.3 (Build 2642998 on Wed Sep 04 10:25:22 MDT 2019) -* Project: out.prj -* Solution: solution1 -* Product family: zynq -* Target device: xc7z020-clg484-1 - - -================================================================ -== Performance Estimates -================================================================ -+ Timing (ns): - * Summary: - +--------+-------+----------+------------+ - | Clock | Target| Estimated| Uncertainty| - +--------+-------+----------+------------+ - |ap_clk | 10.00| 6.186| 1.25| - +--------+-------+----------+------------+ - -+ Latency (clock cycles): - * Summary: - +------+------+------+------+----------+ - | Latency | Interval | Pipeline | - | min | max | min | max | Type | - +------+------+------+------+----------+ - | 3137| 3137| 3138| 3138| dataflow | - +------+------+------+------+----------+ - - + Detail: - * Instance: - +--------------------+-----------------+------+------+------+------+---------+ - | | | Latency | Interval | Pipeline| - | Instance | Module | min | max | min | max | Type | - +--------------------+-----------------+------+------+------+------+---------+ - |Loop_B_i_proc4_U0 |Loop_B_i_proc4 | 3137| 3137| 3137| 3137| none | - |Loop_E_i2_proc6_U0 |Loop_E_i2_proc6 | 3137| 3137| 3137| 3137| none | - |Loop_F_i3_proc7_U0 |Loop_F_i3_proc7 | 2113| 2113| 2113| 2113| none | - |Loop_D_i1_proc5_U0 |Loop_D_i1_proc5 | 2113| 2113| 2113| 2113| none | - +--------------------+-----------------+------+------+------+------+---------+ - - * Loop: - N/A - - - -================================================================ -== Utilization Estimates -================================================================ -* Summary: -+-----------------+---------+-------+--------+-------+-----+ -| Name | BRAM_18K| DSP48E| FF | LUT | URAM| -+-----------------+---------+-------+--------+-------+-----+ -|DSP | -| -| -| -| -| -|Expression | -| -| 0| 32| -| -|FIFO | 0| -| 15| 132| -| -|Instance | -| -| 278| 712| -| -|Memory | -| -| -| -| -| -|Multiplexer | -| -| -| 36| -| -|Register | -| -| 6| -| -| -+-----------------+---------+-------+--------+-------+-----+ -|Total | 0| 0| 299| 912| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Available | 280| 220| 106400| 53200| 0| -+-----------------+---------+-------+--------+-------+-----+ -|Utilization (%) | 0| 0| ~0 | 1| 0| -+-----------------+---------+-------+--------+-------+-----+ - -+ Detail: - * Instance: - +--------------------+-----------------+---------+-------+----+-----+-----+ - | Instance | Module | BRAM_18K| DSP48E| FF | LUT | URAM| - +--------------------+-----------------+---------+-------+----+-----+-----+ - |Loop_B_i_proc4_U0 |Loop_B_i_proc4 | 0| 0| 69| 183| 0| - |Loop_D_i1_proc5_U0 |Loop_D_i1_proc5 | 0| 0| 61| 167| 0| - |Loop_E_i2_proc6_U0 |Loop_E_i2_proc6 | 0| 0| 69| 183| 0| - |Loop_F_i3_proc7_U0 |Loop_F_i3_proc7 | 0| 0| 79| 179| 0| - +--------------------+-----------------+---------+-------+----+-----+-----+ - |Total | | 0| 0| 278| 712| 0| - +--------------------+-----------------+---------+-------+----+-----+-----+ - - * DSP48E: - N/A - - * Memory: - N/A - - * FIFO: - +--------------+---------+---+----+-----+------+-----+---------+ - | Name | BRAM_18K| FF| LUT| URAM| Depth| Bits| Size:D*B| - +--------------+---------+---+----+-----+------+-----+---------+ - |B_pipe_1_V_U | 0| 5| 0| -| 1| 32| 32| - |D_pipe_2_V_U | 0| 5| 0| -| 1| 32| 32| - |E_pipe_3_V_U | 0| 5| 0| -| 1| 32| 32| - +--------------+---------+---+----+-----+------+-----+---------+ - |Total | 0| 15| 0| 0| 3| 96| 96| - +--------------+---------+---+----+-----+------+-----+---------+ - - * Expression: - +-------------------------------------+----------+-------+---+----+------------+------------+ - | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| - +-------------------------------------+----------+-------+---+----+------------+------------+ - |Loop_B_i_proc4_U0_ap_ready_count | + | 0| 0| 10| 2| 1| - |Loop_E_i2_proc6_U0_ap_ready_count | + | 0| 0| 10| 2| 1| - |Loop_B_i_proc4_U0_ap_start | and | 0| 0| 2| 1| 1| - |Loop_E_i2_proc6_U0_ap_start | and | 0| 0| 2| 1| 1| - |ap_idle | and | 0| 0| 2| 1| 1| - |ap_sync_ready | and | 0| 0| 2| 1| 1| - |ap_sync_Loop_B_i_proc4_U0_ap_ready | or | 0| 0| 2| 1| 1| - |ap_sync_Loop_E_i2_proc6_U0_ap_ready | or | 0| 0| 2| 1| 1| - +-------------------------------------+----------+-------+---+----+------------+------------+ - |Total | | 0| 0| 32| 10| 8| - +-------------------------------------+----------+-------+---+----+------------+------------+ - - * Multiplexer: - +-----------------------------------------+----+-----------+-----+-----------+ - | Name | LUT| Input Size| Bits| Total Bits| - +-----------------------------------------+----+-----------+-----+-----------+ - |Loop_B_i_proc4_U0_ap_ready_count | 9| 2| 2| 4| - |Loop_E_i2_proc6_U0_ap_ready_count | 9| 2| 2| 4| - |ap_sync_reg_Loop_B_i_proc4_U0_ap_ready | 9| 2| 1| 2| - |ap_sync_reg_Loop_E_i2_proc6_U0_ap_ready | 9| 2| 1| 2| - +-----------------------------------------+----+-----------+-----+-----------+ - |Total | 36| 8| 6| 12| - +-----------------------------------------+----+-----------+-----+-----------+ - - * Register: - +-----------------------------------------+---+----+-----+-----------+ - | Name | FF| LUT| Bits| Const Bits| - +-----------------------------------------+---+----+-----+-----------+ - |Loop_B_i_proc4_U0_ap_ready_count | 2| 0| 2| 0| - |Loop_E_i2_proc6_U0_ap_ready_count | 2| 0| 2| 0| - |ap_sync_reg_Loop_B_i_proc4_U0_ap_ready | 1| 0| 1| 0| - |ap_sync_reg_Loop_E_i2_proc6_U0_ap_ready | 1| 0| 1| 0| - +-----------------------------------------+---+----+-----+-----------+ - |Total | 6| 0| 6| 0| - +-----------------------------------------+---+----+-----+-----------+ - - - -================================================================ -== Interface -================================================================ -* Summary: -+------------+-----+-----+------------+--------------+--------------+ -| RTL Ports | Dir | Bits| Protocol | Source Object| C Type | -+------------+-----+-----+------------+--------------+--------------+ -|A_address0 | out | 10| ap_memory | A | array | -|A_ce0 | out | 1| ap_memory | A | array | -|A_d0 | out | 32| ap_memory | A | array | -|A_q0 | in | 32| ap_memory | A | array | -|A_we0 | out | 1| ap_memory | A | array | -|A_address1 | out | 10| ap_memory | A | array | -|A_ce1 | out | 1| ap_memory | A | array | -|A_d1 | out | 32| ap_memory | A | array | -|A_q1 | in | 32| ap_memory | A | array | -|A_we1 | out | 1| ap_memory | A | array | -|C_address0 | out | 10| ap_memory | C | array | -|C_ce0 | out | 1| ap_memory | C | array | -|C_d0 | out | 32| ap_memory | C | array | -|C_q0 | in | 32| ap_memory | C | array | -|C_we0 | out | 1| ap_memory | C | array | -|C_address1 | out | 10| ap_memory | C | array | -|C_ce1 | out | 1| ap_memory | C | array | -|C_d1 | out | 32| ap_memory | C | array | -|C_q1 | in | 32| ap_memory | C | array | -|C_we1 | out | 1| ap_memory | C | array | -|F_address0 | out | 10| ap_memory | F | array | -|F_ce0 | out | 1| ap_memory | F | array | -|F_d0 | out | 32| ap_memory | F | array | -|F_q0 | in | 32| ap_memory | F | array | -|F_we0 | out | 1| ap_memory | F | array | -|F_address1 | out | 10| ap_memory | F | array | -|F_ce1 | out | 1| ap_memory | F | array | -|F_d1 | out | 32| ap_memory | F | array | -|F_q1 | in | 32| ap_memory | F | array | -|F_we1 | out | 1| ap_memory | F | array | -|ap_clk | in | 1| ap_ctrl_hs | test | return value | -|ap_rst | in | 1| ap_ctrl_hs | test | return value | -|ap_start | in | 1| ap_ctrl_hs | test | return value | -|ap_done | out | 1| ap_ctrl_hs | test | return value | -|ap_ready | out | 1| ap_ctrl_hs | test | return value | -|ap_idle | out | 1| ap_ctrl_hs | test | return value | -+------------+-----+-----+------------+--------------+--------------+ -