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*** Running vivado
with args -log user_proj_example.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source user_proj_example.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source user_proj_example.tcl -notrace
Command: read_checkpoint -auto_incremental -incremental /home/ubuntu/Desktop/project_3/project_3.srcs/utils_1/imports/synth_1/user_proj_example.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from /home/ubuntu/Desktop/project_3/project_3.srcs/utils_1/imports/synth_1/user_proj_example.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top user_proj_example -part xc7z020clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 40865
WARNING: [Synth 8-9887] parameter declaration becomes local in 'fir' with formal parameter declaration list [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:48]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'fir' with formal parameter declaration list [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:48]
CRITICAL WARNING: [Synth 8-9873] overwriting previous definition of module 'fir' [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:473]
INFO: [Synth 8-9937] previous definition of design element 'fir' is here [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:473]
CRITICAL WARNING: [Synth 8-9873] overwriting previous definition of module 'bram11' [/home/ubuntu/lab-caravel_fir/rtl/user/bram11.v:21]
INFO: [Synth 8-9937] previous definition of design element 'bram11' is here [/home/ubuntu/lab-caravel_fir/rtl/user/bram11.v:21]
WARNING: [Synth 8-9971] redeclaration of ansi port 'io_in' is not allowed [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:84]
WARNING: [Synth 8-9971] redeclaration of ansi port 'io_out' is not allowed [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:85]
WARNING: [Synth 8-9971] redeclaration of ansi port 'io_oeb' is not allowed [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:86]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 5359 ; free virtual = 10916
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'user_proj_example' [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:44]
INFO: [Synth 8-6157] synthesizing module 'bram' [/home/ubuntu/lab-caravel_fir/rtl/user/bram.v:1]
INFO: [Synth 8-6155] done synthesizing module 'bram' (0#1) [/home/ubuntu/lab-caravel_fir/rtl/user/bram.v:1]
INFO: [Synth 8-6157] synthesizing module 'WBtoAXI' [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:361]
INFO: [Synth 8-6155] done synthesizing module 'WBtoAXI' (0#1) [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:361]
INFO: [Synth 8-6157] synthesizing module 'fir' [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:1]
INFO: [Synth 8-6155] done synthesizing module 'fir' (0#1) [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:1]
INFO: [Synth 8-6157] synthesizing module 'bram11' [/home/ubuntu/lab-caravel_fir/rtl/user/bram11.v:2]
INFO: [Synth 8-6155] done synthesizing module 'bram11' (0#1) [/home/ubuntu/lab-caravel_fir/rtl/user/bram11.v:2]
INFO: [Synth 8-6155] done synthesizing module 'user_proj_example' (0#1) [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:44]
WARNING: [Synth 8-6014] Unused sequential element last_data_reg was removed. [/home/ubuntu/lab-caravel_fir/rtl/user/fir.v:331]
WARNING: [Synth 8-3848] Net la_data_out in module/entity user_proj_example does not have driver. [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:70]
WARNING: [Synth 8-3848] Net io_out in module/entity user_proj_example does not have driver. [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:75]
WARNING: [Synth 8-3848] Net io_oeb in module/entity user_proj_example does not have driver. [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:76]
WARNING: [Synth 8-3848] Net irq in module/entity user_proj_example does not have driver. [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:79]
WARNING: [Synth 8-7129] Port waddr[11] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[10] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[9] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[8] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[7] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[6] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[5] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port waddr[4] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[11] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[10] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[9] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[8] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[7] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[6] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[5] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr[4] in module bram11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ss_tlast in module fir is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_sel_i[3] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_sel_i[2] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_sel_i[1] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_sel_i[0] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[23] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[22] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[21] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[20] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[19] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[18] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[17] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[16] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[15] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[14] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[13] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port wbs_adr_i[12] in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port sm_tlast in module WBtoAXI is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[31] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[30] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[29] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[28] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[27] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[26] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[25] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[24] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[23] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[22] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[21] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[20] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[19] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[18] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[17] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[16] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[15] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[14] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[13] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[12] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[11] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port A0[10] in module bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[127] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[126] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[125] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[124] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[123] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[122] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[121] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[120] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[119] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[118] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[117] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[116] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[115] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[114] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[113] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[112] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[111] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[110] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[109] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[108] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[107] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[106] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[105] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[104] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[103] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[102] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[101] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[100] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[99] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[98] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[97] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[96] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[95] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[94] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[93] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[92] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[91] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[90] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[89] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[88] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[87] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[86] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[85] in module user_proj_example is either unconnected or has no load
WARNING: [Synth 8-7129] Port la_data_out[84] in module user_proj_example is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 6370 ; free virtual = 11928
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 6421 ; free virtual = 11979
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 6421 ; free virtual = 11979
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 6421 ; free virtual = 11979
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ubuntu/Desktop/project_3/project_3.srcs/constrs_1/new/c.xdc]
Finished Parsing XDC File [/home/ubuntu/Desktop/project_3/project_3.srcs/constrs_1/new/c.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2919.086 ; gain = 0.000 ; free physical = 6355 ; free virtual = 11913
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2919.086 ; gain = 0.000 ; free physical = 6355 ; free virtual = 11913
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6411 ; free virtual = 11969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6411 ; free virtual = 11969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6411 ; free virtual = 11969
---------------------------------------------------------------------------------
WARNING: [Synth 8-327] inferring latch for variable 'wbs_dat_o_reg' [/home/ubuntu/lab-caravel_fir/rtl/user/user_proj_example.counter.v:499]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6411 ; free virtual = 11970
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
2 Input 12 Bit Adders := 3
2 Input 10 Bit Adders := 1
2 Input 6 Bit Adders := 1
2 Input 4 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
32 Bit Registers := 10
12 Bit Registers := 2
10 Bit Registers := 1
6 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 16
+---Multipliers :
32x32 Multipliers := 1
+---RAMs :
32K Bit (1024 X 32 bit) RAMs := 1
352 Bit (11 X 32 bit) RAMs := 2
+---Muxes :
2 Input 32 Bit Muxes := 19
3 Input 32 Bit Muxes := 1
2 Input 12 Bit Muxes := 2
2 Input 10 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
6 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 22
3 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP fir_v/mult_result, operation Mode is: A2*B.
DSP Report: register fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: Generating DSP fir_v/mult_result, operation Mode is: (PCIN>>17)+A*B2.
DSP Report: register tap_ram/rdo_reg is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: Generating DSP fir_v/mult_result, operation Mode is: A*B2.
DSP Report: register fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: Generating DSP fir_v/mult_result, operation Mode is: (PCIN>>17)+A*B2.
DSP Report: register tap_ram/rdo_reg is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
DSP Report: operator fir_v/mult_result is absorbed into DSP fir_v/mult_result.
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6379 ; free virtual = 11942
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
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Block RAM: Preliminary Mapping Report (see note below)
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|bram: | RAM_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+------------------+------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------------+------------------+-----------+----------------------+----------------+
|user_proj_example | tap_ram/RAM_reg | Implied | 16 x 32 | RAM16X1S x 32 |
|user_proj_example | data_ram/RAM_reg | Implied | 16 x 32 | RAM16X1S x 32 |
+------------------+------------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|user_proj_example | A2*B | 18 | 15 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|user_proj_example | (PCIN>>17)+A*B2 | 15 | 15 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|user_proj_example | A*B2 | 18 | 18 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|user_proj_example | (PCIN>>17)+A*B2 | 18 | 15 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
+------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6248 ; free virtual = 11811
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6218 ; free virtual = 11781
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|bram: | RAM_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+------------------+------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------------+------------------+-----------+----------------------+----------------+
|user_proj_example | tap_ram/RAM_reg | Implied | 16 x 32 | RAM16X1S x 32 |
|user_proj_example | data_ram/RAM_reg | Implied | 16 x 32 | RAM16X1S x 32 |
+------------------+------------------+-----------+----------------------+----------------+
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
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Start Technology Mapping
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INFO: [Synth 8-7052] The timing for the instance user_bram/RAM_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11777
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Start Writing Synthesis Report
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DSP Final Report (the ' indicates corresponding REG is set)
+------------------+---------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------------+---------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|user_proj_example | A'*B | 17 | 18 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|user_proj_example | A*B' | 17 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|user_proj_example | PCIN>>17+A*B' | 17 | 18 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
+------------------+---------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 27|
|3 |DSP48E1 | 3|
|5 |LUT1 | 32|
|6 |LUT2 | 176|
|7 |LUT3 | 57|
|8 |LUT4 | 70|
|9 |LUT5 | 82|
|10 |LUT6 | 137|
|11 |RAM16X1S | 64|
|12 |RAMB36E1 | 1|
|13 |FDCE | 269|
|14 |FDPE | 4|
|15 |FDRE | 104|
|16 |LD | 32|
|17 |IBUF | 61|
|18 |OBUF | 33|
|19 |OBUFT | 207|
+------+---------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 6213 ; free virtual = 11776
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Synthesis finished with 0 errors, 0 critical warnings and 503 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2919.086 ; gain = 0.000 ; free physical = 6266 ; free virtual = 11829
Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.094 ; gain = 16.008 ; free physical = 6266 ; free virtual = 11829
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2919.094 ; gain = 0.000 ; free physical = 6361 ; free virtual = 11924
INFO: [Netlist 29-17] Analyzing 127 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2919.094 ; gain = 0.000 ; free physical = 6313 ; free virtual = 11876
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 96 instances were transformed.
LD => LDCE: 32 instances
RAM16X1S => RAM32X1S (RAMS32): 64 instances
Synth Design complete, checksum: e6ba1d78
INFO: [Common 17-83] Releasing license: Synthesis
34 Infos, 112 Warnings, 2 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2919.094 ; gain = 16.016 ; free physical = 6519 ; free virtual = 12082
INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
INFO: [Common 17-1381] The checkpoint '/home/ubuntu/Desktop/project_3/project_3.runs/synth_1/user_proj_example.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file user_proj_example_utilization_synth.rpt -pb user_proj_example_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Nov 4 10:00:44 2023...