Running Riscduino in Openlane

[Parthatgit]

Hello Dinesh sir,
I am trying to run the Riscduino soc using openlane toolflow, but it seems that I keep running into problems with on step 4, where the flow uses tries to use pin_order.cfg file, but after trying multipl variations in the format and value in this file, it keeps giving me the same error that I will attach below.
Additionally on designs like DFFRAM, where I made my own config.json and .sdc file, it runs into some problem on step 26, detailed routing, for some reason the flow gets killed. It can't be due to storage, as I have tried it on a setup with 1TB memory.
Can you suggest any changes that we need to make in the designs to make it openlane compatible or point me to an updated resource. I have already used Openlane documentation as a reference.
Thanks