30 30 ****** START compiling Program:Test3(struct) (MethodHash=f3234b3d) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: Stack probing is DISABLED IL to import: IL_0000 02 ldarg.0 IL_0001 7b 01 00 00 04 ldfld 0x4000001 IL_0006 02 ldarg.0 IL_0007 7b 01 00 00 04 ldfld 0x4000001 IL_000c 5a mul IL_000d 02 ldarg.0 IL_000e 7b 02 00 00 04 ldfld 0x4000002 IL_0013 02 ldarg.0 IL_0014 7b 02 00 00 04 ldfld 0x4000002 IL_0019 5a mul IL_001a 58 add IL_001b 02 ldarg.0 IL_001c 7b 03 00 00 04 ldfld 0x4000003 IL_0021 02 ldarg.0 IL_0022 7b 03 00 00 04 ldfld 0x4000003 IL_0027 5a mul IL_0028 58 add IL_0029 02 ldarg.0 IL_002a 7b 04 00 00 04 ldfld 0x4000004 IL_002f 02 ldarg.0 IL_0030 7b 04 00 00 04 ldfld 0x4000004 IL_0035 5a mul IL_0036 58 add IL_0037 28 06 00 00 0a call 0xA000006 IL_003c 2a ret Set preferred register for V00 to [rcx] Arg #0 passed in register(s) rcx ; Initial local variable assignments ; ; V00 arg0 struct (16) *************** In compInitDebuggingInfo() for Program:Test3(struct) getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 1 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 03Dh info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Program:Test3(struct) Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..03D) IL Code Size,Instr 61, 25, Basic Block count 1, Local Variable Num,Ref count 1, 8 for method Program:Test3(struct) OPTIONS: opts.MinOpts() == false Basic block list for 'Program:Test3(struct)' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..03D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Program:Test3(struct) impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Program:Test3(struct)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000001 [ 1] 6 (0x006) ldarg.0 [ 2] 7 (0x007) ldfld 04000001 [ 2] 12 (0x00c) mul [ 1] 13 (0x00d) ldarg.0 [ 2] 14 (0x00e) ldfld 04000002 [ 2] 19 (0x013) ldarg.0 [ 3] 20 (0x014) ldfld 04000002 [ 3] 25 (0x019) mul [ 2] 26 (0x01a) add [ 1] 27 (0x01b) ldarg.0 [ 2] 28 (0x01c) ldfld 04000003 [ 2] 33 (0x021) ldarg.0 [ 3] 34 (0x022) ldfld 04000003 [ 3] 39 (0x027) mul [ 2] 40 (0x028) add [ 1] 41 (0x029) ldarg.0 [ 2] 42 (0x02a) ldfld 04000004 [ 2] 47 (0x02f) ldarg.0 [ 3] 48 (0x030) ldfld 04000004 [ 3] 53 (0x035) mul [ 2] 54 (0x036) add [ 1] 55 (0x037) call 0A000006 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 info.compCompHnd->canTailCall returned false for call [000032] INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Program:Test3(struct)' calling 'System.Console:WriteLine(float)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000034] ------------ * STMT void (IL 0x000... ???) [000032] --C-G------- \--* CALL void System.Console.WriteLine [000029] ----G------- | /--* FIELD float W [000028] L----------- | | \--* ADDR byref [000027] ------------ | | \--* LCL_VAR struct V00 arg0 [000030] ----G------- | /--* MUL float [000026] ----G------- | | \--* FIELD float W [000025] L----------- | | \--* ADDR byref [000024] ------------ | | \--* LCL_VAR struct V00 arg0 [000031] ----G------- arg0 \--* ADD float [000021] ----G------- | /--* FIELD float Z [000020] L----------- | | \--* ADDR byref [000019] ------------ | | \--* LCL_VAR struct V00 arg0 [000022] ----G------- | /--* MUL float [000018] ----G------- | | \--* FIELD float Z [000017] L----------- | | \--* ADDR byref [000016] ------------ | | \--* LCL_VAR struct V00 arg0 [000023] ----G------- \--* ADD float [000013] ----G------- | /--* FIELD float Y [000012] L----------- | | \--* ADDR byref [000011] ------------ | | \--* LCL_VAR struct V00 arg0 [000014] ----G------- | /--* MUL float [000010] ----G------- | | \--* FIELD float Y [000009] L----------- | | \--* ADDR byref [000008] ------------ | | \--* LCL_VAR struct V00 arg0 [000015] ----G------- \--* ADD float [000006] ----G------- | /--* FIELD float X [000005] L----------- | | \--* ADDR byref [000004] ------------ | | \--* LCL_VAR struct V00 arg0 [000007] ----G------- \--* MUL float [000003] ----G------- \--* FIELD float X [000002] L----------- \--* ADDR byref [000001] ------------ \--* LCL_VAR struct V00 arg0 [ 0] 60 (0x03c) ret [000036] ------------ * STMT void (IL 0x03C... ???) [000035] ------------ \--* RETURN void New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgMorph() *************** In fgDebugCheckBBlist *************** In fgInline() *************** After fgInline() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..03D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..03D) (return), preds={} succs={} ***** BB01, stmt 1 [000034] ------------ * STMT void (IL 0x000...0x03C) [000032] --C-G------- \--* CALL void System.Console.WriteLine [000029] ----G------- | /--* FIELD float W [000028] L----------- | | \--* ADDR byref [000027] ------------ | | \--* LCL_VAR struct V00 arg0 [000030] ----G------- | /--* MUL float [000026] ----G------- | | \--* FIELD float W [000025] L----------- | | \--* ADDR byref [000024] ------------ | | \--* LCL_VAR struct V00 arg0 [000031] ----G------- arg0 \--* ADD float [000021] ----G------- | /--* FIELD float Z [000020] L----------- | | \--* ADDR byref [000019] ------------ | | \--* LCL_VAR struct V00 arg0 [000022] ----G------- | /--* MUL float [000018] ----G------- | | \--* FIELD float Z [000017] L----------- | | \--* ADDR byref [000016] ------------ | | \--* LCL_VAR struct V00 arg0 [000023] ----G------- \--* ADD float [000013] ----G------- | /--* FIELD float Y [000012] L----------- | | \--* ADDR byref [000011] ------------ | | \--* LCL_VAR struct V00 arg0 [000014] ----G------- | /--* MUL float [000010] ----G------- | | \--* FIELD float Y [000009] L----------- | | \--* ADDR byref [000008] ------------ | | \--* LCL_VAR struct V00 arg0 [000015] ----G------- \--* ADD float [000006] ----G------- | /--* FIELD float X [000005] L----------- | | \--* ADDR byref [000004] ------------ | | \--* LCL_VAR struct V00 arg0 [000007] ----G------- \--* MUL float [000003] ----G------- \--* FIELD float X [000002] L----------- \--* ADDR byref [000001] ------------ \--* LCL_VAR struct V00 arg0 ***** BB01, stmt 2 [000036] ------------ * STMT void (IL 0x03C... ???) [000035] ------------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty **************** Inline Tree Inlines into 06000004 Program:Test3(struct) [0 IL=0055 TR=000032 0600007D] [FAILED: noinline per IL/cached result] System.Console:WriteLine(float) Budget: initialTime=243, finalTime=243, initialBudget=2430, currentBudget=2430 Budget: initialSize=1522, finalSize=1522 *************** After fgAddInternal() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..03D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** In fgRemoveEmptyFinally() No EH in this method, nothing to remove. *************** In fgMergeFinallyChains() No EH in this method, nothing to merge. *************** In fgCloneFinally() No EH in this method, no cloning. *************** In fgMarkImplicitByRefs() *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 struct (16) Promoting struct local V00 (Vector4): lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for field V00.X (fldOffset=0x0). New refCnts for V01: refCnt = 1, refCntWtd = 1 lvaGrabTemp returning 2 (V02 tmp1) (a long lifetime temp) called for field V00.Y (fldOffset=0x4). New refCnts for V02: refCnt = 1, refCntWtd = 1 lvaGrabTemp returning 3 (V03 tmp2) (a long lifetime temp) called for field V00.Z (fldOffset=0x8). New refCnts for V03: refCnt = 1, refCntWtd = 1 lvaGrabTemp returning 4 (V04 tmp3) (a long lifetime temp) called for field V00.W (fldOffset=0xc). New refCnts for V04: refCnt = 1, refCntWtd = 1 lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 struct (16) ; V01 tmp0 float V00.X(offs=0x00) P-INDEP ; V02 tmp1 float V00.Y(offs=0x04) P-INDEP ; V03 tmp2 float V00.Z(offs=0x08) P-INDEP ; V04 tmp3 float V00.W(offs=0x0c) P-INDEP *************** In fgMarkAddressExposedLocals() Incrementing ref count from 0 to 1 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 1 to 2 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 2 to 3 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 3 to 4 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 4 to 5 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 5 to 6 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 6 to 7 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: Incrementing ref count from 7 to 8 for V00 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: [000032] --C-G------- * CALL void System.Console.WriteLine [000029] ------------ | /--* LCL_VAR float V04 tmp3 [000030] ----G------- | /--* MUL float [000026] ------------ | | \--* LCL_VAR float V04 tmp3 [000031] ----G------- arg0 \--* ADD float [000021] ------------ | /--* LCL_VAR float V03 tmp2 [000022] ----G------- | /--* MUL float [000018] ------------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G------- \--* ADD float [000013] ------------ | /--* LCL_VAR float V02 tmp1 [000014] ----G------- | /--* MUL float [000010] ------------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G------- \--* ADD float [000006] ------------ | /--* LCL_VAR float V01 tmp0 [000007] ----G------- \--* MUL float [000003] ------------ \--* LCL_VAR float V01 tmp0 *************** In fgRetypeImplicitByRefArgs() lvaGrabTemp returning 5 (V05 tmp4) (a long lifetime temp) called for Promoted implicit byref. New Basic Block BB02 [0001] created. New scratch BB02 Changing the lvType for struct parameter V00 to TYP_BYREF. *************** In fgMorphBlocks() Morphing BB02 of 'Program:Test3(struct)' fgMorphTree BB02, stmt 1 (before) [000039] ------------ /--* BLK(16) struct [000038] ------------ | \--* LCL_VAR byref (P?!) V00 arg0 [000040] -A---------- * ASG struct (copy) [000037] D------N---- \--* LCL_VAR struct(P) V05 tmp4 \--* float V05.X (offs=0x00) -> V01 tmp0 \--* float V05.Y (offs=0x04) -> V02 tmp1 \--* float V05.Z (offs=0x08) -> V03 tmp2 \--* float V05.W (offs=0x0c) -> V04 tmp3 fgMorphCopyBlock:block assignment to morph: [000039] x----+------ /--* BLK(16) struct [000038] -----+------ | \--* LCL_VAR byref (P?!) V00 arg0 [000040] -A---------- * ASG struct (copy) [000037] D----+-N---- \--* LCL_VAR struct(P) V05 tmp4 \--* float V05.X (offs=0x00) -> V01 tmp0 \--* float V05.Y (offs=0x04) -> V02 tmp1 \--* float V05.Z (offs=0x08) -> V03 tmp2 \--* float V05.W (offs=0x0c) -> V04 tmp3 (destDoFldAsg=true) using field by field assignments. fgMorphCopyBlock (after): [000067] x----------- /--* IND float [000065] ------------ | | /--* CNS_INT long 12 Fseq[W] [000066] ------------ | \--* ADD byref [000064] ------------ | \--* LCL_VAR byref (P?!) V00 arg0 [000068] -A---------- /--* ASG float [000063] D------N---- | \--* LCL_VAR float V04 tmp3 [000069] -A---+------ * COMMA void [000060] x----------- | /--* IND float [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] [000059] ------------ | | \--* ADD byref [000057] ------------ | | \--* LCL_VAR byref (P?!) V00 arg0 [000061] -A---------- | /--* ASG float [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 [000062] -A---------- \--* COMMA void [000053] x----------- | /--* IND float [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] [000052] ------------ | | \--* ADD byref [000050] ------------ | | \--* LCL_VAR byref (P?!) V00 arg0 [000054] -A---------- | /--* ASG float [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 [000055] -A---------- \--* COMMA void [000047] x----------- | /--* IND float [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] [000046] ------------ | | \--* ADD byref [000044] ------------ | | \--* LCL_VAR byref (P?!) V00 arg0 [000048] -A---------- \--* ASG float [000043] D------N---- \--* LCL_VAR float V01 tmp0 fgMorphTree BB02, stmt 1 (after) [000067] x----------- /--* IND float [000065] ------------ | | /--* CNS_INT long 12 Fseq[W] [000066] ------------ | \--* ADD byref [000064] ------------ | \--* LCL_VAR byref (P?!) V00 arg0 [000068] -A---------- /--* ASG float [000063] D------N---- | \--* LCL_VAR float V04 tmp3 [000069] -A---+------ * COMMA void [000060] x----------- | /--* IND float [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] [000059] ------------ | | \--* ADD byref [000057] ------------ | | \--* LCL_VAR byref (P?!) V00 arg0 [000061] -A---------- | /--* ASG float [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 [000062] -A---------- \--* COMMA void [000053] x----------- | /--* IND float [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] [000052] ------------ | | \--* ADD byref [000050] ------------ | | \--* LCL_VAR byref (P?!) V00 arg0 [000054] -A---------- | /--* ASG float [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 [000055] -A---------- \--* COMMA void [000047] x----------- | /--* IND float [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] [000046] ------------ | | \--* ADD byref [000044] ------------ | | \--* LCL_VAR byref (P?!) V00 arg0 [000048] -A---------- \--* ASG float [000043] D------N---- \--* LCL_VAR float V01 tmp0 Morphing BB01 of 'Program:Test3(struct)' fgMorphTree BB01, stmt 2 (before) [000032] --C-G------- * CALL void System.Console.WriteLine [000029] ------------ | /--* LCL_VAR float V04 tmp3 [000030] ----G------- | /--* MUL float [000026] ------------ | | \--* LCL_VAR float V04 tmp3 [000031] ----G------- arg0 \--* ADD float [000021] ------------ | /--* LCL_VAR float V03 tmp2 [000022] ----G------- | /--* MUL float [000018] ------------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G------- \--* ADD float [000013] ------------ | /--* LCL_VAR float V02 tmp1 [000014] ----G------- | /--* MUL float [000010] ------------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G------- \--* ADD float [000006] ------------ | /--* LCL_VAR float V01 tmp0 [000007] ----G------- \--* MUL float [000003] ------------ \--* LCL_VAR float V01 tmp0 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('mm0'): [000029] -----+------ /--* LCL_VAR float V04 tmp3 [000030] ----G+------ /--* MUL float [000026] -----+------ | \--* LCL_VAR float V04 tmp3 [000031] ----G+------ * ADD float [000021] -----+------ | /--* LCL_VAR float V03 tmp2 [000022] ----G+------ | /--* MUL float [000018] -----+------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G+------ \--* ADD float [000013] -----+------ | /--* LCL_VAR float V02 tmp1 [000014] ----G+------ | /--* MUL float [000010] -----+------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G+------ \--* ADD float [000006] -----+------ | /--* LCL_VAR float V01 tmp0 [000007] ----G+------ \--* MUL float [000003] -----+------ \--* LCL_VAR float V01 tmp0 Replaced with placeholder node: [000070] ----------L- * ARGPLACE float Shuffled argument table: mm0 fgArgTabEntry[arg 0 31.ADD, mm0, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB01, stmt 2 (after) [000032] --CXG+------ * CALL void System.Console.WriteLine [000029] -----+------ | /--* LCL_VAR float V04 tmp3 [000030] ----G+------ | /--* MUL float [000026] -----+------ | | \--* LCL_VAR float V04 tmp3 [000031] ----G+------ arg0 in mm0 \--* ADD float [000021] -----+------ | /--* LCL_VAR float V03 tmp2 [000022] ----G+------ | /--* MUL float [000018] -----+------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G+------ \--* ADD float [000013] -----+------ | /--* LCL_VAR float V02 tmp1 [000014] ----G+------ | /--* MUL float [000010] -----+------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G+------ \--* ADD float [000006] -----+------ | /--* LCL_VAR float V01 tmp0 [000007] ----G+------ \--* MUL float [000003] -----+------ \--* LCL_VAR float V01 tmp0 fgMorphTree BB01, stmt 3 (before) [000035] ------------ * RETURN void Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [???..???) i internal BB01 [0000] 1 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB02 to BB01 Renumber BB01 to BB02 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal BB02 [0000] 1 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 3, bitset array size: 1 (short) *************** In fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal BB02 [0000] 1 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgComputeEdgeWeights() fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- fgComputeEdgeWeights() was able to compute exact edge weights for all of the 1 edges, using 1 passes. Edge weights into BB02 :BB01 (100) *************** In fgCreateFunclets() After fgCreateFunclets() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 After computing reachability: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB02 *************** In Allocate Objects Trees before Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000041] ------------ * STMT void (IL ???... ???) [000067] x----------- | /--* IND float [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] [000066] ------------ | | \--* ADD byref [000064] ------------ | | \--* LCL_VAR byref V00 arg0 [000068] -A---------- | /--* ASG float [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 [000069] -A---+------ \--* COMMA void [000060] x----------- | /--* IND float [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] [000059] ------------ | | \--* ADD byref [000057] ------------ | | \--* LCL_VAR byref V00 arg0 [000061] -A---------- | /--* ASG float [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 [000062] -A---------- \--* COMMA void [000053] x----------- | /--* IND float [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] [000052] ------------ | | \--* ADD byref [000050] ------------ | | \--* LCL_VAR byref V00 arg0 [000054] -A---------- | /--* ASG float [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 [000055] -A---------- \--* COMMA void [000047] x----------- | /--* IND float [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] [000046] ------------ | | \--* ADD byref [000044] ------------ | | \--* LCL_VAR byref V00 arg0 [000048] -A---------- \--* ASG float [000043] D------N---- \--* LCL_VAR float V01 tmp0 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 [000034] ------------ * STMT void (IL 0x000...0x03C) [000032] --CXG+------ \--* CALL void System.Console.WriteLine [000029] -----+------ | /--* LCL_VAR float V04 tmp3 [000030] ----G+------ | /--* MUL float [000026] -----+------ | | \--* LCL_VAR float V04 tmp3 [000031] ----G+------ arg0 in mm0 \--* ADD float [000021] -----+------ | /--* LCL_VAR float V03 tmp2 [000022] ----G+------ | /--* MUL float [000018] -----+------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G+------ \--* ADD float [000013] -----+------ | /--* LCL_VAR float V02 tmp1 [000014] ----G+------ | /--* MUL float [000010] -----+------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G+------ \--* ADD float [000006] -----+------ | /--* LCL_VAR float V01 tmp0 [000007] ----G+------ \--* MUL float [000003] -----+------ \--* LCL_VAR float V01 tmp0 ***** BB02, stmt 3 [000036] ------------ * STMT void (IL 0x03C... ???) [000035] -----+------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Exiting Allocate Objects Trees after Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000041] ------------ * STMT void (IL ???... ???) [000067] x----------- | /--* IND float [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] [000066] ------------ | | \--* ADD byref [000064] ------------ | | \--* LCL_VAR byref V00 arg0 [000068] -A---------- | /--* ASG float [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 [000069] -A---+------ \--* COMMA void [000060] x----------- | /--* IND float [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] [000059] ------------ | | \--* ADD byref [000057] ------------ | | \--* LCL_VAR byref V00 arg0 [000061] -A---------- | /--* ASG float [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 [000062] -A---------- \--* COMMA void [000053] x----------- | /--* IND float [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] [000052] ------------ | | \--* ADD byref [000050] ------------ | | \--* LCL_VAR byref V00 arg0 [000054] -A---------- | /--* ASG float [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 [000055] -A---------- \--* COMMA void [000047] x----------- | /--* IND float [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] [000046] ------------ | | \--* ADD byref [000044] ------------ | | \--* LCL_VAR byref V00 arg0 [000048] -A---------- \--* ASG float [000043] D------N---- \--* LCL_VAR float V01 tmp0 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 [000034] ------------ * STMT void (IL 0x000...0x03C) [000032] --CXG+------ \--* CALL void System.Console.WriteLine [000029] -----+------ | /--* LCL_VAR float V04 tmp3 [000030] ----G+------ | /--* MUL float [000026] -----+------ | | \--* LCL_VAR float V04 tmp3 [000031] ----G+------ arg0 in mm0 \--* ADD float [000021] -----+------ | /--* LCL_VAR float V03 tmp2 [000022] ----G+------ | /--* MUL float [000018] -----+------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G+------ \--* ADD float [000013] -----+------ | /--* LCL_VAR float V02 tmp1 [000014] ----G+------ | /--* MUL float [000010] -----+------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G+------ \--* ADD float [000006] -----+------ | /--* LCL_VAR float V01 tmp0 [000007] ----G+------ \--* MUL float [000003] -----+------ \--* LCL_VAR float V01 tmp0 ***** BB02, stmt 3 [000036] ------------ * STMT void (IL 0x03C... ???) [000035] -----+------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In optOptimizeLoops() *************** In fgDebugCheckBBlist *************** In optCloneLoops() *************** In lvaMarkLocalVars() lvaGrabTemp returning 6 (V06 tmp5) (a long lifetime temp) called for OutgoingArgSpace. *** marking local variables in block BB01 (weight=1 ) [000041] ------------ * STMT void (IL ???... ???) [000067] x----------- | /--* IND float [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] [000066] ------------ | | \--* ADD byref [000064] ------------ | | \--* LCL_VAR byref V00 arg0 [000068] -A---------- | /--* ASG float [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 [000069] -A---+------ \--* COMMA void [000060] x----------- | /--* IND float [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] [000059] ------------ | | \--* ADD byref [000057] ------------ | | \--* LCL_VAR byref V00 arg0 [000061] -A---------- | /--* ASG float [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 [000062] -A---------- \--* COMMA void [000053] x----------- | /--* IND float [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] [000052] ------------ | | \--* ADD byref [000050] ------------ | | \--* LCL_VAR byref V00 arg0 [000054] -A---------- | /--* ASG float [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 [000055] -A---------- \--* COMMA void [000047] x----------- | /--* IND float [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] [000046] ------------ | | \--* ADD byref [000044] ------------ | | \--* LCL_VAR byref V00 arg0 [000048] -A---------- \--* ASG float [000043] D------N---- \--* LCL_VAR float V01 tmp0 New refCnts for V01: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 9, refCntWtd = 2 New refCnts for V02: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 10, refCntWtd = 4 New refCnts for V03: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 11, refCntWtd = 6 New refCnts for V04: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 12, refCntWtd = 8 *** marking local variables in block BB02 (weight=1 ) [000034] ------------ * STMT void (IL 0x000...0x03C) [000032] --CXG+------ \--* CALL void System.Console.WriteLine [000029] -----+------ | /--* LCL_VAR float V04 tmp3 [000030] ----G+------ | /--* MUL float [000026] -----+------ | | \--* LCL_VAR float V04 tmp3 [000031] ----G+------ arg0 in mm0 \--* ADD float [000021] -----+------ | /--* LCL_VAR float V03 tmp2 [000022] ----G+------ | /--* MUL float [000018] -----+------ | | \--* LCL_VAR float V03 tmp2 [000023] ----G+------ \--* ADD float [000013] -----+------ | /--* LCL_VAR float V02 tmp1 [000014] ----G+------ | /--* MUL float [000010] -----+------ | | \--* LCL_VAR float V02 tmp1 [000015] ----G+------ \--* ADD float [000006] -----+------ | /--* LCL_VAR float V01 tmp0 [000007] ----G+------ \--* MUL float [000003] -----+------ \--* LCL_VAR float V01 tmp0 New refCnts for V01: refCnt = 2, refCntWtd = 3 New refCnts for V01: refCnt = 3, refCntWtd = 4 New refCnts for V02: refCnt = 2, refCntWtd = 3 New refCnts for V02: refCnt = 3, refCntWtd = 4 New refCnts for V03: refCnt = 2, refCntWtd = 3 New refCnts for V03: refCnt = 3, refCntWtd = 4 New refCnts for V04: refCnt = 2, refCntWtd = 3 New refCnts for V04: refCnt = 3, refCntWtd = 4 [000036] ------------ * STMT void (IL 0x03C... ???) [000035] -----+------ \--* RETURN void New refCnts for V00: refCnt = 13, refCntWtd = 10 New refCnts for V00: refCnt = 14, refCntWtd = 12 *************** In optAddCopies() refCnt table for 'Test3': V00 arg0 [ byref]: refCnt = 14, refCntWtd = 12 pref [rcx] V01 tmp0 [ float]: refCnt = 3, refCntWtd = 4 V02 tmp1 [ float]: refCnt = 3, refCntWtd = 4 V03 tmp2 [ float]: refCnt = 3, refCntWtd = 4 V04 tmp3 [ float]: refCnt = 3, refCntWtd = 4 V06 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** In fgFindOperOrder() *************** In fgSetBlockOrder() The biggest BB has 27 tree nodes -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 16, 15) [000041] ------------ * STMT void (IL ???... ???) N024 ( 4, 4) [000067] x----------- | /--* IND float N022 ( 1, 1) [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] N023 ( 2, 2) [000066] -------N---- | | \--* ADD byref N021 ( 1, 1) [000064] ------------ | | \--* LCL_VAR byref V00 arg0 N026 ( 4, 4) [000068] -A------R--- | /--* ASG float N025 ( 1, 2) [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 N027 ( 16, 15) [000069] -A---------- \--* COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 ( 57, 50) [000034] ------------ * STMT void (IL 0x000...0x03C) N019 ( 57, 50) [000032] --CXG------- \--* CALL void System.Console.WriteLine N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 ***** BB02, stmt 3 ( 0, 0) [000036] ------------ * STMT void (IL 0x03C... ???) N001 ( 0, 0) [000035] ------------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 3. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] *************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...) *************** In SsaBuilder::InsertPhiFunctions() *************** In fgLocalVarLiveness() *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00 } + ByrefExposed + GcHeap DEF(4)={ V01 V02 V03 V04} BB02 USE(4)={V01 V02 V03 V04} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (1)={V00 } + ByrefExposed + GcHeap OUT(4)={ V01 V02 V03 V04} + ByrefExposed + GcHeap BB02 IN (4)={V01 V02 V03 V04} + ByrefExposed + GcHeap OUT(0)={ } Inserting phi functions: *************** In SsaBuilder::RenameVariables() After fgSsaBuild: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 16, 15) [000041] ------------ * STMT void (IL ???... ???) N024 ( 4, 4) [000067] x----------- | /--* IND float N022 ( 1, 1) [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] N023 ( 2, 2) [000066] -------N---- | | \--* ADD byref N021 ( 1, 1) [000064] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) N026 ( 4, 4) [000068] -A------R--- | /--* ASG float N025 ( 1, 2) [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- \--* COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 ( 57, 50) [000034] ------------ * STMT void (IL 0x000...0x03C) N019 ( 57, 50) [000032] --CXG------- \--* CALL void System.Console.WriteLine N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 ***** BB02, stmt 3 ( 0, 0) [000036] ------------ * STMT void (IL 0x03C... ???) N001 ( 0, 0) [000035] ------------ \--* RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In optEarlyProp() *************** In fgValueNumber() Memory Initial Value in BB01 is: $c0 The SSA definition for ByrefExposed (#2) at start of BB01 is $c0 {InitVal($41)} The SSA definition for GcHeap (#2) at start of BB01 is $c0 {InitVal($41)} ***** BB01, stmt 1 (before) N024 ( 4, 4) [000067] x----------- /--* IND float N022 ( 1, 1) [000065] ------------ | | /--* CNS_INT long 12 Fseq[W] N023 ( 2, 2) [000066] -------N---- | \--* ADD byref N021 ( 1, 1) [000064] ------------ | \--* LCL_VAR byref V00 arg0 u:2 (last use) N026 ( 4, 4) [000068] -A------R--- /--* ASG float N025 ( 1, 2) [000063] D------N---- | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- * COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 N001 [000044] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N002 [000045] CNS_INT 0 Fseq[X] => $100 {LngCns: 0} N003 [000046] ADD => $140 {ADD($80, $100)} N004 [000047] IND => N005 [000043] LCL_VAR V01 tmp0 d:2 => N006 [000048] ASG => N007 [000050] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N008 [000051] CNS_INT 4 Fseq[Y] => $101 {LngCns: 4} N009 [000052] ADD => $141 {ADD($80, $101)} N010 [000053] IND => N011 [000049] LCL_VAR V02 tmp1 d:2 => N012 [000054] ASG => N013 [000055] COMMA => N014 [000057] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N015 [000058] CNS_INT 8 Fseq[Z] => $102 {LngCns: 8} N016 [000059] ADD => $142 {ADD($80, $102)} N017 [000060] IND => N018 [000056] LCL_VAR V03 tmp2 d:2 => N019 [000061] ASG => N020 [000062] COMMA => N021 [000064] LCL_VAR V00 arg0 u:2 (last use) => $80 {InitVal($40)} N022 [000065] CNS_INT 12 Fseq[W] => $103 {LngCns: 12} N023 [000066] ADD => $143 {ADD($80, $103)} N024 [000067] IND => N025 [000063] LCL_VAR V04 tmp3 d:2 => N026 [000068] ASG => N027 [000069] COMMA => ***** BB01, stmt 1 (after) N024 ( 4, 4) [000067] x----------- /--* IND float N022 ( 1, 1) [000065] ------------ | | /--* CNS_INT long 12 Fseq[W] $103 N023 ( 2, 2) [000066] -------N---- | \--* ADD byref $143 N021 ( 1, 1) [000064] ------------ | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N026 ( 4, 4) [000068] -A------R--- /--* ASG float N025 ( 1, 2) [000063] D------N---- | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- * COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] $102 N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref $142 N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] $101 N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] $100 N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB02 is $c0 {InitVal($41)} The SSA definition for GcHeap (#2) at start of BB02 is $c0 {InitVal($41)} ***** BB02, stmt 2 (before) N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 N001 [000070] ARGPLACE => $1c8 {1c8} N002 [000033] LIST => $200 {LIST($1c8, $0)} N003 [000003] LCL_VAR V01 tmp0 u:2 => N004 [000006] LCL_VAR V01 tmp0 u:2 (last use) => N005 [000007] MUL => N006 [000010] LCL_VAR V02 tmp1 u:2 => N007 [000013] LCL_VAR V02 tmp1 u:2 (last use) => N008 [000014] MUL => N009 [000015] ADD => N010 [000018] LCL_VAR V03 tmp2 u:2 => N011 [000021] LCL_VAR V03 tmp2 u:2 (last use) => N012 [000022] MUL => N013 [000023] ADD => N014 [000026] LCL_VAR V04 tmp3 u:2 => N015 [000029] LCL_VAR V04 tmp3 u:2 (last use) => N016 [000030] MUL => N017 [000031] ADD => N018 [000071] LIST => VN of ARGPLACE tree [000070] updated to N002 [000033] LIST => fgCurMemoryVN[GcHeap] assigned by CALL at [000032] to VN: $2c0. N019 [000032] CALL => $VN.Void ***** BB02, stmt 2 (after) N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 --------- ***** BB02, stmt 3 (before) N001 ( 0, 0) [000035] ------------ * RETURN void N001 [000035] RETURN => $300 {300} ***** BB02, stmt 3 (after) N001 ( 0, 0) [000035] ------------ * RETURN void $300 finish(BB02). *************** In optVnCopyProp() *************** In SsaBuilder::ComputeDominators(Compiler*, ...) Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V02} Live vars: {V00 V01 V02} => {V00 V01 V02 V03} Live vars: {V00 V01 V02 V03} => {V01 V02 V03} Live vars: {V01 V02 V03} => {V01 V02 V03 V04} Copy Assertion for BB02 curSsaName stack: { 0-[000044]:V00 1-[000043]:V01 2-[000049]:V02 3-[000056]:V03 4-[000063]:V04 } Live vars: {V01 V02 V03 V04} => {V02 V03 V04} Live vars: {V02 V03 V04} => {V03 V04} Live vars: {V03 V04} => {V04} Live vars: {V04} => {} *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 16, 15) [000041] ------------ * STMT void (IL ???... ???) N024 ( 4, 4) [000067] x----------- | /--* IND float N022 ( 1, 1) [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] $103 N023 ( 2, 2) [000066] -------N---- | | \--* ADD byref $143 N021 ( 1, 1) [000064] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N026 ( 4, 4) [000068] -A------R--- | /--* ASG float N025 ( 1, 2) [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- \--* COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] $102 N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref $142 N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] $101 N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] $100 N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 ( 57, 50) [000034] ------------ * STMT void (IL 0x000...0x03C) N019 ( 57, 50) [000032] --CXG------- \--* CALL void System.Console.WriteLine $VN.Void N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 ***** BB02, stmt 3 ( 0, 0) [000036] ------------ * STMT void (IL 0x03C... ???) N001 ( 0, 0) [000035] ------------ \--* RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() *************** In optAssertionPropMain() Blocks/Trees at start of phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 16, 15) [000041] ------------ * STMT void (IL ???... ???) N024 ( 4, 4) [000067] x----------- | /--* IND float N022 ( 1, 1) [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] $103 N023 ( 2, 2) [000066] -------N---- | | \--* ADD byref $143 N021 ( 1, 1) [000064] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N026 ( 4, 4) [000068] -A------R--- | /--* ASG float N025 ( 1, 2) [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- \--* COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] $102 N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref $142 N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] $101 N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] $100 N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 ( 57, 50) [000034] ------------ * STMT void (IL 0x000...0x03C) N019 ( 57, 50) [000032] --CXG------- \--* CALL void System.Console.WriteLine $VN.Void N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 ***** BB02, stmt 3 ( 0, 0) [000036] ------------ * STMT void (IL 0x03C... ???) N001 ( 0, 0) [000035] ------------ \--* RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In OptimizeRangeChecks() Blocks/trees before phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 16, 15) [000041] ------------ * STMT void (IL ???... ???) N024 ( 4, 4) [000067] x----------- | /--* IND float N022 ( 1, 1) [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] $103 N023 ( 2, 2) [000066] -------N---- | | \--* ADD byref $143 N021 ( 1, 1) [000064] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N026 ( 4, 4) [000068] -A------R--- | /--* ASG float N025 ( 1, 2) [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- \--* COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] $102 N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref $142 N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] $101 N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] $100 N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 ( 57, 50) [000034] ------------ * STMT void (IL 0x000...0x03C) N019 ( 57, 50) [000032] --CXG------- \--* CALL void System.Console.WriteLine $VN.Void N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 ***** BB02, stmt 3 ( 0, 0) [000036] ------------ * STMT void (IL 0x03C... ???) N001 ( 0, 0) [000035] ------------ \--* RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** In IR Rationalize Trees before IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 16, 15) [000041] ------------ * STMT void (IL ???... ???) N024 ( 4, 4) [000067] x----------- | /--* IND float N022 ( 1, 1) [000065] ------------ | | | /--* CNS_INT long 12 Fseq[W] $103 N023 ( 2, 2) [000066] -------N---- | | \--* ADD byref $143 N021 ( 1, 1) [000064] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N026 ( 4, 4) [000068] -A------R--- | /--* ASG float N025 ( 1, 2) [000063] D------N---- | | \--* LCL_VAR float V04 tmp3 d:2 N027 ( 16, 15) [000069] -A---------- \--* COMMA void N017 ( 4, 4) [000060] x----------- | /--* IND float N015 ( 1, 1) [000058] ------------ | | | /--* CNS_INT long 8 Fseq[Z] $102 N016 ( 2, 2) [000059] -------N---- | | \--* ADD byref $142 N014 ( 1, 1) [000057] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N019 ( 4, 4) [000061] -A------R--- | /--* ASG float N018 ( 1, 2) [000056] D------N---- | | \--* LCL_VAR float V03 tmp2 d:2 N020 ( 12, 11) [000062] -A---------- \--* COMMA void N010 ( 4, 4) [000053] x----------- | /--* IND float N008 ( 1, 1) [000051] ------------ | | | /--* CNS_INT long 4 Fseq[Y] $101 N009 ( 2, 2) [000052] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000050] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [000054] -A------R--- | /--* ASG float N011 ( 1, 2) [000049] D------N---- | | \--* LCL_VAR float V02 tmp1 d:2 N013 ( 8, 7) [000055] -A---------- \--* COMMA void N004 ( 4, 3) [000047] x----------- | /--* IND float N002 ( 1, 1) [000045] ------------ | | | /--* CNS_INT long 0 Fseq[X] $100 N003 ( 3, 3) [000046] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000044] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 4, 3) [000048] -A------R--- \--* ASG float N005 ( 1, 2) [000043] D------N---- \--* LCL_VAR float V01 tmp0 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ***** BB02, stmt 2 ( 57, 50) [000034] ------------ * STMT void (IL 0x000...0x03C) N019 ( 57, 50) [000032] --CXG------- \--* CALL void System.Console.WriteLine $VN.Void N015 ( 1, 2) [000029] ------------ | /--* LCL_VAR float V04 tmp3 u:2 (last use) N016 ( 7, 8) [000030] ----G------- | /--* MUL float N014 ( 1, 2) [000026] ------------ | | \--* LCL_VAR float V04 tmp3 u:2 N017 ( 43, 44) [000031] ----G------- arg0 in mm0 \--* ADD float N011 ( 1, 2) [000021] ------------ | /--* LCL_VAR float V03 tmp2 u:2 (last use) N012 ( 7, 8) [000022] ----G------- | /--* MUL float N010 ( 1, 2) [000018] ------------ | | \--* LCL_VAR float V03 tmp2 u:2 N013 ( 31, 32) [000023] ----G------- \--* ADD float N007 ( 1, 2) [000013] ------------ | /--* LCL_VAR float V02 tmp1 u:2 (last use) N008 ( 7, 8) [000014] ----G------- | /--* MUL float N006 ( 1, 2) [000010] ------------ | | \--* LCL_VAR float V02 tmp1 u:2 N009 ( 19, 20) [000015] ----G------- \--* ADD float N004 ( 1, 2) [000006] ------------ | /--* LCL_VAR float V01 tmp0 u:2 (last use) N005 ( 7, 8) [000007] ----G------- \--* MUL float N003 ( 1, 2) [000003] ------------ \--* LCL_VAR float V01 tmp0 u:2 ***** BB02, stmt 3 ( 0, 0) [000036] ------------ * STMT void (IL 0x03C... ???) N001 ( 0, 0) [000035] ------------ \--* RETURN void $300 ------------------------------------------------------------------------------------------------------------------- rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 *************** Exiting IR Rationalize Trees after IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [000045] ------------ t45 = CNS_INT long 0 Fseq[X] $100 /--* t44 byref +--* t45 long N003 ( 3, 3) [000046] -------N---- t46 = * ADD byref $140 /--* t46 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [000051] ------------ t51 = CNS_INT long 4 Fseq[Y] $101 /--* t50 byref +--* t51 long N009 ( 2, 2) [000052] -------N---- t52 = * ADD byref $141 /--* t52 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 N015 ( 1, 1) [000058] ------------ t58 = CNS_INT long 8 Fseq[Z] $102 /--* t57 byref +--* t58 long N016 ( 2, 2) [000059] -------N---- t59 = * ADD byref $142 /--* t59 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N022 ( 1, 1) [000065] ------------ t65 = CNS_INT long 12 Fseq[W] $103 /--* t64 byref +--* t65 long N023 ( 2, 2) [000066] -------N---- t66 = * ADD byref $143 /--* t66 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Bumping outgoingArgSpaceSize to 32 for call [000032] *************** In fgDebugCheckBBlist *************** In Lowering Trees before Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [000045] ------------ t45 = CNS_INT long 0 Fseq[X] $100 /--* t44 byref +--* t45 long N003 ( 3, 3) [000046] -------N---- t46 = * ADD byref $140 /--* t46 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [000051] ------------ t51 = CNS_INT long 4 Fseq[Y] $101 /--* t50 byref +--* t51 long N009 ( 2, 2) [000052] -------N---- t52 = * ADD byref $141 /--* t52 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 N015 ( 1, 1) [000058] ------------ t58 = CNS_INT long 8 Fseq[Z] $102 /--* t57 byref +--* t58 long N016 ( 2, 2) [000059] -------N---- t59 = * ADD byref $142 /--* t59 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N022 ( 1, 1) [000065] ------------ t65 = CNS_INT long 12 Fseq[W] $103 /--* t64 byref +--* t65 long N023 ( 2, 2) [000066] -------N---- t66 = * ADD byref $143 /--* t66 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- Addressing mode: Base N001 ( 1, 1) [000044] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 0 New addressing mode node: [000072] ------------ * LEA(b+0) byref Addressing mode: Base N007 ( 1, 1) [000050] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 4 New addressing mode node: [000073] ------------ * LEA(b+4) byref Addressing mode: Base N014 ( 1, 1) [000057] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 8 New addressing mode node: [000074] ------------ * LEA(b+8) byref Addressing mode: Base N021 ( 1, 1) [000064] ------------ * LCL_VAR byref V00 arg0 u:2 (last use) $80 + 12 New addressing mode node: [000075] ------------ * LEA(b+12) byref lowering call (before): N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000070] ----------L- * ARGPLACE float late: ====== lowering arg : N017 ( 43, 44) [000031] ----G------- * ADD float new node is : [000076] ----G------- * PUTARG_REG float REG mm0 lowering call (after): N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void lowering GT_RETURN N001 ( 0, 0) [000035] ------------ * RETURN void $300 ============Lower has completed modifying nodes. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 /--* t44 byref [000072] -c---------- t72 = * LEA(b+0) byref /--* t72 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 /--* t50 byref [000073] -c---------- t73 = * LEA(b+4) byref /--* t73 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 /--* t57 byref [000074] -c---------- t74 = * LEA(b+8) byref /--* t74 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t64 byref [000075] -c---------- t75 = * LEA(b+12) byref /--* t75 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 byref ; V01 tmp0 float V05.X(offs=0x00) P-INDEP ; V02 tmp1 float V05.Y(offs=0x04) P-INDEP ; V03 tmp2 float V05.Z(offs=0x08) P-INDEP ; V04 tmp3 float V05.W(offs=0x0c) P-INDEP ; V05 tmp4 struct (16) ; V06 OutArgs lclBlk (32) In fgLocalVarLivenessInit, sorting locals refCnt table for 'Test3': V00 arg0 [ byref]: refCnt = 14, refCntWtd = 12 pref [rcx] V01 tmp0 [ float]: refCnt = 3, refCntWtd = 4 V02 tmp1 [ float]: refCnt = 3, refCntWtd = 4 V03 tmp2 [ float]: refCnt = 3, refCntWtd = 4 V04 tmp3 [ float]: refCnt = 3, refCntWtd = 4 V06 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00 } + ByrefExposed + GcHeap DEF(4)={ V01 V02 V03 V04} BB02 USE(4)={V01 V02 V03 V04} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (1)={V00 } + ByrefExposed + GcHeap OUT(4)={ V01 V02 V03 V04} + ByrefExposed + GcHeap BB02 IN (4)={V01 V02 V03 V04} + ByrefExposed + GcHeap OUT(0)={ } *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Liveness pass finished after lowering, IR: lvasortagain = 0 -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 /--* t44 byref [000072] -c---------- t72 = * LEA(b+0) byref /--* t72 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 /--* t50 byref [000073] -c---------- t73 = * LEA(b+4) byref /--* t73 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 /--* t57 byref [000074] -c---------- t74 = * LEA(b+8) byref /--* t74 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t64 byref [000075] -c---------- t75 = * LEA(b+12) byref /--* t75 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** Exiting Lowering Trees after Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 /--* t44 byref [000072] -c---------- t72 = * LEA(b+0) byref /--* t72 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 /--* t50 byref [000073] -c---------- t73 = * LEA(b+4) byref /--* t73 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 /--* t57 byref [000074] -c---------- t74 = * LEA(b+8) byref /--* t74 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t64 byref [000075] -c---------- t75 = * LEA(b+12) byref /--* t75 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In StackLevelSetter Trees before StackLevelSetter -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 /--* t44 byref [000072] -c---------- t72 = * LEA(b+0) byref /--* t72 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 /--* t50 byref [000073] -c---------- t73 = * LEA(b+4) byref /--* t73 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 /--* t57 byref [000074] -c---------- t74 = * LEA(b+8) byref /--* t74 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t64 byref [000075] -c---------- t75 = * LEA(b+12) byref /--* t75 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** Exiting StackLevelSetter Trees after StackLevelSetter -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 $80 /--* t44 byref [000072] -c---------- t72 = * LEA(b+0) byref /--* t72 byref N004 ( 4, 3) [000047] x----------- t47 = * IND float /--* t47 float N006 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 N007 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 $80 /--* t50 byref [000073] -c---------- t73 = * LEA(b+4) byref /--* t73 byref N010 ( 4, 4) [000053] x----------- t53 = * IND float /--* t53 float N012 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 N014 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 $80 /--* t57 byref [000074] -c---------- t74 = * LEA(b+8) byref /--* t74 byref N017 ( 4, 4) [000060] x----------- t60 = * IND float /--* t60 float N019 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 N021 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t64 byref [000075] -c---------- t75 = * LEA(b+12) byref /--* t75 byref N024 ( 4, 4) [000067] x----------- t67 = * IND float /--* t67 float N026 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 ------------ BB02 [000..03D) (return), preds={BB01} succs={} ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 N003 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 N004 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 (last use) /--* t3 float +--* t6 float N005 ( 7, 8) [000007] ----G------- t7 = * MUL float N006 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 N007 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 (last use) /--* t10 float +--* t13 float N008 ( 7, 8) [000014] ----G------- t14 = * MUL float /--* t7 float +--* t14 float N009 ( 19, 20) [000015] ----G------- t15 = * ADD float N010 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 N011 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 (last use) /--* t18 float +--* t21 float N012 ( 7, 8) [000022] ----G------- t22 = * MUL float /--* t15 float +--* t22 float N013 ( 31, 32) [000023] ----G------- t23 = * ADD float N014 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 N015 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 (last use) /--* t26 float +--* t29 float N016 ( 7, 8) [000030] ----G------- t30 = * MUL float /--* t23 float +--* t30 float N017 ( 43, 44) [000031] ----G------- t31 = * ADD float /--* t31 float [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N019 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c N001 ( 0, 0) [000035] ------------ RETURN void $300 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V00} {V01 V02 V03 V04} {V00} {V01 V02 V03 V04} BB02 use def in out {V01 V02 V03 V04} {} {V01 V02 V03 V04} {} Interval 0: RefPositions {} physReg:NA Preferences=[allInt] Interval 1: RefPositions {} physReg:NA Preferences=[allFloat] Interval 2: RefPositions {} physReg:NA Preferences=[allFloat] Interval 3: RefPositions {} physReg:NA Preferences=[allFloat] Interval 4: RefPositions {} physReg:NA Preferences=[allFloat] FP callee save candidate vars: {V01 V02 V03 V04} floatVarCount = 4; hasLoops = 0, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB01 [???..???), preds={} succs={BB02} ===== N001. V00(t44) N000. t72 = LEA(b+0) ; t44 N004. t47 = IND ; t72 N006. V01(t48); t47 N007. V00(t50) N000. t73 = LEA(b+4) ; t50 N010. t53 = IND ; t73 N012. V02(t54); t53 N014. V00(t57) N000. t74 = LEA(b+8) ; t57 N017. t60 = IND ; t74 N019. V03(t61); t60 N021. V00(t64*) N000. t75 = LEA(b+12); t64* N024. t67 = IND ; t75 N026. V04(t68); t67 BB02 [000..03D) (return), preds={BB01} succs={} ===== N000. IL_OFFSET IL offset: 0x0 N003. V01(t3) N004. V01(t6*) N005. t7 = MUL ; t3,t6* N006. V02(t10) N007. V02(t13*) N008. t14 = MUL ; t10,t13* N009. t15 = ADD ; t7,t14 N010. V03(t18) N011. V03(t21*) N012. t22 = MUL ; t18,t21* N013. t23 = ADD ; t15,t22 N014. V04(t26) N015. V04(t29*) N016. t30 = MUL ; t26,t29* N017. t31 = ADD ; t23,t30 N000. t76 = PUTARG_REG; t31 N019. CALL ; t76 N000. IL_OFFSET IL offset: 0x3c N001. RETURN buildIntervals second part ======== Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 ( 1, 1) [000044] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N003.t44. LCL_VAR } N005 (???,???) [000072] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N003.t44. LCL_VAR } N007 ( 4, 3) [000047] x----------- * IND float REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 5: RefPositions {} physReg:NA Preferences=[allFloat] IND BB01 regmask=[allFloat] minReg=1> DefList: { N007.t47. IND } N009 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last> DefList: { } N011 ( 1, 1) [000050] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N011.t50. LCL_VAR } N013 (???,???) [000073] -c---------- * LEA(b+4) byref REG NA Contained DefList: { N011.t50. LCL_VAR } N015 ( 4, 4) [000053] x----------- * IND float REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 6: RefPositions {} physReg:NA Preferences=[allFloat] IND BB01 regmask=[allFloat] minReg=1> DefList: { N015.t53. IND } N017 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last> DefList: { } N019 ( 1, 1) [000057] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N019.t57. LCL_VAR } N021 (???,???) [000074] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N019.t57. LCL_VAR } N023 ( 4, 4) [000060] x----------- * IND float REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 7: RefPositions {} physReg:NA Preferences=[allFloat] IND BB01 regmask=[allFloat] minReg=1> DefList: { N023.t60. IND } N025 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last> DefList: { } N027 ( 1, 1) [000064] ------------ * LCL_VAR byref V00 arg0 u:2 NA (last use) REG NA $80 +[--] consume=0 produce=1 DefList: { N027.t64. LCL_VAR } N029 (???,???) [000075] -c---------- * LEA(b+12) byref REG NA Contained DefList: { N027.t64. LCL_VAR } N031 ( 4, 4) [000067] x----------- * IND float REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 8: RefPositions {} physReg:NA Preferences=[allFloat] IND BB01 regmask=[allFloat] minReg=1> DefList: { N031.t67. IND } N033 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last> CHECKING LAST USES for block 1, liveout={V01 V02 V03 V04} ============================== use: {V00} def: {V01 V02 V03 V04} NEW BLOCK BB02 Setting BB02 as the predecessor for determining incoming variable registers of BB01 DefList: { } N037 ( 57, 50) [000034] ------------ * IL_OFFSET void IL offset: 0x0 REG NA +[--] consume=0 produce=0 DefList: { } N039 ( 1, 2) [000003] ------------ * LCL_VAR float V01 tmp0 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N039.t3. LCL_VAR } N041 ( 1, 2) [000006] ------------ * LCL_VAR float V01 tmp0 u:2 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N039.t3. LCL_VAR; N041.t6. LCL_VAR } N043 ( 7, 8) [000007] ----G------- * MUL float REG NA +[-O] consume=2 produce=1 LCL_VAR BB02 regmask=[allFloat] minReg=1 last> LCL_VAR BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 9: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to MUL BB02 regmask=[allFloat] minReg=1> DefList: { N043.t7. MUL } N045 ( 1, 2) [000010] ------------ * LCL_VAR float V02 tmp1 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N043.t7. MUL; N045.t10. LCL_VAR } N047 ( 1, 2) [000013] ------------ * LCL_VAR float V02 tmp1 u:2 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N043.t7. MUL; N045.t10. LCL_VAR; N047.t13. LCL_VAR } N049 ( 7, 8) [000014] ----G------- * MUL float REG NA +[--] consume=2 produce=1 LCL_VAR BB02 regmask=[allFloat] minReg=1 last> LCL_VAR BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 10: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to MUL BB02 regmask=[allFloat] minReg=1> DefList: { N043.t7. MUL; N049.t14. MUL } N051 ( 19, 20) [000015] ----G------- * ADD float REG NA +[-O] consume=2 produce=1 BB02 regmask=[allFloat] minReg=1 last> BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 11: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to ADD BB02 regmask=[allFloat] minReg=1> DefList: { N051.t15. ADD } N053 ( 1, 2) [000018] ------------ * LCL_VAR float V03 tmp2 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N051.t15. ADD; N053.t18. LCL_VAR } N055 ( 1, 2) [000021] ------------ * LCL_VAR float V03 tmp2 u:2 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N051.t15. ADD; N053.t18. LCL_VAR; N055.t21. LCL_VAR } N057 ( 7, 8) [000022] ----G------- * MUL float REG NA +[--] consume=2 produce=1 LCL_VAR BB02 regmask=[allFloat] minReg=1 last> LCL_VAR BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 12: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to MUL BB02 regmask=[allFloat] minReg=1> DefList: { N051.t15. ADD; N057.t22. MUL } N059 ( 31, 32) [000023] ----G------- * ADD float REG NA +[-O] consume=2 produce=1 BB02 regmask=[allFloat] minReg=1 last> BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 13: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to ADD BB02 regmask=[allFloat] minReg=1> DefList: { N059.t23. ADD } N061 ( 1, 2) [000026] ------------ * LCL_VAR float V04 tmp3 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N059.t23. ADD; N061.t26. LCL_VAR } N063 ( 1, 2) [000029] ------------ * LCL_VAR float V04 tmp3 u:2 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N059.t23. ADD; N061.t26. LCL_VAR; N063.t29. LCL_VAR } N065 ( 7, 8) [000030] ----G------- * MUL float REG NA +[--] consume=2 produce=1 LCL_VAR BB02 regmask=[allFloat] minReg=1 last> LCL_VAR BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 14: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to MUL BB02 regmask=[allFloat] minReg=1> DefList: { N059.t23. ADD; N065.t30. MUL } N067 ( 43, 44) [000031] ----G------- * ADD float REG NA +[--] consume=2 produce=1 BB02 regmask=[allFloat] minReg=1 last> BB02 regmask=[allFloat] minReg=1 last> Def candidates [allFloat], Use candidates [allFloat] Interval 15: RefPositions {} physReg:NA Preferences=[allFloat] Assigning related to ADD BB02 regmask=[allFloat] minReg=1> DefList: { N067.t31. ADD } N069 (???,???) [000076] ----G------- * PUTARG_REG float REG mm0 +[--] consume=1 produce=1 BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> Def candidates [mm0], Use candidates [mm0] Interval 16: RefPositions {} physReg:NA Preferences=[allFloat] BB02 regmask=[mm0] minReg=1> PUTARG_REG BB02 regmask=[mm0] minReg=1 fixed> DefList: { N069.t76. PUTARG_REG } N071 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void +[--] consume=1 produce=0 BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm1] minReg=1> BB02 regmask=[mm2] minReg=1> BB02 regmask=[mm3] minReg=1> BB02 regmask=[mm4] minReg=1> BB02 regmask=[mm5] minReg=1> DefList: { } N073 ( 0, 0) [000036] ------------ * IL_OFFSET void IL offset: 0x3c REG NA +[--] consume=0 produce=0 DefList: { } N075 ( 0, 0) [000035] ------------ * RETURN void REG NA $300 +[--] consume=0 produce=0 CHECKING LAST USES for block 2, liveout={} ============================== use: {V01 V02 V03 V04} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) RefPositions {#0@0 #2@7 #6@15 #10@23 #14@31} physReg:rcx Preferences=[rcx] Interval 1: (V01) (struct) RefPositions {#5@10 #19@43 #20@43} physReg:NA Preferences=[allFloat] Interval 2: (V02) (struct) RefPositions {#9@18 #22@49 #23@49} physReg:NA Preferences=[allFloat] Interval 3: (V03) (struct) RefPositions {#13@26 #28@57 #29@57} physReg:NA Preferences=[allFloat] Interval 4: (V04) (struct) RefPositions {#17@34 #34@65 #35@65} physReg:NA Preferences=[allFloat] Interval 5: RefPositions {#3@8 #4@9} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9D80] Interval 6: RefPositions {#7@16 #8@17} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9DD8] Interval 7: RefPositions {#11@24 #12@25} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E30] Interval 8: RefPositions {#15@32 #16@33} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E88] Interval 9: RefPositions {#21@44 #25@51} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9D80] Interval 10: RefPositions {#24@50 #26@51} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9DD8] Interval 11: RefPositions {#27@52 #31@59} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451AAAF8] Interval 12: RefPositions {#30@58 #32@59} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E30] Interval 13: RefPositions {#33@60 #37@67} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451AAE28] Interval 14: RefPositions {#36@66 #38@67} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E88] Interval 15: RefPositions {#39@68 #41@69} physReg:NA Preferences=[mm0] RelatedInterval [0000021C451AB158] Interval 16: RefPositions {#43@70 #45@71} physReg:NA Preferences=[mm0] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ #2 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #6 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #4 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #19 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #10 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #8 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #22 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #14 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #12 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #28 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #16 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #34 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #20 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #25 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> #23 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #26 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> BB02 regmask=[allFloat] minReg=1 last regOptional> BB02 regmask=[allFloat] minReg=1 last> #31 RefTypeDef ADD BB02 regmask=[allFloat] minReg=1> #29 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #32 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> BB02 regmask=[allFloat] minReg=1 last regOptional> BB02 regmask=[allFloat] minReg=1 last> #37 RefTypeDef ADD BB02 regmask=[allFloat] minReg=1> #35 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #38 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> BB02 regmask=[allFloat] minReg=1 last regOptional> BB02 regmask=[allFloat] minReg=1 last> #41 RefTypeDef ADD BB02 regmask=[mm0] minReg=1> #42 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> #44 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> #45 RefTypeDef PUTARG_REG BB02 regmask=[mm0] minReg=1 fixed> #53 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[mm0] minReg=1 last> BB02 regmask=[mm1] minReg=1 last> BB02 regmask=[mm2] minReg=1 last> BB02 regmask=[mm3] minReg=1 last> BB02 regmask=[mm4] minReg=1 last> BB02 regmask=[mm5] minReg=1 last> ----------------- #2 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #6 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #10 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #14 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #19 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #20 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> ----------------- #22 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #23 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> ----------------- #28 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #29 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> ----------------- #34 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #35 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 BB01 [???..???), preds={} succs={BB02} ===== N003. V00(L0) N005. LEA(b+0) N007. IND Use:(#2) Def:(#3) Pref: N009. V01(L1) Use:(#4) * Def:(#5) N011. V00(L0) N013. LEA(b+4) N015. IND Use:(#6) Def:(#7) Pref: N017. V02(L2) Use:(#8) * Def:(#9) N019. V00(L0) N021. LEA(b+8) N023. IND Use:(#10) Def:(#11) Pref: N025. V03(L3) Use:(#12) * Def:(#13) N027. V00(L0) N029. LEA(b+12) N031. IND Use:(#14) * Def:(#15) Pref: N033. V04(L4) Use:(#16) * Def:(#17) BB02 [000..03D) (return), preds={BB01} succs={} ===== N037. IL_OFFSET IL offset: 0x0 REG NA N039. V01(L1) N041. V01(L1) N043. MUL Use:(#19) Use:(#20) * Def:(#21) Pref: N045. V02(L2) N047. V02(L2) N049. MUL Use:(#22) Use:(#23) * Def:(#24) Pref: N051. ADD Use:(#25) * Use:(#26) * Def:(#27) Pref: N053. V03(L3) N055. V03(L3) N057. MUL Use:(#28) Use:(#29) * Def:(#30) Pref: N059. ADD Use:(#31) * Use:(#32) * Def:(#33) Pref: N061. V04(L4) N063. V04(L4) N065. MUL Use:(#34) Use:(#35) * Def:(#36) Pref: N067. ADD Use:(#37) * Use:(#38) * Def:(#39) Pref: N069. PUTARG_REG Use:(#41) Fixed:mm0(#40) * Def:(#43) mm0 N071. CALL Use:(#45) Fixed:mm0(#44) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N073. IL_OFFSET IL offset: 0x3c REG NA N075. RETURN Linear scan intervals after buildIntervals: Interval 0: (V00) RefPositions {#0@0 #2@7 #6@15 #10@23 #14@31} physReg:rcx Preferences=[rcx] Interval 1: (V01) (struct) RefPositions {#5@10 #19@43 #20@43} physReg:NA Preferences=[allFloat] Interval 2: (V02) (struct) RefPositions {#9@18 #22@49 #23@49} physReg:NA Preferences=[allFloat] Interval 3: (V03) (struct) RefPositions {#13@26 #28@57 #29@57} physReg:NA Preferences=[allFloat] Interval 4: (V04) (struct) RefPositions {#17@34 #34@65 #35@65} physReg:NA Preferences=[allFloat] Interval 5: RefPositions {#3@8 #4@9} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9D80] Interval 6: RefPositions {#7@16 #8@17} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9DD8] Interval 7: RefPositions {#11@24 #12@25} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E30] Interval 8: RefPositions {#15@32 #16@33} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E88] Interval 9: RefPositions {#21@44 #25@51} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9D80] Interval 10: RefPositions {#24@50 #26@51} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9DD8] Interval 11: RefPositions {#27@52 #31@59} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451AAAF8] Interval 12: RefPositions {#30@58 #32@59} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E30] Interval 13: RefPositions {#33@60 #37@67} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451AAE28] Interval 14: RefPositions {#36@66 #38@67} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E88] Interval 15: RefPositions {#39@68 #41@69} physReg:NA Preferences=[mm0] RelatedInterval [0000021C451AB158] Interval 16: RefPositions {#43@70 #45@71} physReg:NA Preferences=[mm0] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) RefPositions {#0@0 #2@7 #6@15 #10@23 #14@31} physReg:rcx Preferences=[rcx] Interval 1: (V01) (struct) RefPositions {#5@10 #19@43 #20@43} physReg:NA Preferences=[allFloat] Interval 2: (V02) (struct) RefPositions {#9@18 #22@49 #23@49} physReg:NA Preferences=[allFloat] Interval 3: (V03) (struct) RefPositions {#13@26 #28@57 #29@57} physReg:NA Preferences=[allFloat] Interval 4: (V04) (struct) RefPositions {#17@34 #34@65 #35@65} physReg:NA Preferences=[allFloat] Interval 5: RefPositions {#3@8 #4@9} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9D80] Interval 6: RefPositions {#7@16 #8@17} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9DD8] Interval 7: RefPositions {#11@24 #12@25} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E30] Interval 8: RefPositions {#15@32 #16@33} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E88] Interval 9: RefPositions {#21@44 #25@51} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9D80] Interval 10: RefPositions {#24@50 #26@51} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9DD8] Interval 11: RefPositions {#27@52 #31@59} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451AAAF8] Interval 12: RefPositions {#30@58 #32@59} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E30] Interval 13: RefPositions {#33@60 #37@67} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451AAE28] Interval 14: RefPositions {#36@66 #38@67} physReg:NA Preferences=[allFloat] RelatedInterval [0000021C451A9E88] Interval 15: RefPositions {#39@68 #41@69} physReg:NA Preferences=[mm0] RelatedInterval [0000021C451AB158] Interval 16: RefPositions {#43@70 #45@71} physReg:NA Preferences=[mm0] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ #2 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #6 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #4 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #19 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #10 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #8 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #22 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #14 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #12 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #28 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #16 RefTypeDef IND BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allFloat] minReg=1 last> #34 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #20 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #25 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> #23 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #26 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> BB02 regmask=[allFloat] minReg=1 last regOptional> BB02 regmask=[allFloat] minReg=1 last> #31 RefTypeDef ADD BB02 regmask=[allFloat] minReg=1> #29 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #32 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> BB02 regmask=[allFloat] minReg=1 last regOptional> BB02 regmask=[allFloat] minReg=1 last> #37 RefTypeDef ADD BB02 regmask=[allFloat] minReg=1> #35 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> #38 RefTypeDef MUL BB02 regmask=[allFloat] minReg=1> BB02 regmask=[allFloat] minReg=1 last regOptional> BB02 regmask=[allFloat] minReg=1 last> #41 RefTypeDef ADD BB02 regmask=[mm0] minReg=1> #42 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> #44 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> #45 RefTypeDef PUTARG_REG BB02 regmask=[mm0] minReg=1 fixed> #53 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[mm0] minReg=1 last> BB02 regmask=[mm1] minReg=1 last> BB02 regmask=[mm2] minReg=1 last> BB02 regmask=[mm3] minReg=1 last> BB02 regmask=[mm4] minReg=1 last> BB02 regmask=[mm5] minReg=1 last> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 #2 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #6 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #10 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #14 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V01 #19 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #20 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> --- V02 #22 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #23 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> --- V03 #28 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #29 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> --- V04 #34 RefTypeDef STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> #35 RefTypeUse LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 last regOptional> --- V05 --- V06 Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+ LocRP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm6 |mm7 | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+ | |V0 a| | | | | | | | | | 0.#0 V0 Parm Keep rcx | |V0 a| | | | | | | | | | 1.#1 BB1 PredBB0 | |V0 a| | | | | | | | | | 7.#2 V0 Use Keep rcx | |V0 a| | | | | | | | | | 8.#3 I5 Def Alloc mm0 | |V0 a| | | | |I5 a| | | | | 9.#4 I5 Use * Keep mm0 | |V0 a| | | | |I5 a| | | | | 10.#5 V1 Def Alloc mm0 | |V0 a| | | | |V1 a| | | | | 15.#6 V0 Use Keep rcx | |V0 a| | | | |V1 a| | | | | 16.#7 I6 Def Alloc mm1 | |V0 a| | | | |V1 a|I6 a| | | | 17.#8 I6 Use * Keep mm1 | |V0 a| | | | |V1 a|I6 a| | | | 18.#9 V2 Def Alloc mm1 | |V0 a| | | | |V1 a|V2 a| | | | 23.#10 V0 Use Keep rcx | |V0 a| | | | |V1 a|V2 a| | | | 24.#11 I7 Def Alloc mm2 | |V0 a| | | | |V1 a|V2 a|I7 a| | | 25.#12 I7 Use * Keep mm2 | |V0 a| | | | |V1 a|V2 a|I7 a| | | 26.#13 V3 Def Alloc mm2 | |V0 a| | | | |V1 a|V2 a|V3 a| | | 31.#14 V0 Use * Keep rcx | |V0 a| | | | |V1 a|V2 a|V3 a| | | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ LocRP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 32.#15 I8 Def Alloc mm3 | | | | | | |V1 a|V2 a|V3 a|I8 a| | | 33.#16 I8 Use * Keep mm3 | | | | | | |V1 a|V2 a|V3 a|I8 a| | | 34.#17 V4 Def Alloc mm3 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ LocRP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 35.#18 BB2 PredBB1 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | 43.#19 V1 Use Keep mm0 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | 43.#20 V1 Use * Keep mm0 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | 44.#21 I9 Def Alloc mm0 | | | | | | |I9 a|V2 a|V3 a|V4 a| | | 49.#22 V2 Use Keep mm1 | | | | | | |I9 a|V2 a|V3 a|V4 a| | | 49.#23 V2 Use * Keep mm1 | | | | | | |I9 a|V2 a|V3 a|V4 a| | | 50.#24 I10 Def Alloc mm1 | | | | | | |I9 a|I10a|V3 a|V4 a| | | 51.#25 I9 Use * Keep mm0 | | | | | | |I9 a|I10a|V3 a|V4 a| | | 51.#26 I10 Use * Keep mm1 | | | | | | |I9 a|I10a|V3 a|V4 a| | | 52.#27 I11 Def Alloc mm0 | | | | | | |I11a| |V3 a|V4 a| | | 57.#28 V3 Use Keep mm2 | | | | | | |I11a| |V3 a|V4 a| | | 57.#29 V3 Use * Keep mm2 | | | | | | |I11a| |V3 a|V4 a| | | 58.#30 I12 Def Alloc mm2 | | | | | | |I11a| |I12a|V4 a| | | 59.#31 I11 Use * Keep mm0 | | | | | | |I11a| |I12a|V4 a| | | 59.#32 I12 Use * Keep mm2 | | | | | | |I11a| |I12a|V4 a| | | 60.#33 I13 Def Alloc mm0 | | | | | | |I13a| | |V4 a| | | 65.#34 V4 Use Keep mm3 | | | | | | |I13a| | |V4 a| | | 65.#35 V4 Use * Keep mm3 | | | | | | |I13a| | |V4 a| | | 66.#36 I14 Def Alloc mm3 | | | | | | |I13a| | |I14a| | | 67.#37 I13 Use * Keep mm0 | | | | | | |I13a| | |I14a| | | 67.#38 I14 Use * Keep mm3 | | | | | | |I13a| | |I14a| | | 68.#39 I15 Def Alloc mm0 | | | | | | |I15a| | | | | | 69.#40 mm0 Fixd Keep mm0 | | | | | | |I15a| | | | | | 69.#41 I15 Use * Keep mm0 | | | | | | |I15a| | | | | | 70.#42 mm0 Fixd Keep mm0 | | | | | | | | | | | | | 70.#43 I16 Def Alloc mm0 | | | | | | |I16a| | | | | | 71.#44 mm0 Fixd Keep mm0 | | | | | | |I16a| | | | | | 71.#45 I16 Use * Keep mm0 | | | | | | |I16a| | | | | | 72.#46 rax Kill Keep rax | | | | | | | | | | | | | 72.#47 rcx Kill Keep rcx | | | | | | | | | | | | | 72.#48 rdx Kill Keep rdx | | | | | | | | | | | | | 72.#49 r8 Kill Keep r8 | | | | | | | | | | | | | 72.#50 r9 Kill Keep r9 | | | | | | | | | | | | | 72.#51 r10 Kill Keep r10 | | | | | | | | | | | | | 72.#52 r11 Kill Keep r11 | | | | | | | | | | | | | 72.#53 mm0 Kill Keep mm0 | | | | | | | | | | | | | 72.#54 mm1 Kill Keep mm1 | | | | | | | | | | | | | 72.#55 mm2 Kill Keep mm2 | | | | | | | | | | | | | 72.#56 mm3 Kill Keep mm3 | | | | | | | | | | | | | 72.#57 mm4 Kill Keep mm4 | | | | | | | | | | | | | 72.#58 mm5 Kill Keep mm5 | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ #2 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #6 RefTypeUse LCL_VAR BB01 regmask=[rcx] minReg=1> #4 RefTypeDef IND BB01 regmask=[mm0] minReg=1> BB01 regmask=[mm0] minReg=1 last> #19 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm0] minReg=1> #10 RefTypeUse LCL_VAR BB01 regmask=[rcx] minReg=1> #8 RefTypeDef IND BB01 regmask=[mm1] minReg=1> BB01 regmask=[mm1] minReg=1 last> #22 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm1] minReg=1> #14 RefTypeUse LCL_VAR BB01 regmask=[rcx] minReg=1> #12 RefTypeDef IND BB01 regmask=[mm2] minReg=1> BB01 regmask=[mm2] minReg=1 last> #28 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm2] minReg=1> LCL_VAR BB01 regmask=[rcx] minReg=1 last> #16 RefTypeDef IND BB01 regmask=[mm3] minReg=1> BB01 regmask=[mm3] minReg=1 last> #34 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm3] minReg=1> #20 RefTypeUse LCL_VAR BB02 regmask=[mm0] minReg=1> LCL_VAR BB02 regmask=[mm0] minReg=1 last regOptional> #25 RefTypeDef MUL BB02 regmask=[mm0] minReg=1> #23 RefTypeUse LCL_VAR BB02 regmask=[mm1] minReg=1> LCL_VAR BB02 regmask=[mm1] minReg=1 last regOptional> #26 RefTypeDef MUL BB02 regmask=[mm1] minReg=1> BB02 regmask=[mm0] minReg=1 last regOptional> BB02 regmask=[mm1] minReg=1 last> #31 RefTypeDef ADD BB02 regmask=[mm0] minReg=1> #29 RefTypeUse LCL_VAR BB02 regmask=[mm2] minReg=1> LCL_VAR BB02 regmask=[mm2] minReg=1 last regOptional> #32 RefTypeDef MUL BB02 regmask=[mm2] minReg=1> BB02 regmask=[mm0] minReg=1 last regOptional> BB02 regmask=[mm2] minReg=1 last> #37 RefTypeDef ADD BB02 regmask=[mm0] minReg=1> #35 RefTypeUse LCL_VAR BB02 regmask=[mm3] minReg=1> LCL_VAR BB02 regmask=[mm3] minReg=1 last regOptional> #38 RefTypeDef MUL BB02 regmask=[mm3] minReg=1> BB02 regmask=[mm0] minReg=1 last regOptional> BB02 regmask=[mm3] minReg=1 last> #41 RefTypeDef ADD BB02 regmask=[mm0] minReg=1> #42 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> #44 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> #45 RefTypeDef PUTARG_REG BB02 regmask=[mm0] minReg=1 fixed> #53 RefTypeFixedReg BB02 regmask=[mm0] minReg=1> BB02 regmask=[mm0] minReg=1 last fixed> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[mm0] minReg=1 last> BB02 regmask=[mm1] minReg=1 last> BB02 regmask=[mm2] minReg=1 last> BB02 regmask=[mm3] minReg=1 last> BB02 regmask=[mm4] minReg=1 last> BB02 regmask=[mm5] minReg=1 last> VAR REFPOSITIONS AFTER ALLOCATION --- V00 #2 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #6 RefTypeUse LCL_VAR BB01 regmask=[rcx] minReg=1> #10 RefTypeUse LCL_VAR BB01 regmask=[rcx] minReg=1> #14 RefTypeUse LCL_VAR BB01 regmask=[rcx] minReg=1> LCL_VAR BB01 regmask=[rcx] minReg=1 last> --- V01 #19 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm0] minReg=1> #20 RefTypeUse LCL_VAR BB02 regmask=[mm0] minReg=1> LCL_VAR BB02 regmask=[mm0] minReg=1 last regOptional> --- V02 #22 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm1] minReg=1> #23 RefTypeUse LCL_VAR BB02 regmask=[mm1] minReg=1> LCL_VAR BB02 regmask=[mm1] minReg=1 last regOptional> --- V03 #28 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm2] minReg=1> #29 RefTypeUse LCL_VAR BB02 regmask=[mm2] minReg=1> LCL_VAR BB02 regmask=[mm2] minReg=1 last regOptional> --- V04 #34 RefTypeDef STORE_LCL_VAR BB01 regmask=[mm3] minReg=1> #35 RefTypeUse LCL_VAR BB02 regmask=[mm3] minReg=1> LCL_VAR BB02 regmask=[mm3] minReg=1 last regOptional> --- V05 --- V06 Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V02 V03 V04} Has NoCritical Edges Prior to Resolution BB01 use def in out {V00} {V01 V02 V03 V04} {V00} {V01 V02 V03 V04} Var=Reg beg of BB01: V00=rcx Var=Reg end of BB01: V01=mm0 V02=mm1 V03=mm2 V04=mm3 BB02 use def in out {V01 V02 V03 V04} {} {V01 V02 V03 V04} {} Var=Reg beg of BB02: V01=mm0 V02=mm1 V03=mm2 V04=mm3 Var=Reg end of BB02: none RESOLVING EDGES Set V00 argument initial register to rcx Trees after linear scan register allocator (LSRA) -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N003 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 rcx REG rcx $80 /--* t44 byref N005 (???,???) [000072] -c---------- t72 = * LEA(b+0) byref REG NA /--* t72 byref N007 ( 4, 3) [000047] x----------- t47 = * IND float REG mm0 /--* t47 float N009 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 mm0 REG mm0 N011 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 rcx REG rcx $80 /--* t50 byref N013 (???,???) [000073] -c---------- t73 = * LEA(b+4) byref REG NA /--* t73 byref N015 ( 4, 4) [000053] x----------- t53 = * IND float REG mm1 /--* t53 float N017 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 mm1 REG mm1 N019 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 rcx REG rcx $80 /--* t57 byref N021 (???,???) [000074] -c---------- t74 = * LEA(b+8) byref REG NA /--* t74 byref N023 ( 4, 4) [000060] x----------- t60 = * IND float REG mm2 /--* t60 float N025 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 mm2 REG mm2 N027 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 rcx (last use) REG rcx $80 /--* t64 byref N029 (???,???) [000075] -c---------- t75 = * LEA(b+12) byref REG NA /--* t75 byref N031 ( 4, 4) [000067] x----------- t67 = * IND float REG mm3 /--* t67 float N033 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 mm3 REG mm3 ------------ BB02 [000..03D) (return), preds={BB01} succs={} N037 ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 REG NA N039 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 mm0 REG mm0 N041 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 mm0 (last use) REG mm0 /--* t3 float +--* t6 float N043 ( 7, 8) [000007] ----G------- t7 = * MUL float REG mm0 N045 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 mm1 REG mm1 N047 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 mm1 (last use) REG mm1 /--* t10 float +--* t13 float N049 ( 7, 8) [000014] ----G------- t14 = * MUL float REG mm1 /--* t7 float +--* t14 float N051 ( 19, 20) [000015] ----G------- t15 = * ADD float REG mm0 N053 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 mm2 REG mm2 N055 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 mm2 (last use) REG mm2 /--* t18 float +--* t21 float N057 ( 7, 8) [000022] ----G------- t22 = * MUL float REG mm2 /--* t15 float +--* t22 float N059 ( 31, 32) [000023] ----G------- t23 = * ADD float REG mm0 N061 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 mm3 REG mm3 N063 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 mm3 (last use) REG mm3 /--* t26 float +--* t29 float N065 ( 7, 8) [000030] ----G------- t30 = * MUL float REG mm3 /--* t23 float +--* t30 float N067 ( 43, 44) [000031] ----G------- t31 = * ADD float REG mm0 /--* t31 float N069 (???,???) [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 N071 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void N073 ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c REG NA N075 ( 0, 0) [000035] ------------ RETURN void REG NA $300 ------------------------------------------------------------------------------------------------------------------- Final allocation ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ LocRP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 V0 Parm Alloc rcx | |V0 a| | | | | | | | | | | 1.#1 BB1 PredBB0 | |V0 a| | | | | | | | | | | 7.#2 V0 Use Keep rcx | |V0 a| | | | | | | | | | | 8.#3 I5 Def Alloc mm0 | |V0 a| | | | |I5 a| | | | | | 9.#4 I5 Use * Keep mm0 | |V0 a| | | | |I5 i| | | | | | 10.#5 V1 Def Alloc mm0 | |V0 a| | | | |V1 a| | | | | | 15.#6 V0 Use Keep rcx | |V0 a| | | | |V1 a| | | | | | 16.#7 I6 Def Alloc mm1 | |V0 a| | | | |V1 a|I6 a| | | | | 17.#8 I6 Use * Keep mm1 | |V0 a| | | | |V1 a|I6 i| | | | | 18.#9 V2 Def Alloc mm1 | |V0 a| | | | |V1 a|V2 a| | | | | 23.#10 V0 Use Keep rcx | |V0 a| | | | |V1 a|V2 a| | | | | 24.#11 I7 Def Alloc mm2 | |V0 a| | | | |V1 a|V2 a|I7 a| | | | 25.#12 I7 Use * Keep mm2 | |V0 a| | | | |V1 a|V2 a|I7 i| | | | 26.#13 V3 Def Alloc mm2 | |V0 a| | | | |V1 a|V2 a|V3 a| | | | 31.#14 V0 Use * Keep rcx | |V0 i| | | | |V1 a|V2 a|V3 a| | | | 32.#15 I8 Def Alloc mm3 | | | | | | |V1 a|V2 a|V3 a|I8 a| | | 33.#16 I8 Use * Keep mm3 | | | | | | |V1 a|V2 a|V3 a|I8 i| | | 34.#17 V4 Def Alloc mm3 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ LocRP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 | ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 35.#18 BB2 PredBB1 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | 43.#19 V1 Use Keep mm0 | | | | | | |V1 a|V2 a|V3 a|V4 a| | | 43.#20 V1 Use * Keep mm0 | | | | | | |V1 i|V2 a|V3 a|V4 a| | | 44.#21 I9 Def Alloc mm0 | | | | | | |I9 a|V2 a|V3 a|V4 a| | | 49.#22 V2 Use Keep mm1 | | | | | | |I9 a|V2 a|V3 a|V4 a| | | 49.#23 V2 Use * Keep mm1 | | | | | | |I9 a|V2 i|V3 a|V4 a| | | 50.#24 I10 Def Alloc mm1 | | | | | | |I9 a|I10a|V3 a|V4 a| | | 51.#25 I9 Use * Keep mm0 | | | | | | |I9 i|I10a|V3 a|V4 a| | | 51.#26 I10 Use * Keep mm1 | | | | | | | |I10i|V3 a|V4 a| | | 52.#27 I11 Def Alloc mm0 | | | | | | |I11a| |V3 a|V4 a| | | 57.#28 V3 Use Keep mm2 | | | | | | |I11a| |V3 a|V4 a| | | 57.#29 V3 Use * Keep mm2 | | | | | | |I11a| |V3 i|V4 a| | | 58.#30 I12 Def Alloc mm2 | | | | | | |I11a| |I12a|V4 a| | | 59.#31 I11 Use * Keep mm0 | | | | | | |I11i| |I12a|V4 a| | | 59.#32 I12 Use * Keep mm2 | | | | | | | | |I12i|V4 a| | | 60.#33 I13 Def Alloc mm0 | | | | | | |I13a| | |V4 a| | | 65.#34 V4 Use Keep mm3 | | | | | | |I13a| | |V4 a| | | 65.#35 V4 Use * Keep mm3 | | | | | | |I13a| | |V4 i| | | 66.#36 I14 Def Alloc mm3 | | | | | | |I13a| | |I14a| | | 67.#37 I13 Use * Keep mm0 | | | | | | |I13i| | |I14a| | | 67.#38 I14 Use * Keep mm3 | | | | | | | | | |I14i| | | 68.#39 I15 Def Alloc mm0 | | | | | | |I15a| | | | | | 69.#40 mm0 Fixd Keep mm0 | | | | | | |I15a| | | | | | 69.#41 I15 Use * Keep mm0 | | | | | | |I15i| | | | | | 70.#42 mm0 Fixd Keep mm0 | | | | | | | | | | | | | 70.#43 I16 Def Alloc mm0 | | | | | | |I16a| | | | | | 71.#44 mm0 Fixd Keep mm0 | | | | | | |I16a| | | | | | 71.#45 I16 Use * Keep mm0 | | | | | | |I16i| | | | | | 72.#46 rax Kill Keep rax | | | | | | | | | | | | | 72.#47 rcx Kill Keep rcx | | | | | | | | | | | | | 72.#48 rdx Kill Keep rdx | | | | | | | | | | | | | 72.#49 r8 Kill Keep r8 | | | | | | | | | | | | | 72.#50 r9 Kill Keep r9 | | | | | | | | | | | | | 72.#51 r10 Kill Keep r10 | | | | | | | | | | | | | 72.#52 r11 Kill Keep r11 | | | | | | | | | | | | | 72.#53 mm0 Kill Keep mm0 | | | | | | | | | | | | | 72.#54 mm1 Kill Keep mm1 | | | | | | | | | | | | | 72.#55 mm2 Kill Keep mm2 | | | | | | | | | | | | | 72.#56 mm3 Kill Keep mm3 | | | | | | | | | | | | | 72.#57 mm4 Kill Keep mm4 | | | | | | | | | | | | | 72.#58 mm5 Kill Keep mm5 | | | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 5 Total Reg Cand Vars: 5 Total number of Intervals: 16 Total number of RefPositions: 58 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rcx) BB01 [???..???), preds={} succs={BB02} ===== N003. V00(rcx) N005. STK = LEA(b+0) ; rcx N007. mm0 = IND ; STK * N009. V01(mm0); mm0 N011. V00(rcx) N013. STK = LEA(b+4) ; rcx N015. mm1 = IND ; STK * N017. V02(mm1); mm1 N019. V00(rcx) N021. STK = LEA(b+8) ; rcx N023. mm2 = IND ; STK * N025. V03(mm2); mm2 N027. V00(rcx*) N029. STK = LEA(b+12); rcx* N031. mm3 = IND ; STK * N033. V04(mm3); mm3 Var=Reg end of BB01: V01=mm0 V02=mm1 V03=mm2 V04=mm3 BB02 [000..03D) (return), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V01=mm0 V02=mm1 V03=mm2 V04=mm3 N037. IL_OFFSET IL offset: 0x0 REG NA N039. V01(mm0) N041. V01(mm0*) N043. mm0 = MUL ; mm0,mm0* N045. V02(mm1) N047. V02(mm1*) N049. mm1 = MUL ; mm1,mm1* N051. mm0 = ADD ; mm0,mm1 N053. V03(mm2) N055. V03(mm2*) N057. mm2 = MUL ; mm2,mm2* N059. mm0 = ADD ; mm0,mm2 N061. V04(mm3) N063. V04(mm3*) N065. mm3 = MUL ; mm3,mm3* N067. mm0 = ADD ; mm0,mm3 N069. mm0 = PUTARG_REG; mm0 N071. CALL ; mm0 N073. IL_OFFSET IL offset: 0x3c REG NA N075. RETURN Var=Reg end of BB02: none *************** In genGenerateCode() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..03D) (return) i gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rcx) Modified regs: [rax rcx rdx r8-r11 mm0-mm5] Callee-saved registers pushed: 0 [] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V06 OutArgs, size=32, stkOffs=-0x28 ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 14, 12 ) byref -> rcx ; V01 tmp0 [V01,T01] ( 3, 4 ) float -> mm0 V05.X(offs=0x00) P-INDEP ; V02 tmp1 [V02,T02] ( 3, 4 ) float -> mm1 V05.Y(offs=0x04) P-INDEP ; V03 tmp2 [V03,T03] ( 3, 4 ) float -> mm2 V05.Z(offs=0x08) P-INDEP ; V04 tmp3 [V04,T04] ( 3, 4 ) float -> mm3 V05.W(offs=0x0c) P-INDEP ;* V05 tmp4 [V05 ] ( 0, 0 ) struct (16) zero-ref ; V06 OutArgs [V06 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] ; ; Lcl frame size = 40 =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.40030060: i internal label target LIR BB01 IN (1)={V00 } + ByrefExposed + GcHeap OUT(4)={ V01 V02 V03 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(rcx) Change life 0000000000000000 {} -> 0000000000000001 {V00} V00 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} Live regs: (unchanged) 00000002 {rcx} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000002 {rcx} L_M46274_BB01: Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000002 {rcx} Setting stack level from -572662307 to 0 Scope info: begin block BB01, IL range [???..???) Scope info: ignoring block beginning Generating: N003 ( 1, 1) [000044] ------------ t44 = LCL_VAR byref V00 arg0 u:2 rcx REG rcx $80 /--* t44 byref Generating: N005 (???,???) [000072] -c---------- t72 = * LEA(b+0) byref REG NA /--* t72 byref Generating: N007 ( 4, 3) [000047] x----------- t47 = * IND float REG mm0 IN0001: vmovss xmm0, dword ptr [rcx] /--* t47 float Generating: N009 ( 4, 3) [000048] DA---------- * STORE_LCL_VAR float V01 tmp0 d:2 mm0 REG mm0 V01 in reg mm0 is becoming live [000048] Live regs: 00000002 {rcx} => 00000002 {rcx xmm0} Live vars: {V00} => {V00 V01} Generating: N011 ( 1, 1) [000050] ------------ t50 = LCL_VAR byref V00 arg0 u:2 rcx REG rcx $80 /--* t50 byref Generating: N013 (???,???) [000073] -c---------- t73 = * LEA(b+4) byref REG NA /--* t73 byref Generating: N015 ( 4, 4) [000053] x----------- t53 = * IND float REG mm1 IN0002: vmovss xmm1, dword ptr [rcx+4] /--* t53 float Generating: N017 ( 4, 4) [000054] DA---------- * STORE_LCL_VAR float V02 tmp1 d:2 mm1 REG mm1 V02 in reg mm1 is becoming live [000054] Live regs: 00000002 {rcx xmm0} => 00000002 {rcx xmm0 xmm1} Live vars: {V00 V01} => {V00 V01 V02} Generating: N019 ( 1, 1) [000057] ------------ t57 = LCL_VAR byref V00 arg0 u:2 rcx REG rcx $80 /--* t57 byref Generating: N021 (???,???) [000074] -c---------- t74 = * LEA(b+8) byref REG NA /--* t74 byref Generating: N023 ( 4, 4) [000060] x----------- t60 = * IND float REG mm2 IN0003: vmovss xmm2, dword ptr [rcx+8] /--* t60 float Generating: N025 ( 4, 4) [000061] DA---------- * STORE_LCL_VAR float V03 tmp2 d:2 mm2 REG mm2 V03 in reg mm2 is becoming live [000061] Live regs: 00000002 {rcx xmm0 xmm1} => 00000002 {rcx xmm0 xmm1 xmm2} Live vars: {V00 V01 V02} => {V00 V01 V02 V03} Generating: N027 ( 1, 1) [000064] ------------ t64 = LCL_VAR byref V00 arg0 u:2 rcx (last use) REG rcx $80 /--* t64 byref Generating: N029 (???,???) [000075] -c---------- t75 = * LEA(b+12) byref REG NA /--* t75 byref Generating: N031 ( 4, 4) [000067] x----------- t67 = * IND float REG mm3 V00 in reg rcx is becoming dead [000064] Live regs: 00000002 {rcx xmm0 xmm1 xmm2} => 00000000 {xmm0 xmm1 xmm2} Live vars: {V00 V01 V02 V03} => {V01 V02 V03} Byref regs: 00000002 {rcx} => 00000000 {} IN0004: vmovss xmm3, dword ptr [rcx+12] /--* t67 float Generating: N033 ( 4, 4) [000068] DA---------- * STORE_LCL_VAR float V04 tmp3 d:2 mm3 REG mm3 V04 in reg mm3 is becoming live [000068] Live regs: 00000000 {xmm0 xmm1 xmm2} => 00000000 {xmm0 xmm1 xmm2 xmm3} Live vars: {V01 V02 V03} => {V01 V02 V03 V04} Scope info: end block BB01, IL range [???..???) Scope info: ignoring block end =============== Generating BB02 [000..03D) (return), preds={BB01} succs={} flags=0x00000000.40080020: i gcsafe LIR BB02 IN (4)={V01 V02 V03 V04} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB02 V01(mm0) V02(mm1) V03(mm2) V04(mm3) Liveness not changing: 000000000000001E {V01 V02 V03 V04} Live regs: 00000000 {} => 00000000 {xmm0 xmm1 xmm2 xmm3} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M46274_BB02: Scope info: begin block BB02, IL range [000..03D) Scope info: open scopes = Added IP mapping: 0x0000 STACK_EMPTY (G_M46274_IG02,ins#4,ofs#23) label Generating: N037 ( 57, 50) [000034] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N039 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V01 tmp0 u:2 mm0 REG mm0 Generating: N041 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V01 tmp0 u:2 mm0 (last use) REG mm0 /--* t3 float +--* t6 float Generating: N043 ( 7, 8) [000007] ----G------- t7 = * MUL float REG mm0 V01 in reg mm0 is becoming dead [000006] Live regs: 00000000 {xmm0 xmm1 xmm2 xmm3} => 00000000 {xmm1 xmm2 xmm3} Live vars: {V01 V02 V03 V04} => {V02 V03 V04} IN0005: vmulss xmm0, xmm0 Generating: N045 ( 1, 2) [000010] ------------ t10 = LCL_VAR float V02 tmp1 u:2 mm1 REG mm1 Generating: N047 ( 1, 2) [000013] ------------ t13 = LCL_VAR float V02 tmp1 u:2 mm1 (last use) REG mm1 /--* t10 float +--* t13 float Generating: N049 ( 7, 8) [000014] ----G------- t14 = * MUL float REG mm1 V02 in reg mm1 is becoming dead [000013] Live regs: 00000000 {xmm1 xmm2 xmm3} => 00000000 {xmm2 xmm3} Live vars: {V02 V03 V04} => {V03 V04} IN0006: vmulss xmm1, xmm1 /--* t7 float +--* t14 float Generating: N051 ( 19, 20) [000015] ----G------- t15 = * ADD float REG mm0 IN0007: vaddss xmm0, xmm1 Generating: N053 ( 1, 2) [000018] ------------ t18 = LCL_VAR float V03 tmp2 u:2 mm2 REG mm2 Generating: N055 ( 1, 2) [000021] ------------ t21 = LCL_VAR float V03 tmp2 u:2 mm2 (last use) REG mm2 /--* t18 float +--* t21 float Generating: N057 ( 7, 8) [000022] ----G------- t22 = * MUL float REG mm2 V03 in reg mm2 is becoming dead [000021] Live regs: 00000000 {xmm2 xmm3} => 00000000 {xmm3} Live vars: {V03 V04} => {V04} IN0008: vmulss xmm2, xmm2 /--* t15 float +--* t22 float Generating: N059 ( 31, 32) [000023] ----G------- t23 = * ADD float REG mm0 IN0009: vaddss xmm0, xmm2 Generating: N061 ( 1, 2) [000026] ------------ t26 = LCL_VAR float V04 tmp3 u:2 mm3 REG mm3 Generating: N063 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V04 tmp3 u:2 mm3 (last use) REG mm3 /--* t26 float +--* t29 float Generating: N065 ( 7, 8) [000030] ----G------- t30 = * MUL float REG mm3 V04 in reg mm3 is becoming dead [000029] Live regs: 00000000 {xmm3} => 00000000 {} Live vars: {V04} => {} IN000a: vmulss xmm3, xmm3 /--* t23 float +--* t30 float Generating: N067 ( 43, 44) [000031] ----G------- t31 = * ADD float REG mm0 IN000b: vaddss xmm0, xmm3 /--* t31 float Generating: N069 (???,???) [000076] ----G------- t76 = * PUTARG_REG float REG mm0 /--* t76 float arg0 in mm0 Generating: N071 ( 57, 50) [000032] --CXG------- * CALL void System.Console.WriteLine $VN.Void Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN000c: call System.Console:WriteLine(float) Added IP mapping: 0x003C STACK_EMPTY (G_M46274_IG02,ins#12,ofs#63) Generating: N073 ( 0, 0) [000036] ------------ IL_OFFSET void IL offset: 0x3c REG NA Generating: N075 ( 0, 0) [000035] ------------ RETURN void REG NA $300 Scope info: end block BB02, IL range [000..03D) Scope info: ending scope, LVnum=0 [000..03D) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M46274_IG02,ins#12,ofs#63) label Reserving epilog IG for block BB02 IN000d: nop G_M46274_IG02: ; offs=000000H, funclet=00 *************** After placeholder IG creation G_M46274_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M46274_IG02: ; offs=000000H, size=0040H, gcrefRegs=00000000 {}, byrefRegs=00000002 {rcx}, byref G_M46274_IG03: ; epilog placeholder, next placeholder=, BB02 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000002 {rcx} Liveness not changing: 0000000000000000 {} # compCycleEstimate = 73, compSizeEstimate = 65 Program:Test3(struct) ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 14, 12 ) byref -> rcx ; V01 tmp0 [V01,T01] ( 3, 4 ) float -> mm0 V05.X(offs=0x00) P-INDEP ; V02 tmp1 [V02,T02] ( 3, 4 ) float -> mm1 V05.Y(offs=0x04) P-INDEP ; V03 tmp2 [V03,T03] ( 3, 4 ) float -> mm2 V05.Z(offs=0x08) P-INDEP ; V04 tmp3 [V04,T04] ( 3, 4 ) float -> mm3 V05.W(offs=0x0c) P-INDEP ;* V05 tmp4 [V05 ] ( 0, 0 ) struct (16) zero-ref ; V06 OutArgs [V06 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] ; ; Lcl frame size = 40 *************** Before prolog / epilog generation G_M46274_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M46274_IG02: ; offs=000000H, size=0040H, gcrefRegs=00000000 {}, byrefRegs=00000002 {rcx}, byref G_M46274_IG03: ; epilog placeholder, next placeholder=, BB02 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000002 {rcx} Recording Var Locations at start of BB01 V00(rcx) *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M46274_IG01,ins#0,ofs#0) label __prolog: IN000e: sub rsp, 40 IN000f: vzeroupper *************** In genFnPrologCalleeRegArgs() for int regs *************** In genEnregisterIncomingStackArgs() G_M46274_IG01: ; offs=000000H, funclet=00 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000002 {rcx} IN0010: add rsp, 40 IN0011: ret G_M46274_IG03: ; offs=000040H, funclet=00 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M46274_IG01: ; func=00, offs=000000H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M46274_IG02: ; offs=000007H, size=0040H, gcrefRegs=00000000 {}, byrefRegs=00000002 {rcx}, byref G_M46274_IG03: ; offs=000047H, size=0005H, epilog, nogc, emitadd *************** In emitJumpDistBind() Hot code size = 0x4C bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x6) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M46274_IG01: ; func=00, offs=000000H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN000e: 000000 4883EC28 sub rsp, 40 IN000f: 000004 C5F877 vzeroupper G_M46274_IG02: ; func=00, offs=000007H, size=0040H, gcrefRegs=00000000 {}, byrefRegs=00000002 {rcx}, byref New byrReg live regs=00000002 {rcx} byrReg +[rcx] IN0001: 000007 C4E17A1001 vmovss xmm0, dword ptr [rcx] IN0002: 00000C C4E17A104904 vmovss xmm1, dword ptr [rcx+4] IN0003: 000012 C4E17A105108 vmovss xmm2, dword ptr [rcx+8] IN0004: 000018 C4E17A10590C vmovss xmm3, dword ptr [rcx+12] IN0005: 00001E C4E17A59C0 vmulss xmm0, xmm0 IN0006: 000023 C4E17259C9 vmulss xmm1, xmm1 IN0007: 000028 C4E17A58C1 vaddss xmm0, xmm1 IN0008: 00002D C4E16A59D2 vmulss xmm2, xmm2 IN0009: 000032 C4E17A58C2 vaddss xmm0, xmm2 IN000a: 000037 C4E16259DB vmulss xmm3, xmm3 IN000b: 00003C C4E17A58C3 vaddss xmm0, xmm3 New byrReg live regs=00000000 {} byrReg -[rcx] [5F4F9988] ptr arg pop 0 IN000c: 000041 E89AD3FFFF call System.Console:WriteLine(float) IN000d: 000046 90 nop G_M46274_IG03: ; func=00, offs=000047H, size=0005H, epilog, nogc, emitadd IN0010: 000047 4883C428 add rsp, 40 IN0011: 00004B C3 ret Allocated method code size = 76 , actual size = 76 *************** After end code gen, before unwindEmit() G_M46274_IG01: ; func=00, offs=000000H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN000e: 000000 sub rsp, 40 IN000f: 000004 vzeroupper G_M46274_IG02: ; offs=000007H, size=0040H, gcrefRegs=00000000 {}, byrefRegs=00000002 {rcx}, byref IN0001: 000007 vmovss xmm0, dword ptr [rcx] IN0002: 00000C vmovss xmm1, dword ptr [rcx+4] IN0003: 000012 vmovss xmm2, dword ptr [rcx+8] IN0004: 000018 vmovss xmm3, dword ptr [rcx+12] IN0005: 00001E vmulss xmm0, xmm0 IN0006: 000023 vmulss xmm1, xmm1 IN0007: 000028 vaddss xmm0, xmm1 IN0008: 00002D vmulss xmm2, xmm2 IN0009: 000032 vaddss xmm0, xmm2 IN000a: 000037 vmulss xmm3, xmm3 IN000b: 00003C vaddss xmm0, xmm3 IN000c: 000041 call System.Console:WriteLine(float) IN000d: 000046 nop G_M46274_IG03: ; offs=000047H, size=0005H, epilog, nogc, emitadd IN0010: 000047 add rsp, 40 IN0011: 00004B ret Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x00004c (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x04 CountOfUnwindCodes: 1 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x04 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 4 * 8 + 8 = 40 = 0x28 allocUnwindInfo(pHotCode=0x00007FF8F9AD4890, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x4c, unwindSize=0x6, pUnwindBlock=0x0000021C451A352A, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 4 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x0000001E ( STACK_EMPTY ) IL offs 0x003C : 0x00000046 ( STACK_EMPTY ) IL offs EPILOG : 0x00000046 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 1 *************** Variable debug info 1 vars 0( UNKNOWN) : From 00000000h to 00000007h, in rcx *************** In gcInfoBlockHdrSave() Set code length to 76. Set ReturnKind to Scalar. Set Outgoing stack arg area size to 32. Defining 1 call sites: Offset 0x41, size 5. Method code size: 76 Allocations for Program:Test3(struct) (MethodHash=f3234b3d) count: 555, size: 57378, max = 3072 allocateMemory: 131072, nraUsed: 71584 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 11.26% ASTNode | 10064 | 17.54% InstDesc | 2808 | 4.89% ImpStack | 0 | 0.00% BasicBlock | 1136 | 1.98% fgArgInfo | 56 | 0.10% fgArgInfoPtrArr | 8 | 0.01% FlowList | 32 | 0.06% TreeStatementList | 0 | 0.00% SiScope | 72 | 0.13% FlatFPStateX87 | 0 | 0.00% DominatorMemory | 88 | 0.15% LSRA | 3556 | 6.20% LSRA_Interval | 1496 | 2.61% LSRA_RefPosition | 3776 | 6.58% Reachability | 16 | 0.03% SSA | 1292 | 2.25% ValueNumber | 10915 | 19.02% LvaTable | 2292 | 3.99% UnwindInfo | 0 | 0.00% hashBv | 80 | 0.14% bitset | 144 | 0.25% FixedBitVect | 0 | 0.00% Generic | 644 | 1.12% IndirAssignMap | 56 | 0.10% FieldSeqStore | 336 | 0.59% ZeroOffsetFieldMap | 56 | 0.10% ArrayInfoMap | 56 | 0.10% MemoryPhiArg | 0 | 0.00% CSE | 1904 | 3.32% GC | 1349 | 2.35% CorSig | 104 | 0.18% Inlining | 368 | 0.64% ArrayStack | 0 | 0.00% DebugInfo | 208 | 0.36% DebugOnly | 6863 | 11.96% Codegen | 0 | 0.00% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 159 | 0.28% RangeCheck | 0 | 0.00% CopyProp | 984 | 1.71% ****** DONE compiling Program:Test3(struct) 30