From 539d02a8240ea7220d7ff4d2cd08e2af8b3e46e4 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Mon, 10 Feb 2025 17:52:31 -0800 Subject: [PATCH] Update SVE instructions that writes to GC regs --- src/coreclr/jit/emitarm64.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index d0dbc6367be2fe..5cc121542b05f1 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -1087,6 +1087,22 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id) case IF_SR_1A: // SR_1A ................ ...........ttttt Rt (dc zva, mrs) return ins == INS_mrs_tpid0; + // Below SVE instructions write to GPR and hence GC reg + case IF_SVE_CO_3A: // clasta, clastb + case IF_SVE_BM_1A: // decb, decd, dech, decw, incb, incd, inch, incw + case IF_SVE_BO_1A: // sqdecb, sqdecd, sqdech, sqdecw, sqincb, sqincd, sqinch, sqincw, uqdecb, uqdecd, uqdech, + // uqdecw, uqincb, uqincd, uqinch, uqincw + case IF_SVE_CS_3A: // lasta, lastb + case IF_SVE_DK_3A: // cntp + case IF_SVE_DL_2A: // cntp + case IF_SVE_DM_2A: // decp, incp + case IF_SVE_DO_2A: // sqdecp, sqincp, uqdecp, uqincp + case IF_SVE_BB_2A: // addpl, addvl + case IF_SVE_BC_1A: // rdvl + case IF_SVE_BL_1A: // cntb, cntd, cnth, cntw + case IF_SVE_DS_2A: // ctermeq, ctermne + return true; + default: return false; }