stm32/spi: slave mode support

[Dirbaio]

No description provided.

[vldm]

Hi, i want to implement this mode.
I already experimented with it, and the blocking mode working fine. (two stm32f407 discovery boards communicate correctly)
But then i tried to combine master and slave on single board to emulate Double SPI.
Using DMA, and found an issues, with first clock (that looks like pullup registor to me)
.

Oscilloscope Image of problem

Master and slave send &[0b10010001]

During tranfser initialization clock rise up and slave shift its registor.

The research lead me to the

embassy/embassy-stm32/src/spi/mod.rs

Lines 443 to 446 in a0f1b0e

	unsafe {
	T::REGS.cr1().modify(|w| {
	w.set_spe(false);
	});

- in this lines spi is disabled.

1. Can you clarify is it important to reset spe flag during reconfiguration, i cannot find any info in my manual about this.

1.1. On my case it works without spi enabled flag changing - so this can be solution.

1.2. Other solution would be to set slave select signal only after reseting spi. But in order to make this work we need to change interface of transfer_inner to something like:

async fn transfer_inner<W: Word>(
        &mut self,
        read: *mut [W],
        write: *const [W],
        mut handle_slave_select: impl FnMut(),
    ) -> Result<(), Error> 

In embedded-has-async they propose to move this logic to level of SPI device https://docs.rs/embedded-hal-async/0.1.0-alpha.1/src/embedded_hal_async/spi.rs.html#59

2. The second issue that blocks me from complete implementation is about sending only one byte (spi word?) trough DMA.
   For some reason, in this scenario, it tries to send same byte multiple time. If i send two bytes or more - it works fine.

[rokadvednt03]

async fn transfer_inner<W: Word>(
&mut self,
read: *mut [W],
write: *const [W],
mut handle_slave_select: impl FnMut(),
) -> Result<(), Error>