From 72dd7bf2834776d3145d2c113faf7d8e084dd38b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 16 Jul 2021 14:51:25 +0200 Subject: [PATCH] mac/core/LiteEthMACCore: Switch CDC to ClockDomainCrossing and reduce buffering. --- liteeth/mac/core.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py index e4b107c2..9929b5ec 100644 --- a/liteeth/mac/core.py +++ b/liteeth/mac/core.py @@ -103,10 +103,9 @@ def __init__(self, phy, dw, endianness="big", with_preamble_crc=True, with_paddi rx_pipeline += [rx_converter] # Cross Domain Crossing - tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64) - rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), 64) - self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc) - self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc) + tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="sys", cd_to="eth_tx", depth=32) + rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="eth_rx", cd_to="sys", depth=32) + self.submodules += tx_cdc, rx_cdc tx_pipeline += [tx_cdc] rx_pipeline += [rx_cdc]