From fe7321d4a1b33f730fa077682fe9e6202c37bd8f Mon Sep 17 00:00:00 2001
From: Taiki Endo <te316e89@gmail.com>
Date: Sun, 27 Oct 2024 16:20:43 +0900
Subject: [PATCH 1/2] Add XTENSA_ALLOWED_FEATURES to supported_target_features

---
 compiler/rustc_target/src/target_features.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs
index 86dab5f1399c5..bd479b41ceef7 100644
--- a/compiler/rustc_target/src/target_features.rs
+++ b/compiler/rustc_target/src/target_features.rs
@@ -566,6 +566,7 @@ impl super::spec::Target {
             "csky" => CSKY_ALLOWED_FEATURES,
             "loongarch64" => LOONGARCH_ALLOWED_FEATURES,
             "s390x" => IBMZ_ALLOWED_FEATURES,
+            "xtensa" => XTENSA_ALLOWED_FEATURES,
             _ => &[],
         }
     }

From e2b066222c60795e4e9237fca075381b4b3eb518 Mon Sep 17 00:00:00 2001
From: Taiki Endo <te316e89@gmail.com>
Date: Sun, 27 Oct 2024 18:09:30 +0900
Subject: [PATCH 2/2] Fix inline assembly test

---
 tests/assembly/asm/xtensa-types.rs | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/tests/assembly/asm/xtensa-types.rs b/tests/assembly/asm/xtensa-types.rs
index 8bdecc4f37b46..74908bc038f8f 100644
--- a/tests/assembly/asm/xtensa-types.rs
+++ b/tests/assembly/asm/xtensa-types.rs
@@ -1,9 +1,8 @@
-// min-llvm-version: 10.0.1
-// assembly-output: emit-asm
-// compile-flags: --target xtensa-esp32-none-elf
-// needs-llvm-components: xtensa
+//@ assembly-output: emit-asm
+//@ compile-flags: --target xtensa-esp32-none-elf
+//@ needs-llvm-components: xtensa
 
-#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
+#![feature(no_core, lang_items, rustc_attrs, repr_simd, asm_experimental_arch)]
 #![crate_type = "rlib"]
 #![no_core]
 #![allow(asm_sub_register, non_camel_case_types)]
@@ -68,25 +67,25 @@ macro_rules! check_general_reg {
 
 // CHECK-LABEL: reg_i8:
 // CHECK: #APP
-// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
+// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
 // CHECK: #NO_APP
 check_general_reg!(reg_i8 i8 reg "mov");
 
 // CHECK-LABEL: reg_i16:
 // CHECK: #APP
-// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
+// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
 // CHECK: #NO_APP
 check_general_reg!(reg_i16 i16 reg "mov");
 
 // CHECK-LABEL: reg_i32:
 // CHECK: #APP
-// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
+// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
 // CHECK: #NO_APP
 check_general_reg!(reg_i32 i32 reg "mov");
 
 // CHECK-LABEL: reg_ptr:
 // CHECK: #APP
-// CHECK: mov a{{[0-9]+}}, a{{[0-9]+}}
+// CHECK: or a{{[0-9]+}}, a{{[0-9]+}}, a{{[0-9]+}}
 // CHECK: #NO_APP
 check_general_reg!(reg_ptr ptr reg "mov");
 
@@ -111,25 +110,25 @@ macro_rules! check_explicit_reg {
 
 // CHECK-LABEL: a5_i8:
 // CHECK: #APP
-// CHECK: mov a5, a5
+// CHECK: or a5, a5, a5
 // CHECK: #NO_APP
 check_explicit_reg!(a5_i8 i8 "a5" "mov");
 
 // CHECK-LABEL: a5_i16:
 // CHECK: #APP
-// CHECK: mov a5, a5
+// CHECK: or a5, a5, a5
 // CHECK: #NO_APP
 check_explicit_reg!(a5_i16 i16 "a5" "mov");
 
-// CHECK-LABEL: a0_i32:
+// CHECK-LABEL: a5_i32:
 // CHECK: #APP
-// CHECK: mov a5, a5
+// CHECK: or a5, a5, a5
 // CHECK: #NO_APP
 check_explicit_reg!(a5_i32 i32 "a5" "mov");
 
 // CHECK-LABEL: a5_ptr:
 // CHECK: #APP
-// CHECK: mov a5, a5
+// CHECK: or a5, a5, a5
 // CHECK: #NO_APP
 check_explicit_reg!(a5_ptr ptr "a5" "mov");