diff --git a/boards/xtensa/up_squared_adsp/tools/logtool.py b/boards/xtensa/up_squared_adsp/tools/logtool.py
new file mode 100644
index 00000000000000..f6419d64ffc3a1
--- /dev/null
+++ b/boards/xtensa/up_squared_adsp/tools/logtool.py
@@ -0,0 +1,33 @@
+#!/usr/bin/python3
+
+#FILE = "/dev/shm/qemu-bridge-hp-sram-mem"
+FILE = "/sys/kernel/debug/sof/etrace"
+#OFFSET = 0x8000
+OFFSET = 0x0
+MAGIC = 0x55aa
+SLOT_NUM = 32
+SLOT_LEN = 256
+
+def read_id(f):
+    buf = f.read(2)
+    return int.from_bytes(buf, byteorder='little')
+
+def read_magic(f):
+    buf = f.read(2)
+    return int.from_bytes(buf, byteorder='little')
+
+def read_log_slot(f):
+    magic = read_magic(f)
+
+    if magic == MAGIC:
+        id = read_id(f)
+        slot = f.read(SLOT_LEN - 4)
+        logstr = slot.decode(errors='replace').split('\r', 1)[0]
+        print("id %d %s" % (id, logstr))
+
+# Open a file
+f = open(FILE, "rb")
+
+for x in range(0, SLOT_NUM):
+    f.seek(OFFSET + x * SLOT_LEN)
+    read_log_slot(f)
diff --git a/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/.gitignore b/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/.gitignore
new file mode 100644
index 00000000000000..9b1041a7a16961
--- /dev/null
+++ b/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/.gitignore
@@ -0,0 +1,2 @@
+zephyr_adsp_logger
+*.o
diff --git a/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/Makefile b/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/Makefile
new file mode 100644
index 00000000000000..0690ae7321f0f5
--- /dev/null
+++ b/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/Makefile
@@ -0,0 +1,14 @@
+.PHONY: all clean
+.SECONDARY:
+
+CFLAGS = -march=native -O2 -g
+
+EXECUTABLES = zephyr_adsp_logger
+
+all: $(EXECUTABLES)
+
+clean:
+	rm -f $(EXECUTABLES)
+
+%.o: %.c
+	$(C) $(CFLAGS) -c $< -o $@
diff --git a/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/zephyr_adsp_logger.c b/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/zephyr_adsp_logger.c
new file mode 100644
index 00000000000000..1abfafa5227115
--- /dev/null
+++ b/boards/xtensa/up_squared_adsp/tools/zephyr_adsp_logger/zephyr_adsp_logger.c
@@ -0,0 +1,207 @@
+#include <errno.h>
+#include <limits.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#define MAGIC		0x55AA
+
+struct config_t {
+	char *infile;
+
+	unsigned long int trace_size;
+	unsigned long int buf_size;
+
+	unsigned long int interval_usecs;
+} cfg;
+
+struct log_t {
+	uint16_t magic;
+	uint16_t id;
+	char log[0];
+};
+
+char *sof_etrace_path = "/sys/kernel/debug/sof/etrace";
+char *qemu_etrace_path = "/dev/shm/qemu-bridge-etrace-mem";
+
+unsigned long int default_trace_size = 0x2000;
+unsigned long int default_buf_size = 256;
+
+void usage(char *prog_name)
+{
+	fprintf(stdout, "Usage: %s [options]\n\n", prog_name);
+	fprintf(stdout, "Options:\n");
+	fprintf(stdout, "  -s        : Use %s as input\n", sof_etrace_path);
+	fprintf(stdout, "  -q        : Use %s as input\n", qemu_etrace_path);
+	fprintf(stdout, "  -i infile : Use infile as input\n");
+	fprintf(stdout, "\n");
+	fprintf(stdout,
+		"  -t size   : Size of the trace buffer (in bytes, default %lu)\n",
+		default_trace_size);
+	fprintf(stdout,
+		"  -b size   : Size of buffer of one log line (in bytes, default %lu)\n",
+		default_buf_size);
+	fprintf(stdout, "\n");
+	fprintf(stdout,
+		"  -n usecs  : Read logs with update interval (microseconds, default is to read once)\n");
+}
+
+int read_logs()
+{
+	FILE *fd;
+	int ret;
+	unsigned long int offset;
+	struct log_t *log;
+	uint8_t *buf = NULL;
+	char *log_buf = NULL;
+	unsigned int max_log_strlen;
+
+	max_log_strlen = cfg.buf_size - sizeof(log->magic) - sizeof(log->id);
+
+	/* Open file */
+	fd = fopen(cfg.infile, "rb");
+	if (!fd) {
+		fprintf(stderr,
+			"[ERROR] Cannot open %s for reading!\n", cfg.infile);
+		ret = -1;
+		goto read_out;
+	}
+
+	/* Allocate buffers */
+	buf = malloc(cfg.trace_size);
+	if (!buf) {
+		fprintf(stderr,
+			"[ERROR] Cannot allocate trace buffer!\n");
+		ret = -2;
+		goto read_out;
+	}
+
+	log_buf = malloc(cfg.buf_size + 1);
+	if (!log_buf) {
+		fprintf(stderr,
+			"[ERROR] Cannot allocate log buffer!\n");
+		ret = -2;
+		goto read_out;
+	}
+
+read_repeat:
+	fprintf(stdout, "\n");
+
+	/* Read everything in file */
+	rewind(fd);
+	ret = fread(buf, 1, cfg.trace_size, fd);
+	if (ret == 0) {
+		fprintf(stderr,
+			"[ERROR] Nothing to read?\n");
+		ret = -3;
+		goto read_out;
+	}
+
+	/* Go through each log line and display it */
+	offset = 0;
+	while ((offset + cfg.buf_size) <= cfg.trace_size) {
+		log = (struct log_t *)(buf + offset);
+
+		if (log->magic == MAGIC) {
+			/* Avoid non-null terminated strings */
+			ret = snprintf(log_buf, max_log_strlen,
+				       "%s", &log->log[0]);
+			log_buf[max_log_strlen] = 0;
+
+			fprintf(stdout,	"[ID:%5u] %s", log->id, log_buf);
+		}
+
+		/* Move to next log line */
+		offset += cfg.buf_size;
+	};
+
+	/* If interval is specified, wait and loop */
+	if (cfg.interval_usecs) {
+		usleep(cfg.interval_usecs);
+		goto read_repeat;
+	}
+
+	ret = 0;
+
+read_out:
+	if (buf) {
+		free(buf);
+	}
+	if (log_buf) {
+		free(log_buf);
+	}
+	if (fd) {
+		fclose(fd);
+	}
+	return ret;
+}
+
+int main(int argc, char *argv[])
+{
+	int opt, ret = 0;
+
+	/* Defaults */
+	cfg.infile = sof_etrace_path;
+	cfg.trace_size = default_trace_size;
+	cfg.buf_size = default_buf_size;
+	cfg.interval_usecs = 0;
+
+	/* Parse arguments */
+	while ((opt = getopt(argc, argv, "hsqi:t:b:n:")) != -1) {
+		switch (opt) {
+		case 's':
+			cfg.infile = sof_etrace_path;
+			break;
+		case 'q':
+			cfg.infile = qemu_etrace_path;
+			break;
+		case 'i':
+			cfg.infile = optarg;
+			break;
+		case 't':
+			cfg.trace_size = strtoul(optarg, NULL, 0);
+			if (cfg.trace_size == ULONG_MAX) {
+				fprintf(stderr, "[ERROR] Error parsing -t\n");
+				ret = errno;
+				goto main_out;
+			}
+			break;
+		case 'b':
+			cfg.buf_size = strtoul(optarg, NULL, 0);
+			if (cfg.buf_size == ULONG_MAX) {
+				fprintf(stderr, "[ERROR] Error parsing -b\n");
+				ret = errno;
+				goto main_out;
+			}
+			break;
+		case 'n':
+			cfg.interval_usecs = strtoul(optarg, NULL, 0);
+			if (cfg.interval_usecs == ULONG_MAX) {
+				fprintf(stderr, "[ERROR] Error parsing -n\n");
+				ret = errno;
+				goto main_out;
+			}
+			break;
+		case 'h':
+		default:
+			usage(argv[0]);
+			goto main_out;
+		}
+	}
+
+	fprintf(stdout, "[INFO ] Using %s as input file\n", cfg.infile);
+	fprintf(stdout, "[INFO ] Trace buffer size: %lu\n", cfg.trace_size);
+	fprintf(stdout, "[INFO ] Log line buffer size: %lu\n", cfg.buf_size);
+	if (cfg.interval_usecs == 0) {
+		fprintf(stdout, "[INFO ] Read once\n");
+	} else {
+		fprintf(stdout, "[INFO ] Update Interval: %lu\n",
+			cfg.interval_usecs);
+	}
+
+	ret = read_logs();
+
+main_out:
+	return ret;
+}
diff --git a/samples/audio/sof/prj.conf b/samples/audio/sof/prj.conf
index 91e324113ae9d1..aa91e76f15960f 100644
--- a/samples/audio/sof/prj.conf
+++ b/samples/audio/sof/prj.conf
@@ -1,6 +1,7 @@
 CONFIG_SOF=y
 CONFIG_LOG=y
 CONFIG_LOG_BACKEND_XTENSA_SIM=y
+CONFIG_LOG_BACKEND_ADSP=y
 CONFIG_LOG_IMMEDIATE=y
 CONFIG_SOF_LOG_LEVEL=4
 # SOF requires malloc/calloc
diff --git a/samples/hello_world/src/main.c b/samples/hello_world/src/main.c
index be4146c1c9eb42..6c5c8a27dc698f 100644
--- a/samples/hello_world/src/main.c
+++ b/samples/hello_world/src/main.c
@@ -7,80 +7,7 @@
 #include <zephyr.h>
 #include <sys/printk.h>
 
-#include <stdint.h>
-
-#include <xtensa/config/core.h>
-#include <xtensa/hal.h>
-
-#define CONFIG_TRACE 1
-
-/* SRAM window 0 FW "registers" */
-#define SRAM_REG_ROM_STATUS                     0x0
-#define SRAM_REG_FW_STATUS                      0x4
-#define SRAM_REG_FW_TRACEP                      0x8
-#define SRAM_REG_FW_IPC_RECEIVED_COUNT          0xc
-#define SRAM_REG_FW_IPC_PROCESSED_COUNT         0x10
-#define SRAM_REG_FW_END                         0x14
-
-#define HP_SRAM_BASE            0xBE000000
-#define HEAP_HP_BUFFER_BASE     HP_SRAM_BASE
-#define HEAP_HP_BUFFER_SIZE     0x8000
-#define SRAM_WND_BASE           (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
-#define SRAM_SW_REG_BASE        (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
-#define MAILBOX_SW_REG_BASE     SRAM_SW_REG_BASE
-
-#define SRAM_TRACE_BASE         SRAM_WND_BASE
-#if CONFIG_TRACE
-#define SRAM_TRACE_SIZE         0x2000
-#else
-#define SRAM_TRACE_SIZE         0
-#endif
-#define SRAM_DEBUG_BASE         (SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
-#define SRAM_DEBUG_SIZE         0x800
-#define SRAM_EXCEPT_BASE        (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
-#define SRAM_EXCEPT_SIZE        0x800
-#define SRAM_STREAM_BASE        (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
-#define SRAM_STREAM_SIZE        0x1000
-#define SRAM_INBOX_BASE         (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#define SRAM_INBOX_SIZE         0x2000
-
-#define DCACHE_LINE_SIZE        XCHAL_DCACHE_LINESIZE
-
-static inline void dcache_writeback_region(void *addr, size_t size)
-{
-#if XCHAL_DCACHE_SIZE > 0
-	xthal_dcache_region_writeback(addr, size);
-#endif
-}
-
-static inline void mailbox_sw_reg_write(size_t offset, uint32_t src)
-{
-	*((volatile uint32_t*)(MAILBOX_SW_REG_BASE + offset)) = src;
-	dcache_writeback_region((void *)(MAILBOX_SW_REG_BASE + offset),
-                                sizeof(src));
-}
-
-/* Platform defined trace code */
-#define platform_trace_point(__x) \
-        mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x))
-
-
-#define SHIM_BASE             0x00001000
-
-static inline uint32_t shim_read(uint32_t reg)
-{
-        return *((volatile uint32_t*)(SHIM_BASE + reg));
-}
-
-static inline void shim_write(uint32_t reg, uint32_t val)
-{
-        *((volatile uint32_t*)(SHIM_BASE + reg)) = val;
-}
-
 void main(void)
 {
-	mailbox_sw_reg_write(SRAM_REG_ROM_STATUS, 0xabbac0fe);
-#if 0
-	platform_trace_point(0xabbac0ffe);
-#endif
+	printk("Hello World! %s\n", CONFIG_BOARD);
 }
diff --git a/soc/xtensa/intel_apl_adsp/include/config.h b/soc/xtensa/intel_apl_adsp/include/config.h
new file mode 100644
index 00000000000000..6851ce08ae2f04
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/config.h
@@ -0,0 +1 @@
+#include "sof_config.h"
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/asm_ldo_management.h b/soc/xtensa/intel_apl_adsp/include/platform/asm_ldo_management.h
new file mode 100644
index 00000000000000..b142abcfd10ceb
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/asm_ldo_management.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Lech Betlej <lech.betlej@linux.intel.com>
+ */
+
+/**
+ * \file platform/apollolake/include/platform/asm_ldo_management.h
+ * \brief Macros for controlling LDO state specific for cAVS 1.5
+ * \author Lech Betlej <lech.betlej@linux.intel.com>
+ */
+#ifndef ASM_LDO_MANAGEMENT_H
+#define ASM_LDO_MANAGEMENT_H
+
+#ifndef ASSEMBLY
+#warning "Header can only be used by assembly sources."
+#endif
+
+#include <platform/shim.h>
+
+.macro m_cavs_set_ldo_state state, ax
+movi \ax, (SHIM_BASE + SHIM_LDOCTL)
+s32i \state, \ax, 0
+memw
+// wait loop > 300ns (min 100ns required)
+movi \ax, 128
+1 :
+addi \ax, \ax, -1
+nop
+bnez \ax, 1b
+.endm
+
+.macro m_cavs_set_hpldo_state state, ax, ay
+movi \ax, (SHIM_BASE + SHIM_LDOCTL)
+l32i \ay, \ax, 0
+
+movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
+and \ay, \ax, \ay
+or \state, \ay, \state
+
+m_cavs_set_ldo_state \state, \ax
+.endm
+
+.macro m_cavs_set_lpldo_state state, ax, ay
+movi \ax, (SHIM_BASE + SHIM_LDOCTL)
+l32i \ay, \ax, 0
+// LP SRAM mask
+movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
+and \ay, \ax, \ay
+or \state, \ay, \state
+
+m_cavs_set_ldo_state \state, \ax
+.endm
+
+.macro m_cavs_set_ldo_on_state ax, ay, az
+movi \ay, (SHIM_BASE + SHIM_LDOCTL)
+l32i \az, \ay, 0
+
+movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
+and \az, \ax, \az
+movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
+or \ax, \az, \ax
+
+m_cavs_set_ldo_state \ax, \ay
+.endm
+
+.macro m_cavs_set_ldo_off_state ax, ay, az
+// wait loop > 300ns (min 100ns required)
+movi \ax, 128
+1 :
+		addi \ax, \ax, -1
+		nop
+		bnez \ax, 1b
+movi \ay, (SHIM_BASE + SHIM_LDOCTL)
+l32i \az, \ay, 0
+
+movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
+and \az, \az, \ax
+
+movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
+or \ax, \ax, \az
+
+s32i \ax, \ay, 0
+l32i \ax, \ay, 0
+.endm
+
+.macro m_cavs_set_ldo_bypass_state ax, ay, az
+// wait loop > 300ns (min 100ns required)
+movi \ax, 128
+1 :
+		addi \ax, \ax, -1
+		nop
+		bnez \ax, 1b
+movi \ay, (SHIM_BASE + SHIM_LDOCTL)
+l32i \az, \ay, 0
+
+movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
+and \az, \az, \ax
+
+movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
+or \ax, \ax, \az
+
+s32i \ax, \ay, 0
+l32i \ax, \ay, 0
+.endm
+
+#endif /* ASM_LDO_MANAGEMENT_H */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/asm_memory_management.h b/soc/xtensa/intel_apl_adsp/include/platform/asm_memory_management.h
new file mode 100644
index 00000000000000..59a1980511bdab
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/asm_memory_management.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Lech Betlej <lech.betlej@linux.intel.com>
+ */
+
+/**
+ * \file platform/apollolake/include/platform/asm_memory_management.h
+ * \brief Macros for power gating memory banks specific for Apollolake
+ * \author Lech Betlej <lech.betlej@linux.intel.com>
+ */
+#ifndef ASM_MEMORY_MANAGEMENT_H
+#define ASM_MEMORY_MANAGEMENT_H
+
+#ifndef ASSEMBLY
+#warning "ASSEMBLY macro not defined."
+#endif
+
+#include <sof/bit.h>
+#include <platform/shim.h>
+#include <platform/platform.h>
+
+	/* Macro powers down entire hpsram. on entry literals and code for
+	 * section from where this code is executed needs to be placed in
+	 * memory which is not HPSRAM (in case when this code is located in
+	 * HPSRAM lock memory in L1$ or L1 SRAM)
+	 */
+	.macro m_cavs_hpsram_power_off ax, ay, az
+	// SEGMENT #0
+	movi \az, (SHIM_BASE + SHIM_HSPGISTS)
+	movi \ax, (SHIM_BASE + SHIM_HSPGCTL)
+	movi \ay, HPSRAM_MASK(0)
+	s32i \ay, \ax, 0
+	memw
+	/* since HPSRAM EBB bank #0 might be used as buffer for legacy
+	 * streaming, should not be checked in status
+	 */
+	movi \ax, 0xfffffffe
+	and \ay, \ay, \ax
+	1 :
+	l32i \ax, \az, 0
+	and \ax, \ax, \ay
+	bne \ax, \ay, 1b
+	/* there is no possibility to check from DSP whether EBB #0 is actually
+	 * in use therefore wait additional 4K DSP cycles as chicken check -
+	 * after that time EBB #0 should be already power gated unless is used
+	 * by other HW components (like HD-A)
+	 */
+	l32i \ax, \az, 0
+	beq \ax, \ay, m_cavs_hpsram_power_off_end
+	movi \ax, 4096
+	1 :
+	addi \ax, \ax, -1
+	bnez \ax, 1b
+	m_cavs_hpsram_power_off_end :
+	.endm
+
+	.macro m_cavs_lpsram_power_off ax, ay, az
+	movi \az, (SHIM_BASE + SHIM_LSPGISTS)
+	movi \ax, (SHIM_BASE + SHIM_LSPGCTL)
+	movi \ay, LPSRAM_MASK()
+	s32i \ay, \ax, 0
+	memw
+	1 :
+	l32i \ax, \az, 0
+	bne \ax, \ay, 1b
+	.endm
+
+#endif /* ASM_MEMORY_MANAGEMENT_H */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/clk-map.h b/soc/xtensa/intel_apl_adsp/include/platform/clk-map.h
new file mode 100644
index 00000000000000..30735583295468
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/clk-map.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_CLOCK_MAP__
+#define __INCLUDE_CLOCK_MAP__
+
+#include <sof/clk.h>
+
+#define CLK_MAX_CPU_HZ		400000000
+
+static const struct freq_table cpu_freq[] = {
+	{100000000, 100000, 0x3},
+	{200000000, 200000, 0x1},
+	{CLK_MAX_CPU_HZ, 400000, 0x0}, /* the default one */
+};
+
+#define CPU_DEFAULT_IDX	2
+
+/* IMPORTANT: array should be filled in increasing order
+ * (regarding to .freq field)
+ */
+static const struct freq_table ssp_freq[] = {
+	{ 19200000, 19200, CLOCK_SSP_XTAL_OSCILLATOR }, /* the default one */
+	{ 24576000, 24576, CLOCK_SSP_AUDIO_CARDINAL },
+	{ 96000000, 96000, CLOCK_SSP_PLL_FIXED },
+};
+
+#define SSP_DEFAULT_IDX	0
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/clk.h b/soc/xtensa/intel_apl_adsp/include/platform/clk.h
new file mode 100644
index 00000000000000..08a977ec9a3749
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_CLOCK__
+#define __PLATFORM_CLOCK__
+
+#include <cavs/clk.h>
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/dai.h b/soc/xtensa/intel_apl_adsp/include/platform/dai.h
new file mode 100644
index 00000000000000..8d0a99bfb1e58b
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/dai.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Marcin Maka <marcin.maka@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_DAI_H__
+#define __PLATFORM_DAI_H__
+
+/* APOLLOLAKE */
+
+/* SSP */
+
+/*
+ * Number of base and extended SSP ports must be defined separately
+ * since some HW registers are in two groups, one for base and one
+ * for extended.
+ */
+
+/** \brief Number of 'base' SSP ports available */
+#define DAI_NUM_SSP_BASE	4
+
+/** \brief Number of 'extended' SSP ports available */
+#define DAI_NUM_SSP_EXT		2
+
+/* HD/A */
+
+/** \brief Number of HD/A Link Outputs */
+#define DAI_NUM_HDA_OUT		6
+
+/** \brief Number of HD/A Link Inputs */
+#define DAI_NUM_HDA_IN		7
+
+int dai_init(void);
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/dma.h b/soc/xtensa/intel_apl_adsp/include/platform/dma.h
new file mode 100644
index 00000000000000..64867c5c79bc39
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/dma.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_DMA_H__
+#define __PLATFORM_DMA_H__
+
+#include <stdint.h>
+#include <sof/io.h>
+#include <arch/cache.h>
+#include <sof/dma.h>
+
+/* available DMACs */
+#define DMA_GP_LP_DMAC0		0
+#define DMA_GP_LP_DMAC1		1
+#define DMA_GP_HP_DMAC0		2
+#define DMA_GP_HP_DMAC1		3
+#define DMA_HOST_IN_DMAC	4
+#define DMA_HOST_OUT_DMAC	5
+#define DMA_LINK_IN_DMAC	6
+#define DMA_LINK_OUT_DMAC	7
+
+/* mappings - TODO improve API to get type */
+#define DMA_ID_DMAC0		DMA_HOST_IN_DMAC
+#define DMA_ID_DMAC1		DMA_GP_LP_DMAC0
+#define DMA_ID_DMAC2		DMA_HOST_OUT_DMAC
+#define DMA_ID_DMAC3		DMA_GP_HP_DMAC0
+#define DMA_ID_DMAC4		DMA_GP_LP_DMAC1
+#define DMA_ID_DMAC5		DMA_GP_HP_DMAC1
+#define DMA_ID_DMAC6		DMA_LINK_IN_DMAC
+#define DMA_ID_DMAC7		DMA_LINK_OUT_DMAC
+
+/* handshakes */
+#define DMA_HANDSHAKE_DMIC_CH0	0
+#define DMA_HANDSHAKE_DMIC_CH1	1
+#define DMA_HANDSHAKE_SSP0_TX	2
+#define DMA_HANDSHAKE_SSP0_RX	3
+#define DMA_HANDSHAKE_SSP1_TX	4
+#define DMA_HANDSHAKE_SSP1_RX	5
+#define DMA_HANDSHAKE_SSP2_TX	6
+#define DMA_HANDSHAKE_SSP2_RX	7
+#define DMA_HANDSHAKE_SSP3_TX	8
+#define DMA_HANDSHAKE_SSP3_RX	9
+#define DMA_HANDSHAKE_SSP4_TX	10
+#define DMA_HANDSHAKE_SSP4_RX	11
+#define DMA_HANDSHAKE_SSP5_TX	12
+#define DMA_HANDSHAKE_SSP5_RX	13
+
+#define dma_chan_irq(dma, cpu, chan) \
+	(dma_irq(dma, cpu) + (channel << SOF_IRQ_BIT_SHIFT))
+
+int dmac_init(void);
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/dw-dma.h b/soc/xtensa/intel_apl_adsp/include/platform/dw-dma.h
new file mode 100644
index 00000000000000..a5e2c96df23e54
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/dw-dma.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2019 Intel Corporation. All rights reserved.
+ *
+ * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_DW_DMA_H__
+#define __INCLUDE_PLATFORM_DW_DMA_H__
+
+#include <cavs/dw-dma.h>
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/idc.h b/soc/xtensa/intel_apl_adsp/include/platform/idc.h
new file mode 100644
index 00000000000000..12d970130fa455
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/idc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_IDC_H__
+#define __INCLUDE_PLATFORM_IDC_H__
+
+#include <cavs/idc.h>
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/interrupt.h b/soc/xtensa/intel_apl_adsp/include/platform/interrupt.h
new file mode 100644
index 00000000000000..3de728ca264147
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/interrupt.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_INTERRUPT__
+#define __INCLUDE_PLATFORM_INTERRUPT__
+
+#include <stdint.h>
+#include <sof/interrupt-map.h>
+
+#define PLATFORM_IRQ_CHILDREN	32
+
+/* IRQ numbers - wrt Tensilica DSP */
+#define IRQ_NUM_SOFTWARE0	0	/* level 1 */
+#define IRQ_NUM_TIMER1		1	/* level 1 */
+#define IRQ_NUM_EXT_LEVEL1	2	/* level 1 */
+#define IRQ_NUM_SOFTWARE1	3	/* level 1 */
+#define IRQ_NUM_SOFTWARE2	4	/* level 2 */
+#define IRQ_NUM_TIMER2		5	/* level 2 */
+#define IRQ_NUM_EXT_LEVEL2	6	/* level 2 */
+#define IRQ_NUM_SOFTWARE3	7	/* level 2 */
+#define IRQ_NUM_SOFTWARE4	8	/* level 3 */
+#define IRQ_NUM_TIMER3		9	/* level 3 */
+#define IRQ_NUM_EXT_LEVEL3	10	/* level 3 */
+#define IRQ_NUM_SOFTWARE5	11	/* level 3 */
+#define IRQ_NUM_SOFTWARE6	12	/* level 4 */
+#define IRQ_NUM_EXT_LEVEL4	13	/* level 4 */
+#define IRQ_NUM_SOFTWARE7	14	/* level 4 */
+#define IRQ_NUM_SOFTWARE8	15	/* level 5 */
+#define IRQ_NUM_EXT_LEVEL5	16	/* level 5 */
+#define IRQ_NUM_EXT_LEVEL6	17	/* level 5 */
+#define IRQ_NUM_EXT_LEVEL7	18	/* level 5 */
+#define IRQ_NUM_SOFTWARE9	19	/* level 5 */
+#define IRQ_NUM_NMI		20	/* level 7 */
+
+/* IRQ Level 2 bits */
+#define IRQ_BIT_LVL2_HP_GP_DMA0(x)	(x + 24)
+#define IRQ_BIT_LVL2_WALL_CLK1		23
+#define IRQ_BIT_LVL2_WALL_CLK0		22
+#define IRQ_BIT_LVL2_L2_MEMERR		21
+#define IRQ_BIT_LVL2_SHA256		16
+#define IRQ_BIT_LVL2_L2_CACHE		15
+#define IRQ_BIT_LVL2_IDC		8
+#define IRQ_BIT_LVL2_HOST_IPC		7
+#define IRQ_BIT_LVL2_CSME_IPC		6
+#define IRQ_BIT_LVL2_PMC_IPC		5
+
+/* IRQ Level 3 bits */
+#define IRQ_BIT_LVL3_CODE_LOADER	31
+#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x)	(16 + x)
+#define IRQ_BIT_LVL3_HOST_STREAM_IN(x)	(0 + x)
+
+/* IRQ Level 4 bits */
+#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x)	(16 + x)
+#define IRQ_BIT_LVL4_LINK_STREAM_IN(x)	(0 + x)
+
+/* IRQ Level 5 bits */
+#define IRQ_BIT_LVL5_LP_GP_DMA1(x)	(24 + x)
+#define IRQ_BIT_LVL5_LP_GP_DMA0(x)	(16 + x)
+#define IRQ_BIT_LVL5_DMIC(x)		6
+#define IRQ_BIT_LVL5_SSP(x)		(0 + x)
+
+/* Level 2 Peripheral IRQ mappings */
+#define IRQ_EXT_HP_GPDMA_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_HP_GP_DMA0(0), 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_IDC_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_IDC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_IPC_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_HOST_IPC, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_TSTAMP1_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK1, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_TSTAMP0_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK0, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_MERR_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_L2_MEMERR, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_L2CACHE_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_L2_CACHE, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+#define IRQ_EXT_SHA256_LVL2(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL2_SHA256, 2, xcpu, IRQ_NUM_EXT_LEVEL2)
+
+/* Level 3 Peripheral IRQ mappings */
+#define IRQ_EXT_CODE_DMA_LVL3(xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL3_CODE_LOADER, 3, xcpu, IRQ_NUM_EXT_LEVEL3)
+#define IRQ_EXT_HOST_DMA_IN_LVL3(xcpu, channel) \
+	SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_IN(channel), 3, xcpu, \
+		IRQ_NUM_EXT_LEVEL3)
+#define IRQ_EXT_HOST_DMA_OUT_LVL3(xcpu, channel) \
+	SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_OUT(channel), 3, xcpu, \
+		IRQ_NUM_EXT_LEVEL3)
+
+/* Level 4 Peripheral IRQ mappings */
+#define IRQ_EXT_LINK_DMA_IN_LVL4(xcpu, channel) \
+	SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_IN(channel), 4, xcpu, \
+		IRQ_NUM_EXT_LEVEL4)
+#define IRQ_EXT_LINK_DMA_OUT_LVL4(xcpu, channel) \
+	SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_OUT(channel), 4, xcpu, \
+		IRQ_NUM_EXT_LEVEL4)
+
+/* Level 5 Peripheral IRQ mappings */
+#define IRQ_EXT_LP_GPDMA0_LVL5(xcpu, channel) \
+	SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA0(channel), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+#define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
+	SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA1(channel), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+#define IRQ_EXT_SSPx_LVL5(x, xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL5_SSP(x), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+#define IRQ_EXT_DMIC_LVL5(x, xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL5_DMIC(x), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+
+/* IRQ Masks */
+#define IRQ_MASK_SOFTWARE0	(1 << IRQ_NUM_SOFTWARE0)
+#define IRQ_MASK_TIMER1		(1 << IRQ_NUM_TIMER1)
+#define IRQ_MASK_EXT_LEVEL1	(1 << IRQ_NUM_EXT_LEVEL1)
+#define IRQ_MASK_SOFTWARE1	(1 << IRQ_NUM_SOFTWARE1)
+#define IRQ_MASK_SOFTWARE2	(1 << IRQ_NUM_SOFTWARE2)
+#define IRQ_MASK_TIMER2		(1 << IRQ_NUM_TIMER2)
+#define IRQ_MASK_EXT_LEVEL2	(1 << IRQ_NUM_EXT_LEVEL2)
+#define IRQ_MASK_SOFTWARE3	(1 << IRQ_NUM_SOFTWARE3)
+#define IRQ_MASK_SOFTWARE4	(1 << IRQ_NUM_SOFTWARE4)
+#define IRQ_MASK_TIMER3		(1 << IRQ_NUM_TIMER3)
+#define IRQ_MASK_EXT_LEVEL3	(1 << IRQ_NUM_EXT_LEVEL3)
+#define IRQ_MASK_SOFTWARE5	(1 << IRQ_NUM_SOFTWARE5)
+#define IRQ_MASK_SOFTWARE6	(1 << IRQ_NUM_SOFTWARE6)
+#define IRQ_MASK_EXT_LEVEL4	(1 << IRQ_NUM_EXT_LEVEL4)
+#define IRQ_MASK_SOFTWARE7	(1 << IRQ_NUM_SOFTWARE7)
+#define IRQ_MASK_SOFTWARE8	(1 << IRQ_NUM_SOFTWARE8)
+#define IRQ_MASK_EXT_LEVEL5	(1 << IRQ_NUM_EXT_LEVEL5)
+#define IRQ_MASK_EXT_LEVEL6	(1 << IRQ_NUM_EXT_LEVEL6)
+#define IRQ_MASK_EXT_LEVEL7	(1 << IRQ_NUM_EXT_LEVEL7)
+#define IRQ_MASK_SOFTWARE9	(1 << IRQ_NUM_SOFTWARE9)
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/mailbox.h b/soc/xtensa/intel_apl_adsp/include/platform/mailbox.h
new file mode 100644
index 00000000000000..644d9bc368419b
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/mailbox.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_MAILBOX__
+#define __INCLUDE_PLATFORM_MAILBOX__
+
+#include <cavs/mailbox.h>
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/memory.h b/soc/xtensa/intel_apl_adsp/include/platform/memory.h
new file mode 100644
index 00000000000000..2b625471015d88
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/memory.h
@@ -0,0 +1,410 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_MEMORY_H__
+#define __PLATFORM_MEMORY_H__
+
+#ifdef CONFIG_SOF
+#include <config.h>
+#include <cavs/memory.h>
+#include <cavs/mailbox.h>
+#endif
+
+/* ===== Begin - from SOF arch/memory.h ===== */
+
+/* Stack size. */
+#define ARCH_STACK_SIZE		0x1000
+
+/* Stack total size. */
+#define ARCH_STACK_TOTAL_SIZE	(PLATFORM_CORE_COUNT * ARCH_STACK_SIZE)
+
+/* ===== End - from SOF arch/memory.h ===== */
+
+/* physical DSP addresses */
+
+/* shim */
+#define SHIM_BASE		0x00001000
+#define SHIM_SIZE		0x00000100
+
+/* cmd IO to audio codecs */
+#define CMD_BASE		0x00001100
+#define CMD_SIZE		0x00000010
+
+/* resource allocation */
+#define RES_BASE		0x00001110
+#define RES_SIZE		0x00000010
+
+/* IPC to the host */
+#define IPC_HOST_BASE		0x00001180
+#define IPC_HOST_SIZE		0x00000020
+
+/* intra DSP  IPC */
+#define IPC_DSP_SIZE		0x00000080
+#define IPC_DSP_BASE(x)		(0x00001200 + x * IPC_DSP_SIZE)
+
+/* SRAM window for HOST */
+#define HOST_WIN_SIZE		0x00000008
+#define HOST_WIN_BASE(x)	(0x00001580 + x * HOST_WIN_SIZE)
+
+/* IRQ controller */
+#define IRQ_BASE		0x00001600
+#define IRQ_SIZE		0x00000200
+
+/* time stamping */
+#define TIME_BASE		0x00001800
+#define TIME_SIZE		0x00000200
+
+/* M/N dividers */
+#define MN_BASE			0x00008E00
+#define MN_SIZE			0x00000200
+
+/* low power DMA position */
+#define LP_GP_DMA_LINK_SIZE	0x00000010
+#define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE)
+
+/* high performance DMA position */
+#define HP_GP_DMA_LINK_SIZE	0x00000010
+#define HP_GP_DMA_LINK_BASE(x)	(0x00001D00 + x * HP_GP_DMA_LINK_SIZE)
+
+/* link DMAC stream */
+#define GTW_LINK_OUT_STREAM_SIZE	0x00000020
+#define GTW_LINK_OUT_STREAM_BASE(x) \
+	(0x00002400 + x * GTW_LINK_OUT_STREAM_SIZE)
+
+#define GTW_LINK_IN_STREAM_SIZE	0x00000020
+#define GTW_LINK_IN_STREAM_BASE(x) \
+	(0x00002600 + x * GTW_LINK_IN_STREAM_SIZE)
+
+/* host DMAC stream */
+#define GTW_HOST_OUT_STREAM_SIZE	0x00000040
+#define GTW_HOST_OUT_STREAM_BASE(x) \
+	(0x00002800 + x * GTW_HOST_OUT_STREAM_SIZE)
+
+#define GTW_HOST_IN_STREAM_SIZE		0x00000040
+#define GTW_HOST_IN_STREAM_BASE(x) \
+	(0x00002C00 + x * GTW_HOST_IN_STREAM_SIZE)
+
+/* code loader */
+#define GTW_CODE_LDR_SIZE	0x00000040
+#define GTW_CODE_LDR_BASE	0x00002BC0
+
+/* L2 TLBs */
+#define L2_HP_SRAM_TLB_SIZE	0x00001000
+#define L2_HP_SRAM_TLB_BASE	0x00003000
+
+/* DMICs */
+#define DMIC_BASE		0x00004000
+#define DMIC_SIZE		0x00004000
+
+/* SSP */
+#define SSP_SIZE		0x0000200
+#define SSP_BASE(x)		(0x00008000 + x * SSP_SIZE)
+
+/* low power DMACs */
+#define LP_GP_DMA_SIZE		0x00001000
+#define LP_GP_DMA_BASE(x)	(0x0000C000 + x * LP_GP_DMA_SIZE)
+
+/* high performance DMACs */
+#define HP_GP_DMA_SIZE		0x00001000
+#define HP_GP_DMA_BASE(x)	(0x0000E000 + x * HP_GP_DMA_SIZE)
+
+/* ROM */
+#define ROM_BASE		0xBEFE0000
+#define ROM_SIZE		0x00002000
+
+/* IMR accessible via L2$ */
+#define L2_SRAM_BASE		0xA000A000
+#define L2_SRAM_SIZE		0x00056000
+
+/* Heap section sizes for system runtime heap for master core */
+#define HEAP_SYS_RT_0_COUNT64		64
+#define HEAP_SYS_RT_0_COUNT512		16
+#define HEAP_SYS_RT_0_COUNT1024		4
+
+/* Heap section sizes for system runtime heap for slave core */
+#define HEAP_SYS_RT_X_COUNT64		32
+#define HEAP_SYS_RT_X_COUNT512		8
+#define HEAP_SYS_RT_X_COUNT1024		4
+
+/* Heap section sizes for module pool */
+#define HEAP_RT_COUNT64			128
+#define HEAP_RT_COUNT128		64
+#define HEAP_RT_COUNT256		128
+#define HEAP_RT_COUNT512		8
+#define HEAP_RT_COUNT1024		4
+
+#define L2_VECTOR_SIZE			0x1000
+
+/* Heap configuration */
+#define HEAP_SYSTEM_0_BASE	(SOF_FW_BASE + SOF_FW_MAX_SIZE)
+
+#define HEAP_SYSTEM_M_SIZE		0x8000	/* heap master core size */
+#define HEAP_SYSTEM_S_SIZE		0x5000	/* heap slave core size */
+#define HEAP_SYSTEM_T_SIZE \
+	(HEAP_SYSTEM_M_SIZE + ((PLATFORM_CORE_COUNT - 1) * HEAP_SYSTEM_S_SIZE))
+
+#define HEAP_SYS_RUNTIME_0_BASE \
+	(HEAP_SYSTEM_0_BASE + HEAP_SYSTEM_M_SIZE + \
+	((PLATFORM_CORE_COUNT - 1) * HEAP_SYSTEM_S_SIZE))
+
+#define HEAP_SYS_RUNTIME_M_SIZE \
+	(HEAP_SYS_RT_0_COUNT64 * 64 + HEAP_SYS_RT_0_COUNT512 * 512 + \
+	HEAP_SYS_RT_0_COUNT1024 * 1024)
+
+#define HEAP_SYS_RUNTIME_S_SIZE \
+	(HEAP_SYS_RT_X_COUNT64 * 64 + HEAP_SYS_RT_X_COUNT512 * 512 + \
+	HEAP_SYS_RT_X_COUNT1024 * 1024)
+
+#define HEAP_SYS_RUNTIME_T_SIZE \
+	(HEAP_SYS_RUNTIME_M_SIZE + ((PLATFORM_CORE_COUNT - 1) * \
+	HEAP_SYS_RUNTIME_S_SIZE))
+
+#define HEAP_RUNTIME_BASE \
+	(HEAP_SYS_RUNTIME_0_BASE + HEAP_SYS_RUNTIME_M_SIZE + \
+	((PLATFORM_CORE_COUNT - 1) * HEAP_SYS_RUNTIME_S_SIZE))
+
+#define HEAP_RUNTIME_SIZE \
+	(HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \
+	HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \
+	HEAP_RT_COUNT1024 * 1024)
+
+#define HEAP_BUFFER_BASE	(HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
+#define HEAP_BUFFER_SIZE	(SOF_STACK_END - HEAP_BUFFER_BASE)
+#define HEAP_BUFFER_BLOCK_SIZE	0x180
+#define HEAP_BUFFER_COUNT	(HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
+
+#define LOG_ENTRY_ELF_BASE	0x20000000
+#define LOG_ENTRY_ELF_SIZE	0x2000000
+
+/*
+ * The HP SRAM Region Apollolake is organised like this :-
+ * +--------------------------------------------------------------------------+
+ * | Offset              | Region         |  Size                             |
+ * +---------------------+----------------+-----------------------------------+
+ * | HP_SRAM_BASE        | DMA            |  HEAP_HP_BUFFER_SIZE              |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_TRACE_BASE     | Trace Buffer W3|  SRAM_TRACE_SIZE                  |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_DEBUG_BASE     | Debug data  W2 |  SRAM_DEBUG_SIZE                  |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_EXCEPT_BASE    | Debug data  W2 |  SRAM_EXCEPT_SIZE                 |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_STREAM_BASE    | Stream data W2 |  SRAM_STREAM_SIZE                 |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_INBOX_BASE     | Inbox  W1      |  SRAM_INBOX_SIZE                  |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_SW_REG_BASE    | SW Registers W0|  SRAM_SW_REG_SIZE                 |
+ * +---------------------+----------------+-----------------------------------+
+ * | SRAM_OUTBOX_BASE    | Outbox W0      |  SRAM_MAILBOX_SIZE                |
+ * +---------------------+----------------+-----------------------------------+
+ */
+
+/* HP SRAM */
+
+#define HP_SRAM_BASE		0xBE000000
+#define HP_SRAM_MASK		0xFF000000
+
+/* HP SRAM Heap */
+#define HEAP_HP_BUFFER_BASE	HP_SRAM_BASE
+#define HEAP_HP_BUFFER_SIZE	0x8000
+
+#define HEAP_HP_BUFFER_BLOCK_SIZE	0x180
+#define HEAP_HP_BUFFER_COUNT \
+	(HEAP_HP_BUFFER_SIZE / HEAP_HP_BUFFER_BLOCK_SIZE)
+
+/* HP SRAM windows */
+
+/* window 3 */
+#define SRAM_TRACE_BASE		SRAM_WND_BASE
+#if CONFIG_TRACE
+#define SRAM_TRACE_SIZE		0x2000
+#else
+#define SRAM_TRACE_SIZE		0
+#endif
+
+/* window 2 */
+#define SRAM_DEBUG_BASE		(SRAM_TRACE_BASE + SRAM_TRACE_SIZE)
+#define SRAM_DEBUG_SIZE		0x800
+
+#define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
+#define SRAM_EXCEPT_SIZE	0x800
+
+#define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
+#define SRAM_STREAM_SIZE	0x1000
+
+/* window 1 */
+#define SRAM_INBOX_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
+#define SRAM_INBOX_SIZE		0x2000
+
+/* window 0 */
+#define SRAM_SW_REG_BASE	(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
+#define SRAM_SW_REG_SIZE	0x1000
+
+/* SRAM window 0 FW "registers" */
+#define SRAM_REG_ROM_STATUS			0x0
+#define SRAM_REG_FW_STATUS			0x4
+#define SRAM_REG_FW_TRACEP			0x8
+#define SRAM_REG_FW_IPC_RECEIVED_COUNT		0xc
+#define SRAM_REG_FW_IPC_PROCESSED_COUNT		0x10
+#define SRAM_REG_FW_END				0x14
+
+#define SRAM_OUTBOX_BASE	(SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
+#define SRAM_OUTBOX_SIZE	0x1000
+
+#define HP_SRAM_WIN0_BASE	SRAM_SW_REG_BASE
+#define HP_SRAM_WIN0_SIZE	(SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE)
+#define HP_SRAM_WIN1_BASE	SRAM_INBOX_BASE
+#define HP_SRAM_WIN1_SIZE	SRAM_INBOX_SIZE
+#define HP_SRAM_WIN2_BASE	SRAM_DEBUG_BASE
+#define HP_SRAM_WIN2_SIZE	(SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
+				SRAM_STREAM_SIZE)
+#define HP_SRAM_WIN3_BASE	SRAM_TRACE_BASE
+#define HP_SRAM_WIN3_SIZE	SRAM_TRACE_SIZE
+
+/* Apollolake HP-SRAM config */
+#define SRAM_ALIAS_OFFSET	0x20000000
+
+#define SRAM_WND_BASE		(HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
+
+#define HP_SRAM_VECBASE_RESET	(HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)
+#define HP_SRAM_VECBASE_OFFSET	0x0
+
+#define SOF_FW_START		(HP_SRAM_VECBASE_RESET + 0x400)
+#define SOF_FW_BASE		(SOF_FW_START)
+
+/* max size for all var-size sections (text/rodata/bss) */
+#define SOF_FW_MAX_SIZE		(0x41000 - 0x400)
+
+#define SOF_TEXT_START		(SOF_FW_START)
+#define SOF_TEXT_BASE		(SOF_FW_START)
+
+/* Stack configuration */
+#define SOF_STACK_SIZE		ARCH_STACK_SIZE
+#define SOF_STACK_TOTAL_SIZE	ARCH_STACK_TOTAL_SIZE
+#define SOF_STACK_BASE		(HP_SRAM_BASE + HP_SRAM_SIZE)
+#define SOF_STACK_END		(SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
+
+#define SOF_MEMORY_SIZE		(SOF_STACK_BASE - HP_SRAM_BASE)
+
+/*
+ * The LP SRAM Heap and Stack on Apollolake are organised like this :-
+ *
+ * +--------------------------------------------------------------------------+
+ * | Offset              | Region         |  Size                             |
+ * +---------------------+----------------+-----------------------------------+
+ * | LP_SRAM_BASE        | RO Data        |  SOF_LP_DATA_SIZE                |
+ * |                     | Data           |                                   |
+ * |                     | BSS            |                                   |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_LP_SYSTEM_BASE | System Heap    |  HEAP_LP_SYSTEM_SIZE              |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_LP_RUNTIME_BASE| Runtime Heap   |  HEAP_LP_RUNTIME_SIZE             |
+ * +---------------------+----------------+-----------------------------------+
+ * | HEAP_LP_BUFFER_BASE | Module Buffers |  HEAP_LP_BUFFER_SIZE              |
+ * +---------------------+----------------+-----------------------------------+
+ * | SOF_LP_STACK_END   | Stack          |  SOF_LP_STACK_SIZE               |
+ * +---------------------+----------------+-----------------------------------+
+ * | SOF_STACK_BASE     |                |                                   |
+ * +---------------------+----------------+-----------------------------------+
+ */
+
+/* LP SRAM */
+#define LP_SRAM_BASE		0xBE800000
+
+/* Heap section sizes for module pool */
+#define HEAP_RT_LP_COUNT8		0
+#define HEAP_RT_LP_COUNT16		256
+#define HEAP_RT_LP_COUNT32		128
+#define HEAP_RT_LP_COUNT64		64
+#define HEAP_RT_LP_COUNT128		64
+#define HEAP_RT_LP_COUNT256		96
+#define HEAP_RT_LP_COUNT512		8
+#define HEAP_RT_LP_COUNT1024		4
+
+/* Heap configuration */
+#define SOF_LP_DATA_SIZE		0x4000
+
+#define HEAP_LP_SYSTEM_BASE		(LP_SRAM_BASE + SOF_LP_DATA_SIZE)
+#define HEAP_LP_SYSTEM_SIZE		0x1000
+
+#define HEAP_LP_RUNTIME_BASE \
+	(HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE)
+#define HEAP_LP_RUNTIME_SIZE \
+	(HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \
+	HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \
+	HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \
+	HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024)
+
+#define HEAP_LP_BUFFER_BASE LP_SRAM_BASE
+#define HEAP_LP_BUFFER_SIZE LP_SRAM_SIZE
+
+#define HEAP_LP_BUFFER_BLOCK_SIZE	0x180
+#define HEAP_LP_BUFFER_COUNT \
+	(HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE)
+
+#define PLATFORM_HEAP_SYSTEM		PLATFORM_CORE_COUNT /* one per core */
+#define PLATFORM_HEAP_SYSTEM_RUNTIME	PLATFORM_CORE_COUNT /* one per core */
+#define PLATFORM_HEAP_RUNTIME		1
+#define PLATFORM_HEAP_BUFFER		3
+
+/* Stack configuration */
+#define SOF_LP_STACK_SIZE		0x1000
+#define SOF_LP_STACK_BASE		(LP_SRAM_BASE + LP_SRAM_SIZE)
+#define SOF_LP_STACK_END		(SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE)
+
+/* Vector and literal sizes - not in core-isa.h */
+#define SOF_MEM_VECT_LIT_SIZE		0x8
+#define SOF_MEM_VECT_TEXT_SIZE		0x38
+#define SOF_MEM_VECT_SIZE		(SOF_MEM_VECT_TEXT_SIZE + \
+					SOF_MEM_VECT_LIT_SIZE)
+
+#define SOF_MEM_ERROR_TEXT_SIZE	0x180
+#define SOF_MEM_ERROR_LIT_SIZE		0x8
+
+#define SOF_MEM_VECBASE	\
+	(HP_SRAM_VECBASE_RESET + HP_SRAM_VECBASE_OFFSET)
+#define SOF_MEM_VECBASE_LIT_SIZE	0x178
+
+#define SOF_MEM_RO_SIZE		0x8
+
+/* VM ROM sizes */
+#define ROM_RESET_TEXT_SIZE	0x400
+#define ROM_RESET_LIT_SIZE	0x200
+
+/* boot loader in IMR */
+#define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB000A000
+
+#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x86
+#define IMR_BOOT_LDR_LIT_BASE		(IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
+					IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
+#define IMR_BOOT_LDR_LIT_SIZE		0x70
+#define IMR_BOOT_LDR_TEXT_BASE		(IMR_BOOT_LDR_LIT_BASE + \
+					IMR_BOOT_LDR_LIT_SIZE)
+#define IMR_BOOT_LDR_TEXT_SIZE		0x1C00
+#define IMR_BOOT_LDR_TEXT1_BASE		(IMR_BOOT_LDR_TEXT_BASE + \
+					IMR_BOOT_LDR_TEXT_SIZE)
+#define IMR_BOOT_LDR_TEXT1_SIZE		0x2000
+#define IMR_BOOT_LDR_DATA_BASE		0xB0002000
+#define IMR_BOOT_LDR_DATA_SIZE		0x1000
+#define IMR_BOOT_LDR_BSS_BASE		0xB0100000
+#define IMR_BOOT_LDR_BSS_SIZE		0x10000
+
+/** \brief Manifest base address in IMR - used by boot loader copy procedure. */
+#define IMR_BOOT_LDR_MANIFEST_BASE	0xB0004000
+
+/** \brief Manifest size (seems unused). */
+#define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
+
+#define uncache_to_cache(address) \
+	((__typeof__((address)))((uint32_t)((address)) + SRAM_ALIAS_OFFSET))
+#define cache_to_uncache(address) \
+	((__typeof__((address)))((uint32_t)((address)) - SRAM_ALIAS_OFFSET))
+#define is_uncached(address) \
+	(((uint32_t)(address) & HP_SRAM_MASK) != HP_SRAM_BASE)
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/platform.h b/soc/xtensa/intel_apl_adsp/include/platform/platform.h
new file mode 100644
index 00000000000000..6101ddc29e522c
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/platform.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ *         Xiuli Pan <xiuli.pan@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_PLATFORM_H__
+#define __PLATFORM_PLATFORM_H__
+
+#include <cavs/memory.h>
+
+#define PLATFORM_RESET_MHE_AT_BOOT		1
+
+#define PLATFORM_DISABLE_L2CACHE_AT_BOOT	1
+
+#define PLATFORM_MASTER_CORE_ID			0
+
+#define MAX_CORE_COUNT				2
+
+#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
+#error "Invalid core count - exceeding core limit"
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(LINKER)
+
+#include <sof/platform.h>
+#include <platform/clk.h>
+#include <platform/shim.h>
+#include <platform/interrupt.h>
+
+struct sof;
+
+/*! \def PLATFORM_DEFAULT_CLOCK
+ *  \brief clock source for audio pipeline
+ *
+ *  There are two types of clock: cpu clock which is a internal clock in
+ *  xtensa core, and ssp clock which is provided by external HW IP.
+ *  The choice depends on HW features on different platform
+ */
+#define PLATFORM_DEFAULT_CLOCK CLK_SSP
+
+/* DGMBS align value */
+#define PLATFORM_HDA_BUFFER_ALIGNMENT	0x20
+
+/* Host page size */
+#define HOST_PAGE_SIZE		4096
+#define PLATFORM_PAGE_TABLE_SIZE	256
+
+/* IDC Interrupt */
+#define PLATFORM_IDC_INTERRUPT(x)	IRQ_EXT_IDC_LVL2(x)
+
+/* IPC Interrupt */
+#define PLATFORM_IPC_INTERRUPT	IRQ_EXT_IPC_LVL2(0)
+
+/* pipeline IRQ */
+#define PLATFORM_SCHEDULE_IRQ	IRQ_NUM_SOFTWARE4
+
+#define PLATFORM_IRQ_TASK_HIGH	IRQ_NUM_SOFTWARE3
+#define PLATFORM_IRQ_TASK_MED	IRQ_NUM_SOFTWARE2
+#define PLATFORM_IRQ_TASK_LOW	IRQ_NUM_SOFTWARE1
+
+#define PLATFORM_SCHEDULE_COST	200
+
+/* maximum preload pipeline depth */
+#define MAX_PRELOAD_SIZE	20
+
+/* DMA treats PHY addresses as host address unless within DSP region */
+#define PLATFORM_HOST_DMA_MASK	0x00000000
+
+/* Platform stream capabilities */
+#define PLATFORM_MAX_CHANNELS	8
+#define PLATFORM_MAX_STREAMS	16
+
+/* clock source used by scheduler for deadline calculations */
+#define PLATFORM_SCHED_CLOCK	PLATFORM_DEFAULT_CLOCK
+
+/* DMA channel drain timeout in microseconds
+ * TODO: calculate based on topology
+ */
+#define PLATFORM_DMA_TIMEOUT	1333
+
+/* DMA host transfer timeouts in microseconds */
+#define PLATFORM_HOST_DMA_TIMEOUT	200
+
+/* DMA link transfer timeouts in microseconds
+ * TODO: timeout should be reduced
+ * (DMA might needs some further changes to do that)
+ */
+#define PLATFORM_LINK_DMA_TIMEOUT	1000
+
+/* WorkQ window size in microseconds */
+#define PLATFORM_WORKQ_WINDOW	2000
+
+/* platform WorkQ clock */
+#define PLATFORM_WORKQ_CLOCK	PLATFORM_DEFAULT_CLOCK
+
+/* work queue default timeout in microseconds */
+#define PLATFORM_WORKQ_DEFAULT_TIMEOUT	1000
+
+/* Host finish work schedule delay in microseconds */
+#define PLATFORM_HOST_FINISH_DELAY	100
+
+/* Host finish work(drain from host to dai) timeout in microseconds */
+#define PLATFORM_HOST_FINISH_TIMEOUT	50000
+
+/* local buffer size of DMA tracing */
+#define DMA_TRACE_LOCAL_SIZE	(HOST_PAGE_SIZE * 2)
+
+/* trace bytes flushed during panic */
+#define DMA_FLUSH_TRACE_SIZE    (MAILBOX_TRACE_SIZE >> 2)
+
+/* the interval of DMA trace copying */
+#define DMA_TRACE_PERIOD		500000
+
+/*
+ * the interval of reschedule DMA trace copying in special case like half
+ * fullness of local DMA trace buffer
+ */
+#define DMA_TRACE_RESCHEDULE_TIME	500
+
+/* DSP should be idle in this time frame */
+#define PLATFORM_IDLE_TIME	750000
+
+/* platform has DMA memory type */
+#define PLATFORM_MEM_HAS_DMA
+
+/* platform has low power memory type */
+#define PLATFORM_MEM_HAS_LP_RAM
+
+/* DSP default delay in cycles */
+#define PLATFORM_DEFAULT_DELAY	12
+
+/* minimal L1 exit time in cycles */
+#define PLATFORM_FORCE_L1_EXIT_TIME	585
+
+/* the SSP port fifo depth */
+#define SSP_FIFO_DEPTH		16
+
+/* the watermark for the SSP fifo depth setting */
+#define SSP_FIFO_WATERMARK	8
+
+/* minimal SSP port delay in cycles */
+#define PLATFORM_SSP_DELAY	2400
+
+/* timer driven scheduling start offset in microseconds */
+#define PLATFORM_TIMER_START_OFFSET	100
+
+/* Platform defined panic code */
+static inline void platform_panic(uint32_t p)
+{
+	mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p & 0x3fffffff);
+	ipc_write(IPC_DIPCIE, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000);
+	ipc_write(IPC_DIPCI, 0x80000000 | (p & 0x3fffffff));
+}
+
+/* Platform defined trace code */
+#define platform_trace_point(__x) \
+	mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x))
+
+extern struct timer *platform_timer;
+
+extern intptr_t _module_init_start;
+extern intptr_t _module_init_end;
+
+/*
+ * APIs declared here are defined for every platform and IPC mechanism.
+ */
+
+int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate,
+	uint32_t bclk_fs);
+
+void platform_ssp_disable_mn(uint32_t ssp_port);
+
+#endif
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/pm_runtime.h b/soc/xtensa/intel_apl_adsp/include/platform/pm_runtime.h
new file mode 100644
index 00000000000000..e7ffe5c521d10b
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/pm_runtime.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
+ */
+
+/**
+ * \file platform/apollolake/include/platform/pm_runtime.h
+ * \brief Runtime power management header file for Apollolake
+ * \author Tomasz Lauda <tomasz.lauda@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_PM_RUNTIME__
+#define __INCLUDE_PLATFORM_PM_RUNTIME__
+
+#include <sof/pm_runtime.h>
+
+/** \brief Platform specific runtime power management data. */
+struct platform_pm_runtime_data {
+	/* TBD */
+};
+
+/**
+ * \brief Initializes platform specific runtime power management.
+ *
+ * \param[in,out] prd Runtime power management data.
+ */
+void platform_pm_runtime_init(struct pm_runtime_data *prd);
+
+/**
+ * \brief Retrieves platform specific power management resource.
+ *
+ * \param[in] context Type of power management context.
+ * \param[in] index Index of the device.
+ * \param[in] flags Flags, set of RPM_...
+ */
+void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index,
+			     uint32_t flags);
+
+/**
+ * \brief Releases platform specific power management resource.
+ *
+ * \param[in] context Type of power management context.
+ * \param[in] index Index of the device.
+ * \param[in] flags Flags, set of RPM_...
+ */
+void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index,
+			     uint32_t flags);
+
+
+/**
+ * \brief Power gates platform specific hardware resources.
+ * \param[in] context Type of power management context.
+ */
+void platform_pm_runtime_power_off(void);
+
+#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/power_down.h b/soc/xtensa/intel_apl_adsp/include/platform/power_down.h
new file mode 100644
index 00000000000000..68382fbe8613cb
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/power_down.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2018 Intel Corporation. All rights reserved.
+ *
+ * Author: Lech Betlej <lech.betlej@linux.intel.com>
+ */
+
+#ifndef __INCLUDE_PLATFORM_POWER_DOWN__
+#define __INCLUDE_PLATFORM_POWER_DOWN__
+
+#include <cavs/power_down.h>
+
+#endif /* __INCLUDE_PLATFORM_POWER_DOWN__ */
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/shim.h b/soc/xtensa/intel_apl_adsp/include/platform/shim.h
new file mode 100644
index 00000000000000..d2d57042173820
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/shim.h
@@ -0,0 +1,329 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_SHIM_H__
+#define __PLATFORM_SHIM_H__
+
+#include <platform/memory.h>
+
+#ifndef ASSEMBLY
+#include <stdint.h>
+#endif
+
+#ifndef BIT
+#define BIT(b)			(1 << (b))
+#endif
+
+/* DSP IPC for Host Registers */
+#define IPC_DIPCT		0x00
+#define IPC_DIPCTE		0x04
+#define IPC_DIPCI		0x08
+#define IPC_DIPCIE		0x0c
+#define IPC_DIPCCTL		0x10
+
+/* DIPCT */
+#define IPC_DIPCT_BUSY		(1 << 31)
+#define IPC_DIPCT_MSG_MASK	0x7FFFFFFF
+
+/* DIPCTE */
+#define IPC_DIPCTE_MSG_MASK	0x3FFFFFFF
+
+/* DIPCI */
+#define IPC_DIPCI_BUSY		(1 << 31)
+#define IPC_DIPCI_MSG_MASK	0x7FFFFFFF
+
+/* DIPCIE */
+#define IPC_DIPCIE_DONE		(1 << 30)
+#define IPC_DIPCIE_MSG_MASK	0x3FFFFFFF
+
+/* DIPCCTL */
+#define IPC_DIPCCTL_IPCIDIE	(1 << 1)
+#define IPC_DIPCCTL_IPCTBIE	(1 << 0)
+
+#define IPC_DSP_OFFSET		0x10
+
+/* DSP IPC for intra DSP communication */
+#define IPC_IDCTFC(x)		(0x0 + x * IPC_DSP_OFFSET)
+#define IPC_IDCTEFC(x)		(0x4 + x * IPC_DSP_OFFSET)
+#define IPC_IDCITC(x)		(0x8 + x * IPC_DSP_OFFSET)
+#define IPC_IDCIETC(x)		(0xc + x * IPC_DSP_OFFSET)
+#define IPC_IDCCTL		0x50
+
+/* IDCTFC */
+#define IPC_IDCTFC_BUSY		(1 << 31)
+#define IPC_IDCTFC_MSG_MASK	0x7FFFFFFF
+
+/* IDCTEFC */
+#define IPC_IDCTEFC_MSG_MASK	0x3FFFFFFF
+
+/* IDCITC */
+#define IPC_IDCITC_BUSY		(1 << 31)
+#define IPC_IDCITC_MSG_MASK	0x7FFFFFFF
+
+/* IDCIETC */
+#define IPC_IDCIETC_DONE	(1 << 30)
+#define IPC_IDCIETC_MSG_MASK	0x3FFFFFFF
+
+/* IDCCTL */
+#define IPC_IDCCTL_IDCIDIE(x)	(0x100 << (x))
+#define IPC_IDCCTL_IDCTBIE(x)	(0x1 << (x))
+
+#define IRQ_CPU_OFFSET	0x40
+
+#define REG_IRQ_IL2MSD(xcpu)	(0x0 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MCD(xcpu)	(0x4 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2MD(xcpu)	(0x8 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL2SD(xcpu)	(0xc + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL2MD_ALL	0x03F181F0
+
+#define REG_IRQ_IL3MSD(xcpu)	(0x10 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MCD(xcpu)	(0x14 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3MD(xcpu)	(0x18 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL3SD(xcpu)	(0x1c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL3MD_ALL	0x807F81FF
+
+#define REG_IRQ_IL4MSD(xcpu)	(0x20 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MCD(xcpu)	(0x24 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4MD(xcpu)	(0x28 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL4SD(xcpu)	(0x2c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL4MD_ALL	0x807F81FF
+
+#define REG_IRQ_IL5MSD(xcpu)	(0x30 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MCD(xcpu)	(0x34 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5MD(xcpu)	(0x38 + (xcpu * IRQ_CPU_OFFSET))
+#define REG_IRQ_IL5SD(xcpu)	(0x3c + (xcpu * IRQ_CPU_OFFSET))
+
+/* all mask valid bits */
+#define REG_IRQ_IL5MD_ALL	0xFFFFC0CF
+
+#define REG_IRQ_IL2RSD		0x100
+#define REG_IRQ_IL3RSD		0x104
+#define REG_IRQ_IL4RSD		0x108
+#define REG_IRQ_IL5RSD		0x10c
+
+#define REG_IRQ_LVL5_LP_GPDMA0_MASK		(0xff << 16)
+#define REG_IRQ_LVL5_LP_GPDMA1_MASK		(0xff << 24)
+
+/* DSP Shim Registers */
+#define SHIM_DSPWC		0x20 /* DSP Wall Clock */
+#define SHIM_DSPWCTCS		0x28 /* DSP Wall Clock Timer Control & Status */
+#define SHIM_DSPWCT0C		0x30 /* DSP Wall Clock Timer 0 Compare */
+#define SHIM_DSPWCT1C		0x38 /* DSP Wall Clock Timer 1 Compare */
+
+#define SHIM_DSPWCTCS_T1T	(0x1 << 5) /* Timer 1 triggered */
+#define SHIM_DSPWCTCS_T0T	(0x1 << 4) /* Timer 0 triggered */
+#define SHIM_DSPWCTCS_T1A	(0x1 << 1) /* Timer 1 armed */
+#define SHIM_DSPWCTCS_T0A	(0x1 << 0) /* Timer 0 armed */
+
+/** \brief Clock control */
+#define SHIM_CLKCTL		0x78
+
+/** \brief Clock status */
+#define SHIM_CLKSTS		0x7C
+
+/** \brief Request Audio PLL Clock */
+#define SHIM_CLKCTL_RAPLLC	BIT(31)
+
+/** \brief Request XTAL Oscillator Clock */
+#define SHIM_CLKCTL_RXOSCC	BIT(30)
+
+/** \brief Request Fast RING Oscillator Clock */
+#define SHIM_CLKCTL_RFROSCC	BIT(29)
+
+/** \brief LP GPDMA Force Dynamic Clock Gating bits, 0: enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB(x)	BIT(26 + x)
+
+/** \brief DMIC Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_DMICFDCGB           BIT(24)
+
+/** \brief I2S Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
+
+/** \brief I2S Extension Force Dynamic Clock Gating */
+#define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
+
+/** \brief Tensilica Core Prevent Local Clock Gating */
+#define SHIM_CLKCTL_TCPLCG_EN(x)	BIT(16 + x)
+#define SHIM_CLKCTL_TCPLCG_DIS(x)	0
+
+/** \brief Core clock PLL divisor */
+#define SHIM_CLKCTL_DPCS_MASK(x)	(0x3 << (8 + x * 2))
+#define SHIM_CLKCTL_DPCS_DIV1(x)	(0x0 << (8 + x * 2))
+#define SHIM_CLKCTL_DPCS_DIV2(x)	(0x1 << (8 + x * 2))
+#define SHIM_CLKCTL_DPCS_DIV4(x)	(0x3 << (8 + x * 2))
+
+/** \brief Tensilica Core Prevent Audio PLL Shutdown */
+#define SHIM_CLKCTL_TCPAPLLS_EN		BIT(7)
+#define SHIM_CLKCTL_TCPAPLLS_DIS	0
+
+/** \brief LP domain clock select, 0: PLL, 1: oscillator */
+#define SHIM_CLKCTL_LDCS_XTAL	BIT(5)
+#define SHIM_CLKCTL_LDCS_PLL	0
+
+/** \brief HP domain clock select */
+#define SHIM_CLKCTL_HDCS	BIT(4)
+#define SHIM_CLKCTL_HDCS_XTAL	BIT(4)
+#define SHIM_CLKCTL_HDCS_PLL	0
+
+/** \brief LP domain oscillator clock select select, 0: XTAL, 1: Fast RING */
+#define SHIM_CLKCTL_LDOCS	BIT(3)
+
+/** \brief HP domain oscillator clock select select, 0: XTAL, 1: Fast RING */
+#define SHIM_CLKCTL_HDOCS	BIT(2)
+
+/** \brief LP memory clock PLL divisor, 0: div by 2, 1: div by 4 */
+#define SHIM_CLKCTL_LPMPCS_DIV4	BIT(1)
+#define SHIM_CLKCTL_LPMPCS_DIV2	0
+
+/** \brief HP memory clock PLL divisor, 0: div by 2, 1: div by 4 */
+#define SHIM_CLKCTL_HPMPCS_DIV4	BIT(0)
+#define SHIM_CLKCTL_HPMPCS_DIV2	0
+
+#define SHIM_PWRCTL		0x90
+#define SHIM_PWRSTS		0x92
+#define SHIM_LPSCTL		0x94
+
+/* HP & LP SRAM Power Gating */
+#define SHIM_HSPGCTL		0x80
+#define SHIM_LSPGCTL		0x84
+#define SHIM_SPSREQ		0xa0
+#define LSPGCTL			SHIM_LSPGCTL
+
+#define SHIM_SPSREQ_RVNNP	(0x1 << 0)
+
+/** \brief LDO Control */
+#define SHIM_LDOCTL		0xA4
+#define SHIM_LDOCTL_HPSRAM_MASK	(3 << 0)
+#define SHIM_LDOCTL_LPSRAM_MASK	(3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_ON	(3 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_ON	(3 << 2)
+#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS	BIT(0)
+#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS	BIT(2)
+#define SHIM_LDOCTL_HPSRAM_LDO_OFF	(0 << 0)
+#define SHIM_LDOCTL_LPSRAM_LDO_OFF	(0 << 2)
+
+#define SHIM_HSPGISTS		0xb0
+#define SHIM_LSPGISTS		0xb4
+#define LSPGISTS		(SHIM_BASE + SHIM_LSPGISTS)
+
+
+#define SHIM_LPSCTL_FDSPRUN	(0X1 << 9)
+#define SHIM_LPSCTL_FDMARUN	(0X1 << 8)
+
+#define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
+
+#define SHIM_LPGPDMAC(x)	(0x1110 + (2 * x))
+#define SHIM_LPGPDMAC_CTLOSEL	(1 << 15)
+#define SHIM_LPGPDMAC_CHOSEL	(0xFF)
+
+#define SHIM_DSPIOPO		0x1118
+#define SHIM_DSPIOPO_DMICOSEL	(1 << 0)
+#define SHIM_DSPIOPO_I2SOSEL	(0x3F << 8)
+
+#define SHIM_GENO		0x111C
+#define SHIM_GENO_SHIMOSEL	(1 << 0)
+#define SHIM_GENO_MDIVOSEL	(1 << 1)
+#define SHIM_GENO_DIOPTOSEL	(1 << 2)
+
+#define SHIM_L2_CACHE_CTRL	(SHIM_BASE + 0x500)
+#define SHIM_L2_PREF_CFG	(SHIM_BASE + 0x508)
+#define SHIM_L2_CACHE_PREF	(SHIM_BASE + 0x510)
+
+#define SHIM_SVCFG			0xF4
+#define SHIM_SVCFG_FORCE_L1_EXIT	(0x1 << 1)
+
+
+/* host windows */
+#define DMWBA(x)		(HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x)		(HOST_WIN_BASE(x) + 0x4)
+
+#define DMWBA_ENABLE		(1 << 0)
+#define DMWBA_READONLY		(1 << 1)
+
+#ifndef ASSEMBLY
+
+static inline uint32_t shim_read(uint32_t reg)
+{
+	return *((volatile uint32_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write(uint32_t reg, uint32_t val)
+{
+	*((volatile uint32_t*)(SHIM_BASE + reg)) = val;
+}
+
+static inline uint64_t shim_read64(uint32_t reg)
+{
+	return *((volatile uint64_t*)(SHIM_BASE + reg));
+}
+
+static inline void shim_write64(uint32_t reg, uint64_t val)
+{
+	*((volatile uint64_t*)(SHIM_BASE + reg)) = val;
+}
+
+static inline uint32_t sw_reg_read(uint32_t reg)
+{
+	return *((volatile uint32_t*)((SRAM_SW_REG_BASE -
+		SRAM_ALIAS_OFFSET) + reg));
+}
+
+static inline void sw_reg_write(uint32_t reg, uint32_t val)
+{
+	*((volatile uint32_t*)((SRAM_SW_REG_BASE -
+		SRAM_ALIAS_OFFSET) + reg)) = val;
+}
+
+static inline uint32_t mn_reg_read(uint32_t reg)
+{
+	return *((volatile uint32_t*)(MN_BASE + reg));
+}
+
+static inline void mn_reg_write(uint32_t reg, uint32_t val)
+{
+	*((volatile uint32_t*)(MN_BASE + reg)) = val;
+}
+
+static inline uint32_t irq_read(uint32_t reg)
+{
+	return *((volatile uint32_t*)(IRQ_BASE + reg));
+}
+
+static inline void irq_write(uint32_t reg, uint32_t val)
+{
+	*((volatile uint32_t*)(IRQ_BASE + reg)) = val;
+}
+
+static inline uint32_t ipc_read(uint32_t reg)
+{
+	return *((volatile uint32_t*)(IPC_HOST_BASE + reg));
+}
+
+static inline void ipc_write(uint32_t reg, uint32_t val)
+{
+	*((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val;
+}
+
+static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
+{
+	return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
+}
+
+static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
+{
+	*((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
+}
+#endif
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/platform/timer.h b/soc/xtensa/intel_apl_adsp/include/platform/timer.h
new file mode 100644
index 00000000000000..11b7119fc10c89
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/platform/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ *
+ * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *         Keyon Jie <yang.jie@linux.intel.com>
+ */
+
+#ifndef __PLATFORM_TIMER_H__
+#define __PLATFORM_TIMER_H__
+
+#include <stdint.h>
+#include <sof/timer.h>
+#include <platform/interrupt.h>
+
+#define TIMER_COUNT	5
+
+/* timer numbers must use associated IRQ number */
+#define TIMER0		IRQ_NUM_TIMER1
+#define TIMER1		IRQ_NUM_TIMER2
+#define TIMER2		IRQ_NUM_TIMER3
+#define TIMER3		IRQ_EXT_TSTAMP0_LVL2(0)
+#define TIMER4		IRQ_EXT_TSTAMP1_LVL2(0)
+
+#endif
diff --git a/soc/xtensa/intel_apl_adsp/include/sof_config.h b/soc/xtensa/intel_apl_adsp/include/sof_config.h
new file mode 100644
index 00000000000000..0d918424307b95
--- /dev/null
+++ b/soc/xtensa/intel_apl_adsp/include/sof_config.h
@@ -0,0 +1,44 @@
+/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */
+#define CONFIG_HP_MEMORY_BANKS 8
+#define CONFIG_LP_MEMORY_BANKS 2
+#define CONFIG_TASK_HAVE_PRIORITY_MEDIUM 1
+#define CONFIG_TASK_HAVE_PRIORITY_LOW 1
+#define CONFIG_BOOT_LOADER 1
+#define CONFIG_IRQ_MAP 1
+#define CONFIG_DMA_GW 1
+#define CONFIG_MEM_WND 1
+#define CONFIG_HW_LLI 1
+#define CONFIG_DMA_FIFO_PARTITION 1
+#define CONFIG_CORE_COUNT 1
+#define CONFIG_APOLLOLAKE 1
+#define CONFIG_INTEL 1
+#define CONFIG_CAVS 1
+#define CONFIG_CAVS_VERSION_1_5 1
+#define CONFIG_FIRMWARE_SHORT_NAME "apl"
+#define CONFIG_CAVS_DMIC 1
+#define CONFIG_CAVS_DMIC_FIR_FULL 1
+#define CONFIG_CAVS_DMIC_FIR_DECIMATE_BY_2 1
+#define CONFIG_CAVS_DMIC_FIR_DECIMATE_BY_3 1
+#define CONFIG_CAVS_DMIC_FIR_DECIMATE_BY_4 1
+#define CONFIG_CAVS_DMIC_FIR_DECIMATE_BY_5 1
+#define CONFIG_CAVS_DMIC_FIR_DECIMATE_BY_6 1
+#define CONFIG_CAVS_DMIC_FIR_DECIMATE_BY_8 1
+#define CONFIG_CAVS_SSP 1
+#define CONFIG_DW 1
+#define CONFIG_DW_DMA 1
+#define CONFIG_COMP_DAI 1
+#define CONFIG_COMP_VOLUME 1
+#define CONFIG_COMP_SRC 1
+#define CONFIG_COMP_FIR 1
+#define CONFIG_COMP_IIR 1
+#define CONFIG_COMP_TONE 1
+#define CONFIG_COMP_MIXER 1
+#define CONFIG_COMP_MUX 1
+#define CONFIG_COMP_SWITCH 1
+#define CONFIG_COMP_KPB 1
+#define CONFIG_COMP_SEL 1
+#define CONFIG_COMP_TEST_KEYPHRASE 1
+#define CONFIG_TRACE 1
+#define CONFIG_TRACEE 1
+#define CONFIG_DEBUG 1
+#define CONFIG_BUILD_VM_ROM 1
diff --git a/soc/xtensa/intel_apl_adsp/memory.h b/soc/xtensa/intel_apl_adsp/memory.h
index c375ff61cd0d9a..23d87e6de3de66 100644
--- a/soc/xtensa/intel_apl_adsp/memory.h
+++ b/soc/xtensa/intel_apl_adsp/memory.h
@@ -96,4 +96,6 @@
 #define LPRAM_BASE				(DT_LP_SRAM_BASE)
 #define LPRAM_SIZE				(DT_LP_SRAM_SIZE)
 
+#include <platform/memory.h>
+
 #endif /* __INC_MEMORY_H */
diff --git a/soc/xtensa/intel_apl_adsp/soc.c b/soc/xtensa/intel_apl_adsp/soc.c
index d082d848cc9ae2..510455cd272b52 100644
--- a/soc/xtensa/intel_apl_adsp/soc.c
+++ b/soc/xtensa/intel_apl_adsp/soc.c
@@ -257,85 +257,18 @@ static inline void soc_read_bootstraps(void)
 	}
 }
 
-#if 0
 static int soc_init(struct device *dev)
 {
+#if 0
 	soc_read_bootstraps();
 
 	LOG_INF("Reference clock frequency: %u Hz", ref_clk_freq);
 
 	soc_set_resource_ownership();
 	soc_set_power_and_clock();
+#endif
 
 	return 0;
 }
 
 SYS_INIT(soc_init, PRE_KERNEL_1, 99);
-#endif
-
-#define SOF_GLB_TYPE_SHIFT			28
-#define SOF_GLB_TYPE(x)				((x) << SOF_GLB_TYPE_SHIFT)
-#define SOF_IPC_FW_READY			SOF_GLB_TYPE(0x7U)
-
-struct sof_ipc_hdr {
-	uint32_t size;			/**< size of structure */
-} __attribute__((packed));
-
-struct sof_ipc_cmd_hdr {
-	uint32_t size;			/**< size of structure */
-	uint32_t cmd;			/**< SOF_IPC_GLB_ + cmd */
-} __attribute__((packed));
-
-/* FW version - SOF_IPC_GLB_VERSION */
-struct sof_ipc_fw_version {
-	struct sof_ipc_hdr hdr;
-	uint16_t major;
-	uint16_t minor;
-	uint16_t micro;
-	uint16_t build;
-	uint8_t date[12];
-	uint8_t time[10];
-	uint8_t tag[6];
-	uint32_t abi_version;
-
-	/* reserved for future use */
-	uint32_t reserved[4];
-} __attribute__((packed));
-
-/* FW ready Message - sent by firmware when boot has completed */
-struct sof_ipc_fw_ready {
-	struct sof_ipc_cmd_hdr hdr;
-	uint32_t dspbox_offset;	 /* dsp initiated IPC mailbox */
-	uint32_t hostbox_offset; /* host initiated IPC mailbox */
-	uint32_t dspbox_size;
-	uint32_t hostbox_size;
-	struct sof_ipc_fw_version version;
-
-	/* Miscellaneous flags */
-	uint64_t flags;
-
-	/* reserved for future use */
-	uint32_t reserved[4];
-} __attribute__((packed));
-
-static const struct sof_ipc_fw_ready fw_ready_apl
-	__attribute__((section(".fw_ready"))) __attribute__((used)) = {
-	.hdr = {
-		.cmd = SOF_IPC_FW_READY,
-		.size = sizeof(struct sof_ipc_fw_ready),
-	},
-	.version = {
-		.hdr.size = sizeof(struct sof_ipc_fw_version),
-		.micro = 3,
-		.minor = 2,
-		.major = 1,
-#ifdef CONFIG_DEBUG
-		/* only added in debug for reproducability in releases */
-		.date = __DATE__,
-		.time = __TIME__,
-#endif
-		.tag = "1234",
-		.abi_version = 0x1234,
-	},
-	.flags = 0,
-};
diff --git a/soc/xtensa/intel_apl_adsp/soc.h b/soc/xtensa/intel_apl_adsp/soc.h
index f6da8fb99b3bb2..dfb6a7dae7abbf 100644
--- a/soc/xtensa/intel_apl_adsp/soc.h
+++ b/soc/xtensa/intel_apl_adsp/soc.h
@@ -3,6 +3,13 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <string.h>
+#include <errno.h>
+
+#include <sys/sys_io.h>
+
+#include "memory.h"
+
 #ifndef __INC_SOC_H
 #define __INC_SOC_H
 
@@ -96,8 +103,6 @@
 #define I2S2_CAVS_IRQ				I2S_CAVS_IRQ(2)
 #define I2S3_CAVS_IRQ				I2S_CAVS_IRQ(3)
 
-#define SSP_SIZE				0x0000200
-#define SSP_BASE(x)				(0x00008000 + (x) * SSP_SIZE)
 #define SSP_MN_DIV_SIZE				(8)
 #define SSP_MN_DIV_BASE(x)			\
 	(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
diff --git a/subsys/audio/sof.c b/subsys/audio/sof.c
index be92f201fd6875..fdadc2e6f0eedf 100644
--- a/subsys/audio/sof.c
+++ b/subsys/audio/sof.c
@@ -13,6 +13,12 @@
 #include <logging/log.h>
 LOG_MODULE_REGISTER(sof, CONFIG_SOF_LOG_LEVEL);
 
+#include <platform/shim.h>
+#include <sof/mailbox.h>
+#include <sof/notifier.h>
+#include <sof/timer.h>
+#include <ipc/info.h>
+
 #include "sof/sof.h"
 #include "sof/ipc.h"
 
@@ -24,10 +30,150 @@ LOG_MODULE_REGISTER(sof, CONFIG_SOF_LOG_LEVEL);
 #define SRAM_REG_FW_IPC_PROCESSED_COUNT         0x10
 #define SRAM_REG_FW_END                         0x14
 
+/* Clock control */
+#define SHIM_CLKCTL				0x78
+
+/* Power control and status */
+#define SHIM_PWRCTL				0x90
+#define SHIM_PWRSTS				0x92
+#define SHIM_LPSCTL				0x94
+
+#define SHIM_CLKCTL_HDCS_PLL			0
+#define SHIM_CLKCTL_LDCS_PLL			0
+#define SHIM_CLKCTL_DPCS_DIV1(x)		(0x0 << (8 + x * 2))
+#define SHIM_CLKCTL_HPMPCS_DIV2			0
+#define SHIM_CLKCTL_LPMPCS_DIV4			BIT(1)
+#define SHIM_CLKCTL_TCPAPLLS_DIS		0
+#define SHIM_CLKCTL_TCPLCG_DIS(x)		0
+
+/* host windows */
+#define DMWBA(x)			(HOST_WIN_BASE(x) + 0x0)
+#define DMWLO(x)			(HOST_WIN_BASE(x) + 0x4)
+#define DMWBA_ENABLE			(1 << 0)
+#define DMWBA_READONLY			(1 << 1)
+
+#define SOF_GLB_TYPE_SHIFT			28
+#define SOF_GLB_TYPE(x)				((x) << SOF_GLB_TYPE_SHIFT)
+#define SOF_IPC_FW_READY			SOF_GLB_TYPE(0x7U)
+
 static struct sof sof;
 
 #define CASE(x) case TRACE_CLASS_##x: return #x
 
+struct timesource_data platform_generic_queue[] = {
+{
+	.timer = {
+		.id = TIMER3, /* external timer */
+		.irq = IRQ_EXT_TSTAMP0_LVL2(0),
+	},
+	.clk		= CLK_SSP,
+	.notifier	= NOTIFIER_ID_SSP_FREQ,
+	.timer_set	= platform_timer_set,
+	.timer_clear	= platform_timer_clear,
+	.timer_get	= platform_timer_get,
+},
+{
+	.timer = {
+		.id = TIMER3, /* external timer */
+		.irq = IRQ_EXT_TSTAMP0_LVL2(1),
+	},
+	.clk		= CLK_SSP,
+	.notifier	= NOTIFIER_ID_SSP_FREQ,
+	.timer_set	= platform_timer_set,
+	.timer_clear	= platform_timer_clear,
+	.timer_get	= platform_timer_get,
+},
+};
+
+struct timer *platform_timer =
+	&platform_generic_queue[PLATFORM_MASTER_CORE_ID].timer;
+
+static const struct sof_ipc_fw_ready fw_ready_apl
+	__attribute__((section(".fw_ready"))) __attribute__((used)) = {
+	.hdr = {
+		.cmd = SOF_IPC_FW_READY,
+		.size = sizeof(struct sof_ipc_fw_ready),
+	},
+	.version = {
+		.hdr.size = sizeof(struct sof_ipc_fw_version),
+		.micro = 0,
+		.minor = 1,
+		.major = 1,
+#ifdef CONFIG_DEBUG
+		/* only added in debug for reproducability in releases */
+		.build = 8,
+		.date = __DATE__,
+		.time = __TIME__,
+#endif
+		.tag = "9e2aa",
+		.abi_version = (3 << 24) | (9 << 12) | (0 << 0),
+	},
+	.flags = 0,
+};
+
+#define NUM_WINDOWS		7
+
+static const struct sof_ipc_window sram_window = {
+	.ext_hdr = {
+		.hdr.cmd = SOF_IPC_FW_READY,
+		.hdr.size = sizeof(struct sof_ipc_window) +
+			    sizeof(struct sof_ipc_window_elem) * NUM_WINDOWS,
+		.type = SOF_IPC_EXT_WINDOW,
+	},
+	.num_windows = NUM_WINDOWS,
+	.window = {
+		{
+			.type   = SOF_IPC_REGION_REGS,
+			.id     = 0,    /* map to host window 0 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_SW_REG_SIZE,
+			.offset = 0,
+		},
+		{
+			.type   = SOF_IPC_REGION_UPBOX,
+			.id     = 0,    /* map to host window 0 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_DSPBOX_SIZE,
+			.offset = MAILBOX_SW_REG_SIZE,
+		},
+		{
+			.type   = SOF_IPC_REGION_DOWNBOX,
+			.id     = 1,    /* map to host window 1 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_HOSTBOX_SIZE,
+			.offset = 0,
+		},
+		{
+			.type   = SOF_IPC_REGION_DEBUG,
+			.id     = 2,    /* map to host window 2 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_EXCEPTION_SIZE + MAILBOX_DEBUG_SIZE,
+			.offset = 0,
+		},
+		{
+			.type   = SOF_IPC_REGION_EXCEPTION,
+			.id     = 2,    /* map to host window 2 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_EXCEPTION_SIZE,
+			.offset = MAILBOX_EXCEPTION_OFFSET,
+		},
+		{
+			.type   = SOF_IPC_REGION_STREAM,
+			.id     = 2,    /* map to host window 2 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_STREAM_SIZE,
+			.offset = MAILBOX_STREAM_OFFSET,
+		},
+		{
+			.type   = SOF_IPC_REGION_TRACE,
+			.id     = 3,    /* map to host window 3 */
+			.flags  = 0, // TODO: set later
+			.size   = MAILBOX_TRACE_SIZE,
+			.offset = 0,
+		},
+	},
+};
+
 /* look up subsystem class name from table */
 char *get_trace_class(uint32_t trace_class)
 {
@@ -103,6 +249,37 @@ void dma_sg_free(struct dma_sg_elem_array *elem_array)
 {
 }
 
+static void prepare_host_windows()
+{
+	/* window0, for fw status & outbox/uplink mbox */
+	sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0));
+	sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE),
+		    DMWBA(0));
+	memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0,
+	      HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
+	SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
+			 HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
+
+	/* window1, for inbox/downlink mbox */
+	sys_write32((HP_SRAM_WIN1_SIZE | 0x7), DMWLO(1));
+	sys_write32((HP_SRAM_WIN1_BASE | DMWBA_ENABLE), DMWBA(1));
+	memset((void *)HP_SRAM_WIN1_BASE, 0, HP_SRAM_WIN1_SIZE);
+	SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
+
+	/* window2, for debug */
+	sys_write32((HP_SRAM_WIN2_SIZE | 0x7), DMWLO(2));
+	sys_write32((HP_SRAM_WIN2_BASE | DMWBA_ENABLE), DMWBA(2));
+	memset((void *)HP_SRAM_WIN2_BASE, 0, HP_SRAM_WIN2_SIZE);
+	SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
+
+	/* window3, for trace
+	 * zeroed by trace initialization
+	 */
+	sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
+	sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
+		    DMWBA(3));
+}
+
 static void sys_module_init(void)
 {
 	Z_STRUCT_SECTION_FOREACH(_sof_module, mod) {
@@ -111,10 +288,43 @@ static void sys_module_init(void)
 	}
 }
 
+static void hw_init()
+{
+	/* Setup clocks and power management */
+	shim_write(SHIM_CLKCTL,
+		   SHIM_CLKCTL_HDCS_PLL | /* HP domain clocked by PLL */
+		   SHIM_CLKCTL_LDCS_PLL | /* LP domain clocked by PLL */
+		   SHIM_CLKCTL_DPCS_DIV1(0) | /* Core 0 clk not divided */
+		   SHIM_CLKCTL_DPCS_DIV1(1) | /* Core 1 clk not divided */
+		   SHIM_CLKCTL_HPMPCS_DIV2 | /* HP mem clock div by 2 */
+		   SHIM_CLKCTL_LPMPCS_DIV4 | /* LP mem clock div by 4 */
+		   SHIM_CLKCTL_TCPAPLLS_DIS |
+		   SHIM_CLKCTL_TCPLCG_DIS(0) | SHIM_CLKCTL_TCPLCG_DIS(1));
+
+	shim_write(SHIM_LPSCTL, shim_read(SHIM_LPSCTL));
+}
+
+static int sof_boot_complete()
+{
+	mailbox_dspbox_write(0, &fw_ready_apl, sizeof(fw_ready_apl));
+        mailbox_dspbox_write(sizeof(fw_ready_apl), &sram_window,
+			     sram_window.ext_hdr.hdr.size);
+
+	ipc_write(IPC_DIPCIE, 0);
+	ipc_write(IPC_DIPCI, (0x80000000 | SOF_IPC_FW_READY));
+
+	return 0;
+}
+
 static int sof_init(struct device *unused)
 {
 	int ret;
 
+	/* prepare host windows */
+	prepare_host_windows();
+
+	hw_init();
+
 	/* init components */
 	sys_comp_init();
 
@@ -152,6 +362,10 @@ static int sof_init(struct device *unused)
 
 	mailbox_sw_reg_write(SRAM_REG_ROM_STATUS, 0xabbac0fe);
 
+	sof_boot_complete();
+
+	LOG_INF("FW Boot Completed");
+
 	return 0;
 }
 
diff --git a/subsys/logging/Kconfig b/subsys/logging/Kconfig
index f15fc52be2bf2b..128116a0b1e183 100644
--- a/subsys/logging/Kconfig
+++ b/subsys/logging/Kconfig
@@ -425,7 +425,7 @@ endif # LOG_BACKEND_NET
 
 config LOG_BACKEND_ADSP
 	bool "Enable Intel ADSP backend"
-	depends on SOC_INTEL_APL_ADSP
+	depends on SOC_INTEL_APL_ADSP && SOF
 	select RING_BUFFER
 	help
 	  Enable backend in APL ADSP using memory mailbox
diff --git a/subsys/logging/log_backend_adsp.c b/subsys/logging/log_backend_adsp.c
index 89be243c08a134..d4f355de2bbf5c 100644
--- a/subsys/logging/log_backend_adsp.c
+++ b/subsys/logging/log_backend_adsp.c
@@ -14,11 +14,17 @@
 
 #define BUF_SIZE 256
 
-#define MAILBOX_TRACE_BASE	0xbe008000
-#define MAILBOX_TRACE_SIZE	0x2000
-
 static struct ring_buf ringbuf;
 
+static u16_t magic = 0x55aa;
+static u16_t log_id;
+
+/*
+ * Log message format
+ * logging started with magic number 0x55aa followed by lo message id.
+ * Log message ended with null terminator and takes BUF_SIZE slot
+ */
+
 static void init(void)
 {
 	ring_buf_init(&ringbuf, MAILBOX_TRACE_SIZE,
@@ -35,20 +41,30 @@ static inline void dcache_writeback_region(void *addr, size_t size)
 static void trace(const u8_t *data, size_t length)
 {
 	volatile u8_t *t;
+	int space;
 	int i;
 
-	if (ring_buf_put_claim(&ringbuf, &t, BUF_SIZE) < BUF_SIZE) {
+	space = ring_buf_space_get(&ringbuf);
+	if (space < BUF_SIZE) {
 		u8_t *dummy;
 
 		/* Remove oldest entry */
 		ring_buf_get_claim(&ringbuf, &dummy, BUF_SIZE);
 		ring_buf_get_finish(&ringbuf, BUF_SIZE);
-
-		ring_buf_put_claim(&ringbuf, &t, BUF_SIZE);
 	}
 
+	ring_buf_put_claim(&ringbuf, &t, BUF_SIZE);
+
+	/* Add magic number at the beginning of the slot */
+	*(u16_t *)t = magic;
+	t += 2;
+
+	/* Add log id */
+	*(u16_t *)t = log_id++;
+	t += 2;
+
 	for (i = 0; i < length; i++) {
-		t[i] = data[i];
+		*t++ = data[i];
 	}
 
 	dcache_writeback_region(t, i);
@@ -63,7 +79,8 @@ static int char_out(u8_t *data, size_t length, void *ctx)
 	return length;
 }
 
-static u8_t buf[BUF_SIZE];
+/* magic and log id takes space */
+static u8_t buf[BUF_SIZE - 4];
 
 LOG_OUTPUT_DEFINE(log_output, char_out, buf, sizeof(buf));