From eb2564c242bd1fdd58004a87d322b9b835207f8c Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Fri, 2 Mar 2018 14:27:53 -0800 Subject: [PATCH] synthesis: update constraints to be more careful about identifying reset nets --- syn/cons/NV_NVDLA_partition_a.sdc | 3 +-- syn/cons/NV_NVDLA_partition_c.sdc | 3 +-- syn/cons/NV_NVDLA_partition_m.sdc | 3 +-- syn/cons/NV_NVDLA_partition_o.sdc | 5 +++-- syn/cons/NV_NVDLA_partition_p.sdc | 3 +-- 5 files changed, 7 insertions(+), 10 deletions(-) diff --git a/syn/cons/NV_NVDLA_partition_a.sdc b/syn/cons/NV_NVDLA_partition_a.sdc index 9ca995a9..e0a294d1 100644 --- a/syn/cons/NV_NVDLA_partition_a.sdc +++ b/syn/cons/NV_NVDLA_partition_a.sdc @@ -10,8 +10,8 @@ set_max_area 0 set_ideal_network [get_ports direct_reset_] set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] set_ideal_network [get_ports test_mode] -set_ideal_network [get_pins u_partition_a_reset/synced_rstn] # [get_ports nvdla_core_rstn] create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45} set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk] set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk] @@ -19,7 +19,6 @@ set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk] set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk] set_false_path -from [get_ports direct_reset_] set_false_path -from [get_ports dla_reset_rstn] -set_false_path -from [get_pins u_partition_a_reset/synced_rstn] # [get_ports nvdla_core_rstn] set_false_path -from [get_ports test_mode] set_false_path -from [get_ports pwrbus_ram_pd*] set_false_path -from [get_ports tmc2slcg_disable_clock_gating] diff --git a/syn/cons/NV_NVDLA_partition_c.sdc b/syn/cons/NV_NVDLA_partition_c.sdc index 38884c6c..edc1145a 100644 --- a/syn/cons/NV_NVDLA_partition_c.sdc +++ b/syn/cons/NV_NVDLA_partition_c.sdc @@ -10,8 +10,8 @@ set_max_area 0 set_ideal_network [get_ports direct_reset_] set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] set_ideal_network [get_ports test_mode] -set_ideal_network [get_pins u_partition_c_reset/synced_rstn] # [get_ports nvdla_core_rstn] create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45} set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk] set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk] @@ -19,7 +19,6 @@ set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk] set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk] set_false_path -from [get_ports direct_reset_] set_false_path -from [get_ports dla_reset_rstn] -set_false_path -from [get_pins u_partition_c_reset/synced_rstn] # [get_ports nvdla_core_rstn] set_false_path -from [get_ports test_mode] set_false_path -from [get_ports pwrbus_ram_pd*] set_false_path -from [get_ports tmc2slcg_disable_clock_gating] diff --git a/syn/cons/NV_NVDLA_partition_m.sdc b/syn/cons/NV_NVDLA_partition_m.sdc index 422fdc0a..f35ae0b3 100644 --- a/syn/cons/NV_NVDLA_partition_m.sdc +++ b/syn/cons/NV_NVDLA_partition_m.sdc @@ -10,8 +10,8 @@ set_max_area 0 set_ideal_network [get_ports direct_reset_] set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] set_ideal_network [get_ports test_mode] -set_ideal_network [get_pins u_partition_m_reset/synced_rstn] # [get_ports nvdla_core_rstn] create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45} set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk] set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk] @@ -19,7 +19,6 @@ set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk] set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk] set_false_path -from [get_ports direct_reset_] set_false_path -from [get_ports dla_reset_rstn] -set_false_path -from [get_pins u_partition_m_reset/synced_rstn] # [get_ports nvdla_core_rstn] set_false_path -from [get_ports test_mode] set_false_path -from [get_ports tmc2slcg_disable_clock_gating] set_false_path -from [get_ports global_clk_ovr_on] diff --git a/syn/cons/NV_NVDLA_partition_o.sdc b/syn/cons/NV_NVDLA_partition_o.sdc index 2273453c..35dff9ab 100644 --- a/syn/cons/NV_NVDLA_partition_o.sdc +++ b/syn/cons/NV_NVDLA_partition_o.sdc @@ -11,7 +11,7 @@ set_max_area 0 set_ideal_network [get_ports test_mode] set_ideal_network [get_ports direct_reset_] set_ideal_network [get_ports dla_reset_rstn] -set_ideal_network [get_pins u_partition_o_reset/synced_rstn] # [get_ports nvdla_core_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45} set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk] set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk] @@ -24,8 +24,9 @@ set_clock_transition -min -rise 0.05 [get_clocks nvdla_falcon_clk] set_clock_transition -min -fall 0.05 [get_clocks nvdla_falcon_clk] set_false_path -from [get_ports direct_reset_] set_false_path -from [get_ports dla_reset_rstn] -set_false_path -from [get_pins u_partition_o_reset/synced_rstn] # [get_ports nvdla_core_rstn] set_false_path -from [get_ports test_mode] set_false_path -from [get_ports pwrbus_ram_pd*] set_false_path -from [get_ports tmc2slcg_disable_clock_gating] set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_clocks nvdla_core_clk] -to [get_clocks nvdla_falcon_clk] +set_false_path -from [get_clocks nvdla_falcon_clk] -to [get_clocks nvdla_core_clk] diff --git a/syn/cons/NV_NVDLA_partition_p.sdc b/syn/cons/NV_NVDLA_partition_p.sdc index f094e3fd..7bc05fe4 100644 --- a/syn/cons/NV_NVDLA_partition_p.sdc +++ b/syn/cons/NV_NVDLA_partition_p.sdc @@ -10,7 +10,7 @@ set_max_area 0 set_ideal_network [get_ports direct_reset_] set_ideal_network [get_ports dla_reset_rstn] -set_ideal_network [get_pins u_partition_p_reset/synced_rstn] # [get_ports nvdla_core_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] set_ideal_network [get_ports test_mode] create_clock [get_ports nvdla_core_clk] -period 0.9 -waveform {0 0.45} set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk] @@ -19,7 +19,6 @@ set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk] set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk] set_false_path -from [get_ports direct_reset_] set_false_path -from [get_ports dla_reset_rstn] -set_false_path -from [get_pins u_partition_p_reset/synced_rstn] # [get_ports nvdla_core_rstn] set_false_path -from [get_ports test_mode] set_false_path -from [get_ports pwrbus_ram_pd*] set_false_path -from [get_ports tmc2slcg_disable_clock_gating]