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blitter.cpp
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blitter.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Custom chip emulation
*
* (c) 1995 Bernd Schmidt, Alessandro Bissacco
* (c) 2002 - 2005 Toni Wilen
*/
#define SPEEDUP 1
#define BLITTER_DEBUG 0
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "memory.h"
#include "custom.h"
#include "events.h"
#include "newcpu.h"
#include "blitter.h"
#include "blit.h"
#include "savestate.h"
#include "debug.h"
// 1 = logging
// 2 = no wait detection
// 4 = no D
// 8 = instant
// 16 = activate debugger if weird things
#if BLITTER_DEBUG
int log_blitter = 1 | 16;
#else
int log_blitter = 0;
#endif
/* we must not change ce-mode while blitter is running.. */
static int blitter_cycle_exact, immediate_blits;
static int blt_statefile_type;
uae_u16 bltcon0, bltcon1;
uae_u32 bltapt, bltbpt, bltcpt, bltdpt;
uae_u32 bltptx;
int bltptxpos, bltptxc;
int blitter_nasty;
// blitter is active and D may write to visible bitplane addresses
int blitter_dangerous_bpl;
static int original_ch, original_fill, original_line;
static int blinea_shift;
static uae_u16 blinea, blineb;
static int blitline, blitfc, blitfill, blitife, blitsing, blitdesc;
static int blitline_started;
static int blitonedot, blitsign, blitlinepixel;
static int blit_add;
static int blit_modadda, blit_modaddb, blit_modaddc, blit_modaddd;
static int blit_ch;
static int blitter_dontdo;
static int blitter_delayed_debug;
#ifdef BLITTER_SLOWDOWNDEBUG
static int blitter_slowdowndebug;
#endif
struct bltinfo blt_info;
static uae_u8 blit_filltable[256][4][2];
uae_u32 blit_masktable[BLITTER_MAX_WORDS];
enum blitter_states bltstate;
static int blit_cyclecounter, blit_waitcyclecounter;
static int blit_maxcyclecounter, blit_slowdown, blit_totalcyclecounter;
static int blit_startcycles, blit_misscyclecounter;
#ifdef CPUEMU_13
extern uae_u8 cycle_line[256];
#endif
static long blit_firstline_cycles;
static long blit_first_cycle;
static int blit_last_cycle, blit_dmacount, blit_dmacount2;
static int blit_linecycles, blit_extracycles, blit_nod;
static const int *blit_diag;
static int blit_frozen, blit_faulty;
static int blit_final;
static int blt_delayed_irq;
static uae_u16 ddat1, ddat2;
static int ddat1use, ddat2use;
int blit_interrupt;
static int last_blitter_hpos;
#define BLITTER_STARTUP_CYCLES 2
/*
Blitter Idle Cycle:
Cycles that are free cycles (available for CPU) and
are not used by any other Agnus DMA channel. Blitter
idle cycle is not "used" by blitter, CPU can still use
it normally if it needs the bus.
same in both block and line modes
number of cycles, initial cycle, main cycle
*/
#define DIAGSIZE 10
static const int blit_cycle_diagram[][DIAGSIZE] =
{
{ 2, 0,0, 0,0 }, /* 0 -- */
{ 2, 0,0, 0,4 }, /* 1 -D */
{ 2, 0,3, 0,3 }, /* 2 -C */
{ 3, 0,3,0, 0,3,4 }, /* 3 -CD */
{ 3, 0,2,0, 0,2,0 }, /* 4 -B- */
{ 3, 0,2,0, 0,2,4 }, /* 5 -BD */
{ 3, 0,2,3, 0,2,3 }, /* 6 -BC */
{ 4, 0,2,3,0, 0,2,3,4 }, /* 7 -BCD */
{ 2, 1,0, 1,0 }, /* 8 A- */
{ 2, 1,0, 1,4 }, /* 9 AD */
{ 2, 1,3, 1,3 }, /* A AC */
{ 3, 1,3,0, 1,3,4, }, /* B ACD */
{ 3, 1,2,0, 1,2,0 }, /* C AB- */
{ 3, 1,2,0, 1,2,4 }, /* D ABD */
{ 3, 1,2,3, 1,2,3 }, /* E ABC */
{ 4, 1,2,3,0, 1,2,3,4 } /* F ABCD */
};
/*
following 4 channel combinations in fill mode have extra
idle cycle added (still requires free bus cycle)
*/
static const int blit_cycle_diagram_fill[][DIAGSIZE] =
{
{ 0 }, /* 0 */
{ 3, 0,0,0, 0,4,0 }, /* 1 */
{ 0 }, /* 2 */
{ 0 }, /* 3 */
{ 0 }, /* 4 */
{ 4, 0,2,0,0, 0,2,4,0 }, /* 5 */
{ 0 }, /* 6 */
{ 0 }, /* 7 */
{ 0 }, /* 8 */
{ 3, 1,0,0, 1,4,0 }, /* 9 */
{ 0 }, /* A */
{ 0 }, /* B */
{ 0 }, /* C */
{ 4, 1,2,0,0, 1,2,4,0 }, /* D */
{ 0 }, /* E */
{ 0 }, /* F */
};
/*
-C-D C-D- ... C-D- --
line draw takes 4 cycles (-C-D)
idle cycles do the same as above, 2 dma fetches
(read from C, write to D, but see below)
Oddities:
- first word is written to address pointed by BLTDPT
but all following writes go to address pointed by BLTCPT!
(some kind of internal copy because all bus cyles are
using normal BLTDDAT)
- BLTDMOD is ignored by blitter (BLTCMOD is used)
- state of D-channel enable bit does not matter!
- disabling A-channel freezes the content of BPLAPT
- C-channel disabled: nothing is written
There is one tricky situation, writing to DFF058 just before
last D write cycle (which is normally free) does not disturb
blitter operation, final D is still written correctly before
blitter starts normally (after 2 idle cycles)
There is at least one demo that does this..
*/
// 5 = internal "processing cycle"
static const int blit_cycle_diagram_line[] =
{
4, 0,3,5,4, 0,3,5,4
};
static const int blit_cycle_diagram_finald[] =
{
2, 0,4, 0,4
};
static const int blit_cycle_diagram_finalld[] =
{
2, 0,0, 0,0
};
static int get_cycle_diagram_type (const int *diag)
{
for (int i = 0; i < 16; i++) {
if (diag == &blit_cycle_diagram[i][0])
return i;
if (diag == &blit_cycle_diagram_fill[i][0])
return i + 0x40;
}
if (diag == blit_cycle_diagram_line)
return 0x80;
if (diag == blit_cycle_diagram_finald)
return 0x81;
if (diag == blit_cycle_diagram_finalld)
return 0x82;
return 0xff;
}
static const int *set_cycle_diagram_type (uae_u8 diag)
{
if (diag >= 0x00 && diag <= 0x0f)
return &blit_cycle_diagram[diag][0];
if (diag >= 0x40 && diag <= 0x4f)
return &blit_cycle_diagram_fill[diag][0];
if (diag == 0x80)
return blit_cycle_diagram_line;
if (diag == 0x81)
return blit_cycle_diagram_finald;
if (diag == 0x82)
return blit_cycle_diagram_finalld;
return NULL;
}
void build_blitfilltable (void)
{
unsigned int d, fillmask;
int i;
for (i = 0; i < BLITTER_MAX_WORDS; i++)
blit_masktable[i] = 0xFFFF;
for (d = 0; d < 256; d++) {
for (i = 0; i < 4; i++) {
int fc = i & 1;
uae_u8 data = d;
for (fillmask = 1; fillmask != 0x100; fillmask <<= 1) {
uae_u16 tmp = data;
if (fc) {
if (i & 2)
data |= fillmask;
else
data ^= fillmask;
}
if (tmp & fillmask) fc = !fc;
}
blit_filltable[d][i][0] = data;
blit_filltable[d][i][1] = fc;
}
}
}
STATIC_INLINE void record_dma_blit (uae_u16 reg, uae_u16 dat, uae_u32 addr, int hpos)
{
#ifdef DEBUGGER
int type;
if (blitline)
type = DMARECORD_BLITTER_LINE;
else if (blitfill)
type = DMARECORD_BLITTER_FILL;
else
type = DMARECORD_BLITTER;
if (debug_dma)
record_dma (reg, dat, addr, hpos, vpos, type);
if (memwatch_enabled) {
if (reg == 0)
debug_wputpeekdma_chipram(addr, dat, MW_MASK_BLITTER_D, reg);
else if (reg == 0x70)
debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_C, reg);
else if (reg == 0x72)
debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_B, reg);
else if (reg == 0x74)
debug_wgetpeekdma_chipram(addr, dat, MW_MASK_BLITTER_A, reg);
}
#endif
}
static void blitter_dump (void)
{
int chipsize = currprefs.chipmem_size;
write_log (_T("PT A=%08X B=%08X C=%08X D=%08X\n"), bltapt, bltbpt, bltcpt, bltdpt);
write_log (_T("CON0=%04X CON1=%04X DAT A=%04X B=%04X C=%04X\n"),
bltcon0, bltcon1, blt_info.bltadat, blt_info.bltbdat, blt_info.bltcdat);
write_log (_T("AFWM=%04X ALWM=%04X MOD A=%04X B=%04X C=%04X D=%04X\n"),
blt_info.bltafwm, blt_info.bltalwm,
blt_info.bltamod & 0xffff, blt_info.bltbmod & 0xffff, blt_info.bltcmod & 0xffff, blt_info.bltdmod & 0xffff);
write_log (_T("PC=%08X DMA=%d\n"), m68k_getpc (), dmaen (DMA_BLITTER));
if (((bltcon0 & 0x800) && bltapt >= chipsize) || ((bltcon0 & 0x400) && bltbpt >= chipsize) ||
((bltcon0 & 0x200) && bltcpt >= chipsize) || ((bltcon0 & 0x100) && bltdpt >= chipsize))
write_log (_T("PT outside of chipram\n"));
}
STATIC_INLINE const int *get_ch (void)
{
if (blit_faulty)
return &blit_diag[0];
if (blit_final)
return blitline || blit_nod ? blit_cycle_diagram_finalld : blit_cycle_diagram_finald;
return blit_diag;
}
STATIC_INLINE int channel_state (int cycles)
{
const int *diag;
if (cycles < 0)
return 0;
diag = get_ch ();
if (cycles < diag[0])
return diag[1 + cycles];
cycles -= diag[0];
cycles %= diag[0];
return diag[1 + diag[0] + cycles];
}
STATIC_INLINE int channel_pos (int cycles)
{
const int *diag;
if (cycles < 0)
return 0;
diag = get_ch ();
if (cycles < diag[0])
return cycles;
cycles -= diag[0];
cycles %= diag[0];
return cycles;
}
int blitter_channel_state (void)
{
return channel_state (blit_cyclecounter);
}
extern int is_bitplane_dma (int hpos);
STATIC_INLINE int canblit (int hpos)
{
if (!dmaen (DMA_BLITTER))
return -1;
if (is_bitplane_dma (hpos))
return 0;
if (cycle_line[hpos] & CYCLE_MASK) {
#if 0
if ((dmacon & DMA_BLITPRI) && (cycle_line[hpos] & CYCLE_MASK) == CYCLE_CPU)
write_log (_T("BLITTER: CPU stole cycle from blitter without nasty!?\n"));
#endif
return 0;
}
return 1;
}
static void markidlecycle (int hpos)
{
if (debug_dma)
record_dma_event (DMA_EVENT_BLITSTARTFINISH, hpos, vpos);
}
static void reset_channel_mods (void)
{
if (bltptxpos < 0)
return;
bltptxpos = -1;
switch (bltptxc)
{
case 1:
bltapt = bltptx;
break;
case 2:
bltbpt = bltptx;
break;
case 3:
bltcpt = bltptx;
break;
case 4:
bltdpt = bltptx;
break;
}
}
static void check_channel_mods (int hpos, int ch)
{
if (bltptxpos != hpos)
return;
if (ch == bltptxc) {
bltptxpos = -1;
write_log (_T("BLITTER: %08X write to %cPT ignored! %08x\n"), bltptx, ch + 'A' - 1, m68k_getpc ());
}
}
// blitter interrupt is set (and busy bit cleared) when
// last "main" cycle has been finished, any non-linedraw
// D-channel blit still needs 2 more cycles before final
// D is written (idle cycle, final D write)
//
// line draw interrupt triggers when last D is written
// (or cycle where last D write would have been if
// ONEDOT was active)
static void blitter_interrupt (int hpos, int done)
{
if (blit_interrupt)
return;
if (!done && (!blitter_cycle_exact || immediate_blits || currprefs.cpu_model >= 68030 || currprefs.cachesize || currprefs.m68k_speed < 0))
return;
blit_interrupt = 1;
send_interrupt (6, 4 * CYCLE_UNIT);
if (debug_dma)
record_dma_event (DMA_EVENT_BLITIRQ, hpos, vpos);
}
static void blitter_done (int hpos)
{
ddat1use = ddat2use = 0;
bltstate = blit_startcycles == 0 || !blitter_cycle_exact || immediate_blits ? BLT_done : BLT_init;
blitter_interrupt (hpos, 1);
blitter_done_notify (hpos);
markidlecycle (hpos);
event2_remevent (ev2_blitter);
unset_special (SPCFLAG_BLTNASTY);
if (log_blitter & 1)
write_log (_T("cycles %d, missed %d, total %d\n"),
blit_totalcyclecounter, blit_misscyclecounter, blit_totalcyclecounter + blit_misscyclecounter);
blitter_dangerous_bpl = 0;
}
STATIC_INLINE void chipmem_agnus_wput2 (uaecptr addr, uae_u32 w)
{
//last_custom_value1 = w; blitter writes are not stored
if (!(log_blitter & 4)) {
chipmem_wput_indirect (addr, w);
debug_wputpeekdma_chipram (addr, w, MW_MASK_BLITTER_D, 0x000);
}
}
static void blitter_dofast (void)
{
int i,j;
uaecptr bltadatptr = 0, bltbdatptr = 0, bltcdatptr = 0, bltddatptr = 0;
uae_u8 mt = bltcon0 & 0xFF;
blit_masktable[0] = blt_info.bltafwm;
blit_masktable[blt_info.hblitsize - 1] &= blt_info.bltalwm;
if (bltcon0 & 0x800) {
bltadatptr = bltapt;
bltapt += (blt_info.hblitsize * 2 + blt_info.bltamod) * blt_info.vblitsize;
}
if (bltcon0 & 0x400) {
bltbdatptr = bltbpt;
bltbpt += (blt_info.hblitsize * 2 + blt_info.bltbmod) * blt_info.vblitsize;
}
if (bltcon0 & 0x200) {
bltcdatptr = bltcpt;
bltcpt += (blt_info.hblitsize * 2 + blt_info.bltcmod) * blt_info.vblitsize;
}
if (bltcon0 & 0x100) {
bltddatptr = bltdpt;
bltdpt += (blt_info.hblitsize * 2 + blt_info.bltdmod) * blt_info.vblitsize;
}
#if SPEEDUP
if (blitfunc_dofast[mt] && !blitfill) {
(*blitfunc_dofast[mt])(bltadatptr, bltbdatptr, bltcdatptr, bltddatptr, &blt_info);
} else
#endif
{
uae_u32 blitbhold = blt_info.bltbhold;
uae_u32 preva = 0, prevb = 0;
uaecptr dstp = 0;
int dodst = 0;
for (j = 0; j < blt_info.vblitsize; j++) {
blitfc = !!(bltcon1 & 0x4);
for (i = 0; i < blt_info.hblitsize; i++) {
uae_u32 bltadat, blitahold;
uae_u16 bltbdat;
if (bltadatptr) {
blt_info.bltadat = bltadat = chipmem_wget_indirect (bltadatptr);
bltadatptr += 2;
} else
bltadat = blt_info.bltadat;
bltadat &= blit_masktable[i];
blitahold = (((uae_u32)preva << 16) | bltadat) >> blt_info.blitashift;
preva = bltadat;
if (bltbdatptr) {
blt_info.bltbdat = bltbdat = chipmem_wget_indirect (bltbdatptr);
bltbdatptr += 2;
blitbhold = (((uae_u32)prevb << 16) | bltbdat) >> blt_info.blitbshift;
prevb = bltbdat;
}
if (bltcdatptr) {
blt_info.bltcdat = chipmem_wget_indirect (bltcdatptr);
bltcdatptr += 2;
}
if (dodst)
chipmem_agnus_wput2 (dstp, blt_info.bltddat);
blt_info.bltddat = blit_func (blitahold, blitbhold, blt_info.bltcdat, mt) & 0xFFFF;
if (blitfill) {
uae_u16 d = blt_info.bltddat;
int ifemode = blitife ? 2 : 0;
int fc1 = blit_filltable[d & 255][ifemode + blitfc][1];
blt_info.bltddat = (blit_filltable[d & 255][ifemode + blitfc][0]
+ (blit_filltable[d >> 8][ifemode + fc1][0] << 8));
blitfc = blit_filltable[d >> 8][ifemode + fc1][1];
}
if (blt_info.bltddat)
blt_info.blitzero = 0;
if (bltddatptr) {
dodst = 1;
dstp = bltddatptr;
bltddatptr += 2;
}
}
if (bltadatptr)
bltadatptr += blt_info.bltamod;
if (bltbdatptr)
bltbdatptr += blt_info.bltbmod;
if (bltcdatptr)
bltcdatptr += blt_info.bltcmod;
if (bltddatptr)
bltddatptr += blt_info.bltdmod;
}
if (dodst)
chipmem_agnus_wput2 (dstp, blt_info.bltddat);
blt_info.bltbhold = blitbhold;
}
blit_masktable[0] = 0xFFFF;
blit_masktable[blt_info.hblitsize - 1] = 0xFFFF;
bltstate = BLT_done;
}
static void blitter_dofast_desc (void)
{
int i,j;
uaecptr bltadatptr = 0, bltbdatptr = 0, bltcdatptr = 0, bltddatptr = 0;
uae_u8 mt = bltcon0 & 0xFF;
blit_masktable[0] = blt_info.bltafwm;
blit_masktable[blt_info.hblitsize - 1] &= blt_info.bltalwm;
if (bltcon0 & 0x800) {
bltadatptr = bltapt;
bltapt -= (blt_info.hblitsize * 2 + blt_info.bltamod) * blt_info.vblitsize;
}
if (bltcon0 & 0x400) {
bltbdatptr = bltbpt;
bltbpt -= (blt_info.hblitsize * 2 + blt_info.bltbmod) * blt_info.vblitsize;
}
if (bltcon0 & 0x200) {
bltcdatptr = bltcpt;
bltcpt -= (blt_info.hblitsize * 2 + blt_info.bltcmod) * blt_info.vblitsize;
}
if (bltcon0 & 0x100) {
bltddatptr = bltdpt;
bltdpt -= (blt_info.hblitsize * 2 + blt_info.bltdmod) * blt_info.vblitsize;
}
#if SPEEDUP
if (blitfunc_dofast_desc[mt] && !blitfill) {
(*blitfunc_dofast_desc[mt])(bltadatptr, bltbdatptr, bltcdatptr, bltddatptr, &blt_info);
} else
#endif
{
uae_u32 blitbhold = blt_info.bltbhold;
uae_u32 preva = 0, prevb = 0;
uaecptr dstp = 0;
int dodst = 0;
for (j = 0; j < blt_info.vblitsize; j++) {
blitfc = !!(bltcon1 & 0x4);
for (i = 0; i < blt_info.hblitsize; i++) {
uae_u32 bltadat, blitahold;
uae_u16 bltbdat;
if (bltadatptr) {
bltadat = blt_info.bltadat = chipmem_wget_indirect (bltadatptr);
bltadatptr -= 2;
} else
bltadat = blt_info.bltadat;
bltadat &= blit_masktable[i];
blitahold = (((uae_u32)bltadat << 16) | preva) >> blt_info.blitdownashift;
preva = bltadat;
if (bltbdatptr) {
blt_info.bltbdat = bltbdat = chipmem_wget_indirect (bltbdatptr);
bltbdatptr -= 2;
blitbhold = (((uae_u32)bltbdat << 16) | prevb) >> blt_info.blitdownbshift;
prevb = bltbdat;
}
if (bltcdatptr) {
blt_info.bltcdat = blt_info.bltbdat = chipmem_wget_indirect (bltcdatptr);
bltcdatptr -= 2;
}
if (dodst)
chipmem_agnus_wput2 (dstp, blt_info.bltddat);
blt_info.bltddat = blit_func (blitahold, blitbhold, blt_info.bltcdat, mt) & 0xFFFF;
if (blitfill) {
uae_u16 d = blt_info.bltddat;
int ifemode = blitife ? 2 : 0;
int fc1 = blit_filltable[d & 255][ifemode + blitfc][1];
blt_info.bltddat = (blit_filltable[d & 255][ifemode + blitfc][0]
+ (blit_filltable[d >> 8][ifemode + fc1][0] << 8));
blitfc = blit_filltable[d >> 8][ifemode + fc1][1];
}
if (blt_info.bltddat)
blt_info.blitzero = 0;
if (bltddatptr) {
dstp = bltddatptr;
dodst = 1;
bltddatptr -= 2;
}
}
if (bltadatptr)
bltadatptr -= blt_info.bltamod;
if (bltbdatptr)
bltbdatptr -= blt_info.bltbmod;
if (bltcdatptr)
bltcdatptr -= blt_info.bltcmod;
if (bltddatptr)
bltddatptr -= blt_info.bltdmod;
}
if (dodst)
chipmem_agnus_wput2 (dstp, blt_info.bltddat);
blt_info.bltbhold = blitbhold;
}
blit_masktable[0] = 0xFFFF;
blit_masktable[blt_info.hblitsize - 1] = 0xFFFF;
bltstate = BLT_done;
}
STATIC_INLINE void blitter_read (void)
{
if (bltcon0 & 0x200) {
if (!dmaen (DMA_BLITTER))
return;
blt_info.bltcdat = chipmem_wget_indirect (bltcpt);
debug_wgetpeekdma_chipram (bltcpt, blt_info.bltcdat, MW_MASK_BLITTER_C, 0x070);
last_custom_value1 = blt_info.bltcdat;
}
bltstate = BLT_work;
}
STATIC_INLINE void blitter_write (void)
{
if (blt_info.bltddat)
blt_info.blitzero = 0;
/* D-channel state has no effect on linedraw, but C must be enabled or nothing is drawn! */
if (bltcon0 & 0x200) {
if (!dmaen (DMA_BLITTER))
return;
//last_custom_value1 = blt_info.bltddat; blitter writes are not stored
chipmem_wput_indirect (bltdpt, blt_info.bltddat);
debug_wputpeekdma_chipram (bltdpt, blt_info.bltddat, MW_MASK_BLITTER_D, 0x000);
}
bltstate = BLT_next;
}
STATIC_INLINE void blitter_line_incx (void)
{
if (++blinea_shift == 16) {
blinea_shift = 0;
bltcpt += 2;
}
}
STATIC_INLINE void blitter_line_decx (void)
{
if (blinea_shift-- == 0) {
blinea_shift = 15;
bltcpt -= 2;
}
}
STATIC_INLINE void blitter_line_decy (void)
{
bltcpt -= blt_info.bltcmod;
blitonedot = 0;
}
STATIC_INLINE void blitter_line_incy (void)
{
bltcpt += blt_info.bltcmod;
blitonedot = 0;
}
static void blitter_line (void)
{
uae_u16 blitahold = (blinea & blt_info.bltafwm) >> blinea_shift;
uae_u16 blitchold = blt_info.bltcdat;
blt_info.bltbhold = (blineb & 1) ? 0xFFFF : 0;
blitlinepixel = !blitsing || (blitsing && !blitonedot);
blt_info.bltddat = blit_func (blitahold, blt_info.bltbhold, blitchold, bltcon0 & 0xFF);
blitonedot++;
}
static void blitter_line_proc (void)
{
if (bltcon0 & 0x800) {
if (blitsign)
bltapt += (uae_s16)blt_info.bltbmod;
else
bltapt += (uae_s16)blt_info.bltamod;
}
if (!blitsign) {
if (bltcon1 & 0x10) {
if (bltcon1 & 0x8)
blitter_line_decy ();
else
blitter_line_incy ();
} else {
if (bltcon1 & 0x8)
blitter_line_decx ();
else
blitter_line_incx ();
}
}
if (bltcon1 & 0x10) {
if (bltcon1 & 0x4)
blitter_line_decx ();
else
blitter_line_incx ();
} else {
if (bltcon1 & 0x4)
blitter_line_decy ();
else
blitter_line_incy ();
}
blitsign = 0 > (uae_s16)bltapt;
bltstate = BLT_write;
}
STATIC_INLINE void blitter_nxline (void)
{
blineb = (blineb << 1) | (blineb >> 15);
blt_info.vblitsize--;
bltstate = BLT_read;
}
#ifdef CPUEMU_13
static int blitter_cyclecounter;
static int blitter_hcounter1, blitter_hcounter2;
static int blitter_vcounter1, blitter_vcounter2;
static void decide_blitter_line (int hsync, int hpos)
{
if (blit_final && blt_info.vblitsize)
blit_final = 0;
while (last_blitter_hpos < hpos) {
int c = channel_state (blit_cyclecounter);
for (;;) {
int v = canblit (last_blitter_hpos);
if (blit_waitcyclecounter) {
blit_waitcyclecounter = 0;
break;
}
// final 2 idle cycles? does not need free bus
if (blit_final) {
blit_cyclecounter++;
blit_totalcyclecounter++;
if (blit_cyclecounter >= 2) {
blitter_done (last_blitter_hpos);
return;
}
break;
}
if (v <= 0) {
blit_misscyclecounter++;
blitter_nasty++;
break;
}
blit_cyclecounter++;
blit_totalcyclecounter++;
check_channel_mods (last_blitter_hpos, c);
if (c == 3) {
blitter_read ();
alloc_cycle_blitter (last_blitter_hpos, &bltcpt, 3);
record_dma_blit (0x70, blt_info.bltcdat, bltcpt, last_blitter_hpos);
blitter_nasty++;
} else if (c == 5) {
if (ddat1use) {
bltdpt = bltcpt;
}
ddat1use = 1;
blitter_line ();
blitter_line_proc ();
blitter_nxline ();
} else if (c == 4) {
/* onedot mode and no pixel = bus write access is skipped */
if (blitlinepixel) {
blitter_write ();
alloc_cycle_blitter (last_blitter_hpos, &bltdpt, 4);
record_dma_blit (0x00, blt_info.bltddat, bltdpt, last_blitter_hpos);
blitlinepixel = 0;
blitter_nasty++;
}
if (blt_info.vblitsize == 0) {
bltdpt = bltcpt;
blit_final = 1;
blit_cyclecounter = 0;
blit_waitcyclecounter = 0;
// blit finished bit is set and interrupt triggered
// immediately after last D write
blitter_interrupt (last_blitter_hpos, 0);
break;
}
}
break;
}
last_blitter_hpos++;
}
if (hsync)
last_blitter_hpos = 0;
reset_channel_mods ();
}
#endif
static void actually_do_blit (void)
{
if (blitline) {
do {
blitter_read ();
if (ddat1use)
bltdpt = bltcpt;
ddat1use = 1;
blitter_line ();
blitter_line_proc ();
blitter_nxline ();
if (blitlinepixel) {
blitter_write ();
blitlinepixel = 0;
}
if (blt_info.vblitsize == 0)
bltstate = BLT_done;
} while (bltstate != BLT_done);
bltdpt = bltcpt;
} else {
if (blitdesc)
blitter_dofast_desc ();
else
blitter_dofast ();
bltstate = BLT_done;
}
}
static void blitter_doit (void)
{
if (blt_info.vblitsize == 0 || (blitline && blt_info.hblitsize != 2)) {
blitter_done (current_hpos());
return;
}
if (log_blitter) {
if (!blitter_dontdo)
actually_do_blit ();
else
bltstate = BLT_done;
} else {
actually_do_blit ();
}
blitter_done (current_hpos ());
}
void blitter_handler (uae_u32 data)
{
static int blitter_stuck;
if (!dmaen (DMA_BLITTER)) {
event2_newevent (ev2_blitter, 10, 0);
blitter_stuck++;
if (blitter_stuck < 20000 || !immediate_blits)
return; /* gotta come back later. */
/* "free" blitter in immediate mode if it has been "stuck" ~3 frames
* fixes some JIT game incompatibilities
*/
debugtest (DEBUGTEST_BLITTER, _T("force-unstuck!\n"));
}
blitter_stuck = 0;
if (blit_slowdown > 0 && !immediate_blits) {
event2_newevent (ev2_blitter, blit_slowdown, 0);
blit_slowdown = -1;
return;
}
blitter_doit ();
}
#ifdef CPUEMU_13
static uae_u32 preva, prevb;
STATIC_INLINE uae_u16 blitter_doblit (void)
{
uae_u32 blitahold;
uae_u16 bltadat, ddat;
uae_u8 mt = bltcon0 & 0xFF;
bltadat = blt_info.bltadat;
if (blitter_hcounter1 == 0)
bltadat &= blt_info.bltafwm;
if (blitter_hcounter1 == blt_info.hblitsize - 1)
bltadat &= blt_info.bltalwm;
if (blitdesc)
blitahold = (((uae_u32)bltadat << 16) | preva) >> blt_info.blitdownashift;
else
blitahold = (((uae_u32)preva << 16) | bltadat) >> blt_info.blitashift;
preva = bltadat;
ddat = blit_func (blitahold, blt_info.bltbhold, blt_info.bltcdat, mt) & 0xFFFF;
if ((bltcon1 & 0x18)) {
uae_u16 d = ddat;
int ifemode = blitife ? 2 : 0;
int fc1 = blit_filltable[d & 255][ifemode + blitfc][1];
ddat = (blit_filltable[d & 255][ifemode + blitfc][0]
+ (blit_filltable[d >> 8][ifemode + fc1][0] << 8));
blitfc = blit_filltable[d >> 8][ifemode + fc1][1];
}
if (ddat)
blt_info.blitzero = 0;
return ddat;
}
STATIC_INLINE void blitter_doddma (int hpos)
{
int wd;
uae_u16 d;
wd = 0;
if (blit_dmacount2 == 0) {
d = blitter_doblit ();
wd = -1;
} else if (ddat2use) {
d = ddat2;
ddat2use = 0;
wd = 2;
} else if (ddat1use) {
d = ddat1;
ddat1use = 0;
wd = 1;
} else {
static int warn = 10;
if (warn > 0) {
warn--;
write_log (_T("BLITTER: D-channel without nothing to do?\n"));
}
return;
}
record_dma_blit (0x00, d, bltdpt, hpos);
//last_custom_value1 = d; blitter writes are not stored
chipmem_agnus_wput2 (bltdpt, d);
alloc_cycle_blitter (hpos, &bltdpt, 4);
bltdpt += blit_add;
blitter_hcounter2++;
if (blitter_hcounter2 == blt_info.hblitsize) {
blitter_hcounter2 = 0;
bltdpt += blit_modaddd;
blitter_vcounter2++;
if (blit_dmacount2 == 0) // d-only
blitter_vcounter1++;
if (blitter_vcounter2 > blitter_vcounter1)
blitter_vcounter1 = blitter_vcounter2;
}
if (blit_ch == 1)
blitter_hcounter1 = blitter_hcounter2;
}
STATIC_INLINE void blitter_dodma (int ch, int hpos)
{
uae_u16 dat, reg;