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cpummu30.cpp
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cpummu30.cpp
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/* Emulation of MC68030 MMU
* This code has been written for Previous - a NeXT Computer emulator
*
* This file is distributed under the GNU General Public License, version 2
* or at your option any later version. Read the file gpl.txt for details.
*
*
* Written by Andreas Grabher
*
* Many thanks go to Thomas Huth and the Hatari community for helping
* to test and debug this code!
*
*
* Release notes:
* 01-09-2012: First release
* 29-09-2012: Improved function code handling
* 16-11-2012: Improved exception handling
*
*
* - Check if read-modify-write operations are correctly detected for
* handling transparent access (see TT matching functions)
* - If possible, test mmu030_table_search with all kinds of translations
* (early termination, invalid descriptors, bus errors, indirect
* descriptors, PTEST in different levels, etc).
* - Check which bits of an ATC entry or the status register should be set
* and which should be un-set, if an invalid translation occurs.
* - Handle cache inhibit bit when accessing ATC entries
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "memory.h"
#include "newcpu.h"
#include "cpummu030.h"
#define MMU030_OP_DBG_MSG 0
#define MMU030_ATC_DBG_MSG 0
#define MMU030_REG_DBG_MSG 0
#define TT_FC_MASK 0x00000007
#define TT_FC_BASE 0x00000070
#define TT_RWM 0x00000100
#define TT_RW 0x00000200
#define TT_CI 0x00000400
#define TT_ENABLE 0x00008000
#define TT_ADDR_MASK 0x00FF0000
#define TT_ADDR_BASE 0xFF000000
static int bBusErrorReadWrite;
static int atcindextable[32];
static int tt_enabled;
int mmu030_idx;
uae_u32 mm030_stageb_address;
bool mmu030_retry;
int mmu030_opcode;
int mmu030_opcode_stageb;
int mmu030_fake_prefetch;
uae_u16 mmu030_state[3];
uae_u32 mmu030_data_buffer;
uae_u32 mmu030_disp_store[2];
uae_u32 mmu030_fmovem_store[2];
struct mmu030_access mmu030_ad[MAX_MMU030_ACCESS];
/* for debugging messages */
char table_letter[4] = {'A','B','C','D'};
uae_u64 srp_030, crp_030;
uae_u32 tt0_030, tt1_030, tc_030;
uae_u16 mmusr_030;
/* ATC struct */
#define ATC030_NUM_ENTRIES 22
typedef struct {
struct {
uaecptr addr;
bool modified;
bool write_protect;
bool cache_inhibit;
bool bus_error;
} physical;
struct {
uaecptr addr;
uae_u32 fc;
bool valid;
} logical;
/* history bit */
int mru;
} MMU030_ATC_LINE;
/* MMU struct for 68030 */
static struct {
/* Translation tables */
struct {
struct {
uae_u32 mask;
uae_u8 shift;
} table[4];
struct {
uae_u32 mask;
uae_u32 imask;
uae_u8 size;
} page;
uae_u8 init_shift;
uae_u8 last_table;
} translation;
/* Transparent translation */
struct {
TT_info tt0;
TT_info tt1;
} transparent;
/* Address translation cache */
MMU030_ATC_LINE atc[ATC030_NUM_ENTRIES];
/* Condition */
bool enabled;
uae_u16 status;
} mmu030;
/* MMU Status Register
*
* ---x ---x x-xx x---
* reserved (all 0)
*
* x--- ---- ---- ----
* bus error
*
* -x-- ---- ---- ----
* limit violation
*
* --x- ---- ---- ----
* supervisor only
*
* ---- x--- ---- ----
* write protected
*
* ---- -x-- ---- ----
* invalid
*
* ---- --x- ---- ----
* modified
*
* ---- ---- -x-- ----
* transparent access
*
* ---- ---- ---- -xxx
* number of levels (number of tables accessed during search)
*
*/
#define MMUSR_BUS_ERROR 0x8000
#define MMUSR_LIMIT_VIOLATION 0x4000
#define MMUSR_SUPER_VIOLATION 0x2000
#define MMUSR_WRITE_PROTECTED 0x0800
#define MMUSR_INVALID 0x0400
#define MMUSR_MODIFIED 0x0200
#define MMUSR_TRANSP_ACCESS 0x0040
#define MMUSR_NUM_LEVELS_MASK 0x0007
/* -- MMU instructions -- */
bool mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
int preg = (next >> 10) & 31;
int rw = (next >> 9) & 1;
int fd = (next >> 8) & 1;
#if MMU030_OP_DBG_MSG
switch (preg) {
case 0x10:
write_log(_T("PMOVE: %s TC %08X\n"), rw?"read":"write",
rw?tc_030:x_get_long(extra));
break;
case 0x12:
write_log(_T("PMOVE: %s SRP %08X%08X\n"), rw?"read":"write",
rw?(uae_u32)(srp_030>>32)&0xFFFFFFFF:x_get_long(extra),
rw?(uae_u32)srp_030&0xFFFFFFFF:x_get_long(extra+4));
break;
case 0x13:
write_log(_T("PMOVE: %s CRP %08X%08X\n"), rw?"read":"write",
rw?(uae_u32)(crp_030>>32)&0xFFFFFFFF:x_get_long(extra),
rw?(uae_u32)crp_030&0xFFFFFFFF:x_get_long(extra+4));
break;
case 0x18:
write_log(_T("PMOVE: %s MMUSR %04X\n"), rw?"read":"write",
rw?mmusr_030:x_get_word(extra));
break;
case 0x02:
write_log(_T("PMOVE: %s TT0 %08X\n"), rw?"read":"write",
rw?tt0_030:x_get_long(extra));
break;
case 0x03:
write_log(_T("PMOVE: %s TT1 %08X\n"), rw?"read":"write",
rw?tt1_030:x_get_long(extra));
break;
default:
break;
}
if (!fd && !rw && !(preg==0x18)) {
write_log(_T("PMOVE: flush ATC\n"));
}
#endif
switch (preg)
{
case 0x10: // TC
if (rw)
x_put_long (extra, tc_030);
else {
tc_030 = x_get_long (extra);
if (mmu030_decode_tc(tc_030))
return true;
}
break;
case 0x12: // SRP
if (rw) {
x_put_long (extra, srp_030 >> 32);
x_put_long (extra + 4, srp_030);
} else {
srp_030 = (uae_u64)x_get_long (extra) << 32;
srp_030 |= x_get_long (extra + 4);
if (mmu030_decode_rp(srp_030))
return true;
}
break;
case 0x13: // CRP
if (rw) {
x_put_long (extra, crp_030 >> 32);
x_put_long (extra + 4, crp_030);
} else {
crp_030 = (uae_u64)x_get_long (extra) << 32;
crp_030 |= x_get_long (extra + 4);
if (mmu030_decode_rp(crp_030))
return true;
}
break;
case 0x18: // MMUSR
if (rw)
x_put_word (extra, mmusr_030);
else
mmusr_030 = x_get_word (extra);
break;
case 0x02: // TT0
if (rw)
x_put_long (extra, tt0_030);
else {
tt0_030 = x_get_long (extra);
mmu030.transparent.tt0 = mmu030_decode_tt(tt0_030);
}
break;
case 0x03: // TT1
if (rw)
x_put_long (extra, tt1_030);
else {
tt1_030 = x_get_long (extra);
mmu030.transparent.tt1 = mmu030_decode_tt(tt1_030);
}
break;
default:
write_log (_T("Bad PMOVE at %08x\n"),m68k_getpc());
op_illg (opcode);
return true;
}
if (!fd && !rw && !(preg==0x18)) {
mmu030_flush_atc_all();
}
tt_enabled = (tt0_030 & TT_ENABLE) || (tt1_030 & TT_ENABLE);
return false;
}
bool mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
mmu030.status = mmusr_030 = 0;
int level = (next&0x1C00)>>10;
int rw = (next >> 9) & 1;
int a = (next >> 8) & 1;
int areg = (next&0xE0)>>5;
uae_u32 fc = mmu_op30_helper_get_fc(next);
bool write = rw ? false : true;
uae_u32 ret = 0;
/* Check this - datasheet says:
* "When the instruction specifies an address translation cache search
* with an address register operand, the MC68030 takes an F-line
* unimplemented instruction exception."
*/
if (!level && a) { /* correct ? */
write_log(_T("PTEST: Bad instruction causing F-line unimplemented instruction exception!\n"));
Exception(11); /* F-line unimplemented instruction exception */
return true;
}
#if MMU030_OP_DBG_MSG
write_log(_T("PTEST%c: addr = %08X, fc = %i, level = %i, "),
rw?'R':'W', extra, fc, level);
if (a) {
write_log(_T("return descriptor to register A%i\n"), areg);
} else {
write_log(_T("do not return descriptor\n"));
}
#endif
if (!level) {
mmu030_ptest_atc_search(extra, fc, write);
} else {
ret = mmu030_ptest_table_search(extra, fc, write, level);
if (a) {
m68k_areg (regs, areg) = ret;
}
}
mmusr_030 = mmu030.status;
#if MMU030_OP_DBG_MSG
write_log(_T("PTEST status: %04X, B = %i, L = %i, S = %i, W = %i, I = %i, M = %i, T = %i, N = %i\n"),
mmusr_030, (mmusr_030&MMUSR_BUS_ERROR)?1:0, (mmusr_030&MMUSR_LIMIT_VIOLATION)?1:0,
(mmusr_030&MMUSR_SUPER_VIOLATION)?1:0, (mmusr_030&MMUSR_WRITE_PROTECTED)?1:0,
(mmusr_030&MMUSR_INVALID)?1:0, (mmusr_030&MMUSR_MODIFIED)?1:0,
(mmusr_030&MMUSR_TRANSP_ACCESS)?1:0, mmusr_030&MMUSR_NUM_LEVELS_MASK);
#endif
return false;
}
bool mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
int rw = (next >> 9) & 1;
uae_u32 fc = mmu_op30_helper_get_fc(next);
bool write = rw ? false : true;
#if 0
write_log (_T("PLOAD%c: Create ATC entry for %08X, FC = %i\n"), write?'W':'R', extra, fc);
#endif
mmu030_flush_atc_page(extra);
mmu030_table_search(extra, fc, write, 0);
return false;
}
bool mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
uae_u16 mode = (next&0x1C00)>>10;
uae_u32 fc_mask = (uae_u32)(next&0x00E0)>>5;
uae_u32 fc_base = mmu_op30_helper_get_fc(next);
#if 0
switch (mode) {
case 0x1:
write_log(_T("PFLUSH: Flush all entries\n"));
break;
case 0x4:
write_log(_T("PFLUSH: Flush by function code only\n"));
write_log(_T("PFLUSH: function code: base = %08X, mask = %08X\n"), fc_base, fc_mask);
break;
case 0x6:
write_log(_T("PFLUSH: Flush by function code and effective address\n"));
write_log(_T("PFLUSH: function code: base = %08X, mask = %08X\n"), fc_base, fc_mask);
write_log(_T("PFLUSH: effective address = %08X\n"), extra);
break;
default:
break;
}
#endif
switch (mode) {
case 0x1:
mmu030_flush_atc_all();
break;
case 0x4:
mmu030_flush_atc_fc(fc_base, fc_mask);
break;
case 0x6:
mmu030_flush_atc_page_fc(extra, fc_base, fc_mask);
break;
default:
write_log(_T("PFLUSH ERROR: bad mode! (%i)\n"),mode);
break;
}
return false;
}
/* -- Helper function for MMU instructions -- */
uae_u32 mmu_op30_helper_get_fc(uae_u16 next) {
switch (next&0x0018) {
case 0x0010:
return (next&0x7);
case 0x0008:
return (m68k_dreg(regs, next&0x7)&0x7);
case 0x0000:
if (next&1) {
return (regs.dfc);
} else {
return (regs.sfc);
}
default:
write_log(_T("MMU_OP30 ERROR: bad fc source! (%04X)\n"),next&0x0018);
return 0;
}
}
/* -- ATC flushing functions -- */
/* This function flushes ATC entries depending on their function code */
void mmu030_flush_atc_fc(uae_u32 fc_base, uae_u32 fc_mask) {
int i;
for (i=0; i<ATC030_NUM_ENTRIES; i++) {
if (((fc_base&fc_mask)==(mmu030.atc[i].logical.fc&fc_mask)) &&
mmu030.atc[i].logical.valid) {
mmu030.atc[i].logical.valid = false;
#if MMU030_OP_DBG_MSG
write_log(_T("ATC: Flushing %08X\n"), mmu030.atc[i].physical.addr);
#endif
}
}
}
/* This function flushes ATC entries depending on their logical address
* and their function code */
void mmu030_flush_atc_page_fc(uaecptr logical_addr, uae_u32 fc_base, uae_u32 fc_mask) {
int i;
logical_addr &= mmu030.translation.page.imask;
for (i=0; i<ATC030_NUM_ENTRIES; i++) {
if (((fc_base&fc_mask)==(mmu030.atc[i].logical.fc&fc_mask)) &&
(mmu030.atc[i].logical.addr == logical_addr) &&
mmu030.atc[i].logical.valid) {
mmu030.atc[i].logical.valid = false;
#if MMU030_OP_DBG_MSG
write_log(_T("ATC: Flushing %08X\n"), mmu030.atc[i].physical.addr);
#endif
}
}
}
/* This function flushes ATC entries depending on their logical address */
void mmu030_flush_atc_page(uaecptr logical_addr) {
int i;
logical_addr &= mmu030.translation.page.imask;
for (i=0; i<ATC030_NUM_ENTRIES; i++) {
if ((mmu030.atc[i].logical.addr == logical_addr) &&
mmu030.atc[i].logical.valid) {
mmu030.atc[i].logical.valid = false;
#if MMU030_OP_DBG_MSG
write_log(_T("ATC: Flushing %08X\n"), mmu030.atc[i].physical.addr);
#endif
}
}
}
/* This function flushes all ATC entries */
void mmu030_flush_atc_all(void) {
#if MMU030_OP_DBG_MSG
write_log(_T("ATC: Flushing all entries\n"));
#endif
int i;
for (i=0; i<ATC030_NUM_ENTRIES; i++) {
mmu030.atc[i].logical.valid = false;
}
}
/* Transparent Translation Registers (TT0 and TT1)
*
* ---- ---- ---- ---- -xxx x--- x--- x---
* reserved, must be 0
*
* ---- ---- ---- ---- ---- ---- ---- -xxx
* function code mask (FC bits to be ignored)
*
* ---- ---- ---- ---- ---- ---- -xxx ----
* function code base (FC value for transparent block)
*
* ---- ---- ---- ---- ---- ---x ---- ----
* 0 = r/w field used, 1 = read and write is transparently translated
*
* ---- ---- ---- ---- ---- --x- ---- ----
* r/w field: 0 = write ..., 1 = read access transparent
*
* ---- ---- ---- ---- ---- -x-- ---- ----
* cache inhibit: 0 = caching allowed, 1 = caching inhibited
*
* ---- ---- ---- ---- x--- ---- ---- ----
* 0 = transparent translation enabled disabled, 1 = enabled
*
* ---- ---- xxxx xxxx ---- ---- ---- ----
* logical address mask
*
* xxxx xxxx ---- ---- ---- ---- ---- ----
* logical address base
*
*/
/* TT comparision results */
#define TT_NO_MATCH 0x1
#define TT_OK_MATCH 0x2
#define TT_NO_READ 0x4
#define TT_NO_WRITE 0x8
TT_info mmu030_decode_tt(uae_u32 TT) {
TT_info ret;
ret.fc_mask = ~((TT&TT_FC_MASK)|0xFFFFFFF8);
ret.fc_base = (TT&TT_FC_BASE)>>4;
ret.addr_base = TT & TT_ADDR_BASE;
ret.addr_mask = ~(((TT&TT_ADDR_MASK)<<8)|0x00FFFFFF);
#if 0
if ((TT&TT_ENABLE) && !(TT&TT_RWM)) {
write_log(_T("MMU Warning: Transparent translation of read-modify-write cycle is not correctly handled!\n"));
}
#endif
#if MMU030_REG_DBG_MSG /* enable or disable debugging messages */
write_log(_T("\n"));
write_log(_T("TRANSPARENT TRANSLATION: %08X\n"), TT);
write_log(_T("\n"));
write_log(_T("TT: transparent translation "));
if (TT&TT_ENABLE) {
write_log(_T("enabled\n"));
} else {
write_log(_T("disabled\n"));
return ret;
}
write_log(_T("TT: caching %s\n"), (TT&TT_CI) ? _T("inhibited") : _T("enabled"));
write_log(_T("TT: read-modify-write "));
if (TT&TT_RWM) {
write_log(_T("enabled\n"));
} else {
write_log(_T("disabled (%s only)\n"), (TT&TT_RW) ? _T("read") : _T("write"));
}
write_log(_T("\n"));
write_log(_T("TT: function code base: %08X\n"), ret.fc_base);
write_log(_T("TT: function code mask: %08X\n"), ret.fc_mask);
write_log(_T("\n"));
write_log(_T("TT: address base: %08X\n"), ret.addr_base);
write_log(_T("TT: address mask: %08X\n"), ret.addr_mask);
write_log(_T("\n"));
#endif
return ret;
}
/* This function compares the address with both transparent
* translation registers and returns the result */
int mmu030_match_ttr(uaecptr addr, uae_u32 fc, bool write)
{
int tt0, tt1;
bool cache_inhibit = false; /* TODO: pass to memory access function */
tt0 = mmu030_do_match_ttr(tt0_030, mmu030.transparent.tt0, addr, fc, write);
if (tt0&TT_OK_MATCH) {
cache_inhibit = (tt0_030&TT_CI) ? true : false;
}
tt1 = mmu030_do_match_ttr(tt1_030, mmu030.transparent.tt1, addr, fc, write);
if (tt1&TT_OK_MATCH) {
if (!cache_inhibit) {
cache_inhibit = (tt1_030&TT_CI) ? true : false;
}
}
return (tt0|tt1);
}
int mmu030_match_ttr_access(uaecptr addr, uae_u32 fc, bool write)
{
int tt0, tt1;
if (!tt_enabled)
return 0;
tt0 = mmu030_do_match_ttr(tt0_030, mmu030.transparent.tt0, addr, fc, write);
tt1 = mmu030_do_match_ttr(tt1_030, mmu030.transparent.tt1, addr, fc, write);
return (tt0|tt1) & TT_OK_MATCH;
}
/* Locked Read-Modify-Write */
int mmu030_match_lrmw_ttr_access(uaecptr addr, uae_u32 fc)
{
int tt0, tt1;
if (!tt_enabled)
return 0;
tt0 = mmu030_do_match_lrmw_ttr(tt0_030, mmu030.transparent.tt0, addr, fc);
tt1 = mmu030_do_match_lrmw_ttr(tt1_030, mmu030.transparent.tt1, addr, fc);
return (tt0|tt1) & TT_OK_MATCH;
}
/* This function checks if an address matches a transparent
* translation register */
/* FIXME:
* If !(tt&TT_RMW) neither the read nor the write portion
* of a read-modify-write cycle is transparently translated! */
int mmu030_do_match_ttr(uae_u32 tt, TT_info comp, uaecptr addr, uae_u32 fc, bool write)
{
if (tt & TT_ENABLE) { /* transparent translation enabled */
/* Compare actual function code with function code base using mask */
if ((comp.fc_base&comp.fc_mask)==(fc&comp.fc_mask)) {
/* Compare actual address with address base using mask */
if ((comp.addr_base&comp.addr_mask)==(addr&comp.addr_mask)) {
if (tt&TT_RWM) { /* r/w field disabled */
return TT_OK_MATCH;
} else {
if (tt&TT_RW) { /* read access transparent */
return write ? TT_NO_WRITE : TT_OK_MATCH;
} else { /* write access transparent */
return write ? TT_OK_MATCH : TT_NO_READ; /* TODO: check this! */
}
}
}
}
}
return TT_NO_MATCH;
}
int mmu030_do_match_lrmw_ttr(uae_u32 tt, TT_info comp, uaecptr addr, uae_u32 fc)
{
if ((tt & TT_ENABLE) && (tt & TT_RWM)) { /* transparent translation enabled */
/* Compare actual function code with function code base using mask */
if ((comp.fc_base&comp.fc_mask)==(fc&comp.fc_mask)) {
/* Compare actual address with address base using mask */
if ((comp.addr_base&comp.addr_mask)==(addr&comp.addr_mask)) {
return TT_OK_MATCH;
}
}
}
return TT_NO_MATCH;
}
/* Translation Control Register:
*
* x--- ---- ---- ---- ---- ---- ---- ----
* translation: 1 = enable, 0 = disable
*
* ---- --x- ---- ---- ---- ---- ---- ----
* supervisor root: 1 = enable, 0 = disable
*
* ---- ---x ---- ---- ---- ---- ---- ----
* function code lookup: 1 = enable, 0 = disable
*
* ---- ---- xxxx ---- ---- ---- ---- ----
* page size:
* 1000 = 256 bytes
* 1001 = 512 bytes
* 1010 = 1 kB
* 1011 = 2 kB
* 1100 = 4 kB
* 1101 = 8 kB
* 1110 = 16 kB
* 1111 = 32 kB
*
* ---- ---- ---- xxxx ---- ---- ---- ----
* initial shift
*
* ---- ---- ---- ---- xxxx ---- ---- ----
* number of bits for table index A
*
* ---- ---- ---- ---- ---- xxxx ---- ----
* number of bits for table index B
*
* ---- ---- ---- ---- ---- ---- xxxx ----
* number of bits for table index C
*
* ---- ---- ---- ---- ---- ----- ---- xxxx
* number of bits for table index D
*
*/
#define TC_ENABLE_TRANSLATION 0x80000000
#define TC_ENABLE_SUPERVISOR 0x02000000
#define TC_ENABLE_FCL 0x01000000
#define TC_PS_MASK 0x00F00000
#define TC_IS_MASK 0x000F0000
#define TC_TIA_MASK 0x0000F000
#define TC_TIB_MASK 0x00000F00
#define TC_TIC_MASK 0x000000F0
#define TC_TID_MASK 0x0000000F
static void mmu030_do_fake_prefetch(void)
{
uaecptr pc = m68k_getpci();
// fetch next opcode before MMU state switches.
// There are programs that do following:
// - enable MMU
// - JMP (An)
// "enable MMU" unmaps memory under us.
TRY (prb) {
mmu030_fake_prefetch = x_prefetch(0);
} CATCH (prb) {
// didn't work, oh well..
mmu030_fake_prefetch = -1;
} ENDTRY
write_log(_T("MMU030 fake prefetched %04X\n"), mmu030_fake_prefetch);
}
bool mmu030_decode_tc(uae_u32 TC)
{
/* Set MMU condition */
if (TC & TC_ENABLE_TRANSLATION) {
if (!mmu030.enabled)
mmu030_do_fake_prefetch();
mmu030.enabled = true;
} else {
if (mmu030.enabled) {
mmu030_do_fake_prefetch();
write_log(_T("MMU disabled\n"));
}
mmu030.enabled = false;
return false;
}
/* Note: 0 = Table A, 1 = Table B, 2 = Table C, 3 = Table D */
int i, j;
uae_u8 TI_bits[4] = {0,0,0,0};
/* Reset variables before extracting new values from TC */
for (i = 0; i < 4; i++) {
mmu030.translation.table[i].mask = 0;
mmu030.translation.table[i].shift = 0;
}
/* Extract initial shift and page size values from TC register */
mmu030.translation.page.size = (TC & TC_PS_MASK) >> 20;
mmu030.translation.init_shift = (TC & TC_IS_MASK) >> 16;
regs.mmu_page_size = 1 << mmu030.translation.page.size;
write_log(_T("68030 MMU enabled. Page size = %d\n"), regs.mmu_page_size);
if (mmu030.translation.page.size<8) {
write_log(_T("MMU Configuration Exception: Bad value in TC register! (bad page size: %i byte)\n"),
1<<mmu030.translation.page.size);
Exception(56); /* MMU Configuration Exception */
return true;
}
mmu030.translation.page.mask = regs.mmu_page_size - 1;
mmu030.translation.page.imask = ~mmu030.translation.page.mask;
/* Calculate masks and shifts for later extracting table indices
* from logical addresses using: index = (addr&mask)>>shift */
/* Get number of bits for each table index */
for (i = 0; i < 4; i++) {
j = (3-i)*4;
TI_bits[i] = (TC >> j) & 0xF;
}
/* Calculate masks and shifts for each table */
mmu030.translation.last_table = 0;
uae_u8 shift = 32 - mmu030.translation.init_shift;
for (i = 0; (i < 4) && TI_bits[i]; i++) {
/* Get the shift */
shift -= TI_bits[i];
mmu030.translation.table[i].shift = shift;
/* Build the mask */
for (j = 0; j < TI_bits[i]; j++) {
mmu030.translation.table[i].mask |= (1<<(mmu030.translation.table[i].shift + j));
}
/* Update until reaching the last table */
mmu030.translation.last_table = i;
}
#if MMU030_REG_DBG_MSG
/* At least one table has to be defined using at least
* 1 bit for the index. At least 2 bits are necessary
* if there is no second table. If these conditions are
* not met, it will automatically lead to a sum <32
* and cause an exception (see below). */
if (!TI_bits[0]) {
write_log(_T("MMU Configuration Exception: Bad value in TC register! (no first table index defined)\n"));
} else if ((TI_bits[0]<2) && !TI_bits[1]) {
write_log(_T("MMU Configuration Exception: Bad value in TC register! (no second table index defined and)\n"));
write_log(_T("MMU Configuration Exception: Bad value in TC register! (only 1 bit for first table index)\n"));
}
#endif
/* TI fields are summed up until a zero field is reached (see above
* loop). The sum of all TI field values plus page size and initial
* shift has to be 32: IS + PS + TIA + TIB + TIC + TID = 32 */
if ((shift-mmu030.translation.page.size)!=0) {
write_log(_T("MMU Configuration Exception: Bad value in TC register! (bad sum)\n"));
Exception(56); /* MMU Configuration Exception */
return true;
}
#if MMU030_REG_DBG_MSG /* enable or disable debugging output */
write_log(_T("\n"));
write_log(_T("TRANSLATION CONTROL: %08X\n"), TC);
write_log(_T("\n"));
write_log(_T("TC: translation %s\n"), (TC&TC_ENABLE_TRANSLATION ? _T("enabled") : _T("disabled")));
write_log(_T("TC: supervisor root pointer %s\n"), (TC&TC_ENABLE_SUPERVISOR ? _T("enabled") : _T("disabled")));
write_log(_T("TC: function code lookup %s\n"), (TC&TC_ENABLE_FCL ? _T("enabled") : _T("disabled")));
write_log(_T("\n"));
write_log(_T("TC: Initial Shift: %i\n"), mmu030.translation.init_shift);
write_log(_T("TC: Page Size: %i byte\n"), (1<<mmu030.translation.page.size));
write_log(_T("\n"));
for (i = 0; i <= mmu030.translation.last_table; i++) {
write_log(_T("TC: Table %c: mask = %08X, shift = %i\n"), table_letter[i], mmu030.translation.table[i].mask, mmu030.translation.table[i].shift);
}
write_log(_T("TC: Page: mask = %08X\n"), mmu030.translation.page.mask);
write_log(_T("\n"));
write_log(_T("TC: Last Table: %c\n"), table_letter[mmu030.translation.last_table]);
write_log(_T("\n"));
#endif
return false;
}
/* Root Pointer Registers (SRP and CRP)
*
* ---- ---- ---- ---- xxxx xxxx xxxx xx-- ---- ---- ---- ---- ---- ---- ---- xxxx
* reserved, must be 0
*
* ---- ---- ---- ---- ---- ---- ---- ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx ----
* table A address
*
* ---- ---- ---- ---- ---- ---- ---- --xx ---- ---- ---- ---- ---- ---- ---- ----
* descriptor type
*
* -xxx xxxx xxxx xxxx ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
* limit
*
* x--- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
* 0 = upper limit, 1 = lower limit
*
*/
#define RP_ADDR_MASK (UVAL64(0x00000000FFFFFFF0))
#define RP_DESCR_MASK (UVAL64(0x0000000300000000))
#define RP_LIMIT_MASK (UVAL64(0x7FFF000000000000))
#define RP_LOWER_MASK (UVAL64(0x8000000000000000))
#define RP_ZERO_BITS 0x0000FFFC /* These bits in upper longword of RP must be 0 */
bool mmu030_decode_rp(uae_u64 RP) {
uae_u8 descriptor_type = (RP & RP_DESCR_MASK) >> 32;
if (!descriptor_type) { /* If descriptor type is invalid */
write_log(_T("MMU Configuration Exception: Root Pointer is invalid!\n"));
Exception(56); /* MMU Configuration Exception */
return true;
}
return false;
#if MMU030_REG_DBG_MSG /* enable or disable debugging output */
uae_u32 table_limit = (RP & RP_LIMIT_MASK) >> 48;
uae_u32 first_addr = (RP & RP_ADDR_MASK);
write_log(_T("\n"));
write_log(_T("ROOT POINTER: %08X%08X\n"), (uae_u32)(RP>>32)&0xFFFFFFFF, (uae_u32)(RP&0xFFFFFFFF));
write_log(_T("\n"));
write_log(_T("RP: descriptor type = %i "), descriptor_type);
switch (descriptor_type) {
case 0:
write_log(_T("(invalid descriptor)\n"));
break;
case 1:
write_log(_T("(early termination page descriptor)\n"));
break;
case 2:
write_log(_T("(valid 4 byte descriptor)\n"));
break;
case 3:
write_log(_T("(valid 8 byte descriptor)\n"));
break;
}
write_log(_T("RP: %s limit = %i\n"), (RP&RP_LOWER_MASK) ? _T("lower") : _T("upper"), table_limit);
write_log(_T("RP: first table address = %08X\n"), first_addr);
write_log(_T("\n"));
#endif
}
/* Descriptors */
#define DESCR_TYPE_MASK 0x00000003
#define DESCR_TYPE_INVALID 0 /* all tables */
#define DESCR_TYPE_EARLY_TERM 1 /* all but lowest level table */
#define DESCR_TYPE_PAGE 1 /* only lowest level table */
#define DESCR_TYPE_VALID4 2 /* all but lowest level table */
#define DESCR_TYPE_INDIRECT4 2 /* only lowest level table */
#define DESCR_TYPE_VALID8 3 /* all but lowest level table */
#define DESCR_TYPE_INDIRECT8 3 /* only lowest level table */
#define DESCR_TYPE_VALID_MASK 0x2 /* all but lowest level table */
#define DESCR_TYPE_INDIRECT_MASK 0x2 /* only lowest level table */
/* Short format (4 byte):
*
* ---- ---- ---- ---- ---- ---- ---- --xx
* descriptor type:
* 0 = invalid
* 1 = page descriptor (early termination)
* 2 = valid (4 byte)
* 3 = valid (8 byte)
*
*
* table descriptor:
* ---- ---- ---- ---- ---- ---- ---- -x--
* write protect
*
* ---- ---- ---- ---- ---- ---- ---- x---
* update
*
* xxxx xxxx xxxx xxxx xxxx xxxx xxxx ----
* table address
*
*
* (early termination) page descriptor:
* ---- ---- ---- ---- ---- ---- ---- -x--
* write protect
*
* ---- ---- ---- ---- ---- ---- ---- x---
* update
*
* ---- ---- ---- ---- ---- ---- ---x ----
* modified
*
* ---- ---- ---- ---- ---- ---- -x-- ----
* cache inhibit
*
* ---- ---- ---- ---- ---- ---- x-x- ----
* reserved (must be 0)
*
* xxxx xxxx xxxx xxxx xxxx xxxx ---- ----
* page address
*
*
* indirect descriptor:
* xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx--
* descriptor address
*
*/
#define DESCR_WP 0x00000004
#define DESCR_U 0x00000008
#define DESCR_M 0x00000010 /* only last level table */
#define DESCR_CI 0x00000040 /* only last level table */
#define DESCR_TD_ADDR_MASK 0xFFFFFFF0
#define DESCR_PD_ADDR_MASK 0xFFFFFF00
#define DESCR_ID_ADDR_MASK 0xFFFFFFFC
/* Long format (8 byte):
*
* ---- ---- ---- ---- ---- ---- ---- --xx | ---- ---- ---- ---- ---- ---- ---- ----
* descriptor type:
* 0 = invalid
* 1 = page descriptor (early termination)
* 2 = valid (4 byte)
* 3 = valid (8 byte)