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fpp.cpp
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fpp.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* MC68881/68882/68040/68060 FPU emulation
*
* Copyright 1996 Herman ten Brugge
* Modified 2005 Peter Keunecke
* 68040+ exceptions and more by Toni Wilen
*/
#define __USE_ISOC9X /* We might be able to pick up a NaN */
#include <math.h>
#include <float.h>
#include <fenv.h>
#include "sysconfig.h"
#include "sysdeps.h"
#ifdef _MSC_VER
#pragma fenv_access(on)
#endif
#include "options.h"
#include "memory.h"
#include "custom.h"
#include "events.h"
#include "newcpu.h"
#include "md-fpp.h"
#include "savestate.h"
#include "cpu_prefetch.h"
#include "cpummu.h"
#include "cpummu030.h"
#include "debug.h"
#ifdef WITH_SOFTFLOAT
#include "softfloatx80.h"
#endif
#ifdef X86_MSVC_ASSEMBLY
#define X86_MSVC_ASSEMBLY_FPU
#define NATIVE_FPUCW
#endif
#define DEBUG_FPP 0
#define EXCEPTION_FPP 1
STATIC_INLINE int isinrom (void)
{
return (munge24 (m68k_getpc ()) & 0xFFF80000) == 0xF80000 && !currprefs.mmu_model;
}
static uae_u32 xhex_pi[] ={0x2168c235, 0xc90fdaa2, 0x4000};
uae_u32 xhex_exp_1[] ={0xa2bb4a9a, 0xadf85458, 0x4000};
static uae_u32 xhex_l2_e[] ={0x5c17f0bc, 0xb8aa3b29, 0x3fff};
static uae_u32 xhex_ln_2[] ={0xd1cf79ac, 0xb17217f7, 0x3ffe};
uae_u32 xhex_ln_10[] ={0xaaa8ac17, 0x935d8ddd, 0x4000};
uae_u32 xhex_l10_2[] ={0xfbcff798, 0x9a209a84, 0x3ffd};
uae_u32 xhex_l10_e[] ={0x37287195, 0xde5bd8a9, 0x3ffd};
uae_u32 xhex_1e16[] ={0x04000000, 0x8e1bc9bf, 0x4034};
uae_u32 xhex_1e32[] ={0x2b70b59e, 0x9dc5ada8, 0x4069};
uae_u32 xhex_1e64[] ={0xffcfa6d5, 0xc2781f49, 0x40d3};
uae_u32 xhex_1e128[] ={0x80e98ce0, 0x93ba47c9, 0x41a8};
uae_u32 xhex_1e256[] ={0x9df9de8e, 0xaa7eebfb, 0x4351};
uae_u32 xhex_1e512[] ={0xa60e91c7, 0xe319a0ae, 0x46a3};
uae_u32 xhex_1e1024[]={0x81750c17, 0xc9767586, 0x4d48};
uae_u32 xhex_1e2048[]={0xc53d5de5, 0x9e8b3b5d, 0x5a92};
uae_u32 xhex_1e4096[]={0x8a20979b, 0xc4605202, 0x7525};
static uae_u32 xhex_inf[] ={0x00000000, 0x00000000, 0x7fff};
static uae_u32 xhex_nan[] ={0xffffffff, 0xffffffff, 0x7fff};
static uae_u32 xhex_snan[] ={0xffffffff, 0xbfffffff, 0x7fff};
#if USE_LONG_DOUBLE
static long double *fp_pi = (long double *)xhex_pi;
static long double *fp_exp_1 = (long double *)xhex_exp_1;
static long double *fp_l2_e = (long double *)xhex_l2_e;
static long double *fp_ln_2 = (long double *)xhex_ln_2;
static long double *fp_ln_10 = (long double *)xhex_ln_10;
static long double *fp_l10_2 = (long double *)xhex_l10_2;
static long double *fp_l10_e = (long double *)xhex_l10_e;
static long double *fp_1e16 = (long double *)xhex_1e16;
static long double *fp_1e32 = (long double *)xhex_1e32;
static long double *fp_1e64 = (long double *)xhex_1e64;
static long double *fp_1e128 = (long double *)xhex_1e128;
static long double *fp_1e256 = (long double *)xhex_1e256;
static long double *fp_1e512 = (long double *)xhex_1e512;
static long double *fp_1e1024 = (long double *)xhex_1e1024;
static long double *fp_1e2048 = (long double *)xhex_1e2048;
static long double *fp_1e4096 = (long double *)xhex_1e4096;
static long double *fp_inf = (long double *)xhex_inf;
static long double *fp_nan = (long double *)xhex_nan;
#else
static uae_u32 dhex_pi[] ={0x54442D18, 0x400921FB};
static uae_u32 dhex_exp_1[] ={0x8B145769, 0x4005BF0A};
static uae_u32 dhex_l2_e[] ={0x652B82FE, 0x3FF71547};
static uae_u32 dhex_ln_2[] ={0xFEFA39EF, 0x3FE62E42};
static uae_u32 dhex_ln_10[] ={0xBBB55516, 0x40026BB1};
static uae_u32 dhex_l10_2[] ={0x509F79FF, 0x3FD34413};
static uae_u32 dhex_l10_e[] ={0x1526E50E, 0x3FDBCB7B};
static uae_u32 dhex_1e16[] ={0x37E08000, 0x4341C379};
static uae_u32 dhex_1e32[] ={0xB5056E17, 0x4693B8B5};
static uae_u32 dhex_1e64[] ={0xE93FF9F5, 0x4D384F03};
static uae_u32 dhex_1e128[] ={0xF9301D32, 0x5A827748};
static uae_u32 dhex_1e256[] ={0x7F73BF3C, 0x75154FDD};
static uae_u32 dhex_inf[] ={0x00000000, 0x7ff00000};
static uae_u32 dhex_nan[] ={0xffffffff, 0x7fffffff};
static double *fp_pi = (double *)dhex_pi;
static double *fp_exp_1 = (double *)dhex_exp_1;
static double *fp_l2_e = (double *)dhex_l2_e;
static double *fp_ln_2 = (double *)dhex_ln_2;
static double *fp_ln_10 = (double *)dhex_ln_10;
static double *fp_l10_2 = (double *)dhex_l10_2;
static double *fp_l10_e = (double *)dhex_l10_e;
static double *fp_1e16 = (double *)dhex_1e16;
static double *fp_1e32 = (double *)dhex_1e32;
static double *fp_1e64 = (double *)dhex_1e64;
static double *fp_1e128 = (double *)dhex_1e128;
static double *fp_1e256 = (double *)dhex_1e256;
static double *fp_1e512 = (double *)dhex_inf;
static double *fp_1e1024 = (double *)dhex_inf;
static double *fp_1e2048 = (double *)dhex_inf;
static double *fp_1e4096 = (double *)dhex_inf;
static double *fp_inf = (double *)dhex_inf;
static double *fp_nan = (double *)dhex_nan;
#endif
double fp_1e8 = 1.0e8;
float fp_1e0 = 1, fp_1e1 = 10, fp_1e2 = 100, fp_1e4 = 10000;
static bool fpu_mmu_fixup;
#define FFLAG_Z 0x4000
#define FFLAG_N 0x0100
#define FFLAG_NAN 0x0400
#ifdef WITH_SOFTFLOAT
static floatx80 fxsizes[6] = { 0 };
static floatx80 fxzero;
static floatx80 fx_1e0, fx_1e1, fx_1e2, fx_1e4, fx_1e8;
struct float_status_t fxstatus;
#endif
static fptype fsizes[] = { -128.0, 127.0, -32768.0, 32767.0, -2147483648.0, 2147483647.0 };
#define FP_INEXACT (1 << 9)
#define FP_DIVBYZERO (1 << 10)
#define FP_UNDERFLOW (1 << 11)
#define FP_OVERFLOW (1 << 12)
#define FP_OPERAND (1 << 13)
#define FP_SNAN (1 << 14)
#define FP_BSUN (1 << 15)
STATIC_INLINE void MAKE_FPSR (fptype *fp)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat)
return;
#endif
int status = fetestexcept (FE_ALL_EXCEPT);
if (status) {
if (status & FE_INEXACT)
regs.fp_result_status |= FP_INEXACT;
if (status & FE_DIVBYZERO)
regs.fp_result_status |= FP_DIVBYZERO;
if (status & FE_UNDERFLOW)
regs.fp_result_status |= FP_UNDERFLOW;
if (status & FE_OVERFLOW)
regs.fp_result_status |= FP_OVERFLOW;
if (status & FE_INVALID)
regs.fp_result_status |= FP_OPERAND;
}
regs.fp_result.fp = *fp;
}
#ifdef WITH_SOFTFLOAT
STATIC_INLINE void MAKE_FPSR_SOFTFLOAT(floatx80 fx)
{
if (fxstatus.float_exception_flags & float_flag_invalid)
regs.fp_result_status |= FP_OPERAND;
if (fxstatus.float_exception_flags & float_flag_divbyzero)
regs.fp_result_status |= FP_DIVBYZERO;
if (fxstatus.float_exception_flags & float_flag_overflow)
regs.fp_result_status |= FP_OVERFLOW;
if (fxstatus.float_exception_flags & float_flag_underflow)
regs.fp_result_status |= FP_UNDERFLOW;
if (fxstatus.float_exception_flags & float_flag_inexact)
regs.fp_result_status |= FP_INEXACT;
regs.fp_result.fpx = fx;
}
#endif
STATIC_INLINE void CLEAR_STATUS (void)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat)
return;
#endif
feclearexcept (FE_ALL_EXCEPT);
}
#ifdef WITH_SOFTFLOAT
static void softfloat_set(floatx80 *fx, uae_u32 *f)
{
fx->exp = (uae_u16)f[2];
fx->fraction = ((uae_u64)f[1] << 32) | f[0];
}
static void softfloat_get(floatx80 *fx, uae_u32 *f)
{
f[2] = fx->exp;
f[1] = fx->fraction >> 32;
f[0] = (uae_u32)fx->fraction;
}
#endif
static void fpnan (fpdata *fpd)
{
fpd->fp = *fp_nan;
#ifdef WITH_SOFTFLOAT
softfloat_set(&fpd->fpx, xhex_nan);
#endif
}
static void fpclear (fpdata *fpd)
{
fpd->fp = 0;
#ifdef WITH_SOFTFLOAT
fpd->fpx = int32_to_floatx80(0);
#endif
}
static void fpset (fpdata *fpd, uae_s32 val)
{
fpd->fp = (fptype)val;
#ifdef WITH_SOFTFLOAT
fpd->fpx = int32_to_floatx80(val);
#endif
}
void to_single(fpdata *fpd, uae_u32 value)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
float32 f = value;
fpd->fpx = float32_to_floatx80(f, fxstatus);
} else
#endif
fpd->fp = to_single_x(value);
}
static uae_u32 from_single(fpdata *fpd)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
float32 f = floatx80_to_float32(fpd->fpx, fxstatus);
return f;
} else
#endif
return from_single_x(fpd->fp);
}
void to_double(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
float64 f = ((float64)wrd1 << 32) | wrd2;
fpd->fpx = float64_to_floatx80(f, fxstatus);
} else
#endif
fpd->fp = to_double_x(wrd1, wrd2);
}
static void from_double(fpdata *fpd, uae_u32 *wrd1, uae_u32 *wrd2)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
float64 f = floatx80_to_float64(fpd->fpx, fxstatus);
*wrd1 = f >> 32;
*wrd2 = (uae_u32)f;
return;
} else
#endif
return from_double_x(fpd->fp, wrd1, wrd2);
}
void to_exten(fpdata *fpd, uae_u32 wrd1, uae_u32 wrd2, uae_u32 wrd3)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
fpd->fpx.exp = wrd1 >> 16;
fpd->fpx.fraction = ((uae_u64)wrd2 << 32) | wrd3;
#if 0
if ((currprefs.fpu_model == 68881 || currprefs.fpu_model == 68882) || currprefs.fpu_no_unimplemented) {
// automatically fix denormals if 6888x or no implemented emulation
Bit64u Sig = extractFloatx80Frac(fpd->fpx);
Bit32s Exp = extractFloatx80Exp(fpd->fpx);
if (Exp == 0 && Sig != 0)
normalizeFloatx80Subnormal(Sig, &Exp, &Sig);
}
#endif
} else
#endif
to_exten_x(&fpd->fp, wrd1, wrd2, wrd3);
}
static void from_exten(fpdata *fpd, uae_u32 * wrd1, uae_u32 * wrd2, uae_u32 * wrd3)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
*wrd1 = fpd->fpx.exp << 16;
*wrd2 = fpd->fpx.fraction >> 32;
*wrd3 = (uae_u32)fpd->fpx.fraction;
} else
#endif
from_exten_x(fpd->fp, wrd1, wrd2, wrd3);
}
#if 0
static void normalize(uae_u32 *pwrd1, uae_u32 *pwrd2, uae_u32 *pwrd3)
{
uae_u32 wrd1 = *pwrd1;
uae_u32 wrd2 = *pwrd2;
uae_u32 wrd3 = *pwrd3;
int exp = (wrd1 >> 16) & 0x7fff;
// Normalize if unnormal.
if (exp != 0 && exp != 0x7fff && !(wrd2 & 0x80000000)) {
while (!(wrd2 & 0x80000000) && (wrd2 || wrd3)) {
wrd2 <<= 1;
if (wrd3 & 0x80000000)
wrd2 |= 1;
wrd3 <<= 1;
exp--;
}
if (exp < 0)
exp = 0;
if (!wrd2 && !wrd3)
exp = 0;
*pwrd1 = (wrd1 & 0x80000000) | (exp << 16);
*pwrd2 = wrd2;
*pwrd3 = wrd3;
}
}
#endif
static bool fpu_get_constant_fp(fpdata *fp, int cr)
{
fptype f;
switch (cr & 0x7f)
{
case 0x00:
f = *fp_pi;
break;
case 0x0b:
f = *fp_l10_2;
break;
case 0x0c:
f = *fp_exp_1;
break;
case 0x0d:
f = *fp_l2_e;
break;
case 0x0e:
f = *fp_l10_e;
break;
case 0x0f:
f = 0.0;
break;
case 0x30:
f = *fp_ln_2;
break;
case 0x31:
f = *fp_ln_10;
break;
case 0x32:
f = (fptype)fp_1e0;
break;
case 0x33:
f = (fptype)fp_1e1;
break;
case 0x34:
f = (fptype)fp_1e2;
break;
case 0x35:
f = (fptype)fp_1e4;
break;
case 0x36:
f = (fptype)fp_1e8;
break;
case 0x37:
f = *fp_1e16;
break;
case 0x38:
f = *fp_1e32;
break;
case 0x39:
f = *fp_1e64;
break;
case 0x3a:
f = *fp_1e128;
break;
case 0x3b:
f = *fp_1e256;
break;
case 0x3c:
f = *fp_1e512;
break;
case 0x3d:
f = *fp_1e1024;
break;
case 0x3e:
f = *fp_1e2048;
break;
case 0x3f:
f = *fp_1e4096;
break;
default:
return false;
}
fp->fp = f;
return true;
}
#ifdef WITH_SOFTFLOAT
static bool fpu_get_constant_softfloat(fpdata *fp, int cr)
{
uae_u32 *f = NULL;
floatx80 fx;
switch (cr & 0x7f)
{
case 0x00:
f = xhex_pi;
break;
case 0x0b:
f = xhex_l10_2;
break;
case 0x0c:
f = xhex_exp_1;
break;
case 0x0d:
f = xhex_l2_e;
break;
case 0x0e:
f = xhex_l10_e;
break;
case 0x0f:
fx = fxzero;
break;
case 0x30:
f = xhex_ln_2;
break;
case 0x31:
f = xhex_ln_10;
break;
case 0x32:
fx = fx_1e0;
break;
case 0x33:
fx = fx_1e1;
break;
case 0x34:
fx = fx_1e2;
break;
case 0x35:
fx = fx_1e4;
break;
case 0x36:
fx = fx_1e8;
break;
case 0x37:
f = xhex_1e16;
break;
case 0x38:
f = xhex_1e32;
break;
case 0x39:
f = xhex_1e64;
break;
case 0x3a:
f = xhex_1e128;
break;
case 0x3b:
f = xhex_1e256;
break;
case 0x3c:
f = xhex_1e512;
break;
case 0x3d:
f = xhex_1e1024;
break;
case 0x3e:
f = xhex_1e2048;
break;
case 0x3f:
f = xhex_1e4096;
break;
default:
return false;
}
if (f)
softfloat_set(&fp->fpx, f);
else
fp->fpx = fx;
return true;
}
#endif
bool fpu_get_constant(fpdata *fp, int cr)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat)
return fpu_get_constant_softfloat(fp, cr);
#endif
return fpu_get_constant_fp(fp, cr);
}
static void native_set_fpucw (uae_u32 m68k_cw)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
switch((m68k_cw >> 6) & 3)
{
case 0: // X
default: // undefined
fxstatus.float_rounding_precision = 80;
break;
case 1: // S
fxstatus.float_rounding_precision = 32;
break;
case 2: // D
fxstatus.float_rounding_precision = 64;
break;
}
switch((m68k_cw >> 4) & 3)
{
case 0: // to neareset
fxstatus.float_rounding_precision = float_round_nearest_even;
break;
case 1: // to zero
fxstatus.float_rounding_mode = float_round_to_zero;
break;
case 2: // to minus
fxstatus.float_rounding_mode = float_round_down;
break;
case 3: // to plus
fxstatus.float_rounding_mode = float_round_up;
break;
}
} else
#endif
{
#ifdef NATIVE_FPUCW
#ifdef _WIN32
static int ex = 0;
// RN, RZ, RM, RP
static const unsigned int fp87_round[4] = { _RC_NEAR, _RC_CHOP, _RC_DOWN, _RC_UP };
// Extend X, Single S, Double D, Undefined
static const unsigned int fp87_prec[4] = { _PC_64 , _PC_24 , _PC_53, 0 };
#ifdef WIN64
_controlfp (ex | fp87_round[(m68k_cw >> 4) & 3], _MCW_RC);
#else
_control87 (ex | fp87_round[(m68k_cw >> 4) & 3] | fp87_prec[(m68k_cw >> 6) & 3], _MCW_RC | _MCW_PC);
#endif
#else
static const uae_u16 x87_cw_tab[] = {
0x137f, 0x1f7f, 0x177f, 0x1b7f, /* Extended */
0x107f, 0x1c7f, 0x147f, 0x187f, /* Single */
0x127f, 0x1e7f, 0x167f, 0x1a7f, /* Double */
0x137f, 0x1f7f, 0x177f, 0x1b7f /* undefined */
};
#if USE_X86_FPUCW
uae_u16 x87_cw = x87_cw_tab[(m68k_cw >> 4) & 0xf];
#if defined(X86_MSVC_ASSEMBLY)
__asm {
fldcw word ptr x87_cw
}
#elif defined(X86_ASSEMBLY)
__asm__ ("fldcw %0" : : "m" (*&x87_cw));
#endif
#endif
#endif
#endif
}
}
#if defined(uae_s64) /* Close enough for government work? */
typedef uae_s64 tointtype;
#else
typedef uae_s32 tointtype;
#endif
static void fpu_format_error (void)
{
uaecptr newpc;
regs.t0 = regs.t1 = 0;
MakeSR ();
if (!regs.s) {
regs.usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.isp;
}
regs.s = 1;
m68k_areg (regs, 7) -= 2;
x_put_long (m68k_areg (regs, 7), 0x0000 + 14 * 4);
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), m68k_getpc ());
m68k_areg (regs, 7) -= 2;
x_put_long (m68k_areg (regs, 7), regs.sr);
newpc = x_get_long (regs.vbr + 14 * 4);
m68k_setpc (newpc);
#ifdef JIT
set_special (SPCFLAG_END_COMPILE);
#endif
regs.fp_exception = true;
}
#define FPU_EXP_UNIMP_INS 0
#define FPU_EXP_DISABLED 1
#define FPU_EXP_UNIMP_DATATYPE_PRE 2
#define FPU_EXP_UNIMP_DATATYPE_POST 3
#define FPU_EXP_UNIMP_DATATYPE_PACKED_PRE 4
#define FPU_EXP_UNIMP_DATATYPE_PACKED_POST 5
#define FPU_EXP_UNIMP_EA 6
static void fpu_arithmetic_exception (uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc, int type, fpdata *src, int reg)
{
// TODO
}
static void fpu_op_unimp (uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc, int type, fpdata *src, int reg, int size)
{
/* 68040 unimplemented/68060 FPU disabled exception.
* Line F exception with different stack frame.. */
int vector = 11;
uaecptr newpc = m68k_getpc (); // next instruction
static int warned = 20;
regs.t0 = regs.t1 = 0;
MakeSR ();
if (!regs.s) {
regs.usp = m68k_areg (regs, 7);
if (currprefs.cpu_model == 68060) {
m68k_areg (regs, 7) = regs.isp;
} else if (currprefs.cpu_model >= 68020) {
m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp;
} else {
m68k_areg (regs, 7) = regs.isp;
}
regs.s = 1;
if (currprefs.mmu_model)
mmu_set_super (regs.s != 0);
}
regs.fpu_exp_state = 1;
if (currprefs.cpu_model == 68060) {
regs.fpiar = oldpc;
regs.exp_extra = extra;
regs.exp_opcode = opcode;
regs.exp_size = size;
if (src)
regs.exp_src1 = *src;
regs.exp_type = type;
if (type == FPU_EXP_DISABLED) {
// current PC
newpc = oldpc;
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), oldpc);
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), ea);
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), 0x4000 + vector * 4);
} else if (type == FPU_EXP_UNIMP_INS) {
// PC = next instruction
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), ea);
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
} else if (type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE || type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST || type == FPU_EXP_UNIMP_DATATYPE_PRE || type == FPU_EXP_UNIMP_DATATYPE_POST) {
regs.fpu_exp_state = 2; // EXC frame
// PC = next instruction
vector = 55;
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), ea);
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
} else { // FPU_EXP_UNIMP_EA
// current PC
newpc = oldpc;
vector = 60;
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), 0x0000 + vector * 4);
}
} else if (currprefs.cpu_model == 68040) {
regs.fpiar = oldpc;
regs.exp_extra = extra;
regs.exp_opcode = opcode;
regs.exp_size = size;
if (src)
regs.exp_src1 = *src;
regs.exp_type = type;
if (reg >= 0)
regs.exp_src2 = regs.fp[reg];
else
fpclear (®s.exp_src2);
if (type == FPU_EXP_UNIMP_INS || type == FPU_EXP_DISABLED) {
// PC = next instruction
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), ea);
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
} else if (type == FPU_EXP_UNIMP_DATATYPE_PACKED_PRE || type == FPU_EXP_UNIMP_DATATYPE_PACKED_POST || type == FPU_EXP_UNIMP_DATATYPE_PRE || type == FPU_EXP_UNIMP_DATATYPE_POST) {
// PC = next instruction
vector = 55;
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), ea);
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), 0x2000 + vector * 4);
regs.fpu_exp_state = 2; // BUSY frame
}
}
oldpc = newpc;
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), newpc);
m68k_areg (regs, 7) -= 2;
x_put_word (m68k_areg (regs, 7), regs.sr);
newpc = x_get_long (regs.vbr + vector * 4);
if (warned > 0) {
write_log (_T("FPU EXCEPTION %d OP=%04X-%04X EA=%08X PC=%08X -> %08X\n"), type, opcode, extra, ea, oldpc, newpc);
#if EXCEPTION_FPP == 0
warned--;
#endif
}
regs.fp_exception = true;
m68k_setpc (newpc);
#ifdef JIT
set_special (SPCFLAG_END_COMPILE);
#endif
}
static void fpu_op_illg2 (uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc)
{
if ((currprefs.cpu_model == 68060 && (currprefs.fpu_model == 0 || (regs.pcr & 2)))
|| (currprefs.cpu_model == 68040 && currprefs.fpu_model == 0)) {
fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_DISABLED, NULL, -1, -1);
return;
}
regs.fp_exception = true;
m68k_setpc (oldpc);
op_illg (opcode);
}
static void fpu_op_illg (uae_u16 opcode, uae_u16 extra, uaecptr oldpc)
{
fpu_op_illg2 (opcode, extra, 0, oldpc);
}
static void fpu_noinst (uae_u16 opcode, uaecptr pc)
{
#if EXCEPTION_FPP
write_log (_T("Unknown FPU instruction %04X %08X\n"), opcode, pc);
#endif
regs.fp_exception = true;
m68k_setpc (pc);
op_illg (opcode);
}
static bool fault_if_no_fpu (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc)
{
if ((regs.pcr & 2) || currprefs.fpu_model <= 0) {
#if EXCEPTION_FPP
write_log (_T("no FPU: %04X-%04X PC=%08X\n"), opcode, extra, oldpc);
#endif
fpu_op_illg2 (opcode, extra, ea, oldpc);
return true;
}
return false;
}
static bool fault_if_unimplemented_680x0 (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, fpdata *src, int reg)
{
if (fault_if_no_fpu (opcode, extra, ea, oldpc))
return true;
if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
if ((extra & (0x8000 | 0x2000)) != 0)
return false;
if ((extra & 0xfc00) == 0x5c00) {
// FMOVECR
fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, src, reg, -1);
return true;
}
uae_u16 v = extra & 0x7f;
switch (v)
{
case 0x01: /* FINT */
case 0x03: /* FINTRZ */
// Unimplemented only in 68040.
if (currprefs.cpu_model == 68040) {
fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, src, reg, -1);
return true;
}
return false;
case 0x02: /* FSINH */
case 0x06: /* FLOGNP1 */
case 0x08: /* FETOXM1 */
case 0x09: /* FTANH */
case 0x0a: /* FATAN */
case 0x0c: /* FASIN */
case 0x0d: /* FATANH */
case 0x0e: /* FSIN */
case 0x0f: /* FTAN */
case 0x10: /* FETOX */
case 0x11: /* FTWOTOX */
case 0x12: /* FTENTOX */
case 0x14: /* FLOGN */
case 0x15: /* FLOG10 */
case 0x16: /* FLOG2 */
case 0x19: /* FCOSH */
case 0x1c: /* FACOS */
case 0x1d: /* FCOS */
case 0x1e: /* FGETEXP */
case 0x1f: /* FGETMAN */
case 0x30: /* FSINCOS */
case 0x31: /* FSINCOS */
case 0x32: /* FSINCOS */
case 0x33: /* FSINCOS */
case 0x34: /* FSINCOS */
case 0x35: /* FSINCOS */
case 0x36: /* FSINCOS */
case 0x37: /* FSINCOS */
case 0x21: /* FMOD */
case 0x25: /* FREM */
case 0x26: /* FSCALE */
fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, src, reg, -1);
return true;
}
}
return false;
}
static bool fault_if_unimplemented_6888x (uae_u16 opcode, uae_u16 extra, uaecptr oldpc)
{
if ((currprefs.fpu_model == 68881 || currprefs.fpu_model == 68882) && currprefs.fpu_no_unimplemented) {
uae_u16 v = extra & 0x7f;
/* 68040/68060 only variants. 6888x = F-line exception. */
switch (v)
{
case 0x62: /* FSADD */
case 0x66: /* FDADD */
case 0x68: /* FSSUB */
case 0x6c: /* FDSUB */
case 0x5a: /* FSNEG */
case 0x5e: /* FDNEG */
case 0x58: /* FSABS */
case 0x5c: /* FDABS */
case 0x63: /* FSMUL */
case 0x67: /* FDMUL */
case 0x41: /* FSSQRT */
case 0x45: /* FDSQRT */
fpu_noinst (opcode, oldpc);
return true;
}
}
return false;
}
static bool fault_if_60 (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, int type)
{
if (currprefs.cpu_model == 68060 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
fpu_op_unimp (opcode, extra, ea, oldpc, type, NULL, -1, -1);
return true;
}
return false;
}
static bool fault_if_4060 (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc, int type, fpdata *src, uae_u32 *pack)
{
if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
if (pack) {
regs.exp_pack[0] = pack[0];
regs.exp_pack[1] = pack[1];
regs.exp_pack[2] = pack[2];
}
fpu_op_unimp (opcode, extra, ea, oldpc, type, src, -1, -1);
return true;
}
return false;
}
static bool fault_if_no_fpu_u (uae_u16 opcode, uae_u16 extra, uaecptr ea, uaecptr oldpc)
{
if (fault_if_no_fpu (opcode, extra, ea, oldpc))
return true;
if (currprefs.cpu_model == 68060 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
// 68060 FTRAP, FDBcc or FScc are not implemented.
fpu_op_unimp (opcode, extra, ea, oldpc, FPU_EXP_UNIMP_INS, NULL, -1, -1);
return true;
}
return false;
}
static bool fault_if_no_6888x (uae_u16 opcode, uae_u16 extra, uaecptr oldpc)
{
if (currprefs.cpu_model < 68040 && currprefs.fpu_model <= 0) {
#if EXCEPTION_FPP
write_log (_T("6888x no FPU: %04X-%04X PC=%08X\n"), opcode, extra, oldpc);
#endif
m68k_setpc (oldpc);
regs.fp_exception = true;
op_illg (opcode);
return true;
}
return false;
}
static int get_fpu_version (void)
{
int v = 0;
switch (currprefs.fpu_model)
{
case 68881:
v = 0x1f;
break;
case 68882:
v = 0x20;
break;
case 68040:
if (currprefs.fpu_revision == 0x40)
v = 0x40;
else
v = 0x41;
break;
}
return v;
}
static void fpu_null (void)
{
regs.fpu_state = 0;
regs.fpu_exp_state = 0;
regs.fpcr = 0;
regs.fpsr = 0;
regs.fpiar = 0;
fpclear (®s.fp_result);
for (int i = 0; i < 8; i++)
fpnan (®s.fp[i]);
}
#define fp_round_to_minus_infinity(x) floor(x)
#define fp_round_to_plus_infinity(x) ceil(x)
#define fp_round_to_zero(x) ((x) >= 0.0 ? floor(x) : ceil(x))
#define fp_round_to_nearest(x) ((x) >= 0.0 ? (int)((x) + 0.5) : (int)((x) - 0.5))
static tointtype toint(fpdata *src, int size)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat) {
if (floatx80_compare(src->fpx, fxsizes[size * 2 + 0], fxstatus) == float_relation_greater)
return floatx80_to_int32(fxsizes[size * 2 + 0], fxstatus);
if (floatx80_compare(src->fpx, fxsizes[size * 2 + 1], fxstatus) == float_relation_less)
return floatx80_to_int32(fxsizes[size * 2 + 1], fxstatus);
return floatx80_to_int32(src->fpx, fxstatus);
} else
#endif
{
fptype fp = src->fp;
if (fp < fsizes[size * 2 + 0])
fp = fsizes[size * 2 + 0];
if (fp > fsizes[size * 2 + 1])
fp = fsizes[size * 2 + 1];
#if defined(X86_MSVC_ASSEMBLY_FPU)
{
fptype tmp_fp;
__asm {
fld LDPTR fp
frndint
fstp LDPTR tmp_fp
}
return (tointtype)tmp_fp;
}
#else /* no X86_MSVC */
{
int result = (int)fp;
switch (regs.fpcr & 0x30)
{
case FPCR_ROUND_ZERO:
result = (int)fp_round_to_zero (fp);
break;
case FPCR_ROUND_MINF:
result = (int)fp_round_to_minus_infinity (fp);
break;
case FPCR_ROUND_NEAR:
result = fp_round_to_nearest (fp);
break;
case FPCR_ROUND_PINF:
result = (int)fp_round_to_plus_infinity (fp);
break;
}
return result;
}
#endif
}
}
static bool fp_is_snan(fpdata *fpd)
{
#ifdef WITH_SOFTFLOAT
if (currprefs.fpu_softfloat)
return floatx80_is_signaling_nan(fpd->fpx) != 0;