From f2b929affd8a9db8db69fb030b074a8333b70021 Mon Sep 17 00:00:00 2001 From: David Garske Date: Tue, 1 Oct 2024 07:06:02 -0700 Subject: [PATCH] QSPI Power control (active low). --- config/examples/nrf5340.config | 3 +++ hal/spi/spi_drv_nrf5340.c | 7 +++++++ hal/spi/spi_drv_nrf5340.h | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/config/examples/nrf5340.config b/config/examples/nrf5340.config index c92b5bc84..707fe3386 100644 --- a/config/examples/nrf5340.config +++ b/config/examples/nrf5340.config @@ -48,5 +48,8 @@ USE_GCC=1 # Use larger block size for swapping sectors CFLAGS_EXTRA+=-DFLASHBUFFER_SIZE=0x1000 +# Enable optional power control pin (active low) P1.00 +CFLAGS_EXTRA+=-DQSPI_PWR_CTRL_PORT=1 -DQSPI_PWR_CTRL_PIN=0 + CFLAGS_EXTRA+=-DDEBUG_FLASH CFLAGS_EXTRA+=-DDEBUG_QSPI=1 diff --git a/hal/spi/spi_drv_nrf5340.c b/hal/spi/spi_drv_nrf5340.c index 7789997a8..dcbbe3aa1 100644 --- a/hal/spi/spi_drv_nrf5340.c +++ b/hal/spi/spi_drv_nrf5340.c @@ -195,6 +195,10 @@ void spi_init(int polarity, int phase) GPIO_PIN_CNF(QSPI_IO1_PORT, QSPI_IO1_PIN) = (GPIO_CNF_IN_DIS | GPIO_CNF_HIGH_DRIVE); GPIO_PIN_CNF(QSPI_IO2_PORT, QSPI_IO2_PIN) = (GPIO_CNF_IN_DIS | GPIO_CNF_HIGH_DRIVE); GPIO_PIN_CNF(QSPI_IO3_PORT, QSPI_IO3_PIN) = (GPIO_CNF_IN_DIS | GPIO_CNF_HIGH_DRIVE); +#if defined(QSPI_PWR_CTRL_PORT) && defined(QSPI_PWR_CTRL_PIN) + GPIO_PIN_CNF(QSPI_PWR_CTRL_PORT, QSPI_PWR_CTRL_PIN) = (GPIO_CNF_IN_DIS | GPIO_CNF_HIGH_DRIVE); + GPIO_OUTCLR(QSPI_PWR_CTRL_PORT) = (1 << QSPI_PWR_CTRL_PIN); /* active low */ +#endif reg = QSPI_IFCONFIG0; reg &= ~(QSPI_IFCONFIG0_READOC_MASK | QSPI_IFCONFIG0_WRITEOC_MASK); @@ -278,6 +282,9 @@ void spi_release(void) /* Disable QSPI Clock to save power */ QSPI_ENABLE = 0; CLOCK_HFCLK192MSTOP = 1; + #if defined(QSPI_PWR_CTRL_PORT) && defined(QSPI_PWR_CTRL_PIN) + GPIO_OUTSET(QSPI_PWR_CTRL_PORT) = (1 << QSPI_PWR_CTRL_PIN); + #endif } } diff --git a/hal/spi/spi_drv_nrf5340.h b/hal/spi/spi_drv_nrf5340.h index 961dfe50c..01d796784 100644 --- a/hal/spi/spi_drv_nrf5340.h +++ b/hal/spi/spi_drv_nrf5340.h @@ -83,6 +83,10 @@ #define QSPI_CLOCK_MHZ 48000000UL #endif +/* Optional power pin for QSPI enable */ +//#define QSPI_PWR_CTRL_PORT 1 +//#define QSPI_PWR_CTRL_PIN 0 + /* MX25R6435F */ #define QSPI_NO_SR2