diff --git a/.gitignore b/.gitignore index 51c7bde6..ef0d3c46 100644 --- a/.gitignore +++ b/.gitignore @@ -13,3 +13,4 @@ autom4te.cache Makefile /cov *.pyc +/examples/*/*.json diff --git a/.travis.yml b/.travis.yml index f3be7fa0..08f2c8dd 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,29 +7,12 @@ before_install: - wget https://github.com/SimonKagstrom/kcov/archive/master.tar.gz && tar xzf master.tar.gz - (mkdir kcov-master/build && cd kcov-master/build && cmake .. && make && make install DESTDIR=../tmp) script: - - ./configure --host=arm-none-eabi - - cargo build --target=$TARGET --verbose --features mcu_$PLATFORM - - ./support/build-examples.sh -after_script: - - cargo test --lib --verbose - - (cd ./ioreg; cargo build --verbose; cargo test --verbose) - - (kcov-master/tmp/usr/local/bin/kcov --coveralls-id=$TRAVIS_JOB_ID --exclude-pattern=/.cargo,ioreg/tests target/kcov ioreg/target/debug/test-*) - - (cd ./platformtree; cargo build --verbose; cargo test --verbose) - - (cd ./macro_platformtree; cargo build --verbose; cargo test --verbose) - - (cd ./macro_zinc; cargo test --verbose) - - (kcov-master/tmp/usr/local/bin/kcov --coveralls-id=$TRAVIS_JOB_ID --exclude-pattern=/.cargo target/kcov target/debug/zinc-*) - + - ./support/build-jenkins.sh env: matrix: + - PLATFORM=native + - PLATFORM=lpc11xx - PLATFORM=lpc17xx - TARGET=thumbv7m-none-eabi - EXAMPLES="blink blink_pt uart dht22 empty" - PLATFORM=k20 - TARGET=thumbv7em-none-eabi - EXAMPLES="blink_k20 blink_k20_isr empty" - PLATFORM=stm32f4 - TARGET=thumbv7em-none-eabi - EXAMPLES="blink_stm32f4 empty" - PLATFORM=stm32l1 - TARGET=thumbv7m-none-eabi - EXAMPLES="blink_stm32l1 bluenrg_stm32l1 usart_stm32l1 empty" diff --git a/Cargo.toml b/Cargo.toml index dd51e29b..c1935ad1 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -9,9 +9,13 @@ name = "zinc" crate-type = ["lib"] [features] +test = ["volatile_cell/replayer"] + +cpu_cortex-m0 = [] cpu_cortex-m3 = [] cpu_cortex-m4 = [] +mcu_lpc11xx = ["cpu_cortex-m0"] mcu_lpc17xx = ["cpu_cortex-m3"] mcu_stm32f4 = ["cpu_cortex-m4"] mcu_stm32l1 = ["cpu_cortex-m3"] @@ -19,6 +23,9 @@ mcu_k20 = ["cpu_cortex-m4"] mcu_tiva_c = ["cpu_cortex-m4"] multitasking = ["cpu_cortex-m4"] +[target.thumbv6-none-eabi.dependencies.core] +git = "https://github.com/hackndev/rust-libcore" + [target.thumbv7m-none-eabi.dependencies.core] git = "https://github.com/hackndev/rust-libcore" @@ -32,9 +39,12 @@ path = "./ioreg" path = "./volatile_cell" [dependencies.rlibc] -git = "https://github.com/mcoffin/rlibc" +git = "https://github.com/hackndev/rlibc" branch = "zinc" +[dev-dependencies] +expectest = "*" + [dev-dependencies.platformtree] path = "./platformtree" @@ -43,63 +53,3 @@ path = "./macro_platformtree" [dev-dependencies.macro_zinc] path = "./macro_zinc" - -[[example]] -name = "nothing" -path = "examples/nothing.rs" - -[[example]] -name = "blink" -path = "examples/blink.rs" - -[[example]] -name = "blink_k20" -path = "examples/blink_k20.rs" - -[[example]] -name = "blink_k20_isr" -path = "examples/blink_k20_isr.rs" - -[[example]] -name = "blink_pt" -path = "examples/blink_pt.rs" - -[[example]] -name = "blink_stm32f4" -path = "examples/blink_stm32f4.rs" - -[[example]] -name = "blink_stm32l1" -path = "examples/blink_stm32l1.rs" - -[[example]] -name = "blink_tiva_c" -path = "examples/blink_tiva_c.rs" - -[[example]] -name = "bluenrg_stm32l1" -path = "examples/bluenrg_stm32l1.rs" - -[[example]] -name = "dht22" -path = "examples/dht22.rs" - -[[example]] -name = "empty" -path = "examples/empty.rs" - -[[example]] -name = "lcd_tiva_c" -path = "examples/lcd_tiva_c.rs" - -[[example]] -name = "uart" -path = "examples/uart.rs" - -[[example]] -name = "uart_tiva_c" -path = "examples/uart_tiva_c.rs" - -[[example]] -name = "usart_stm32l1" -path = "examples/usart_stm32l1.rs" diff --git a/build.rs b/build.rs index 1f711ac7..9e2666bc 100644 --- a/build.rs +++ b/build.rs @@ -15,12 +15,17 @@ fn get_platform() -> Option { } fn copy_linker_scripts, Q: AsRef>(target: P, out_path: Q) -> io::Result<()> { + let path_prefix = if env::var("CARGO_MANIFEST_DIR").unwrap().find("/examples/").is_none() { + Path::new(".") + } else { + Path::new("./../..") + }; // Try copying the linker scripts let target_dir = Path::new("src/hal").join(target); let out_dir: &Path = out_path.as_ref(); - try!(fs::copy("src/hal/layout_common.ld", out_dir.join("layout_common.ld"))); - try!(fs::copy(target_dir.join("iomem.ld"), out_dir.join("iomem.ld"))); - try!(fs::copy(target_dir.join("layout.ld"), out_dir.join("layout.ld"))); + try!(fs::copy(path_prefix.join("src/hal/layout_common.ld"), out_dir.join("layout_common.ld"))); + try!(fs::copy(path_prefix.join(target_dir.join("iomem.ld")), out_dir.join("iomem.ld"))); + try!(fs::copy(path_prefix.join(target_dir.join("layout.ld")), out_dir.join("layout.ld"))); Ok(()) } diff --git a/configure b/configure index d725d889..8784ce64 100755 --- a/configure +++ b/configure @@ -2146,6 +2146,9 @@ CC=$GCC case $PLATFORM in +lpc11xx) + platform_target=thumbv6-none-eabi + ;; lpc17xx | stm32l1) platform_target=thumbv7m-none-eabi ;; diff --git a/configure.ac b/configure.ac index 4eb57e2f..8c884c17 100644 --- a/configure.ac +++ b/configure.ac @@ -13,6 +13,9 @@ AC_SUBST(CC, $GCC) AC_ARG_VAR(PLATFORM, [Platform for which to build]) case $PLATFORM in +lpc11xx) + platform_target=thumbv6-none-eabi + ;; lpc17xx | stm32l1) platform_target=thumbv7m-none-eabi ;; diff --git a/examples/blink_k20/Cargo.toml b/examples/blink_k20/Cargo.toml new file mode 100644 index 00000000..4f6aa2cb --- /dev/null +++ b/examples/blink_k20/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "blink" +version = "0.0.1" + +[features] +default = ["mcu_k20"] +mcu_k20 = ["zinc/mcu_k20"] + +[dependencies] +zinc = { path = "../.." } +macro_zinc = { path = "../../macro_zinc" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink_k20.rs b/examples/blink_k20/src/main.rs similarity index 99% rename from examples/blink_k20.rs rename to examples/blink_k20/src/main.rs index 7e5cbb38..e5e120ee 100644 --- a/examples/blink_k20.rs +++ b/examples/blink_k20/src/main.rs @@ -6,9 +6,10 @@ extern crate core; extern crate zinc; use core::option::Option::Some; + +use zinc::hal::cortex_m4::systick; use zinc::hal::k20::{pin, watchdog}; use zinc::hal::pin::Gpio; -use zinc::hal::cortex_m4::systick; /// Wait the given number of SysTick ticks pub fn wait(ticks: u32) { diff --git a/examples/blink_k20_isr/Cargo.toml b/examples/blink_k20_isr/Cargo.toml new file mode 100644 index 00000000..bf2029d3 --- /dev/null +++ b/examples/blink_k20_isr/Cargo.toml @@ -0,0 +1,11 @@ +[package] +name = "blink_k20_isr" +version = "0.0.1" + +[features] +default = ["mcu_k20"] +mcu_k20 = ["zinc/mcu_k20"] + +[dependencies] +zinc = { path = "../.." } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink_k20_isr.rs b/examples/blink_k20_isr/src/main.rs similarity index 100% rename from examples/blink_k20_isr.rs rename to examples/blink_k20_isr/src/main.rs diff --git a/examples/blink_lpc17xx/Cargo.toml b/examples/blink_lpc17xx/Cargo.toml new file mode 100644 index 00000000..7f324ecb --- /dev/null +++ b/examples/blink_lpc17xx/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "blink" +version = "0.0.1" + +[features] +default = ["mcu_lpc17xx"] +mcu_lpc17xx = ["zinc/mcu_lpc17xx"] + +[dependencies] +zinc = { path = "../.." } +macro_zinc = { path = "../../macro_zinc" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink.rs b/examples/blink_lpc17xx/src/main.rs similarity index 99% rename from examples/blink.rs rename to examples/blink_lpc17xx/src/main.rs index a8a3110e..710d470a 100644 --- a/examples/blink.rs +++ b/examples/blink_lpc17xx/src/main.rs @@ -5,11 +5,12 @@ extern crate core; extern crate zinc; -use zinc::hal::timer::Timer; +use core::option::Option::Some; + use zinc::hal::lpc17xx::{pin, timer}; -use zinc::hal::pin::GpioDirection; use zinc::hal::pin::Gpio; -use core::option::Option::Some; +use zinc::hal::pin::GpioDirection; +use zinc::hal::timer::Timer; #[zinc_main] pub fn main() { diff --git a/examples/blink_pt/Cargo.toml b/examples/blink_pt/Cargo.toml new file mode 100644 index 00000000..c6ecc140 --- /dev/null +++ b/examples/blink_pt/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "blink" +version = "0.0.1" + +[features] +default = ["mcu_lpc17xx"] +mcu_lpc17xx = ["zinc/mcu_lpc17xx"] + +[dependencies] +zinc = { path = "../.." } +macro_platformtree = { path = "../../macro_platformtree" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink_pt.rs b/examples/blink_pt/src/main.rs similarity index 100% rename from examples/blink_pt.rs rename to examples/blink_pt/src/main.rs diff --git a/examples/blink_stm32f4/Cargo.toml b/examples/blink_stm32f4/Cargo.toml new file mode 100644 index 00000000..5202af1d --- /dev/null +++ b/examples/blink_stm32f4/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "blink_stm32f4" +version = "0.0.1" + +[features] +default = ["mcu_stm32f4"] +mcu_stm32f4 = ["zinc/mcu_stm32f4"] + +[dependencies] +zinc = { path = "../.." } +macro_zinc = { path = "../../macro_zinc" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink_stm32f4.rs b/examples/blink_stm32f4/src/main.rs similarity index 100% rename from examples/blink_stm32f4.rs rename to examples/blink_stm32f4/src/main.rs diff --git a/examples/blink_stm32l1/Cargo.toml b/examples/blink_stm32l1/Cargo.toml new file mode 100644 index 00000000..ac60bf4b --- /dev/null +++ b/examples/blink_stm32l1/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "blink_stm32l1" +version = "0.0.1" + +[features] +default = ["mcu_stm32l1"] +mcu_stm32l1 = ["zinc/mcu_stm32l1"] + +[dependencies] +zinc = { path = "../.." } +macro_zinc = { path = "../../macro_zinc" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink_stm32l1.rs b/examples/blink_stm32l1/src/main.rs similarity index 100% rename from examples/blink_stm32l1.rs rename to examples/blink_stm32l1/src/main.rs diff --git a/examples/blink_tiva_c/Cargo.toml b/examples/blink_tiva_c/Cargo.toml new file mode 100644 index 00000000..4af5654c --- /dev/null +++ b/examples/blink_tiva_c/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "blink_tiva_c" +version = "0.0.1" + +[features] +default = ["mcu_tiva_c"] +mcu_tiva_c = ["zinc/mcu_tiva_c"] + +[dependencies] +zinc = { path = "../.." } +macro_platformtree = { path = "../../macro_platformtree" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/blink_tiva_c.rs b/examples/blink_tiva_c/src/main.rs similarity index 100% rename from examples/blink_tiva_c.rs rename to examples/blink_tiva_c/src/main.rs diff --git a/examples/bluenrg_stm32l1/Cargo.toml b/examples/bluenrg_stm32l1/Cargo.toml new file mode 100644 index 00000000..a6c16f3d --- /dev/null +++ b/examples/bluenrg_stm32l1/Cargo.toml @@ -0,0 +1,11 @@ +[package] +name = "bluenrg_stm32l1" +version = "0.0.1" + +[features] +default = ["mcu_stm32l1"] +mcu_stm32l1 = ["zinc/mcu_stm32l1"] + +[dependencies] +zinc = { path = "../.." } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/bluenrg_stm32l1.rs b/examples/bluenrg_stm32l1/src/main.rs similarity index 100% rename from examples/bluenrg_stm32l1.rs rename to examples/bluenrg_stm32l1/src/main.rs diff --git a/examples/dht22/Cargo.toml b/examples/dht22/Cargo.toml new file mode 100644 index 00000000..8f7a6816 --- /dev/null +++ b/examples/dht22/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "dht22" +version = "0.0.1" + +[features] +default = ["mcu_lpc17xx"] +mcu_lpc17xx = ["zinc/mcu_lpc17xx"] + +[dependencies] +zinc = { path = "../.." } +macro_platformtree = { path = "../../macro_platformtree" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/dht22.rs b/examples/dht22/src/main.rs similarity index 100% rename from examples/dht22.rs rename to examples/dht22/src/main.rs diff --git a/examples/empty/Cargo.toml b/examples/empty/Cargo.toml new file mode 100644 index 00000000..c299acab --- /dev/null +++ b/examples/empty/Cargo.toml @@ -0,0 +1,16 @@ +[package] +name = "empty" +version = "0.0.1" + +[features] +mcu_lpc11xx = ["zinc/mcu_lpc11xx"] +mcu_lpc17xx = ["zinc/mcu_lpc17xx"] +mcu_stm32f4 = ["zinc/mcu_stm32f4"] +mcu_stm32l1 = ["zinc/mcu_stm32l1"] +mcu_k20 = ["zinc/mcu_k20"] +mcu_tiva_c = ["zinc/mcu_tiva_c"] + +[dependencies] +zinc = { path = "../.." } +macro_zinc = { path = "../../macro_zinc" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/empty.rs b/examples/empty/src/main.rs similarity index 100% rename from examples/empty.rs rename to examples/empty/src/main.rs diff --git a/examples/lcd_tiva_c/Cargo.toml b/examples/lcd_tiva_c/Cargo.toml new file mode 100644 index 00000000..bf9d6bde --- /dev/null +++ b/examples/lcd_tiva_c/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "lcd_tiva_c" +version = "0.0.1" + +[features] +default = ["mcu_tiva_c"] +mcu_tiva_c = ["zinc/mcu_tiva_c"] + +[dependencies] +zinc = { path = "../.." } +macro_platformtree = { path = "../../macro_platformtree" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/lcd_tiva_c.rs b/examples/lcd_tiva_c/src/main.rs similarity index 100% rename from examples/lcd_tiva_c.rs rename to examples/lcd_tiva_c/src/main.rs diff --git a/examples/nothing.rs b/examples/nothing.rs deleted file mode 100644 index cbadaa7d..00000000 --- a/examples/nothing.rs +++ /dev/null @@ -1,9 +0,0 @@ -#![feature(plugin, no_std, core, start, core_intrinsics)] -#![no_std] -#![plugin(macro_zinc)] - -extern crate zinc; - -#[zinc_main] -pub fn main() { -} diff --git a/examples/uart/Cargo.toml b/examples/uart/Cargo.toml new file mode 100644 index 00000000..397ab071 --- /dev/null +++ b/examples/uart/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "uart" +version = "0.0.1" + +[features] +default = ["mcu_lpc17xx"] +mcu_lpc17xx = ["zinc/mcu_lpc17xx"] + +[dependencies] +zinc = { path = "../.." } +macro_platformtree = { path = "../../macro_platformtree" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/uart.rs b/examples/uart/src/main.rs similarity index 100% rename from examples/uart.rs rename to examples/uart/src/main.rs diff --git a/examples/uart_tiva_c/Cargo.toml b/examples/uart_tiva_c/Cargo.toml new file mode 100644 index 00000000..787392f4 --- /dev/null +++ b/examples/uart_tiva_c/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "uart_tiva_c" +version = "0.0.1" + +[features] +default = ["mcu_tiva_c"] +mcu_tiva_c = ["zinc/mcu_tiva_c"] + +[dependencies] +zinc = { path = "../.." } +macro_platformtree = { path = "../../macro_platformtree" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/uart_tiva_c.rs b/examples/uart_tiva_c/src/main.rs similarity index 100% rename from examples/uart_tiva_c.rs rename to examples/uart_tiva_c/src/main.rs diff --git a/examples/usart_stm32l1/Cargo.toml b/examples/usart_stm32l1/Cargo.toml new file mode 100644 index 00000000..efaeedbb --- /dev/null +++ b/examples/usart_stm32l1/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "usart_stm32l1" +version = "0.0.1" + +[features] +default = ["mcu_stm32l1"] +mcu_stm32l1 = ["zinc/mcu_stm32l1"] + +[dependencies] +zinc = { path = "../.." } +macro_zinc = { path = "../../macro_zinc" } +core = { git = "https://github.com/hackndev/rust-libcore" } diff --git a/examples/usart_stm32l1.rs b/examples/usart_stm32l1/src/main.rs similarity index 100% rename from examples/usart_stm32l1.rs rename to examples/usart_stm32l1/src/main.rs diff --git a/ioreg/src/builder/register.rs b/ioreg/src/builder/register.rs index d334ac49..d341beb7 100644 --- a/ioreg/src/builder/register.rs +++ b/ioreg/src/builder/register.rs @@ -77,6 +77,9 @@ fn build_field_type(cx: &ExtCtxt, path: &Vec, variants.iter().map(|v| P(build_enum_variant(cx, v)))), }; let attrs: Vec = vec!( + utils::list_attribute(cx, "derive", + vec!("PartialEq"), + field.name.span), utils::list_attribute(cx, "allow", vec!("dead_code", "non_camel_case_types", diff --git a/ioreg/src/builder/union.rs b/ioreg/src/builder/union.rs index a6fce1d7..d9ed603a 100644 --- a/ioreg/src/builder/union.rs +++ b/ioreg/src/builder/union.rs @@ -229,11 +229,18 @@ impl<'a> BuildUnionTypes<'a> { } ).unwrap(); - let copy_impl = quote_item!(self.cx, impl ::core::marker::Copy for $name {}).unwrap(); + let copy_impl = quote_item!( + self.cx, impl ::core::marker::Copy for $name {}).unwrap(); let item_address = reg.address; + let docstring = format!("Placement getter for register {} at address 0x{:x}", + reg.name.node, + item_address); + let doc_attr = utils::doc_attribute(self.cx, utils::intern_string( + self.cx, docstring)); let item_getter = quote_item!(self.cx, #[allow(non_snake_case, dead_code)] + $doc_attr pub fn $name() -> &'static $name { unsafe { ::core::intrinsics::transmute($item_address as usize) } } diff --git a/src/drivers/lcd/font_small_7.rs b/src/drivers/lcd/font_small_7.rs index e05814e1..2c710f3c 100644 --- a/src/drivers/lcd/font_small_7.rs +++ b/src/drivers/lcd/font_small_7.rs @@ -14,7 +14,7 @@ // limitations under the License. //! Definition of a 9x9 font. -//! +//! //! Font definition consists of a 4 byte header: //! - Length of a character definition //! - Maximum width of a character @@ -23,9 +23,10 @@ //! //! Each character definition consists of: //! - Single byte describing actual width of the character -//! - Remaining bytes describe vertical lines from left to right with the +//! - Remaining bytes describe vertical lines from left to right with the //! LSB defining the top of the line +/// Definition of a 9x9 font. pub static FONT: &'static [u8] = &[ 19,9,9,2, // Length,horz,vert,byte/vert 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Code for char diff --git a/src/hal/cortex_m0/mod.rs b/src/hal/cortex_m0/mod.rs index 7b1488b0..2aad0552 100644 --- a/src/hal/cortex_m0/mod.rs +++ b/src/hal/cortex_m0/mod.rs @@ -14,7 +14,7 @@ // limitations under the License. /*! -Generic routines for ARM Cortex-M3 cores. +Generic routines for ARM Cortex-M0 cores. This module also provides `isr.rs`, that is not compiled as a part of this crate. `isr.rs` provides ISR vector table. diff --git a/src/hal/isr.rs b/src/hal/isr.rs index 722439fd..ac8a5871 100644 --- a/src/hal/isr.rs +++ b/src/hal/isr.rs @@ -18,6 +18,9 @@ #![allow(missing_docs)] +#[cfg(feature = "cpu_cortex-m0")] +#[path="cortex_m3/isr.rs"] pub mod isr_cortex_m0; + #[cfg(feature = "cpu_cortex-m3")] #[path="cortex_m3/isr.rs"] pub mod isr_cortex_m3; diff --git a/src/hal/k20/layout.ld b/src/hal/k20/layout.ld index 155ab6dc..28b1c8c8 100644 --- a/src/hal/k20/layout.ld +++ b/src/hal/k20/layout.ld @@ -87,6 +87,7 @@ SECTIONS *(.rel.*) /* dynamic relocations */ *(.ARM.exidx*) /* index entries for section unwinding */ *(.ARM.extab*) /* exception unwinding information */ + *(.debug_gdb_scripts) } } diff --git a/src/hal/layout_common.ld b/src/hal/layout_common.ld index 1d713a56..5ab161e8 100644 --- a/src/hal/layout_common.ld +++ b/src/hal/layout_common.ld @@ -60,5 +60,6 @@ SECTIONS *(.rel.*) /* dynamic relocations */ *(.ARM.exidx*) /* index entries for section unwinding */ *(.ARM.extab*) /* exception unwinding information */ + *(.debug_gdb_scripts) } } diff --git a/src/hal/lpc11xx/iomem.ld b/src/hal/lpc11xx/iomem.ld new file mode 100644 index 00000000..d2cdf53c --- /dev/null +++ b/src/hal/lpc11xx/iomem.ld @@ -0,0 +1 @@ +/* lpc11xx uses placement ioregs */ diff --git a/src/hal/lpc11xx/layout.ld b/src/hal/lpc11xx/layout.ld new file mode 100644 index 00000000..8796f5f0 --- /dev/null +++ b/src/hal/lpc11xx/layout.ld @@ -0,0 +1,17 @@ +__STACK_BASE = 0x10002000; + +isr_reserved_1 = 0 - (__STACK_BASE + main + 1 + isr_nmi + 1 + isr_hardfault + 1); + +_data_load = LOADADDR(.data); + +ENTRY(main) + +MEMORY +{ + rom(RX) : ORIGIN = 0x00000000, LENGTH = 32K + ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 4K +} + +REGION_ALIAS("vectors", rom); + +INCLUDE layout_common.ld diff --git a/src/hal/lpc11xx/mod.rs b/src/hal/lpc11xx/mod.rs new file mode 100644 index 00000000..fdfee07b --- /dev/null +++ b/src/hal/lpc11xx/mod.rs @@ -0,0 +1,19 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2015 Vladimir "farcaller" Pouzanov +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//! HAL for NXP LPC11xx. + +mod regs; +pub mod syscon; diff --git a/src/hal/lpc11xx/regs.rs b/src/hal/lpc11xx/regs.rs new file mode 100644 index 00000000..60cac536 --- /dev/null +++ b/src/hal/lpc11xx/regs.rs @@ -0,0 +1,3797 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2015 zinc developers +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// THIS FILE IS AUTOMATICALLY GENERATED. DO NOT MODIFY IT DIRECTLY, UPDATE THE +// SVD DEFINITION IN SUPPORT/SVD/DATA AND RE-GENERATE, ADDING THE CHANGES MADE +// INTO THE RELEVANT CHANGELOG ENTRY. + +//! ioregs definition based on support/svd/data/NXP/LPC11xx-v6-z0.xml + +use volatile_cell::VolatileCell; +use core::ops::Drop; + +ioregs! (I2C @ 0x40000000 = { //! I2C + 0x00 => reg32 conset { //! I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. + 2 => aa, //= Assert acknowledge flag. + 3 => si, //= I2C interrupt flag. + 4 => sto, //= STOP flag. + 5 => sta, //= START flag. + 6 => i2en, //= I2C interface enable. + }, + 0x04 => reg32 stat { //! I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. + 3..7 => status: ro, //= These bits give the actual status information about the I 2C interface. + }, + 0x08 => reg32 dat { //! I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. + 0..7 => data, //= This register holds data values that have been received or are to be transmitted. + }, + 0x0c => reg32 adr0 { //! I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + 0 => gc, //= General Call enable bit. + 1..7 => address, //= The I2C device address for slave mode. + }, + 0x10 => reg32 sclh { //! SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. + 0..15 => sclh, //= Count for SCL HIGH time period selection. + }, + 0x14 => reg32 scll { //! SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. + 0..15 => scll, //= Count for SCL low time period selection. + }, + 0x18 => reg32 conclr { //! I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. + 2 => aac: wo, //= Assert acknowledge Clear bit. + 3 => sic: wo, //= I2C interrupt Clear bit. + 5 => stac: wo, //= START flag Clear bit. + 6 => i2enc: wo, //= I2C interface Disable bit. + }, + 0x1c => reg32 mmctrl { //! Monitor mode control register. + 0 => mm_ena { //! Monitor mode enable. + 0 => MONITOR_MODE_DISABLE, //= Monitor mode disabled. + 1 => THE_I2C_MODULE_WILL_, //= The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. + } + 1 => ena_scl { //! SCL output enable. + 0 => HIGH, //= When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. + 1 => NORMAL, //= When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] + } + 2 => match_all { //! Select interrupt register match. + 0 => MATCH, //= When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. + 1 => ANYADDRESS, //= When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. + } + }, + 0x20 => reg32 adr1 { //! I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + 0 => gc, //= General Call enable bit. + 1..7 => address, //= The I2C device address for slave mode. + }, + 0x24 => reg32 adr2 { //! I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + 0 => gc, //= General Call enable bit. + 1..7 => address, //= The I2C device address for slave mode. + }, + 0x28 => reg32 adr3 { //! I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. + 0 => gc, //= General Call enable bit. + 1..7 => address, //= The I2C device address for slave mode. + }, + 0x2c => reg32 data_buffer { //! Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. + 0..7 => data: ro, //= This register holds contents of the 8 MSBs of the DAT shift register. + }, + 0x30 => reg32 mask0 { //! I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). + 1..7 => mask, //= Mask bits. + }, + 0x34 => reg32 mask1 { //! I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). + 1..7 => mask, //= Mask bits. + }, + 0x38 => reg32 mask2 { //! I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). + 1..7 => mask, //= Mask bits. + }, + 0x3c => reg32 mask3 { //! I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). + 1..7 => mask, //= Mask bits. + }, +}); +ioregs! (WWDT @ 0x40004000 = { //! Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT) Modification date=9/19/2011 Major revision=6 Minor revision=not available + 0x00 => reg32 wdmod { //! Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. + 0 => wden { //! Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one. + 0 => STOPPED, //= The watchdog timer is stopped. + 1 => RUN, //= The watchdog timer is running. + } + 1 => wdreset { //! Watchdog reset enable bit. This bit is Set Only. + 0 => NORESET, //= A watchdog timeout will not cause a chip reset. + 1 => RESET, //= A watchdog timeout will cause a chip reset. + } + 2 => wdtof, //= Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. + 3 => wdint, //= Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. + 4 => wdprotect { //! Watchdog update mode. This bit is Set Only. + 0 => ANYTIME, //= The watchdog reload value (WDTC) can be changed at any time. + 1 => LOWCOUNTER, //= The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1. + } + }, + 0x04 => reg32 wdtc { //! Watchdog timer constant register. This register determines the time-out value. + 0..23 => count, //= Watchdog time-out interval. + }, + 0x08 => reg32 wdfeed { //! Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. + 0..7 => feed: wo, //= Feed value should be 0xAA followed by 0x55. + }, + 0x0c => reg32 wdtv { //! Watchdog timer value register. This register reads out the current value of the Watchdog timer. + 0..23 => count: ro, //= Counter timer value. + }, + 0x14 => reg32 wdwarnint { //! Watchdog Warning Interrupt compare value. + 0..9 => warnint, //= Watchdog warning interrupt compare value. + }, + 0x18 => reg32 wdwindow { //! Watchdog Window compare value. + 0..23 => window, //= Watchdog window value. + }, +}); +ioregs! (UART @ 0x40008000 = { //! Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx UART Modification date=9/19/2011 Major revision=7 Minor revision=not available + 0x00 => reg32 rbr { //! Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) + 0..7 => rbr: ro, //= The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO. + }, + 0x00 => reg32 thr { //! Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) + 0..7 => thr: wo, //= Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. + }, + 0x00 => reg32 dll { //! Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) + 0..7 => dllsb, //= The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART. + }, + 0x04 => reg32 dlm { //! Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) + 0..7 => dlmsb, //= The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART. + }, + 0x04 => reg32 ier { //! Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0) + 0 => rbrie { //! RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. + 0 => DISABLE_THE_RDA_INTE, //= Disable the RDA interrupt. + 1 => ENABLE_THE_RDA_INTER, //= Enable the RDA interrupt. + } + 1 => threie { //! THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5]. + 0 => DISABLE_THE_THRE_INT, //= Disable the THRE interrupt. + 1 => ENABLE_THE_THRE_INTE, //= Enable the THRE interrupt. + } + 2 => rxlie { //! RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. + 0 => DISABLE_THE_RX_LINE_, //= Disable the RX line status interrupts. + 1 => ENABLE_THE_RX_LINE_S, //= Enable the RX line status interrupts. + } + 8 => abeointen { //! Enables the end of auto-baud interrupt. + 0 => DISABLE_END_OF_AUTO_, //= Disable end of auto-baud Interrupt. + 1 => ENABLE_END_OF_AUTO_B, //= Enable end of auto-baud Interrupt. + } + 9 => abtointen { //! Enables the auto-baud time-out interrupt. + 0 => DISABLE_AUTO_BAUD_TI, //= Disable auto-baud time-out Interrupt. + 1 => ENABLE_AUTO_BAUD_TIM, //= Enable auto-baud time-out Interrupt. + } + }, + 0x08 => reg32 iir { //! Interrupt ID Register. Identifies which interrupt(s) are pending. + 0 => intstatus: ro { //! Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. + 0 => PENDING, //= At least one interrupt is pending. + 1 => NO_INTERRUPT_IS_PEND, //= No interrupt is pending. + } + 1..3 => intid: ro { //! Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). + 3 => E_1_RECEIVE_LINE_S, //= 1 - Receive Line Status (RLS). + 2 => E_2A__RECEIVE_DATA_AV, //= 2a - Receive Data Available (RDA). + 6 => E_2B__CHARACTER_TIME_, //= 2b - Character Time-out Indicator (CTI). + 1 => E_3_THRE_INTERRUPT, //= 3 - THRE Interrupt. + 0 => E_4_MODEM_INTERRUP, //= 4 - Modem interrupt. + } + 6..7 => fifoenable: ro, //= These bits are equivalent to FCR[0]. + 8 => abeoint: ro, //= End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. + 9 => abtoint: ro, //= Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. + }, + 0x08 => reg32 fcr { //! FIFO Control Register. Controls UART FIFO usage and modes. + 0 => fifoen: wo { //! FIFO Enable + 0 => DISABLED, //= UART FIFOs are disabled. Must not be used in the application. + 1 => ENABLED, //= Active high enable for both UART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs. + } + 1 => rxfifores: wo { //! RX FIFO Reset + 0 => NO_IMPACT_ON_EITHER_, //= No impact on either of UART FIFOs. + 1 => CLEAR, //= Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing. + } + 2 => txfifores: wo { //! TX FIFO Reset + 0 => NO_IMPACT_ON_EITHER_, //= No impact on either of UART FIFOs. + 1 => CLEAR, //= Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing. + } + 6..7 => rxtl: wo { //! RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated. + 0 => TRIGGER_LEVEL_0_1_C, //= Trigger level 0 (1 character or 0x01). + 1 => TRIGGER_LEVEL_1_4_C, //= Trigger level 1 (4 characters or 0x04). + 2 => TRIGGER_LEVEL_2_8_C, //= Trigger level 2 (8 characters or 0x08). + 3 => TRIGGER_LEVEL_3_14_, //= Trigger level 3 (14 characters or 0x0E). + } + }, + 0x0c => reg32 lcr { //! Line Control Register. Contains controls for frame formatting and break generation. + 0..1 => wls { //! Word Length Select + 0 => E_5_BIT_CHARACTER_LENG, //= 5-bit character length. + 1 => E_6_BIT_CHARACTER_LENG, //= 6-bit character length. + 2 => E_7_BIT_CHARACTER_LENG, //= 7-bit character length. + 3 => E_8_BIT_CHARACTER_LENG, //= 8-bit character length. + } + 2 => sbs { //! Stop Bit Select + 0 => E_1_STOP_BIT_, //= 1 stop bit. + 1 => E_2_STOP_BITS, //= 2 stop bits (1.5 if LCR[1:0]=00). + } + 3 => pe { //! Parity Enable + 0 => DISABLE_PARITY_GENER, //= Disable parity generation and checking. + 1 => ENABLE_PARITY_GENERA, //= Enable parity generation and checking. + } + 4..5 => ps { //! Parity Select + 0 => ODD_PARITY_NUMBER_O, //= Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. + 1 => EVEN_PARITY_NUMBER_, //= Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. + 2 => FORCED_1_STICK_PARIT, //= Forced 1 stick parity. + 3 => FORCED_0_STICK_PARIT, //= Forced 0 stick parity. + } + 6 => bc { //! Break Control + 0 => DISABLE_BREAK_TRANSM, //= Disable break transmission. + 1 => ENABLE_BREAK_TRANSMI, //= Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high. + } + 7 => dlab { //! Divisor Latch Access Bit + 0 => DISABLE_ACCESS_TO_DI, //= Disable access to Divisor Latches. + 1 => ENABLE_ACCESS_TO_DIV, //= Enable access to Divisor Latches. + } + }, + 0x10 => reg32 mcr { //! Modem control register + 0 => dtrc, //= DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. + 1 => rtsc, //= RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. + 4 => lms, //= Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR. + 6 => rtsen { //! RTS flow control + 0 => DISABLE_AUTO_RTS_FLO, //= Disable auto-rts flow control. + 1 => ENABLE_AUTO_RTS_FLOW, //= Enable auto-rts flow control. + } + 7 => ctsen { //! CTS flow control + 0 => DISABLE_AUTO_CTS_FLO, //= Disable auto-cts flow control. + 1 => ENABLE_AUTO_CTS_FLOW, //= Enable auto-cts flow control. + } + }, + 0x14 => reg32 lsr { //! Line Status Register. Contains flags for transmit and receive status, including line errors. + 0 => rdr: ro { //! Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty. + 0 => EMPTY_, //= RBR is empty. + 1 => VALID, //= RBR contains valid data. + } + 1 => oe: ro { //! Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost. + 0 => INACTIVE, //= Overrun error status is inactive. + 1 => ACTIVE, //= Overrun error status is active. + } + 2 => pe: ro { //! Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO. + 0 => INACTIVE, //= Parity error status is inactive. + 1 => ACTIVE, //= Parity error status is active. + } + 3 => fe: ro { //! Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO. + 0 => INACTIVE, //= Framing error status is inactive. + 1 => ACTIVE, //= Framing error status is active. + } + 4 => bi: ro { //! Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO. + 0 => INACTIVE, //= Break interrupt status is inactive. + 1 => ACTIVE, //= Break interrupt status is active. + } + 5 => thre: ro { //! Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write. + 0 => VALID, //= THR contains valid data. + 1 => EMPTY_, //= THR is empty. + } + 6 => temt: ro { //! Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. + 0 => VALID, //= THR and/or the TSR contains valid data. + 1 => EMPTY_, //= THR and the TSR are empty. + } + 7 => rxfe: ro { //! Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO. + 0 => NOERROR, //= RBR contains no UART RX errors or FCR[0]=0. + 1 => ERROR, //= UART RBR contains at least one UART RX error. + } + }, + 0x18 => reg32 msr { //! Modem status register + 0 => dcts: ro { //! Delta CTS. Set upon state change of input CTS. Cleared on a MSR read. + 0 => NO_CHANGE_DETECTED_O, //= No change detected on modem input CTS. + 1 => STATE_CHANGE_DETECTE, //= State change detected on modem input CTS. + } + 1 => ddsr: ro { //! Delta DSR. Set upon state change of input DSR. Cleared on a MSR read. + 0 => NO_CHANGE_DETECTED_O, //= No change detected on modem input DSR. + 1 => STATE_CHANGE_DETECTE, //= State change detected on modem input DSR. + } + 2 => teri: ro { //! Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read. + 0 => NO_CHANGE_DETECTED_O, //= No change detected on modem input, RI. + 1 => LOW_TO_HIGH_TRANSITI, //= Low-to-high transition detected on RI. + } + 3 => ddcd: ro { //! Delta DCD. Set upon state change of input DCD. Cleared on a MSR read. + 0 => NO_CHANGE_DETECTED_O, //= No change detected on modem input DCD. + 1 => STATE_CHANGE_DETECTE, //= State change detected on modem input DCD. + } + 4 => cts: ro, //= Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. + 5 => dsr: ro, //= Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. + 6 => ri: ro, //= Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. + 7 => dcd: ro, //= Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. + }, + 0x1c => reg32 scr { //! Scratch Pad Register. Eight-bit temporary storage for software. + 0..7 => pad, //= A readable, writable byte. + }, + 0x20 => reg32 acr { //! Auto-baud Control Register. Contains controls for the auto-baud feature. + 0 => start { //! Start bit. This bit is automatically cleared after auto-baud completion. + 0 => STOP, //= Auto-baud stop (auto-baud is not running). + 1 => START, //= Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. + } + 1 => mode { //! Auto-baud mode select + 0 => MODE_0_, //= Mode 0. + 1 => MODE_1_, //= Mode 1. + } + 2 => autorestart { //! Restart enable + 0 => NO_RESTART, //= No restart + 1 => RESTART_IN_CASE_OF_T, //= Restart in case of time-out (counter restarts at next UART Rx falling edge) + } + 8 => abeointclr { //! End of auto-baud interrupt clear (write only accessible) + 0 => NOIMPACT, //= Writing a 0 has no impact. + 1 => CLEAR, //= Writing a 1 will clear the corresponding interrupt in the IIR. + } + 9 => abtointclr { //! Auto-baud time-out interrupt clear (write only accessible) + 0 => NOIMPACT, //= Writing a 0 has no impact. + 1 => CLEAR, //= Writing a 1 will clear the corresponding interrupt in the IIR. + } + }, + 0x28 => reg32 fdr { //! Fractional Divider Register. Generates a clock input for the baud rate divider. + 0..3 => divaddval, //= Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate. + 4..7 => mulval, //= Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not. + }, + 0x30 => reg32 ter { //! Transmit Enable Register. Turns off UART transmitter for use with software flow control. + 7 => txen, //= When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. + }, + 0x4c => reg32 rs485ctrl { //! RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. + 0 => nmmen { //! NMM enable. + 0 => DISABLED, //= RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. + 1 => ENABLED, //= RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. + } + 1 => rxdis { //! Receiver enable. + 0 => ENABLED, //= The receiver is enabled. + 1 => DISABLED, //= The receiver is disabled. + } + 2 => aaden { //! AAD enable. + 0 => DISABLED, //= Auto Address Detect (AAD) is disabled. + 1 => ENABLED, //= Auto Address Detect (AAD) is enabled. + } + 3 => sel { //! Select direction control pin + 0 => RTS, //= If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. + 1 => DTR, //= If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. + } + 4 => dctrl { //! Auto direction control enable. + 0 => DISABLE_AUTO_DIRECTI, //= Disable Auto Direction Control. + 1 => ENABLE_AUTO_DIRECTIO, //= Enable Auto Direction Control. + } + 5 => oinv { //! Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. + 0 => LOW, //= The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. + 1 => HIGH, //= The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. + } + }, + 0x50 => reg32 rs485adrmatch { //! RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. + 0..7 => adrmatch, //= Contains the address match value. + }, + 0x54 => reg32 rs485dly { //! RS-485/EIA-485 direction control delay. + 0..7 => dly, //= Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. + }, +}); +ioregs! (CT16B0 @ 0x4000c000 = { //! Product name title=UM10398 Chapter title=LPC1100XL series: 16-bit counter/timer CT16B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available + 0x00 => reg32 ir { //! Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. + 0 => mr0int, //= Interrupt flag for match channel 0. + 1 => mr1int, //= Interrupt flag for match channel 1. + 2 => mr2int, //= Interrupt flag for match channel 2. + 3 => mr3int, //= Interrupt flag for match channel 3. + 4 => cr0int, //= Interrupt flag for capture channel 0 event. + 5 => cr1int, //= Interrupt flag for capture channel 1 event. + }, + 0x04 => reg32 tcr { //! Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0 => cen, //= Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + 1 => crst, //= Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + }, + 0x08 => reg32 tc { //! Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + 0..15 => tc, //= Timer counter value. + }, + 0x0c => reg32 pr { //! Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. + 0..15 => pr, //= Prescale max value. + }, + 0x10 => reg32 pc { //! Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + 0..15 => pc, //= Prescale counter value. + }, + 0x14 => reg32 mcr { //! Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + 0 => mr0i { //! Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => mr0r { //! Reset on MR0: the TC will be reset if MR0 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => mr0s { //! Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => mr1i { //! Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => mr1r { //! Reset on MR1: the TC will be reset if MR1 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => mr1s { //! Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 6 => mr2i { //! Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 7 => mr2r { //! Reset on MR2: the TC will be reset if MR2 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 8 => mr2s { //! Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 9 => mr3i { //! Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 10 => mr3r { //! Reset on MR3: the TC will be reset if MR3 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 11 => mr3s { //! Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x18 => reg32 mr0 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x1c => reg32 mr1 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x20 => reg32 mr2 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x24 => reg32 mr3 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x28 => reg32 ccr { //! Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0 => cap0re { //! Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => cap0fe { //! Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => cap0i { //! Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => cap1re { //! Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => cap1fe { //! Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => cap1i { //! Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x2c => reg32 cr0 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..15 => cap: ro, //= Timer counter capture value. + }, + 0x30 => reg32 cr1 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..15 => cap: ro, //= Timer counter capture value. + }, + 0x3c => reg32 emr { //! External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. + 0 => em0, //= External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 1 => em1, //= External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 2 => em2, //= External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 3 => em3, //= External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. + 4..5 => emc0 { //! External Match Control 0. Determines the functionality of External Match 0. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 6..7 => emc1 { //! External Match Control 1. Determines the functionality of External Match 1. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 8..9 => emc2 { //! External Match Control 2. Determines the functionality of External Match 2. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 10..11 => emc3 { //! External Match Control 3. Determines the functionality of External Match 3. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + }, + 0x70 => reg32 ctcr { //! Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0..1 => ctm { //! Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + 0 => TIMER_MODE_EVERY_RI, //= Timer Mode: every rising PCLK edge + 1 => COUNTER_MODE_TC_IS_RISING, //= Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + 2 => COUNTER_MODE_TC_IS_FALLING, //= Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + 3 => COUNTER_MODE_TC_IS_BOTH, //= Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + } + 2..3 => cis { //! Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. + 0 => CT16BN_CAP0, //= CT16Bn_CAP0 + 1 => CT16BN_CAP1, //= CT16Bn_CAP1 + } + 4 => encc, //= Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 5..7 => selcc { //! When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero. + 0 => RISING_EDGE_OF_CAP0_, //= Rising Edge of CAP0 clears the timer (if bit 4 is set). + 1 => FALLING_EDGE_OF_CAP0, //= Falling Edge of CAP0 clears the timer (if bit 4 is set). + 2 => RISING_EDGE_OF_CAP1_, //= Rising Edge of CAP1 clears the timer (if bit 4 is set). + 3 => FALLING_EDGE_OF_CAP1, //= Falling Edge of CAP1 clears the timer (if bit 4 is set). + } + }, + 0x74 => reg32 pwmc { //! PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. + 0 => pwmen0 { //! PWM channel0 enable + 0 => CT16BN_MAT0_IS_CONTR, //= CT16Bn_MAT0 is controlled by EM0. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT16Bn_MAT0. + } + 1 => pwmen1 { //! PWM channel1 enable + 0 => CT16BN_MAT1_IS_CONTR, //= CT16Bn_MAT1 is controlled by EM1. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT16Bn_MAT1. + } + 2 => pwmen2 { //! PWM channel2 enable + 0 => MATCH_CHANNEL_2_OR_P, //= Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. + } + 3 => pwmen3 { //! PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. + 0 => MATCH_CHANNEL_3_MATC, //= Match channel 3 match channel 3 is controlled by EM3. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for match channel 3match channel 3. + } + }, +}); +ioregs! (CT16B1 @ 0x40010000 = { //! Product name title=UM10398 Chapter title=LPC1100XL series: 16-bit counter/timer CT16B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available + 0x00 => reg32 ir { //! Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. + 0 => mr0int, //= Interrupt flag for match channel 0. + 1 => mr1int, //= Interrupt flag for match channel 1. + 2 => mr2int, //= Interrupt flag for match channel 2. + 3 => mr3int, //= Interrupt flag for match channel 3. + 4 => cr0int, //= Interrupt flag for capture channel 0 event. + 5 => cr1int, //= Interrupt flag for capture channel 1 event. + }, + 0x04 => reg32 tcr { //! Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0 => cen, //= Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + 1 => crst, //= Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + }, + 0x08 => reg32 tc { //! Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + 0..15 => tc, //= Timer counter value. + }, + 0x0c => reg32 pr { //! Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. + 0..15 => pr, //= Prescale max value. + }, + 0x10 => reg32 pc { //! Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + 0..15 => pc, //= Prescale counter value. + }, + 0x14 => reg32 mcr { //! Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + 0 => mr0i { //! Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => mr0r { //! Reset on MR0: the TC will be reset if MR0 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => mr0s { //! Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => mr1i { //! Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => mr1r { //! Reset on MR1: the TC will be reset if MR1 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => mr1s { //! Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 6 => mr2i { //! Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 7 => mr2r { //! Reset on MR2: the TC will be reset if MR2 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 8 => mr2s { //! Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 9 => mr3i { //! Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 10 => mr3r { //! Reset on MR3: the TC will be reset if MR3 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 11 => mr3s { //! Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x18 => reg32 mr0 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x1c => reg32 mr1 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x20 => reg32 mr2 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x24 => reg32 mr3 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..15 => f_match, //= Timer counter match value. + }, + 0x28 => reg32 ccr { //! Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0 => cap0re { //! Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => cap0fe { //! Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => cap0i { //! Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => cap1re { //! Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => cap1fe { //! Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => cap1i { //! Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x2c => reg32 cr0 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..15 => cap: ro, //= Timer counter capture value. + }, + 0x30 => reg32 cr1 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..15 => cap: ro, //= Timer counter capture value. + }, + 0x3c => reg32 emr { //! External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. + 0 => em0, //= External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 1 => em1, //= External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 2 => em2, //= External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 3 => em3, //= External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. + 4..5 => emc0 { //! External Match Control 0. Determines the functionality of External Match 0. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 6..7 => emc1 { //! External Match Control 1. Determines the functionality of External Match 1. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 8..9 => emc2 { //! External Match Control 2. Determines the functionality of External Match 2. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 10..11 => emc3 { //! External Match Control 3. Determines the functionality of External Match 3. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + }, + 0x70 => reg32 ctcr { //! Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0..1 => ctm { //! Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). + 0 => TIMER_MODE_EVERY_RI, //= Timer Mode: every rising PCLK edge + 1 => COUNTER_MODE_TC_IS_RISING, //= Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + 2 => COUNTER_MODE_TC_IS_FALLING, //= Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + 3 => COUNTER_MODE_TC_IS_BOTH, //= Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + } + 2..3 => cis { //! Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. + 0 => CT16BN_CAP0, //= CT16Bn_CAP0 + 1 => CT16BN_CAP1, //= CT16Bn_CAP1 + } + 4 => encc, //= Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 5..7 => selcc { //! When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero. + 0 => RISING_EDGE_OF_CAP0_, //= Rising Edge of CAP0 clears the timer (if bit 4 is set). + 1 => FALLING_EDGE_OF_CAP0, //= Falling Edge of CAP0 clears the timer (if bit 4 is set). + 2 => RISING_EDGE_OF_CAP1_, //= Rising Edge of CAP1 clears the timer (if bit 4 is set). + 3 => FALLING_EDGE_OF_CAP1, //= Falling Edge of CAP1 clears the timer (if bit 4 is set). + } + }, + 0x74 => reg32 pwmc { //! PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. + 0 => pwmen0 { //! PWM channel0 enable + 0 => CT16BN_MAT0_IS_CONTR, //= CT16Bn_MAT0 is controlled by EM0. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT16Bn_MAT0. + } + 1 => pwmen1 { //! PWM channel1 enable + 0 => CT16BN_MAT1_IS_CONTR, //= CT16Bn_MAT1 is controlled by EM1. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT16Bn_MAT1. + } + 2 => pwmen2 { //! PWM channel2 enable + 0 => MATCH_CHANNEL_2_OR_P, //= Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. + } + 3 => pwmen3 { //! PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. + 0 => MATCH_CHANNEL_3_MATC, //= Match channel 3 match channel 3 is controlled by EM3. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for match channel 3match channel 3. + } + }, +}); +ioregs! (CT32B0 @ 0x40014000 = { //! Product name title=UM10398 Chapter title=LPC1100XL series: 32-bit counter/timer CT32B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available + 0x00 => reg32 ir { //! Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. + 0 => mr0int, //= Interrupt flag for match channel 0. + 1 => mr1int, //= Interrupt flag for match channel 1. + 2 => mr2int, //= Interrupt flag for match channel 2. + 3 => mr3int, //= Interrupt flag for match channel 3. + 4 => cr0int, //= Interrupt flag for capture channel 0 event. + 5 => cr1int, //= Interrupt flag for capture channel 1 event. + }, + 0x04 => reg32 tcr { //! Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0 => cen, //= When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + 1 => crst, //= When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + }, + 0x08 => reg32 tc { //! Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + 0..31 => tc, //= Timer counter value. + }, + 0x0c => reg32 pr { //! Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. + 0..31 => pr, //= Prescale value. + }, + 0x10 => reg32 pc { //! Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + 0..31 => pc, //= Prescale counter value. + }, + 0x14 => reg32 mcr { //! Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + 0 => mr0i { //! Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => mr0r { //! Reset on MR0: the TC will be reset if MR0 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => mr0s { //! Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => mr1i { //! Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => mr1r { //! Reset on MR1: the TC will be reset if MR1 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => mr1s { //! Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 6 => mr2i { //! Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 7 => mr2r { //! Reset on MR2: the TC will be reset if MR2 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 8 => mr2s { //! Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 9 => mr3i { //! Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 10 => mr3r { //! Reset on MR3: the TC will be reset if MR3 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 11 => mr3s { //! Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x18 => reg32 mr0 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x1c => reg32 mr1 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x20 => reg32 mr2 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x24 => reg32 mr3 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x28 => reg32 ccr { //! Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0 => cap0re { //! Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => cap0fe { //! Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => cap0i { //! Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => cap1re { //! Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => cap1fe { //! Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => cap1i { //! Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x2c => reg32 cr0 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..31 => cap: ro, //= Timer counter capture value. + }, + 0x30 => reg32 cr1 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..31 => cap: ro, //= Timer counter capture value. + }, + 0x3c => reg32 emr { //! External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. + 0 => em0, //= External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 1 => em1, //= External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 2 => em2, //= External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 3 => em3, //= External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 4..5 => emc0 { //! External Match Control 0. Determines the functionality of External Match 0. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 6..7 => emc1 { //! External Match Control 1. Determines the functionality of External Match 1. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 8..9 => emc2 { //! External Match Control 2. Determines the functionality of External Match 2. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 10..11 => emc3 { //! External Match Control 3. Determines the functionality of External Match 3. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + }, + 0x70 => reg32 ctcr { //! Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0..1 => ctm { //! Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge + 0 => TIMER_MODE_EVERY_RI, //= Timer Mode: every rising PCLK edge + 1 => COUNTER_MODE_TC_IS_RISING, //= Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + 2 => COUNTER_MODE_TC_IS_FALLING, //= Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + 3 => COUNTER_MODE_TC_IS_BOTH, //= Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + } + 2..3 => cis { //! Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: + 0 => CT32BN_CAP0, //= CT32Bn_CAP0 + 1 => CT32BN_CAP1, //= CT32Bn_CAP1 + } + 4 => encc, //= Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 5..7 => selcc { //! When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero. + 0 => RISING_EDGE_OF_CAP0_, //= Rising Edge of CAP0 clears the timer (if bit 4 is set). + 1 => FALLING_EDGE_OF_CAP0, //= Falling Edge of CAP0 clears the timer (if bit 4 is set). + 2 => RISING_EDGE_OF_CAP1_, //= Rising Edge of CAP1 clears the timer (if bit 4 is set). + 3 => FALLING_EDGE_OF_CAP1, //= Falling Edge of CAP1 clears the timer (if bit 4 is set). + } + }, + 0x74 => reg32 pwmc { //! PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. + 0 => pwmen0 { //! PWM channel 0 enable + 0 => CT32BN_MAT0_IS_CONTR, //= CT32Bn_MAT0 is controlled by EM0. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT0. + } + 1 => pwmen1 { //! PWM channel 1 enable + 0 => CT32BN_MAT1_IS_CONTR, //= CT32Bn_MAT1 is controlled by EM1. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT1. + } + 2 => pwmen2 { //! PWM channel 2 enable + 0 => CT32BN_MAT2_IS_CONTR, //= CT32Bn_MAT2 is controlled by EM2. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT2. + } + 3 => pwmen3 { //! PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. + 0 => CT32BN_MAT3_IS_CONTR, //= CT32Bn_MAT3 is controlled by EM3. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT3. + } + }, +}); +ioregs! (CT32B1 @ 0x40018000 = { //! Product name title=UM10398 Chapter title=LPC1100XL series: 32-bit counter/timer CT32B0/1 Modification date=2/22/2012 Major revision=8 Minor revision=not available + 0x00 => reg32 ir { //! Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. + 0 => mr0int, //= Interrupt flag for match channel 0. + 1 => mr1int, //= Interrupt flag for match channel 1. + 2 => mr2int, //= Interrupt flag for match channel 2. + 3 => mr3int, //= Interrupt flag for match channel 3. + 4 => cr0int, //= Interrupt flag for capture channel 0 event. + 5 => cr1int, //= Interrupt flag for capture channel 1 event. + }, + 0x04 => reg32 tcr { //! Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. + 0 => cen, //= When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. + 1 => crst, //= When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. + }, + 0x08 => reg32 tc { //! Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. + 0..31 => tc, //= Timer counter value. + }, + 0x0c => reg32 pr { //! Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. + 0..31 => pr, //= Prescale value. + }, + 0x10 => reg32 pc { //! Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. + 0..31 => pc, //= Prescale counter value. + }, + 0x14 => reg32 mcr { //! Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. + 0 => mr0i { //! Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => mr0r { //! Reset on MR0: the TC will be reset if MR0 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => mr0s { //! Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => mr1i { //! Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => mr1r { //! Reset on MR1: the TC will be reset if MR1 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => mr1s { //! Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 6 => mr2i { //! Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 7 => mr2r { //! Reset on MR2: the TC will be reset if MR2 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 8 => mr2s { //! Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 9 => mr3i { //! Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 10 => mr3r { //! Reset on MR3: the TC will be reset if MR3 matches it. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 11 => mr3s { //! Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x18 => reg32 mr0 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x1c => reg32 mr1 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x20 => reg32 mr2 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x24 => reg32 mr3 { //! Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. + 0..31 => f_match, //= Timer counter match value. + }, + 0x28 => reg32 ccr { //! Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. + 0 => cap0re { //! Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 1 => cap0fe { //! Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 2 => cap0i { //! Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 3 => cap1re { //! Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 4 => cap1fe { //! Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + 5 => cap1i { //! Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt. + 1 => ENABLED, //= Enabled + 0 => DISABLED, //= Disabled + } + }, + 0x2c => reg32 cr0 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..31 => cap: ro, //= Timer counter capture value. + }, + 0x30 => reg32 cr1 { //! Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input. + 0..31 => cap: ro, //= Timer counter capture value. + }, + 0x3c => reg32 emr { //! External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. + 0 => em0, //= External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 1 => em1, //= External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 2 => em2, //= External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 3 => em3, //= External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). + 4..5 => emc0 { //! External Match Control 0. Determines the functionality of External Match 0. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 6..7 => emc1 { //! External Match Control 1. Determines the functionality of External Match 1. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 8..9 => emc2 { //! External Match Control 2. Determines the functionality of External Match 2. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + 10..11 => emc3 { //! External Match Control 3. Determines the functionality of External Match 3. + 0 => DO_NOTHING_, //= Do Nothing. + 1 => CLEAR_THE_CORRESPOND, //= Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). + 2 => SET_THE_CORRESPONDIN, //= Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). + 3 => TOGGLE_THE_CORRESPON, //= Toggle the corresponding External Match bit/output. + } + }, + 0x70 => reg32 ctcr { //! Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. + 0..1 => ctm { //! Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge + 0 => TIMER_MODE_EVERY_RI, //= Timer Mode: every rising PCLK edge + 1 => COUNTER_MODE_TC_IS_RISING, //= Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. + 2 => COUNTER_MODE_TC_IS_FALLING, //= Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. + 3 => COUNTER_MODE_TC_IS_BOTH, //= Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. + } + 2..3 => cis { //! Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: + 0 => CT32BN_CAP0, //= CT32Bn_CAP0 + 1 => CT32BN_CAP1, //= CT32Bn_CAP1 + } + 4 => encc, //= Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. + 5..7 => selcc { //! When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero. + 0 => RISING_EDGE_OF_CAP0_, //= Rising Edge of CAP0 clears the timer (if bit 4 is set). + 1 => FALLING_EDGE_OF_CAP0, //= Falling Edge of CAP0 clears the timer (if bit 4 is set). + 2 => RISING_EDGE_OF_CAP1_, //= Rising Edge of CAP1 clears the timer (if bit 4 is set). + 3 => FALLING_EDGE_OF_CAP1, //= Falling Edge of CAP1 clears the timer (if bit 4 is set). + } + }, + 0x74 => reg32 pwmc { //! PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. + 0 => pwmen0 { //! PWM channel 0 enable + 0 => CT32BN_MAT0_IS_CONTR, //= CT32Bn_MAT0 is controlled by EM0. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT0. + } + 1 => pwmen1 { //! PWM channel 1 enable + 0 => CT32BN_MAT1_IS_CONTR, //= CT32Bn_MAT1 is controlled by EM1. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT1. + } + 2 => pwmen2 { //! PWM channel 2 enable + 0 => CT32BN_MAT2_IS_CONTR, //= CT32Bn_MAT2 is controlled by EM2. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT2. + } + 3 => pwmen3 { //! PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. + 0 => CT32BN_MAT3_IS_CONTR, //= CT32Bn_MAT3 is controlled by EM3. + 1 => PWM_MODE_IS_ENABLED_, //= PWM mode is enabled for CT32Bn_MAT3. + } + }, +}); +ioregs! (ADC @ 0x4001c000 = { //! 10-bit ADC + 0x00 => reg32 cr { //! A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur. + 0..7 => sel, //= Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01). + 8..15 => clkdiv, //= The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. + 16 => burst { //! Burst mode + 0 => SWMODE, //= Software-controlled mode: Conversions are software-controlled and require 11 clocks. + 1 => HWMODE, //= Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. + } + 17..19 => clks { //! This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). + 0 => E_10BIT, //= 11 clocks / 10 bits + 1 => E_9BIT, //= 10 clocks / 9 bits + 2 => E_8BIT, //= 9 clocks / 8 bits + 3 => E_7BIT, //= 8 clocks / 7 bits + 4 => E_6BIT, //= 7 clocks / 6 bits + 5 => E_5BIT, //= 6 clocks / 5 bits + 6 => E_4BIT, //= 5 clocks / 4 bits + 7 => E_3BIT, //= 4 clocks / 3 bits + } + 24..26 => start { //! When the BURST bit is 0, these bits control whether and when an A/D conversion is started: + 0 => STOP, //= No start (this value should be used when clearing PDN to 0). + 1 => START, //= Start conversion now. + 2 => EDGEPIO0_2, //= Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0. + 3 => EDGEPIO1_5, //= Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0. + 4 => EDGECT32B0_MAT0_1, //= Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]. + 5 => EDGECT32B0_MAT1_1, //= Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]. + 6 => EDGECT16B0_MAT0_1, //= Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]. + 7 => EDGECT16B0_MAT1_1, //= Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]. + } + 27 => edge { //! This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal. + 0 => RISING, //= Start conversion on a rising edge on the selected CAP/MAT signal. + 1 => FALLING, //= Start conversion on a rising edge on the selected CAP/MAT signal. + } + }, + 0x04 => reg32 gdr { //! A/D Global Data Register. Contains the result of the most recent A/D conversion. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF. + 24..26 => chn, //= These bits contain the channel from which the result bits V_VREF were converted. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. + }, + 0x30 => reg32 stat { //! A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. + 0..7 => done: ro, //= These bits mirror the DONE status flags that appear in the result register for each A/D channel n. + 8..15 => overrun: ro, //= These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously. + 16 => adint: ro, //= This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. + }, + 0x0c => reg32 inten { //! A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. + 0..7 => adintenn, //= These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. + 8 => adginten, //= When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. + }, + 0x10 => reg32 dr0 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x14 => reg32 dr1 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x18 => reg32 dr2 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x1c => reg32 dr3 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x20 => reg32 dr4 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x24 => reg32 dr5 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x28 => reg32 dr6 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, + 0x2c => reg32 dr7 { //! A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n. + 6..15 => v_vref, //= When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. + 30 => overrun, //= This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. + 31 => done, //= This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. + }, +}); +ioregs! (PMU @ 0x40038000 = { //! power management unit + 0x00 => reg32 pcon { //! Power control register + 1 => dpden { //! Deep power-down mode enable + 0 => SLEEPMODE, //= ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 core turned off). + 1 => DEEPPOWERDOWN, //= ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down). + } + 8 => sleepflag { //! Sleep mode flag + 0 => NOPOWERDOWN, //= Read: No power-down mode entered. LPC111x/LPC11C1x is in Active mode. Write: No effect. + 1 => POWERDOWN, //= Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. + } + 11 => dpdflag { //! Deep power-down flag + 0 => NODEEPPOWERDOWN, //= Read: Deep power-down mode not entered. Write: No effect. + 1 => DEEPPOWERDOWN, //= Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. + } + }, + 0x04 => reg32 gpreg0 { //! General purpose register + 0..31 => gpdata, //= Data retained during Deep power-down mode. + }, + 0x08 => reg32 gpreg1 { //! General purpose register + 0..31 => gpdata, //= Data retained during Deep power-down mode. + }, + 0x0c => reg32 gpreg2 { //! General purpose register + 0..31 => gpdata, //= Data retained during Deep power-down mode. + }, + 0x10 => reg32 gpreg3 { //! General purpose register + 0..31 => gpdata, //= Data retained during Deep power-down mode. + }, + 0x14 => reg32 gpreg4 { //! General purpose register 4 + 10 => wakeuphys { //! WAKEUP pin hysteresis enable + 1 => ENABLED, //= Hysteresis for WAKEUP pin enabled. + 0 => DISABLED, //= Hysteresis for WAKUP pin disabled. + } + 11..31 => gpdata, //= Data retained during Deep power-down mode. + }, +}); +ioregs! (FLASHCTRL @ 0x4003c000 = { //! Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 + 0x10 => reg32 flashcfg { //! Flash memory access time configuration register + 0..1 => flashtim { //! Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. + 1 => E_1_SYSTEM_CLOCK_FLASH, //= 1 system clock flash access time (for system clock frequencies of up to 20 MHz). + 2 => E_2_SYSTEM_CLOCKS_FLAS, //= 2 system clocks flash access time (for system clock frequencies of up to 40 MHz). + 3 => E_3_SYSTEM_CLOCKS_FLAS, //= 3 system clocks flash access time (for system clock frequencies of up to 50 MHz). + } + }, + 0x20 => reg32 fmsstart { //! Signature start address register + 0..16 => start, //= Signature generation start address (corresponds to AHB byte address bits[20:4]). + }, + 0x24 => reg32 fmsstop { //! Signature stop-address register + 0..16 => stop, //= BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). + 17 => sig_start { //! Start control bit for signature generation. + 0 => SIGNATURE_GENERATION, //= Signature generation is stopped + 1 => INITIATE_SIGNATURE_G, //= Initiate signature generation + } + }, + 0x2c => reg32 fmsw0 { //! Word 0 [31:0] + 0..31 => sw0_31_0: ro, //= Word 0 of 128-bit signature (bits 31 to 0). + }, + 0x30 => reg32 fmsw1 { //! Word 1 [63:32] + 0..31 => sw1_63_32: ro, //= Word 1 of 128-bit signature (bits 63 to 32). + }, + 0x34 => reg32 fmsw2 { //! Word 2 [95:64] + 0..31 => sw2_95_64: ro, //= Word 2 of 128-bit signature (bits 95 to 64). + }, + 0x38 => reg32 fmsw3 { //! Word 3 [127:96] + 0..31 => sw3_127_96: ro, //= Word 3 of 128-bit signature (bits 127 to 96). + }, + 0xfe0 => reg32 fmstat { //! Signature generation status register + 2 => sig_done: ro, //= When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag. + }, + 0xfe8 => reg32 fmstatclr { //! Signature generation status clear register + 2 => sig_done_clr: wo, //= Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. + }, +}); +ioregs! (SPI0 @ 0x40040000 = { //! SPI0 + 0x00 => reg32 cr0 { //! Control Register 0. Selects the serial clock rate, bus type, and data size. + 0..3 => dss { //! Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. + 3 => E_4_BIT_TRANSFER, //= 4-bit transfer + 4 => E_5_BIT_TRANSFER, //= 5-bit transfer + 5 => E_6_BIT_TRANSFER, //= 6-bit transfer + 6 => E_7_BIT_TRANSFER, //= 7-bit transfer + 7 => E_8_BIT_TRANSFER, //= 8-bit transfer + 8 => E_9_BIT_TRANSFER, //= 9-bit transfer + 9 => E_10_BIT_TRANSFER, //= 10-bit transfer + 10 => E_11_BIT_TRANSFER, //= 11-bit transfer + 11 => E_12_BIT_TRANSFER, //= 12-bit transfer + 12 => E_13_BIT_TRANSFER, //= 13-bit transfer + 13 => E_14_BIT_TRANSFER, //= 14-bit transfer + 14 => E_15_BIT_TRANSFER, //= 15-bit transfer + 15 => E_16_BIT_TRANSFER, //= 16-bit transfer + } + 4..5 => frf { //! Frame Format. + 0 => SPI, //= SPI + 1 => TI, //= TI + 2 => MICROWIRE, //= Microwire + } + 6 => cpol { //! Clock Out Polarity. This bit is only used in SPI mode. + 0 => LOW, //= SPI controller maintains the bus clock low between frames. + 1 => HIGH, //= SPI controller maintains the bus clock high between frames. + } + 7 => cpha { //! Clock Out Phase. This bit is only used in SPI mode. + 0 => FIRSTCLOCK, //= SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. + 1 => SECONDCLOCK, //= SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. + } + 8..15 => scr, //= Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + }, + 0x04 => reg32 cr1 { //! Control Register 1. Selects master/slave and other modes. + 0 => lbm { //! Loop Back Mode. + 0 => NORMAL, //= During normal operation. + 1 => LOOPBACK, //= Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). + } + 1 => sse { //! SPI Enable. + 0 => DISABLE, //= The SPI controller is disabled. + 1 => ENABLE, //= The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit. + } + 2 => ms { //! Master/Slave Mode.This bit can only be written when the SSE bit is 0. + 0 => MASTER, //= The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. + 1 => SLAVE, //= The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. + } + 3 => sod, //= Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). + }, + 0x08 => reg32 dr { //! Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + 0..15 => data, //= Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. + }, + 0x0c => reg32 sr { //! Status Register + 0 => tfe: ro, //= Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + 1 => tnf: ro, //= Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + 2 => rne: ro, //= Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + 3 => rff: ro, //= Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + 4 => bsy: ro, //= Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + }, + 0x10 => reg32 cpsr { //! Clock Prescale Register + 0..7 => cpsdvsr, //= This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. + }, + 0x14 => reg32 imsc { //! Interrupt Mask Set and Clear Register + 0 => rorim, //= Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + 1 => rtim, //= Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + 2 => rxim, //= Software should set this bit to enable interrupt when the Rx FIFO is at least half full. + 3 => txim, //= Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + }, + 0x18 => reg32 ris { //! Raw Interrupt Status Register + 0 => rorris: ro, //= This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + 1 => rtris: ro, //= This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + 2 => rxris: ro, //= This bit is 1 if the Rx FIFO is at least half full. + 3 => txris: ro, //= This bit is 1 if the Tx FIFO is at least half empty. + }, + 0x1c => reg32 mis { //! Masked Interrupt Status Register + 0 => rormis: ro, //= This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. + 1 => rtmis: ro, //= This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + 2 => rxmis: ro, //= This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. + 3 => txmis: ro, //= This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + }, + 0x20 => reg32 icr { //! SSPICR Interrupt Clear Register + 0 => roric: wo, //= Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. + 1 => rtic: wo, //= Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + }, +}); +ioregs! (IOCON @ 0x40044000 = { //! Product name title=UM10398 Chapter title=LPC1100XL series: I/O configuration (IOCONFIG) Modification date=2/22/2012 Major revision=8 Minor revision=not available + 0x00 => reg32 iocon_pio2_6 { //! I/O configuration for pin PIO2_6/ CT32B0_MAT1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_6. + 1 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x08 => reg32 iocon_pio2_0 { //! I/O configuration for pin PIO2_0/DTR/SSEL1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_0. + 1 => SELECT_FUNCTION_DTR_, //= Select function DTR. + 2 => SELECT_FUNCTION_SSEL, //= Select function SSEL1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x0c => reg32 iocon_reset_pio0_0 { //! I/O configuration for pin RESET/PIO0_0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_RES, //= Selects function RESET. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x10 => reg32 iocon_pio0_1 { //! I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_1. + 1 => SELECTS_FUNCTION_CLK, //= Selects function CLKOUT. + 2 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT2. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x14 => reg32 iocon_pio1_8 { //! I/O configuration for pin PIO1_8/CT16B1_CAP0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_8. + 1 => SELECTS_FUNCTION_CT1, //= Selects function CT16B1_CAP0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x1c => reg32 iocon_pio0_2 { //! I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_2. + 1 => SELECTS_FUNCTION_SSE, //= Selects function SSEL0. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_CAP0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x20 => reg32 iocon_pio2_7 { //! I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_7. + 1 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT2. + 2 => SELECTS_FUNCTION_RXD, //= Selects function RXD. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x24 => reg32 iocon_pio2_8 { //! I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_8. + 1 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT3. + 2 => SELECTS_FUNCTION_TXD, //= Selects function TXD. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x28 => reg32 iocon_pio2_1 { //! I/O configuration for pin PIO2_1/DSR/SCK1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_1. + 1 => SELECT_FUNCTION_DSR_, //= Select function DSR. + 2 => SELECT_FUNCTION_SCK1, //= Select function SCK1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x2c => reg32 iocon_pio0_3 { //! I/O configuration for pin PIO0_3 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_3. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x30 => reg32 iocon_pio0_4 { //! I/O configuration for pin PIO0_4/SCL + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_4 (open-drain pin). + 1 => SELECTS_I2C_FUNCTION, //= Selects I2C function SCL (open-drain pin). + } + 8..9 => i2cmode { //! Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). + 0 => STANDARD_MODE_FAST, //= Standard mode/ Fast-mode I2C. + 1 => STANDARD_IO_FUNCTION, //= Standard I/O functionality + 2 => FAST_MODE_PLUS_I2C, //= Fast-mode Plus I2C + } + }, + 0x34 => reg32 iocon_pio0_5 { //! I/O configuration for pin PIO0_5/SDA + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_5 (open-drain pin). + 1 => SELECTS_I2C_FUNCTION, //= Selects I2C function SDA (open-drain pin). + } + 8..9 => i2cmode { //! Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). + 0 => STANDARD_MODE_FAST, //= Standard mode/ Fast-mode I2C. + 1 => STANDARD_IO_FUNCTION, //= Standard I/O functionality + 2 => FAST_MODE_PLUS_I2C, //= Fast-mode Plus I2C + } + }, + 0x38 => reg32 iocon_pio1_9 { //! I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_9. + 1 => SELECTS_FUNCTION_CT1, //= Selects function CT16B1_MAT0. + 2 => SELECTS_FUNCTION_MOS, //= Selects function MOSI1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x3c => reg32 iocon_pio3_4 { //! I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO3_4. + 1 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_CAP1. + 2 => SELECTS_FUNCTION_RXD, //= Selects function RXD. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x40 => reg32 iocon_pio2_4 { //! I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_4. + 1 => SELECTS_FUNCTION_CT1, //= Selects function CT16B1_MAT1. + 2 => SELECTS_FUNCTION_SSE, //= Selects function SSEL1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x44 => reg32 iocon_pio2_5 { //! I/O configuration for pin PIO2_5/ CT32B0_MAT0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_5. + 1 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x48 => reg32 iocon_pio3_5 { //! I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO3_5. + 1 => SELECTS_FUNCTION_CT1, //= Selects function CT16B1_CAP1. + 2 => SELECTS_FUNCTION_TXD, //= Selects function TXD. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x4c => reg32 iocon_pio0_6 { //! I/O configuration for pin PIO0_6/SCK0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_6. + 2 => SELECTS_FUNCTION_SCK, //= Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147). + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x50 => reg32 iocon_pio0_7 { //! I/O configuration for pin PIO0_7/CTS + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_7. + 1 => SELECT_FUNCTION_CTS_, //= Select function CTS. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x54 => reg32 iocon_pio2_9 { //! I/O configuration for pin PIO2_9/ CT32B0_CAP0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_9. + 1 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_CAP0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x58 => reg32 iocon_pio2_10 { //! I/O configuration for pin PIO2_10 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_10. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x5c => reg32 iocon_pio2_2 { //! I/O configuration for pin PIO2_2/DCD/MISO1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_2. + 1 => SELECT_FUNCTION_DCD_, //= Select function DCD. + 2 => SELECT_FUNCTION_MISO, //= Select function MISO1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x60 => reg32 iocon_pio0_8 { //! I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_8. + 1 => SELECTS_FUNCTION_MIS, //= Selects function MISO0. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_MAT0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x64 => reg32 iocon_pio0_9 { //! I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_9. + 1 => SELECTS_FUNCTION_MOS, //= Selects function MOSI0. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_MAT1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x68 => reg32 iocon_swclk_pio0_10 { //! I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_SWC, //= Selects function SWCLK. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_10. + 2 => SELECTS_FUNCTION_SCK, //= Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 147). + 3 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_MAT2. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x6c => reg32 iocon_pio1_10 { //! I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_10. + 1 => SELECTS_FUNCTION_AD6, //= Selects function AD6. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B1_MAT1. + 3 => SELECTS_FUNCTION_MIS, //= Selects function MISO1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x70 => reg32 iocon_pio2_11 { //! I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_11. + 1 => SELECT_FUNCTION_SCK0, //= Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147). + 2 => SELECT_FUNCTION_CT32, //= Select function CT32B0_CAP1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x74 => reg32 iocon_r_pio0_11 { //! I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_R_, //= Selects function R. This function is reserved. Select one of the alternate functions below. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO0_11. + 2 => SELECTS_FUNCTION_AD0, //= Selects function AD0. + 3 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT3. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x78 => reg32 iocon_r_pio1_0 { //! I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_R_, //= Selects function R. This function is reserved. Select one of the alternate functions below. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_0. + 2 => SELECTS_FUNCTION_AD1, //= Selects function AD1. + 3 => SELECTS_FUNCTION_CT3, //= Selects function CT32B1_CAP0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x7c => reg32 iocon_r_pio1_1 { //! I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_R_, //= Selects function R. This function is reserved. Select one of the alternate functions below. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_1. + 2 => SELECTS_FUNCTION_AD2, //= Selects function AD2. + 3 => SELECTS_FUNCTION_CT3, //= Selects function CT32B1_MAT0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x80 => reg32 iocon_r_pio1_2 { //! I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_R_, //= Selects function R. This function is reserved. Select one of the alternate functions below. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_2. + 2 => SELECTS_FUNCTION_AD3, //= Selects function AD3. + 3 => SELECTS_FUNCTION_CT3, //= Selects function CT32B1_MAT1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x84 => reg32 iocon_pio3_0 { //! I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO3_0. + 1 => SELECTS_FUNCTION_DTR, //= Selects function DTR. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_MAT0. + 3 => SELECTS_FUNCTION_TXD, //= Selects function TXD. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x88 => reg32 iocon_pio3_1 { //! I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO3_1. + 1 => SELECTS_FUNCTION_DSR, //= Selects function DSR. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_MAT1. + 3 => SELECTS_FUNCTION_RXD, //= Selects function RXD. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x8c => reg32 iocon_pio2_3 { //! I/O configuration for pin PIO2_3/RI/MOSI1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO2_3. + 1 => SELECTS_FUNCTION_RI_, //= Selects function RI. + 2 => SELECTS_FUNCTION_MOS, //= Selects function MOSI1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x90 => reg32 iocon_swdio_pio1_3 { //! I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_SWD, //= Selects function SWDIO. + 1 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_3. + 2 => SELECTS_FUNCTION_AD4, //= Selects function AD4. + 3 => SELECTS_FUNCTION_CT3, //= Selects function CT32B1_MAT2. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x94 => reg32 iocon_pio1_4 { //! I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 + 0..2 => func { //! Selects pin function. This pin functions as WAKEUP pin if the LPC111x/LPC11Cxx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_4. + 1 => SELECTS_FUNCTION_AD5, //= Selects function AD5. + 2 => SELECTS_FUNCTION_CT3, //= Selects function CT32B1_MAT3. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x98 => reg32 iocon_pio1_11 { //! I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_11. + 1 => SELECTS_FUNCTION_AD7, //= Selects function AD7. + 2 => SELECTS_FUNCTION_CT3, //= Selects function CT32B1_CAP1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 7 => admode { //! Selects Analog/Digital mode + 0 => ANALOG_INPUT_MODE, //= Analog input mode + 1 => DIGITAL_FUNCTIONAL_M, //= Digital functional mode + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0x9c => reg32 iocon_pio3_2 { //! I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO3_2. + 1 => SELECTS_FUNCTION_DCD, //= Selects function DCD. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_MAT2. + 3 => SELECTS_FUNCTION_SCK, //= Selects function SCK1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0xa0 => reg32 iocon_pio1_5 { //! I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_5. + 1 => SELECTS_FUNCTION_RTS, //= Selects function RTS. + 2 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_CAP0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0xa4 => reg32 iocon_pio1_6 { //! I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_6. + 1 => SELECTS_FUNCTION_RXD, //= Selects function RXD. + 2 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0xa8 => reg32 iocon_pio1_7 { //! I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO1_7. + 1 => SELECTS_FUNCTION_TXD, //= Selects function TXD. + 2 => SELECTS_FUNCTION_CT3, //= Selects function CT32B0_MAT1. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0xac => reg32 iocon_pio3_3 { //! I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0 + 0..2 => func { //! Selects pin function. All other values are reserved. + 0 => SELECTS_FUNCTION_PIO, //= Selects function PIO3_3. + 1 => SELECTS_FUNCTION_RI_, //= Selects function RI. + 2 => SELECTS_FUNCTION_CT1, //= Selects function CT16B0_CAP0. + } + 3..4 => mode { //! Selects function mode (on-chip pull-up/pull-down resistor control). + 0 => INACTIVE_NO_PULL_DO, //= Inactive (no pull-down/pull-up resistor enabled). + 1 => PULL_DOWN_RESISTOR_E, //= Pull-down resistor enabled. + 2 => PULL_UP_RESISTOR_ENA, //= Pull-up resistor enabled. + 3 => REPEATER_MODE_, //= Repeater mode. + } + 5 => hys { //! Hysteresis. + 0 => DISABLE_, //= Disable. + 1 => ENABLE_, //= Enable. + } + 10 => od { //! Selects pseudo open-drain mode. + 0 => STANDARD_GPIO_OUTPUT, //= Standard GPIO output + 1 => OPEN_DRAIN_OUTPUT, //= Open-drain output + } + }, + 0xb0 => reg32 iocon_sck0_loc { //! SCK0 pin location select register + 0..1 => sckloc { //! Selects pin location for SCK0 function. + 0 => SELECTS_SCK0_FUNCTIO_PIO0_10, //= Selects SCK0 function in pin location SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 129). + 1 => SELECTS_SCK0_FUNCTIO_PIO2_11, //= Selects SCK0 function in pin location PIO2_11/SCK0 (see Table 131). + 2 => SELECTS_SCK0_FUNCTIO_PIO0_6, //= Selects SCK0 function in pin location PIO0_6/SCK0 (see Table 122). + } + }, + 0xb4 => reg32 iocon_dsr_loc { //! DSR pin location select register + 0..1 => dsrloc { //! Selects pin location for DSR function. + 0 => SELECTS_DSR_FUNCTIO_PIO2_1, //= Selects DSR function in pin location PIO2_1/DSR/SCK1 (see Table 113). + 1 => SELECTS_DSR_FUNCTION_PIO3_1, //= Selects DSR function in pin location PIO3_1/DSR (see Table 137). + } + }, + 0xb8 => reg32 iocon_dcd_loc { //! DCD pin location select register + 0..1 => dcdloc { //! Selects pin location for DCD function. + 0 => SELECTS_DCD_FUNCTIO_PIO2_2, //= Selects DCD function in pin location PIO2_2/DCD/MISO1 (see Table 126). + 1 => SELECTS_DCD_FUNCTION_PIO3_2, //= Selects DCD function in pin location PIO3_2/DCD (see Table 142). + } + }, + 0xbc => reg32 iocon_ri_loc { //! RI pin location select register + 0..1 => riloc { //! Selects pin location for RI function. + 0 => SELECTS_RI_FUNCTION_PIO2_3, //= Selects RI function in pin location PIO2_3/RI/MOSI1 (see Table 138). + 1 => SELECTS_RI_FUNCTION_PIO3_3, //= Selects RI function in pin location PIO3_3/RI (see Table 146). + } + }, + 0x18 => reg32 iocon_ssel1_loc { //! SSEL1 pin location select register + 0..1 => ssel1loc { //! Selects pin location for SSEL1 function. + 0 => SELECTS_SSEL1_FUNCTI_PIO2_2, //= Selects SSEL1 function in pin location PIO2_2/DCD/MISO1 (see Table 126). + 1 => SELECTS_SSEL1_FUNCTI_PIO2_4, //= Selects SSEL1 function in pin location PIO2_4/CT16B1_MAT1/SSEL1 (see Table 119). + } + }, + 0xc0 => reg32 iocon_ct16b0_cap0_loc { //! CT16B0_CAP0 pin location select register + 0..1 => ct16b0_cap0loc { //! Selects pin location for CT16B0_CAP0 function. + 0 => SELECTS_CT16B0_CAP0_PIO0_2, //= Selects CT16B0_CAP0 function in pin location PIO0_2/SSEL0/CT16B0_CAP0 (see Table 110). + 1 => SELECTS_CT16B0_CAP0_PIO3_3, //= Selects CT16B0_CAP0 function in pin location PIO3_3/RI/CT16B0 (see Table 146). + } + }, + 0xc4 => reg32 iocon_sck1_loc { //! SCK1 pin location select register + 0..1 => sck1loc { //! Selects pin location for SCK1 function. + 0 => SELECTS_SCK1_FUNCTIO_PIO2_1, //= Selects SCK1 function in pin location PIO2_1/DSR/SCK1 (see Table 113). + 1 => SELECTS_SCK1_FUNCTIO_PIO3_2, //= Selects SCK1 function in pin location PIO3_2/DCD/CT16B0_MAT2/SCK1 (see Table 142). + } + }, + 0xc8 => reg32 iocon_miso1_loc { //! MISO1 pin location select register + 0..1 => miso1loc { //! Selects pin location for the MISO1 function. + 0 => SELECTS_MISO1_FUNCTI_PIO2_2, //= Selects MISO1 function in pin location PIO2_2/DCD/MISO1 (see Table 126). + 1 => SELECTS_MISO1_FUNCTI_PIO1_10, //= Selects MISO1 function in pin location PIO1_10/AD6/CT16B1_MAT1/MISO1 (see Table 130). + } + }, + 0xcc => reg32 iocon_mosi1_loc { //! MOSI1 pin location select register + 0..1 => mosi1loc { //! Selects pin location for the MOSI1 function. + 0 => SELECTS_MOSI1_FUNCTI_PIO2_3, //= Selects MOSI1 function in pin location PIO2_3/RI/MOSI1 (see Table 138). + 1 => SELECTS_MOSI1_FUNCTI_PIO1_9, //= Selects MOSI1 function in pin location PIO1_9/CT16B1_MAT0/MOSI1 (see Table 117). + } + }, + 0xd0 => reg32 iocon_ct32b0_cap0_loc { //! CT32B0_CAP0 pin location select register + 0..1 => ct32b0_cap0loc { //! Selects pin location for the CT32B0_CAP0 function. + 0 => SELECTS_CT32B0_CAP0_PIO1_5, //= Selects CT32B0_CAP0 function in pin location PIO1_5/RTS/CT32B0_CAP0 (see Table 143). + 1 => SELECTS_CT32B0_CAP0_PIO2_9, //= Selects CT32B0_CAP0 function in pin location PIO2_9/CT32B0_CAP0 (Table 124). + } + }, + 0xd4 => reg32 iocon_rxd_loc { //! RXD pin location select register + 0..1 => rxdloc { //! Selects pin location for the RXD function. + 0 => SELECTS_RXD_FUNCTION_PIO1_6, //= Selects RXD function in pin location PIO1_6/RXD/CT32B0_MAT0 (see Table 144). + 1 => SELECTS_RXD_FUNCTION_PIO2_7, //= Selects RXD function in pin location PIO2_7/CT32B0_MAT2/RXD (see Table 111). + 2 => SELECTS_RXD_FUNCTION_PIO3_1, //= Selects RXD function in pin location PIO3_1/DSR/CT16B0_MAT1/RXD (see Table 137). + 3 => SELECTS_RXD_FUNCTION_PIO3_4, //= Selects RXD function in pin location PIO3_4/CT16B0_CAP1/RXD (see Table 118). + } + }, +}); +ioregs! (SYSCON @ 0x40048000 = { //! Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx System configuration (SYSCON) Modification date=2/22/2012 Major revision=8 Minor revision=not available + 0x00 => reg32 sysmemremap { //! System memory remap + 0..1 => map { //! System memory remap + 0 => BOOT_LOADER_MODE_IN, //= Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. + 1 => USER_RAM_MODE_INTER, //= User RAM Mode. Interrupt vectors are re-mapped to Static RAM. + 2 => USER_FLASH_MODE_INT, //= User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. + } + }, + 0x04 => reg32 presetctrl { //! Peripheral reset control + 0 => ssp0_rst_n { //! SPI0 reset control + 0 => SPIO0RESET, //= Resets the SPI0 peripheral. + 1 => SPIO0NORESET, //= SPI0 reset de-asserted. + } + 1 => i2c_rst_n { //! I2C reset control + 0 => I2CRESET, //= Resets the I2C peripheral. + 1 => I2CNORESET, //= I2C reset de-asserted. + } + 2 => ssp1_rst_n { //! SPI1 reset control + 0 => SPI1RESET, //= Resets the SPI1 peripheral. + 1 => SPI2NORESET, //= SPI1 reset de-asserted. + } + 3 => can_rst_n { //! C_CAN reset control. See Section 3.1 for part specific details. + 0 => CANRESET, //= Resets the C_CAN peripheral. + 1 => CANNORESET, //= C_CAN reset de-asserted. + } + }, + 0x08 => reg32 syspllctrl { //! System PLL control + 0..4 => msel, //= Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32. + 5..6 => psel { //! Post divider ratio P. The division ratio is 2 x P. + 0 => P_EQ_1, //= P = 1 + 1 => P_EQ_2, //= P = 2 + 2 => P_EQ_4, //= P = 4 + 3 => P_EQ_8, //= P = 8 + } + }, + 0x0c => reg32 syspllstat { //! System PLL status + 0 => lock: ro { //! PLL lock status + 0 => PLL_NOT_LOCKED, //= PLL not locked + 1 => PLL_LOCKED, //= PLL locked + } + }, + 0x20 => reg32 sysoscctrl { //! System oscillator control + 0 => bypass { //! Bypass system oscillator + 0 => NOBYPASS, //= Oscillator is not bypassed. + 1 => BYPASS_ENABLED_PLL_, //= Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins. + } + 1 => freqrange { //! Determines frequency range for Low-power oscillator. + 0 => LOW, //= 1 - 20 MHz frequency range. + 1 => HIGH, //= 15 - 25 MHz frequency range + } + }, + 0x24 => reg32 wdtoscctrl { //! Watchdog oscillator control + 0..4 => divsel, //= Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 + 5..8 => freqsel { //! Select watchdog oscillator analog output frequency (Fclkana). + 1 => E_0_5_MHZ, //= 0.5 MHz + 2 => E_0_8_MHZ, //= 0.8 MHz + 3 => E_1_1_MHZ, //= 1.1 MHz + 4 => E_1_4_MHZ, //= 1.4 MHz + 5 => E_1_6_MHZ, //= 1.6 MHz + 6 => E_1_8_MHZ, //= 1.8 MHz + 7 => E_2_0_MHZ, //= 2.0 MHz + 8 => E_2_2_MHZ, //= 2.2 MHz + 9 => E_2_4_MHZ, //= 2.4 MHz + 10 => E_2_6_MHZ, //= 2.6 MHz + 11 => E_2_7_MHZ, //= 2.7 MHz + 12 => E_2_9_MHZ, //= 2.9 MHz + 13 => E_3_1_MHZ, //= 3.1 MHz + 14 => E_3_2_MHZ, //= 3.2 MHz + 15 => E_3_4_MHZ, //= 3.4 MHz + } + }, + 0x28 => reg32 ircctrl { //! IRC control + 0..7 => trim, //= Trim value + }, + 0x30 => reg32 sysrststat { //! System reset status register + 0 => por: ro { //! POR reset status + 0 => NO_POR_DETECTED_, //= No POR detected. + 1 => POR_DETECTED_WRITIN, //= POR detected. Writing a one clears this reset. + } + 1 => extrst: ro { //! Status of the external RESET pin. + 0 => NO_RESET_EVENT_DETEC, //= No RESET event detected. + 1 => RESET_DETECTED_WRIT, //= RESET detected. Writing a one clears this reset. + } + 2 => wdt: ro { //! Status of the Watchdog reset + 0 => NO_WDT_RESET_DETECTE, //= No WDT reset detected. + 1 => WDT_RESET_DETECTED_, //= WDT reset detected. Writing a one clears this reset. + } + 3 => bod: ro { //! Status of the Brown-out detect reset + 0 => NO_BOD_RESET_DETECTE, //= No BOD reset detected. + 1 => BOD_RESET_DETECTED_, //= BOD reset detected. Writing a one clears this reset. + } + 4 => sysrst: ro { //! Status of the software system reset + 0 => NO_SYSTEM_RESET_DETE, //= No System reset detected. + 1 => SYSTEM_RESET_DETECTE, //= System reset detected. Writing a one clears this reset. + } + }, + 0x40 => reg32 syspllclksel { //! System PLL clock source select + 0..1 => sel { //! System PLL clock source + 0 => IRC_OSCILLATOR, //= IRC oscillator + 1 => SYSTEM_OSCILLATOR, //= System oscillator + } + }, + 0x44 => reg32 syspllclkuen { //! System PLL clock source update enable + 0 => ena { //! Enable system PLL clock source update + 0 => NO_CHANGE, //= No change + 1 => UPDATE_CLOCK_SOURCE, //= Update clock source + } + }, + 0x70 => reg32 mainclksel { //! Main clock source select + 0..1 => sel { //! Clock source for main clock + 0 => IRC_OSCILLATOR, //= IRC oscillator + 1 => INPUT_CLOCK_TO_SYSTE, //= Input clock to system PLL + 2 => WDT_OSCILLATOR, //= WDT oscillator + 3 => SYSTEM_PLL_CLOCK_OUT, //= System PLL clock out + } + }, + 0x74 => reg32 mainclkuen { //! Main clock source update enable + 0 => ena { //! Enable main clock source update + 0 => NO_CHANGE, //= No change + 1 => UPDATE_CLOCK_SOURCE, //= Update clock source + } + }, + 0x78 => reg32 sysahbclkdiv { //! System AHB clock divider + 0..7 => div, //= System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. + }, + 0x80 => reg32 sysahbclkctrl { //! System AHB clock control + 0 => sys { //! Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only. + 1 => ENABLE, //= Enable + } + 1 => rom { //! Enables clock for ROM. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 2 => ram { //! Enables clock for RAM. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 3 => flashreg { //! Enables clock for flash register interface. + 0 => DISABLED, //= Disabled + 1 => ENABLED, //= Enabled + } + 4 => flasharray { //! Enables clock for flash array access. + 0 => DISABLED, //= Disabled + 1 => ENABLED, //= Enabled + } + 5 => i2c { //! Enables clock for I2C. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 6 => gpio { //! Enables clock for GPIO. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 7 => ct16b0 { //! Enables clock for 16-bit counter/timer 0. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 8 => ct16b1 { //! Enables clock for 16-bit counter/timer 1. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 9 => ct32b0 { //! Enables clock for 32-bit counter/timer 0. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 10 => ct32b1 { //! Enables clock for 32-bit counter/timer 1. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 11 => ssp0 { //! Enables clock for SPI0. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 12 => uart { //! Enables clock for UART. See Section 3.1 for part specific details. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 13 => adc { //! Enables clock for ADC. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 15 => wdt { //! Enables clock for WDT. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 16 => iocon { //! Enables clock for I/O configuration block. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 17 => can { //! Enables clock for C_CAN. See Section 3.1 for part specific details. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + 18 => ssp1 { //! Enables clock for SPI1. + 0 => DISABLE, //= Disable + 1 => ENABLE, //= Enable + } + }, + 0x94 => reg32 ssp0clkdiv { //! SPI0 clock divider + 0..7 => div, //= SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255. + }, + 0x98 => reg32 uartclkdiv { //! UART clock divder + 0..7 => div, //= UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. + }, + 0x9c => reg32 ssp1clkdiv { //! SPI1 clock divder + 0..7 => div, //= SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255. + }, + 0xd0 => reg32 wdtclksel { //! WDT clock source select + 0..1 => sel { //! WDT clock source + 0 => IRC_OSCILLATOR, //= IRC oscillator + 1 => MAIN_CLOCK, //= Main clock + 2 => WATCHDOG_OSCILLATOR, //= Watchdog oscillator + } + }, + 0xd4 => reg32 wdtclkuen { //! WDT clock source update enable + 0 => ena { //! Enable WDT clock source update + 0 => NO_CHANGE, //= No change + 1 => UPDATE_CLOCK_SOURCE, //= Update clock source + } + }, + 0xd8 => reg32 wdtclkdiv { //! WDT clock divider + 0..7 => div, //= WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255. + }, + 0xe0 => reg32 clkoutclksel { //! CLKOUT clock source select + 0..1 => sel { //! CLKOUT clock source + 0 => IRC_OSCILLATOR, //= IRC oscillator + 1 => SYSTEM_OSCILLATOR, //= System oscillator + 2 => WATCHDOG_OSCILLATOR, //= Watchdog oscillator + 3 => MAIN_CLOCK, //= Main clock + } + }, + 0xe4 => reg32 clkoutuen { //! CLKOUT clock source update enable + 0 => ena { //! Enable CLKOUT clock source update + 0 => NO_CHANGE, //= No change + 1 => UPDATE_CLOCK_SOURCE, //= Update clock source + } + }, + 0xe8 => reg32 clkoutclkdiv { //! CLKOUT clock divider + 0..7 => div, //= Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255. + }, + 0x100 => reg32 pioporcap0 { //! POR captured PIO status 0 + 0..11 => cappio0_n: ro, //= Raw reset status input PIO0_n: PIO0_11 to PIO0_0 + 12..23 => cappio1_n: ro, //= Raw reset status input PIO1_n: PIO1_11 to PIO1_0 + 24..31 => cappio2_n: ro, //= Raw reset status input PIO2_n: PIO2_7 to PIO2_0 + }, + 0x104 => reg32 pioporcap1 { //! POR captured PIO status 1 + 0 => cappio2_8: ro, //= Raw reset status input PIO2_8 + 1 => cappio2_9: ro, //= Raw reset status input PIO2_9 + 2 => cappio2_10: ro, //= Raw reset status input PIO2_10 + 3 => cappio2_11: ro, //= Raw reset status input PIO2_11 + 4 => cappio3_0: ro, //= Raw reset status input PIO3_0 + 5 => cappio3_1: ro, //= Raw reset status input PIO3_1 + 6 => cappio3_2: ro, //= Raw reset status input PIO3_2 + 7 => cappio3_3: ro, //= Raw reset status input PIO3_3 + 8 => cappio3_4: ro, //= Raw reset status input PIO3_4 + 9 => cappio3_5: ro, //= Raw reset status input PIO3_5 + }, + 0x150 => reg32 bodctrl { //! BOD control + 0..1 => bodrstlev { //! BOD reset level + 0 => LEVEL_0_THE_RESET_A, //= Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V. + 1 => LEVEL_1_THE_RESET_A, //= Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V. + 2 => LEVEL_2_THE_RESET_A, //= Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V. + 3 => LEVEL_3_THE_RESET_A, //= Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V. + } + 2..3 => bodintval { //! BOD interrupt level + 0 => LEVEL_0_THE_INTERRU, //= Level 0: The interrupt assertion threshold voltage is 1.65 V; the interrupt de-assertion threshold voltage is 1.80 V. + 1 => LEVEL_1THE_INTERRUP, //= Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V. + 2 => LEVEL_2_THE_INTERRU, //= Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V. + 3 => LEVEL_3_THE_INTERRU, //= Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V. + } + 4 => bodrstena { //! BOD reset enable + 0 => DISABLE_RESET_FUNCTI, //= Disable reset function. + 1 => ENABLE_RESET_FUNCTIO, //= Enable reset function. + } + }, + 0x154 => reg32 systckcal { //! System tick counter calibration + 0..25 => cal, //= System tick timer calibration value + }, + 0x174 => reg32 nmisrc { //! NMI source selection + 0..4 => irqno, //= The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers. + 31 => nmien, //= Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. + }, + 0x200 => reg32 startaprp0 { //! Start logic edge control register 0 + 0 => aprpio0_0, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 1 => aprpio0_1, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 2 => aprpio0_2, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 3 => aprpio0_3, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 4 => aprpio0_4, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 5 => aprpio0_5, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 6 => aprpio0_6, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 7 => aprpio0_7, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 8 => aprpio0_8, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 9 => aprpio0_9, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 10 => aprpio0_10, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 11 => aprpio0_11, //= Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge + 12 => aprpio1_0, //= Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge + }, + 0x204 => reg32 starterp0 { //! Start logic signal enable register 0 + 0 => erpio0_0, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 1 => erpio0_1, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 2 => erpio0_2, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 3 => erpio0_3, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 4 => erpio0_4, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 5 => erpio0_5, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 6 => erpio0_6, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 7 => erpio0_7, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 8 => erpio0_8, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 9 => erpio0_9, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 10 => erpio0_10, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 11 => erpio0_11, //= Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled + 12 => erpio1_0, //= Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled + }, + 0x208 => reg32 startrsrp0clr { //! Start logic reset register 0 + 0 => rsrpio0_0: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 1 => rsrpio0_1: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 2 => rsrpio0_2: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 3 => rsrpio0_3: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 4 => rsrpio0_4: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 5 => rsrpio0_5: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 6 => rsrpio0_6: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 7 => rsrpio0_7: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 8 => rsrpio0_8: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 9 => rsrpio0_9: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 10 => rsrpio0_10: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 11 => rsrpio0_11: wo, //= Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + 12 => rsrpio1_0: wo, //= Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal. + }, + 0x20c => reg32 startsrp0 { //! Start logic status register 0 + 0 => srpio0_0: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 1 => srpio0_1: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 2 => srpio0_2: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 3 => srpio0_3: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 4 => srpio0_4: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 5 => srpio0_5: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 6 => srpio0_6: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 7 => srpio0_7: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 8 => srpio0_8: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 9 => srpio0_9: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 10 => srpio0_10: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 11 => srpio0_11: ro, //= Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending. + 12 => srpio1_0: ro, //= Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending. + }, + 0x230 => reg32 pdsleepcfg { //! Power-down states in Deep-sleep mode + 0..2 => notused0, //= Reserved. Always write these bits as 111. + 3 => bod_pd { //! BOD power-down control in Deep-sleep mode, see Table 40. + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 4..5 => notused1, //= Reserved. Always write these bits as 11. + 6 => wdtosc_pd { //! Watchdog oscillator power control in Deep-sleep mode, see Table 40. + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 7 => notused2, //= Reserved. Always write this bit as 1. + 8..10 => notused3, //= Reserved. Always write these bits as 000. + 11..12 => notused4, //= Reserved. Always write these bits as 11. + }, + 0x234 => reg32 pdawakecfg { //! Power-down states after wake-up from Deep-sleep mode + 0 => ircout_pd { //! IRC oscillator output wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 1 => irc_pd { //! IRC oscillator power-down wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 2 => flash_pd { //! Flash wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 3 => bod_pd { //! BOD wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 4 => adc_pd { //! ADC wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 5 => sysosc_pd { //! System oscillator wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 6 => wdtosc_pd { //! Watchdog oscillator wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 7 => syspll_pd { //! System PLL wake-up configuration + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 8 => notused0, //= Reserved. Always write this bit as 1. + 9 => notused1, //= Reserved. Always write this bit as 0. + 10 => notused2, //= Reserved. Always write this bit as 1. + 11 => notused3, //= Reserved. Always write this bit as 1. + 12 => notused4, //= Reserved. Always write this bit as 0. + 13..15 => notused5, //= Reserved. Always write these bits as 111. + }, + 0x238 => reg32 pdruncfg { //! Power-down configuration register + 0 => ircout_pd { //! IRC oscillator output power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 1 => irc_pd { //! IRC oscillator power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 2 => flash_pd { //! Flash power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 3 => bod_pd { //! BOD power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 4 => adc_pd { //! ADC power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 5 => sysosc_pd { //! System oscillator power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 6 => wdtosc_pd { //! Watchdog oscillator power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 7 => syspll_pd { //! System PLL power-down + 0 => POWERED, //= Powered + 1 => POWERED_DOWN, //= Powered down + } + 8 => notused0, //= Reserved. Always write this bit as 1. + 9 => notused1, //= Reserved. Always write this bit as 0. + 10 => notused2, //= Reserved. Always write this bit as 1. + 11 => notused3, //= Reserved. Always write this bit as 1. + 12 => notused4, //= Reserved. Always write this bit as 0. + 13..15 => notused5, //= Reserved. Always write these bits as 111. + }, + 0x3f4 => reg32 device_id { //! Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L. + 0..31 => deviceid: ro, //= Part ID numbers for LPC111x/LPC11Cxx parts 0x041E 502B; 0x2516 D02B = LPC1111FHN33/101 0x2516 D02B = LPC1111FHN33/102 0x0416 502B; 0x2516 902B = LPC1111FHN33/201 0x2516 902B = LPC1111FHN33/202 0x042D 502B; 0x2524 D02B = LPC1112FHN33/101 0x2524 D02B = LPC1112FHN33/102 0x0425 502B; 0x2524 902B = LPC1112FHN33/201 0x2524 902B = LPC1112FHN33/202 0x2524 902B = LPC1112FHI33/202 0x0434 502B; 0x2532 902B = LPC1113FHN33/201 0x2532 902B = LPC1113FHN33/202 0x0434 102B; 0x2532 102B = LPC1113FHN33/301 0x2532 102B = LPC1113FHN33/302 0x0434 102B; 0x2532 102B = LPC1113FBD48/301 0x2532 102B = LPC1113FBD48/302 0x0444 502B; 0x2540 902B = LPC1114FHN33/201 0x2540 902B = LPC1114FHN33/202 0x0444 102B; 0x2540 102B = LPC1114FHN33/301 0x2540 102B = LPC1114FHN33/302 0x2540 102B = LPC1114FHI33/302 0x0444 102B; 0x2540 102B = LPC1114FBD48/301 0x2540 102B = LPC1114FBD48/302 0x2540 102B = LPC11D14FBD100/302 0x1421 102B = LPC11C12/FBD48/301 0x1440 102B = LPC11C14/FBD48/301 0x1431 102B = LPC11C22/FBD48/301 0X1430 102B = LPC11C24/FBD48/301 + }, +}); +ioregs! (C_CAN @ 0x40050000 = { //! Product name title=UM10398 Chapter title=LPC111x/LPC11Cxx C_CAN controller Modification date=9/19/2011 Major revision=7 Minor revision=not available + 0x00 => reg32 cancntl { //! CAN control + 0 => init { //! Initialization + 0 => NORMAL_OPERATION_, //= Normal operation. + 1 => INITIALIZATION, //= Initialization is started. On reset, software needs to initialize the CAN controller. + } + 1 => ie { //! Module interrupt enable + 0 => DISABLE_CAN_INTERRUP, //= Disable CAN interrupts. The interrupt line is always HIGH. + 1 => ENABLE_CAN_INTERRUPT, //= Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared. + } + 2 => sie { //! Status change interrupt enable + 0 => DISABLE_STATUS_CHANG, //= Disable status change interrupts. No status change interrupt will be generated. + 1 => ENABLE_STATUS_CHANGE, //= Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. + } + 3 => eie { //! Error interrupt enable + 0 => DISABLE_ERROR_INTERR, //= Disable error interrupt. No error status interrupt will be generated. + 1 => ENABLE_ERROR_INTERRU, //= Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt. + } + 5 => dar { //! Disable automatic retransmission + 0 => ENABLED, //= Automatic retransmission of disturbed messages enabled. + 1 => DISABLED, //= Automatic retransmission disabled. + } + 6 => cce { //! Configuration change enable + 0 => NOACCESS, //= The CPU has no write access to the bit timing register. + 1 => ACCESS, //= The CPU has write access to the CANBT register while the INIT bit is one. + } + 7 => test { //! Test mode enable + 0 => NORMAL_OPERATION_, //= Normal operation. + 1 => TEST_MODE_, //= Test mode. + } + }, + 0x04 => reg32 canstat { //! Status register + 0..2 => lec { //! Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates. + 0 => NO_ERROR_, //= No error. + 1 => STUFF_ERROR, //= Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + 2 => FORM_ERROR, //= Form error: A fixed format part of a received frame has the wrong format. + 3 => ACKERROR, //= AckError: The message this CAN core transmitted was not acknowledged. + 4 => BIT1ERROR, //= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant. + 5 => BIT0ERROR, //= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed). + 6 => CRCERROR, //= CRCError: The CRC checksum was incorrect in the message received. + 7 => UNUSED, //= Unused: No CAN bus event was detected (written by the CPU). + } + 3 => txok { //! Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller. + 0 => NOTRANSMIT, //= Since this bit was reset by the CPU, no message has been successfully transmitted. + 1 => TRANSMIT, //= Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node). + } + 4 => rxok { //! Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller. + 0 => NOTRANSMIT, //= Since this bit was last reset by the CPU, no message has been successfully transmitted. + 1 => TRANSMIT, //= Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering. + } + 5 => epass { //! Error passive + 0 => ACTIVE, //= The CAN controller is in the error active state. + 1 => PASSIVE, //= The CAN controller is in the error passive state as defined in the CAN 2.0 specification. + } + 6 => ewarn { //! Warning status + 0 => BELOWWARNINGLIM, //= Both error counters are below the error warning limit of 96. + 1 => WARNINGLIM, //= At least one of the error counters in the EML has reached the error warning limit of 96. + } + 7 => boff { //! Busoff status + 0 => NOTBUSOFF, //= The CAN module is not in busoff. + 1 => BUSOFF, //= The CAN controller is in busoff state. + } + }, + 0x08 => reg32 canec { //! Error counter + 0..7 => tec_7_0: ro, //= Transmit error counter Current value of the transmit error counter (maximum value 255) + 8..14 => rec_6_0: ro, //= Receive error counter Current value of the receive error counter (maximum value 127). + 15 => rp: ro { //! Receive error passive + 0 => BELOWERRORPASSIVE, //= The receive counter is below the error passive level. + 1 => ERRORPASSIVE, //= The receive counter has reached the error passive level as defined in the CAN2.0 specification. + } + }, + 0x0c => reg32 canbt { //! Bit timing register + 0..5 => brp, //= Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63.[1] + 6..7 => sjw, //= (Re)synchronization jump width Valid programmed values are 0 to 3.[1] + 8..11 => tseg1, //= Time segment before the sample point Valid values are 1 to 15.[1] + 12..14 => tseg2, //= Time segment after the sample point Valid values are 0 to 7.[1] + }, + 0x10 => reg32 canint { //! Interrupt register + 0..15 => intid: ro, //= 0x0000 = No interrupt is pending. 0x0001 - 0x0020 = Number of message object which caused the interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 - 0xFFFF = Unused + }, + 0x14 => reg32 cantest { //! Test register + 2 => basic { //! Basic mode + 0 => BASIC_MODE_DISABLED_, //= Basic mode disabled. + 1 => TXRX, //= IF1 registers used as TX buffer, IF2 registers used as RX buffer. + } + 3 => silent { //! Silent mode + 0 => NORMAL_OPERATION_, //= Normal operation. + 1 => SILENT, //= The module is in silent mode. + } + 4 => lback { //! Loop back mode + 0 => DISABLED, //= Loop back mode is disabled. + 1 => ENABLED, //= Loop back mode is enabled. + } + 5..6 => tx { //! Control of CAN_TXD pins + 0 => LEVEL, //= Level at the CAN_TXD pin is controlled by the CAN controller. This is the value at reset. + 1 => TXD, //= The sample point can be monitored at the CAN_TXD pin. + 2 => LOW, //= CAN_TXD pin is driven LOW/dominant. + 3 => HIGH, //= CAN_TXD pin is driven HIGH/recessive. + } + 7 => rx { //! Monitors the actual value of the CAN_RXD pin. + 0 => RECESSIVE, //= The CAN bus is recessive (CAN_RXD = 1). + 1 => DORMANT, //= The CAN bus is dominant (CAN_RXD = 0). + } + }, + 0x18 => reg32 canbrpe { //! Baud rate prescaler extension register + 0..3 => brpe, //= Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0 to 15. + }, + 0x20 => reg32 canif1_cmdreq { //! Message interface command request + 0..5 => mn, //= Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1] + 15 => busy { //! BUSY flag + 0 => ZERO, //= Set to zero by hardware when read/write action to this Command request register has finished. + 1 => ONE, //= Set to one by hardware when writing to this Command request register. + } + }, + 0x80 => reg32 canif2_cmdreq { //! Message interface command request + 0..5 => mn, //= Message number 0x01 - 0x20 = Valid message numbers. The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 - 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1] + 15 => busy { //! BUSY flag + 0 => ZERO, //= Set to zero by hardware when read/write action to this Command request register has finished. + 1 => ONE, //= Set to one by hardware when writing to this Command request register. + } + }, + 0x24 => reg32 canif1_cmdmsk_w { //! Message interface command mask - write direction + 0 => data_b { //! Access data bytes 4-7 + 0 => DATA_BYTES_4_7_UNCHA, //= Data bytes 4-7 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 4-7 to message object. + } + 1 => data_a { //! Access data bytes 0-3 + 0 => DATA_BYTES_0_3_UNCHA, //= Data bytes 0-3 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 0-3 to message object. + } + 2 => txrqst { //! Access transmission request bit + 0 => NO_TRANSMISSION_REQU, //= No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored. + 1 => REQUEST_A_TRANSMISSI, //= Request a transmission. Set the TXRQST bit IF1/2_MCTRL. + } + 3 => clrintpnd, //= This bit is ignored in the write direction. + 4 => ctrl { //! Access control bits + 0 => UNCHANGED, //= Control bits unchanged. + 1 => TRANSFER_CONTROL_BIT, //= Transfer control bits to message object + } + 5 => arb { //! Access arbitration bits + 0 => UNCHANGED, //= Arbitration bits unchanged. + 1 => TRANSFER_IDENTIFIER, //= Transfer Identifier, DIR, XTD, and MSGVAL bits to message object. + } + 6 => mask { //! Access mask bits + 0 => UNCHANGED, //= Mask bits unchanged. + 1 => TRANSFER_IDENTIFIER_, //= Transfer Identifier MASK + MDIR + MXTD to message object. + } + 7 => wr_rd, //= Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ. + }, + 0x84 => reg32 canif2_cmdmsk_w { //! Message interface command mask - write direction + 0 => data_b { //! Access data bytes 4-7 + 0 => DATA_BYTES_4_7_UNCHA, //= Data bytes 4-7 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 4-7 to message object. + } + 1 => data_a { //! Access data bytes 0-3 + 0 => DATA_BYTES_0_3_UNCHA, //= Data bytes 0-3 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 0-3 to message object. + } + 2 => txrqst { //! Access transmission request bit + 0 => NO_TRANSMISSION_REQU, //= No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored. + 1 => REQUEST_A_TRANSMISSI, //= Request a transmission. Set the TXRQST bit IF1/2_MCTRL. + } + 3 => clrintpnd, //= This bit is ignored in the write direction. + 4 => ctrl { //! Access control bits + 0 => UNCHANGED, //= Control bits unchanged. + 1 => TRANSFER_CONTROL_BIT, //= Transfer control bits to message object + } + 5 => arb { //! Access arbitration bits + 0 => UNCHANGED, //= Arbitration bits unchanged. + 1 => TRANSFER_IDENTIFIER, //= Transfer Identifier, DIR, XTD, and MSGVAL bits to message object. + } + 6 => mask { //! Access mask bits + 0 => UNCHANGED, //= Mask bits unchanged. + 1 => TRANSFER_IDENTIFIER_, //= Transfer Identifier MASK + MDIR + MXTD to message object. + } + 7 => wr_rd, //= Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ. + }, + 0x24 => reg32 canif1_cmdmsk_r { //! Message interface command mask - read direction + 0 => data_b { //! Access data bytes 4-7 + 0 => UNCHANGED, //= Data bytes 4-7 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 4-7 to IFx message buffer register. + } + 1 => data_a { //! Access data bytes 0-3 + 0 => UNCHANGED, //= Data bytes 0-3 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 0-3 to IFx message buffer. + } + 2 => newdat { //! Access new data bit + 0 => UNCHANGED, //= NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits. + 1 => CLEAR_NEWDAT_BIT_IN_, //= Clear NEWDAT bit in the message object. + } + 3 => clrintpnd { //! Clear interrupt pending bit. + 0 => UNCHANGED, //= INTPND bit remains unchanged. + 1 => CLEAR_INTPND_BIT_IN_, //= Clear INTPND bit in the message object. + } + 4 => ctrl { //! Access control bits + 0 => UNCHANGED, //= Control bits unchanged. + 1 => TRANSFER_CONTROL_BIT, //= Transfer control bits to IFx message buffer. + } + 5 => arb { //! Access arbitration bits + 0 => UNCHANGED, //= Arbitration bits unchanged. + 1 => TRANSFER_IDENTIFIER, //= Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register. + } + 6 => mask { //! Access mask bits + 0 => UNCHANGED, //= Mask bits unchanged. + 1 => TRANSFER_IDENTIFIER_, //= Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register. + } + 7 => wr_rd, //= Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ. + }, + 0x84 => reg32 canif2_cmdmsk_r { //! Message interface command mask - read direction + 0 => data_b { //! Access data bytes 4-7 + 0 => UNCHANGED, //= Data bytes 4-7 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 4-7 to IFx message buffer register. + } + 1 => data_a { //! Access data bytes 0-3 + 0 => UNCHANGED, //= Data bytes 0-3 unchanged. + 1 => TRANSFER_DATA_BYTES_, //= Transfer data bytes 0-3 to IFx message buffer. + } + 2 => newdat { //! Access new data bit + 0 => UNCHANGED, //= NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits. + 1 => CLEAR_NEWDAT_BIT_IN_, //= Clear NEWDAT bit in the message object. + } + 3 => clrintpnd { //! Clear interrupt pending bit. + 0 => UNCHANGED, //= INTPND bit remains unchanged. + 1 => CLEAR_INTPND_BIT_IN_, //= Clear INTPND bit in the message object. + } + 4 => ctrl { //! Access control bits + 0 => UNCHANGED, //= Control bits unchanged. + 1 => TRANSFER_CONTROL_BIT, //= Transfer control bits to IFx message buffer. + } + 5 => arb { //! Access arbitration bits + 0 => UNCHANGED, //= Arbitration bits unchanged. + 1 => TRANSFER_IDENTIFIER, //= Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register. + } + 6 => mask { //! Access mask bits + 0 => UNCHANGED, //= Mask bits unchanged. + 1 => TRANSFER_IDENTIFIER_, //= Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register. + } + 7 => wr_rd, //= Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ. + }, + 0x28 => reg32 canif1_msk1 { //! Message interface 1 mask 1 + 0..15 => msk_15_0 { //! Identifier mask + 0 => NOINHIBIT, //= The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The corresponding identifier bit is used for acceptance filtering. + } + }, + 0x88 => reg32 canif2_msk1 { //! Message interface 1 mask 1 + 0..15 => msk_15_0 { //! Identifier mask + 0 => NOINHIBIT, //= The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The corresponding identifier bit is used for acceptance filtering. + } + }, + 0x2c => reg32 canif1_msk2 { //! Message interface 1 mask 2 + 0..12 => msk_28_16 { //! Identifier mask + 0 => NOINHIBIT, //= The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The corresponding identifier bit is used for acceptance filtering. + } + 14 => mdir { //! Mask message direction + 0 => NOEFFECT, //= The message direction bit (DIR) has no effect on acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The message direction bit (DIR) is used for acceptance filtering. + } + 15 => mxtd { //! Mask extend identifier + 0 => NOEFFECT, //= The extended identifier bit (XTD) has no effect on acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The extended identifier bit (XTD) is used for acceptance filtering. + } + }, + 0x8c => reg32 canif2_msk2 { //! Message interface 1 mask 2 + 0..12 => msk_28_16 { //! Identifier mask + 0 => NOINHIBIT, //= The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The corresponding identifier bit is used for acceptance filtering. + } + 14 => mdir { //! Mask message direction + 0 => NOEFFECT, //= The message direction bit (DIR) has no effect on acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The message direction bit (DIR) is used for acceptance filtering. + } + 15 => mxtd { //! Mask extend identifier + 0 => NOEFFECT, //= The extended identifier bit (XTD) has no effect on acceptance filtering. + 1 => ACCEPTANCEFILTERING, //= The extended identifier bit (XTD) is used for acceptance filtering. + } + }, + 0x30 => reg32 canif1_arb1 { //! Message interface 1 arbitration 1 + 0..15 => id_15_0, //= Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) + }, + 0x90 => reg32 canif2_arb1 { //! Message interface 1 arbitration 1 + 0..15 => id_15_0, //= Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) + }, + 0x34 => reg32 canif1_arb2 { //! Message interface 1 arbitration 2 + 0..12 => id_28_16, //= Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) + 13 => dir { //! Message direction + 0 => RECEIVE, //= Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + 1 => TRANSMIT, //= Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one). + } + 14 => xtd { //! Extend identifier + 0 => E_11_BIT_STANDARD_, //= The 11-bit standard identifier will be used for this message object. + 1 => E_29_BIT_EXTENDED_, //= The 29-bit extended identifier will be used for this message object. + } + 15 => msgval { //! Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required. + 0 => IGNORE, //= The message object is ignored by the message handler. + 1 => CONFIGURED, //= The message object is configured and should be considered by the message handler. + } + }, + 0x94 => reg32 canif2_arb2 { //! Message interface 1 arbitration 2 + 0..12 => id_28_16, //= Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) + 13 => dir { //! Message direction + 0 => RECEIVE, //= Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + 1 => TRANSMIT, //= Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one). + } + 14 => xtd { //! Extend identifier + 0 => E_11_BIT_STANDARD_, //= The 11-bit standard identifier will be used for this message object. + 1 => E_29_BIT_EXTENDED_, //= The 29-bit extended identifier will be used for this message object. + } + 15 => msgval { //! Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required. + 0 => IGNORE, //= The message object is ignored by the message handler. + 1 => CONFIGURED, //= The message object is configured and should be considered by the message handler. + } + }, + 0x38 => reg32 canif1_mctrl { //! Message interface 1 message control + 0..3 => dlc_3_0, //= Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes. + 7 => eob { //! End of buffer + 0 => FIFO, //= Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer. + 1 => SINGELAST, //= Single message object or last message object of a FIFO buffer. + } + 8 => txrqst { //! Transmit request + 0 => NOWAIT, //= This message object is not waiting for transmission. + 1 => WAIT, //= The transmission of this message object is requested and is not yet done + } + 9 => rmten { //! Remote enable + 0 => NOCHANGE, //= At the reception of a remote frame, TXRQST is left unchanged. + 1 => SET, //= At the reception of a remote frame, TXRQST is set. + } + 10 => rxie { //! Receive interrupt enable + 0 => NOCHANGE, //= INTPND will be left unchanged after successful reception of a frame. + 1 => SET, //= INTPND will be set after successful reception of a frame. + } + 11 => txie { //! Transmit interrupt enable + 0 => NOCHANGE, //= The INTPND bit will be left unchanged after a successful transmission of a frame. + 1 => SET, //= INTPND will be set after a successful transmission of a frame. + } + 12 => umask { //! Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1. + 0 => IGNORE, //= Mask ignored. + 1 => USEMASK, //= Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering. + } + 13 => intpnd { //! Interrupt pending + 0 => NOINTSOURCE, //= This message object is not the source of an interrupt. + 1 => INTSOURCE, //= This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + } + 14 => msglst { //! Message lost (only valid for message objects in the direction receive). + 0 => NOLOST, //= No message lost since this bit was reset last by the CPU. + 1 => NEWMESSAGE, //= The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message. + } + 15 => newdat { //! New data + 0 => NONEWDATA, //= No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU. + 1 => NEWDATA, //= The message handler or the CPU has written new data into the data portion of this message object. + } + }, + 0x98 => reg32 canif2_mctrl { //! Message interface 1 message control + 0..3 => dlc_3_0, //= Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 - 1000 = Data frame has 0 - 8 data bytes. 1001 - 1111 = Data frame has 8 data bytes. + 7 => eob { //! End of buffer + 0 => FIFO, //= Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer. + 1 => SINGELAST, //= Single message object or last message object of a FIFO buffer. + } + 8 => txrqst { //! Transmit request + 0 => NOWAIT, //= This message object is not waiting for transmission. + 1 => WAIT, //= The transmission of this message object is requested and is not yet done + } + 9 => rmten { //! Remote enable + 0 => NOCHANGE, //= At the reception of a remote frame, TXRQST is left unchanged. + 1 => SET, //= At the reception of a remote frame, TXRQST is set. + } + 10 => rxie { //! Receive interrupt enable + 0 => NOCHANGE, //= INTPND will be left unchanged after successful reception of a frame. + 1 => SET, //= INTPND will be set after successful reception of a frame. + } + 11 => txie { //! Transmit interrupt enable + 0 => NOCHANGE, //= The INTPND bit will be left unchanged after a successful transmission of a frame. + 1 => SET, //= INTPND will be set after a successful transmission of a frame. + } + 12 => umask { //! Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1. + 0 => IGNORE, //= Mask ignored. + 1 => USEMASK, //= Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering. + } + 13 => intpnd { //! Interrupt pending + 0 => NOINTSOURCE, //= This message object is not the source of an interrupt. + 1 => INTSOURCE, //= This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + } + 14 => msglst { //! Message lost (only valid for message objects in the direction receive). + 0 => NOLOST, //= No message lost since this bit was reset last by the CPU. + 1 => NEWMESSAGE, //= The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message. + } + 15 => newdat { //! New data + 0 => NONEWDATA, //= No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU. + 1 => NEWDATA, //= The message handler or the CPU has written new data into the data portion of this message object. + } + }, + 0x3c => reg32 canif1_da1 { //! Message interface 1 data A1 + 0..7 => data0, //= Data byte 0 + 8..15 => data1, //= Data byte 1 + }, + 0x9c => reg32 canif2_da1 { //! Message interface 1 data A1 + 0..7 => data0, //= Data byte 0 + 8..15 => data1, //= Data byte 1 + }, + 0x40 => reg32 canif1_da2 { //! Message interface 1 data A2 + 0..7 => data2, //= Data byte 2 + 8..15 => data3, //= Data byte 3 + }, + 0xa0 => reg32 canif2_da2 { //! Message interface 1 data A2 + 0..7 => data2, //= Data byte 2 + 8..15 => data3, //= Data byte 3 + }, + 0x44 => reg32 canif1_db1 { //! Message interface 1 data B1 + 0..7 => data4, //= Data byte 4 + 8..15 => data5, //= Data byte 5 + }, + 0xa4 => reg32 canif2_db1 { //! Message interface 1 data B1 + 0..7 => data4, //= Data byte 4 + 8..15 => data5, //= Data byte 5 + }, + 0x48 => reg32 canif1_db2 { //! Message interface 1 data B2 + 0..7 => data6, //= Data byte 6 + 8..15 => data7, //= Data byte 7 + }, + 0xa8 => reg32 canif2_db2 { //! Message interface 1 data B2 + 0..7 => data6, //= Data byte 6 + 8..15 => data7, //= Data byte 7 + }, + 0x100 => reg32 cantxreq1 { //! Transmission request 1 + 0..15 => txrqst_16_1: ro, //= Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. + }, + 0x104 => reg32 cantxreq2 { //! Transmission request 2 + 0..15 => txrqst_32_17: ro, //= Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. + }, + 0x120 => reg32 cannd1 { //! New data 1 + 0..15 => newdat_16_1: ro, //= New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object. + }, + 0x124 => reg32 cannd2 { //! New data 2 + 0..15 => newdat_32_17: ro, //= New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object. + }, + 0x140 => reg32 canir1 { //! Interrupt pending 1 + 0..15 => intpnd_16_1: ro, //= Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. + }, + 0x144 => reg32 canir2 { //! Interrupt pending 2 + 0..15 => intpnd_32_17: ro, //= Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. + }, + 0x160 => reg32 canmsgv1 { //! Message valid 1 + 0..15 => msgval_16_1: ro, //= Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. + }, + 0x164 => reg32 canmsgv2 { //! Message valid 2 + 0..15 => msgval_32_17: ro, //= Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. + }, + 0x180 => reg32 canclkdiv { //! Can clock divider register + 0..3 => clkdivval, //= Clock divider value. CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3 0010: CAN_CLK = PCLK divided by 4. ... 1111: CAN_CLK = PCLK divided by 16. + }, +}); +ioregs! (SPI1 @ 0x40058000 = { //! SPI0 + 0x00 => reg32 cr0 { //! Control Register 0. Selects the serial clock rate, bus type, and data size. + 0..3 => dss { //! Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. + 3 => E_4_BIT_TRANSFER, //= 4-bit transfer + 4 => E_5_BIT_TRANSFER, //= 5-bit transfer + 5 => E_6_BIT_TRANSFER, //= 6-bit transfer + 6 => E_7_BIT_TRANSFER, //= 7-bit transfer + 7 => E_8_BIT_TRANSFER, //= 8-bit transfer + 8 => E_9_BIT_TRANSFER, //= 9-bit transfer + 9 => E_10_BIT_TRANSFER, //= 10-bit transfer + 10 => E_11_BIT_TRANSFER, //= 11-bit transfer + 11 => E_12_BIT_TRANSFER, //= 12-bit transfer + 12 => E_13_BIT_TRANSFER, //= 13-bit transfer + 13 => E_14_BIT_TRANSFER, //= 14-bit transfer + 14 => E_15_BIT_TRANSFER, //= 15-bit transfer + 15 => E_16_BIT_TRANSFER, //= 16-bit transfer + } + 4..5 => frf { //! Frame Format. + 0 => SPI, //= SPI + 1 => TI, //= TI + 2 => MICROWIRE, //= Microwire + } + 6 => cpol { //! Clock Out Polarity. This bit is only used in SPI mode. + 0 => LOW, //= SPI controller maintains the bus clock low between frames. + 1 => HIGH, //= SPI controller maintains the bus clock high between frames. + } + 7 => cpha { //! Clock Out Phase. This bit is only used in SPI mode. + 0 => FIRSTCLOCK, //= SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. + 1 => SECONDCLOCK, //= SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. + } + 8..15 => scr, //= Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). + }, + 0x04 => reg32 cr1 { //! Control Register 1. Selects master/slave and other modes. + 0 => lbm { //! Loop Back Mode. + 0 => NORMAL, //= During normal operation. + 1 => LOOPBACK, //= Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). + } + 1 => sse { //! SPI Enable. + 0 => DISABLE, //= The SPI controller is disabled. + 1 => ENABLE, //= The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit. + } + 2 => ms { //! Master/Slave Mode.This bit can only be written when the SSE bit is 0. + 0 => MASTER, //= The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. + 1 => SLAVE, //= The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. + } + 3 => sod, //= Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). + }, + 0x08 => reg32 dr { //! Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. + 0..15 => data, //= Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. + }, + 0x0c => reg32 sr { //! Status Register + 0 => tfe: ro, //= Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. + 1 => tnf: ro, //= Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. + 2 => rne: ro, //= Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. + 3 => rff: ro, //= Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. + 4 => bsy: ro, //= Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. + }, + 0x10 => reg32 cpsr { //! Clock Prescale Register + 0..7 => cpsdvsr, //= This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. + }, + 0x14 => reg32 imsc { //! Interrupt Mask Set and Clear Register + 0 => rorim, //= Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + 1 => rtim, //= Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + 2 => rxim, //= Software should set this bit to enable interrupt when the Rx FIFO is at least half full. + 3 => txim, //= Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. + }, + 0x18 => reg32 ris { //! Raw Interrupt Status Register + 0 => rorris: ro, //= This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. + 1 => rtris: ro, //= This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + 2 => rxris: ro, //= This bit is 1 if the Rx FIFO is at least half full. + 3 => txris: ro, //= This bit is 1 if the Tx FIFO is at least half empty. + }, + 0x1c => reg32 mis { //! Masked Interrupt Status Register + 0 => rormis: ro, //= This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. + 1 => rtmis: ro, //= This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + 2 => rxmis: ro, //= This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. + 3 => txmis: ro, //= This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. + }, + 0x20 => reg32 icr { //! SSPICR Interrupt Clear Register + 0 => roric: wo, //= Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. + 1 => rtic: wo, //= Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). + }, +}); +ioregs! (GPIO0 @ 0x50000000 = { //! GPIO0 + 0x3ffc => reg32 data { //! Port n data register for pins PIOn_0 to PIOn_11 + 0 => data0, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 1 => data1, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 2 => data2, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 3 => data3, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 4 => data4, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 5 => data5, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 6 => data6, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 7 => data7, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 8 => data8, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 9 => data9, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 10 => data10, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 11 => data11, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + }, + 0x8000 => reg32 dir { //! Data direction register for port n + 0 => io0, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 1 => io1, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 2 => io2, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 3 => io3, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 4 => io4, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 5 => io5, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 6 => io6, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 7 => io7, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 8 => io8, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 9 => io9, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 10 => io10, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 11 => io11, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + }, + 0x8004 => reg32 is { //! Interrupt sense register for port n + 0 => isense0, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 1 => isense1, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 2 => isense2, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 3 => isense3, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 4 => isense4, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 5 => isense5, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 6 => isense6, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 7 => isense7, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 8 => isense8, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 9 => isense9, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 10 => isense10, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 11 => isense11, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + }, + 0x8008 => reg32 ibe { //! Interrupt both edges register for port n + 0 => ibe0, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 1 => ibe1, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 2 => ibe2, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 3 => ibe3, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 4 => ibe4, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 5 => ibe5, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 6 => ibe6, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 7 => ibe7, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 8 => ibe8, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 9 => ibe9, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 10 => ibe10, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 11 => ibe11, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + }, + 0x800c => reg32 iev { //! Interrupt event register for port n + 0 => iev0, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 1 => iev1, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 2 => iev2, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 3 => iev3, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 4 => iev4, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 5 => iev5, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 6 => iev6, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 7 => iev7, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 8 => iev8, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 9 => iev9, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 10 => iev10, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 11 => iev11, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + }, + 0x8010 => reg32 ie { //! Interrupt mask register for port n + 0 => mask0, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 1 => mask1, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 2 => mask2, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 3 => mask3, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 4 => mask4, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 5 => mask5, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 6 => mask6, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 7 => mask7, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 8 => mask8, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 9 => mask9, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 10 => mask10, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 11 => mask11, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + }, + 0x8014 => reg32 ris { //! Raw interrupt status register for port n + 0 => rawst0: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 1 => rawst1: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 2 => rawst2: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 3 => rawst3: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 4 => rawst4: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 5 => rawst5: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 6 => rawst6: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 7 => rawst7: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 8 => rawst8: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 9 => rawst9: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 10 => rawst10: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 11 => rawst11: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + }, + 0x8018 => reg32 mis { //! Masked interrupt status register for port n + 0 => mask0: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 1 => mask1: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 2 => mask2: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 3 => mask3: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 4 => mask4: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 5 => mask5: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 6 => mask6: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 7 => mask7: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 8 => mask8: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 9 => mask9: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 10 => mask10: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 11 => mask11: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + }, + 0x801c => reg32 ic { //! Interrupt clear register for port n + 0 => clr0: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 1 => clr1: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 2 => clr2: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 3 => clr3: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 4 => clr4: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 5 => clr5: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 6 => clr6: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 7 => clr7: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 8 => clr8: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 9 => clr9: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 10 => clr10: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 11 => clr11: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + }, +}); +ioregs! (GPIO1 @ 0x50010000 = { //! GPIO0 + 0x3ffc => reg32 data { //! Port n data register for pins PIOn_0 to PIOn_11 + 0 => data0, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 1 => data1, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 2 => data2, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 3 => data3, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 4 => data4, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 5 => data5, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 6 => data6, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 7 => data7, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 8 => data8, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 9 => data9, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 10 => data10, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 11 => data11, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + }, + 0x8000 => reg32 dir { //! Data direction register for port n + 0 => io0, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 1 => io1, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 2 => io2, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 3 => io3, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 4 => io4, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 5 => io5, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 6 => io6, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 7 => io7, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 8 => io8, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 9 => io9, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 10 => io10, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 11 => io11, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + }, + 0x8004 => reg32 is { //! Interrupt sense register for port n + 0 => isense0, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 1 => isense1, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 2 => isense2, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 3 => isense3, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 4 => isense4, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 5 => isense5, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 6 => isense6, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 7 => isense7, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 8 => isense8, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 9 => isense9, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 10 => isense10, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 11 => isense11, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + }, + 0x8008 => reg32 ibe { //! Interrupt both edges register for port n + 0 => ibe0, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 1 => ibe1, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 2 => ibe2, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 3 => ibe3, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 4 => ibe4, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 5 => ibe5, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 6 => ibe6, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 7 => ibe7, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 8 => ibe8, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 9 => ibe9, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 10 => ibe10, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 11 => ibe11, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + }, + 0x800c => reg32 iev { //! Interrupt event register for port n + 0 => iev0, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 1 => iev1, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 2 => iev2, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 3 => iev3, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 4 => iev4, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 5 => iev5, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 6 => iev6, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 7 => iev7, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 8 => iev8, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 9 => iev9, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 10 => iev10, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 11 => iev11, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + }, + 0x8010 => reg32 ie { //! Interrupt mask register for port n + 0 => mask0, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 1 => mask1, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 2 => mask2, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 3 => mask3, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 4 => mask4, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 5 => mask5, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 6 => mask6, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 7 => mask7, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 8 => mask8, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 9 => mask9, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 10 => mask10, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 11 => mask11, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + }, + 0x8014 => reg32 ris { //! Raw interrupt status register for port n + 0 => rawst0: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 1 => rawst1: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 2 => rawst2: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 3 => rawst3: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 4 => rawst4: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 5 => rawst5: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 6 => rawst6: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 7 => rawst7: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 8 => rawst8: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 9 => rawst9: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 10 => rawst10: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 11 => rawst11: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + }, + 0x8018 => reg32 mis { //! Masked interrupt status register for port n + 0 => mask0: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 1 => mask1: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 2 => mask2: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 3 => mask3: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 4 => mask4: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 5 => mask5: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 6 => mask6: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 7 => mask7: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 8 => mask8: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 9 => mask9: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 10 => mask10: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 11 => mask11: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + }, + 0x801c => reg32 ic { //! Interrupt clear register for port n + 0 => clr0: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 1 => clr1: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 2 => clr2: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 3 => clr3: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 4 => clr4: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 5 => clr5: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 6 => clr6: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 7 => clr7: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 8 => clr8: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 9 => clr9: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 10 => clr10: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 11 => clr11: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + }, +}); +ioregs! (GPIO2 @ 0x50020000 = { //! GPIO0 + 0x3ffc => reg32 data { //! Port n data register for pins PIOn_0 to PIOn_11 + 0 => data0, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 1 => data1, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 2 => data2, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 3 => data3, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 4 => data4, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 5 => data5, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 6 => data6, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 7 => data7, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 8 => data8, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 9 => data9, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 10 => data10, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 11 => data11, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + }, + 0x8000 => reg32 dir { //! Data direction register for port n + 0 => io0, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 1 => io1, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 2 => io2, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 3 => io3, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 4 => io4, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 5 => io5, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 6 => io6, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 7 => io7, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 8 => io8, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 9 => io9, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 10 => io10, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 11 => io11, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + }, + 0x8004 => reg32 is { //! Interrupt sense register for port n + 0 => isense0, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 1 => isense1, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 2 => isense2, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 3 => isense3, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 4 => isense4, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 5 => isense5, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 6 => isense6, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 7 => isense7, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 8 => isense8, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 9 => isense9, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 10 => isense10, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 11 => isense11, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + }, + 0x8008 => reg32 ibe { //! Interrupt both edges register for port n + 0 => ibe0, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 1 => ibe1, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 2 => ibe2, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 3 => ibe3, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 4 => ibe4, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 5 => ibe5, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 6 => ibe6, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 7 => ibe7, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 8 => ibe8, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 9 => ibe9, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 10 => ibe10, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 11 => ibe11, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + }, + 0x800c => reg32 iev { //! Interrupt event register for port n + 0 => iev0, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 1 => iev1, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 2 => iev2, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 3 => iev3, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 4 => iev4, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 5 => iev5, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 6 => iev6, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 7 => iev7, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 8 => iev8, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 9 => iev9, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 10 => iev10, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 11 => iev11, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + }, + 0x8010 => reg32 ie { //! Interrupt mask register for port n + 0 => mask0, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 1 => mask1, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 2 => mask2, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 3 => mask3, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 4 => mask4, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 5 => mask5, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 6 => mask6, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 7 => mask7, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 8 => mask8, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 9 => mask9, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 10 => mask10, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 11 => mask11, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + }, + 0x8014 => reg32 ris { //! Raw interrupt status register for port n + 0 => rawst0: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 1 => rawst1: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 2 => rawst2: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 3 => rawst3: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 4 => rawst4: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 5 => rawst5: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 6 => rawst6: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 7 => rawst7: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 8 => rawst8: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 9 => rawst9: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 10 => rawst10: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 11 => rawst11: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + }, + 0x8018 => reg32 mis { //! Masked interrupt status register for port n + 0 => mask0: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 1 => mask1: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 2 => mask2: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 3 => mask3: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 4 => mask4: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 5 => mask5: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 6 => mask6: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 7 => mask7: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 8 => mask8: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 9 => mask9: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 10 => mask10: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 11 => mask11: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + }, + 0x801c => reg32 ic { //! Interrupt clear register for port n + 0 => clr0: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 1 => clr1: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 2 => clr2: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 3 => clr3: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 4 => clr4: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 5 => clr5: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 6 => clr6: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 7 => clr7: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 8 => clr8: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 9 => clr9: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 10 => clr10: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 11 => clr11: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + }, +}); +ioregs! (GPIO3 @ 0x50030000 = { //! GPIO0 + 0x3ffc => reg32 data { //! Port n data register for pins PIOn_0 to PIOn_11 + 0 => data0, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 1 => data1, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 2 => data2, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 3 => data3, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 4 => data4, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 5 => data5, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 6 => data6, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 7 => data7, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 8 => data8, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 9 => data9, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 10 => data10, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + 11 => data11, //= Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. + }, + 0x8000 => reg32 dir { //! Data direction register for port n + 0 => io0, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 1 => io1, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 2 => io2, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 3 => io3, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 4 => io4, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 5 => io5, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 6 => io6, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 7 => io7, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 8 => io8, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 9 => io9, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 10 => io10, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + 11 => io11, //= Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. + }, + 0x8004 => reg32 is { //! Interrupt sense register for port n + 0 => isense0, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 1 => isense1, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 2 => isense2, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 3 => isense3, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 4 => isense4, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 5 => isense5, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 6 => isense6, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 7 => isense7, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 8 => isense8, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 9 => isense9, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 10 => isense10, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + 11 => isense11, //= Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. + }, + 0x8008 => reg32 ibe { //! Interrupt both edges register for port n + 0 => ibe0, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 1 => ibe1, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 2 => ibe2, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 3 => ibe3, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 4 => ibe4, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 5 => ibe5, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 6 => ibe6, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 7 => ibe7, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 8 => ibe8, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 9 => ibe9, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 10 => ibe10, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + 11 => ibe11, //= Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. + }, + 0x800c => reg32 iev { //! Interrupt event register for port n + 0 => iev0, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 1 => iev1, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 2 => iev2, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 3 => iev3, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 4 => iev4, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 5 => iev5, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 6 => iev6, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 7 => iev7, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 8 => iev8, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 9 => iev9, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 10 => iev10, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + 11 => iev11, //= Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt. + }, + 0x8010 => reg32 ie { //! Interrupt mask register for port n + 0 => mask0, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 1 => mask1, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 2 => mask2, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 3 => mask3, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 4 => mask4, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 5 => mask5, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 6 => mask6, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 7 => mask7, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 8 => mask8, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 9 => mask9, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 10 => mask10, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + 11 => mask11, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. + }, + 0x8014 => reg32 ris { //! Raw interrupt status register for port n + 0 => rawst0: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 1 => rawst1: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 2 => rawst2: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 3 => rawst3: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 4 => rawst4: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 5 => rawst5: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 6 => rawst6: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 7 => rawst7: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 8 => rawst8: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 9 => rawst9: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 10 => rawst10: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + 11 => rawst11: ro, //= Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. + }, + 0x8018 => reg32 mis { //! Masked interrupt status register for port n + 0 => mask0: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 1 => mask1: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 2 => mask2: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 3 => mask3: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 4 => mask4: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 5 => mask5: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 6 => mask6: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 7 => mask7: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 8 => mask8: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 9 => mask9: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 10 => mask10: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + 11 => mask11: ro, //= Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. + }, + 0x801c => reg32 ic { //! Interrupt clear register for port n + 0 => clr0: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 1 => clr1: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 2 => clr2: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 3 => clr3: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 4 => clr4: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 5 => clr5: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 6 => clr6: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 7 => clr7: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 8 => clr8: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 9 => clr9: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 10 => clr10: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + 11 => clr11: wo, //= Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. + }, +}); diff --git a/src/hal/lpc11xx/syscon.rs b/src/hal/lpc11xx/syscon.rs new file mode 100644 index 00000000..429a495d --- /dev/null +++ b/src/hal/lpc11xx/syscon.rs @@ -0,0 +1,207 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2015 Vladimir "farcaller" Pouzanov +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//! Routines for initialization and system configuration of NXP LPC11xx. +//! +//! This module includes code for setting up the clock, flash, access time and +//! performing initial peripheral configuration. + +use super::regs; + +/// Interrupt vectors source. +#[derive(PartialEq, Debug)] +pub enum ISRLocation { + /// ISR mapped to bootloader. + Bootloader = 0, + /// ISR mapped to RAM. + RAM = 1, + /// ISR mapped to Flash ROM. + Flash = 2 +} + +/// Returns the current source of interrupt vectors. +pub fn get_isr_location() -> ISRLocation { + match regs::SYSCON().sysmemremap.map() { + regs::SYSCON_sysmemremap_map::BOOT_LOADER_MODE_IN => ISRLocation::Bootloader, + regs::SYSCON_sysmemremap_map::USER_RAM_MODE_INTER => ISRLocation::RAM, + regs::SYSCON_sysmemremap_map::USER_FLASH_MODE_INT => ISRLocation::Flash, + } +} + +/// Re-maps interrupt vectors to either RAM or Flash. +pub fn set_isr_location(loc: ISRLocation) { + regs::SYSCON().sysmemremap.ignoring_state().set_map(match loc { + ISRLocation::RAM => regs::SYSCON_sysmemremap_map::USER_RAM_MODE_INTER, + ISRLocation::Flash => regs::SYSCON_sysmemremap_map::USER_FLASH_MODE_INT, + _ => panic!(), + }); +} + +/// Peripherals that are soft-resettable via reset_peripheral. +pub enum ResetPeripheral { + /// Reset SPI0. + SPI0, + /// Reset SPI1. + SPI1, + /// Reset I2C. + I2C, + /// Reset CAN. + CAN, +} + +/// Soft-resets the given peripheral. +pub unsafe fn reset_peripheral(peripheral: ResetPeripheral) { + match peripheral { + ResetPeripheral::SPI0 => { + regs::SYSCON().presetctrl.set_ssp0_rst_n( + regs::SYSCON_presetctrl_ssp0_rst_n::SPIO0RESET); + regs::SYSCON().presetctrl.set_ssp0_rst_n( + regs::SYSCON_presetctrl_ssp0_rst_n::SPIO0NORESET); + }, + ResetPeripheral::SPI1 => { + regs::SYSCON().presetctrl.set_ssp1_rst_n( + regs::SYSCON_presetctrl_ssp1_rst_n::SPI1RESET); + regs::SYSCON().presetctrl.set_ssp1_rst_n( + regs::SYSCON_presetctrl_ssp1_rst_n::SPI2NORESET); + }, + ResetPeripheral::I2C => { + regs::SYSCON().presetctrl.set_i2c_rst_n( + regs::SYSCON_presetctrl_i2c_rst_n::I2CRESET); + regs::SYSCON().presetctrl.set_i2c_rst_n( + regs::SYSCON_presetctrl_i2c_rst_n::I2CNORESET); + }, + ResetPeripheral::CAN => { + regs::SYSCON().presetctrl.set_can_rst_n( + regs::SYSCON_presetctrl_can_rst_n::CANRESET); + regs::SYSCON().presetctrl.set_can_rst_n( + regs::SYSCON_presetctrl_can_rst_n::CANNORESET); + } + } +} + +/// Initialises system clock to specified boot configuration. +pub fn init_system_clock() { + regs::SYSCON().pdruncfg + .set_sysosc_pd(regs::SYSCON_pdruncfg_sysosc_pd::POWERED); + regs::SYSCON().sysoscctrl.ignoring_state() + .set_bypass(regs::SYSCON_sysoscctrl_bypass::NOBYPASS) + .set_freqrange(regs::SYSCON_sysoscctrl_freqrange::LOW); + regs::SYSCON().syspllclksel.ignoring_state() + .set_sel(regs::SYSCON_syspllclksel_sel::SYSTEM_OSCILLATOR); + + regs::SYSCON().syspllclkuen.ignoring_state() + .set_ena(regs::SYSCON_syspllclkuen_ena::UPDATE_CLOCK_SOURCE); + regs::SYSCON().syspllclkuen.ignoring_state() + .set_ena(regs::SYSCON_syspllclkuen_ena::NO_CHANGE); + regs::SYSCON().syspllclkuen.ignoring_state() + .set_ena(regs::SYSCON_syspllclkuen_ena::UPDATE_CLOCK_SOURCE); + + loop { + if regs::SYSCON().syspllclkuen.ena() == regs::SYSCON_syspllclkuen_ena::UPDATE_CLOCK_SOURCE { + break + } + } +} + +#[cfg(test)] +mod test { + use super::*; + use volatile_cell::{VolatileCellReplayer, set_replayer}; + use expectest::prelude::*; + use expectest; + use std::thread; + use std::string::String; + use std::convert::From; + + #[test] + fn returns_isr_location() { + init_replayer!(); + + expect_volatile_read!(0x4004_8000, 0b10); + + expect!(get_isr_location()).to(be_equal_to(ISRLocation::Flash)); + + expect_replayer_valid!(); + } + + #[test] + fn sets_isr_location() { + init_replayer!(); + + expect_volatile_write!(0x4004_8000, 2); + + set_isr_location(ISRLocation::Flash); + + expect_replayer_valid!(); + } + + #[test] + fn fails_to_set_isr_location_to_bootloader() { + let j = thread::Builder::new() + .name(String::from("fails_to_set_isr_location_to_bootloader")) + .spawn(|| { + init_replayer!(); + expect_volatile_write!(0x4004_8000, 0); + set_isr_location(ISRLocation::Bootloader); + }).unwrap(); + let res = j.join(); + + expect!(res.is_err()).to(be_equal_to(true)); + } + + #[test] + fn performs_soft_reset_on_peripherals() { + init_replayer!(); + + expect_volatile_read!(0x4004_8004, 0); + expect_volatile_write!(0x4004_8004, 0); + expect_volatile_read!(0x4004_8004, 0); + expect_volatile_write!(0x4004_8004, 1); + unsafe { reset_peripheral(ResetPeripheral::SPI0) } + + expect_replayer_valid!(); + } + + #[test] + fn initialize_system_clock() { + init_replayer!(); + + // read PDRUNCFG, returns reset value + expect_volatile_read!( 0x4004_8238, 0x0000_EDF0); + // write PDRUNCFG, set SYSOSC_PD to POWERED + expect_volatile_write!(0x4004_8238, 0x0000_EDD0); + + // write SYSOSCCTRL, set BYPASS to off, FREQRANGE 1-20MHz + expect_volatile_write!(0x4004_8020, 0x0000_0000); + + // write SYSPLLCLKSEL, set SEL to system oscillator + expect_volatile_write!(0x4004_8040, 0x0000_0001); + + // write SYSPLLCLKUEN, set update/no change/update + expect_volatile_write!(0x4004_8044, 0x0000_0001); + expect_volatile_write!(0x4004_8044, 0x0000_0000); + expect_volatile_write!(0x4004_8044, 0x0000_0001); + + // poll-read SYSPLLCLKUEN until returns update + expect_volatile_read!( 0x4004_8044, 0x0000_0000); + expect_volatile_read!( 0x4004_8044, 0x0000_0000); + expect_volatile_read!( 0x4004_8044, 0x0000_0000); + expect_volatile_read!( 0x4004_8044, 0x0000_0001); + + init_system_clock(); + + expect_replayer_valid!(); + } +} diff --git a/src/hal/mod.rs b/src/hal/mod.rs index 49d7917c..af1743e0 100644 --- a/src/hal/mod.rs +++ b/src/hal/mod.rs @@ -21,19 +21,15 @@ and each such struct has a `setup()` method that configures the hardware (returning the object to interact with it where applicable). */ +pub mod lpc11xx; +#[cfg(feature = "mcu_lpc17xx")] pub mod lpc17xx; +#[cfg(feature = "mcu_stm32f4")] pub mod stm32f4; +#[cfg(feature = "mcu_stm32l1")] pub mod stm32l1; +#[cfg(feature = "mcu_k20")] pub mod k20; +#[cfg(feature = "mcu_tiva_c")] pub mod tiva_c; -#[cfg(feature = "mcu_lpc17xx")] -pub mod lpc17xx; -#[cfg(feature = "mcu_stm32f4")] -pub mod stm32f4; -#[cfg(feature = "mcu_stm32l1")] -pub mod stm32l1; -#[cfg(feature = "mcu_k20")] -pub mod k20; -#[cfg(feature = "mcu_tiva_c")] -pub mod tiva_c; - -#[cfg(any(feature = "cpu_cortex-m3", +#[cfg(any(feature = "cpu_cortex-m0", + feature = "cpu_cortex-m3", feature = "cpu_cortex-m4"))] mod cortex_common; #[cfg(feature = "cpu_cortex-m3")] diff --git a/src/lib.rs b/src/lib.rs index 7a8b3551..9ce69523 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -53,10 +53,12 @@ STM32F403/407). extern crate rlibc; #[macro_use] #[no_link] extern crate ioreg; -extern crate volatile_cell; +#[macro_use] extern crate volatile_cell; #[cfg(test)] extern crate std; +#[cfg(test)] #[macro_use(expect)] extern crate expectest; + pub mod drivers; pub mod hal; pub mod util; diff --git a/src/os/mutex.rs b/src/os/mutex.rs index f237d28e..162af106 100644 --- a/src/os/mutex.rs +++ b/src/os/mutex.rs @@ -152,6 +152,7 @@ mod internal { taken: UnsafeCell, } + /// Static initializer pub const MUTEX_INIT: Mutex = Mutex { taken: UnsafeCell { value: false } }; /// A mutex lock diff --git a/src/util/shared.rs b/src/util/shared.rs index 7e47bbd1..7f750647 100644 --- a/src/util/shared.rs +++ b/src/util/shared.rs @@ -33,6 +33,7 @@ mod dummy_irq { pub struct NoInterrupts; impl NoInterrupts { + #[allow(dead_code)] pub fn new() -> NoInterrupts { NoInterrupts } diff --git a/support/build-jenkins.sh b/support/build-jenkins.sh index a18f4a34..0c8f17fa 100755 --- a/support/build-jenkins.sh +++ b/support/build-jenkins.sh @@ -6,45 +6,63 @@ echo " * rustc version: `rustc --version`" if [ "$PLATFORM" == "native" ]; then # build unit tests - cargo test --lib --verbose + echo " * building zinc" + cargo test --features test --lib --verbose + echo " * building ioreg" (cd ./ioreg; cargo build --verbose; cargo test --verbose) + echo " * building platformtree" (cd ./platformtree; cargo build --verbose; cargo test --verbose) + echo " * building platformtree macro" (cd ./macro_platformtree; cargo build --verbose; cargo test --verbose) + echo " * building zinc macro" (cd ./macro_zinc; cargo test --verbose) echo " * generating coverage data" - kcov cov/ target/debug/zinc-* - support/fixcov.py src/ cov/zinc-????????????????/cobertura.xml - kcov cov/ ioreg/target/debug/test-* - support/fixcov.py ioreg/src/ cov/test-????????????????/cobertura.xml - kcov cov/ platformtree/target/debug/platformtree-* - support/fixcov.py platformtree/src/ cov/platformtree-????????????????/cobertura.xml + if [ "$TRAVIS_JOB_ID" != "" ]; then + kcov-master/tmp/usr/local/bin/kcov --coveralls-id=$TRAVIS_JOB_ID --exclude-pattern=/.cargo target/kcov target/debug/zinc-* + kcov-master/tmp/usr/local/bin/kcov --coveralls-id=$TRAVIS_JOB_ID --exclude-pattern=/.cargo target/kcov ioreg/target/debug/test-* + kcov-master/tmp/usr/local/bin/kcov --coveralls-id=$TRAVIS_JOB_ID --exclude-pattern=/.cargo target/kcov platformtree/target/debug/platformtree-* + else + kcov cov/ target/debug/zinc-* + support/fixcov.py src/ cov/zinc-????????????????/cobertura.xml + kcov cov/ ioreg/target/debug/test-* + support/fixcov.py ioreg/src/ cov/test-????????????????/cobertura.xml + kcov cov/ platformtree/target/debug/platformtree-* + support/fixcov.py platformtree/src/ cov/platformtree-????????????????/cobertura.xml + fi else # build cross-compiled lib and examples case "$PLATFORM" in + lpc11xx ) + TARGET=thumbv6-none-eabi + EXAMPLES="empty" + ;; lpc17xx ) TARGET=thumbv7m-none-eabi - EXAMPLES="blink blink_pt uart dht22 empty" + EXAMPLES="empty blink_lpc17xx blink_pt uart dht22" ;; k20 ) TARGET=thumbv7em-none-eabi - EXAMPLES="blink_k20 blink_k20_isr empty" + EXAMPLES="empty blink_k20 blink_k20_isr" ;; stm32f4 ) TARGET=thumbv7em-none-eabi - EXAMPLES="blink_stm32f4 empty" + EXAMPLES="empty blink_stm32f4" ;; stm32l1 ) TARGET=thumbv7m-none-eabi - EXAMPLES="blink_stm32l1 bluenrg_stm32l1 usart_stm32l1 empty" + EXAMPLES="empty blink_stm32l1 bluenrg_stm32l1 usart_stm32l1" ;; esac ./configure --host=arm-none-eabi - cargo build --target=$TARGET --verbose --features "mcu_$PLATFORM" + cargo build --target=$TARGET --verbose --features "mcu_$PLATFORM" --lib for e in $EXAMPLES; do - EXAMPLE_NAME=$e make build + pushd "examples/$e" + ln -sf "../../$TARGET.json" + cargo build --target=$TARGET --verbose --features "mcu_$PLATFORM" --release + popd done fi diff --git a/support/svd/data/NXP/Changelog.md b/support/svd/data/NXP/Changelog.md new file mode 100644 index 00000000..83ba1f10 --- /dev/null +++ b/support/svd/data/NXP/Changelog.md @@ -0,0 +1,8 @@ +LPC11xx +======= + +* LPC11xx-v6-z0 + modified a few constants to make the enums compilable + +* LPC11xx-v6 + original fetched from http://www.lpcware.com/content/nxpfile/lpc11xx-svd-file diff --git a/support/svd/data/NXP/LPC11xx-v6-z0.xml b/support/svd/data/NXP/LPC11xx-v6-z0.xml new file mode 100755 index 00000000..cc915f6b --- /dev/null +++ b/support/svd/data/NXP/LPC11xx-v6-z0.xml @@ -0,0 +1,17083 @@ + + + + LPC111x_LPC11Cxx + 6 + LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL + + + + CM0 + r0p0 + little + 0 + 0 + 2 + 0 + + 8 + 32 + 32 + + + I2C + I2C + I2C + 0x40000000 + + 0 + 0xFFF + registers + + + I2C + 15 + + + + CONSET + I2C Control Set Register. When a one is + written to a bit of this register, the corresponding bit + in the I2C control register is set. Writing a zero has no + effect on the corresponding bit in the I2C control + register. + 0x000 + read-write + 0x00 + 0xFFFFFFFF + + + RESERVED + Reserved. User software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [1:0] + + + AA + Assert acknowledge flag. + [2:2] + + + SI + I2C interrupt flag. + [3:3] + + + STO + STOP flag. + [4:4] + + + STA + START flag. + [5:5] + + + I2EN + I2C interface enable. + [6:6] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:7] + + + + + STAT + I2C Status Register. During I2C operation, + this register provides detailed status codes that allow + software to determine the next action + needed. + 0x004 + read-only + 0xF8 + 0xFFFFFFFF + + + RESERVED + These bits are unused and are always + 0. + [2:0] + + + Status + These bits give the actual status + information about the I 2C interface. + [7:3] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:8] + + + + + DAT + I2C Data Register. During master or slave + transmit mode, data to be transmitted is written to this + register. During master or slave receive mode, data that + has been received may be read from this + register. + 0x008 + read-write + 0x00 + 0xFFFFFFFF + + + Data + This register holds data values that + have been received or are to be + transmitted. + [7:0] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:8] + + + + + ADR0 + I2C Slave Address Register 0. Contains the + 7-bit slave address for operation of the I2C interface in + slave mode, and is not used in master mode. The least + significant bit determines whether a slave responds to + the General Call address. + 0x00C + read-write + 0x00 + 0xFFFFFFFF + + + GC + General Call enable bit. + [0:0] + + + Address + The I2C device address for slave + mode. + [7:1] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:8] + + + + + SCLH + SCH Duty Cycle Register High Half Word. + Determines the high time of the I2C clock. + 0x010 + read-write + 0x04 + 0xFFFFFFFF + + + SCLH + Count for SCL HIGH time period + selection. + [15:0] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:16] + + + + + SCLL + SCL Duty Cycle Register Low Half Word. + Determines the low time of the I2C clock. I2nSCLL and + I2nSCLH together determine the clock frequency generated + by an I2C master and certain times used in slave + mode. + 0x014 + read-write + 0x04 + 0xFFFFFFFF + + + SCLL + Count for SCL low time period + selection. + [15:0] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:16] + + + + + CONCLR + I2C Control Clear Register. When a one is + written to a bit of this register, the corresponding bit + in the I2C control register is cleared. Writing a zero + has no effect on the corresponding bit in the I2C control + register. + 0x018 + write-only + 0 + 0x00000000 + + + RESERVED + Reserved. User software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [1:0] + + + AAC + Assert acknowledge Clear + bit. + [2:2] + + + SIC + I2C interrupt Clear bit. + [3:3] + + + RESERVED + Reserved. User software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [4:4] + + + STAC + START flag Clear bit. + [5:5] + + + I2ENC + I2C interface Disable bit. + [6:6] + + + RESERVED + Reserved. User software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [7:7] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:8] + + + + + MMCTRL + Monitor mode control register. + 0x01C + read-write + 0x00 + 0xFFFFFFFF + + + MM_ENA + Monitor mode enable. + [0:0] + + ENUM + + MONITOR_MODE_DISABLE + Monitor mode disabled. + 0 + + + THE_I2C_MODULE_WILL_ + The I2C module will enter monitor + mode. In this mode the SDA output will be forced + high. This will prevent the I2C module from + outputting data of any kind (including ACK) onto + the I 2C data bus. Depending on the state of the + ENA_SCL bit, the output may be also forced high, + preventing the module from having control over + the I2C clock line. + 1 + + + + + ENA_SCL + SCL output enable. + [1:1] + + ENUM + + HIGH + When this bit is cleared to 0, the + SCL output will be forced high when the module is + in monitor mode. As described above, this will + prevent the module from having any control over + the I2C clock line. + 0 + + + NORMAL + When this bit is set, the I2C module + may exercise the same control over the clock line + that it would in normal operation. This means + that, acting as a slave peripheral, the I2C + module can stretch the clock line (hold it low) + until it has had time to respond to an I2C + interrupt.[1] + 1 + + + + + MATCH_ALL + Select interrupt register + match. + [2:2] + + ENUM + + MATCH + When this bit is cleared, an + interrupt will only be generated when a match + occurs to one of the (up-to) four address + registers described above. That is, the module + will respond as a normal slave as far as + address-recognition is concerned. + 0 + + + ANYADDRESS + When this bit is set to 1 and the + I2C is in monitor mode, an interrupt will be + generated on ANY address received. This will + enable the part to monitor all traffic on the + bus. + 1 + + + + + RESERVED + Reserved. The value read from reserved + bits is not defined. + [31:3] + + + + + 3 + 0x4 + 1-3 + ADR%s + I2C Slave Address Register 1. Contains the + 7-bit slave address for operation of the I2C interface in + slave mode, and is not used in master mode. The least + significant bit determines whether a slave responds to + the General Call address. + 0x020 + read-write + 0x00 + 0xFFFFFFFF + + + GC + General Call enable bit. + [0:0] + + + Address + The I2C device address for slave + mode. + [7:1] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:8] + + + + + DATA_BUFFER + Data buffer register. The contents of the 8 + MSBs of the I2DAT shift register will be transferred to + the DATA_BUFFER automatically after every nine bits (8 + bits of data plus ACK or NACK) has been received on the + bus. + 0x02C + read-only + 0x00 + 0xFFFFFFFF + + + Data + This register holds contents of the 8 + MSBs of the DAT shift register. + [7:0] + + + RESERVED + Reserved. The value read from a reserved + bit is not defined. + [31:8] + + + + + 4 + 0x4 + 0-3 + MASK%s + I2C Slave address mask register 0. This mask + register is associated with I2ADR0 to determine an + address match. The mask register has no effect when + comparing to the General Call address + (0000000). + 0x030 + read-write + 0x00 + 0xFFFFFFFF + + + RESERVED + Reserved. User software should not write + ones to reserved bits. This bit reads always back as + 0. + [0:0] + + + MASK + Mask bits. + [7:1] + + + RESERVED + Reserved. The value read from reserved + bits is undefined. + [31:8] + + + + + + + WWDT + Product name title=UM10398 Chapter + title=LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT) + Modification date=9/19/2011 Major revision=6 Minor + revision=not available + WWDT + 0x40004000 + + 0x0 + 0xFFF + registers + + + WDT + 25 + + + + WDMOD + Watchdog mode register. This register + contains the basic mode and status of the Watchdog + Timer. + 0x000 + read-write + 0 + 0xFFFFFFFF + + + WDEN + Watchdog enable bit. This bit is Set + Only. Setting this bit to one also locks the watchdog + clock source. Once the watchdog timer is enabled, the + watchdog timer clock source cannot be changed. If the + watchdog timer is needed in Deep-sleep mode, the + watchdog clock source must be changed to the watchdog + oscillator before setting this bit to + one. + [0:0] + + ENUM + + STOPPED + The watchdog timer is + stopped. + 0 + + + RUN + The watchdog timer is + running. + 1 + + + + + WDRESET + Watchdog reset enable bit. This bit is + Set Only. + [1:1] + + ENUM + + NORESET + A watchdog timeout will not cause a + chip reset. + 0 + + + RESET + A watchdog timeout will cause a chip + reset. + 1 + + + + + WDTOF + Watchdog time-out flag. Set when the + watchdog timer times out, by a feed error, or by + events associated with WDPROTECT, cleared by + software. Causes a chip reset if WDRESET = + 1. + [2:2] + + + WDINT + Watchdog interrupt flag. Set when the + timer reaches the value in WDWARNINT. Cleared by + software. + [3:3] + + + WDPROTECT + Watchdog update mode. This bit is Set + Only. + [4:4] + + ENUM + + ANYTIME + The watchdog reload value (WDTC) can + be changed at any time. + 0 + + + LOWCOUNTER + The watchdog reload value (WDTC) can + be changed only after the counter is below the + value of WDWARNINT and WDWINDOW. Note: this mode + is intended for use only when WDRESET + =1. + 1 + + + + + RESERVED + Reserved. Read value is undefined, only + zero should be written. + [31:5] + + + + + WDTC + Watchdog timer constant register. This + register determines the time-out value. + 0x004 + read-write + 0xFF + 0xFFFFFFFF + + + Count + Watchdog time-out + interval. + [23:0] + + + RESERVED + Reserved. Read value is undefined, only + zero should be written. + [31:24] + + + + + WDFEED + Watchdog feed sequence register. Writing + 0xAA followed by 0x55 to this register reloads the + Watchdog timer with the value contained in + WDTC. + 0x008 + write-only + 0 + 0x00000000 + + + Feed + Feed value should be 0xAA followed by + 0x55. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + WDTV + Watchdog timer value register. This register + reads out the current value of the Watchdog + timer. + 0x00C + read-only + 0xFF + 0xFFFFFFFF + + + Count + Counter timer value. + [23:0] + + + RESERVED + Reserved. Read value is undefined, only + zero should be written. + [31:24] + + + + + WDWARNINT + Watchdog Warning Interrupt compare + value. + 0x014 + read-write + 0 + 0xFFFFFFFF + + + WARNINT + Watchdog warning interrupt compare + value. + [9:0] + + + RESERVED + Reserved. Read value is undefined, only + zero should be written. + [31:10] + + + + + WDWINDOW + Watchdog Window compare value. + 0x018 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + WINDOW + Watchdog window value. + [23:0] + + + RESERVED + Reserved. Read value is undefined, only + zero should be written. + [31:24] + + + + + + + UART + Product name title=UM10398 Chapter + title=LPC111x/LPC11Cxx UART Modification date=9/19/2011 Major + revision=7 Minor revision=not available + UART + 0x40008000 + + 0x0 + 0xFFF + registers + + + UART + 21 + + + + RBR + Receiver Buffer Register. Contains the next + received character to be read. (DLAB=0) + 0x000 + read-only + 0 + 0x00000000 + + + RBR + The UART Receiver Buffer Register + contains the oldest received byte in the UART RX + FIFO. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + THR + Transmit Holding Register. The next + character to be transmitted is written here. + (DLAB=0) + RBR + 0x000 + write-only + 0 + 0x00000000 + + + THR + Writing to the UART Transmit Holding + Register causes the data to be stored in the UART + transmit FIFO. The byte will be sent when it reaches + the bottom of the FIFO and the transmitter is + available. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + DLL + Divisor Latch LSB. Least significant byte of + the baud rate divisor value. The full divisor is used to + generate a baud rate from the fractional rate divider. + (DLAB=1) + RBR + 0x000 + read-write + 0x01 + 0xFFFFFFFF + + + DLLSB + The UART Divisor Latch LSB Register, + along with the DLM register, determines the baud rate + of the UART. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + DLM + Divisor Latch MSB. Most significant byte of + the baud rate divisor value. The full divisor is used to + generate a baud rate from the fractional rate divider. + (DLAB=1) + 0x004 + read-write + 0x00 + 0xFFFFFFFF + + + DLMSB + The UART Divisor Latch MSB Register, + along with the DLL register, determines the baud rate + of the UART. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + IER + Interrupt Enable Register. Contains + individual interrupt enable bits for the 7 potential UART + interrupts. (DLAB=0) + DLM + 0x004 + read-write + 0x00 + 0xFFFFFFFF + + + RBRIE + RBR Interrupt Enable. Enables the + Receive Data Available interrupt for UART. It also + controls the Character Receive Time-out + interrupt. + [0:0] + + ENUM + + DISABLE_THE_RDA_INTE + Disable the RDA + interrupt. + 0 + + + ENABLE_THE_RDA_INTER + Enable the RDA + interrupt. + 1 + + + + + THREIE + THRE Interrupt Enable. Enables the THRE + interrupt for UART. The status of this interrupt can + be read from LSR[5]. + [1:1] + + ENUM + + DISABLE_THE_THRE_INT + Disable the THRE + interrupt. + 0 + + + ENABLE_THE_THRE_INTE + Enable the THRE + interrupt. + 1 + + + + + RXLIE + RX Line Interrupt Enable. Enables the + UART RX line status interrupts. The status of this + interrupt can be read from LSR[4:1]. + [2:2] + + ENUM + + DISABLE_THE_RX_LINE_ + Disable the RX line status + interrupts. + 0 + + + ENABLE_THE_RX_LINE_S + Enable the RX line status + interrupts. + 1 + + + + + RESERVED + Reserved + [3:3] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [6:4] + + + RESERVED + Reserved + [7:7] + + + ABEOINTEN + Enables the end of auto-baud + interrupt. + [8:8] + + ENUM + + DISABLE_END_OF_AUTO_ + Disable end of auto-baud + Interrupt. + 0 + + + ENABLE_END_OF_AUTO_B + Enable end of auto-baud + Interrupt. + 1 + + + + + ABTOINTEN + Enables the auto-baud time-out + interrupt. + [9:9] + + ENUM + + DISABLE_AUTO_BAUD_TI + Disable auto-baud time-out + Interrupt. + 0 + + + ENABLE_AUTO_BAUD_TIM + Enable auto-baud time-out + Interrupt. + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:10] + + + + + IIR + Interrupt ID Register. Identifies which + interrupt(s) are pending. + 0x008 + read-only + 0x01 + 0xFFFFFFFF + + + INTSTATUS + Interrupt status. Note that IIR[0] is + active low. The pending interrupt can be determined + by evaluating IIR[3:1]. + [0:0] + + ENUM + + PENDING + At least one interrupt is + pending. + 0 + + + NO_INTERRUPT_IS_PEND + No interrupt is + pending. + 1 + + + + + INTID + Interrupt identification. IER[3:1] + identifies an interrupt corresponding to the UART Rx + FIFO. All other combinations of IER[3:1] not listed + below are reserved (100,101,111). + [3:1] + + ENUM + + 1_RECEIVE_LINE_S + 1 - Receive Line Status + (RLS). + 0x3 + + + 2A__RECEIVE_DATA_AV + 2a - Receive Data Available + (RDA). + 0x2 + + + 2B__CHARACTER_TIME_ + 2b - Character Time-out Indicator + (CTI). + 0x6 + + + 3_THRE_INTERRUPT + 3 - THRE Interrupt. + 0x1 + + + 4_MODEM_INTERRUP + 4 - Modem interrupt. + 0x0 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [5:4] + + + FIFOENABLE + These bits are equivalent to + FCR[0]. + [7:6] + + + ABEOINT + End of auto-baud interrupt. True if + auto-baud has finished successfully and interrupt is + enabled. + [8:8] + + + ABTOINT + Auto-baud time-out interrupt. True if + auto-baud has timed out and interrupt is + enabled. + [9:9] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:10] + + + + + FCR + FIFO Control Register. Controls UART FIFO + usage and modes. + IIR + 0x008 + write-only + 0x00 + 0xFFFFFFFF + + + FIFOEN + FIFO Enable + [0:0] + + ENUM + + DISABLED + UART FIFOs are disabled. Must not be + used in the application. + 0 + + + ENABLED + Active high enable for both UART Rx + and TX FIFOs and FCR[7:1] access. This bit must + be set for proper UART operation. Any transition + on this bit will automatically clear the UART + FIFOs. + 1 + + + + + RXFIFORES + RX FIFO Reset + [1:1] + + ENUM + + NO_IMPACT_ON_EITHER_ + No impact on either of UART + FIFOs. + 0 + + + CLEAR + Writing a logic 1 to FCR[1] will + clear all bytes in UART Rx FIFO, reset the + pointer logic. This bit is + self-clearing. + 1 + + + + + TXFIFORES + TX FIFO Reset + [2:2] + + ENUM + + NO_IMPACT_ON_EITHER_ + No impact on either of UART + FIFOs. + 0 + + + CLEAR + Writing a logic 1 to FCR[2] will + clear all bytes in UART TX FIFO, reset the + pointer logic. This bit is + self-clearing. + 1 + + + + + RESERVED + Reserved + [3:3] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [5:4] + + + RXTL + RX Trigger Level. These two bits + determine how many receiver UART FIFO characters must + be written before an interrupt is + activated. + [7:6] + + ENUM + + TRIGGER_LEVEL_0_1_C + Trigger level 0 (1 character or + 0x01). + 0x0 + + + TRIGGER_LEVEL_1_4_C + Trigger level 1 (4 characters or + 0x04). + 0x1 + + + TRIGGER_LEVEL_2_8_C + Trigger level 2 (8 characters or + 0x08). + 0x2 + + + TRIGGER_LEVEL_3_14_ + Trigger level 3 (14 characters or + 0x0E). + 0x3 + + + + + RESERVED + Reserved + [31:8] + + + + + LCR + Line Control Register. Contains controls for + frame formatting and break generation. + 0x00C + read-write + 0x00 + 0xFFFFFFFF + + + WLS + Word Length Select + [1:0] + + ENUM + + 5_BIT_CHARACTER_LENG + 5-bit character + length. + 0x0 + + + 6_BIT_CHARACTER_LENG + 6-bit character + length. + 0x1 + + + 7_BIT_CHARACTER_LENG + 7-bit character + length. + 0x2 + + + 8_BIT_CHARACTER_LENG + 8-bit character + length. + 0x3 + + + + + SBS + Stop Bit Select + [2:2] + + ENUM + + 1_STOP_BIT_ + 1 stop bit. + 0 + + + 2_STOP_BITS + 2 stop bits (1.5 if + LCR[1:0]=00). + 1 + + + + + PE + Parity Enable + [3:3] + + ENUM + + DISABLE_PARITY_GENER + Disable parity generation and + checking. + 0 + + + ENABLE_PARITY_GENERA + Enable parity generation and + checking. + 1 + + + + + PS + Parity Select + [5:4] + + ENUM + + ODD_PARITY_NUMBER_O + Odd parity. Number of 1s in the + transmitted character and the attached parity bit + will be odd. + 0x0 + + + EVEN_PARITY_NUMBER_ + Even Parity. Number of 1s in the + transmitted character and the attached parity bit + will be even. + 0x1 + + + FORCED_1_STICK_PARIT + Forced 1 stick parity. + 0x2 + + + FORCED_0_STICK_PARIT + Forced 0 stick parity. + 0x3 + + + + + BC + Break Control + [6:6] + + ENUM + + DISABLE_BREAK_TRANSM + Disable break + transmission. + 0 + + + ENABLE_BREAK_TRANSMI + Enable break transmission. Output + pin UART TXD is forced to logic 0 when LCR[6] is + active high. + 1 + + + + + DLAB + Divisor Latch Access Bit + [7:7] + + ENUM + + DISABLE_ACCESS_TO_DI + Disable access to Divisor + Latches. + 0 + + + ENABLE_ACCESS_TO_DIV + Enable access to Divisor + Latches. + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + MCR + Modem control register + 0x010 + read-write + 0x00 + 0xFFFFFFFF + + + DTRC + DTR Control. Source for modem output + pin, DTR. This bit reads as 0 when modem loopback + mode is active. + [0:0] + + + RTSC + RTS Control. Source for modem output pin + RTS. This bit reads as 0 when modem loopback mode is + active. + [1:1] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [3:2] + + + LMS + Loopback Mode Select. The modem loopback + mode provides a mechanism to perform diagnostic + loopback testing. Serial data from the transmitter is + connected internally to serial input of the receiver. + Input pin, RXD, has no effect on loopback and output + pin, TXD is held in marking state. The four modem + inputs (CTS, DSR, RI and DCD) are disconnected + externally. Externally, the modem outputs (RTS, DTR) + are set inactive. Internally, the four modem outputs + are connected to the four modem inputs. As a result + of these connections, the upper four bits of the MSR + will be driven by the lower four bits of the MCR + rather than the four modem inputs in normal mode. + This permits modem status interrupts to be generated + in loopback mode by writing the lower four bits of + MCR. + [4:4] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [5:5] + + + RTSEN + RTS flow control + [6:6] + + ENUM + + DISABLE_AUTO_RTS_FLO + Disable auto-rts flow + control. + 0 + + + ENABLE_AUTO_RTS_FLOW + Enable auto-rts flow + control. + 1 + + + + + CTSEN + CTS flow control + [7:7] + + ENUM + + DISABLE_AUTO_CTS_FLO + Disable auto-cts flow + control. + 0 + + + ENABLE_AUTO_CTS_FLOW + Enable auto-cts flow + control. + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + LSR + Line Status Register. Contains flags for + transmit and receive status, including line + errors. + 0x014 + read-only + 0x60 + 0xFFFFFFFF + + + RDR + Receiver Data Ready. LSR[0] is set when + the RBR holds an unread character and is cleared when + the UART RBR FIFO is empty. + [0:0] + + ENUM + + EMPTY_ + RBR is empty. + 0 + + + VALID + RBR contains valid + data. + 1 + + + + + OE + Overrun Error. The overrun error + condition is set as soon as it occurs. A LSR read + clears LSR[1]. LSR[1] is set when UART RSR has a new + character assembled and the UART RBR FIFO is full. In + this case, the UART RBR FIFO will not be overwritten + and the character in the UART RSR will be + lost. + [1:1] + + ENUM + + INACTIVE + Overrun error status is + inactive. + 0 + + + ACTIVE + Overrun error status is + active. + 1 + + + + + PE + Parity Error. When the parity bit of a + received character is in the wrong state, a parity + error occurs. A LSR read clears LSR[2]. Time of + parity error detection is dependent on FCR[0]. Note: + A parity error is associated with the character at + the top of the UART RBR FIFO. + [2:2] + + ENUM + + INACTIVE + Parity error status is + inactive. + 0 + + + ACTIVE + Parity error status is + active. + 1 + + + + + FE + Framing Error. When the stop bit of a + received character is a logic 0, a framing error + occurs. A LSR read clears LSR[3]. The time of the + framing error detection is dependent on FCR0. Upon + detection of a framing error, the RX will attempt to + re-synchronize to the data and assume that the bad + stop bit is actually an early start bit. However, it + cannot be assumed that the next received byte will be + correct even if there is no Framing Error. Note: A + framing error is associated with the character at the + top of the UART RBR FIFO. + [3:3] + + ENUM + + INACTIVE + Framing error status is + inactive. + 0 + + + ACTIVE + Framing error status is + active. + 1 + + + + + BI + Break Interrupt. When RXD1 is held in + the spacing state (all zeros) for one full character + transmission (start, data, parity, stop), a break + interrupt occurs. Once the break condition has been + detected, the receiver goes idle until RXD1 goes to + marking state (all ones). A LSR read clears this + status bit. The time of break detection is dependent + on FCR[0]. Note: The break interrupt is associated + with the character at the top of the UART RBR + FIFO. + [4:4] + + ENUM + + INACTIVE + Break interrupt status is + inactive. + 0 + + + ACTIVE + Break interrupt status is + active. + 1 + + + + + THRE + Transmitter Holding Register Empty. THRE + is set immediately upon detection of an empty UART + THR and is cleared on a THR write. + [5:5] + + ENUM + + VALID + THR contains valid + data. + 0 + + + EMPTY_ + THR is empty. + 1 + + + + + TEMT + Transmitter Empty. TEMT is set when both + THR and TSR are empty; TEMT is cleared when either + the TSR or the THR contain valid data. + [6:6] + + ENUM + + VALID + THR and/or the TSR contains valid + data. + 0 + + + EMPTY_ + THR and the TSR are + empty. + 1 + + + + + RXFE + Error in RX FIFO. LSR[7] is set when a + character with a RX error such as framing error, + parity error or break interrupt, is loaded into the + RBR. This bit is cleared when the LSR register is + read and there are no subsequent errors in the UART + FIFO. + [7:7] + + ENUM + + NOERROR + RBR contains no UART RX errors or + FCR[0]=0. + 0 + + + ERROR + UART RBR contains at least one UART + RX error. + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + MSR + Modem status register + 0x018 + read-only + 0x00 + 0xFFFFFFFF + + + DCTS + Delta CTS. Set upon state change of + input CTS. Cleared on a MSR read. + [0:0] + + ENUM + + NO_CHANGE_DETECTED_O + No change detected on modem input + CTS. + 0 + + + STATE_CHANGE_DETECTE + State change detected on modem input + CTS. + 1 + + + + + DDSR + Delta DSR. Set upon state change of + input DSR. Cleared on a MSR read. + [1:1] + + ENUM + + NO_CHANGE_DETECTED_O + No change detected on modem input + DSR. + 0 + + + STATE_CHANGE_DETECTE + State change detected on modem input + DSR. + 1 + + + + + TERI + Trailing Edge RI. Set upon low to high + transition of input RI. Cleared on a MSR + read. + [2:2] + + ENUM + + NO_CHANGE_DETECTED_O + No change detected on modem input, + RI. + 0 + + + LOW_TO_HIGH_TRANSITI + Low-to-high transition detected on + RI. + 1 + + + + + DDCD + Delta DCD. Set upon state change of + input DCD. Cleared on a MSR read. + [3:3] + + ENUM + + NO_CHANGE_DETECTED_O + No change detected on modem input + DCD. + 0 + + + STATE_CHANGE_DETECTE + State change detected on modem input + DCD. + 1 + + + + + CTS + Clear To Send State. Complement of input + signal CTS. This bit is connected to MCR[1] in modem + loopback mode. + [4:4] + + + DSR + Data Set Ready State. Complement of + input signal DSR. This bit is connected to MCR[0] in + modem loopback mode. + [5:5] + + + RI + Ring Indicator State. Complement of + input RI. This bit is connected to MCR[2] in modem + loopback mode. + [6:6] + + + DCD + Data Carrier Detect State. Complement of + input DCD. This bit is connected to MCR[3] in modem + loopback mode. + [7:7] + + + RESERVED + Reserved + [31:8] + + + + + SCR + Scratch Pad Register. Eight-bit temporary + storage for software. + 0x01C + read-write + 0x00 + 0xFFFFFFFF + + + pad + A readable, writable byte. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + ACR + Auto-baud Control Register. Contains + controls for the auto-baud feature. + 0x020 + read-write + 0x00 + 0xFFFFFFFF + + + START + Start bit. This bit is automatically + cleared after auto-baud completion. + [0:0] + + ENUM + + STOP + Auto-baud stop (auto-baud is not + running). + 0 + + + START + Auto-baud start (auto-baud is + running). Auto-baud run bit. This bit is + automatically cleared after auto-baud + completion. + 1 + + + + + MODE + Auto-baud mode select + [1:1] + + ENUM + + MODE_0_ + Mode 0. + 0 + + + MODE_1_ + Mode 1. + 1 + + + + + AUTORESTART + Restart enable + [2:2] + + ENUM + + NO_RESTART + No restart + 0 + + + RESTART_IN_CASE_OF_T + Restart in case of time-out (counter + restarts at next UART Rx falling + edge) + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [7:3] + + + ABEOINTCLR + End of auto-baud interrupt clear (write + only accessible) + [8:8] + + ENUM + + NOIMPACT + Writing a 0 has no + impact. + 0 + + + CLEAR + Writing a 1 will clear the + corresponding interrupt in the IIR. + 1 + + + + + ABTOINTCLR + Auto-baud time-out interrupt clear + (write only accessible) + [9:9] + + ENUM + + NOIMPACT + Writing a 0 has no + impact. + 0 + + + CLEAR + Writing a 1 will clear the + corresponding interrupt in the IIR. + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:10] + + + + + FDR + Fractional Divider Register. Generates a + clock input for the baud rate divider. + 0x028 + read-write + 0x10 + 0xFFFFFFFF + + + DIVADDVAL + Baud rate generation pre-scaler divisor + value. If this field is 0, fractional baud rate + generator will not impact the UART baud + rate. + [3:0] + + + MULVAL + Baud rate pre-scaler multiplier value. + This field must be greater or equal 1 for UART to + operate properly, regardless of whether the + fractional baud rate generator is used or + not. + [7:4] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:8] + + + + + TER + Transmit Enable Register. Turns off UART + transmitter for use with software flow + control. + 0x030 + read-write + 0x80 + 0xFFFFFFFF + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [6:0] + + + TXEN + When this bit is 1, as it is after a + Reset, data written to the THR is output on the TXD + pin as soon as any preceding data has been sent. If + this bit cleared to 0 while a character is being + sent, the transmission of that character is + completed, but no further characters are sent until + this bit is set again. In other words, a 0 in this + bit blocks the transfer of characters from the THR or + TX FIFO into the transmit shift register. Software + can clear this bit when it detects that the a + hardware-handshaking TX-permit signal (CTS) has gone + false, or with software handshaking, when it receives + an XOFF character (DC3). Software can set this bit + again when it detects that the TX-permit signal has + gone true, or when it receives an XON (DC1) + character. + [7:7] + + + RESERVED + Reserved + [31:8] + + + + + RS485CTRL + RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 + modes. + 0x04C + read-write + 0x00 + 0xFFFFFFFF + + + NMMEN + NMM enable. + [0:0] + + ENUM + + DISABLED + RS-485/EIA-485 Normal Multidrop Mode + (NMM) is disabled. + 0 + + + ENABLED + RS-485/EIA-485 Normal Multidrop Mode + (NMM) is enabled. In this mode, an address is + detected when a received byte causes the UART to + set the parity error and generate an + interrupt. + 1 + + + + + RXDIS + Receiver enable. + [1:1] + + ENUM + + ENABLED + The receiver is + enabled. + 0 + + + DISABLED + The receiver is + disabled. + 1 + + + + + AADEN + AAD enable. + [2:2] + + ENUM + + DISABLED + Auto Address Detect (AAD) is + disabled. + 0 + + + ENABLED + Auto Address Detect (AAD) is + enabled. + 1 + + + + + SEL + Select direction control + pin + [3:3] + + ENUM + + RTS + If direction control is enabled (bit + DCTRL = 1), pin RTS is used for direction + control. + 0 + + + DTR + If direction control is enabled (bit + DCTRL = 1), pin DTR is used for direction + control. + 1 + + + + + DCTRL + Auto direction control + enable. + [4:4] + + ENUM + + DISABLE_AUTO_DIRECTI + Disable Auto Direction + Control. + 0 + + + ENABLE_AUTO_DIRECTIO + Enable Auto Direction + Control. + 1 + + + + + OINV + Polarity control. This bit reverses the + polarity of the direction control signal on the RTS + (or DTR) pin. + [5:5] + + ENUM + + LOW + The direction control pin will be + driven to logic 0 when the transmitter has data + to be sent. It will be driven to logic 1 after + the last bit of data has been + transmitted. + 0 + + + HIGH + The direction control pin will be + driven to logic 1 when the transmitter has data + to be sent. It will be driven to logic 0 after + the last bit of data has been + transmitted. + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:6] + + + + + RS485ADRMATCH + RS-485/EIA-485 address match. Contains the + address match value for RS-485/EIA-485 + mode. + 0x050 + read-write + 0x00 + 0xFFFFFFFF + + + ADRMATCH + Contains the address match + value. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + RS485DLY + RS-485/EIA-485 direction control + delay. + 0x054 + read-write + 0x00 + 0xFFFFFFFF + + + DLY + Contains the direction control (RTS or + DTR) delay value. This register works in conjunction + with an 8-bit counter. + [7:0] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:8] + + + + + + + CT16B0 + Product name title=UM10398 Chapter + title=LPC1100XL series: 16-bit counter/timer CT16B0/1 + Modification date=2/22/2012 Major revision=8 Minor + revision=not available + CT16B0 + 0x4000C000 + + 0x0 + 0xFFF + registers + + + CT16B0 + 16 + + + + IR + Interrupt Register (IR). The IR can be + written to clear interrupts. The IR can be read to + identify which of five possible interrupt sources are + pending. + 0x000 + read-write + 0 + 0xFFFFFFFF + + + MR0INT + Interrupt flag for match channel + 0. + [0:0] + + + MR1INT + Interrupt flag for match channel + 1. + [1:1] + + + MR2INT + Interrupt flag for match channel + 2. + [2:2] + + + MR3INT + Interrupt flag for match channel + 3. + [3:3] + + + CR0INT + Interrupt flag for capture channel 0 + event. + [4:4] + + + CR1INT + Interrupt flag for capture channel 1 + event. + [5:5] + + + RESERVED + Reserved + [31:6] + + + + + TCR + Timer Control Register (TCR). The TCR is + used to control the Timer Counter functions. The Timer + Counter can be disabled or reset through the + TCR. + 0x004 + read-write + 0 + 0xFFFFFFFF + + + CEN + Counter Enable. When one, the Timer + Counter and Prescale Counter are enabled for + counting. When zero, the counters are + disabled. + [0:0] + + + CRST + Counter Reset. When one, the Timer + Counter and the Prescale Counter are synchronously + reset on the next positive edge of PCLK. The counters + remain reset until TCR[1] is returned to + zero. + [1:1] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:2] + + + + + TC + Timer Counter (TC). The 16-bit TC is + incremented every PR+1 cycles of PCLK. The TC is + controlled through the TCR. + 0x008 + read-write + 0 + 0xFFFFFFFF + + + TC + Timer counter value. + [15:0] + + + RESERVED + Reserved. + [31:16] + + + + + PR + Prescale Register (PR). When the Prescale + Counter (below) is equal to this value, the next clock + increments the TC and clears the PC. + 0x00C + read-write + 0 + 0xFFFFFFFF + + + PR + Prescale max value. + [15:0] + + + RESERVED + Reserved. + [31:16] + + + + + PC + Prescale Counter (PC). The 16-bit PC is a + counter which is incremented to the value stored in PR. + When the value in PR is reached, the TC is incremented + and the PC is cleared. The PC is observable and + controllable through the bus interface. + 0x010 + read-write + 0 + 0xFFFFFFFF + + + PC + Prescale counter value. + [15:0] + + + RESERVED + Reserved. + [31:16] + + + + + MCR + Match Control Register (MCR). The MCR is + used to control if an interrupt is generated and if the + TC is reset when a Match occurs. + 0x014 + read-write + 0 + 0xFFFFFFFF + + + MR0I + Interrupt on MR0: an interrupt is + generated when MR0 matches the value in the + TC. + [0:0] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR0R + Reset on MR0: the TC will be reset if + MR0 matches it. + [1:1] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR0S + Stop on MR0: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR0 matches + the TC. + [2:2] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR1I + Interrupt on MR1: an interrupt is + generated when MR1 matches the value in the + TC. + [3:3] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR1R + Reset on MR1: the TC will be reset if + MR1 matches it. + [4:4] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR1S + Stop on MR1: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR1 matches + the TC. + [5:5] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR2I + Interrupt on MR2: an interrupt is + generated when MR2 matches the value in the + TC. + [6:6] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR2R + Reset on MR2: the TC will be reset if + MR2 matches it. + [7:7] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR2S + Stop on MR2: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR2 matches + the TC. + [8:8] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR3I + Interrupt on MR3: an interrupt is + generated when MR3 matches the value in the + TC. + [9:9] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR3R + Reset on MR3: the TC will be reset if + MR3 matches it. + [10:10] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR3S + Stop on MR3: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR3 matches + the TC. + [11:11] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:12] + + + + + 4 + 0x4 + 0-3 + MR%s + Match Register. MR can be enabled through + the MCR to reset the TC, stop both the TC and PC, and/or + generate an interrupt every time MR matches the + TC. + 0x018 + read-write + 0 + 0xFFFFFFFF + + + MATCH + Timer counter match value. + [15:0] + + + RESERVED + Reserved. + [31:16] + + + + + CCR + Capture Control Register (CCR). The CCR + controls which edges of the capture inputs are used to + load the Capture Registers and whether or not an + interrupt is generated when a capture takes + place. + 0x028 + read-write + 0 + 0xFFFFFFFF + + + CAP0RE + Capture on CT16Bn_CAP0 rising edge: a + sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to + be loaded with the contents of TC. + [0:0] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP0FE + Capture on CT16Bn_CAP0 falling edge: a + sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to + be loaded with the contents of TC. + [1:1] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP0I + Interrupt on CT16Bn_CAP0 event: a CR0 + load due to a CT16Bn_CAP0 event will generate an + interrupt. + [2:2] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP1RE + Capture on CT16Bn_CAP1 rising edge: a + sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to + be loaded with the contents of TC. + [3:3] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP1FE + Capture on CT16Bn_CAP1 falling edge: a + sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to + be loaded with the contents of TC. + [4:4] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP1I + Interrupt on CT16Bn_CAP1 event: a CR1 + load due to a CT16Bn_CAP1 event will generate an + interrupt. + [5:5] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:6] + + + + + 2 + 0x4 + 0-1 + CR%s + Capture Register (CR). CR is loaded with the + value of TC when there is an event on the CT16Bn_CAPm + input. + 0x02C + read-only + 0 + 0xFFFFFFFF + + + CAP + Timer counter capture + value. + [15:0] + + + RESERVED + Reserved. + [31:16] + + + + + EMR + External Match Register (EMR). The EMR + controls the match function and the external match pins + CT16B0_MAT[2:0]. + 0x03C + read-write + 0 + 0xFFFFFFFF + + + EM0 + External Match 0. This bit reflects the + state of output CT16B0_MAT0/CT16B1_MAT0, whether or + not this output is connected to its pin. When a match + occurs between the TC and MR0, this bit can either + toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] + control the functionality of this output. This bit is + driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the + match function is selected in the IOCON registers (0 + = LOW, 1 = HIGH). + [0:0] + + + EM1 + External Match 1. This bit reflects the + state of output CT16B0_MAT1/CT16B1_MAT1, whether or + not this output is connected to its pin. When a match + occurs between the TC and MR1, this bit can either + toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] + control the functionality of this output. This bit is + driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the + match function is selected in the IOCON registers (0 + = LOW, 1 = HIGH). + [1:1] + + + EM2 + External Match 2. This bit reflects the + state of output match channel 2, whether or not this + output is connected to its pin. When a match occurs + between the TC and MR2, this bit can either toggle, + go LOW, go HIGH, or do nothing. Bits EMR[9:8] control + the functionality of this output. Note that on + counter/timer 0 this match channel is not pinned out. + This bit is driven to the CT16B1_MAT2 pin if the + match function is selected in the IOCON registers (0 + = LOW, 1 = HIGH). + [2:2] + + + EM3 + External Match 3. This bit reflects the + state of output of match channel 3. When a match + occurs between the TC and MR3, this bit can either + toggle, go LOW, go HIGH, or do nothing. Bits + EMR[11:10] control the functionality of this output. + There is no output pin available for this channel on + either of the 16-bit timers. + [3:3] + + + EMC0 + External Match Control 0. Determines the + functionality of External Match 0. + [5:4] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT16Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT16Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + EMC1 + External Match Control 1. Determines the + functionality of External Match 1. + [7:6] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT16Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT16Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + EMC2 + External Match Control 2. Determines the + functionality of External Match 2. + [9:8] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT16Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT16Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + EMC3 + External Match Control 3. Determines the + functionality of External Match 3. + [11:10] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT16Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT16Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:12] + + + + + CTCR + Count Control Register (CTCR). The CTCR + selects between Timer and Counter mode, and in Counter + mode selects the signal and edge(s) for + counting. + 0x070 + read-write + 0 + 0xFFFFFFFF + + + CTM + Counter/Timer Mode. This field selects + which rising PCLK edges can increment Timer's + Prescale Counter (PC), or clear PC and increment + Timer Counter (TC). + [1:0] + + ENUM + + TIMER_MODE_EVERY_RI + Timer Mode: every rising PCLK + edge + 0x0 + + + COUNTER_MODE_TC_IS_RISING + Counter Mode: TC is incremented on + rising edges on the CAP input selected by bits + 3:2. + 0x1 + + + COUNTER_MODE_TC_IS_FALLING + Counter Mode: TC is incremented on + falling edges on the CAP input selected by bits + 3:2. + 0x2 + + + COUNTER_MODE_TC_IS_BOTH + Counter Mode: TC is incremented on + both edges on the CAP input selected by bits + 3:2. + 0x3 + + + + + CIS + Count Input Select. In counter mode + (when bits 1:0 in this register are not 00), these + bits select which CAP pin is sampled for clocking. + Note: If Counter mode is selected in the CTCR + register, bits 2:0 in the Capture Control Register + (CCR) must be programmed as 000. + [3:2] + + ENUM + + CT16BN_CAP0 + CT16Bn_CAP0 + 0x0 + + + CT16BN_CAP1 + CT16Bn_CAP1 + 0x1 + + + + + ENCC + Setting this bit to one enables clearing + of the timer and the prescaler when the capture-edge + event specified in bits 7:5 occurs. + [4:4] + + + SELCC + When bit 4 is one, these bits select + which capture input edge will cause the timer and + prescaler to be cleared. These bits have no effect + when bit 4 is zero. + [7:5] + + ENUM + + RISING_EDGE_OF_CAP0_ + Rising Edge of CAP0 clears the timer + (if bit 4 is set). + 0x0 + + + FALLING_EDGE_OF_CAP0 + Falling Edge of CAP0 clears the + timer (if bit 4 is set). + 0x1 + + + RISING_EDGE_OF_CAP1_ + Rising Edge of CAP1 clears the timer + (if bit 4 is set). + 0x2 + + + FALLING_EDGE_OF_CAP1 + Falling Edge of CAP1 clears the + timer (if bit 4 is set). + 0x3 + + + RESERVED_ + Reserved. + 0x4 + + + RESERVED_ + Reserved. + 0x5 + + + RESERVED_ + Reserved. + 0x6 + + + RESERVED_ + Reserved. + 0x7 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:8] + + + + + PWMC + PWM Control Register (PWMCON). The PWMCON + enables PWM mode for the external match pins + CT16B0_MAT[2:0]. + 0x074 + read-write + 0 + 0xFFFFFFFF + + + PWMEN0 + PWM channel0 enable + [0:0] + + ENUM + + CT16BN_MAT0_IS_CONTR + CT16Bn_MAT0 is controlled by + EM0. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for + CT16Bn_MAT0. + 1 + + + + + PWMEN1 + PWM channel1 enable + [1:1] + + ENUM + + CT16BN_MAT1_IS_CONTR + CT16Bn_MAT1 is controlled by + EM1. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for + CT16Bn_MAT1. + 1 + + + + + PWMEN2 + PWM channel2 enable + [2:2] + + ENUM + + MATCH_CHANNEL_2_OR_P + Match channel 2 or pin CT16B0_MAT2 + is controlled by EM2. Match channel 2 is not + pinned out on timer 1. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for match + channel 2 or pin CT16B0_MAT2. + 1 + + + + + PWMEN3 + PWM channel3 enable Note: It is + recommended to use match channel 3 to set the PWM + cycle because it is not pinned out. + [3:3] + + ENUM + + MATCH_CHANNEL_3_MATC + Match channel 3 match channel 3 is + controlled by EM3. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for match + channel 3match channel 3. + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:4] + + + + + + + CT16B1 + 0x40010000 + + 0 + 0xFFF + registers + + + CT16B1 + 17 + + + + CT32B0 + Product name title=UM10398 Chapter + title=LPC1100XL series: 32-bit counter/timer CT32B0/1 + Modification date=2/22/2012 Major revision=8 Minor + revision=not available + CT32B0 + 0x40014000 + + 0x0 + 0xFFF + registers + + + CT32B0 + 18 + + + + IR + Interrupt Register (IR). The IR can be + written to clear interrupts. The IR can be read to + identify which of five possible interrupt sources are + pending. + 0x000 + read-write + 0 + 0xFFFFFFFF + + + MR0INT + Interrupt flag for match channel + 0. + [0:0] + + + MR1INT + Interrupt flag for match channel + 1. + [1:1] + + + MR2INT + Interrupt flag for match channel + 2. + [2:2] + + + MR3INT + Interrupt flag for match channel + 3. + [3:3] + + + CR0INT + Interrupt flag for capture channel 0 + event. + [4:4] + + + CR1INT + Interrupt flag for capture channel 1 + event. + [5:5] + + + RESERVED + Reserved + [31:6] + + + + + TCR + Timer Control Register (TCR). The TCR is + used to control the Timer Counter functions. The Timer + Counter can be disabled or reset through the + TCR. + 0x004 + read-write + 0 + 0xFFFFFFFF + + + CEN + When one, the Timer Counter and Prescale + Counter are enabled for counting. When zero, the + counters are disabled. + [0:0] + + + CRST + When one, the Timer Counter and the + Prescale Counter are synchronously reset on the next + positive edge of PCLK. The counters remain reset + until TCR[1] is returned to zero. + [1:1] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:2] + + + + + TC + Timer Counter (TC). The 32-bit TC is + incremented every PR+1 cycles of PCLK. The TC is + controlled through the TCR. + 0x008 + read-write + 0 + 0xFFFFFFFF + + + TC + Timer counter value. + [31:0] + + + + + PR + Prescale Register (PR). When the Prescale + Counter (below) is equal to this value, the next clock + increments the TC and clears the PC. + 0x00C + read-write + 0 + 0xFFFFFFFF + + + PR + Prescale value. + [31:0] + + + + + PC + Prescale Counter (PC). The 32-bit PC is a + counter which is incremented to the value stored in PR. + When the value in PR is reached, the TC is incremented + and the PC is cleared. The PC is observable and + controllable through the bus interface. + 0x010 + read-write + 0 + 0xFFFFFFFF + + + PC + Prescale counter value. + [31:0] + + + + + MCR + Match Control Register (MCR). The MCR is + used to control if an interrupt is generated and if the + TC is reset when a Match occurs. + 0x014 + read-write + 0 + 0xFFFFFFFF + + + MR0I + Interrupt on MR0: an interrupt is + generated when MR0 matches the value in the + TC. + [0:0] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR0R + Reset on MR0: the TC will be reset if + MR0 matches it. + [1:1] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR0S + Stop on MR0: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR0 matches + the TC. + [2:2] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR1I + Interrupt on MR1: an interrupt is + generated when MR1 matches the value in the + TC. + [3:3] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR1R + Reset on MR1: the TC will be reset if + MR1 matches it. + [4:4] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR1S + Stop on MR1: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR1 matches + the TC. + [5:5] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR2I + Interrupt on MR2: an interrupt is + generated when MR2 matches the value in the + TC. + [6:6] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR2R + Reset on MR2: the TC will be reset if + MR2 matches it. + [7:7] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR2S + Stop on MR2: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR2 matches + the TC. + [8:8] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR3I + Interrupt on MR3: an interrupt is + generated when MR3 matches the value in the + TC. + [9:9] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR3R + Reset on MR3: the TC will be reset if + MR3 matches it. + [10:10] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + MR3S + Stop on MR3: the TC and PC will be + stopped and TCR[0] will be set to 0 if MR3 matches + the TC. + [11:11] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:12] + + + + + 4 + 0x4 + 0-3 + MR%s + Match Register. MR can be enabled through + the MCR to reset the TC, stop both the TC and PC, and/or + generate an interrupt every time MR matches the + TC. + 0x018 + read-write + 0 + 0xFFFFFFFF + + + MATCH + Timer counter match value. + [31:0] + + + + + CCR + Capture Control Register (CCR). The CCR + controls which edges of the capture inputs are used to + load the Capture Registers and whether or not an + interrupt is generated when a capture takes + place. + 0x028 + read-write + 0 + 0xFFFFFFFF + + + CAP0RE + Capture on CT32Bn_CAP0 rising edge: a + sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to + be loaded with the contents of TC. + [0:0] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP0FE + Capture on CT32Bn_CAP0 falling edge: a + sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to + be loaded with the contents of TC. + [1:1] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP0I + Interrupt on CT32Bn_CAP0 event: a CR0 + load due to a CT32Bn_CAP0 event will generate an + interrupt. + [2:2] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP1RE + Capture on CT32Bn_CAP1 rising edge: a + sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to + be loaded with the contents of TC. + [3:3] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP1FE + Capture on CT32Bn_CAP1 falling edge: a + sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to + be loaded with the contents of TC. + [4:4] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + CAP1I + Interrupt on CT32Bn_CAP1 event: a CR1 + load due to a CT32Bn_CAP1 event will generate an + interrupt. + [5:5] + + ENUM + + ENABLED + Enabled + 1 + + + DISABLED + Disabled + 0 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:6] + + + + + 2 + 0x4 + 0-1 + CR%s + Capture Register (CR). CR is loaded with the + value of TC when there is an event on the CT16Bn_CAPm + input. + 0x02C + read-only + 0 + 0xFFFFFFFF + + + CAP + Timer counter capture + value. + [31:0] + + + + + EMR + External Match Register (EMR). The EMR + controls the match function and the external match pins + CT32B0_MAT[3:0]. + 0x03C + read-write + 0 + 0xFFFFFFFF + + + EM0 + External Match 0. This bit reflects the + state of output CT32Bn_MAT0, whether or not this + output is connected to its pin. When a match occurs + between the TC and MR0, this bit can either toggle, + go LOW, go HIGH, or do nothing. Bits EMR[5:4] control + the functionality of this output. This bit is driven + to the CT32B0_MAT0/CT16B1_MAT0 pins if the match + function is selected in the IOCON registers (0 = LOW, + 1 = HIGH). + [0:0] + + + EM1 + External Match 1. This bit reflects the + state of output CT32Bn_MAT1, whether or not this + output is connected to its pin. When a match occurs + between the TC and MR1, this bit can either toggle, + go LOW, go HIGH, or do nothing. Bits EMR[7:6] control + the functionality of this output. This bit is driven + to the CT32B0_MAT1/CT16B1_MAT1 pins if the match + function is selected in the IOCON registers (0 = LOW, + 1 = HIGH). + [1:1] + + + EM2 + External Match 2. This bit reflects the + state of output CT32Bn_MAT2, whether or not this + output is connected to its pin. When a match occurs + between the TC and MR2, this bit can either toggle, + go LOW, go HIGH, or do nothing. Bits EMR[9:8] control + the functionality of this output. This bit is driven + to the CT32B0_MAT2/CT16B1_MAT2 pins if the match + function is selected in the IOCON registers (0 = LOW, + 1 = HIGH). + [2:2] + + + EM3 + External Match 3. This bit reflects the + state of output CT32Bn_MAT3, whether or not this + output is connected to its pin. When a match occurs + between the TC and MR3, this bit can either toggle, + go LOW, go HIGH, or do nothing. Bits EMR[11:10] + control the functionality of this output. This bit is + driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the + match function is selected in the IOCON registers (0 + = LOW, 1 = HIGH). + [3:3] + + + EMC0 + External Match Control 0. Determines the + functionality of External Match 0. + [5:4] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT32Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT32Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + EMC1 + External Match Control 1. Determines the + functionality of External Match 1. + [7:6] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT32Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT32Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + EMC2 + External Match Control 2. Determines the + functionality of External Match 2. + [9:8] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT32Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT32Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + EMC3 + External Match Control 3. Determines the + functionality of External Match 3. + [11:10] + + ENUM + + DO_NOTHING_ + Do Nothing. + 0x0 + + + CLEAR_THE_CORRESPOND + Clear the corresponding External + Match bit/output to 0 (CT32Bn_MATm pin is LOW if + pinned out). + 0x1 + + + SET_THE_CORRESPONDIN + Set the corresponding External Match + bit/output to 1 (CT32Bn_MATm pin is HIGH if + pinned out). + 0x2 + + + TOGGLE_THE_CORRESPON + Toggle the corresponding External + Match bit/output. + 0x3 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:12] + + + + + CTCR + Count Control Register (CTCR). The CTCR + selects between Timer and Counter mode, and in Counter + mode selects the signal and edge(s) for + counting. + 0x070 + read-write + 0 + 0xFFFFFFFF + + + CTM + Counter/Timer Mode. This field selects + which rising PCLK edges can increment Timer's + Prescale Counter (PC), or clear PC and increment + Timer Counter (TC). Timer Mode: every rising PCLK + edge + [1:0] + + ENUM + + TIMER_MODE_EVERY_RI + Timer Mode: every rising PCLK + edge + 0x0 + + + COUNTER_MODE_TC_IS_RISING + Counter Mode: TC is incremented on + rising edges on the CAP input selected by bits + 3:2. + 0x1 + + + COUNTER_MODE_TC_IS_FALLING + Counter Mode: TC is incremented on + falling edges on the CAP input selected by bits + 3:2. + 0x2 + + + COUNTER_MODE_TC_IS_BOTH + Counter Mode: TC is incremented on + both edges on the CAP input selected by bits + 3:2. + 0x3 + + + + + CIS + Count Input Select. When bits 1:0 in + this register are not 00, these bits select which CAP + pin is sampled for clocking: + [3:2] + + ENUM + + CT32BN_CAP0 + CT32Bn_CAP0 + 0x0 + + + CT32BN_CAP1 + CT32Bn_CAP1 + 0x1 + + + RESERVED + Reserved + 0x2 + + + RESERVED_NOTE_IF_CO + Reserved Note: If Counter mode is + selected in the TnCTCR, the 3 bits for that input + in the Capture Control Register (TnCCR) must be + programmed as 000. + 0x3 + + + + + ENCC + Setting this bit to one enables clearing + of the timer and the prescaler when the capture-edge + event specified in bits 7:5 occurs. + [4:4] + + + SELCC + When bit 4 is one, these bits select + which capture input edge will cause the timer and + prescaler to be cleared. These bits have no effect + when bit 4 is zero. + [7:5] + + ENUM + + RISING_EDGE_OF_CAP0_ + Rising Edge of CAP0 clears the timer + (if bit 4 is set). + 0x0 + + + FALLING_EDGE_OF_CAP0 + Falling Edge of CAP0 clears the + timer (if bit 4 is set). + 0x1 + + + RISING_EDGE_OF_CAP1_ + Rising Edge of CAP1 clears the timer + (if bit 4 is set). + 0x2 + + + FALLING_EDGE_OF_CAP1 + Falling Edge of CAP1 clears the + timer (if bit 4 is set). + 0x3 + + + RESERVED_ + Reserved. + 0x4 + + + RESERVED_ + Reserved. + 0x5 + + + RESERVED_ + Reserved. + 0x6 + + + RESERVED_ + Reserved. + 0x7 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:8] + + + + + PWMC + PWM Control Register (PWMCON). The PWMCON + enables PWM mode for the external match pins + CT32B0_MAT[3:0]. + 0x074 + read-write + 0 + 0xFFFFFFFF + + + PWMEN0 + PWM channel 0 enable + [0:0] + + ENUM + + CT32BN_MAT0_IS_CONTR + CT32Bn_MAT0 is controlled by + EM0. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for + CT32Bn_MAT0. + 1 + + + + + PWMEN1 + PWM channel 1 enable + [1:1] + + ENUM + + CT32BN_MAT1_IS_CONTR + CT32Bn_MAT1 is controlled by + EM1. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for + CT32Bn_MAT1. + 1 + + + + + PWMEN2 + PWM channel 2 enable + [2:2] + + ENUM + + CT32BN_MAT2_IS_CONTR + CT32Bn_MAT2 is controlled by + EM2. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for + CT32Bn_MAT2. + 1 + + + + + PWMEN3 + PWM channel 3 enable Note: It is + recommended to use match channel 3 to set the PWM + cycle. + [3:3] + + ENUM + + CT32BN_MAT3_IS_CONTR + CT32Bn_MAT3 is controlled by + EM3. + 0 + + + PWM_MODE_IS_ENABLED_ + PWM mode is enabled for + CT32Bn_MAT3. + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:4] + + + + + + + CT32B1 + 0x40018000 + + 0 + 0xFFF + registers + + + CT32B1 + 19 + + + + ADC + 10-bit ADC + ADC + 0x4001C000 + + 0 + 0xFFF + registers + + + ADC + 24 + + + + CR + A/D Control Register. The ADCR register must + be written to select the operating mode before A/D + conversion can occur. + 0x000 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEL + Selects which of the AD7:0 pins is (are) + to be sampled and converted. Bit 0 selects Pin AD0, + bit 1 selects pin AD1,..., and bit 7 selects pin AD7. + In software-controlled mode (BURST = 0), only one + channel can be selected, i.e. only one of these bits + should be 1. In hardware scan mode (BURST = 1), any + numbers of channels can be selected, i.e any or all + bits can be set to 1. If all bits are set to 0, + channel 0 is selected automatically (SEL = + 0x01). + [7:0] + + + CLKDIV + The APB clock (PCLK) is divided by + CLKDIV +1 to produce the clock for the ADC, which + should be less than or equal to 4.5 MHz. Typically, + software should program the smallest value in this + field that yields a clock of 4.5 MHz or slightly + less, but in certain cases (such as a high-impedance + analog source) a slower clock may be + desirable. + [15:8] + + + BURST + Burst mode + [16:16] + + test + + SWMODE + Software-controlled mode: + Conversions are software-controlled and require + 11 clocks. + 0 + + + HWMODE + Hardware scan mode: The AD converter + does repeated conversions at the rate selected by + the CLKS field, scanning (if necessary) through + the pins selected by 1s in the SEL field. The + first conversion after the start corresponds to + the least-significant bit set to 1 in the SEL + field, then the next higher bits (pins) set to 1 + are scanned if applicable. Repeated conversions + can be terminated by clearing this bit, but the + conversion in progress when this bit is cleared + will be completed. Important: START bits must be + 000 when BURST = 1 or conversions will not + start. + 1 + + + + + CLKS + This field selects the number of clocks + used for each conversion in Burst mode, and the + number of bits of accuracy of the result in the LS + bits of ADDR, between 11 clocks (10 bits) and 4 + clocks (3 bits). + [19:17] + + test + + 10BIT + 11 clocks / 10 bits + 0x0 + + + 9BIT + 10 clocks / 9 bits + 0x1 + + + 8BIT + 9 clocks / 8 bits + 0x2 + + + 7BIT + 8 clocks / 7 bits + 0x3 + + + 6BIT + 7 clocks / 6 bits + 0x4 + + + 5BIT + 6 clocks / 5 bits + 0x5 + + + 4BIT + 5 clocks / 4 bits + 0x6 + + + 3BIT + 4 clocks / 3 bits + 0x7 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [23:20] + + + START + When the BURST bit is 0, these bits + control whether and when an A/D conversion is + started: + [26:24] + + test + + STOP + No start (this value should be used + when clearing PDN to 0). + 0x0 + + + START + Start conversion now. + 0x1 + + + EDGEPIO0_2 + Start conversion when the edge + selected by bit 27 occurs on + PIO0_2/SSEL/CT16B0_CAP0. + 0x2 + + + EDGEPIO1_5 + Start conversion when the edge + selected by bit 27 occurs on + PIO1_5/DIR/CT32B0_CAP0. + 0x3 + + + EDGECT32B0_MAT0_1 + Start conversion when the edge + selected by bit 27 occurs on + CT32B0_MAT0[1]. + 0x4 + + + EDGECT32B0_MAT1_1 + Start conversion when the edge + selected by bit 27 occurs on + CT32B0_MAT1[1]. + 0x5 + + + EDGECT16B0_MAT0_1 + Start conversion when the edge + selected by bit 27 occurs on + CT16B0_MAT0[1]. + 0x6 + + + EDGECT16B0_MAT1_1 + Start conversion when the edge + selected by bit 27 occurs on + CT16B0_MAT1[1]. + 0x7 + + + + + EDGE + This bit is significant only when the + START field contains 010-111. In these cases: Start + conversion on a falling edge on the selected CAP/MAT + signal. + [27:27] + + test + + RISING + Start conversion on a rising edge on + the selected CAP/MAT signal. + 0 + + + FALLING + Start conversion on a rising edge on + the selected CAP/MAT signal. + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:28] + + + + + GDR + A/D Global Data Register. Contains the + result of the most recent A/D conversion. + 0x004 + read-write + 0 + 0x00000000 + + + RESERVED + Reserved. These bits always read as + zeroes. + [5:0] + + + V_VREF + When DONE is 1, this field contains a + binary fraction representing the voltage on the ADn + pin selected by the SEL field, divided by the voltage + on the VDD pin. Zero in the field indicates that the + voltage on the ADn pin was less than, equal to, or + close to that on VSS, while 0x3FF indicates that the + voltage on ADn was close to, equal to, or greater + than that on VREF. + [15:6] + + + RESERVED + Reserved. These bits always read as + zeroes. + [23:16] + + + CHN + These bits contain the channel from + which the result bits V_VREF were + converted. + [26:24] + + + RESERVED + Reserved. These bits always read as + zeroes. + [29:27] + + + OVERRUN + This bit is 1 in burst mode if the + results of one or more conversions was (were) lost + and overwritten before the conversion that produced + the result in the V_VREF bits. + [30:30] + + + DONE + This bit is set to 1 when an A/D + conversion completes. It is cleared when this + register is read and when the ADCR is written. If the + ADCR is written while a conversion is still in + progress, this bit is set and a new conversion is + started. + [31:31] + + + + + STAT + A/D Status Register. This register contains + DONE and OVERRUN flags for all of the A/D channels, as + well as the A/D interrupt flag. + 0x030 + read-only + 0 + 0xFFFFFFFF + + + DONE + These bits mirror the DONE status flags + that appear in the result register for each A/D + channel n. + [7:0] + + + OVERRUN + These bits mirror the OVERRRUN status + flags that appear in the result register for each A/D + channel n. Reading ADSTAT allows checking the status + of all A/D channels simultaneously. + [15:8] + + + ADINT + This bit is the A/D interrupt flag. It + is one when any of the individual A/D channel Done + flags is asserted and enabled to contribute to the + A/D interrupt via the ADINTEN register. + [16:16] + + + RESERVED + Unused, always 0. + [31:17] + + + + + INTEN + A/D Interrupt Enable Register. This register + contains enable bits that allow the DONE flag of each A/D + channel to be included or excluded from contributing to + the generation of an A/D interrupt. + 0x00C + read-write + 0x00000100 + 0xFFFFFFFF + + + ADINTENn + These bits allow control over which A/D + channels generate interrupts for conversion + completion. When bit 0 is one, completion of a + conversion on A/D channel 0 will generate an + interrupt, when bit 1 is one, completion of a + conversion on A/D channel 1 will generate an + interrupt, etc. + [7:0] + + + ADGINTEN + When 1, enables the global DONE flag in + ADDR to generate an interrupt. When 0, only the + individual A/D channels enabled by ADINTEN 7:0 will + generate interrupts. + [8:8] + + + RESERVED + Unused, always 0. + [31:9] + + + + + 8 + 0x4 + 0-7 + DR%s + A/D Channel n Data Register. This register + contains the result of the most recent conversion + completed on channel n. + 0x010 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + Reserved, always 0. These bits always + read as zeroes. + [5:0] + + + V_VREF + When DONE is 1, this field contains a + binary fraction representing the voltage on the ADn + pin, divided by the voltage on the VREF pin. Zero in + the field indicates that the voltage on the ADn pin + was less than, equal to, or close to that on VREF, + while 0x3FF indicates that the voltage on AD input + was close to, equal to, or greater than that on + VREF. + [15:6] + + + RESERVED + These bits always read as + zeroes. + [29:16] + + + OVERRUN + This bit is 1 in burst mode if the + results of one or more conversions was (were) lost + and overwritten before the conversion that produced + the result in the V_VREF bits.This bit is cleared by + reading this register. + [30:30] + + + DONE + This bit is set to 1 when an A/D + conversion completes. It is cleared when this + register is read. + [31:31] + + + + + + + PMU + power management unit + PMU + 0x40038000 + + 0 + 0xFFF + registers + + + + PCON + Power control register + 0x000 + read-write + 0x0 + 0xFFFFFFFF + + + RESERVED + Reserved. Do not write 1 to this + bit. + [0:0] + + + DPDEN + Deep power-down mode + enable + [1:1] + + test + + SLEEPMODE + ARM WFI will enter Sleep or + Deep-sleep mode (clock to ARM Cortex-M0 core + turned off). + 0 + + + DEEPPOWERDOWN + ARM WFI will enter Deep-power down + mode (ARM Cortex-M0 core + powered-down). + 1 + + + + + RESERVED + Reserved. Do not write ones to this + bit. + [7:2] + + + SLEEPFLAG + Sleep mode flag + [8:8] + + test + + NOPOWERDOWN + Read: No power-down mode entered. + LPC111x/LPC11C1x is in Active mode. Write: No + effect. + 0 + + + POWERDOWN + Read: Sleep/Deep-sleep or Deep + power-down mode entered. Write: Writing a 1 + clears the SLEEPFLAG bit to 0. + 1 + + + + + RESERVED + Reserved. Do not write ones to this + bit. + [10:9] + + + DPDFLAG + Deep power-down flag + [11:11] + + test + + NODEEPPOWERDOWN + Read: Deep power-down mode not + entered. Write: No effect. + 0 + + + DEEPPOWERDOWN + Read: Deep power-down mode entered. + Write: Clear the Deep power-down + flag. + 1 + + + + + RESERVED + Reserved. Do not write ones to this + bit. + [31:12] + + + + + 4 + 0x4 + 0-3 + GPREG%s + General purpose register + 0x004 + read-write + 0x0 + 0xFFFFFFFF + + + GPDATA + Data retained during Deep power-down + mode. + [31:0] + + + + + GPREG4 + General purpose register 4 + 0x014 + read-write + 0x0 + 0xFFFFFFFF + + + RESERVED + Reserved. Do not write ones to this + bit. + [9:0] + + + WAKEUPHYS + WAKEUP pin hysteresis + enable + [10:10] + + test + + ENABLED + Hysteresis for WAKEUP pin + enabled. + 1 + + + DISABLED + Hysteresis for WAKUP pin + disabled. + 0 + + + + + GPDATA + Data retained during Deep power-down + mode. + [31:11] + + + + + + + FLASHCTRL + Product name title=UM10462 Chapter + title=LPC11U1x Flash programming firmware Modification + date=3/17/2011 Major revision=0 Minor + revision=3 + FLASHCTRL + 0x4003C000 + + 0 + 0xFFF + registers + + + FMC + 27 + + + + FLASHCFG + Flash memory access time configuration + register + 0x010 + read-write + 0 + 0x00000000 + + + FLASHTIM + Flash memory access time. FLASHTIM +1 is + equal to the number of system clocks used for flash + access. + [1:0] + + ENUM + + 1_SYSTEM_CLOCK_FLASH + 1 system clock flash access time + (for system clock frequencies of up to 20 + MHz). + 0x1 + + + 2_SYSTEM_CLOCKS_FLAS + 2 system clocks flash access time + (for system clock frequencies of up to 40 + MHz). + 0x2 + + + 3_SYSTEM_CLOCKS_FLAS + 3 system clocks flash access time + (for system clock frequencies of up to 50 + MHz). + 0x3 + + + + + RESERVED + Reserved. User software must not change + the value of these bits. Bits 31:2 must be written + back exactly as read. + [31:2] + + + + + FMSSTART + Signature start address + register + 0x020 + read-write + 0 + 0xFFFFFFFF + + + START + Signature generation start address + (corresponds to AHB byte address + bits[20:4]). + [16:0] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:17] + + + + + FMSSTOP + Signature stop-address + register + 0x024 + read-write + 0 + 0xFFFFFFFF + + + STOP + BIST stop address divided by 16 + (corresponds to AHB byte address + [20:4]). + [16:0] + + + SIG_START + Start control bit for signature + generation. + [17:17] + + ENUM + + SIGNATURE_GENERATION + Signature generation is + stopped + 0 + + + INITIATE_SIGNATURE_G + Initiate signature + generation + 1 + + + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:18] + + + + + FMSW0 + Word 0 [31:0] + 0x02C + read-only + 0 + 0x00000000 + + + SW0_31_0 + Word 0 of 128-bit signature (bits 31 to + 0). + [31:0] + + + + + FMSW1 + Word 1 [63:32] + 0x030 + read-only + 0 + 0x00000000 + + + SW1_63_32 + Word 1 of 128-bit signature (bits 63 to + 32). + [31:0] + + + + + FMSW2 + Word 2 [95:64] + 0x034 + read-only + 0 + 0x00000000 + + + SW2_95_64 + Word 2 of 128-bit signature (bits 95 to + 64). + [31:0] + + + + + FMSW3 + Word 3 [127:96] + 0x038 + read-only + 0 + 0x00000000 + + + SW3_127_96 + Word 3 of 128-bit signature (bits 127 to + 96). + [31:0] + + + + + FMSTAT + Signature generation status + register + 0xFE0 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [1:0] + + + SIG_DONE + When 1, a previously started signature + generation has completed. See FMSTATCLR register + description for clearing this flag. + [2:2] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:3] + + + + + FMSTATCLR + Signature generation status clear + register + 0xFE8 + write-only + 0 + 0x00000000 + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [1:0] + + + SIG_DONE_CLR + Writing a 1 to this bits clears the + signature generation completion flag (SIG_DONE) in + the FMSTAT register. + [2:2] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:3] + + + + + + + SPI0 + SPI0 + SPI + 0x40040000 + + 0 + 0xFFF + registers + + + SPI0 + 20 + + + + CR0 + Control Register 0. Selects the serial clock + rate, bus type, and data size. + 0x000 + read-write + 0 + 0xFFFFFFFF + + + DSS + Data Size Select. This field controls + the number of bits transferred in each frame. Values + 0000-0010 are not supported and should not be + used. + [3:0] + + ENUM + + 4_BIT_TRANSFER + 4-bit transfer + 0x3 + + + 5_BIT_TRANSFER + 5-bit transfer + 0x4 + + + 6_BIT_TRANSFER + 6-bit transfer + 0x5 + + + 7_BIT_TRANSFER + 7-bit transfer + 0x6 + + + 8_BIT_TRANSFER + 8-bit transfer + 0x7 + + + 9_BIT_TRANSFER + 9-bit transfer + 0x8 + + + 10_BIT_TRANSFER + 10-bit transfer + 0x9 + + + 11_BIT_TRANSFER + 11-bit transfer + 0xA + + + 12_BIT_TRANSFER + 12-bit transfer + 0xB + + + 13_BIT_TRANSFER + 13-bit transfer + 0xC + + + 14_BIT_TRANSFER + 14-bit transfer + 0xD + + + 15_BIT_TRANSFER + 15-bit transfer + 0xE + + + 16_BIT_TRANSFER + 16-bit transfer + 0xF + + + + + FRF + Frame Format. + [5:4] + + ENUM + + SPI + SPI + 0x0 + + + TI + TI + 0x1 + + + MICROWIRE + Microwire + 0x2 + + + RESERVED + This combination is not supported + and should not be used. + 0x3 + + + + + CPOL + Clock Out Polarity. This bit is only + used in SPI mode. + [6:6] + + ENUM + + LOW + SPI controller maintains the bus + clock low between frames. + 0 + + + HIGH + SPI controller maintains the bus + clock high between frames. + 1 + + + + + CPHA + Clock Out Phase. This bit is only used + in SPI mode. + [7:7] + + ENUM + + FIRSTCLOCK + SPI controller captures serial data + on the first clock transition of the frame, that + is, the transition away from the inter-frame + state of the clock line. + 0 + + + SECONDCLOCK + SPI controller captures serial data + on the second clock transition of the frame, that + is, the transition back to the inter-frame state + of the clock line. + 1 + + + + + SCR + Serial Clock Rate. The number of + prescaler output clocks per bit on the bus, minus + one. Given that CPSDVSR is the prescale divider, and + the APB clock PCLK clocks the prescaler, the bit + frequency is PCLK / (CPSDVSR X + [SCR+1]). + [15:8] + + + RESERVED + Reserved + [31:16] + + + + + CR1 + Control Register 1. Selects master/slave and + other modes. + 0x004 + read-write + 0 + 0xFFFFFFFF + + + LBM + Loop Back Mode. + [0:0] + + test + + NORMAL + During normal + operation. + 0 + + + LOOPBACK + Serial input is taken from the + serial output (MOSI or MISO) rather than the + serial input pin (MISO or MOSI + respectively). + 1 + + + + + SSE + SPI Enable. + [1:1] + + test + + DISABLE + The SPI controller is + disabled. + 0 + + + ENABLE + The SPI controller will interact + with other devices on the serial bus. Software + should write the appropriate control information + to the other SPI/SSP registers and interrupt + controller registers, before setting this + bit. + 1 + + + + + MS + Master/Slave Mode.This bit can only be + written when the SSE bit is 0. + [2:2] + + test + + MASTER + The SPI controller acts as a master + on the bus, driving the SCLK, MOSI, and SSEL + lines and receiving the MISO line. + 0 + + + SLAVE + The SPI controller acts as a slave + on the bus, driving MISO line and receiving SCLK, + MOSI, and SSEL lines. + 1 + + + + + SOD + Slave Output Disable. This bit is + relevant only in slave mode (MS = 1). If it is 1, + this blocks this SPI controller from driving the + transmit data line (MISO). + [3:3] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:4] + + + + + DR + Data Register. Writes fill the transmit + FIFO, and reads empty the receive FIFO. + 0x008 + read-write + 0 + 0xFFFFFFFF + + + DATA + Write: software can write data to be + sent in a future frame to this register whenever the + TNF bit in the Status register is 1, indicating that + the Tx FIFO is not full. If the Tx FIFO was + previously empty and the SPI controller is not busy + on the bus, transmission of the data will begin + immediately. Otherwise the data written to this + register will be sent as soon as all previous data + has been sent (and received). If the data length is + less than 16 bit, software must right-justify the + data written to this register. Read: software can + read data from this register whenever the RNE bit in + the Status register is 1, indicating that the Rx FIFO + is not empty. When software reads this register, the + SPI controller returns data from the least recent + frame in the Rx FIFO. If the data length is less than + 16 bit, the data is right-justified in this field + with higher order bits filled with 0s. + [15:0] + + + RESERVED + Reserved. + [31:16] + + + + + SR + Status Register + 0x00C + read-only + 0x00000003 + 0xFFFFFFFF + + + TFE + Transmit FIFO Empty. This bit is 1 is + the Transmit FIFO is empty, 0 if not. + [0:0] + + + TNF + Transmit FIFO Not Full. This bit is 0 if + the Tx FIFO is full, 1 if not. + [1:1] + + + RNE + Receive FIFO Not Empty. This bit is 0 if + the Receive FIFO is empty, 1 if not. + [2:2] + + + RFF + Receive FIFO Full. This bit is 1 if the + Receive FIFO is full, 0 if not. + [3:3] + + + BSY + Busy. This bit is 0 if the SPI + controller is idle, 1 if it is currently + sending/receiving a frame and/or the Tx FIFO is not + empty. + [4:4] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:5] + + + + + CPSR + Clock Prescale Register + 0x010 + read-write + 0 + 0xFFFFFFFF + + + CPSDVSR + This even value between 2 and 254, by + which SPI_PCLK is divided to yield the prescaler + output clock. Bit 0 always reads as 0. + [7:0] + + + RESERVED + Reserved. + [31:8] + + + + + IMSC + Interrupt Mask Set and Clear + Register + 0x014 + read-write + 0 + 0xFFFFFFFF + + + RORIM + Software should set this bit to enable + interrupt when a Receive Overrun occurs, that is, + when the Rx FIFO is full and another frame is + completely received. The ARM spec implies that the + preceding frame data is overwritten by the new frame + data when this occurs. + [0:0] + + + RTIM + Software should set this bit to enable + interrupt when a Receive Time-out condition occurs. A + Receive Time-out occurs when the Rx FIFO is not + empty, and no has not been read for a time-out + period. The time-out period is the same for master + and slave modes and is determined by the SSP bit + rate: 32 bits at PCLK / (CPSDVSR x + [SCR+1]). + [1:1] + + + RXIM + Software should set this bit to enable + interrupt when the Rx FIFO is at least half + full. + [2:2] + + + TXIM + Software should set this bit to enable + interrupt when the Tx FIFO is at least half + empty. + [3:3] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:4] + + + + + RIS + Raw Interrupt Status Register + 0x018 + read-only + 0x00000008 + 0xFFFFFFFF + + + RORRIS + This bit is 1 if another frame was + completely received while the RxFIFO was full. The + ARM spec implies that the preceding frame data is + overwritten by the new frame data when this + occurs. + [0:0] + + + RTRIS + This bit is 1 if the Rx FIFO is not + empty, and has not been read for a time-out period. + The time-out period is the same for master and slave + modes and is determined by the SSP bit rate: 32 bits + at PCLK / (CPSDVSR x [SCR+1]). + [1:1] + + + RXRIS + This bit is 1 if the Rx FIFO is at least + half full. + [2:2] + + + TXRIS + This bit is 1 if the Tx FIFO is at least + half empty. + [3:3] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:4] + + + + + MIS + Masked Interrupt Status + Register + 0x01C + read-only + 0 + 0xFFFFFFFF + + + RORMIS + This bit is 1 if another frame was + completely received while the RxFIFO was full, and + this interrupt is enabled. + [0:0] + + + RTMIS + This bit is 1 if the Rx FIFO is not + empty, has not been read for a time-out period, and + this interrupt is enabled. The time-out period is the + same for master and slave modes and is determined by + the SSP bit rate: 32 bits at PCLK / (CPSDVSR x + [SCR+1]). + [1:1] + + + RXMIS + This bit is 1 if the Rx FIFO is at least + half full, and this interrupt is + enabled. + [2:2] + + + TXMIS + This bit is 1 if the Tx FIFO is at least + half empty, and this interrupt is + enabled. + [3:3] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:4] + + + + + ICR + SSPICR Interrupt Clear + Register + 0x020 + write-only + 0 + 0x00000000 + + + RORIC + Writing a 1 to this bit clears the frame + was received when RxFIFO was full + interrupt. + [0:0] + + + RTIC + Writing a 1 to this bit clears the Rx + FIFO was not empty and has not been read for a + timeout period interrupt. The timeout period is the + same for master and slave modes and is determined by + the SSP bit rate: 32 bits at PCLK / (CPSDVSR x + [SCR+1]). + [1:1] + + + RESERVED + Reserved, user software should not write + ones to reserved bits. The value read from a reserved + bit is not defined. + [31:2] + + + + + + + IOCON + Product name title=UM10398 Chapter + title=LPC1100XL series: I/O configuration (IOCONFIG) + Modification date=2/22/2012 Major revision=8 Minor + revision=not available + IOCON + 0x40044000 + + 0x0 + 0xFFF + registers + + + + IOCON_PIO2_6 + I/O configuration for pin PIO2_6/ + CT32B0_MAT1 + 0x000 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_6. + 0x0 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT1. + 0x1 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_0 + I/O configuration for pin + PIO2_0/DTR/SSEL1 + 0x008 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_0. + 0x0 + + + SELECT_FUNCTION_DTR_ + Select function DTR. + 0x1 + + + SELECT_FUNCTION_SSEL + Select function SSEL1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_RESET_PIO0_0 + I/O configuration for pin + RESET/PIO0_0 + 0x00C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_RES + Selects function + RESET. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO0_0. + 0x1 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_1 + I/O configuration for pin + PIO0_1/CLKOUT/CT32B0_MAT2 + 0x010 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_1. + 0x0 + + + SELECTS_FUNCTION_CLK + Selects function + CLKOUT. + 0x1 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT2. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_8 + I/O configuration for pin + PIO1_8/CT16B1_CAP0 + 0x014 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_8. + 0x0 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B1_CAP0. + 0x1 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_2 + I/O configuration for pin + PIO0_2/SSEL0/CT16B0_CAP0 + 0x01C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_2. + 0x0 + + + SELECTS_FUNCTION_SSE + Selects function + SSEL0. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_CAP0. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_7 + I/O configuration for pin PIO2_7/ + CT32B0_MAT2/RXD + 0x020 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_7. + 0x0 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT2. + 0x1 + + + SELECTS_FUNCTION_RXD + Selects function RXD. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_8 + I/O configuration for pin PIO2_8/ + CT32B0_MAT3/TXD + 0x024 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_8. + 0x0 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT3. + 0x1 + + + SELECTS_FUNCTION_TXD + Selects function TXD. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_1 + I/O configuration for pin + PIO2_1/DSR/SCK1 + 0x028 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_1. + 0x0 + + + SELECT_FUNCTION_DSR_ + Select function DSR. + 0x1 + + + SELECT_FUNCTION_SCK1 + Select function SCK1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_3 + I/O configuration for pin + PIO0_3 + 0x02C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_3. + 0x0 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_4 + I/O configuration for pin + PIO0_4/SCL + 0x030 + read-write + 0x00 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function PIO0_4 (open-drain + pin). + 0x0 + + + SELECTS_I2C_FUNCTION + Selects I2C function SCL (open-drain + pin). + 0x1 + + + + + I2CMODE + Selects I2C mode. Select Standard mode + (I2CMODE = 00, default) or Standard I/O functionality + (I2CMODE = 01) if the pin function is GPIO (FUNC = + 000). + [9:8] + + ENUM + + STANDARD_MODE_FAST + Standard mode/ Fast-mode + I2C. + 0x0 + + + STANDARD_IO_FUNCTION + Standard I/O + functionality + 0x1 + + + FAST_MODE_PLUS_I2C + Fast-mode Plus I2C + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:10] + + + + + IOCON_PIO0_5 + I/O configuration for pin + PIO0_5/SDA + 0x034 + read-write + 0x00 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function PIO0_5 (open-drain + pin). + 0x0 + + + SELECTS_I2C_FUNCTION + Selects I2C function SDA (open-drain + pin). + 0x1 + + + + + I2CMODE + Selects I2C mode. Select Standard mode + (I2CMODE = 00, default) or Standard I/O functionality + (I2CMODE = 01) if the pin function is GPIO (FUNC = + 000). + [9:8] + + ENUM + + STANDARD_MODE_FAST + Standard mode/ Fast-mode + I2C. + 0x0 + + + STANDARD_IO_FUNCTION + Standard I/O + functionality + 0x1 + + + FAST_MODE_PLUS_I2C + Fast-mode Plus I2C + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:10] + + + + + IOCON_PIO1_9 + I/O configuration for pin + PIO1_9/CT16B1_MAT0/ MOSI1 + 0x038 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_9. + 0x0 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B1_MAT0. + 0x1 + + + SELECTS_FUNCTION_MOS + Selects function + MOSI1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO3_4 + I/O configuration for pin PIO3_4/ + CT16B0_CAP1/RXD + 0x03C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO3_4. + 0x0 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_CAP1. + 0x1 + + + SELECTS_FUNCTION_RXD + Selects function RXD. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_4 + I/O configuration for pin PIO2_4/ + CT16B1_MAT1/ SSEL1 + 0x040 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_4. + 0x0 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B1_MAT1. + 0x1 + + + SELECTS_FUNCTION_SSE + Selects function + SSEL1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_5 + I/O configuration for pin PIO2_5/ + CT32B0_MAT0 + 0x044 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_5. + 0x0 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT0. + 0x1 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO3_5 + I/O configuration for pin PIO3_5/ + CT16B1_CAP1/TXD + 0x048 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO3_5. + 0x0 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B1_CAP1. + 0x1 + + + SELECTS_FUNCTION_TXD + Selects function TXD. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_6 + I/O configuration for pin + PIO0_6/SCK0 + 0x04C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_6. + 0x0 + + + RESERVED_ + Reserved. + 0x1 + + + SELECTS_FUNCTION_SCK + Selects function SCK0 (only if pin + PIO0_6/SCK0 selected in Table 147). + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_7 + I/O configuration for pin + PIO0_7/CTS + 0x050 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_7. + 0x0 + + + SELECT_FUNCTION_CTS_ + Select function CTS. + 0x1 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_9 + I/O configuration for pin PIO2_9/ + CT32B0_CAP0 + 0x054 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_9. + 0x0 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_CAP0. + 0x1 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_10 + I/O configuration for pin + PIO2_10 + 0x058 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_10. + 0x0 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_2 + I/O configuration for pin + PIO2_2/DCD/MISO1 + 0x05C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_2. + 0x0 + + + SELECT_FUNCTION_DCD_ + Select function DCD. + 0x1 + + + SELECT_FUNCTION_MISO + Select function MISO1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_8 + I/O configuration for pin + PIO0_8/MISO0/CT16B0_MAT0 + 0x060 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_8. + 0x0 + + + SELECTS_FUNCTION_MIS + Selects function + MISO0. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_MAT0. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO0_9 + I/O configuration for pin + PIO0_9/MOSI0/CT16B0_MAT1 + 0x064 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO0_9. + 0x0 + + + SELECTS_FUNCTION_MOS + Selects function + MOSI0. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_MAT1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_SWCLK_PIO0_10 + I/O configuration for pin SWCLK/PIO0_10/ + SCK0/CT16B0_MAT2 + 0x068 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_SWC + Selects function + SWCLK. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO0_10. + 0x1 + + + SELECTS_FUNCTION_SCK + Selects function SCK0 (only if pin + SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table + 147). + 0x2 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_MAT2. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_10 + I/O configuration for pin + PIO1_10/AD6/CT16B1_MAT1/ MISO1 + 0x06C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_10. + 0x0 + + + SELECTS_FUNCTION_AD6 + Selects function AD6. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B1_MAT1. + 0x2 + + + SELECTS_FUNCTION_MIS + Selects function + MISO1. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_11 + I/O configuration for pin PIO2_11/SCK0/ + CT32B0_CAP1 + 0x070 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_11. + 0x0 + + + SELECT_FUNCTION_SCK0 + Select function SCK0 (only if pin + PIO2_11/SCK0 selected in Table + 147). + 0x1 + + + SELECT_FUNCTION_CT32 + Select function + CT32B0_CAP1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_R_PIO0_11 + I/O configuration for pin + R/PIO0_11/AD0/CT32B0_MAT3 + 0x074 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_R_ + Selects function R. This function is + reserved. Select one of the alternate functions + below. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO0_11. + 0x1 + + + SELECTS_FUNCTION_AD0 + Selects function AD0. + 0x2 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT3. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_R_PIO1_0 + I/O configuration for pin + R/PIO1_0/AD1/CT32B1_CAP0 + 0x078 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_R_ + Selects function R. This function is + reserved. Select one of the alternate functions + below. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO1_0. + 0x1 + + + SELECTS_FUNCTION_AD1 + Selects function AD1. + 0x2 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B1_CAP0. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_R_PIO1_1 + I/O configuration for pin + R/PIO1_1/AD2/CT32B1_MAT0 + 0x07C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_R_ + Selects function R. This function is + reserved. Select one of the alternate functions + below. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO1_1. + 0x1 + + + SELECTS_FUNCTION_AD2 + Selects function AD2. + 0x2 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B1_MAT0. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_R_PIO1_2 + I/O configuration for pin + R/PIO1_2/AD3/CT32B1_MAT1 + 0x080 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_R_ + Selects function R. This function is + reserved. Select one of the alternate functions + below. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO1_2. + 0x1 + + + SELECTS_FUNCTION_AD3 + Selects function AD3. + 0x2 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B1_MAT1. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO3_0 + I/O configuration for pin + PIO3_0/DTR/CT16B0_MAT0/TXD + 0x084 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO3_0. + 0x0 + + + SELECTS_FUNCTION_DTR + Selects function DTR. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_MAT0. + 0x2 + + + SELECTS_FUNCTION_TXD + Selects function TXD. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO3_1 + I/O configuration for pin + PIO3_1/DSR/CT16B0_MAT1/RXD + 0x088 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO3_1. + 0x0 + + + SELECTS_FUNCTION_DSR + Selects function DSR. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_MAT1. + 0x2 + + + SELECTS_FUNCTION_RXD + Selects function RXD. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO2_3 + I/O configuration for pin + PIO2_3/RI/MOSI1 + 0x08C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO2_3. + 0x0 + + + SELECTS_FUNCTION_RI_ + Selects function RI. + 0x1 + + + SELECTS_FUNCTION_MOS + Selects function + MOSI1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_SWDIO_PIO1_3 + I/O configuration for pin + SWDIO/PIO1_3/AD4/CT32B1_MAT2 + 0x090 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_SWD + Selects function + SWDIO. + 0x0 + + + SELECTS_FUNCTION_PIO + Selects function + PIO1_3. + 0x1 + + + SELECTS_FUNCTION_AD4 + Selects function AD4. + 0x2 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B1_MAT2. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_4 + I/O configuration for pin + PIO1_4/AD5/CT32B1_MAT3 + 0x094 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. This pin functions + as WAKEUP pin if the LPC111x/LPC11Cxx is in Deep + power-down mode regardless of the value of FUNC. All + other values are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_4. + 0x0 + + + SELECTS_FUNCTION_AD5 + Selects function AD5. + 0x1 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B1_MAT3. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_11 + I/O configuration for pin + PIO1_11/AD7/CT32B1_CAP1 + 0x098 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_11. + 0x0 + + + SELECTS_FUNCTION_AD7 + Selects function AD7. + 0x1 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B1_CAP1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [6:6] + + + ADMODE + Selects Analog/Digital + mode + [7:7] + + ENUM + + ANALOG_INPUT_MODE + Analog input mode + 0 + + + DIGITAL_FUNCTIONAL_M + Digital functional + mode + 1 + + + + + RESERVED + Reserved + [9:8] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO3_2 + I/O configuration for pin PIO3_2/DCD/ + CT16B0_MAT2/SCK1 + 0x09C + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO3_2. + 0x0 + + + SELECTS_FUNCTION_DCD + Selects function DCD. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_MAT2. + 0x2 + + + SELECTS_FUNCTION_SCK + Selects function SCK1. + 0x3 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_5 + I/O configuration for pin + PIO1_5/RTS/CT32B0_CAP0 + 0x0A0 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_5. + 0x0 + + + SELECTS_FUNCTION_RTS + Selects function RTS. + 0x1 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_CAP0. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_6 + I/O configuration for pin + PIO1_6/RXD/CT32B0_MAT0 + 0x0A4 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_6. + 0x0 + + + SELECTS_FUNCTION_RXD + Selects function RXD. + 0x1 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT0. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO1_7 + I/O configuration for pin + PIO1_7/TXD/CT32B0_MAT1 + 0x0A8 + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO1_7. + 0x0 + + + SELECTS_FUNCTION_TXD + Selects function TXD. + 0x1 + + + SELECTS_FUNCTION_CT3 + Selects function + CT32B0_MAT1. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_PIO3_3 + I/O configuration for pin PIO3_3/RI/ + CT16B0_CAP0 + 0x0AC + read-write + 0xD0 + 0xFFFFFFFF + + + FUNC + Selects pin function. All other values + are reserved. + [2:0] + + ENUM + + SELECTS_FUNCTION_PIO + Selects function + PIO3_3. + 0x0 + + + SELECTS_FUNCTION_RI_ + Selects function RI. + 0x1 + + + SELECTS_FUNCTION_CT1 + Selects function + CT16B0_CAP0. + 0x2 + + + + + MODE + Selects function mode (on-chip + pull-up/pull-down resistor control). + [4:3] + + ENUM + + INACTIVE_NO_PULL_DO + Inactive (no pull-down/pull-up + resistor enabled). + 0x0 + + + PULL_DOWN_RESISTOR_E + Pull-down resistor + enabled. + 0x1 + + + PULL_UP_RESISTOR_ENA + Pull-up resistor + enabled. + 0x2 + + + REPEATER_MODE_ + Repeater mode. + 0x3 + + + + + HYS + Hysteresis. + [5:5] + + ENUM + + DISABLE_ + Disable. + 0 + + + ENABLE_ + Enable. + 1 + + + + + RESERVED + Reserved + [9:6] + + + OD + Selects pseudo open-drain + mode. + [10:10] + + ENUM + + STANDARD_GPIO_OUTPUT + Standard GPIO output + 0 + + + OPEN_DRAIN_OUTPUT + Open-drain output + 1 + + + + + RESERVED + Reserved + [31:11] + + + + + IOCON_SCK0_LOC + SCK0 pin location select + register + 0x0B0 + read-write + 0x00 + 0xFFFFFFFF + + + SCKLOC + Selects pin location for SCK0 + function. + [1:0] + + ENUM + + SELECTS_SCK0_FUNCTIO_PIO0_10 + Selects SCK0 function in pin + location SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see + Table 129). + 0x0 + + + SELECTS_SCK0_FUNCTIO_PIO2_11 + Selects SCK0 function in pin + location PIO2_11/SCK0 (see Table + 131). + 0x1 + + + SELECTS_SCK0_FUNCTIO_PIO0_6 + Selects SCK0 function in pin + location PIO0_6/SCK0 (see Table + 122). + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_DSR_LOC + DSR pin location select + register + 0x0B4 + read-write + 0x00 + 0xFFFFFFFF + + + DSRLOC + Selects pin location for DSR + function. + [1:0] + + ENUM + + SELECTS_DSR_FUNCTIO_PIO2_1 + Selects DSR function in pin location + PIO2_1/DSR/SCK1 (see Table 113). + 0x0 + + + SELECTS_DSR_FUNCTION_PIO3_1 + Selects DSR function in pin location + PIO3_1/DSR (see Table 137). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_DCD_LOC + DCD pin location select + register + 0x0B8 + read-write + 0x00 + 0xFFFFFFFF + + + DCDLOC + Selects pin location for DCD + function. + [1:0] + + ENUM + + SELECTS_DCD_FUNCTIO_PIO2_2 + Selects DCD function in pin location + PIO2_2/DCD/MISO1 (see Table 126). + 0x0 + + + SELECTS_DCD_FUNCTION_PIO3_2 + Selects DCD function in pin location + PIO3_2/DCD (see Table 142). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_RI_LOC + RI pin location select + register + 0x0BC + read-write + 0x00 + 0xFFFFFFFF + + + RILOC + Selects pin location for RI + function. + [1:0] + + ENUM + + SELECTS_RI_FUNCTION_PIO2_3 + Selects RI function in pin location + PIO2_3/RI/MOSI1 (see Table 138). + 0x0 + + + SELECTS_RI_FUNCTION_PIO3_3 + Selects RI function in pin location + PIO3_3/RI (see Table 146). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_SSEL1_LOC + SSEL1 pin location select + register + 0x018 + read-write + 0x0 + 0xFFFFFFFF + + + SSEL1LOC + Selects pin location for SSEL1 + function. + [1:0] + + ENUM + + SELECTS_SSEL1_FUNCTI_PIO2_2 + Selects SSEL1 function in pin + location PIO2_2/DCD/MISO1 (see Table + 126). + 0x0 + + + SELECTS_SSEL1_FUNCTI_PIO2_4 + Selects SSEL1 function in pin + location PIO2_4/CT16B1_MAT1/SSEL1 (see Table + 119). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_CT16B0_CAP0_LOC + CT16B0_CAP0 pin location select + register + 0x0C0 + read-write + 0x00 + 0xFFFFFFFF + + + CT16B0_CAP0LOC + Selects pin location for CT16B0_CAP0 + function. + [1:0] + + ENUM + + SELECTS_CT16B0_CAP0_PIO0_2 + Selects CT16B0_CAP0 function in pin + location PIO0_2/SSEL0/CT16B0_CAP0 (see Table + 110). + 0x0 + + + SELECTS_CT16B0_CAP0_PIO3_3 + Selects CT16B0_CAP0 function in pin + location PIO3_3/RI/CT16B0 (see Table + 146). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_SCK1_LOC + SCK1 pin location select + register + 0x0C4 + read-write + 0x00 + 0xFFFFFFFF + + + SCK1LOC + Selects pin location for SCK1 + function. + [1:0] + + ENUM + + SELECTS_SCK1_FUNCTIO_PIO2_1 + Selects SCK1 function in pin + location PIO2_1/DSR/SCK1 (see Table + 113). + 0x0 + + + SELECTS_SCK1_FUNCTIO_PIO3_2 + Selects SCK1 function in pin + location PIO3_2/DCD/CT16B0_MAT2/SCK1 (see Table + 142). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_MISO1_LOC + MISO1 pin location select + register + 0x0C8 + read-write + 0x00 + 0xFFFFFFFF + + + MISO1LOC + Selects pin location for the MISO1 + function. + [1:0] + + ENUM + + SELECTS_MISO1_FUNCTI_PIO2_2 + Selects MISO1 function in pin + location PIO2_2/DCD/MISO1 (see Table + 126). + 0x0 + + + SELECTS_MISO1_FUNCTI_PIO1_10 + Selects MISO1 function in pin + location PIO1_10/AD6/CT16B1_MAT1/MISO1 (see Table + 130). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_MOSI1_LOC + MOSI1 pin location select + register + 0x0CC + read-write + 0x00 + 0xFFFFFFFF + + + MOSI1LOC + Selects pin location for the MOSI1 + function. + [1:0] + + ENUM + + SELECTS_MOSI1_FUNCTI_PIO2_3 + Selects MOSI1 function in pin + location PIO2_3/RI/MOSI1 (see Table + 138). + 0x0 + + + SELECTS_MOSI1_FUNCTI_PIO1_9 + Selects MOSI1 function in pin + location PIO1_9/CT16B1_MAT0/MOSI1 (see Table + 117). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_CT32B0_CAP0_LOC + CT32B0_CAP0 pin location select + register + 0x0D0 + read-write + 0x00 + 0xFFFFFFFF + + + CT32B0_CAP0LOC + Selects pin location for the CT32B0_CAP0 + function. + [1:0] + + ENUM + + SELECTS_CT32B0_CAP0_PIO1_5 + Selects CT32B0_CAP0 function in pin + location PIO1_5/RTS/CT32B0_CAP0 (see Table + 143). + 0x0 + + + SELECTS_CT32B0_CAP0_PIO2_9 + Selects CT32B0_CAP0 function in pin + location PIO2_9/CT32B0_CAP0 (Table + 124). + 0x1 + + + RESERVED_ + Reserved. + 0x2 + + + RESERVED_ + Reserved. + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + IOCON_RXD_LOC + RXD pin location select + register + 0x0D4 + read-write + 0x00 + 0xFFFFFFFF + + + RXDLOC + Selects pin location for the RXD + function. + [1:0] + + ENUM + + SELECTS_RXD_FUNCTION_PIO1_6 + Selects RXD function in pin location + PIO1_6/RXD/CT32B0_MAT0 (see Table + 144). + 0x0 + + + SELECTS_RXD_FUNCTION_PIO2_7 + Selects RXD function in pin location + PIO2_7/CT32B0_MAT2/RXD (see Table + 111). + 0x1 + + + SELECTS_RXD_FUNCTION_PIO3_1 + Selects RXD function in pin location + PIO3_1/DSR/CT16B0_MAT1/RXD (see Table + 137). + 0x2 + + + SELECTS_RXD_FUNCTION_PIO3_4 + Selects RXD function in pin location + PIO3_4/CT16B0_CAP1/RXD (see Table + 118). + 0x3 + + + + + RESERVED + Reserved. + [31:2] + + + + + + + SYSCON + Product name title=UM10398 Chapter + title=LPC111x/LPC11Cxx System configuration (SYSCON) + Modification date=2/22/2012 Major revision=8 Minor + revision=not available + SYSCON + 0x40048000 + + 0x0 + 0xFFF + registers + + + BOD + 26 + + + PIO0_0 + 0 + + + PIO0_1 + 1 + + + PIO0_2 + 2 + + + PIO0_3 + 3 + + + PIO0_4 + 4 + + + PIO0_5 + 5 + + + PIO0_6 + 6 + + + PIO0_7 + 7 + + + PIO0_8 + 8 + + + PIO0_9 + 9 + + + PIO0_10 + 10 + + + PIO0_11 + 11 + + + PIO1_0 + 12 + + + + SYSMEMREMAP + System memory remap + 0x000 + read-write + 0x002 + 0xFFFFFFFF + + + MAP + System memory remap + [1:0] + + ENUM + + BOOT_LOADER_MODE_IN + Boot Loader Mode. Interrupt vectors + are re-mapped to Boot ROM. + 0x0 + + + USER_RAM_MODE_INTER + User RAM Mode. Interrupt vectors are + re-mapped to Static RAM. + 0x1 + + + USER_FLASH_MODE_INT + User Flash Mode. Interrupt vectors + are not re-mapped and reside in + Flash. + 0x2 + + + + + RESERVED + Reserved + [31:2] + + + + + PRESETCTRL + Peripheral reset control + 0x004 + read-write + 0x000 + 0xFFFFFFFF + + + SSP0_RST_N + SPI0 reset control + [0:0] + + ENUM + + SPIO0RESET + Resets the SPI0 + peripheral. + 0 + + + SPIO0NORESET + SPI0 reset + de-asserted. + 1 + + + + + I2C_RST_N + I2C reset control + [1:1] + + ENUM + + I2CRESET + Resets the I2C + peripheral. + 0 + + + I2CNORESET + I2C reset de-asserted. + 1 + + + + + SSP1_RST_N + SPI1 reset control + [2:2] + + ENUM + + SPI1RESET + Resets the SPI1 + peripheral. + 0 + + + SPI2NORESET + SPI1 reset + de-asserted. + 1 + + + + + CAN_RST_N + C_CAN reset control. See Section 3.1 for + part specific details. + [3:3] + + ENUM + + CANRESET + Resets the C_CAN + peripheral. + 0 + + + CANNORESET + C_CAN reset + de-asserted. + 1 + + + + + RESERVED + Reserved + [31:4] + + + + + SYSPLLCTRL + System PLL control + 0x008 + read-write + 0x000 + 0xFFFFFFFF + + + MSEL + Feedback divider value. The division + value M is the programmed MSEL value + 1. 00000: + Division ratio M = 1 to 11111: Division ratio M = + 32. + [4:0] + + + PSEL + Post divider ratio P. The division ratio + is 2 x P. + [6:5] + + ENUM + + P_EQ_1 + P = 1 + 0x0 + + + P_EQ_2 + P = 2 + 0x1 + + + P_EQ_4 + P = 4 + 0x2 + + + P_EQ_8 + P = 8 + 0x3 + + + + + RESERVED + Reserved. Do not write ones to reserved + bits. + [31:7] + + + + + SYSPLLSTAT + System PLL status + 0x00C + read-only + 0x000 + 0xFFFFFFFF + + + LOCK + PLL lock status + [0:0] + + ENUM + + PLL_NOT_LOCKED + PLL not locked + 0 + + + PLL_LOCKED + PLL locked + 1 + + + + + RESERVED + Reserved + [31:1] + + + + + SYSOSCCTRL + System oscillator control + 0x020 + read-write + 0x000 + 0xFFFFFFFF + + + BYPASS + Bypass system oscillator + [0:0] + + ENUM + + NOBYPASS + Oscillator is not + bypassed. + 0 + + + BYPASS_ENABLED_PLL_ + Bypass enabled. PLL input + (sys_osc_clk) is fed directly from the XTALIN and + XTALOUT pins. + 1 + + + + + FREQRANGE + Determines frequency range for Low-power + oscillator. + [1:1] + + ENUM + + LOW + 1 - 20 MHz frequency + range. + 0 + + + HIGH + 15 - 25 MHz frequency + range + 1 + + + + + RESERVED + Reserved + [31:2] + + + + + WDTOSCCTRL + Watchdog oscillator control + 0x024 + read-write + 0x000 + 0xFFFFFFFF + + + DIVSEL + Select divider for Fclkana. wdt_osc_clk + = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) + = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + + DIVSEL) = 64 + [4:0] + + + FREQSEL + Select watchdog oscillator analog output + frequency (Fclkana). + [8:5] + + ENUM + + 0_5_MHZ + 0.5 MHz + 0x1 + + + 0_8_MHZ + 0.8 MHz + 0x2 + + + 1_1_MHZ + 1.1 MHz + 0x3 + + + 1_4_MHZ + 1.4 MHz + 0x4 + + + 1_6_MHZ + 1.6 MHz + 0x5 + + + 1_8_MHZ + 1.8 MHz + 0x6 + + + 2_0_MHZ + 2.0 MHz + 0x7 + + + 2_2_MHZ + 2.2 MHz + 0x8 + + + 2_4_MHZ + 2.4 MHz + 0x9 + + + 2_6_MHZ + 2.6 MHz + 0xA + + + 2_7_MHZ + 2.7 MHz + 0xB + + + 2_9_MHZ + 2.9 MHz + 0xC + + + 3_1_MHZ + 3.1 MHz + 0xD + + + 3_2_MHZ + 3.2 MHz + 0xE + + + 3_4_MHZ + 3.4 MHz + 0xF + + + + + RESERVED + Reserved + [31:9] + + + + + IRCCTRL + IRC control + 0x028 + read-write + 0x080 + 0xFFFFFFFF + + + TRIM + Trim value + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + SYSRSTSTAT + System reset status register + 0x030 + read-only + 0x000 + 0xFFFFFFFF + + + POR + POR reset status + [0:0] + + ENUM + + NO_POR_DETECTED_ + No POR detected. + 0 + + + POR_DETECTED_WRITIN + POR detected. Writing a one clears + this reset. + 1 + + + + + EXTRST + Status of the external RESET + pin. + [1:1] + + ENUM + + NO_RESET_EVENT_DETEC + No RESET event + detected. + 0 + + + RESET_DETECTED_WRIT + RESET detected. Writing a one clears + this reset. + 1 + + + + + WDT + Status of the Watchdog + reset + [2:2] + + ENUM + + NO_WDT_RESET_DETECTE + No WDT reset detected. + 0 + + + WDT_RESET_DETECTED_ + WDT reset detected. Writing a one + clears this reset. + 1 + + + + + BOD + Status of the Brown-out detect + reset + [3:3] + + ENUM + + NO_BOD_RESET_DETECTE + No BOD reset detected. + 0 + + + BOD_RESET_DETECTED_ + BOD reset detected. Writing a one + clears this reset. + 1 + + + + + SYSRST + Status of the software system + reset + [4:4] + + ENUM + + NO_SYSTEM_RESET_DETE + No System reset + detected. + 0 + + + SYSTEM_RESET_DETECTE + System reset detected. Writing a one + clears this reset. + 1 + + + + + RESERVED + Reserved + [31:5] + + + + + SYSPLLCLKSEL + System PLL clock source select + 0x040 + read-write + 0x000 + 0xFFFFFFFF + + + SEL + System PLL clock source + [1:0] + + ENUM + + IRC_OSCILLATOR + IRC oscillator + 0x0 + + + SYSTEM_OSCILLATOR + System oscillator + 0x1 + + + RESERVED + Reserved + 0x2 + + + RESERVED + Reserved + 0x3 + + + + + RESERVED + Reserved + [31:2] + + + + + SYSPLLCLKUEN + System PLL clock source update + enable + 0x044 + read-write + 0x000 + 0xFFFFFFFF + + + ENA + Enable system PLL clock source + update + [0:0] + + ENUM + + NO_CHANGE + No change + 0 + + + UPDATE_CLOCK_SOURCE + Update clock source + 1 + + + + + RESERVED + Reserved + [31:1] + + + + + MAINCLKSEL + Main clock source select + 0x070 + read-write + 0x000 + 0xFFFFFFFF + + + SEL + Clock source for main + clock + [1:0] + + ENUM + + IRC_OSCILLATOR + IRC oscillator + 0x0 + + + INPUT_CLOCK_TO_SYSTE + Input clock to system + PLL + 0x1 + + + WDT_OSCILLATOR + WDT oscillator + 0x2 + + + SYSTEM_PLL_CLOCK_OUT + System PLL clock out + 0x3 + + + + + RESERVED + Reserved + [31:2] + + + + + MAINCLKUEN + Main clock source update + enable + 0x074 + read-write + 0x000 + 0xFFFFFFFF + + + ENA + Enable main clock source + update + [0:0] + + ENUM + + NO_CHANGE + No change + 0 + + + UPDATE_CLOCK_SOURCE + Update clock source + 1 + + + + + RESERVED + Reserved + [31:1] + + + + + SYSAHBCLKDIV + System AHB clock divider + 0x078 + read-write + 0x001 + 0xFFFFFFFF + + + DIV + System AHB clock divider values 0: + System clock disabled. 1: Divide by 1. to 255: Divide + by 255. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + SYSAHBCLKCTRL + System AHB clock control + 0x080 + read-write + 0x85F + 0xFFFFFFFF + + + SYS + Enables clock for AHB to APB bridge, to + the AHB matrix, to the Cortex-M0 FCLK and HCLK, to + the SysCon, and to the PMU. This bit is read + only. + [0:0] + + ENUM + + RESERVED + Reserved + 0 + + + ENABLE + Enable + 1 + + + + + ROM + Enables clock for ROM. + [1:1] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + RAM + Enables clock for RAM. + [2:2] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + FLASHREG + Enables clock for flash register + interface. + [3:3] + + ENUM + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 1 + + + + + FLASHARRAY + Enables clock for flash array + access. + [4:4] + + ENUM + + DISABLED + Disabled + 0 + + + ENABLED + Enabled + 1 + + + + + I2C + Enables clock for I2C. + [5:5] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + GPIO + Enables clock for GPIO. + [6:6] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CT16B0 + Enables clock for 16-bit counter/timer + 0. + [7:7] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CT16B1 + Enables clock for 16-bit counter/timer + 1. + [8:8] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CT32B0 + Enables clock for 32-bit counter/timer + 0. + [9:9] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CT32B1 + Enables clock for 32-bit counter/timer + 1. + [10:10] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + SSP0 + Enables clock for SPI0. + [11:11] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + UART + Enables clock for UART. See Section 3.1 + for part specific details. + [12:12] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + ADC + Enables clock for ADC. + [13:13] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + RESERVED + Reserved + [14:14] + + + WDT + Enables clock for WDT. + [15:15] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + IOCON + Enables clock for I/O configuration + block. + [16:16] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + CAN + Enables clock for C_CAN. See Section 3.1 + for part specific details. + [17:17] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + SSP1 + Enables clock for SPI1. + [18:18] + + ENUM + + DISABLE + Disable + 0 + + + ENABLE + Enable + 1 + + + + + RESERVED + Reserved + [31:19] + + + + + SSP0CLKDIV + SPI0 clock divider + 0x094 + read-write + 0x000 + 0xFFFFFFFF + + + DIV + SPI0_PCLK clock divider values 0: + Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by + 255. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + UARTCLKDIV + UART clock divder + 0x098 + read-write + 0x000 + 0xFFFFFFFF + + + DIV + UART_PCLK clock divider values 0: + Disable UART_PCLK. 1: Divide by 1. to 255: Divide by + 255. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + SSP1CLKDIV + SPI1 clock divder + 0x09C + read-write + 0x000 + 0xFFFFFFFF + + + DIV + SPI1_PCLK clock divider values 0: + Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by + 255. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + WDTCLKSEL + WDT clock source select + 0x0D0 + read-write + 0x000 + 0xFFFFFFFF + + + SEL + WDT clock source + [1:0] + + ENUM + + IRC_OSCILLATOR + IRC oscillator + 0x0 + + + MAIN_CLOCK + Main clock + 0x1 + + + WATCHDOG_OSCILLATOR + Watchdog oscillator + 0x2 + + + RESERVED + Reserved + 0x3 + + + + + RESERVED + Reserved + [31:2] + + + + + WDTCLKUEN + WDT clock source update enable + 0x0D4 + read-write + 0x000 + 0xFFFFFFFF + + + ENA + Enable WDT clock source + update + [0:0] + + ENUM + + NO_CHANGE + No change + 0 + + + UPDATE_CLOCK_SOURCE + Update clock source + 1 + + + + + RESERVED + Reserved + [31:1] + + + + + WDTCLKDIV + WDT clock divider + 0x0D8 + read-write + 0x000 + 0xFFFFFFFF + + + DIV + WDT clock divider values 0: Disable + WDCLK. 1: Divide by 1. to 255: Divide by + 255. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + CLKOUTCLKSEL + CLKOUT clock source select + 0x0E0 + read-write + 0x000 + 0xFFFFFFFF + + + SEL + CLKOUT clock source + [1:0] + + ENUM + + IRC_OSCILLATOR + IRC oscillator + 0x0 + + + SYSTEM_OSCILLATOR + System oscillator + 0x1 + + + WATCHDOG_OSCILLATOR + Watchdog oscillator + 0x2 + + + MAIN_CLOCK + Main clock + 0x3 + + + + + RESERVED + Reserved + [31:2] + + + + + CLKOUTUEN + CLKOUT clock source update + enable + 0x0E4 + read-write + 0x000 + 0xFFFFFFFF + + + ENA + Enable CLKOUT clock source + update + [0:0] + + ENUM + + NO_CHANGE + No change + 0 + + + UPDATE_CLOCK_SOURCE + Update clock source + 1 + + + + + RESERVED + Reserved + [31:1] + + + + + CLKOUTCLKDIV + CLKOUT clock divider + 0x0E8 + read-write + 0x000 + 0xFFFFFFFF + + + DIV + Clock output divider values 0: Disable + CLKOUT. 1: Divide by 1. to 255: Divide by + 255. + [7:0] + + + RESERVED + Reserved + [31:8] + + + + + PIOPORCAP0 + POR captured PIO status 0 + 0x100 + read-only + 0 + 0x00000000 + + + CAPPIO0_n + Raw reset status input PIO0_n: PIO0_11 + to PIO0_0 + [11:0] + + + CAPPIO1_n + Raw reset status input PIO1_n: PIO1_11 + to PIO1_0 + [23:12] + + + CAPPIO2_n + Raw reset status input PIO2_n: PIO2_7 to + PIO2_0 + [31:24] + + + + + PIOPORCAP1 + POR captured PIO status 1 + 0x104 + read-only + 0 + 0x00000000 + + + CAPPIO2_8 + Raw reset status input + PIO2_8 + [0:0] + + + CAPPIO2_9 + Raw reset status input + PIO2_9 + [1:1] + + + CAPPIO2_10 + Raw reset status input + PIO2_10 + [2:2] + + + CAPPIO2_11 + Raw reset status input + PIO2_11 + [3:3] + + + CAPPIO3_0 + Raw reset status input + PIO3_0 + [4:4] + + + CAPPIO3_1 + Raw reset status input + PIO3_1 + [5:5] + + + CAPPIO3_2 + Raw reset status input + PIO3_2 + [6:6] + + + CAPPIO3_3 + Raw reset status input + PIO3_3 + [7:7] + + + CAPPIO3_4 + Raw reset status input + PIO3_4 + [8:8] + + + CAPPIO3_5 + Raw reset status input + PIO3_5 + [9:9] + + + RESERVED + Reserved + [31:10] + + + + + BODCTRL + BOD control + 0x150 + read-write + 0x000 + 0xFFFFFFFF + + + BODRSTLEV + BOD reset level + [1:0] + + ENUM + + LEVEL_0_THE_RESET_A + Level 0: The reset assertion + threshold voltage is 1.46 V; the reset + de-assertion threshold voltage is 1.63 + V. + 0x0 + + + LEVEL_1_THE_RESET_A + Level 1: The reset assertion + threshold voltage is 2.06 V; the reset + de-assertion threshold voltage is 2.15 + V. + 0x1 + + + LEVEL_2_THE_RESET_A + Level 2: The reset assertion + threshold voltage is 2.35 V; the reset + de-assertion threshold voltage is 2.43 + V. + 0x2 + + + LEVEL_3_THE_RESET_A + Level 3: The reset assertion + threshold voltage is 2.63 V; the reset + de-assertion threshold voltage is 2.71 + V. + 0x3 + + + + + BODINTVAL + BOD interrupt level + [3:2] + + ENUM + + LEVEL_0_THE_INTERRU + Level 0: The interrupt assertion + threshold voltage is 1.65 V; the interrupt + de-assertion threshold voltage is 1.80 + V. + 0x0 + + + LEVEL_1THE_INTERRUP + Level 1:The interrupt assertion + threshold voltage is 2.22 V; the interrupt + de-assertion threshold voltage is 2.35 + V. + 0x1 + + + LEVEL_2_THE_INTERRU + Level 2: The interrupt assertion + threshold voltage is 2.52 V; the interrupt + de-assertion threshold voltage is 2.66 + V. + 0x2 + + + LEVEL_3_THE_INTERRU + Level 3: The interrupt assertion + threshold voltage is 2.80 V; the interrupt + de-assertion threshold voltage is 2.90 + V. + 0x3 + + + + + BODRSTENA + BOD reset enable + [4:4] + + ENUM + + DISABLE_RESET_FUNCTI + Disable reset + function. + 0 + + + ENABLE_RESET_FUNCTIO + Enable reset function. + 1 + + + + + RESERVED + Reserved + [31:5] + + + + + SYSTCKCAL + System tick counter + calibration + 0x154 + read-write + 0x004 + 0xFFFFFFFF + + + CAL + System tick timer calibration + value + [25:0] + + + RESERVED + Reserved + [31:26] + + + + + NMISRC + NMI source selection + 0x174 + read-write + 0x000 + 0xFFFFFFFF + + + IRQNO + The IRQ number of the interrupt that + acts as the Non-Maskable Interrupt (NMI) if bit 31 in + this register is 1. See Table 54 for the list of + interrupt sources and their IRQ + numbers. + [4:0] + + + RESERVED + Reserved + [30:5] + + + NMIEN + Write a 1 to this bit to enable the + Non-Maskable Interrupt (NMI) source selected by bits + 4:0. + [31:31] + + + + + STARTAPRP0 + Start logic edge control register + 0 + 0x200 + read-write + 0 + 0x00000000 + + + APRPIO0_0 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [0:0] + + + APRPIO0_1 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [1:1] + + + APRPIO0_2 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [2:2] + + + APRPIO0_3 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [3:3] + + + APRPIO0_4 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [4:4] + + + APRPIO0_5 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [5:5] + + + APRPIO0_6 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [6:6] + + + APRPIO0_7 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [7:7] + + + APRPIO0_8 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [8:8] + + + APRPIO0_9 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [9:9] + + + APRPIO0_10 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [10:10] + + + APRPIO0_11 + Edge select for start logic input + PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising + edge + [11:11] + + + APRPIO1_0 + Edge select for start logic input PIO1_0 + 0 = Falling edge 1 = Rising edge + [12:12] + + + RESERVED + Reserved. Do not write a 1 to reserved + bits in this register. + [31:13] + + + + + STARTERP0 + Start logic signal enable register + 0 + 0x204 + read-write + 0 + 0x00000000 + + + ERPIO0_0 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [0:0] + + + ERPIO0_1 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [1:1] + + + ERPIO0_2 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [2:2] + + + ERPIO0_3 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [3:3] + + + ERPIO0_4 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [4:4] + + + ERPIO0_5 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [5:5] + + + ERPIO0_6 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [6:6] + + + ERPIO0_7 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [7:7] + + + ERPIO0_8 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [8:8] + + + ERPIO0_9 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [9:9] + + + ERPIO0_10 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [10:10] + + + ERPIO0_11 + Enable start signal for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = + Enabled + [11:11] + + + ERPIO1_0 + Enable start signal for start logic + input PIO1_0 0 = Disabled 1 = Enabled + [12:12] + + + RESERVED + Reserved. Do not write a 1 to reserved + bits in this register. + [31:13] + + + + + STARTRSRP0CLR + Start logic reset register 0 + 0x208 + write-only + 0 + 0x00000000 + + + RSRPIO0_0 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [0:0] + + + RSRPIO0_1 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [1:1] + + + RSRPIO0_2 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [2:2] + + + RSRPIO0_3 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [3:3] + + + RSRPIO0_4 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [4:4] + + + RSRPIO0_5 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [5:5] + + + RSRPIO0_6 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [6:6] + + + RSRPIO0_7 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [7:7] + + + RSRPIO0_8 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [8:8] + + + RSRPIO0_9 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [9:9] + + + RSRPIO0_10 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [10:10] + + + RSRPIO0_11 + Start signal reset for start logic input + PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing + 1 resets the start signal. + [11:11] + + + RSRPIO1_0 + Start signal reset for start logic input + PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start + signal. + [12:12] + + + RESERVED + Reserved. Do not write a 1 to reserved + bits in this register. + [31:13] + + + + + STARTSRP0 + Start logic status register 0 + 0x20C + read-only + 0 + 0x00000000 + + + SRPIO0_0 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [0:0] + + + SRPIO0_1 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [1:1] + + + SRPIO0_2 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [2:2] + + + SRPIO0_3 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [3:3] + + + SRPIO0_4 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [4:4] + + + SRPIO0_5 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [5:5] + + + SRPIO0_6 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [6:6] + + + SRPIO0_7 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [7:7] + + + SRPIO0_8 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [8:8] + + + SRPIO0_9 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [9:9] + + + SRPIO0_10 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [10:10] + + + SRPIO0_11 + Start signal status for start logic + input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal + received. 1 = Start signal pending. + [11:11] + + + SRPIO1_0 + Start signal status for start logic + input PIO1_0 0 = No start signal received. 1 = Start + signal pending. + [12:12] + + + RESERVED + Reserved + [31:13] + + + + + PDSLEEPCFG + Power-down states in Deep-sleep + mode + 0x230 + read-write + 0x00000000 + 0xFFFFFFFF + + + NOTUSED0 + Reserved. Always write these bits as + 111. + [2:0] + + + BOD_PD + BOD power-down control in Deep-sleep + mode, see Table 40. + [3:3] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + NOTUSED1 + Reserved. Always write these bits as + 11. + [5:4] + + + WDTOSC_PD + Watchdog oscillator power control in + Deep-sleep mode, see Table 40. + [6:6] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + NOTUSED2 + Reserved. Always write this bit as + 1. + [7:7] + + + NOTUSED3 + Reserved. Always write these bits as + 000. + [10:8] + + + NOTUSED4 + Reserved. Always write these bits as + 11. + [12:11] + + + RESERVED + Reserved + [31:13] + + + + + PDAWAKECFG + Power-down states after wake-up from + Deep-sleep mode + 0x234 + read-write + 0x0000EDF0 + 0xFFFFFFFF + + + IRCOUT_PD + IRC oscillator output wake-up + configuration + [0:0] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + IRC_PD + IRC oscillator power-down wake-up + configuration + [1:1] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + FLASH_PD + Flash wake-up + configuration + [2:2] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + BOD_PD + BOD wake-up configuration + [3:3] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + ADC_PD + ADC wake-up configuration + [4:4] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + SYSOSC_PD + System oscillator wake-up + configuration + [5:5] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + WDTOSC_PD + Watchdog oscillator wake-up + configuration + [6:6] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + SYSPLL_PD + System PLL wake-up + configuration + [7:7] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + NOTUSED0 + Reserved. Always write this bit as + 1. + [8:8] + + + NOTUSED1 + Reserved. Always write this bit as + 0. + [9:9] + + + NOTUSED2 + Reserved. Always write this bit as + 1. + [10:10] + + + NOTUSED3 + Reserved. Always write this bit as + 1. + [11:11] + + + NOTUSED4 + Reserved. Always write this bit as + 0. + [12:12] + + + NOTUSED5 + Reserved. Always write these bits as + 111. + [15:13] + + + RESERVED + Reserved + [31:16] + + + + + PDRUNCFG + Power-down configuration + register + 0x238 + read-write + 0x0000EDF0 + 0xFFFFFFFF + + + IRCOUT_PD + IRC oscillator output + power-down + [0:0] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + IRC_PD + IRC oscillator power-down + [1:1] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + FLASH_PD + Flash power-down + [2:2] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + BOD_PD + BOD power-down + [3:3] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + ADC_PD + ADC power-down + [4:4] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + SYSOSC_PD + System oscillator + power-down + [5:5] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + WDTOSC_PD + Watchdog oscillator + power-down + [6:6] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + SYSPLL_PD + System PLL power-down + [7:7] + + ENUM + + POWERED + Powered + 0 + + + POWERED_DOWN + Powered down + 1 + + + + + NOTUSED0 + Reserved. Always write this bit as + 1. + [8:8] + + + NOTUSED1 + Reserved. Always write this bit as + 0. + [9:9] + + + NOTUSED2 + Reserved. Always write this bit as + 1. + [10:10] + + + NOTUSED3 + Reserved. Always write this bit as + 1. + [11:11] + + + NOTUSED4 + Reserved. Always write this bit as + 0. + [12:12] + + + NOTUSED5 + Reserved. Always write these bits as + 111. + [15:13] + + + RESERVED + Reserved + [31:16] + + + + + DEVICE_ID + Device ID register 0 for parts LPC1100, + LPC1100C, LPC1100L. + 0x3F4 + read-only + 0 + 0x00000000 + + + DEVICEID + Part ID numbers for LPC111x/LPC11Cxx + parts 0x041E 502B; 0x2516 D02B = LPC1111FHN33/101 + 0x2516 D02B = LPC1111FHN33/102 0x0416 502B; 0x2516 + 902B = LPC1111FHN33/201 0x2516 902B = + LPC1111FHN33/202 0x042D 502B; 0x2524 D02B = + LPC1112FHN33/101 0x2524 D02B = LPC1112FHN33/102 + 0x0425 502B; 0x2524 902B = LPC1112FHN33/201 0x2524 + 902B = LPC1112FHN33/202 0x2524 902B = + LPC1112FHI33/202 0x0434 502B; 0x2532 902B = + LPC1113FHN33/201 0x2532 902B = LPC1113FHN33/202 + 0x0434 102B; 0x2532 102B = LPC1113FHN33/301 0x2532 + 102B = LPC1113FHN33/302 0x0434 102B; 0x2532 102B = + LPC1113FBD48/301 0x2532 102B = LPC1113FBD48/302 + 0x0444 502B; 0x2540 902B = LPC1114FHN33/201 0x2540 + 902B = LPC1114FHN33/202 0x0444 102B; 0x2540 102B = + LPC1114FHN33/301 0x2540 102B = LPC1114FHN33/302 + 0x2540 102B = LPC1114FHI33/302 0x0444 102B; 0x2540 + 102B = LPC1114FBD48/301 0x2540 102B = + LPC1114FBD48/302 0x2540 102B = LPC11D14FBD100/302 + 0x1421 102B = LPC11C12/FBD48/301 0x1440 102B = + LPC11C14/FBD48/301 0x1431 102B = LPC11C22/FBD48/301 + 0X1430 102B = LPC11C24/FBD48/301 + [31:0] + + + + + + + C_CAN + Product name title=UM10398 Chapter + title=LPC111x/LPC11Cxx C_CAN controller Modification + date=9/19/2011 Major revision=7 Minor revision=not + available + C_CAN + 0x40050000 + + 0x0 + 0xFFF + registers + + + C_CAN + 13 + + + + CANCNTL + CAN control + 0x000 + read-write + 0x0001 + 0xFFFFFFFF + + + INIT + Initialization + [0:0] + + ENUM + + NORMAL_OPERATION_ + Normal operation. + 0 + + + INITIALIZATION + Initialization is started. On reset, + software needs to initialize the CAN + controller. + 1 + + + + + IE + Module interrupt enable + [1:1] + + ENUM + + DISABLE_CAN_INTERRUP + Disable CAN interrupts. The + interrupt line is always HIGH. + 0 + + + ENABLE_CAN_INTERRUPT + Enable CAN interrupts. The interrupt + line is set to LOW and remains LOW until all + pending interrupts are cleared. + 1 + + + + + SIE + Status change interrupt + enable + [2:2] + + ENUM + + DISABLE_STATUS_CHANG + Disable status change interrupts. No + status change interrupt will be + generated. + 0 + + + ENABLE_STATUS_CHANGE + Enable status change interrupts. A + status change interrupt will be generated when a + message transfer is successfully completed or a + CAN bus error is detected. + 1 + + + + + EIE + Error interrupt enable + [3:3] + + ENUM + + DISABLE_ERROR_INTERR + Disable error interrupt. No error + status interrupt will be generated. + 0 + + + ENABLE_ERROR_INTERRU + Enable error interrupt. A change in + the bits BOFF or EWARN in the CANSTAT registers + will generate an interrupt. + 1 + + + + + RESERVED + reserved + [4:4] + + + DAR + Disable automatic + retransmission + [5:5] + + ENUM + + ENABLED + Automatic retransmission of + disturbed messages enabled. + 0 + + + DISABLED + Automatic retransmission + disabled. + 1 + + + + + CCE + Configuration change + enable + [6:6] + + ENUM + + NOACCESS + The CPU has no write access to the + bit timing register. + 0 + + + ACCESS + The CPU has write access to the + CANBT register while the INIT bit is + one. + 1 + + + + + TEST + Test mode enable + [7:7] + + ENUM + + NORMAL_OPERATION_ + Normal operation. + 0 + + + TEST_MODE_ + Test mode. + 1 + + + + + RESERVED + reserved + [31:8] + + + + + CANSTAT + Status register + 0x004 + read-write + 0x0000 + 0xFFFFFFFF + + + LEC + Last error code Type of the last error + to occur on the CAN bus.The LEC field holds a code + which indicates the type of the last error to occur + on the CAN bus. This field will be cleared to 0 when + a message has been transferred (reception or + transmission) without error. The unused code 111 may + be written by the CPU to check for + updates. + [2:0] + + ENUM + + NO_ERROR_ + No error. + 0x0 + + + STUFF_ERROR + Stuff error: More than 5 equal bits + in a sequence have occurred in a part of a + received message where this is not + allowed. + 0x1 + + + FORM_ERROR + Form error: A fixed format part of a + received frame has the wrong + format. + 0x2 + + + ACKERROR + AckError: The message this CAN core + transmitted was not acknowledged. + 0x3 + + + BIT1ERROR + Bit1Error: During the transmission + of a message (with the exception of the + arbitration field), the device wanted to send a + HIGH/recessive level (bit of logical value 1), + but the monitored bus value was + LOW/dominant. + 0x4 + + + BIT0ERROR + Bit0Error: During the transmission + of a message (or acknowledge bit, or active error + flag, or overload flag), the device wanted to + send a LOW/dominant level (data or identifier bit + logical value 0), but the monitored Bus value was + HIGH/recessive. During busoff recovery this + status is set each time a sequence of 11 + HIGH/recessive bits has been monitored. This + enables the CPU to monitor the proceeding of the + busoff recovery sequence (indicating the bus is + not stuck at LOW/dominant or continuously + disturbed). + 0x5 + + + CRCERROR + CRCError: The CRC checksum was + incorrect in the message received. + 0x6 + + + UNUSED + Unused: No CAN bus event was + detected (written by the CPU). + 0x7 + + + + + TXOK + Transmitted a message successfully This + bit is reset by the CPU. It is never reset by the CAN + controller. + [3:3] + + ENUM + + NOTRANSMIT + Since this bit was reset by the CPU, + no message has been successfully + transmitted. + 0 + + + TRANSMIT + Since this bit was last reset by the + CPU, a message has been successfully transmitted + (error free and acknowledged by at least one + other node). + 1 + + + + + RXOK + Received a message successfully This bit + is reset by the CPU. It is never reset by the CAN + controller. + [4:4] + + ENUM + + NOTRANSMIT + Since this bit was last reset by the + CPU, no message has been successfully + transmitted. + 0 + + + TRANSMIT + Since this bit was last set to zero + by the CPU, a message has been successfully + received independent of the result of acceptance + filtering. + 1 + + + + + EPASS + Error passive + [5:5] + + ENUM + + ACTIVE + The CAN controller is in the error + active state. + 0 + + + PASSIVE + The CAN controller is in the error + passive state as defined in the CAN 2.0 + specification. + 1 + + + + + EWARN + Warning status + [6:6] + + ENUM + + BELOWWARNINGLIM + Both error counters are below the + error warning limit of 96. + 0 + + + WARNINGLIM + At least one of the error counters + in the EML has reached the error warning limit of + 96. + 1 + + + + + BOFF + Busoff status + [7:7] + + ENUM + + NOTBUSOFF + The CAN module is not in + busoff. + 0 + + + BUSOFF + The CAN controller is in busoff + state. + 1 + + + + + RESERVED + reserved + [31:8] + + + + + CANEC + Error counter + 0x008 + read-only + 0x0000 + 0xFFFFFFFF + + + TEC_7_0 + Transmit error counter Current value of + the transmit error counter (maximum value + 255) + [7:0] + + + REC_6_0 + Receive error counter Current value of + the receive error counter (maximum value + 127). + [14:8] + + + RP + Receive error passive + [15:15] + + ENUM + + BELOWERRORPASSIVE + The receive counter is below the + error passive level. + 0 + + + ERRORPASSIVE + The receive counter has reached the + error passive level as defined in the CAN2.0 + specification. + 1 + + + + + RESERVED + Reserved + [31:16] + + + + + CANBT + Bit timing register + 0x00C + read-write + 0x2301 + 0xFFFFFFFF + + + BRP + Baud rate prescaler The value by which + the oscillator frequency is divided for generating + the bit time quanta. The bit time is built up from a + multiple of this quanta. Valid values for the Baud + Rate Prescaler are 0 to 63.[1] + [5:0] + + + SJW + (Re)synchronization jump width Valid + programmed values are 0 to 3.[1] + [7:6] + + + TSEG1 + Time segment before the sample point + Valid values are 1 to 15.[1] + [11:8] + + + TSEG2 + Time segment after the sample point + Valid values are 0 to 7.[1] + [14:12] + + + RESERVED + Reserved + [31:15] + + + + + CANINT + Interrupt register + 0x010 + read-only + 0x0000 + 0xFFFFFFFF + + + INTID + 0x0000 = No interrupt is pending. 0x0001 + - 0x0020 = Number of message object which caused the + interrupt. 0x0021 - 0x7FFF = Unused 0x8000 = Status + interrupt 0x8001 - 0xFFFF = Unused + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANTEST + Test register + 0x014 + read-write + 0 + 0x00000000 + + + RESERVED + Reserved + [1:0] + + + BASIC + Basic mode + [2:2] + + ENUM + + BASIC_MODE_DISABLED_ + Basic mode disabled. + 0 + + + TXRX + IF1 registers used as TX buffer, IF2 + registers used as RX buffer. + 1 + + + + + SILENT + Silent mode + [3:3] + + ENUM + + NORMAL_OPERATION_ + Normal operation. + 0 + + + SILENT + The module is in silent + mode. + 1 + + + + + LBACK + Loop back mode + [4:4] + + ENUM + + DISABLED + Loop back mode is + disabled. + 0 + + + ENABLED + Loop back mode is + enabled. + 1 + + + + + TX + Control of CAN_TXD pins + [6:5] + + ENUM + + LEVEL + Level at the CAN_TXD pin is + controlled by the CAN controller. This is the + value at reset. + 0x0 + + + TXD + The sample point can be monitored at + the CAN_TXD pin. + 0x1 + + + LOW + CAN_TXD pin is driven + LOW/dominant. + 0x2 + + + HIGH + CAN_TXD pin is driven + HIGH/recessive. + 0x3 + + + + + RX + Monitors the actual value of the CAN_RXD + pin. + [7:7] + + ENUM + + RECESSIVE + The CAN bus is recessive (CAN_RXD = + 1). + 0 + + + DORMANT + The CAN bus is dominant (CAN_RXD = + 0). + 1 + + + + + RESERVED + R/W + [31:8] + + + + + CANBRPE + Baud rate prescaler extension + register + 0x018 + read-write + 0x0000 + 0xFFFFFFFF + + + BRPE + Baud rate prescaler extension By + programming BRPE the Baud Rate Prescaler can be + extended to values up to 1023. Hardware interprets + the value as the value of BRPE (MSBs) and BRP (LSBs) + plus one. Allowed values are 0 to 15. + [3:0] + + + RESERVED + Reserved + [31:4] + + + + + 2 + 0x60 + 1-2 + CANIF%s_CMDREQ + Message interface command + request + 0x020 + read-write + 0x0001 + 0xFFFFFFFF + + + MN + Message number 0x01 - 0x20 = Valid + message numbers. The message object in the message + RAM is selected for data transfer. 0x00 = Not a valid + message number. This value is interpreted as 0x20.[1] + 0x21 - 0x3F = Not a valid message number. This value + is interpreted as 0x01 - 0x1F.[1] + [5:0] + + + RESERVED + reserved + [14:6] + + + BUSY + BUSY flag + [15:15] + + ENUM + + ZERO + Set to zero by hardware when + read/write action to this Command request + register has finished. + 0 + + + ONE + Set to one by hardware when writing + to this Command request register. + 1 + + + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_CMDMSK_W + Message interface command mask - write + direction + 0x024 + read-write + 0x0000 + 0xFFFFFFFF + + + DATA_B + Access data bytes 4-7 + [0:0] + + ENUM + + DATA_BYTES_4_7_UNCHA + Data bytes 4-7 + unchanged. + 0 + + + TRANSFER_DATA_BYTES_ + Transfer data bytes 4-7 to message + object. + 1 + + + + + DATA_A + Access data bytes 0-3 + [1:1] + + ENUM + + DATA_BYTES_0_3_UNCHA + Data bytes 0-3 + unchanged. + 0 + + + TRANSFER_DATA_BYTES_ + Transfer data bytes 0-3 to message + object. + 1 + + + + + TXRQST + Access transmission request + bit + [2:2] + + ENUM + + NO_TRANSMISSION_REQU + No transmission request. TXRQSRT bit + unchanged in IF1/2_MCTRL. If a transmission is + requested by programming this bit, the TXRQST bit + in the CANIFn_MCTRL register is + ignored. + 0 + + + REQUEST_A_TRANSMISSI + Request a transmission. Set the + TXRQST bit IF1/2_MCTRL. + 1 + + + + + CLRINTPND + This bit is ignored in the write + direction. + [3:3] + + + CTRL + Access control bits + [4:4] + + ENUM + + UNCHANGED + Control bits + unchanged. + 0 + + + TRANSFER_CONTROL_BIT + Transfer control bits to message + object + 1 + + + + + ARB + Access arbitration bits + [5:5] + + ENUM + + UNCHANGED + Arbitration bits + unchanged. + 0 + + + TRANSFER_IDENTIFIER + Transfer Identifier, DIR, XTD, and + MSGVAL bits to message object. + 1 + + + + + MASK + Access mask bits + [6:6] + + ENUM + + UNCHANGED + Mask bits unchanged. + 0 + + + TRANSFER_IDENTIFIER_ + Transfer Identifier MASK + MDIR + + MXTD to message object. + 1 + + + + + WR_RD + Write transfer Transfer data from the + selected message buffer registers to the message + object addressed by the command request register + CANIFn_CMDREQ. + [7:7] + + + RESERVED + reserved + [31:8] + + + + + 2 + 0x60 + 1-2 + CANIF%s_CMDMSK_R + Message interface command mask - read + direction + CANIF%s_CMDMSK_W + 0x024 + read-write + 0x0000 + 0xFFFFFFFF + + + DATA_B + Access data bytes 4-7 + [0:0] + + ENUM + + UNCHANGED + Data bytes 4-7 + unchanged. + 0 + + + TRANSFER_DATA_BYTES_ + Transfer data bytes 4-7 to IFx + message buffer register. + 1 + + + + + DATA_A + Access data bytes 0-3 + [1:1] + + ENUM + + UNCHANGED + Data bytes 0-3 + unchanged. + 0 + + + TRANSFER_DATA_BYTES_ + Transfer data bytes 0-3 to IFx + message buffer. + 1 + + + + + NEWDAT + Access new data bit + [2:2] + + ENUM + + UNCHANGED + NEWDAT bit remains unchanged. A read + access to a message object can be combined with + the reset of the control bits INTPND and NEWDAT + in IF1/2_MCTRL. The values of these bits + transferred to the IFx Message Control Register + always reflect the status before resetting these + bits. + 0 + + + CLEAR_NEWDAT_BIT_IN_ + Clear NEWDAT bit in the message + object. + 1 + + + + + CLRINTPND + Clear interrupt pending + bit. + [3:3] + + ENUM + + UNCHANGED + INTPND bit remains + unchanged. + 0 + + + CLEAR_INTPND_BIT_IN_ + Clear INTPND bit in the message + object. + 1 + + + + + CTRL + Access control bits + [4:4] + + ENUM + + UNCHANGED + Control bits + unchanged. + 0 + + + TRANSFER_CONTROL_BIT + Transfer control bits to IFx message + buffer. + 1 + + + + + ARB + Access arbitration bits + [5:5] + + ENUM + + UNCHANGED + Arbitration bits + unchanged. + 0 + + + TRANSFER_IDENTIFIER + Transfer Identifier, DIR, XTD, and + MSGVAL bits to IFx message buffer + register. + 1 + + + + + MASK + Access mask bits + [6:6] + + ENUM + + UNCHANGED + Mask bits unchanged. + 0 + + + TRANSFER_IDENTIFIER_ + Transfer Identifier MASK + MDIR + + MXTD to IFx message buffer + register. + 1 + + + + + WR_RD + Read transfer Transfer data from the + message object addressed by the command request + register to the selected message buffer registers + CANIFn_CMDREQ. + [7:7] + + + RESERVED + reserved + [31:8] + + + + + 2 + 0x60 + 1-2 + CANIF%s_MSK1 + Message interface 1 mask 1 + 0x028 + read-write + 0xFFFF + 0xFFFFFFFF + + + MSK_15_0 + Identifier mask + [15:0] + + ENUM + + NOINHIBIT + The corresponding bit in the + identifier of the message can not inhibit the + match in the acceptance filtering. + 0 + + + ACCEPTANCEFILTERING + The corresponding identifier bit is + used for acceptance filtering. + 1 + + + + + RESERVED + reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_MSK2 + Message interface 1 mask 2 + 0x02C + read-write + 0xFFFF + 0xFFFFFFFF + + + MSK_28_16 + Identifier mask + [12:0] + + ENUM + + NOINHIBIT + The corresponding bit in the + identifier of the message can not inhibit the + match in the acceptance filtering. + 0 + + + ACCEPTANCEFILTERING + The corresponding identifier bit is + used for acceptance filtering. + 1 + + + + + RESERVED + Reserved + [13:13] + + + MDIR + Mask message direction + [14:14] + + ENUM + + NOEFFECT + The message direction bit (DIR) has + no effect on acceptance filtering. + 0 + + + ACCEPTANCEFILTERING + The message direction bit (DIR) is + used for acceptance filtering. + 1 + + + + + MXTD + Mask extend identifier + [15:15] + + ENUM + + NOEFFECT + The extended identifier bit (XTD) + has no effect on acceptance + filtering. + 0 + + + ACCEPTANCEFILTERING + The extended identifier bit (XTD) is + used for acceptance filtering. + 1 + + + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_ARB1 + Message interface 1 arbitration + 1 + 0x030 + read-write + 0x0000 + 0xFFFFFFFF + + + ID_15_0 + Message identifier 29-bit identifier + (extended frame) 11-bit identifier (standard + frame) + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_ARB2 + Message interface 1 arbitration + 2 + 0x034 + read-write + 0x0000 + 0xFFFFFFFF + + + ID_28_16 + Message identifier 29-bit identifier + (extended frame) 11-bit identifier (standard + frame) + [12:0] + + + DIR + Message direction + [13:13] + + ENUM + + RECEIVE + Direction = receive. On TXRQST, a + Remote Frame with the identifier of this Message + Object is transmitted. On reception of a Data + Frame with matching identifier, that message is + stored in this Message Object. + 0 + + + TRANSMIT + Direction = transmit. On TXRQST, the + respective Message Object is transmitted as a + Data Frame. On reception of a Remote Frame with + matching identifier, the TXRQST bit of this + Message Object is set (if RMTEN = + one). + 1 + + + + + XTD + Extend identifier + [14:14] + + ENUM + + 11_BIT_STANDARD_ + The 11-bit standard identifier will + be used for this message object. + 0 + + + 29_BIT_EXTENDED_ + The 29-bit extended identifier will + be used for this message object. + 1 + + + + + MSGVAL + Message valid The CPU must reset the + MSGVAL bit of all unused Messages Objects during the + initialization before it resets bit INIT in the CAN + Control Register. This bit must also be reset before + the identifier ID28:0, the control bits XTD, DIR, or + the Data Length Code DLC3:0 are modified, or if the + Messages Object is no longer required. + [15:15] + + ENUM + + IGNORE + The message object is ignored by the + message handler. + 0 + + + CONFIGURED + The message object is configured and + should be considered by the message + handler. + 1 + + + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_MCTRL + Message interface 1 message + control + 0x038 + read-write + 0x0000 + 0xFFFFFFFF + + + DLC_3_0 + Data length code The Data Length Code of + a Message Object must be defined the same as in all + the corresponding objects with the same identifier at + other nodes. When the Message Handler stores a data + frame, it will write the DLC to the value given by + the received message. 0000 - 1000 = Data frame has 0 + - 8 data bytes. 1001 - 1111 = Data frame has 8 data + bytes. + [3:0] + + + RESERVED + reserved + [6:4] + + + EOB + End of buffer + [7:7] + + ENUM + + FIFO + Message object belongs to a FIFO + buffer and is not the last message object of that + FIFO buffer. + 0 + + + SINGELAST + Single message object or last + message object of a FIFO buffer. + 1 + + + + + TXRQST + Transmit request + [8:8] + + ENUM + + NOWAIT + This message object is not waiting + for transmission. + 0 + + + WAIT + The transmission of this message + object is requested and is not yet + done + 1 + + + + + RMTEN + Remote enable + [9:9] + + ENUM + + NOCHANGE + At the reception of a remote frame, + TXRQST is left unchanged. + 0 + + + SET + At the reception of a remote frame, + TXRQST is set. + 1 + + + + + RXIE + Receive interrupt enable + [10:10] + + ENUM + + NOCHANGE + INTPND will be left unchanged after + successful reception of a frame. + 0 + + + SET + INTPND will be set after successful + reception of a frame. + 1 + + + + + TXIE + Transmit interrupt enable + [11:11] + + ENUM + + NOCHANGE + The INTPND bit will be left + unchanged after a successful transmission of a + frame. + 0 + + + SET + INTPND will be set after a + successful transmission of a frame. + 1 + + + + + UMASK + Use acceptance mask If UMASK is set to + 1, the message object's mask bits have to be + programmed during initialization of the message + object before MAGVAL is set to 1. + [12:12] + + ENUM + + IGNORE + Mask ignored. + 0 + + + USEMASK + Use mask (MSK[28:0], MXTD, and MDIR) + for acceptance filtering. + 1 + + + + + INTPND + Interrupt pending + [13:13] + + ENUM + + NOINTSOURCE + This message object is not the + source of an interrupt. + 0 + + + INTSOURCE + This message object is the source of + an interrupt. The Interrupt Identifier in the + Interrupt Register will point to this message + object if there is no other interrupt source with + higher priority. + 1 + + + + + MSGLST + Message lost (only valid for message + objects in the direction receive). + [14:14] + + ENUM + + NOLOST + No message lost since this bit was + reset last by the CPU. + 0 + + + NEWMESSAGE + The Message Handler stored a new + message into this object when NEWDAT was still + set, the CPU has lost a message. + 1 + + + + + NEWDAT + New data + [15:15] + + ENUM + + NONEWDATA + No new data has been written into + the data portion of this message object by the + message handler since this flag was cleared last + by the CPU. + 0 + + + NEWDATA + The message handler or the CPU has + written new data into the data portion of this + message object. + 1 + + + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_DA1 + Message interface 1 data A1 + 0x03C + read-write + 0x0000 + 0xFFFFFFFF + + + DATA0 + Data byte 0 + [7:0] + + + DATA1 + Data byte 1 + [15:8] + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_DA2 + Message interface 1 data A2 + 0x040 + read-write + 0x0000 + 0xFFFFFFFF + + + DATA2 + Data byte 2 + [7:0] + + + DATA3 + Data byte 3 + [15:8] + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_DB1 + Message interface 1 data B1 + 0x044 + read-write + 0x0000 + 0xFFFFFFFF + + + DATA4 + Data byte 4 + [7:0] + + + DATA5 + Data byte 5 + [15:8] + + + RESERVED + Reserved + [31:16] + + + + + 2 + 0x60 + 1-2 + CANIF%s_DB2 + Message interface 1 data B2 + 0x048 + read-write + 0x0000 + 0xFFFFFFFF + + + DATA6 + Data byte 6 + [7:0] + + + DATA7 + Data byte 7 + [15:8] + + + RESERVED + Reserved + [31:16] + + + + + CANTXREQ1 + Transmission request 1 + 0x100 + read-only + 0x0000 + 0xFFFFFFFF + + + TXRQST_16_1 + Transmission request bit of message + objects 16 to 1. 0 = This message object is not + waiting for transmission. 1 = The transmission of + this message object is requested and not yet + done. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANTXREQ2 + Transmission request 2 + 0x104 + read-only + 0x0000 + 0xFFFFFFFF + + + TXRQST_32_17 + Transmission request bit of message + objects 32 to 17. 0 = This message object is not + waiting for transmission. 1 = The transmission of + this message object is requested and not yet + done. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANND1 + New data 1 + 0x120 + read-only + 0x0000 + 0xFFFFFFFF + + + NEWDAT_16_1 + New data bits of message objects 16 to + 1. 0 = No new data has been written into the data + portion of this Message Object by the Message Handler + since last time this flag was cleared by the CPU. 1 = + The Message Handler or the CPU has written new data + into the data portion of this Message + Object. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANND2 + New data 2 + 0x124 + read-only + 0x0000 + 0xFFFFFFFF + + + NEWDAT_32_17 + New data bits of message objects 32 to + 17. 0 = No new data has been written into the data + portion of this Message Object by the Message Handler + since last time this flag was cleared by the CPU. 1 = + The Message Handler or the CPU has written new data + into the data portion of this Message + Object. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANIR1 + Interrupt pending 1 + 0x140 + read-only + 0x0000 + 0xFFFFFFFF + + + INTPND_16_1 + Interrupt pending bits of message + objects 16 to 1. 0 = This message object is ignored + by the message handler. 1 = This message object is + the source of an interrupt. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANIR2 + Interrupt pending 2 + 0x144 + read-only + 0x0000 + 0xFFFFFFFF + + + INTPND_32_17 + Interrupt pending bits of message + objects 32 to 17. 0 = This message object is ignored + by the message handler. 1 = This message object is + the source of an interrupt. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANMSGV1 + Message valid 1 + 0x160 + read-only + 0x0000 + 0xFFFFFFFF + + + MSGVAL_16_1 + Message valid bits of message objects 16 + to 1. 0 = This message object is ignored by the + message handler. 1 = This message object is + configured and should be considered by the message + handler. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANMSGV2 + Message valid 2 + 0x164 + read-only + 0x0000 + 0xFFFFFFFF + + + MSGVAL_32_17 + Message valid bits of message objects 32 + to 17. 0 = This message object is ignored by the + message handler. 1 = This message object is + configured and should be considered by the message + handler. + [15:0] + + + RESERVED + Reserved + [31:16] + + + + + CANCLKDIV + Can clock divider register + 0x180 + read-write + 0x0000 + 0xFFFFFFFF + + + CLKDIVVAL + Clock divider value. CAN_CLK = + PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by + 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = + PCLK divided by 3 0010: CAN_CLK = PCLK divided by 4. + ... 1111: CAN_CLK = PCLK divided by 16. + [3:0] + + + RESERVED + reserved + [31:4] + + + + + + + SPI1 + 0x40058000 + + 0 + 0xFFF + registers + + + SPI1 + 14 + + + + GPIO0 + GPIO0 + GPIO + 0x50000000 + + 0 + 0xFFFFFF + registers + + + GPIO0 + 31 + + + + DATA + Port n data register for pins PIOn_0 to + PIOn_11 + 0x3FFC + read-write + 0 + 0x00000000 + + + DATA0 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [0:0] + + + DATA1 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [1:1] + + + DATA2 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [2:2] + + + DATA3 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [3:3] + + + DATA4 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [4:4] + + + DATA5 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [5:5] + + + DATA6 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [6:6] + + + DATA7 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [7:7] + + + DATA8 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [8:8] + + + DATA9 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [9:9] + + + DATA10 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [10:10] + + + DATA11 + Logic levels for pins PIOn_0 to PIOn_11. + HIGH = 1, LOW = 0. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + DIR + Data direction register for port + n + 0x8000 + read-write + 0x00 + 0xFFFFFFFF + + + IO0 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [0:0] + + + IO1 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [1:1] + + + IO2 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [2:2] + + + IO3 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [3:3] + + + IO4 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [4:4] + + + IO5 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [5:5] + + + IO6 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [6:6] + + + IO7 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [7:7] + + + IO8 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [8:8] + + + IO9 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [9:9] + + + IO10 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [10:10] + + + IO11 + Selects pin x as input or output (x = 0 + to 11). 0 = Pin PIOn_x is configured as input. 1 = + Pin PIOn_x is configured as output. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + IS + Interrupt sense register for port + n + 0x8004 + read-write + 0x00 + 0xFFFFFFFF + + + ISENSE0 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [0:0] + + + ISENSE1 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [1:1] + + + ISENSE2 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [2:2] + + + ISENSE3 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [3:3] + + + ISENSE4 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [4:4] + + + ISENSE5 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [5:5] + + + ISENSE6 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [6:6] + + + ISENSE7 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [7:7] + + + ISENSE8 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [8:8] + + + ISENSE9 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [9:9] + + + ISENSE10 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [10:10] + + + ISENSE11 + Selects interrupt on pin x as level or + edge sensitive (x = 0 to 11). 0 = Interrupt on pin + PIOn_x is configured as edge sensitive. 1 = Interrupt + on pin PIOn_x is configured as level + sensitive. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + IBE + Interrupt both edges register for port + n + 0x8008 + read-write + 0x00 + 0xFFFFFFFF + + + IBE0 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [0:0] + + + IBE1 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [1:1] + + + IBE2 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [2:2] + + + IBE3 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [3:3] + + + IBE4 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [4:4] + + + IBE5 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [5:5] + + + IBE6 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [6:6] + + + IBE7 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [7:7] + + + IBE8 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [8:8] + + + IBE9 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [9:9] + + + IBE10 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [10:10] + + + IBE11 + Selects interrupt on pin x to be + triggered on both edges (x = 0 to 11). 0 = Interrupt + on pin PIOn_x is controlled through register + GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an + interrupt. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + IEV + Interrupt event register for port + n + 0x800C + read-write + 0x00 + 0xFFFFFFFF + + + IEV0 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [0:0] + + + IEV1 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [1:1] + + + IEV2 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [2:2] + + + IEV3 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [3:3] + + + IEV4 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [4:4] + + + IEV5 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [5:5] + + + IEV6 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [6:6] + + + IEV7 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [7:7] + + + IEV8 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [8:8] + + + IEV9 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [9:9] + + + IEV10 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [10:10] + + + IEV11 + Selects interrupt on pin x to be + triggered rising or falling edges (x = 0 to 11). 0 = + Depending on setting in register GPIOnIS (see Table + 109), falling edges or LOW level on pin PIOn_x + trigger an interrupt. 1 = Depending on setting in + register GPIOnIS (see Table 109), rising edges or + HIGH level on pin PIOn_x trigger an + interrupt. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + IE + Interrupt mask register for port + n + 0x8010 + read-write + 0x00 + 0xFFFFFFFF + + + MASK0 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [0:0] + + + MASK1 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [1:1] + + + MASK2 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [2:2] + + + MASK3 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [3:3] + + + MASK4 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [4:4] + + + MASK5 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [5:5] + + + MASK6 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [6:6] + + + MASK7 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [7:7] + + + MASK8 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [8:8] + + + MASK9 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [9:9] + + + MASK10 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [10:10] + + + MASK11 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. + 1 = Interrupt on pin PIOn_x is not + masked. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + RIS + Raw interrupt status register for port + n + 0x8014 + read-only + 0x00 + 0xFFFFFFFF + + + RAWST0 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [0:0] + + + RAWST1 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [1:1] + + + RAWST2 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [2:2] + + + RAWST3 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [3:3] + + + RAWST4 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [4:4] + + + RAWST5 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [5:5] + + + RAWST6 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [6:6] + + + RAWST7 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [7:7] + + + RAWST8 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [8:8] + + + RAWST9 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [9:9] + + + RAWST10 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [10:10] + + + RAWST11 + Raw interrupt status (x = 0 to 11). 0 = + No interrupt on pin PIOn_x. 1 = Interrupt + requirements met on PIOn_x. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + MIS + Masked interrupt status register for port + n + 0x8018 + read-only + 0x00 + 0xFFFFFFFF + + + MASK0 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [0:0] + + + MASK1 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [1:1] + + + MASK2 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [2:2] + + + MASK3 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [3:3] + + + MASK4 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [4:4] + + + MASK5 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [5:5] + + + MASK6 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [6:6] + + + MASK7 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [7:7] + + + MASK8 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [8:8] + + + MASK9 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [9:9] + + + MASK10 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [10:10] + + + MASK11 + Selects interrupt on pin x to be masked + (x = 0 to 11). 0 = No interrupt or interrupt masked + on pin PIOn_x. 1 = Interrupt on PIOn_x. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + IC + Interrupt clear register for port + n + 0x801C + write-only + 0x00 + 0xFFFFFFFF + + + CLR0 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [0:0] + + + CLR1 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [1:1] + + + CLR2 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [2:2] + + + CLR3 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [3:3] + + + CLR4 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [4:4] + + + CLR5 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [5:5] + + + CLR6 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [6:6] + + + CLR7 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [7:7] + + + CLR8 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [8:8] + + + CLR9 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [9:9] + + + CLR10 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [10:10] + + + CLR11 + Selects interrupt on pin x to be cleared + (x = 0 to 11). Clears the interrupt edge detection + logic. This register is write-only. The synchronizer + between the GPIO and the NVIC blocks causes a delay + of 2 clocks. It is recommended to add two NOPs after + the clear of the interrupt edge detection logic + before the exit of the interrupt service routine. 0 = + No effect. 1 = Clears edge detection logic for pin + PIOn_x. + [11:11] + + + RESERVED + Reserved + [31:12] + + + + + + + GPIO1 + 0x50010000 + + 0 + 0xFFFFFF + registers + + + GPIO1 + 30 + + + + GPIO2 + 0x50020000 + + 0 + 0xFFFFFF + registers + + + GPIO2 + 29 + + + + GPIO3 + 0x50030000 + + 0 + 0xFFFFFF + registers + + + GPIO3 + 28 + + + + diff --git a/support/svd/svd.rb b/support/svd/svd.rb index c89853eb..db0cb298 100755 --- a/support/svd/svd.rb +++ b/support/svd/svd.rb @@ -245,6 +245,7 @@ def to_hex } puts tpl.evaluate( + filename: fn, svd: svd, map_access: Proc.new do |i| name = ACCESS_MAP[i] diff --git a/support/svd/template.rs.erb b/support/svd/template.rs.erb index 5ceeea33..18030052 100644 --- a/support/svd/template.rs.erb +++ b/support/svd/template.rs.erb @@ -1,3 +1,24 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2015 zinc developers +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// THIS FILE IS AUTOMATICALLY GENERATED. DO NOT MODIFY IT DIRECTLY, UPDATE THE +// SVD DEFINITION IN SUPPORT/SVD/DATA AND RE-GENERATE, ADDING THE CHANGES MADE +// INTO THE RELEVANT CHANGELOG ENTRY. + +//! ioregs definition based on <%= @filename %> + use volatile_cell::VolatileCell; use core::ops::Drop; diff --git a/thumbv6-none-eabi.json b/thumbv6-none-eabi.json new file mode 100644 index 00000000..9b5ab43b --- /dev/null +++ b/thumbv6-none-eabi.json @@ -0,0 +1,21 @@ +{ + "arch": "arm", + "cpu": "cortex-m0", + "data-layout": "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64", + "disable-redzone": true, + "executables": true, + "llvm-target": "thumbv6-none-eabi", + "morestack": false, + "os": "none", + "relocation-model": "static", + "target-endian": "little", + "target-pointer-width": "32", + "no-compiler-rt": true, + "pre-link-args": [ + "-mcpu=cortex-m0", "-mthumb", + "-Tlayout.ld" + ], + "post-link-args": [ + "-lm", "-lgcc", "-lnosys" + ] +} diff --git a/volatile_cell/Cargo.toml b/volatile_cell/Cargo.toml index 8d01d3e4..6ef65fe1 100644 --- a/volatile_cell/Cargo.toml +++ b/volatile_cell/Cargo.toml @@ -13,7 +13,10 @@ doc = true crate-type = ["rlib"] [features] -replayer = ["hamcrest"] +replayer = ["expectest"] + +[target.thumbv6-none-eabi.dependencies.core] +git = "https://github.com/hackndev/rust-libcore" [target.thumbv7m-none-eabi.dependencies.core] git = "https://github.com/hackndev/rust-libcore" @@ -21,6 +24,5 @@ git = "https://github.com/hackndev/rust-libcore" [target.thumbv7em-none-eabi.dependencies.core] git = "https://github.com/hackndev/rust-libcore" -[dependencies.hamcrest] -git = "https://github.com/carllerche/hamcrest-rust" +[dependencies.expectest] optional = true diff --git a/volatile_cell/lib.rs b/volatile_cell/lib.rs index 41b4731c..07ea0a92 100644 --- a/volatile_cell/lib.rs +++ b/volatile_cell/lib.rs @@ -18,13 +18,18 @@ #![feature(core, no_std, core_intrinsics)] #![no_std] -#[cfg(feature="replayer")] extern crate hamcrest; +extern crate core; + +#[cfg(feature="replayer")] #[macro_use(expect)] extern crate expectest; #[cfg(feature="replayer")] #[macro_use] extern crate std; #[cfg(feature="replayer")] use std::vec::Vec; -#[cfg(feature="replayer")] use hamcrest::{assert_that, is, equal_to}; - -extern crate core; +#[cfg(feature="replayer")] use expectest::prelude::*; +#[cfg(feature="replayer")] use std::string::String; +#[cfg(feature="replayer")] use std::fmt; +#[cfg(feature="replayer")] use core::cmp::PartialEq; +#[cfg(feature="replayer")] use core::clone::Clone; +#[cfg(feature="replayer")] use core::cell::RefCell; #[cfg(not(feature="replayer"))] use core::intrinsics::{volatile_load, volatile_store}; #[cfg(feature="replayer")] use core::intrinsics::transmute; @@ -68,13 +73,13 @@ impl VolatileCell { impl VolatileCell { pub fn get(&self) -> u32 { unsafe { - (*GlobalReplayer).get_cell(transmute(&self.value)) + GLOBAL_REPLAYER.with(|gr| { gr.borrow_mut().get_cell(transmute(&self.value)) }) } } pub fn set(&self, value: u32) { unsafe { - (*GlobalReplayer).set_cell(transmute(&self.value), value) + GLOBAL_REPLAYER.with(|gr| { gr.borrow_mut().set_cell(transmute(&self.value), value) }) } } } @@ -83,13 +88,13 @@ impl VolatileCell { impl VolatileCell { pub fn get(&self) -> u16 { unsafe { - (*GlobalReplayer).get_cell(transmute(&self.value)) as u16 + GLOBAL_REPLAYER.with(|gr| { gr.borrow_mut().get_cell(transmute(&self.value)) }) as u16 } } pub fn set(&self, value: u16) { unsafe { - (*GlobalReplayer).set_cell(transmute(&self.value), value as u32) + GLOBAL_REPLAYER.with(|gr| { gr.borrow_mut().set_cell(transmute(&self.value), value as u32) }) } } } @@ -98,13 +103,13 @@ impl VolatileCell { impl VolatileCell { pub fn get(&self) -> u8 { unsafe { - (*GlobalReplayer).get_cell(transmute(&self.value)) as u8 + GLOBAL_REPLAYER.with(|gr| { gr.borrow_mut().get_cell(transmute(&self.value)) }) as u8 } } pub fn set(&self, value: u8) { unsafe { - (*GlobalReplayer).set_cell(transmute(&self.value), value as u32) + GLOBAL_REPLAYER.with(|gr| { gr.borrow_mut().set_cell(transmute(&self.value), value as u32) }) } } } @@ -119,6 +124,18 @@ struct ReplayRecord { did_read: bool, actual_address: usize, actual_value: u32, + + loc: expectest::core::SourceLocation, +} + +#[cfg(feature="replayer")] +impl core::fmt::Display for ReplayRecord { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.is_read { + true => write!(f, "read 0x{:x} from 0x{:x}", self.value, self.address), + false => write!(f, "write 0x{:x} to 0x{:x}", self.value, self.address), + } + } } #[cfg(feature="replayer")] @@ -136,7 +153,8 @@ impl VolatileCellReplayer { } } - pub fn expect_read(&mut self, address: usize, value: u32) { + pub fn expect_read(&mut self, address: usize, value: u32, + loc: expectest::core::SourceLocation) { self.replays.push(ReplayRecord { is_read: true, address: address, @@ -145,10 +163,12 @@ impl VolatileCellReplayer { did_read: false, actual_address: 0, actual_value: 0, + loc: loc, }); } - pub fn expect_write(&mut self, address: usize, value: u32) { + pub fn expect_write(&mut self, address: usize, value: u32, + loc: expectest::core::SourceLocation) { self.replays.push(ReplayRecord { is_read: false, address: address, @@ -157,32 +177,36 @@ impl VolatileCellReplayer { did_read: false, actual_address: 0, actual_value: 0, + loc: loc, }); } - pub fn verify(&self) { - assert_that(self.current_replay, is(equal_to(self.replays.len()))); + pub fn verify(&self, loc: expectest::core::SourceLocation) { + expect(self.current_replay).location(loc).to( + be_equal_to_with_context( + self.replays.len(), + format!("expected {} replays, performed {}", + self.replays.len(), self.current_replay))); - let mut i = 1usize; for ref replay in &*self.replays { - println!("replay {}", i); - println!("replayed?"); - assert_that(replay.replayed, is(equal_to(true))); - println!("is read?"); - assert_that(replay.is_read, is(equal_to(replay.did_read))); - println!("address correct?"); - assert_that(replay.address, is(equal_to(replay.actual_address))); + expect(replay.replayed).location(replay.loc).to(be_equal_to_with_context(true, + format!("expected replay {} to be performed, was not", replay))); + expect(replay.is_read).location(replay.loc).to(be_equal_to_with_context(replay.did_read, + format!("expected replay to be {} replay, was {} replay", + if replay.is_read {"read"} else {"write"}, + if replay.is_read {"write"} else {"read"}))); + expect(replay.address).location(replay.loc).to(be_equal_to_with_context(replay.actual_address, + format!("expected replay address 0x{:x}, was 0x{:x}", replay.address, replay.actual_address))); if !replay.is_read { - println!("value written is correct?"); - assert_that(replay.value, is(equal_to(replay.actual_value))); + expect(replay.value).location(replay.loc).to(be_equal_to_with_context(replay.actual_value, + format!("expected replay to write 0x{:x}, written 0x{:x}", replay.value, replay.actual_value))); } - i += 1; } } pub fn get_cell(&mut self, address: usize) -> u32 { if self.current_replay >= self.replays.len() { - panic!("get_cell({}) faled, current replay: {}, total replays: {}", + panic!("get_cell(0x{:x}) faled, current replay: {}, total replays: {}", address, self.current_replay+1, self.replays.len()); } let replay: &mut ReplayRecord = &mut self.replays[self.current_replay]; @@ -197,7 +221,7 @@ impl VolatileCellReplayer { pub fn set_cell(&mut self, address: usize, value: u32) { if self.current_replay >= self.replays.len() { - panic!("set_cell({}, {}) faled, current replay: {}, total replays: {}", + panic!("set_cell(0x{:x}, 0x{:x}) faled, current replay: {}, total replays: {}", address, value, self.current_replay+1, self.replays.len()); } let replay: &mut ReplayRecord = &mut self.replays[self.current_replay]; @@ -211,11 +235,83 @@ impl VolatileCellReplayer { } #[cfg(feature="replayer")] -static mut GlobalReplayer: *mut VolatileCellReplayer = 0 as *mut VolatileCellReplayer; +thread_local!(static GLOBAL_REPLAYER: RefCell = RefCell::new(VolatileCellReplayer::new())); #[cfg(feature="replayer")] -pub fn set_replayer(replayer: &mut VolatileCellReplayer) { - unsafe { - GlobalReplayer = replayer; - } +pub fn set_replayer(replayer: VolatileCellReplayer) { + GLOBAL_REPLAYER.with(|gr| { + let mut bm = gr.borrow_mut(); + *bm = replayer; + }); +} + +#[cfg(feature="replayer")] +pub fn with_mut_replayer(f: F) where F: core::ops::FnOnce(&mut VolatileCellReplayer) { + GLOBAL_REPLAYER.with(|gr| { + let mut bm = gr.borrow_mut(); + f(&mut *bm); + }); +} + +#[cfg(feature="replayer")] +struct BeEqualToWithContext { + expected: E, + context: String, +} + +#[cfg(feature="replayer")] +fn be_equal_to_with_context(expected: E, context: String) -> BeEqualToWithContext { + BeEqualToWithContext { + expected: expected, + context: context, + } +} + +#[cfg(feature="replayer")] +impl Matcher for BeEqualToWithContext + where + A: PartialEq + fmt::Debug, + E: fmt::Debug { + + fn failure_message(&self, _: expectest::core::Join, _: &A) -> String { + self.context.clone() + } + + fn matches(&self, actual: &A) -> bool { + *actual == self.expected + } +} + +#[macro_export] +macro_rules! expect_volatile_read { + ($addr: expr, $val: expr) => ( + $crate::with_mut_replayer(|r| { + r.expect_read($addr, $val, expectest::core::SourceLocation::new(file!(), line!())); + }) + ); +} + +#[macro_export] +macro_rules! expect_volatile_write { + ($addr: expr, $val: expr) => ( + $crate::with_mut_replayer(|r| { + r.expect_write($addr, $val, expectest::core::SourceLocation::new(file!(), line!())); + }) + ); +} + +#[macro_export] +macro_rules! expect_replayer_valid { + () => ( + $crate::with_mut_replayer(|r| { + r.verify(expectest::core::SourceLocation::new(file!(), line!())); + }) + ); +} + +#[macro_export] +macro_rules! init_replayer { + () => ( + set_replayer(VolatileCellReplayer::new()); + ); }