ATF15XX TT2 File Generation or Running Fitter?

[jdgabbard]

I have previously used Digital to export VHDL code, and imported into Quartus for integration into a design. I actually did a video series on this previously, which can be seen here: https://www.youtube.com/watch?v=S5_qUptb8OQ

However, I would like to ultimately generate a JEDEC file for use with a ATF15xx device directly. Reading through the documentation this should be possible by exporting to a TT2 file, which Digital then uses the WinCUPL fitter to create the JEDEC. However, I'm not seeing any documentation regarding how to generate this TT2 file type.

I do have WinCUPL installed, and the locations to the fitters located in Digital. I also have ATMISP7 installed, and it's location is also specified in Digital. Looking through the menus and options, I see nothing indicating there is anything allowing for TT2 generation, or to run a fitter. Am I missing something??? It would be nice to label pins, and generate this directly.

Any help, or a link to an example even would be fantastic.

[hneemann]

To create a TT2 file, the circuit must first be analyzed. The TT2 file can then be created from the truth table window. In reality, the TT2 file contains the Boolean expressions that arise after minimizing the truth table. Although these are coded in a very special way in the TT2 file.
Therefore, in my opinion, the workflow is better represented if the creation also takes place from the truth table window.