Deca.core

CAPI=2:
name : ::Deca:0

description: SOC for Deca fpga board

filesets:

  data:
    files:
      - data/Deca/deca.sdc 	: {file_type : SDC}
      - data/Deca/DecaWishbone/pinmap.tcl	: {file_type: tclSource}

  rtl:
    files:
      - rtl/Deca/DecaWishbone/WbAvlCdc/AvlStreamAdapter.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/WbAvlCdc/MemoryStreamArbiter.v : { file_type : verilogSource}
      - rtl/Deca/DecaWishbone/WbAvlCdc/WbStreamCdc.v : { file_type : verilogSource}
      - rtl/Deca/DecaWishbone/WbAvlCdc/WbAvlBridge.v : { file_type : verilogSource}
      - rtl/RisingEdgePulse/RisingEdgePulse.v : { file_type : verilogSource }
      - rtl/Deca/DecaWishbone/VexRiscv.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/TUSB1210/WishboneTUSB1210.v : {file_type : verilogSource}
      - rtl/peripheral/icontrol.v : {file_type : verilogSource}
      - rtl/peripheral/MachineTimer/WishboneMachineTimer.v : {file_type : verilogSource}
      - rtl/peripheral/Switch/WishboneSwitch.v : {file_type : verilogSource}
      - rtl/peripheral/I2c/WishboneI2cCtrl.v : {file_type : verilogSource}
      - rtl/peripheral/Video/VideoCtrl.v : {file_type : verilogSource }
      - rtl/Deca/DecaWishbone/UartWishbone/WishboneUartCtrl.v : {file_type : verilogSource}
      - rtl/peripheral/Wishbone8LedsCtrl/WishboneLedsCtrl.v : {file_type : verilogSource}
      - rtl/peripheral/MicroWire/MicroWireWishbone.v : {file_type : verilogSource}
      - rtl/peripheral/DDR3Manager/WishboneDDR3Manager.v : {file_type : verilogSource}
      - rtl/ResetManager/ResetManager.v : {file_type : verilogSource}
    #  - rtl/ResetManager/ResetBufferCC.v : {file_type : verilogSource}
   
   
    depend: ["fusesoc:utils:generators",i2c,wb_intercon-1.3.0,gpio,servant,simple_spi]

  NODDR3: #NOT WORKING
    files:
      - rtl/Deca/DecaWishbone/DecaSoc.v : {file_type : verilogSource}

  IntelDDR3:
    files:
      - rtl/Deca/DecaWishbone/DecaSocDDR3.v : {file_type : verilogSource}

  BrianHG_DDR3:
    files:
      - data/Deca/DecaWishbone/DecaWishbone.sdc 	: {file_type : SDC}
      - data/Deca/pinmap.tcl	: {file_type: tclSource}
      - rtl/Deca/DecaWishbone/DecaTopLevel.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/usbpll/usbpll.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/usbpll/usbpll.qip : {file_type : QIP}
      - rtl/Deca/DecaWishbone/DecaSocBrianHG_DDR3.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/altera_gpio_lite.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_CMD_SEQUENCER.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_COMMANDER.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_CONTROLLER_top.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_FIFOs.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_GEN_tCK.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_IO_PORT_ALTERA.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_PHY_SEQ.sv : {file_type : systemVerilogSource}
      - rtl/Deca/DecaWishbone/BrianHG_DDR3/BrianHG_DDR3_PLL.sv : {file_type : systemVerilogSource}



  Deca:
    files:
 #     - rtl/Deca/pll/pll.qip : {file_type : QIP}
      - rtl/Deca/DecaWishbone/pll/pll.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/usbpll/usbpll.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/usbpll/usbpll.qip : {file_type : QIP}
      - rtl/Deca/DecaWishbone/DecaTopLevel.v : {file_type : verilogSource}
      - rtl/Deca/DecaWishbone/ddr/ddr3.qip : {file_type : QIP}
      - rtl/Deca/DecaWishbone/ddr/ddr3.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0.sdc : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_parameters.tcl : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_timing.tcl : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_report_timing_core.tcl : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_pin_map.tcl : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_0002.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_c0.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_mm_st_converter.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_addr_cmd.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_addr_cmd_wrap.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ddr2_odt_gen.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ddr3_odt_gen.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_lpddr2_addr_cmd.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_odt_gen.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_rdwr_data_tmg.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_arbiter.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_burst_gen.v : {is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_cmd_gen.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_csr.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_buffer.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_buffer_manager.v :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_burst_tracking.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_dataid_manager.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_fifo.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_list.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_rdata_path.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_wdata_path.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_decoder.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_decoder_32_syn.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_decoder_64_syn.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_encoder.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_encoder_32_syn.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_encoder_64_syn.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_axi_st_converter.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_input_if.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_rank_timer.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_sideband.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_tbp.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_timing_param.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_controller.v :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_controller_st_top.v :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_if_nextgen_ddr3_controller_core.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_read_datapath.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_avalon_sc_fifo.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_rsp_mux.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_mem_if_sequencer_rst.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_cmd_demux.sv : {is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_di_buffer.v :  { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/sequencer_pll_mgr.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/sequencer_phy_mgr.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_merlin_arbitrator.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_datamux.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_pattern_fifo.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_lfsr36.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_merlin_slave_agent.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_merlin_slave_translator.sv :  {is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_merlin_master_translator.sv :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_generic.sv :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_router.sv :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/sequencer_m10.sv :  { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_core.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_ram.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_write_decoder.v  : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_dm_decoder.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_router_001.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_ram_csr.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_ddr3.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_bitcheck.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_data_decoder.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_lfsr12.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_lfsr72.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_inst_ROM_reg.v : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_jumplogic.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_di_buffer_wrap.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_data_broadcast.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_rsp_demux.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_cmd_mux.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_merlin_master_agent.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_ac_ROM_reg.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_merlin_burst_uncompressor.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_m10_ac_ROM.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/rw_manager_m10_inst_ROM.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/afi_mux_ddr3_ddrx.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_clock_pair_generator.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_read_valid_selector.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_addr_cmd_datapath.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_reset_m10.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_memphy_m10.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_dqdqs_pads_m10.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_reset_sync.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_fr_cycle_shifter.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_read_datapath_m10.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_write_datapath_m10.v : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_simple_ddio_out_m10.sv : { is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/max10emif_dcfifo.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_iss_probe.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_addr_cmd_pads_m10.v : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0_flop_mem.v : {is_include_file : true }
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_p0.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/altera_gpio_lite.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_pll0.sv : { is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/alt_mem_ddrx_define.iv : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_AC_ROM.hex : {is_include_file : true}
      - rtl/Deca/DecaWishbone/ddr/ddr3/ddr3_s0_inst_ROM.hex : {is_include_file : true}


 # DecaBrianHG_DDR3:
 #   files:
 #     - data/Deca/deca.sdc 	: {file_type : SDC}
 #     - data/Deca/pinmap.tcl	: {file_type: tclSource}


  Deca_testbench:
    files:
      - rtl/sim/DDR3/DDR3Sim.v : {file_type : verilogSource}
      - bench/Deca/DecaTopLevelSim.v : {file_type : verilogSource}
      - bench/Deca/Deca_tb.cpp : {file_type : cppSource}
    depend : [vlog_tb_utils]

 # ddr3_sim:



 # memfiles:
 #   files:
 #     - sw/Deca/blink/blink.hex   : { copyto : blink.hex}
 #     - sw/Deca/uart/uart.hex : { copyto : uart.hex }
 #     - sw/Deca/temp_sensor/temp_sensor.hex : {copyto : temp_sensor.hex}
 #     - sw/Deca/rh_temp/rh_temp.hex : {copyto : rh_temp.hex}

targets:

  Deca:
    default_tool: quartus
    filesets_append: [data,rtl,IntelDDR3,Deca]  #IntelDDR3
    parameters: [memfile,memsize=0x20000,PLL=DDR3]  #DDR3,PLL,NONE
    generate: [wb_intercon]
    tools:
      quartus:
        family:  MAX 10
        device:  10M50DAF484C6GES
    toplevel: DecaTopLevel

  Deca_BrianHG_DDR3:
    default_tool: quartus
    filesets_append: [rtl,BrianHG_DDR3]
    parameters : [memfile,memsize=0x20000,PLL=DDR3]
    generate: [wb_intercon]
    tools:
      quartus:
        family: MAX 10
        device: 10M50DAF484C6GES
    toplevel: DecaTopLevel


  Deca_testbench:
    default_tool: verilator
    filesets_append: [rtl,IntelDDR3,Deca_testbench]
    generate: [wb_intercon]
    parameters:
      - PLL=NONE
      - firmware
      - memsize=0x20000
      - vcd=true
      - vcd_start=0
    tools:
      verilator:
        verilator_options : [--trace,-Wno-fatal]
    toplevel : DecaTopLevelSim



parameters:
  PLL:
    datatype : str
    description : PLL type to use for main clock generation
    paramtype : vlogparam

  memfile:
    datatype    : file
    description : Preload RAM with a hex file at compile-time
    paramtype   : vlogparam

  memsize:
    datatype    : int
    default     : 8192
    description : Memory size in bytes for RAM (default 8kiB)
    paramtype   : vlogparam

  firmware:
    datatype : file
    description : Preload RAM with a hex file at runtime (overrides memfile)
    paramtype : plusarg

  vcd:
    datatype : bool
    paramtype : plusarg

  vcd_start:
    datatype    : int
    description : Delay start of VCD dumping until the specified time
    paramtype   : plusarg


generate:

  wb_intercon:
    generator: wb_intercon_gen

    parameters:
      endian: little

      masters:
        cpu_ibus:
          slaves: [mem]


        cpu_dbus:
          slaves:
            - mem
            - gpioA
            - gpioB
            - key1
            - sw0
            - sw1
            - timer
            - leds
            - uart_0
            - i2c_0
            - spi_0
            - cap_sense
            - light
            - rh_temp
            - board_temp_sensor
            - gsensor
            - pmonitor
#            - tusb1210
            - ddr3manager
            - hdmi_i2c
            - HdmiCtrl
            - ictrl #interrupt controller
            - wb_avl_cdc

      slaves: #size must be a power of 2

        mem:
          offset: 0x00000000
          size: 0x00020000

        gpioA:
          offset: 0x00040000
          size: 2
          datawidth: 8

        gpioB:
          offset: 0x00040010
          size: 2
          datawidth: 8

        leds:
          offset: 0x00040020
          size: 2
          datawidth: 8

        timer:
          offset: 0x00040040
          size: 32

        uart_0:
          offset: 0x00040100
          size: 16

        i2c_0:
          offset: 0x00042000
          size: 1024
          datawidth: 32

        spi_0:
          offset: 0x00040140
          size: 8
          datawidth: 8

        cap_sense:
          offset: 0x00043000
          size : 1024
          datawidth: 32

        light:
          offset: 0x00040810
          size : 8
          datawidth: 8

        rh_temp:
          offset: 0x00045000
          size : 1024
          datawidth: 32

        board_temp_sensor:
          offset: 0x00040840
          size : 4
          datawidth: 8

        gsensor:  #gsensor is on spi bus
          offset: 0x00040880
          size: 8
          datawidth: 8

        pmonitor:
          offset:  0x00040900
          size: 8
          datawidth: 8

#      tusb1210:
#        offset:  0x00040910
#        size: 2
#        datawidth: 8

        key1:
          offset: 0x00041000
          size: 1
          datawidth: 8

        sw0:
          offset: 0x00041010
          size: 1
          datawidth: 8

        sw1:
          offset: 0x00041020
          size: 1
          datawidth: 8

        ddr3manager:
          offset:  0x00050000
          size : 1
          datawidth: 8

        hdmi_i2c:
          offset: 0x00051000
          size : 1024
          datawidth : 32

        HdmiCtrl:
          offset: 0x00060000
          size : 64
          datawidth : 32

        ictrl:
          offset: 0x00100000
          size: 4

        wb_avl_cdc:
          offset: 0x80000000
          size: 536870912