Consider RISC-V "V" vector extensions.

[ldalessa]

The RISC-V "V" Standard Vector Instructions specification has reached version 1.

https://github.com/riscv/riscv-v-spec
https://github.com/riscv/riscv-v-spec/releases

It has some interesting implications for eve. In particular the vector length is not encoded in the register name or instruction, it's set elsewhere and can vary. I believe that the specific hardware implementation sets a maximum (up to 65kbits at this time) and I also believe that the user can dynamically set their desired length dynamically with vsetvli.

In any case, this should be fun and may become important as more of the industry adopts RISC-V.