From 5d058ee7d1694a41663e992ae174bb01ee9901db Mon Sep 17 00:00:00 2001 From: Nitin John Raj Date: Wed, 4 Oct 2023 13:20:10 -0700 Subject: [PATCH] Made comment clearer --- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 4c9a15c3afa33c5..58143c174259857 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -240,8 +240,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { case TargetOpcode::G_SEXT_INREG: return selectSExtInreg(MI, MIB); case TargetOpcode::G_FRAME_INDEX: { - // FIXME: We want to replace this with tablegen code that matches for - // FrameAddrRegImm + // TODO: We may want to replace this code with the SelectionDAG patterns, + // which fail to get imported because it uses FrameAddrRegImm, which is a + // ComplexPattern Register DstReg = MI.getOperand(0).getReg(); if (!MRI.getType(DstReg).isPointer())