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[RISCV] Wrong operand order in ISEL pattern for masked vmslt[u] #48967

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arcbbb opened this issue Mar 18, 2021 · 4 comments
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[RISCV] Wrong operand order in ISEL pattern for masked vmslt[u] #48967

arcbbb opened this issue Mar 18, 2021 · 4 comments
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backend:RISC-V bugzilla Issues migrated from bugzilla

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@arcbbb
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arcbbb commented Mar 18, 2021

Bugzilla Link 49623
Resolution FIXED
Resolved on May 06, 2021 17:02
Version trunk
OS All
Blocks #48661
CC @asb,@topperc,@frasercrmck,@tstellar
Fixed by commit(s) fca5d63 c1831fc

Extended Description

The input operand order of masked vmslt[u] is (maskedoff, vector_in, vector_in/scalar_in, mask, vl),
but the isel pattern is (mask, vector_in, vector_in/scalar_in, maskedoff, vl)
This was solved by https://reviews.llvm.org/D98839

@asb
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asb commented Mar 18, 2021

Adding Fraser and Craig to the CC. Given 12.0 is at RC3 already and this only impacts a feature behind an experimental flag, I'm not sure we can reasonably expect the fix to go into 12.0.

@topperc
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topperc commented Mar 18, 2021

I agree, it's probably too late to fix this for 12.0.0. Maybe we can do it for 12.0.1?

@arcbbb
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arcbbb commented Mar 19, 2021

Actually I have no thoughts on this, so I have no problem to change it to 12.0.1.

@tstellar
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tstellar commented May 7, 2021

Merged: c1831fc

@llvmbot llvmbot transferred this issue from llvm/llvm-bugzilla-archive Dec 11, 2021
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