diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 9d4e0c647048f5..073c9a082d1263 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -528,7 +528,10 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI, continue; MachineInstr *NewDbgMI = SinkDst->getMF()->CloneMachineInstr(DbgMI); SinkMBB.insertAfter(InsertPt, NewDbgMI); - NewDbgMI->getOperand(0).setReg(DstReg); + for (auto &SrcMO : DbgMI->getDebugOperandsForReg(DefReg)) { + auto &DstMO = NewDbgMI->getOperand(SrcMO.getOperandNo()); + DstMO.setReg(DstReg); + } } } else { // Fold instruction into the addressing mode of a memory instruction. diff --git a/llvm/test/CodeGen/AArch64/sink-and-fold-dbg-value-crash.mir b/llvm/test/CodeGen/AArch64/sink-and-fold-dbg-value-crash.mir index 0fc645022780d6..82dae8a86ea2b7 100644 --- a/llvm/test/CodeGen/AArch64/sink-and-fold-dbg-value-crash.mir +++ b/llvm/test/CodeGen/AArch64/sink-and-fold-dbg-value-crash.mir @@ -26,7 +26,16 @@ ret void } - declare ptr @g(ptr) + define ptr @g(ptr) { + entry: + br label %if.then + if.then: + br label %if.end + if.end: + br label %exit + exit: + ret ptr null + } declare void @llvm.dbg.value(metadata, metadata, metadata) #0 @@ -170,3 +179,126 @@ body: | RET_ReallyLR ... +--- +name: g +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gpr64all, preferred-register: '' } + - { id: 1, class: gpr64common, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr64sp, preferred-register: '' } + - { id: 6, class: gpr64all, preferred-register: '' } +liveins: + - { reg: '$x0', virtual-reg: '%1' } + - { reg: '$w1', virtual-reg: '%2' } + - { reg: '$w2', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: g + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $x0, $w1, $w2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0 + ; CHECK-NEXT: DBG_VALUE_LIST !4, !DIExpression(), [[COPY]], $noreg, debug-location !10 + ; CHECK-NEXT: TBZW [[COPY1]], 0, %bb.2 + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.if.then: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY]] + ; CHECK-NEXT: DBG_VALUE_LIST !4, !DIExpression(), [[COPY3]], $noreg, debug-location !10 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $x0 = ADDXri [[COPY2]], 8, 0 + ; CHECK-NEXT: DBG_VALUE_LIST !4, !DIExpression(), [[COPY3]], $x0, debug-location !10 + ; CHECK-NEXT: BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $x0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: TBNZW [[COPY3]], 0, %bb.3 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.end: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: RET_ReallyLR + bb.0.entry: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $x0, $w1, $w2 + + %3:gpr32 = COPY $w2 + %2:gpr32 = COPY $w1 + %1:gpr64common = COPY $x0 + %4:gpr32 = COPY %3 + %5:gpr64sp = ADDXri %1, 8, 0 + DBG_VALUE_LIST !4, !DIExpression(), %4:gpr32, %5:gpr64sp, debug-location !10 + %0:gpr64all = COPY %5 + TBZW %2, 0, %bb.2 + B %bb.1 + + bb.1.if.then: + successors: %bb.3(0x40000000), %bb.2(0x40000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + $x0 = COPY %0 + BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $x0 + ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + TBNZW %4, 0, %bb.3 + B %bb.2 + + bb.2.if.end: + successors: %bb.3(0x80000000) + + + bb.3.exit: + RET_ReallyLR + +...