diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f18b2bb576fead..7fbfec54b2abd11 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -245,6 +245,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   }
   case TargetOpcode::G_SEXT_INREG:
     return selectSExtInreg(MI, MIB);
+  case TargetOpcode::G_FRAME_INDEX: {
+    // TODO: We may want to replace this code with the SelectionDAG patterns,
+    // which fail to get imported because it uses FrameAddrRegImm, which is a
+    // ComplexPattern
+    MI.setDesc(TII.get(RISCV::ADDI));
+    MI.addOperand(MachineOperand::CreateImm(0));
+    return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+  }
   case TargetOpcode::G_SELECT:
     return selectSelect(MI, MIB, MRI);
   default:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 63686bd4bdbc3ae..59aebc7960bc3dc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_STORE:
     break;
   case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_FRAME_INDEX:
   case TargetOpcode::G_GLOBAL_VALUE:
   case TargetOpcode::G_BRCOND:
     OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
new file mode 100644
index 000000000000000..20747bd1876180c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gprb, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
new file mode 100644
index 000000000000000..dc265bda0a68894
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gprb, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
new file mode 100644
index 000000000000000..f701ef616962552
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...